[CHERI] Rename chericcallcce to chericcallee

resistor · resistor · commit fb37ee1beab6 · 2025-08-26T22:19:08.000+08:00
diff --git a/clang/test/CodeGen/cheri/cheri-ccall-attrs.c b/clang/test/CodeGen/cheri/cheri-ccall-attrs.c
@@ -45,7 +45,7 @@ __attribute__((cheri_method_class(cls)))
 __attribute__((cheri_method_suffix("_cap")))
 void fish(void)
 {
-  // CHECK-LABEL: define dso_local chericcallcce void @fish()
+  // CHECK-LABEL: define dso_local chericcallee void @fish()
 }
 
 __attribute__((cheri_method_suffix("_cap")))
@@ -55,7 +55,7 @@ void flibble(void);
 // CHECK-LABEL: define dso_local void @call()
 void call(void)
 {
-  // CHECK: call chericcallcce void @fish()
+  // CHECK: call chericcallee void @fish()
 	fish();
 	// Check that we get a ccall to cheri_invoke with the correct method number
 	// CHECK: load i64, ptr @__cheri_method.cls.fish, align 8, [[$INVARIANT_LOAD]]
diff --git a/clang/test/CodeGen/cheri/cheri-mcu-ccall.c b/clang/test/CodeGen/cheri/cheri-mcu-ccall.c
@@ -1,6 +1,6 @@
 // RUN: %clang_cc1 %s -o - "-triple" "riscv32cheriot-unknown-cheriotrtos" "-emit-llvm" "-mframe-pointer=none" "-mcmodel=small" "-target-abi" "cheriot" "-target-feature" "+xcheriot" "-Oz" "-Werror" "-cheri-compartment=example" | FileCheck %s
 
-// CHECK: define dso_local chericcallcce i32 @_Z5test2ii(i32 noundef %a0, i32 noundef %a1) local_unnamed_addr addrspace(200) #0
+// CHECK: define dso_local chericcallee i32 @_Z5test2ii(i32 noundef %a0, i32 noundef %a1) local_unnamed_addr addrspace(200) #0
 __attribute__((cheriot_compartment("example"))) int test2(int a0, int a1) {
   return a0 + a1;
 }
diff --git a/clang/test/CodeGen/cheri/cheri-mcu-interrupts.c b/clang/test/CodeGen/cheri/cheri-mcu-interrupts.c
@@ -24,7 +24,7 @@ int inherit(void)
 
 // The default for exported functions should be interrupts enabled
 //
-// CHECK: define dso_local chericcallcce noundef i32 @_Z21default_enable_calleev() local_unnamed_addr addrspace(200) #[[DEFEN:[0-9]]]
+// CHECK: define dso_local chericcallee noundef i32 @_Z21default_enable_calleev() local_unnamed_addr addrspace(200) #[[DEFEN:[0-9]]]
 __attribute__((cheri_compartment("example")))
 int default_enable_callee(void)
 {
@@ -46,7 +46,7 @@ void default_enable_callback2(void)
 
 // Explicitly setting interrupt status should override the default
 
-// CHECK: define dso_local chericcallcce noundef i32 @_Z23explicit_disable_calleev() local_unnamed_addr addrspace(200) #[[EXPDIS:[0-9]]]
+// CHECK: define dso_local chericcallee noundef i32 @_Z23explicit_disable_calleev() local_unnamed_addr addrspace(200) #[[EXPDIS:[0-9]]]
 __attribute__((cheriot_interrupt_state(disabled)))
 __attribute__((cheri_compartment("example")))
 int explicit_disable_callee(void)
@@ -84,7 +84,7 @@ int inherit1(void)
 	return foo();
 }
 
-// CHECK: define dso_local chericcallcce noundef i32 @_Z24explicit_disable_callee1v() local_unnamed_addr addrspace(200) #[[EXPDIS]]
+// CHECK: define dso_local chericcallee noundef i32 @_Z24explicit_disable_callee1v() local_unnamed_addr addrspace(200) #[[EXPDIS]]
 __attribute__((cheri_interrupt_state(disabled)))
 __attribute__((cheri_compartment("example")))
 int explicit_disable_callee1(void)
diff --git a/clang/test/CodeGen/cheri/cheriot-struct-ret.c b/clang/test/CodeGen/cheri/cheriot-struct-ret.c
diff --git a/llvm/include/llvm/AsmParser/LLToken.h b/llvm/include/llvm/AsmParser/LLToken.h
@@ -159,7 +159,7 @@ enum Kind {
   kw_spir_func,
   kw_chericcallcc,
   kw_cherilibcallcc,
-  kw_chericcallcce,
+  kw_chericcallee,
   kw_x86_64_sysvcc,
   kw_win64cc,
   kw_anyregcc,
diff --git a/llvm/lib/AsmParser/LLLexer.cpp b/llvm/lib/AsmParser/LLLexer.cpp
@@ -634,7 +634,7 @@ lltok::Kind LLLexer::LexIdentifier() {
   KEYWORD(fastcc);
   KEYWORD(coldcc);
   KEYWORD(chericcallcc);
-  KEYWORD(chericcallcce);
+  KEYWORD(chericcallee);
   KEYWORD(cherilibcallcc);
   KEYWORD(cfguard_checkcc);
   KEYWORD(x86_stdcallcc);
diff --git a/llvm/lib/AsmParser/LLParser.cpp b/llvm/lib/AsmParser/LLParser.cpp
@@ -2216,7 +2216,9 @@ bool LLParser::parseOptionalCallingConv(unsigned &CC) {
   case lltok::kw_fastcc:         CC = CallingConv::Fast; break;
   case lltok::kw_coldcc:         CC = CallingConv::Cold; break;
   case lltok::kw_chericcallcc:   CC = CallingConv::CHERI_CCall; break;
-  case lltok::kw_chericcallcce:  CC = CallingConv::CHERI_CCallee; break;
+  case lltok::kw_chericcallee:
+    CC = CallingConv::CHERI_CCallee;
+    break;
   case lltok::kw_cherilibcallcc:
     CC = CallingConv::CHERI_LibCall;
     break;
diff --git a/llvm/lib/IR/AsmWriter.cpp b/llvm/lib/IR/AsmWriter.cpp
@@ -342,7 +342,9 @@ static void PrintCallingConv(unsigned cc, raw_ostream &Out) {
   case CallingConv::SPIR_FUNC:     Out << "spir_func"; break;
   case CallingConv::SPIR_KERNEL:   Out << "spir_kernel"; break;
   case CallingConv::CHERI_CCall:   Out << "chericcallcc"; break;
-  case CallingConv::CHERI_CCallee: Out << "chericcallcce"; break;
+  case CallingConv::CHERI_CCallee:
+    Out << "chericcallee";
+    break;
   case CallingConv::CHERI_LibCall:
     Out << "cherilibcallcc";
     break;
diff --git a/llvm/test/CodeGen/Mips/cheri/cheri-ccallee.ll b/llvm/test/CodeGen/Mips/cheri/cheri-ccallee.ll
@@ -2,7 +2,7 @@
 ; RUN: %cheri_llc %s -O1 -o - | FileCheck %s
 
 ; Function Attrs: nounwind
-define chericcallcce void @fish() {
+define chericcallee void @fish() {
 ; CHECK-LABEL: fish:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    daddiu $2, $zero, 0
diff --git a/llvm/test/CodeGen/RISCV/cheri/cheri-local-libcall.ll b/llvm/test/CodeGen/RISCV/cheri/cheri-local-libcall.ll
@@ -9,7 +9,7 @@ entry:
   ret void
 }
 
-define dso_local chericcallcce void @_Z9say_hellov() local_unnamed_addr addrspace(200) #1 {
+define dso_local chericcallee void @_Z9say_hellov() local_unnamed_addr addrspace(200) #1 {
 entry:
   store ptr addrspace(200) @_Z11id_functionv, ptr addrspace(200) @f, align 8
   ret void
diff --git a/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-call-ccallee.ll b/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-call-ccallee.ll
@@ -9,11 +9,11 @@ define dso_local void @func() local_unnamed_addr addrspace(200) #0 {
 entry:
   ; Make sure that there's a 4-byte stack argument passed in ct0.
   ; CHECK:         csetbounds      ct0, csp, 4
-  call chericcallcce void @ccall(i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6) #2
+  call chericcallee void @ccall(i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6) #2
   ret void
 }
 
-declare dso_local chericcallcce void @ccall(i32, i32, i32, i32, i32, i32, i32) local_unnamed_addr addrspace(200) #1
+declare dso_local chericcallee void @ccall(i32, i32, i32, i32, i32, i32, i32) local_unnamed_addr addrspace(200) #1
 
 attributes #0 = { nounwind "frame-pointer"="none" "min-legal-vector-width"="0" "no-builtin-printf" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cheriot" "target-features"="+xcheri,-64bit,-relax,-save-restore" }
 attributes #1 = { "frame-pointer"="none" "no-builtin-printf" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cheriot" "target-features"="+xcheri,-64bit,-relax,-save-restore" }
diff --git a/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-ccall.ll b/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-ccall.ll
@@ -9,7 +9,7 @@ target triple = "riscv32-unknown-unknown"
 @testcall8.stack_arg = internal addrspace(200) global i32 0, align 4
 
 ; Function Attrs: minsize mustprogress nofree norecurse nosync nounwind optsize readnone willreturn
-define dso_local chericcallcce i32 @test2(i32 %a0, i32 %a1) local_unnamed_addr addrspace(200) #0 {
+define dso_local chericcallee i32 @test2(i32 %a0, i32 %a1) local_unnamed_addr addrspace(200) #0 {
 ; Check that we have the first two arguments in the right registers.
 ; CHECK-LABEL: test2:
 ; CHECK:       # %bb.0: # %entry
@@ -21,7 +21,7 @@ entry:
 }
 
 ; Function Attrs: minsize mustprogress nofree norecurse nosync nounwind optsize readonly willreturn
-define dso_local chericcallcce i32 @test6(i32 addrspace(200)* nocapture readonly %a0, i32 addrspace(200)* nocapture readonly %a1, i32 addrspace(200)* nocapture readonly %a2, i32 addrspace(200)* nocapture readonly %a3, i32 addrspace(200)* nocapture readonly %a4, i32 addrspace(200)* nocapture readonly %a5) local_unnamed_addr addrspace(200) #1 {
+define dso_local chericcallee i32 @test6(i32 addrspace(200)* nocapture readonly %a0, i32 addrspace(200)* nocapture readonly %a1, i32 addrspace(200)* nocapture readonly %a2, i32 addrspace(200)* nocapture readonly %a3, i32 addrspace(200)* nocapture readonly %a4, i32 addrspace(200)* nocapture readonly %a5) local_unnamed_addr addrspace(200) #1 {
 ; Check that we are loading the last register argument
 ; CHECK-LABEL: test6:
 ; CHECK: clw     a5, 0(ca5)
@@ -41,7 +41,7 @@ entry:
 }
 
 ; Function Attrs: minsize mustprogress nofree norecurse nosync nounwind optsize readonly willreturn
-define dso_local chericcallcce i32 @test8(i32 addrspace(200)* nocapture readonly %a0, i32 addrspace(200)* nocapture readonly %a1, i32 addrspace(200)* nocapture readonly %a2, i32 addrspace(200)* nocapture readonly %a3, i32 addrspace(200)* nocapture readonly %a4, i32 addrspace(200)* nocapture readonly %a5, i32 addrspace(200)* nocapture readonly %a6, i32 addrspace(200)* nocapture readonly %a7) local_unnamed_addr addrspace(200) #1 {
+define dso_local chericcallee i32 @test8(i32 addrspace(200)* nocapture readonly %a0, i32 addrspace(200)* nocapture readonly %a1, i32 addrspace(200)* nocapture readonly %a2, i32 addrspace(200)* nocapture readonly %a3, i32 addrspace(200)* nocapture readonly %a4, i32 addrspace(200)* nocapture readonly %a5, i32 addrspace(200)* nocapture readonly %a6, i32 addrspace(200)* nocapture readonly %a7) local_unnamed_addr addrspace(200) #1 {
 ; Check that the last argument (used in the multiply) is loaded from offset 8
 ; in the stack-argument capability.
 ; CHECK-LABEL: test8:
diff --git a/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-exported-interrupts.ll b/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-exported-interrupts.ll
@@ -7,7 +7,7 @@ target triple = "riscv32-unknown-unknown"
 ; Function Attrs: minsize mustprogress nounwind optsize
 define dso_local void @_Z15internal_callerv() local_unnamed_addr addrspace(200) #0 {
 entry:
-  tail call chericcallcce void @_Z5emptyv() #2
+  tail call chericcallee void @_Z5emptyv() #2
   ret void
 }
 
@@ -23,7 +23,7 @@ entry:
 ; CHECK:         .word   __export_example__Z5emptyv+1
 
 ; Function Attrs: minsize optsize
-declare dso_local chericcallcce void @_Z5emptyv() local_unnamed_addr addrspace(200) #1
+declare dso_local chericcallee void @_Z5emptyv() local_unnamed_addr addrspace(200) #1
 
 attributes #0 = { minsize mustprogress nounwind optsize "cheri-compartment"="example" "frame-pointer"="none" "min-legal-vector-width"="0" "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cheriot" "target-features"="+xcheri,-64bit,-relax,-save-restore" }
 attributes #1 = { minsize optsize "cheri-compartment"="example" "frame-pointer"="none" "interrupt-state"="enabled" "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cheriot" "target-features"="+xcheri,-64bit,-relax,-save-restore" }
diff --git a/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-exported-unused-args.ll b/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-exported-unused-args.ll
@@ -5,7 +5,7 @@ target datalayout = "e-m:e-pf200:64:64:64:32-p:32:32-i64:64-n32-S128-A200-P200-G
 target triple = "riscv32-unknown-unknown"
 
 ; Function Attrs: minsize mustprogress nofree norecurse nosync nounwind optsize readnone willreturn
-define dso_local chericcallcce i32 @_Z2fnPvS_i(i8 addrspace(200)* nocapture readnone %a, i8 addrspace(200)* nocapture readnone %b, i32 returned %c) local_unnamed_addr addrspace(200) #0 {
+define dso_local chericcallee i32 @_Z2fnPvS_i(i8 addrspace(200)* nocapture readnone %a, i8 addrspace(200)* nocapture readnone %b, i32 returned %c) local_unnamed_addr addrspace(200) #0 {
 entry:
   ret i32 %c
 }
diff --git a/llvm/test/CodeGen/RISCV/cheri/cheriot-check-arg-permissions.ll b/llvm/test/CodeGen/RISCV/cheri/cheriot-check-arg-permissions.ll
@@ -14,7 +14,7 @@ target triple = "riscv32-unknown-unknown"
 ; may be on the stack).
 
 ; Function Attrs: minsize mustprogress nofree norecurse nosync nounwind optsize willreturn writeonly
-define dso_local chericcallcce void @_Z4ret2v(%struct.ret addrspace(200)* noalias nocapture sret(%struct.ret) align 8 %agg.result) local_unnamed_addr addrspace(200) #0 {
+define dso_local chericcallee void @_Z4ret2v(%struct.ret addrspace(200)* noalias nocapture sret(%struct.ret) align 8 %agg.result) local_unnamed_addr addrspace(200) #0 {
 entry:
   ; CHECK-LABEL: _Z4ret2v:
   ; Make sure that the base points to the current address
@@ -42,7 +42,7 @@ entry:
 ; compiler must insert the check that they are valid.
 
 ; Function Attrs: minsize mustprogress nofree norecurse nosync nounwind optsize readnone willreturn
-define dso_local chericcallcce i32 @_Z7bigargsiiiiiiii(i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, i32 %a6, i32 %a7) local_unnamed_addr addrspace(200) #1 {
+define dso_local chericcallee i32 @_Z7bigargsiiiiiiii(i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, i32 %a6, i32 %a7) local_unnamed_addr addrspace(200) #1 {
 entry:
   ; CHECK-LABEL: _Z7bigargsiiiiiiii:
   ; Make sure that the base points to the current address
diff --git a/llvm/test/CodeGen/RISCV/cheri/cheriot-frame-checks.ll b/llvm/test/CodeGen/RISCV/cheri/cheriot-frame-checks.ll
@@ -6,7 +6,7 @@ target triple = "riscv32-unknown-unknown"
 @.str = private unnamed_addr addrspace(200) constant [16 x i8] c"Seven arguments\00", align 1
 
 ; Function Attrs: minsize mustprogress nounwind optsize
-define dso_local chericcallcce noundef i32 @_Z22compartment_call_inneriiPKiiS0_ii(i32 noundef %0, i32 noundef %1, ptr addrspace(200) nocapture noundef readnone %2, i32 noundef %3, ptr addrspace(200) nocapture noundef readnone %4, i32 noundef %5, i32 noundef %6) local_unnamed_addr addrspace(200) #0 {
+define dso_local chericcallee noundef i32 @_Z22compartment_call_inneriiPKiiS0_ii(i32 noundef %0, i32 noundef %1, ptr addrspace(200) nocapture noundef readnone %2, i32 noundef %3, ptr addrspace(200) nocapture noundef readnone %4, i32 noundef %5, i32 noundef %6) local_unnamed_addr addrspace(200) #0 {
 ; CHECK-LABEL: _Z22compartment_call_inneriiPKiiS0_ii:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    cgetbase t2, ct0
diff --git a/llvm/test/CodeGen/RISCV/cheri/cheriot-jumptable.ll b/llvm/test/CodeGen/RISCV/cheri/cheriot-jumptable.ll
@@ -4,7 +4,7 @@ target datalayout = "e-m:e-pf200:64:64:64:32-p:32:32-i64:64-n32-S128-A200-P200-G
 target triple = "riscv32-unknown-unknown"
 
 ; Function Attrs: minsize nounwind optsize
-define dso_local chericcallcce i32 @_Z2swi(i32 noundef %v) local_unnamed_addr addrspace(200) #0 {
+define dso_local chericcallee i32 @_Z2swi(i32 noundef %v) local_unnamed_addr addrspace(200) #0 {
 ; CHECK-LABEL: _Z2swi:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addi a0, a0, -1
diff --git a/llvm/test/CodeGen/RISCV/cheri/cheriot-sealed-attr.ll b/llvm/test/CodeGen/RISCV/cheri/cheriot-sealed-attr.ll
@@ -14,7 +14,7 @@ target triple = "riscv32cheriot-unknown-cheriotrtos"
 %struct.SealedAllocatorCapabilityState = type { i32, i32, %struct.AllocatorCapabilityState }
 
 ; Function Attrs: minsize mustprogress nounwind optsize
-define dso_local chericcallcce noundef i32 @test_static_sealing() local_unnamed_addr addrspace(200) #0 {
+define dso_local chericcallee noundef i32 @test_static_sealing() local_unnamed_addr addrspace(200) #0 {
 entry:
 
 ;; CHECK:        .LBB0_1:                                # %entry
diff --git a/llvm/test/CodeGen/RISCV/cheri/cheriot-stack-size-export.ll b/llvm/test/CodeGen/RISCV/cheri/cheriot-stack-size-export.ll
@@ -4,7 +4,7 @@ target datalayout = "e-m:e-pf200:64:64:64:32-p:32:32-i64:64-n32-S128-A200-P200-G
 target triple = "riscv32-unknown-unknown"
 
 ; Function Attrs: noinline nounwind optnone
-define dso_local chericcallcce void @_Z9usesStackv() addrspace(200) #0 {
+define dso_local chericcallee void @_Z9usesStackv() addrspace(200) #0 {
 ; CHECK-LABEL: _Z9usesStackv
 ; Make sure that the stack is what we expect.  If this changes, we need to
 ; update the number in the export table below.
@@ -23,13 +23,13 @@ declare dso_local void @foo(i8 addrspace(200)*) addrspace(200) #1
 ; CHECK-LABEL: _Z11usesNoStackv
 ; Make sure we don't allocate anything on the stack here.
 ; CHECK-NOT: csp
-define dso_local chericcallcce void @_Z11usesNoStackv() addrspace(200) #0 {
+define dso_local chericcallee void @_Z11usesNoStackv() addrspace(200) #0 {
 entry:
   ret void
 }
 
 ; Function Attrs: noinline nounwind optnone
-define dso_local chericcallcce void @_Z13usesHugeStackv() addrspace(200) #0 {
+define dso_local chericcallee void @_Z13usesHugeStackv() addrspace(200) #0 {
 ; CHECK-LABEL: _Z13usesHugeStackv
 ; Make sure that we allocate a load of things on the stack, it doesn't matter
 ; if this changes to another large value.
diff --git a/llvm/test/CodeGen/RISCV/cheri/cheriot-stack-size.ll b/llvm/test/CodeGen/RISCV/cheri/cheriot-stack-size.ll
@@ -6,7 +6,7 @@ target triple = "riscv32-unknown-unknown"
 
 ; Explicit 256-byte stack requirement
 ; Function Attrs: minsize nounwind optsize
-define dso_local chericcallcce i32 @needs256() local_unnamed_addr addrspace(200) #0 {
+define dso_local chericcallee i32 @needs256() local_unnamed_addr addrspace(200) #0 {
 entry:
   %call = tail call i32 @foo() #2
   ret i32 %call
@@ -17,23 +17,23 @@ declare i32 @foo() local_unnamed_addr addrspace(200) #1
 
 ; Explicit 512-byte stack requirement
 ; Function Attrs: minsize nounwind optsize
-define dso_local chericcallcce i32 @needs512() local_unnamed_addr addrspace(200) #3 {
+define dso_local chericcallee i32 @needs512() local_unnamed_addr addrspace(200) #3 {
 entry:
   %call = tail call i32 @foo() #2
   ret i32 %call
 }
 
 ; No stack requirement
 ; Function Attrs: minsize nounwind optsize
-define dso_local chericcallcce i32 @noStack() local_unnamed_addr addrspace(200) #4 {
+define dso_local chericcallee i32 @noStack() local_unnamed_addr addrspace(200) #4 {
 entry:
   ret i32 0
 }
 
 ; Implicit 16-byte requirement as a result of spilling the return value (and
 ; the 16-byte alignment requirement)
 ; Function Attrs: minsize nounwind optsize
-define dso_local chericcallcce i32 @tinyStack() local_unnamed_addr addrspace(200) #4 {
+define dso_local chericcallee i32 @tinyStack() local_unnamed_addr addrspace(200) #4 {
 entry:
   %call = tail call i32 @foo() #2
   %add1 = add nsw i32 %call, 1
diff --git a/llvm/test/CodeGen/RISCV/cheri/cheriot-struct-ret.ll b/llvm/test/CodeGen/RISCV/cheri/cheriot-struct-ret.ll
diff --git a/llvm/test/CodeGen/RISCV/cheri/cheriot-zero-ret.ll b/llvm/test/CodeGen/RISCV/cheri/cheriot-zero-ret.ll

Original file line number	Diff line number	Diff line change
`@@ -45,7 +45,7 @@ __attribute__((cheri_method_class(cls)))`
`45`	`45`	`__attribute__((cheri_method_suffix("_cap")))`
`46`	`46`	`void fish(void)`
`47`	`47`	`{`
`48`		`- // CHECK-LABEL: define dso_local chericcallcce void @fish()`
	`48`	`+ // CHECK-LABEL: define dso_local chericcallee void @fish()`
`49`	`49`	`}`
`50`	`50`
`51`	`51`	`__attribute__((cheri_method_suffix("_cap")))`
`@@ -55,7 +55,7 @@ void flibble(void);`
`55`	`55`	`// CHECK-LABEL: define dso_local void @call()`
`56`	`56`	`void call(void)`
`57`	`57`	`{`
`58`		`- // CHECK: call chericcallcce void @fish()`
	`58`	`+ // CHECK: call chericcallee void @fish()`
`59`	`59`	`fish();`
`60`	`60`	`// Check that we get a ccall to cheri_invoke with the correct method number`
`61`	`61`	`// CHECK: load i64, ptr @__cheri_method.cls.fish, align 8, [[$INVARIANT_LOAD]]`
Original file line number	Diff line number	Diff line change
`@@ -1,6 +1,6 @@`
`1`	`1`	`// RUN: %clang_cc1 %s -o - "-triple" "riscv32cheriot-unknown-cheriotrtos" "-emit-llvm" "-mframe-pointer=none" "-mcmodel=small" "-target-abi" "cheriot" "-target-feature" "+xcheriot" "-Oz" "-Werror" "-cheri-compartment=example" \| FileCheck %s`
`2`	`2`
`3`		`-// CHECK: define dso_local chericcallcce i32 @_Z5test2ii(i32 noundef %a0, i32 noundef %a1) local_unnamed_addr addrspace(200) #0`
	`3`	`+// CHECK: define dso_local chericcallee i32 @_Z5test2ii(i32 noundef %a0, i32 noundef %a1) local_unnamed_addr addrspace(200) #0`
`4`	`4`	`__attribute__((cheriot_compartment("example"))) int test2(int a0, int a1) {`
`5`	`5`	`return a0 + a1;`
`6`	`6`	`}`
Original file line number	Diff line number	Diff line change
`@@ -9,7 +9,7 @@ entry:`
`9`	`9`	`ret void`
`10`	`10`	`}`
`11`	`11`
`12`		`-define dso_local chericcallcce void @_Z9say_hellov() local_unnamed_addr addrspace(200) #1 {`
	`12`	`+define dso_local chericcallee void @_Z9say_hellov() local_unnamed_addr addrspace(200) #1 {`
`13`	`13`	`entry:`
`14`	`14`	`store ptr addrspace(200) @_Z11id_functionv, ptr addrspace(200) @f, align 8`
`15`	`15`	`ret void`