diff --git a/clang/lib/Basic/Targets/RISCV.cpp b/clang/lib/Basic/Targets/RISCV.cpp index af20fd1879833..56d248da96cad 100644 --- a/clang/lib/Basic/Targets/RISCV.cpp +++ b/clang/lib/Basic/Targets/RISCV.cpp @@ -379,7 +379,7 @@ bool RISCVTargetInfo::initFeatureMap( if (getTriple().getSubArch() == llvm::Triple::RISCV32SubArch_cheriot_v1) { Features["xcheri"] = true; - Features["cap-mode"] = true; + Features["xcheripurecap"] = true; Features["c"] = true; Features["e"] = true; Features["m"] = true; diff --git a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp index 2c9789ddb5217..19c1445a8e72c 100644 --- a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp +++ b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp @@ -220,7 +220,7 @@ void riscv::getRISCVTargetFeatures(const Driver &D, const llvm::Triple &Triple, << "pure capability ABI requires xcheri extension to be specified"; return; } - Features.push_back("+cap-mode"); + Features.push_back("+xcheripurecap"); } } @@ -232,7 +232,7 @@ void riscv::getRISCVTargetFeatures(const Driver &D, const llvm::Triple &Triple, << "pure capability ABI requires xcheri extension to be specified"; return; } - Features.push_back("+cap-mode"); + Features.push_back("+xcheripurecap"); } } @@ -244,7 +244,7 @@ void riscv::getRISCVTargetFeatures(const Driver &D, const llvm::Triple &Triple, << "pure capability ABI requires xcheri extension to be specified"; return; } - Features.push_back("+cap-mode"); + Features.push_back("+xcheripurecap"); } } @@ -256,7 +256,7 @@ void riscv::getRISCVTargetFeatures(const Driver &D, const llvm::Triple &Triple, << "pure capability ABI requires xcheri extension to be specified"; return; } - Features.push_back("+cap-mode"); + Features.push_back("+xcheripurecap"); } } diff --git a/clang/test/CodeGen/cheri/cheriot-struct-ret.c b/clang/test/CodeGen/cheri/cheriot-struct-ret.c index 9de473733470f..fafeed8c299b7 100644 --- a/clang/test/CodeGen/cheri/cheriot-struct-ret.c +++ b/clang/test/CodeGen/cheri/cheriot-struct-ret.c @@ -810,6 +810,6 @@ __attribute__((cheri_compartment("example"))) void CheckOnePtr () { } -// CHECK: attributes #0 = { mustprogress nofree noinline norecurse nosync nounwind willreturn memory(readwrite, argmem: none, inaccessiblemem: none) "cheri-compartment"="example" "interrupt-state"="enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+c,+cap-mode,+e,+m,+xcheri" } -// CHECK: attributes #1 = { mustprogress nofree noinline norecurse nosync nounwind willreturn memory(readwrite, inaccessiblemem: none) "cheri-compartment"="example" "interrupt-state"="enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+c,+cap-mode,+e,+m,+xcheri" } -// CHECK: attributes #2 = { mustprogress nofree norecurse nosync nounwind willreturn memory(readwrite, inaccessiblemem: none) "cheri-compartment"="example" "interrupt-state"="enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+c,+cap-mode,+e,+m,+xcheri" } +// CHECK: attributes #0 = { mustprogress nofree noinline norecurse nosync nounwind willreturn memory(readwrite, argmem: none, inaccessiblemem: none) "cheri-compartment"="example" "interrupt-state"="enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+c,+e,+m,+xcheri,+xcheripurecap" } +// CHECK: attributes #1 = { mustprogress nofree noinline norecurse nosync nounwind willreturn memory(readwrite, inaccessiblemem: none) "cheri-compartment"="example" "interrupt-state"="enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+c,+e,+m,+xcheri,+xcheripurecap" } +// CHECK: attributes #2 = { mustprogress nofree norecurse nosync nounwind willreturn memory(readwrite, inaccessiblemem: none) "cheri-compartment"="example" "interrupt-state"="enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+c,+e,+m,+xcheri,+xcheripurecap" } diff --git a/clang/test/CodeGen/cheri/riscv/cheriot-static-sealed-value-attr.c b/clang/test/CodeGen/cheri/riscv/cheriot-static-sealed-value-attr.c index 576626e0d52ee..89f2f6eea05c7 100644 --- a/clang/test/CodeGen/cheri/riscv/cheriot-static-sealed-value-attr.c +++ b/clang/test/CodeGen/cheri/riscv/cheriot-static-sealed-value-attr.c @@ -42,6 +42,6 @@ void func() { // CHECK: declare void @doSomething2(ptr addrspace(200) noundef) local_unnamed_addr addrspace(200) #2 // CHECK: attributes #0 = { "cheriot_sealed_value" } -// CHECK: attributes #1 = { minsize nounwind optsize "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+c,+cap-mode,+e,+m,+xcheri" } -// CHECK: attributes #2 = { minsize optsize "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+c,+cap-mode,+e,+m,+xcheri" } +// CHECK: attributes #1 = { minsize nounwind optsize "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+c,+e,+m,+xcheri,+xcheripurecap" } +// CHECK: attributes #2 = { minsize optsize "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+c,+e,+m,+xcheri,+xcheripurecap" } // CHECK: attributes #3 = { minsize nounwind optsize } diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c index 0139c9bfbabd0..63fb3e3c47b32 100644 --- a/clang/test/Driver/print-supported-extensions-riscv.c +++ b/clang/test/Driver/print-supported-extensions-riscv.c @@ -152,6 +152,7 @@ // CHECK-NEXT: svvptc 1.0 'Svvptc' (Obviating Memory-Management Instructions after Marking PTEs Valid) // CHECK-NEXT: xcheri 0.0 'XCheri' (Implements CHERI extension) // CHECK-NEXT: xcheriot 1.0 'XCheriot' (Implements XCheriot extension) +// CHECK-NEXT: xcheripurecap 0.0 'XCheriPureCap' (Implements CHERI pure capability mode) // CHECK-NEXT: xcvalu 1.0 'XCValu' (CORE-V ALU Operations) // CHECK-NEXT: xcvbi 1.0 'XCVbi' (CORE-V Immediate Branching) // CHECK-NEXT: xcvbitmanip 1.0 'XCVbitmanip' (CORE-V Bit Manipulation) diff --git a/lld/test/ELF/cheri/riscv/cheriot_compartment_lo_i.s b/lld/test/ELF/cheri/riscv/cheriot_compartment_lo_i.s index feece61e9bc1f..e5cb7d12ae472 100644 --- a/lld/test/ELF/cheri/riscv/cheriot_compartment_lo_i.s +++ b/lld/test/ELF/cheri/riscv/cheriot_compartment_lo_i.s @@ -1,10 +1,10 @@ # REQUIRES: riscv -# RUN: llvm-mc -triple=riscv32cheriot-unknown-cheriotrtos -mcpu=cheriot -mattr=+c,+xcheri,+xcheriot -filetype=obj %s -o %t.o +# RUN: llvm-mc -triple=riscv32cheriot-unknown-cheriotrtos -mcpu=cheriot -mattr=+c,+xcheri,+xcheripurecap,+xcheriot -filetype=obj %s -o %t.o # RUN: ld.lld %t.o -o %t.exe # RUN: llvm-objdump -d %t.exe | FileCheck %s .attribute 4, 16 - .attribute 5, "rv32e2p0_m2p0_c2p0_zmmul1p0_xcheri0p0_xcheriot1p0" + .attribute 5, "rv32e2p0_m2p0_c2p0_zmmul1p0_xcheri0p0_xcheriot1p0_xcheripurecap1p0" .section .text,"ax",@progbits .globl _start .p2align 1 @@ -43,8 +43,8 @@ _start: # @_Z5entryv near: .word 1 -# CHECK: 00012010 : -# CHECK-NEXT: 12010: 01 00 00 00 00 00 00 00 +# CHECK: 00012020 : +# CHECK-NEXT: 12020: 01 00 00 00 00 00 00 00 .type mid,@object .p2align 12, 0x0 diff --git a/llvm/lib/Object/ELFObjectFile.cpp b/llvm/lib/Object/ELFObjectFile.cpp index bf7876922edae..69f28e9376832 100644 --- a/llvm/lib/Object/ELFObjectFile.cpp +++ b/llvm/lib/Object/ELFObjectFile.cpp @@ -383,7 +383,7 @@ Expected ELFObjectFileBase::getRISCVFeatures() const { if (PlatformFlags & ELF::EF_RISCV_CAP_MODE) { Features.AddFeature("xcheri"); - Features.AddFeature("cap-mode"); + Features.AddFeature("xcheripurecap"); } RISCVAttributeParser Attributes; diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp index 75be904193f53..ae313fd17a9ee 100644 --- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp @@ -3427,7 +3427,7 @@ bool RISCVAsmParser::parseDirectiveOption() { "option requires 'xcheri' extension"); getTargetStreamer().emitDirectiveOptionCapMode(); - setFeatureBits(RISCV::FeatureCapMode, "cap-mode"); + setFeatureBits(RISCV::FeatureVendorXCheriPureCap, "xcheripurecap"); return false; } @@ -3440,7 +3440,7 @@ bool RISCVAsmParser::parseDirectiveOption() { "option requires 'xcheri' extension"); getTargetStreamer().emitDirectiveOptionNoCapMode(); - clearFeatureBits(RISCV::FeatureCapMode, "cap-mode"); + clearFeatureBits(RISCV::FeatureVendorXCheriPureCap, "xcheripurecap"); return false; } diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index b8f77bfeca496..833a88b93c2d5 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -668,14 +668,14 @@ DecodeStatus RISCVDisassembler::getInstruction32(MCInst &MI, uint64_t &Size, uint32_t Insn = support::endian::read32le(Bytes.data()); - TRY_TO_DECODE(STI.hasFeature(RISCV::FeatureCapMode) && - !STI.hasFeature(RISCV::Feature64Bit), - DecoderTableRISCV32CapModeOnly_32, - "RISCV32CapModeOnly_32 table"); - TRY_TO_DECODE(!STI.hasFeature(RISCV::Feature64Bit), - DecoderTableRISCV32Only_32, "RISCV32Only_32 table"); - TRY_TO_DECODE_FEATURE(RISCV::FeatureCapMode, DecoderTableCapModeOnly_32, - "CapModeOnly_32 table"); + TRY_TO_DECODE(STI.hasFeature(RISCV::FeatureVendorXCheriPureCap) && + !STI.hasFeature(RISCV::Feature64Bit), + DecoderTableRISCV32CapModeOnly_32, + "RISCV32CapModeOnly_32 table"); + TRY_TO_DECODE(!STI.hasFeature(RISCV::Feature64Bit), + DecoderTableRISCV32Only_32, "RISCV32Only_32 table"); + TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCheriPureCap, + DecoderTableCapModeOnly_32, "CapModeOnly_32 table"); TRY_TO_DECODE(STI.hasFeature(RISCV::FeatureStdExtZdinx) && !STI.hasFeature(RISCV::Feature64Bit), DecoderTableRV32Zdinx32, @@ -794,11 +794,11 @@ DecodeStatus RISCVDisassembler::getInstruction16(MCInst &MI, uint64_t &Size, Size = 2; uint32_t Insn = support::endian::read16le(Bytes.data()); - TRY_TO_DECODE_AND_ADD_SP(!STI.hasFeature(RISCV::Feature64Bit) && - STI.hasFeature(RISCV::FeatureCapMode), - DecoderTableRISCV32CapModeOnly_16, - "RISCV32CapModeOnly_16"); - TRY_TO_DECODE_AND_ADD_SP(STI.hasFeature(RISCV::FeatureCapMode), + TRY_TO_DECODE_AND_ADD_SP( + !STI.hasFeature(RISCV::Feature64Bit) && + STI.hasFeature(RISCV::FeatureVendorXCheriPureCap), + DecoderTableRISCV32CapModeOnly_16, "RISCV32CapModeOnly_16"); + TRY_TO_DECODE_AND_ADD_SP(STI.hasFeature(RISCV::FeatureVendorXCheriPureCap), DecoderTableCapModeOnly_16, "CapModeOnly_16 table"); TRY_TO_DECODE_AND_ADD_SP(!STI.hasFeature(RISCV::Feature64Bit), DecoderTableRISCV32Only_16, diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp index 2a4148db441e5..5ee06da62e77d 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp @@ -368,7 +368,7 @@ std::pair RISCVAsmBackend::relaxLEB128(const MCAssembler &Asm, // Given a compressed control flow instruction this function returns // the expanded instruction. unsigned RISCVAsmBackend::getRelaxedOpcode(unsigned Op) const { - bool IsCapMode = STI.getFeatureBits()[RISCV::FeatureCapMode]; + bool IsCapMode = STI.getFeatureBits()[RISCV::FeatureVendorXCheriPureCap]; switch (Op) { default: diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp index 0dfa41ca4f559..1d3275a86ba50 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp @@ -148,8 +148,8 @@ void validate(const Triple &TT, const FeatureBitset &FeatureBits) { if (FeatureBits[RISCV::FeatureVendorXCheriot]) { if (!FeatureBits[RISCV::FeatureVendorXCheri]) report_fatal_error("XCheriot extension requires XCheri extension"); - if (!FeatureBits[RISCV::FeatureCapMode]) - report_fatal_error("XCheriot extension requires CapMode"); + if (!FeatureBits[RISCV::FeatureVendorXCheriPureCap]) + report_fatal_error("XCheriot extension requires XCheriPureCap"); } } diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp index a3000598d76b1..00b798dcbb9c0 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp @@ -62,7 +62,7 @@ void RISCVTargetStreamer::setFlagsFromFeatures(const MCSubtargetInfo &STI) { HasRVC = STI.hasFeature(RISCV::FeatureStdExtC) || STI.hasFeature(RISCV::FeatureStdExtZca); HasTSO = STI.hasFeature(RISCV::FeatureStdExtZtso); - IsCapMode = STI.hasFeature(RISCV::FeatureCapMode); + IsCapMode = STI.hasFeature(RISCV::FeatureVendorXCheriPureCap); } void RISCVTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI, diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index a7fc6f20134d3..5bd2bb03e6bba 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -1368,15 +1368,15 @@ def HasCheriRVC : Predicate<"Subtarget->enableCheriRVCInstrs()">, AssemblerPredicate<(all_of (not FeatureCheriNoRVC)), "CHERI RVC Instructions">; -def FeatureCapMode - : SubtargetFeature<"cap-mode", "IsCapMode", "true", - "Capability mode">; -def IsCapMode : Predicate<"Subtarget->isCapMode()">, - AssemblerPredicate<(all_of FeatureCapMode), - "Capability Mode">; -def NotCapMode : Predicate<"!Subtarget->isCapMode()">, - AssemblerPredicate<(all_of (not FeatureCapMode)), - "Not Capability Mode">; +def FeatureVendorXCheriPureCap + : RISCVExtension< + 0, 0, "Implements CHERI pure capability mode", [FeatureVendorXCheri]>; +def IsCapMode : Predicate<"Subtarget->hasVendorXCheriPureCap()">, + AssemblerPredicate<(all_of FeatureVendorXCheriPureCap), + "Capability Mode">; +def NotCapMode : Predicate<"!Subtarget->hasVendorXCheriPureCap()">, + AssemblerPredicate<(all_of(not FeatureVendorXCheriPureCap)), + "Not Capability Mode">; def IsPureCapABI : Predicate<"RISCVABI::isCheriPureCapABI(Subtarget->getTargetABI())">; diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td index 51dea4ea508a7..83a57a84b4931 100644 --- a/llvm/lib/Target/RISCV/RISCVProcessors.td +++ b/llvm/lib/Target/RISCV/RISCVProcessors.td @@ -597,8 +597,9 @@ def RP2350_HAZARD3 : RISCVProcessorModel<"rp2350-hazard3", FeatureStdExtZcmp]>; // NB: FeatureCheri =>'s RVC (!FeatureCheriNoRVC) -def CHERIOT : RISCVProcessorModel<"cheriot", NoSchedModel, - [Feature32Bit, FeatureVendorXCheri, - FeatureVendorXCheriot, FeatureCapMode, - FeatureStdExtC, FeatureStdExtE, - FeatureStdExtM, FeatureUnalignedScalarMem]>; +def CHERIOT + : RISCVProcessorModel<"cheriot", NoSchedModel, + [Feature32Bit, FeatureVendorXCheri, + FeatureVendorXCheriot, FeatureVendorXCheriPureCap, + FeatureStdExtC, FeatureStdExtE, FeatureStdExtM, + FeatureUnalignedScalarMem]>; diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/atomic-rmw-cap-ptr-arg.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/atomic-rmw-cap-ptr-arg.ll index d73508ec61c2f..8f05b529a6c93 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/atomic-rmw-cap-ptr-arg.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/atomic-rmw-cap-ptr-arg.ll @@ -2,8 +2,8 @@ ; DO NOT EDIT -- This file was generated from test/CodeGen/CHERI-Generic/Inputs/atomic-rmw-cap-ptr-arg.ll ; Check that we can generate sensible code for atomic operations using capability pointers on capabilities ; See https://github.com/CTSRD-CHERI/llvm-project/issues/470 -; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+cap-mode,+f -mattr=+a < %s | FileCheck %s --check-prefixes=PURECAP,PURECAP-ATOMICS --allow-unused-prefixes -; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+cap-mode,+f -mattr=-a < %s | FileCheck %s --check-prefixes=PURECAP,PURECAP-LIBCALLS --allow-unused-prefixes +; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+xcheripurecap,+f -mattr=+a < %s | FileCheck %s --check-prefixes=PURECAP,PURECAP-ATOMICS --allow-unused-prefixes +; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+xcheripurecap,+f -mattr=-a < %s | FileCheck %s --check-prefixes=PURECAP,PURECAP-LIBCALLS --allow-unused-prefixes ; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi ilp32f -mattr=+xcheri,+f -mattr=+a < %s | FileCheck %s --check-prefixes=HYBRID,HYBRID-ATOMICS --allow-unused-prefixes ; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi ilp32f -mattr=+xcheri,+f -mattr=-a < %s | FileCheck %s --check-prefixes=HYBRID,HYBRID-LIBCALLS --allow-unused-prefixes diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/atomic-rmw-cap-ptr.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/atomic-rmw-cap-ptr.ll index af5e07e9a8f3f..ae4bcd583c295 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/atomic-rmw-cap-ptr.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/atomic-rmw-cap-ptr.ll @@ -2,8 +2,8 @@ ; DO NOT EDIT -- This file was generated from test/CodeGen/CHERI-Generic/Inputs/atomic-rmw-cap-ptr.ll ; Check that we can generate sensible code for atomic operations using capability pointers ; https://github.com/CTSRD-CHERI/llvm-project/issues/470 -; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+cap-mode,+f -mattr=+a < %s | FileCheck %s --check-prefixes=PURECAP,PURECAP-ATOMICS --allow-unused-prefixes -; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+cap-mode,+f -mattr=-a < %s | FileCheck %s --check-prefixes=PURECAP,PURECAP-LIBCALLS --allow-unused-prefixes +; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+xcheripurecap,+f -mattr=+a < %s | FileCheck %s --check-prefixes=PURECAP,PURECAP-ATOMICS --allow-unused-prefixes +; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+xcheripurecap,+f -mattr=-a < %s | FileCheck %s --check-prefixes=PURECAP,PURECAP-LIBCALLS --allow-unused-prefixes ; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi ilp32f -mattr=+xcheri,+f -mattr=+a < %s | FileCheck %s --check-prefixes=HYBRID,HYBRID-ATOMICS --allow-unused-prefixes ; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi ilp32f -mattr=+xcheri,+f -mattr=-a < %s | FileCheck %s --check-prefixes=HYBRID,HYBRID-LIBCALLS --allow-unused-prefixes diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/bounded-allocas-lifetimes.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/bounded-allocas-lifetimes.ll index 9edc4d128277d..13938abf006cb 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/bounded-allocas-lifetimes.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/bounded-allocas-lifetimes.ll @@ -2,7 +2,7 @@ ; DO NOT EDIT -- This file was generated from test/CodeGen/CHERI-Generic/Inputs/bounded-allocas-lifetimes.ll ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py ; CHERI-GENERIC-UTC: mir -; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+cap-mode,+f %s -o - --stop-after=finalize-isel | FileCheck %s +; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+xcheripurecap,+f %s -o - --stop-after=finalize-isel | FileCheck %s ; Check that lifetime markers don't get lost due to CheriBoundAllocas, as we'd ; risk StackSlotColoring reusing the slot. diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/cap-from-ptr.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/cap-from-ptr.ll index 09e1fc3c5f0cc..dc080e17aa0fe 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/cap-from-ptr.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/cap-from-ptr.ll @@ -3,8 +3,8 @@ ;; Check that we can correctly generate code for llvm.cheri.cap.from.pointer() ;; This previously asserted on RISC-V due to a broken ISel pattern. ;; We pipe this input through instcombine first to ensure SelectionDAG sees canonical IR. -; RUN: opt -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+cap-mode,+f -passes=instcombine -S < %s | FileCheck %s --check-prefix=CHECK-IR -; RUN: opt -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+cap-mode,+f -passes=instcombine -S < %s | llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+cap-mode,+f | FileCheck %s --check-prefix=PURECAP +; RUN: opt -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+xcheripurecap,+f -passes=instcombine -S < %s | FileCheck %s --check-prefix=CHECK-IR +; RUN: opt -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+xcheripurecap,+f -passes=instcombine -S < %s | llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+xcheripurecap,+f | FileCheck %s --check-prefix=PURECAP ; RUN: opt -mtriple=riscv32 --relocation-model=pic -target-abi ilp32f -mattr=+xcheri,+f -passes=instcombine -S < %s | llc -mtriple=riscv32 --relocation-model=pic -target-abi ilp32f -mattr=+xcheri,+f | FileCheck %s --check-prefix=HYBRID define internal ptr addrspace(200) @test(ptr addrspace(200) %ptr, ptr addrspace(200) %cap, i32 %offset) addrspace(200) nounwind { diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/cheri-csub.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/cheri-csub.ll index cb9c2ad24a1c8..2d28f9383c67f 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/cheri-csub.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/cheri-csub.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --scrub-attributes --version 2 ; DO NOT EDIT -- This file was generated from test/CodeGen/CHERI-Generic/Inputs/cheri-csub.ll ; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi ilp32f -mattr=+xcheri,+f %s -o - | FileCheck %s --check-prefix=HYBRID -; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+cap-mode,+f %s -o - | FileCheck %s --check-prefix=PURECAP +; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+xcheripurecap,+f %s -o - | FileCheck %s --check-prefix=PURECAP define i32 @subp(i8 addrspace(200)* readnone %a, i8 addrspace(200)* readnone %b) nounwind { ; HYBRID-LABEL: subp: diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/cheri-intrinsics-folding-broken-module-regression.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/cheri-intrinsics-folding-broken-module-regression.ll index f3db990f090e9..50c6a604f56c6 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/cheri-intrinsics-folding-broken-module-regression.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/cheri-intrinsics-folding-broken-module-regression.ll @@ -3,8 +3,8 @@ ; This used to create a broken function. ; FIXME: the getoffset+add sequence should be folded to an increment ; REQUIRES: mips-registered-target -; RUN: opt -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+cap-mode,+f -S -passes=instcombine %s -o - | FileCheck %s -; RUN: opt -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+cap-mode,+f -S '-passes=default' %s | llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+cap-mode,+f -O3 -o - | FileCheck %s --check-prefix ASM +; RUN: opt -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+xcheripurecap,+f -S -passes=instcombine %s -o - | FileCheck %s +; RUN: opt -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+xcheripurecap,+f -S '-passes=default' %s | llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+xcheripurecap,+f -O3 -o - | FileCheck %s --check-prefix ASM target datalayout = "e-m:e-pf200:64:64:64:32-p:32:32-i64:64-n32-S128-A200-P200-G200" @d = common addrspace(200) global i32 0, align 4 diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/cheri-memfn-call.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/cheri-memfn-call.ll index bd889a8f9400e..2861d2b0edb7c 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/cheri-memfn-call.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/cheri-memfn-call.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --scrub-attributes --version 2 ; DO NOT EDIT -- This file was generated from test/CodeGen/CHERI-Generic/Inputs/cheri-memfn-call.ll ; Check that we call memset_c/memmove_c/memcpy_c in hybrid mode. -; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+cap-mode,+f %s -o - | FileCheck %s --check-prefix=PURECAP +; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+xcheripurecap,+f %s -o - | FileCheck %s --check-prefix=PURECAP ; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi ilp32f -mattr=+xcheri,+f %s -o - | FileCheck %s --check-prefix=HYBRID %struct.x = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/cheri-pointer-comparison.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/cheri-pointer-comparison.ll index 7e2ba46e5dcc3..2dd404d6f0467 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/cheri-pointer-comparison.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/cheri-pointer-comparison.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --scrub-attributes --version 2 ; DO NOT EDIT -- This file was generated from test/CodeGen/CHERI-Generic/Inputs/cheri-pointer-comparison.ll ; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi ilp32f -mattr=+xcheri,+f %s -o - | FileCheck %s --check-prefix=HYBRID -; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+cap-mode,+f %s -o - | FileCheck %s --check-prefix=PURECAP +; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+xcheripurecap,+f %s -o - | FileCheck %s --check-prefix=PURECAP ; This series of tests serves two purposes. ; The first purpose is to check that we generate efficient code for all ; capability comparisons, conditional branches and conditional selects. diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/cmpxchg-cap-ptr.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/cmpxchg-cap-ptr.ll index 946cff07386ba..a54a7f5089acc 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/cmpxchg-cap-ptr.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/cmpxchg-cap-ptr.ll @@ -3,8 +3,8 @@ ; Check that we can generate sensible code for atomic operations using capability pointers on capabilities ; in both hybrid and purecap mode. ; See https://github.com/CTSRD-CHERI/llvm-project/issues/470 -; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+cap-mode,+f -mattr=+a < %s | FileCheck %s --check-prefixes=PURECAP,PURECAP-ATOMICS --allow-unused-prefixes -; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+cap-mode,+f -mattr=-a < %s | FileCheck %s --check-prefixes=PURECAP,PURECAP-LIBCALLS --allow-unused-prefixes +; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+xcheripurecap,+f -mattr=+a < %s | FileCheck %s --check-prefixes=PURECAP,PURECAP-ATOMICS --allow-unused-prefixes +; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+xcheripurecap,+f -mattr=-a < %s | FileCheck %s --check-prefixes=PURECAP,PURECAP-LIBCALLS --allow-unused-prefixes ; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi ilp32f -mattr=+xcheri,+f -mattr=+a < %s | FileCheck %s --check-prefixes=HYBRID,HYBRID-ATOMICS --allow-unused-prefixes ; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi ilp32f -mattr=+xcheri,+f -mattr=+a < %s | FileCheck %s --check-prefixes=HYBRID,HYBRID-LIBCALLS --allow-unused-prefixes diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/dagcombine-ptradd-deleted-regression.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/dagcombine-ptradd-deleted-regression.ll index 755d4c029456c..88ab85881772a 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/dagcombine-ptradd-deleted-regression.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/dagcombine-ptradd-deleted-regression.ll @@ -5,7 +5,7 @@ ; reassociated and delete the synthesised PTRADD node, not just the ADD, which ; the folding code was not prepared for. ; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi ilp32f -mattr=+xcheri,+f %s -o - | FileCheck %s --check-prefix=HYBRID -; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+cap-mode,+f %s -o - | FileCheck %s --check-prefix=PURECAP +; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+xcheripurecap,+f %s -o - | FileCheck %s --check-prefix=PURECAP declare i32 @bar(i32 addrspace(200)*) diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/frameindex-arith.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/frameindex-arith.ll index 47d31ab44ba1a..aee3426edc30a 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/frameindex-arith.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/frameindex-arith.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --scrub-attributes --version 2 ; DO NOT EDIT -- This file was generated from test/CodeGen/CHERI-Generic/Inputs/frameindex-arith.ll -; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+cap-mode,+f %s -o - | FileCheck %s +; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+xcheripurecap,+f %s -o - | FileCheck %s ; Check that we can fold the GEP (PTRADD) into the FrameIndex calculation ; rather than emitting two instructions. diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/function-alias-size.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/function-alias-size.ll index 9253e4da149fa..3e3a90e8184d9 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/function-alias-size.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/function-alias-size.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --scrub-attributes --version 2 ; DO NOT EDIT -- This file was generated from test/CodeGen/CHERI-Generic/Inputs/function-alias-size.ll -; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+cap-mode,+f %s -o - < %s | FileCheck %s --check-prefix=ASM -; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+cap-mode,+f %s -o - -filetype=obj < %s | llvm-objdump --syms -r - | FileCheck %s --check-prefix=OBJDUMP +; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+xcheripurecap,+f %s -o - < %s | FileCheck %s --check-prefix=ASM +; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+xcheripurecap,+f %s -o - -filetype=obj < %s | llvm-objdump --syms -r - | FileCheck %s --check-prefix=OBJDUMP ; The MIPS backend asserts emitting a relocation against an unsized but defined ; function-type global, which was happening with destructor aliases: ; The _ZN*D1Ev destructor is emitted as an alias for the defined _ZN*D2Ev destructor, diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/gvn-capability-store-to-load-fwd.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/gvn-capability-store-to-load-fwd.ll index 8b1e3e464bda0..f8ece3981fd0f 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/gvn-capability-store-to-load-fwd.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/gvn-capability-store-to-load-fwd.ll @@ -11,8 +11,8 @@ ; %2 = trunc i64 %1 to i32 ; truncate to drop the high bits ; It assumed it could get bits 32-63 by doing a ptrtoint, but on CHERI-MIPS ptrtoint returns bits 65-127 -; RUN: opt -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+cap-mode,+f -S -aa-pipeline=basic-aa -passes=gvn -o - %s | FileCheck %s -; RUN: opt -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+cap-mode,+f -S -aa-pipeline=basic-aa -passes=gvn -o - %s | llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+cap-mode,+f -O0 -o - | FileCheck %s --check-prefix=ASM +; RUN: opt -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+xcheripurecap,+f -S -aa-pipeline=basic-aa -passes=gvn -o - %s | FileCheck %s +; RUN: opt -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+xcheripurecap,+f -S -aa-pipeline=basic-aa -passes=gvn -o - %s | llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+xcheripurecap,+f -O0 -o - | FileCheck %s --check-prefix=ASM ; Check in the baseline (broken test now) to show the diff in the fixed commit diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/hoist-alloca.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/hoist-alloca.ll index 3c7e370dfca94..4abc0c392efd7 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/hoist-alloca.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/hoist-alloca.ll @@ -29,8 +29,8 @@ ; } ; } -; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+cap-mode,+f -o %t.mir -stop-before=early-machinelicm < %s -; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+cap-mode,+f -run-pass=early-machinelicm -debug-only=machinelicm %t.mir -o /dev/null 2>%t.dbg +; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+xcheripurecap,+f -o %t.mir -stop-before=early-machinelicm < %s +; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+xcheripurecap,+f -run-pass=early-machinelicm -debug-only=machinelicm %t.mir -o /dev/null 2>%t.dbg ; RUN: FileCheck --input-file=%t.dbg --check-prefix=MACHINELICM-DBG %s ; Check that MachineLICM hoists the CheriBoundedStackPseudoImm (MIPS) / IncOffset+SetBoundsImm (RISCV) instructions ; MACHINELICM-DBG-LABEL: ******** Pre-regalloc Machine LICM: hoist_alloca_uncond @@ -52,7 +52,7 @@ ; MACHINELICM-DBG: Hoisting [[BOUNDS:%[0-9]+]]:gpcr = CSetBoundsImm [[INC]]:gpcr, 88 ; MACHINELICM-DBG-NEXT: from %bb.3 to %bb.0 -; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+cap-mode,+f -O1 -o - < %s | FileCheck %s +; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+xcheripurecap,+f -O1 -o - < %s | FileCheck %s define void @hoist_alloca_uncond(i32 signext %cond) local_unnamed_addr addrspace(200) nounwind { ; CHECK-LABEL: hoist_alloca_uncond: diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/intrinsics-purecap-only.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/intrinsics-purecap-only.ll index 966c57697072a..fe560712d6bc1 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/intrinsics-purecap-only.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/intrinsics-purecap-only.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --scrub-attributes --version 2 ; DO NOT EDIT -- This file was generated from test/CodeGen/CHERI-Generic/Inputs/intrinsics-purecap-only.ll -; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+cap-mode,+f < %s -o - | FileCheck %s --check-prefix=PURECAP +; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+xcheripurecap,+f < %s -o - | FileCheck %s --check-prefix=PURECAP ; RUN: not --crash llc -mtriple=riscv32 --relocation-model=pic -target-abi ilp32f -mattr=+xcheri,+f < %s -o - 2>&1 | FileCheck %s --check-prefix HYBRID-ERROR ; This test checks target-independent CHERI intrinsics that are only available for purecap code diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/intrinsics.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/intrinsics.ll index 15475227394c8..35676e1311adc 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/intrinsics.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/intrinsics.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 ; DO NOT EDIT -- This file was generated from test/CodeGen/CHERI-Generic/Inputs/intrinsics.ll -; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+cap-mode,+f %s -o - < %s | FileCheck %s --check-prefix=PURECAP +; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+xcheripurecap,+f %s -o - < %s | FileCheck %s --check-prefix=PURECAP ; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi ilp32f -mattr=+xcheri,+f -o - < %s | FileCheck %s --check-prefix=HYBRID ; Check that the target-independent CHERI intrinsics are support for all architectures ; The grouping/ordering in this test is based on the RISC-V instruction listing diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/landingpad-non-preemptible.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/landingpad-non-preemptible.ll index d4b0917af8390..31b45fe256107 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/landingpad-non-preemptible.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/landingpad-non-preemptible.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 ; DO NOT EDIT -- This file was generated from test/CodeGen/CHERI-Generic/Inputs/landingpad-non-preemptible.ll -; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+cap-mode,+f --relocation-model=pic < %s -o - | FileCheck %s -; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+cap-mode,+f --relocation-model=pic < %s -o - -filetype=obj | llvm-readobj --relocs --symbols - | FileCheck %s --check-prefix=RELOCS +; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+xcheripurecap,+f --relocation-model=pic < %s -o - | FileCheck %s +; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+xcheripurecap,+f --relocation-model=pic < %s -o - -filetype=obj | llvm-readobj --relocs --symbols - | FileCheck %s --check-prefix=RELOCS ; Capabilities for exception landing pads were using preemptible relocations such as ; .chericap foo + .Ltmp - .Lfunc_begin instead of using a local alias. ; https://github.com/CTSRD-CHERI/llvm-project/issues/512 diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/machinelicm-hoist-csetbounds.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/machinelicm-hoist-csetbounds.ll index 8a3416bbba208..62fba6134d3a8 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/machinelicm-hoist-csetbounds.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/machinelicm-hoist-csetbounds.ll @@ -6,8 +6,8 @@ ; Note: Opt correctly hoists the condition+csetbounds into a preheader, and LLC ; used to unconditionally hoist the csetbounds. -; RUN: opt -data-layout="e-m:e-pf200:64:64:64:32-p:32:32-i64:64-n32-S128-A200-P200-G200" -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+cap-mode,+f "-passes=default" -S < %s | FileCheck %s --check-prefix=HOIST-OPT -; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+cap-mode,+f -O3 < %s | FileCheck %s +; RUN: opt -data-layout="e-m:e-pf200:64:64:64:32-p:32:32-i64:64-n32-S128-A200-P200-G200" -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+xcheripurecap,+f "-passes=default" -S < %s | FileCheck %s --check-prefix=HOIST-OPT +; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+xcheripurecap,+f -O3 < %s | FileCheck %s ; Generated from the following C code (with subobject bounds): ; struct foo { diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/memcpy-from-constant.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/memcpy-from-constant.ll index 3c3b6520ae129..9c49cca9353f5 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/memcpy-from-constant.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/memcpy-from-constant.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --scrub-attributes --version 2 ; DO NOT EDIT -- This file was generated from test/CodeGen/CHERI-Generic/Inputs/memcpy-from-constant.ll ;; Copying from a zero constant can be converted to a memset (even with the tag preservation flags) -; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+cap-mode,+f < %s -o - | FileCheck %s +; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+xcheripurecap,+f < %s -o - | FileCheck %s @a = internal addrspace(200) constant ptr addrspace(200) null @b = internal addrspace(200) constant ptr addrspace(200) null diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/memcpy-no-preserve-tags-attr.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/memcpy-no-preserve-tags-attr.ll index de4c319a5e30e..bddeed2821306 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/memcpy-no-preserve-tags-attr.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/memcpy-no-preserve-tags-attr.ll @@ -2,7 +2,7 @@ ; DO NOT EDIT -- This file was generated from test/CodeGen/CHERI-Generic/Inputs/memcpy-no-preserve-tags-attr.ll ; Check that the no_preserve_tags annotation on memcpy/memmove intrinsics allows ; use to inline struct copies >= capability size. -; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+cap-mode,+f -o - < %s | FileCheck %s +; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+xcheripurecap,+f -o - < %s | FileCheck %s %struct.pair = type { i32, i32 } diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/memcpy-preserve-tags-assume-aligned.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/memcpy-preserve-tags-assume-aligned.ll index 15a54d5f6134a..a84f0746ab029 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/memcpy-preserve-tags-assume-aligned.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/memcpy-preserve-tags-assume-aligned.ll @@ -2,7 +2,7 @@ ; DO NOT EDIT -- This file was generated from test/CodeGen/CHERI-Generic/Inputs/memcpy-preserve-tags-assume-aligned.ll ; Check that __builtin_assume_aligned does the right thing and allows us to elide the memcpy ; call even with must_preserve_cheri_tags attribute (run instcombine to propagate assume information) -; RUN: opt -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+cap-mode,+f -S -passes=instcombine < %s | llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+cap-mode,+f -O2 -o - | FileCheck %s +; RUN: opt -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+xcheripurecap,+f -S -passes=instcombine < %s | llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+xcheripurecap,+f -O2 -o - | FileCheck %s target datalayout = "e-m:e-pf200:64:64:64:32-p:32:32-i64:64-n32-S128-A200-P200-G200" declare void @llvm.memcpy.p200i8.p200i8.i32(i8 addrspace(200)* nocapture writeonly, i8 addrspace(200)* nocapture readonly, i32, i1) diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/memcpy-preserve-tags-size-not-multiple.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/memcpy-preserve-tags-size-not-multiple.ll index f7a75ef9d1152..68d0978f39722 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/memcpy-preserve-tags-size-not-multiple.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/memcpy-preserve-tags-size-not-multiple.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --scrub-attributes --version 2 ; DO NOT EDIT -- This file was generated from test/CodeGen/CHERI-Generic/Inputs/memcpy-preserve-tags-size-not-multiple.ll -; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+cap-mode,+f -o - -O0 -verify-machineinstrs %s | FileCheck %s -check-prefixes CHECK +; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+xcheripurecap,+f -o - -O0 -verify-machineinstrs %s | FileCheck %s -check-prefixes CHECK ; Check that we can inline memmove/memcpy despite having the must_preserve_cheri_tags property and the size not ; being a multiple of CAP_SIZE. Since the pointers are aligned we can start with capability copies and use ; word/byte copies for the trailing bytes. diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/memcpy-zeroinit.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/memcpy-zeroinit.ll index 382655b6ed467..8f46f4916a60d 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/memcpy-zeroinit.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/memcpy-zeroinit.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --scrub-attributes --version 2 ; DO NOT EDIT -- This file was generated from test/CodeGen/CHERI-Generic/Inputs/memcpy-zeroinit.ll -; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+cap-mode,+f < %s -o - | FileCheck %s +; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+xcheripurecap,+f < %s -o - | FileCheck %s ; Check that the copy from the zeroinitializer global is turned into a series of zero stores ; or memset() as long as the memcpy is not volatile: diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/optsize-preserve-tags-memcpy-crash.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/optsize-preserve-tags-memcpy-crash.ll index 87421de9676b3..09db63e59c7f0 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/optsize-preserve-tags-memcpy-crash.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/optsize-preserve-tags-memcpy-crash.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --scrub-attributes --version 2 ; DO NOT EDIT -- This file was generated from test/CodeGen/CHERI-Generic/Inputs/optsize-preserve-tags-memcpy-crash.ll -; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+cap-mode,+f < %s -o - | FileCheck %s +; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+xcheripurecap,+f < %s -o - | FileCheck %s ; The following code copying 31 bytes (with capability alignment) using the ; must_preserve_tags attribute used to trigger a "(Align < CapSize)" assertion ; inside diagnoseInefficientCheriMemOp() when compiling with -Oz. diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/ptrtoint.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/ptrtoint.ll index fd7aede769115..952106e48c71f 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/ptrtoint.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/ptrtoint.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --scrub-attributes --version 2 ; DO NOT EDIT -- This file was generated from test/CodeGen/CHERI-Generic/Inputs/ptrtoint.ll ;; Check that we can correctly generate code for ptrtoint and perform simple folds -; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+cap-mode,+f < %s | FileCheck %s +; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+xcheripurecap,+f < %s | FileCheck %s ; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi ilp32f -mattr=+xcheri,+f < %s | FileCheck %s --check-prefix=HYBRID define internal i32 @ptrtoint(i8 addrspace(200)* %cap) addrspace(200) nounwind { diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/purecap-jumptable.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/purecap-jumptable.ll index 7707e5d0fbb86..4157f5eb032af 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/purecap-jumptable.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/purecap-jumptable.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 ; DO NOT EDIT -- This file was generated from test/CodeGen/CHERI-Generic/Inputs/purecap-jumptable.ll -; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+cap-mode,+f < %s -o - | FileCheck %s -; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+cap-mode,+f -relocation-model=static < %s -o - | FileCheck %s +; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+xcheripurecap,+f < %s -o - | FileCheck %s +; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+xcheripurecap,+f -relocation-model=static < %s -o - | FileCheck %s ; Check that we can generate jump tables for switch statements. ; TODO: this is currently not implemented for CHERI-RISC-V diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/setoffset-multiple-uses.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/setoffset-multiple-uses.ll index b9a22c3b30d65..59fe0403b345c 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/setoffset-multiple-uses.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/setoffset-multiple-uses.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --scrub-attributes --version 2 ; DO NOT EDIT -- This file was generated from test/CodeGen/CHERI-Generic/Inputs/setoffset-multiple-uses.ll ; RUN: opt -S -passes=instcombine -o - %s | FileCheck %s -; RUN: opt -S -passes=instcombine -o - %s | llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+cap-mode,+f -O1 - -o - | %cheri_FileCheck %s --check-prefix ASM +; RUN: opt -S -passes=instcombine -o - %s | llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+xcheripurecap,+f -O1 - -o - | %cheri_FileCheck %s --check-prefix ASM target datalayout = "e-m:e-pf200:64:64:64:32-p:32:32-i64:64-n32-S128-A200-P200-G200" ; Reduced test case for a crash in the new optimization to fold multiple setoffset calls (orignally found when compiling libunwind) diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/stack-bounds-dynamic-alloca.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/stack-bounds-dynamic-alloca.ll index c156990216aff..85804365a6a64 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/stack-bounds-dynamic-alloca.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/stack-bounds-dynamic-alloca.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --scrub-attributes --version 2 ; DO NOT EDIT -- This file was generated from test/CodeGen/CHERI-Generic/Inputs/stack-bounds-dynamic-alloca.ll -; RUN: opt -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+cap-mode,+f -passes=cheri-bound-allocas -o - -S %s | FileCheck %s -; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+cap-mode,+f -O0 %s -o - | FileCheck %s -check-prefix ASM -; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+cap-mode,+f -O2 %s -o - | FileCheck %s -check-prefix ASM-OPT +; RUN: opt -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+xcheripurecap,+f -passes=cheri-bound-allocas -o - -S %s | FileCheck %s +; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+xcheripurecap,+f -O0 %s -o - | FileCheck %s -check-prefix ASM +; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+xcheripurecap,+f -O2 %s -o - | FileCheck %s -check-prefix ASM-OPT ; reduced C test case: ; __builtin_va_list a; diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/stack-bounds-opaque-spill-too-early.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/stack-bounds-opaque-spill-too-early.ll index 255fb77b53738..0b9dbcd7afc4f 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/stack-bounds-opaque-spill-too-early.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/stack-bounds-opaque-spill-too-early.ll @@ -4,9 +4,9 @@ ;; miscompilations in the stack bounding pass (the unbounded value was used instead of ;; the bounded one due to the removal of the bitcast instructions). ; REQUIRES: asserts -; RUN: opt -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+cap-mode,+f -passes=cheri-bound-allocas -o - -S %s -debug-only=cheri-bound-allocas 2>%t.dbg| FileCheck %s +; RUN: opt -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+xcheripurecap,+f -passes=cheri-bound-allocas -o - -S %s -debug-only=cheri-bound-allocas 2>%t.dbg| FileCheck %s ; RUN: FileCheck %s -input-file=%t.dbg -check-prefix DBG -; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+cap-mode,+f %s -o - | FileCheck %s -check-prefix ASM +; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+xcheripurecap,+f %s -o - | FileCheck %s -check-prefix ASM target datalayout = "e-m:e-pf200:64:64:64:32-p:32:32-i64:64-n32-S128-A200-P200-G200" ; DBG-LABEL: Checking function lazy_bind_args diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/stack-bounds-pass-phi.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/stack-bounds-pass-phi.ll index c3972fa9fe5be..8c157d981db90 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/stack-bounds-pass-phi.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/stack-bounds-pass-phi.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --scrub-attributes --version 2 ; DO NOT EDIT -- This file was generated from test/CodeGen/CHERI-Generic/Inputs/stack-bounds-pass-phi.ll ; REQUIRES: asserts -; RUN: opt -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+cap-mode,+f -passes=cheri-bound-allocas %s -o - -S -cheri-stack-bounds=if-needed \ +; RUN: opt -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+xcheripurecap,+f -passes=cheri-bound-allocas %s -o - -S -cheri-stack-bounds=if-needed \ ; RUN: -cheri-stack-bounds-single-intrinsic-threshold=10 -debug-only=cheri-bound-allocas 2>%t.dbg | FileCheck %s -; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+cap-mode,+f -cheri-stack-bounds=if-needed -O2 -cheri-stack-bounds-single-intrinsic-threshold=10 < %s | %cheri_FileCheck %s -check-prefix ASM +; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+xcheripurecap,+f -cheri-stack-bounds=if-needed -O2 -cheri-stack-bounds-single-intrinsic-threshold=10 < %s | %cheri_FileCheck %s -check-prefix ASM ; RUN: FileCheck %s -check-prefix DBG -input-file=%t.dbg target datalayout = "e-m:e-pf200:64:64:64:32-p:32:32-i64:64-n32-S128-A200-P200-G200" diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/stack-spill-unnecessary.c.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/stack-spill-unnecessary.c.ll index 70b13412cd5d5..33e440994739d 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/stack-spill-unnecessary.c.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/stack-spill-unnecessary.c.ll @@ -5,9 +5,9 @@ ; Previously we were moving the allocation of the register that is only used later to the beginning of ; the function and saving+restoring it instead of materializing it just before -; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+cap-mode,+f -O2 --cheri-stack-bounds-single-intrinsic-threshold=0 < %s | %cheri_FileCheck %s --check-prefixes=CHECK +; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+xcheripurecap,+f -O2 --cheri-stack-bounds-single-intrinsic-threshold=0 < %s | %cheri_FileCheck %s --check-prefixes=CHECK ; Always use a single intrinsic for the calls (should result in same codegen) -; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+cap-mode,+f -O2 --cheri-stack-bounds-single-intrinsic-threshold=0 < %s | %cheri_FileCheck %s --check-prefixes=CHECK +; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+xcheripurecap,+f -O2 --cheri-stack-bounds-single-intrinsic-threshold=0 < %s | %cheri_FileCheck %s --check-prefixes=CHECK ; RUN: sed 's/addrspace(200)/addrspace(0)/g' %s | llc -mtriple=riscv32 --relocation-model=pic -target-abi ilp32f -mattr=+xcheri,+f | FileCheck --check-prefix HYBRID %s diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/stackframe-intrinsics.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/stackframe-intrinsics.ll index 1670ff55de111..109878322829b 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/stackframe-intrinsics.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/stackframe-intrinsics.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --scrub-attributes --version 2 ; DO NOT EDIT -- This file was generated from test/CodeGen/CHERI-Generic/Inputs/stackframe-intrinsics.ll -; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+cap-mode,+f %s -o - | FileCheck %s --check-prefix=PURECAP +; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+xcheripurecap,+f %s -o - | FileCheck %s --check-prefix=PURECAP ; RUN: sed 's/addrspace(200)/addrspace(0)/g' %s | llc -mtriple=riscv32 --relocation-model=pic -target-abi ilp32f -mattr=+xcheri,+f | FileCheck %s --check-prefix HYBRID ; Check that we can lower llvm.frameaddress/llvm.returnaddress diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/strcpy-to-memcpy-no-tags.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/strcpy-to-memcpy-no-tags.ll index f18c8bba532bd..c385acaf07e65 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/strcpy-to-memcpy-no-tags.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/strcpy-to-memcpy-no-tags.ll @@ -6,7 +6,7 @@ ; Note: unlike other tests we do want to test attributes in this one. ; CHERI-GENERIC-UTC: opt --function-signature ; RUN: opt < %s -passes=instcombine -S | FileCheck %s --check-prefix=CHECK-IR -; RUN: opt < %s -passes=instcombine -S | llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+cap-mode,+f - -o - | FileCheck %s --check-prefix=CHECK-ASM +; RUN: opt < %s -passes=instcombine -S | llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+xcheripurecap,+f - -o - | FileCheck %s --check-prefix=CHECK-ASM target datalayout = "e-m:e-pf200:64:64:64:32-p:32:32-i64:64-n32-S128-A200-P200-G200" @str = private unnamed_addr addrspace(200) constant [17 x i8] c"exactly 16 chars\00", align 4 diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/subobject-bounds-redundant-setbounds.c.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/subobject-bounds-redundant-setbounds.c.ll index 1a1076df70a2f..dd4f709d40abe 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/subobject-bounds-redundant-setbounds.c.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/subobject-bounds-redundant-setbounds.c.ll @@ -2,9 +2,9 @@ ; DO NOT EDIT -- This file was generated from test/CodeGen/CHERI-Generic/Inputs/subobject-bounds-redundant-setbounds.c.ll ; REQUIRES: asserts ; RUN: rm -f %t.dbg-opt %t.dbg-llc -; RUN: opt -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+cap-mode,+f -passes=cheri-bound-allocas -debug-only=cheri-bound-allocas -S -o - %s 2>%t.dbg-opt | FileCheck %s +; RUN: opt -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+xcheripurecap,+f -passes=cheri-bound-allocas -debug-only=cheri-bound-allocas -S -o - %s 2>%t.dbg-opt | FileCheck %s ; RUN: FileCheck %s -input-file=%t.dbg-opt -check-prefix DBG -; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+cap-mode,+f -debug-only=cheri-bound-allocas -o - %s 2>%t.dbg-llc | FileCheck %s -check-prefix ASM +; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+xcheripurecap,+f -debug-only=cheri-bound-allocas -o - %s 2>%t.dbg-llc | FileCheck %s -check-prefix ASM ; RUN: FileCheck %s -input-file=%t.dbg-llc -check-prefix DBG target datalayout = "e-m:e-pf200:64:64:64:32-p:32:32-i64:64-n32-S128-A200-P200-G200" diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/trunc-load.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/trunc-load.ll index c07083f39997a..bba2cc391d1a0 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/trunc-load.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/trunc-load.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --scrub-attributes --version 2 ; DO NOT EDIT -- This file was generated from test/CodeGen/CHERI-Generic/Inputs/trunc-load.ll -; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+cap-mode,+f %s -o - < %s | FileCheck %s --check-prefix=PURECAP +; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+xcheripurecap,+f %s -o - < %s | FileCheck %s --check-prefix=PURECAP ; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi ilp32f -mattr=+xcheri,+f -o - < %s | FileCheck %s --check-prefix=HYBRID define zeroext i16 @trunc_load_zext(i32 addrspace(200)* %p) { diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/unaligned-loads-stores-purecap.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/unaligned-loads-stores-purecap.ll index 0a95988bab271..ac6165170b5da 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/unaligned-loads-stores-purecap.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/unaligned-loads-stores-purecap.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --scrub-attributes --version 2 ; DO NOT EDIT -- This file was generated from test/CodeGen/CHERI-Generic/Inputs/unaligned-loads-stores-purecap.ll -; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+cap-mode,+f %s -o - | FileCheck %s +; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+xcheripurecap,+f %s -o - | FileCheck %s @a1 = addrspace(200) global i64 0, align 1 @a2 = addrspace(200) global i64 0, align 2 diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/atomic-rmw-cap-ptr-arg.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/atomic-rmw-cap-ptr-arg.ll index ab33f739afeb1..6654ea98b03ac 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/atomic-rmw-cap-ptr-arg.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/atomic-rmw-cap-ptr-arg.ll @@ -2,8 +2,8 @@ ; DO NOT EDIT -- This file was generated from test/CodeGen/CHERI-Generic/Inputs/atomic-rmw-cap-ptr-arg.ll ; Check that we can generate sensible code for atomic operations using capability pointers on capabilities ; See https://github.com/CTSRD-CHERI/llvm-project/issues/470 -; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+cap-mode,+f,+d -mattr=+a < %s | FileCheck %s --check-prefixes=PURECAP,PURECAP-ATOMICS --allow-unused-prefixes -; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+cap-mode,+f,+d -mattr=-a < %s | FileCheck %s --check-prefixes=PURECAP,PURECAP-LIBCALLS --allow-unused-prefixes +; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+xcheripurecap,+f,+d -mattr=+a < %s | FileCheck %s --check-prefixes=PURECAP,PURECAP-ATOMICS --allow-unused-prefixes +; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+xcheripurecap,+f,+d -mattr=-a < %s | FileCheck %s --check-prefixes=PURECAP,PURECAP-LIBCALLS --allow-unused-prefixes ; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi lp64d -mattr=+xcheri,+f,+d -mattr=+a < %s | FileCheck %s --check-prefixes=HYBRID,HYBRID-ATOMICS --allow-unused-prefixes ; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi lp64d -mattr=+xcheri,+f,+d -mattr=-a < %s | FileCheck %s --check-prefixes=HYBRID,HYBRID-LIBCALLS --allow-unused-prefixes diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/atomic-rmw-cap-ptr.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/atomic-rmw-cap-ptr.ll index 167b7efd2dd1e..2b39924b669e2 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/atomic-rmw-cap-ptr.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/atomic-rmw-cap-ptr.ll @@ -2,8 +2,8 @@ ; DO NOT EDIT -- This file was generated from test/CodeGen/CHERI-Generic/Inputs/atomic-rmw-cap-ptr.ll ; Check that we can generate sensible code for atomic operations using capability pointers ; https://github.com/CTSRD-CHERI/llvm-project/issues/470 -; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+cap-mode,+f,+d -mattr=+a < %s | FileCheck %s --check-prefixes=PURECAP,PURECAP-ATOMICS --allow-unused-prefixes -; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+cap-mode,+f,+d -mattr=-a < %s | FileCheck %s --check-prefixes=PURECAP,PURECAP-LIBCALLS --allow-unused-prefixes +; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+xcheripurecap,+f,+d -mattr=+a < %s | FileCheck %s --check-prefixes=PURECAP,PURECAP-ATOMICS --allow-unused-prefixes +; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+xcheripurecap,+f,+d -mattr=-a < %s | FileCheck %s --check-prefixes=PURECAP,PURECAP-LIBCALLS --allow-unused-prefixes ; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi lp64d -mattr=+xcheri,+f,+d -mattr=+a < %s | FileCheck %s --check-prefixes=HYBRID,HYBRID-ATOMICS --allow-unused-prefixes ; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi lp64d -mattr=+xcheri,+f,+d -mattr=-a < %s | FileCheck %s --check-prefixes=HYBRID,HYBRID-LIBCALLS --allow-unused-prefixes diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/bounded-allocas-lifetimes.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/bounded-allocas-lifetimes.ll index 9ff00fe1c1c24..a43b8a98d945a 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/bounded-allocas-lifetimes.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/bounded-allocas-lifetimes.ll @@ -2,7 +2,7 @@ ; DO NOT EDIT -- This file was generated from test/CodeGen/CHERI-Generic/Inputs/bounded-allocas-lifetimes.ll ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py ; CHERI-GENERIC-UTC: mir -; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+cap-mode,+f,+d %s -o - --stop-after=finalize-isel | FileCheck %s +; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+xcheripurecap,+f,+d %s -o - --stop-after=finalize-isel | FileCheck %s ; Check that lifetime markers don't get lost due to CheriBoundAllocas, as we'd ; risk StackSlotColoring reusing the slot. diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/cap-from-ptr.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/cap-from-ptr.ll index 239b52dadf5ba..5b57a41fd7d2e 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/cap-from-ptr.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/cap-from-ptr.ll @@ -3,8 +3,8 @@ ;; Check that we can correctly generate code for llvm.cheri.cap.from.pointer() ;; This previously asserted on RISC-V due to a broken ISel pattern. ;; We pipe this input through instcombine first to ensure SelectionDAG sees canonical IR. -; RUN: opt -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+cap-mode,+f,+d -passes=instcombine -S < %s | FileCheck %s --check-prefix=CHECK-IR -; RUN: opt -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+cap-mode,+f,+d -passes=instcombine -S < %s | llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+cap-mode,+f,+d | FileCheck %s --check-prefix=PURECAP +; RUN: opt -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+xcheripurecap,+f,+d -passes=instcombine -S < %s | FileCheck %s --check-prefix=CHECK-IR +; RUN: opt -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+xcheripurecap,+f,+d -passes=instcombine -S < %s | llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+xcheripurecap,+f,+d | FileCheck %s --check-prefix=PURECAP ; RUN: opt -mtriple=riscv64 --relocation-model=pic -target-abi lp64d -mattr=+xcheri,+f,+d -passes=instcombine -S < %s | llc -mtriple=riscv64 --relocation-model=pic -target-abi lp64d -mattr=+xcheri,+f,+d | FileCheck %s --check-prefix=HYBRID define internal ptr addrspace(200) @test(ptr addrspace(200) %ptr, ptr addrspace(200) %cap, i64 %offset) addrspace(200) nounwind { diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/cheri-csub.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/cheri-csub.ll index 5cb3b4342b037..9d63d921b07f2 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/cheri-csub.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/cheri-csub.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --scrub-attributes --version 2 ; DO NOT EDIT -- This file was generated from test/CodeGen/CHERI-Generic/Inputs/cheri-csub.ll ; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi lp64d -mattr=+xcheri,+f,+d %s -o - | FileCheck %s --check-prefix=HYBRID -; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+cap-mode,+f,+d %s -o - | FileCheck %s --check-prefix=PURECAP +; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+xcheripurecap,+f,+d %s -o - | FileCheck %s --check-prefix=PURECAP define i64 @subp(i8 addrspace(200)* readnone %a, i8 addrspace(200)* readnone %b) nounwind { ; HYBRID-LABEL: subp: diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/cheri-intrinsics-folding-broken-module-regression.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/cheri-intrinsics-folding-broken-module-regression.ll index aab44e96f1eb7..52538fdca0eb7 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/cheri-intrinsics-folding-broken-module-regression.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/cheri-intrinsics-folding-broken-module-regression.ll @@ -3,8 +3,8 @@ ; This used to create a broken function. ; FIXME: the getoffset+add sequence should be folded to an increment ; REQUIRES: mips-registered-target -; RUN: opt -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+cap-mode,+f,+d -S -passes=instcombine %s -o - | FileCheck %s -; RUN: opt -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+cap-mode,+f,+d -S '-passes=default' %s | llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+cap-mode,+f,+d -O3 -o - | FileCheck %s --check-prefix ASM +; RUN: opt -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+xcheripurecap,+f,+d -S -passes=instcombine %s -o - | FileCheck %s +; RUN: opt -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+xcheripurecap,+f,+d -S '-passes=default' %s | llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+xcheripurecap,+f,+d -O3 -o - | FileCheck %s --check-prefix ASM target datalayout = "e-m:e-pf200:128:128:128:64-p:64:64-i64:64-i128:128-n64-S128-A200-P200-G200" @d = common addrspace(200) global i64 0, align 4 diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/cheri-memfn-call.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/cheri-memfn-call.ll index 3107b0cde4969..0098660981577 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/cheri-memfn-call.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/cheri-memfn-call.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --scrub-attributes --version 2 ; DO NOT EDIT -- This file was generated from test/CodeGen/CHERI-Generic/Inputs/cheri-memfn-call.ll ; Check that we call memset_c/memmove_c/memcpy_c in hybrid mode. -; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+cap-mode,+f,+d %s -o - | FileCheck %s --check-prefix=PURECAP +; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+xcheripurecap,+f,+d %s -o - | FileCheck %s --check-prefix=PURECAP ; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi lp64d -mattr=+xcheri,+f,+d %s -o - | FileCheck %s --check-prefix=HYBRID %struct.x = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/cheri-pointer-comparison.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/cheri-pointer-comparison.ll index b6fa5582958d6..26a5599781aca 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/cheri-pointer-comparison.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/cheri-pointer-comparison.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --scrub-attributes --version 2 ; DO NOT EDIT -- This file was generated from test/CodeGen/CHERI-Generic/Inputs/cheri-pointer-comparison.ll ; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi lp64d -mattr=+xcheri,+f,+d %s -o - | FileCheck %s --check-prefix=HYBRID -; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+cap-mode,+f,+d %s -o - | FileCheck %s --check-prefix=PURECAP +; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+xcheripurecap,+f,+d %s -o - | FileCheck %s --check-prefix=PURECAP ; This series of tests serves two purposes. ; The first purpose is to check that we generate efficient code for all ; capability comparisons, conditional branches and conditional selects. diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/cmpxchg-cap-ptr.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/cmpxchg-cap-ptr.ll index 804e865530b41..6934cd220fc3c 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/cmpxchg-cap-ptr.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/cmpxchg-cap-ptr.ll @@ -3,8 +3,8 @@ ; Check that we can generate sensible code for atomic operations using capability pointers on capabilities ; in both hybrid and purecap mode. ; See https://github.com/CTSRD-CHERI/llvm-project/issues/470 -; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+cap-mode,+f,+d -mattr=+a < %s | FileCheck %s --check-prefixes=PURECAP,PURECAP-ATOMICS --allow-unused-prefixes -; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+cap-mode,+f,+d -mattr=-a < %s | FileCheck %s --check-prefixes=PURECAP,PURECAP-LIBCALLS --allow-unused-prefixes +; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+xcheripurecap,+f,+d -mattr=+a < %s | FileCheck %s --check-prefixes=PURECAP,PURECAP-ATOMICS --allow-unused-prefixes +; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+xcheripurecap,+f,+d -mattr=-a < %s | FileCheck %s --check-prefixes=PURECAP,PURECAP-LIBCALLS --allow-unused-prefixes ; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi lp64d -mattr=+xcheri,+f,+d -mattr=+a < %s | FileCheck %s --check-prefixes=HYBRID,HYBRID-ATOMICS --allow-unused-prefixes ; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi lp64d -mattr=+xcheri,+f,+d -mattr=+a < %s | FileCheck %s --check-prefixes=HYBRID,HYBRID-LIBCALLS --allow-unused-prefixes diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/dagcombine-ptradd-deleted-regression.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/dagcombine-ptradd-deleted-regression.ll index ce370954abcd9..4b0c3f6e6c579 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/dagcombine-ptradd-deleted-regression.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/dagcombine-ptradd-deleted-regression.ll @@ -5,7 +5,7 @@ ; reassociated and delete the synthesised PTRADD node, not just the ADD, which ; the folding code was not prepared for. ; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi lp64d -mattr=+xcheri,+f,+d %s -o - | FileCheck %s --check-prefix=HYBRID -; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+cap-mode,+f,+d %s -o - | FileCheck %s --check-prefix=PURECAP +; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+xcheripurecap,+f,+d %s -o - | FileCheck %s --check-prefix=PURECAP declare i32 @bar(i32 addrspace(200)*) diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/frameindex-arith.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/frameindex-arith.ll index b640c405e5f65..3bea36d98ea4c 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/frameindex-arith.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/frameindex-arith.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --scrub-attributes --version 2 ; DO NOT EDIT -- This file was generated from test/CodeGen/CHERI-Generic/Inputs/frameindex-arith.ll -; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+cap-mode,+f,+d %s -o - | FileCheck %s +; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+xcheripurecap,+f,+d %s -o - | FileCheck %s ; Check that we can fold the GEP (PTRADD) into the FrameIndex calculation ; rather than emitting two instructions. diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/function-alias-size.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/function-alias-size.ll index 0ff895acb80d5..298d3e7c80fb8 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/function-alias-size.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/function-alias-size.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --scrub-attributes --version 2 ; DO NOT EDIT -- This file was generated from test/CodeGen/CHERI-Generic/Inputs/function-alias-size.ll -; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+cap-mode,+f,+d %s -o - < %s | FileCheck %s --check-prefix=ASM -; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+cap-mode,+f,+d %s -o - -filetype=obj < %s | llvm-objdump --syms -r - | FileCheck %s --check-prefix=OBJDUMP +; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+xcheripurecap,+f,+d %s -o - < %s | FileCheck %s --check-prefix=ASM +; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+xcheripurecap,+f,+d %s -o - -filetype=obj < %s | llvm-objdump --syms -r - | FileCheck %s --check-prefix=OBJDUMP ; The MIPS backend asserts emitting a relocation against an unsized but defined ; function-type global, which was happening with destructor aliases: ; The _ZN*D1Ev destructor is emitted as an alias for the defined _ZN*D2Ev destructor, diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/gvn-capability-store-to-load-fwd.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/gvn-capability-store-to-load-fwd.ll index aa26defc127a4..8f29ad64e83f9 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/gvn-capability-store-to-load-fwd.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/gvn-capability-store-to-load-fwd.ll @@ -11,8 +11,8 @@ ; %2 = trunc i64 %1 to i32 ; truncate to drop the high bits ; It assumed it could get bits 32-63 by doing a ptrtoint, but on CHERI-MIPS ptrtoint returns bits 65-127 -; RUN: opt -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+cap-mode,+f,+d -S -aa-pipeline=basic-aa -passes=gvn -o - %s | FileCheck %s -; RUN: opt -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+cap-mode,+f,+d -S -aa-pipeline=basic-aa -passes=gvn -o - %s | llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+cap-mode,+f,+d -O0 -o - | FileCheck %s --check-prefix=ASM +; RUN: opt -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+xcheripurecap,+f,+d -S -aa-pipeline=basic-aa -passes=gvn -o - %s | FileCheck %s +; RUN: opt -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+xcheripurecap,+f,+d -S -aa-pipeline=basic-aa -passes=gvn -o - %s | llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+xcheripurecap,+f,+d -O0 -o - | FileCheck %s --check-prefix=ASM ; Check in the baseline (broken test now) to show the diff in the fixed commit diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/hoist-alloca.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/hoist-alloca.ll index 4c7a9fe17d987..b16c202ea2f40 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/hoist-alloca.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/hoist-alloca.ll @@ -29,8 +29,8 @@ ; } ; } -; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+cap-mode,+f,+d -o %t.mir -stop-before=early-machinelicm < %s -; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+cap-mode,+f,+d -run-pass=early-machinelicm -debug-only=machinelicm %t.mir -o /dev/null 2>%t.dbg +; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+xcheripurecap,+f,+d -o %t.mir -stop-before=early-machinelicm < %s +; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+xcheripurecap,+f,+d -run-pass=early-machinelicm -debug-only=machinelicm %t.mir -o /dev/null 2>%t.dbg ; RUN: FileCheck --input-file=%t.dbg --check-prefix=MACHINELICM-DBG %s ; Check that MachineLICM hoists the CheriBoundedStackPseudoImm (MIPS) / IncOffset+SetBoundsImm (RISCV) instructions ; MACHINELICM-DBG-LABEL: ******** Pre-regalloc Machine LICM: hoist_alloca_uncond @@ -52,7 +52,7 @@ ; MACHINELICM-DBG: Hoisting [[BOUNDS:%[0-9]+]]:gpcr = CSetBoundsImm [[INC]]:gpcr, 88 ; MACHINELICM-DBG-NEXT: from %bb.3 to %bb.0 -; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+cap-mode,+f,+d -O1 -o - < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+xcheripurecap,+f,+d -O1 -o - < %s | FileCheck %s define void @hoist_alloca_uncond(i32 signext %cond) local_unnamed_addr addrspace(200) nounwind { ; CHECK-LABEL: hoist_alloca_uncond: diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/intrinsics-purecap-only.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/intrinsics-purecap-only.ll index cd1d6130a5727..34e69b3cbf827 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/intrinsics-purecap-only.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/intrinsics-purecap-only.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --scrub-attributes --version 2 ; DO NOT EDIT -- This file was generated from test/CodeGen/CHERI-Generic/Inputs/intrinsics-purecap-only.ll -; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+cap-mode,+f,+d < %s -o - | FileCheck %s --check-prefix=PURECAP +; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+xcheripurecap,+f,+d < %s -o - | FileCheck %s --check-prefix=PURECAP ; RUN: not --crash llc -mtriple=riscv64 --relocation-model=pic -target-abi lp64d -mattr=+xcheri,+f,+d < %s -o - 2>&1 | FileCheck %s --check-prefix HYBRID-ERROR ; This test checks target-independent CHERI intrinsics that are only available for purecap code diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/intrinsics.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/intrinsics.ll index 5c8971671ea33..2f382347f19e4 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/intrinsics.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/intrinsics.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 ; DO NOT EDIT -- This file was generated from test/CodeGen/CHERI-Generic/Inputs/intrinsics.ll -; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+cap-mode,+f,+d %s -o - < %s | FileCheck %s --check-prefix=PURECAP +; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+xcheripurecap,+f,+d %s -o - < %s | FileCheck %s --check-prefix=PURECAP ; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi lp64d -mattr=+xcheri,+f,+d -o - < %s | FileCheck %s --check-prefix=HYBRID ; Check that the target-independent CHERI intrinsics are support for all architectures ; The grouping/ordering in this test is based on the RISC-V instruction listing diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/landingpad-non-preemptible.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/landingpad-non-preemptible.ll index 5956633f139b6..f1682f80b13ed 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/landingpad-non-preemptible.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/landingpad-non-preemptible.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 ; DO NOT EDIT -- This file was generated from test/CodeGen/CHERI-Generic/Inputs/landingpad-non-preemptible.ll -; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+cap-mode,+f,+d --relocation-model=pic < %s -o - | FileCheck %s -; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+cap-mode,+f,+d --relocation-model=pic < %s -o - -filetype=obj | llvm-readobj --relocs --symbols - | FileCheck %s --check-prefix=RELOCS +; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+xcheripurecap,+f,+d --relocation-model=pic < %s -o - | FileCheck %s +; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+xcheripurecap,+f,+d --relocation-model=pic < %s -o - -filetype=obj | llvm-readobj --relocs --symbols - | FileCheck %s --check-prefix=RELOCS ; Capabilities for exception landing pads were using preemptible relocations such as ; .chericap foo + .Ltmp - .Lfunc_begin instead of using a local alias. ; https://github.com/CTSRD-CHERI/llvm-project/issues/512 diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/machinelicm-hoist-csetbounds.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/machinelicm-hoist-csetbounds.ll index f3150ff894b2f..1ae74f27507bc 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/machinelicm-hoist-csetbounds.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/machinelicm-hoist-csetbounds.ll @@ -6,8 +6,8 @@ ; Note: Opt correctly hoists the condition+csetbounds into a preheader, and LLC ; used to unconditionally hoist the csetbounds. -; RUN: opt -data-layout="e-m:e-pf200:128:128:128:64-p:64:64-i64:64-i128:128-n64-S128-A200-P200-G200" -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+cap-mode,+f,+d "-passes=default" -S < %s | FileCheck %s --check-prefix=HOIST-OPT -; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+cap-mode,+f,+d -O3 < %s | FileCheck %s +; RUN: opt -data-layout="e-m:e-pf200:128:128:128:64-p:64:64-i64:64-i128:128-n64-S128-A200-P200-G200" -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+xcheripurecap,+f,+d "-passes=default" -S < %s | FileCheck %s --check-prefix=HOIST-OPT +; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+xcheripurecap,+f,+d -O3 < %s | FileCheck %s ; Generated from the following C code (with subobject bounds): ; struct foo { diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/memcpy-from-constant.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/memcpy-from-constant.ll index aa9e71c43562e..90e9c6fbed407 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/memcpy-from-constant.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/memcpy-from-constant.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --scrub-attributes --version 2 ; DO NOT EDIT -- This file was generated from test/CodeGen/CHERI-Generic/Inputs/memcpy-from-constant.ll ;; Copying from a zero constant can be converted to a memset (even with the tag preservation flags) -; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+cap-mode,+f,+d < %s -o - | FileCheck %s +; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+xcheripurecap,+f,+d < %s -o - | FileCheck %s @a = internal addrspace(200) constant ptr addrspace(200) null @b = internal addrspace(200) constant ptr addrspace(200) null diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/memcpy-no-preserve-tags-attr.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/memcpy-no-preserve-tags-attr.ll index 65b68c6e373fc..da9a55bc16e91 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/memcpy-no-preserve-tags-attr.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/memcpy-no-preserve-tags-attr.ll @@ -2,7 +2,7 @@ ; DO NOT EDIT -- This file was generated from test/CodeGen/CHERI-Generic/Inputs/memcpy-no-preserve-tags-attr.ll ; Check that the no_preserve_tags annotation on memcpy/memmove intrinsics allows ; use to inline struct copies >= capability size. -; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+cap-mode,+f,+d -o - < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+xcheripurecap,+f,+d -o - < %s | FileCheck %s %struct.pair = type { i64, i64 } diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/memcpy-preserve-tags-assume-aligned.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/memcpy-preserve-tags-assume-aligned.ll index 609dc62ab701f..f819b65ccd24e 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/memcpy-preserve-tags-assume-aligned.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/memcpy-preserve-tags-assume-aligned.ll @@ -2,7 +2,7 @@ ; DO NOT EDIT -- This file was generated from test/CodeGen/CHERI-Generic/Inputs/memcpy-preserve-tags-assume-aligned.ll ; Check that __builtin_assume_aligned does the right thing and allows us to elide the memcpy ; call even with must_preserve_cheri_tags attribute (run instcombine to propagate assume information) -; RUN: opt -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+cap-mode,+f,+d -S -passes=instcombine < %s | llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+cap-mode,+f,+d -O2 -o - | FileCheck %s +; RUN: opt -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+xcheripurecap,+f,+d -S -passes=instcombine < %s | llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+xcheripurecap,+f,+d -O2 -o - | FileCheck %s target datalayout = "e-m:e-pf200:128:128:128:64-p:64:64-i64:64-i128:128-n64-S128-A200-P200-G200" declare void @llvm.memcpy.p200i8.p200i8.i64(i8 addrspace(200)* nocapture writeonly, i8 addrspace(200)* nocapture readonly, i64, i1) diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/memcpy-preserve-tags-size-not-multiple.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/memcpy-preserve-tags-size-not-multiple.ll index 701c2939998fd..95930fdd1cc83 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/memcpy-preserve-tags-size-not-multiple.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/memcpy-preserve-tags-size-not-multiple.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --scrub-attributes --version 2 ; DO NOT EDIT -- This file was generated from test/CodeGen/CHERI-Generic/Inputs/memcpy-preserve-tags-size-not-multiple.ll -; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+cap-mode,+f,+d -o - -O0 -verify-machineinstrs %s | FileCheck %s -check-prefixes CHECK +; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+xcheripurecap,+f,+d -o - -O0 -verify-machineinstrs %s | FileCheck %s -check-prefixes CHECK ; Check that we can inline memmove/memcpy despite having the must_preserve_cheri_tags property and the size not ; being a multiple of CAP_SIZE. Since the pointers are aligned we can start with capability copies and use ; word/byte copies for the trailing bytes. diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/memcpy-zeroinit.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/memcpy-zeroinit.ll index 2b95ba6e61dfd..a185a54ee8395 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/memcpy-zeroinit.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/memcpy-zeroinit.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --scrub-attributes --version 2 ; DO NOT EDIT -- This file was generated from test/CodeGen/CHERI-Generic/Inputs/memcpy-zeroinit.ll -; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+cap-mode,+f,+d < %s -o - | FileCheck %s +; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+xcheripurecap,+f,+d < %s -o - | FileCheck %s ; Check that the copy from the zeroinitializer global is turned into a series of zero stores ; or memset() as long as the memcpy is not volatile: diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/optsize-preserve-tags-memcpy-crash.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/optsize-preserve-tags-memcpy-crash.ll index 6afd328503839..3ea4240c0c702 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/optsize-preserve-tags-memcpy-crash.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/optsize-preserve-tags-memcpy-crash.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --scrub-attributes --version 2 ; DO NOT EDIT -- This file was generated from test/CodeGen/CHERI-Generic/Inputs/optsize-preserve-tags-memcpy-crash.ll -; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+cap-mode,+f,+d < %s -o - | FileCheck %s +; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+xcheripurecap,+f,+d < %s -o - | FileCheck %s ; The following code copying 31 bytes (with capability alignment) using the ; must_preserve_tags attribute used to trigger a "(Align < CapSize)" assertion ; inside diagnoseInefficientCheriMemOp() when compiling with -Oz. diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/ptrtoint.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/ptrtoint.ll index 26bf336a28814..1ea9ef794b5a8 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/ptrtoint.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/ptrtoint.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --scrub-attributes --version 2 ; DO NOT EDIT -- This file was generated from test/CodeGen/CHERI-Generic/Inputs/ptrtoint.ll ;; Check that we can correctly generate code for ptrtoint and perform simple folds -; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+cap-mode,+f,+d < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+xcheripurecap,+f,+d < %s | FileCheck %s ; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi lp64d -mattr=+xcheri,+f,+d < %s | FileCheck %s --check-prefix=HYBRID define internal i64 @ptrtoint(i8 addrspace(200)* %cap) addrspace(200) nounwind { diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/purecap-jumptable.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/purecap-jumptable.ll index 4879b190e8eb8..5c0c427a89f36 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/purecap-jumptable.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/purecap-jumptable.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 ; DO NOT EDIT -- This file was generated from test/CodeGen/CHERI-Generic/Inputs/purecap-jumptable.ll -; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+cap-mode,+f,+d < %s -o - | FileCheck %s -; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+cap-mode,+f,+d -relocation-model=static < %s -o - | FileCheck %s +; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+xcheripurecap,+f,+d < %s -o - | FileCheck %s +; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+xcheripurecap,+f,+d -relocation-model=static < %s -o - | FileCheck %s ; Check that we can generate jump tables for switch statements. ; TODO: this is currently not implemented for CHERI-RISC-V diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/setoffset-multiple-uses.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/setoffset-multiple-uses.ll index 45c37889cab36..16675f6374e8a 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/setoffset-multiple-uses.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/setoffset-multiple-uses.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --scrub-attributes --version 2 ; DO NOT EDIT -- This file was generated from test/CodeGen/CHERI-Generic/Inputs/setoffset-multiple-uses.ll ; RUN: opt -S -passes=instcombine -o - %s | FileCheck %s -; RUN: opt -S -passes=instcombine -o - %s | llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+cap-mode,+f,+d -O1 - -o - | %cheri_FileCheck %s --check-prefix ASM +; RUN: opt -S -passes=instcombine -o - %s | llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+xcheripurecap,+f,+d -O1 - -o - | %cheri_FileCheck %s --check-prefix ASM target datalayout = "e-m:e-pf200:128:128:128:64-p:64:64-i64:64-i128:128-n64-S128-A200-P200-G200" ; Reduced test case for a crash in the new optimization to fold multiple setoffset calls (orignally found when compiling libunwind) diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/stack-bounds-dynamic-alloca.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/stack-bounds-dynamic-alloca.ll index 7a905d6de0379..4f21e35062506 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/stack-bounds-dynamic-alloca.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/stack-bounds-dynamic-alloca.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --scrub-attributes --version 2 ; DO NOT EDIT -- This file was generated from test/CodeGen/CHERI-Generic/Inputs/stack-bounds-dynamic-alloca.ll -; RUN: opt -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+cap-mode,+f,+d -passes=cheri-bound-allocas -o - -S %s | FileCheck %s -; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+cap-mode,+f,+d -O0 %s -o - | FileCheck %s -check-prefix ASM -; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+cap-mode,+f,+d -O2 %s -o - | FileCheck %s -check-prefix ASM-OPT +; RUN: opt -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+xcheripurecap,+f,+d -passes=cheri-bound-allocas -o - -S %s | FileCheck %s +; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+xcheripurecap,+f,+d -O0 %s -o - | FileCheck %s -check-prefix ASM +; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+xcheripurecap,+f,+d -O2 %s -o - | FileCheck %s -check-prefix ASM-OPT ; reduced C test case: ; __builtin_va_list a; diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/stack-bounds-opaque-spill-too-early.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/stack-bounds-opaque-spill-too-early.ll index 43618c83eb198..af21f1ec50052 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/stack-bounds-opaque-spill-too-early.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/stack-bounds-opaque-spill-too-early.ll @@ -4,9 +4,9 @@ ;; miscompilations in the stack bounding pass (the unbounded value was used instead of ;; the bounded one due to the removal of the bitcast instructions). ; REQUIRES: asserts -; RUN: opt -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+cap-mode,+f,+d -passes=cheri-bound-allocas -o - -S %s -debug-only=cheri-bound-allocas 2>%t.dbg| FileCheck %s +; RUN: opt -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+xcheripurecap,+f,+d -passes=cheri-bound-allocas -o - -S %s -debug-only=cheri-bound-allocas 2>%t.dbg| FileCheck %s ; RUN: FileCheck %s -input-file=%t.dbg -check-prefix DBG -; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+cap-mode,+f,+d %s -o - | FileCheck %s -check-prefix ASM +; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+xcheripurecap,+f,+d %s -o - | FileCheck %s -check-prefix ASM target datalayout = "e-m:e-pf200:128:128:128:64-p:64:64-i64:64-i128:128-n64-S128-A200-P200-G200" ; DBG-LABEL: Checking function lazy_bind_args diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/stack-bounds-pass-phi.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/stack-bounds-pass-phi.ll index b9901e1714dec..8216ebb59e8f5 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/stack-bounds-pass-phi.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/stack-bounds-pass-phi.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --scrub-attributes --version 2 ; DO NOT EDIT -- This file was generated from test/CodeGen/CHERI-Generic/Inputs/stack-bounds-pass-phi.ll ; REQUIRES: asserts -; RUN: opt -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+cap-mode,+f,+d -passes=cheri-bound-allocas %s -o - -S -cheri-stack-bounds=if-needed \ +; RUN: opt -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+xcheripurecap,+f,+d -passes=cheri-bound-allocas %s -o - -S -cheri-stack-bounds=if-needed \ ; RUN: -cheri-stack-bounds-single-intrinsic-threshold=10 -debug-only=cheri-bound-allocas 2>%t.dbg | FileCheck %s -; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+cap-mode,+f,+d -cheri-stack-bounds=if-needed -O2 -cheri-stack-bounds-single-intrinsic-threshold=10 < %s | %cheri_FileCheck %s -check-prefix ASM +; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+xcheripurecap,+f,+d -cheri-stack-bounds=if-needed -O2 -cheri-stack-bounds-single-intrinsic-threshold=10 < %s | %cheri_FileCheck %s -check-prefix ASM ; RUN: FileCheck %s -check-prefix DBG -input-file=%t.dbg target datalayout = "e-m:e-pf200:128:128:128:64-p:64:64-i64:64-i128:128-n64-S128-A200-P200-G200" diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/stack-spill-unnecessary.c.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/stack-spill-unnecessary.c.ll index 8676442a2e806..a5adb5172577b 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/stack-spill-unnecessary.c.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/stack-spill-unnecessary.c.ll @@ -5,9 +5,9 @@ ; Previously we were moving the allocation of the register that is only used later to the beginning of ; the function and saving+restoring it instead of materializing it just before -; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+cap-mode,+f,+d -O2 --cheri-stack-bounds-single-intrinsic-threshold=0 < %s | %cheri_FileCheck %s --check-prefixes=CHECK +; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+xcheripurecap,+f,+d -O2 --cheri-stack-bounds-single-intrinsic-threshold=0 < %s | %cheri_FileCheck %s --check-prefixes=CHECK ; Always use a single intrinsic for the calls (should result in same codegen) -; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+cap-mode,+f,+d -O2 --cheri-stack-bounds-single-intrinsic-threshold=0 < %s | %cheri_FileCheck %s --check-prefixes=CHECK +; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+xcheripurecap,+f,+d -O2 --cheri-stack-bounds-single-intrinsic-threshold=0 < %s | %cheri_FileCheck %s --check-prefixes=CHECK ; RUN: sed 's/addrspace(200)/addrspace(0)/g' %s | llc -mtriple=riscv64 --relocation-model=pic -target-abi lp64d -mattr=+xcheri,+f,+d | FileCheck --check-prefix HYBRID %s diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/stackframe-intrinsics.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/stackframe-intrinsics.ll index 8a58ed16379c3..a8340e3b13f1d 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/stackframe-intrinsics.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/stackframe-intrinsics.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --scrub-attributes --version 2 ; DO NOT EDIT -- This file was generated from test/CodeGen/CHERI-Generic/Inputs/stackframe-intrinsics.ll -; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+cap-mode,+f,+d %s -o - < %s | FileCheck %s --check-prefix=PURECAP +; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+xcheripurecap,+f,+d %s -o - < %s | FileCheck %s --check-prefix=PURECAP ; RUN: sed 's/addrspace(200)/addrspace(0)/g' %s | llc -mtriple=riscv64 --relocation-model=pic -target-abi lp64d -mattr=+xcheri,+f,+d | FileCheck %s --check-prefix HYBRID ; Check that we can lower llvm.frameaddress/llvm.returnaddress diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/strcpy-to-memcpy-no-tags.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/strcpy-to-memcpy-no-tags.ll index cabca11ccde31..b1799b55e698c 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/strcpy-to-memcpy-no-tags.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/strcpy-to-memcpy-no-tags.ll @@ -6,7 +6,7 @@ ; Note: unlike other tests we do want to test attributes in this one. ; CHERI-GENERIC-UTC: opt --function-signature ; RUN: opt < %s -passes=instcombine -S | FileCheck %s --check-prefix=CHECK-IR -; RUN: opt < %s -passes=instcombine -S | llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+cap-mode,+f,+d - -o - | FileCheck %s --check-prefix=CHECK-ASM +; RUN: opt < %s -passes=instcombine -S | llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+xcheripurecap,+f,+d - -o - | FileCheck %s --check-prefix=CHECK-ASM target datalayout = "e-m:e-pf200:128:128:128:64-p:64:64-i64:64-i128:128-n64-S128-A200-P200-G200" @str = private unnamed_addr addrspace(200) constant [17 x i8] c"exactly 16 chars\00", align 8 diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/subobject-bounds-redundant-setbounds.c.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/subobject-bounds-redundant-setbounds.c.ll index b853c3b7aa7ba..e8cb55092650f 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/subobject-bounds-redundant-setbounds.c.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/subobject-bounds-redundant-setbounds.c.ll @@ -2,9 +2,9 @@ ; DO NOT EDIT -- This file was generated from test/CodeGen/CHERI-Generic/Inputs/subobject-bounds-redundant-setbounds.c.ll ; REQUIRES: asserts ; RUN: rm -f %t.dbg-opt %t.dbg-llc -; RUN: opt -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+cap-mode,+f,+d -passes=cheri-bound-allocas -debug-only=cheri-bound-allocas -S -o - %s 2>%t.dbg-opt | FileCheck %s +; RUN: opt -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+xcheripurecap,+f,+d -passes=cheri-bound-allocas -debug-only=cheri-bound-allocas -S -o - %s 2>%t.dbg-opt | FileCheck %s ; RUN: FileCheck %s -input-file=%t.dbg-opt -check-prefix DBG -; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+cap-mode,+f,+d -debug-only=cheri-bound-allocas -o - %s 2>%t.dbg-llc | FileCheck %s -check-prefix ASM +; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+xcheripurecap,+f,+d -debug-only=cheri-bound-allocas -o - %s 2>%t.dbg-llc | FileCheck %s -check-prefix ASM ; RUN: FileCheck %s -input-file=%t.dbg-llc -check-prefix DBG target datalayout = "e-m:e-pf200:128:128:128:64-p:64:64-i64:64-i128:128-n64-S128-A200-P200-G200" diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/trunc-load.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/trunc-load.ll index 4548456cf5166..1e8cd650ed7e3 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/trunc-load.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/trunc-load.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --scrub-attributes --version 2 ; DO NOT EDIT -- This file was generated from test/CodeGen/CHERI-Generic/Inputs/trunc-load.ll -; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+cap-mode,+f,+d %s -o - < %s | FileCheck %s --check-prefix=PURECAP +; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+xcheripurecap,+f,+d %s -o - < %s | FileCheck %s --check-prefix=PURECAP ; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi lp64d -mattr=+xcheri,+f,+d -o - < %s | FileCheck %s --check-prefix=HYBRID define zeroext i16 @trunc_load_zext(i32 addrspace(200)* %p) { diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/unaligned-loads-stores-purecap.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/unaligned-loads-stores-purecap.ll index a1379eddabfed..be1f0a74fdb4b 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/unaligned-loads-stores-purecap.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/unaligned-loads-stores-purecap.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --scrub-attributes --version 2 ; DO NOT EDIT -- This file was generated from test/CodeGen/CHERI-Generic/Inputs/unaligned-loads-stores-purecap.ll -; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+cap-mode,+f,+d %s -o - | FileCheck %s +; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+xcheripurecap,+f,+d %s -o - | FileCheck %s @a1 = addrspace(200) global i64 0, align 1 @a2 = addrspace(200) global i64 0, align 2 diff --git a/llvm/test/CodeGen/CHERI-Generic/regenerate-all.py b/llvm/test/CodeGen/CHERI-Generic/regenerate-all.py index 7c7c738ca16f4..644de2c78a65d 100755 --- a/llvm/test/CodeGen/CHERI-Generic/regenerate-all.py +++ b/llvm/test/CodeGen/CHERI-Generic/regenerate-all.py @@ -48,16 +48,16 @@ def __init__(self, architecture: str, *, cap_range, cap_width, common_args=["-mtriple=riscv32", "--relocation-model=pic"], hybrid_sf_args=["-target-abi", "ilp32", "-mattr=+xcheri,-f"], hybrid_hf_args=["-target-abi", "ilp32f", "-mattr=+xcheri,+f"], - purecap_sf_args=["-target-abi", "il32pc64", "-mattr=+xcheri,+cap-mode,-f"], - purecap_hf_args=["-target-abi", "il32pc64f", "-mattr=+xcheri,+cap-mode,+f"], + purecap_sf_args=["-target-abi", "il32pc64", "-mattr=+xcheri,+xcheripurecap,-f"], + purecap_hf_args=["-target-abi", "il32pc64f", "-mattr=+xcheri,+xcheripurecap,+f"], datalayout=b"e-m:e-pf200:64:64:64:32-p:32:32-i64:64-n32-S128") RISCV64Config = ArchSpecificValues( "RISCV64", base_architecture="RISCV", cap_range=64, cap_width=128, common_args=["-mtriple=riscv64", "--relocation-model=pic"], hybrid_sf_args=["-target-abi", "lp64", "-mattr=+xcheri,-f,-d"], hybrid_hf_args=["-target-abi", "lp64d", "-mattr=+xcheri,+f,+d"], - purecap_sf_args=["-target-abi", "l64pc128", "-mattr=+xcheri,+cap-mode,-f,-d"], - purecap_hf_args=["-target-abi", "l64pc128d", "-mattr=+xcheri,+cap-mode,+f,+d"], + purecap_sf_args=["-target-abi", "l64pc128", "-mattr=+xcheri,+xcheripurecap,-f,-d"], + purecap_hf_args=["-target-abi", "l64pc128d", "-mattr=+xcheri,+xcheripurecap,+f,+d"], datalayout=b"e-m:e-pf200:128:128:128:64-p:64:64-i64:64-i128:128-n64-S128") ALL_ARCHITECTURES = [MIPSConfig, RISCV32Config, RISCV64Config] diff --git a/llvm/test/CodeGen/RISCV/cheri/cheri-local-libcall.ll b/llvm/test/CodeGen/RISCV/cheri/cheri-local-libcall.ll index 1840e1bb9ae5e..b36272d3ef421 100644 --- a/llvm/test/CodeGen/RISCV/cheri/cheri-local-libcall.ll +++ b/llvm/test/CodeGen/RISCV/cheri/cheri-local-libcall.ll @@ -1,4 +1,4 @@ -; RUN: llc --filetype=asm --mcpu=cheriot --mtriple=riscv32-unknown-unknown -target-abi cheriot -mattr=+xcheri,+cap-mode < %s | FileCheck %s +; RUN: llc --filetype=asm --mcpu=cheriot --mtriple=riscv32-unknown-unknown -target-abi cheriot -mattr=+xcheri,+xcheripurecap < %s | FileCheck %s target datalayout = "e-m:e-pf200:64:64:64:32-p:32:32-i64:64-n32-S128-A200-P200-G200" target triple = "riscv32cheriot-unknown-cheriotrtos" @@ -15,8 +15,8 @@ entry: ret void } -attributes #0 = { minsize mustprogress nofree norecurse nosync nounwind optsize willreturn memory(none) "cheri-compartment"="hello" "interrupt-state"="disabled" "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cheriot" "target-features"="+32bit,+c,+cap-mode,+e,+m,+relax,+xcheri,-a,-d,-experimental-smaia,-experimental-ssaia,-experimental-zacas,-experimental-zfa,-experimental-zfbfmin,-experimental-zicond,-experimental-zihintntl,-experimental-ztso,-experimental-zvbb,-experimental-zvbc,-experimental-zvfbfmin,-experimental-zvfbfwma,-experimental-zvkg,-experimental-zvkn,-experimental-zvknc,-experimental-zvkned,-experimental-zvkng,-experimental-zvknha,-experimental-zvknhb,-experimental-zvks,-experimental-zvksc,-experimental-zvksed,-experimental-zvksg,-experimental-zvksh,-experimental-zvkt,-f,-h,-save-restore,-svinval,-svnapot,-svpbmt,-v,-xcvbitmanip,-xcvmac,-xsfcie,-xsfvcp,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zicbom,-zicbop,-zicboz,-zicntr,-zicsr,-zifencei,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } -attributes #1 = { minsize mustprogress nofree norecurse nosync nounwind optsize willreturn memory(write, argmem: none, inaccessiblemem: none) "cheri-compartment"="hello" "interrupt-state"="enabled" "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cheriot" "target-features"="+32bit,+c,+cap-mode,+e,+m,+relax,+xcheri,-a,-d,-experimental-smaia,-experimental-ssaia,-experimental-zacas,-experimental-zfa,-experimental-zfbfmin,-experimental-zicond,-experimental-zihintntl,-experimental-ztso,-experimental-zvbb,-experimental-zvbc,-experimental-zvfbfmin,-experimental-zvfbfwma,-experimental-zvkg,-experimental-zvkn,-experimental-zvknc,-experimental-zvkned,-experimental-zvkng,-experimental-zvknha,-experimental-zvknhb,-experimental-zvks,-experimental-zvksc,-experimental-zvksed,-experimental-zvksg,-experimental-zvksh,-experimental-zvkt,-f,-h,-save-restore,-svinval,-svnapot,-svpbmt,-v,-xcvbitmanip,-xcvmac,-xsfcie,-xsfvcp,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zicbom,-zicbop,-zicboz,-zicntr,-zicsr,-zifencei,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } +attributes #0 = { minsize mustprogress nofree norecurse nosync nounwind optsize willreturn memory(none) "cheri-compartment"="hello" "interrupt-state"="disabled" "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cheriot" "target-features"="+32bit,+c,+xcheripurecap,+e,+m,+relax,+xcheri,-a,-d,-experimental-smaia,-experimental-ssaia,-experimental-zacas,-experimental-zfa,-experimental-zfbfmin,-experimental-zicond,-experimental-zihintntl,-experimental-ztso,-experimental-zvbb,-experimental-zvbc,-experimental-zvfbfmin,-experimental-zvfbfwma,-experimental-zvkg,-experimental-zvkn,-experimental-zvknc,-experimental-zvkned,-experimental-zvkng,-experimental-zvknha,-experimental-zvknhb,-experimental-zvks,-experimental-zvksc,-experimental-zvksed,-experimental-zvksg,-experimental-zvksh,-experimental-zvkt,-f,-h,-save-restore,-svinval,-svnapot,-svpbmt,-v,-xcvbitmanip,-xcvmac,-xsfcie,-xsfvcp,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zicbom,-zicbop,-zicboz,-zicntr,-zicsr,-zifencei,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } +attributes #1 = { minsize mustprogress nofree norecurse nosync nounwind optsize willreturn memory(write, argmem: none, inaccessiblemem: none) "cheri-compartment"="hello" "interrupt-state"="enabled" "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cheriot" "target-features"="+32bit,+c,+xcheripurecap,+e,+m,+relax,+xcheri,-a,-d,-experimental-smaia,-experimental-ssaia,-experimental-zacas,-experimental-zfa,-experimental-zfbfmin,-experimental-zicond,-experimental-zihintntl,-experimental-ztso,-experimental-zvbb,-experimental-zvbc,-experimental-zvfbfmin,-experimental-zvfbfwma,-experimental-zvkg,-experimental-zvkn,-experimental-zvknc,-experimental-zvkned,-experimental-zvkng,-experimental-zvknha,-experimental-zvknhb,-experimental-zvks,-experimental-zvksc,-experimental-zvksed,-experimental-zvksg,-experimental-zvksh,-experimental-zvkt,-f,-h,-save-restore,-svinval,-svnapot,-svpbmt,-v,-xcvbitmanip,-xcvmac,-xsfcie,-xsfvcp,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zicbom,-zicbop,-zicboz,-zicntr,-zicsr,-zifencei,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } ; CHECK: .section .compartment_exports,"aR",@progbits ; CHECK-NEXT: .type __library_export_hello__Z11id_functionv,@object diff --git a/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-call-ccallee.ll b/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-call-ccallee.ll index f5f827aa5b102..46d2e95956dd7 100644 --- a/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-call-ccallee.ll +++ b/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-call-ccallee.ll @@ -1,4 +1,4 @@ -; RUN: llc --filetype=asm --mcpu=cheriot --mtriple=riscv32-unknown-unknown -target-abi cheriot %s -mattr=+xcheri,+cap-mode -o - | FileCheck %s +; RUN: llc --filetype=asm --mcpu=cheriot --mtriple=riscv32-unknown-unknown -target-abi cheriot %s -mattr=+xcheri,+xcheripurecap -o - | FileCheck %s ; ModuleID = '/tmp/ccall-size.c' source_filename = "/tmp/ccall-size.c" target datalayout = "e-m:e-pf200:64:64:64:32-p:32:32-i64:64-n32-S128-A200-P200-G200" diff --git a/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-call-libcall.ll b/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-call-libcall.ll index b44449daa3b6d..d8be431e09f2b 100644 --- a/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-call-libcall.ll +++ b/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-call-libcall.ll @@ -1,4 +1,4 @@ -; RUN: llc --filetype=asm --mcpu=cheriot --mtriple=riscv32-unknown-unknown -target-abi cheriot %s -mattr=+xcheri,+cap-mode -o - | FileCheck %s +; RUN: llc --filetype=asm --mcpu=cheriot --mtriple=riscv32-unknown-unknown -target-abi cheriot %s -mattr=+xcheri,+xcheripurecap -o - | FileCheck %s source_filename = "/usr/home/theraven/llvm-project/clang/test/CodeGen/cheri/cheri-mcu-call-libcall.c" target datalayout = "e-m:e-pf200:64:64:64:32-p:32:32-i64:64-n32-S128-A200-P200-G200" target triple = "riscv32-unknown-unknown" diff --git a/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-ccall.ll b/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-ccall.ll index 65b8bc634fe88..6b71d1d4382a5 100644 --- a/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-ccall.ll +++ b/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-ccall.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 -; RUN: llc --filetype=asm --code-model=small --mcpu=cheriot --mtriple=riscv32-unknown-unknown -target-abi cheriot %s -mattr=+xcheri,+cap-mode -o - | FileCheck %s +; RUN: llc --filetype=asm --code-model=small --mcpu=cheriot --mtriple=riscv32-unknown-unknown -target-abi cheriot %s -mattr=+xcheri,+xcheripurecap -o - | FileCheck %s ; ModuleID = 'ccall.c' source_filename = "ccall.c" target datalayout = "e-m:e-pf200:64:64:64:32-p:32:32-i64:64-n32-S128-A200-P200-G200" diff --git a/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-ccallback.ll b/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-ccallback.ll index 8d2215d6328d7..7d4c279759097 100644 --- a/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-ccallback.ll +++ b/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-ccallback.ll @@ -1,4 +1,4 @@ -; RUN: llc --filetype=asm --mcpu=cheriot --mtriple=riscv32-unknown-unknown -target-abi cheriot %s -mattr=+xcheri,+cap-mode -o - | FileCheck %s +; RUN: llc --filetype=asm --mcpu=cheriot --mtriple=riscv32-unknown-unknown -target-abi cheriot %s -mattr=+xcheri,+xcheripurecap -o - | FileCheck %s ; ModuleID = 'ccallback.c' source_filename = "ccallback.c" target datalayout = "e-m:e-pf200:64:64:64:32-p:32:32-i64:64-n32-S128-A200-P200-G200" diff --git a/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-define-libcall.ll b/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-define-libcall.ll index ddf620e0aaefe..7a9147e0911ec 100644 --- a/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-define-libcall.ll +++ b/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-define-libcall.ll @@ -1,4 +1,4 @@ -; RUN: llc --filetype=asm --mcpu=cheriot --mtriple=riscv32-unknown-unknown -target-abi cheriot %s -mattr=+xcheri,+cap-mode -o - | FileCheck %s +; RUN: llc --filetype=asm --mcpu=cheriot --mtriple=riscv32-unknown-unknown -target-abi cheriot %s -mattr=+xcheri,+xcheripurecap -o - | FileCheck %s ; ModuleID = '/usr/home/theraven/llvm-project/clang/test/CodeGen/cheri/cheri-mcu-define-libcall.c' source_filename = "/usr/home/theraven/llvm-project/clang/test/CodeGen/cheri/cheri-mcu-define-libcall.c" target datalayout = "e-m:e-pf200:64:64:64:32-p:32:32-i64:64-n32-S128-A200-P200-G200" diff --git a/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-exported-interrupts.ll b/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-exported-interrupts.ll index 88a97723f6838..7967b32c88811 100644 --- a/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-exported-interrupts.ll +++ b/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-exported-interrupts.ll @@ -1,4 +1,4 @@ -; RUN: llc --filetype=asm --mcpu=cheriot --mtriple=riscv32-unknown-unknown -target-abi cheriot %s -mattr=+xcheri,+cap-mode -o - | FileCheck %s +; RUN: llc --filetype=asm --mcpu=cheriot --mtriple=riscv32-unknown-unknown -target-abi cheriot %s -mattr=+xcheri,+xcheripurecap -o - | FileCheck %s ; ModuleID = 'test.cc' source_filename = "test.cc" target datalayout = "e-m:e-pf200:64:64:64:32-p:32:32-i64:64-n32-S128-A200-P200-G200" diff --git a/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-exported-unused-args.ll b/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-exported-unused-args.ll index 8928e10bf08e7..2796c6daf2233 100644 --- a/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-exported-unused-args.ll +++ b/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-exported-unused-args.ll @@ -1,4 +1,4 @@ -; RUN: llc --filetype=asm --mcpu=cheriot --mtriple=riscv32-unknown-unknown -target-abi cheriot %s -mattr=+xcheri,+cap-mode -o - | FileCheck %s +; RUN: llc --filetype=asm --mcpu=cheriot --mtriple=riscv32-unknown-unknown -target-abi cheriot %s -mattr=+xcheri,+xcheripurecap -o - | FileCheck %s ; ModuleID = 'cheri-export.c' source_filename = "cheri-export.c" target datalayout = "e-m:e-pf200:64:64:64:32-p:32:32-i64:64-n32-S128-A200-P200-G200" diff --git a/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-fastcc.ll b/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-fastcc.ll index 5750a04a8ebf3..b64c27f8b4098 100644 --- a/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-fastcc.ll +++ b/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-fastcc.ll @@ -1,4 +1,4 @@ -; RUN: llc --filetype=asm --mcpu=cheriot --mtriple=riscv32-unknown-unknown -target-abi cheriot %s -mattr=+xcheri,+cap-mode -o - | FileCheck %s +; RUN: llc --filetype=asm --mcpu=cheriot --mtriple=riscv32-unknown-unknown -target-abi cheriot %s -mattr=+xcheri,+xcheripurecap -o - | FileCheck %s ; ModuleID = 'ccall.c' source_filename = "ccall.c" target datalayout = "e-m:e-pf200:64:64:64:32-p:32:32-i64:64-n32-S128-A200-P200-G200" diff --git a/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-fnptr.ll b/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-fnptr.ll index b589e10570cdb..c0697142c4992 100644 --- a/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-fnptr.ll +++ b/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-fnptr.ll @@ -1,4 +1,4 @@ -; RUN: llc --filetype=asm --mcpu=cheriot --mtriple=riscv32-unknown-unknown -target-abi cheriot %s -mattr=+xcheri,+cap-mode -o - | FileCheck %s +; RUN: llc --filetype=asm --mcpu=cheriot --mtriple=riscv32-unknown-unknown -target-abi cheriot %s -mattr=+xcheri,+xcheripurecap -o - | FileCheck %s ; ModuleID = '/tmp/fnptr.c' source_filename = "/tmp/fnptr.c" target datalayout = "e-m:e-pf200:64:64:64:32-p:32:32-i64:64-n32-S128-A200-P200-G200" diff --git a/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-interrupt-attributes.ll b/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-interrupt-attributes.ll index bdd0c5f736d66..7a6a2a67ea7b2 100644 --- a/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-interrupt-attributes.ll +++ b/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-interrupt-attributes.ll @@ -1,4 +1,4 @@ -; RUN: llc --filetype=asm --mcpu=cheriot --mtriple=riscv32-unknown-unknown -target-abi cheriot %s -mattr=+xcheri,+cap-mode -o - | FileCheck %s +; RUN: llc --filetype=asm --mcpu=cheriot --mtriple=riscv32-unknown-unknown -target-abi cheriot %s -mattr=+xcheri,+xcheripurecap -o - | FileCheck %s ; ModuleID = '../llvm-trunk-release/inline.c' source_filename = "../llvm-trunk-release/inline.c" target datalayout = "e-m:e-pf200:64:64:64:32-p:32:32-i64:64-n32-S128-A200-P200-G200" diff --git a/llvm/test/CodeGen/RISCV/cheri/cheriot-arg-regs.ll b/llvm/test/CodeGen/RISCV/cheri/cheriot-arg-regs.ll index 8c6c81acfaa50..df27ca92c0cdc 100644 --- a/llvm/test/CodeGen/RISCV/cheri/cheriot-arg-regs.ll +++ b/llvm/test/CodeGen/RISCV/cheri/cheriot-arg-regs.ll @@ -1,4 +1,4 @@ -; RUN: llc --filetype=asm --mcpu=cheriot --mtriple=riscv32-unknown-unknown -target-abi cheriot %s -mattr=+xcheri,+cap-mode -o - | FileCheck %s +; RUN: llc --filetype=asm --mcpu=cheriot --mtriple=riscv32-unknown-unknown -target-abi cheriot %s -mattr=+xcheri,+xcheripurecap -o - | FileCheck %s ; ModuleID = 'big.c' ; Smoke test the calling convention. Isn't actually checking that things go in diff --git a/llvm/test/CodeGen/RISCV/cheri/cheriot-callback.ll b/llvm/test/CodeGen/RISCV/cheri/cheriot-callback.ll index 187f2d7681930..579f9ba4ed49f 100644 --- a/llvm/test/CodeGen/RISCV/cheri/cheriot-callback.ll +++ b/llvm/test/CodeGen/RISCV/cheri/cheriot-callback.ll @@ -1,4 +1,4 @@ -; RUN: llc --filetype=asm --mcpu=cheriot --mtriple=riscv32-unknown-unknown -target-abi cheriot %s -mattr=+xcheri,+cap-mode -o - | FileCheck %s +; RUN: llc --filetype=asm --mcpu=cheriot --mtriple=riscv32-unknown-unknown -target-abi cheriot %s -mattr=+xcheri,+xcheripurecap -o - | FileCheck %s ; ModuleID = 'test.cc' source_filename = "test.cc" target datalayout = "e-m:e-pf200:64:64:64:32-p:32:32-i64:64-n32-S128-A200-P200-G200" diff --git a/llvm/test/CodeGen/RISCV/cheri/cheriot-check-arg-permissions.ll b/llvm/test/CodeGen/RISCV/cheri/cheriot-check-arg-permissions.ll index be3952cbe9b68..5872ce6b56b7a 100644 --- a/llvm/test/CodeGen/RISCV/cheri/cheriot-check-arg-permissions.ll +++ b/llvm/test/CodeGen/RISCV/cheri/cheriot-check-arg-permissions.ll @@ -1,4 +1,4 @@ -; RUN: llc --filetype=asm --mcpu=cheriot --mtriple=riscv32-unknown-unknown -target-abi cheriot %s -mattr=+xcheri,+cap-mode -o - | FileCheck %s +; RUN: llc --filetype=asm --mcpu=cheriot --mtriple=riscv32-unknown-unknown -target-abi cheriot %s -mattr=+xcheri,+xcheripurecap -o - | FileCheck %s ; ModuleID = 'test.cc' source_filename = "test.cc" target datalayout = "e-m:e-pf200:64:64:64:32-p:32:32-i64:64-n32-S128-A200-P200-G200" diff --git a/llvm/test/CodeGen/RISCV/cheri/cheriot-clc64.ll b/llvm/test/CodeGen/RISCV/cheri/cheriot-clc64.ll index b472ad62bf5aa..02e76b818154c 100644 --- a/llvm/test/CodeGen/RISCV/cheri/cheriot-clc64.ll +++ b/llvm/test/CodeGen/RISCV/cheri/cheriot-clc64.ll @@ -1,4 +1,4 @@ -; RUN: llc --filetype=asm --mcpu=cheriot --mtriple=riscv32-unknown-unknown -target-abi cheriot %s -mattr=+xcheri,+cap-mode -o - | FileCheck %s +; RUN: llc --filetype=asm --mcpu=cheriot --mtriple=riscv32-unknown-unknown -target-abi cheriot %s -mattr=+xcheri,+xcheripurecap -o - | FileCheck %s ; ModuleID = '/tmp/timer.ll' source_filename = "/tmp/timer-8b64ae.cpp" target datalayout = "e-m:e-pf200:64:64:64:32-p:32:32-i64:64-n32-S128-A200-P200-G200" diff --git a/llvm/test/CodeGen/RISCV/cheri/cheriot-csetboundsexact.ll b/llvm/test/CodeGen/RISCV/cheri/cheriot-csetboundsexact.ll index 801e5818bea11..ada8cd923719d 100644 --- a/llvm/test/CodeGen/RISCV/cheri/cheriot-csetboundsexact.ll +++ b/llvm/test/CodeGen/RISCV/cheri/cheriot-csetboundsexact.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -mtriple=riscv32cheriot --mcpu=cheriot -target-abi=cheriot -mattr=+xcheri,+cap-mode,+xcheriot -o - %s | FileCheck %s +; RUN: llc -mtriple=riscv32cheriot --mcpu=cheriot -target-abi=cheriot -mattr=+xcheri,+xcheripurecap,+xcheriot -o - %s | FileCheck %s define i8 addrspace(200)* @test1(i8 addrspace(200)* %cap, i32 %bounds) nounwind { ; CHECK-LABEL: test1: diff --git a/llvm/test/CodeGen/RISCV/cheri/cheriot-csetboundsrounddown.ll b/llvm/test/CodeGen/RISCV/cheri/cheriot-csetboundsrounddown.ll index 95702fe9fba86..a050f35debedd 100644 --- a/llvm/test/CodeGen/RISCV/cheri/cheriot-csetboundsrounddown.ll +++ b/llvm/test/CodeGen/RISCV/cheri/cheriot-csetboundsrounddown.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 -; RUN: llc --filetype=asm --mcpu=cheriot --mtriple=riscv32cheriot-unknown-cheriotrtos -target-abi cheriot %s -mattr=+xcheri,+cap-mode -o - | FileCheck %s +; RUN: llc --filetype=asm --mcpu=cheriot --mtriple=riscv32cheriot-unknown-cheriotrtos -target-abi cheriot %s -mattr=+xcheri,+xcheripurecap -o - | FileCheck %s target datalayout = "e-m:e-pf200:64:64:64:32-p:32:32-i64:64-n32-S128-A200-P200-G200" target triple = "riscv32cheriot-unknown-cheriotrtos" diff --git a/llvm/test/CodeGen/RISCV/cheri/cheriot-elf-flags.ll b/llvm/test/CodeGen/RISCV/cheri/cheriot-elf-flags.ll index c0cc45836a063..ff19175df7478 100644 --- a/llvm/test/CodeGen/RISCV/cheri/cheriot-elf-flags.ll +++ b/llvm/test/CodeGen/RISCV/cheri/cheriot-elf-flags.ll @@ -1,4 +1,4 @@ -; RUN: llc --filetype=obj --mcpu=cheriot --mtriple=riscv32-unknown-unknown -target-abi cheriot %s -mattr=+xcheri,+cap-mode -o - | llvm-readelf -a - | FileCheck %s +; RUN: llc --filetype=obj --mcpu=cheriot --mtriple=riscv32-unknown-unknown -target-abi cheriot %s -mattr=+xcheri,+xcheripurecap -o - | llvm-readelf -a - | FileCheck %s ; CHECK-LABEL: ELF Header: ; CHECK: Flags: 0x70009, RVC, RVE, cheriabi, capability mode, cheriot diff --git a/llvm/test/CodeGen/RISCV/cheri/cheriot-frame-checks.ll b/llvm/test/CodeGen/RISCV/cheri/cheriot-frame-checks.ll index b700137322813..a151d8e5f2883 100644 --- a/llvm/test/CodeGen/RISCV/cheri/cheriot-frame-checks.ll +++ b/llvm/test/CodeGen/RISCV/cheri/cheriot-frame-checks.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 -; RUN: llc --filetype=asm --mcpu=cheriot --mtriple=riscv32-unknown-unknown -target-abi cheriot %s -mattr=+xcheri,+cap-mode -o - | FileCheck %s +; RUN: llc --filetype=asm --mcpu=cheriot --mtriple=riscv32-unknown-unknown -target-abi cheriot %s -mattr=+xcheri,+xcheripurecap -o - | FileCheck %s target datalayout = "e-m:e-pf200:64:64:64:32-p:32:32-i64:64-n32-S128-A200-P200-G200" target triple = "riscv32-unknown-unknown" diff --git a/llvm/test/CodeGen/RISCV/cheri/cheriot-global-weak.ll b/llvm/test/CodeGen/RISCV/cheri/cheriot-global-weak.ll index 949935691ae9e..24c4c76b02163 100644 --- a/llvm/test/CodeGen/RISCV/cheri/cheriot-global-weak.ll +++ b/llvm/test/CodeGen/RISCV/cheri/cheriot-global-weak.ll @@ -1,4 +1,4 @@ -; RUN: llc --filetype=asm --mcpu=cheriot --mtriple=riscv32cheriot-unknown-cheriotrtos -target-abi cheriot %s -mattr=+xcheri,+cap-mode,+xcheriot -o - | FileCheck %s +; RUN: llc --filetype=asm --mcpu=cheriot --mtriple=riscv32cheriot-unknown-cheriotrtos -target-abi cheriot %s -mattr=+xcheri,+xcheripurecap,+xcheriot -o - | FileCheck %s target datalayout = "e-m:e-p:32:32-i64:64-n32-S128-pf200:64:64:64:32-A200-P200-G200" target triple = "riscv32cheriot-unknown-cheriotrtos" @@ -19,7 +19,7 @@ entry: ret i32 42 } -attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cheriot" "target-features"="+32bit,+c,+cap-mode,+e,+m,+relax,+xcheri,+zmmul,-a,-b,-d,-experimental-sdext,-experimental-sdtrig,-experimental-smctr,-experimental-ssctr,-experimental-svukte,-experimental-xqcia,-experimental-xqciac,-experimental-xqcicli,-experimental-xqcicm,-experimental-xqcics,-experimental-xqcicsr,-experimental-xqciint,-experimental-xqcilo,-experimental-xqcilsm,-experimental-xqcisls,-experimental-zalasr,-experimental-zicfilp,-experimental-zicfiss,-experimental-zvbc32e,-experimental-zvkgs,-f,-h,-i,-sha,-shcounterenw,-shgatpa,-shtvala,-shvsatpa,-shvstvala,-shvstvecd,-smaia,-smcdeleg,-smcsrind,-smdbltrp,-smepmp,-smmpm,-smnpm,-smrnmi,-smstateen,-ssaia,-ssccfg,-ssccptr,-sscofpmf,-sscounterenw,-sscsrind,-ssdbltrp,-ssnpm,-sspm,-ssqosid,-ssstateen,-ssstrict,-sstc,-sstvala,-sstvecd,-ssu64xl,-supm,-svade,-svadu,-svbare,-svinval,-svnapot,-svpbmt,-svvptc,-v,-xcheriot,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xmipscmove,-xmipslsp,-xsfcease,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xsifivecdiscarddlone,-xsifivecflushdlone,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-xwchc,-za128rs,-za64rs,-zaamo,-zabha,-zacas,-zalrsc,-zama16b,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmop,-zcmp,-zcmt,-zdinx,-zfa,-zfbfmin,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zimop,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-ztso,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfbfmin,-zvfbfwma,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } +attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cheriot" "target-features"="+32bit,+c,+xcheripurecap,+e,+m,+relax,+xcheri,+zmmul,-a,-b,-d,-experimental-sdext,-experimental-sdtrig,-experimental-smctr,-experimental-ssctr,-experimental-svukte,-experimental-xqcia,-experimental-xqciac,-experimental-xqcicli,-experimental-xqcicm,-experimental-xqcics,-experimental-xqcicsr,-experimental-xqciint,-experimental-xqcilo,-experimental-xqcilsm,-experimental-xqcisls,-experimental-zalasr,-experimental-zicfilp,-experimental-zicfiss,-experimental-zvbc32e,-experimental-zvkgs,-f,-h,-i,-sha,-shcounterenw,-shgatpa,-shtvala,-shvsatpa,-shvstvala,-shvstvecd,-smaia,-smcdeleg,-smcsrind,-smdbltrp,-smepmp,-smmpm,-smnpm,-smrnmi,-smstateen,-ssaia,-ssccfg,-ssccptr,-sscofpmf,-sscounterenw,-sscsrind,-ssdbltrp,-ssnpm,-sspm,-ssqosid,-ssstateen,-ssstrict,-sstc,-sstvala,-sstvecd,-ssu64xl,-supm,-svade,-svadu,-svbare,-svinval,-svnapot,-svpbmt,-svvptc,-v,-xcheriot,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xmipscmove,-xmipslsp,-xsfcease,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xsifivecdiscarddlone,-xsifivecflushdlone,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-xwchc,-za128rs,-za64rs,-zaamo,-zabha,-zacas,-zalrsc,-zama16b,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmop,-zcmp,-zcmt,-zdinx,-zfa,-zfbfmin,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zimop,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-ztso,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfbfmin,-zvfbfwma,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } !llvm.module.flags = !{!0, !1, !2, !4} !llvm.ident = !{!5} diff --git a/llvm/test/CodeGen/RISCV/cheri/cheriot-globalalias.ll b/llvm/test/CodeGen/RISCV/cheri/cheriot-globalalias.ll index b1f9a92fa5127..31bea950eee3c 100644 --- a/llvm/test/CodeGen/RISCV/cheri/cheriot-globalalias.ll +++ b/llvm/test/CodeGen/RISCV/cheri/cheriot-globalalias.ll @@ -1,4 +1,4 @@ -; RUN: llc --filetype=asm --mcpu=cheriot --mtriple=riscv32cheriot-unknown-cheriotrtos -target-abi cheriot %s -mattr=+xcheri,+cap-mode,+xcheriot -o - | FileCheck %s +; RUN: llc --filetype=asm --mcpu=cheriot --mtriple=riscv32cheriot-unknown-cheriotrtos -target-abi cheriot %s -mattr=+xcheri,+xcheripurecap,+xcheriot -o - | FileCheck %s target datalayout = "e-m:e-p:32:32-i64:64-n32-S128-pf200:64:64:64:32-A200-P200-G200" target triple = "riscv32cheriot-unknown-cheriotrtos" @@ -27,7 +27,7 @@ entry: @_Z3barv = alias i32(), ptr addrspace(200) @_Z3foov -attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cheriot" "target-features"="+32bit,+c,+cap-mode,+e,+m,+relax,+xcheri,+zmmul,-a,-b,-d,-experimental-sdext,-experimental-sdtrig,-experimental-smctr,-experimental-ssctr,-experimental-svukte,-experimental-xqcia,-experimental-xqciac,-experimental-xqcicli,-experimental-xqcicm,-experimental-xqcics,-experimental-xqcicsr,-experimental-xqciint,-experimental-xqcilo,-experimental-xqcilsm,-experimental-xqcisls,-experimental-zalasr,-experimental-zicfilp,-experimental-zicfiss,-experimental-zvbc32e,-experimental-zvkgs,-f,-h,-i,-sha,-shcounterenw,-shgatpa,-shtvala,-shvsatpa,-shvstvala,-shvstvecd,-smaia,-smcdeleg,-smcsrind,-smdbltrp,-smepmp,-smmpm,-smnpm,-smrnmi,-smstateen,-ssaia,-ssccfg,-ssccptr,-sscofpmf,-sscounterenw,-sscsrind,-ssdbltrp,-ssnpm,-sspm,-ssqosid,-ssstateen,-ssstrict,-sstc,-sstvala,-sstvecd,-ssu64xl,-supm,-svade,-svadu,-svbare,-svinval,-svnapot,-svpbmt,-svvptc,-v,-xcheriot,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xmipscmove,-xmipslsp,-xsfcease,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xsifivecdiscarddlone,-xsifivecflushdlone,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-xwchc,-za128rs,-za64rs,-zaamo,-zabha,-zacas,-zalrsc,-zama16b,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmop,-zcmp,-zcmt,-zdinx,-zfa,-zfbfmin,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zimop,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-ztso,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfbfmin,-zvfbfwma,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } +attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cheriot" "target-features"="+32bit,+c,+xcheripurecap,+e,+m,+relax,+xcheri,+zmmul,-a,-b,-d,-experimental-sdext,-experimental-sdtrig,-experimental-smctr,-experimental-ssctr,-experimental-svukte,-experimental-xqcia,-experimental-xqciac,-experimental-xqcicli,-experimental-xqcicm,-experimental-xqcics,-experimental-xqcicsr,-experimental-xqciint,-experimental-xqcilo,-experimental-xqcilsm,-experimental-xqcisls,-experimental-zalasr,-experimental-zicfilp,-experimental-zicfiss,-experimental-zvbc32e,-experimental-zvkgs,-f,-h,-i,-sha,-shcounterenw,-shgatpa,-shtvala,-shvsatpa,-shvstvala,-shvstvecd,-smaia,-smcdeleg,-smcsrind,-smdbltrp,-smepmp,-smmpm,-smnpm,-smrnmi,-smstateen,-ssaia,-ssccfg,-ssccptr,-sscofpmf,-sscounterenw,-sscsrind,-ssdbltrp,-ssnpm,-sspm,-ssqosid,-ssstateen,-ssstrict,-sstc,-sstvala,-sstvecd,-ssu64xl,-supm,-svade,-svadu,-svbare,-svinval,-svnapot,-svpbmt,-svvptc,-v,-xcheriot,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xmipscmove,-xmipslsp,-xsfcease,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xsifivecdiscarddlone,-xsifivecflushdlone,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-xwchc,-za128rs,-za64rs,-zaamo,-zabha,-zacas,-zalrsc,-zama16b,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmop,-zcmp,-zcmt,-zdinx,-zfa,-zfbfmin,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zimop,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-ztso,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfbfmin,-zvfbfwma,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } !llvm.module.flags = !{!0, !1, !2, !4} !llvm.ident = !{!5} diff --git a/llvm/test/CodeGen/RISCV/cheri/cheriot-globals.ll b/llvm/test/CodeGen/RISCV/cheri/cheriot-globals.ll index e0f6d81385ce1..2c99ffc706045 100644 --- a/llvm/test/CodeGen/RISCV/cheri/cheriot-globals.ll +++ b/llvm/test/CodeGen/RISCV/cheri/cheriot-globals.ll @@ -1,4 +1,4 @@ -; RUN: llc --filetype=asm --mcpu=cheriot --mtriple=riscv32-unknown-unknown -target-abi cheriot %s -mattr=+xcheri,+cap-mode -o - | FileCheck %s +; RUN: llc --filetype=asm --mcpu=cheriot --mtriple=riscv32-unknown-unknown -target-abi cheriot %s -mattr=+xcheri,+xcheripurecap -o - | FileCheck %s ; ModuleID = 'glob.c' source_filename = "glob.c" target datalayout = "e-m:e-pf200:64:64:64:32-p:32:32-i64:64-n32-S128-A200-P200-G200" diff --git a/llvm/test/CodeGen/RISCV/cheri/cheriot-jump-table-address.ll b/llvm/test/CodeGen/RISCV/cheri/cheriot-jump-table-address.ll index 04105be1820f2..8d4ff2866081f 100644 --- a/llvm/test/CodeGen/RISCV/cheri/cheriot-jump-table-address.ll +++ b/llvm/test/CodeGen/RISCV/cheri/cheriot-jump-table-address.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 -; RUN: llc --filetype=asm --mcpu=cheriot --mtriple=riscv32-unknown-unknown -target-abi cheriot %s -mattr=+xcheri,+cap-mode -o - | FileCheck %s +; RUN: llc --filetype=asm --mcpu=cheriot --mtriple=riscv32-unknown-unknown -target-abi cheriot %s -mattr=+xcheri,+xcheripurecap -o - | FileCheck %s target datalayout = "e-m:e-pf200:64:64:64:32-p:32:32-i64:64-n32-S128-A200-P200-G200" target triple = "riscv32-unknown-unknown" diff --git a/llvm/test/CodeGen/RISCV/cheri/cheriot-jumptable.ll b/llvm/test/CodeGen/RISCV/cheri/cheriot-jumptable.ll index 896694df1a96a..71ccb637412d4 100644 --- a/llvm/test/CodeGen/RISCV/cheri/cheriot-jumptable.ll +++ b/llvm/test/CodeGen/RISCV/cheri/cheriot-jumptable.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 -; RUN: llc --filetype=asm --mcpu=cheriot --mtriple=riscv32-unknown-unknown -target-abi cheriot -mattr=+xcheri,+cap-mode -o - -verify-machineinstrs < %s | FileCheck %s +; RUN: llc --filetype=asm --mcpu=cheriot --mtriple=riscv32-unknown-unknown -target-abi cheriot -mattr=+xcheri,+xcheripurecap -o - -verify-machineinstrs < %s | FileCheck %s target datalayout = "e-m:e-pf200:64:64:64:32-p:32:32-i64:64-n32-S128-A200-P200-G200" target triple = "riscv32-unknown-unknown" diff --git a/llvm/test/CodeGen/RISCV/cheri/cheriot-load-store-relocs.ll b/llvm/test/CodeGen/RISCV/cheri/cheriot-load-store-relocs.ll index f5ad0ad3f9c1d..19581264e9ed0 100644 --- a/llvm/test/CodeGen/RISCV/cheri/cheriot-load-store-relocs.ll +++ b/llvm/test/CodeGen/RISCV/cheri/cheriot-load-store-relocs.ll @@ -1,4 +1,4 @@ -; RUN: llc --filetype=asm --mcpu=cheriot --mtriple=riscv32-unknown-unknown -target-abi cheriot %s -mattr=+xcheri,+cap-mode -o - | FileCheck %s +; RUN: llc --filetype=asm --mcpu=cheriot --mtriple=riscv32-unknown-unknown -target-abi cheriot %s -mattr=+xcheri,+xcheripurecap -o - | FileCheck %s ; ModuleID = 'ex.c' target datalayout = "e-m:e-pf200:64:64:64:32-p:32:32-i64:64-n32-S128-A200-P200-G200" target triple = "riscv32-unknown-unknown" diff --git a/llvm/test/CodeGen/RISCV/cheri/cheriot-no-global-bounds-checks.ll b/llvm/test/CodeGen/RISCV/cheri/cheriot-no-global-bounds-checks.ll index d08f0e314a9bd..3dcdf10651d5a 100644 --- a/llvm/test/CodeGen/RISCV/cheri/cheriot-no-global-bounds-checks.ll +++ b/llvm/test/CodeGen/RISCV/cheri/cheriot-no-global-bounds-checks.ll @@ -1,4 +1,4 @@ -; RUN: llc --filetype=asm --mcpu=cheriot --mtriple=riscv32cheriot-unknown-unknown -target-abi cheriot %s -mattr=+xcheri,+cap-mode -o - | FileCheck %s +; RUN: llc --filetype=asm --mcpu=cheriot --mtriple=riscv32cheriot-unknown-unknown -target-abi cheriot %s -mattr=+xcheri,+xcheripurecap -o - | FileCheck %s ; ModuleID = 'test.c' source_filename = "../Release/test.c" target datalayout = "e-m:e-pf200:64:64:64:32-p:32:32-i64:64-n32-S128-A200-P200-G200" diff --git a/llvm/test/CodeGen/RISCV/cheri/cheriot-offset-get.ll b/llvm/test/CodeGen/RISCV/cheri/cheriot-offset-get.ll index 6452ec234c875..3a0663fc59b76 100644 --- a/llvm/test/CodeGen/RISCV/cheri/cheriot-offset-get.ll +++ b/llvm/test/CodeGen/RISCV/cheri/cheriot-offset-get.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -mtriple=riscv32cheriot --mcpu=cheriot -target-abi=cheriot -mattr=+xcheri,+cap-mode,+xcheriot -o - %s | FileCheck %s +; RUN: llc -mtriple=riscv32cheriot --mcpu=cheriot -target-abi=cheriot -mattr=+xcheri,+xcheripurecap,+xcheriot -o - %s | FileCheck %s define i32 @test1(i8 addrspace(200)* %cap) nounwind { ; CHECK-LABEL: test1: diff --git a/llvm/test/CodeGen/RISCV/cheri/cheriot-sealed-attr.ll b/llvm/test/CodeGen/RISCV/cheri/cheriot-sealed-attr.ll index 7573d20112634..2a35abeff6bbf 100644 --- a/llvm/test/CodeGen/RISCV/cheri/cheriot-sealed-attr.ll +++ b/llvm/test/CodeGen/RISCV/cheri/cheriot-sealed-attr.ll @@ -1,4 +1,4 @@ -; RUN: llc -O0 --filetype=asm --mcpu=cheriot --mtriple=riscv32cheriot-unknown-cheriotrtos -target-abi cheriot -mattr=+c,+xcheriot,+xcheri,+cap-mode < %s | FileCheck %s +; RUN: llc -O0 --filetype=asm --mcpu=cheriot --mtriple=riscv32cheriot-unknown-cheriotrtos -target-abi cheriot -mattr=+c,+xcheriot,+xcheri,+xcheripurecap < %s | FileCheck %s target datalayout = "e-m:e-p:32:32-i64:64-n32-S128-pf200:64:64:64:32-A200-P200-G200" target triple = "riscv32cheriot-unknown-cheriotrtos" diff --git a/llvm/test/CodeGen/RISCV/cheri/cheriot-sealing-key-attr.ll b/llvm/test/CodeGen/RISCV/cheri/cheriot-sealing-key-attr.ll index 17468909cde17..3710dc4e4e483 100644 --- a/llvm/test/CodeGen/RISCV/cheri/cheriot-sealing-key-attr.ll +++ b/llvm/test/CodeGen/RISCV/cheri/cheriot-sealing-key-attr.ll @@ -1,4 +1,4 @@ -; RUN: llc -O0 --filetype=asm --mcpu=cheriot --mtriple=riscv32-unknown-unknown-cheriotrtos -target-abi cheriot -mattr=+xcheri,+cap-mode < %s | FileCheck %s +; RUN: llc -O0 --filetype=asm --mcpu=cheriot --mtriple=riscv32-unknown-unknown-cheriotrtos -target-abi cheriot -mattr=+xcheri,+xcheripurecap < %s | FileCheck %s target datalayout = "e-m:e-p:32:32-i64:64-n32-S128-pf200:64:64:64:32-A200-P200-G200" target triple = "riscv32-unknown-cheriotrtos-unknown" diff --git a/llvm/test/CodeGen/RISCV/cheri/cheriot-stack-size-export.ll b/llvm/test/CodeGen/RISCV/cheri/cheriot-stack-size-export.ll index 9245be22de1f0..7e2d307fea591 100644 --- a/llvm/test/CodeGen/RISCV/cheri/cheriot-stack-size-export.ll +++ b/llvm/test/CodeGen/RISCV/cheri/cheriot-stack-size-export.ll @@ -1,4 +1,4 @@ -; RUN: llc --filetype=asm --mcpu=cheriot --mtriple=riscv32-unknown-unknown -target-abi cheriot %s -mattr=+xcheri,+cap-mode -o - | FileCheck %s +; RUN: llc --filetype=asm --mcpu=cheriot --mtriple=riscv32-unknown-unknown -target-abi cheriot %s -mattr=+xcheri,+xcheripurecap -o - | FileCheck %s ; ModuleID = '/tmp/spill.c' target datalayout = "e-m:e-pf200:64:64:64:32-p:32:32-i64:64-n32-S128-A200-P200-G200" target triple = "riscv32-unknown-unknown" diff --git a/llvm/test/CodeGen/RISCV/cheri/cheriot-stack-size.ll b/llvm/test/CodeGen/RISCV/cheri/cheriot-stack-size.ll index 9c558667ceced..d452f2623d502 100644 --- a/llvm/test/CodeGen/RISCV/cheri/cheriot-stack-size.ll +++ b/llvm/test/CodeGen/RISCV/cheri/cheriot-stack-size.ll @@ -1,4 +1,4 @@ -; RUN: llc --filetype=asm --mcpu=cheriot --mtriple=riscv32-unknown-unknown -target-abi cheriot %s -mattr=+xcheri,+cap-mode -o - | FileCheck %s +; RUN: llc --filetype=asm --mcpu=cheriot --mtriple=riscv32-unknown-unknown -target-abi cheriot %s -mattr=+xcheri,+xcheripurecap -o - | FileCheck %s ; ModuleID = 'stack.c' source_filename = "stack.c" target datalayout = "e-m:e-pf200:64:64:64:32-p:32:32-i64:64-n32-S128-A200-P200-G200" diff --git a/llvm/test/CodeGen/RISCV/cheri/cheriot-struct-ret.ll b/llvm/test/CodeGen/RISCV/cheri/cheriot-struct-ret.ll index cd18b779ba468..9648bfde98d80 100644 --- a/llvm/test/CodeGen/RISCV/cheri/cheriot-struct-ret.ll +++ b/llvm/test/CodeGen/RISCV/cheri/cheriot-struct-ret.ll @@ -1,4 +1,4 @@ -; RUN: llc --filetype=asm --mcpu=cheriot --mtriple=riscv32cheriot-unknown-cheriotrtos -target-abi cheriot %s -mattr=+xcheri,+cap-mode,+xcheriot -o - | FileCheck %s +; RUN: llc --filetype=asm --mcpu=cheriot --mtriple=riscv32cheriot-unknown-cheriotrtos -target-abi cheriot %s -mattr=+xcheri,+xcheripurecap,+xcheriot -o - | FileCheck %s target datalayout = "e-m:e-p:32:32-i64:64-n32-S128-pf200:64:64:64:32-A200-P200-G200" target triple = "riscv32cheriot-unknown-cheriotrtos" @@ -736,14 +736,14 @@ entry: ret %struct.ParentPtr %.fca.1.0.insert } -attributes #0 = { mustprogress nofree noinline norecurse nosync nounwind willreturn memory(readwrite, argmem: none, inaccessiblemem: none) "cheri-compartment"="example" "interrupt-state"="enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+c,+cap-mode,+e,+m,+xcheri" } -attributes #1 = { mustprogress nofree noinline norecurse nosync nounwind willreturn memory(readwrite, inaccessiblemem: none) "cheri-compartment"="example" "interrupt-state"="enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+c,+cap-mode,+e,+m,+xcheri" } -attributes #2 = { mustprogress nofree norecurse nosync nounwind willreturn memory(readwrite, inaccessiblemem: none) "cheri-compartment"="example" "interrupt-state"="enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+c,+cap-mode,+e,+m,+xcheri" } +attributes #0 = { mustprogress nofree noinline norecurse nosync nounwind willreturn memory(readwrite, argmem: none, inaccessiblemem: none) "cheri-compartment"="example" "interrupt-state"="enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+c,+xcheripurecap,+e,+m,+xcheri" } +attributes #1 = { mustprogress nofree noinline norecurse nosync nounwind willreturn memory(readwrite, inaccessiblemem: none) "cheri-compartment"="example" "interrupt-state"="enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+c,+xcheripurecap,+e,+m,+xcheri" } +attributes #2 = { mustprogress nofree norecurse nosync nounwind willreturn memory(readwrite, inaccessiblemem: none) "cheri-compartment"="example" "interrupt-state"="enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+c,+xcheripurecap,+e,+m,+xcheri" } attributes #3 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) } -attributes #4 = { mustprogress nofree noinline norecurse nosync nounwind willreturn memory(none) "cheri-compartment"="example" "interrupt-state"="enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+c,+cap-mode,+e,+m,+xcheri" } -attributes #5 = { nofree noinline norecurse nosync nounwind "cheri-compartment"="example" "interrupt-state"="enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+c,+cap-mode,+e,+m,+xcheri" } +attributes #4 = { mustprogress nofree noinline norecurse nosync nounwind willreturn memory(none) "cheri-compartment"="example" "interrupt-state"="enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+c,+xcheripurecap,+e,+m,+xcheri" } +attributes #5 = { nofree noinline norecurse nosync nounwind "cheri-compartment"="example" "interrupt-state"="enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+c,+xcheripurecap,+e,+m,+xcheri" } attributes #6 = { mustprogress nocallback nofree nosync nounwind willreturn } -attributes #7 = { nofree noinline norecurse nounwind "cheri-compartment"="example" "interrupt-state"="enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+c,+cap-mode,+e,+m,+xcheri" } +attributes #7 = { nofree noinline norecurse nounwind "cheri-compartment"="example" "interrupt-state"="enabled" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+32bit,+c,+xcheripurecap,+e,+m,+xcheri" } attributes #8 = { nounwind } !llvm.module.flags = !{!0, !1, !2, !4, !5} diff --git a/llvm/test/CodeGen/RISCV/cheri/cheriot-variadic-double-align.ll b/llvm/test/CodeGen/RISCV/cheri/cheriot-variadic-double-align.ll index 67708f3915265..05f4e481e44da 100644 --- a/llvm/test/CodeGen/RISCV/cheri/cheriot-variadic-double-align.ll +++ b/llvm/test/CodeGen/RISCV/cheri/cheriot-variadic-double-align.ll @@ -1,4 +1,4 @@ -; RUN: llc --filetype=asm --mcpu=cheriot --mtriple=riscv32cheriot-unknown-cheriotrtos -target-abi cheriot -mattr=+xcheri,+cap-mode,+xcheriot %s -o - | FileCheck %s +; RUN: llc --filetype=asm --mcpu=cheriot --mtriple=riscv32cheriot-unknown-cheriotrtos -target-abi cheriot -mattr=+xcheri,+xcheripurecap,+xcheriot %s -o - | FileCheck %s ; Verify that varargs doubles are aligned to 8 bytes on the stack. diff --git a/llvm/test/CodeGen/RISCV/cheri/cheriot-zero-ret.ll b/llvm/test/CodeGen/RISCV/cheri/cheriot-zero-ret.ll index 51b394f510dda..8cbc4c4aad69e 100644 --- a/llvm/test/CodeGen/RISCV/cheri/cheriot-zero-ret.ll +++ b/llvm/test/CodeGen/RISCV/cheri/cheriot-zero-ret.ll @@ -1,4 +1,4 @@ -; RUN: llc --filetype=asm --mcpu=cheriot --mtriple=riscv32-unknown-unknown -target-abi cheriot %s -mattr=+xcheri,+cap-mode -o - | FileCheck %s +; RUN: llc --filetype=asm --mcpu=cheriot --mtriple=riscv32-unknown-unknown -target-abi cheriot %s -mattr=+xcheri,+xcheripurecap -o - | FileCheck %s ; ModuleID = 'test.cc' source_filename = "test.cc" target datalayout = "e-m:e-pf200:64:64:64:32-p:32:32-i64:64-n32-S128-A200-P200-G200" diff --git a/llvm/test/CodeGen/RISCV/cheri/cheriot-zero-sret.ll b/llvm/test/CodeGen/RISCV/cheri/cheriot-zero-sret.ll index f907f04f6731c..6cd84026d9e23 100644 --- a/llvm/test/CodeGen/RISCV/cheri/cheriot-zero-sret.ll +++ b/llvm/test/CodeGen/RISCV/cheri/cheriot-zero-sret.ll @@ -1,4 +1,4 @@ -; RUN: llc --filetype=asm --mcpu=cheriot --mtriple=riscv32-unknown-unknown -target-abi cheriot %s -mattr=+xcheri,+cap-mode -o - | FileCheck %s +; RUN: llc --filetype=asm --mcpu=cheriot --mtriple=riscv32-unknown-unknown -target-abi cheriot %s -mattr=+xcheri,+xcheripurecap -o - | FileCheck %s ; ModuleID = 'sret.cc' source_filename = "sret.cc" target datalayout = "e-m:e-pf200:64:64:64:32-p:32:32-i64:64-n32-S128-A200-P200-G200" diff --git a/llvm/test/CodeGen/RISCV/cheri/compress.ll b/llvm/test/CodeGen/RISCV/cheri/compress.ll index be89d9ba1feaa..f546d91ec2f5a 100644 --- a/llvm/test/CodeGen/RISCV/cheri/compress.ll +++ b/llvm/test/CodeGen/RISCV/cheri/compress.ll @@ -4,21 +4,21 @@ ; ; RUN: cat %s > %t.tgtattr ; RUN: echo 'attributes #0 = { nounwind }' >> %t.tgtattr -; RUN: %riscv32_cheri_purecap_llc -mattr=+c,+xcheri,+cap-mode -filetype=obj < %t.tgtattr \ +; RUN: %riscv32_cheri_purecap_llc -mattr=+c,+xcheri,+xcheripurecap -filetype=obj < %t.tgtattr \ ; RUN: | llvm-objdump -d -M no-aliases - | FileCheck %s -; RUN: %riscv64_cheri_purecap_llc -mattr=+c,+xcheri,+cap-mode -filetype=obj < %t.tgtattr \ +; RUN: %riscv64_cheri_purecap_llc -mattr=+c,+xcheri,+xcheripurecap -filetype=obj < %t.tgtattr \ ; RUN: | llvm-objdump -d -M no-aliases - | FileCheck %s -; RUN: %riscv64_cheri_purecap_llc -mattr=+c,+xcheri,+cap-mode,+xcheri-norvc -filetype=obj < %t.tgtattr \ +; RUN: %riscv64_cheri_purecap_llc -mattr=+c,+xcheri,+xcheripurecap,+xcheri-norvc -filetype=obj < %t.tgtattr \ ; RUN: | llvm-objdump -d -M no-aliases - | FileCheck %s --check-prefix=CHECK-NORVC ; RUN: cat %s > %t.fnattr -; RUN: echo 'attributes #0 = { nounwind "target-features"="+c,+xcheri,+cap-mode" }' >> %t.fnattr +; RUN: echo 'attributes #0 = { nounwind "target-features"="+c,+xcheri,+xcheripurecap" }' >> %t.fnattr ; RUN: %riscv32_cheri_purecap_llc -filetype=obj < %t.fnattr \ ; RUN: | llvm-objdump -d --mattr=+c -M no-aliases - | FileCheck %s ; RUN: %riscv64_cheri_purecap_llc -filetype=obj < %t.fnattr \ ; RUN: | llvm-objdump -d --mattr=+c -M no-aliases - | FileCheck %s ; RUN: cat %s > %t.fnattr -; RUN: echo 'attributes #0 = { nounwind "target-features"="+c,+xcheri,+cap-mode,+xcheri-norvc" }' >> %t.fnattr +; RUN: echo 'attributes #0 = { nounwind "target-features"="+c,+xcheri,+xcheripurecap,+xcheri-norvc" }' >> %t.fnattr ; RUN: %riscv64_cheri_purecap_llc -filetype=obj < %t.fnattr \ ; RUN: | llvm-objdump -d --mattr=+c -M no-aliases - | FileCheck %s --check-prefix=CHECK-NORVC diff --git a/llvm/test/CodeGen/RISCV/cheri/double-mem.ll b/llvm/test/CodeGen/RISCV/cheri/double-mem.ll index 1338b0f272b02..880188873ab09 100644 --- a/llvm/test/CodeGen/RISCV/cheri/double-mem.ll +++ b/llvm/test/CodeGen/RISCV/cheri/double-mem.ll @@ -3,17 +3,17 @@ ; RUN: | FileCheck -check-prefix=CHECK-ILP32 %s ; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=+f,+d,+xcheri,-cap-mode -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=CHECK-ILP32D %s -; RUN: llc -mtriple=riscv32 -target-abi il32pc64 -mattr=+f,+d,+xcheri,+cap-mode -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -target-abi il32pc64 -mattr=+f,+d,+xcheri,+xcheripurecap -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=CHECK-IL32PC64 %s -; RUN: llc -mtriple=riscv32 -target-abi il32pc64d -mattr=+f,+d,+xcheri,+cap-mode -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -target-abi il32pc64d -mattr=+f,+d,+xcheri,+xcheripurecap -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=CHECK-IL32PC64D %s ; RUN: llc -mtriple=riscv64 -target-abi lp64 -mattr=+f,+d,+xcheri,-cap-mode -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=CHECK-LP64 %s ; RUN: llc -mtriple=riscv64 -target-abi lp64d -mattr=+f,+d,+xcheri,-cap-mode -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=CHECK-LP64D %s -; RUN: llc -mtriple=riscv64 -target-abi l64pc128 -mattr=+f,+d,+xcheri,+cap-mode -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -target-abi l64pc128 -mattr=+f,+d,+xcheri,+xcheripurecap -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=CHECK-L64PC128 %s -; RUN: llc -mtriple=riscv64 -target-abi l64pc128d -mattr=+f,+d,+xcheri,+cap-mode -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -target-abi l64pc128d -mattr=+f,+d,+xcheri,+xcheripurecap -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=CHECK-L64PC128D %s ; Uses both loaded values in an FP op to ensure an fld is used, even for the diff --git a/llvm/test/CodeGen/RISCV/cheri/float-mem.ll b/llvm/test/CodeGen/RISCV/cheri/float-mem.ll index 932f023db87ff..eb327403624b8 100644 --- a/llvm/test/CodeGen/RISCV/cheri/float-mem.ll +++ b/llvm/test/CodeGen/RISCV/cheri/float-mem.ll @@ -3,17 +3,17 @@ ; RUN: | FileCheck -check-prefix=CHECK-ILP32 %s ; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+f,+xcheri,-cap-mode -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=CHECK-ILP32F %s -; RUN: llc -mtriple=riscv32 -target-abi il32pc64 -mattr=+f,+xcheri,+cap-mode -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -target-abi il32pc64 -mattr=+f,+xcheri,+xcheripurecap -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=CHECK-IL32PC64 %s -; RUN: llc -mtriple=riscv32 -target-abi il32pc64f -mattr=+f,+xcheri,+cap-mode -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -target-abi il32pc64f -mattr=+f,+xcheri,+xcheripurecap -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=CHECK-IL32PC64F %s ; RUN: llc -mtriple=riscv64 -target-abi lp64 -mattr=+f,+xcheri,-cap-mode -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=CHECK-LP64 %s ; RUN: llc -mtriple=riscv64 -target-abi lp64f -mattr=+f,+xcheri,-cap-mode -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=CHECK-LP64F %s -; RUN: llc -mtriple=riscv64 -target-abi l64pc128 -mattr=+f,+xcheri,+cap-mode -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -target-abi l64pc128 -mattr=+f,+xcheri,+xcheripurecap -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=CHECK-L64PC128 %s -; RUN: llc -mtriple=riscv64 -target-abi l64pc128f -mattr=+f,+xcheri,+cap-mode -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -target-abi l64pc128f -mattr=+f,+xcheri,+xcheripurecap -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=CHECK-L64PC128F %s ; Uses both loaded values in an FP op to ensure an flw is used, even for the diff --git a/llvm/test/CodeGen/RISCV/cheri/function-start-directives.ll b/llvm/test/CodeGen/RISCV/cheri/function-start-directives.ll index 45ed524a385c1..7bd3666a46632 100644 --- a/llvm/test/CodeGen/RISCV/cheri/function-start-directives.ll +++ b/llvm/test/CodeGen/RISCV/cheri/function-start-directives.ll @@ -42,7 +42,7 @@ declare dso_local ptr addrspace(200) @__cxa_begin_catch(ptr addrspace(200)) loca declare dso_local void @__cxa_end_catch() local_unnamed_addr addrspace(200) ; CHECK: .attribute 4, 16 -; CHECK-NEXT: .attribute 5, "rv64i2p1_xcheri0p0" +; CHECK-NEXT: .attribute 5, "rv64i2p1_xcheri0p0_xcheripurecap0p0" ; CHECK-NEXT: .file "" ; CHECK-NEXT: .text ; CHECK-NEXT: .globl _Z4testv # -- Begin function _Z4testv diff --git a/llvm/test/CodeGen/RISCV/cheri/global-cap-import-attributes.ll b/llvm/test/CodeGen/RISCV/cheri/global-cap-import-attributes.ll index 416a43c9d2846..6fb95cd8bb084 100644 --- a/llvm/test/CodeGen/RISCV/cheri/global-cap-import-attributes.ll +++ b/llvm/test/CodeGen/RISCV/cheri/global-cap-import-attributes.ll @@ -1,4 +1,4 @@ -; RUN: llc --filetype=asm --mcpu=cheriot --mtriple=riscv32-unknown-unknown-cheriotrtos -target-abi cheriot -mattr=+xcheri,+cap-mode < %s | FileCheck %s +; RUN: llc --filetype=asm --mcpu=cheriot --mtriple=riscv32-unknown-unknown-cheriotrtos -target-abi cheriot -mattr=+xcheri,+xcheripurecap < %s | FileCheck %s target datalayout = "e-m:e-p:32:32-i64:64-n32-S128-pf200:64:64:64:32-A200-P200-G200" target triple = "riscv32cheriot-unknown-cheriotrtos" @@ -341,8 +341,8 @@ declare dso_local void @_Z19doSomethingWithSharedObjectP4SharedObject(ptr addrsp ; CHECK-NEXT: .size __import_cheriot_shared_object_shared_obj_RWcm, 8 @shared_obj_RWcm = external addrspace(200) global %struct.Uart, align 1 "cheriot_global_cap_import" = "cheriot_shared_object,shared_obj,RWcm" -attributes #0 = { mustprogress noinline optnone "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cheriot" "target-features"="+32bit,+c,+cap-mode,+e,+m,+relax,+xcheri,+zmmul,-a,-b,-d,-experimental-sdext,-experimental-sdtrig,-experimental-smctr,-experimental-ssctr,-experimental-svukte,-experimental-xqcia,-experimental-xqciac,-experimental-xqcicli,-experimental-xqcicm,-experimental-xqcics,-experimental-xqcicsr,-experimental-xqciint,-experimental-xqcilo,-experimental-xqcilsm,-experimental-xqcisls,-experimental-zalasr,-experimental-zicfilp,-experimental-zicfiss,-experimental-zvbc32e,-experimental-zvkgs,-f,-h,-i,-sha,-shcounterenw,-shgatpa,-shtvala,-shvsatpa,-shvstvala,-shvstvecd,-smaia,-smcdeleg,-smcsrind,-smdbltrp,-smepmp,-smmpm,-smnpm,-smrnmi,-smstateen,-ssaia,-ssccfg,-ssccptr,-sscofpmf,-sscounterenw,-sscsrind,-ssdbltrp,-ssnpm,-sspm,-ssqosid,-ssstateen,-ssstrict,-sstc,-sstvala,-sstvecd,-ssu64xl,-supm,-svade,-svadu,-svbare,-svinval,-svnapot,-svpbmt,-svvptc,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xmipscmove,-xmipslsp,-xsfcease,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xsifivecdiscarddlone,-xsifivecflushdlone,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-xwchc,-za128rs,-za64rs,-zaamo,-zabha,-zacas,-zalrsc,-zama16b,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmop,-zcmp,-zcmt,-zdinx,-zfa,-zfbfmin,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zimop,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-ztso,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfbfmin,-zvfbfwma,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } -attributes #1 = { "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cheriot" "target-features"="+32bit,+c,+cap-mode,+e,+m,+relax,+xcheri,+zmmul,-a,-b,-d,-experimental-sdext,-experimental-sdtrig,-experimental-smctr,-experimental-ssctr,-experimental-svukte,-experimental-xqcia,-experimental-xqciac,-experimental-xqcicli,-experimental-xqcicm,-experimental-xqcics,-experimental-xqcicsr,-experimental-xqciint,-experimental-xqcilo,-experimental-xqcilsm,-experimental-xqcisls,-experimental-zalasr,-experimental-zicfilp,-experimental-zicfiss,-experimental-zvbc32e,-experimental-zvkgs,-f,-h,-i,-sha,-shcounterenw,-shgatpa,-shtvala,-shvsatpa,-shvstvala,-shvstvecd,-smaia,-smcdeleg,-smcsrind,-smdbltrp,-smepmp,-smmpm,-smnpm,-smrnmi,-smstateen,-ssaia,-ssccfg,-ssccptr,-sscofpmf,-sscounterenw,-sscsrind,-ssdbltrp,-ssnpm,-sspm,-ssqosid,-ssstateen,-ssstrict,-sstc,-sstvala,-sstvecd,-ssu64xl,-supm,-svade,-svadu,-svbare,-svinval,-svnapot,-svpbmt,-svvptc,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xmipscmove,-xmipslsp,-xsfcease,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xsifivecdiscarddlone,-xsifivecflushdlone,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-xwchc,-za128rs,-za64rs,-zaamo,-zabha,-zacas,-zalrsc,-zama16b,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmop,-zcmp,-zcmt,-zdinx,-zfa,-zfbfmin,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zimop,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-ztso,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfbfmin,-zvfbfwma,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } +attributes #0 = { mustprogress noinline optnone "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cheriot" "target-features"="+32bit,+c,+xcheripurecap,+e,+m,+relax,+xcheri,+zmmul,-a,-b,-d,-experimental-sdext,-experimental-sdtrig,-experimental-smctr,-experimental-ssctr,-experimental-svukte,-experimental-xqcia,-experimental-xqciac,-experimental-xqcicli,-experimental-xqcicm,-experimental-xqcics,-experimental-xqcicsr,-experimental-xqciint,-experimental-xqcilo,-experimental-xqcilsm,-experimental-xqcisls,-experimental-zalasr,-experimental-zicfilp,-experimental-zicfiss,-experimental-zvbc32e,-experimental-zvkgs,-f,-h,-i,-sha,-shcounterenw,-shgatpa,-shtvala,-shvsatpa,-shvstvala,-shvstvecd,-smaia,-smcdeleg,-smcsrind,-smdbltrp,-smepmp,-smmpm,-smnpm,-smrnmi,-smstateen,-ssaia,-ssccfg,-ssccptr,-sscofpmf,-sscounterenw,-sscsrind,-ssdbltrp,-ssnpm,-sspm,-ssqosid,-ssstateen,-ssstrict,-sstc,-sstvala,-sstvecd,-ssu64xl,-supm,-svade,-svadu,-svbare,-svinval,-svnapot,-svpbmt,-svvptc,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xmipscmove,-xmipslsp,-xsfcease,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xsifivecdiscarddlone,-xsifivecflushdlone,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-xwchc,-za128rs,-za64rs,-zaamo,-zabha,-zacas,-zalrsc,-zama16b,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmop,-zcmp,-zcmt,-zdinx,-zfa,-zfbfmin,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zimop,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-ztso,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfbfmin,-zvfbfwma,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } +attributes #1 = { "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cheriot" "target-features"="+32bit,+c,+xcheripurecap,+e,+m,+relax,+xcheri,+zmmul,-a,-b,-d,-experimental-sdext,-experimental-sdtrig,-experimental-smctr,-experimental-ssctr,-experimental-svukte,-experimental-xqcia,-experimental-xqciac,-experimental-xqcicli,-experimental-xqcicm,-experimental-xqcics,-experimental-xqcicsr,-experimental-xqciint,-experimental-xqcilo,-experimental-xqcilsm,-experimental-xqcisls,-experimental-zalasr,-experimental-zicfilp,-experimental-zicfiss,-experimental-zvbc32e,-experimental-zvkgs,-f,-h,-i,-sha,-shcounterenw,-shgatpa,-shtvala,-shvsatpa,-shvstvala,-shvstvecd,-smaia,-smcdeleg,-smcsrind,-smdbltrp,-smepmp,-smmpm,-smnpm,-smrnmi,-smstateen,-ssaia,-ssccfg,-ssccptr,-sscofpmf,-sscounterenw,-sscsrind,-ssdbltrp,-ssnpm,-sspm,-ssqosid,-ssstateen,-ssstrict,-sstc,-sstvala,-sstvecd,-ssu64xl,-supm,-svade,-svadu,-svbare,-svinval,-svnapot,-svpbmt,-svvptc,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xmipscmove,-xmipslsp,-xsfcease,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xsifivecdiscarddlone,-xsifivecflushdlone,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-xwchc,-za128rs,-za64rs,-zaamo,-zabha,-zacas,-zalrsc,-zama16b,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmop,-zcmp,-zcmt,-zdinx,-zfa,-zfbfmin,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zimop,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-ztso,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfbfmin,-zvfbfwma,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } !llvm.module.flags = !{!0, !1, !2, !4, !5} !llvm.ident = !{!6} diff --git a/llvm/test/CodeGen/RISCV/cheri/hoist-setbounds.mir b/llvm/test/CodeGen/RISCV/cheri/hoist-setbounds.mir index 9c1a28dc0e8ca..b64fdf74ed5de 100644 --- a/llvm/test/CodeGen/RISCV/cheri/hoist-setbounds.mir +++ b/llvm/test/CodeGen/RISCV/cheri/hoist-setbounds.mir @@ -43,7 +43,7 @@ declare i8 addrspace(200)* @llvm.cheri.bounded.stack.cap.i64(i8 addrspace(200)*, i64) addrspace(200) #1 - attributes #0 = { nounwind "target-features"="+cap-mode,+xcheri" } + attributes #0 = { nounwind "target-features"="+xcheripurecap,+xcheri" } attributes #1 = { nounwind readnone willreturn } ... diff --git a/llvm/test/CodeGen/RISCV/cheri/rv32-double-calling-conv.ll b/llvm/test/CodeGen/RISCV/cheri/rv32-double-calling-conv.ll index 4083e34f4f180..6c6f390380e2f 100644 --- a/llvm/test/CodeGen/RISCV/cheri/rv32-double-calling-conv.ll +++ b/llvm/test/CodeGen/RISCV/cheri/rv32-double-calling-conv.ll @@ -1,13 +1,13 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -target-abi il32pc64 -mattr=-f,-d,+xcheri,+cap-mode -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -target-abi il32pc64 -mattr=-f,-d,+xcheri,+xcheripurecap -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32IXCHERI-IL32PC64 %s -; RUN: llc -mtriple=riscv32 -target-abi il32pc64 -mattr=+f,+d,+xcheri,+cap-mode -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -target-abi il32pc64 -mattr=+f,+d,+xcheri,+xcheripurecap -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32IFDXCHERI-IL32PC64 %s -; RUN: llc -mtriple=riscv32 -target-abi il32pc64f -mattr=+f,-d,+xcheri,+cap-mode -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -target-abi il32pc64f -mattr=+f,-d,+xcheri,+xcheripurecap -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32IFXCHERI-IL32PC64F %s -; RUN: llc -mtriple=riscv32 -target-abi il32pc64f -mattr=+f,+d,+xcheri,+cap-mode -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -target-abi il32pc64f -mattr=+f,+d,+xcheri,+xcheripurecap -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32IFDXCHERI-IL32PC64F %s -; RUN: llc -mtriple=riscv32 -target-abi il32pc64d -mattr=+f,+d,+xcheri,+cap-mode -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -target-abi il32pc64d -mattr=+f,+d,+xcheri,+xcheripurecap -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32IFDXCHERI-IL32PC64D %s declare void @fixed(double) diff --git a/llvm/test/CodeGen/RISCV/cheri/select-null.ll b/llvm/test/CodeGen/RISCV/cheri/select-null.ll index fcdac867821a8..b8fa2d5399833 100644 --- a/llvm/test/CodeGen/RISCV/cheri/select-null.ll +++ b/llvm/test/CodeGen/RISCV/cheri/select-null.ll @@ -6,7 +6,7 @@ ; Check that integer pointers work: ; RUN: sed 's/addrspace(200)/addrspace(0)/g' %s | %riscv64_cheri_llc -o - -O2 - | FileCheck %s --check-prefix RV64 ; RUN: %riscv64_cheri_purecap_llc %s -o - -O2 | FileCheck %s --check-prefix PURECAP -; RUNs: /Users/alex/cheri/llvm-project/cmake-build-debug/bin/llc -target-abi l64pc128 -mattr=+cap-mode -mtriple=riscv64-unknown-freebsd -mattr=+xcheri -verify-machineinstrs /Users/alex/cheri/llvm-project/llvm/test/CodeGen/RISCV/cheri/phi-not-live-out-regression.ll -o - +; RUNs: /Users/alex/cheri/llvm-project/cmake-build-debug/bin/llc -target-abi l64pc128 -mattr=+xcheripurecap -mtriple=riscv64-unknown-freebsd -mattr=+xcheri -verify-machineinstrs /Users/alex/cheri/llvm-project/llvm/test/CodeGen/RISCV/cheri/phi-not-live-out-regression.ll -o - ; ModuleID = '/Users/alex/cheri/llvm-project/llvm/test/CodeGen/RISCV/cheri/jemalloc_crash.ll' ;source_filename = "/Users/alex/cheri/llvm-project/llvm/test/CodeGen/RISCV/cheri/jemalloc_crash.ll" ;target datalayout = "e-m:e-pf200:128:128:128:64-p:64:64-i64:64-i128:128-n64-S128-A200-P200-G200" diff --git a/llvm/test/CodeGen/RISCV/cheri/unaligned-fp-load-store.ll b/llvm/test/CodeGen/RISCV/cheri/unaligned-fp-load-store.ll index b3e141fb541fa..995ea68cb622e 100644 --- a/llvm/test/CodeGen/RISCV/cheri/unaligned-fp-load-store.ll +++ b/llvm/test/CodeGen/RISCV/cheri/unaligned-fp-load-store.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --extra_scrub ; TODO: Once https://github.com/CTSRD-CHERI/llvm-project/issues/459 has been fixed use +d and il32pc64d -; RUN: llc -mtriple=riscv32 -mattr=+f,+xcheri,+cap-mode -target-abi il32pc64f -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+f,+xcheri,+xcheripurecap -target-abi il32pc64f -verify-machineinstrs < %s \ ; RUN: | %cheri64_FileCheck --check-prefixes=CHECK,RV32IFXCHERI %s --allow-unused-prefixes -; RUN: llc -mtriple=riscv64 -mattr=+f,+xcheri,+cap-mode -target-abi l64pc128f -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+f,+xcheri,+xcheripurecap -target-abi l64pc128f -verify-machineinstrs < %s \ ; RUN: | %cheri128_FileCheck --check-prefixes=CHECK,RV64IFXCHERI %s --allow-unused-prefixes ; Previously expandUnalignedLoad() would trigger assertions for unaligned floating-point values since we were creating ; incorrect capability constants. diff --git a/llvm/test/MC/RISCV/cheri/cheriot.s b/llvm/test/MC/RISCV/cheri/cheriot.s index c5a0dc6ee91a6..1b0f53998cfee 100644 --- a/llvm/test/MC/RISCV/cheri/cheriot.s +++ b/llvm/test/MC/RISCV/cheri/cheriot.s @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 5 // RUN: llvm-mc %s -triple=riscv32cheriot -mcpu=cheriot -mattr=+xcheri,+xcheriot -show-encoding | FileCheck %s -check-prefixes=CHERIOT -// RUN: llvm-mc %s -triple=riscv32 -mattr=+xcheri,+cap-mode -show-encoding | FileCheck %s -check-prefixes=CHERI +// RUN: llvm-mc %s -triple=riscv32 -mattr=+xcheri,+xcheripurecap -show-encoding | FileCheck %s -check-prefixes=CHERI csetboundsrounddown cra, cra, zero // CHERIOT: ct.csetboundsrounddown cra, cra, zero # encoding: [0xdb,0x80,0x00,0x14] diff --git a/llvm/test/MC/RISCV/cheri/rv32axcheri-cap-mode-invalid.s b/llvm/test/MC/RISCV/cheri/rv32axcheri-cap-mode-invalid.s index 5f49ac1ec185d..674620aa0c129 100644 --- a/llvm/test/MC/RISCV/cheri/rv32axcheri-cap-mode-invalid.s +++ b/llvm/test/MC/RISCV/cheri/rv32axcheri-cap-mode-invalid.s @@ -1,4 +1,4 @@ -# RUN: not llvm-mc -triple riscv32 -mattr=+a,+xcheri,+cap-mode < %s 2>&1 | FileCheck %s +# RUN: not llvm-mc -triple riscv32 -mattr=+a,+xcheri,+xcheripurecap < %s 2>&1 | FileCheck %s # Final operand must have parentheses camoswap.w a1, a2, c3 # CHECK: :[[@LINE]]:20: error: expected '(' or optional integer offset diff --git a/llvm/test/MC/RISCV/cheri/rv32axcheri-cap-mode-only-valid.s b/llvm/test/MC/RISCV/cheri/rv32axcheri-cap-mode-only-valid.s index 23275f2c9c4d2..8865eac659d33 100644 --- a/llvm/test/MC/RISCV/cheri/rv32axcheri-cap-mode-only-valid.s +++ b/llvm/test/MC/RISCV/cheri/rv32axcheri-cap-mode-only-valid.s @@ -1,15 +1,15 @@ -# RUN: llvm-mc -triple=riscv32 -mattr=+a,+xcheri,+cap-mode -riscv-no-aliases -show-encoding < %s \ +# RUN: llvm-mc -triple=riscv32 -mattr=+a,+xcheri,+xcheripurecap -riscv-no-aliases -show-encoding < %s \ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+a,+xcheri,+cap-mode < %s \ -# RUN: | llvm-objdump --mattr=+a,+xcheri,+cap-mode -M no-aliases -d -r - \ +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+a,+xcheri,+xcheripurecap < %s \ +# RUN: | llvm-objdump --mattr=+a,+xcheri,+xcheripurecap -M no-aliases -d -r - \ # RUN: | FileCheck -check-prefixes=CHECK-ASM-AND-OBJ %s ## Same test again without the "c" prefix on all lines # RUN: sed -e 's/^c//' < %s > %t.s -# RUN: llvm-mc -triple=riscv32 -mattr=+a,+xcheri,+cap-mode -riscv-no-aliases -show-encoding < %t.s \ +# RUN: llvm-mc -triple=riscv32 -mattr=+a,+xcheri,+xcheripurecap -riscv-no-aliases -show-encoding < %t.s \ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+a,+xcheri,+cap-mode < %t.s \ -# RUN: | llvm-objdump --mattr=+a,+xcheri,+cap-mode -M no-aliases -d -r - \ +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+a,+xcheri,+xcheripurecap < %t.s \ +# RUN: | llvm-objdump --mattr=+a,+xcheri,+xcheripurecap -M no-aliases -d -r - \ # RUN: | FileCheck -check-prefixes=CHECK-ASM-AND-OBJ %s # CHECK-ASM-AND-OBJ: clr.c ct0, (ct1) diff --git a/llvm/test/MC/RISCV/cheri/rv32axcheri-cap-mode-valid.s b/llvm/test/MC/RISCV/cheri/rv32axcheri-cap-mode-valid.s index 9e6db9062e918..e485d6309513f 100644 --- a/llvm/test/MC/RISCV/cheri/rv32axcheri-cap-mode-valid.s +++ b/llvm/test/MC/RISCV/cheri/rv32axcheri-cap-mode-valid.s @@ -1,25 +1,25 @@ -# RUN: llvm-mc -triple=riscv32 -mattr=+a,+xcheri,+cap-mode -riscv-no-aliases -show-encoding < %s\ +# RUN: llvm-mc -triple=riscv32 -mattr=+a,+xcheri,+xcheripurecap -riscv-no-aliases -show-encoding < %s\ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -triple=riscv64 -mattr=+a,+xcheri,+cap-mode -riscv-no-aliases -show-encoding < %s\ +# RUN: llvm-mc -triple=riscv64 -mattr=+a,+xcheri,+xcheripurecap -riscv-no-aliases -show-encoding < %s\ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+a,+xcheri,+cap-mode < %s \ -# RUN: | llvm-objdump --mattr=+a,+xcheri,+cap-mode -M no-aliases -d -r - \ +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+a,+xcheri,+xcheripurecap < %s \ +# RUN: | llvm-objdump --mattr=+a,+xcheri,+xcheripurecap -M no-aliases -d -r - \ # RUN: | FileCheck -check-prefixes=CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+a,+xcheri,+cap-mode < %s \ -# RUN: | llvm-objdump --mattr=+a,+xcheri,+cap-mode -M no-aliases -d -r - \ +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+a,+xcheri,+xcheripurecap < %s \ +# RUN: | llvm-objdump --mattr=+a,+xcheri,+xcheripurecap -M no-aliases -d -r - \ # RUN: | FileCheck -check-prefixes=CHECK-ASM-AND-OBJ %s ## Same test again without the "c" prefix on all lines # RUN: sed -e 's/^c//' < %s > %t.s -# RUN: llvm-mc %t.s -triple=riscv32 -mattr=+a,+xcheri,+cap-mode -riscv-no-aliases -show-encoding \ +# RUN: llvm-mc %t.s -triple=riscv32 -mattr=+a,+xcheri,+xcheripurecap -riscv-no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc %t.s -triple=riscv64 -mattr=+a,+xcheri,+cap-mode -riscv-no-aliases -show-encoding \ +# RUN: llvm-mc %t.s -triple=riscv64 -mattr=+a,+xcheri,+xcheripurecap -riscv-no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+a,+xcheri,+cap-mode < %t.s \ -# RUN: | llvm-objdump --mattr=+a,+xcheri,+cap-mode -M no-aliases -d -r - \ +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+a,+xcheri,+xcheripurecap < %t.s \ +# RUN: | llvm-objdump --mattr=+a,+xcheri,+xcheripurecap -M no-aliases -d -r - \ # RUN: | FileCheck -check-prefixes=CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+a,+xcheri,+cap-mode < %t.s \ -# RUN: | llvm-objdump --mattr=+a,+xcheri,+cap-mode -M no-aliases -d -r - \ +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+a,+xcheri,+xcheripurecap < %t.s \ +# RUN: | llvm-objdump --mattr=+a,+xcheri,+xcheripurecap -M no-aliases -d -r - \ # RUN: | FileCheck -check-prefixes=CHECK-ASM-AND-OBJ %s # CHECK-ASM-AND-OBJ: clr.b t0, (ct1) diff --git a/llvm/test/MC/RISCV/cheri/rv32cxcheri-cap-mode-invalid.s b/llvm/test/MC/RISCV/cheri/rv32cxcheri-cap-mode-invalid.s index 5907f9fd5f334..b66b845ad5113 100644 --- a/llvm/test/MC/RISCV/cheri/rv32cxcheri-cap-mode-invalid.s +++ b/llvm/test/MC/RISCV/cheri/rv32cxcheri-cap-mode-invalid.s @@ -1,10 +1,10 @@ -# RUN: not llvm-mc -triple riscv32 -mattr=+c,+xcheri,+cap-mode -filetype=null -riscv-no-aliases -show-encoding < %s 2>&1 \ +# RUN: not llvm-mc -triple riscv32 -mattr=+c,+xcheri,+xcheripurecap -filetype=null -riscv-no-aliases -show-encoding < %s 2>&1 \ # RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-RV32,CHECK-RV32-C --implicit-check-not="error:" -# RUN: not llvm-mc -triple riscv32 -mattr=+xcheri,+cap-mode -filetype=null -riscv-no-aliases -show-encoding < %s 2>&1 \ +# RUN: not llvm-mc -triple riscv32 -mattr=+xcheri,+xcheripurecap -filetype=null -riscv-no-aliases -show-encoding < %s 2>&1 \ # RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-RV32,CHECK-RV32-NO-C --implicit-check-not="error:" -# RUN: not llvm-mc -triple riscv64 -mattr=+c,+xcheri,+cap-mode -filetype=null -riscv-no-aliases -show-encoding < %s 2>&1\ +# RUN: not llvm-mc -triple riscv64 -mattr=+c,+xcheri,+xcheripurecap -filetype=null -riscv-no-aliases -show-encoding < %s 2>&1\ # RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-RV64-C --implicit-check-not="error:" -# RUN: not llvm-mc -triple riscv64 -mattr=+xcheri,+cap-mode -filetype=null -riscv-no-aliases -show-encoding < %s 2>&1 \ +# RUN: not llvm-mc -triple riscv64 -mattr=+xcheri,+xcheripurecap -filetype=null -riscv-no-aliases -show-encoding < %s 2>&1 \ # RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-RV64-NO-C --implicit-check-not="error:" ## C.JAL is only defined for RV32C: diff --git a/llvm/test/MC/RISCV/cheri/rv32cxcheri-cap-mode-only-valid.s b/llvm/test/MC/RISCV/cheri/rv32cxcheri-cap-mode-only-valid.s index d913558a67f22..2bb91810d672e 100644 --- a/llvm/test/MC/RISCV/cheri/rv32cxcheri-cap-mode-only-valid.s +++ b/llvm/test/MC/RISCV/cheri/rv32cxcheri-cap-mode-only-valid.s @@ -1,7 +1,7 @@ -# RUN: llvm-mc %s -triple=riscv32 -mattr=+c,+xcheri,+cap-mode -riscv-no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+c,+xcheri,+xcheripurecap -riscv-no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c,+xcheri,+cap-mode < %s \ -# RUN: | llvm-objdump --no-print-imm-hex -M no-aliases --mattr=+c,+xcheri,+cap-mode -d - \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c,+xcheri,+xcheripurecap < %s \ +# RUN: | llvm-objdump --no-print-imm-hex -M no-aliases --mattr=+c,+xcheri,+xcheripurecap -d - \ # RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s ## Different encoding between RV64 and RV32 (see rv64cxcheri-cap-mode-only-valid.s) diff --git a/llvm/test/MC/RISCV/cheri/rv32cxcheri-cap-mode-valid.s b/llvm/test/MC/RISCV/cheri/rv32cxcheri-cap-mode-valid.s index 8c350fb5e354d..01187030df72c 100644 --- a/llvm/test/MC/RISCV/cheri/rv32cxcheri-cap-mode-valid.s +++ b/llvm/test/MC/RISCV/cheri/rv32cxcheri-cap-mode-valid.s @@ -1,12 +1,12 @@ -# RUN: llvm-mc %s -triple=riscv32 -mattr=+c,+xcheri,+cap-mode -riscv-no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+c,+xcheri,+xcheripurecap -riscv-no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc %s -triple=riscv64 -mattr=+c,+xcheri,+cap-mode -riscv-no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv64 -mattr=+c,+xcheri,+xcheripurecap -riscv-no-aliases -show-encoding \ # RUN: | FileCheck --check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c,+xcheri,+cap-mode < %s \ -# RUN: | llvm-objdump --no-print-imm-hex -M no-aliases --mattr=+c,+xcheri,+cap-mode -d - \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c,+xcheri,+xcheripurecap < %s \ +# RUN: | llvm-objdump --no-print-imm-hex -M no-aliases --mattr=+c,+xcheri,+xcheripurecap -d - \ # RUN: | FileCheck -check-prefixes=CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+c,+xcheri,+cap-mode < %s \ -# RUN: | llvm-objdump --no-print-imm-hex -M no-aliases --mattr=+c,+xcheri,+cap-mode -d - \ +# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+c,+xcheri,+xcheripurecap < %s \ +# RUN: | llvm-objdump --no-print-imm-hex -M no-aliases --mattr=+c,+xcheri,+xcheripurecap -d - \ # RUN: | FileCheck --check-prefixes=CHECK-ASM-AND-OBJ %s # CHECK-ASM-AND-OBJ: c.clwcsp ra, 0(csp) diff --git a/llvm/test/MC/RISCV/cheri/rv32fdcxcheri-cap-mode-only-valid.s b/llvm/test/MC/RISCV/cheri/rv32fdcxcheri-cap-mode-only-valid.s index 093f9e2919844..572de2f566b6f 100644 --- a/llvm/test/MC/RISCV/cheri/rv32fdcxcheri-cap-mode-only-valid.s +++ b/llvm/test/MC/RISCV/cheri/rv32fdcxcheri-cap-mode-only-valid.s @@ -1,7 +1,7 @@ -# RUN: llvm-mc %s -triple=riscv32 -mattr=+c,+xcheri,+cap-mode,+f,+d -riscv-no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+c,+xcheri,+xcheripurecap,+f,+d -riscv-no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c,+xcheri,+cap-mode,+f,+d < %s \ -# RUN: | llvm-objdump --no-print-imm-hex -M no-aliases --mattr=+c,+xcheri,+cap-mode,+f,+d -d - \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c,+xcheri,+xcheripurecap,+f,+d < %s \ +# RUN: | llvm-objdump --no-print-imm-hex -M no-aliases --mattr=+c,+xcheri,+xcheripurecap,+f,+d -d - \ # RUN: | FileCheck -check-prefixes=CHECK-ASM-AND-OBJ %s ## Floating-point store is only supported in capmode for RV32 diff --git a/llvm/test/MC/RISCV/cheri/rv32fdxcheri-cap-mode-valid.s b/llvm/test/MC/RISCV/cheri/rv32fdxcheri-cap-mode-valid.s index eeae6d549f4c3..72b02b1096fce 100644 --- a/llvm/test/MC/RISCV/cheri/rv32fdxcheri-cap-mode-valid.s +++ b/llvm/test/MC/RISCV/cheri/rv32fdxcheri-cap-mode-valid.s @@ -1,12 +1,12 @@ -# RUN: llvm-mc %s -triple=riscv32 -mattr=+xcheri,+cap-mode,+f,+d -riscv-no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+xcheri,+xcheripurecap,+f,+d -riscv-no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xcheri,+cap-mode,+f,+d < %s \ -# RUN: | llvm-objdump --no-print-imm-hex -M no-aliases --mattr=+xcheri,+cap-mode,+f,+d -d - \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xcheri,+xcheripurecap,+f,+d < %s \ +# RUN: | llvm-objdump --no-print-imm-hex -M no-aliases --mattr=+xcheri,+xcheripurecap,+f,+d -d - \ # RUN: | FileCheck -check-prefixes=CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc %s -triple=riscv64 -mattr=+xcheri,+cap-mode,+f,+d -riscv-no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv64 -mattr=+xcheri,+xcheripurecap,+f,+d -riscv-no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+xcheri,+cap-mode,+f,+d < %s \ -# RUN: | llvm-objdump --no-print-imm-hex -M no-aliases --mattr=+xcheri,+cap-mode,+f,+d -d - \ +# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+xcheri,+xcheripurecap,+f,+d < %s \ +# RUN: | llvm-objdump --no-print-imm-hex -M no-aliases --mattr=+xcheri,+xcheripurecap,+f,+d -d - \ # RUN: | FileCheck -check-prefixes=CHECK-ASM-AND-OBJ %s diff --git a/llvm/test/MC/RISCV/cheri/rv32xcheri-cap-mode-only-valid.s b/llvm/test/MC/RISCV/cheri/rv32xcheri-cap-mode-only-valid.s index 40e27532d5cff..e2912723d73d0 100644 --- a/llvm/test/MC/RISCV/cheri/rv32xcheri-cap-mode-only-valid.s +++ b/llvm/test/MC/RISCV/cheri/rv32xcheri-cap-mode-only-valid.s @@ -1,15 +1,15 @@ -# RUN: llvm-mc -triple=riscv32 -mattr=+xcheri,+cap-mode -riscv-no-aliases -show-encoding < %s \ +# RUN: llvm-mc -triple=riscv32 -mattr=+xcheri,+xcheripurecap -riscv-no-aliases -show-encoding < %s \ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xcheri,+cap-mode < %s \ -# RUN: | llvm-objdump --no-print-imm-hex -M no-aliases --mattr=+xcheri,+cap-mode -d - \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xcheri,+xcheripurecap < %s \ +# RUN: | llvm-objdump --no-print-imm-hex -M no-aliases --mattr=+xcheri,+xcheripurecap -d - \ # RUN: | FileCheck -check-prefixes=CHECK-ASM-AND-OBJ %s ## Same test again without the "c" prefix on all lines # RUN: sed -e 's/^c//' < %s > %t.s -# RUN: llvm-mc -triple=riscv32 -mattr=+xcheri,+cap-mode -riscv-no-aliases -show-encoding < %t.s \ +# RUN: llvm-mc -triple=riscv32 -mattr=+xcheri,+xcheripurecap -riscv-no-aliases -show-encoding < %t.s \ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xcheri,+cap-mode < %t.s \ -# RUN: | llvm-objdump --no-print-imm-hex -M no-aliases --mattr=+xcheri,+cap-mode -d - \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xcheri,+xcheripurecap < %t.s \ +# RUN: | llvm-objdump --no-print-imm-hex -M no-aliases --mattr=+xcheri,+xcheripurecap -d - \ # RUN: | FileCheck -check-prefixes=CHECK-ASM-AND-OBJ %s # Capability load/store uses different encodings for RV32 vs RV64 diff --git a/llvm/test/MC/RISCV/cheri/rv32xcheri-cap-mode-valid.s b/llvm/test/MC/RISCV/cheri/rv32xcheri-cap-mode-valid.s index 54569988debfd..745f724bdd5b9 100644 --- a/llvm/test/MC/RISCV/cheri/rv32xcheri-cap-mode-valid.s +++ b/llvm/test/MC/RISCV/cheri/rv32xcheri-cap-mode-valid.s @@ -1,25 +1,25 @@ -# RUN: llvm-mc -triple=riscv32 -mattr=+xcheri,+cap-mode -riscv-no-aliases -show-encoding < %s \ +# RUN: llvm-mc -triple=riscv32 -mattr=+xcheri,+xcheripurecap -riscv-no-aliases -show-encoding < %s \ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -triple=riscv64 -mattr=+xcheri,+cap-mode -riscv-no-aliases -show-encoding < %s \ +# RUN: llvm-mc -triple=riscv64 -mattr=+xcheri,+xcheripurecap -riscv-no-aliases -show-encoding < %s \ # RUN: | FileCheck --check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xcheri,+cap-mode < %s \ -# RUN: | llvm-objdump --no-print-imm-hex -M no-aliases --mattr=+xcheri,+cap-mode -d - \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xcheri,+xcheripurecap < %s \ +# RUN: | llvm-objdump --no-print-imm-hex -M no-aliases --mattr=+xcheri,+xcheripurecap -d - \ # RUN: | FileCheck -check-prefixes=CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+xcheri,+cap-mode < %s \ -# RUN: | llvm-objdump --no-print-imm-hex -M no-aliases --mattr=+xcheri,+cap-mode -d - \ +# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+xcheri,+xcheripurecap < %s \ +# RUN: | llvm-objdump --no-print-imm-hex -M no-aliases --mattr=+xcheri,+xcheripurecap -d - \ # RUN: | FileCheck --check-prefixes=CHECK-ASM-AND-OBJ %s ## Same test again without the "c" prefix on all lines # RUN: sed -e 's/^c//' < %s > %t.s -# RUN: llvm-mc -triple=riscv32 -mattr=+xcheri,+cap-mode -riscv-no-aliases -show-encoding < %t.s \ +# RUN: llvm-mc -triple=riscv32 -mattr=+xcheri,+xcheripurecap -riscv-no-aliases -show-encoding < %t.s \ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -triple=riscv64 -mattr=+xcheri,+cap-mode -riscv-no-aliases -show-encoding < %t.s \ +# RUN: llvm-mc -triple=riscv64 -mattr=+xcheri,+xcheripurecap -riscv-no-aliases -show-encoding < %t.s \ # RUN: | FileCheck --check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xcheri,+cap-mode < %t.s \ -# RUN: | llvm-objdump --no-print-imm-hex -M no-aliases --mattr=+xcheri,+cap-mode -d - \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xcheri,+xcheripurecap < %t.s \ +# RUN: | llvm-objdump --no-print-imm-hex -M no-aliases --mattr=+xcheri,+xcheripurecap -d - \ # RUN: | FileCheck -check-prefixes=CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+xcheri,+cap-mode < %t.s \ -# RUN: | llvm-objdump --no-print-imm-hex -M no-aliases --mattr=+xcheri,+cap-mode -d - \ +# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+xcheri,+xcheripurecap < %t.s \ +# RUN: | llvm-objdump --no-print-imm-hex -M no-aliases --mattr=+xcheri,+xcheripurecap -d - \ # RUN: | FileCheck --check-prefixes=CHECK-ASM-AND-OBJ %s # CHECK-ASM-AND-OBJ: clb a2, 17(ca0) diff --git a/llvm/test/MC/RISCV/cheri/rv64axcheri-cap-mode-aliases-valid.s b/llvm/test/MC/RISCV/cheri/rv64axcheri-cap-mode-aliases-valid.s index 6f9817e60c89d..509ce74fb3218 100644 --- a/llvm/test/MC/RISCV/cheri/rv64axcheri-cap-mode-aliases-valid.s +++ b/llvm/test/MC/RISCV/cheri/rv64axcheri-cap-mode-aliases-valid.s @@ -1,12 +1,12 @@ -# RUN: llvm-mc %s -triple=riscv64 -mattr=+a,+xcheri,+cap-mode -riscv-no-aliases \ +# RUN: llvm-mc %s -triple=riscv64 -mattr=+a,+xcheri,+xcheripurecap -riscv-no-aliases \ # RUN: | FileCheck -check-prefix=CHECK-INST %s -# RUN: llvm-mc %s -triple=riscv64 -mattr=+a,+xcheri,+cap-mode \ +# RUN: llvm-mc %s -triple=riscv64 -mattr=+a,+xcheri,+xcheripurecap \ # RUN: | FileCheck -check-prefix=CHECK-ALIAS %s -# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+a,+xcheri,+cap-mode < %s \ -# RUN: | llvm-objdump -d --mattr=+a,+xcheri,+cap-mode -M no-aliases - \ +# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+a,+xcheri,+xcheripurecap < %s \ +# RUN: | llvm-objdump -d --mattr=+a,+xcheri,+xcheripurecap -M no-aliases - \ # RUN: | FileCheck -check-prefix=CHECK-INST %s -# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+a,+xcheri,+cap-mode < %s \ -# RUN: | llvm-objdump -d --mattr=+a,+xcheri,+cap-mode - \ +# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+a,+xcheri,+xcheripurecap < %s \ +# RUN: | llvm-objdump -d --mattr=+a,+xcheri,+xcheripurecap - \ # RUN: | FileCheck -check-prefix=CHECK-ALIAS %s # The below tests for clr.d, csc.d and camo*.d, using `0(reg)` are actually diff --git a/llvm/test/MC/RISCV/cheri/rv64axcheri-cap-mode-invalid.s b/llvm/test/MC/RISCV/cheri/rv64axcheri-cap-mode-invalid.s index 731fdc5c5ff09..e53e57cf8f3d1 100644 --- a/llvm/test/MC/RISCV/cheri/rv64axcheri-cap-mode-invalid.s +++ b/llvm/test/MC/RISCV/cheri/rv64axcheri-cap-mode-invalid.s @@ -1,4 +1,4 @@ -# RUN: not llvm-mc -triple riscv64 -mattr=+a,+xcheri,+cap-mode < %s 2>&1 | FileCheck %s +# RUN: not llvm-mc -triple riscv64 -mattr=+a,+xcheri,+xcheripurecap < %s 2>&1 | FileCheck %s # Final operand must have parentheses camoswap.d a1, a2, ca3 # CHECK: :[[@LINE]]:20: error: expected '(' or optional integer offset diff --git a/llvm/test/MC/RISCV/cheri/rv64axcheri-cap-mode-valid.s b/llvm/test/MC/RISCV/cheri/rv64axcheri-cap-mode-valid.s index b61bbd13516e5..ebd7badb35b52 100644 --- a/llvm/test/MC/RISCV/cheri/rv64axcheri-cap-mode-valid.s +++ b/llvm/test/MC/RISCV/cheri/rv64axcheri-cap-mode-valid.s @@ -1,15 +1,15 @@ -# RUN: llvm-mc -triple=riscv64 -mattr=+a,+xcheri,+cap-mode -riscv-no-aliases -show-encoding < %s \ +# RUN: llvm-mc -triple=riscv64 -mattr=+a,+xcheri,+xcheripurecap -riscv-no-aliases -show-encoding < %s \ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+a,+xcheri,+cap-mode < %s \ -# RUN: | llvm-objdump --mattr=+a,+xcheri,+cap-mode -M no-aliases -d -r - \ +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+a,+xcheri,+xcheripurecap < %s \ +# RUN: | llvm-objdump --mattr=+a,+xcheri,+xcheripurecap -M no-aliases -d -r - \ # RUN: | FileCheck -check-prefixes=CHECK-ASM-AND-OBJ %s ## Same test again without the "c" prefix on all lines # RUN: sed -e 's/^c//' < %s > %t.s -# RUN: llvm-mc -triple=riscv64 -mattr=+a,+xcheri,+cap-mode -riscv-no-aliases -show-encoding < %t.s \ +# RUN: llvm-mc -triple=riscv64 -mattr=+a,+xcheri,+xcheripurecap -riscv-no-aliases -show-encoding < %t.s \ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+a,+xcheri,+cap-mode < %t.s \ -# RUN: | llvm-objdump --mattr=+a,+xcheri,+cap-mode -M no-aliases -d -r - \ +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+a,+xcheri,+xcheripurecap < %t.s \ +# RUN: | llvm-objdump --mattr=+a,+xcheri,+xcheripurecap -M no-aliases -d -r - \ # RUN: | FileCheck -check-prefixes=CHECK-ASM-AND-OBJ %s diff --git a/llvm/test/MC/RISCV/cheri/rv64cxcheri-cap-mode-invalid.s b/llvm/test/MC/RISCV/cheri/rv64cxcheri-cap-mode-invalid.s index 16b6f957e2549..731aee789b8ba 100644 --- a/llvm/test/MC/RISCV/cheri/rv64cxcheri-cap-mode-invalid.s +++ b/llvm/test/MC/RISCV/cheri/rv64cxcheri-cap-mode-invalid.s @@ -1,8 +1,8 @@ -# RUN: not llvm-mc -triple riscv64 -mattr=+c,+xcheri,+cap-mode -filetype=null -riscv-no-aliases -show-encoding < %s 2>&1\ +# RUN: not llvm-mc -triple riscv64 -mattr=+c,+xcheri,+xcheripurecap -filetype=null -riscv-no-aliases -show-encoding < %s 2>&1\ # RUN: | FileCheck %s --check-prefixes=CHECK-RV64 --implicit-check-not="error:" -# RUN: not llvm-mc -triple riscv64 -mattr=+xcheri,+cap-mode -filetype=null -riscv-no-aliases -show-encoding < %s 2>&1 \ +# RUN: not llvm-mc -triple riscv64 -mattr=+xcheri,+xcheripurecap -filetype=null -riscv-no-aliases -show-encoding < %s 2>&1 \ # RUN: | FileCheck %s --check-prefixes=CHECK-RV64-NO-C --implicit-check-not="error:" -# RUN: not llvm-mc -triple riscv32 -mattr=+c,+xcheri,+cap-mode -filetype=null -riscv-no-aliases -show-encoding < %s 2>&1 \ +# RUN: not llvm-mc -triple riscv32 -mattr=+c,+xcheri,+xcheripurecap -filetype=null -riscv-no-aliases -show-encoding < %s 2>&1 \ # RUN: | FileCheck %s --check-prefixes=CHECK-RV32 --implicit-check-not="error:" ## Invalid immediates diff --git a/llvm/test/MC/RISCV/cheri/rv64cxcheri-cap-mode-only-valid.s b/llvm/test/MC/RISCV/cheri/rv64cxcheri-cap-mode-only-valid.s index 5956603d3b655..c10f669dc8d78 100644 --- a/llvm/test/MC/RISCV/cheri/rv64cxcheri-cap-mode-only-valid.s +++ b/llvm/test/MC/RISCV/cheri/rv64cxcheri-cap-mode-only-valid.s @@ -1,7 +1,7 @@ -# RUN: llvm-mc %s -triple=riscv64 -mattr=+c,+xcheri,+cap-mode -riscv-no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv64 -mattr=+c,+xcheri,+xcheripurecap -riscv-no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+c,+xcheri,+cap-mode < %s \ -# RUN: | llvm-objdump --no-print-imm-hex -M no-aliases --mattr=+c,+xcheri,+cap-mode -d - \ +# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+c,+xcheri,+xcheripurecap < %s \ +# RUN: | llvm-objdump --no-print-imm-hex -M no-aliases --mattr=+c,+xcheri,+xcheripurecap -d - \ # RUN: | FileCheck -check-prefixes=CHECK-ASM-AND-OBJ %s ## Different encoding between RV64 and RV32 (see rv32cxcheri-cap-mode-only-valid.s) diff --git a/llvm/test/MC/RISCV/cheri/rv64xcheri-cap-mode-only-valid.s b/llvm/test/MC/RISCV/cheri/rv64xcheri-cap-mode-only-valid.s index ab4a81272ce58..2e51167f7454b 100644 --- a/llvm/test/MC/RISCV/cheri/rv64xcheri-cap-mode-only-valid.s +++ b/llvm/test/MC/RISCV/cheri/rv64xcheri-cap-mode-only-valid.s @@ -1,15 +1,15 @@ -# RUN: llvm-mc -triple=riscv64 -mattr=+xcheri,+cap-mode -riscv-no-aliases -show-encoding < %s\ +# RUN: llvm-mc -triple=riscv64 -mattr=+xcheri,+xcheripurecap -riscv-no-aliases -show-encoding < %s\ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+xcheri,+cap-mode < %s \ -# RUN: | llvm-objdump --no-print-imm-hex -M no-aliases --mattr=+xcheri,+cap-mode -d - \ +# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+xcheri,+xcheripurecap < %s \ +# RUN: | llvm-objdump --no-print-imm-hex -M no-aliases --mattr=+xcheri,+xcheripurecap -d - \ # RUN: | FileCheck -check-prefixes=CHECK-ASM-AND-OBJ %s ## Same test again without the "c" prefix on all lines # RUN: sed -e 's/^c//' < %s > %t.s -# RUN: llvm-mc -triple=riscv64 -mattr=+xcheri,+cap-mode -riscv-no-aliases -show-encoding < %t.s\ +# RUN: llvm-mc -triple=riscv64 -mattr=+xcheri,+xcheripurecap -riscv-no-aliases -show-encoding < %t.s\ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+xcheri,+cap-mode < %t.s \ -# RUN: | llvm-objdump --no-print-imm-hex -M no-aliases --mattr=+xcheri,+cap-mode -d - \ +# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+xcheri,+xcheripurecap < %t.s \ +# RUN: | llvm-objdump --no-print-imm-hex -M no-aliases --mattr=+xcheri,+xcheripurecap -d - \ # RUN: | FileCheck -check-prefixes=CHECK-ASM-AND-OBJ %s # Capability load/store uses different encodings for RV32 vs RV64 diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp index 0d83ab44c68c7..5134d3e3501d2 100644 --- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp +++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp @@ -1078,6 +1078,7 @@ R"(All available -march extensions for RISC-V svvptc 1.0 xcheri 0.0 xcheriot 1.0 + xcheripurecap 0.0 xcvalu 1.0 xcvbi 1.0 xcvbitmanip 1.0 diff --git a/llvm/utils/lit/lit/llvm/config.py b/llvm/utils/lit/lit/llvm/config.py index 133117e7e79c4..b36cb9029697e 100644 --- a/llvm/utils/lit/lit/llvm/config.py +++ b/llvm/utils/lit/lit/llvm/config.py @@ -485,8 +485,8 @@ def _add_cheri_tool_substitution(self, tool): cheri128_args = [triple_opt + '=mips64-unknown-freebsd', '-mcpu=cheri128', '-mattr=+cheri128'] + extra_args riscv32_cheri_args = [triple_opt + '=riscv32-unknown-freebsd', '-mattr=+xcheri'] + extra_args riscv64_cheri_args = [triple_opt + '=riscv64-unknown-freebsd', '-mattr=+xcheri'] + extra_args - riscv32_cheri_purecap_args = ['-target-abi', 'il32pc64d', '-mattr=+cap-mode'] + riscv32_cheri_args - riscv64_cheri_purecap_args = ['-target-abi', 'l64pc128d', '-mattr=+cap-mode'] + riscv64_cheri_args + riscv32_cheri_purecap_args = ['-target-abi', 'il32pc64d', '-mattr=+xcheripurecap'] + riscv32_cheri_args + riscv64_cheri_purecap_args = ['-target-abi', 'l64pc128d', '-mattr=+xcheripurecap'] + riscv64_cheri_args default_args = cheri128_args tool_patterns = [ @@ -676,8 +676,8 @@ def use_clang( ToolSubst('%cheri_clang', command=self.config.clang, extra_args=cheri_clang_args+additional_flags), ToolSubst('%cheri_purecap_clang', command=self.config.clang, extra_args=cheri_clang_args + ['-mabi=purecap']+additional_flags), - ToolSubst('%riscv32_cheri_purecap_cc1', command='%riscv32_cheri_cc1', extra_args=['-target-abi', 'il32pc64', '-target-feature', '+cap-mode']+additional_flags), - ToolSubst('%riscv64_cheri_purecap_cc1', command='%riscv64_cheri_cc1', extra_args=['-target-abi', 'l64pc128', '-target-feature', '+cap-mode']+additional_flags), + ToolSubst('%riscv32_cheri_purecap_cc1', command='%riscv32_cheri_cc1', extra_args=['-target-abi', 'il32pc64', '-target-feature', '+xcheripurecap']+additional_flags), + ToolSubst('%riscv64_cheri_purecap_cc1', command='%riscv64_cheri_cc1', extra_args=['-target-abi', 'l64pc128', '-target-feature', '+xcheripurecap']+additional_flags), ToolSubst('%riscv32_cheri_purecap_clang', command='%riscv32_cheri_clang', extra_args=['-mabi=il32pc64']+additional_flags), ToolSubst('%riscv64_cheri_purecap_clang', command='%riscv64_cheri_clang', extra_args=['-mabi=l64pc128']+additional_flags), ToolSubst('%riscv32_cheri_cc1', command=self.config.clang, extra_args=riscv32_cheri_cc1_args+additional_flags), diff --git a/llvm/utils/update_cc_test_checks.py b/llvm/utils/update_cc_test_checks.py index 05dd2772eb61a..5cca06bd60ca3 100755 --- a/llvm/utils/update_cc_test_checks.py +++ b/llvm/utils/update_cc_test_checks.py @@ -41,8 +41,8 @@ '%riscv64_cheri_cc1': ['-cc1', "-triple=riscv64-unknown-freebsd", "-target-feature", "+xcheri"], '%riscv32_cheri_clang': ['-target', 'riscv32-unknown-freebsd', '-march=rv32imafdcxcheri'], '%riscv64_cheri_clang': ['-target', 'riscv64-unknown-freebsd', '-march=rv64imafdcxcheri'], - '%riscv32_cheri_purecap_cc1': ['-cc1', "-triple=riscv32-unknown-freebsd", "-target-feature", "+xcheri", "-target-abi", "il32pc64", '-target-feature', '+cap-mode'], - '%riscv64_cheri_purecap_cc1': ['-cc1', "-triple=riscv64-unknown-freebsd", "-target-feature", "+xcheri", "-target-abi", "l64pc128", '-target-feature', '+cap-mode'], + '%riscv32_cheri_purecap_cc1': ['-cc1', "-triple=riscv32-unknown-freebsd", "-target-feature", "+xcheri", "-target-abi", "il32pc64", '-target-feature', '+xcheripurecap'], + '%riscv64_cheri_purecap_cc1': ['-cc1', "-triple=riscv64-unknown-freebsd", "-target-feature", "+xcheri", "-target-abi", "l64pc128", '-target-feature', '+xcheripurecap'], '%riscv32_cheri_purecap_clang': ['-target', 'riscv32-unknown-freebsd', '-march=rv32imafdcxcheri', '-mabi=il32pc64'], '%riscv64_cheri_purecap_clang': ['-target', 'riscv64-unknown-freebsd', '-march=rv64imafdcxcheri', '-mabi=l64pc128'], } diff --git a/llvm/utils/update_llc_test_checks.py b/llvm/utils/update_llc_test_checks.py index 4aac65e280668..f7768805d5982 100755 --- a/llvm/utils/update_llc_test_checks.py +++ b/llvm/utils/update_llc_test_checks.py @@ -101,8 +101,8 @@ def main(): preprocess_cmd = preprocess_cmd.replace("%cheri128_purecap_opt", "opt -mtriple=mips64-unknown-freebsd -target-abi purecap -relocation-model pic -mcpu=cheri128 -mattr=+cheri128") preprocess_cmd = preprocess_cmd.replace("%cheri_opt", "opt -mtriple=mips64-unknown-freebsd -mcpu=cheri128 -mattr=+cheri128") preprocess_cmd = preprocess_cmd.replace("%cheri128_opt", "opt -mtriple=mips64-unknown-freebsd -mcpu=cheri128 -mattr=+cheri128") - preprocess_cmd = preprocess_cmd.replace("%riscv32_cheri_purecap_opt", "opt -mtriple=riscv32-unknown-freebsd -target-abi il32pc64d -mattr=+xcheri,+cap-mode") - preprocess_cmd = preprocess_cmd.replace("%riscv64_cheri_purecap_opt", "opt -mtriple=riscv64-unknown-freebsd -target-abi l64pc128d -mattr=+xcheri,+cap-mode") + preprocess_cmd = preprocess_cmd.replace("%riscv32_cheri_purecap_opt", "opt -mtriple=riscv32-unknown-freebsd -target-abi il32pc64d -mattr=+xcheri,+xcheripurecap") + preprocess_cmd = preprocess_cmd.replace("%riscv64_cheri_purecap_opt", "opt -mtriple=riscv64-unknown-freebsd -target-abi l64pc128d -mattr=+xcheri,+xcheripurecap") preprocess_cmd = preprocess_cmd.replace("%riscv32_cheri_opt", "opt -mtriple=riscv32-unknown-freebsd -mattr=+xcheri") preprocess_cmd = preprocess_cmd.replace("%riscv64_cheri_opt", "opt -mtriple=riscv64-unknown-freebsd -mattr=+xcheri") preprocess_cmd_list = preprocess_cmd.split() @@ -114,8 +114,8 @@ def main(): llc_cmd = llc_cmd.replace("%cheri128_purecap_llc", "llc -mtriple=mips64-unknown-freebsd -target-abi purecap -relocation-model pic -mcpu=cheri128 -mattr=+cheri128") llc_cmd = llc_cmd.replace("%cheri_llc", "llc -mtriple=mips64-unknown-freebsd -mcpu=cheri128 -mattr=+cheri128") llc_cmd = llc_cmd.replace("%cheri128_llc", "llc -mtriple=mips64-unknown-freebsd -mcpu=cheri128 -mattr=+cheri128") - llc_cmd = llc_cmd.replace("%riscv32_cheri_purecap_llc", "llc -mtriple=riscv32-unknown-freebsd -target-abi il32pc64d -mattr=+xcheri,+cap-mode") - llc_cmd = llc_cmd.replace("%riscv64_cheri_purecap_llc", "llc -mtriple=riscv64-unknown-freebsd -target-abi l64pc128d -mattr=+xcheri,+cap-mode") + llc_cmd = llc_cmd.replace("%riscv32_cheri_purecap_llc", "llc -mtriple=riscv32-unknown-freebsd -target-abi il32pc64d -mattr=+xcheri,+xcheripurecap") + llc_cmd = llc_cmd.replace("%riscv64_cheri_purecap_llc", "llc -mtriple=riscv64-unknown-freebsd -target-abi l64pc128d -mattr=+xcheri,+xcheripurecap") llc_cmd = llc_cmd.replace("%riscv32_cheri_llc", "llc -mtriple=riscv32-unknown-freebsd -mattr=+xcheri") llc_cmd = llc_cmd.replace("%riscv64_cheri_llc", "llc -mtriple=riscv64-unknown-freebsd -mattr=+xcheri") filecheck_cmd = commands[-1] diff --git a/llvm/utils/update_mir_test_checks.py b/llvm/utils/update_mir_test_checks.py index 617ea6cfaf6cb..b13772d07cb8a 100755 --- a/llvm/utils/update_mir_test_checks.py +++ b/llvm/utils/update_mir_test_checks.py @@ -127,8 +127,8 @@ def build_run_list(test, run_lines, verbose=False): llc_cmd = llc_cmd.replace("%cheri128_purecap_llc", "llc -mtriple=mips64-unknown-freebsd -target-abi purecap -relocation-model pic -mcpu=cheri128 -mattr=+cheri128") llc_cmd = llc_cmd.replace("%cheri_llc", "llc -mtriple=mips64-unknown-freebsd -mcpu=cheri128 -mattr=+cheri128") llc_cmd = llc_cmd.replace("%cheri128_llc", "llc -mtriple=mips64-unknown-freebsd -mcpu=cheri128 -mattr=+cheri128") - llc_cmd = llc_cmd.replace("%riscv32_cheri_purecap_llc", "llc -mtriple=riscv32-unknown-freebsd -target-abi il32pc64 -mattr=+xcheri,+cap-mode") - llc_cmd = llc_cmd.replace("%riscv64_cheri_purecap_llc", "llc -mtriple=riscv64-unknown-freebsd -target-abi l64pc128 -mattr=+xcheri,+cap-mode") + llc_cmd = llc_cmd.replace("%riscv32_cheri_purecap_llc", "llc -mtriple=riscv32-unknown-freebsd -target-abi il32pc64 -mattr=+xcheri,+xcheripurecap") + llc_cmd = llc_cmd.replace("%riscv64_cheri_purecap_llc", "llc -mtriple=riscv64-unknown-freebsd -target-abi l64pc128 -mattr=+xcheri,+xcheripurecap") llc_cmd = llc_cmd.replace("%riscv32_cheri_llc", "llc -mtriple=riscv32-unknown-freebsd -mattr=+xcheri") llc_cmd = llc_cmd.replace("%riscv64_cheri_llc", "llc -mtriple=riscv64-unknown-freebsd -mattr=+xcheri") diff --git a/llvm/utils/update_test_checks.py b/llvm/utils/update_test_checks.py index 53a899f2a2e81..ada830d013622 100755 --- a/llvm/utils/update_test_checks.py +++ b/llvm/utils/update_test_checks.py @@ -141,8 +141,8 @@ def main(): tool_cmd = tool_cmd.replace("%cheri128_purecap_opt", "opt -mtriple=mips64-unknown-freebsd -target-abi purecap -relocation-model pic -mcpu=cheri128 -mattr=+cheri128") tool_cmd = tool_cmd.replace("%cheri_opt", "opt -mtriple=mips64-unknown-freebsd -mcpu=cheri128 -mattr=+cheri128") tool_cmd = tool_cmd.replace("%cheri128_opt", "opt -mtriple=mips64-unknown-freebsd -mcpu=cheri128 -mattr=+cheri128") - tool_cmd = tool_cmd.replace("%riscv32_cheri_purecap_opt", "opt -mtriple=riscv32-unknown-freebsd -target-abi il32pc64 -mattr=+xcheri,+cap-mode") - tool_cmd = tool_cmd.replace("%riscv64_cheri_purecap_opt", "opt -mtriple=riscv64-unknown-freebsd -target-abi l64pc128 -mattr=+xcheri,+cap-mode") + tool_cmd = tool_cmd.replace("%riscv32_cheri_purecap_opt", "opt -mtriple=riscv32-unknown-freebsd -target-abi il32pc64 -mattr=+xcheri,+xcheripurecap") + tool_cmd = tool_cmd.replace("%riscv64_cheri_purecap_opt", "opt -mtriple=riscv64-unknown-freebsd -target-abi l64pc128 -mattr=+xcheri,+xcheripurecap") tool_cmd = tool_cmd.replace("%riscv32_cheri_opt", "opt -mtriple=riscv32-unknown-freebsd -mattr=+xcheri") tool_cmd = tool_cmd.replace("%riscv64_cheri_opt", "opt -mtriple=riscv64-unknown-freebsd -mattr=+xcheri")