From ba4fb19e4c418c2c6ddb37127f499722715c9d78 Mon Sep 17 00:00:00 2001
From: Owen Anderson <resistor@mac.com>
Date: Thu, 2 Oct 2025 23:10:28 +0900
Subject: [PATCH] [CHERI] Integrate the RISCV Y version of the CHERI register
 file.

---
 .../CodeGen/cheri/cheri-hybrid-ptr-to-cap.c   |    20 +-
 .../CodeGen/cheri/cheri-mcu-atomic-libcall.c  |     6 +-
 .../ELF/cheri/riscv/cheriot_compartment_hi.s  |     8 +-
 .../cheri/riscv/cheriot_compartment_lo_i.s    |    32 +-
 lld/test/ELF/cheri/riscv/plt.s                |    32 +-
 lld/test/ELF/cheri/riscv/tls.s                |    84 +-
 .../Target/RISCV/AsmParser/RISCVAsmParser.cpp |    22 +-
 .../RISCV/Disassembler/RISCVDisassembler.cpp  |    22 +-
 .../RISCV/MCTargetDesc/RISCVBaseInfo.cpp      |     2 +-
 .../RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp |     8 +-
 .../RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp  |     4 +-
 llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp     |    10 +-
 llvm/lib/Target/RISCV/RISCVCallingConv.cpp    |    53 +-
 llvm/lib/Target/RISCV/RISCVCallingConv.h      |     2 +-
 llvm/lib/Target/RISCV/RISCVCallingConv.td     |    80 +-
 llvm/lib/Target/RISCV/RISCVCheriCleanup.cpp   |     2 +-
 .../Target/RISCV/RISCVExpandPseudoInsts.cpp   |    18 +-
 llvm/lib/Target/RISCV/RISCVFrameLowering.cpp  |    14 +-
 llvm/lib/Target/RISCV/RISCVISelLowering.cpp   |   157 +-
 llvm/lib/Target/RISCV/RISCVInstrInfo.cpp      |    46 +-
 llvm/lib/Target/RISCV/RISCVInstrInfoXCheri.td |  1940 +--
 llvm/lib/Target/RISCV/RISCVInstrPredicates.td |     4 +-
 llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp   |    27 +-
 llvm/lib/Target/RISCV/RISCVRegisterInfo.td    |   197 +-
 .../RISCV32/atomic-rmw-cap-ptr-arg.ll         |   778 +-
 .../RISCV32/atomic-rmw-cap-ptr.ll             |   344 +-
 .../RISCV32/bounded-allocas-lifetimes.ll      |    34 +-
 .../CHERI-Generic/RISCV32/cap-from-ptr.ll     |    68 +-
 ...insics-folding-broken-module-regression.ll |    16 +-
 .../CHERI-Generic/RISCV32/cheri-memfn-call.ll |    24 +-
 .../RISCV32/cheri-pointer-comparison.ll       |    80 +-
 .../CHERI-Generic/RISCV32/cmpxchg-cap-ptr.ll  |   320 +-
 .../dagcombine-ptradd-deleted-regression.ll   |    18 +-
 .../CHERI-Generic/RISCV32/frameindex-arith.ll |    12 +-
 .../gvn-capability-store-to-load-fwd.ll       |    28 +-
 .../CHERI-Generic/RISCV32/hoist-alloca.ll     |   104 +-
 .../RISCV32/intrinsics-purecap-only.ll        |     2 +-
 .../CHERI-Generic/RISCV32/intrinsics.ll       |   144 +-
 .../RISCV32/landingpad-non-preemptible.ll     |    12 +-
 .../RISCV32/machinelicm-hoist-csetbounds.ll   |    40 +-
 .../RISCV32/memcpy-from-constant.ll           |    52 +-
 .../RISCV32/memcpy-no-preserve-tags-attr.ll   |    64 +-
 .../memcpy-preserve-tags-assume-aligned.ll    |    32 +-
 .../memcpy-preserve-tags-size-not-multiple.ll |    70 +-
 .../CHERI-Generic/RISCV32/memcpy-zeroinit.ll  |    40 +-
 .../optsize-preserve-tags-memcpy-crash.ll     |   114 +-
 .../CodeGen/CHERI-Generic/RISCV32/ptrtoint.ll |    12 +-
 .../RISCV32/purecap-jumptable.ll              |    30 +-
 .../RISCV32/setoffset-multiple-uses.ll        |    44 +-
 .../RISCV32/stack-bounds-dynamic-alloca.ll    |   164 +-
 .../stack-bounds-opaque-spill-too-early.ll    |    22 +-
 .../RISCV32/stack-bounds-pass-phi.ll          |   116 +-
 .../RISCV32/stack-spill-unnecessary.c.ll      |    82 +-
 .../RISCV32/stackframe-intrinsics.ll          |    26 +-
 .../RISCV32/strcpy-to-memcpy-no-tags.ll       |    64 +-
 .../subobject-bounds-redundant-setbounds.c.ll |    88 +-
 .../CHERI-Generic/RISCV32/trunc-load.ll       |    32 +-
 .../RISCV32/unaligned-loads-stores-hybrid.ll  |   160 +-
 .../RISCV32/unaligned-loads-stores-purecap.ll |    96 +-
 .../RISCV64/atomic-rmw-cap-ptr-arg.ll         |   778 +-
 .../RISCV64/atomic-rmw-cap-ptr.ll             |   344 +-
 .../RISCV64/bounded-allocas-lifetimes.ll      |    34 +-
 .../CHERI-Generic/RISCV64/cap-from-ptr.ll     |    68 +-
 ...insics-folding-broken-module-regression.ll |    16 +-
 .../CHERI-Generic/RISCV64/cheri-memfn-call.ll |    24 +-
 .../RISCV64/cheri-pointer-comparison.ll       |    80 +-
 .../CHERI-Generic/RISCV64/cmpxchg-cap-ptr.ll  |   280 +-
 .../dagcombine-ptradd-deleted-regression.ll   |    16 +-
 .../CHERI-Generic/RISCV64/frameindex-arith.ll |    12 +-
 .../gvn-capability-store-to-load-fwd.ll       |    32 +-
 .../CHERI-Generic/RISCV64/hoist-alloca.ll     |    84 +-
 .../RISCV64/intrinsics-purecap-only.ll        |     2 +-
 .../CHERI-Generic/RISCV64/intrinsics.ll       |   144 +-
 .../RISCV64/landingpad-non-preemptible.ll     |    12 +-
 .../RISCV64/machinelicm-hoist-csetbounds.ll   |    40 +-
 .../RISCV64/memcpy-from-constant.ll           |    52 +-
 .../RISCV64/memcpy-no-preserve-tags-attr.ll   |    48 +-
 .../memcpy-preserve-tags-assume-aligned.ll    |    16 +-
 .../memcpy-preserve-tags-size-not-multiple.ll |    54 +-
 .../CHERI-Generic/RISCV64/memcpy-zeroinit.ll  |    22 +-
 .../optsize-preserve-tags-memcpy-crash.ll     |    98 +-
 .../CodeGen/CHERI-Generic/RISCV64/ptrtoint.ll |    12 +-
 .../RISCV64/purecap-jumptable.ll              |    30 +-
 .../RISCV64/setoffset-multiple-uses.ll        |    44 +-
 .../RISCV64/stack-bounds-dynamic-alloca.ll    |   156 +-
 .../stack-bounds-opaque-spill-too-early.ll    |    22 +-
 .../RISCV64/stack-bounds-pass-phi.ll          |    58 +-
 .../RISCV64/stack-spill-unnecessary.c.ll      |    82 +-
 .../RISCV64/stackframe-intrinsics.ll          |    26 +-
 .../RISCV64/strcpy-to-memcpy-no-tags.ll       |    92 +-
 .../subobject-bounds-redundant-setbounds.c.ll |    88 +-
 .../CHERI-Generic/RISCV64/trunc-load.ll       |    34 +-
 .../RISCV64/unaligned-loads-stores-hybrid.ll  |   152 +-
 .../RISCV64/unaligned-loads-stores-purecap.ll |    94 +-
 .../CodeGen/CHERI-Generic/byval-buffer.ll     |    28 +-
 .../CodeGen/CHERI-Generic/byval-varargs.ll    |    74 +-
 .../RISCV/cheri/atomic-cmpxchg-hybrid.ll      |   120 +-
 .../CodeGen/RISCV/cheri/atomic-cmpxchg.ll     |  1940 +--
 .../CodeGen/RISCV/cheri/atomic-load-store.ll  |   688 +-
 .../RISCV/cheri/atomic-load-store32.ll        |    80 +-
 .../RISCV/cheri/atomic-load-store64.ll        |   688 +-
 .../CodeGen/RISCV/cheri/atomic-rmw-hybrid.ll  |    20 +-
 llvm/test/CodeGen/RISCV/cheri/atomic-rmw.ll   | 12060 ++++++++--------
 llvm/test/CodeGen/RISCV/cheri/base-pointer.ll |    80 +-
 .../CodeGen/RISCV/cheri/branch-relaxation.ll  |     6 +-
 .../RISCV/cheri/calling-conv-common.ll        |    48 +-
 .../RISCV/cheri/calling-conv-il32pc64.ll      |    52 +-
 .../RISCV/cheri/calling-conv-l64pc128.ll      |    54 +-
 .../RISCV/cheri/cheri-mcu-call-ccallee.ll     |     4 +-
 .../RISCV/cheri/cheri-mcu-call-libcall.ll     |    12 +-
 .../CodeGen/RISCV/cheri/cheri-mcu-ccall.ll    |    22 +-
 .../RISCV/cheri/cheri-mcu-ccallback.ll        |    24 +-
 .../RISCV/cheri/cheri-mcu-define-libcall.ll   |     2 +-
 .../cheri/cheri-mcu-exported-interrupts.ll    |     6 +-
 .../CodeGen/RISCV/cheri/cheri-mcu-fnptr.ll    |     4 +-
 .../cheri/cheriot-check-arg-permissions.ll    |    14 +-
 .../RISCV/cheri/cheriot-csetboundsexact.ll    |     6 +-
 .../cheri/cheriot-csetboundsrounddown.ll      |     2 +-
 .../CodeGen/RISCV/cheri/cheriot-f64-abi.ll    |   324 +-
 .../RISCV/cheri/cheriot-frame-checks.ll       |    20 +-
 .../CodeGen/RISCV/cheri/cheriot-globals.ll    |     2 +-
 .../RISCV/cheri/cheriot-jump-table-address.ll |    26 +-
 .../CodeGen/RISCV/cheri/cheriot-jumptable.ll  |    24 +-
 .../RISCV/cheri/cheriot-load-store-relocs.ll  |    33 +-
 .../CodeGen/RISCV/cheri/cheriot-offset-get.ll |     2 +-
 .../RISCV/cheri/cheriot-sealed-attr.ll        |    14 +-
 .../RISCV/cheri/cheriot-sealing-key-attr.ll   |    20 +-
 .../RISCV/cheri/cheriot-stack-size-export.ll  |     6 +-
 .../CodeGen/RISCV/cheri/cheriot-struct-ret.ll |   312 +-
 .../cheri/cheriot-variadic-double-align.ll    |     8 +-
 .../CodeGen/RISCV/cheri/cheriot-zero-sret.ll  |    10 +-
 llvm/test/CodeGen/RISCV/cheri/compress.ll     |    96 +-
 llvm/test/CodeGen/RISCV/cheri/double-imm.ll   |     6 +-
 llvm/test/CodeGen/RISCV/cheri/double-mem.ll   |   228 +-
 llvm/test/CodeGen/RISCV/cheri/float-mem.ll    |    88 +-
 .../RISCV/cheri/frameaddr-returnaddr.ll       |   292 +-
 .../CodeGen/RISCV/cheri/get-global-addr.ll    |    70 +-
 .../cheri/global-cap-import-attributes.ll     |    98 +-
 .../CodeGen/RISCV/cheri/hoist-setbounds.mir   |   134 +-
 llvm/test/CodeGen/RISCV/cheri/indirectbr.ll   |    40 +-
 .../CodeGen/RISCV/cheri/isav9-cap-from-ptr.ll |    18 +-
 .../CodeGen/RISCV/cheri/isav9-cap-to-ptr.ll   |     8 +-
 .../CodeGen/RISCV/cheri/isav9-inttoptr.ll     |    44 +-
 .../CodeGen/RISCV/cheri/isav9-ptrtoint.ll     |    12 +-
 llvm/test/CodeGen/RISCV/cheri/landing-pad.ll  |    16 +-
 llvm/test/CodeGen/RISCV/cheri/large-frame.ll  |    46 +-
 .../cheri/load-imm-from-constant-pool.ll      |     6 +-
 .../test/CodeGen/RISCV/cheri/lower-ptrmask.ll |     8 +-
 .../CodeGen/RISCV/cheri/machine-outliner.mir  |    92 +-
 .../cheri/machinelicm-capability-pseudos.ll   |    84 +-
 .../CodeGen/RISCV/cheri/machinelicm-hoist.mir |   464 +-
 llvm/test/CodeGen/RISCV/cheri/mem32.ll        |   144 +-
 llvm/test/CodeGen/RISCV/cheri/mem64.ll        |   230 +-
 .../RISCV/cheri/ptradd-dagcombine-infinite.ll |    26 +-
 .../RISCV/cheri/purecap-large-frame.ll        |    42 +-
 .../RISCV/cheri/read_write_register.ll        |    44 +-
 .../test/CodeGen/RISCV/cheri/realign-stack.ll |    44 +-
 .../CodeGen/RISCV/cheri/rematerialize.mir     |   100 +-
 .../RISCV/cheri/rv32-double-calling-conv.ll   |   396 +-
 llvm/test/CodeGen/RISCV/cheri/select-null.ll  |    20 +-
 llvm/test/CodeGen/RISCV/cheri/spill.ll        |    18 +-
 .../CodeGen/RISCV/cheri/stack-protector.ll    |    80 +-
 llvm/test/CodeGen/RISCV/cheri/stack.ll        |    72 +-
 llvm/test/CodeGen/RISCV/cheri/tls-models.ll   |   112 +-
 .../RISCV/cheri/unaligned-fp-load-store.ll    |   340 +-
 llvm/test/CodeGen/RISCV/cheri/vector-store.ll |    14 +-
 llvm/test/CodeGen/RISCV/stack-folding.ll      |   432 +-
 .../MC/RISCV/cheri/attribute-with-insts.s     |     2 +-
 llvm/test/MC/RISCV/cheri/cheriot-auipcccgp.s  |     8 +-
 llvm/test/MC/RISCV/cheri/cheriot-only.s       |     4 +-
 llvm/test/MC/RISCV/cheri/cheriot.s            |   140 +-
 .../cheri/rv32axcheri-cap-mode-only-valid.s   |    24 +-
 .../RISCV/cheri/rv32axcheri-cap-mode-valid.s  |   120 +-
 .../MC/RISCV/cheri/rv32axcheri-only-valid.s   |    32 +-
 llvm/test/MC/RISCV/cheri/rv32axcheri-valid.s  |    12 +-
 .../cheri/rv32cxcheri-cap-mode-invalid.s      |    26 +-
 .../cheri/rv32cxcheri-cap-mode-only-valid.s   |    16 +-
 .../RISCV/cheri/rv32cxcheri-cap-mode-valid.s  |    28 +-
 .../cheri/rv32fdcxcheri-cap-mode-only-valid.s |    16 +-
 .../RISCV/cheri/rv32fdxcheri-cap-mode-valid.s |    32 +-
 .../cheri/rv32xcheri-cap-mode-only-valid.s    |     8 +-
 .../RISCV/cheri/rv32xcheri-cap-mode-valid.s   |    32 +-
 .../MC/RISCV/cheri/rv32xcheri-only-valid.s    |    12 +-
 llvm/test/MC/RISCV/cheri/rv32xcheri-valid.s   |   104 +-
 .../rv64axcheri-cap-mode-aliases-valid.s      |   176 +-
 .../RISCV/cheri/rv64axcheri-cap-mode-valid.s  |   112 +-
 llvm/test/MC/RISCV/cheri/rv64axcheri-valid.s  |    36 +-
 .../cheri/rv64cxcheri-cap-mode-only-valid.s   |    32 +-
 .../cheri/rv64xcheri-cap-mode-only-valid.s    |    20 +-
 llvm/test/MC/RISCV/cheri/rv64xcheri-valid.s   |    18 +-
 llvm/test/MC/RISCV/rvi-pseudos-invalid.s      |     2 +-
 .../RelLookupTableConverter/cheri.ll          |     8 +-
 192 files changed, 15592 insertions(+), 15495 deletions(-)

diff --git a/clang/test/CodeGen/cheri/cheri-hybrid-ptr-to-cap.c b/clang/test/CodeGen/cheri/cheri-hybrid-ptr-to-cap.c
index 5c803b4bb916a..a4bba00c06649 100644
--- a/clang/test/CodeGen/cheri/cheri-hybrid-ptr-to-cap.c
+++ b/clang/test/CodeGen/cheri/cheri-hybrid-ptr-to-cap.c
@@ -26,10 +26,10 @@ void *__capability global_fn_to_cap(void) {
   // ASM-MIPS:      cgetpcc $c1
   // ASM-MIPS-NEXT: ld $1, %got_disp(external_fn)($1)
   // ASM-MIPS-NEXT: cfromptr $c3, $c1, $1
-  // ASM-RISCV: cspecialr ca1, pcc
+  // ASM-RISCV: cspecialr a1, pcc
   // ASM-RISCV: auipc a0, %got_pcrel_hi(external_fn)
   // ASM-RISCV-NEXT:  ld a0, %pcrel_lo(.Lpcrel_hi0)(a0)
-  // ASM-RISCV-NEXT:  csetaddr ca1, ca1, a0
+  // ASM-RISCV-NEXT:  csetaddr a1, a1, a0
   return (__cheri_tocap void *__capability)&external_fn;
 }
 
@@ -46,8 +46,8 @@ void *__capability global_data_to_cap(void) {
   // ASM-MIPS-NEXT: csetbounds $c3, $c1, 4
   // ASM-RISCV: auipc a0, %got_pcrel_hi(external_global)
   // ASM-RISCV-NEXT:  ld a0, %pcrel_lo(.Lpcrel_hi1)(a0)
-  // ASM-RISCV-NEXT:  cspecialr ca1, ddc
-  // ASM-RISCV-NEXT:  csetaddr ca1, ca1, a0
+  // ASM-RISCV-NEXT:  cspecialr a1, ddc
+  // ASM-RISCV-NEXT:  csetaddr a1, a1, a0
   // We do not set bounds on RISCV
   // ASM-RISCV-NOT: csetbounds
   return (__cheri_tocap void *__capability)&external_global;
@@ -68,8 +68,8 @@ void *__capability fn_ptr_to_cap(void (*fn_ptr)(void)) {
   // ASM-LABEL: fn_ptr_to_cap:
   // ASM-MIPS:      cgetpcc $c1
   // ASM-MIPS-NEXT: cfromptr $c3, $c1, $1
-  // ASM-RISCV:      cspecialr ca1, pcc
-  // ASM-RISCV-NEXT: csetaddr ca1, ca1, a0
+  // ASM-RISCV:      cspecialr a1, pcc
+  // ASM-RISCV-NEXT: csetaddr a1, a1, a0
   return (__cheri_tocap void *__capability)fn_ptr;
 }
 
@@ -88,8 +88,8 @@ void *__capability fn_ptr_to_cap(void (*fn_ptr)(void)) {
 void *__capability fn_ptr_to_cap_not_smart_enough(void (*fn_ptr)(void)) {
   // ASM-LABEL: fn_ptr_to_cap_not_smart_enough:
   // ASM-MIPS:  cfromddc $c3, $1
-  // ASM-RISCV: cspecialr ca1, ddc
-  // ASM-RISCV-NEXT:  csetaddr ca1, ca1, a0
+  // ASM-RISCV: cspecialr a1, ddc
+  // ASM-RISCV-NEXT:  csetaddr a1, a1, a0
   // Note: In this case clang doesn't see that the result is actual a function
   // so it uses DDC:
   void *tmp = (void *)fn_ptr;
@@ -109,7 +109,7 @@ void *__capability data_ptr_to_cap(int *data_ptr) {
   // Note: For data pointers we derive from DDC:
   // ASM-LABEL: data_ptr_to_cap:
   // ASM-MIPS:  cfromddc $c3, $1
-  // ASM-RISCV: cspecialr ca1, ddc
-  // ASM-RISCV-NEXT:  csetaddr ca1, ca1, a0
+  // ASM-RISCV: cspecialr a1, ddc
+  // ASM-RISCV-NEXT:  csetaddr a1, a1, a0
   return (__cheri_tocap void *__capability)data_ptr;
 }
diff --git a/clang/test/CodeGen/cheri/cheri-mcu-atomic-libcall.c b/clang/test/CodeGen/cheri/cheri-mcu-atomic-libcall.c
index 54b65d2984a46..01cdb3557450a 100644
--- a/clang/test/CodeGen/cheri/cheri-mcu-atomic-libcall.c
+++ b/clang/test/CodeGen/cheri/cheri-mcu-atomic-libcall.c
@@ -4,8 +4,8 @@ _Atomic(int) x;
 
 int callFromNotLibcall(void) {
   // Check that atomic libcalls get the right calling convention at the call site.
-  // CHECK: auipcc  ct2, %cheriot_compartment_hi(__library_import_libcalls___atomic_fetch_add_4)
-  // CHECK: clc     ct2, %cheriot_compartment_lo_i(.LBB0_2)(ct2)
-  // CHECK: cjalr   ct2
+  // CHECK: auipcc  t2, %cheriot_compartment_hi(__library_import_libcalls___atomic_fetch_add_4)
+  // CHECK: clc     t2, %cheriot_compartment_lo_i(.LBB0_2)(t2)
+  // CHECK: cjalr   t2
   return __c11_atomic_fetch_add(&x, 1, 5);
 }
diff --git a/lld/test/ELF/cheri/riscv/cheriot_compartment_hi.s b/lld/test/ELF/cheri/riscv/cheriot_compartment_hi.s
index f9978a8f2e4af..54cadaa379361 100644
--- a/lld/test/ELF/cheri/riscv/cheriot_compartment_hi.s
+++ b/lld/test/ELF/cheri/riscv/cheriot_compartment_hi.s
@@ -10,12 +10,12 @@
 	.p2align	1
 	.type	_start,@function
 _start:                              # @_Z5entryv
-	ct.auipcc	ct1, %cheriot_compartment_hi(near)
-	ct.auipcc	ct1, %cheriot_compartment_hi(mid)
+	ct.auipcc	t1, %cheriot_compartment_hi(near)
+	ct.auipcc	t1, %cheriot_compartment_hi(mid)
 
 # CHECK:        00012000 <_start>:
-# CHECK-NEXT:   12000: 00000317      ct.auipcc       ct1, 0x0
-# CHECK-NEXT:   12004: 00001317      ct.auipcc       ct1, 0x1
+# CHECK-NEXT:   12000: 00000317      ct.auipcc       t1, 0x0
+# CHECK-NEXT:   12004: 00001317      ct.auipcc       t1, 0x1
 
 	.type	near,@object
 	.p2align	3, 0x0
diff --git a/lld/test/ELF/cheri/riscv/cheriot_compartment_lo_i.s b/lld/test/ELF/cheri/riscv/cheriot_compartment_lo_i.s
index 1eba49483851a..df32a6c4edb9b 100644
--- a/lld/test/ELF/cheri/riscv/cheriot_compartment_lo_i.s
+++ b/lld/test/ELF/cheri/riscv/cheriot_compartment_lo_i.s
@@ -10,33 +10,33 @@
 	.p2align	1
 	.type	_start,@function
 _start:                              # @_Z5entryv
-	ct.auipcc	ct1, %cheriot_compartment_hi(near)
-    ct.clc	ct1, %cheriot_compartment_lo_i(_start)(ct1)
+	ct.auipcc	t1, %cheriot_compartment_hi(near)
+    ct.clc	t1, %cheriot_compartment_lo_i(_start)(t1)
 .MID_BLOCK:
-	ct.auipcc	ct1, %cheriot_compartment_hi(mid)
-    ct.clc	ct1, %cheriot_compartment_lo_i(.MID_BLOCK)(ct1)
+	ct.auipcc	t1, %cheriot_compartment_hi(mid)
+    ct.clc	t1, %cheriot_compartment_lo_i(.MID_BLOCK)(t1)
 .CGP_BLOCK:
-	ct.auipcc	ct1, %cheriot_compartment_hi(cgp)
-    ct.clw	ra, %cheriot_compartment_lo_i(.CGP_BLOCK)(ct1)
+	ct.auipcc	t1, %cheriot_compartment_hi(cgp)
+    ct.clw	ra, %cheriot_compartment_lo_i(.CGP_BLOCK)(t1)
 .CGP_FAR_BLOCK:
-	ct.auipcc	ct1, %cheriot_compartment_hi(cgp_far)
-    ct.clw	ra, %cheriot_compartment_lo_i(.CGP_FAR_BLOCK)(ct1)
+	ct.auipcc	t1, %cheriot_compartment_hi(cgp_far)
+    ct.clw	ra, %cheriot_compartment_lo_i(.CGP_FAR_BLOCK)(t1)
 
 # CHECK:        00012000 <_start>:
-# CHECK-NEXT:   12000: 00000317      ct.auipcc       ct1, 0x0
-# CHECK-NEXT:   12004: 02033303      ct.clc  ct1, 0x20(ct1)
+# CHECK-NEXT:   12000: 00000317      ct.auipcc       t1, 0x0
+# CHECK-NEXT:   12004: 02033303      ct.clc  t1, 0x20(t1)
 
 # CHECK:        00012008 <.MID_BLOCK>:
-# CHECK-NEXT:   12008: 00001317      ct.auipcc       ct1, 0x1
-# CHECK-NEXT:   1200c: 7f833303      ct.clc  ct1, 0x7f8(ct1)
+# CHECK-NEXT:   12008: 00001317      ct.auipcc       t1, 0x1
+# CHECK-NEXT:   1200c: 7f833303      ct.clc  t1, 0x7f8(t1)
 
 # CHECK: 00012010 <.CGP_BLOCK>:
-# CHECK-NEXT: 12010: ffffe37b      ct.auicgp       ct1, 0xffffe
-# CHECK-NEXT: 12014: ffc32083      ct.clw  ra, -0x4(ct1)
+# CHECK-NEXT: 12010: ffffe37b      ct.auicgp       t1, 0xffffe
+# CHECK-NEXT: 12014: ffc32083      ct.clw  ra, -0x4(t1)
 
 # CHECK: 00012018 <.CGP_FAR_BLOCK>:
-# CHECK-NEXT: 12018: 0000237b      ct.auicgp       ct1, 0x2
-# CHECK-NEXT: 1201c: 00032083      ct.clw  ra, 0x0(ct1)
+# CHECK-NEXT: 12018: 0000237b      ct.auicgp       t1, 0x2
+# CHECK-NEXT: 1201c: 00032083      ct.clw  ra, 0x0(t1)
 
 	.type	near,@object
 	.p2align	3, 0x0
diff --git a/lld/test/ELF/cheri/riscv/plt.s b/lld/test/ELF/cheri/riscv/plt.s
index 8c2abe85fb35f..1a0e1dc7cf69f 100644
--- a/lld/test/ELF/cheri/riscv/plt.s
+++ b/lld/test/ELF/cheri/riscv/plt.s
@@ -44,17 +44,17 @@
 # DIS:      <_start>:
 ## Direct call
 ## foo - . = 0x11020-0x11000 = 32
-# DIS-NEXT:   11000: auipcc cra, 0
-# DIS-NEXT:          cjalr 32(cra)
+# DIS-NEXT:   11000: auipcc ra, 0
+# DIS-NEXT:          cjalr 32(ra)
 ## bar@plt - . = 0x11050-0x11008 = 72
-# DIS-NEXT:   11008: auipcc cra, 0
-# DIS-NEXT:          cjalr 72(cra)
+# DIS-NEXT:   11008: auipcc ra, 0
+# DIS-NEXT:          cjalr 72(ra)
 ## bar@plt - . = 0x11050-0x11010 = 64
-# DIS-NEXT:   11010: auipcc cra, 0
-# DIS-NEXT:          cjalr 64(cra)
+# DIS-NEXT:   11010: auipcc ra, 0
+# DIS-NEXT:          cjalr 64(ra)
 ## weak@plt - . = 0x11060-0x11018 = 72
-# DIS-NEXT:   11018: auipcc cra, 0
-# DIS-NEXT:          cjalr 72(cra)
+# DIS-NEXT:   11018: auipcc ra, 0
+# DIS-NEXT:          cjalr 72(ra)
 # DIS:      <foo>:
 # DIS-NEXT:   11020:
 
@@ -63,17 +63,17 @@
 # DIS-NEXT:     ...
 
 ## 32-bit: &.captable[bar]-. = 0x12000-0x11050 = 4096*1-80
-# DIS:        11050: auipcc ct3, 1
-# DIS32-NEXT:   clc ct3, -80(ct3)
-# DIS64-NEXT:   clc ct3, -80(ct3)
-# DIS-NEXT:     cjalr ct1, ct3
+# DIS:        11050: auipcc t3, 1
+# DIS32-NEXT:   clc t3, -80(t3)
+# DIS64-NEXT:   clc t3, -80(t3)
+# DIS-NEXT:     cjalr t1, t3
 # DIS-NEXT:     nop
 
 ## 32-bit: &.captable[weak]-. = 0x12008-0x11060 = 4096*1-88
-# DIS:        11060: auipcc ct3, 1
-# DIS32-NEXT:   clc ct3, -88(ct3)
-# DIS64-NEXT:   clc ct3, -80(ct3)
-# DIS-NEXT:     cjalr ct1, ct3
+# DIS:        11060: auipcc t3, 1
+# DIS32-NEXT:   clc t3, -88(t3)
+# DIS64-NEXT:   clc t3, -80(t3)
+# DIS-NEXT:     cjalr t1, t3
 # DIS-NEXT:     nop
 
 .global _start, foo, bar
diff --git a/lld/test/ELF/cheri/riscv/tls.s b/lld/test/ELF/cheri/riscv/tls.s
index 45e05734007e4..fbf5931f32fd4 100644
--- a/lld/test/ELF/cheri/riscv/tls.s
+++ b/lld/test/ELF/cheri/riscv/tls.s
@@ -54,40 +54,40 @@
 # RV32-SO-CAP-NEXT: 0x00003298 00000000 00000000
 
 # 0x121e0 - 0x111b4 = 0x0102c (GD evar)
-# RV32-DIS:      111b4: auipcc ca0, 1
-# RV32-DIS-NEXT:        cincoffset ca0, ca0, 44
+# RV32-DIS:      111b4: auipcc a0, 1
+# RV32-DIS-NEXT:        cincoffset a0, a0, 44
 
 # 0x121f0 - 0x111bc = 0x01034 (IE evar)
-# RV32-DIS:      111bc: auipcc ca0, 1
-# RV32-DIS-NEXT:        clw a0, 52(ca0)
+# RV32-DIS:      111bc: auipcc a0, 1
+# RV32-DIS-NEXT:        clw a0, 52(a0)
 
 # 0x121e8 - 0x111c4 = 0x01024 (GD lvar)
-# RV32-DIS:      111c4: auipcc ca0, 1
-# RV32-DIS-NEXT:        cincoffset ca0, ca0, 36
+# RV32-DIS:      111c4: auipcc a0, 1
+# RV32-DIS-NEXT:        cincoffset a0, a0, 36
 
 # 0x121f4 - 0x111cc = 0x01028 (IE lvar)
-# RV32-DIS:      111cc: auipcc ca0, 1
-# RV32-DIS-NEXT:        clw a0, 40(ca0)
+# RV32-DIS:      111cc: auipcc a0, 1
+# RV32-DIS-NEXT:        clw a0, 40(a0)
 
 # RV32-DIS:      111d4: lui a0, 0
-# RV32-DIS-NEXT:        cincoffset ca0, ctp, a0
-# RV32-DIS-NEXT:        cincoffset ca0, ca0, 4
+# RV32-DIS-NEXT:        cincoffset a0, tp, a0
+# RV32-DIS-NEXT:        cincoffset a0, a0, 4
 
 # 0x3288 - 0x1210 = 0x2078 (GD evar)
-# RV32-SO-DIS:      1210: auipcc ca0, 2
-# RV32-SO-DIS-NEXT:       cincoffset ca0, ca0, 120
+# RV32-SO-DIS:      1210: auipcc a0, 2
+# RV32-SO-DIS-NEXT:       cincoffset a0, a0, 120
 
 # 0x3298 - 0x1218 = 0x2080 (IE evar)
-# RV32-SO-DIS:      1218: auipcc ca0, 2
-# RV32-SO-DIS-NEXT:       clw a0, 128(ca0)
+# RV32-SO-DIS:      1218: auipcc a0, 2
+# RV32-SO-DIS-NEXT:       clw a0, 128(a0)
 
 # 0x3290 - 0x1220 = 0x2070 (GD lvar)
-# RV32-SO-DIS:      1220: auipcc ca0, 2
-# RV32-SO-DIS-NEXT:       cincoffset ca0, ca0, 112
+# RV32-SO-DIS:      1220: auipcc a0, 2
+# RV32-SO-DIS-NEXT:       cincoffset a0, a0, 112
 
 # 0x329c - 0x1228 = 0x2074 (IE lvar)
-# RV32-SO-DIS:      1228: auipcc ca0, 2
-# RV32-SO-DIS-NEXT:       clw a0, 116(ca0)
+# RV32-SO-DIS:      1228: auipcc a0, 2
+# RV32-SO-DIS-NEXT:       clw a0, 116(a0)
 
 # RV64-REL:      .rela.dyn {
 # RV64-REL-NEXT:   0x122F0 R_RISCV_TLS_DTPMOD64 evar 0x0
@@ -114,55 +114,55 @@
 # RV64-SO-CAP-NEXT: 0x00003440 00000000 00000000 00000000 00000000
 
 # 0x122f0 - 0x112b8 = 0x01038 (GD evar)
-# RV64-DIS:      112b8: auipcc ca0, 1
-# RV64-DIS-NEXT:        cincoffset ca0, ca0, 56
+# RV64-DIS:      112b8: auipcc a0, 1
+# RV64-DIS-NEXT:        cincoffset a0, a0, 56
 
 # 0x12310 - 0x112c0 = 0x01050 (IE evar)
-# RV64-DIS:      112c0: auipcc ca0, 1
-# RV64-DIS-NEXT:        cld a0, 80(ca0)
+# RV64-DIS:      112c0: auipcc a0, 1
+# RV64-DIS-NEXT:        cld a0, 80(a0)
 
 # 0x12300 - 0x112c8 = 0x01038 (GD lvar)
-# RV64-DIS:      112c8: auipcc ca0, 1
-# RV64-DIS-NEXT:        cincoffset ca0, ca0, 56
+# RV64-DIS:      112c8: auipcc a0, 1
+# RV64-DIS-NEXT:        cincoffset a0, a0, 56
 
 # 0x12318 - 0x112d0 = 0x01048 (IE lvar)
-# RV64-DIS:      112d0: auipcc ca0, 1
-# RV64-DIS-NEXT:        cld a0, 72(ca0)
+# RV64-DIS:      112d0: auipcc a0, 1
+# RV64-DIS-NEXT:        cld a0, 72(a0)
 
 # RV64-DIS:      112d8: lui a0, 0
-# RV64-DIS-NEXT:        cincoffset ca0, ctp, a0
-# RV64-DIS-NEXT:        cincoffset ca0, ca0, 4
+# RV64-DIS-NEXT:        cincoffset a0, tp, a0
+# RV64-DIS-NEXT:        cincoffset a0, a0, 4
 
 # 0x3420 - 0x1350 = 0x20d0 (GD evar)
-# RV64-SO-DIS:      1350: auipcc ca0, 2
-# RV64-SO-DIS-NEXT:       cincoffset ca0, ca0, 208
+# RV64-SO-DIS:      1350: auipcc a0, 2
+# RV64-SO-DIS-NEXT:       cincoffset a0, a0, 208
 
 # 0x3440 - 0x1358 = 0x20e8 (IE evar)
-# RV64-SO-DIS:      1358: auipcc ca0, 2
-# RV64-SO-DIS-NEXT:       cld a0, 232(ca0)
+# RV64-SO-DIS:      1358: auipcc a0, 2
+# RV64-SO-DIS-NEXT:       cld a0, 232(a0)
 
 # 0x3430 - 0x1360 = 0x20d0 (GD lvar)
-# RV64-SO-DIS:      1360: auipcc ca0, 2
-# RV64-SO-DIS-NEXT:       cincoffset ca0, ca0, 208
+# RV64-SO-DIS:      1360: auipcc a0, 2
+# RV64-SO-DIS-NEXT:       cincoffset a0, a0, 208
 
 # 0x3448 - 0x1368 = 0x20e0 (IE lvar)
-# RV64-SO-DIS:      1368: auipcc ca0, 2
-# RV64-SO-DIS-NEXT:       cld a0, 224(ca0)
+# RV64-SO-DIS:      1368: auipcc a0, 2
+# RV64-SO-DIS-NEXT:       cld a0, 224(a0)
 
 .global _start
 _start:
-	clc.tls.gd ca0, evar
+	clc.tls.gd a0, evar
 
-	cla.tls.ie a0, evar, ca0
+	cla.tls.ie a0, evar, a0
 
-	clc.tls.gd ca0, lvar
+	clc.tls.gd a0, lvar
 
-	cla.tls.ie a0, lvar, ca0
+	cla.tls.ie a0, lvar, a0
 
 .if PIC == 0
 	lui a0, %tprel_hi(lvar)
-	cincoffset ca0, ctp, a0, %tprel_cincoffset(lvar)
-	cincoffset ca0, ca0, %tprel_lo(lvar)
+	cincoffset a0, tp, a0, %tprel_cincoffset(lvar)
+	cincoffset a0, a0, %tprel_lo(lvar)
 .endif
 
 .tbss
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index c9c7405e76537..9241d93b5a506 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -549,9 +549,9 @@ struct RISCVOperand final : public MCParsedAsmOperand {
            RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg.RegNum);
   }
 
-  bool isGPCR() const {
+  bool isYGPR() const {
     return Kind == KindTy::Register &&
-           RISCVMCRegisterClasses[RISCV::GPCRRegClassID].contains(Reg.RegNum);
+           RISCVMCRegisterClasses[RISCV::YGPRRegClassID].contains(Reg.RegNum);
   }
 
   bool isGPRPair() const {
@@ -1464,6 +1464,11 @@ static MCRegister convertFPR64ToFPR128(MCRegister Reg) {
   return Reg - RISCV::F0_D + RISCV::F0_Q;
 }
 
+static MCRegister convertGPRToYGPR(MCRegister Reg) {
+  assert(Reg >= RISCV::X0 && Reg <= RISCV::X31 && "Invalid register");
+  return Reg - RISCV::X0 + RISCV::X0_Y;
+}
+
 static MCRegister convertVRToVRMx(const MCRegisterInfo &RI, MCRegister Reg,
                                   unsigned Kind) {
   unsigned RegClassID;
@@ -1492,6 +1497,17 @@ unsigned RISCVAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
       RISCVMCRegisterClasses[RISCV::FPR64CRegClassID].contains(Reg);
   bool IsRegVR = RISCVMCRegisterClasses[RISCV::VRRegClassID].contains(Reg);
 
+  bool WantsYReg = Kind == MCK_YGPR || Kind == MCK_YGPRC ||
+                   Kind == MCK_YGPRTC || Kind == MCK_YGPRE ||
+                   Kind == MCK_YGPRNoX0X1 || Kind == MCK_YGPRNoX0 ||
+                   Kind == MCK_YGPRX0IsDDC;
+
+  if (Op.isGPR() && WantsYReg) {
+    // GPR and capability GPR use the same register names, convert if required.
+    Op.Reg.RegNum = convertGPRToYGPR(Reg);
+    return Match_Success;
+  }
+
   if (IsRegFPR64 && Kind == MCK_FPR128) {
     Op.Reg.RegNum = convertFPR64ToFPR128(Reg);
     return Match_Success;
@@ -4245,7 +4261,7 @@ bool RISCVAsmParser::checkPseudoCIncOffsetTPRel(MCInst &Inst,
   assert(Inst.getOpcode() == RISCV::PseudoCIncOffsetTPRel &&
          "Invalid instruction");
   assert(Inst.getOperand(1).isReg() && "Unexpected first operand kind");
-  if (Inst.getOperand(1).getReg() != RISCV::C4) {
+  if (Inst.getOperand(1).getReg() != RISCV::X4_Y) {
     SMLoc ErrorLoc = ((RISCVOperand &)*Operands[2]).getStartLoc();
     return Error(ErrorLoc, "the first input operand must be ctp/c4 when using "
                            "%tprel_cincoffset modifier");
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 9dd4e5b9c7f95..9042ae989feaa 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -125,7 +125,7 @@ static DecodeStatus DecodeGPRX1X5RegisterClass(MCInst &Inst, uint32_t RegNo,
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeGPCRRegisterClass(MCInst &Inst, uint64_t RegNo,
+static DecodeStatus DecodeYGPRRegisterClass(MCInst &Inst, uint64_t RegNo,
                                             uint64_t Address,
                                             const MCDisassembler *Decoder) {
   bool IsRV32E = Decoder->getSubtargetInfo().hasFeature(RISCV::FeatureStdExtE);
@@ -133,7 +133,7 @@ static DecodeStatus DecodeGPCRRegisterClass(MCInst &Inst, uint64_t RegNo,
   if (RegNo >= 32 || (IsRV32E && RegNo >= 16))
     return MCDisassembler::Fail;
 
-  MCRegister Reg = RISCV::C0 + RegNo;
+  MCRegister Reg = RISCV::X0_Y + RegNo;
   Inst.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
@@ -204,15 +204,15 @@ static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, uint32_t RegNo,
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeGPCRC0IsDDCRegisterClass(MCInst &Inst, uint64_t RegNo,
-                                                   uint64_t Address,
-                                                   const MCDisassembler *Decoder) {
+static DecodeStatus
+DecodeYGPRX0IsDDCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address,
+                               const MCDisassembler *Decoder) {
   if (RegNo == 0) {
     Inst.addOperand(MCOperand::createReg(RISCV::DDC));
     return MCDisassembler::Success;
   }
 
-  return DecodeGPCRRegisterClass(Inst, RegNo, Address, Decoder);
+  return DecodeYGPRRegisterClass(Inst, RegNo, Address, Decoder);
 }
 
 static DecodeStatus DecodeGPRNoX0RegisterClass(MCInst &Inst, uint32_t RegNo,
@@ -225,14 +225,14 @@ static DecodeStatus DecodeGPRNoX0RegisterClass(MCInst &Inst, uint32_t RegNo,
   return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
 }
 
-static DecodeStatus DecodeGPCRNoC0RegisterClass(MCInst &Inst, uint64_t RegNo,
+static DecodeStatus DecodeYGPRNoX0RegisterClass(MCInst &Inst, uint64_t RegNo,
                                                 uint64_t Address,
                                                 const MCDisassembler *Decoder) {
   if (RegNo == 0) {
     return MCDisassembler::Fail;
   }
 
-  return DecodeGPCRRegisterClass(Inst, RegNo, Address, Decoder);
+  return DecodeYGPRRegisterClass(Inst, RegNo, Address, Decoder);
 }
 
 static DecodeStatus
@@ -266,13 +266,13 @@ static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint32_t RegNo,
   return MCDisassembler::Success;
 }
 
-static DecodeStatus DecodeGPCRCRegisterClass(MCInst &Inst, uint64_t RegNo,
+static DecodeStatus DecodeYGPRCRegisterClass(MCInst &Inst, uint64_t RegNo,
                                              uint64_t Address,
                                              const void *Decoder) {
   if (RegNo >= 8)
     return MCDisassembler::Fail;
 
-  MCRegister Reg = RISCV::C8 + RegNo;
+  MCRegister Reg = RISCV::X8_Y + RegNo;
   Inst.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
@@ -763,7 +763,7 @@ void RISCVDisassembler::addSPOperands(MCInst &MI) const {
     if (MCID.operands()[i].RegClass == RISCV::SPRegClassID)
       MI.insert(MI.begin() + i, MCOperand::createReg(RISCV::X2));
     if (MCID.operands()[i].RegClass == RISCV::CSPRegClassID)
-      MI.insert(MI.begin() + i, MCOperand::createReg(RISCV::C2));
+      MI.insert(MI.begin() + i, MCOperand::createReg(RISCV::X2_Y));
   }
 }
 
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
index 2a88112d26495..bac268417db48 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
@@ -152,7 +152,7 @@ ABI getTargetABI(StringRef ABIName, const Triple &TT) {
 // callee saved register to save the value. RV32E only has X8 and X9 as callee
 // saved registers and X8 will be used as fp. So we choose X9 as bp.
 MCRegister getBPReg(ABI TargetABI) {
-  return isCheriPureCapABI(TargetABI) ? RISCV::C9 : RISCV::X9;
+  return isCheriPureCapABI(TargetABI) ? RISCV::X9_Y : RISCV::X9;
 }
 
 // Returns the register holding shadow call stack pointer.
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
index d01915f26cf02..2684e62ef9b79 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
@@ -186,7 +186,7 @@ void RISCVMCCodeEmitter::expandFunctionCall(const MCInst &MI,
     IsCap = false;
   } else if (MI.getOpcode() == RISCV::PseudoCTAIL) {
     Func = MI.getOperand(0);
-    Ra = RISCV::C6;
+    Ra = RISCV::X6_Y;
     IsCap = true;
   } else if (MI.getOpcode() == RISCV::PseudoCCALLReg) {
     Func = MI.getOperand(1);
@@ -194,7 +194,7 @@ void RISCVMCCodeEmitter::expandFunctionCall(const MCInst &MI,
     IsCap = true;
   } else if (MI.getOpcode() == RISCV::PseudoCCALL) {
     Func = MI.getOperand(0);
-    Ra = RISCV::C1;
+    Ra = RISCV::X1_Y;
     IsCap = true;
   } else if (MI.getOpcode() == RISCV::PseudoCJump) {
     Func = MI.getOperand(1);
@@ -220,7 +220,7 @@ void RISCVMCCodeEmitter::expandFunctionCall(const MCInst &MI,
       MI.getOpcode() == RISCV::PseudoCJump)
     // Emit [C]JALR [XC]0, Ra, 0
     TmpInst = MCInstBuilder(IsCap ? RISCV::CJALR : RISCV::JALR)
-                  .addReg(IsCap ? RISCV::C0 : RISCV::X0)
+                  .addReg(IsCap ? RISCV::X0_Y : RISCV::X0)
                   .addReg(Ra)
                   .addImm(0);
   else
@@ -292,7 +292,7 @@ void RISCVMCCodeEmitter::expandCIncOffsetTPRel(
   MCOperand DestReg = MI.getOperand(0);
   MCOperand TPReg = MI.getOperand(1);
   MCOperand SrcReg = MI.getOperand(2);
-  assert(TPReg.isReg() && TPReg.getReg() == RISCV::C4 &&
+  assert(TPReg.isReg() && TPReg.getReg() == RISCV::X4_Y &&
          "Expected thread pointer as first input to CTP-relative cincoffset");
 
   MCOperand SrcSymbol = MI.getOperand(3);
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
index bb0956779e855..eb3ec1bfe6ec1 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
@@ -57,7 +57,7 @@ createRISCVMCRegisterInfo(const Triple &TT, const MCTargetOptions &Options) {
 
   MCRegister RAReg;
   if (ABI != RISCVABI::ABI_Unknown && RISCVABI::isCheriPureCapABI(ABI))
-    RAReg = RISCV::C1;
+    RAReg = RISCV::X1_Y;
   else
     RAReg = RISCV::X1;
 
@@ -73,7 +73,7 @@ static MCAsmInfo *createRISCVMCAsmInfo(const MCRegisterInfo &MRI,
 
   MCRegister SPReg;
   if (ABI != RISCVABI::ABI_Unknown && RISCVABI::isCheriPureCapABI(ABI))
-    SPReg = RISCV::C2;
+    SPReg = RISCV::X2_Y;
   else
     SPReg = RISCV::X2;
 
diff --git a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
index c506089f61a2d..4068d974cf8ab 100644
--- a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
+++ b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
@@ -593,16 +593,16 @@ bool RISCVAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
   // switcher will zero all of the ones above this.
   auto countUsedArgRegisters = [](auto const &MF) -> int {
     static constexpr int ArgRegCount = 7;
-    static const MCPhysReg ArgGPCRsE[ArgRegCount] = {
-        RISCV::C10, RISCV::C11, RISCV::C12, RISCV::C13,
-        RISCV::C14, RISCV::C15, RISCV::C5};
+    static const MCPhysReg ArgYGPRsE[ArgRegCount] = {
+        RISCV::X10_Y, RISCV::X11_Y, RISCV::X12_Y, RISCV::X13_Y,
+        RISCV::X14_Y, RISCV::X15_Y, RISCV::X5_Y};
     auto LiveIns = MF.getRegInfo().liveins();
     auto *TRI = MF.getRegInfo().getTargetRegisterInfo();
     int NumArgRegs = 0;
     for (auto LI : LiveIns)
       for (int i = 0; i < ArgRegCount; i++)
-        if ((ArgGPCRsE[i] == LI.first) ||
-            TRI->isSubRegister(ArgGPCRsE[i], LI.first)) {
+        if ((ArgYGPRsE[i] == LI.first) ||
+            TRI->isSubRegister(ArgYGPRsE[i], LI.first)) {
           NumArgRegs = std::max(NumArgRegs, i + 1);
           break;
         }
diff --git a/llvm/lib/Target/RISCV/RISCVCallingConv.cpp b/llvm/lib/Target/RISCV/RISCVCallingConv.cpp
index d036be1a20d84..15d5a723ef387 100644
--- a/llvm/lib/Target/RISCV/RISCVCallingConv.cpp
+++ b/llvm/lib/Target/RISCV/RISCVCallingConv.cpp
@@ -142,43 +142,44 @@ ArrayRef<MCPhysReg> RISCV::getArgGPRs(const RISCVABI::ABI ABI) {
   return ArrayRef(ArgIGPRs);
 }
 
-ArrayRef<MCPhysReg> RISCV::getArgGPCRs(const RISCVABI::ABI ABI) {
+ArrayRef<MCPhysReg> RISCV::getArgYGPRs(const RISCVABI::ABI ABI) {
   // The GPRs used for passing arguments in the ILP32* and LP64* ABIs, except
   // the ILP32E ABI.
-  static const MCPhysReg ArgIGPCRs[] = {RISCV::C10, RISCV::C11, RISCV::C12,
-                                        RISCV::C13, RISCV::C14, RISCV::C15,
-                                        RISCV::C16, RISCV::C17};
+  static const MCPhysReg ArgIYGPRs[] = {
+      RISCV::X10_Y, RISCV::X11_Y, RISCV::X12_Y, RISCV::X13_Y,
+      RISCV::X14_Y, RISCV::X15_Y, RISCV::X16_Y, RISCV::X17_Y};
   // The GPRs used for passing arguments in the ILP32E/ILP64E ABI.
-  static const MCPhysReg ArgEGPCRs[] = {RISCV::C10, RISCV::C11, RISCV::C12,
-                                        RISCV::C13, RISCV::C14, RISCV::C15};
+  static const MCPhysReg ArgEYGPRs[] = {RISCV::X10_Y, RISCV::X11_Y,
+                                        RISCV::X12_Y, RISCV::X13_Y,
+                                        RISCV::X14_Y, RISCV::X15_Y};
 
   if (ABI == RISCVABI::ABI_ILP32E || ABI == RISCVABI::ABI_LP64E ||
       ABI == RISCVABI::ABI_IL32PC64E ||
       ABI == RISCVABI::ABI_CHERIOT || ABI == RISCVABI::ABI_CHERIOT_BAREMETAL)
-    return ArrayRef(ArgEGPCRs);
+    return ArrayRef(ArgEYGPRs);
 
-  return ArrayRef(ArgIGPCRs);
+  return ArrayRef(ArgIYGPRs);
 }
 
-static ArrayRef<MCPhysReg> getFastCCArgGPCRs(const RISCVABI::ABI ABI) {
+static ArrayRef<MCPhysReg> getFastCCArgYGPRs(const RISCVABI::ABI ABI) {
   // The GPRs used for passing arguments in the FastCC, X5 and X6 might be used
   // for save-restore libcall, so we don't use them.
-  static const MCPhysReg FastCCIGPCRs[] = {
-      RISCV::C10, RISCV::C11, RISCV::C12, RISCV::C13, RISCV::C14,
-      RISCV::C15, RISCV::C16, RISCV::C17, RISCV::C7,  RISCV::C28,
-      RISCV::C29, RISCV::C30, RISCV::C31};
+  static const MCPhysReg FastCCIYGPRs[] = {
+      RISCV::X10_Y, RISCV::X11_Y, RISCV::X12_Y, RISCV::X13_Y, RISCV::X14_Y,
+      RISCV::X15_Y, RISCV::X16_Y, RISCV::X17_Y, RISCV::X7_Y,  RISCV::X28_Y,
+      RISCV::X29_Y, RISCV::X30_Y, RISCV::X31_Y};
 
   // The GPRs used for passing arguments in the FastCC when using ILP32E/ILP64E.
-  static const MCPhysReg FastCCEGPCRs[] = {RISCV::C10, RISCV::C11, RISCV::C12,
-                                           RISCV::C13, RISCV::C14, RISCV::C15,
-                                           RISCV::C7};
+  static const MCPhysReg FastCCEYGPRs[] = {
+      RISCV::X10_Y, RISCV::X11_Y, RISCV::X12_Y, RISCV::X13_Y,
+      RISCV::X14_Y, RISCV::X15_Y, RISCV::X7_Y};
 
   if (ABI == RISCVABI::ABI_ILP32E || ABI == RISCVABI::ABI_LP64E ||
       ABI == RISCVABI::ABI_IL32PC64E ||
       ABI == RISCVABI::ABI_CHERIOT || ABI == RISCVABI::ABI_CHERIOT_BAREMETAL)
-    return ArrayRef(FastCCEGPCRs);
+    return ArrayRef(FastCCEYGPRs);
 
-  return ArrayRef(FastCCIGPCRs);
+  return ArrayRef(FastCCIYGPRs);
 }
 
 static ArrayRef<MCPhysReg> getArgGPR16s(const RISCVABI::ABI ABI) {
@@ -491,7 +492,7 @@ bool llvm::CC_RISCV(unsigned ValNo, MVT ValVT, MVT LocVT,
   }
 
   ArrayRef<MCPhysReg> ArgGPRs = RISCV::getArgGPRs(ABI);
-  ArrayRef<MCPhysReg> ArgGPCRs = RISCV::getArgGPCRs(ABI);
+  ArrayRef<MCPhysReg> ArgYGPRs = RISCV::getArgYGPRs(ABI);
 
   // Zdinx use GPR without a bitcast when possible.
   if (LocVT == MVT::f64 && XLen == 64 && Subtarget.hasStdExtZdinx()) {
@@ -501,9 +502,9 @@ bool llvm::CC_RISCV(unsigned ValNo, MVT ValVT, MVT LocVT,
     }
   }
 
-  // Cheriot uses GPCR without a bitcast when possible.
+  // Cheriot uses YGPR without a bitcast when possible.
   if (LocVT == MVT::f64 && Subtarget.hasVendorXCheriot() && !IsPureCapVarArgs) {
-    if (MCRegister Reg = State.AllocateReg(ArgGPCRs)) {
+    if (MCRegister Reg = State.AllocateReg(ArgYGPRs)) {
       State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
       return false;
     }
@@ -627,7 +628,7 @@ bool llvm::CC_RISCV(unsigned ValNo, MVT ValVT, MVT LocVT,
   if (IsPureCapVarArgs)
     Reg = 0;
   else if (ValVT == CLenVT)
-    Reg = State.AllocateReg(ArgGPCRs);
+    Reg = State.AllocateReg(ArgYGPRs);
   else if (ValVT.isVector() || ValVT.isRISCVVectorTuple()) {
     Reg = allocateRVVReg(ValVT, ValNo, State, TLI);
     if (Reg) {
@@ -665,7 +666,7 @@ bool llvm::CC_RISCV(unsigned ValNo, MVT ValVT, MVT LocVT,
     // split arguments.
     assert(ArgFlags.isSplitEnd() && "Expected ArgFlags.isSplitEnd()");
     assert(PendingLocs.size() > 2 && "Unexpected PendingLocs.size()");
-    Reg = State.AllocateReg(ArgGPCRs);
+    Reg = State.AllocateReg(ArgYGPRs);
   } else {
     Reg = State.AllocateReg(ArgGPRs);
   }
@@ -721,9 +722,9 @@ bool llvm::CC_RISCV_FastCC(unsigned ValNo, MVT ValVT, MVT LocVT,
 
   if (LocVT.isFatPointer()) {
     // C5 and C6 might be used for save-restore libcall.
-    const ArrayRef<MCPhysReg> GPCRList =
-      getFastCCArgGPCRs(Subtarget.getTargetABI());
-    if (unsigned Reg = State.AllocateReg(GPCRList)) {
+    const ArrayRef<MCPhysReg> YGPRList =
+        getFastCCArgYGPRs(Subtarget.getTargetABI());
+    if (unsigned Reg = State.AllocateReg(YGPRList)) {
       State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
       return false;
     }
diff --git a/llvm/lib/Target/RISCV/RISCVCallingConv.h b/llvm/lib/Target/RISCV/RISCVCallingConv.h
index f42b869367fd5..afbaae1dfbe2d 100644
--- a/llvm/lib/Target/RISCV/RISCVCallingConv.h
+++ b/llvm/lib/Target/RISCV/RISCVCallingConv.h
@@ -38,7 +38,7 @@ bool CC_RISCV_GHC(unsigned ValNo, MVT ValVT, MVT LocVT,
 namespace RISCV {
 
 ArrayRef<MCPhysReg> getArgGPRs(const RISCVABI::ABI ABI);
-ArrayRef<MCPhysReg> getArgGPCRs(const RISCVABI::ABI ABI);
+ArrayRef<MCPhysReg> getArgYGPRs(const RISCVABI::ABI ABI);
 
 } // end namespace RISCV
 
diff --git a/llvm/lib/Target/RISCV/RISCVCallingConv.td b/llvm/lib/Target/RISCV/RISCVCallingConv.td
index f4c540d2a5102..3871ca26f42dd 100644
--- a/llvm/lib/Target/RISCV/RISCVCallingConv.td
+++ b/llvm/lib/Target/RISCV/RISCVCallingConv.td
@@ -40,8 +40,8 @@ def CSR_ILP32D_LP64D_V
     : CalleeSavedRegs<(add CSR_ILP32D_LP64D, CSR_V)>;
 
 def CSR_IL32PC64_L64PC128
-    : CalleeSavedRegs<(add X1, X3, X4, X8, X9, (sequence "X%u", 18, 27),
-                           C1, C3, C4, C8, C9, (sequence "C%u", 18, 27))>;
+    : CalleeSavedRegs<(add X1, X3, X4, X8, X9, (sequence "X%u", 18, 27), X1_Y,
+          X3_Y, X4_Y, X8_Y, X9_Y, (sequence "X%u_Y", 18, 27))>;
 
 def CSR_IL32PC64F_L64PC128F
     : CalleeSavedRegs<(add CSR_IL32PC64_L64PC128,
@@ -51,9 +51,7 @@ def CSR_IL32PC64D_L64PC128D
     : CalleeSavedRegs<(add CSR_IL32PC64_L64PC128,
                        F8_D, F9_D, (sequence "F%u_D", 18, 27))>;
 
-def CSR_CHERIOT
-    : CalleeSavedRegs<(add X1, X3, X8, X9,
-                           C1, C3, C8, C9)>;
+def CSR_CHERIOT : CalleeSavedRegs<(add X1, X3, X8, X9, X1_Y, X3_Y, X8_Y, X9_Y)>;
 
 // Needed for implementation of RISCVRegisterInfo::getNoPreservedMask()
 def CSR_NoRegs : CalleeSavedRegs<(add)>;
@@ -112,55 +110,31 @@ def CSR_XLEN_F64_V_Interrupt_RVE: CalleeSavedRegs<(sub CSR_XLEN_F64_V_Interrupt,
 
 // Same as CSR_Interrupt, but including all capability registers that are used,
 // both Caller and Callee saved registers.
-def CSR_XLEN_CLEN_Interrupt : CalleeSavedRegs<(add X1,
-    (sequence "X%u", 3, 9),
-    (sequence "X%u", 10, 11),
-    (sequence "X%u", 12, 17),
-    (sequence "X%u", 18, 27),
-    (sequence "X%u", 28, 31),
-    C1,
-    (sequence "C%u", 3, 9),
-    (sequence "C%u", 10, 11),
-    (sequence "C%u", 12, 17),
-    (sequence "C%u", 18, 27),
-    (sequence "C%u", 28, 31))>;
+def CSR_XLEN_CLEN_Interrupt
+    : CalleeSavedRegs<(add X1, (sequence "X%u", 3, 9), (sequence "X%u", 10, 11),
+          (sequence "X%u", 12, 17), (sequence "X%u", 18, 27),
+          (sequence "X%u", 28, 31), X1_Y, (sequence "X%u_Y", 3, 9),
+          (sequence "X%u_Y", 10, 11), (sequence "X%u_Y", 12, 17),
+          (sequence "X%u_Y", 18, 27), (sequence "X%u_Y", 28, 31))>;
 
 // Same as CSR_XLEN_CLEN_Interrupt, but including all 32-bit FP registers.
-def CSR_XLEN_CLEN_F32_Interrupt: CalleeSavedRegs<(add X1,
-    (sequence "X%u", 3, 9),
-    (sequence "X%u", 10, 11),
-    (sequence "X%u", 12, 17),
-    (sequence "X%u", 18, 27),
-    (sequence "X%u", 28, 31),
-    C1,
-    (sequence "C%u", 3, 9),
-    (sequence "C%u", 10, 11),
-    (sequence "C%u", 12, 17),
-    (sequence "C%u", 18, 27),
-    (sequence "C%u", 28, 31),
-    (sequence "F%u_F", 0, 7),
-    (sequence "F%u_F", 10, 11),
-    (sequence "F%u_F", 12, 17),
-    (sequence "F%u_F", 28, 31),
-    (sequence "F%u_F", 8, 9),
-    (sequence "F%u_F", 18, 27))>;
+def CSR_XLEN_CLEN_F32_Interrupt
+    : CalleeSavedRegs<(add X1, (sequence "X%u", 3, 9), (sequence "X%u", 10, 11),
+          (sequence "X%u", 12, 17), (sequence "X%u", 18, 27),
+          (sequence "X%u", 28, 31), X1_Y, (sequence "X%u_Y", 3, 9),
+          (sequence "X%u_Y", 10, 11), (sequence "X%u_Y", 12, 17),
+          (sequence "X%u_Y", 18, 27), (sequence "X%u_Y", 28, 31),
+          (sequence "F%u_F", 0, 7), (sequence "F%u_F", 10, 11),
+          (sequence "F%u_F", 12, 17), (sequence "F%u_F", 28, 31),
+          (sequence "F%u_F", 8, 9), (sequence "F%u_F", 18, 27))>;
 
 // Same as CSR_XLEN_CLEN_Interrupt, but including all 64-bit FP registers.
-def CSR_XLEN_CLEN_F64_Interrupt: CalleeSavedRegs<(add X1,
-    (sequence "X%u", 3, 9),
-    (sequence "X%u", 10, 11),
-    (sequence "X%u", 12, 17),
-    (sequence "X%u", 18, 27),
-    (sequence "X%u", 28, 31),
-    C1,
-    (sequence "C%u", 3, 9),
-    (sequence "C%u", 10, 11),
-    (sequence "C%u", 12, 17),
-    (sequence "C%u", 18, 27),
-    (sequence "C%u", 28, 31),
-    (sequence "F%u_D", 0, 7),
-    (sequence "F%u_D", 10, 11),
-    (sequence "F%u_D", 12, 17),
-    (sequence "F%u_D", 28, 31),
-    (sequence "F%u_D", 8, 9),
-    (sequence "F%u_D", 18, 27))>;
+def CSR_XLEN_CLEN_F64_Interrupt
+    : CalleeSavedRegs<(add X1, (sequence "X%u", 3, 9), (sequence "X%u", 10, 11),
+          (sequence "X%u", 12, 17), (sequence "X%u", 18, 27),
+          (sequence "X%u", 28, 31), X1_Y, (sequence "X%u_Y", 3, 9),
+          (sequence "X%u_Y", 10, 11), (sequence "X%u_Y", 12, 17),
+          (sequence "X%u_Y", 18, 27), (sequence "X%u_Y", 28, 31),
+          (sequence "F%u_D", 0, 7), (sequence "F%u_D", 10, 11),
+          (sequence "F%u_D", 12, 17), (sequence "F%u_D", 28, 31),
+          (sequence "F%u_D", 8, 9), (sequence "F%u_D", 18, 27))>;
diff --git a/llvm/lib/Target/RISCV/RISCVCheriCleanup.cpp b/llvm/lib/Target/RISCV/RISCVCheriCleanup.cpp
index ce41271221d2c..be02edaa0b1eb 100644
--- a/llvm/lib/Target/RISCV/RISCVCheriCleanup.cpp
+++ b/llvm/lib/Target/RISCV/RISCVCheriCleanup.cpp
@@ -137,7 +137,7 @@ bool RISCVCheriCleanupOpt::runOnMachineFunction(MachineFunction &MF) {
       SizeReg = Out;
     }
     const Register DstReg = MI.getOperand(0).getReg();
-    const Register Unbounded = MRI.createVirtualRegister(&RISCV::GPCRRegClass);
+    const Register Unbounded = MRI.createVirtualRegister(&RISCV::YGPRRegClass);
     MI.getOperand(0).setReg(Unbounded);
     // Replace the pseudo with the version that doesn't need CSetBounds applied.
     MI.setDesc(TII->get(RISCV::PseudoCLLCInbounds));
diff --git a/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp b/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
index 6f1bde4898928..dc3db668077a5 100644
--- a/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
@@ -403,13 +403,13 @@ bool RISCVExpandPseudo::expandCompartmentCall(MachineBasicBlock &MBB,
 
   MF->insert(++MBB.getIterator(), NewMBB);
 
-  BuildMI(NewMBB, DL, TII->get(RISCV::AUIPCC), RISCV::C7)
+  BuildMI(NewMBB, DL, TII->get(RISCV::AUIPCC), RISCV::X7_Y)
       .addDisp(Switcher, 0, RISCVII::MO_CHERIOT_COMPARTMENT_HI);
-  BuildMI(NewMBB, DL, TII->get(RISCV::CLC_64), RISCV::C7)
-      .addReg(RISCV::C7, RegState::Kill)
+  BuildMI(NewMBB, DL, TII->get(RISCV::CLC_64), RISCV::X7_Y)
+      .addReg(RISCV::X7_Y, RegState::Kill)
       .addMBB(NewMBB, RISCVII::MO_CHERIOT_COMPARTMENT_LO_I);
   BuildMI(NewMBB, DL, TII->get(RISCV::C_CJALR))
-      .addReg(RISCV::C7, RegState::Kill);
+      .addReg(RISCV::X7_Y, RegState::Kill);
 
   // Move all the rest of the instructions to NewMBB.
   NewMBB->splice(NewMBB->end(), &MBB, std::next(MBBI), MBB.end());
@@ -424,11 +424,11 @@ bool RISCVExpandPseudo::expandCompartmentCall(MachineBasicBlock &MBB,
 
   if (Callee.isGlobal()) {
     auto *Fn = dyn_cast<Function>(resolveGlobalAlias(Callee.getGlobal()));
-    insertLoadOfImportTable(MBB, MBBI, Fn, RISCV::C6);
+    insertLoadOfImportTable(MBB, MBBI, Fn, RISCV::X6_Y);
   } else {
     assert(Callee.isReg() && "Expected register operand");
-    if (Callee.getReg() != RISCV::C6) {
-      BuildMI(&MBB, DL, TII->get(RISCV::CMove)).addReg(RISCV::C6).add(Callee);
+    if (Callee.getReg() != RISCV::X6_Y) {
+      BuildMI(&MBB, DL, TII->get(RISCV::CMove)).addReg(RISCV::X6_Y).add(Callee);
     }
   }
 
@@ -455,7 +455,7 @@ bool RISCVExpandPseudo::expandLibraryCall(
       MI.setDesc(TII->get(RISCV::PseudoCCALL));
       return true;
     }
-    insertLoadOfImportTable(MBB, MBBI, Fn, RISCV::C7, true, true);
+    insertLoadOfImportTable(MBB, MBBI, Fn, RISCV::X7_Y, true, true);
 
     NextMBBI = MBB.end();
   } else if (Callee.isSymbol()) {
@@ -485,7 +485,7 @@ bool RISCVExpandPseudo::expandLibraryCall(
     MCSymbol *ExportSymbol =
         MF->getContext().getOrCreateSymbol(ExportEntryName);
     insertLoadOfImportTable(MBB, MBBI, ImportSymbol, ExportSymbol,
-                            Callee.getSymbolName(), RISCV::C7, true, true,
+                            Callee.getSymbolName(), RISCV::X7_Y, true, true,
                             true);
 
     NextMBBI = MBB.end();
diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
index c9aa6271512b1..5e1119f3ac6de 100644
--- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
@@ -532,7 +532,7 @@ uint64_t RISCVFrameLowering::getStackSizeWithRVVPadding(
 // Returns the register used to hold the frame pointer.
 Register RISCVFrameLowering::getFPReg() const {
   if (RISCVABI::isCheriPureCapABI(STI.getTargetABI()))
-    return RISCV::C8;
+    return RISCV::X8_Y;
   else
     return RISCV::X8;
 }
@@ -540,7 +540,7 @@ Register RISCVFrameLowering::getFPReg() const {
 // Returns the register used to hold the stack pointer.
 Register RISCVFrameLowering::getSPReg() const {
   if (RISCVABI::isCheriPureCapABI(STI.getTargetABI()))
-    return RISCV::C2;
+    return RISCV::X2_Y;
   else
     return RISCV::X2;
 }
@@ -1006,13 +1006,13 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
           .addMBB(failMBB);
     };
     if (RVFI->getStackArgumentSize() > 0)
-      createChecks(RISCV::C5, RVFI->getStackArgumentSize());
+      createChecks(RISCV::X5_Y, RVFI->getStackArgumentSize());
 
     auto &F = MF.getFunction();
     if (!F.args().empty()) {
       auto *Arg = F.args().begin();
       if (Arg->hasStructRetAttr())
-        createChecks(RISCV::C10,
+        createChecks(RISCV::X10_Y,
                      F.getParent()->getDataLayout().getTypeStoreSize(
                          Arg->getParamStructRetType()));
     }
@@ -1655,8 +1655,8 @@ void RISCVFrameLowering::determineCalleeSaves(MachineFunction &MF,
   // pointer.
   if (hasFP(MF)) {
     if (RISCVABI::isCheriPureCapABI(STI.getTargetABI())) {
-      SavedRegs.set(RISCV::C1);
-      SavedRegs.set(RISCV::C8);
+      SavedRegs.set(RISCV::X1_Y);
+      SavedRegs.set(RISCV::X8_Y);
     } else {
       SavedRegs.set(RAReg);
       SavedRegs.set(FPReg);
@@ -1857,7 +1857,7 @@ void RISCVFrameLowering::processFunctionBeforeFrameFinalized(
   MachineFrameInfo &MFI = MF.getFrameInfo();
   const TargetRegisterClass *RC;
   if (RISCVABI::isCheriPureCapABI(STI.getTargetABI()))
-    RC = &RISCV::GPCRRegClass;
+    RC = &RISCV::YGPRRegClass;
   else
     RC = &RISCV::GPRRegClass;
   auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index cbbe1ed0826c5..eee2ee362f404 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -168,19 +168,19 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
 
   if (Subtarget.hasVendorXCheri()) {
     CapType = Subtarget.typeForCapabilities();
-    NullCapabilityRegister = RISCV::C0;
-    addRegisterClass(CapType, &RISCV::GPCRRegClass);
+    NullCapabilityRegister = RISCV::X0_Y;
+    addRegisterClass(CapType, &RISCV::YGPRRegClass);
   }
 
   if (Subtarget.hasVendorXCheri()) {
     CapType = Subtarget.typeForCapabilities();
-    NullCapabilityRegister = RISCV::C0;
-    addRegisterClass(CapType, &RISCV::GPCRRegClass);
+    NullCapabilityRegister = RISCV::X0_Y;
+    addRegisterClass(CapType, &RISCV::YGPRRegClass);
   }
 
   if (Subtarget.hasVendorXCheriot()) {
     // Cheriot holds f64's in capability registers.
-    addRegisterClass(MVT::f64, &RISCV::GPCRRegClass);
+    addRegisterClass(MVT::f64, &RISCV::YGPRRegClass);
   }
 
   static const MVT::SimpleValueType BoolVecVTs[] = {
@@ -320,7 +320,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
   computeRegisterProperties(STI.getRegisterInfo());
 
   if (RISCVABI::isCheriPureCapABI(ABI))
-    setStackPointerRegisterToSaveRestore(RISCV::C2);
+    setStackPointerRegisterToSaveRestore(RISCV::X2_Y);
   else
     setStackPointerRegisterToSaveRestore(RISCV::X2);
 
@@ -9178,7 +9178,7 @@ SDValue RISCVTargetLowering::getStaticTLSAddr(GlobalAddressSDNode *N,
       DAG.setNodeMemRefs(cast<MachineSDNode>(Load.getNode()), {MemOp});
 
       // Add the thread pointer.
-      SDValue TPReg = DAG.getRegister(RISCV::C4, Ty);
+      SDValue TPReg = DAG.getRegister(RISCV::X4_Y, Ty);
       return DAG.getMemBasePlusOffset(TPReg, Load, DL);
     }
 
@@ -9197,7 +9197,7 @@ SDValue RISCVTargetLowering::getStaticTLSAddr(GlobalAddressSDNode *N,
 
     SDValue MNHi =
         SDValue(DAG.getMachineNode(RISCV::LUI, DL, XLenVT, AddrHi), 0);
-    SDValue TPReg = DAG.getRegister(RISCV::C4, Ty);
+    SDValue TPReg = DAG.getRegister(RISCV::X4_Y, Ty);
     SDValue MNAdd = SDValue(
         DAG.getMachineNode(RISCV::PseudoCIncOffsetTPRel, DL, Ty, TPReg, MNHi,
                            AddrCIncOffset),
@@ -11106,7 +11106,8 @@ SDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
     return emitCToPtrReplacement(DAG, DL, Op->getOperand(2), XLenVT);
   case Intrinsic::thread_pointer: {
     MCPhysReg PhysReg = RISCVABI::isCheriPureCapABI(Subtarget.getTargetABI())
-        ? RISCV::C4 : RISCV::X4;
+                            ? RISCV::X4_Y
+                            : RISCV::X4;
     EVT PtrVT = getPointerTy(DAG.getDataLayout(),
                              DAG.getDataLayout().getGlobalsAddressSpace());
     return DAG.getRegister(PhysReg, PtrVT);
@@ -22590,8 +22591,8 @@ RISCVTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
   case RISCV::Select_GPRNoX0_Using_CC_UImm16NonZero_QC:
   case RISCV::Select_GPR_Using_CC_UImmLog2XLen_NDS:
   case RISCV::Select_GPR_Using_CC_UImm7_NDS:
-  case RISCV::Select_GPCR_Using_CC_GPR:
-  case RISCV::Select_GPCR_f64_Using_CC_GPR:
+  case RISCV::Select_YGPR_Using_CC_GPR:
+  case RISCV::Select_YGPR_f64_Using_CC_GPR:
   case RISCV::Select_FPR16_Using_CC_GPR:
   case RISCV::Select_FPR16INX_Using_CC_GPR:
   case RISCV::Select_FPR32_Using_CC_GPR:
@@ -22872,7 +22873,7 @@ static SDValue unpackFromMemLoc(SelectionDAG &DAG, SDValue Chain,
     Val = DAG.getExtLoad(
         ExtType, DL, LocVT, Chain,
         DAG.getMemBasePlusOffset(
-            DAG.getCopyFromReg(Chain, DL, RISCV::C5, MVT::c64),
+            DAG.getCopyFromReg(Chain, DL, RISCV::X5_Y, MVT::c64),
             TypeSize::getFixed(VA.getLocMemOffset()), DL),
         MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), ValVT);
   else {
@@ -23077,7 +23078,7 @@ SDValue RISCVTargetLowering::LowerFormalArguments(
   }
 
   if (stackArgumentSize && isCHERIoTCompartmentCall)
-    MF.getRegInfo().addLiveIn(RISCV::C5);
+    MF.getRegInfo().addLiveIn(RISCV::X5_Y);
 
   MachineFrameInfo &MFI = MF.getFrameInfo();
   RISCVMachineFunctionInfo *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
@@ -23460,7 +23461,7 @@ SDValue RISCVTargetLowering::LowerCall(CallLoweringInfo &CLI,
       SDValue BoundedArgFrame =
           DAG.getNode(RISCVISD::BOUNDS_SET, DL, PtrVT, StackPtr,
                       DAG.getIntPtrConstant(NumBytes, DL));
-      RegsToPass.emplace_back(RISCV::C5, BoundedArgFrame);
+      RegsToPass.emplace_back(RISCV::X5_Y, BoundedArgFrame);
     }
   }
 
@@ -23680,11 +23681,11 @@ RISCVTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
         CallConv == CallingConv::CHERIoT_CompartmentCallee) {
       switch (VA.getLocReg()) {
       case RISCV::X10:
-      case RISCV::C10:
+      case RISCV::X10_Y:
         zeroX10 = false;
         break;
       case RISCV::X11:
-      case RISCV::C11:
+      case RISCV::X11_Y:
         zeroX11 = false;
         break;
       }
@@ -23887,7 +23888,7 @@ RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
       return std::make_pair(0U, &RISCV::GPRNoX0RegClass);
     case 'C':
       if (Subtarget.hasVendorXCheri() && VT == Subtarget.typeForCapabilities())
-        return std::make_pair(0U, &RISCV::GPCRRegClass);
+        return std::make_pair(0U, &RISCV::YGPRRegClass);
       break;
     case 'f':
       if (VT == MVT::f16) {
@@ -23979,6 +23980,84 @@ RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
     }
   }
 
+  if (Subtarget.hasVendorXCheri()) {
+    // Allow capability register ABI names to be used in constraint.
+    unsigned YRegFromAlias =
+        StringSwitch<unsigned>(Constraint.lower())
+            .Cases("{c0}", "{cnull}", "{czero}", RISCV::X0_Y)
+            .Cases("{c1}", "{cra}", RISCV::X1_Y)
+            .Cases("{c2}", "{csp}", RISCV::X2_Y)
+            .Cases("{c3}", "{cgp}", RISCV::X3_Y)
+            .Cases("{c4}", "{ctp}", RISCV::X4_Y)
+            .Cases("{c5}", "{ct0}", RISCV::X5_Y)
+            .Cases("{c6}", "{ct1}", RISCV::X6_Y)
+            .Cases("{c7}", "{ct2}", RISCV::X7_Y)
+            .Cases("{c8}", "{cs0}", "{cfp}", RISCV::X8_Y)
+            .Cases("{c9}", "{cs1}", RISCV::X9_Y)
+            .Cases("{c10}", "{ca0}", RISCV::X10_Y)
+            .Cases("{c11}", "{ca1}", RISCV::X11_Y)
+            .Cases("{c12}", "{ca2}", RISCV::X12_Y)
+            .Cases("{c13}", "{ca3}", RISCV::X13_Y)
+            .Cases("{c14}", "{ca4}", RISCV::X14_Y)
+            .Cases("{c15}", "{ca5}", RISCV::X15_Y)
+            .Cases("{c16}", "{ca6}", RISCV::X16_Y)
+            .Cases("{c17}", "{ca7}", RISCV::X17_Y)
+            .Cases("{c18}", "{cs2}", RISCV::X18_Y)
+            .Cases("{c19}", "{cs3}", RISCV::X19_Y)
+            .Cases("{c20}", "{cs4}", RISCV::X20_Y)
+            .Cases("{c21}", "{cs5}", RISCV::X21_Y)
+            .Cases("{c22}", "{cs6}", RISCV::X22_Y)
+            .Cases("{c23}", "{cs7}", RISCV::X23_Y)
+            .Cases("{c24}", "{cs8}", RISCV::X24_Y)
+            .Cases("{c25}", "{cs9}", RISCV::X25_Y)
+            .Cases("{c26}", "{cs10}", RISCV::X26_Y)
+            .Cases("{c27}", "{cs11}", RISCV::X27_Y)
+            .Cases("{c28}", "{ct3}", RISCV::X28_Y)
+            .Cases("{c29}", "{ct4}", RISCV::X29_Y)
+            .Cases("{c30}", "{ct5}", RISCV::X30_Y)
+            .Cases("{c31}", "{ct6}", RISCV::X31_Y)
+            .Default(RISCV::NoRegister);
+
+    if (YRegFromAlias == RISCV::NoRegister &&
+        VT == Subtarget.typeForCapabilities())
+      YRegFromAlias = StringSwitch<unsigned>(Constraint.lower())
+                          .Cases("{x0}", "{zero}", RISCV::X0_Y)
+                          .Cases("{x1}", "{ra}", RISCV::X1_Y)
+                          .Cases("{x2}", "{sp}", RISCV::X2_Y)
+                          .Cases("{x3}", "{gp}", RISCV::X3_Y)
+                          .Cases("{x4}", "{tp}", RISCV::X4_Y)
+                          .Cases("{x5}", "{t0}", RISCV::X5_Y)
+                          .Cases("{x6}", "{t1}", RISCV::X6_Y)
+                          .Cases("{x7}", "{t2}", RISCV::X7_Y)
+                          .Cases("{x8}", "{s0}", "{fp}", RISCV::X8_Y)
+                          .Cases("{x9}", "{s1}", RISCV::X9_Y)
+                          .Cases("{x10}", "{a0}", RISCV::X10_Y)
+                          .Cases("{x11}", "{a1}", RISCV::X11_Y)
+                          .Cases("{x12}", "{a2}", RISCV::X12_Y)
+                          .Cases("{x13}", "{a3}", RISCV::X13_Y)
+                          .Cases("{x14}", "{a4}", RISCV::X14_Y)
+                          .Cases("{x15}", "{a5}", RISCV::X15_Y)
+                          .Cases("{x16}", "{a6}", RISCV::X16_Y)
+                          .Cases("{x17}", "{a7}", RISCV::X17_Y)
+                          .Cases("{x18}", "{s2}", RISCV::X18_Y)
+                          .Cases("{x19}", "{s3}", RISCV::X19_Y)
+                          .Cases("{x20}", "{s4}", RISCV::X20_Y)
+                          .Cases("{x21}", "{s5}", RISCV::X21_Y)
+                          .Cases("{x22}", "{s6}", RISCV::X22_Y)
+                          .Cases("{x23}", "{s7}", RISCV::X23_Y)
+                          .Cases("{x24}", "{s8}", RISCV::X24_Y)
+                          .Cases("{x25}", "{s9}", RISCV::X25_Y)
+                          .Cases("{x26}", "{s10}", RISCV::X26_Y)
+                          .Cases("{x27}", "{s11}", RISCV::X27_Y)
+                          .Cases("{x28}", "{t3}", RISCV::X28_Y)
+                          .Cases("{x29}", "{t4}", RISCV::X29_Y)
+                          .Cases("{x30}", "{t5}", RISCV::X30_Y)
+                          .Cases("{x31}", "{t6}", RISCV::X31_Y)
+                          .Default(RISCV::NoRegister);
+    if (YRegFromAlias != RISCV::NoRegister)
+      return std::make_pair(YRegFromAlias, &RISCV::YGPRRegClass);
+  }
+
   // Clang will correctly decode the usage of register name aliases into their
   // official names. However, other frontends like `rustc` do not. This allows
   // users of these frontends to use the ABI names for registers in LLVM-style
@@ -24020,46 +24099,6 @@ RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
   if (XRegFromAlias != RISCV::NoRegister)
     return std::make_pair(XRegFromAlias, &RISCV::GPRRegClass);
 
-  // Similarly, allow capability register ABI names to be used in constraint.
-  if (Subtarget.hasVendorXCheri()) {
-    Register CRegFromAlias = StringSwitch<Register>(Constraint.lower())
-                                 .Case("{cnull}", RISCV::C0)
-                                 .Case("{cra}", RISCV::C1)
-                                 .Case("{csp}", RISCV::C2)
-                                 .Case("{cgp}", RISCV::C3)
-                                 .Case("{ctp}", RISCV::C4)
-                                 .Case("{ct0}", RISCV::C5)
-                                 .Case("{ct1}", RISCV::C6)
-                                 .Case("{ct2}", RISCV::C7)
-                                 .Cases("{cs0}", "{cfp}", RISCV::C8)
-                                 .Case("{cs1}", RISCV::C9)
-                                 .Case("{ca0}", RISCV::C10)
-                                 .Case("{ca1}", RISCV::C11)
-                                 .Case("{ca2}", RISCV::C12)
-                                 .Case("{ca3}", RISCV::C13)
-                                 .Case("{ca4}", RISCV::C14)
-                                 .Case("{ca5}", RISCV::C15)
-                                 .Case("{ca6}", RISCV::C16)
-                                 .Case("{ca7}", RISCV::C17)
-                                 .Case("{cs2}", RISCV::C18)
-                                 .Case("{cs3}", RISCV::C19)
-                                 .Case("{cs4}", RISCV::C20)
-                                 .Case("{cs5}", RISCV::C21)
-                                 .Case("{cs6}", RISCV::C22)
-                                 .Case("{cs7}", RISCV::C23)
-                                 .Case("{cs8}", RISCV::C24)
-                                 .Case("{cs9}", RISCV::C25)
-                                 .Case("{cs10}", RISCV::C26)
-                                 .Case("{cs11}", RISCV::C27)
-                                 .Case("{ct3}", RISCV::C28)
-                                 .Case("{ct4}", RISCV::C29)
-                                 .Case("{ct5}", RISCV::C30)
-                                 .Case("{ct6}", RISCV::C31)
-                                 .Default(RISCV::NoRegister);
-    if (CRegFromAlias != RISCV::NoRegister)
-      return std::make_pair(CRegFromAlias, &RISCV::GPCRRegClass);
-  }
-
   // Since TargetLowering::getRegForInlineAsmConstraint uses the name of the
   // TableGen record rather than the AsmName to choose registers for InlineAsm
   // constraints, plus we want to match those names to the widest floating point
@@ -24696,8 +24735,8 @@ ISD::NodeType RISCVTargetLowering::getExtendForAtomicCmpSwapArg() const {
 
 Register RISCVTargetLowering::getExceptionPointerRegister(
     const Constant *PersonalityFn) const {
-  return RISCVABI::isCheriPureCapABI(Subtarget.getTargetABI())
-      ? RISCV::C10 : RISCV::X10;
+  return RISCVABI::isCheriPureCapABI(Subtarget.getTargetABI()) ? RISCV::X10_Y
+                                                               : RISCV::X10;
 }
 
 Register RISCVTargetLowering::getExceptionSelectorRegister(
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index b77a7d5e38cdb..45fa71746e66c 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -566,7 +566,7 @@ void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
     return;
   }
 
-  if (RISCV::GPCRRegClass.contains(DstReg, SrcReg)) {
+  if (RISCV::YGPRRegClass.contains(DstReg, SrcReg)) {
     BuildMI(MBB, MBBI, DL, get(RISCV::CMove), DstReg)
         .addReg(SrcReg, KillFlag | getRenamableRegState(RenamableSrc));
     return;
@@ -692,8 +692,8 @@ void RISCVInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
     if (RISCV::GPRRegClass.hasSubClassEq(RC)) {
       Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ? RISCV::CSW
                                                                : RISCV::CSD;
-    } else if (RISCV::GPCRRegClass.hasSubClassEq(RC)) {
-      Opcode = TRI->getRegSizeInBits(RISCV::GPCRRegClass) == 64
+    } else if (RISCV::YGPRRegClass.hasSubClassEq(RC)) {
+      Opcode = TRI->getRegSizeInBits(RISCV::YGPRRegClass) == 64
                    ? RISCV::CSC_64
                    : RISCV::CSC_128;
     } else if (RISCV::FPR32RegClass.hasSubClassEq(RC)) {
@@ -706,22 +706,22 @@ void RISCVInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
   } else if (RISCV::GPRRegClass.hasSubClassEq(RC)) {
     Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ?
               RISCV::SW : RISCV::SD;
-  } else if (RISCV::GPCRRegClass.hasSubClassEq(RC)) {
-      Opcode = TRI->getRegSizeInBits(RISCV::GPCRRegClass) == 64 ? RISCV::SC_64
-                                                                : RISCV::SC_128;
+  } else if (RISCV::YGPRRegClass.hasSubClassEq(RC)) {
+    Opcode = TRI->getRegSizeInBits(RISCV::YGPRRegClass) == 64 ? RISCV::SC_64
+                                                              : RISCV::SC_128;
   } else if (RISCV::GPRF16RegClass.hasSubClassEq(RC)) {
     Opcode = RISCV::SH_INX;
   } else if (RISCV::GPRF32RegClass.hasSubClassEq(RC)) {
     Opcode = RISCV::SW_INX;
   } else if (RISCV::GPRPairRegClass.hasSubClassEq(RC)) {
     Opcode = RISCV::PseudoRV32ZdinxSD;
-    } else if (RISCV::FPR16RegClass.hasSubClassEq(RC)) {
+  } else if (RISCV::FPR16RegClass.hasSubClassEq(RC)) {
     Opcode = RISCV::FSH;
-    } else if (RISCV::FPR32RegClass.hasSubClassEq(RC)) {
+  } else if (RISCV::FPR32RegClass.hasSubClassEq(RC)) {
     Opcode = RISCV::FSW;
-    } else if (RISCV::FPR64RegClass.hasSubClassEq(RC)) {
+  } else if (RISCV::FPR64RegClass.hasSubClassEq(RC)) {
     Opcode = RISCV::FSD;
-    } else if (RISCV::VRRegClass.hasSubClassEq(RC)) {
+  } else if (RISCV::VRRegClass.hasSubClassEq(RC)) {
     Opcode = RISCV::VS1R_V;
   } else if (RISCV::VRM2RegClass.hasSubClassEq(RC)) {
     Opcode = RISCV::VS2R_V;
@@ -794,8 +794,8 @@ void RISCVInstrInfo::loadRegFromStackSlot(
     if (RISCV::GPRRegClass.hasSubClassEq(RC)) {
       Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ? RISCV::CLW
                                                                : RISCV::CLD;
-    } else if (RISCV::GPCRRegClass.hasSubClassEq(RC)) {
-      Opcode = TRI->getRegSizeInBits(RISCV::GPCRRegClass) == 64
+    } else if (RISCV::YGPRRegClass.hasSubClassEq(RC)) {
+      Opcode = TRI->getRegSizeInBits(RISCV::YGPRRegClass) == 64
                    ? RISCV::CLC_64
                    : RISCV::CLC_128;
     } else if (RISCV::FPR32RegClass.hasSubClassEq(RC)) {
@@ -808,8 +808,8 @@ void RISCVInstrInfo::loadRegFromStackSlot(
   } else if (RISCV::GPRRegClass.hasSubClassEq(RC)) {
     Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ?
               RISCV::LW : RISCV::LD;
-  } else if (RISCV::GPCRRegClass.hasSubClassEq(RC)) {
-    Opcode = TRI->getRegSizeInBits(RISCV::GPCRRegClass) == 64 ? RISCV::LC_64
+  } else if (RISCV::YGPRRegClass.hasSubClassEq(RC)) {
+    Opcode = TRI->getRegSizeInBits(RISCV::YGPRRegClass) == 64 ? RISCV::LC_64
                                                               : RISCV::LC_128;
   } else if (RISCV::GPRF16RegClass.hasSubClassEq(RC)) {
     Opcode = RISCV::LH_INX;
@@ -1400,7 +1400,7 @@ void RISCVInstrInfo::insertIndirectBranch(MachineBasicBlock &MBB,
   const TargetRegisterClass *RC;
   unsigned PseudoOpcode;
   if (RISCVABI::isCheriPureCapABI(ST.getTargetABI())) {
-    RC = &RISCV::GPCRRegClass;
+    RC = &RISCV::YGPRRegClass;
     PseudoOpcode = RISCV::PseudoCJump;
   } else {
     RC = &RISCV::GPRRegClass;
@@ -1429,7 +1429,7 @@ void RISCVInstrInfo::insertIndirectBranch(MachineBasicBlock &MBB,
 
     // Pick s11(or s1 for rve) because it doesn't make a difference.
     if (RISCVABI::isCheriPureCapABI(ST.getTargetABI())) {
-      TmpGPR = STI.hasStdExtE() ? RISCV::C9 : RISCV::C27;
+      TmpGPR = STI.hasStdExtE() ? RISCV::X9_Y : RISCV::X27_Y;
     } else {
       TmpGPR = STI.hasStdExtE() ? RISCV::X9 : RISCV::X27;
     }
@@ -2022,10 +2022,12 @@ bool RISCVInstrInfo::isAsCheapAsAMove(const MachineInstr &MI) const {
     // be attempted unless isAsCheapAsAMove returns true!
     return (MI.getOperand(2).isReg() &&
             MI.getOperand(2).getReg() == RISCV::X0) ||
-           (MI.getOperand(1).isReg() && MI.getOperand(1).getReg() == RISCV::C0);
+           (MI.getOperand(1).isReg() &&
+            MI.getOperand(1).getReg() == RISCV::X0_Y);
   case RISCV::CIncOffsetImm:
     return (MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0) ||
-           (MI.getOperand(1).isReg() && MI.getOperand(1).getReg() == RISCV::C0);
+           (MI.getOperand(1).isReg() &&
+            MI.getOperand(1).getReg() == RISCV::X0_Y);
   case RISCV::FSGNJ_D:
   case RISCV::FSGNJ_S:
   case RISCV::FSGNJ_H:
@@ -3757,14 +3759,14 @@ void RISCVInstrInfo::buildOutlinedFrame(
 
   bool IsPurecap = RISCVABI::isCheriPureCapABI(
       MF.getSubtarget<RISCVSubtarget>().getTargetABI());
-  MBB.addLiveIn(IsPurecap ? RISCV::C5 : RISCV::X5);
+  MBB.addLiveIn(IsPurecap ? RISCV::X5_Y : RISCV::X5);
 
   // Add in a return instruction to the end of the outlined frame.
   MBB.insert(
       MBB.end(),
       BuildMI(MF, DebugLoc(), get(IsPurecap ? RISCV::CJALR : RISCV::JALR))
-          .addReg(IsPurecap ? RISCV::C0 : RISCV::X0, RegState::Define)
-          .addReg(IsPurecap ? RISCV::C5 : RISCV::X5)
+          .addReg(IsPurecap ? RISCV::X0_Y : RISCV::X0, RegState::Define)
+          .addReg(IsPurecap ? RISCV::X5_Y : RISCV::X5)
           .addImm(0));
 }
 
@@ -3790,7 +3792,7 @@ MachineBasicBlock::iterator RISCVInstrInfo::insertOutlinedCall(
       It,
       BuildMI(MF, DebugLoc(),
               get(IsPurecap ? RISCV::PseudoCCALLReg : RISCV::PseudoCALLReg),
-              IsPurecap ? RISCV::C5 : RISCV::X5)
+              IsPurecap ? RISCV::X5_Y : RISCV::X5)
           .addGlobalAddress(M.getNamedValue(MF.getName()), 0,
                             IsPurecap ? RISCVII::MO_CCALL : RISCVII::MO_CALL));
   return It;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXCheri.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXCheri.td
index ee2951cfe3467..53c8e98bc1a26 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXCheri.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXCheri.td
@@ -11,19 +11,17 @@
 //===----------------------------------------------------------------------===//
 
 // Target-dependent type requirements.
-def SDT_RISCVCapCall        : SDTypeProfile<0, -1, [SDTCisVT<0, CLenVT>]>;
+def SDT_RISCVCapCall : SDTypeProfile<0, -1, [SDTCisVT<0, YLenVT>]>;
 
-def SDT_RISCVCheriBoolUnary : SDTypeProfile<1, 1, [
-  SDTCisInt<0>, SDTCisVT<1, CLenVT>
-]>;
+def SDT_RISCVCheriBoolUnary
+    : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVT<1, YLenVT>]>;
 
-def SDT_RISCVCheriBoolUnaryChain : SDTypeProfile<1, 1, [
-  SDTCisInt<0>, SDTCisVT<2, CLenVT>
-]>;
+def SDT_RISCVCheriBoolUnaryChain
+    : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVT<2, YLenVT>]>;
 
-def SDT_RISCVCheriBoolBinary : SDTypeProfile<1, 2, [
-  SDTCisInt<0>, SDTCisVT<1, CLenVT>, SDTCisVT<2, CLenVT>
-]>;
+def SDT_RISCVCheriBoolBinary
+    : SDTypeProfile<
+          1, 2, [SDTCisInt<0>, SDTCisVT<1, YLenVT>, SDTCisVT<2, YLenVT>]>;
 
 // Target-dependent nodes.
 def riscv_cap_call        : RVSDNode<"CAP_CALL", SDT_RISCVCapCall,
@@ -53,10 +51,11 @@ def riscv_clgc            : RVSDNode<"CLGC", SDT_RISCVSymLoad,
 def riscv_cla_tls_ie      : RVSDNode<"CLA_TLS_IE", SDT_RISCVSymLoad,
                                    [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
 def riscv_clc_tls_gd      : RVSDNode<"CLC_TLS_GD", SDT_RISCVSymLoad>;
-def riscv_cap_bounds_set  : RVSDNode<"BOUNDS_SET",
-                                   SDTypeProfile<1, 2, [SDTCisVT<0, CLenVT>,
-                                                 SDTCisVT<1, CLenVT>,
-                                                 SDTCisVT<2, XLenVT>]>>;
+def riscv_cap_bounds_set
+    : RVSDNode<"BOUNDS_SET",
+               SDTypeProfile<1, 2,
+                             [SDTCisVT<0, YLenVT>, SDTCisVT<1, YLenVT>,
+                              SDTCisVT<2, XLenVT>]>>;
 
 //===----------------------------------------------------------------------===//
 // Operand and SDNode transformation definitions.
@@ -69,9 +68,7 @@ def CCallSymbol : AsmOperandClass {
   let ParserMethod = "parseCallSymbol<true>";
 }
 
-def cap_call_symbol : Operand<CLenVT> {
-  let ParserMatchClass = CCallSymbol;
-}
+def cap_call_symbol : Operand<YLenVT> { let ParserMatchClass = CCallSymbol; }
 
 def PseudoCJumpSymbol : AsmOperandClass {
   let Name = "PseudoCJumpSymbol";
@@ -80,7 +77,7 @@ def PseudoCJumpSymbol : AsmOperandClass {
   let ParserMethod = "parsePseudoJumpSymbol<true>";
 }
 
-def pseudo_cap_jump_symbol : Operand<CLenVT> {
+def pseudo_cap_jump_symbol : Operand<YLenVT> {
   let ParserMatchClass = PseudoCJumpSymbol;
 }
 
@@ -99,11 +96,11 @@ def tprel_cincoffset_symbol : Operand<XLenVT> {
 def CheriZeroOffsetMemOpOperand : AsmOperandClass {
   let Name = "CheriZeroOffsetMemOpOperand";
   let RenderMethod = "addRegOperands";
-  let PredicateMethod = "isGPCR";
+  let PredicateMethod = "isYGPR";
   let ParserMethod = "parseZeroOffsetMemOp";
 }
 
-def GPCRMemZeroOffset : RegisterOperand<GPCR> {
+def YGPRMemZeroOffset : RegisterOperand<YGPR> {
   let ParserMatchClass = CheriZeroOffsetMemOpOperand;
   let PrintMethod = "printZeroOffsetMemOp";
 }
@@ -151,24 +148,25 @@ include "RISCVInstrFormatsXCheri.td"
 // Instruction Class Templates
 //===----------------------------------------------------------------------===//
 
-let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
-class Cheri_r<bits<5> funct5, string opcodestr, RegisterClass rdClass=GPR,
-              DAGOperand rs1Operand=GPCR>
+let hasSideEffects = 0, mayLoad = 0,
+    mayStore = 0 in class Cheri_r<bits<5> funct5, string opcodestr,
+                                  RegisterClass rdClass = GPR,
+                                  DAGOperand rs1Operand = YGPR>
     : RVInstCheriSrcDst<0x7f, funct5, 0, OPC_CHERI, (outs rdClass:$rd),
                         (ins rs1Operand:$rs1), opcodestr, "$rd, $rs1">;
 
-let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
-class Cheri_rr<bits<7> funct7, string opcodestr, RegisterClass rdClass=GPCR,
-               RegisterClass rs2Class=GPR, RegisterClass rs1Class=GPCR>
+let hasSideEffects = 0, mayLoad = 0,
+    mayStore = 0 in class Cheri_rr<
+        bits<7> funct7, string opcodestr, RegisterClass rdClass = YGPR,
+        RegisterClass rs2Class = GPR, RegisterClass rs1Class = YGPR>
     : RVInstR<funct7, 0, OPC_CHERI, (outs rdClass:$rd),
-              (ins rs1Class:$rs1, rs2Class:$rs2),
-              opcodestr, "$rd, $rs1, $rs2">;
+              (ins rs1Class:$rs1, rs2Class:$rs2), opcodestr, "$rd, $rs1, $rs2">;
 
-let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
-class Cheri_ri<bits<3> funct3, string opcodestr, bit simm>
-    : RVInstI<funct3, OPC_CHERI, (outs GPCR:$rd),
-              (ins GPCR:$rs1, !if(simm,simm12,uimm12):$imm12),
-              opcodestr, "$rd, $rs1, $imm12">;
+let hasSideEffects = 0, mayLoad = 0,
+    mayStore = 0 in class Cheri_ri<bits<3> funct3, string opcodestr, bit simm>
+    : RVInstI<funct3, OPC_CHERI, (outs YGPR:$rd),
+              (ins YGPR:$rs1, !if(simm, simm12, uimm12):$imm12), opcodestr,
+              "$rd, $rs1, $imm12">;
 
 let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
 class Cheri_clear<bits<5> funct5, string opcodestr>
@@ -196,58 +194,57 @@ class CheriStoreCond_r<bits<5> op, string opcodestr, RegisterClass rs2Class,
                         (ins rs2Class:$rs2, rs1Operand:$rs1),
                         opcodestr, "$rs2, $rs1">;
 
-let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
-class LR_C_r<bit aq, bit rl, bits<3> funct3, string opcodestr>
-    : RVInstRAtomic<0b00010, aq, rl, funct3, OPC_AMO,
-                    (outs GPCR:$rd), (ins GPRMemZeroOffset:$rs1),
-                    opcodestr, "$rd, $rs1"> {
+let hasSideEffects = 0, mayLoad = 1,
+    mayStore =
+        0 in class LR_C_r<bit aq, bit rl, bits<3> funct3, string opcodestr>
+    : RVInstRAtomic<0b00010, aq, rl, funct3, OPC_AMO, (outs YGPR:$rd),
+                    (ins GPRMemZeroOffset:$rs1), opcodestr, "$rd, $rs1"> {
   let rs2 = 0;
 }
 
-multiclass LR_C_r_aq_rl<string clenstr, bits<3> funct3, string opcodestr> {
-  def _ # clenstr       : LR_C_r<0, 0, funct3, opcodestr>;
-  def _AQ_ # clenstr    : LR_C_r<1, 0, funct3, opcodestr # ".aq">;
-  def _RL_ # clenstr    : LR_C_r<0, 1, funct3, opcodestr # ".rl">;
-  def _AQ_RL_ # clenstr : LR_C_r<1, 1, funct3, opcodestr # ".aqrl">;
+multiclass LR_C_r_aq_rl<string YLenstr, bits<3> funct3, string opcodestr> {
+  def _#YLenstr : LR_C_r<0, 0, funct3, opcodestr>;
+  def _AQ_#YLenstr : LR_C_r<1, 0, funct3, opcodestr#".aq">;
+  def _RL_#YLenstr : LR_C_r<0, 1, funct3, opcodestr#".rl">;
+  def _AQ_RL_#YLenstr : LR_C_r<1, 1, funct3, opcodestr#".aqrl">;
 }
 
-let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in
-class AMO_C_rr<bits<5> funct5, bit aq, bit rl, bits<3> funct3, string opcodestr,
-               RegisterClass rdClass>
-    : RVInstRAtomic<funct5, aq, rl, funct3, OPC_AMO,
-                    (outs rdClass:$rd), (ins GPRMemZeroOffset:$rs1, GPCR:$rs2),
-                    opcodestr, "$rd, $rs2, $rs1">;
+let hasSideEffects = 0, mayLoad = 1,
+    mayStore =
+        1 in class AMO_C_rr<bits<5> funct5, bit aq, bit rl, bits<3> funct3,
+                            string opcodestr, RegisterClass rdClass>
+    : RVInstRAtomic<funct5, aq, rl, funct3, OPC_AMO, (outs rdClass:$rd),
+                    (ins GPRMemZeroOffset:$rs1, YGPR:$rs2), opcodestr,
+                    "$rd, $rs2, $rs1">;
 
-multiclass AMO_C_rr_aq_rl<string clenstr, bits<5> funct5, bits<3> funct3,
+multiclass AMO_C_rr_aq_rl<string YLenstr, bits<5> funct5, bits<3> funct3,
                           string opcodestr, RegisterClass rdClass> {
-  def _ # clenstr       : AMO_C_rr<funct5, 0, 0, funct3, opcodestr, rdClass>;
-  def _AQ_ # clenstr    : AMO_C_rr<funct5, 1, 0, funct3, opcodestr # ".aq",
-                                   rdClass>;
-  def _RL_ # clenstr    : AMO_C_rr<funct5, 0, 1, funct3, opcodestr # ".rl",
-                                   rdClass>;
-  def _AQ_RL_ # clenstr : AMO_C_rr<funct5, 1, 1, funct3, opcodestr # ".aqrl",
-                                   rdClass>;
+  def _#YLenstr : AMO_C_rr<funct5, 0, 0, funct3, opcodestr, rdClass>;
+  def _AQ_#YLenstr : AMO_C_rr<funct5, 1, 0, funct3, opcodestr#".aq", rdClass>;
+  def _RL_#YLenstr : AMO_C_rr<funct5, 0, 1, funct3, opcodestr#".rl", rdClass>;
+  def _AQ_RL_#YLenstr
+      : AMO_C_rr<funct5, 1, 1, funct3, opcodestr#".aqrl", rdClass>;
 }
 
 multiclass CheriLoad_ri<bits<3> funct3, string opcodestr> {
   let hasSideEffects = 0, mayLoad = 1, mayStore = 0,
-      DecoderNamespace = "CapModeOnly_" in
-  def "" : RVInstI<funct3, OPC_LOAD, (outs GPR:$rd),
-                   (ins GPCR:$rs1, simm12:$imm12), "c" # opcodestr,
-                   "$rd, ${imm12}(${rs1})">;
-  def : InstAlias<opcodestr # " $rd, ${imm12}(${rs1})",
-                  (!cast<Instruction>(NAME) GPR:$rd, GPCR:$rs1, simm12:$imm12),
+      DecoderNamespace = "CapModeOnly_" in def ""
+      : RVInstI<funct3, OPC_LOAD, (outs GPR:$rd),
+                (ins YGPR:$rs1, simm12:$imm12), "c"#opcodestr,
+                "$rd, ${imm12}(${rs1})">;
+  def : InstAlias<opcodestr#" $rd, ${imm12}(${rs1})",
+                  (!cast<Instruction>(NAME) GPR:$rd, YGPR:$rs1, simm12:$imm12),
                   0>;
 }
 
 multiclass CheriStore_ri<bits<3> funct3, string opcodestr> {
   let hasSideEffects = 0, mayLoad = 0, mayStore = 1,
-      DecoderNamespace = "CapModeOnly_" in
-  def "" : RVInstS<funct3, OPC_STORE, (outs),
-                   (ins GPR:$rs2, GPCR:$rs1, simm12:$imm12),
-                   "c" # opcodestr, "$rs2, ${imm12}(${rs1})">;
-  def : InstAlias<opcodestr # "$rs2, ${imm12}(${rs1})",
-                  (!cast<Instruction>(NAME) GPR:$rs2, GPCR:$rs1, simm12:$imm12),
+      DecoderNamespace = "CapModeOnly_" in def ""
+      : RVInstS<funct3, OPC_STORE, (outs),
+                (ins GPR:$rs2, YGPR:$rs1, simm12:$imm12), "c"#opcodestr,
+                "$rs2, ${imm12}(${rs1})">;
+  def : InstAlias<opcodestr#"$rs2, ${imm12}(${rs1})",
+                  (!cast<Instruction>(NAME) GPR:$rs2, YGPR:$rs1, simm12:$imm12),
                   0>;
 }
 
@@ -255,14 +252,14 @@ multiclass CheriStore_ri<bits<3> funct3, string opcodestr> {
 multiclass CLR_r<bit aq, bit rl, bits<3> funct3, string opcodestr,
                  string Namespace> {
   let hasSideEffects = 0, mayLoad = 1, mayStore = 0,
-      DecoderNamespace = Namespace in
-  def "" : RVInstRAtomic<0b00010, aq, rl, funct3, OPC_AMO,
-                         (outs GPR:$rd), (ins GPCRMemZeroOffset:$rs1),
-                         "c" # opcodestr, "$rd, $rs1"> {
+      DecoderNamespace = Namespace in def ""
+      : RVInstRAtomic<0b00010, aq, rl, funct3, OPC_AMO, (outs GPR:$rd),
+                      (ins YGPRMemZeroOffset:$rs1), "c"#opcodestr,
+                      "$rd, $rs1"> {
     let rs2 = 0;
   }
-  def : InstAlias<opcodestr # "$rd, $rs1",
-                  (!cast<Instruction>(NAME) GPR:$rd, GPCRMemZeroOffset:$rs1),
+  def : InstAlias<opcodestr#"$rd, $rs1",
+                  (!cast<Instruction>(NAME) GPR:$rd, YGPRMemZeroOffset:$rs1),
                   0>;
 }
 
@@ -277,13 +274,14 @@ multiclass CLR_r_aq_rl<bits<3> funct3, string opcodestr,
 multiclass CAMO_rr<bits<5> funct5, bit aq, bit rl, bits<3> funct3,
                    string opcodestr, string Namespace> {
   let hasSideEffects = 0, mayLoad = 1, mayStore = 1,
-      DecoderNamespace = Namespace in
-  def "" : RVInstRAtomic<funct5, aq, rl, funct3, OPC_AMO,
-                         (outs GPR:$rd), (ins GPCRMemZeroOffset:$rs1, GPR:$rs2),
-                         "c" # opcodestr, "$rd, $rs2, $rs1">;
-  def : InstAlias<opcodestr # "$rd, $rs2, $rs1",
-                  (!cast<Instruction>(NAME) GPR:$rd, GPCRMemZeroOffset:$rs1,
-                   GPR:$rs2), 0>;
+      DecoderNamespace = Namespace in def ""
+      : RVInstRAtomic<funct5, aq, rl, funct3, OPC_AMO, (outs GPR:$rd),
+                      (ins YGPRMemZeroOffset:$rs1, GPR:$rs2), "c"#opcodestr,
+                      "$rd, $rs2, $rs1">;
+  def : InstAlias<opcodestr#"$rd, $rs2, $rs1",
+                  (!cast<Instruction>(NAME) GPR:$rd, YGPRMemZeroOffset:$rs1,
+                      GPR:$rs2),
+                  0>;
 }
 
 multiclass CAMO_rr_aq_rl<bits<5> funct5, bits<3> funct3, string opcodestr,
@@ -296,50 +294,50 @@ multiclass CAMO_rr_aq_rl<bits<5> funct5, bits<3> funct3, string opcodestr,
 
 multiclass CLR_C_r<bit aq, bit rl, bits<3> funct3, string opcodestr,
                    string Namespace> {
-let hasSideEffects = 0, mayLoad = 1, mayStore = 0,
-    DecoderNamespace = Namespace in
-  def "" : RVInstRAtomic<0b00010, aq, rl, funct3, OPC_AMO,
-                         (outs GPCR:$rd), (ins GPCRMemZeroOffset:$rs1),
-                         "c" # opcodestr, "$rd, $rs1"> {
+  let hasSideEffects = 0, mayLoad = 1, mayStore = 0,
+      DecoderNamespace = Namespace in def ""
+      : RVInstRAtomic<0b00010, aq, rl, funct3, OPC_AMO, (outs YGPR:$rd),
+                      (ins YGPRMemZeroOffset:$rs1), "c"#opcodestr,
+                      "$rd, $rs1"> {
     let rs2 = 0;
   }
-  def : InstAlias<opcodestr # "$rd, $rs1",
-                  (!cast<Instruction>(NAME) GPCR:$rd, GPCRMemZeroOffset:$rs1),
+  def : InstAlias<opcodestr#"$rd, $rs1",
+                  (!cast<Instruction>(NAME) YGPR:$rd, YGPRMemZeroOffset:$rs1),
                   0>;
 }
 
-multiclass CLR_C_r_aq_rl<string clenstr, bits<3> funct3, string opcodestr,
+multiclass CLR_C_r_aq_rl<string YLenstr, bits<3> funct3, string opcodestr,
                          string Namespace = "CapModeOnly_"> {
-  defm _ # clenstr       : CLR_C_r<0, 0, funct3, opcodestr, Namespace>;
-  defm _AQ_ # clenstr    : CLR_C_r<1, 0, funct3, opcodestr # ".aq", Namespace>;
-  defm _RL_ # clenstr    : CLR_C_r<0, 1, funct3, opcodestr # ".rl", Namespace>;
-  defm _AQ_RL_ # clenstr : CLR_C_r<1, 1, funct3, opcodestr # ".aqrl", Namespace>;
+  defm _#YLenstr : CLR_C_r<0, 0, funct3, opcodestr, Namespace>;
+  defm _AQ_#YLenstr : CLR_C_r<1, 0, funct3, opcodestr#".aq", Namespace>;
+  defm _RL_#YLenstr : CLR_C_r<0, 1, funct3, opcodestr#".rl", Namespace>;
+  defm _AQ_RL_#YLenstr : CLR_C_r<1, 1, funct3, opcodestr#".aqrl", Namespace>;
 }
 
 multiclass CAMO_C_rr<bits<5> funct5, bit aq, bit rl, bits<3> funct3,
                 string opcodestr, RegisterClass rdClass, string Namespace> {
   let hasSideEffects = 0, mayLoad = 1, mayStore = 1,
-      DecoderNamespace = Namespace in
-  def "" : RVInstRAtomic<funct5, aq, rl, funct3, OPC_AMO,
-                         (outs rdClass:$rd),
-                         (ins GPCRMemZeroOffset:$rs1, GPCR:$rs2),
-                         "c" # opcodestr, "$rd, $rs2, $rs1">;
-  def : InstAlias<opcodestr # "$rd, $rs2, $rs1",
-                 (!cast<Instruction>(NAME) rdClass:$rd, GPCRMemZeroOffset:$rs1,
-                  GPCR:$rs2), 0>;
-}
-
-multiclass CAMO_C_rr_aq_rl<string clenstr, bits<5> funct5, bits<3> funct3,
-                          string opcodestr, RegisterClass rdClass,
-                          string Namespace = "CapModeOnly_"> {
-  defm _ # clenstr       : CAMO_C_rr<funct5, 0, 0, funct3, opcodestr, rdClass,
-                                     Namespace>;
-  defm _AQ_ # clenstr    : CAMO_C_rr<funct5, 1, 0, funct3, opcodestr # ".aq",
-                                     rdClass, Namespace>;
-  defm _RL_ # clenstr    : CAMO_C_rr<funct5, 0, 1, funct3, opcodestr # ".rl",
-                                     rdClass, Namespace>;
-  defm _AQ_RL_ # clenstr : CAMO_C_rr<funct5, 1, 1, funct3, opcodestr # ".aqrl",
-                                     rdClass, Namespace>;
+      DecoderNamespace = Namespace in def ""
+      : RVInstRAtomic<funct5, aq, rl, funct3, OPC_AMO, (outs rdClass:$rd),
+                      (ins YGPRMemZeroOffset:$rs1, YGPR:$rs2), "c"#opcodestr,
+                      "$rd, $rs2, $rs1">;
+  def : InstAlias<opcodestr#"$rd, $rs2, $rs1",
+                  (!cast<Instruction>(NAME) rdClass:$rd, YGPRMemZeroOffset:$rs1,
+                      YGPR:$rs2),
+                  0>;
+}
+
+multiclass CAMO_C_rr_aq_rl<string YLenstr, bits<5> funct5, bits<3> funct3,
+                           string opcodestr, RegisterClass rdClass,
+                           string Namespace = "CapModeOnly_"> {
+  defm _#YLenstr
+      : CAMO_C_rr<funct5, 0, 0, funct3, opcodestr, rdClass, Namespace>;
+  defm _AQ_#YLenstr
+      : CAMO_C_rr<funct5, 1, 0, funct3, opcodestr#".aq", rdClass, Namespace>;
+  defm _RL_#YLenstr
+      : CAMO_C_rr<funct5, 0, 1, funct3, opcodestr#".rl", rdClass, Namespace>;
+  defm _AQ_RL_#YLenstr
+      : CAMO_C_rr<funct5, 1, 1, funct3, opcodestr#".aqrl", rdClass, Namespace>;
 }
 
 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
@@ -354,16 +352,16 @@ class CCheriStackStore<bits<3> funct3, string OpcodeStr,
     : RVInst16CSS<funct3, 0b10, (outs), (ins cls:$rs2, CSP:$rs1, opnd:$imm),
                   OpcodeStr, "$rs2, ${imm}(${rs1})">;
 
-let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
-class CCheriLoad_ri<bits<3> funct3, string OpcodeStr,
-                    RegisterClass cls, DAGOperand opnd>
-    : RVInst16CL<funct3, 0b00, (outs cls:$rd), (ins GPCRC:$rs1, opnd:$imm),
+let hasSideEffects = 0, mayLoad = 1,
+    mayStore = 0 in class CCheriLoad_ri<bits<3> funct3, string OpcodeStr,
+                                        RegisterClass cls, DAGOperand opnd>
+    : RVInst16CL<funct3, 0b00, (outs cls:$rd), (ins YGPRC:$rs1, opnd:$imm),
                  OpcodeStr, "$rd, ${imm}(${rs1})">;
 
-let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
-class CCheriStore_rri<bits<3> funct3, string OpcodeStr,
-                      RegisterClass cls, DAGOperand opnd>
-    : RVInst16CS<funct3, 0b00, (outs), (ins cls:$rs2, GPCRC:$rs1, opnd:$imm),
+let hasSideEffects = 0, mayLoad = 0,
+    mayStore = 1 in class CCheriStore_rri<bits<3> funct3, string OpcodeStr,
+                                          RegisterClass cls, DAGOperand opnd>
+    : RVInst16CS<funct3, 0b00, (outs), (ins cls:$rs2, YGPRC:$rs1, opnd:$imm),
                  OpcodeStr, "$rs2, ${imm}(${rs1})">;
 
 //===----------------------------------------------------------------------===//
@@ -383,9 +381,8 @@ def CGetHigh   : Cheri_r<0x17, "cgethigh">;
 def CGetTop    : Cheri_r<0x18, "cgettop">;
 // For backwards compatibility we still accept cgetaddr from assembly.
 let mayStore = false, mayLoad = false, Size = 4, isCodeGenOnly = false,
-hasSideEffects = false in
-def PseudoCGetAddr : Pseudo<(outs GPR:$rd), (ins GPCR:$cs1), [],
-                            "cgetaddr", "$rd, $cs1">;
+    hasSideEffects = false in def PseudoCGetAddr
+    : Pseudo<(outs GPR:$rd), (ins YGPR:$cs1), [], "cgetaddr", "$rd, $cs1">;
 }
 
 let Predicates = [HasCheri, HasNoCheriot] in {
@@ -393,14 +390,14 @@ let Predicates = [HasCheri, HasNoCheriot] in {
 }
 
 let Predicates = [HasCheriot] in {
-  def : InstAlias<"ct.cgetperm $rd, $rs1", (CGetPerm GPR:$rd, GPCR:$rs1)>;
-  def : InstAlias<"ct.cgettype $rd, $rs1", (CGetType GPR:$rd, GPCR:$rs1)>;
-  def : InstAlias<"ct.cgetbase $rd, $rs1", (CGetBase GPR:$rd, GPCR:$rs1)>;
-  def : InstAlias<"ct.cgetlen $rd, $rs1", (CGetLen GPR:$rd, GPCR:$rs1)>;
-  def : InstAlias<"ct.cgettag $rd, $rs1", (CGetTag GPR:$rd, GPCR:$rs1)>;
-  def : InstAlias<"ct.cgethigh $rd, $rs1", (CGetHigh GPR:$rd, GPCR:$rs1)>;
-  def : InstAlias<"ct.cgettop $rd, $rs1", (CGetTop GPR:$rd, GPCR:$rs1)>;
-  def : InstAlias<"ct.cgetaddr $rd, $rs1", (PseudoCGetAddr GPR:$rd, GPCR:$rs1)>;
+  def : InstAlias<"ct.cgetperm $rd, $rs1", (CGetPerm GPR:$rd, YGPR:$rs1)>;
+  def : InstAlias<"ct.cgettype $rd, $rs1", (CGetType GPR:$rd, YGPR:$rs1)>;
+  def : InstAlias<"ct.cgetbase $rd, $rs1", (CGetBase GPR:$rd, YGPR:$rs1)>;
+  def : InstAlias<"ct.cgetlen $rd, $rs1", (CGetLen GPR:$rd, YGPR:$rs1)>;
+  def : InstAlias<"ct.cgettag $rd, $rs1", (CGetTag GPR:$rd, YGPR:$rs1)>;
+  def : InstAlias<"ct.cgethigh $rd, $rs1", (CGetHigh GPR:$rd, YGPR:$rs1)>;
+  def : InstAlias<"ct.cgettop $rd, $rs1", (CGetTop GPR:$rd, YGPR:$rs1)>;
+  def : InstAlias<"ct.cgetaddr $rd, $rs1", (PseudoCGetAddr GPR:$rd, YGPR:$rs1)>;
 }
 
 //===----------------------------------------------------------------------===//
@@ -408,72 +405,69 @@ let Predicates = [HasCheriot] in {
 //===----------------------------------------------------------------------===//
 
 let Predicates = [HasCheri] in {
-let defsCanBeSealed = 1 in
-def CSeal           : Cheri_rr<0xb, "cseal", GPCR, GPCR>;
-def CUnseal         : Cheri_rr<0xc, "cunseal", GPCR, GPCR>;
-def CAndPerm        : Cheri_rr<0xd, "candperm">;
-def CSetFlags       : Cheri_rr<0xe, "csetflags">;
-def CSetOffset      : Cheri_rr<0xf, "csetoffset">;
-def CSetAddr        : Cheri_rr<0x10, "csetaddr">;
-def CSetHigh        : Cheri_rr<0x16, "csethigh">;
-let isReMaterializable = 1, isAsCheapAsAMove = 1 in
-def CIncOffset      : Cheri_rr<0x11, "cincoffset">;
-let isReMaterializable = 1, isAsCheapAsAMove = 1 in
-def CIncOffsetImm   : Cheri_ri<0x1, "cincoffset", 1>;
-def CSetBounds      : Cheri_rr<0x8, "csetbounds">;
-def CSetBoundsExact : Cheri_rr<0x9, "csetboundsexact">;
-def CSetBoundsImm   : Cheri_ri<0x2, "csetbounds", 0>;
-def CSetBoundsRoundDown : Cheri_rr<0xA, "csetboundsrounddown">;
-def CClearTag       : Cheri_r<0xb, "ccleartag", GPCR>;
-let defsCanBeSealed = 1 in
-def CBuildCap       : Cheri_rr<0x1d, "cbuildcap", GPCR, GPCR, GPCRC0IsDDC>;
-def CCopyType       : Cheri_rr<0x1e, "ccopytype", GPCR, GPCR>;
-let defsCanBeSealed = 1 in
-def CCSeal          : Cheri_rr<0x1f, "ccseal", GPCR, GPCR>;
-let defsCanBeSealed = 1 in
-def CSealEntry      : Cheri_r<0x11, "csealentry", GPCR>;
-
-def : InstAlias<"cincoffsetimm $cd, $cs1, $imm",
-                (CIncOffsetImm GPCR:$cd, GPCR:$cs1, simm12:$imm), 0>;
-def : InstAlias<"csetboundsimm $cd, $cs1, $imm",
-                (CSetBoundsImm GPCR:$cd, GPCR:$cs1, uimm12:$imm), 0>;
+  let defsCanBeSealed = 1 in def CSeal : Cheri_rr<0xb, "cseal", YGPR, YGPR>;
+  def CUnseal : Cheri_rr<0xc, "cunseal", YGPR, YGPR>;
+  def CAndPerm : Cheri_rr<0xd, "candperm">;
+  def CSetFlags : Cheri_rr<0xe, "csetflags">;
+  def CSetOffset : Cheri_rr<0xf, "csetoffset">;
+  def CSetAddr : Cheri_rr<0x10, "csetaddr">;
+  def CSetHigh : Cheri_rr<0x16, "csethigh">;
+  let isReMaterializable = 1,
+      isAsCheapAsAMove = 1 in def CIncOffset : Cheri_rr<0x11, "cincoffset">;
+  let isReMaterializable = 1, isAsCheapAsAMove = 1 in def CIncOffsetImm
+      : Cheri_ri<0x1, "cincoffset", 1>;
+  def CSetBounds : Cheri_rr<0x8, "csetbounds">;
+  def CSetBoundsExact : Cheri_rr<0x9, "csetboundsexact">;
+  def CSetBoundsImm : Cheri_ri<0x2, "csetbounds", 0>;
+  def CSetBoundsRoundDown : Cheri_rr<0xA, "csetboundsrounddown">;
+  def CClearTag : Cheri_r<0xb, "ccleartag", YGPR>;
+  let defsCanBeSealed =
+      1 in def CBuildCap : Cheri_rr<0x1d, "cbuildcap", YGPR, YGPR, YGPRX0IsDDC>;
+  def CCopyType : Cheri_rr<0x1e, "ccopytype", YGPR, YGPR>;
+  let defsCanBeSealed = 1 in def CCSeal : Cheri_rr<0x1f, "ccseal", YGPR, YGPR>;
+  let defsCanBeSealed = 1 in def CSealEntry : Cheri_r<0x11, "csealentry", YGPR>;
+
+  def : InstAlias<"cincoffsetimm $cd, $cs1, $imm",
+                  (CIncOffsetImm YGPR:$cd, YGPR:$cs1, simm12:$imm), 0>;
+  def : InstAlias<"csetboundsimm $cd, $cs1, $imm",
+                  (CSetBoundsImm YGPR:$cd, YGPR:$cs1, uimm12:$imm), 0>;
 }
 
 let Predicates = [HasCheriot] in {
-  def : InstAlias<"ct.cseal $rd, $rs1, $rs2", (CSeal GPCR:$rd, GPCR:$rs1,
-                                                  GPCR:$rs2)>;
-  def : InstAlias<"ct.cunseal $rd, $rs1, $rs2", (CUnseal GPCR:$rd, GPCR:$rs1,
-                                                    GPCR:$rs2)>;
-  def : InstAlias<"ct.candperm $rd, $rs1, $rs2", (CAndPerm GPCR:$rd, GPCR:$rs1,
+  def : InstAlias<"ct.cseal $rd, $rs1, $rs2", (CSeal YGPR:$rd, YGPR:$rs1,
+                                                  YGPR:$rs2)>;
+  def : InstAlias<"ct.cunseal $rd, $rs1, $rs2", (CUnseal YGPR:$rd, YGPR:$rs1,
+                                                    YGPR:$rs2)>;
+  def : InstAlias<"ct.candperm $rd, $rs1, $rs2", (CAndPerm YGPR:$rd, YGPR:$rs1,
                                                      GPR:$rs2)>;
-  def : InstAlias<"ct.csetaddr $rd, $rs1, $rs2", (CSetAddr GPCR:$rd, GPCR:$rs1,
+  def : InstAlias<"ct.csetaddr $rd, $rs1, $rs2", (CSetAddr YGPR:$rd, YGPR:$rs1,
                                                      GPR:$rs2)>;
-  def : InstAlias<"ct.csethigh $rd, $rs1, $rs2", (CSetHigh GPCR:$rd, GPCR:$rs1,
+  def : InstAlias<"ct.csethigh $rd, $rs1, $rs2", (CSetHigh YGPR:$rd, YGPR:$rs1,
                                                      GPR:$rs2)>;
   def : InstAlias<"ct.cincaddr $rd, $rs1, $rs2",
-                  (CIncOffset GPCR:$rd, GPCR:$rs1, GPR:$rs2), 0>;
-  def : InstAlias<"ct.cincoffset $rd, $rs1, $rs2", (CIncOffset GPCR:$rd,
-                                                       GPCR:$rs1, GPR:$rs2)>;
+                  (CIncOffset YGPR:$rd, YGPR:$rs1, GPR:$rs2), 0>;
+  def : InstAlias<"ct.cincoffset $rd, $rs1, $rs2", (CIncOffset YGPR:$rd,
+                                                       YGPR:$rs1, GPR:$rs2)>;
   def : InstAlias<"ct.cincaddr $rd, $rs1, $rs2",
-                  (CIncOffsetImm GPCR:$rd, GPCR:$rs1, simm12:$rs2), 0>;
-  def : InstAlias<"ct.cincoffset $rd, $rs1, $rs2", (CIncOffsetImm GPCR:$rd,
-                                                       GPCR:$rs1, simm12:$rs2)>;
-  def : InstAlias<"ct.csetbounds $rd, $rs1, $rs2", (CSetBounds GPCR:$rd,
-                                                       GPCR:$rs1, GPR:$rs2)>;
+                  (CIncOffsetImm YGPR:$rd, YGPR:$rs1, simm12:$rs2), 0>;
+  def : InstAlias<"ct.cincoffset $rd, $rs1, $rs2", (CIncOffsetImm YGPR:$rd,
+                                                       YGPR:$rs1, simm12:$rs2)>;
+  def : InstAlias<"ct.csetbounds $rd, $rs1, $rs2", (CSetBounds YGPR:$rd,
+                                                       YGPR:$rs1, GPR:$rs2)>;
   def : InstAlias<"ct.csetboundsexact $rd, $rs1, $rs2",
-                  (CSetBoundsExact GPCR:$rd, GPCR:$rs1, GPR:$rs2)>;
-  def : InstAlias<"ct.csetbounds $rd, $rs1, $rs2", (CSetBoundsImm GPCR:$rd,
-                                                       GPCR:$rs1, uimm12:$rs2)>;
+                  (CSetBoundsExact YGPR:$rd, YGPR:$rs1, GPR:$rs2)>;
+  def : InstAlias<"ct.csetbounds $rd, $rs1, $rs2", (CSetBoundsImm YGPR:$rd,
+                                                       YGPR:$rs1, uimm12:$rs2)>;
   def : InstAlias<"ct.csetboundsrounddown $rd, $rs1, $rs2",
-                  (CSetBoundsRoundDown GPCR:$rd, GPCR:$rs1, GPR:$rs2)>;
-  def : InstAlias<"ct.ccleartag $rd, $rs1", (CClearTag GPCR:$rd, GPCR:$rs1)>;
+                  (CSetBoundsRoundDown YGPR:$rd, YGPR:$rs1, GPR:$rs2)>;
+  def : InstAlias<"ct.ccleartag $rd, $rs1", (CClearTag YGPR:$rd, YGPR:$rs1)>;
 
   def : InstAlias<"ct.cincaddrimm $cd, $cs1, $imm",
-                  (CIncOffsetImm GPCR:$cd, GPCR:$cs1, simm12:$imm), 0>;
+                  (CIncOffsetImm YGPR:$cd, YGPR:$cs1, simm12:$imm), 0>;
   def : InstAlias<"ct.cincoffsetimm $cd, $cs1, $imm",
-                  (CIncOffsetImm GPCR:$cd, GPCR:$cs1, simm12:$imm), 0>;
+                  (CIncOffsetImm YGPR:$cd, YGPR:$cs1, simm12:$imm), 0>;
   def : InstAlias<"ct.csetboundsimm $cd, $cs1, $imm",
-                  (CSetBoundsImm GPCR:$cd, GPCR:$cs1, uimm12:$imm), 0>;
+                  (CSetBoundsImm YGPR:$cd, YGPR:$cs1, uimm12:$imm), 0>;
 }
 
 //===----------------------------------------------------------------------===//
@@ -481,19 +475,18 @@ let Predicates = [HasCheriot] in {
 //===----------------------------------------------------------------------===//
 
 let Predicates = [HasCheri] in {
-let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCodeGenOnly = 0,
-    isAsmParserOnly = 1 in
-def PseudoCSub : Pseudo<(outs GPR:$rd), (ins GPCR:$cs1, GPCR:$cs2), [],
-                        "csub", "$rd, $cs1, $cs2">;
-let isMoveReg = 1, isReMaterializable = 1, isAsCheapAsAMove = 1,
-    defsCanBeSealed = 1 in
-def CMove       : Cheri_r<0xa, "cmove", GPCR>;
+  let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCodeGenOnly = 0,
+      isAsmParserOnly = 1 in def PseudoCSub
+      : Pseudo<(outs GPR:$rd), (ins YGPR:$cs1, YGPR:$cs2), [], "csub",
+               "$rd, $cs1, $cs2">;
+  let isMoveReg = 1, isReMaterializable = 1, isAsCheapAsAMove = 1,
+      defsCanBeSealed = 1 in def CMove : Cheri_r<0xa, "cmove", YGPR>;
 }
 
 let Predicates = [HasCheriot] in {
-  def : InstAlias<"ct.cmove $rd, $rs1", (CMove GPCR:$rd, GPCR:$rs1)>;
-  def : InstAlias<"ct.csub $rd, $rs1, $rs2", (PseudoCSub GPR:$rd, GPCR:$rs1,
-                                                 GPCR:$rs2)>;
+  def : InstAlias<"ct.cmove $rd, $rs1", (CMove YGPR:$rd, YGPR:$rs1)>;
+  def : InstAlias<"ct.csub $rd, $rs1, $rs2", (PseudoCSub GPR:$rd, YGPR:$rs1,
+                                                 YGPR:$rs2)>;
 }
 
 //===----------------------------------------------------------------------===//
@@ -501,26 +494,28 @@ let Predicates = [HasCheriot] in {
 //===----------------------------------------------------------------------===//
 
 let Predicates = [HasCheri] in {
-let isCall = 1, hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
-def JALR_CAP : RVInstCheriSrcDst<0x7f, 0xc, 0, OPC_CHERI, (outs GPCR:$rd),
-                                 (ins GPCR:$rs1), "jalr.cap", "$rd, $rs1">;
+  let isCall = 1, hasSideEffects = 0, mayLoad = 0,
+      mayStore = 0 in def JALR_CAP
+      : RVInstCheriSrcDst<0x7f, 0xc, 0, OPC_CHERI, (outs YGPR:$rd),
+                          (ins YGPR:$rs1), "jalr.cap", "$rd, $rs1">;
 
-let isCall = 1, hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
-def JALR_PCC : RVInstCheriSrcDst<0x7f, 0x14, 0, OPC_CHERI, (outs GPR:$rd),
-                                 (ins GPR:$rs1), "jalr.pcc", "$rd, $rs1">;
+  let isCall = 1, hasSideEffects = 0, mayLoad = 0,
+      mayStore = 0 in def JALR_PCC
+      : RVInstCheriSrcDst<0x7f, 0x14, 0, OPC_CHERI, (outs GPR:$rd),
+                          (ins GPR:$rs1), "jalr.pcc", "$rd, $rs1">;
 
-let isCall = 1, hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
-def CInvoke : RVInstCheriTwoSrc<0x7e, 0x1, 0, OPC_CHERI, (outs),
-                                (ins GPCR:$rs1, GPCR:$rs2),
-                                "cinvoke", "$rs1, $rs2">;
+  let isCall = 1, hasSideEffects = 0, mayLoad = 0,
+      mayStore = 0 in def CInvoke
+      : RVInstCheriTwoSrc<0x7e, 0x1, 0, OPC_CHERI, (outs),
+                          (ins YGPR:$rs1, YGPR:$rs2), "cinvoke", "$rs1, $rs2">;
 
-def : InstAlias<"jalr.cap $cs1", (JALR_CAP C1, GPCR:$cs1), 1>;
-def : InstAlias<"jr.cap $cs1",   (JALR_CAP C0, GPCR:$cs1), 1>;
-def : InstAlias<"ret.cap",       (JALR_CAP C0,        C1), 2>;
+  def : InstAlias<"jalr.cap $cs1", (JALR_CAP X1_Y, YGPR:$cs1), 1>;
+  def : InstAlias<"jr.cap $cs1", (JALR_CAP X0_Y, YGPR:$cs1), 1>;
+  def : InstAlias<"ret.cap", (JALR_CAP X0_Y, X1_Y), 2>;
 
-def : InstAlias<"jalr.pcc $cs1", (JALR_PCC X1, GPR:$cs1), 1>;
-def : InstAlias<"jr.pcc $cs1",   (JALR_PCC X0, GPR:$cs1), 1>;
-def : InstAlias<"ret.pcc",       (JALR_PCC X0,       X1), 2>;
+  def : InstAlias<"jalr.pcc $cs1", (JALR_PCC X1, GPR:$cs1), 1>;
+  def : InstAlias<"jr.pcc $cs1", (JALR_PCC X0, GPR:$cs1), 1>;
+  def : InstAlias<"ret.pcc", (JALR_PCC X0, X1), 2>;
 }
 
 //===----------------------------------------------------------------------===//
@@ -528,19 +523,20 @@ def : InstAlias<"ret.pcc",       (JALR_PCC X0,       X1), 2>;
 //===----------------------------------------------------------------------===//
 
 let Predicates = [HasCheri] in {
-def CTestSubset : Cheri_rr<0x20, "ctestsubset", GPR, GPCR, GPCRC0IsDDC>;
-def CSEQX       : Cheri_rr<0x21, "csetequalexact", GPR, GPCR, GPCR>;
+  def CTestSubset : Cheri_rr<0x20, "ctestsubset", GPR, YGPR, YGPRX0IsDDC>;
+  def CSEQX : Cheri_rr<0x21, "csetequalexact", GPR, YGPR, YGPR>;
 
-def : InstAlias<"cseqx $rd, $cs1, $cs2", (CSEQX GPR:$rd, GPCR:$cs1, GPCR:$cs2)>;
+  def : InstAlias<"cseqx $rd, $cs1, $cs2", (CSEQX GPR:$rd, YGPR:$cs1,
+                                               YGPR:$cs2)>;
 }
 
 let Predicates = [HasCheriot] in {
   def : InstAlias<"ct.ctestsubset $rd, $rs1, $rs2",
-                  (CTestSubset GPR:$rd, GPCRC0IsDDC:$rs1, GPCR:$rs2)>;
+                  (CTestSubset GPR:$rd, YGPRX0IsDDC:$rs1, YGPR:$rs2)>;
   def : InstAlias<"ct.csetequalexact $rd, $rs1, $rs2",
-                  (CSEQX GPR:$rd, GPCR:$rs1, GPCR:$rs2), 0>;
+                  (CSEQX GPR:$rd, YGPR:$rs1, YGPR:$rs2), 0>;
   def : InstAlias<"ct.cseqx $rd, $cs1, $cs2",
-                  (CSEQX GPR:$rd, GPCR:$cs1, GPCR:$cs2), 2>;
+                  (CSEQX GPR:$rd, YGPR:$cs1, YGPR:$cs2), 2>;
 }
 
 //===----------------------------------------------------------------------===//
@@ -548,24 +544,25 @@ let Predicates = [HasCheriot] in {
 //===----------------------------------------------------------------------===//
 
 let Predicates = [HasCheri] in {
-let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
-def CSpecialRW : RVInstCheriSCR<0x1, 0, OPC_CHERI, (outs GPCR:$rd),
-                                (ins special_capreg:$imm5, GPCR:$rs1),
-                                "cspecialrw", "$rd, $imm5, $rs1">;
+  let hasSideEffects = 1, mayLoad = 0,
+      mayStore = 0 in def CSpecialRW
+      : RVInstCheriSCR<0x1, 0, OPC_CHERI, (outs YGPR:$rd),
+                       (ins special_capreg:$imm5, YGPR:$rs1), "cspecialrw",
+                       "$rd, $imm5, $rs1">;
 
-def : InstAlias<"cspecialr $cd, $scr",
-                (CSpecialRW GPCR:$cd, special_capreg:$scr,           C0)>;
-def : InstAlias<"cspecialw $scr, $cs",
-                (CSpecialRW       C0, special_capreg:$scr, GPCRNoC0:$cs)>;
+  def : InstAlias<"cspecialr $cd, $scr", (CSpecialRW YGPR:$cd,
+                                             special_capreg:$scr, X0_Y)>;
+  def : InstAlias<"cspecialw $scr, $cs", (CSpecialRW X0_Y, special_capreg:$scr,
+                                             YGPRNoX0:$cs)>;
 }
 
 let Predicates = [HasCheriot] in {
   def : InstAlias<"ct.cspecialrw $rd, $imm5, $rs1",
-                  (CSpecialRW GPCR:$rd, special_capreg:$imm5, GPCR:$rs1)>;
+                  (CSpecialRW YGPR:$rd, special_capreg:$imm5, YGPR:$rs1)>;
   def : InstAlias<"ct.cspecialr $cd, $scr",
-                  (CSpecialRW GPCR:$cd, special_capreg:$scr, C0), 2>;
+                  (CSpecialRW YGPR:$cd, special_capreg:$scr, X0_Y), 2>;
   def : InstAlias<"ct.cspecialw $scr, $cs",
-                  (CSpecialRW C0, special_capreg:$scr, GPCRNoC0:$cs), 2>;
+                  (CSpecialRW X0_Y, special_capreg:$scr, YGPRNoX0:$cs), 2>;
 }
 
 //===----------------------------------------------------------------------===//
@@ -603,8 +600,9 @@ let Predicates = [HasCheriot] in {
 // Tag-Memory Access Instructions
 //===----------------------------------------------------------------------===//
 
-let Predicates = [HasCheri], hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
-def CLoadTags : Cheri_r<0x12, "cloadtags", GPR, GPCRMemZeroOffset>;
+let Predicates = [HasCheri], hasSideEffects = 0, mayLoad = 1,
+    mayStore =
+        0 in def CLoadTags : Cheri_r<0x12, "cloadtags", GPR, YGPRMemZeroOffset>;
 
 //===----------------------------------------------------------------------===//
 // Memory-Access with Explicit Address Type Instructions
@@ -624,11 +622,11 @@ def LD_DDC  : CheriLoad_r<0b00011, "ld.ddc",  GPR, GPRMemZeroOffset>;
 }
 
 let DecoderNamespace = "RISCV32Only_",
-    Predicates = [HasCheri, IsRV32] in
-def LC_DDC_64  : CheriLoad_r<0b00011, "lc.ddc", GPCR, GPRMemZeroOffset>;
+    Predicates = [HasCheri, IsRV32] in def LC_DDC_64
+    : CheriLoad_r<0b00011, "lc.ddc", YGPR, GPRMemZeroOffset>;
 
-let Predicates = [HasCheri, IsRV64] in
-def LC_DDC_128 : CheriLoad_r<0b10111, "lc.ddc", GPCR, GPRMemZeroOffset>;
+let Predicates = [HasCheri, IsRV64] in def LC_DDC_128
+    : CheriLoad_r<0b10111, "lc.ddc", YGPR, GPRMemZeroOffset>;
 
 let Predicates = [HasCheri] in {
 def SB_DDC  : CheriStore_r<0b00000, "sb.ddc", GPR, GPRMemZeroOffset>;
@@ -641,48 +639,48 @@ def SD_DDC  : CheriStore_r<0b00011, "sd.ddc", GPR, GPRMemZeroOffset>;
 }
 
 let DecoderNamespace = "RISCV32Only_",
-    Predicates = [HasCheri, IsRV32] in
-def SC_DDC_64  : CheriStore_r<0b00011, "sc.ddc", GPCR, GPRMemZeroOffset>;
+    Predicates = [HasCheri, IsRV32] in def SC_DDC_64
+    : CheriStore_r<0b00011, "sc.ddc", YGPR, GPRMemZeroOffset>;
 
-let Predicates = [HasCheri, IsRV64] in
-def SC_DDC_128 : CheriStore_r<0b00100, "sc.ddc", GPCR, GPRMemZeroOffset>;
+let Predicates = [HasCheri, IsRV64] in def SC_DDC_128
+    : CheriStore_r<0b00100, "sc.ddc", YGPR, GPRMemZeroOffset>;
 
 let Predicates = [HasCheri] in {
-def LB_CAP  : CheriLoad_r<0b01000, "lb.cap",  GPR, GPCRMemZeroOffset>;
-def LH_CAP  : CheriLoad_r<0b01001, "lh.cap",  GPR, GPCRMemZeroOffset>;
-def LW_CAP  : CheriLoad_r<0b01010, "lw.cap",  GPR, GPCRMemZeroOffset>;
-def LBU_CAP : CheriLoad_r<0b01100, "lbu.cap", GPR, GPCRMemZeroOffset>;
-def LHU_CAP : CheriLoad_r<0b01101, "lhu.cap", GPR, GPCRMemZeroOffset>;
+  def LB_CAP : CheriLoad_r<0b01000, "lb.cap", GPR, YGPRMemZeroOffset>;
+  def LH_CAP : CheriLoad_r<0b01001, "lh.cap", GPR, YGPRMemZeroOffset>;
+  def LW_CAP : CheriLoad_r<0b01010, "lw.cap", GPR, YGPRMemZeroOffset>;
+  def LBU_CAP : CheriLoad_r<0b01100, "lbu.cap", GPR, YGPRMemZeroOffset>;
+  def LHU_CAP : CheriLoad_r<0b01101, "lhu.cap", GPR, YGPRMemZeroOffset>;
 }
 
 let Predicates = [HasCheri, IsRV64] in {
-def LWU_CAP : CheriLoad_r<0b01110, "lwu.cap", GPR, GPCRMemZeroOffset>;
-def LD_CAP  : CheriLoad_r<0b01011, "ld.cap",  GPR, GPCRMemZeroOffset>;
+  def LWU_CAP : CheriLoad_r<0b01110, "lwu.cap", GPR, YGPRMemZeroOffset>;
+  def LD_CAP : CheriLoad_r<0b01011, "ld.cap", GPR, YGPRMemZeroOffset>;
 }
 
 let DecoderNamespace = "RISCV32Only_",
-    Predicates = [HasCheri, IsRV32] in
-def LC_CAP_64  : CheriLoad_r<0b01011, "lc.cap", GPCR, GPCRMemZeroOffset>;
+    Predicates = [HasCheri, IsRV32] in def LC_CAP_64
+    : CheriLoad_r<0b01011, "lc.cap", YGPR, YGPRMemZeroOffset>;
 
-let Predicates = [HasCheri, IsRV64] in
-def LC_CAP_128 : CheriLoad_r<0b11111, "lc.cap", GPCR, GPCRMemZeroOffset>;
+let Predicates = [HasCheri, IsRV64] in def LC_CAP_128
+    : CheriLoad_r<0b11111, "lc.cap", YGPR, YGPRMemZeroOffset>;
 
 let Predicates = [HasCheri] in {
-def SB_CAP  : CheriStore_r<0b01000, "sb.cap", GPR, GPCRMemZeroOffset>;
-def SH_CAP  : CheriStore_r<0b01001, "sh.cap", GPR, GPCRMemZeroOffset>;
-def SW_CAP  : CheriStore_r<0b01010, "sw.cap", GPR, GPCRMemZeroOffset>;
+  def SB_CAP : CheriStore_r<0b01000, "sb.cap", GPR, YGPRMemZeroOffset>;
+  def SH_CAP : CheriStore_r<0b01001, "sh.cap", GPR, YGPRMemZeroOffset>;
+  def SW_CAP : CheriStore_r<0b01010, "sw.cap", GPR, YGPRMemZeroOffset>;
 }
 
 let Predicates = [HasCheri, IsRV64] in {
-def SD_CAP  : CheriStore_r<0b01011, "sd.cap", GPR, GPCRMemZeroOffset>;
+  def SD_CAP : CheriStore_r<0b01011, "sd.cap", GPR, YGPRMemZeroOffset>;
 }
 
 let DecoderNamespace = "RISCV32Only_",
-    Predicates = [HasCheri, IsRV32] in
-def SC_CAP_64  : CheriStore_r<0b01011, "sc.cap", GPCR, GPCRMemZeroOffset>;
+    Predicates = [HasCheri, IsRV32] in def SC_CAP_64
+    : CheriStore_r<0b01011, "sc.cap", YGPR, YGPRMemZeroOffset>;
 
-let Predicates = [HasCheri, IsRV64] in
-def SC_CAP_128 : CheriStore_r<0b01100, "sc.cap", GPCR, GPCRMemZeroOffset>;
+let Predicates = [HasCheri, IsRV64] in def SC_CAP_128
+    : CheriStore_r<0b01100, "sc.cap", YGPR, YGPRMemZeroOffset>;
 
 let Predicates = [HasCheri, HasStdExtA] in {
 def LR_B_DDC  : CheriLoad_r<0b10000, "lr.b.ddc",  GPR, GPRMemZeroOffset>;
@@ -694,27 +692,27 @@ let Predicates = [HasCheri, HasStdExtA, IsRV64] in
 def LR_D_DDC  : CheriLoad_r<0b10011, "lr.d.ddc",  GPR, GPRMemZeroOffset>;
 
 let DecoderNamespace = "RISCV32Only_",
-    Predicates = [HasCheri, HasStdExtA, IsRV32] in
-def LR_C_DDC_64  : CheriLoad_r<0b10011, "lr.c.ddc", GPCR, GPRMemZeroOffset>;
+    Predicates = [HasCheri, HasStdExtA, IsRV32] in def LR_C_DDC_64
+    : CheriLoad_r<0b10011, "lr.c.ddc", YGPR, GPRMemZeroOffset>;
 
-let Predicates = [HasCheri, HasStdExtA, IsRV64] in
-def LR_C_DDC_128 : CheriLoad_r<0b10100, "lr.c.ddc", GPCR, GPRMemZeroOffset>;
+let Predicates = [HasCheri, HasStdExtA, IsRV64] in def LR_C_DDC_128
+    : CheriLoad_r<0b10100, "lr.c.ddc", YGPR, GPRMemZeroOffset>;
 
 let Predicates = [HasCheri, HasStdExtA] in {
-def LR_B_CAP  : CheriLoad_r<0b11000, "lr.b.cap",  GPR, GPCRMemZeroOffset>;
-def LR_H_CAP  : CheriLoad_r<0b11001, "lr.h.cap",  GPR, GPCRMemZeroOffset>;
-def LR_W_CAP  : CheriLoad_r<0b11010, "lr.w.cap",  GPR, GPCRMemZeroOffset>;
+  def LR_B_CAP : CheriLoad_r<0b11000, "lr.b.cap", GPR, YGPRMemZeroOffset>;
+  def LR_H_CAP : CheriLoad_r<0b11001, "lr.h.cap", GPR, YGPRMemZeroOffset>;
+  def LR_W_CAP : CheriLoad_r<0b11010, "lr.w.cap", GPR, YGPRMemZeroOffset>;
 }
 
-let Predicates = [HasCheri, HasStdExtA, IsRV64] in
-def LR_D_CAP  : CheriLoad_r<0b11011, "lr.d.cap",  GPR, GPCRMemZeroOffset>;
+let Predicates = [HasCheri, HasStdExtA, IsRV64] in def LR_D_CAP
+    : CheriLoad_r<0b11011, "lr.d.cap", GPR, YGPRMemZeroOffset>;
 
 let DecoderNamespace = "RISCV32Only_",
-    Predicates = [HasCheri, HasStdExtA, IsRV32] in
-def LR_C_CAP_64  : CheriLoad_r<0b11011, "lr.c.cap", GPCR, GPCRMemZeroOffset>;
+    Predicates = [HasCheri, HasStdExtA, IsRV32] in def LR_C_CAP_64
+    : CheriLoad_r<0b11011, "lr.c.cap", YGPR, YGPRMemZeroOffset>;
 
-let Predicates = [HasCheri, HasStdExtA, IsRV64] in
-def LR_C_CAP_128 : CheriLoad_r<0b11100, "lr.c.cap", GPCR, GPCRMemZeroOffset>;
+let Predicates = [HasCheri, HasStdExtA, IsRV64] in def LR_C_CAP_128
+    : CheriLoad_r<0b11100, "lr.c.cap", YGPR, YGPRMemZeroOffset>;
 
 let Predicates = [HasCheri, HasStdExtA] in {
 def SC_B_DDC  : CheriStoreCond_r<0b10000, "sc.b.ddc",  GPR, GPRMemZeroOffset>;
@@ -726,83 +724,79 @@ let Predicates = [HasCheri, HasStdExtA, IsRV64] in
 def SC_D_DDC  : CheriStoreCond_r<0b10011, "sc.d.ddc",  GPR, GPRMemZeroOffset>;
 
 let DecoderNamespace = "RISCV32Only_",
-    Predicates = [HasCheri, HasStdExtA, IsRV32] in
-def SC_C_DDC_64  : CheriStoreCond_r<0b10011, "sc.c.ddc", GPCR, GPRMemZeroOffset>;
+    Predicates = [HasCheri, HasStdExtA, IsRV32] in def SC_C_DDC_64
+    : CheriStoreCond_r<0b10011, "sc.c.ddc", YGPR, GPRMemZeroOffset>;
 
-let Predicates = [HasCheri, HasStdExtA, IsRV64] in
-def SC_C_DDC_128 : CheriStoreCond_r<0b10100, "sc.c.ddc", GPCR, GPRMemZeroOffset>;
+let Predicates = [HasCheri, HasStdExtA, IsRV64] in def SC_C_DDC_128
+    : CheriStoreCond_r<0b10100, "sc.c.ddc", YGPR, GPRMemZeroOffset>;
 
 let Predicates = [HasCheri, HasStdExtA] in {
-def SC_B_CAP  : CheriStoreCond_r<0b11000, "sc.b.cap",  GPR, GPCRMemZeroOffset>;
-def SC_H_CAP  : CheriStoreCond_r<0b11001, "sc.h.cap",  GPR, GPCRMemZeroOffset>;
-def SC_W_CAP  : CheriStoreCond_r<0b11010, "sc.w.cap",  GPR, GPCRMemZeroOffset>;
+  def SC_B_CAP : CheriStoreCond_r<0b11000, "sc.b.cap", GPR, YGPRMemZeroOffset>;
+  def SC_H_CAP : CheriStoreCond_r<0b11001, "sc.h.cap", GPR, YGPRMemZeroOffset>;
+  def SC_W_CAP : CheriStoreCond_r<0b11010, "sc.w.cap", GPR, YGPRMemZeroOffset>;
 }
 
-let Predicates = [HasCheri, HasStdExtA, IsRV64] in
-def SC_D_CAP  : CheriStoreCond_r<0b11011, "sc.d.cap",  GPR, GPCRMemZeroOffset>;
+let Predicates = [HasCheri, HasStdExtA, IsRV64] in def SC_D_CAP
+    : CheriStoreCond_r<0b11011, "sc.d.cap", GPR, YGPRMemZeroOffset>;
 
 let DecoderNamespace = "RISCV32Only_",
-    Predicates = [HasCheri, HasStdExtA, IsRV32] in
-def SC_C_CAP_64  : CheriStoreCond_r<0b11011, "sc.c.cap", GPCR, GPCRMemZeroOffset>;
+    Predicates = [HasCheri, HasStdExtA, IsRV32] in def SC_C_CAP_64
+    : CheriStoreCond_r<0b11011, "sc.c.cap", YGPR, YGPRMemZeroOffset>;
 
-let Predicates = [HasCheri, HasStdExtA, IsRV64] in
-def SC_C_CAP_128 : CheriStoreCond_r<0b11100, "sc.c.cap", GPCR, GPCRMemZeroOffset>;
+let Predicates = [HasCheri, HasStdExtA, IsRV64] in def SC_C_CAP_128
+    : CheriStoreCond_r<0b11100, "sc.c.cap", YGPR, YGPRMemZeroOffset>;
 
 //===----------------------------------------------------------------------===//
 // Memory-Access Instructions
 //===----------------------------------------------------------------------===//
 
 let Predicates = [HasCheri, IsRV32, NotCapMode] in {
-let DecoderNamespace = "RISCV32Only_",
-    hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
-def LC_64  : RVInstI<0x3, OPC_LOAD, (outs GPCR:$rd),
-                     (ins GPR:$rs1, simm12:$imm12),
-                     "lc", "$rd, ${imm12}(${rs1})">;
-
-let DecoderNamespace = "RISCV32Only_",
-    hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
-def SC_64  : RVInstS<0x3, OPC_STORE, (outs),
-                     (ins GPCR:$rs2, GPR:$rs1, simm12:$imm12),
-                     "sc", "$rs2, ${imm12}(${rs1})">;
-
-let EmitPriority = 0 in {
-def : InstAlias<"lc $rd, (${rs1})",
-                (LC_64  GPCR:$rd, GPR:$rs1, 0)>;
-def : InstAlias<"sc $rs2, (${rs1})",
-                (SC_64  GPCR:$rs2, GPR:$rs1, 0)>;
-}
+  let DecoderNamespace = "RISCV32Only_", hasSideEffects = 0, mayLoad = 1,
+      mayStore = 0 in def LC_64
+      : RVInstI<0x3, OPC_LOAD, (outs YGPR:$rd), (ins GPR:$rs1, simm12:$imm12),
+                "lc", "$rd, ${imm12}(${rs1})">;
+
+  let DecoderNamespace = "RISCV32Only_", hasSideEffects = 0, mayLoad = 0,
+      mayStore =
+          1 in def SC_64 : RVInstS<0x3, OPC_STORE, (outs),
+                                   (ins YGPR:$rs2, GPR:$rs1, simm12:$imm12),
+                                   "sc", "$rs2, ${imm12}(${rs1})">;
+
+  let EmitPriority = 0 in {
+    def : InstAlias<"lc $rd, (${rs1})", (LC_64 YGPR:$rd, GPR:$rs1, 0)>;
+    def : InstAlias<"sc $rs2, (${rs1})", (SC_64 YGPR:$rs2, GPR:$rs1, 0)>;
+  }
 }
 
 let Predicates = [HasCheri, IsRV64, NotCapMode] in {
-let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
-def LC_128  : RVInstI<0x2, OPC_MISC_MEM, (outs GPCR:$rd),
-                      (ins GPR:$rs1, simm12:$imm12),
-                      "lc", "$rd, ${imm12}(${rs1})">;
-
-let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
-def SC_128  : RVInstS<0x4, OPC_STORE, (outs),
-                      (ins GPCR:$rs2, GPR:$rs1, simm12:$imm12),
-                      "sc", "$rs2, ${imm12}(${rs1})">;
-
-let EmitPriority = 0 in {
-def : InstAlias<"lc $rd, (${rs1})",
-                (LC_128  GPCR:$rd, GPR:$rs1, 0)>;
-def : InstAlias<"sc $rs2, (${rs1})",
-                (SC_128  GPCR:$rs2, GPR:$rs1, 0)>;
-}
+  let hasSideEffects = 0, mayLoad = 1,
+      mayStore = 0 in def LC_128
+      : RVInstI<0x2, OPC_MISC_MEM, (outs YGPR:$rd),
+                (ins GPR:$rs1, simm12:$imm12), "lc", "$rd, ${imm12}(${rs1})">;
+
+  let hasSideEffects = 0, mayLoad = 0,
+      mayStore =
+          1 in def SC_128 : RVInstS<0x4, OPC_STORE, (outs),
+                                    (ins YGPR:$rs2, GPR:$rs1, simm12:$imm12),
+                                    "sc", "$rs2, ${imm12}(${rs1})">;
+
+  let EmitPriority = 0 in {
+    def : InstAlias<"lc $rd, (${rs1})", (LC_128 YGPR:$rd, GPR:$rs1, 0)>;
+    def : InstAlias<"sc $rs2, (${rs1})", (SC_128 YGPR:$rs2, GPR:$rs1, 0)>;
+  }
 }
 
 let DecoderNamespace = "RISCV32Only_",
     Predicates = [HasCheri, HasStdExtA, IsRV32, NotCapMode] in {
 defm LR_C       : LR_C_r_aq_rl<"64", 0b011, "lr.c">;
 defm SC_C       : AMO_C_rr_aq_rl<"64", 0b00011, 0b011, "sc.c", GPR>;
-defm AMOSWAP_C  : AMO_C_rr_aq_rl<"64", 0b00001, 0b011, "amoswap.c", GPCR>;
+defm AMOSWAP_C : AMO_C_rr_aq_rl<"64", 0b00001, 0b011, "amoswap.c", YGPR>;
 }
 
 let Predicates = [HasCheri, HasStdExtA, IsRV64, NotCapMode] in {
 defm LR_C       : LR_C_r_aq_rl<"128", 0b100, "lr.c">;
 defm SC_C       : AMO_C_rr_aq_rl<"128", 0b00011, 0b100, "sc.c", GPR>;
-defm AMOSWAP_C  : AMO_C_rr_aq_rl<"128", 0b00001, 0b100, "amoswap.c", GPCR>;
+defm AMOSWAP_C : AMO_C_rr_aq_rl<"128", 0b00001, 0b100, "amoswap.c", YGPR>;
 }
 
 //===----------------------------------------------------------------------===//
@@ -815,77 +809,81 @@ defm AMOSWAP_C  : AMO_C_rr_aq_rl<"128", 0b00001, 0b100, "amoswap.c", GPCR>;
 let DecoderNamespace = "CapModeOnly_" in {
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
 let Predicates = [HasCheri, IsCapMode] in {
-def AUIPCC : RVInstU<OPC_AUIPC, (outs GPCR:$rd), (ins uimm20_auipc:$imm20),
-                     "auipcc", "$rd, $imm20">;
+  def AUIPCC : RVInstU<OPC_AUIPC, (outs YGPR:$rd), (ins uimm20_auipc:$imm20),
+                       "auipcc", "$rd, $imm20">;
 
-let Uses = [C3] in {
-def AUICGP : RVInstU<OPC_AUIGP, (outs GPCR:$rd), (ins uimm20_auigp:$imm20),
-                     "auicgp", "$rd, $imm20">;
-}
+  let Uses = [X3_Y] in {
+    def AUICGP : RVInstU<OPC_AUIGP, (outs YGPR:$rd), (ins uimm20_auigp:$imm20),
+                         "auicgp", "$rd, $imm20">;
+  }
 
-let isCall = 1 in
-def CJAL : RVInstJ<OPC_JAL, (outs GPCR:$rd), (ins simm21_lsb0_jal:$imm20),
-                   "cjal", "$rd, $imm20">;
+  let isCall = 1 in def CJAL
+      : RVInstJ<OPC_JAL, (outs YGPR:$rd), (ins simm21_lsb0_jal:$imm20), "cjal",
+                "$rd, $imm20">;
 
-let isCall = 1 in
-def CJALR : RVInstI<0b000, OPC_JALR, (outs GPCR:$rd),
-                    (ins GPCR:$rs1, simm12:$imm12),
-                    "cjalr", "$rd, ${imm12}(${rs1})">;
+  let isCall = 1 in def CJALR : RVInstI<0b000, OPC_JALR, (outs YGPR:$rd),
+                                        (ins YGPR:$rs1, simm12:$imm12), "cjalr",
+                                        "$rd, ${imm12}(${rs1})">;
 } // Predicates = [HasCheri, IsCapMode]
 } // hasSideEffects = 0, mayLoad = 0, mayStore = 0
 } // DecoderNameSpace = "CapModeOnly_"
 
 let Predicates = [HasCheri, IsCapMode] in {
-def : InstAlias<"j $offset",    (CJAL C0, simm21_lsb0_jal:$offset)>;
-def : InstAlias<"cjal $offset", (CJAL C1, simm21_lsb0_jal:$offset)>;
-
-// Non-canonical form; JAL X0 and CJAL X0 are semantically identical so "j" is
-// the canonical form, but we provide this for completeness.
-def : InstAlias<"cj $offset",   (CJAL C0, simm21_lsb0_jal:$offset), 0>;
-
-// Non-zero offset aliases of "cjalr" are the lowest weight, followed by the
-// two-register form, then the one-register forms and finally "cret".
-def : InstAlias<"cjr $rs",                (CJALR       C0, GPCR:$rs, 0), 3>;
-def : InstAlias<"cjr ${offset}(${rs})",   (CJALR       C0, GPCR:$rs, simm12:$offset)>;
-def : InstAlias<"cjalr $rs",              (CJALR       C1, GPCR:$rs, 0), 3>;
-def : InstAlias<"cjalr ${offset}(${rs})", (CJALR       C1, GPCR:$rs, simm12:$offset)>;
-def : InstAlias<"cjalr $rd, $rs",         (CJALR GPCR:$rd, GPCR:$rs, 0), 2>;
-def : InstAlias<"cret",                   (CJALR       C0,       C1, 0), 4>;
-
-// Non-canonical forms for jump targets also accepted by the assembler.
-def : InstAlias<"cjr $rs, $offset",        (CJALR       C0, GPCR:$rs, simm12:$offset), 0>;
-def : InstAlias<"cjalr $rs, $offset",      (CJALR       C1, GPCR:$rs, simm12:$offset), 0>;
-def : InstAlias<"cjalr $rd, $rs, $offset", (CJALR GPCR:$rd, GPCR:$rs, simm12:$offset), 0>;
+  def : InstAlias<"j $offset", (CJAL X0_Y, simm21_lsb0_jal:$offset)>;
+  def : InstAlias<"cjal $offset", (CJAL X1_Y, simm21_lsb0_jal:$offset)>;
+
+  // Non-canonical form; JAL X0 and CJAL X0 are semantically identical so "j" is
+  // the canonical form, but we provide this for completeness.
+  def : InstAlias<"cj $offset", (CJAL X0_Y, simm21_lsb0_jal:$offset), 0>;
+
+  // Non-zero offset aliases of "cjalr" are the lowest weight, followed by the
+  // two-register form, then the one-register forms and finally "cret".
+  def : InstAlias<"cjr $rs", (CJALR X0_Y, YGPR:$rs, 0), 3>;
+  def : InstAlias<"cjr ${offset}(${rs})", (CJALR X0_Y, YGPR:$rs,
+                                              simm12:$offset)>;
+  def : InstAlias<"cjalr $rs", (CJALR X1_Y, YGPR:$rs, 0), 3>;
+  def : InstAlias<"cjalr ${offset}(${rs})", (CJALR X1_Y, YGPR:$rs,
+                                                simm12:$offset)>;
+  def : InstAlias<"cjalr $rd, $rs", (CJALR YGPR:$rd, YGPR:$rs, 0), 2>;
+  def : InstAlias<"cret", (CJALR X0_Y, X1_Y, 0), 4>;
+
+  // Non-canonical forms for jump targets also accepted by the assembler.
+  def : InstAlias<"cjr $rs, $offset", (CJALR X0_Y, YGPR:$rs, simm12:$offset),
+                  0>;
+  def : InstAlias<"cjalr $rs, $offset", (CJALR X1_Y, YGPR:$rs, simm12:$offset),
+                  0>;
+  def : InstAlias<"cjalr $rd, $rs, $offset",
+                  (CJALR YGPR:$rd, YGPR:$rs, simm12:$offset), 0>;
 } // Predicates = [HasCheri, IsCapMode]
 
 let Predicates = [HasCheriot] in {
-  def : InstAlias<"ct.auipcc $rd, $imm20", (AUIPCC GPCR:$rd,
+  def : InstAlias<"ct.auipcc $rd, $imm20", (AUIPCC YGPR:$rd,
                                                uimm20_auipc:$imm20)>;
-  def : InstAlias<"ct.auicgp $rd, $imm20", (AUICGP GPCR:$rd,
+  def : InstAlias<"ct.auicgp $rd, $imm20", (AUICGP YGPR:$rd,
                                                uimm20_auigp:$imm20)>;
-  def : InstAlias<"ct.cjal $rd, $imm20", (CJAL GPCR:$rd,
+  def : InstAlias<"ct.cjal $rd, $imm20", (CJAL YGPR:$rd,
                                              simm21_lsb0_jal:$imm20)>;
-  def : InstAlias<"ct.cjalr $rd, ${imm12}(${rs1})", (CJALR GPCR:$rd, GPCR:$rs1,
+  def : InstAlias<"ct.cjalr $rd, ${imm12}(${rs1})", (CJALR YGPR:$rd, YGPR:$rs1,
                                                         simm12:$imm12)>;
 
-  def : InstAlias<"ct.cjal $offset", (CJAL C1, simm21_lsb0_jal:$offset), 2>;
-  def : InstAlias<"ct.cj $offset", (CJAL C0, simm21_lsb0_jal:$offset), 0>;
+  def : InstAlias<"ct.cjal $offset", (CJAL X1_Y, simm21_lsb0_jal:$offset), 2>;
+  def : InstAlias<"ct.cj $offset", (CJAL X0_Y, simm21_lsb0_jal:$offset), 0>;
 
-  def : InstAlias<"ct.cjr $rs", (CJALR C0, GPCR:$rs, 0), 8>;
+  def : InstAlias<"ct.cjr $rs", (CJALR X0_Y, YGPR:$rs, 0), 8>;
   def : InstAlias<"ct.cjr ${offset}(${rs})",
-                  (CJALR C0, GPCR:$rs, simm12:$offset), 5>;
-  def : InstAlias<"ct.cjalr $rs", (CJALR C1, GPCR:$rs, 0), 8>;
+                  (CJALR X0_Y, YGPR:$rs, simm12:$offset), 5>;
+  def : InstAlias<"ct.cjalr $rs", (CJALR X1_Y, YGPR:$rs, 0), 8>;
   def : InstAlias<"ct.cjalr ${offset}(${rs})",
-                  (CJALR C1, GPCR:$rs, simm12:$offset), 5>;
-  def : InstAlias<"ct.cjalr $rd, $rs", (CJALR GPCR:$rd, GPCR:$rs, 0), 7>;
-  def : InstAlias<"ct.cret", (CJALR C0, C1, 0), 9>;
+                  (CJALR X1_Y, YGPR:$rs, simm12:$offset), 5>;
+  def : InstAlias<"ct.cjalr $rd, $rs", (CJALR YGPR:$rd, YGPR:$rs, 0), 7>;
+  def : InstAlias<"ct.cret", (CJALR X0_Y, X1_Y, 0), 9>;
 
-  def : InstAlias<"ct.cjr $rs, $offset", (CJALR C0, GPCR:$rs, simm12:$offset),
-                  0>;
-  def : InstAlias<"ct.cjalr $rs, $offset", (CJALR C1, GPCR:$rs, simm12:$offset),
+  def : InstAlias<"ct.cjr $rs, $offset", (CJALR X0_Y, YGPR:$rs, simm12:$offset),
                   0>;
+  def : InstAlias<"ct.cjalr $rs, $offset",
+                  (CJALR X1_Y, YGPR:$rs, simm12:$offset), 0>;
   def : InstAlias<"ct.cjalr $rd, $rs, $offset",
-                  (CJALR GPCR:$rd, GPCR:$rs, simm12:$offset), 0>;
+                  (CJALR YGPR:$rd, YGPR:$rs, simm12:$offset), 0>;
 }
 
 // Expands to an instruction alias with and without a c prefix for loads/stores
@@ -908,22 +906,22 @@ defm CSW : CheriStore_ri<0b010, "sw">;
 } // Predicates = [HasCheri, IsCapMode]
 
 let Predicates = [HasCheriot] in {
-  def : InstAlias<"ct.clb $rd, ${imm12}(${rs1})", (CLB GPR:$rd, GPCR:$rs1,
+  def : InstAlias<"ct.clb $rd, ${imm12}(${rs1})", (CLB GPR:$rd, YGPR:$rs1,
                                                       simm12:$imm12)>;
-  def : InstAlias<"ct.clh $rd, ${imm12}(${rs1})", (CLH GPR:$rd, GPCR:$rs1,
+  def : InstAlias<"ct.clh $rd, ${imm12}(${rs1})", (CLH GPR:$rd, YGPR:$rs1,
                                                       simm12:$imm12)>;
-  def : InstAlias<"ct.clw $rd, ${imm12}(${rs1})", (CLW GPR:$rd, GPCR:$rs1,
+  def : InstAlias<"ct.clw $rd, ${imm12}(${rs1})", (CLW GPR:$rd, YGPR:$rs1,
                                                       simm12:$imm12)>;
-  def : InstAlias<"ct.clbu $rd, ${imm12}(${rs1})", (CLBU GPR:$rd, GPCR:$rs1,
+  def : InstAlias<"ct.clbu $rd, ${imm12}(${rs1})", (CLBU GPR:$rd, YGPR:$rs1,
                                                        simm12:$imm12)>;
-  def : InstAlias<"ct.clhu $rd, ${imm12}(${rs1})", (CLHU GPR:$rd, GPCR:$rs1,
+  def : InstAlias<"ct.clhu $rd, ${imm12}(${rs1})", (CLHU GPR:$rd, YGPR:$rs1,
                                                        simm12:$imm12)>;
 
-  def : InstAlias<"ct.csb $rs2, ${imm12}(${rs1})", (CSB GPR:$rs2, GPCR:$rs1,
+  def : InstAlias<"ct.csb $rs2, ${imm12}(${rs1})", (CSB GPR:$rs2, YGPR:$rs1,
                                                        simm12:$imm12)>;
-  def : InstAlias<"ct.csh $rs2, ${imm12}(${rs1})", (CSH GPR:$rs2, GPCR:$rs1,
+  def : InstAlias<"ct.csh $rs2, ${imm12}(${rs1})", (CSH GPR:$rs2, YGPR:$rs1,
                                                        simm12:$imm12)>;
-  def : InstAlias<"ct.csw $rs2, ${imm12}(${rs1})", (CSW GPR:$rs2, GPCR:$rs1,
+  def : InstAlias<"ct.csw $rs2, ${imm12}(${rs1})", (CSW GPR:$rs2, YGPR:$rs1,
                                                        simm12:$imm12)>;
 }
 
@@ -934,74 +932,72 @@ defm CSD    : CheriStore_ri<0b011, "sd">;
 } // Predicates = [HasCheri, IsRV64, IsCapMode]
 
 let Predicates = [HasCheri, IsRV32, IsCapMode] in {
-let DecoderNamespace = "RISCV32CapModeOnly_",
-    hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
-def CLC_64  : RVInstI<0x3, OPC_LOAD, (outs GPCR:$rd),
-                      (ins GPCR:$rs1, simm12:$imm12),
-                      "clc", "$rd, ${imm12}(${rs1})">;
-def : InstAlias<"lc $rd, ${imm12}(${rs1})",
-                (CLC_64  GPCR:$rd, GPCR:$rs1, simm12:$imm12), 0>;
-
-let DecoderNamespace = "RISCV32CapModeOnly_",
-    hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
-def CSC_64  : RVInstS<0x3, OPC_STORE, (outs),
-                      (ins GPCR:$rs2, GPCR:$rs1, simm12:$imm12),
-                      "csc", "$rs2, ${imm12}(${rs1})">;
-def : InstAlias<"sc $rs2, ${imm12}(${rs1})",
-                (CSC_64  GPCR:$rs2, GPCR:$rs1, simm12:$imm12), 0>;
-
-defm : CPrefixedInstAlias<"lc $rd, (${rs1})",
-                          (CLC_64  GPCR:$rd, GPCR:$rs1, 0)>;
-defm : CPrefixedInstAlias<"sc $rs2, (${rs1})",
-                          (CSC_64  GPCR:$rs2, GPCR:$rs1, 0)>;
+  let DecoderNamespace = "RISCV32CapModeOnly_", hasSideEffects = 0, mayLoad = 1,
+      mayStore = 0 in def CLC_64
+      : RVInstI<0x3, OPC_LOAD, (outs YGPR:$rd), (ins YGPR:$rs1, simm12:$imm12),
+                "clc", "$rd, ${imm12}(${rs1})">;
+  def : InstAlias<"lc $rd, ${imm12}(${rs1})",
+                  (CLC_64 YGPR:$rd, YGPR:$rs1, simm12:$imm12), 0>;
+
+  let DecoderNamespace = "RISCV32CapModeOnly_", hasSideEffects = 0, mayLoad = 0,
+      mayStore =
+          1 in def CSC_64 : RVInstS<0x3, OPC_STORE, (outs),
+                                    (ins YGPR:$rs2, YGPR:$rs1, simm12:$imm12),
+                                    "csc", "$rs2, ${imm12}(${rs1})">;
+  def : InstAlias<"sc $rs2, ${imm12}(${rs1})",
+                  (CSC_64 YGPR:$rs2, YGPR:$rs1, simm12:$imm12), 0>;
+
+  defm : CPrefixedInstAlias<"lc $rd, (${rs1})", (CLC_64 YGPR:$rd, YGPR:$rs1,
+                                                    0)>;
+  defm : CPrefixedInstAlias<"sc $rs2, (${rs1})", (CSC_64 YGPR:$rs2, YGPR:$rs1,
+                                                     0)>;
 }
 
 let Predicates = [HasCheriot] in {
-  def : InstAlias<"ct.clc $rd, ${imm12}(${rs1})", (CLC_64 GPCR:$rd, GPCR:$rs1,
+  def : InstAlias<"ct.clc $rd, ${imm12}(${rs1})", (CLC_64 YGPR:$rd, YGPR:$rs1,
                                                       simm12:$imm12)>;
-  def : InstAlias<"ct.csc $rd, ${imm12}(${rs1})", (CSC_64 GPCR:$rd, GPCR:$rs1,
+  def : InstAlias<"ct.csc $rd, ${imm12}(${rs1})", (CSC_64 YGPR:$rd, YGPR:$rs1,
                                                       simm12:$imm12)>;
 }
 
 let Predicates = [HasCheri, IsRV64, IsCapMode] in {
-let DecoderNamespace = "CapModeOnly_",
-    hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
-def CLC_128  : RVInstI<0x2, OPC_MISC_MEM, (outs GPCR:$rd),
-                       (ins GPCR:$rs1, simm12:$imm12),
-                       "clc", "$rd, ${imm12}(${rs1})">;
-def : InstAlias<"lc $rd, ${imm12}(${rs1})",
-                (CLC_128  GPCR:$rd, GPCR:$rs1, simm12:$imm12), 0>;
-
-let DecoderNamespace = "CapModeOnly_",
-    hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
-def CSC_128  : RVInstS<0x4, OPC_STORE, (outs),
-                       (ins GPCR:$rs2, GPCR:$rs1, simm12:$imm12),
-                       "csc", "$rs2, ${imm12}(${rs1})">;
-def : InstAlias<"sc $rs2, ${imm12}(${rs1})",
-                (CSC_128  GPCR:$rs2, GPCR:$rs1, simm12:$imm12), 0>;
-
-defm : CPrefixedInstAlias<"lc $rd, (${rs1})",
-                          (CLC_128  GPCR:$rd, GPCR:$rs1, 0)>;
-defm : CPrefixedInstAlias<"sc $rs2, (${rs1})",
-                          (CSC_128  GPCR:$rs2, GPCR:$rs1, 0)>;
+  let DecoderNamespace = "CapModeOnly_", hasSideEffects = 0, mayLoad = 1,
+      mayStore = 0 in def CLC_128
+      : RVInstI<0x2, OPC_MISC_MEM, (outs YGPR:$rd),
+                (ins YGPR:$rs1, simm12:$imm12), "clc", "$rd, ${imm12}(${rs1})">;
+  def : InstAlias<"lc $rd, ${imm12}(${rs1})",
+                  (CLC_128 YGPR:$rd, YGPR:$rs1, simm12:$imm12), 0>;
+
+  let DecoderNamespace = "CapModeOnly_", hasSideEffects = 0, mayLoad = 0,
+      mayStore =
+          1 in def CSC_128 : RVInstS<0x4, OPC_STORE, (outs),
+                                     (ins YGPR:$rs2, YGPR:$rs1, simm12:$imm12),
+                                     "csc", "$rs2, ${imm12}(${rs1})">;
+  def : InstAlias<"sc $rs2, ${imm12}(${rs1})",
+                  (CSC_128 YGPR:$rs2, YGPR:$rs1, simm12:$imm12), 0>;
+
+  defm : CPrefixedInstAlias<"lc $rd, (${rs1})", (CLC_128 YGPR:$rd, YGPR:$rs1,
+                                                    0)>;
+  defm : CPrefixedInstAlias<"sc $rs2, (${rs1})", (CSC_128 YGPR:$rs2, YGPR:$rs1,
+                                                     0)>;
 }
 
 let Predicates = [HasCheri, IsCapMode] in {
-defm : CPrefixedInstAlias<"lb $rd, (${rs1})", (CLB  GPR:$rd, GPCR:$rs1, 0)>;
-defm : CPrefixedInstAlias<"lh $rd, (${rs1})", (CLH  GPR:$rd, GPCR:$rs1, 0)>;
-defm : CPrefixedInstAlias<"lw $rd, (${rs1})", (CLW  GPR:$rd, GPCR:$rs1, 0)>;
-defm : CPrefixedInstAlias<"lbu $rd, (${rs1})", (CLBU  GPR:$rd, GPCR:$rs1, 0)>;
-defm : CPrefixedInstAlias<"lhu $rd, (${rs1})", (CLHU  GPR:$rd, GPCR:$rs1, 0)>;
-
-defm : CPrefixedInstAlias<"sb $rs2, (${rs1})", (CSB  GPR:$rs2, GPCR:$rs1, 0)>;
-defm : CPrefixedInstAlias<"sh $rs2, (${rs1})", (CSH  GPR:$rs2, GPCR:$rs1, 0)>;
-defm : CPrefixedInstAlias<"sw $rs2, (${rs1})", (CSW  GPR:$rs2, GPCR:$rs1, 0)>;
+  defm : CPrefixedInstAlias<"lb $rd, (${rs1})", (CLB GPR:$rd, YGPR:$rs1, 0)>;
+  defm : CPrefixedInstAlias<"lh $rd, (${rs1})", (CLH GPR:$rd, YGPR:$rs1, 0)>;
+  defm : CPrefixedInstAlias<"lw $rd, (${rs1})", (CLW GPR:$rd, YGPR:$rs1, 0)>;
+  defm : CPrefixedInstAlias<"lbu $rd, (${rs1})", (CLBU GPR:$rd, YGPR:$rs1, 0)>;
+  defm : CPrefixedInstAlias<"lhu $rd, (${rs1})", (CLHU GPR:$rd, YGPR:$rs1, 0)>;
+
+  defm : CPrefixedInstAlias<"sb $rs2, (${rs1})", (CSB GPR:$rs2, YGPR:$rs1, 0)>;
+  defm : CPrefixedInstAlias<"sh $rs2, (${rs1})", (CSH GPR:$rs2, YGPR:$rs1, 0)>;
+  defm : CPrefixedInstAlias<"sw $rs2, (${rs1})", (CSW GPR:$rs2, YGPR:$rs1, 0)>;
 } // Predicates = [HasCheri, IsCapMode]
 
 let Predicates = [HasCheri, IsRV64, IsCapMode] in {
-defm : CPrefixedInstAlias<"lwu $rd, (${rs1})", (CLWU  GPR:$rd, GPCR:$rs1, 0)>;
-defm : CPrefixedInstAlias<"ld $rd, (${rs1})", (CLD  GPR:$rd, GPCR:$rs1, 0)>;
-defm : CPrefixedInstAlias<"sd $rs2, (${rs1})", (CSD  GPR:$rs2, GPCR:$rs1, 0)>;
+  defm : CPrefixedInstAlias<"lwu $rd, (${rs1})", (CLWU GPR:$rd, YGPR:$rs1, 0)>;
+  defm : CPrefixedInstAlias<"ld $rd, (${rs1})", (CLD GPR:$rd, YGPR:$rs1, 0)>;
+  defm : CPrefixedInstAlias<"sd $rs2, (${rs1})", (CSD GPR:$rs2, YGPR:$rs1, 0)>;
 } // Predicates = [HasCheri, IsRV64, IsCapMode]
 
 /// 'A' (Atomic Instructions) extension
@@ -1044,62 +1040,62 @@ let Predicates = [HasCheri, HasStdExtA, IsRV32, IsCapMode] in {
 defm CLR_C       : CLR_C_r_aq_rl<"64", 0b011, "lr.c", "RISCV32CapModeOnly_">;
 defm CSC_C       : CAMO_C_rr_aq_rl<"64", 0b00011, 0b011, "sc.c", GPR,
                                    "RISCV32CapModeOnly_">;
-defm CAMOSWAP_C  : CAMO_C_rr_aq_rl<"64", 0b00001, 0b011, "amoswap.c", GPCR,
-                                   "RISCV32CapModeOnly_">;
+defm CAMOSWAP_C : CAMO_C_rr_aq_rl<"64", 0b00001, 0b011, "amoswap.c", YGPR,
+                                  "RISCV32CapModeOnly_">;
 }
 
 let Predicates = [HasCheri, HasStdExtA, IsRV64, IsCapMode] in {
 defm CLR_C       : CLR_C_r_aq_rl<"128", 0b100, "lr.c">;
 defm CSC_C       : CAMO_C_rr_aq_rl<"128", 0b00011, 0b100, "sc.c", GPR>;
-defm CAMOSWAP_C  : CAMO_C_rr_aq_rl<"128", 0b00001, 0b100, "amoswap.c", GPCR>;
+defm CAMOSWAP_C : CAMO_C_rr_aq_rl<"128", 0b00001, 0b100, "amoswap.c", YGPR>;
 }
 
 /// 'F' (Single-Precision Floating-Point) extension
 
 let Predicates = [HasCheri, HasStdExtF, IsCapMode] in {
-let DecoderNamespace = "CapModeOnly_",
-    hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
-def CFLW : RVInstI<0b010, OPC_LOAD_FP, (outs FPR32:$rd),
-                   (ins GPCR:$rs1, simm12:$imm12),
-                   "cflw", "$rd, ${imm12}(${rs1})">;
-
-let DecoderNamespace = "CapModeOnly_",
-    hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
-def CFSW : RVInstS<0b010, OPC_STORE_FP, (outs),
-                   (ins FPR32:$rs2, GPCR:$rs1, simm12:$imm12),
-                   "cfsw", "$rs2, ${imm12}(${rs1})">;
-
-defm : CPrefixedInstAlias<"flw $rd, (${rs1})", (CFLW FPR32:$rd, GPCR:$rs1, 0)>;
-defm : CPrefixedInstAlias<"fsw $rs2, (${rs1})",
-                          (CFSW FPR32:$rs2, GPCR:$rs1, 0)>;
-def : InstAlias<"flw $rd, ${imm12}(${rs1})",
-                (CFLW FPR32:$rd, GPCR:$rs1, simm12:$imm12), 0>;
-def : InstAlias<"fsw $rs2, ${imm12}(${rs1})",
-                (CFSW FPR32:$rs2, GPCR:$rs1, simm12:$imm12), 0>;
+  let DecoderNamespace = "CapModeOnly_", hasSideEffects = 0, mayLoad = 1,
+      mayStore = 0 in def CFLW : RVInstI<0b010, OPC_LOAD_FP, (outs FPR32:$rd),
+                                         (ins YGPR:$rs1, simm12:$imm12), "cflw",
+                                         "$rd, ${imm12}(${rs1})">;
+
+  let DecoderNamespace = "CapModeOnly_", hasSideEffects = 0, mayLoad = 0,
+      mayStore =
+          1 in def CFSW : RVInstS<0b010, OPC_STORE_FP, (outs),
+                                  (ins FPR32:$rs2, YGPR:$rs1, simm12:$imm12),
+                                  "cfsw", "$rs2, ${imm12}(${rs1})">;
+
+  defm : CPrefixedInstAlias<"flw $rd, (${rs1})", (CFLW FPR32:$rd, YGPR:$rs1,
+                                                     0)>;
+  defm : CPrefixedInstAlias<"fsw $rs2, (${rs1})", (CFSW FPR32:$rs2, YGPR:$rs1,
+                                                      0)>;
+  def : InstAlias<"flw $rd, ${imm12}(${rs1})",
+                  (CFLW FPR32:$rd, YGPR:$rs1, simm12:$imm12), 0>;
+  def : InstAlias<"fsw $rs2, ${imm12}(${rs1})",
+                  (CFSW FPR32:$rs2, YGPR:$rs1, simm12:$imm12), 0>;
 } // Predicates = [HasCheri, HasStdExtF, IsCapMode]
 
 /// 'D' (Single-Precision Floating-Point) extension
 
 let Predicates = [HasCheri, HasStdExtD, IsCapMode] in {
-let DecoderNamespace = "CapModeOnly_",
-    hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
-def CFLD : RVInstI<0b011, OPC_LOAD_FP, (outs FPR64:$rd),
-                   (ins GPCR:$rs1, simm12:$imm12),
-                   "cfld", "$rd, ${imm12}(${rs1})">;
-
-let DecoderNamespace = "CapModeOnly_",
-    hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
-def CFSD : RVInstS<0b011, OPC_STORE_FP, (outs),
-                   (ins FPR64:$rs2, GPCR:$rs1, simm12:$imm12),
-                   "cfsd", "$rs2, ${imm12}(${rs1})">;
-
-defm : CPrefixedInstAlias<"fld $rd, (${rs1})", (CFLD FPR64:$rd, GPCR:$rs1, 0)>;
-defm : CPrefixedInstAlias<"fsd $rs2, (${rs1})",
-                          (CFSD FPR64:$rs2, GPCR:$rs1, 0)>;
-def : InstAlias<"fld $rd, ${imm12}(${rs1})",
-                (CFLD FPR64:$rd, GPCR:$rs1, simm12:$imm12), 0>;
-def : InstAlias<"fsd $rs2, ${imm12}(${rs1})",
-                (CFSD FPR64:$rs2, GPCR:$rs1, simm12:$imm12), 0>;
+  let DecoderNamespace = "CapModeOnly_", hasSideEffects = 0, mayLoad = 1,
+      mayStore = 0 in def CFLD : RVInstI<0b011, OPC_LOAD_FP, (outs FPR64:$rd),
+                                         (ins YGPR:$rs1, simm12:$imm12), "cfld",
+                                         "$rd, ${imm12}(${rs1})">;
+
+  let DecoderNamespace = "CapModeOnly_", hasSideEffects = 0, mayLoad = 0,
+      mayStore =
+          1 in def CFSD : RVInstS<0b011, OPC_STORE_FP, (outs),
+                                  (ins FPR64:$rs2, YGPR:$rs1, simm12:$imm12),
+                                  "cfsd", "$rs2, ${imm12}(${rs1})">;
+
+  defm : CPrefixedInstAlias<"fld $rd, (${rs1})", (CFLD FPR64:$rd, YGPR:$rs1,
+                                                     0)>;
+  defm : CPrefixedInstAlias<"fsd $rs2, (${rs1})", (CFSD FPR64:$rs2, YGPR:$rs1,
+                                                      0)>;
+  def : InstAlias<"fld $rd, ${imm12}(${rs1})",
+                  (CFLD FPR64:$rd, YGPR:$rs1, simm12:$imm12), 0>;
+  def : InstAlias<"fsd $rs2, ${imm12}(${rs1})",
+                  (CFSD FPR64:$rs2, YGPR:$rs1, simm12:$imm12), 0>;
 } // Predicates = [HasCheri, HasStdExtD, IsCapMode]
 
 /// 'C' (Compressed Instructions) extension
@@ -1107,16 +1103,17 @@ def : InstAlias<"fsd $rs2, ${imm12}(${rs1})",
 let DecoderNamespace = "CapModeOnly_" in {
 let Predicates = [HasCheri, HasCheriRVC, HasStdExtC, IsCapMode] in {
 
-let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Uses = [C2] in
-def C_CIncOffsetImm4CSPN : RVInst16CIW<0b000, 0b00, (outs GPCRC:$rd),
-                                       (ins CSP:$rs1, uimm10_lsb00nonzero:$imm),
-                                       "c.cincoffset4cspn", "$rd, $rs1, $imm"> {
-  bits<5> rs1;
-  let Inst{12-11} = imm{5-4};
-  let Inst{10-7} = imm{9-6};
-  let Inst{6} = imm{2};
-  let Inst{5} = imm{3};
-}
+  let hasSideEffects = 0, mayLoad = 0, mayStore = 0,
+      Uses = [X2_Y] in def C_CIncOffsetImm4CSPN
+      : RVInst16CIW<0b000, 0b00, (outs YGPRC:$rd),
+                    (ins CSP:$rs1, uimm10_lsb00nonzero:$imm),
+                    "c.cincoffset4cspn", "$rd, $rs1, $imm"> {
+    bits<5> rs1;
+    let Inst{12 -11} = imm{5 -4};
+    let Inst{10 -7} = imm{9 -6};
+    let Inst{6} = imm{2};
+    let Inst{5} = imm{3};
+  }
 
 let DecoderNamespace = "RISCV32CapModeOnly_",
     Predicates = [HasCheri, HasCheriRVC, HasStdExtC, HasStdExtD, IsRV32, IsCapMode] in
@@ -1126,8 +1123,9 @@ def C_CFLD : CCheriLoad_ri<0b001, "c.cfld", FPR64C, uimm8_lsb000> {
   let Inst{6-5} = imm{7-6};
 }
 
-let Predicates = [HasCheri, HasCheriRVC, HasStdExtC, IsRV64, IsCapMode] in
-def C_CLC_128 : CCheriLoad_ri<0b001, "c.clc", GPCRC, uimm9_lsb0000> {
+let Predicates = [HasCheri, HasCheriRVC, HasStdExtC, IsRV64,
+                  IsCapMode] in def C_CLC_128
+    : CCheriLoad_ri<0b001, "c.clc", YGPRC, uimm9_lsb0000> {
   bits<9> imm;
   let Inst{12-11} = imm{5-4};
   let Inst{10} = imm{8};
@@ -1142,8 +1140,9 @@ def C_CLW : CCheriLoad_ri<0b010, "c.clw", GPRC, uimm7_lsb00> {
 }
 
 let DecoderNamespace = "RISCV32CapModeOnly_",
-    Predicates = [HasCheri, HasCheriRVC, HasStdExtC, IsRV32, IsCapMode] in
-def C_CLC_64 : CCheriLoad_ri<0b011, "c.clc", GPCRC, uimm8_lsb000> {
+    Predicates = [HasCheri, HasCheriRVC, HasStdExtC, IsRV32,
+                  IsCapMode] in def C_CLC_64
+    : CCheriLoad_ri<0b011, "c.clc", YGPRC, uimm8_lsb000> {
   bits<8> imm;
   let Inst{12-10} = imm{5-3};
   let Inst{6-5} = imm{7-6};
@@ -1164,8 +1163,9 @@ def C_CFSD : CCheriStore_rri<0b101, "c.cfsd", FPR64C, uimm8_lsb000> {
   let Inst{6-5} = imm{7-6};
 }
 
-let Predicates = [HasCheri, HasCheriRVC, HasStdExtC, IsRV64, IsCapMode] in
-def C_CSC_128 : CCheriStore_rri<0b101, "c.csc", GPCRC, uimm9_lsb0000> {
+let Predicates = [HasCheri, HasCheriRVC, HasStdExtC, IsRV64,
+                  IsCapMode] in def C_CSC_128
+    : CCheriStore_rri<0b101, "c.csc", YGPRC, uimm9_lsb0000> {
   bits<9> imm;
   let Inst{12-11} = imm{5-4};
   let Inst{10} = imm{8};
@@ -1180,8 +1180,9 @@ def C_CSW : CCheriStore_rri<0b110, "c.csw", GPRC, uimm7_lsb00> {
 }
 
 let DecoderNamespace = "RISCV32CapModeOnly_",
-    Predicates = [HasCheri, HasCheriRVC, HasStdExtC, IsRV32, IsCapMode]  in
-def C_CSC_64 : CCheriStore_rri<0b111, "c.csc", GPCRC, uimm8_lsb000> {
+    Predicates = [HasCheri, HasCheriRVC, HasStdExtC, IsRV32,
+                  IsCapMode] in def C_CSC_64
+    : CCheriStore_rri<0b111, "c.csc", YGPRC, uimm8_lsb000> {
   bits<8> imm;
   let Inst{12-10} = imm{5-3};
   let Inst{6-5} = imm{7-6};
@@ -1195,10 +1196,11 @@ def C_CSD : CCheriStore_rri<0b111, "c.csd", GPRC, uimm8_lsb000> {
 }
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCall = 1,
-    DecoderNamespace = "RISCV32CapModeOnly_", Defs = [C1],
-    Predicates = [HasCheri, HasCheriRVC, HasStdExtC, IsRV32, IsCapMode]  in
-def C_CJAL : RVInst16CJ<0b001, 0b01, (outs), (ins bare_simm12_lsb0:$offset),
-                        "c.cjal", "$offset">;
+    DecoderNamespace = "RISCV32CapModeOnly_", Defs = [X1_Y],
+    Predicates = [HasCheri, HasCheriRVC, HasStdExtC, IsRV32,
+                  IsCapMode] in def C_CJAL
+    : RVInst16CJ<0b001, 0b01, (outs), (ins bare_simm12_lsb0:$offset), "c.cjal",
+                 "$offset">;
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
 def C_CIncOffsetImm16CSP : RVInst16CI<0b011, 0b01, (outs CSP:$rd_wb),
@@ -1220,8 +1222,9 @@ def C_CFLDCSP : CCheriStackLoad<0b001, "c.cfldcsp", FPR64, uimm9_lsb000> {
   let Inst{4-2} = imm{8-6};
 }
 
-let Predicates = [HasCheri, HasCheriRVC, HasStdExtC, IsRV64, IsCapMode] in
-def C_CLCCSP_128 : CCheriStackLoad<0b001, "c.clccsp", GPCRNoC0, uimm10_lsb0000> {
+let Predicates = [HasCheri, HasCheriRVC, HasStdExtC, IsRV64,
+                  IsCapMode] in def C_CLCCSP_128
+    : CCheriStackLoad<0b001, "c.clccsp", YGPRNoX0, uimm10_lsb0000> {
   let Inst{6} = imm{4};
   let Inst{5-2} = imm{9-6};
 }
@@ -1232,8 +1235,9 @@ def C_CLWCSP : CCheriStackLoad<0b010, "c.clwcsp", GPRNoX0, uimm8_lsb00> {
 }
 
 let DecoderNamespace = "RISCV32CapModeOnly_",
-    Predicates = [HasCheri, HasCheriRVC, HasStdExtC, IsRV32, IsCapMode] in
-def C_CLCCSP_64 : CCheriStackLoad<0b011, "c.clccsp", GPCRNoC0, uimm9_lsb000> {
+    Predicates = [HasCheri, HasCheriRVC, HasStdExtC, IsRV32,
+                  IsCapMode] in def C_CLCCSP_64
+    : CCheriStackLoad<0b011, "c.clccsp", YGPRNoX0, uimm9_lsb000> {
   let Inst{6-5} = imm{4-3};
   let Inst{4-2} = imm{8-6};
 }
@@ -1244,9 +1248,9 @@ def C_CLDCSP : CCheriStackLoad<0b011, "c.cldcsp", GPRNoX0, uimm9_lsb000> {
   let Inst{4-2} = imm{8-6};
 }
 
-let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
-def C_CJR : RVInst16CR<0b1000, 0b10, (outs), (ins GPCRNoC0:$rs1),
-                       "c.cjr", "$rs1"> {
+let hasSideEffects = 0, mayLoad = 0,
+    mayStore = 0 in def C_CJR
+    : RVInst16CR<0b1000, 0b10, (outs), (ins YGPRNoX0:$rs1), "c.cjr", "$rs1"> {
   let isBranch = 1;
   let isBarrier = 1;
   let isTerminator = 1;
@@ -1254,10 +1258,9 @@ def C_CJR : RVInst16CR<0b1000, 0b10, (outs), (ins GPCRNoC0:$rs1),
   let rs2 = 0;
 }
 
-let hasSideEffects = 0, mayLoad = 0, mayStore = 0,
-    isCall = 1, Defs = [C1], rs2 = 0 in
-def C_CJALR : RVInst16CR<0b1001, 0b10, (outs), (ins GPCRNoC0:$rs1),
-                         "c.cjalr", "$rs1">;
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCall = 1, Defs = [X1_Y],
+    rs2 = 0 in def C_CJALR
+    : RVInst16CR<0b1001, 0b10, (outs), (ins YGPRNoX0:$rs1), "c.cjalr", "$rs1">;
 
 let DecoderNamespace = "RISCV32CapModeOnly_",
     Predicates = [HasCheri, HasCheriRVC, HasStdExtC, HasStdExtD, IsRV32, IsCapMode] in
@@ -1266,8 +1269,9 @@ def C_CFSDCSP : CCheriStackStore<0b101, "c.cfsdcsp", FPR64, uimm9_lsb000> {
   let Inst{9-7}   = imm{8-6};
 }
 
-let Predicates = [HasCheri, HasCheriRVC, HasStdExtC, IsRV64, IsCapMode] in
-def C_CSCCSP_128 : CCheriStackStore<0b101, "c.csccsp", GPCR, uimm10_lsb0000> {
+let Predicates = [HasCheri, HasCheriRVC, HasStdExtC, IsRV64,
+                  IsCapMode] in def C_CSCCSP_128
+    : CCheriStackStore<0b101, "c.csccsp", YGPR, uimm10_lsb0000> {
   let Inst{12-11} = imm{5-4};
   let Inst{10-7}  = imm{9-6};
 }
@@ -1278,8 +1282,9 @@ def C_CSWCSP : CCheriStackStore<0b110, "c.cswcsp", GPR, uimm8_lsb00> {
 }
 
 let DecoderNamespace = "RISCV32CapModeOnly_",
-    Predicates = [HasCheri, HasCheriRVC, HasStdExtC, IsRV32, IsCapMode] in
-def C_CSCCSP_64 : CCheriStackStore<0b111, "c.csccsp", GPCR, uimm9_lsb000> {
+    Predicates = [HasCheri, HasCheriRVC, HasStdExtC, IsRV32,
+                  IsCapMode] in def C_CSCCSP_64
+    : CCheriStackStore<0b111, "c.csccsp", YGPR, uimm9_lsb000> {
   let Inst{12-10} = imm{5-3};
   let Inst{9-7}   = imm{8-6};
 }
@@ -1294,18 +1299,21 @@ def C_CSDCSP : CCheriStackStore<0b111, "c.csdcsp", GPR, uimm9_lsb000> {
 } // DecoderNamespace = "CapModeOnly_"
 
 let Predicates = [HasCheri, HasCheriRVC, HasStdExtC, IsCapMode] in {
-def : InstAlias<"c.cincoffsetimm4cspn $rd, $rs1, $imm",
-                (C_CIncOffsetImm4CSPN GPCRC:$rd, CSP:$rs1, uimm10_lsb00nonzero:$imm), 0>;
-def : InstAlias<"c.cincoffsetimm16csp $rd, $imm",
-                (C_CIncOffsetImm16CSP CSP:$rd, simm10_lsb0000nonzero:$imm), 0>;
-def : MnemonicAlias<"c.lw", "c.clw">;
-def : MnemonicAlias<"c.sw", "c.csw">;
-def : MnemonicAlias<"c.sc", "c.csc">;
-def : MnemonicAlias<"c.lc", "c.clc">;
-def : MnemonicAlias<"c.lwsp", "c.clwcsp">;
-def : MnemonicAlias<"c.swsp", "c.cswcsp">;
-def : MnemonicAlias<"c.scsp", "c.csccsp">;
-def : MnemonicAlias<"c.lcsp", "c.clccsp">;
+  def : InstAlias<"c.cincoffsetimm4cspn $rd, $rs1, $imm",
+                  (C_CIncOffsetImm4CSPN YGPRC:$rd, CSP:$rs1,
+                      uimm10_lsb00nonzero:$imm),
+                  0>;
+  def : InstAlias<"c.cincoffsetimm16csp $rd, $imm",
+                  (C_CIncOffsetImm16CSP CSP:$rd, simm10_lsb0000nonzero:$imm),
+                  0>;
+  def : MnemonicAlias<"c.lw", "c.clw">;
+  def : MnemonicAlias<"c.sw", "c.csw">;
+  def : MnemonicAlias<"c.sc", "c.csc">;
+  def : MnemonicAlias<"c.lc", "c.clc">;
+  def : MnemonicAlias<"c.lwsp", "c.clwcsp">;
+  def : MnemonicAlias<"c.swsp", "c.cswcsp">;
+  def : MnemonicAlias<"c.scsp", "c.csccsp">;
+  def : MnemonicAlias<"c.lcsp", "c.clccsp">;
 } // Predicates = [HasCheri, HasCheriRVC, HasStdExtC, IsCapMode]
 let Predicates = [HasCheri, HasCheriRVC, HasStdExtC, IsRV64, IsCapMode] in {
 def : MnemonicAlias<"c.ld", "c.cld">;
@@ -1330,10 +1338,10 @@ let Predicates = [HasCheri, IsCapMode] in {
 // maximum expanded size of this Pseudo is 12 bytes.
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCodeGenOnly = 0,
     isAsmParserOnly = 1, Size = 12 in {
-def PseudoCLLC : Pseudo<(outs GPCR:$dst), (ins bare_symbol:$src), [],
-                        "cllc", "$dst, $src">;
-def PseudoCLLCInbounds : Pseudo<(outs GPCR:$dst), (ins bare_symbol:$src), [],
-                        "cllc.inbounds", "$dst, $src">;
+  def PseudoCLLC : Pseudo<(outs YGPR:$dst), (ins bare_symbol:$src), [], "cllc",
+                          "$dst, $src">;
+  def PseudoCLLCInbounds : Pseudo<(outs YGPR:$dst), (ins bare_symbol:$src), [],
+                                  "cllc.inbounds", "$dst, $src">;
 }
 
 def : Pat<(riscv_cllc tglobaladdr:$in), (PseudoCLLC tglobaladdr:$in)>;
@@ -1344,27 +1352,28 @@ def : Pat<(riscv_cllc tconstpool:$in), (PseudoCLLC tconstpool:$in)>;
 let hasSideEffects = 0, mayLoad = 1, mayStore = 0, isCodeGenOnly = 0,
     isAsmParserOnly = 1,
     Size = 12 in def PseudoCLGC
-    : Pseudo<(outs GPCR:$dst), (ins bare_symbol:$src), [], "clgc",
+    : Pseudo<(outs YGPR:$dst), (ins bare_symbol:$src), [], "clgc",
              "$dst, $src">;
 
 def : Pat<(riscv_clgc tglobaladdr:$in), (PseudoCLGC tglobaladdr:$in)>;
 
 let hasSideEffects = 0, mayLoad = 1, mayStore = 0, isCodeGenOnly = 0,
-    isAsmParserOnly = 1, Size = 8 in
-def PseudoCLA_TLS_IE : Pseudo<(outs GPR:$dst, GPCR:$tmp),
-                              (ins bare_symbol:$src), [],
-                              "cla.tls.ie", "$dst, $src, $tmp">;
+    isAsmParserOnly = 1,
+    Size = 8 in def PseudoCLA_TLS_IE
+    : Pseudo<(outs GPR:$dst, YGPR:$tmp), (ins bare_symbol:$src), [],
+             "cla.tls.ie", "$dst, $src, $tmp">;
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCodeGenOnly = 0,
-    isAsmParserOnly = 1, Size = 8 in
-def PseudoCLC_TLS_GD : Pseudo<(outs GPCR:$dst), (ins bare_symbol:$src), [],
-                              "clc.tls.gd", "$dst, $src">;
+    isAsmParserOnly = 1,
+    Size = 8 in def PseudoCLC_TLS_GD
+    : Pseudo<(outs YGPR:$dst), (ins bare_symbol:$src), [], "clc.tls.gd",
+             "$dst, $src">;
 
-let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCodeGenOnly = 0 in
-def PseudoCIncOffsetTPRel : Pseudo<(outs GPCR:$rd),
-                                   (ins GPCR:$rs1, GPR:$rs2,
-                                        tprel_cincoffset_symbol:$src), [],
-                                   "cincoffset", "$rd, $rs1, $rs2, $src">;
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0,
+    isCodeGenOnly = 0 in def PseudoCIncOffsetTPRel
+    : Pseudo<(outs YGPR:$rd),
+             (ins YGPR:$rs1, GPR:$rs2, tprel_cincoffset_symbol:$src), [],
+             "cincoffset", "$rd, $rs1, $rs2, $src">;
 }
 
 let Predicates = [HasCheri, HasStdExtD, IsRV32] in {
@@ -1380,105 +1389,107 @@ def SplitStoreF64Pseudo
 // Stores an FPR via splitting to two GPRs.
 let hasSideEffects = 0, mayLoad = 0, mayStore = 1,
     Constraints = "@earlyclobber $tmplo,@earlyclobber $tmphi",
-    usesCustomInserter = 1 in
-def CheriSplitStoreF64Pseudo
-    : Pseudo<(outs GPR:$tmplo, GPR:$tmphi, GPCR:$tmpdst),
-             (ins FPR64:$src, GPCR:$dst), []>;
+    usesCustomInserter = 1 in def CheriSplitStoreF64Pseudo
+    : Pseudo<(outs GPR:$tmplo, GPR:$tmphi, YGPR:$tmpdst),
+             (ins FPR64:$src, YGPR:$dst), []>;
 
 } // Predicates = [HasCheri, HasStdExtD, IsRV32]
 
-class PatGpcr<SDPatternOperator OpNode, RVInstCheriSrcDst Inst, ValueType RetVt=XLenVT>
-    : Pat<(RetVt (OpNode GPCR:$rs1)), (Inst GPCR:$rs1)>;
+class PatYGPR<SDPatternOperator OpNode, RVInstCheriSrcDst Inst,
+              ValueType RetVt = XLenVT>
+    : Pat<(RetVt(OpNode YGPR:$rs1)), (Inst YGPR:$rs1)>;
 
-class PatGpcrGpcr<SDPatternOperator OpNode, RVInst Inst, ValueType RetVt=CLenVT>
-    : Pat<(RetVt (OpNode GPCR:$rs1, GPCR:$rs2)), (Inst GPCR:$rs1, GPCR:$rs2)>;
+class PatYGPRYGPR<SDPatternOperator OpNode, RVInst Inst,
+                  ValueType RetVt = YLenVT>
+    : Pat<(RetVt(OpNode YGPR:$rs1, YGPR:$rs2)), (Inst YGPR:$rs1, YGPR:$rs2)>;
 
-class PatGpcrGpr<SDPatternOperator OpNode, RVInst Inst>
-    : Pat<(OpNode GPCR:$rs1, (XLenVT GPR:$rs2)), (Inst GPCR:$rs1, GPR:$rs2)>;
+class PatYGPRGpr<SDPatternOperator OpNode, RVInst Inst>
+    : Pat<(OpNode YGPR:$rs1, (XLenVT GPR:$rs2)), (Inst YGPR:$rs1, GPR:$rs2)>;
 
-class PatGpcrSimm12<SDPatternOperator OpNode, RVInstI Inst>
-    : Pat<(OpNode GPCR:$rs1, simm12:$imm12), (Inst GPCR:$rs1, simm12:$imm12)>;
+class PatYGPRSimm12<SDPatternOperator OpNode, RVInstI Inst>
+    : Pat<(OpNode YGPR:$rs1, simm12:$imm12), (Inst YGPR:$rs1, simm12:$imm12)>;
 
-class PatGpcrUimm12<SDPatternOperator OpNode, RVInstI Inst>
-    : Pat<(OpNode GPCR:$rs1, uimm12:$imm12), (Inst GPCR:$rs1, uimm12:$imm12)>;
+class PatYGPRUimm12<SDPatternOperator OpNode, RVInstI Inst>
+    : Pat<(OpNode YGPR:$rs1, uimm12:$imm12), (Inst YGPR:$rs1, uimm12:$imm12)>;
 
-class PatGprGpcr<SDPatternOperator OpNode, RVInst Inst>
-    : Pat<(OpNode GPR:$rs1, GPCR:$rs2), (Inst GPR:$rs1, GPCR:$rs2)>;
+class PatGprYGPR<SDPatternOperator OpNode, RVInst Inst>
+    : Pat<(OpNode GPR:$rs1, YGPR:$rs2), (Inst GPR:$rs1, YGPR:$rs2)>;
 
 /// Capability-Inspection Instructions
 
-def : PatGpcr<int_cheri_cap_perms_get, CGetPerm>;
-def : PatGpcr<int_cheri_cap_type_get, CGetType>;
-def : PatGpcr<int_cheri_cap_base_get, CGetBase>;
-def : PatGpcr<int_cheri_cap_length_get, CGetLen>;
-def : PatGpcr<riscv_cap_sealed_get, CGetSealed>;
-let Predicates = [HasNoCheriot] in def : PatGpcr<int_cheri_cap_offset_get,
+def : PatYGPR<int_cheri_cap_perms_get, CGetPerm>;
+def : PatYGPR<int_cheri_cap_type_get, CGetType>;
+def : PatYGPR<int_cheri_cap_base_get, CGetBase>;
+def : PatYGPR<int_cheri_cap_length_get, CGetLen>;
+def : PatYGPR<riscv_cap_sealed_get, CGetSealed>;
+let Predicates = [HasNoCheriot] in def : PatYGPR<int_cheri_cap_offset_get,
                                                  CGetOffset>;
-def : PatGpcr<int_cheri_cap_flags_get, CGetFlags>;
-def : Pat<(XLenVT (int_cheri_cap_address_get GPCR:$cs1)), (PseudoCGetAddr GPCR:$cs1)>;
-def : PatGpcr<int_cheri_cap_high_get, CGetHigh>;
-def : PatGpcr<int_cheri_cap_top_get, CGetTop>;
+def : PatYGPR<int_cheri_cap_flags_get, CGetFlags>;
+def : Pat<(XLenVT(int_cheri_cap_address_get YGPR:$cs1)),
+          (PseudoCGetAddr YGPR:$cs1)>;
+def : PatYGPR<int_cheri_cap_high_get, CGetHigh>;
+def : PatYGPR<int_cheri_cap_top_get, CGetTop>;
 
 /// Capability-Modification Instructions
 
-def : PatGpcrGpcr<int_cheri_cap_seal, CSeal>;
-def : PatGpcrGpcr<int_cheri_cap_unseal, CUnseal>;
-def : PatGpcrGpr<int_cheri_cap_perms_and, CAndPerm>;
-def : PatGpcrGpr<int_cheri_cap_flags_set, CSetFlags>;
-def : PatGpcrGpr<int_cheri_cap_offset_set, CSetOffset>;
-def : PatGpcrGpr<int_cheri_cap_address_set, CSetAddr>;
-def : PatGpcrGpr<int_cheri_cap_high_set, CSetHigh>;
-def : PatGpcrGpr<cptradd, CIncOffset>;
-def : PatGpcrSimm12<cptradd, CIncOffsetImm>;
-def : PatGpcrGpr<int_cheri_cap_bounds_set, CSetBounds>;
-def : PatGpcrGpr<int_cheri_cap_bounds_set_exact, CSetBoundsExact>;
-def : PatGpcrGpr<int_cheri_cap_bounds_set_round_down, CSetBoundsRoundDown>;
-def : PatGpcrGpr<riscv_cap_bounds_set, CSetBounds>;
-def : PatGpcrUimm12<riscv_cap_bounds_set, CSetBoundsImm>;
-def : PatGpcrUimm12<int_cheri_cap_bounds_set, CSetBoundsImm>;
-def : PatGpcr<int_cheri_cap_tag_clear, CClearTag, CLenVT>;
-def : PatGpcrGpcr<int_cheri_cap_build, CBuildCap>;
-def : PatGpcrGpcr<int_cheri_cap_type_copy, CCopyType>;
-def : PatGpcrGpcr<int_cheri_cap_conditional_seal, CCSeal>;
-def : PatGpcr<int_cheri_cap_seal_entry, CSealEntry, CLenVT>;
+def : PatYGPRYGPR<int_cheri_cap_seal, CSeal>;
+def : PatYGPRYGPR<int_cheri_cap_unseal, CUnseal>;
+def : PatYGPRGpr<int_cheri_cap_perms_and, CAndPerm>;
+def : PatYGPRGpr<int_cheri_cap_flags_set, CSetFlags>;
+def : PatYGPRGpr<int_cheri_cap_offset_set, CSetOffset>;
+def : PatYGPRGpr<int_cheri_cap_address_set, CSetAddr>;
+def : PatYGPRGpr<int_cheri_cap_high_set, CSetHigh>;
+def : PatYGPRGpr<cptradd, CIncOffset>;
+def : PatYGPRSimm12<cptradd, CIncOffsetImm>;
+def : PatYGPRGpr<int_cheri_cap_bounds_set, CSetBounds>;
+def : PatYGPRGpr<int_cheri_cap_bounds_set_exact, CSetBoundsExact>;
+def : PatYGPRGpr<int_cheri_cap_bounds_set_round_down, CSetBoundsRoundDown>;
+def : PatYGPRGpr<riscv_cap_bounds_set, CSetBounds>;
+def : PatYGPRUimm12<riscv_cap_bounds_set, CSetBoundsImm>;
+def : PatYGPRUimm12<int_cheri_cap_bounds_set, CSetBoundsImm>;
+def : PatYGPR<int_cheri_cap_tag_clear, CClearTag, YLenVT>;
+def : PatYGPRYGPR<int_cheri_cap_build, CBuildCap>;
+def : PatYGPRYGPR<int_cheri_cap_type_copy, CCopyType>;
+def : PatYGPRYGPR<int_cheri_cap_conditional_seal, CCSeal>;
+def : PatYGPR<int_cheri_cap_seal_entry, CSealEntry, YLenVT>;
 
 def uimm12_lt512 : Operand<XLenVT>,
                    ImmLeaf<XLenVT, "return isUInt<12>(Imm) && (Imm < 512);">;
 
 let Predicates =
-    [HasCheriot] in def : Pat<(int_cheri_cap_bounds_set_exact GPCR:$rs1,
+    [HasCheriot] in def : Pat<(int_cheri_cap_bounds_set_exact YGPR:$rs1,
                                   uimm12_lt512:$imm12),
-                              (CSetBoundsImm GPCR:$rs1, uimm12_lt512:$imm12)>;
+                              (CSetBoundsImm YGPR:$rs1, uimm12_lt512:$imm12)>;
 
 // TODO: Make this rematerialisable like MIPS
-def : PatGpcrGpr<int_cheri_bounded_stack_cap, CSetBounds>;
-def : PatGpcrUimm12<int_cheri_bounded_stack_cap, CSetBoundsImm>;
-def : PatGpcrGpr<int_cheri_bounded_stack_cap_dynamic, CSetBounds>;
-def : PatGpcrUimm12<int_cheri_bounded_stack_cap_dynamic, CSetBoundsImm>;
+def : PatYGPRGpr<int_cheri_bounded_stack_cap, CSetBounds>;
+def : PatYGPRUimm12<int_cheri_bounded_stack_cap, CSetBoundsImm>;
+def : PatYGPRGpr<int_cheri_bounded_stack_cap_dynamic, CSetBounds>;
+def : PatYGPRUimm12<int_cheri_bounded_stack_cap_dynamic, CSetBoundsImm>;
 
-def : Pat<(CapFrameAddrRegImm(cPTR GPCR:$rs1), simm12:$imm12),
-          (CIncOffsetImm GPCR:$rs1, simm12:$imm12)>;
+def : Pat<(CapFrameAddrRegImm(cPTR YGPR:$rs1), simm12:$imm12),
+          (CIncOffsetImm YGPR:$rs1, simm12:$imm12)>;
 
 /// Pointer-Arithmetic Instructions
 
 // int_cheri_cap_to_pointer and int_cheri_cap_from_pointer are expanded in C++
 // code for ISAv9, so we don't need replacement patterns here.
-def : Pat<(XLenVT (int_cheri_cap_diff GPCR:$cs1, GPCR:$cs2)),
-          (SUB (XLenVT (EXTRACT_SUBREG GPCR:$cs1, sub_cap_addr)),
-               (XLenVT (EXTRACT_SUBREG GPCR:$cs2, sub_cap_addr)))>;
+def : Pat<(XLenVT(int_cheri_cap_diff YGPR:$cs1, YGPR:$cs2)),
+          (SUB(XLenVT(EXTRACT_SUBREG YGPR:$cs1, sub_cap_addr)),
+              (XLenVT(EXTRACT_SUBREG YGPR:$cs2, sub_cap_addr)))>;
 
 let Predicates = [IsPureCapABI] in {
-  def : Pat<(inttoptr(XLenVT GPR:$rs2)), (cPTR(CIncOffset(cPTR C0), GPR:$rs2))>;
-  def : Pat<(inttoptr simm12:$imm12), (cPTR(CIncOffsetImm(cPTR C0),
+  def : Pat<(inttoptr(XLenVT GPR:$rs2)), (cPTR(CIncOffset(cPTR X0_Y),
+                                             GPR:$rs2))>;
+  def : Pat<(inttoptr simm12:$imm12), (cPTR(CIncOffsetImm(cPTR X0_Y),
                                           simm12:$imm12))>;
-  def : Pat<(XLenVT(ptrtoint(cPTR GPCR:$rs1))), (PseudoCGetAddr GPCR:$rs1)>;
+  def : Pat<(XLenVT(ptrtoint(cPTR YGPR:$rs1))), (PseudoCGetAddr YGPR:$rs1)>;
 }
 
 /// Null Capability Patterns
 
-def : Pat<(inttoptr(XLenVT 0)), (CLenVT(COPY(cPTR C0)))>;
-def : Pat<(ptrtoint (CLenVT (inttoptr (XLenVT 0)))),
-          (XLenVT (COPY (XLenVT X0)))>;
+def : Pat<(inttoptr(XLenVT 0)), (YLenVT(COPY(cPTR X0_Y)))>;
+def : Pat<(ptrtoint(YLenVT(inttoptr(XLenVT 0)))), (XLenVT(COPY(XLenVT X0)))>;
 
 /// Pointer-Comparison Instructions
 
@@ -1486,43 +1497,43 @@ def : Pat<(ptrtoint (CLenVT (inttoptr (XLenVT 0)))),
 // * Rely on a merged register file
 // * Break untagged < tagged semantics
 // * Can't implement exact equality
-class CheriSetCCPatGpcrGpcr<PatFrag CondOp, dag GprGprDag>
-    : Pat<(XLenVT(CondOp(cPTR GPCR:$cs1), (cPTR GPCR:$cs2))),
+class CheriSetCCPatYGPRYGPR<PatFrag CondOp, dag GprGprDag>
+    : Pat<(XLenVT(CondOp(cPTR YGPR:$cs1), (cPTR YGPR:$cs2))),
           (OutPatFrag<(ops node:$rs1, node:$rs2), GprGprDag>(XLenVT
-               (EXTRACT_SUBREG GPCR:$cs1, sub_cap_addr)),
-              (XLenVT(EXTRACT_SUBREG GPCR:$cs2, sub_cap_addr)))>;
+               (EXTRACT_SUBREG YGPR:$cs1, sub_cap_addr)),
+              (XLenVT(EXTRACT_SUBREG YGPR:$cs2, sub_cap_addr)))>;
 
-multiclass CheriSetCCPatGpcrImm<PatFrag CondOp, Operand ImmTy, dag GprImmDag> {
-  def : Pat<(XLenVT(CondOp(cPTR GPCR:$cs1), (inttoptr ImmTy:$imm12))),
+multiclass CheriSetCCPatYGPRImm<PatFrag CondOp, Operand ImmTy, dag GprImmDag> {
+  def : Pat<(XLenVT(CondOp(cPTR YGPR:$cs1), (inttoptr ImmTy:$imm12))),
             (OutPatFrag<(ops node:$rs1, node:$imm12), GprImmDag>(XLenVT
-                 (EXTRACT_SUBREG GPCR:$cs1, sub_cap_addr)),
+                 (EXTRACT_SUBREG YGPR:$cs1, sub_cap_addr)),
                 ImmTy:$imm12)>;
-  def : Pat<(XLenVT(CondOp(cPTR GPCR:$cs1), (cptradd(inttoptr(XLenVT 0)),
+  def : Pat<(XLenVT(CondOp(cPTR YGPR:$cs1), (cptradd(inttoptr(XLenVT 0)),
                                                 ImmTy:$imm12))),
             (OutPatFrag<(ops node:$rs1, node:$imm12), GprImmDag>(XLenVT
-                 (EXTRACT_SUBREG GPCR:$cs1, sub_cap_addr)),
+                 (EXTRACT_SUBREG YGPR:$cs1, sub_cap_addr)),
                 ImmTy:$imm12)>;
-  def : Pat<(XLenVT(CondOp(cPTR GPCR:$cs1),
+  def : Pat<(XLenVT(CondOp(cPTR YGPR:$cs1),
                 (int_cheri_cap_offset_set(inttoptr(XLenVT 0)), ImmTy:$imm12))),
             (OutPatFrag<(ops node:$rs1, node:$imm12), GprImmDag>(XLenVT
-                 (EXTRACT_SUBREG GPCR:$cs1, sub_cap_addr)),
+                 (EXTRACT_SUBREG YGPR:$cs1, sub_cap_addr)),
                 ImmTy:$imm12)>;
-  def : Pat<(XLenVT(CondOp(cPTR GPCR:$cs1),
+  def : Pat<(XLenVT(CondOp(cPTR YGPR:$cs1),
                 (int_cheri_cap_address_set(inttoptr(XLenVT 0)), ImmTy:$imm12))),
             (OutPatFrag<(ops node:$rs1, node:$imm12), GprImmDag>(XLenVT
-                 (EXTRACT_SUBREG GPCR:$cs1, sub_cap_addr)),
+                 (EXTRACT_SUBREG YGPR:$cs1, sub_cap_addr)),
                 ImmTy:$imm12)>;
 }
 
-multiclass CheriSetCCPatGpcrSimm12<PatFrag CondOp, dag GprImmDag>
-    : CheriSetCCPatGpcrImm<CondOp, simm12, GprImmDag>;
+multiclass CheriSetCCPatYGPRSimm12<PatFrag CondOp, dag GprImmDag>
+    : CheriSetCCPatYGPRImm<CondOp, simm12, GprImmDag>;
 
-multiclass CheriSetCCPatGpcrSimm12Plus1<PatFrag CondOp, dag GprImmDag>
-    : CheriSetCCPatGpcrImm<CondOp, simm12_plus1, GprImmDag>;
+multiclass CheriSetCCPatYGPRSimm12Plus1<PatFrag CondOp, dag GprImmDag>
+    : CheriSetCCPatYGPRImm<CondOp, simm12_plus1, GprImmDag>;
 
-class CheriSetCCPatGpcrNull<PatFrag CondOp, dag GprDag>
-    : Pat<(XLenVT(CondOp(cPTR GPCR:$cs1), (inttoptr(XLenVT 0)))),
-          (OutPatFrag<(ops node:$rs1), GprDag>(XLenVT(EXTRACT_SUBREG GPCR:$cs1,
+class CheriSetCCPatYGPRNull<PatFrag CondOp, dag GprDag>
+    : Pat<(XLenVT(CondOp(cPTR YGPR:$cs1), (inttoptr(XLenVT 0)))),
+          (OutPatFrag<(ops node:$rs1), GprDag>(XLenVT(EXTRACT_SUBREG YGPR:$cs1,
               sub_cap_addr)))>;
 
 class Swap<PatFrag BinFrag>
@@ -1533,43 +1544,45 @@ class Swap<PatFrag BinFrag>
 // the commutative and inverse cases. Maybe we should support Constant:cN,
 // represent them as (inttoptr C), or just canonicalise the current form?
 
-def  : CheriSetCCPatGpcrGpcr<setlt, (SLT node:$rs1, node:$rs2)>;
-defm : CheriSetCCPatGpcrSimm12<setlt, (SLTI node:$rs1, node:$imm12)>;
-defm : CheriSetCCPatGpcrSimm12<Swap<setgt>, (SLTI node:$rs1, node:$imm12)>;
-def  : CheriSetCCPatGpcrGpcr<setult, (SLTU node:$rs1, node:$rs2)>;
-defm : CheriSetCCPatGpcrSimm12<setult, (SLTIU node:$rs1, node:$imm12)>;
-defm : CheriSetCCPatGpcrSimm12<Swap<setugt>, (SLTIU node:$rs1, node:$imm12)>;
-
-def  : CheriSetCCPatGpcrNull<seteq, (SLTIU node:$rs1, 1)>;
-def  : CheriSetCCPatGpcrGpcr<seteq, (SLTIU (XOR node:$rs1, node:$rs2), 1)>;
-defm : CheriSetCCPatGpcrSimm12Plus1<
-           seteq, (SLTIU (ADDI node:$rs1, (NegImm node:$imm12)), 1)>;
-defm : CheriSetCCPatGpcrSimm12Plus1<
-           Swap<seteq>, (SLTIU (ADDI node:$rs1, (NegImm node:$imm12)), 1)>;
-def  : CheriSetCCPatGpcrNull<setne, (SLTU (XLenVT X0), node:$rs1)>;
-def  : CheriSetCCPatGpcrGpcr<setne, (SLTU (XLenVT X0), (XOR node:$rs1, node:$rs2))>;
-defm : CheriSetCCPatGpcrSimm12Plus1<
-           setne, (SLTU (XLenVT X0), (ADDI node:$rs1, (NegImm node:$imm12)))>;
-defm : CheriSetCCPatGpcrSimm12Plus1<
-           Swap<setne>, (SLTU (XLenVT X0), (ADDI node:$rs1, (NegImm node:$imm12)))>;
-def  : CheriSetCCPatGpcrGpcr<setugt, (SLTU node:$rs2, node:$rs1)>;
-def  : CheriSetCCPatGpcrGpcr<setuge, (XORI (SLTU node:$rs1, node:$rs2), 1)>;
-def  : CheriSetCCPatGpcrGpcr<setule, (XORI (SLTU node:$rs2, node:$rs1), 1)>;
-def  : CheriSetCCPatGpcrGpcr<setgt, (SLT node:$rs2, node:$rs1)>;
-def  : CheriSetCCPatGpcrGpcr<setge, (XORI (SLT node:$rs1, node:$rs2), 1)>;
-def  : CheriSetCCPatGpcrGpcr<setle, (XORI (SLT node:$rs2, node:$rs1), 1)>;
-
-defm Select_GPCR : SelectCC_GPR_rrirr<GPCR, CLenVT>;
-defm Select_GPCR_f64 : SelectCC_GPR_rrirr<GPCR, f64>;
+def : CheriSetCCPatYGPRYGPR<setlt, (SLT node:$rs1, node:$rs2)>;
+defm : CheriSetCCPatYGPRSimm12<setlt, (SLTI node:$rs1, node:$imm12)>;
+defm : CheriSetCCPatYGPRSimm12<Swap<setgt>, (SLTI node:$rs1, node:$imm12)>;
+def : CheriSetCCPatYGPRYGPR<setult, (SLTU node:$rs1, node:$rs2)>;
+defm : CheriSetCCPatYGPRSimm12<setult, (SLTIU node:$rs1, node:$imm12)>;
+defm : CheriSetCCPatYGPRSimm12<Swap<setugt>, (SLTIU node:$rs1, node:$imm12)>;
+
+def : CheriSetCCPatYGPRNull<seteq, (SLTIU node:$rs1, 1)>;
+def : CheriSetCCPatYGPRYGPR<seteq, (SLTIU(XOR node:$rs1, node:$rs2), 1)>;
+defm : CheriSetCCPatYGPRSimm12Plus1<
+           seteq, (SLTIU(ADDI node:$rs1, (NegImm node:$imm12)), 1)>;
+defm : CheriSetCCPatYGPRSimm12Plus1<
+           Swap<seteq>, (SLTIU(ADDI node:$rs1, (NegImm node:$imm12)), 1)>;
+def : CheriSetCCPatYGPRNull<setne, (SLTU(XLenVT X0), node:$rs1)>;
+def : CheriSetCCPatYGPRYGPR<setne, (SLTU(XLenVT X0), (XOR node:$rs1,
+                                                         node:$rs2))>;
+defm : CheriSetCCPatYGPRSimm12Plus1<
+           setne, (SLTU(XLenVT X0), (ADDI node:$rs1, (NegImm node:$imm12)))>;
+defm : CheriSetCCPatYGPRSimm12Plus1<
+           Swap<setne>, (SLTU(XLenVT X0), (ADDI node:$rs1,
+                                              (NegImm node:$imm12)))>;
+def : CheriSetCCPatYGPRYGPR<setugt, (SLTU node:$rs2, node:$rs1)>;
+def : CheriSetCCPatYGPRYGPR<setuge, (XORI(SLTU node:$rs1, node:$rs2), 1)>;
+def : CheriSetCCPatYGPRYGPR<setule, (XORI(SLTU node:$rs2, node:$rs1), 1)>;
+def : CheriSetCCPatYGPRYGPR<setgt, (SLT node:$rs2, node:$rs1)>;
+def : CheriSetCCPatYGPRYGPR<setge, (XORI(SLT node:$rs1, node:$rs2), 1)>;
+def : CheriSetCCPatYGPRYGPR<setle, (XORI(SLT node:$rs2, node:$rs1), 1)>;
+
+defm Select_YGPR : SelectCC_GPR_rrirr<YGPR, YLenVT>;
+defm Select_YGPR_f64 : SelectCC_GPR_rrirr<YGPR, f64>;
 
 /// Control-Flow Instructions
 
 // No dedicated instructions; see above
 
 class CheriBccPat<PatFrag CondOp, RVInstB Inst>
-    : Pat<(brcond(XLenVT(CondOp(cPTR GPCR:$rs1), (cPTR GPCR:$rs2))), bb:$imm12),
-          (Inst(XLenVT(EXTRACT_SUBREG GPCR:$rs1, sub_cap_addr)),
-              (XLenVT(EXTRACT_SUBREG GPCR:$rs2, sub_cap_addr)),
+    : Pat<(brcond(XLenVT(CondOp(cPTR YGPR:$rs1), (cPTR YGPR:$rs2))), bb:$imm12),
+          (Inst(XLenVT(EXTRACT_SUBREG YGPR:$rs1, sub_cap_addr)),
+              (XLenVT(EXTRACT_SUBREG YGPR:$rs2, sub_cap_addr)),
               bare_simm13_lsb0_bb:$imm12)>;
 
 def : CheriBccPat<seteq, BEQ>;
@@ -1580,9 +1593,9 @@ def : CheriBccPat<setult, BLTU>;
 def : CheriBccPat<setuge, BGEU>;
 
 class CheriBccSwapPat<PatFrag CondOp, RVInst InstBcc>
-    : Pat<(brcond(XLenVT(CondOp(cPTR GPCR:$rs1), (cPTR GPCR:$rs2))), bb:$imm12),
-          (InstBcc(XLenVT(EXTRACT_SUBREG GPCR:$rs2, sub_cap_addr)),
-              (XLenVT(EXTRACT_SUBREG GPCR:$rs1, sub_cap_addr)),
+    : Pat<(brcond(XLenVT(CondOp(cPTR YGPR:$rs1), (cPTR YGPR:$rs2))), bb:$imm12),
+          (InstBcc(XLenVT(EXTRACT_SUBREG YGPR:$rs2, sub_cap_addr)),
+              (XLenVT(EXTRACT_SUBREG YGPR:$rs1, sub_cap_addr)),
               bare_simm13_lsb0_bb:$imm12)>;
 
 def : CheriBccSwapPat<setgt, BLT>;
@@ -1592,15 +1605,15 @@ def : CheriBccSwapPat<setule, BGEU>;
 
 /// Assertion Instructions
 
-def : PatGpcrGpcr<riscv_cap_subset_test, CTestSubset, XLenVT>;
-def : PatGpcrGpcr<riscv_cap_equal_exact, CSEQX, XLenVT>;
+def : PatYGPRYGPR<riscv_cap_subset_test, CTestSubset, XLenVT>;
+def : PatYGPRYGPR<riscv_cap_equal_exact, CSEQX, XLenVT>;
 
 /// Special Capability Register Access Instructions
 
-def : Pat<(int_cheri_ddc_get), (CSpecialRW SCR_DDC.Encoding, (cPTR C0))>;
+def : Pat<(int_cheri_ddc_get), (CSpecialRW SCR_DDC.Encoding, (cPTR X0_Y))>;
 let Predicates = [HasCheri,
                   IsPureCapABI] in def : Pat<(int_cheri_stack_cap_get),
-                                             (CLenVT(COPY(cPTR C2)))>;
+                                             (YLenVT(COPY(cPTR X2_Y)))>;
 
 let Predicates = [HasCheri, IsCapMode] in
 def : Pat<(int_cheri_pcc_get), (AUIPCC 0)>;
@@ -1608,7 +1621,7 @@ def : Pat<(int_cheri_pcc_get), (AUIPCC 0)>;
 let Predicates = [HasCheri,
                   NotCapMode] in def : Pat<(int_cheri_pcc_get),
                                            (CSpecialRW SCR_PCC.Encoding,
-                                               (cPTR C0))>;
+                                               (cPTR X0_Y))>;
 
 /// Fast Register-Clearing Instructions
 
@@ -1619,7 +1632,7 @@ def : PatGpr<int_cheri_representable_alignment_mask, CRAM>;
 
 /// Tag-Memory Access Instructions
 
-def : PatGpcr<int_cheri_cap_load_tags, CLoadTags, XLenVT>;
+def : PatYGPR<int_cheri_cap_load_tags, CLoadTags, XLenVT>;
 
 /// Memory-Access with Explicit Address Type Instructions
 
@@ -1650,7 +1663,7 @@ defm : CheriExplicitLdPat<zextloadi16, LHU_DDC, GPR>;
 
 let Predicates = [HasCheri, IsCapMode, IsRV32] in {
 defm : CheriExplicitLdPat<load, LW_DDC, GPR>;
-defm : CheriExplicitLdPat<load, LC_DDC_64, GPR, XLenVT, CLenVT>;
+defm : CheriExplicitLdPat<load, LC_DDC_64, GPR, XLenVT, YLenVT>;
 }
 
 let Predicates = [HasCheri, IsCapMode, IsRV64] in {
@@ -1658,7 +1671,7 @@ defm : CheriExplicitLdPat<sextloadi32, LW_DDC, GPR>;
 defm : CheriExplicitLdPat<extloadi32, LW_DDC, GPR>;
 defm : CheriExplicitLdPat<load, LD_DDC, GPR>;
 defm : CheriExplicitLdPat<zextloadi32, LWU_DDC, GPR>;
-defm : CheriExplicitLdPat<load, LC_DDC_128, GPR, XLenVT, CLenVT>;
+defm : CheriExplicitLdPat<load, LC_DDC_128, GPR, XLenVT, YLenVT>;
 }
 
 let Predicates = [HasCheri, IsCapMode, HasStdExtF] in
@@ -1681,13 +1694,13 @@ defm : CheriExplicitStPat<truncstorei16, SH_DDC, GPR, GPR>;
 
 let Predicates = [HasCheri, IsCapMode, IsRV32] in {
 defm : CheriExplicitStPat<store, SW_DDC, GPR, GPR>;
-defm : CheriExplicitStPat<store, SC_DDC_64, GPCR, GPR, CLenVT, XLenVT>;
+defm : CheriExplicitStPat<store, SC_DDC_64, YGPR, GPR, YLenVT, XLenVT>;
 }
 
 let Predicates = [HasCheri, IsCapMode, IsRV64] in {
 defm : CheriExplicitStPat<truncstorei32, SW_DDC, GPR, GPR>;
 defm : CheriExplicitStPat<store, SD_DDC, GPR, GPR>;
-defm : CheriExplicitStPat<store, SC_DDC_128, GPCR, GPR, CLenVT, XLenVT>;
+defm : CheriExplicitStPat<store, SC_DDC_128, YGPR, GPR, YLenVT, XLenVT>;
 }
 
 let Predicates = [HasCheri, IsCapMode, HasStdExtF] in
@@ -1705,180 +1718,197 @@ def : Pat<(store FPR64:$rs2, (XLenVT GPR:$rs1)),
 /// Capability loads
 
 let Predicates = [HasCheri, NotCapMode] in {
-defm : CheriExplicitLdPat<sextloadi8, LB_CAP, GPCR, CLenVT, XLenVT>;
-defm : CheriExplicitLdPat<extloadi8, LB_CAP, GPCR, CLenVT, XLenVT>;
-defm : CheriExplicitLdPat<sextloadi16, LH_CAP, GPCR, CLenVT, XLenVT>;
-defm : CheriExplicitLdPat<extloadi16, LH_CAP, GPCR, CLenVT, XLenVT>;
-defm : CheriExplicitLdPat<zextloadi8, LBU_CAP, GPCR, CLenVT, XLenVT>;
-defm : CheriExplicitLdPat<zextloadi16, LHU_CAP, GPCR, CLenVT, XLenVT>;
+  defm : CheriExplicitLdPat<sextloadi8, LB_CAP, YGPR, YLenVT, XLenVT>;
+  defm : CheriExplicitLdPat<extloadi8, LB_CAP, YGPR, YLenVT, XLenVT>;
+  defm : CheriExplicitLdPat<sextloadi16, LH_CAP, YGPR, YLenVT, XLenVT>;
+  defm : CheriExplicitLdPat<extloadi16, LH_CAP, YGPR, YLenVT, XLenVT>;
+  defm : CheriExplicitLdPat<zextloadi8, LBU_CAP, YGPR, YLenVT, XLenVT>;
+  defm : CheriExplicitLdPat<zextloadi16, LHU_CAP, YGPR, YLenVT, XLenVT>;
 }
 
 let Predicates = [HasCheri, NotCapMode, IsRV32] in {
-defm : CheriExplicitLdPat<load, LW_CAP, GPCR, CLenVT, XLenVT>;
-defm : CheriExplicitLdPat<load, LC_CAP_64, GPCR, CLenVT, CLenVT>;
+  defm : CheriExplicitLdPat<load, LW_CAP, YGPR, YLenVT, XLenVT>;
+  defm : CheriExplicitLdPat<load, LC_CAP_64, YGPR, YLenVT, YLenVT>;
 }
 
 let Predicates = [HasCheri, NotCapMode, IsRV64] in {
-defm : CheriExplicitLdPat<sextloadi32, LW_CAP, GPCR, CLenVT, XLenVT>;
-defm : CheriExplicitLdPat<extloadi32, LW_CAP, GPCR, CLenVT, XLenVT>;
-defm : CheriExplicitLdPat<load, LD_CAP, GPCR, CLenVT, XLenVT>;
-defm : CheriExplicitLdPat<zextloadi32, LWU_CAP, GPCR, CLenVT, XLenVT>;
-defm : CheriExplicitLdPat<load, LC_CAP_128, GPCR, CLenVT, CLenVT>;
+  defm : CheriExplicitLdPat<sextloadi32, LW_CAP, YGPR, YLenVT, XLenVT>;
+  defm : CheriExplicitLdPat<extloadi32, LW_CAP, YGPR, YLenVT, XLenVT>;
+  defm : CheriExplicitLdPat<load, LD_CAP, YGPR, YLenVT, XLenVT>;
+  defm : CheriExplicitLdPat<zextloadi32, LWU_CAP, YGPR, YLenVT, XLenVT>;
+  defm : CheriExplicitLdPat<load, LC_CAP_128, YGPR, YLenVT, YLenVT>;
 }
 
-let Predicates = [HasCheri, NotCapMode, HasStdExtF] in
-def : Pat<(load GPCR:$rs1), (FMV_W_X (LW_CAP GPCR:$rs1))>;
+let Predicates = [HasCheri, NotCapMode,
+                  HasStdExtF] in def : Pat<(load YGPR:$rs1),
+                                           (FMV_W_X(LW_CAP YGPR:$rs1))>;
 
-let Predicates = [HasCheri, NotCapMode, HasStdExtD, IsRV32] in
-def : Pat<(load GPCR:$rs1),
-          (BuildPairF64Pseudo (LW_CAP GPCR:$rs1),
-                              (LW_CAP (CIncOffsetImm GPCR:$rs1, 4)))>;
+let Predicates = [HasCheri, NotCapMode, HasStdExtD,
+                  IsRV32] in def : Pat<(load YGPR:$rs1),
+                                       (BuildPairF64Pseudo(LW_CAP YGPR:$rs1),
+                                           (LW_CAP(CIncOffsetImm YGPR:$rs1,
+                                               4)))>;
 
-let Predicates = [HasCheri, NotCapMode, HasStdExtD, IsRV64] in
-def : Pat<(load GPCR:$rs1), (FMV_D_X (LD_CAP GPCR:$rs1))>;
+let Predicates = [HasCheri, NotCapMode, HasStdExtD,
+                  IsRV64] in def : Pat<(load YGPR:$rs1),
+                                       (FMV_D_X(LD_CAP YGPR:$rs1))>;
 
 /// Capability stores
 
 let Predicates = [HasCheri, NotCapMode] in {
-defm : CheriExplicitStPat<truncstorei8, SB_CAP, GPR, GPCR, XLenVT, CLenVT>;
-defm : CheriExplicitStPat<truncstorei16, SH_CAP, GPR, GPCR, XLenVT, CLenVT>;
+  defm : CheriExplicitStPat<truncstorei8, SB_CAP, GPR, YGPR, XLenVT, YLenVT>;
+  defm : CheriExplicitStPat<truncstorei16, SH_CAP, GPR, YGPR, XLenVT, YLenVT>;
 }
 
 let Predicates = [HasCheri, NotCapMode, IsRV32] in {
-defm : CheriExplicitStPat<store, SW_CAP, GPR, GPCR, XLenVT, CLenVT>;
-defm : CheriExplicitStPat<store, SC_CAP_64, GPCR, GPCR, CLenVT, CLenVT>;
+  defm : CheriExplicitStPat<store, SW_CAP, GPR, YGPR, XLenVT, YLenVT>;
+  defm : CheriExplicitStPat<store, SC_CAP_64, YGPR, YGPR, YLenVT, YLenVT>;
 }
 
 let Predicates = [HasCheri, NotCapMode, IsRV64] in {
-defm : CheriExplicitStPat<truncstorei32, SW_CAP, GPR, GPCR, XLenVT, CLenVT>;
-defm : CheriExplicitStPat<store, SD_CAP, GPR, GPCR, XLenVT, CLenVT>;
-defm : CheriExplicitStPat<store, SC_CAP_128, GPCR, GPCR, CLenVT, CLenVT>;
+  defm : CheriExplicitStPat<truncstorei32, SW_CAP, GPR, YGPR, XLenVT, YLenVT>;
+  defm : CheriExplicitStPat<store, SD_CAP, GPR, YGPR, XLenVT, YLenVT>;
+  defm : CheriExplicitStPat<store, SC_CAP_128, YGPR, YGPR, YLenVT, YLenVT>;
 }
 
-let Predicates = [HasCheri, NotCapMode, HasStdExtF] in
-def : Pat<(store FPR32:$rs2, GPCR:$rs1),
-          (SW_CAP (FMV_X_W FPR32:$rs2), GPCR:$rs1)>;
+let Predicates = [HasCheri, NotCapMode,
+                  HasStdExtF] in def : Pat<(store FPR32:$rs2, YGPR:$rs1),
+                                           (SW_CAP(FMV_X_W FPR32:$rs2),
+                                               YGPR:$rs1)>;
 
-let Predicates = [HasCheri, NotCapMode, HasStdExtD, IsRV32] in
-def : Pat<(store FPR64:$rs2, GPCR:$rs1),
-          (KILL (CheriSplitStoreF64Pseudo FPR64:$rs2, GPCR:$rs1))>;
+let Predicates = [HasCheri, NotCapMode, HasStdExtD,
+                  IsRV32] in def : Pat<(store FPR64:$rs2, YGPR:$rs1),
+                                       (KILL
+                                           (CheriSplitStoreF64Pseudo FPR64:$rs2,
+                                               YGPR:$rs1))>;
 
-let Predicates = [HasCheri, NotCapMode, HasStdExtD, IsRV64] in
-def : Pat<(store FPR64:$rs2, GPCR:$rs1),
-          (SD_CAP (FMV_X_D FPR64:$rs2), GPCR:$rs1)>;
+let Predicates = [HasCheri, NotCapMode, HasStdExtD,
+                  IsRV64] in def : Pat<(store FPR64:$rs2, YGPR:$rs1),
+                                       (SD_CAP(FMV_X_D FPR64:$rs2), YGPR:$rs1)>;
 
 /// Non-Capability Mode Instructions
 
 /// Memory-Access Instructions
 
-multiclass AMOCapPat<string CLenStr, string AtomicOp, string BaseInst> {
-  def : PatGprGpcr<!cast<PatFrag>(AtomicOp#"_monotonic"),
-                   !cast<RVInst>(BaseInst#"_"#CLenStr)>;
-  def : PatGprGpcr<!cast<PatFrag>(AtomicOp#"_acquire"),
-                   !cast<RVInst>(BaseInst#"_AQ_"#CLenStr)>;
-  def : PatGprGpcr<!cast<PatFrag>(AtomicOp#"_release"),
-                   !cast<RVInst>(BaseInst#"_RL_"#CLenStr)>;
-  def : PatGprGpcr<!cast<PatFrag>(AtomicOp#"_acq_rel"),
-                   !cast<RVInst>(BaseInst#"_AQ_RL_"#CLenStr)>;
-  def : PatGprGpcr<!cast<PatFrag>(AtomicOp#"_seq_cst"),
-                   !cast<RVInst>(BaseInst#"_AQ_RL_"#CLenStr)>;
+multiclass AMOCapPat<string YLenStr, string AtomicOp, string BaseInst> {
+  def : PatGprYGPR<!cast<PatFrag>(AtomicOp#"_monotonic"),
+                   !cast<RVInst>(BaseInst#"_"#YLenStr)>;
+  def : PatGprYGPR<!cast<PatFrag>(AtomicOp#"_acquire"),
+                   !cast<RVInst>(BaseInst#"_AQ_"#YLenStr)>;
+  def : PatGprYGPR<!cast<PatFrag>(AtomicOp#"_release"),
+                   !cast<RVInst>(BaseInst#"_RL_"#YLenStr)>;
+  def : PatGprYGPR<!cast<PatFrag>(AtomicOp#"_acq_rel"),
+                   !cast<RVInst>(BaseInst#"_AQ_RL_"#YLenStr)>;
+  def : PatGprYGPR<!cast<PatFrag>(AtomicOp#"_seq_cst"),
+                   !cast<RVInst>(BaseInst#"_AQ_RL_"#YLenStr)>;
 }
 
 let Predicates = [HasCheri, IsRV32, NotCapMode] in {
 def : LdPat<load, LC_64, c64>;
-def : StPat<store, SC_64, GPCR, c64>;
+def : StPat<store, SC_64, YGPR, c64>;
 } // Predicates = [HasCheri, IsRV32, NotCapMode]
 
 let Predicates = [HasCheri, IsRV64, NotCapMode] in {
 def : LdPat<load, LC_128, c128>;
-def : StPat<store, SC_128, GPCR, c128>;
+def : StPat<store, SC_128, YGPR, c128>;
 } // Predicates = [HasCheri, IsRV64, NotCapMode]
 
 let Predicates = [HasCheri, HasStdExtA, IsRV32, NotCapMode] in {
 def : LdPat<atomic_load_cap, LC_64, c64>;
-def : StPat<atomic_store_cap, SC_64, GPCR, c64>;
+def : StPat<atomic_store_cap, SC_64, YGPR, c64>;
 defm : AMOCapPat<"64", "atomic_swap_cap", "AMOSWAP_C">;
 } // Predicates = [HasCheri, HasStdExtA, IsRV32, NotCapMode]
 
 let Predicates = [HasCheri, HasStdExtA, IsRV64, NotCapMode] in {
 def : LdPat<atomic_load_cap, LC_128, c128>;
-def : StPat<atomic_store_cap, SC_128, GPCR, c128>;
+def : StPat<atomic_store_cap, SC_128, YGPR, c128>;
 defm : AMOCapPat<"128", "atomic_swap_cap", "AMOSWAP_C">;
 } // Predicates = [HasCheri, HasStdExtA, IsRV64, NotCapMode]
 
 let Predicates = [HasCheri, HasStdExtA] in {
-def PseudoAtomicLoadAddCap : PseudoAMO<GPCR> { let Size = 16; }
-def PseudoAtomicLoadSubCap : PseudoAMO<GPCR> { let Size = 20; }
-def PseudoAtomicLoadAndCap : PseudoAMO<GPCR> { let Size = 20; }
-def PseudoAtomicLoadOrCap : PseudoAMO<GPCR> { let Size = 20; }
-def PseudoAtomicLoadXorCap : PseudoAMO<GPCR> { let Size = 20; }
-def PseudoAtomicLoadMaxCap : PseudoAMO<GPCR> { let Size = 24; }
-def PseudoAtomicLoadMinCap : PseudoAMO<GPCR> { let Size = 24; }
-def PseudoAtomicLoadUMaxCap : PseudoAMO<GPCR> { let Size = 24; }
-def PseudoAtomicLoadUMinCap : PseudoAMO<GPCR> { let Size = 24; }
-def PseudoAtomicLoadNandCap : PseudoAMO<GPCR> { let Size = 24; }
-def PseudoCmpXchgCap : PseudoCmpXchg<GPCR> { let Size = 16; }
+  def PseudoAtomicLoadAddCap : PseudoAMO<YGPR> { let Size = 16; }
+  def PseudoAtomicLoadSubCap : PseudoAMO<YGPR> { let Size = 20; }
+  def PseudoAtomicLoadAndCap : PseudoAMO<YGPR> { let Size = 20; }
+  def PseudoAtomicLoadOrCap : PseudoAMO<YGPR> { let Size = 20; }
+  def PseudoAtomicLoadXorCap : PseudoAMO<YGPR> { let Size = 20; }
+  def PseudoAtomicLoadMaxCap : PseudoAMO<YGPR> { let Size = 24; }
+  def PseudoAtomicLoadMinCap : PseudoAMO<YGPR> { let Size = 24; }
+  def PseudoAtomicLoadUMaxCap : PseudoAMO<YGPR> { let Size = 24; }
+  def PseudoAtomicLoadUMinCap : PseudoAMO<YGPR> { let Size = 24; }
+  def PseudoAtomicLoadNandCap : PseudoAMO<YGPR> { let Size = 24; }
+  def PseudoCmpXchgCap : PseudoCmpXchg<YGPR> { let Size = 16; }
 } // Predicates = [HasCheri, HasStdExtA]f
 
 let Predicates = [HasCheri, HasStdExtA, NotCapMode] in {
-defm : PseudoAMOPat<"atomic_load_add_cap", PseudoAtomicLoadAddCap, GPCR>;
-defm : PseudoAMOPat<"atomic_load_sub_cap", PseudoAtomicLoadSubCap, GPCR>;
-defm : PseudoAMOPat<"atomic_load_and_cap", PseudoAtomicLoadAndCap, GPCR>;
-defm : PseudoAMOPat<"atomic_load_or_cap", PseudoAtomicLoadOrCap, GPCR>;
-defm : PseudoAMOPat<"atomic_load_xor_cap", PseudoAtomicLoadXorCap, GPCR>;
-defm : PseudoAMOPat<"atomic_load_max_cap", PseudoAtomicLoadMaxCap, GPCR>;
-defm : PseudoAMOPat<"atomic_load_min_cap", PseudoAtomicLoadMinCap, GPCR>;
-defm : PseudoAMOPat<"atomic_load_umax_cap", PseudoAtomicLoadUMaxCap, GPCR>;
-defm : PseudoAMOPat<"atomic_load_umin_cap", PseudoAtomicLoadUMinCap, GPCR>;
-defm : PseudoAMOPat<"atomic_load_nand_cap", PseudoAtomicLoadNandCap, GPCR>;
-defm : PseudoCmpXchgPat<"atomic_cmp_swap_cap", PseudoCmpXchgCap, CLenVT, GPCR>;
+  defm : PseudoAMOPat<"atomic_load_add_cap", PseudoAtomicLoadAddCap, YGPR>;
+  defm : PseudoAMOPat<"atomic_load_sub_cap", PseudoAtomicLoadSubCap, YGPR>;
+  defm : PseudoAMOPat<"atomic_load_and_cap", PseudoAtomicLoadAndCap, YGPR>;
+  defm : PseudoAMOPat<"atomic_load_or_cap", PseudoAtomicLoadOrCap, YGPR>;
+  defm : PseudoAMOPat<"atomic_load_xor_cap", PseudoAtomicLoadXorCap, YGPR>;
+  defm : PseudoAMOPat<"atomic_load_max_cap", PseudoAtomicLoadMaxCap, YGPR>;
+  defm : PseudoAMOPat<"atomic_load_min_cap", PseudoAtomicLoadMinCap, YGPR>;
+  defm : PseudoAMOPat<"atomic_load_umax_cap", PseudoAtomicLoadUMaxCap, YGPR>;
+  defm : PseudoAMOPat<"atomic_load_umin_cap", PseudoAtomicLoadUMinCap, YGPR>;
+  defm : PseudoAMOPat<"atomic_load_nand_cap", PseudoAtomicLoadNandCap, YGPR>;
+  defm : PseudoCmpXchgPat<"atomic_cmp_swap_cap", PseudoCmpXchgCap, YLenVT,
+                          YGPR>;
 } // Predicates = [HasCheri, HasStdExtA, NotCapMode]
 
 /// Capability Mode Instructions
 
 multiclass CheriLdPat<PatFrag LoadOp, RVInst Inst, ValueType ReturnVt = XLenVT> {
-  def : Pat<(ReturnVt(LoadOp(CapRegImm(cPTR GPCR:$rs1), simm12:$imm12))),
-            (Inst GPCR:$rs1, simm12:$imm12)>;
+  def : Pat<(ReturnVt(LoadOp(CapRegImm(cPTR YGPR:$rs1), simm12:$imm12))),
+            (Inst YGPR:$rs1, simm12:$imm12)>;
 }
 
 multiclass CheriStPat<PatFrag StoreOp, RVInst Inst, RegisterClass StTy, ValueType StoreVt = XLenVT> {
-  def : Pat<(StoreOp(StoreVt StTy:$rs2), (CapRegImm(cPTR GPCR:$rs1),
+  def : Pat<(StoreOp(StoreVt StTy:$rs2), (CapRegImm(cPTR YGPR:$rs1),
                                              simm12:$imm12)),
-            (Inst(StoreVt StTy:$rs2), GPCR:$rs1, simm12:$imm12)>;
+            (Inst(StoreVt StTy:$rs2), YGPR:$rs1, simm12:$imm12)>;
 }
 
 multiclass CheriAtomicStPat<PatFrag StoreOp, RVInst Inst, RegisterClass StTy, ValueType StoreVt>
     : CheriStPat<StoreOp, Inst, StTy, StoreVt>;
 
 multiclass CheriAMOPat<string AtomicOp, string BaseInst> {
-  def : PatGpcrGpr<!cast<PatFrag>(AtomicOp#"_monotonic"),
+  def : PatYGPRGpr<!cast<PatFrag>(AtomicOp#"_monotonic"),
                    !cast<RVInst>(BaseInst)>;
-  def : PatGpcrGpr<!cast<PatFrag>(AtomicOp#"_acquire"),
+  def : PatYGPRGpr<!cast<PatFrag>(AtomicOp#"_acquire"),
                    !cast<RVInst>(BaseInst#"_AQ")>;
-  def : PatGpcrGpr<!cast<PatFrag>(AtomicOp#"_release"),
+  def : PatYGPRGpr<!cast<PatFrag>(AtomicOp#"_release"),
                    !cast<RVInst>(BaseInst#"_RL")>;
-  def : PatGpcrGpr<!cast<PatFrag>(AtomicOp#"_acq_rel"),
+  def : PatYGPRGpr<!cast<PatFrag>(AtomicOp#"_acq_rel"),
                    !cast<RVInst>(BaseInst#"_AQ_RL")>;
-  def : PatGpcrGpr<!cast<PatFrag>(AtomicOp#"_seq_cst"),
+  def : PatYGPRGpr<!cast<PatFrag>(AtomicOp#"_seq_cst"),
                    !cast<RVInst>(BaseInst#"_AQ_RL")>;
 }
 
 multiclass CheriAMOSubPat<string AtomicOp, string BaseInst> {
-  def : Pat<(!cast<PatFrag>(AtomicOp#"_monotonic") GPCR:$addr, (XLenVT GPR:$incr)),
-            (!cast<RVInst>(BaseInst) GPCR:$addr, (SUB (XLenVT X0), (XLenVT GPR:$incr)))>;
-  def : Pat<(!cast<PatFrag>(AtomicOp#"_acquire") GPCR:$addr, (XLenVT GPR:$incr)),
-            (!cast<RVInst>(BaseInst#"_AQ") GPCR:$addr, (SUB (XLenVT X0), (XLenVT GPR:$incr)))>;
-  def : Pat<(!cast<PatFrag>(AtomicOp#"_release") GPCR:$addr, (XLenVT GPR:$incr)),
-            (!cast<RVInst>(BaseInst#"_RL") GPCR:$addr, (SUB (XLenVT X0), (XLenVT GPR:$incr)))>;
-  def : Pat<(!cast<PatFrag>(AtomicOp#"_acq_rel") GPCR:$addr, (XLenVT GPR:$incr)),
-            (!cast<RVInst>(BaseInst#"_AQ_RL") GPCR:$addr, (SUB (XLenVT X0), (XLenVT GPR:$incr)))>;
-  def : Pat<(!cast<PatFrag>(AtomicOp#"_seq_cst") GPCR:$addr, (XLenVT GPR:$incr)),
-            (!cast<RVInst>(BaseInst#"_AQ_RL") GPCR:$addr, (SUB (XLenVT X0), (XLenVT GPR:$incr)))>;
-}
-
-class PseudoCheriAMO<RegisterClass ValTy=GPR>
+  def : Pat<(!cast<PatFrag>(AtomicOp#"_monotonic") YGPR:$addr,
+                (XLenVT GPR:$incr)),
+            (!cast<RVInst>(BaseInst) YGPR:$addr, (SUB(XLenVT X0),
+                                                     (XLenVT GPR:$incr)))>;
+  def : Pat<(!cast<PatFrag>(AtomicOp#"_acquire") YGPR:$addr,
+                (XLenVT GPR:$incr)),
+            (!cast<RVInst>(BaseInst#"_AQ") YGPR:$addr,
+                (SUB(XLenVT X0), (XLenVT GPR:$incr)))>;
+  def : Pat<(!cast<PatFrag>(AtomicOp#"_release") YGPR:$addr,
+                (XLenVT GPR:$incr)),
+            (!cast<RVInst>(BaseInst#"_RL") YGPR:$addr,
+                (SUB(XLenVT X0), (XLenVT GPR:$incr)))>;
+  def : Pat<(!cast<PatFrag>(AtomicOp#"_acq_rel") YGPR:$addr,
+                (XLenVT GPR:$incr)),
+            (!cast<RVInst>(BaseInst#"_AQ_RL") YGPR:$addr,
+                (SUB(XLenVT X0), (XLenVT GPR:$incr)))>;
+  def : Pat<(!cast<PatFrag>(AtomicOp#"_seq_cst") YGPR:$addr,
+                (XLenVT GPR:$incr)),
+            (!cast<RVInst>(BaseInst#"_AQ_RL") YGPR:$addr,
+                (SUB(XLenVT X0), (XLenVT GPR:$incr)))>;
+}
+
+class PseudoCheriAMO<RegisterClass ValTy = GPR>
     : Pseudo<(outs ValTy:$res, ValTy:$scratch),
-             (ins GPCR:$addr, ValTy:$incr, ixlenimm:$ordering), []> {
+             (ins YGPR:$addr, ValTy:$incr, ixlenimm:$ordering), []> {
   let Constraints = "@earlyclobber $res,@earlyclobber $scratch";
   let mayLoad = 1;
   let mayStore = 1;
@@ -1888,21 +1918,23 @@ class PseudoCheriAMO<RegisterClass ValTy=GPR>
 multiclass PseudoCheriAMOPat<string AtomicOp, Instruction BaseInst,
                              RegisterClass ValTy=GPR> {
   defvar vt = ValTy.RegTypes[0];
-  def : Pat<(!cast<PatFrag>(AtomicOp#"_monotonic") GPCR:$addr, (vt ValTy:$incr)),
-            (BaseInst GPCR:$addr, ValTy:$incr, 2)>;
-  def : Pat<(!cast<PatFrag>(AtomicOp#"_acquire") GPCR:$addr, (vt ValTy:$incr)),
-            (BaseInst GPCR:$addr, ValTy:$incr, 4)>;
-  def : Pat<(!cast<PatFrag>(AtomicOp#"_release") GPCR:$addr, (vt ValTy:$incr)),
-            (BaseInst GPCR:$addr, ValTy:$incr, 5)>;
-  def : Pat<(!cast<PatFrag>(AtomicOp#"_acq_rel") GPCR:$addr, (vt ValTy:$incr)),
-            (BaseInst GPCR:$addr, ValTy:$incr, 6)>;
-  def : Pat<(!cast<PatFrag>(AtomicOp#"_seq_cst") GPCR:$addr, (vt ValTy:$incr)),
-            (BaseInst GPCR:$addr, ValTy:$incr, 7)>;
-}
-
-class PseudoCheriCmpXchg<RegisterClass ValTy=GPR>
+  def : Pat<(!cast<PatFrag>(AtomicOp#"_monotonic") YGPR:$addr,
+                (vt ValTy:$incr)),
+            (BaseInst YGPR:$addr, ValTy:$incr, 2)>;
+  def : Pat<(!cast<PatFrag>(AtomicOp#"_acquire") YGPR:$addr, (vt ValTy:$incr)),
+            (BaseInst YGPR:$addr, ValTy:$incr, 4)>;
+  def : Pat<(!cast<PatFrag>(AtomicOp#"_release") YGPR:$addr, (vt ValTy:$incr)),
+            (BaseInst YGPR:$addr, ValTy:$incr, 5)>;
+  def : Pat<(!cast<PatFrag>(AtomicOp#"_acq_rel") YGPR:$addr, (vt ValTy:$incr)),
+            (BaseInst YGPR:$addr, ValTy:$incr, 6)>;
+  def : Pat<(!cast<PatFrag>(AtomicOp#"_seq_cst") YGPR:$addr, (vt ValTy:$incr)),
+            (BaseInst YGPR:$addr, ValTy:$incr, 7)>;
+}
+
+class PseudoCheriCmpXchg<RegisterClass ValTy = GPR>
     : Pseudo<(outs ValTy:$res, GPR:$scratch),
-             (ins GPCR:$addr, ValTy:$cmpval, ValTy:$newval, ixlenimm:$ordering), []> {
+             (ins YGPR:$addr, ValTy:$cmpval, ValTy:$newval, ixlenimm:$ordering),
+             []> {
   let Constraints = "@earlyclobber $res,@earlyclobber $scratch";
   let mayLoad = 1;
   let mayStore = 1;
@@ -1912,29 +1944,34 @@ class PseudoCheriCmpXchg<RegisterClass ValTy=GPR>
 multiclass PseudoCheriCmpXchgPat<string Op, Pseudo CmpXchgInst,
                                  RegisterClass ValTy=GPR> {
   defvar vt = ValTy.RegTypes[0];
-  def : Pat<(!cast<PatFrag>(Op#"_monotonic") GPCR:$addr, (vt ValTy:$cmp), (vt ValTy:$new)),
-            (CmpXchgInst GPCR:$addr, ValTy:$cmp, ValTy:$new, 2)>;
-  def : Pat<(!cast<PatFrag>(Op#"_acquire") GPCR:$addr, (vt ValTy:$cmp), (vt ValTy:$new)),
-            (CmpXchgInst GPCR:$addr, ValTy:$cmp, ValTy:$new, 4)>;
-  def : Pat<(!cast<PatFrag>(Op#"_release") GPCR:$addr, (vt ValTy:$cmp), (vt ValTy:$new)),
-            (CmpXchgInst GPCR:$addr, ValTy:$cmp, ValTy:$new, 5)>;
-  def : Pat<(!cast<PatFrag>(Op#"_acq_rel") GPCR:$addr, (vt ValTy:$cmp), (vt ValTy:$new)),
-            (CmpXchgInst GPCR:$addr, ValTy:$cmp, ValTy:$new, 6)>;
-  def : Pat<(!cast<PatFrag>(Op#"_seq_cst") GPCR:$addr, (vt ValTy:$cmp), (vt ValTy:$new)),
-            (CmpXchgInst GPCR:$addr, ValTy:$cmp, ValTy:$new, 7)>;
-} 
-
-multiclass CheriAMOCapPat<string CLenStr, string AtomicOp, string BaseInst> {
-  def : PatGpcrGpcr<!cast<PatFrag>(AtomicOp#"_monotonic"),
-                    !cast<RVInst>(BaseInst#"_"#CLenStr), CLenVT>;
-  def : PatGpcrGpcr<!cast<PatFrag>(AtomicOp#"_acquire"),
-                    !cast<RVInst>(BaseInst#"_AQ_"#CLenStr), CLenVT>;
-  def : PatGpcrGpcr<!cast<PatFrag>(AtomicOp#"_release"),
-                    !cast<RVInst>(BaseInst#"_RL_"#CLenStr), CLenVT>;
-  def : PatGpcrGpcr<!cast<PatFrag>(AtomicOp#"_acq_rel"),
-                    !cast<RVInst>(BaseInst#"_AQ_RL_"#CLenStr), CLenVT>;
-  def : PatGpcrGpcr<!cast<PatFrag>(AtomicOp#"_seq_cst"),
-                    !cast<RVInst>(BaseInst#"_AQ_RL_"#CLenStr), CLenVT>;
+  def : Pat<(!cast<PatFrag>(Op#"_monotonic") YGPR:$addr, (vt ValTy:$cmp),
+                (vt ValTy:$new)),
+            (CmpXchgInst YGPR:$addr, ValTy:$cmp, ValTy:$new, 2)>;
+  def : Pat<(!cast<PatFrag>(Op#"_acquire") YGPR:$addr, (vt ValTy:$cmp),
+                (vt ValTy:$new)),
+            (CmpXchgInst YGPR:$addr, ValTy:$cmp, ValTy:$new, 4)>;
+  def : Pat<(!cast<PatFrag>(Op#"_release") YGPR:$addr, (vt ValTy:$cmp),
+                (vt ValTy:$new)),
+            (CmpXchgInst YGPR:$addr, ValTy:$cmp, ValTy:$new, 5)>;
+  def : Pat<(!cast<PatFrag>(Op#"_acq_rel") YGPR:$addr, (vt ValTy:$cmp),
+                (vt ValTy:$new)),
+            (CmpXchgInst YGPR:$addr, ValTy:$cmp, ValTy:$new, 6)>;
+  def : Pat<(!cast<PatFrag>(Op#"_seq_cst") YGPR:$addr, (vt ValTy:$cmp),
+                (vt ValTy:$new)),
+            (CmpXchgInst YGPR:$addr, ValTy:$cmp, ValTy:$new, 7)>;
+}
+
+multiclass CheriAMOCapPat<string YLenStr, string AtomicOp, string BaseInst> {
+  def : PatYGPRYGPR<!cast<PatFrag>(AtomicOp#"_monotonic"),
+                    !cast<RVInst>(BaseInst#"_"#YLenStr), YLenVT>;
+  def : PatYGPRYGPR<!cast<PatFrag>(AtomicOp#"_acquire"),
+                    !cast<RVInst>(BaseInst#"_AQ_"#YLenStr), YLenVT>;
+  def : PatYGPRYGPR<!cast<PatFrag>(AtomicOp#"_release"),
+                    !cast<RVInst>(BaseInst#"_RL_"#YLenStr), YLenVT>;
+  def : PatYGPRYGPR<!cast<PatFrag>(AtomicOp#"_acq_rel"),
+                    !cast<RVInst>(BaseInst#"_AQ_RL_"#YLenStr), YLenVT>;
+  def : PatYGPRYGPR<!cast<PatFrag>(AtomicOp#"_seq_cst"),
+                    !cast<RVInst>(BaseInst#"_AQ_RL_"#YLenStr), YLenVT>;
 }
 
 let Predicates = [HasCheri, HasStdExtA] in {
@@ -1967,17 +2004,17 @@ def PseudoCheriCmpXchg16 : PseudoCheriCmpXchg { let Size = 16; }
 def PseudoCheriAtomicLoadNand32 : PseudoCheriAMO { let Size = 20; }
 def PseudoCheriCmpXchg32 : PseudoCheriCmpXchg { let Size = 16; }
 
-def PseudoCheriAtomicLoadAddCap : PseudoCheriAMO<GPCR> { let Size = 16; }
-def PseudoCheriAtomicLoadSubCap : PseudoCheriAMO<GPCR> { let Size = 20; }
-def PseudoCheriAtomicLoadAndCap : PseudoCheriAMO<GPCR> { let Size = 20; }
-def PseudoCheriAtomicLoadOrCap : PseudoCheriAMO<GPCR> { let Size = 20; }
-def PseudoCheriAtomicLoadXorCap : PseudoCheriAMO<GPCR> { let Size = 20; }
-def PseudoCheriAtomicLoadMaxCap : PseudoCheriAMO<GPCR> { let Size = 24; }
-def PseudoCheriAtomicLoadMinCap : PseudoCheriAMO<GPCR> { let Size = 24; }
-def PseudoCheriAtomicLoadUMaxCap : PseudoCheriAMO<GPCR> { let Size = 24; }
-def PseudoCheriAtomicLoadUMinCap : PseudoCheriAMO<GPCR> { let Size = 24; }
-def PseudoCheriAtomicLoadNandCap : PseudoCheriAMO<GPCR> { let Size = 24; }
-def PseudoCheriCmpXchgCap : PseudoCheriCmpXchg<GPCR> { let Size = 16; }
+def PseudoCheriAtomicLoadAddCap : PseudoCheriAMO<YGPR> { let Size = 16; }
+def PseudoCheriAtomicLoadSubCap : PseudoCheriAMO<YGPR> { let Size = 20; }
+def PseudoCheriAtomicLoadAndCap : PseudoCheriAMO<YGPR> { let Size = 20; }
+def PseudoCheriAtomicLoadOrCap : PseudoCheriAMO<YGPR> { let Size = 20; }
+def PseudoCheriAtomicLoadXorCap : PseudoCheriAMO<YGPR> { let Size = 20; }
+def PseudoCheriAtomicLoadMaxCap : PseudoCheriAMO<YGPR> { let Size = 24; }
+def PseudoCheriAtomicLoadMinCap : PseudoCheriAMO<YGPR> { let Size = 24; }
+def PseudoCheriAtomicLoadUMaxCap : PseudoCheriAMO<YGPR> { let Size = 24; }
+def PseudoCheriAtomicLoadUMinCap : PseudoCheriAMO<YGPR> { let Size = 24; }
+def PseudoCheriAtomicLoadNandCap : PseudoCheriAMO<YGPR> { let Size = 24; }
+def PseudoCheriCmpXchgCap : PseudoCheriCmpXchg<YGPR> { let Size = 16; }
 } // Predicates = [HasCheri, HasStdExtA]
 
 let Predicates = [HasCheri, HasStdExtA, IsRV64] in {
@@ -1988,36 +2025,38 @@ def PseudoCheriCmpXchg64 : PseudoCheriCmpXchg { let Size = 16; }
 /// 'I' (Integer) base
 
 let Predicates = [HasCheri, IsCapMode, IsPureCapABI] in {
-let isBarrier = 1, isBranch = 1, isTerminator = 1 in
-def PseudoCBR : Pseudo<(outs), (ins simm21_lsb0_jal:$imm20), [(br bb:$imm20)]>,
-                PseudoInstExpansion<(CJAL C0, simm21_lsb0_jal:$imm20)>;
-
-let isCall = 1, Defs = [C1] in
-let isBarrier = 1, isBranch = 1, isIndirectBranch = 1, isTerminator = 1 in
-def PseudoCBRIND : Pseudo<(outs), (ins GPCRNoC0C1:$rs1, simm12:$imm12), []>,
-                   PseudoInstExpansion<(CJALR C0, GPCR:$rs1, simm12:$imm12)>;
-
-def : Pat<(brind GPCR:$rs1), (PseudoCBRIND GPCR:$rs1, 0)>;
-def : Pat<(brind (cptradd GPCR:$rs1, simm12:$imm12)),
-          (PseudoCBRIND GPCR:$rs1, simm12:$imm12)>;
+  let isBarrier = 1, isBranch = 1,
+      isTerminator = 1 in def PseudoCBR
+      : Pseudo<(outs), (ins simm21_lsb0_jal:$imm20), [(br bb:$imm20)]>,
+      PseudoInstExpansion<(CJAL X0_Y, simm21_lsb0_jal:$imm20)>;
+
+  let isCall = 1, Defs = [X1_Y] in let isBarrier = 1, isBranch = 1,
+      isIndirectBranch = 1,
+      isTerminator = 1 in def PseudoCBRIND
+      : Pseudo<(outs), (ins YGPRNoX0X1:$rs1, simm12:$imm12), []>,
+      PseudoInstExpansion<(CJALR X0_Y, YGPR:$rs1, simm12:$imm12)>;
+
+  def : Pat<(brind YGPR:$rs1), (PseudoCBRIND YGPR:$rs1, 0)>;
+  def : Pat<(brind(cptradd YGPR:$rs1, simm12:$imm12)), (PseudoCBRIND YGPR:$rs1,
+                                                           simm12:$imm12)>;
 } // Predicates = [HasCheri, IsCapMode, IsPureCapABI]
 
-let Predicates = [HasCheri, IsCapMode],
-    isCall = 1, isBarrier = 1, isCodeGenOnly = 0, hasSideEffects = 0,
-    mayStore = 0, mayLoad = 0, Size = 8 in
-def PseudoCCALLReg : Pseudo<(outs GPCR:$rd),
-                            (ins cap_call_symbol:$func), []> {
+let Predicates = [HasCheri, IsCapMode], isCall = 1, isBarrier = 1,
+    isCodeGenOnly = 0, hasSideEffects = 0, mayStore = 0, mayLoad = 0,
+    Size = 8 in def PseudoCCALLReg
+    : Pseudo<(outs YGPR:$rd), (ins cap_call_symbol:$func), []> {
   let AsmString = "ccall\t$rd, $func";
 }
 
-let Predicates = [HasCheri, IsCapMode],
-    isCall = 1, Defs = [C1], isCodeGenOnly = 0, Size = 8 in
-def PseudoCCALL : Pseudo<(outs), (ins cap_call_symbol:$func), []> {
+let Predicates = [HasCheri, IsCapMode], isCall = 1, Defs = [X1_Y],
+    isCodeGenOnly = 0,
+    Size =
+        8 in def PseudoCCALL : Pseudo<(outs), (ins cap_call_symbol:$func), []> {
   let AsmString = "ccall\t$func";
 }
 
 let Predicates = [HasCheriot] in {
-  def : InstAlias<"ct.ccall $rd, $func", (PseudoCCALLReg GPCR:$rd,
+  def : InstAlias<"ct.ccall $rd, $func", (PseudoCCALLReg YGPR:$rd,
                                              cap_call_symbol:$func)>;
   def : InstAlias<"ct.ccall $func", (PseudoCCALL cap_call_symbol:$func)>;
 }
@@ -2025,13 +2064,15 @@ let Predicates = [HasCheriot] in {
 // The PseudoCompartmentCall of expands to AUIPCC, CLC_64, C_CJALR (10 bytes),
 // but the setup to obtain the callee capability from an import table can
 // require up to 8 additional bytes.
-let Predicates = [HasCheri, IsCapMode],
-    isCall = 1, Defs = [C1], isCodeGenOnly = 1, Size = 18 in
-def PseudoCompartmentCall : Pseudo<(outs), (ins cap_call_symbol:$func), []>;
+let Predicates = [HasCheri, IsCapMode], isCall = 1, Defs = [X1_Y],
+    isCodeGenOnly = 1,
+    Size = 18 in def PseudoCompartmentCall
+    : Pseudo<(outs), (ins cap_call_symbol:$func), []>;
 
-let Predicates = [HasCheri, IsCapMode],
-    isCall = 1, Defs = [C1], isCodeGenOnly = 1, Size = 10 in
-def PseudoLibraryCall : Pseudo<(outs), (ins cap_call_symbol:$func), []>;
+let Predicates = [HasCheri, IsCapMode], isCall = 1, Defs = [X1_Y],
+    isCodeGenOnly = 1,
+    Size = 10 in def PseudoLibraryCall
+    : Pseudo<(outs), (ins cap_call_symbol:$func), []>;
 
 let Predicates = [HasCheri, IsCapMode, IsPureCapABI] in {
 def : Pat<(riscv_cap_call tglobaladdr:$func),
@@ -2042,42 +2083,41 @@ def : Pat<(riscv_cap_compartment_call tglobaladdr:$func),
           (PseudoCompartmentCall tglobaladdr:$func)>;
 def : Pat<(riscv_cap_compartment_call texternalsym:$func),
           (PseudoCompartmentCall texternalsym:$func)>;
-def : Pat<(riscv_cap_compartment_call GPCR:$func),
-          (PseudoCompartmentCall GPCR:$func)>;
+def : Pat<(riscv_cap_compartment_call YGPR:$func),
+          (PseudoCompartmentCall YGPR:$func)>;
 def : Pat<(riscv_cap_library_call tglobaladdr:$func),
           (PseudoLibraryCall tglobaladdr:$func)>;
 def : Pat<(riscv_cap_library_call texternalsym:$func),
           (PseudoLibraryCall texternalsym:$func)>;
-def : Pat<(riscv_cap_library_call GPCR:$func),
-          (PseudoLibraryCall GPCR:$func)>;
+def : Pat<(riscv_cap_library_call YGPR:$func), (PseudoLibraryCall YGPR:$func)>;
 } // Predicates = [HasCheri, IsCapMode, IsPureCapABI]
 
-let Predicates = [HasCheri, IsCapMode, IsPureCapABI],
-    isCall = 1, Defs = [C1] in
-def PseudoCCALLIndirect : Pseudo<(outs), (ins GPCRNoC0C1:$rs1),
-                                 [(riscv_cap_call GPCRNoC0C1:$rs1)]>,
-                          PseudoInstExpansion<(CJALR C1, GPCR:$rs1, 0)>;
-
-let Predicates = [HasCheri, IsCapMode, IsPureCapABI],
-    isBarrier = 1, isReturn = 1, isTerminator = 1 in
-def PseudoCRET : Pseudo<(outs), (ins), [(riscv_ret_glue)]>,
-                 PseudoInstExpansion<(CJALR C0, C1, 0)>;
-
-let Predicates = [HasCheri, IsCapMode],
-    isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [C2],
-    isCodeGenOnly = 0, Size = 8 in
-def PseudoCTAIL : Pseudo<(outs), (ins cap_call_symbol:$dst), []> {
+let Predicates = [HasCheri, IsCapMode, IsPureCapABI], isCall = 1,
+    Defs = [X1_Y] in def PseudoCCALLIndirect
+    : Pseudo<(outs), (ins YGPRNoX0X1:$rs1), [(riscv_cap_call YGPRNoX0X1:$rs1)]>,
+    PseudoInstExpansion<(CJALR X1_Y, YGPR:$rs1, 0)>;
+
+let Predicates = [HasCheri, IsCapMode, IsPureCapABI], isBarrier = 1,
+    isReturn = 1,
+    isTerminator =
+        1 in def PseudoCRET : Pseudo<(outs), (ins), [(riscv_ret_glue)]>,
+    PseudoInstExpansion<(CJALR X0_Y, X1_Y, 0)>;
+
+let Predicates = [HasCheri, IsCapMode], isCall = 1, isTerminator = 1,
+    isReturn = 1, isBarrier = 1, Uses = [X2_Y], isCodeGenOnly = 0,
+    Size =
+        8 in def PseudoCTAIL : Pseudo<(outs), (ins cap_call_symbol:$dst), []> {
   let AsmString = "ctail\t$dst";
 }
 
 let Predicates = [HasCheriot] in
 def : InstAlias<"ct.ctail $dst", (PseudoCTAIL cap_call_symbol:$dst)>;
 
-let Predicates = [HasCheri, IsCapMode, IsPureCapABI],
-    isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [C2] in
-def PseudoCTAILIndirect : Pseudo<(outs), (ins GPCRNoC0C1:$rs1),
-                                 [(riscv_cap_tail GPCRNoC0C1:$rs1)]>,
-                          PseudoInstExpansion<(CJALR C0, GPCR:$rs1, 0)>;
+let Predicates = [HasCheri, IsCapMode, IsPureCapABI], isCall = 1,
+    isTerminator = 1, isReturn = 1, isBarrier = 1,
+    Uses = [X2_Y] in def PseudoCTAILIndirect
+    : Pseudo<(outs), (ins YGPRNoX0X1:$rs1), [(riscv_cap_tail YGPRNoX0X1:$rs1)]>,
+    PseudoInstExpansion<(CJALR X0_Y, YGPR:$rs1, 0)>;
 
 let Predicates = [HasCheri, IsCapMode, IsPureCapABI] in {
 def : Pat<(riscv_cap_tail tglobaladdr:$dst),
@@ -2086,17 +2126,17 @@ def : Pat<(riscv_cap_tail texternalsym:$dst),
           (PseudoCTAIL texternalsym:$dst)>;
 } // Predicates = [HasCheri, IsCapMode, IsPureCapABI]
 
-let Predicates = [HasCheri, IsCapMode, IsPureCapABI] in
-let isCall = 0, isBarrier = 1, isBranch = 1, isTerminator = 1, Size = 8,
-    isCodeGenOnly = 0, hasSideEffects = 0, mayStore = 0, mayLoad = 0 in
-def PseudoCJump : Pseudo<(outs GPCR:$rd),
-                         (ins pseudo_cap_jump_symbol:$target), []> {
+let Predicates = [HasCheri, IsCapMode, IsPureCapABI] in let isCall = 0,
+    isBarrier = 1, isBranch = 1, isTerminator = 1, Size = 8, isCodeGenOnly = 0,
+    hasSideEffects = 0, mayStore = 0,
+    mayLoad = 0 in def PseudoCJump
+    : Pseudo<(outs YGPR:$rd), (ins pseudo_cap_jump_symbol:$target), []> {
   let AsmString = "cjump\t$target, $rd";
 }
 
 let Predicates = [HasCheriot] in def : InstAlias<
                                            "ct.cjump $target, $rd",
-                                           (PseudoCJump GPCR:$rd,
+                                           (PseudoCJump YGPR:$rd,
                                                pseudo_cap_jump_symbol:$target)>;
 
 defm : CheriLdPat<sextloadi8, CLB>, Requires<[HasCheri, IsCapMode]>;
@@ -2130,12 +2170,12 @@ defm : CheriStPat<store, CSD, GPR>;
 
 // Pessimistically assume the stack pointer will be clobbered
 let Predicates = [HasCheri, IsPureCapABI] in {
-let Defs = [C2], Uses = [C2] in {
-def ADJCALLSTACKDOWNCAP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
-                                 [(callseq_start timm:$amt1, timm:$amt2)]>;
-def ADJCALLSTACKUPCAP   : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
-                                 [(callseq_end timm:$amt1, timm:$amt2)]>;
-} // Defs = [C2], Uses = [C2]
+  let Defs = [X2_Y], Uses = [X2_Y] in {
+    def ADJCALLSTACKDOWNCAP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
+                                     [(callseq_start timm:$amt1, timm:$amt2)]>;
+    def ADJCALLSTACKUPCAP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
+                                   [(callseq_end timm:$amt1, timm:$amt2)]>;
+  } // Defs = [X2_Y], Uses = [X2_Y]
 } // Predicates = [HasCheri, IsPureCapABI]
 
 /// 'A' (Atomic Instructions) extension
@@ -2196,16 +2236,26 @@ defm : PseudoCheriAMOPat<"atomic_load_nand_i16", PseudoCheriAtomicLoadNand16>;
 
 defm : PseudoCheriAMOPat<"atomic_load_nand_i32", PseudoCheriAtomicLoadNand32>;
 
-defm : PseudoCheriAMOPat<"atomic_load_add_cap", PseudoCheriAtomicLoadAddCap, GPCR>;
-defm : PseudoCheriAMOPat<"atomic_load_sub_cap", PseudoCheriAtomicLoadSubCap, GPCR>;
-defm : PseudoCheriAMOPat<"atomic_load_and_cap", PseudoCheriAtomicLoadAndCap, GPCR>;
-defm : PseudoCheriAMOPat<"atomic_load_or_cap", PseudoCheriAtomicLoadOrCap, GPCR>;
-defm : PseudoCheriAMOPat<"atomic_load_xor_cap", PseudoCheriAtomicLoadXorCap, GPCR>;
-defm : PseudoCheriAMOPat<"atomic_load_max_cap", PseudoCheriAtomicLoadMaxCap, GPCR>;
-defm : PseudoCheriAMOPat<"atomic_load_min_cap", PseudoCheriAtomicLoadMinCap, GPCR>;
-defm : PseudoCheriAMOPat<"atomic_load_umax_cap", PseudoCheriAtomicLoadUMaxCap, GPCR>;
-defm : PseudoCheriAMOPat<"atomic_load_umin_cap", PseudoCheriAtomicLoadUMinCap, GPCR>;
-defm : PseudoCheriAMOPat<"atomic_load_nand_cap", PseudoCheriAtomicLoadNandCap, GPCR>;
+defm : PseudoCheriAMOPat<"atomic_load_add_cap", PseudoCheriAtomicLoadAddCap,
+                         YGPR>;
+defm : PseudoCheriAMOPat<"atomic_load_sub_cap", PseudoCheriAtomicLoadSubCap,
+                         YGPR>;
+defm : PseudoCheriAMOPat<"atomic_load_and_cap", PseudoCheriAtomicLoadAndCap,
+                         YGPR>;
+defm : PseudoCheriAMOPat<"atomic_load_or_cap", PseudoCheriAtomicLoadOrCap,
+                         YGPR>;
+defm : PseudoCheriAMOPat<"atomic_load_xor_cap", PseudoCheriAtomicLoadXorCap,
+                         YGPR>;
+defm : PseudoCheriAMOPat<"atomic_load_max_cap", PseudoCheriAtomicLoadMaxCap,
+                         YGPR>;
+defm : PseudoCheriAMOPat<"atomic_load_min_cap", PseudoCheriAtomicLoadMinCap,
+                         YGPR>;
+defm : PseudoCheriAMOPat<"atomic_load_umax_cap", PseudoCheriAtomicLoadUMaxCap,
+                         YGPR>;
+defm : PseudoCheriAMOPat<"atomic_load_umin_cap", PseudoCheriAtomicLoadUMinCap,
+                         YGPR>;
+defm : PseudoCheriAMOPat<"atomic_load_nand_cap", PseudoCheriAtomicLoadNandCap,
+                         YGPR>;
 
 /// Compare and exchange
 
@@ -2213,7 +2263,8 @@ defm : PseudoCheriCmpXchgPat<"atomic_cmp_swap_i8", PseudoCheriCmpXchg8>;
 defm : PseudoCheriCmpXchgPat<"atomic_cmp_swap_i16", PseudoCheriCmpXchg16>;
 defm : PseudoCheriCmpXchgPat<"atomic_cmp_swap_i32", PseudoCheriCmpXchg32>;
 
-defm : PseudoCheriCmpXchgPat<"atomic_cmp_swap_cap", PseudoCheriCmpXchgCap, GPCR>;
+defm : PseudoCheriCmpXchgPat<"atomic_cmp_swap_cap", PseudoCheriCmpXchgCap,
+                             YGPR>;
 
 } // Predicates = [HasCheri, HasStdExtA, IsCapMode]
 
@@ -2250,15 +2301,15 @@ defm : PseudoCheriCmpXchgPat<"atomic_cmp_swap_i64", PseudoCheriCmpXchg64>;
 } // Predicates = [HasCheri, HasStdExtA, IsRV64, IsCapMode]
 
 let Predicates = [HasCheri, HasStdExtA, IsRV32, IsCapMode] in {
-defm : CheriLdPat<atomic_load_cap, CLC_64, CLenVT>;
-defm : CheriAtomicStPat<atomic_store_cap, CSC_64, GPCR, CLenVT>;
-defm : CheriAMOCapPat<"64", "atomic_swap_cap", "CAMOSWAP_C">;
+  defm : CheriLdPat<atomic_load_cap, CLC_64, YLenVT>;
+  defm : CheriAtomicStPat<atomic_store_cap, CSC_64, YGPR, YLenVT>;
+  defm : CheriAMOCapPat<"64", "atomic_swap_cap", "CAMOSWAP_C">;
 } // Predicates = [HasCheri, HasStdExtA, IsRV32, IsCapMode]
 
 let Predicates = [HasCheri, HasStdExtA, IsRV64, IsCapMode] in {
-defm : CheriLdPat<atomic_load_cap, CLC_128, CLenVT>;
-defm : CheriAtomicStPat<atomic_store_cap, CSC_128, GPCR, CLenVT>;
-defm : CheriAMOCapPat<"128", "atomic_swap_cap", "CAMOSWAP_C">;
+  defm : CheriLdPat<atomic_load_cap, CLC_128, YLenVT>;
+  defm : CheriAtomicStPat<atomic_store_cap, CSC_128, YGPR, YLenVT>;
+  defm : CheriAMOCapPat<"128", "atomic_swap_cap", "CAMOSWAP_C">;
 } // Predicates = [HasCheri, HasStdExtA, IsRV64, IsCapMode]
 
 /// 'F' (Single-Precision Floating-Point) extension
@@ -2292,18 +2343,18 @@ defm : CheriStPat<store, CFSD, FPR64, f64>;
 /// 'XCheri' extension
 
 let Predicates = [HasCheri, IsRV32, IsCapMode] in {
-defm : CheriLdPat<load, CLC_64, CLenVT>;
-defm : CheriStPat<store, CSC_64, GPCR, CLenVT>;
+  defm : CheriLdPat<load, CLC_64, YLenVT>;
+  defm : CheriStPat<store, CSC_64, YGPR, YLenVT>;
 } // Predicates = [HasCheri, IsRV32, IsCapMode]
 
 let Predicates = [HasCheri, IsRV64, IsCapMode] in {
-defm : CheriLdPat<load, CLC_128, CLenVT>;
-defm : CheriStPat<store, CSC_128, GPCR, CLenVT>;
+  defm : CheriLdPat<load, CLC_128, YLenVT>;
+  defm : CheriStPat<store, CSC_128, YGPR, YLenVT>;
 } // Predicates = [HasCheri, IsRV64, IsCapMode]
 
 let Predicates = [HasCheri, HasCheriot, IsRV32, IsCapMode] in {
   defm : CheriLdPat<load, CLC_64, f64>;
-  defm : CheriStPat<store, CSC_64, GPCR, f64>;
+  defm : CheriStPat<store, CSC_64, YGPR, f64>;
 } // Predicates = [HasCheri, HasCheriot, IsRV32, IsCapMode]
 
 //===----------------------------------------------------------------------===//
@@ -2312,74 +2363,76 @@ let Predicates = [HasCheri, HasCheriot, IsRV32, IsCapMode] in {
 
 // Quadrant 0
 let Predicates = [HasCheri, HasCheriRVC, HasStdExtC, IsCapMode] in {
-def : CompressPat<(CIncOffsetImm GPCRC:$rd, CSP:$rs1, uimm10_lsb00nonzero:$imm),
-                  (C_CIncOffsetImm4CSPN GPCRC:$rd, CSP:$rs1, uimm10_lsb00nonzero:$imm)>;
+  def : CompressPat<(CIncOffsetImm YGPRC:$rd, CSP:$rs1,
+                        uimm10_lsb00nonzero:$imm),
+                    (C_CIncOffsetImm4CSPN YGPRC:$rd, CSP:$rs1,
+                        uimm10_lsb00nonzero:$imm)>;
 } // Predicates = [HasCheri, HasCheriRVC, HasStdExtC, IsCapMode]
 
 let Predicates = [HasCheri, HasCheriRVC, HasStdExtC, HasStdExtD, IsRV32, IsCapMode] in {
-def : CompressPat<(CFLD FPR64C:$rd, GPCRC:$rs1, uimm8_lsb000:$imm),
-                  (C_CFLD FPR64C:$rd, GPCRC:$rs1, uimm8_lsb000:$imm)>;
+  def : CompressPat<(CFLD FPR64C:$rd, YGPRC:$rs1, uimm8_lsb000:$imm),
+                    (C_CFLD FPR64C:$rd, YGPRC:$rs1, uimm8_lsb000:$imm)>;
 } // Predicates = [HasCheri, HasCheriRVC, HasStdExtC, HasStdExtD, IsRV32, IsCapMode]
 
 let Predicates = [HasCheri, HasCheriRVC, HasStdExtC, IsRV64, IsCapMode] in {
-def : CompressPat<(CLC_128 GPCRC:$rd, GPCRC:$rs1, uimm9_lsb0000:$imm),
-                  (C_CLC_128 GPCRC:$rd, GPCRC:$rs1, uimm9_lsb0000:$imm)>;
+  def : CompressPat<(CLC_128 YGPRC:$rd, YGPRC:$rs1, uimm9_lsb0000:$imm),
+                    (C_CLC_128 YGPRC:$rd, YGPRC:$rs1, uimm9_lsb0000:$imm)>;
 } // Predicates = [HasCheri, HasCheriRVC, HasStdExtC, IsRV64, IsCapMode]
 
 let Predicates = [HasCheri, HasCheriRVC, HasStdExtC, IsCapMode] in {
-def : CompressPat<(CLW GPRC:$rd, GPCRC:$rs1, uimm7_lsb00:$imm),
-                  (C_CLW GPRC:$rd, GPCRC:$rs1, uimm7_lsb00:$imm)>;
+  def : CompressPat<(CLW GPRC:$rd, YGPRC:$rs1, uimm7_lsb00:$imm),
+                    (C_CLW GPRC:$rd, YGPRC:$rs1, uimm7_lsb00:$imm)>;
 } // Predicates = [HasCheri, HasCheriRVC, HasStdExtC, IsCapMode]
 
 let Predicates = [HasCheri, HasCheriRVC, HasStdExtC, IsRV32, IsCapMode] in {
-def : CompressPat<(CLC_64 GPCRC:$rd, GPCRC:$rs1, uimm8_lsb000:$imm),
-                  (C_CLC_64 GPCRC:$rd, GPCRC:$rs1, uimm8_lsb000:$imm)>;
+  def : CompressPat<(CLC_64 YGPRC:$rd, YGPRC:$rs1, uimm8_lsb000:$imm),
+                    (C_CLC_64 YGPRC:$rd, YGPRC:$rs1, uimm8_lsb000:$imm)>;
 } // Predicates = [HasCheri, HasCheriRVC, HasStdExtC, IsRV32, IsCapMode]
 
 let Predicates = [HasCheri, HasCheriRVC, HasStdExtC, IsRV64, IsCapMode] in {
-def : CompressPat<(CLD GPRC:$rd, GPCRC:$rs1, uimm8_lsb000:$imm),
-                  (C_CLD GPRC:$rd, GPCRC:$rs1, uimm8_lsb000:$imm)>;
+  def : CompressPat<(CLD GPRC:$rd, YGPRC:$rs1, uimm8_lsb000:$imm),
+                    (C_CLD GPRC:$rd, YGPRC:$rs1, uimm8_lsb000:$imm)>;
 } // Predicates = [HasCheri, HasCheriRVC, HasStdExtC, IsRV64, IsCapMode]
 
 let Predicates = [HasCheri, HasCheriRVC, HasStdExtC, HasStdExtD, IsRV32, IsCapMode] in {
-def : CompressPat<(CFSD FPR64C:$rs2, GPCRC:$rs1, uimm8_lsb000:$imm),
-                  (C_CFSD FPR64C:$rs2, GPCRC:$rs1, uimm8_lsb000:$imm)>;
+  def : CompressPat<(CFSD FPR64C:$rs2, YGPRC:$rs1, uimm8_lsb000:$imm),
+                    (C_CFSD FPR64C:$rs2, YGPRC:$rs1, uimm8_lsb000:$imm)>;
 } // Predicates = [HasCheri, HasCheriRVC, HasStdExtC, HasStdExtD, IsRV32, IsCapMode]
 
 let Predicates = [HasCheri, HasCheriRVC, HasStdExtC, IsRV64, IsCapMode] in {
-def : CompressPat<(CSC_128 GPCRC:$rs2, GPCRC:$rs1, uimm9_lsb0000:$imm),
-                  (C_CSC_128 GPCRC:$rs2, GPCRC:$rs1, uimm9_lsb0000:$imm)>;
+  def : CompressPat<(CSC_128 YGPRC:$rs2, YGPRC:$rs1, uimm9_lsb0000:$imm),
+                    (C_CSC_128 YGPRC:$rs2, YGPRC:$rs1, uimm9_lsb0000:$imm)>;
 } // Predicates = [HasCheri, HasCheriRVC, HasStdExtC, IsRV64, IsCapMode]
 
 let Predicates = [HasCheri, HasCheriRVC, HasStdExtC, IsCapMode] in {
-def : CompressPat<(CSW GPRC:$rs2, GPCRC:$rs1, uimm7_lsb00:$imm),
-                  (C_CSW GPRC:$rs2, GPCRC:$rs1, uimm7_lsb00:$imm)>;
+  def : CompressPat<(CSW GPRC:$rs2, YGPRC:$rs1, uimm7_lsb00:$imm),
+                    (C_CSW GPRC:$rs2, YGPRC:$rs1, uimm7_lsb00:$imm)>;
 } // Predicates = [HasCheri, HasCheriRVC, HasStdExtC, IsCapMode]
 
 let Predicates = [HasCheri, HasCheriRVC, HasStdExtC, IsRV32, IsCapMode] in {
-def : CompressPat<(CSC_64 GPCRC:$rs2, GPCRC:$rs1, uimm8_lsb000:$imm),
-                  (C_CSC_64 GPCRC:$rs2, GPCRC:$rs1, uimm8_lsb000:$imm)>;
+  def : CompressPat<(CSC_64 YGPRC:$rs2, YGPRC:$rs1, uimm8_lsb000:$imm),
+                    (C_CSC_64 YGPRC:$rs2, YGPRC:$rs1, uimm8_lsb000:$imm)>;
 } // Predicates = [HasCheri, HasCheriRVC, HasStdExtC, IsRV32, IsCapMode]
 
 let Predicates = [HasCheri, HasCheriRVC, HasStdExtC, IsRV64, IsCapMode] in {
-def : CompressPat<(CSD GPRC:$rs2, GPCRC:$rs1, uimm8_lsb000:$imm),
-                  (C_CSD GPRC:$rs2, GPCRC:$rs1, uimm8_lsb000:$imm)>;
+  def : CompressPat<(CSD GPRC:$rs2, YGPRC:$rs1, uimm8_lsb000:$imm),
+                    (C_CSD GPRC:$rs2, YGPRC:$rs1, uimm8_lsb000:$imm)>;
 } // Predicates = [HasCheri, HasCheriRVC, HasStdExtC, IsRV64, IsCapMode]
 
 // Quadrant 1
 let Predicates = [HasCheri, HasCheriRVC, HasStdExtC, IsRV32, IsCapMode] in {
-def : CompressPat<(CJAL C1, bare_simm12_lsb0:$offset),
-                  (C_CJAL bare_simm12_lsb0:$offset)>;
+  def : CompressPat<(CJAL X1_Y, bare_simm12_lsb0:$offset),
+                    (C_CJAL bare_simm12_lsb0:$offset)>;
 } // Predicates = [HasCheri, HasCheriRVC, HasStdExtC, IsRV32, IsCapMode]
 
 let Predicates = [HasCheri, HasCheriRVC, HasStdExtC, IsCapMode] in {
-def : CompressPat<(CIncOffsetImm C2, C2, simm10_lsb0000nonzero:$imm),
-                  (C_CIncOffsetImm16CSP C2, simm10_lsb0000nonzero:$imm)>;
+  def : CompressPat<(CIncOffsetImm X2_Y, X2_Y, simm10_lsb0000nonzero:$imm),
+                    (C_CIncOffsetImm16CSP X2_Y, simm10_lsb0000nonzero:$imm)>;
 } // Predicates = [HasCheri, HasCheriRVC, HasStdExtC, IsCapMode]
 
 let Predicates = [HasCheri, HasCheriRVC, HasStdExtC, IsCapMode] in {
-def : CompressPat<(CJAL C0, bare_simm12_lsb0:$offset),
-                  (C_J bare_simm12_lsb0:$offset)>;
+  def : CompressPat<(CJAL X0_Y, bare_simm12_lsb0:$offset),
+                    (C_J bare_simm12_lsb0:$offset)>;
 } // Predicates = [HasCheri, HasCheriRVC, HasStdExtC, IsCapMode]
 
 // Quadrant 2
@@ -2389,8 +2442,8 @@ def : CompressPat<(CFLD FPR64:$rd, CSP:$rs1, uimm9_lsb000:$imm),
 } // Predicates = [HasCheri, HasCheriRVC, HasStdExtC, HasStdExtD, IsRV32, IsCapMode]
 
 let Predicates = [HasCheri, HasCheriRVC, HasStdExtC, IsRV64, IsCapMode] in {
-def : CompressPat<(CLC_128 GPCRNoC0:$rd, CSP:$rs1, uimm10_lsb0000:$imm),
-                  (C_CLCCSP_128 GPCRNoC0:$rd, CSP:$rs1, uimm10_lsb0000:$imm)>;
+  def : CompressPat<(CLC_128 YGPRNoX0:$rd, CSP:$rs1, uimm10_lsb0000:$imm),
+                    (C_CLCCSP_128 YGPRNoX0:$rd, CSP:$rs1, uimm10_lsb0000:$imm)>;
 } // Predicates = [HasCheri, HasCheriRVC, HasStdExtC, IsRV64, IsCapMode]
 
 let Predicates = [HasCheri, HasCheriRVC, HasStdExtC, IsCapMode] in {
@@ -2399,8 +2452,8 @@ def : CompressPat<(CLW GPRNoX0:$rd, CSP:$rs1,  uimm8_lsb00:$imm),
 } // Predicates = [HasCheri, HasCheriRVC, HasStdExtC, IsCapMode]
 
 let Predicates = [HasCheri, HasCheriRVC, HasStdExtC, IsRV32, IsCapMode] in {
-def : CompressPat<(CLC_64 GPCRNoC0:$rd, CSP:$rs1, uimm9_lsb000:$imm),
-                  (C_CLCCSP_64 GPCRNoC0:$rd, CSP:$rs1, uimm9_lsb000:$imm)>;
+  def : CompressPat<(CLC_64 YGPRNoX0:$rd, CSP:$rs1, uimm9_lsb000:$imm),
+                    (C_CLCCSP_64 YGPRNoX0:$rd, CSP:$rs1, uimm9_lsb000:$imm)>;
 } // Predicates = [HasCheri, HasCheriRVC, HasStdExtC, IsRV32, IsCapMode]
 
 let Predicates = [HasCheri, HasCheriRVC, HasStdExtC, IsRV64, IsCapMode] in {
@@ -2409,13 +2462,11 @@ def : CompressPat<(CLD GPRNoX0:$rd, CSP:$rs1, uimm9_lsb000:$imm),
 } // Predicates = [HasCheri, HasCheriRVC, HasStdExtC, IsRV64, IsCapMode]
 
 let Predicates = [HasCheri, HasCheriRVC, HasStdExtC, IsCapMode] in {
-def : CompressPat<(CJALR C0, GPCRNoC0:$rs1, 0),
-                  (C_CJR GPCRNoC0:$rs1)>;
+  def : CompressPat<(CJALR X0_Y, YGPRNoX0:$rs1, 0), (C_CJR YGPRNoX0:$rs1)>;
 } // Predicates = [HasCheri, HasCheriRVC, HasStdExtC, IsCapMode]
 
 let Predicates = [HasCheri, HasCheriRVC, HasStdExtC, IsCapMode] in {
-def : CompressPat<(CJALR C1, GPCRNoC0:$rs1, 0),
-                  (C_CJALR GPCRNoC0:$rs1)>;
+  def : CompressPat<(CJALR X1_Y, YGPRNoX0:$rs1, 0), (C_CJALR YGPRNoX0:$rs1)>;
 } // Predicates = [HasCheri, HasCheriRVC, HasStdExtC, IsCapMode]
 
 let Predicates = [HasCheri, HasCheriRVC, HasStdExtC, HasStdExtD, IsRV32, IsCapMode] in {
@@ -2424,8 +2475,8 @@ def : CompressPat<(CFSD FPR64:$rs2, CSP:$rs1, uimm9_lsb000:$imm),
 } // Predicates = [HasCheri, HasCheriRVC, HasStdExtC, HasStdExtD, IsRV32, IsCapMode]
 
 let Predicates = [HasCheri, HasCheriRVC, HasStdExtC, IsRV64, IsCapMode] in {
-def : CompressPat<(CSC_128 GPCR:$rs2, CSP:$rs1, uimm10_lsb0000:$imm),
-                  (C_CSCCSP_128 GPCR:$rs2, CSP:$rs1, uimm10_lsb0000:$imm)>;
+  def : CompressPat<(CSC_128 YGPR:$rs2, CSP:$rs1, uimm10_lsb0000:$imm),
+                    (C_CSCCSP_128 YGPR:$rs2, CSP:$rs1, uimm10_lsb0000:$imm)>;
 } // Predicates = [HasCheri, HasCheriRVC, HasStdExtC, IsRV64, IsCapMode]
 
 let Predicates = [HasCheri, HasCheriRVC, HasStdExtC, IsCapMode] in {
@@ -2434,8 +2485,8 @@ def : CompressPat<(CSW GPR:$rs2, CSP:$rs1, uimm8_lsb00:$imm),
 } // Predicates = [HasCheri, HasCheriRVC, HasStdExtC, IsCapMode]
 
 let Predicates = [HasCheri, HasCheriRVC, HasStdExtC, IsRV32, IsCapMode] in {
-def : CompressPat<(CSC_64 GPCR:$rs2, CSP:$rs1, uimm9_lsb000:$imm),
-                  (C_CSCCSP_64 GPCR:$rs2, CSP:$rs1, uimm9_lsb000:$imm)>;
+  def : CompressPat<(CSC_64 YGPR:$rs2, CSP:$rs1, uimm9_lsb000:$imm),
+                    (C_CSCCSP_64 YGPR:$rs2, CSP:$rs1, uimm9_lsb000:$imm)>;
 } // Predicates = [HasCheri, HasCheriRVC, HasStdExtC, IsRV32, IsCapMode]
 
 let Predicates = [HasCheri, HasCheriRVC, HasStdExtC, IsRV64, IsCapMode] in {
@@ -2445,20 +2496,21 @@ def : CompressPat<(CSD GPR:$rs2, CSP:$rs1, uimm9_lsb000:$imm),
 
 
 let Predicates = [HasCheri, IsRV32, IsCapMode, IsRVE] in {
-let mayLoad = true, mayStore = false, hasSideEffects = false in
-def PseudoCLLW : Pseudo<(outs GPCR:$dst), (ins bare_symbol:$src), [],
-                        "cllc", "$dst, $src">;
-def : Pat<(c64(load(cPTR(load(iPTR globaladdr:$src))))),
-          (PseudoCLLW bare_symbol:$src)>;
-def : Pat<(f64(load(cPTR(load(iPTR globaladdr:$src))))),
-          (PseudoCLLW bare_symbol:$src)>;
+  let mayLoad = true, mayStore = false,
+      hasSideEffects = false in def PseudoCLLW
+      : Pseudo<(outs YGPR:$dst), (ins bare_symbol:$src), [], "cllc",
+               "$dst, $src">;
+  def : Pat<(c64(load(cPTR(load(iPTR globaladdr:$src))))),
+            (PseudoCLLW bare_symbol:$src)>;
+  def : Pat<(f64(load(cPTR(load(iPTR globaladdr:$src))))),
+            (PseudoCLLW bare_symbol:$src)>;
 } // Predicates = [HasCheri, IsRV32, IsCapMode, IsRVE]
 
 // Cheriot stores f64 in cap registers, so bitcasting between f64 and c64
 // is a no-op.
 multiclass NopCapRegCast<ValueType Ty1, ValueType Ty2> {
-  def : Pat<(Ty1(bitconvert(Ty2 GPCR:$Val))), (Ty1 GPCR:$Val)>;
-  def : Pat<(Ty2(bitconvert(Ty1 GPCR:$Val))), (Ty2 GPCR:$Val)>;
+  def : Pat<(Ty1(bitconvert(Ty2 YGPR:$Val))), (Ty1 YGPR:$Val)>;
+  def : Pat<(Ty2(bitconvert(Ty1 YGPR:$Val))), (Ty2 YGPR:$Val)>;
 }
 
 let Predicates = [HasCheri, HasCheriot] in { defm : NopCapRegCast<c64, f64>; }
diff --git a/llvm/lib/Target/RISCV/RISCVInstrPredicates.td b/llvm/lib/Target/RISCV/RISCVInstrPredicates.td
index d8ac168395286..dd86222cd23c0 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrPredicates.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrPredicates.td
@@ -48,8 +48,8 @@ def isSelectPseudo
     : TIIPredicate<
           "isSelectPseudo",
           MCReturnStatement<CheckOpcode<
-              [Select_GPR_Using_CC_GPR, Select_GPCR_Using_CC_GPR,
-               Select_GPCR_f64_Using_CC_GPR, Select_GPR_Using_CC_SImm5_CV,
+              [Select_GPR_Using_CC_GPR, Select_YGPR_Using_CC_GPR,
+               Select_YGPR_f64_Using_CC_GPR, Select_GPR_Using_CC_SImm5_CV,
                Select_GPRNoX0_Using_CC_SImm5NonZero_QC,
                Select_GPRNoX0_Using_CC_UImm5NonZero_QC,
                Select_GPRNoX0_Using_CC_SImm16NonZero_QC,
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
index 11cf384903d1e..b9d10d4e09850 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
@@ -56,9 +56,10 @@ static_assert(RISCV::V31 == RISCV::V0 + 31, "Register list not consecutive");
 
 RISCVRegisterInfo::RISCVRegisterInfo(const RISCVSubtarget &STI)
     : RISCVGenRegisterInfo(RISCVABI::isCheriPureCapABI(STI.getTargetABI())
-                               ? RISCV::C1 : RISCV::X1,
-                           /*DwarfFlavour*/0, /*EHFlavor*/0,
-                           /*PC*/0, STI.getHwMode()) {}
+                               ? RISCV::X1_Y
+                               : RISCV::X1,
+                           /*DwarfFlavour*/ 0, /*EHFlavor*/ 0,
+                           /*PC*/ 0, STI.getHwMode()) {}
 
 const MCPhysReg *
 RISCVRegisterInfo::getIPRACSRegs(const MachineFunction *MF) const {
@@ -168,15 +169,15 @@ BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
   if (TFI->hasBP(MF))
     markSuperRegs(Reserved, RISCV::X9); // bp
 
-  markSuperRegs(Reserved, RISCV::C0); // cnull
-  markSuperRegs(Reserved, RISCV::C2); // csp
-  markSuperRegs(Reserved, RISCV::C3); // cgp
+  markSuperRegs(Reserved, RISCV::X0_Y); // cnull
+  markSuperRegs(Reserved, RISCV::X2_Y); // csp
+  markSuperRegs(Reserved, RISCV::X3_Y); // cgp
   if (STI.getTargetABI() != RISCVABI::ABI_CHERIOT && STI.getTargetABI() != RISCVABI::ABI_CHERIOT_BAREMETAL)
-    markSuperRegs(Reserved, RISCV::C4); // ctp
+    markSuperRegs(Reserved, RISCV::X4_Y); // ctp
   if (TFI->hasFP(MF))
-    markSuperRegs(Reserved, RISCV::C8); // cfp
+    markSuperRegs(Reserved, RISCV::X8_Y); // cfp
   if (TFI->hasBP(MF))
-    markSuperRegs(Reserved, RISCV::C9); // cbp
+    markSuperRegs(Reserved, RISCV::X9_Y); // cbp
 
   markSuperRegs(Reserved, RISCV::DDC);
 
@@ -655,7 +656,7 @@ bool RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
     if (MI.getOpcode() == RISCV::ADDI || MI.getOpcode() == RISCV::CIncOffsetImm)
       DestReg = MI.getOperand(0).getReg();
     else if (RISCVABI::isCheriPureCapABI(ST.getTargetABI()))
-      DestReg = MRI.createVirtualRegister(&RISCV::GPCRRegClass);
+      DestReg = MRI.createVirtualRegister(&RISCV::YGPRRegClass);
     else
       DestReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
     adjustReg(*II->getParent(), II, DL, DestReg, FrameReg, Offset,
@@ -757,8 +758,8 @@ bool RISCVRegisterInfo::needsFrameBaseReg(MachineInstr *MI,
 
       if (RISCV::GPRRegClass.contains(Reg))
         CalleeSavedSize += getSpillSize(RISCV::GPRRegClass);
-       if (RISCV::GPCRRegClass.contains(Reg))
-        CalleeSavedSize += getSpillSize(RISCV::GPCRRegClass);
+      if (RISCV::YGPRRegClass.contains(Reg))
+        CalleeSavedSize += getSpillSize(RISCV::YGPRRegClass);
       else if (RISCV::FPR64RegClass.contains(Reg))
         CalleeSavedSize += getSpillSize(RISCV::FPR64RegClass);
       else if (RISCV::FPR32RegClass.contains(Reg))
@@ -814,7 +815,7 @@ Register RISCVRegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB,
   Register BaseReg;
   if (RISCVABI::isCheriPureCapABI(ST.getTargetABI())) {
     Opc = RISCV::CIncOffsetImm;
-    BaseReg = MFI.createVirtualRegister(&RISCV::GPCRRegClass);
+    BaseReg = MFI.createVirtualRegister(&RISCV::YGPRRegClass);
   } else {
     Opc = RISCV::ADDI;
     BaseReg = MFI.createVirtualRegister(&RISCV::GPRRegClass);
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
index 4df938b831578..10b570648dbb2 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
@@ -52,18 +52,15 @@ class RISCVReg128<RISCVReg64 subreg>
   let SubRegIndices = [sub_64];
 }
 
-// I don't think the size matters here as it's only used if there are multiple
-// sub-registers involved to calculate coverings and other relationships, but
-// we have a simple nesting here with no inference required. Since XLen is
-// based on runtime flags and SubRegIndex wants an integer literal it's awkward
-// to express this properly without introducing separate 32/64-bit registers,
-// classes etc.
-def sub_cap_addr : SubRegIndex<-1, -1>;
-class RISCVCapReg<RISCVRegWithSubRegs subreg, string n, list<string> alt = []> : Register<n> {
-  let HWEncoding{4-0} = subreg.HWEncoding{4-0};
-  let SubRegs = [subreg];
+// A subreg index for the address part of capability registers (this is just the
+// default XLEN-wide X<N> register).
+def sub_cap_addr : SubRegIndex<32> {
+  let SubRegRanges =
+      SubRegRangeByHwMode<[RV32, RV64], [SubRegRange<32>, SubRegRange<64>]>;
+}
+class RISCVCapReg<RISCVRegWithSubRegs subreg, string n, list<string> alt = []>
+    : RISCVRegWithSubRegs<subreg.HWEncoding{4 -0}, n, [subreg], alt> {
   let SubRegIndices = [sub_cap_addr];
-  let AltNames = alt;
 }
 
 class RISCVCapRegPseudo<bits<5> Enc, string n, list<string> alt = []> : Register<n> {
@@ -230,44 +227,69 @@ let RegAltNameIndices = [ABIRegAltName] in {
   def X31 : RISCVRegWithSubRegs<31,"x31", [X31_W], ["t6"]>, DwarfRegNum<[31]>;
   }
   }
-
-  // TODO: Review costs
-  let isConstant = true in
-  def C0  : RISCVCapReg<X0, "c0", ["cnull"]>, DwarfRegNum<[0]>;
-  let CostPerUse = [1] in {
-  def C1  : RISCVCapReg<X1, "c1", ["cra"]>, DwarfRegNum<[1]>;
-  def C2  : RISCVCapReg<X2, "c2", ["csp"]>, DwarfRegNum<[2]>;
-  def C3  : RISCVCapReg<X3, "c3", ["cgp"]>, DwarfRegNum<[3]>;
-  def C4  : RISCVCapReg<X4, "c4", ["ctp"]>, DwarfRegNum<[4]>;
-  def C5  : RISCVCapReg<X5, "c5", ["ct0"]>, DwarfRegNum<[5]>;
-  def C6  : RISCVCapReg<X6, "c6", ["ct1"]>, DwarfRegNum<[6]>;
-  def C7  : RISCVCapReg<X7, "c7", ["ct2"]>, DwarfRegNum<[7]>;
-  }
-  def C8  : RISCVCapReg<X8, "c8", ["cs0", "cfp"]>, DwarfRegNum<[8]>;
-  def C9  : RISCVCapReg<X9, "c9", ["cs1"]>, DwarfRegNum<[9]>;
-  def C10 : RISCVCapReg<X10,"c10", ["ca0"]>, DwarfRegNum<[10]>;
-  def C11 : RISCVCapReg<X11,"c11", ["ca1"]>, DwarfRegNum<[11]>;
-  def C12 : RISCVCapReg<X12,"c12", ["ca2"]>, DwarfRegNum<[12]>;
-  def C13 : RISCVCapReg<X13,"c13", ["ca3"]>, DwarfRegNum<[13]>;
-  def C14 : RISCVCapReg<X14,"c14", ["ca4"]>, DwarfRegNum<[14]>;
-  def C15 : RISCVCapReg<X15,"c15", ["ca5"]>, DwarfRegNum<[15]>;
-  let CostPerUse = [1] in {
-  def C16 : RISCVCapReg<X16,"c16", ["ca6"]>, DwarfRegNum<[16]>;
-  def C17 : RISCVCapReg<X17,"c17", ["ca7"]>, DwarfRegNum<[17]>;
-  def C18 : RISCVCapReg<X18,"c18", ["cs2"]>, DwarfRegNum<[18]>;
-  def C19 : RISCVCapReg<X19,"c19", ["cs3"]>, DwarfRegNum<[19]>;
-  def C20 : RISCVCapReg<X20,"c20", ["cs4"]>, DwarfRegNum<[20]>;
-  def C21 : RISCVCapReg<X21,"c21", ["cs5"]>, DwarfRegNum<[21]>;
-  def C22 : RISCVCapReg<X22,"c22", ["cs6"]>, DwarfRegNum<[22]>;
-  def C23 : RISCVCapReg<X23,"c23", ["cs7"]>, DwarfRegNum<[23]>;
-  def C24 : RISCVCapReg<X24,"c24", ["cs8"]>, DwarfRegNum<[24]>;
-  def C25 : RISCVCapReg<X25,"c25", ["cs9"]>, DwarfRegNum<[25]>;
-  def C26 : RISCVCapReg<X26,"c26", ["cs10"]>, DwarfRegNum<[26]>;
-  def C27 : RISCVCapReg<X27,"c27", ["cs11"]>, DwarfRegNum<[27]>;
-  def C28 : RISCVCapReg<X28,"c28", ["ct3"]>, DwarfRegNum<[28]>;
-  def C29 : RISCVCapReg<X29,"c29", ["ct4"]>, DwarfRegNum<[29]>;
-  def C30 : RISCVCapReg<X30,"c30", ["ct5"]>, DwarfRegNum<[30]>;
-  def C31 : RISCVCapReg<X31,"c31", ["ct6"]>, DwarfRegNum<[31]>;
+  // CHERI capability registers (Y extension)
+  let SubRegIndices = [sub_cap_addr] in {
+    let isConstant = true in def X0_Y
+        : RISCVCapReg<X0, "x0", ["zero", "null", "c0", "czero", "cnull"]>,
+        DwarfRegAlias<X0>;
+    let CostPerUse = [0, 1] in {
+      def X1_Y : RISCVCapReg<X1, "x1", ["ra", "c1", "cra"]>, DwarfRegAlias<X1>;
+      def X2_Y : RISCVCapReg<X2, "x2", ["sp", "c2", "csp"]>, DwarfRegAlias<X2>;
+      def X3_Y : RISCVCapReg<X3, "x3", ["gp", "c3", "cgp"]>, DwarfRegAlias<X3>;
+      def X4_Y : RISCVCapReg<X4, "x4", ["tp", "c4", "ctp"]>, DwarfRegAlias<X4>;
+      def X5_Y : RISCVCapReg<X5, "x5", ["t0", "c5", "ct0"]>, DwarfRegAlias<X5>;
+      def X6_Y : RISCVCapReg<X6, "x6", ["t1", "c6", "ct1"]>, DwarfRegAlias<X6>;
+      def X7_Y : RISCVCapReg<X7, "x7", ["t2", "c7", "ct2"]>, DwarfRegAlias<X7>;
+    }
+    def X8_Y : RISCVCapReg<X8, "x8", ["s0", "fp", "c8", "cs0", "cfp"]>,
+               DwarfRegAlias<X8>;
+    def X9_Y : RISCVCapReg<X9, "x9", ["s1", "c9", "cs1"]>, DwarfRegAlias<X9>;
+    def X10_Y : RISCVCapReg<X10, "x10", ["a0", "c10", "ca0"]>,
+                DwarfRegAlias<X0>;
+    def X11_Y : RISCVCapReg<X11, "x11", ["a1", "c11", "ca1"]>,
+                DwarfRegAlias<X1>;
+    def X12_Y : RISCVCapReg<X12, "x12", ["a2", "c12", "ca2"]>,
+                DwarfRegAlias<X2>;
+    def X13_Y : RISCVCapReg<X13, "x13", ["a3", "c13", "ca3"]>,
+                DwarfRegAlias<X3>;
+    def X14_Y : RISCVCapReg<X14, "x14", ["a4", "c14", "ca4"]>,
+                DwarfRegAlias<X4>;
+    def X15_Y : RISCVCapReg<X15, "x15", ["a5", "c15", "ca5"]>,
+                DwarfRegAlias<X5>;
+    let CostPerUse = [0, 1] in {
+      def X16_Y : RISCVCapReg<X16, "x16", ["a6", "c16", "ca6"]>,
+                  DwarfRegAlias<X16>;
+      def X17_Y : RISCVCapReg<X17, "x17", ["a7", "c17", "ca7"]>,
+                  DwarfRegAlias<X17>;
+      def X18_Y : RISCVCapReg<X18, "x18", ["s2", "c18", "cs2"]>,
+                  DwarfRegAlias<X18>;
+      def X19_Y : RISCVCapReg<X19, "x19", ["s3", "c19", "cs3"]>,
+                  DwarfRegAlias<X19>;
+      def X20_Y : RISCVCapReg<X20, "x20", ["s4", "c20", "cs4"]>,
+                  DwarfRegAlias<X20>;
+      def X21_Y : RISCVCapReg<X21, "x21", ["s5", "c21", "cs5"]>,
+                  DwarfRegAlias<X21>;
+      def X22_Y : RISCVCapReg<X22, "x22", ["s6", "c22", "cs6"]>,
+                  DwarfRegAlias<X22>;
+      def X23_Y : RISCVCapReg<X23, "x23", ["s7", "c23", "cs7"]>,
+                  DwarfRegAlias<X23>;
+      def X24_Y : RISCVCapReg<X24, "x24", ["s8", "c24", "cs8"]>,
+                  DwarfRegAlias<X24>;
+      def X25_Y : RISCVCapReg<X25, "x25", ["s9", "c25", "cs9"]>,
+                  DwarfRegAlias<X25>;
+      def X26_Y : RISCVCapReg<X26, "x26", ["s10", "c26", "cs10"]>,
+                  DwarfRegAlias<X26>;
+      def X27_Y : RISCVCapReg<X27, "x27", ["s11", "c27", "cs11"]>,
+                  DwarfRegAlias<X27>;
+      def X28_Y : RISCVCapReg<X28, "x28", ["t3", "c28", "ct3"]>,
+                  DwarfRegAlias<X28>;
+      def X29_Y : RISCVCapReg<X29, "x29", ["t4", "c29", "ct4"]>,
+                  DwarfRegAlias<X29>;
+      def X30_Y : RISCVCapReg<X30, "x30", ["t5", "c30", "ct5"]>,
+                  DwarfRegAlias<X30>;
+      def X31_Y : RISCVCapReg<X31, "x31", ["t6", "c31", "ct6"]>,
+                  DwarfRegAlias<X31>;
+    }
   }
 
   // This is the encoding of DDC when C0 means DDC, and not the encoding of DDC
@@ -287,13 +309,10 @@ def XLenPairFVT : ValueTypeByHwMode<[RV32],
 def XLenRI : RegInfoByHwMode<
       [RV32,              RV64],
       [RegInfo<32,32,32>, RegInfo<64,64,64>]>;
-def CLenVT : ValueTypeByHwMode<[RV32, RV64],
-                               [c64, c128]>;
-def CLenFloatVT : ValueTypeByHwMode<[RV32, RV64], [f64, f128]>;
-
-def CLenRI : RegInfoByHwMode<
-      [RV32,              RV64],
-      [RegInfo<64,64,64>, RegInfo<128,128,128>]>;
+def YLenVT : ValueTypeByHwMode<[RV32, RV64], [c64, c128]>;
+def YLenRI : RegInfoByHwMode<[RV32, RV64], [RegInfo<64, 64, 64>,
+                                            RegInfo<128, 128, 128>]>;
+def YLenFloatVT : ValueTypeByHwMode<[RV32, RV64], [f64, f128]>;
 
 class RISCVRegisterClass<list<ValueType> regTypes, int align, dag regList>
     : RegisterClass<"RISCV", regTypes, align, regList> {
@@ -320,12 +339,12 @@ def GPR : GPRRegisterClass<(add (sequence "X%u", 10, 17),
                                 (sequence "X%u", 18, 27),
                                 (sequence "X%u", 0, 4))>;
 
-def GPCR
-    : RegisterClass<"RISCV", [CLenVT, CLenFloatVT], 64,
-                    (add(sequence "C%u", 10, 17), (sequence "C%u", 5, 7),
-                        (sequence "C%u", 28, 31), (sequence "C%u", 8, 9),
-                        (sequence "C%u", 18, 27), (sequence "C%u", 0, 4))> {
-  let RegInfos = CLenRI;
+def YGPR
+    : RegisterClass<"RISCV", [YLenVT, YLenFloatVT], 64,
+                    (add(sequence "X%u_Y", 10, 17), (sequence "X%u_Y", 5, 7),
+                        (sequence "X%u_Y", 28, 31), (sequence "X%u_Y", 8, 9),
+                        (sequence "X%u_Y", 18, 27), (sequence "X%u_Y", 0, 4))> {
+  let RegInfos = YLenRI;
 }
 
 def GPRE : RegisterClass<"RISCV", [XLenVT, i32], 32,
@@ -334,19 +353,20 @@ def GPRE : RegisterClass<"RISCV", [XLenVT, i32], 32,
   let RegInfos = XLenRI;
 }
 
-def GPCRE : RegisterClass<"RISCV", [CLenVT, CLenFloatVT], 64,
-                          (add(sequence "C%u", 10, 15), (sequence "C%u", 5, 7),
-                              (sequence "C%u", 8, 9), (sequence "C%u", 0, 4))> {
-  let RegInfos = CLenRI;
+def YGPRE
+    : RegisterClass<"RISCV", [YLenVT, YLenFloatVT], 64,
+                    (add(sequence "X%u_Y", 10, 15), (sequence "X%u_Y", 5, 7),
+                        (sequence "X%u_Y", 8, 9), (sequence "X%u_Y", 0, 4))> {
+  let RegInfos = YLenRI;
 }
 
-def GPCRC0IsDDC
-    : RegisterClass<"RISCV", [CLenVT, CLenFloatVT], 64,
-                    (add(sequence "C%u", 10, 17), (sequence "C%u", 5, 7),
-                        (sequence "C%u", 28, 31), (sequence "C%u", 8, 9),
-                        (sequence "C%u", 18, 27), (sequence "C%u", 1, 4),
+def YGPRX0IsDDC
+    : RegisterClass<"RISCV", [YLenVT, YLenFloatVT], 64,
+                    (add(sequence "X%u_Y", 10, 17), (sequence "X%u_Y", 5, 7),
+                        (sequence "X%u_Y", 28, 31), (sequence "X%u_Y", 8, 9),
+                        (sequence "X%u_Y", 18, 27), (sequence "X%u_Y", 1, 4),
                         DDC)> {
-  let RegInfos = CLenRI;
+  let RegInfos = YLenRI;
 }
 
 def GPRX0 : GPRRegisterClass<(add X0)>;
@@ -373,14 +393,14 @@ def GPRNoX0X2 : GPRRegisterClass<(sub GPR, X0, X2)> {
 
 def GPRX7 : GPRRegisterClass<(add X7)>;
 
-def GPCRNoC0
-    : RegisterClass<"RISCV", [CLenVT, CLenFloatVT], 64, (sub GPCR, C0)> {
-  let RegInfos = CLenRI;
+def YGPRNoX0
+    : RegisterClass<"RISCV", [YLenVT, YLenFloatVT], 64, (sub YGPR, X0_Y)> {
+  let RegInfos = YLenRI;
 }
 
-def GPCRNoC0C1
-    : RegisterClass<"RISCV", [CLenVT, CLenFloatVT], 64, (sub GPCRNoC0, C1)> {
-  let RegInfos = CLenRI;
+def YGPRNoX0X1
+    : RegisterClass<"RISCV", [YLenVT, YLenFloatVT], 64, (sub YGPRNoX0, X1_Y)> {
+  let RegInfos = YLenRI;
 }
 
 // Don't use X1 or X5 for JALR since that is a hint to pop the return address
@@ -394,10 +414,10 @@ def GPRJALRNonX7 : GPRRegisterClass<(sub GPRJALR, X7)>;
 def GPRC : GPRRegisterClass<(add (sequence "X%u", 10, 15),
                                  (sequence "X%u", 8, 9))>;
 
-def GPCRC
-    : RegisterClass<"RISCV", [CLenVT, CLenFloatVT], 64,
-                    (add(sequence "C%u", 10, 15), (sequence "C%u", 8, 9))> {
-  let RegInfos = CLenRI;
+def YGPRC
+    : RegisterClass<"RISCV", [YLenVT, YLenFloatVT], 64,
+                    (add(sequence "X%u_Y", 10, 15), (sequence "X%u_Y", 8, 9))> {
+  let RegInfos = YLenRI;
 }
 
 // For indirect tail calls, we can't use callee-saved registers, as they are
@@ -409,10 +429,11 @@ def GPRTC : GPRRegisterClass<(add (sequence "X%u", 6, 7),
                                   (sequence "X%u", 28, 31))>;
 def GPRTCNonX7 : GPRRegisterClass<(sub GPRTC, X7)>;
 
-def GPCRTC : RegisterClass<"RISCV", [CLenVT, CLenFloatVT], 64,
-                           (add(sequence "C%u", 5, 7), (sequence "C%u", 10, 17),
-                               (sequence "C%u", 28, 31))> {
-  let RegInfos = CLenRI;
+def YGPRTC
+    : RegisterClass<"RISCV", [YLenVT, YLenFloatVT], 64,
+                    (add(sequence "X%u_Y", 5, 7), (sequence "X%u_Y", 10, 17),
+                        (sequence "X%u_Y", 28, 31))> {
+  let RegInfos = YLenRI;
 }
 
 def SP : GPRRegisterClass<(add X2)> {
@@ -420,8 +441,8 @@ def SP : GPRRegisterClass<(add X2)> {
   let DiagnosticString = "register must be sp (x2)";
 }
 
-def CSP : RegisterClass<"RISCV", [CLenVT, CLenFloatVT], 64, (add C2)> {
-  let RegInfos = CLenRI;
+def CSP : RegisterClass<"RISCV", [YLenVT, YLenFloatVT], 64, (add X2_Y)> {
+  let RegInfos = YLenRI;
 }
 
 // Saved Registers from s0 to s7, for C.MVA01S07 instruction in Zcmp extension
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/atomic-rmw-cap-ptr-arg.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/atomic-rmw-cap-ptr-arg.ll
index 8f05b529a6c93..1cae67bcc4191 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/atomic-rmw-cap-ptr-arg.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/atomic-rmw-cap-ptr-arg.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --scrub-attributes --version 2
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
 ; DO NOT EDIT -- This file was generated from test/CodeGen/CHERI-Generic/Inputs/atomic-rmw-cap-ptr-arg.ll
 ; Check that we can generate sensible code for atomic operations using capability pointers on capabilities
 ; See https://github.com/CTSRD-CHERI/llvm-project/issues/470
@@ -10,17 +10,17 @@
 define i32 addrspace(200)* @atomic_cap_ptr_xchg_sc(i32 addrspace(200)* addrspace(200)* %ptr, i32 addrspace(200)* %val) nounwind {
 ; PURECAP-ATOMICS-LABEL: atomic_cap_ptr_xchg_sc:
 ; PURECAP-ATOMICS:       # %bb.0:
-; PURECAP-ATOMICS-NEXT:    camoswap.c.aqrl ca0, ca1, (ca0)
+; PURECAP-ATOMICS-NEXT:    camoswap.c.aqrl a0, a1, (a0)
 ; PURECAP-ATOMICS-NEXT:    cret
 ;
 ; PURECAP-LIBCALLS-LABEL: atomic_cap_ptr_xchg_sc:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -16
-; PURECAP-LIBCALLS-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -16
+; PURECAP-LIBCALLS-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; PURECAP-LIBCALLS-NEXT:    li a2, 5
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_exchange_cap
-; PURECAP-LIBCALLS-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 16
+; PURECAP-LIBCALLS-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 16
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: atomic_cap_ptr_xchg_sc:
@@ -39,17 +39,17 @@ define i32 addrspace(200)* @atomic_cap_ptr_xchg_sc(i32 addrspace(200)* addrspace
 define i32 addrspace(200)* @atomic_cap_ptr_xchg_relaxed(i32 addrspace(200)* addrspace(200)* %ptr, i32 addrspace(200)* %val) nounwind {
 ; PURECAP-ATOMICS-LABEL: atomic_cap_ptr_xchg_relaxed:
 ; PURECAP-ATOMICS:       # %bb.0:
-; PURECAP-ATOMICS-NEXT:    camoswap.c ca0, ca1, (ca0)
+; PURECAP-ATOMICS-NEXT:    camoswap.c a0, a1, (a0)
 ; PURECAP-ATOMICS-NEXT:    cret
 ;
 ; PURECAP-LIBCALLS-LABEL: atomic_cap_ptr_xchg_relaxed:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -16
-; PURECAP-LIBCALLS-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -16
+; PURECAP-LIBCALLS-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; PURECAP-LIBCALLS-NEXT:    li a2, 0
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_exchange_cap
-; PURECAP-LIBCALLS-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 16
+; PURECAP-LIBCALLS-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 16
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: atomic_cap_ptr_xchg_relaxed:
@@ -68,17 +68,17 @@ define i32 addrspace(200)* @atomic_cap_ptr_xchg_relaxed(i32 addrspace(200)* addr
 define i32 addrspace(200)* @atomic_cap_ptr_xchg_acquire(i32 addrspace(200)* addrspace(200)* %ptr, i32 addrspace(200)* %val) nounwind {
 ; PURECAP-ATOMICS-LABEL: atomic_cap_ptr_xchg_acquire:
 ; PURECAP-ATOMICS:       # %bb.0:
-; PURECAP-ATOMICS-NEXT:    camoswap.c.aq ca0, ca1, (ca0)
+; PURECAP-ATOMICS-NEXT:    camoswap.c.aq a0, a1, (a0)
 ; PURECAP-ATOMICS-NEXT:    cret
 ;
 ; PURECAP-LIBCALLS-LABEL: atomic_cap_ptr_xchg_acquire:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -16
-; PURECAP-LIBCALLS-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -16
+; PURECAP-LIBCALLS-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; PURECAP-LIBCALLS-NEXT:    li a2, 2
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_exchange_cap
-; PURECAP-LIBCALLS-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 16
+; PURECAP-LIBCALLS-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 16
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: atomic_cap_ptr_xchg_acquire:
@@ -97,17 +97,17 @@ define i32 addrspace(200)* @atomic_cap_ptr_xchg_acquire(i32 addrspace(200)* addr
 define i32 addrspace(200)* @atomic_cap_ptr_xchg_rel(i32 addrspace(200)* addrspace(200)* %ptr, i32 addrspace(200)* %val) nounwind {
 ; PURECAP-ATOMICS-LABEL: atomic_cap_ptr_xchg_rel:
 ; PURECAP-ATOMICS:       # %bb.0:
-; PURECAP-ATOMICS-NEXT:    camoswap.c.rl ca0, ca1, (ca0)
+; PURECAP-ATOMICS-NEXT:    camoswap.c.rl a0, a1, (a0)
 ; PURECAP-ATOMICS-NEXT:    cret
 ;
 ; PURECAP-LIBCALLS-LABEL: atomic_cap_ptr_xchg_rel:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -16
-; PURECAP-LIBCALLS-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -16
+; PURECAP-LIBCALLS-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; PURECAP-LIBCALLS-NEXT:    li a2, 3
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_exchange_cap
-; PURECAP-LIBCALLS-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 16
+; PURECAP-LIBCALLS-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 16
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: atomic_cap_ptr_xchg_rel:
@@ -126,17 +126,17 @@ define i32 addrspace(200)* @atomic_cap_ptr_xchg_rel(i32 addrspace(200)* addrspac
 define i32 addrspace(200)* @atomic_cap_ptr_xchg_acq_rel(i32 addrspace(200)* addrspace(200)* %ptr, i32 addrspace(200)* %val) nounwind {
 ; PURECAP-ATOMICS-LABEL: atomic_cap_ptr_xchg_acq_rel:
 ; PURECAP-ATOMICS:       # %bb.0:
-; PURECAP-ATOMICS-NEXT:    camoswap.c.aqrl ca0, ca1, (ca0)
+; PURECAP-ATOMICS-NEXT:    camoswap.c.aqrl a0, a1, (a0)
 ; PURECAP-ATOMICS-NEXT:    cret
 ;
 ; PURECAP-LIBCALLS-LABEL: atomic_cap_ptr_xchg_acq_rel:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -16
-; PURECAP-LIBCALLS-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -16
+; PURECAP-LIBCALLS-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; PURECAP-LIBCALLS-NEXT:    li a2, 4
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_exchange_cap
-; PURECAP-LIBCALLS-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 16
+; PURECAP-LIBCALLS-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 16
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: atomic_cap_ptr_xchg_acq_rel:
@@ -156,17 +156,17 @@ define i32 addrspace(200)* @atomic_cap_ptr_xchg_acq_rel(i32 addrspace(200)* addr
 define i32 addrspace(200)* @atomic_cap_ptr_xchg_i32ptr(i32 addrspace(200)* addrspace(200)* %ptr, i32 addrspace(200)* %val) nounwind {
 ; PURECAP-ATOMICS-LABEL: atomic_cap_ptr_xchg_i32ptr:
 ; PURECAP-ATOMICS:       # %bb.0:
-; PURECAP-ATOMICS-NEXT:    camoswap.c.aqrl ca0, ca1, (ca0)
+; PURECAP-ATOMICS-NEXT:    camoswap.c.aqrl a0, a1, (a0)
 ; PURECAP-ATOMICS-NEXT:    cret
 ;
 ; PURECAP-LIBCALLS-LABEL: atomic_cap_ptr_xchg_i32ptr:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -16
-; PURECAP-LIBCALLS-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -16
+; PURECAP-LIBCALLS-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; PURECAP-LIBCALLS-NEXT:    li a2, 4
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_exchange_cap
-; PURECAP-LIBCALLS-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 16
+; PURECAP-LIBCALLS-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 16
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: atomic_cap_ptr_xchg_i32ptr:
@@ -186,69 +186,69 @@ define i32 addrspace(200)* @atomic_cap_ptr_add(i32 addrspace(200)* addrspace(200
 ; PURECAP-ATOMICS-LABEL: atomic_cap_ptr_add:
 ; PURECAP-ATOMICS:       # %bb.0:
 ; PURECAP-ATOMICS-NEXT:  .LBB6_1: # =>This Inner Loop Header: Depth=1
-; PURECAP-ATOMICS-NEXT:    clr.c.aqrl ca2, (ca0)
-; PURECAP-ATOMICS-NEXT:    cincoffset ca3, ca2, a1
-; PURECAP-ATOMICS-NEXT:    csc.c.aqrl a3, ca3, (ca0)
+; PURECAP-ATOMICS-NEXT:    clr.c.aqrl a2, (a0)
+; PURECAP-ATOMICS-NEXT:    cincoffset a3, a2, a1
+; PURECAP-ATOMICS-NEXT:    csc.c.aqrl a3, a3, (a0)
 ; PURECAP-ATOMICS-NEXT:    bnez a3, .LBB6_1
 ; PURECAP-ATOMICS-NEXT:  # %bb.2:
-; PURECAP-ATOMICS-NEXT:    cmove ca0, ca2
+; PURECAP-ATOMICS-NEXT:    cmove a0, a2
 ; PURECAP-ATOMICS-NEXT:    cret
 ;
 ; PURECAP-LIBCALLS-LABEL: atomic_cap_ptr_add:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -48
-; PURECAP-LIBCALLS-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    cmove cs2, ca1
-; PURECAP-LIBCALLS-NEXT:    cmove cs1, ca0
-; PURECAP-LIBCALLS-NEXT:    clc ca1, 0(ca0)
-; PURECAP-LIBCALLS-NEXT:    cincoffset ca0, csp, 8
-; PURECAP-LIBCALLS-NEXT:    csetbounds cs0, ca0, 8
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -48
+; PURECAP-LIBCALLS-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    cmove s0, a1
+; PURECAP-LIBCALLS-NEXT:    cmove s1, a0
+; PURECAP-LIBCALLS-NEXT:    clc a1, 0(a0)
+; PURECAP-LIBCALLS-NEXT:    cincoffset a0, sp, 8
+; PURECAP-LIBCALLS-NEXT:    csetbounds s2, a0, 8
 ; PURECAP-LIBCALLS-NEXT:  .LBB6_1: # %atomicrmw.start
 ; PURECAP-LIBCALLS-NEXT:    # =>This Inner Loop Header: Depth=1
-; PURECAP-LIBCALLS-NEXT:    add a0, a1, s2
-; PURECAP-LIBCALLS-NEXT:    csetaddr ca2, ca1, a0
-; PURECAP-LIBCALLS-NEXT:    csc ca1, 8(csp)
+; PURECAP-LIBCALLS-NEXT:    add a0, a1, s0
+; PURECAP-LIBCALLS-NEXT:    csetaddr a2, a1, a0
+; PURECAP-LIBCALLS-NEXT:    csc a1, 8(sp)
 ; PURECAP-LIBCALLS-NEXT:    li a3, 5
 ; PURECAP-LIBCALLS-NEXT:    li a4, 5
-; PURECAP-LIBCALLS-NEXT:    cmove ca0, cs1
-; PURECAP-LIBCALLS-NEXT:    cmove ca1, cs0
+; PURECAP-LIBCALLS-NEXT:    cmove a0, s1
+; PURECAP-LIBCALLS-NEXT:    cmove a1, s2
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_compare_exchange_cap
-; PURECAP-LIBCALLS-NEXT:    clc ca1, 8(csp)
+; PURECAP-LIBCALLS-NEXT:    clc a1, 8(sp)
 ; PURECAP-LIBCALLS-NEXT:    beqz a0, .LBB6_1
 ; PURECAP-LIBCALLS-NEXT:  # %bb.2: # %atomicrmw.end
-; PURECAP-LIBCALLS-NEXT:    cmove ca0, ca1
-; PURECAP-LIBCALLS-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 48
+; PURECAP-LIBCALLS-NEXT:    cmove a0, a1
+; PURECAP-LIBCALLS-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 48
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: atomic_cap_ptr_add:
 ; HYBRID:       # %bb.0:
 ; HYBRID-NEXT:    addi sp, sp, -32
 ; HYBRID-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
-; HYBRID-NEXT:    sc ca0, 8(sp) # 8-byte Folded Spill
-; HYBRID-NEXT:    lc.cap ca3, (ca0)
-; HYBRID-NEXT:    sc ca1, 0(sp) # 8-byte Folded Spill
+; HYBRID-NEXT:    sc a0, 8(sp) # 8-byte Folded Spill
+; HYBRID-NEXT:    lc.cap a3, (a0)
+; HYBRID-NEXT:    sc a1, 0(sp) # 8-byte Folded Spill
 ; HYBRID-NEXT:  .LBB6_1: # %atomicrmw.start
 ; HYBRID-NEXT:    # =>This Inner Loop Header: Depth=1
-; HYBRID-NEXT:    lc ca0, 0(sp) # 8-byte Folded Reload
+; HYBRID-NEXT:    lc a0, 0(sp) # 8-byte Folded Reload
 ; HYBRID-NEXT:    add a0, a3, a0
-; HYBRID-NEXT:    csetaddr ca2, ca3, a0
-; HYBRID-NEXT:    sc ca3, 16(sp)
+; HYBRID-NEXT:    csetaddr a2, a3, a0
+; HYBRID-NEXT:    sc a3, 16(sp)
 ; HYBRID-NEXT:    addi a1, sp, 16
 ; HYBRID-NEXT:    li a3, 5
 ; HYBRID-NEXT:    li a4, 5
-; HYBRID-NEXT:    lc ca0, 8(sp) # 8-byte Folded Reload
+; HYBRID-NEXT:    lc a0, 8(sp) # 8-byte Folded Reload
 ; HYBRID-NEXT:    call __atomic_compare_exchange_cap_c
-; HYBRID-NEXT:    lc ca3, 16(sp)
+; HYBRID-NEXT:    lc a3, 16(sp)
 ; HYBRID-NEXT:    beqz a0, .LBB6_1
 ; HYBRID-NEXT:  # %bb.2: # %atomicrmw.end
-; HYBRID-NEXT:    cmove ca0, ca3
+; HYBRID-NEXT:    cmove a0, a3
 ; HYBRID-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; HYBRID-NEXT:    addi sp, sp, 32
 ; HYBRID-NEXT:    ret
@@ -260,70 +260,70 @@ define i32 addrspace(200)* @atomic_cap_ptr_sub(i32 addrspace(200)* addrspace(200
 ; PURECAP-ATOMICS-LABEL: atomic_cap_ptr_sub:
 ; PURECAP-ATOMICS:       # %bb.0:
 ; PURECAP-ATOMICS-NEXT:  .LBB7_1: # =>This Inner Loop Header: Depth=1
-; PURECAP-ATOMICS-NEXT:    clr.c.aqrl ca2, (ca0)
+; PURECAP-ATOMICS-NEXT:    clr.c.aqrl a2, (a0)
 ; PURECAP-ATOMICS-NEXT:    sub a3, a2, a1
-; PURECAP-ATOMICS-NEXT:    csetaddr ca3, ca2, a3
-; PURECAP-ATOMICS-NEXT:    csc.c.aqrl a3, ca3, (ca0)
+; PURECAP-ATOMICS-NEXT:    csetaddr a3, a2, a3
+; PURECAP-ATOMICS-NEXT:    csc.c.aqrl a3, a3, (a0)
 ; PURECAP-ATOMICS-NEXT:    bnez a3, .LBB7_1
 ; PURECAP-ATOMICS-NEXT:  # %bb.2:
-; PURECAP-ATOMICS-NEXT:    cmove ca0, ca2
+; PURECAP-ATOMICS-NEXT:    cmove a0, a2
 ; PURECAP-ATOMICS-NEXT:    cret
 ;
 ; PURECAP-LIBCALLS-LABEL: atomic_cap_ptr_sub:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -48
-; PURECAP-LIBCALLS-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    cmove cs2, ca1
-; PURECAP-LIBCALLS-NEXT:    cmove cs1, ca0
-; PURECAP-LIBCALLS-NEXT:    clc ca1, 0(ca0)
-; PURECAP-LIBCALLS-NEXT:    cincoffset ca0, csp, 8
-; PURECAP-LIBCALLS-NEXT:    csetbounds cs0, ca0, 8
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -48
+; PURECAP-LIBCALLS-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    cmove s0, a1
+; PURECAP-LIBCALLS-NEXT:    cmove s1, a0
+; PURECAP-LIBCALLS-NEXT:    clc a1, 0(a0)
+; PURECAP-LIBCALLS-NEXT:    cincoffset a0, sp, 8
+; PURECAP-LIBCALLS-NEXT:    csetbounds s2, a0, 8
 ; PURECAP-LIBCALLS-NEXT:  .LBB7_1: # %atomicrmw.start
 ; PURECAP-LIBCALLS-NEXT:    # =>This Inner Loop Header: Depth=1
-; PURECAP-LIBCALLS-NEXT:    sub a0, a1, s2
-; PURECAP-LIBCALLS-NEXT:    csetaddr ca2, ca1, a0
-; PURECAP-LIBCALLS-NEXT:    csc ca1, 8(csp)
+; PURECAP-LIBCALLS-NEXT:    sub a0, a1, s0
+; PURECAP-LIBCALLS-NEXT:    csetaddr a2, a1, a0
+; PURECAP-LIBCALLS-NEXT:    csc a1, 8(sp)
 ; PURECAP-LIBCALLS-NEXT:    li a3, 5
 ; PURECAP-LIBCALLS-NEXT:    li a4, 5
-; PURECAP-LIBCALLS-NEXT:    cmove ca0, cs1
-; PURECAP-LIBCALLS-NEXT:    cmove ca1, cs0
+; PURECAP-LIBCALLS-NEXT:    cmove a0, s1
+; PURECAP-LIBCALLS-NEXT:    cmove a1, s2
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_compare_exchange_cap
-; PURECAP-LIBCALLS-NEXT:    clc ca1, 8(csp)
+; PURECAP-LIBCALLS-NEXT:    clc a1, 8(sp)
 ; PURECAP-LIBCALLS-NEXT:    beqz a0, .LBB7_1
 ; PURECAP-LIBCALLS-NEXT:  # %bb.2: # %atomicrmw.end
-; PURECAP-LIBCALLS-NEXT:    cmove ca0, ca1
-; PURECAP-LIBCALLS-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 48
+; PURECAP-LIBCALLS-NEXT:    cmove a0, a1
+; PURECAP-LIBCALLS-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 48
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: atomic_cap_ptr_sub:
 ; HYBRID:       # %bb.0:
 ; HYBRID-NEXT:    addi sp, sp, -32
 ; HYBRID-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
-; HYBRID-NEXT:    sc ca0, 8(sp) # 8-byte Folded Spill
-; HYBRID-NEXT:    lc.cap ca3, (ca0)
-; HYBRID-NEXT:    sc ca1, 0(sp) # 8-byte Folded Spill
+; HYBRID-NEXT:    sc a0, 8(sp) # 8-byte Folded Spill
+; HYBRID-NEXT:    lc.cap a3, (a0)
+; HYBRID-NEXT:    sc a1, 0(sp) # 8-byte Folded Spill
 ; HYBRID-NEXT:  .LBB7_1: # %atomicrmw.start
 ; HYBRID-NEXT:    # =>This Inner Loop Header: Depth=1
-; HYBRID-NEXT:    lc ca0, 0(sp) # 8-byte Folded Reload
+; HYBRID-NEXT:    lc a0, 0(sp) # 8-byte Folded Reload
 ; HYBRID-NEXT:    sub a0, a3, a0
-; HYBRID-NEXT:    csetaddr ca2, ca3, a0
-; HYBRID-NEXT:    sc ca3, 16(sp)
+; HYBRID-NEXT:    csetaddr a2, a3, a0
+; HYBRID-NEXT:    sc a3, 16(sp)
 ; HYBRID-NEXT:    addi a1, sp, 16
 ; HYBRID-NEXT:    li a3, 5
 ; HYBRID-NEXT:    li a4, 5
-; HYBRID-NEXT:    lc ca0, 8(sp) # 8-byte Folded Reload
+; HYBRID-NEXT:    lc a0, 8(sp) # 8-byte Folded Reload
 ; HYBRID-NEXT:    call __atomic_compare_exchange_cap_c
-; HYBRID-NEXT:    lc ca3, 16(sp)
+; HYBRID-NEXT:    lc a3, 16(sp)
 ; HYBRID-NEXT:    beqz a0, .LBB7_1
 ; HYBRID-NEXT:  # %bb.2: # %atomicrmw.end
-; HYBRID-NEXT:    cmove ca0, ca3
+; HYBRID-NEXT:    cmove a0, a3
 ; HYBRID-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; HYBRID-NEXT:    addi sp, sp, 32
 ; HYBRID-NEXT:    ret
@@ -335,70 +335,70 @@ define i32 addrspace(200)* @atomic_cap_ptr_and(i32 addrspace(200)* addrspace(200
 ; PURECAP-ATOMICS-LABEL: atomic_cap_ptr_and:
 ; PURECAP-ATOMICS:       # %bb.0:
 ; PURECAP-ATOMICS-NEXT:  .LBB8_1: # =>This Inner Loop Header: Depth=1
-; PURECAP-ATOMICS-NEXT:    clr.c.aqrl ca2, (ca0)
+; PURECAP-ATOMICS-NEXT:    clr.c.aqrl a2, (a0)
 ; PURECAP-ATOMICS-NEXT:    and a3, a2, a1
-; PURECAP-ATOMICS-NEXT:    csetaddr ca3, ca2, a3
-; PURECAP-ATOMICS-NEXT:    csc.c.aqrl a3, ca3, (ca0)
+; PURECAP-ATOMICS-NEXT:    csetaddr a3, a2, a3
+; PURECAP-ATOMICS-NEXT:    csc.c.aqrl a3, a3, (a0)
 ; PURECAP-ATOMICS-NEXT:    bnez a3, .LBB8_1
 ; PURECAP-ATOMICS-NEXT:  # %bb.2:
-; PURECAP-ATOMICS-NEXT:    cmove ca0, ca2
+; PURECAP-ATOMICS-NEXT:    cmove a0, a2
 ; PURECAP-ATOMICS-NEXT:    cret
 ;
 ; PURECAP-LIBCALLS-LABEL: atomic_cap_ptr_and:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -48
-; PURECAP-LIBCALLS-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    cmove cs2, ca1
-; PURECAP-LIBCALLS-NEXT:    cmove cs1, ca0
-; PURECAP-LIBCALLS-NEXT:    clc ca1, 0(ca0)
-; PURECAP-LIBCALLS-NEXT:    cincoffset ca0, csp, 8
-; PURECAP-LIBCALLS-NEXT:    csetbounds cs0, ca0, 8
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -48
+; PURECAP-LIBCALLS-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    cmove s0, a1
+; PURECAP-LIBCALLS-NEXT:    cmove s1, a0
+; PURECAP-LIBCALLS-NEXT:    clc a1, 0(a0)
+; PURECAP-LIBCALLS-NEXT:    cincoffset a0, sp, 8
+; PURECAP-LIBCALLS-NEXT:    csetbounds s2, a0, 8
 ; PURECAP-LIBCALLS-NEXT:  .LBB8_1: # %atomicrmw.start
 ; PURECAP-LIBCALLS-NEXT:    # =>This Inner Loop Header: Depth=1
-; PURECAP-LIBCALLS-NEXT:    and a0, a1, s2
-; PURECAP-LIBCALLS-NEXT:    csetaddr ca2, ca1, a0
-; PURECAP-LIBCALLS-NEXT:    csc ca1, 8(csp)
+; PURECAP-LIBCALLS-NEXT:    and a0, a1, s0
+; PURECAP-LIBCALLS-NEXT:    csetaddr a2, a1, a0
+; PURECAP-LIBCALLS-NEXT:    csc a1, 8(sp)
 ; PURECAP-LIBCALLS-NEXT:    li a3, 5
 ; PURECAP-LIBCALLS-NEXT:    li a4, 5
-; PURECAP-LIBCALLS-NEXT:    cmove ca0, cs1
-; PURECAP-LIBCALLS-NEXT:    cmove ca1, cs0
+; PURECAP-LIBCALLS-NEXT:    cmove a0, s1
+; PURECAP-LIBCALLS-NEXT:    cmove a1, s2
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_compare_exchange_cap
-; PURECAP-LIBCALLS-NEXT:    clc ca1, 8(csp)
+; PURECAP-LIBCALLS-NEXT:    clc a1, 8(sp)
 ; PURECAP-LIBCALLS-NEXT:    beqz a0, .LBB8_1
 ; PURECAP-LIBCALLS-NEXT:  # %bb.2: # %atomicrmw.end
-; PURECAP-LIBCALLS-NEXT:    cmove ca0, ca1
-; PURECAP-LIBCALLS-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 48
+; PURECAP-LIBCALLS-NEXT:    cmove a0, a1
+; PURECAP-LIBCALLS-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 48
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: atomic_cap_ptr_and:
 ; HYBRID:       # %bb.0:
 ; HYBRID-NEXT:    addi sp, sp, -32
 ; HYBRID-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
-; HYBRID-NEXT:    sc ca0, 8(sp) # 8-byte Folded Spill
-; HYBRID-NEXT:    lc.cap ca3, (ca0)
-; HYBRID-NEXT:    sc ca1, 0(sp) # 8-byte Folded Spill
+; HYBRID-NEXT:    sc a0, 8(sp) # 8-byte Folded Spill
+; HYBRID-NEXT:    lc.cap a3, (a0)
+; HYBRID-NEXT:    sc a1, 0(sp) # 8-byte Folded Spill
 ; HYBRID-NEXT:  .LBB8_1: # %atomicrmw.start
 ; HYBRID-NEXT:    # =>This Inner Loop Header: Depth=1
-; HYBRID-NEXT:    lc ca0, 0(sp) # 8-byte Folded Reload
+; HYBRID-NEXT:    lc a0, 0(sp) # 8-byte Folded Reload
 ; HYBRID-NEXT:    and a0, a3, a0
-; HYBRID-NEXT:    csetaddr ca2, ca3, a0
-; HYBRID-NEXT:    sc ca3, 16(sp)
+; HYBRID-NEXT:    csetaddr a2, a3, a0
+; HYBRID-NEXT:    sc a3, 16(sp)
 ; HYBRID-NEXT:    addi a1, sp, 16
 ; HYBRID-NEXT:    li a3, 5
 ; HYBRID-NEXT:    li a4, 5
-; HYBRID-NEXT:    lc ca0, 8(sp) # 8-byte Folded Reload
+; HYBRID-NEXT:    lc a0, 8(sp) # 8-byte Folded Reload
 ; HYBRID-NEXT:    call __atomic_compare_exchange_cap_c
-; HYBRID-NEXT:    lc ca3, 16(sp)
+; HYBRID-NEXT:    lc a3, 16(sp)
 ; HYBRID-NEXT:    beqz a0, .LBB8_1
 ; HYBRID-NEXT:  # %bb.2: # %atomicrmw.end
-; HYBRID-NEXT:    cmove ca0, ca3
+; HYBRID-NEXT:    cmove a0, a3
 ; HYBRID-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; HYBRID-NEXT:    addi sp, sp, 32
 ; HYBRID-NEXT:    ret
@@ -410,73 +410,73 @@ define i32 addrspace(200)* @atomic_cap_ptr_nand(i32 addrspace(200)* addrspace(20
 ; PURECAP-ATOMICS-LABEL: atomic_cap_ptr_nand:
 ; PURECAP-ATOMICS:       # %bb.0:
 ; PURECAP-ATOMICS-NEXT:  .LBB9_1: # =>This Inner Loop Header: Depth=1
-; PURECAP-ATOMICS-NEXT:    clr.c.aqrl ca2, (ca0)
+; PURECAP-ATOMICS-NEXT:    clr.c.aqrl a2, (a0)
 ; PURECAP-ATOMICS-NEXT:    and a3, a2, a1
 ; PURECAP-ATOMICS-NEXT:    not a3, a3
-; PURECAP-ATOMICS-NEXT:    csetaddr ca3, ca2, a3
-; PURECAP-ATOMICS-NEXT:    csc.c.aqrl a3, ca3, (ca0)
+; PURECAP-ATOMICS-NEXT:    csetaddr a3, a2, a3
+; PURECAP-ATOMICS-NEXT:    csc.c.aqrl a3, a3, (a0)
 ; PURECAP-ATOMICS-NEXT:    bnez a3, .LBB9_1
 ; PURECAP-ATOMICS-NEXT:  # %bb.2:
-; PURECAP-ATOMICS-NEXT:    cmove ca0, ca2
+; PURECAP-ATOMICS-NEXT:    cmove a0, a2
 ; PURECAP-ATOMICS-NEXT:    cret
 ;
 ; PURECAP-LIBCALLS-LABEL: atomic_cap_ptr_nand:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -48
-; PURECAP-LIBCALLS-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    cmove cs2, ca1
-; PURECAP-LIBCALLS-NEXT:    cmove cs1, ca0
-; PURECAP-LIBCALLS-NEXT:    clc ca1, 0(ca0)
-; PURECAP-LIBCALLS-NEXT:    cincoffset ca0, csp, 8
-; PURECAP-LIBCALLS-NEXT:    csetbounds cs0, ca0, 8
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -48
+; PURECAP-LIBCALLS-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    cmove s0, a1
+; PURECAP-LIBCALLS-NEXT:    cmove s1, a0
+; PURECAP-LIBCALLS-NEXT:    clc a1, 0(a0)
+; PURECAP-LIBCALLS-NEXT:    cincoffset a0, sp, 8
+; PURECAP-LIBCALLS-NEXT:    csetbounds s2, a0, 8
 ; PURECAP-LIBCALLS-NEXT:  .LBB9_1: # %atomicrmw.start
 ; PURECAP-LIBCALLS-NEXT:    # =>This Inner Loop Header: Depth=1
-; PURECAP-LIBCALLS-NEXT:    and a0, a1, s2
+; PURECAP-LIBCALLS-NEXT:    and a0, a1, s0
 ; PURECAP-LIBCALLS-NEXT:    not a0, a0
-; PURECAP-LIBCALLS-NEXT:    csetaddr ca2, ca1, a0
-; PURECAP-LIBCALLS-NEXT:    csc ca1, 8(csp)
+; PURECAP-LIBCALLS-NEXT:    csetaddr a2, a1, a0
+; PURECAP-LIBCALLS-NEXT:    csc a1, 8(sp)
 ; PURECAP-LIBCALLS-NEXT:    li a3, 5
 ; PURECAP-LIBCALLS-NEXT:    li a4, 5
-; PURECAP-LIBCALLS-NEXT:    cmove ca0, cs1
-; PURECAP-LIBCALLS-NEXT:    cmove ca1, cs0
+; PURECAP-LIBCALLS-NEXT:    cmove a0, s1
+; PURECAP-LIBCALLS-NEXT:    cmove a1, s2
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_compare_exchange_cap
-; PURECAP-LIBCALLS-NEXT:    clc ca1, 8(csp)
+; PURECAP-LIBCALLS-NEXT:    clc a1, 8(sp)
 ; PURECAP-LIBCALLS-NEXT:    beqz a0, .LBB9_1
 ; PURECAP-LIBCALLS-NEXT:  # %bb.2: # %atomicrmw.end
-; PURECAP-LIBCALLS-NEXT:    cmove ca0, ca1
-; PURECAP-LIBCALLS-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 48
+; PURECAP-LIBCALLS-NEXT:    cmove a0, a1
+; PURECAP-LIBCALLS-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 48
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: atomic_cap_ptr_nand:
 ; HYBRID:       # %bb.0:
 ; HYBRID-NEXT:    addi sp, sp, -32
 ; HYBRID-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
-; HYBRID-NEXT:    sc ca0, 8(sp) # 8-byte Folded Spill
-; HYBRID-NEXT:    lc.cap ca3, (ca0)
-; HYBRID-NEXT:    sc ca1, 0(sp) # 8-byte Folded Spill
+; HYBRID-NEXT:    sc a0, 8(sp) # 8-byte Folded Spill
+; HYBRID-NEXT:    lc.cap a3, (a0)
+; HYBRID-NEXT:    sc a1, 0(sp) # 8-byte Folded Spill
 ; HYBRID-NEXT:  .LBB9_1: # %atomicrmw.start
 ; HYBRID-NEXT:    # =>This Inner Loop Header: Depth=1
-; HYBRID-NEXT:    lc ca0, 0(sp) # 8-byte Folded Reload
+; HYBRID-NEXT:    lc a0, 0(sp) # 8-byte Folded Reload
 ; HYBRID-NEXT:    and a0, a3, a0
 ; HYBRID-NEXT:    not a0, a0
-; HYBRID-NEXT:    csetaddr ca2, ca3, a0
-; HYBRID-NEXT:    sc ca3, 16(sp)
+; HYBRID-NEXT:    csetaddr a2, a3, a0
+; HYBRID-NEXT:    sc a3, 16(sp)
 ; HYBRID-NEXT:    addi a1, sp, 16
 ; HYBRID-NEXT:    li a3, 5
 ; HYBRID-NEXT:    li a4, 5
-; HYBRID-NEXT:    lc ca0, 8(sp) # 8-byte Folded Reload
+; HYBRID-NEXT:    lc a0, 8(sp) # 8-byte Folded Reload
 ; HYBRID-NEXT:    call __atomic_compare_exchange_cap_c
-; HYBRID-NEXT:    lc ca3, 16(sp)
+; HYBRID-NEXT:    lc a3, 16(sp)
 ; HYBRID-NEXT:    beqz a0, .LBB9_1
 ; HYBRID-NEXT:  # %bb.2: # %atomicrmw.end
-; HYBRID-NEXT:    cmove ca0, ca3
+; HYBRID-NEXT:    cmove a0, a3
 ; HYBRID-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; HYBRID-NEXT:    addi sp, sp, 32
 ; HYBRID-NEXT:    ret
@@ -488,70 +488,70 @@ define i32 addrspace(200)* @atomic_cap_ptr_or(i32 addrspace(200)* addrspace(200)
 ; PURECAP-ATOMICS-LABEL: atomic_cap_ptr_or:
 ; PURECAP-ATOMICS:       # %bb.0:
 ; PURECAP-ATOMICS-NEXT:  .LBB10_1: # =>This Inner Loop Header: Depth=1
-; PURECAP-ATOMICS-NEXT:    clr.c.aqrl ca2, (ca0)
+; PURECAP-ATOMICS-NEXT:    clr.c.aqrl a2, (a0)
 ; PURECAP-ATOMICS-NEXT:    or a3, a2, a1
-; PURECAP-ATOMICS-NEXT:    csetaddr ca3, ca2, a3
-; PURECAP-ATOMICS-NEXT:    csc.c.aqrl a3, ca3, (ca0)
+; PURECAP-ATOMICS-NEXT:    csetaddr a3, a2, a3
+; PURECAP-ATOMICS-NEXT:    csc.c.aqrl a3, a3, (a0)
 ; PURECAP-ATOMICS-NEXT:    bnez a3, .LBB10_1
 ; PURECAP-ATOMICS-NEXT:  # %bb.2:
-; PURECAP-ATOMICS-NEXT:    cmove ca0, ca2
+; PURECAP-ATOMICS-NEXT:    cmove a0, a2
 ; PURECAP-ATOMICS-NEXT:    cret
 ;
 ; PURECAP-LIBCALLS-LABEL: atomic_cap_ptr_or:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -48
-; PURECAP-LIBCALLS-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    cmove cs2, ca1
-; PURECAP-LIBCALLS-NEXT:    cmove cs1, ca0
-; PURECAP-LIBCALLS-NEXT:    clc ca1, 0(ca0)
-; PURECAP-LIBCALLS-NEXT:    cincoffset ca0, csp, 8
-; PURECAP-LIBCALLS-NEXT:    csetbounds cs0, ca0, 8
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -48
+; PURECAP-LIBCALLS-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    cmove s0, a1
+; PURECAP-LIBCALLS-NEXT:    cmove s1, a0
+; PURECAP-LIBCALLS-NEXT:    clc a1, 0(a0)
+; PURECAP-LIBCALLS-NEXT:    cincoffset a0, sp, 8
+; PURECAP-LIBCALLS-NEXT:    csetbounds s2, a0, 8
 ; PURECAP-LIBCALLS-NEXT:  .LBB10_1: # %atomicrmw.start
 ; PURECAP-LIBCALLS-NEXT:    # =>This Inner Loop Header: Depth=1
-; PURECAP-LIBCALLS-NEXT:    or a0, a1, s2
-; PURECAP-LIBCALLS-NEXT:    csetaddr ca2, ca1, a0
-; PURECAP-LIBCALLS-NEXT:    csc ca1, 8(csp)
+; PURECAP-LIBCALLS-NEXT:    or a0, a1, s0
+; PURECAP-LIBCALLS-NEXT:    csetaddr a2, a1, a0
+; PURECAP-LIBCALLS-NEXT:    csc a1, 8(sp)
 ; PURECAP-LIBCALLS-NEXT:    li a3, 5
 ; PURECAP-LIBCALLS-NEXT:    li a4, 5
-; PURECAP-LIBCALLS-NEXT:    cmove ca0, cs1
-; PURECAP-LIBCALLS-NEXT:    cmove ca1, cs0
+; PURECAP-LIBCALLS-NEXT:    cmove a0, s1
+; PURECAP-LIBCALLS-NEXT:    cmove a1, s2
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_compare_exchange_cap
-; PURECAP-LIBCALLS-NEXT:    clc ca1, 8(csp)
+; PURECAP-LIBCALLS-NEXT:    clc a1, 8(sp)
 ; PURECAP-LIBCALLS-NEXT:    beqz a0, .LBB10_1
 ; PURECAP-LIBCALLS-NEXT:  # %bb.2: # %atomicrmw.end
-; PURECAP-LIBCALLS-NEXT:    cmove ca0, ca1
-; PURECAP-LIBCALLS-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 48
+; PURECAP-LIBCALLS-NEXT:    cmove a0, a1
+; PURECAP-LIBCALLS-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 48
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: atomic_cap_ptr_or:
 ; HYBRID:       # %bb.0:
 ; HYBRID-NEXT:    addi sp, sp, -32
 ; HYBRID-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
-; HYBRID-NEXT:    sc ca0, 8(sp) # 8-byte Folded Spill
-; HYBRID-NEXT:    lc.cap ca3, (ca0)
-; HYBRID-NEXT:    sc ca1, 0(sp) # 8-byte Folded Spill
+; HYBRID-NEXT:    sc a0, 8(sp) # 8-byte Folded Spill
+; HYBRID-NEXT:    lc.cap a3, (a0)
+; HYBRID-NEXT:    sc a1, 0(sp) # 8-byte Folded Spill
 ; HYBRID-NEXT:  .LBB10_1: # %atomicrmw.start
 ; HYBRID-NEXT:    # =>This Inner Loop Header: Depth=1
-; HYBRID-NEXT:    lc ca0, 0(sp) # 8-byte Folded Reload
+; HYBRID-NEXT:    lc a0, 0(sp) # 8-byte Folded Reload
 ; HYBRID-NEXT:    or a0, a3, a0
-; HYBRID-NEXT:    csetaddr ca2, ca3, a0
-; HYBRID-NEXT:    sc ca3, 16(sp)
+; HYBRID-NEXT:    csetaddr a2, a3, a0
+; HYBRID-NEXT:    sc a3, 16(sp)
 ; HYBRID-NEXT:    addi a1, sp, 16
 ; HYBRID-NEXT:    li a3, 5
 ; HYBRID-NEXT:    li a4, 5
-; HYBRID-NEXT:    lc ca0, 8(sp) # 8-byte Folded Reload
+; HYBRID-NEXT:    lc a0, 8(sp) # 8-byte Folded Reload
 ; HYBRID-NEXT:    call __atomic_compare_exchange_cap_c
-; HYBRID-NEXT:    lc ca3, 16(sp)
+; HYBRID-NEXT:    lc a3, 16(sp)
 ; HYBRID-NEXT:    beqz a0, .LBB10_1
 ; HYBRID-NEXT:  # %bb.2: # %atomicrmw.end
-; HYBRID-NEXT:    cmove ca0, ca3
+; HYBRID-NEXT:    cmove a0, a3
 ; HYBRID-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; HYBRID-NEXT:    addi sp, sp, 32
 ; HYBRID-NEXT:    ret
@@ -563,70 +563,70 @@ define i32 addrspace(200)* @atomic_cap_ptr_xor(i32 addrspace(200)* addrspace(200
 ; PURECAP-ATOMICS-LABEL: atomic_cap_ptr_xor:
 ; PURECAP-ATOMICS:       # %bb.0:
 ; PURECAP-ATOMICS-NEXT:  .LBB11_1: # =>This Inner Loop Header: Depth=1
-; PURECAP-ATOMICS-NEXT:    clr.c.aqrl ca2, (ca0)
+; PURECAP-ATOMICS-NEXT:    clr.c.aqrl a2, (a0)
 ; PURECAP-ATOMICS-NEXT:    xor a3, a2, a1
-; PURECAP-ATOMICS-NEXT:    csetaddr ca3, ca2, a3
-; PURECAP-ATOMICS-NEXT:    csc.c.aqrl a3, ca3, (ca0)
+; PURECAP-ATOMICS-NEXT:    csetaddr a3, a2, a3
+; PURECAP-ATOMICS-NEXT:    csc.c.aqrl a3, a3, (a0)
 ; PURECAP-ATOMICS-NEXT:    bnez a3, .LBB11_1
 ; PURECAP-ATOMICS-NEXT:  # %bb.2:
-; PURECAP-ATOMICS-NEXT:    cmove ca0, ca2
+; PURECAP-ATOMICS-NEXT:    cmove a0, a2
 ; PURECAP-ATOMICS-NEXT:    cret
 ;
 ; PURECAP-LIBCALLS-LABEL: atomic_cap_ptr_xor:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -48
-; PURECAP-LIBCALLS-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    cmove cs2, ca1
-; PURECAP-LIBCALLS-NEXT:    cmove cs1, ca0
-; PURECAP-LIBCALLS-NEXT:    clc ca1, 0(ca0)
-; PURECAP-LIBCALLS-NEXT:    cincoffset ca0, csp, 8
-; PURECAP-LIBCALLS-NEXT:    csetbounds cs0, ca0, 8
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -48
+; PURECAP-LIBCALLS-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    cmove s0, a1
+; PURECAP-LIBCALLS-NEXT:    cmove s1, a0
+; PURECAP-LIBCALLS-NEXT:    clc a1, 0(a0)
+; PURECAP-LIBCALLS-NEXT:    cincoffset a0, sp, 8
+; PURECAP-LIBCALLS-NEXT:    csetbounds s2, a0, 8
 ; PURECAP-LIBCALLS-NEXT:  .LBB11_1: # %atomicrmw.start
 ; PURECAP-LIBCALLS-NEXT:    # =>This Inner Loop Header: Depth=1
-; PURECAP-LIBCALLS-NEXT:    xor a0, a1, s2
-; PURECAP-LIBCALLS-NEXT:    csetaddr ca2, ca1, a0
-; PURECAP-LIBCALLS-NEXT:    csc ca1, 8(csp)
+; PURECAP-LIBCALLS-NEXT:    xor a0, a1, s0
+; PURECAP-LIBCALLS-NEXT:    csetaddr a2, a1, a0
+; PURECAP-LIBCALLS-NEXT:    csc a1, 8(sp)
 ; PURECAP-LIBCALLS-NEXT:    li a3, 5
 ; PURECAP-LIBCALLS-NEXT:    li a4, 5
-; PURECAP-LIBCALLS-NEXT:    cmove ca0, cs1
-; PURECAP-LIBCALLS-NEXT:    cmove ca1, cs0
+; PURECAP-LIBCALLS-NEXT:    cmove a0, s1
+; PURECAP-LIBCALLS-NEXT:    cmove a1, s2
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_compare_exchange_cap
-; PURECAP-LIBCALLS-NEXT:    clc ca1, 8(csp)
+; PURECAP-LIBCALLS-NEXT:    clc a1, 8(sp)
 ; PURECAP-LIBCALLS-NEXT:    beqz a0, .LBB11_1
 ; PURECAP-LIBCALLS-NEXT:  # %bb.2: # %atomicrmw.end
-; PURECAP-LIBCALLS-NEXT:    cmove ca0, ca1
-; PURECAP-LIBCALLS-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 48
+; PURECAP-LIBCALLS-NEXT:    cmove a0, a1
+; PURECAP-LIBCALLS-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 48
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: atomic_cap_ptr_xor:
 ; HYBRID:       # %bb.0:
 ; HYBRID-NEXT:    addi sp, sp, -32
 ; HYBRID-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
-; HYBRID-NEXT:    sc ca0, 8(sp) # 8-byte Folded Spill
-; HYBRID-NEXT:    lc.cap ca3, (ca0)
-; HYBRID-NEXT:    sc ca1, 0(sp) # 8-byte Folded Spill
+; HYBRID-NEXT:    sc a0, 8(sp) # 8-byte Folded Spill
+; HYBRID-NEXT:    lc.cap a3, (a0)
+; HYBRID-NEXT:    sc a1, 0(sp) # 8-byte Folded Spill
 ; HYBRID-NEXT:  .LBB11_1: # %atomicrmw.start
 ; HYBRID-NEXT:    # =>This Inner Loop Header: Depth=1
-; HYBRID-NEXT:    lc ca0, 0(sp) # 8-byte Folded Reload
+; HYBRID-NEXT:    lc a0, 0(sp) # 8-byte Folded Reload
 ; HYBRID-NEXT:    xor a0, a3, a0
-; HYBRID-NEXT:    csetaddr ca2, ca3, a0
-; HYBRID-NEXT:    sc ca3, 16(sp)
+; HYBRID-NEXT:    csetaddr a2, a3, a0
+; HYBRID-NEXT:    sc a3, 16(sp)
 ; HYBRID-NEXT:    addi a1, sp, 16
 ; HYBRID-NEXT:    li a3, 5
 ; HYBRID-NEXT:    li a4, 5
-; HYBRID-NEXT:    lc ca0, 8(sp) # 8-byte Folded Reload
+; HYBRID-NEXT:    lc a0, 8(sp) # 8-byte Folded Reload
 ; HYBRID-NEXT:    call __atomic_compare_exchange_cap_c
-; HYBRID-NEXT:    lc ca3, 16(sp)
+; HYBRID-NEXT:    lc a3, 16(sp)
 ; HYBRID-NEXT:    beqz a0, .LBB11_1
 ; HYBRID-NEXT:  # %bb.2: # %atomicrmw.end
-; HYBRID-NEXT:    cmove ca0, ca3
+; HYBRID-NEXT:    cmove a0, a3
 ; HYBRID-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; HYBRID-NEXT:    addi sp, sp, 32
 ; HYBRID-NEXT:    ret
@@ -638,87 +638,87 @@ define i32 addrspace(200)* @atomic_cap_ptr_max(i32 addrspace(200)* addrspace(200
 ; PURECAP-ATOMICS-LABEL: atomic_cap_ptr_max:
 ; PURECAP-ATOMICS:       # %bb.0:
 ; PURECAP-ATOMICS-NEXT:  .LBB12_1: # =>This Inner Loop Header: Depth=1
-; PURECAP-ATOMICS-NEXT:    clr.c.aqrl ca2, (ca0)
-; PURECAP-ATOMICS-NEXT:    cmove ca3, ca2
+; PURECAP-ATOMICS-NEXT:    clr.c.aqrl a2, (a0)
+; PURECAP-ATOMICS-NEXT:    cmove a3, a2
 ; PURECAP-ATOMICS-NEXT:    bge a3, a1, .LBB12_3
 ; PURECAP-ATOMICS-NEXT:  # %bb.2: # in Loop: Header=BB12_1 Depth=1
-; PURECAP-ATOMICS-NEXT:    cmove ca3, ca2
+; PURECAP-ATOMICS-NEXT:    cmove a3, a2
 ; PURECAP-ATOMICS-NEXT:  .LBB12_3: # in Loop: Header=BB12_1 Depth=1
-; PURECAP-ATOMICS-NEXT:    csc.c.aqrl a3, ca3, (ca0)
+; PURECAP-ATOMICS-NEXT:    csc.c.aqrl a3, a3, (a0)
 ; PURECAP-ATOMICS-NEXT:    bnez a3, .LBB12_1
 ; PURECAP-ATOMICS-NEXT:  # %bb.4:
-; PURECAP-ATOMICS-NEXT:    cmove ca0, ca2
+; PURECAP-ATOMICS-NEXT:    cmove a0, a2
 ; PURECAP-ATOMICS-NEXT:    cret
 ;
 ; PURECAP-LIBCALLS-LABEL: atomic_cap_ptr_max:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -48
-; PURECAP-LIBCALLS-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    cmove cs0, ca1
-; PURECAP-LIBCALLS-NEXT:    cmove cs2, ca0
-; PURECAP-LIBCALLS-NEXT:    clc ca1, 0(ca0)
-; PURECAP-LIBCALLS-NEXT:    cincoffset ca0, csp, 8
-; PURECAP-LIBCALLS-NEXT:    csetbounds cs1, ca0, 8
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -48
+; PURECAP-LIBCALLS-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    cmove s0, a1
+; PURECAP-LIBCALLS-NEXT:    cmove s1, a0
+; PURECAP-LIBCALLS-NEXT:    clc a1, 0(a0)
+; PURECAP-LIBCALLS-NEXT:    cincoffset a0, sp, 8
+; PURECAP-LIBCALLS-NEXT:    csetbounds s2, a0, 8
 ; PURECAP-LIBCALLS-NEXT:    j .LBB12_2
 ; PURECAP-LIBCALLS-NEXT:  .LBB12_1: # %atomicrmw.start
 ; PURECAP-LIBCALLS-NEXT:    # in Loop: Header=BB12_2 Depth=1
-; PURECAP-LIBCALLS-NEXT:    csc ca1, 8(csp)
+; PURECAP-LIBCALLS-NEXT:    csc a1, 8(sp)
 ; PURECAP-LIBCALLS-NEXT:    li a3, 5
 ; PURECAP-LIBCALLS-NEXT:    li a4, 5
-; PURECAP-LIBCALLS-NEXT:    cmove ca0, cs2
-; PURECAP-LIBCALLS-NEXT:    cmove ca1, cs1
+; PURECAP-LIBCALLS-NEXT:    cmove a0, s1
+; PURECAP-LIBCALLS-NEXT:    cmove a1, s2
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_compare_exchange_cap
-; PURECAP-LIBCALLS-NEXT:    clc ca1, 8(csp)
+; PURECAP-LIBCALLS-NEXT:    clc a1, 8(sp)
 ; PURECAP-LIBCALLS-NEXT:    bnez a0, .LBB12_4
 ; PURECAP-LIBCALLS-NEXT:  .LBB12_2: # %atomicrmw.start
 ; PURECAP-LIBCALLS-NEXT:    # =>This Inner Loop Header: Depth=1
-; PURECAP-LIBCALLS-NEXT:    cmove ca2, ca1
+; PURECAP-LIBCALLS-NEXT:    cmove a2, a1
 ; PURECAP-LIBCALLS-NEXT:    blt s0, a1, .LBB12_1
 ; PURECAP-LIBCALLS-NEXT:  # %bb.3: # %atomicrmw.start
 ; PURECAP-LIBCALLS-NEXT:    # in Loop: Header=BB12_2 Depth=1
-; PURECAP-LIBCALLS-NEXT:    cmove ca2, cs0
+; PURECAP-LIBCALLS-NEXT:    cmove a2, s0
 ; PURECAP-LIBCALLS-NEXT:    j .LBB12_1
 ; PURECAP-LIBCALLS-NEXT:  .LBB12_4: # %atomicrmw.end
-; PURECAP-LIBCALLS-NEXT:    cmove ca0, ca1
-; PURECAP-LIBCALLS-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 48
+; PURECAP-LIBCALLS-NEXT:    cmove a0, a1
+; PURECAP-LIBCALLS-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 48
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: atomic_cap_ptr_max:
 ; HYBRID:       # %bb.0:
 ; HYBRID-NEXT:    addi sp, sp, -32
 ; HYBRID-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
-; HYBRID-NEXT:    sc ca0, 0(sp) # 8-byte Folded Spill
-; HYBRID-NEXT:    lc.cap ca3, (ca0)
-; HYBRID-NEXT:    sc ca1, 8(sp) # 8-byte Folded Spill
+; HYBRID-NEXT:    sc a0, 0(sp) # 8-byte Folded Spill
+; HYBRID-NEXT:    lc.cap a3, (a0)
+; HYBRID-NEXT:    sc a1, 8(sp) # 8-byte Folded Spill
 ; HYBRID-NEXT:    j .LBB12_2
 ; HYBRID-NEXT:  .LBB12_1: # %atomicrmw.start
 ; HYBRID-NEXT:    # in Loop: Header=BB12_2 Depth=1
-; HYBRID-NEXT:    sc ca3, 16(sp)
+; HYBRID-NEXT:    sc a3, 16(sp)
 ; HYBRID-NEXT:    addi a1, sp, 16
 ; HYBRID-NEXT:    li a3, 5
 ; HYBRID-NEXT:    li a4, 5
-; HYBRID-NEXT:    lc ca0, 0(sp) # 8-byte Folded Reload
+; HYBRID-NEXT:    lc a0, 0(sp) # 8-byte Folded Reload
 ; HYBRID-NEXT:    call __atomic_compare_exchange_cap_c
-; HYBRID-NEXT:    lc ca3, 16(sp)
+; HYBRID-NEXT:    lc a3, 16(sp)
 ; HYBRID-NEXT:    bnez a0, .LBB12_4
 ; HYBRID-NEXT:  .LBB12_2: # %atomicrmw.start
 ; HYBRID-NEXT:    # =>This Inner Loop Header: Depth=1
-; HYBRID-NEXT:    cmove ca2, ca3
-; HYBRID-NEXT:    lc ca0, 8(sp) # 8-byte Folded Reload
+; HYBRID-NEXT:    cmove a2, a3
+; HYBRID-NEXT:    lc a0, 8(sp) # 8-byte Folded Reload
 ; HYBRID-NEXT:    blt a0, a3, .LBB12_1
 ; HYBRID-NEXT:  # %bb.3: # %atomicrmw.start
 ; HYBRID-NEXT:    # in Loop: Header=BB12_2 Depth=1
-; HYBRID-NEXT:    lc ca2, 8(sp) # 8-byte Folded Reload
+; HYBRID-NEXT:    lc a2, 8(sp) # 8-byte Folded Reload
 ; HYBRID-NEXT:    j .LBB12_1
 ; HYBRID-NEXT:  .LBB12_4: # %atomicrmw.end
-; HYBRID-NEXT:    cmove ca0, ca3
+; HYBRID-NEXT:    cmove a0, a3
 ; HYBRID-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; HYBRID-NEXT:    addi sp, sp, 32
 ; HYBRID-NEXT:    ret
@@ -730,87 +730,87 @@ define i32 addrspace(200)* @atomic_cap_ptr_min(i32 addrspace(200)* addrspace(200
 ; PURECAP-ATOMICS-LABEL: atomic_cap_ptr_min:
 ; PURECAP-ATOMICS:       # %bb.0:
 ; PURECAP-ATOMICS-NEXT:  .LBB13_1: # =>This Inner Loop Header: Depth=1
-; PURECAP-ATOMICS-NEXT:    clr.c.aqrl ca2, (ca0)
-; PURECAP-ATOMICS-NEXT:    cmove ca3, ca2
+; PURECAP-ATOMICS-NEXT:    clr.c.aqrl a2, (a0)
+; PURECAP-ATOMICS-NEXT:    cmove a3, a2
 ; PURECAP-ATOMICS-NEXT:    bge a1, a3, .LBB13_3
 ; PURECAP-ATOMICS-NEXT:  # %bb.2: # in Loop: Header=BB13_1 Depth=1
-; PURECAP-ATOMICS-NEXT:    cmove ca3, ca2
+; PURECAP-ATOMICS-NEXT:    cmove a3, a2
 ; PURECAP-ATOMICS-NEXT:  .LBB13_3: # in Loop: Header=BB13_1 Depth=1
-; PURECAP-ATOMICS-NEXT:    csc.c.aqrl a3, ca3, (ca0)
+; PURECAP-ATOMICS-NEXT:    csc.c.aqrl a3, a3, (a0)
 ; PURECAP-ATOMICS-NEXT:    bnez a3, .LBB13_1
 ; PURECAP-ATOMICS-NEXT:  # %bb.4:
-; PURECAP-ATOMICS-NEXT:    cmove ca0, ca2
+; PURECAP-ATOMICS-NEXT:    cmove a0, a2
 ; PURECAP-ATOMICS-NEXT:    cret
 ;
 ; PURECAP-LIBCALLS-LABEL: atomic_cap_ptr_min:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -48
-; PURECAP-LIBCALLS-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    cmove cs0, ca1
-; PURECAP-LIBCALLS-NEXT:    cmove cs2, ca0
-; PURECAP-LIBCALLS-NEXT:    clc ca1, 0(ca0)
-; PURECAP-LIBCALLS-NEXT:    cincoffset ca0, csp, 8
-; PURECAP-LIBCALLS-NEXT:    csetbounds cs1, ca0, 8
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -48
+; PURECAP-LIBCALLS-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    cmove s0, a1
+; PURECAP-LIBCALLS-NEXT:    cmove s1, a0
+; PURECAP-LIBCALLS-NEXT:    clc a1, 0(a0)
+; PURECAP-LIBCALLS-NEXT:    cincoffset a0, sp, 8
+; PURECAP-LIBCALLS-NEXT:    csetbounds s2, a0, 8
 ; PURECAP-LIBCALLS-NEXT:    j .LBB13_2
 ; PURECAP-LIBCALLS-NEXT:  .LBB13_1: # %atomicrmw.start
 ; PURECAP-LIBCALLS-NEXT:    # in Loop: Header=BB13_2 Depth=1
-; PURECAP-LIBCALLS-NEXT:    csc ca1, 8(csp)
+; PURECAP-LIBCALLS-NEXT:    csc a1, 8(sp)
 ; PURECAP-LIBCALLS-NEXT:    li a3, 5
 ; PURECAP-LIBCALLS-NEXT:    li a4, 5
-; PURECAP-LIBCALLS-NEXT:    cmove ca0, cs2
-; PURECAP-LIBCALLS-NEXT:    cmove ca1, cs1
+; PURECAP-LIBCALLS-NEXT:    cmove a0, s1
+; PURECAP-LIBCALLS-NEXT:    cmove a1, s2
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_compare_exchange_cap
-; PURECAP-LIBCALLS-NEXT:    clc ca1, 8(csp)
+; PURECAP-LIBCALLS-NEXT:    clc a1, 8(sp)
 ; PURECAP-LIBCALLS-NEXT:    bnez a0, .LBB13_4
 ; PURECAP-LIBCALLS-NEXT:  .LBB13_2: # %atomicrmw.start
 ; PURECAP-LIBCALLS-NEXT:    # =>This Inner Loop Header: Depth=1
-; PURECAP-LIBCALLS-NEXT:    cmove ca2, ca1
+; PURECAP-LIBCALLS-NEXT:    cmove a2, a1
 ; PURECAP-LIBCALLS-NEXT:    bge s0, a1, .LBB13_1
 ; PURECAP-LIBCALLS-NEXT:  # %bb.3: # %atomicrmw.start
 ; PURECAP-LIBCALLS-NEXT:    # in Loop: Header=BB13_2 Depth=1
-; PURECAP-LIBCALLS-NEXT:    cmove ca2, cs0
+; PURECAP-LIBCALLS-NEXT:    cmove a2, s0
 ; PURECAP-LIBCALLS-NEXT:    j .LBB13_1
 ; PURECAP-LIBCALLS-NEXT:  .LBB13_4: # %atomicrmw.end
-; PURECAP-LIBCALLS-NEXT:    cmove ca0, ca1
-; PURECAP-LIBCALLS-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 48
+; PURECAP-LIBCALLS-NEXT:    cmove a0, a1
+; PURECAP-LIBCALLS-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 48
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: atomic_cap_ptr_min:
 ; HYBRID:       # %bb.0:
 ; HYBRID-NEXT:    addi sp, sp, -32
 ; HYBRID-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
-; HYBRID-NEXT:    sc ca0, 0(sp) # 8-byte Folded Spill
-; HYBRID-NEXT:    lc.cap ca3, (ca0)
-; HYBRID-NEXT:    sc ca1, 8(sp) # 8-byte Folded Spill
+; HYBRID-NEXT:    sc a0, 0(sp) # 8-byte Folded Spill
+; HYBRID-NEXT:    lc.cap a3, (a0)
+; HYBRID-NEXT:    sc a1, 8(sp) # 8-byte Folded Spill
 ; HYBRID-NEXT:    j .LBB13_2
 ; HYBRID-NEXT:  .LBB13_1: # %atomicrmw.start
 ; HYBRID-NEXT:    # in Loop: Header=BB13_2 Depth=1
-; HYBRID-NEXT:    sc ca3, 16(sp)
+; HYBRID-NEXT:    sc a3, 16(sp)
 ; HYBRID-NEXT:    addi a1, sp, 16
 ; HYBRID-NEXT:    li a3, 5
 ; HYBRID-NEXT:    li a4, 5
-; HYBRID-NEXT:    lc ca0, 0(sp) # 8-byte Folded Reload
+; HYBRID-NEXT:    lc a0, 0(sp) # 8-byte Folded Reload
 ; HYBRID-NEXT:    call __atomic_compare_exchange_cap_c
-; HYBRID-NEXT:    lc ca3, 16(sp)
+; HYBRID-NEXT:    lc a3, 16(sp)
 ; HYBRID-NEXT:    bnez a0, .LBB13_4
 ; HYBRID-NEXT:  .LBB13_2: # %atomicrmw.start
 ; HYBRID-NEXT:    # =>This Inner Loop Header: Depth=1
-; HYBRID-NEXT:    cmove ca2, ca3
-; HYBRID-NEXT:    lc ca0, 8(sp) # 8-byte Folded Reload
+; HYBRID-NEXT:    cmove a2, a3
+; HYBRID-NEXT:    lc a0, 8(sp) # 8-byte Folded Reload
 ; HYBRID-NEXT:    bge a0, a3, .LBB13_1
 ; HYBRID-NEXT:  # %bb.3: # %atomicrmw.start
 ; HYBRID-NEXT:    # in Loop: Header=BB13_2 Depth=1
-; HYBRID-NEXT:    lc ca2, 8(sp) # 8-byte Folded Reload
+; HYBRID-NEXT:    lc a2, 8(sp) # 8-byte Folded Reload
 ; HYBRID-NEXT:    j .LBB13_1
 ; HYBRID-NEXT:  .LBB13_4: # %atomicrmw.end
-; HYBRID-NEXT:    cmove ca0, ca3
+; HYBRID-NEXT:    cmove a0, a3
 ; HYBRID-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; HYBRID-NEXT:    addi sp, sp, 32
 ; HYBRID-NEXT:    ret
@@ -822,87 +822,87 @@ define i32 addrspace(200)* @atomic_cap_ptr_umax(i32 addrspace(200)* addrspace(20
 ; PURECAP-ATOMICS-LABEL: atomic_cap_ptr_umax:
 ; PURECAP-ATOMICS:       # %bb.0:
 ; PURECAP-ATOMICS-NEXT:  .LBB14_1: # =>This Inner Loop Header: Depth=1
-; PURECAP-ATOMICS-NEXT:    clr.c.aqrl ca2, (ca0)
-; PURECAP-ATOMICS-NEXT:    cmove ca3, ca2
+; PURECAP-ATOMICS-NEXT:    clr.c.aqrl a2, (a0)
+; PURECAP-ATOMICS-NEXT:    cmove a3, a2
 ; PURECAP-ATOMICS-NEXT:    bgeu a3, a1, .LBB14_3
 ; PURECAP-ATOMICS-NEXT:  # %bb.2: # in Loop: Header=BB14_1 Depth=1
-; PURECAP-ATOMICS-NEXT:    cmove ca3, ca2
+; PURECAP-ATOMICS-NEXT:    cmove a3, a2
 ; PURECAP-ATOMICS-NEXT:  .LBB14_3: # in Loop: Header=BB14_1 Depth=1
-; PURECAP-ATOMICS-NEXT:    csc.c.aqrl a3, ca3, (ca0)
+; PURECAP-ATOMICS-NEXT:    csc.c.aqrl a3, a3, (a0)
 ; PURECAP-ATOMICS-NEXT:    bnez a3, .LBB14_1
 ; PURECAP-ATOMICS-NEXT:  # %bb.4:
-; PURECAP-ATOMICS-NEXT:    cmove ca0, ca2
+; PURECAP-ATOMICS-NEXT:    cmove a0, a2
 ; PURECAP-ATOMICS-NEXT:    cret
 ;
 ; PURECAP-LIBCALLS-LABEL: atomic_cap_ptr_umax:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -48
-; PURECAP-LIBCALLS-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    cmove cs0, ca1
-; PURECAP-LIBCALLS-NEXT:    cmove cs2, ca0
-; PURECAP-LIBCALLS-NEXT:    clc ca1, 0(ca0)
-; PURECAP-LIBCALLS-NEXT:    cincoffset ca0, csp, 8
-; PURECAP-LIBCALLS-NEXT:    csetbounds cs1, ca0, 8
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -48
+; PURECAP-LIBCALLS-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    cmove s0, a1
+; PURECAP-LIBCALLS-NEXT:    cmove s1, a0
+; PURECAP-LIBCALLS-NEXT:    clc a1, 0(a0)
+; PURECAP-LIBCALLS-NEXT:    cincoffset a0, sp, 8
+; PURECAP-LIBCALLS-NEXT:    csetbounds s2, a0, 8
 ; PURECAP-LIBCALLS-NEXT:    j .LBB14_2
 ; PURECAP-LIBCALLS-NEXT:  .LBB14_1: # %atomicrmw.start
 ; PURECAP-LIBCALLS-NEXT:    # in Loop: Header=BB14_2 Depth=1
-; PURECAP-LIBCALLS-NEXT:    csc ca1, 8(csp)
+; PURECAP-LIBCALLS-NEXT:    csc a1, 8(sp)
 ; PURECAP-LIBCALLS-NEXT:    li a3, 5
 ; PURECAP-LIBCALLS-NEXT:    li a4, 5
-; PURECAP-LIBCALLS-NEXT:    cmove ca0, cs2
-; PURECAP-LIBCALLS-NEXT:    cmove ca1, cs1
+; PURECAP-LIBCALLS-NEXT:    cmove a0, s1
+; PURECAP-LIBCALLS-NEXT:    cmove a1, s2
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_compare_exchange_cap
-; PURECAP-LIBCALLS-NEXT:    clc ca1, 8(csp)
+; PURECAP-LIBCALLS-NEXT:    clc a1, 8(sp)
 ; PURECAP-LIBCALLS-NEXT:    bnez a0, .LBB14_4
 ; PURECAP-LIBCALLS-NEXT:  .LBB14_2: # %atomicrmw.start
 ; PURECAP-LIBCALLS-NEXT:    # =>This Inner Loop Header: Depth=1
-; PURECAP-LIBCALLS-NEXT:    cmove ca2, ca1
+; PURECAP-LIBCALLS-NEXT:    cmove a2, a1
 ; PURECAP-LIBCALLS-NEXT:    bltu s0, a1, .LBB14_1
 ; PURECAP-LIBCALLS-NEXT:  # %bb.3: # %atomicrmw.start
 ; PURECAP-LIBCALLS-NEXT:    # in Loop: Header=BB14_2 Depth=1
-; PURECAP-LIBCALLS-NEXT:    cmove ca2, cs0
+; PURECAP-LIBCALLS-NEXT:    cmove a2, s0
 ; PURECAP-LIBCALLS-NEXT:    j .LBB14_1
 ; PURECAP-LIBCALLS-NEXT:  .LBB14_4: # %atomicrmw.end
-; PURECAP-LIBCALLS-NEXT:    cmove ca0, ca1
-; PURECAP-LIBCALLS-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 48
+; PURECAP-LIBCALLS-NEXT:    cmove a0, a1
+; PURECAP-LIBCALLS-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 48
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: atomic_cap_ptr_umax:
 ; HYBRID:       # %bb.0:
 ; HYBRID-NEXT:    addi sp, sp, -32
 ; HYBRID-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
-; HYBRID-NEXT:    sc ca0, 0(sp) # 8-byte Folded Spill
-; HYBRID-NEXT:    lc.cap ca3, (ca0)
-; HYBRID-NEXT:    sc ca1, 8(sp) # 8-byte Folded Spill
+; HYBRID-NEXT:    sc a0, 0(sp) # 8-byte Folded Spill
+; HYBRID-NEXT:    lc.cap a3, (a0)
+; HYBRID-NEXT:    sc a1, 8(sp) # 8-byte Folded Spill
 ; HYBRID-NEXT:    j .LBB14_2
 ; HYBRID-NEXT:  .LBB14_1: # %atomicrmw.start
 ; HYBRID-NEXT:    # in Loop: Header=BB14_2 Depth=1
-; HYBRID-NEXT:    sc ca3, 16(sp)
+; HYBRID-NEXT:    sc a3, 16(sp)
 ; HYBRID-NEXT:    addi a1, sp, 16
 ; HYBRID-NEXT:    li a3, 5
 ; HYBRID-NEXT:    li a4, 5
-; HYBRID-NEXT:    lc ca0, 0(sp) # 8-byte Folded Reload
+; HYBRID-NEXT:    lc a0, 0(sp) # 8-byte Folded Reload
 ; HYBRID-NEXT:    call __atomic_compare_exchange_cap_c
-; HYBRID-NEXT:    lc ca3, 16(sp)
+; HYBRID-NEXT:    lc a3, 16(sp)
 ; HYBRID-NEXT:    bnez a0, .LBB14_4
 ; HYBRID-NEXT:  .LBB14_2: # %atomicrmw.start
 ; HYBRID-NEXT:    # =>This Inner Loop Header: Depth=1
-; HYBRID-NEXT:    cmove ca2, ca3
-; HYBRID-NEXT:    lc ca0, 8(sp) # 8-byte Folded Reload
+; HYBRID-NEXT:    cmove a2, a3
+; HYBRID-NEXT:    lc a0, 8(sp) # 8-byte Folded Reload
 ; HYBRID-NEXT:    bltu a0, a3, .LBB14_1
 ; HYBRID-NEXT:  # %bb.3: # %atomicrmw.start
 ; HYBRID-NEXT:    # in Loop: Header=BB14_2 Depth=1
-; HYBRID-NEXT:    lc ca2, 8(sp) # 8-byte Folded Reload
+; HYBRID-NEXT:    lc a2, 8(sp) # 8-byte Folded Reload
 ; HYBRID-NEXT:    j .LBB14_1
 ; HYBRID-NEXT:  .LBB14_4: # %atomicrmw.end
-; HYBRID-NEXT:    cmove ca0, ca3
+; HYBRID-NEXT:    cmove a0, a3
 ; HYBRID-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; HYBRID-NEXT:    addi sp, sp, 32
 ; HYBRID-NEXT:    ret
@@ -914,87 +914,87 @@ define i32 addrspace(200)* @atomic_cap_ptr_umin(i32 addrspace(200)* addrspace(20
 ; PURECAP-ATOMICS-LABEL: atomic_cap_ptr_umin:
 ; PURECAP-ATOMICS:       # %bb.0:
 ; PURECAP-ATOMICS-NEXT:  .LBB15_1: # =>This Inner Loop Header: Depth=1
-; PURECAP-ATOMICS-NEXT:    clr.c.aqrl ca2, (ca0)
-; PURECAP-ATOMICS-NEXT:    cmove ca3, ca2
+; PURECAP-ATOMICS-NEXT:    clr.c.aqrl a2, (a0)
+; PURECAP-ATOMICS-NEXT:    cmove a3, a2
 ; PURECAP-ATOMICS-NEXT:    bgeu a1, a3, .LBB15_3
 ; PURECAP-ATOMICS-NEXT:  # %bb.2: # in Loop: Header=BB15_1 Depth=1
-; PURECAP-ATOMICS-NEXT:    cmove ca3, ca2
+; PURECAP-ATOMICS-NEXT:    cmove a3, a2
 ; PURECAP-ATOMICS-NEXT:  .LBB15_3: # in Loop: Header=BB15_1 Depth=1
-; PURECAP-ATOMICS-NEXT:    csc.c.aqrl a3, ca3, (ca0)
+; PURECAP-ATOMICS-NEXT:    csc.c.aqrl a3, a3, (a0)
 ; PURECAP-ATOMICS-NEXT:    bnez a3, .LBB15_1
 ; PURECAP-ATOMICS-NEXT:  # %bb.4:
-; PURECAP-ATOMICS-NEXT:    cmove ca0, ca2
+; PURECAP-ATOMICS-NEXT:    cmove a0, a2
 ; PURECAP-ATOMICS-NEXT:    cret
 ;
 ; PURECAP-LIBCALLS-LABEL: atomic_cap_ptr_umin:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -48
-; PURECAP-LIBCALLS-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    cmove cs0, ca1
-; PURECAP-LIBCALLS-NEXT:    cmove cs2, ca0
-; PURECAP-LIBCALLS-NEXT:    clc ca1, 0(ca0)
-; PURECAP-LIBCALLS-NEXT:    cincoffset ca0, csp, 8
-; PURECAP-LIBCALLS-NEXT:    csetbounds cs1, ca0, 8
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -48
+; PURECAP-LIBCALLS-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    cmove s0, a1
+; PURECAP-LIBCALLS-NEXT:    cmove s1, a0
+; PURECAP-LIBCALLS-NEXT:    clc a1, 0(a0)
+; PURECAP-LIBCALLS-NEXT:    cincoffset a0, sp, 8
+; PURECAP-LIBCALLS-NEXT:    csetbounds s2, a0, 8
 ; PURECAP-LIBCALLS-NEXT:    j .LBB15_2
 ; PURECAP-LIBCALLS-NEXT:  .LBB15_1: # %atomicrmw.start
 ; PURECAP-LIBCALLS-NEXT:    # in Loop: Header=BB15_2 Depth=1
-; PURECAP-LIBCALLS-NEXT:    csc ca1, 8(csp)
+; PURECAP-LIBCALLS-NEXT:    csc a1, 8(sp)
 ; PURECAP-LIBCALLS-NEXT:    li a3, 5
 ; PURECAP-LIBCALLS-NEXT:    li a4, 5
-; PURECAP-LIBCALLS-NEXT:    cmove ca0, cs2
-; PURECAP-LIBCALLS-NEXT:    cmove ca1, cs1
+; PURECAP-LIBCALLS-NEXT:    cmove a0, s1
+; PURECAP-LIBCALLS-NEXT:    cmove a1, s2
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_compare_exchange_cap
-; PURECAP-LIBCALLS-NEXT:    clc ca1, 8(csp)
+; PURECAP-LIBCALLS-NEXT:    clc a1, 8(sp)
 ; PURECAP-LIBCALLS-NEXT:    bnez a0, .LBB15_4
 ; PURECAP-LIBCALLS-NEXT:  .LBB15_2: # %atomicrmw.start
 ; PURECAP-LIBCALLS-NEXT:    # =>This Inner Loop Header: Depth=1
-; PURECAP-LIBCALLS-NEXT:    cmove ca2, ca1
+; PURECAP-LIBCALLS-NEXT:    cmove a2, a1
 ; PURECAP-LIBCALLS-NEXT:    bgeu s0, a1, .LBB15_1
 ; PURECAP-LIBCALLS-NEXT:  # %bb.3: # %atomicrmw.start
 ; PURECAP-LIBCALLS-NEXT:    # in Loop: Header=BB15_2 Depth=1
-; PURECAP-LIBCALLS-NEXT:    cmove ca2, cs0
+; PURECAP-LIBCALLS-NEXT:    cmove a2, s0
 ; PURECAP-LIBCALLS-NEXT:    j .LBB15_1
 ; PURECAP-LIBCALLS-NEXT:  .LBB15_4: # %atomicrmw.end
-; PURECAP-LIBCALLS-NEXT:    cmove ca0, ca1
-; PURECAP-LIBCALLS-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 48
+; PURECAP-LIBCALLS-NEXT:    cmove a0, a1
+; PURECAP-LIBCALLS-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 48
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: atomic_cap_ptr_umin:
 ; HYBRID:       # %bb.0:
 ; HYBRID-NEXT:    addi sp, sp, -32
 ; HYBRID-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
-; HYBRID-NEXT:    sc ca0, 0(sp) # 8-byte Folded Spill
-; HYBRID-NEXT:    lc.cap ca3, (ca0)
-; HYBRID-NEXT:    sc ca1, 8(sp) # 8-byte Folded Spill
+; HYBRID-NEXT:    sc a0, 0(sp) # 8-byte Folded Spill
+; HYBRID-NEXT:    lc.cap a3, (a0)
+; HYBRID-NEXT:    sc a1, 8(sp) # 8-byte Folded Spill
 ; HYBRID-NEXT:    j .LBB15_2
 ; HYBRID-NEXT:  .LBB15_1: # %atomicrmw.start
 ; HYBRID-NEXT:    # in Loop: Header=BB15_2 Depth=1
-; HYBRID-NEXT:    sc ca3, 16(sp)
+; HYBRID-NEXT:    sc a3, 16(sp)
 ; HYBRID-NEXT:    addi a1, sp, 16
 ; HYBRID-NEXT:    li a3, 5
 ; HYBRID-NEXT:    li a4, 5
-; HYBRID-NEXT:    lc ca0, 0(sp) # 8-byte Folded Reload
+; HYBRID-NEXT:    lc a0, 0(sp) # 8-byte Folded Reload
 ; HYBRID-NEXT:    call __atomic_compare_exchange_cap_c
-; HYBRID-NEXT:    lc ca3, 16(sp)
+; HYBRID-NEXT:    lc a3, 16(sp)
 ; HYBRID-NEXT:    bnez a0, .LBB15_4
 ; HYBRID-NEXT:  .LBB15_2: # %atomicrmw.start
 ; HYBRID-NEXT:    # =>This Inner Loop Header: Depth=1
-; HYBRID-NEXT:    cmove ca2, ca3
-; HYBRID-NEXT:    lc ca0, 8(sp) # 8-byte Folded Reload
+; HYBRID-NEXT:    cmove a2, a3
+; HYBRID-NEXT:    lc a0, 8(sp) # 8-byte Folded Reload
 ; HYBRID-NEXT:    bgeu a0, a3, .LBB15_1
 ; HYBRID-NEXT:  # %bb.3: # %atomicrmw.start
 ; HYBRID-NEXT:    # in Loop: Header=BB15_2 Depth=1
-; HYBRID-NEXT:    lc ca2, 8(sp) # 8-byte Folded Reload
+; HYBRID-NEXT:    lc a2, 8(sp) # 8-byte Folded Reload
 ; HYBRID-NEXT:    j .LBB15_1
 ; HYBRID-NEXT:  .LBB15_4: # %atomicrmw.end
-; HYBRID-NEXT:    cmove ca0, ca3
+; HYBRID-NEXT:    cmove a0, a3
 ; HYBRID-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; HYBRID-NEXT:    addi sp, sp, 32
 ; HYBRID-NEXT:    ret
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/atomic-rmw-cap-ptr.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/atomic-rmw-cap-ptr.ll
index ae4bcd583c295..26dc20208a177 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/atomic-rmw-cap-ptr.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/atomic-rmw-cap-ptr.ll
@@ -10,17 +10,17 @@
 define i32 @atomic_cap_ptr_xchg(i32 addrspace(200)* %ptr, i32 %val) nounwind {
 ; PURECAP-ATOMICS-LABEL: atomic_cap_ptr_xchg:
 ; PURECAP-ATOMICS:       # %bb.0:
-; PURECAP-ATOMICS-NEXT:    camoswap.w.aqrl a0, a1, (ca0)
+; PURECAP-ATOMICS-NEXT:    camoswap.w.aqrl a0, a1, (a0)
 ; PURECAP-ATOMICS-NEXT:    cret
 ;
 ; PURECAP-LIBCALLS-LABEL: atomic_cap_ptr_xchg:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -16
-; PURECAP-LIBCALLS-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -16
+; PURECAP-LIBCALLS-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; PURECAP-LIBCALLS-NEXT:    li a2, 5
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_exchange_4
-; PURECAP-LIBCALLS-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 16
+; PURECAP-LIBCALLS-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 16
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: atomic_cap_ptr_xchg:
@@ -39,17 +39,17 @@ define i32 @atomic_cap_ptr_xchg(i32 addrspace(200)* %ptr, i32 %val) nounwind {
 define i32 @atomic_cap_ptr_add(i32 addrspace(200)* %ptr, i32 %val) nounwind {
 ; PURECAP-ATOMICS-LABEL: atomic_cap_ptr_add:
 ; PURECAP-ATOMICS:       # %bb.0:
-; PURECAP-ATOMICS-NEXT:    camoadd.w.aqrl a0, a1, (ca0)
+; PURECAP-ATOMICS-NEXT:    camoadd.w.aqrl a0, a1, (a0)
 ; PURECAP-ATOMICS-NEXT:    cret
 ;
 ; PURECAP-LIBCALLS-LABEL: atomic_cap_ptr_add:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -16
-; PURECAP-LIBCALLS-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -16
+; PURECAP-LIBCALLS-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; PURECAP-LIBCALLS-NEXT:    li a2, 5
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_fetch_add_4
-; PURECAP-LIBCALLS-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 16
+; PURECAP-LIBCALLS-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 16
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: atomic_cap_ptr_add:
@@ -69,17 +69,17 @@ define i32 @atomic_cap_ptr_sub(i32 addrspace(200)* %ptr, i32 %val) nounwind {
 ; PURECAP-ATOMICS-LABEL: atomic_cap_ptr_sub:
 ; PURECAP-ATOMICS:       # %bb.0:
 ; PURECAP-ATOMICS-NEXT:    neg a1, a1
-; PURECAP-ATOMICS-NEXT:    camoadd.w.aqrl a0, a1, (ca0)
+; PURECAP-ATOMICS-NEXT:    camoadd.w.aqrl a0, a1, (a0)
 ; PURECAP-ATOMICS-NEXT:    cret
 ;
 ; PURECAP-LIBCALLS-LABEL: atomic_cap_ptr_sub:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -16
-; PURECAP-LIBCALLS-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -16
+; PURECAP-LIBCALLS-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; PURECAP-LIBCALLS-NEXT:    li a2, 5
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_fetch_sub_4
-; PURECAP-LIBCALLS-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 16
+; PURECAP-LIBCALLS-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 16
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: atomic_cap_ptr_sub:
@@ -98,17 +98,17 @@ define i32 @atomic_cap_ptr_sub(i32 addrspace(200)* %ptr, i32 %val) nounwind {
 define i32 @atomic_cap_ptr_and(i32 addrspace(200)* %ptr, i32 %val) nounwind {
 ; PURECAP-ATOMICS-LABEL: atomic_cap_ptr_and:
 ; PURECAP-ATOMICS:       # %bb.0:
-; PURECAP-ATOMICS-NEXT:    camoand.w.aqrl a0, a1, (ca0)
+; PURECAP-ATOMICS-NEXT:    camoand.w.aqrl a0, a1, (a0)
 ; PURECAP-ATOMICS-NEXT:    cret
 ;
 ; PURECAP-LIBCALLS-LABEL: atomic_cap_ptr_and:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -16
-; PURECAP-LIBCALLS-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -16
+; PURECAP-LIBCALLS-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; PURECAP-LIBCALLS-NEXT:    li a2, 5
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_fetch_and_4
-; PURECAP-LIBCALLS-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 16
+; PURECAP-LIBCALLS-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 16
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: atomic_cap_ptr_and:
@@ -128,10 +128,10 @@ define i32 @atomic_cap_ptr_nand(i32 addrspace(200)* %ptr, i32 %val) nounwind {
 ; PURECAP-ATOMICS-LABEL: atomic_cap_ptr_nand:
 ; PURECAP-ATOMICS:       # %bb.0:
 ; PURECAP-ATOMICS-NEXT:  .LBB4_1: # =>This Inner Loop Header: Depth=1
-; PURECAP-ATOMICS-NEXT:    clr.w.aqrl a2, (ca0)
+; PURECAP-ATOMICS-NEXT:    clr.w.aqrl a2, (a0)
 ; PURECAP-ATOMICS-NEXT:    and a3, a2, a1
 ; PURECAP-ATOMICS-NEXT:    not a3, a3
-; PURECAP-ATOMICS-NEXT:    csc.w.rl a3, a3, (ca0)
+; PURECAP-ATOMICS-NEXT:    csc.w.rl a3, a3, (a0)
 ; PURECAP-ATOMICS-NEXT:    bnez a3, .LBB4_1
 ; PURECAP-ATOMICS-NEXT:  # %bb.2:
 ; PURECAP-ATOMICS-NEXT:    mv a0, a2
@@ -139,12 +139,12 @@ define i32 @atomic_cap_ptr_nand(i32 addrspace(200)* %ptr, i32 %val) nounwind {
 ;
 ; PURECAP-LIBCALLS-LABEL: atomic_cap_ptr_nand:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -16
-; PURECAP-LIBCALLS-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -16
+; PURECAP-LIBCALLS-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; PURECAP-LIBCALLS-NEXT:    li a2, 5
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_fetch_nand_4
-; PURECAP-LIBCALLS-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 16
+; PURECAP-LIBCALLS-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 16
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: atomic_cap_ptr_nand:
@@ -163,17 +163,17 @@ define i32 @atomic_cap_ptr_nand(i32 addrspace(200)* %ptr, i32 %val) nounwind {
 define i32 @atomic_cap_ptr_or(i32 addrspace(200)* %ptr, i32 %val) nounwind {
 ; PURECAP-ATOMICS-LABEL: atomic_cap_ptr_or:
 ; PURECAP-ATOMICS:       # %bb.0:
-; PURECAP-ATOMICS-NEXT:    camoor.w.aqrl a0, a1, (ca0)
+; PURECAP-ATOMICS-NEXT:    camoor.w.aqrl a0, a1, (a0)
 ; PURECAP-ATOMICS-NEXT:    cret
 ;
 ; PURECAP-LIBCALLS-LABEL: atomic_cap_ptr_or:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -16
-; PURECAP-LIBCALLS-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -16
+; PURECAP-LIBCALLS-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; PURECAP-LIBCALLS-NEXT:    li a2, 5
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_fetch_or_4
-; PURECAP-LIBCALLS-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 16
+; PURECAP-LIBCALLS-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 16
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: atomic_cap_ptr_or:
@@ -192,17 +192,17 @@ define i32 @atomic_cap_ptr_or(i32 addrspace(200)* %ptr, i32 %val) nounwind {
 define i32 @atomic_cap_ptr_xor(i32 addrspace(200)* %ptr, i32 %val) nounwind {
 ; PURECAP-ATOMICS-LABEL: atomic_cap_ptr_xor:
 ; PURECAP-ATOMICS:       # %bb.0:
-; PURECAP-ATOMICS-NEXT:    camoxor.w.aqrl a0, a1, (ca0)
+; PURECAP-ATOMICS-NEXT:    camoxor.w.aqrl a0, a1, (a0)
 ; PURECAP-ATOMICS-NEXT:    cret
 ;
 ; PURECAP-LIBCALLS-LABEL: atomic_cap_ptr_xor:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -16
-; PURECAP-LIBCALLS-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -16
+; PURECAP-LIBCALLS-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; PURECAP-LIBCALLS-NEXT:    li a2, 5
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_fetch_xor_4
-; PURECAP-LIBCALLS-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 16
+; PURECAP-LIBCALLS-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 16
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: atomic_cap_ptr_xor:
@@ -221,31 +221,31 @@ define i32 @atomic_cap_ptr_xor(i32 addrspace(200)* %ptr, i32 %val) nounwind {
 define i32 @atomic_cap_ptr_max(i32 addrspace(200)* %ptr, i32 %val) nounwind {
 ; PURECAP-ATOMICS-LABEL: atomic_cap_ptr_max:
 ; PURECAP-ATOMICS:       # %bb.0:
-; PURECAP-ATOMICS-NEXT:    camomax.w.aqrl a0, a1, (ca0)
+; PURECAP-ATOMICS-NEXT:    camomax.w.aqrl a0, a1, (a0)
 ; PURECAP-ATOMICS-NEXT:    cret
 ;
 ; PURECAP-LIBCALLS-LABEL: atomic_cap_ptr_max:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -48
-; PURECAP-LIBCALLS-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -48
+; PURECAP-LIBCALLS-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
 ; PURECAP-LIBCALLS-NEXT:    mv s0, a1
-; PURECAP-LIBCALLS-NEXT:    cmove cs2, ca0
-; PURECAP-LIBCALLS-NEXT:    clw a1, 0(ca0)
-; PURECAP-LIBCALLS-NEXT:    cincoffset ca0, csp, 12
-; PURECAP-LIBCALLS-NEXT:    csetbounds cs1, ca0, 4
+; PURECAP-LIBCALLS-NEXT:    cmove s1, a0
+; PURECAP-LIBCALLS-NEXT:    clw a1, 0(a0)
+; PURECAP-LIBCALLS-NEXT:    cincoffset a0, sp, 12
+; PURECAP-LIBCALLS-NEXT:    csetbounds s2, a0, 4
 ; PURECAP-LIBCALLS-NEXT:    j .LBB7_2
 ; PURECAP-LIBCALLS-NEXT:  .LBB7_1: # %atomicrmw.start
 ; PURECAP-LIBCALLS-NEXT:    # in Loop: Header=BB7_2 Depth=1
-; PURECAP-LIBCALLS-NEXT:    csw a1, 12(csp)
+; PURECAP-LIBCALLS-NEXT:    csw a1, 12(sp)
 ; PURECAP-LIBCALLS-NEXT:    li a3, 5
 ; PURECAP-LIBCALLS-NEXT:    li a4, 5
-; PURECAP-LIBCALLS-NEXT:    cmove ca0, cs2
-; PURECAP-LIBCALLS-NEXT:    cmove ca1, cs1
+; PURECAP-LIBCALLS-NEXT:    cmove a0, s1
+; PURECAP-LIBCALLS-NEXT:    cmove a1, s2
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_compare_exchange_4
-; PURECAP-LIBCALLS-NEXT:    clw a1, 12(csp)
+; PURECAP-LIBCALLS-NEXT:    clw a1, 12(sp)
 ; PURECAP-LIBCALLS-NEXT:    bnez a0, .LBB7_4
 ; PURECAP-LIBCALLS-NEXT:  .LBB7_2: # %atomicrmw.start
 ; PURECAP-LIBCALLS-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -257,11 +257,11 @@ define i32 @atomic_cap_ptr_max(i32 addrspace(200)* %ptr, i32 %val) nounwind {
 ; PURECAP-LIBCALLS-NEXT:    j .LBB7_1
 ; PURECAP-LIBCALLS-NEXT:  .LBB7_4: # %atomicrmw.end
 ; PURECAP-LIBCALLS-NEXT:    mv a0, a1
-; PURECAP-LIBCALLS-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 48
+; PURECAP-LIBCALLS-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 48
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: atomic_cap_ptr_max:
@@ -269,8 +269,8 @@ define i32 @atomic_cap_ptr_max(i32 addrspace(200)* %ptr, i32 %val) nounwind {
 ; HYBRID-NEXT:    addi sp, sp, -32
 ; HYBRID-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; HYBRID-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
-; HYBRID-NEXT:    sc ca0, 8(sp) # 8-byte Folded Spill
-; HYBRID-NEXT:    lw.cap a3, (ca0)
+; HYBRID-NEXT:    sc a0, 8(sp) # 8-byte Folded Spill
+; HYBRID-NEXT:    lw.cap a3, (a0)
 ; HYBRID-NEXT:    mv s0, a1
 ; HYBRID-NEXT:    j .LBB7_2
 ; HYBRID-NEXT:  .LBB7_1: # %atomicrmw.start
@@ -279,7 +279,7 @@ define i32 @atomic_cap_ptr_max(i32 addrspace(200)* %ptr, i32 %val) nounwind {
 ; HYBRID-NEXT:    addi a1, sp, 20
 ; HYBRID-NEXT:    li a3, 5
 ; HYBRID-NEXT:    li a4, 5
-; HYBRID-NEXT:    lc ca0, 8(sp) # 8-byte Folded Reload
+; HYBRID-NEXT:    lc a0, 8(sp) # 8-byte Folded Reload
 ; HYBRID-NEXT:    call __atomic_compare_exchange_4_c
 ; HYBRID-NEXT:    lw a3, 20(sp)
 ; HYBRID-NEXT:    bnez a0, .LBB7_4
@@ -304,31 +304,31 @@ define i32 @atomic_cap_ptr_max(i32 addrspace(200)* %ptr, i32 %val) nounwind {
 define i32 @atomic_cap_ptr_min(i32 addrspace(200)* %ptr, i32 %val) nounwind {
 ; PURECAP-ATOMICS-LABEL: atomic_cap_ptr_min:
 ; PURECAP-ATOMICS:       # %bb.0:
-; PURECAP-ATOMICS-NEXT:    camomin.w.aqrl a0, a1, (ca0)
+; PURECAP-ATOMICS-NEXT:    camomin.w.aqrl a0, a1, (a0)
 ; PURECAP-ATOMICS-NEXT:    cret
 ;
 ; PURECAP-LIBCALLS-LABEL: atomic_cap_ptr_min:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -48
-; PURECAP-LIBCALLS-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -48
+; PURECAP-LIBCALLS-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
 ; PURECAP-LIBCALLS-NEXT:    mv s0, a1
-; PURECAP-LIBCALLS-NEXT:    cmove cs2, ca0
-; PURECAP-LIBCALLS-NEXT:    clw a1, 0(ca0)
-; PURECAP-LIBCALLS-NEXT:    cincoffset ca0, csp, 12
-; PURECAP-LIBCALLS-NEXT:    csetbounds cs1, ca0, 4
+; PURECAP-LIBCALLS-NEXT:    cmove s1, a0
+; PURECAP-LIBCALLS-NEXT:    clw a1, 0(a0)
+; PURECAP-LIBCALLS-NEXT:    cincoffset a0, sp, 12
+; PURECAP-LIBCALLS-NEXT:    csetbounds s2, a0, 4
 ; PURECAP-LIBCALLS-NEXT:    j .LBB8_2
 ; PURECAP-LIBCALLS-NEXT:  .LBB8_1: # %atomicrmw.start
 ; PURECAP-LIBCALLS-NEXT:    # in Loop: Header=BB8_2 Depth=1
-; PURECAP-LIBCALLS-NEXT:    csw a1, 12(csp)
+; PURECAP-LIBCALLS-NEXT:    csw a1, 12(sp)
 ; PURECAP-LIBCALLS-NEXT:    li a3, 5
 ; PURECAP-LIBCALLS-NEXT:    li a4, 5
-; PURECAP-LIBCALLS-NEXT:    cmove ca0, cs2
-; PURECAP-LIBCALLS-NEXT:    cmove ca1, cs1
+; PURECAP-LIBCALLS-NEXT:    cmove a0, s1
+; PURECAP-LIBCALLS-NEXT:    cmove a1, s2
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_compare_exchange_4
-; PURECAP-LIBCALLS-NEXT:    clw a1, 12(csp)
+; PURECAP-LIBCALLS-NEXT:    clw a1, 12(sp)
 ; PURECAP-LIBCALLS-NEXT:    bnez a0, .LBB8_4
 ; PURECAP-LIBCALLS-NEXT:  .LBB8_2: # %atomicrmw.start
 ; PURECAP-LIBCALLS-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -340,11 +340,11 @@ define i32 @atomic_cap_ptr_min(i32 addrspace(200)* %ptr, i32 %val) nounwind {
 ; PURECAP-LIBCALLS-NEXT:    j .LBB8_1
 ; PURECAP-LIBCALLS-NEXT:  .LBB8_4: # %atomicrmw.end
 ; PURECAP-LIBCALLS-NEXT:    mv a0, a1
-; PURECAP-LIBCALLS-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 48
+; PURECAP-LIBCALLS-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 48
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: atomic_cap_ptr_min:
@@ -352,8 +352,8 @@ define i32 @atomic_cap_ptr_min(i32 addrspace(200)* %ptr, i32 %val) nounwind {
 ; HYBRID-NEXT:    addi sp, sp, -32
 ; HYBRID-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; HYBRID-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
-; HYBRID-NEXT:    sc ca0, 8(sp) # 8-byte Folded Spill
-; HYBRID-NEXT:    lw.cap a3, (ca0)
+; HYBRID-NEXT:    sc a0, 8(sp) # 8-byte Folded Spill
+; HYBRID-NEXT:    lw.cap a3, (a0)
 ; HYBRID-NEXT:    mv s0, a1
 ; HYBRID-NEXT:    j .LBB8_2
 ; HYBRID-NEXT:  .LBB8_1: # %atomicrmw.start
@@ -362,7 +362,7 @@ define i32 @atomic_cap_ptr_min(i32 addrspace(200)* %ptr, i32 %val) nounwind {
 ; HYBRID-NEXT:    addi a1, sp, 20
 ; HYBRID-NEXT:    li a3, 5
 ; HYBRID-NEXT:    li a4, 5
-; HYBRID-NEXT:    lc ca0, 8(sp) # 8-byte Folded Reload
+; HYBRID-NEXT:    lc a0, 8(sp) # 8-byte Folded Reload
 ; HYBRID-NEXT:    call __atomic_compare_exchange_4_c
 ; HYBRID-NEXT:    lw a3, 20(sp)
 ; HYBRID-NEXT:    bnez a0, .LBB8_4
@@ -387,31 +387,31 @@ define i32 @atomic_cap_ptr_min(i32 addrspace(200)* %ptr, i32 %val) nounwind {
 define i32 @atomic_cap_ptr_umax(i32 addrspace(200)* %ptr, i32 %val) nounwind {
 ; PURECAP-ATOMICS-LABEL: atomic_cap_ptr_umax:
 ; PURECAP-ATOMICS:       # %bb.0:
-; PURECAP-ATOMICS-NEXT:    camomaxu.w.aqrl a0, a1, (ca0)
+; PURECAP-ATOMICS-NEXT:    camomaxu.w.aqrl a0, a1, (a0)
 ; PURECAP-ATOMICS-NEXT:    cret
 ;
 ; PURECAP-LIBCALLS-LABEL: atomic_cap_ptr_umax:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -48
-; PURECAP-LIBCALLS-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -48
+; PURECAP-LIBCALLS-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
 ; PURECAP-LIBCALLS-NEXT:    mv s0, a1
-; PURECAP-LIBCALLS-NEXT:    cmove cs2, ca0
-; PURECAP-LIBCALLS-NEXT:    clw a1, 0(ca0)
-; PURECAP-LIBCALLS-NEXT:    cincoffset ca0, csp, 12
-; PURECAP-LIBCALLS-NEXT:    csetbounds cs1, ca0, 4
+; PURECAP-LIBCALLS-NEXT:    cmove s1, a0
+; PURECAP-LIBCALLS-NEXT:    clw a1, 0(a0)
+; PURECAP-LIBCALLS-NEXT:    cincoffset a0, sp, 12
+; PURECAP-LIBCALLS-NEXT:    csetbounds s2, a0, 4
 ; PURECAP-LIBCALLS-NEXT:    j .LBB9_2
 ; PURECAP-LIBCALLS-NEXT:  .LBB9_1: # %atomicrmw.start
 ; PURECAP-LIBCALLS-NEXT:    # in Loop: Header=BB9_2 Depth=1
-; PURECAP-LIBCALLS-NEXT:    csw a1, 12(csp)
+; PURECAP-LIBCALLS-NEXT:    csw a1, 12(sp)
 ; PURECAP-LIBCALLS-NEXT:    li a3, 5
 ; PURECAP-LIBCALLS-NEXT:    li a4, 5
-; PURECAP-LIBCALLS-NEXT:    cmove ca0, cs2
-; PURECAP-LIBCALLS-NEXT:    cmove ca1, cs1
+; PURECAP-LIBCALLS-NEXT:    cmove a0, s1
+; PURECAP-LIBCALLS-NEXT:    cmove a1, s2
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_compare_exchange_4
-; PURECAP-LIBCALLS-NEXT:    clw a1, 12(csp)
+; PURECAP-LIBCALLS-NEXT:    clw a1, 12(sp)
 ; PURECAP-LIBCALLS-NEXT:    bnez a0, .LBB9_4
 ; PURECAP-LIBCALLS-NEXT:  .LBB9_2: # %atomicrmw.start
 ; PURECAP-LIBCALLS-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -423,11 +423,11 @@ define i32 @atomic_cap_ptr_umax(i32 addrspace(200)* %ptr, i32 %val) nounwind {
 ; PURECAP-LIBCALLS-NEXT:    j .LBB9_1
 ; PURECAP-LIBCALLS-NEXT:  .LBB9_4: # %atomicrmw.end
 ; PURECAP-LIBCALLS-NEXT:    mv a0, a1
-; PURECAP-LIBCALLS-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 48
+; PURECAP-LIBCALLS-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 48
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: atomic_cap_ptr_umax:
@@ -435,8 +435,8 @@ define i32 @atomic_cap_ptr_umax(i32 addrspace(200)* %ptr, i32 %val) nounwind {
 ; HYBRID-NEXT:    addi sp, sp, -32
 ; HYBRID-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; HYBRID-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
-; HYBRID-NEXT:    sc ca0, 8(sp) # 8-byte Folded Spill
-; HYBRID-NEXT:    lw.cap a3, (ca0)
+; HYBRID-NEXT:    sc a0, 8(sp) # 8-byte Folded Spill
+; HYBRID-NEXT:    lw.cap a3, (a0)
 ; HYBRID-NEXT:    mv s0, a1
 ; HYBRID-NEXT:    j .LBB9_2
 ; HYBRID-NEXT:  .LBB9_1: # %atomicrmw.start
@@ -445,7 +445,7 @@ define i32 @atomic_cap_ptr_umax(i32 addrspace(200)* %ptr, i32 %val) nounwind {
 ; HYBRID-NEXT:    addi a1, sp, 20
 ; HYBRID-NEXT:    li a3, 5
 ; HYBRID-NEXT:    li a4, 5
-; HYBRID-NEXT:    lc ca0, 8(sp) # 8-byte Folded Reload
+; HYBRID-NEXT:    lc a0, 8(sp) # 8-byte Folded Reload
 ; HYBRID-NEXT:    call __atomic_compare_exchange_4_c
 ; HYBRID-NEXT:    lw a3, 20(sp)
 ; HYBRID-NEXT:    bnez a0, .LBB9_4
@@ -470,31 +470,31 @@ define i32 @atomic_cap_ptr_umax(i32 addrspace(200)* %ptr, i32 %val) nounwind {
 define i32 @atomic_cap_ptr_umin(i32 addrspace(200)* %ptr, i32 %val) nounwind {
 ; PURECAP-ATOMICS-LABEL: atomic_cap_ptr_umin:
 ; PURECAP-ATOMICS:       # %bb.0:
-; PURECAP-ATOMICS-NEXT:    camominu.w.aqrl a0, a1, (ca0)
+; PURECAP-ATOMICS-NEXT:    camominu.w.aqrl a0, a1, (a0)
 ; PURECAP-ATOMICS-NEXT:    cret
 ;
 ; PURECAP-LIBCALLS-LABEL: atomic_cap_ptr_umin:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -48
-; PURECAP-LIBCALLS-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -48
+; PURECAP-LIBCALLS-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
 ; PURECAP-LIBCALLS-NEXT:    mv s0, a1
-; PURECAP-LIBCALLS-NEXT:    cmove cs2, ca0
-; PURECAP-LIBCALLS-NEXT:    clw a1, 0(ca0)
-; PURECAP-LIBCALLS-NEXT:    cincoffset ca0, csp, 12
-; PURECAP-LIBCALLS-NEXT:    csetbounds cs1, ca0, 4
+; PURECAP-LIBCALLS-NEXT:    cmove s1, a0
+; PURECAP-LIBCALLS-NEXT:    clw a1, 0(a0)
+; PURECAP-LIBCALLS-NEXT:    cincoffset a0, sp, 12
+; PURECAP-LIBCALLS-NEXT:    csetbounds s2, a0, 4
 ; PURECAP-LIBCALLS-NEXT:    j .LBB10_2
 ; PURECAP-LIBCALLS-NEXT:  .LBB10_1: # %atomicrmw.start
 ; PURECAP-LIBCALLS-NEXT:    # in Loop: Header=BB10_2 Depth=1
-; PURECAP-LIBCALLS-NEXT:    csw a1, 12(csp)
+; PURECAP-LIBCALLS-NEXT:    csw a1, 12(sp)
 ; PURECAP-LIBCALLS-NEXT:    li a3, 5
 ; PURECAP-LIBCALLS-NEXT:    li a4, 5
-; PURECAP-LIBCALLS-NEXT:    cmove ca0, cs2
-; PURECAP-LIBCALLS-NEXT:    cmove ca1, cs1
+; PURECAP-LIBCALLS-NEXT:    cmove a0, s1
+; PURECAP-LIBCALLS-NEXT:    cmove a1, s2
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_compare_exchange_4
-; PURECAP-LIBCALLS-NEXT:    clw a1, 12(csp)
+; PURECAP-LIBCALLS-NEXT:    clw a1, 12(sp)
 ; PURECAP-LIBCALLS-NEXT:    bnez a0, .LBB10_4
 ; PURECAP-LIBCALLS-NEXT:  .LBB10_2: # %atomicrmw.start
 ; PURECAP-LIBCALLS-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -506,11 +506,11 @@ define i32 @atomic_cap_ptr_umin(i32 addrspace(200)* %ptr, i32 %val) nounwind {
 ; PURECAP-LIBCALLS-NEXT:    j .LBB10_1
 ; PURECAP-LIBCALLS-NEXT:  .LBB10_4: # %atomicrmw.end
 ; PURECAP-LIBCALLS-NEXT:    mv a0, a1
-; PURECAP-LIBCALLS-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 48
+; PURECAP-LIBCALLS-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 48
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: atomic_cap_ptr_umin:
@@ -518,8 +518,8 @@ define i32 @atomic_cap_ptr_umin(i32 addrspace(200)* %ptr, i32 %val) nounwind {
 ; HYBRID-NEXT:    addi sp, sp, -32
 ; HYBRID-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; HYBRID-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
-; HYBRID-NEXT:    sc ca0, 8(sp) # 8-byte Folded Spill
-; HYBRID-NEXT:    lw.cap a3, (ca0)
+; HYBRID-NEXT:    sc a0, 8(sp) # 8-byte Folded Spill
+; HYBRID-NEXT:    lw.cap a3, (a0)
 ; HYBRID-NEXT:    mv s0, a1
 ; HYBRID-NEXT:    j .LBB10_2
 ; HYBRID-NEXT:  .LBB10_1: # %atomicrmw.start
@@ -528,7 +528,7 @@ define i32 @atomic_cap_ptr_umin(i32 addrspace(200)* %ptr, i32 %val) nounwind {
 ; HYBRID-NEXT:    addi a1, sp, 20
 ; HYBRID-NEXT:    li a3, 5
 ; HYBRID-NEXT:    li a4, 5
-; HYBRID-NEXT:    lc ca0, 8(sp) # 8-byte Folded Reload
+; HYBRID-NEXT:    lc a0, 8(sp) # 8-byte Folded Reload
 ; HYBRID-NEXT:    call __atomic_compare_exchange_4_c
 ; HYBRID-NEXT:    lw a3, 20(sp)
 ; HYBRID-NEXT:    bnez a0, .LBB10_4
@@ -553,7 +553,7 @@ define i32 @atomic_cap_ptr_umin(i32 addrspace(200)* %ptr, i32 %val) nounwind {
 define float @atomic_cap_ptr_fadd(float addrspace(200)* %ptr, float %val) nounwind {
 ; PURECAP-ATOMICS-LABEL: atomic_cap_ptr_fadd:
 ; PURECAP-ATOMICS:       # %bb.0:
-; PURECAP-ATOMICS-NEXT:    cflw fa5, 0(ca0)
+; PURECAP-ATOMICS-NEXT:    cflw fa5, 0(a0)
 ; PURECAP-ATOMICS-NEXT:  .LBB11_1: # %atomicrmw.start
 ; PURECAP-ATOMICS-NEXT:    # =>This Loop Header: Depth=1
 ; PURECAP-ATOMICS-NEXT:    # Child Loop BB11_3 Depth 2
@@ -563,11 +563,11 @@ define float @atomic_cap_ptr_fadd(float addrspace(200)* %ptr, float %val) nounwi
 ; PURECAP-ATOMICS-NEXT:  .LBB11_3: # %atomicrmw.start
 ; PURECAP-ATOMICS-NEXT:    # Parent Loop BB11_1 Depth=1
 ; PURECAP-ATOMICS-NEXT:    # => This Inner Loop Header: Depth=2
-; PURECAP-ATOMICS-NEXT:    clr.w.aqrl a3, (ca0)
+; PURECAP-ATOMICS-NEXT:    clr.w.aqrl a3, (a0)
 ; PURECAP-ATOMICS-NEXT:    bne a3, a2, .LBB11_5
 ; PURECAP-ATOMICS-NEXT:  # %bb.4: # %atomicrmw.start
 ; PURECAP-ATOMICS-NEXT:    # in Loop: Header=BB11_3 Depth=2
-; PURECAP-ATOMICS-NEXT:    csc.w.rl a4, a1, (ca0)
+; PURECAP-ATOMICS-NEXT:    csc.w.rl a4, a1, (a0)
 ; PURECAP-ATOMICS-NEXT:    bnez a4, .LBB11_3
 ; PURECAP-ATOMICS-NEXT:  .LBB11_5: # %atomicrmw.start
 ; PURECAP-ATOMICS-NEXT:    # in Loop: Header=BB11_1 Depth=1
@@ -579,34 +579,34 @@ define float @atomic_cap_ptr_fadd(float addrspace(200)* %ptr, float %val) nounwi
 ;
 ; PURECAP-LIBCALLS-LABEL: atomic_cap_ptr_fadd:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -32
-; PURECAP-LIBCALLS-NEXT:    csc cra, 24(csp) # 8-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs0, 16(csp) # 8-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs1, 8(csp) # 8-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    cfsw fs0, 4(csp) # 4-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -32
+; PURECAP-LIBCALLS-NEXT:    csc ra, 24(sp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s0, 16(sp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s1, 8(sp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    cfsw fs0, 4(sp) # 4-byte Folded Spill
 ; PURECAP-LIBCALLS-NEXT:    fmv.s fs0, fa0
-; PURECAP-LIBCALLS-NEXT:    cmove cs0, ca0
-; PURECAP-LIBCALLS-NEXT:    cflw fa0, 0(ca0)
-; PURECAP-LIBCALLS-NEXT:    cincoffset ca0, csp, 0
-; PURECAP-LIBCALLS-NEXT:    csetbounds cs1, ca0, 4
+; PURECAP-LIBCALLS-NEXT:    cmove s0, a0
+; PURECAP-LIBCALLS-NEXT:    cflw fa0, 0(a0)
+; PURECAP-LIBCALLS-NEXT:    cincoffset a0, sp, 0
+; PURECAP-LIBCALLS-NEXT:    csetbounds s1, a0, 4
 ; PURECAP-LIBCALLS-NEXT:  .LBB11_1: # %atomicrmw.start
 ; PURECAP-LIBCALLS-NEXT:    # =>This Inner Loop Header: Depth=1
 ; PURECAP-LIBCALLS-NEXT:    fadd.s fa5, fa0, fs0
-; PURECAP-LIBCALLS-NEXT:    cfsw fa0, 0(csp)
+; PURECAP-LIBCALLS-NEXT:    cfsw fa0, 0(sp)
 ; PURECAP-LIBCALLS-NEXT:    fmv.x.w a2, fa5
 ; PURECAP-LIBCALLS-NEXT:    li a3, 5
 ; PURECAP-LIBCALLS-NEXT:    li a4, 5
-; PURECAP-LIBCALLS-NEXT:    cmove ca0, cs0
-; PURECAP-LIBCALLS-NEXT:    cmove ca1, cs1
+; PURECAP-LIBCALLS-NEXT:    cmove a0, s0
+; PURECAP-LIBCALLS-NEXT:    cmove a1, s1
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_compare_exchange_4
-; PURECAP-LIBCALLS-NEXT:    cflw fa0, 0(csp)
+; PURECAP-LIBCALLS-NEXT:    cflw fa0, 0(sp)
 ; PURECAP-LIBCALLS-NEXT:    beqz a0, .LBB11_1
 ; PURECAP-LIBCALLS-NEXT:  # %bb.2: # %atomicrmw.end
-; PURECAP-LIBCALLS-NEXT:    clc cra, 24(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs0, 16(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs1, 8(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cflw fs0, 4(csp) # 4-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 32
+; PURECAP-LIBCALLS-NEXT:    clc ra, 24(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s0, 16(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s1, 8(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cflw fs0, 4(sp) # 4-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 32
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: atomic_cap_ptr_fadd:
@@ -615,8 +615,8 @@ define float @atomic_cap_ptr_fadd(float addrspace(200)* %ptr, float %val) nounwi
 ; HYBRID-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; HYBRID-NEXT:    fsw fs0, 24(sp) # 4-byte Folded Spill
 ; HYBRID-NEXT:    fmv.s fs0, fa0
-; HYBRID-NEXT:    sc ca0, 8(sp) # 8-byte Folded Spill
-; HYBRID-NEXT:    lw.cap a0, (ca0)
+; HYBRID-NEXT:    sc a0, 8(sp) # 8-byte Folded Spill
+; HYBRID-NEXT:    lw.cap a0, (a0)
 ; HYBRID-NEXT:    fmv.w.x fa0, a0
 ; HYBRID-NEXT:  .LBB11_1: # %atomicrmw.start
 ; HYBRID-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -626,7 +626,7 @@ define float @atomic_cap_ptr_fadd(float addrspace(200)* %ptr, float %val) nounwi
 ; HYBRID-NEXT:    addi a1, sp, 20
 ; HYBRID-NEXT:    li a3, 5
 ; HYBRID-NEXT:    li a4, 5
-; HYBRID-NEXT:    lc ca0, 8(sp) # 8-byte Folded Reload
+; HYBRID-NEXT:    lc a0, 8(sp) # 8-byte Folded Reload
 ; HYBRID-NEXT:    call __atomic_compare_exchange_4_c
 ; HYBRID-NEXT:    flw fa0, 20(sp)
 ; HYBRID-NEXT:    beqz a0, .LBB11_1
@@ -642,7 +642,7 @@ define float @atomic_cap_ptr_fadd(float addrspace(200)* %ptr, float %val) nounwi
 define float @atomic_cap_ptr_fsub(float addrspace(200)* %ptr, float %val) nounwind {
 ; PURECAP-ATOMICS-LABEL: atomic_cap_ptr_fsub:
 ; PURECAP-ATOMICS:       # %bb.0:
-; PURECAP-ATOMICS-NEXT:    cflw fa5, 0(ca0)
+; PURECAP-ATOMICS-NEXT:    cflw fa5, 0(a0)
 ; PURECAP-ATOMICS-NEXT:  .LBB12_1: # %atomicrmw.start
 ; PURECAP-ATOMICS-NEXT:    # =>This Loop Header: Depth=1
 ; PURECAP-ATOMICS-NEXT:    # Child Loop BB12_3 Depth 2
@@ -652,11 +652,11 @@ define float @atomic_cap_ptr_fsub(float addrspace(200)* %ptr, float %val) nounwi
 ; PURECAP-ATOMICS-NEXT:  .LBB12_3: # %atomicrmw.start
 ; PURECAP-ATOMICS-NEXT:    # Parent Loop BB12_1 Depth=1
 ; PURECAP-ATOMICS-NEXT:    # => This Inner Loop Header: Depth=2
-; PURECAP-ATOMICS-NEXT:    clr.w.aqrl a3, (ca0)
+; PURECAP-ATOMICS-NEXT:    clr.w.aqrl a3, (a0)
 ; PURECAP-ATOMICS-NEXT:    bne a3, a2, .LBB12_5
 ; PURECAP-ATOMICS-NEXT:  # %bb.4: # %atomicrmw.start
 ; PURECAP-ATOMICS-NEXT:    # in Loop: Header=BB12_3 Depth=2
-; PURECAP-ATOMICS-NEXT:    csc.w.rl a4, a1, (ca0)
+; PURECAP-ATOMICS-NEXT:    csc.w.rl a4, a1, (a0)
 ; PURECAP-ATOMICS-NEXT:    bnez a4, .LBB12_3
 ; PURECAP-ATOMICS-NEXT:  .LBB12_5: # %atomicrmw.start
 ; PURECAP-ATOMICS-NEXT:    # in Loop: Header=BB12_1 Depth=1
@@ -668,34 +668,34 @@ define float @atomic_cap_ptr_fsub(float addrspace(200)* %ptr, float %val) nounwi
 ;
 ; PURECAP-LIBCALLS-LABEL: atomic_cap_ptr_fsub:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -32
-; PURECAP-LIBCALLS-NEXT:    csc cra, 24(csp) # 8-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs0, 16(csp) # 8-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs1, 8(csp) # 8-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    cfsw fs0, 4(csp) # 4-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -32
+; PURECAP-LIBCALLS-NEXT:    csc ra, 24(sp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s0, 16(sp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s1, 8(sp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    cfsw fs0, 4(sp) # 4-byte Folded Spill
 ; PURECAP-LIBCALLS-NEXT:    fmv.s fs0, fa0
-; PURECAP-LIBCALLS-NEXT:    cmove cs0, ca0
-; PURECAP-LIBCALLS-NEXT:    cflw fa0, 0(ca0)
-; PURECAP-LIBCALLS-NEXT:    cincoffset ca0, csp, 0
-; PURECAP-LIBCALLS-NEXT:    csetbounds cs1, ca0, 4
+; PURECAP-LIBCALLS-NEXT:    cmove s0, a0
+; PURECAP-LIBCALLS-NEXT:    cflw fa0, 0(a0)
+; PURECAP-LIBCALLS-NEXT:    cincoffset a0, sp, 0
+; PURECAP-LIBCALLS-NEXT:    csetbounds s1, a0, 4
 ; PURECAP-LIBCALLS-NEXT:  .LBB12_1: # %atomicrmw.start
 ; PURECAP-LIBCALLS-NEXT:    # =>This Inner Loop Header: Depth=1
 ; PURECAP-LIBCALLS-NEXT:    fsub.s fa5, fa0, fs0
-; PURECAP-LIBCALLS-NEXT:    cfsw fa0, 0(csp)
+; PURECAP-LIBCALLS-NEXT:    cfsw fa0, 0(sp)
 ; PURECAP-LIBCALLS-NEXT:    fmv.x.w a2, fa5
 ; PURECAP-LIBCALLS-NEXT:    li a3, 5
 ; PURECAP-LIBCALLS-NEXT:    li a4, 5
-; PURECAP-LIBCALLS-NEXT:    cmove ca0, cs0
-; PURECAP-LIBCALLS-NEXT:    cmove ca1, cs1
+; PURECAP-LIBCALLS-NEXT:    cmove a0, s0
+; PURECAP-LIBCALLS-NEXT:    cmove a1, s1
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_compare_exchange_4
-; PURECAP-LIBCALLS-NEXT:    cflw fa0, 0(csp)
+; PURECAP-LIBCALLS-NEXT:    cflw fa0, 0(sp)
 ; PURECAP-LIBCALLS-NEXT:    beqz a0, .LBB12_1
 ; PURECAP-LIBCALLS-NEXT:  # %bb.2: # %atomicrmw.end
-; PURECAP-LIBCALLS-NEXT:    clc cra, 24(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs0, 16(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs1, 8(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cflw fs0, 4(csp) # 4-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 32
+; PURECAP-LIBCALLS-NEXT:    clc ra, 24(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s0, 16(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s1, 8(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cflw fs0, 4(sp) # 4-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 32
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: atomic_cap_ptr_fsub:
@@ -704,8 +704,8 @@ define float @atomic_cap_ptr_fsub(float addrspace(200)* %ptr, float %val) nounwi
 ; HYBRID-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; HYBRID-NEXT:    fsw fs0, 24(sp) # 4-byte Folded Spill
 ; HYBRID-NEXT:    fmv.s fs0, fa0
-; HYBRID-NEXT:    sc ca0, 8(sp) # 8-byte Folded Spill
-; HYBRID-NEXT:    lw.cap a0, (ca0)
+; HYBRID-NEXT:    sc a0, 8(sp) # 8-byte Folded Spill
+; HYBRID-NEXT:    lw.cap a0, (a0)
 ; HYBRID-NEXT:    fmv.w.x fa0, a0
 ; HYBRID-NEXT:  .LBB12_1: # %atomicrmw.start
 ; HYBRID-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -715,7 +715,7 @@ define float @atomic_cap_ptr_fsub(float addrspace(200)* %ptr, float %val) nounwi
 ; HYBRID-NEXT:    addi a1, sp, 20
 ; HYBRID-NEXT:    li a3, 5
 ; HYBRID-NEXT:    li a4, 5
-; HYBRID-NEXT:    lc ca0, 8(sp) # 8-byte Folded Reload
+; HYBRID-NEXT:    lc a0, 8(sp) # 8-byte Folded Reload
 ; HYBRID-NEXT:    call __atomic_compare_exchange_4_c
 ; HYBRID-NEXT:    flw fa0, 20(sp)
 ; HYBRID-NEXT:    beqz a0, .LBB12_1
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/bounded-allocas-lifetimes.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/bounded-allocas-lifetimes.ll
index 13938abf006cb..17527cc770795 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/bounded-allocas-lifetimes.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/bounded-allocas-lifetimes.ll
@@ -12,13 +12,13 @@ declare void @use(i8 addrspace(200)*)
 define void @static_alloca() {
   ; CHECK-LABEL: name: static_alloca
   ; CHECK: bb.0 (%ir-block.0):
-  ; CHECK-NEXT:   [[CIncOffsetImm:%[0-9]+]]:gpcr = CIncOffsetImm %stack.0, 0
-  ; CHECK-NEXT:   [[CSetBoundsImm:%[0-9]+]]:gpcr = CSetBoundsImm killed [[CIncOffsetImm]], 4
+  ; CHECK-NEXT:   [[CIncOffsetImm:%[0-9]+]]:ygpr = CIncOffsetImm %stack.0, 0
+  ; CHECK-NEXT:   [[CSetBoundsImm:%[0-9]+]]:ygpr = CSetBoundsImm killed [[CIncOffsetImm]], 4
   ; CHECK-NEXT:   LIFETIME_START %stack.0
-  ; CHECK-NEXT:   ADJCALLSTACKDOWNCAP 0, 0, implicit-def dead $c2, implicit $c2
-  ; CHECK-NEXT:   $c10 = COPY [[CSetBoundsImm]]
-  ; CHECK-NEXT:   PseudoCCALL target-flags(riscv-ccall) @use, csr_il32pc64f_l64pc128f, implicit-def dead $c1, implicit $c10, implicit-def $c2
-  ; CHECK-NEXT:   ADJCALLSTACKUPCAP 0, 0, implicit-def dead $c2, implicit $c2
+  ; CHECK-NEXT:   ADJCALLSTACKDOWNCAP 0, 0, implicit-def dead $x2_y, implicit $x2_y
+  ; CHECK-NEXT:   $x10_y = COPY [[CSetBoundsImm]]
+  ; CHECK-NEXT:   PseudoCCALL target-flags(riscv-ccall) @use, csr_il32pc64f_l64pc128f, implicit-def dead $x1_y, implicit $x10_y, implicit-def $x2_y
+  ; CHECK-NEXT:   ADJCALLSTACKUPCAP 0, 0, implicit-def dead $x2_y, implicit $x2_y
   ; CHECK-NEXT:   LIFETIME_END %stack.0
   ; CHECK-NEXT:   PseudoCRET
   %1 = alloca i32, align 4, addrspace(200)
@@ -37,8 +37,8 @@ define void @dynamic_alloca(i64 zeroext %n) {
   ; CHECK-NEXT:   liveins: $x10
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr = COPY $x10
-  ; CHECK-NEXT:   ADJCALLSTACKDOWNCAP 0, 0, implicit-def dead $c2, implicit $c2
-  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpcr = COPY $c2
+  ; CHECK-NEXT:   ADJCALLSTACKDOWNCAP 0, 0, implicit-def dead $x2_y, implicit $x2_y
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:ygpr = COPY $x2_y
   ; CHECK-NEXT:   [[PseudoCGetAddr:%[0-9]+]]:gpr = PseudoCGetAddr [[COPY1]]
   ; CHECK-NEXT:   [[SLLI:%[0-9]+]]:gpr = SLLI [[COPY]], 2
   ; CHECK-NEXT:   [[ADDI:%[0-9]+]]:gpr = ADDI [[SLLI]], 15
@@ -47,15 +47,15 @@ define void @dynamic_alloca(i64 zeroext %n) {
   ; CHECK-NEXT:   [[SUB:%[0-9]+]]:gpr = SUB killed [[PseudoCGetAddr]], [[CRRL]]
   ; CHECK-NEXT:   [[CRAM:%[0-9]+]]:gpr = CRAM [[ANDI]]
   ; CHECK-NEXT:   [[AND:%[0-9]+]]:gpr = AND killed [[SUB]], killed [[CRAM]]
-  ; CHECK-NEXT:   [[CSetAddr:%[0-9]+]]:gpcr = CSetAddr [[COPY1]], killed [[AND]]
-  ; CHECK-NEXT:   [[CSetBounds:%[0-9]+]]:gpcr = CSetBounds [[CSetAddr]], [[CRRL]]
-  ; CHECK-NEXT:   $c2 = COPY [[CSetAddr]]
-  ; CHECK-NEXT:   ADJCALLSTACKUPCAP 0, 0, implicit-def dead $c2, implicit $c2
-  ; CHECK-NEXT:   [[CSetBounds1:%[0-9]+]]:gpcr = CSetBounds killed [[CSetBounds]], [[SLLI]]
-  ; CHECK-NEXT:   ADJCALLSTACKDOWNCAP 0, 0, implicit-def dead $c2, implicit $c2
-  ; CHECK-NEXT:   $c10 = COPY [[CSetBounds1]]
-  ; CHECK-NEXT:   PseudoCCALL target-flags(riscv-ccall) @use, csr_il32pc64f_l64pc128f, implicit-def dead $c1, implicit $c10, implicit-def $c2
-  ; CHECK-NEXT:   ADJCALLSTACKUPCAP 0, 0, implicit-def dead $c2, implicit $c2
+  ; CHECK-NEXT:   [[CSetAddr:%[0-9]+]]:ygpr = CSetAddr [[COPY1]], killed [[AND]]
+  ; CHECK-NEXT:   [[CSetBounds:%[0-9]+]]:ygpr = CSetBounds [[CSetAddr]], [[CRRL]]
+  ; CHECK-NEXT:   $x2_y = COPY [[CSetAddr]]
+  ; CHECK-NEXT:   ADJCALLSTACKUPCAP 0, 0, implicit-def dead $x2_y, implicit $x2_y
+  ; CHECK-NEXT:   [[CSetBounds1:%[0-9]+]]:ygpr = CSetBounds killed [[CSetBounds]], [[SLLI]]
+  ; CHECK-NEXT:   ADJCALLSTACKDOWNCAP 0, 0, implicit-def dead $x2_y, implicit $x2_y
+  ; CHECK-NEXT:   $x10_y = COPY [[CSetBounds1]]
+  ; CHECK-NEXT:   PseudoCCALL target-flags(riscv-ccall) @use, csr_il32pc64f_l64pc128f, implicit-def dead $x1_y, implicit $x10_y, implicit-def $x2_y
+  ; CHECK-NEXT:   ADJCALLSTACKUPCAP 0, 0, implicit-def dead $x2_y, implicit $x2_y
   ; CHECK-NEXT:   PseudoCRET
   %1 = alloca i32, i64 %n, align 4, addrspace(200)
   %2 = bitcast i32 addrspace(200)* %1 to i8 addrspace(200)*
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/cap-from-ptr.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/cap-from-ptr.ll
index dc080e17aa0fe..ba504cf0042b5 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/cap-from-ptr.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/cap-from-ptr.ll
@@ -12,26 +12,26 @@ define internal ptr addrspace(200) @test(ptr addrspace(200) %ptr, ptr addrspace(
 ; PURECAP:       # %bb.0: # %entry
 ; PURECAP-NEXT:    bnez a2, .LBB0_2
 ; PURECAP-NEXT:  # %bb.1: # %entry
-; PURECAP-NEXT:    cmove ca1, cnull
+; PURECAP-NEXT:    cmove a1, zero
 ; PURECAP-NEXT:    j .LBB0_3
 ; PURECAP-NEXT:  .LBB0_2:
-; PURECAP-NEXT:    csetaddr ca1, ca1, a2
+; PURECAP-NEXT:    csetaddr a1, a1, a2
 ; PURECAP-NEXT:  .LBB0_3: # %entry
-; PURECAP-NEXT:    csc ca1, 0(ca0)
-; PURECAP-NEXT:    cmove ca0, ca1
+; PURECAP-NEXT:    csc a1, 0(a0)
+; PURECAP-NEXT:    cmove a0, a1
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: test:
 ; HYBRID:       # %bb.0: # %entry
 ; HYBRID-NEXT:    bnez a2, .LBB0_2
 ; HYBRID-NEXT:  # %bb.1: # %entry
-; HYBRID-NEXT:    cmove ca1, cnull
+; HYBRID-NEXT:    cmove a1, zero
 ; HYBRID-NEXT:    j .LBB0_3
 ; HYBRID-NEXT:  .LBB0_2:
-; HYBRID-NEXT:    csetaddr ca1, ca1, a2
+; HYBRID-NEXT:    csetaddr a1, a1, a2
 ; HYBRID-NEXT:  .LBB0_3: # %entry
-; HYBRID-NEXT:    sc.cap ca1, (ca0)
-; HYBRID-NEXT:    cmove ca0, ca1
+; HYBRID-NEXT:    sc.cap a1, (a0)
+; HYBRID-NEXT:    cmove a0, a1
 ; HYBRID-NEXT:    ret
 ; CHECK-IR-LABEL: define {{[^@]+}}@test
 ; CHECK-IR-SAME: (ptr addrspace(200) [[PTR:%.*]], ptr addrspace(200) [[CAP:%.*]], i32 [[OFFSET:%.*]]) addrspace(200) #[[ATTR0:[0-9]+]] {
@@ -50,14 +50,14 @@ entry:
 define internal ptr addrspace(200) @cap_from_ptr_zero(ptr addrspace(200) %ptr, ptr addrspace(200) %cap) addrspace(200) nounwind {
 ; PURECAP-LABEL: cap_from_ptr_zero:
 ; PURECAP:       # %bb.0: # %entry
-; PURECAP-NEXT:    csc cnull, 0(ca0)
-; PURECAP-NEXT:    cmove ca0, cnull
+; PURECAP-NEXT:    csc zero, 0(a0)
+; PURECAP-NEXT:    cmove a0, zero
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: cap_from_ptr_zero:
 ; HYBRID:       # %bb.0: # %entry
-; HYBRID-NEXT:    sc.cap cnull, (ca0)
-; HYBRID-NEXT:    cmove ca0, cnull
+; HYBRID-NEXT:    sc.cap zero, (a0)
+; HYBRID-NEXT:    cmove a0, zero
 ; HYBRID-NEXT:    ret
 ; CHECK-IR-LABEL: define internal ptr addrspace(200) @cap_from_ptr_zero
 ; CHECK-IR-SAME: (ptr addrspace(200) [[PTR:%.*]], ptr addrspace(200) [[CAP:%.*]]) #[[ATTR0]] {
@@ -75,30 +75,30 @@ entry:
 define internal ptr addrspace(200) @cap_from_ptr_ddc(ptr addrspace(200) %ptr, i32 %offset) addrspace(200) nounwind {
 ; PURECAP-LABEL: cap_from_ptr_ddc:
 ; PURECAP:       # %bb.0: # %entry
-; PURECAP-NEXT:    cspecialr ca2, ddc
+; PURECAP-NEXT:    cspecialr a2, ddc
 ; PURECAP-NEXT:    bnez a1, .LBB2_2
 ; PURECAP-NEXT:  # %bb.1: # %entry
-; PURECAP-NEXT:    cmove ca1, cnull
+; PURECAP-NEXT:    cmove a1, zero
 ; PURECAP-NEXT:    j .LBB2_3
 ; PURECAP-NEXT:  .LBB2_2:
-; PURECAP-NEXT:    csetaddr ca1, ca2, a1
+; PURECAP-NEXT:    csetaddr a1, a2, a1
 ; PURECAP-NEXT:  .LBB2_3: # %entry
-; PURECAP-NEXT:    csc ca1, 0(ca0)
-; PURECAP-NEXT:    cmove ca0, ca1
+; PURECAP-NEXT:    csc a1, 0(a0)
+; PURECAP-NEXT:    cmove a0, a1
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: cap_from_ptr_ddc:
 ; HYBRID:       # %bb.0: # %entry
-; HYBRID-NEXT:    cspecialr ca2, ddc
+; HYBRID-NEXT:    cspecialr a2, ddc
 ; HYBRID-NEXT:    bnez a1, .LBB2_2
 ; HYBRID-NEXT:  # %bb.1: # %entry
-; HYBRID-NEXT:    cmove ca1, cnull
+; HYBRID-NEXT:    cmove a1, zero
 ; HYBRID-NEXT:    j .LBB2_3
 ; HYBRID-NEXT:  .LBB2_2:
-; HYBRID-NEXT:    csetaddr ca1, ca2, a1
+; HYBRID-NEXT:    csetaddr a1, a2, a1
 ; HYBRID-NEXT:  .LBB2_3: # %entry
-; HYBRID-NEXT:    sc.cap ca1, (ca0)
-; HYBRID-NEXT:    cmove ca0, ca1
+; HYBRID-NEXT:    sc.cap a1, (a0)
+; HYBRID-NEXT:    cmove a0, a1
 ; HYBRID-NEXT:    ret
 ; CHECK-IR-LABEL: define {{[^@]+}}@cap_from_ptr_ddc
 ; CHECK-IR-SAME: (ptr addrspace(200) [[PTR:%.*]], i32 [[OFFSET:%.*]]) addrspace(200) #[[ATTR0]] {
@@ -119,14 +119,14 @@ entry:
 define internal ptr addrspace(200) @cap_from_ptr_ddc_zero(ptr addrspace(200) %ptr) addrspace(200) nounwind {
 ; PURECAP-LABEL: cap_from_ptr_ddc_zero:
 ; PURECAP:       # %bb.0: # %entry
-; PURECAP-NEXT:    csc cnull, 0(ca0)
-; PURECAP-NEXT:    cmove ca0, cnull
+; PURECAP-NEXT:    csc zero, 0(a0)
+; PURECAP-NEXT:    cmove a0, zero
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: cap_from_ptr_ddc_zero:
 ; HYBRID:       # %bb.0: # %entry
-; HYBRID-NEXT:    sc.cap cnull, (ca0)
-; HYBRID-NEXT:    cmove ca0, cnull
+; HYBRID-NEXT:    sc.cap zero, (a0)
+; HYBRID-NEXT:    cmove a0, zero
 ; HYBRID-NEXT:    ret
 ; CHECK-IR-LABEL: define {{[^@]+}}@cap_from_ptr_ddc_zero
 ; CHECK-IR-SAME: (ptr addrspace(200) [[PTR:%.*]]) addrspace(200) #[[ATTR0]] {
@@ -147,26 +147,26 @@ define internal ptr addrspace(200) @cap_from_ptr_null(ptr addrspace(200) %ptr, i
 ; PURECAP:       # %bb.0: # %entry
 ; PURECAP-NEXT:    bnez a1, .LBB4_2
 ; PURECAP-NEXT:  # %bb.1: # %entry
-; PURECAP-NEXT:    cmove ca1, cnull
+; PURECAP-NEXT:    cmove a1, zero
 ; PURECAP-NEXT:    j .LBB4_3
 ; PURECAP-NEXT:  .LBB4_2:
-; PURECAP-NEXT:    csetaddr ca1, cnull, a1
+; PURECAP-NEXT:    csetaddr a1, zero, a1
 ; PURECAP-NEXT:  .LBB4_3: # %entry
-; PURECAP-NEXT:    csc ca1, 0(ca0)
-; PURECAP-NEXT:    cmove ca0, ca1
+; PURECAP-NEXT:    csc a1, 0(a0)
+; PURECAP-NEXT:    cmove a0, a1
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: cap_from_ptr_null:
 ; HYBRID:       # %bb.0: # %entry
 ; HYBRID-NEXT:    bnez a1, .LBB4_2
 ; HYBRID-NEXT:  # %bb.1: # %entry
-; HYBRID-NEXT:    cmove ca1, cnull
+; HYBRID-NEXT:    cmove a1, zero
 ; HYBRID-NEXT:    j .LBB4_3
 ; HYBRID-NEXT:  .LBB4_2:
-; HYBRID-NEXT:    csetaddr ca1, cnull, a1
+; HYBRID-NEXT:    csetaddr a1, zero, a1
 ; HYBRID-NEXT:  .LBB4_3: # %entry
-; HYBRID-NEXT:    sc.cap ca1, (ca0)
-; HYBRID-NEXT:    cmove ca0, ca1
+; HYBRID-NEXT:    sc.cap a1, (a0)
+; HYBRID-NEXT:    cmove a0, a1
 ; HYBRID-NEXT:    ret
 ; CHECK-IR-LABEL: define {{[^@]+}}@cap_from_ptr_null
 ; CHECK-IR-SAME: (ptr addrspace(200) [[PTR:%.*]], i32 [[OFFSET:%.*]]) addrspace(200) #[[ATTR0]] {
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/cheri-intrinsics-folding-broken-module-regression.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/cheri-intrinsics-folding-broken-module-regression.ll
index 50c6a604f56c6..cbaa2aab56786 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/cheri-intrinsics-folding-broken-module-regression.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/cheri-intrinsics-folding-broken-module-regression.ll
@@ -21,17 +21,17 @@ define void @g(i32 %x, i32 %y) addrspace(200) nounwind {
 ; ASM-LABEL: g:
 ; ASM:       # %bb.0:
 ; ASM-NEXT:  .LBB0_1: # Label of block must be emitted
-; ASM-NEXT:    auipcc ca2, %captab_pcrel_hi(d)
-; ASM-NEXT:    clc ca2, %pcrel_lo(.LBB0_1)(ca2)
+; ASM-NEXT:    auipcc a2, %captab_pcrel_hi(d)
+; ASM-NEXT:    clc a2, %pcrel_lo(.LBB0_1)(a2)
 ; ASM-NEXT:    add a1, a1, a0
 ; ASM-NEXT:  .LBB0_2: # Label of block must be emitted
-; ASM-NEXT:    auipcc ca3, %captab_pcrel_hi(e)
-; ASM-NEXT:    clc ca3, %pcrel_lo(.LBB0_2)(ca3)
-; ASM-NEXT:    cincoffset ca0, ca2, a0
-; ASM-NEXT:    cgetoffset a2, ca2
+; ASM-NEXT:    auipcc a3, %captab_pcrel_hi(e)
+; ASM-NEXT:    clc a3, %pcrel_lo(.LBB0_2)(a3)
+; ASM-NEXT:    cincoffset a0, a2, a0
+; ASM-NEXT:    cgetoffset a2, a2
 ; ASM-NEXT:    add a1, a1, a2
-; ASM-NEXT:    csetoffset ca0, ca0, a1
-; ASM-NEXT:    csc ca0, 0(ca3)
+; ASM-NEXT:    csetoffset a0, a0, a1
+; ASM-NEXT:    csc a0, 0(a3)
 ; ASM-NEXT:    cret
 ; CHECK-LABEL: define void @g
 ; CHECK-SAME: (i32 [[X:%.*]], i32 [[Y:%.*]]) addrspace(200) #[[ATTR0:[0-9]+]] {
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/cheri-memfn-call.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/cheri-memfn-call.ll
index 2861d2b0edb7c..b838fa2bfe1bc 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/cheri-memfn-call.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/cheri-memfn-call.ll
@@ -12,14 +12,14 @@ declare void @llvm.memcpy.p200.p200.i64(ptr addrspace(200) nocapture, ptr addrsp
 define void @call_memset(ptr addrspace(200) align 4 %dst) nounwind {
 ; PURECAP-LABEL: call_memset:
 ; PURECAP:       # %bb.0: # %entry
-; PURECAP-NEXT:    cincoffset csp, csp, -16
-; PURECAP-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; PURECAP-NEXT:    cincoffset sp, sp, -16
+; PURECAP-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; PURECAP-NEXT:    li a2, 40
 ; PURECAP-NEXT:    li a1, 0
 ; PURECAP-NEXT:    li a3, 0
 ; PURECAP-NEXT:    ccall memset
-; PURECAP-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; PURECAP-NEXT:    cincoffset csp, csp, 16
+; PURECAP-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; PURECAP-NEXT:    cincoffset sp, sp, 16
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: call_memset:
@@ -41,13 +41,13 @@ entry:
 define void @call_memcpy(ptr addrspace(200) align 4 %dst, ptr addrspace(200) align 4 %src) nounwind {
 ; PURECAP-LABEL: call_memcpy:
 ; PURECAP:       # %bb.0: # %entry
-; PURECAP-NEXT:    cincoffset csp, csp, -16
-; PURECAP-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; PURECAP-NEXT:    cincoffset sp, sp, -16
+; PURECAP-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; PURECAP-NEXT:    li a2, 40
 ; PURECAP-NEXT:    li a3, 0
 ; PURECAP-NEXT:    ccall memcpy
-; PURECAP-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; PURECAP-NEXT:    cincoffset csp, csp, 16
+; PURECAP-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; PURECAP-NEXT:    cincoffset sp, sp, 16
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: call_memcpy:
@@ -68,13 +68,13 @@ entry:
 define void @call_memmove(ptr addrspace(200) align 4 %dst, ptr addrspace(200) align 4 %src) nounwind {
 ; PURECAP-LABEL: call_memmove:
 ; PURECAP:       # %bb.0: # %entry
-; PURECAP-NEXT:    cincoffset csp, csp, -16
-; PURECAP-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; PURECAP-NEXT:    cincoffset sp, sp, -16
+; PURECAP-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; PURECAP-NEXT:    li a2, 40
 ; PURECAP-NEXT:    li a3, 0
 ; PURECAP-NEXT:    ccall memmove
-; PURECAP-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; PURECAP-NEXT:    cincoffset csp, csp, 16
+; PURECAP-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; PURECAP-NEXT:    cincoffset sp, sp, 16
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: call_memmove:
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/cheri-pointer-comparison.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/cheri-pointer-comparison.ll
index 6220b1038f5ba..487379d6c9bdb 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/cheri-pointer-comparison.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/cheri-pointer-comparison.ll
@@ -365,7 +365,7 @@ define i8 addrspace(200)* @select_eq(i8 addrspace(200)* %a, i8 addrspace(200)* %
 ; HYBRID:       # %bb.0:
 ; HYBRID-NEXT:    beq a0, a1, .LBB20_2
 ; HYBRID-NEXT:  # %bb.1:
-; HYBRID-NEXT:    cmove ca0, ca1
+; HYBRID-NEXT:    cmove a0, a1
 ; HYBRID-NEXT:  .LBB20_2:
 ; HYBRID-NEXT:    ret
 ;
@@ -373,7 +373,7 @@ define i8 addrspace(200)* @select_eq(i8 addrspace(200)* %a, i8 addrspace(200)* %
 ; PURECAP:       # %bb.0:
 ; PURECAP-NEXT:    beq a0, a1, .LBB20_2
 ; PURECAP-NEXT:  # %bb.1:
-; PURECAP-NEXT:    cmove ca0, ca1
+; PURECAP-NEXT:    cmove a0, a1
 ; PURECAP-NEXT:  .LBB20_2:
 ; PURECAP-NEXT:    cret
   %cmp = icmp eq i8 addrspace(200)* %a, %b
@@ -386,7 +386,7 @@ define i8 addrspace(200)* @select_ne(i8 addrspace(200)* %a, i8 addrspace(200)* %
 ; HYBRID:       # %bb.0:
 ; HYBRID-NEXT:    bne a0, a1, .LBB21_2
 ; HYBRID-NEXT:  # %bb.1:
-; HYBRID-NEXT:    cmove ca0, ca1
+; HYBRID-NEXT:    cmove a0, a1
 ; HYBRID-NEXT:  .LBB21_2:
 ; HYBRID-NEXT:    ret
 ;
@@ -394,7 +394,7 @@ define i8 addrspace(200)* @select_ne(i8 addrspace(200)* %a, i8 addrspace(200)* %
 ; PURECAP:       # %bb.0:
 ; PURECAP-NEXT:    bne a0, a1, .LBB21_2
 ; PURECAP-NEXT:  # %bb.1:
-; PURECAP-NEXT:    cmove ca0, ca1
+; PURECAP-NEXT:    cmove a0, a1
 ; PURECAP-NEXT:  .LBB21_2:
 ; PURECAP-NEXT:    cret
   %cmp = icmp ne i8 addrspace(200)* %a, %b
@@ -407,7 +407,7 @@ define i8 addrspace(200)* @select_ugt(i8 addrspace(200)* %a, i8 addrspace(200)*
 ; HYBRID:       # %bb.0:
 ; HYBRID-NEXT:    bltu a1, a0, .LBB22_2
 ; HYBRID-NEXT:  # %bb.1:
-; HYBRID-NEXT:    cmove ca0, ca1
+; HYBRID-NEXT:    cmove a0, a1
 ; HYBRID-NEXT:  .LBB22_2:
 ; HYBRID-NEXT:    ret
 ;
@@ -415,7 +415,7 @@ define i8 addrspace(200)* @select_ugt(i8 addrspace(200)* %a, i8 addrspace(200)*
 ; PURECAP:       # %bb.0:
 ; PURECAP-NEXT:    bltu a1, a0, .LBB22_2
 ; PURECAP-NEXT:  # %bb.1:
-; PURECAP-NEXT:    cmove ca0, ca1
+; PURECAP-NEXT:    cmove a0, a1
 ; PURECAP-NEXT:  .LBB22_2:
 ; PURECAP-NEXT:    cret
   %cmp = icmp ugt i8 addrspace(200)* %a, %b
@@ -428,7 +428,7 @@ define i8 addrspace(200)* @select_uge(i8 addrspace(200)* %a, i8 addrspace(200)*
 ; HYBRID:       # %bb.0:
 ; HYBRID-NEXT:    bgeu a0, a1, .LBB23_2
 ; HYBRID-NEXT:  # %bb.1:
-; HYBRID-NEXT:    cmove ca0, ca1
+; HYBRID-NEXT:    cmove a0, a1
 ; HYBRID-NEXT:  .LBB23_2:
 ; HYBRID-NEXT:    ret
 ;
@@ -436,7 +436,7 @@ define i8 addrspace(200)* @select_uge(i8 addrspace(200)* %a, i8 addrspace(200)*
 ; PURECAP:       # %bb.0:
 ; PURECAP-NEXT:    bgeu a0, a1, .LBB23_2
 ; PURECAP-NEXT:  # %bb.1:
-; PURECAP-NEXT:    cmove ca0, ca1
+; PURECAP-NEXT:    cmove a0, a1
 ; PURECAP-NEXT:  .LBB23_2:
 ; PURECAP-NEXT:    cret
   %cmp = icmp uge i8 addrspace(200)* %a, %b
@@ -449,7 +449,7 @@ define i8 addrspace(200)* @select_ult(i8 addrspace(200)* %a, i8 addrspace(200)*
 ; HYBRID:       # %bb.0:
 ; HYBRID-NEXT:    bltu a0, a1, .LBB24_2
 ; HYBRID-NEXT:  # %bb.1:
-; HYBRID-NEXT:    cmove ca0, ca1
+; HYBRID-NEXT:    cmove a0, a1
 ; HYBRID-NEXT:  .LBB24_2:
 ; HYBRID-NEXT:    ret
 ;
@@ -457,7 +457,7 @@ define i8 addrspace(200)* @select_ult(i8 addrspace(200)* %a, i8 addrspace(200)*
 ; PURECAP:       # %bb.0:
 ; PURECAP-NEXT:    bltu a0, a1, .LBB24_2
 ; PURECAP-NEXT:  # %bb.1:
-; PURECAP-NEXT:    cmove ca0, ca1
+; PURECAP-NEXT:    cmove a0, a1
 ; PURECAP-NEXT:  .LBB24_2:
 ; PURECAP-NEXT:    cret
   %cmp = icmp ult i8 addrspace(200)* %a, %b
@@ -470,7 +470,7 @@ define i8 addrspace(200)* @select_ule(i8 addrspace(200)* %a, i8 addrspace(200)*
 ; HYBRID:       # %bb.0:
 ; HYBRID-NEXT:    bgeu a1, a0, .LBB25_2
 ; HYBRID-NEXT:  # %bb.1:
-; HYBRID-NEXT:    cmove ca0, ca1
+; HYBRID-NEXT:    cmove a0, a1
 ; HYBRID-NEXT:  .LBB25_2:
 ; HYBRID-NEXT:    ret
 ;
@@ -478,7 +478,7 @@ define i8 addrspace(200)* @select_ule(i8 addrspace(200)* %a, i8 addrspace(200)*
 ; PURECAP:       # %bb.0:
 ; PURECAP-NEXT:    bgeu a1, a0, .LBB25_2
 ; PURECAP-NEXT:  # %bb.1:
-; PURECAP-NEXT:    cmove ca0, ca1
+; PURECAP-NEXT:    cmove a0, a1
 ; PURECAP-NEXT:  .LBB25_2:
 ; PURECAP-NEXT:    cret
   %cmp = icmp ule i8 addrspace(200)* %a, %b
@@ -491,7 +491,7 @@ define i8 addrspace(200)* @select_sgt(i8 addrspace(200)* %a, i8 addrspace(200)*
 ; HYBRID:       # %bb.0:
 ; HYBRID-NEXT:    blt a1, a0, .LBB26_2
 ; HYBRID-NEXT:  # %bb.1:
-; HYBRID-NEXT:    cmove ca0, ca1
+; HYBRID-NEXT:    cmove a0, a1
 ; HYBRID-NEXT:  .LBB26_2:
 ; HYBRID-NEXT:    ret
 ;
@@ -499,7 +499,7 @@ define i8 addrspace(200)* @select_sgt(i8 addrspace(200)* %a, i8 addrspace(200)*
 ; PURECAP:       # %bb.0:
 ; PURECAP-NEXT:    blt a1, a0, .LBB26_2
 ; PURECAP-NEXT:  # %bb.1:
-; PURECAP-NEXT:    cmove ca0, ca1
+; PURECAP-NEXT:    cmove a0, a1
 ; PURECAP-NEXT:  .LBB26_2:
 ; PURECAP-NEXT:    cret
   %cmp = icmp sgt i8 addrspace(200)* %a, %b
@@ -512,7 +512,7 @@ define i8 addrspace(200)* @select_sge(i8 addrspace(200)* %a, i8 addrspace(200)*
 ; HYBRID:       # %bb.0:
 ; HYBRID-NEXT:    bge a0, a1, .LBB27_2
 ; HYBRID-NEXT:  # %bb.1:
-; HYBRID-NEXT:    cmove ca0, ca1
+; HYBRID-NEXT:    cmove a0, a1
 ; HYBRID-NEXT:  .LBB27_2:
 ; HYBRID-NEXT:    ret
 ;
@@ -520,7 +520,7 @@ define i8 addrspace(200)* @select_sge(i8 addrspace(200)* %a, i8 addrspace(200)*
 ; PURECAP:       # %bb.0:
 ; PURECAP-NEXT:    bge a0, a1, .LBB27_2
 ; PURECAP-NEXT:  # %bb.1:
-; PURECAP-NEXT:    cmove ca0, ca1
+; PURECAP-NEXT:    cmove a0, a1
 ; PURECAP-NEXT:  .LBB27_2:
 ; PURECAP-NEXT:    cret
   %cmp = icmp sge i8 addrspace(200)* %a, %b
@@ -533,7 +533,7 @@ define i8 addrspace(200)* @select_slt(i8 addrspace(200)* %a, i8 addrspace(200)*
 ; HYBRID:       # %bb.0:
 ; HYBRID-NEXT:    blt a0, a1, .LBB28_2
 ; HYBRID-NEXT:  # %bb.1:
-; HYBRID-NEXT:    cmove ca0, ca1
+; HYBRID-NEXT:    cmove a0, a1
 ; HYBRID-NEXT:  .LBB28_2:
 ; HYBRID-NEXT:    ret
 ;
@@ -541,7 +541,7 @@ define i8 addrspace(200)* @select_slt(i8 addrspace(200)* %a, i8 addrspace(200)*
 ; PURECAP:       # %bb.0:
 ; PURECAP-NEXT:    blt a0, a1, .LBB28_2
 ; PURECAP-NEXT:  # %bb.1:
-; PURECAP-NEXT:    cmove ca0, ca1
+; PURECAP-NEXT:    cmove a0, a1
 ; PURECAP-NEXT:  .LBB28_2:
 ; PURECAP-NEXT:    cret
   %cmp = icmp slt i8 addrspace(200)* %a, %b
@@ -554,7 +554,7 @@ define i8 addrspace(200)* @select_sle(i8 addrspace(200)* %a, i8 addrspace(200)*
 ; HYBRID:       # %bb.0:
 ; HYBRID-NEXT:    bge a1, a0, .LBB29_2
 ; HYBRID-NEXT:  # %bb.1:
-; HYBRID-NEXT:    cmove ca0, ca1
+; HYBRID-NEXT:    cmove a0, a1
 ; HYBRID-NEXT:  .LBB29_2:
 ; HYBRID-NEXT:    ret
 ;
@@ -562,7 +562,7 @@ define i8 addrspace(200)* @select_sle(i8 addrspace(200)* %a, i8 addrspace(200)*
 ; PURECAP:       # %bb.0:
 ; PURECAP-NEXT:    bge a1, a0, .LBB29_2
 ; PURECAP-NEXT:  # %bb.1:
-; PURECAP-NEXT:    cmove ca0, ca1
+; PURECAP-NEXT:    cmove a0, a1
 ; PURECAP-NEXT:  .LBB29_2:
 ; PURECAP-NEXT:    cret
   %cmp = icmp sle i8 addrspace(200)* %a, %b
@@ -575,7 +575,7 @@ define i8 addrspace(200)* @select_eq_null(i8 addrspace(200)* %a, i8 addrspace(20
 ; HYBRID:       # %bb.0:
 ; HYBRID-NEXT:    beqz a0, .LBB30_2
 ; HYBRID-NEXT:  # %bb.1:
-; HYBRID-NEXT:    cmove ca0, ca1
+; HYBRID-NEXT:    cmove a0, a1
 ; HYBRID-NEXT:  .LBB30_2:
 ; HYBRID-NEXT:    ret
 ;
@@ -583,7 +583,7 @@ define i8 addrspace(200)* @select_eq_null(i8 addrspace(200)* %a, i8 addrspace(20
 ; PURECAP:       # %bb.0:
 ; PURECAP-NEXT:    beqz a0, .LBB30_2
 ; PURECAP-NEXT:  # %bb.1:
-; PURECAP-NEXT:    cmove ca0, ca1
+; PURECAP-NEXT:    cmove a0, a1
 ; PURECAP-NEXT:  .LBB30_2:
 ; PURECAP-NEXT:    cret
   %cmp = icmp eq i8 addrspace(200)* %a, null
@@ -596,7 +596,7 @@ define i8 addrspace(200)* @select_ne_null(i8 addrspace(200)* %a, i8 addrspace(20
 ; HYBRID:       # %bb.0:
 ; HYBRID-NEXT:    bnez a0, .LBB31_2
 ; HYBRID-NEXT:  # %bb.1:
-; HYBRID-NEXT:    cmove ca0, ca1
+; HYBRID-NEXT:    cmove a0, a1
 ; HYBRID-NEXT:  .LBB31_2:
 ; HYBRID-NEXT:    ret
 ;
@@ -604,7 +604,7 @@ define i8 addrspace(200)* @select_ne_null(i8 addrspace(200)* %a, i8 addrspace(20
 ; PURECAP:       # %bb.0:
 ; PURECAP-NEXT:    bnez a0, .LBB31_2
 ; PURECAP-NEXT:  # %bb.1:
-; PURECAP-NEXT:    cmove ca0, ca1
+; PURECAP-NEXT:    cmove a0, a1
 ; PURECAP-NEXT:  .LBB31_2:
 ; PURECAP-NEXT:    cret
   %cmp = icmp ne i8 addrspace(200)* %a, null
@@ -617,7 +617,7 @@ define i8 addrspace(200)* @select_ugt_null(i8 addrspace(200)* %a, i8 addrspace(2
 ; HYBRID:       # %bb.0:
 ; HYBRID-NEXT:    bnez a0, .LBB32_2
 ; HYBRID-NEXT:  # %bb.1:
-; HYBRID-NEXT:    cmove ca0, ca1
+; HYBRID-NEXT:    cmove a0, a1
 ; HYBRID-NEXT:  .LBB32_2:
 ; HYBRID-NEXT:    ret
 ;
@@ -625,7 +625,7 @@ define i8 addrspace(200)* @select_ugt_null(i8 addrspace(200)* %a, i8 addrspace(2
 ; PURECAP:       # %bb.0:
 ; PURECAP-NEXT:    bnez a0, .LBB32_2
 ; PURECAP-NEXT:  # %bb.1:
-; PURECAP-NEXT:    cmove ca0, ca1
+; PURECAP-NEXT:    cmove a0, a1
 ; PURECAP-NEXT:  .LBB32_2:
 ; PURECAP-NEXT:    cret
   %cmp = icmp ugt i8 addrspace(200)* %a, null
@@ -638,7 +638,7 @@ define i8 addrspace(200)* @select_uge_null(i8 addrspace(200)* %a, i8 addrspace(2
 ; HYBRID:       # %bb.0:
 ; HYBRID-NEXT:    bgeu a0, zero, .LBB33_2
 ; HYBRID-NEXT:  # %bb.1:
-; HYBRID-NEXT:    cmove ca0, ca1
+; HYBRID-NEXT:    cmove a0, a1
 ; HYBRID-NEXT:  .LBB33_2:
 ; HYBRID-NEXT:    ret
 ;
@@ -646,7 +646,7 @@ define i8 addrspace(200)* @select_uge_null(i8 addrspace(200)* %a, i8 addrspace(2
 ; PURECAP:       # %bb.0:
 ; PURECAP-NEXT:    bgeu a0, zero, .LBB33_2
 ; PURECAP-NEXT:  # %bb.1:
-; PURECAP-NEXT:    cmove ca0, ca1
+; PURECAP-NEXT:    cmove a0, a1
 ; PURECAP-NEXT:  .LBB33_2:
 ; PURECAP-NEXT:    cret
   %cmp = icmp uge i8 addrspace(200)* %a, null
@@ -659,7 +659,7 @@ define i8 addrspace(200)* @select_ult_null(i8 addrspace(200)* %a, i8 addrspace(2
 ; HYBRID:       # %bb.0:
 ; HYBRID-NEXT:    bltu a0, zero, .LBB34_2
 ; HYBRID-NEXT:  # %bb.1:
-; HYBRID-NEXT:    cmove ca0, ca1
+; HYBRID-NEXT:    cmove a0, a1
 ; HYBRID-NEXT:  .LBB34_2:
 ; HYBRID-NEXT:    ret
 ;
@@ -667,7 +667,7 @@ define i8 addrspace(200)* @select_ult_null(i8 addrspace(200)* %a, i8 addrspace(2
 ; PURECAP:       # %bb.0:
 ; PURECAP-NEXT:    bltu a0, zero, .LBB34_2
 ; PURECAP-NEXT:  # %bb.1:
-; PURECAP-NEXT:    cmove ca0, ca1
+; PURECAP-NEXT:    cmove a0, a1
 ; PURECAP-NEXT:  .LBB34_2:
 ; PURECAP-NEXT:    cret
   %cmp = icmp ult i8 addrspace(200)* %a, null
@@ -680,7 +680,7 @@ define i8 addrspace(200)* @select_ule_null(i8 addrspace(200)* %a, i8 addrspace(2
 ; HYBRID:       # %bb.0:
 ; HYBRID-NEXT:    beqz a0, .LBB35_2
 ; HYBRID-NEXT:  # %bb.1:
-; HYBRID-NEXT:    cmove ca0, ca1
+; HYBRID-NEXT:    cmove a0, a1
 ; HYBRID-NEXT:  .LBB35_2:
 ; HYBRID-NEXT:    ret
 ;
@@ -688,7 +688,7 @@ define i8 addrspace(200)* @select_ule_null(i8 addrspace(200)* %a, i8 addrspace(2
 ; PURECAP:       # %bb.0:
 ; PURECAP-NEXT:    beqz a0, .LBB35_2
 ; PURECAP-NEXT:  # %bb.1:
-; PURECAP-NEXT:    cmove ca0, ca1
+; PURECAP-NEXT:    cmove a0, a1
 ; PURECAP-NEXT:  .LBB35_2:
 ; PURECAP-NEXT:    cret
   %cmp = icmp ule i8 addrspace(200)* %a, null
@@ -701,7 +701,7 @@ define i8 addrspace(200)* @select_sgt_null(i8 addrspace(200)* %a, i8 addrspace(2
 ; HYBRID:       # %bb.0:
 ; HYBRID-NEXT:    bgtz a0, .LBB36_2
 ; HYBRID-NEXT:  # %bb.1:
-; HYBRID-NEXT:    cmove ca0, ca1
+; HYBRID-NEXT:    cmove a0, a1
 ; HYBRID-NEXT:  .LBB36_2:
 ; HYBRID-NEXT:    ret
 ;
@@ -709,7 +709,7 @@ define i8 addrspace(200)* @select_sgt_null(i8 addrspace(200)* %a, i8 addrspace(2
 ; PURECAP:       # %bb.0:
 ; PURECAP-NEXT:    bgtz a0, .LBB36_2
 ; PURECAP-NEXT:  # %bb.1:
-; PURECAP-NEXT:    cmove ca0, ca1
+; PURECAP-NEXT:    cmove a0, a1
 ; PURECAP-NEXT:  .LBB36_2:
 ; PURECAP-NEXT:    cret
   %cmp = icmp sgt i8 addrspace(200)* %a, null
@@ -722,7 +722,7 @@ define i8 addrspace(200)* @select_sge_null(i8 addrspace(200)* %a, i8 addrspace(2
 ; HYBRID:       # %bb.0:
 ; HYBRID-NEXT:    bgez a0, .LBB37_2
 ; HYBRID-NEXT:  # %bb.1:
-; HYBRID-NEXT:    cmove ca0, ca1
+; HYBRID-NEXT:    cmove a0, a1
 ; HYBRID-NEXT:  .LBB37_2:
 ; HYBRID-NEXT:    ret
 ;
@@ -730,7 +730,7 @@ define i8 addrspace(200)* @select_sge_null(i8 addrspace(200)* %a, i8 addrspace(2
 ; PURECAP:       # %bb.0:
 ; PURECAP-NEXT:    bgez a0, .LBB37_2
 ; PURECAP-NEXT:  # %bb.1:
-; PURECAP-NEXT:    cmove ca0, ca1
+; PURECAP-NEXT:    cmove a0, a1
 ; PURECAP-NEXT:  .LBB37_2:
 ; PURECAP-NEXT:    cret
   %cmp = icmp sge i8 addrspace(200)* %a, null
@@ -743,7 +743,7 @@ define i8 addrspace(200)* @select_slt_null(i8 addrspace(200)* %a, i8 addrspace(2
 ; HYBRID:       # %bb.0:
 ; HYBRID-NEXT:    bltz a0, .LBB38_2
 ; HYBRID-NEXT:  # %bb.1:
-; HYBRID-NEXT:    cmove ca0, ca1
+; HYBRID-NEXT:    cmove a0, a1
 ; HYBRID-NEXT:  .LBB38_2:
 ; HYBRID-NEXT:    ret
 ;
@@ -751,7 +751,7 @@ define i8 addrspace(200)* @select_slt_null(i8 addrspace(200)* %a, i8 addrspace(2
 ; PURECAP:       # %bb.0:
 ; PURECAP-NEXT:    bltz a0, .LBB38_2
 ; PURECAP-NEXT:  # %bb.1:
-; PURECAP-NEXT:    cmove ca0, ca1
+; PURECAP-NEXT:    cmove a0, a1
 ; PURECAP-NEXT:  .LBB38_2:
 ; PURECAP-NEXT:    cret
   %cmp = icmp slt i8 addrspace(200)* %a, null
@@ -764,7 +764,7 @@ define i8 addrspace(200)* @select_sle_null(i8 addrspace(200)* %a, i8 addrspace(2
 ; HYBRID:       # %bb.0:
 ; HYBRID-NEXT:    blez a0, .LBB39_2
 ; HYBRID-NEXT:  # %bb.1:
-; HYBRID-NEXT:    cmove ca0, ca1
+; HYBRID-NEXT:    cmove a0, a1
 ; HYBRID-NEXT:  .LBB39_2:
 ; HYBRID-NEXT:    ret
 ;
@@ -772,7 +772,7 @@ define i8 addrspace(200)* @select_sle_null(i8 addrspace(200)* %a, i8 addrspace(2
 ; PURECAP:       # %bb.0:
 ; PURECAP-NEXT:    blez a0, .LBB39_2
 ; PURECAP-NEXT:  # %bb.1:
-; PURECAP-NEXT:    cmove ca0, ca1
+; PURECAP-NEXT:    cmove a0, a1
 ; PURECAP-NEXT:  .LBB39_2:
 ; PURECAP-NEXT:    cret
   %cmp = icmp sle i8 addrspace(200)* %a, null
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/cmpxchg-cap-ptr.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/cmpxchg-cap-ptr.ll
index a54a7f5089acc..bb4d3e7e6e210 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/cmpxchg-cap-ptr.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/cmpxchg-cap-ptr.ll
@@ -14,10 +14,10 @@ define { i8, i1 } @test_cmpxchg_strong_i8(ptr addrspace(200) %ptr, i8 %exp, i8 %
 ; PURECAP-ATOMICS-NEXT:    slli a1, a1, 24
 ; PURECAP-ATOMICS-NEXT:    srai a1, a1, 24
 ; PURECAP-ATOMICS-NEXT:  .LBB0_1: # =>This Inner Loop Header: Depth=1
-; PURECAP-ATOMICS-NEXT:    clr.b.aq a3, (ca0)
+; PURECAP-ATOMICS-NEXT:    clr.b.aq a3, (a0)
 ; PURECAP-ATOMICS-NEXT:    bne a3, a1, .LBB0_3
 ; PURECAP-ATOMICS-NEXT:  # %bb.2: # in Loop: Header=BB0_1 Depth=1
-; PURECAP-ATOMICS-NEXT:    csc.b.rl a4, a2, (ca0)
+; PURECAP-ATOMICS-NEXT:    csc.b.rl a4, a2, (a0)
 ; PURECAP-ATOMICS-NEXT:    bnez a4, .LBB0_1
 ; PURECAP-ATOMICS-NEXT:  .LBB0_3:
 ; PURECAP-ATOMICS-NEXT:    xor a1, a3, a1
@@ -27,20 +27,20 @@ define { i8, i1 } @test_cmpxchg_strong_i8(ptr addrspace(200) %ptr, i8 %exp, i8 %
 ;
 ; PURECAP-LIBCALLS-LABEL: test_cmpxchg_strong_i8:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -16
-; PURECAP-LIBCALLS-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csb a1, 7(csp)
-; PURECAP-LIBCALLS-NEXT:    cincoffset ca1, csp, 7
-; PURECAP-LIBCALLS-NEXT:    csetbounds ca1, ca1, 1
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -16
+; PURECAP-LIBCALLS-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csb a1, 7(sp)
+; PURECAP-LIBCALLS-NEXT:    cincoffset a1, sp, 7
+; PURECAP-LIBCALLS-NEXT:    csetbounds a1, a1, 1
 ; PURECAP-LIBCALLS-NEXT:    li a3, 4
 ; PURECAP-LIBCALLS-NEXT:    li a4, 2
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_compare_exchange_1
-; PURECAP-LIBCALLS-NEXT:    clb a1, 7(csp)
+; PURECAP-LIBCALLS-NEXT:    clb a1, 7(sp)
 ; PURECAP-LIBCALLS-NEXT:    mv a2, a0
 ; PURECAP-LIBCALLS-NEXT:    mv a0, a1
 ; PURECAP-LIBCALLS-NEXT:    mv a1, a2
-; PURECAP-LIBCALLS-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 16
+; PURECAP-LIBCALLS-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 16
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: test_cmpxchg_strong_i8:
@@ -69,10 +69,10 @@ define { i16, i1 } @test_cmpxchg_strong_i16(ptr addrspace(200) %ptr, i16 %exp, i
 ; PURECAP-ATOMICS-NEXT:    slli a1, a1, 16
 ; PURECAP-ATOMICS-NEXT:    srai a1, a1, 16
 ; PURECAP-ATOMICS-NEXT:  .LBB1_1: # =>This Inner Loop Header: Depth=1
-; PURECAP-ATOMICS-NEXT:    clr.h.aq a3, (ca0)
+; PURECAP-ATOMICS-NEXT:    clr.h.aq a3, (a0)
 ; PURECAP-ATOMICS-NEXT:    bne a3, a1, .LBB1_3
 ; PURECAP-ATOMICS-NEXT:  # %bb.2: # in Loop: Header=BB1_1 Depth=1
-; PURECAP-ATOMICS-NEXT:    csc.h.rl a4, a2, (ca0)
+; PURECAP-ATOMICS-NEXT:    csc.h.rl a4, a2, (a0)
 ; PURECAP-ATOMICS-NEXT:    bnez a4, .LBB1_1
 ; PURECAP-ATOMICS-NEXT:  .LBB1_3:
 ; PURECAP-ATOMICS-NEXT:    xor a1, a3, a1
@@ -82,20 +82,20 @@ define { i16, i1 } @test_cmpxchg_strong_i16(ptr addrspace(200) %ptr, i16 %exp, i
 ;
 ; PURECAP-LIBCALLS-LABEL: test_cmpxchg_strong_i16:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -16
-; PURECAP-LIBCALLS-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csh a1, 6(csp)
-; PURECAP-LIBCALLS-NEXT:    cincoffset ca1, csp, 6
-; PURECAP-LIBCALLS-NEXT:    csetbounds ca1, ca1, 2
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -16
+; PURECAP-LIBCALLS-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csh a1, 6(sp)
+; PURECAP-LIBCALLS-NEXT:    cincoffset a1, sp, 6
+; PURECAP-LIBCALLS-NEXT:    csetbounds a1, a1, 2
 ; PURECAP-LIBCALLS-NEXT:    li a3, 4
 ; PURECAP-LIBCALLS-NEXT:    li a4, 2
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_compare_exchange_2
-; PURECAP-LIBCALLS-NEXT:    clh a1, 6(csp)
+; PURECAP-LIBCALLS-NEXT:    clh a1, 6(sp)
 ; PURECAP-LIBCALLS-NEXT:    mv a2, a0
 ; PURECAP-LIBCALLS-NEXT:    mv a0, a1
 ; PURECAP-LIBCALLS-NEXT:    mv a1, a2
-; PURECAP-LIBCALLS-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 16
+; PURECAP-LIBCALLS-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 16
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: test_cmpxchg_strong_i16:
@@ -122,10 +122,10 @@ define { i32, i1 } @test_cmpxchg_strong_i32(ptr addrspace(200) %ptr, i32 %exp, i
 ; PURECAP-ATOMICS-LABEL: test_cmpxchg_strong_i32:
 ; PURECAP-ATOMICS:       # %bb.0:
 ; PURECAP-ATOMICS-NEXT:  .LBB2_1: # =>This Inner Loop Header: Depth=1
-; PURECAP-ATOMICS-NEXT:    clr.w.aq a3, (ca0)
+; PURECAP-ATOMICS-NEXT:    clr.w.aq a3, (a0)
 ; PURECAP-ATOMICS-NEXT:    bne a3, a1, .LBB2_3
 ; PURECAP-ATOMICS-NEXT:  # %bb.2: # in Loop: Header=BB2_1 Depth=1
-; PURECAP-ATOMICS-NEXT:    csc.w.rl a4, a2, (ca0)
+; PURECAP-ATOMICS-NEXT:    csc.w.rl a4, a2, (a0)
 ; PURECAP-ATOMICS-NEXT:    bnez a4, .LBB2_1
 ; PURECAP-ATOMICS-NEXT:  .LBB2_3:
 ; PURECAP-ATOMICS-NEXT:    xor a1, a3, a1
@@ -135,20 +135,20 @@ define { i32, i1 } @test_cmpxchg_strong_i32(ptr addrspace(200) %ptr, i32 %exp, i
 ;
 ; PURECAP-LIBCALLS-LABEL: test_cmpxchg_strong_i32:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -16
-; PURECAP-LIBCALLS-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csw a1, 4(csp)
-; PURECAP-LIBCALLS-NEXT:    cincoffset ca1, csp, 4
-; PURECAP-LIBCALLS-NEXT:    csetbounds ca1, ca1, 4
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -16
+; PURECAP-LIBCALLS-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csw a1, 4(sp)
+; PURECAP-LIBCALLS-NEXT:    cincoffset a1, sp, 4
+; PURECAP-LIBCALLS-NEXT:    csetbounds a1, a1, 4
 ; PURECAP-LIBCALLS-NEXT:    li a3, 4
 ; PURECAP-LIBCALLS-NEXT:    li a4, 2
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_compare_exchange_4
-; PURECAP-LIBCALLS-NEXT:    clw a1, 4(csp)
+; PURECAP-LIBCALLS-NEXT:    clw a1, 4(sp)
 ; PURECAP-LIBCALLS-NEXT:    mv a2, a0
 ; PURECAP-LIBCALLS-NEXT:    mv a0, a1
 ; PURECAP-LIBCALLS-NEXT:    mv a1, a2
-; PURECAP-LIBCALLS-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 16
+; PURECAP-LIBCALLS-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 16
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: test_cmpxchg_strong_i32:
@@ -174,31 +174,31 @@ define { i32, i1 } @test_cmpxchg_strong_i32(ptr addrspace(200) %ptr, i32 %exp, i
 define { i64, i1 } @test_cmpxchg_strong_i64(ptr addrspace(200) %ptr, i64 %exp, i64 %new) nounwind {
 ; PURECAP-LABEL: test_cmpxchg_strong_i64:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    cincoffset csp, csp, -32
-; PURECAP-NEXT:    csc cra, 24(csp) # 8-byte Folded Spill
-; PURECAP-NEXT:    csc cs0, 16(csp) # 8-byte Folded Spill
+; PURECAP-NEXT:    cincoffset sp, sp, -32
+; PURECAP-NEXT:    csc ra, 24(sp) # 8-byte Folded Spill
+; PURECAP-NEXT:    csc s0, 16(sp) # 8-byte Folded Spill
 ; PURECAP-NEXT:    mv a6, a5
 ; PURECAP-NEXT:    mv a7, a4
-; PURECAP-NEXT:    cmove ct0, ca1
-; PURECAP-NEXT:    cmove cs0, ca0
-; PURECAP-NEXT:    csw a3, 12(csp)
-; PURECAP-NEXT:    csw a2, 8(csp)
-; PURECAP-NEXT:    cincoffset ca0, csp, 8
-; PURECAP-NEXT:    csetbounds ca1, ca0, 8
+; PURECAP-NEXT:    cmove t0, a1
+; PURECAP-NEXT:    cmove s0, a0
+; PURECAP-NEXT:    csw a3, 12(sp)
+; PURECAP-NEXT:    csw a2, 8(sp)
+; PURECAP-NEXT:    cincoffset a0, sp, 8
+; PURECAP-NEXT:    csetbounds a1, a0, 8
 ; PURECAP-NEXT:    li a4, 4
 ; PURECAP-NEXT:    li a5, 2
-; PURECAP-NEXT:    cmove ca0, ct0
+; PURECAP-NEXT:    cmove a0, t0
 ; PURECAP-NEXT:    mv a2, a7
 ; PURECAP-NEXT:    mv a3, a6
 ; PURECAP-NEXT:    ccall __atomic_compare_exchange_8
-; PURECAP-NEXT:    clw a1, 12(csp)
-; PURECAP-NEXT:    clw a2, 8(csp)
-; PURECAP-NEXT:    csw a1, 4(cs0)
-; PURECAP-NEXT:    csw a2, 0(cs0)
-; PURECAP-NEXT:    csb a0, 8(cs0)
-; PURECAP-NEXT:    clc cra, 24(csp) # 8-byte Folded Reload
-; PURECAP-NEXT:    clc cs0, 16(csp) # 8-byte Folded Reload
-; PURECAP-NEXT:    cincoffset csp, csp, 32
+; PURECAP-NEXT:    clw a1, 12(sp)
+; PURECAP-NEXT:    clw a2, 8(sp)
+; PURECAP-NEXT:    csw a1, 4(s0)
+; PURECAP-NEXT:    csw a2, 0(s0)
+; PURECAP-NEXT:    csb a0, 8(s0)
+; PURECAP-NEXT:    clc ra, 24(sp) # 8-byte Folded Reload
+; PURECAP-NEXT:    clc s0, 16(sp) # 8-byte Folded Reload
+; PURECAP-NEXT:    cincoffset sp, sp, 32
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: test_cmpxchg_strong_i64:
@@ -208,14 +208,14 @@ define { i64, i1 } @test_cmpxchg_strong_i64(ptr addrspace(200) %ptr, i64 %exp, i
 ; HYBRID-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; HYBRID-NEXT:    mv a6, a5
 ; HYBRID-NEXT:    mv a7, a4
-; HYBRID-NEXT:    cmove ct0, ca1
+; HYBRID-NEXT:    cmove t0, a1
 ; HYBRID-NEXT:    mv s0, a0
 ; HYBRID-NEXT:    sw a2, 0(sp)
 ; HYBRID-NEXT:    sw a3, 4(sp)
 ; HYBRID-NEXT:    mv a1, sp
 ; HYBRID-NEXT:    li a4, 4
 ; HYBRID-NEXT:    li a5, 2
-; HYBRID-NEXT:    cmove ca0, ct0
+; HYBRID-NEXT:    cmove a0, t0
 ; HYBRID-NEXT:    mv a2, a7
 ; HYBRID-NEXT:    mv a3, a6
 ; HYBRID-NEXT:    call __atomic_compare_exchange_8_c
@@ -236,47 +236,47 @@ define { ptr addrspace(200), i1 } @test_cmpxchg_strong_cap(ptr addrspace(200) %p
 ; PURECAP-ATOMICS-LABEL: test_cmpxchg_strong_cap:
 ; PURECAP-ATOMICS:       # %bb.0:
 ; PURECAP-ATOMICS-NEXT:  .LBB4_1: # =>This Inner Loop Header: Depth=1
-; PURECAP-ATOMICS-NEXT:    clr.c.aq ca3, (ca0)
+; PURECAP-ATOMICS-NEXT:    clr.c.aq a3, (a0)
 ; PURECAP-ATOMICS-NEXT:    bne a3, a1, .LBB4_3
 ; PURECAP-ATOMICS-NEXT:  # %bb.2: # in Loop: Header=BB4_1 Depth=1
-; PURECAP-ATOMICS-NEXT:    csc.c.aq a4, ca2, (ca0)
+; PURECAP-ATOMICS-NEXT:    csc.c.aq a4, a2, (a0)
 ; PURECAP-ATOMICS-NEXT:    bnez a4, .LBB4_1
 ; PURECAP-ATOMICS-NEXT:  .LBB4_3:
 ; PURECAP-ATOMICS-NEXT:    xor a0, a3, a1
 ; PURECAP-ATOMICS-NEXT:    seqz a1, a0
-; PURECAP-ATOMICS-NEXT:    cmove ca0, ca3
+; PURECAP-ATOMICS-NEXT:    cmove a0, a3
 ; PURECAP-ATOMICS-NEXT:    cret
 ;
 ; PURECAP-LIBCALLS-LABEL: test_cmpxchg_strong_cap:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -16
-; PURECAP-LIBCALLS-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc ca1, 0(csp)
-; PURECAP-LIBCALLS-NEXT:    cincoffset ca1, csp, 0
-; PURECAP-LIBCALLS-NEXT:    csetbounds ca1, ca1, 8
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -16
+; PURECAP-LIBCALLS-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc a1, 0(sp)
+; PURECAP-LIBCALLS-NEXT:    cincoffset a1, sp, 0
+; PURECAP-LIBCALLS-NEXT:    csetbounds a1, a1, 8
 ; PURECAP-LIBCALLS-NEXT:    li a3, 4
 ; PURECAP-LIBCALLS-NEXT:    li a4, 2
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_compare_exchange_cap
-; PURECAP-LIBCALLS-NEXT:    clc ca1, 0(csp)
+; PURECAP-LIBCALLS-NEXT:    clc a1, 0(sp)
 ; PURECAP-LIBCALLS-NEXT:    mv a2, a0
-; PURECAP-LIBCALLS-NEXT:    cmove ca0, ca1
+; PURECAP-LIBCALLS-NEXT:    cmove a0, a1
 ; PURECAP-LIBCALLS-NEXT:    mv a1, a2
-; PURECAP-LIBCALLS-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 16
+; PURECAP-LIBCALLS-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 16
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: test_cmpxchg_strong_cap:
 ; HYBRID:       # %bb.0:
 ; HYBRID-NEXT:    addi sp, sp, -16
 ; HYBRID-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
-; HYBRID-NEXT:    sc ca1, 0(sp)
+; HYBRID-NEXT:    sc a1, 0(sp)
 ; HYBRID-NEXT:    mv a1, sp
 ; HYBRID-NEXT:    li a3, 4
 ; HYBRID-NEXT:    li a4, 2
 ; HYBRID-NEXT:    call __atomic_compare_exchange_cap_c
-; HYBRID-NEXT:    lc ca1, 0(sp)
+; HYBRID-NEXT:    lc a1, 0(sp)
 ; HYBRID-NEXT:    mv a2, a0
-; HYBRID-NEXT:    cmove ca0, ca1
+; HYBRID-NEXT:    cmove a0, a1
 ; HYBRID-NEXT:    mv a1, a2
 ; HYBRID-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; HYBRID-NEXT:    addi sp, sp, 16
@@ -289,47 +289,47 @@ define { ptr addrspace(200), i1 } @test_cmpxchg_strong_cap_i32(ptr addrspace(200
 ; PURECAP-ATOMICS-LABEL: test_cmpxchg_strong_cap_i32:
 ; PURECAP-ATOMICS:       # %bb.0:
 ; PURECAP-ATOMICS-NEXT:  .LBB5_1: # =>This Inner Loop Header: Depth=1
-; PURECAP-ATOMICS-NEXT:    clr.c.aq ca3, (ca0)
+; PURECAP-ATOMICS-NEXT:    clr.c.aq a3, (a0)
 ; PURECAP-ATOMICS-NEXT:    bne a3, a1, .LBB5_3
 ; PURECAP-ATOMICS-NEXT:  # %bb.2: # in Loop: Header=BB5_1 Depth=1
-; PURECAP-ATOMICS-NEXT:    csc.c.aq a4, ca2, (ca0)
+; PURECAP-ATOMICS-NEXT:    csc.c.aq a4, a2, (a0)
 ; PURECAP-ATOMICS-NEXT:    bnez a4, .LBB5_1
 ; PURECAP-ATOMICS-NEXT:  .LBB5_3:
 ; PURECAP-ATOMICS-NEXT:    xor a0, a3, a1
 ; PURECAP-ATOMICS-NEXT:    seqz a1, a0
-; PURECAP-ATOMICS-NEXT:    cmove ca0, ca3
+; PURECAP-ATOMICS-NEXT:    cmove a0, a3
 ; PURECAP-ATOMICS-NEXT:    cret
 ;
 ; PURECAP-LIBCALLS-LABEL: test_cmpxchg_strong_cap_i32:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -16
-; PURECAP-LIBCALLS-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc ca1, 0(csp)
-; PURECAP-LIBCALLS-NEXT:    cincoffset ca1, csp, 0
-; PURECAP-LIBCALLS-NEXT:    csetbounds ca1, ca1, 8
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -16
+; PURECAP-LIBCALLS-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc a1, 0(sp)
+; PURECAP-LIBCALLS-NEXT:    cincoffset a1, sp, 0
+; PURECAP-LIBCALLS-NEXT:    csetbounds a1, a1, 8
 ; PURECAP-LIBCALLS-NEXT:    li a3, 4
 ; PURECAP-LIBCALLS-NEXT:    li a4, 2
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_compare_exchange_cap
-; PURECAP-LIBCALLS-NEXT:    clc ca1, 0(csp)
+; PURECAP-LIBCALLS-NEXT:    clc a1, 0(sp)
 ; PURECAP-LIBCALLS-NEXT:    mv a2, a0
-; PURECAP-LIBCALLS-NEXT:    cmove ca0, ca1
+; PURECAP-LIBCALLS-NEXT:    cmove a0, a1
 ; PURECAP-LIBCALLS-NEXT:    mv a1, a2
-; PURECAP-LIBCALLS-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 16
+; PURECAP-LIBCALLS-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 16
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: test_cmpxchg_strong_cap_i32:
 ; HYBRID:       # %bb.0:
 ; HYBRID-NEXT:    addi sp, sp, -16
 ; HYBRID-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
-; HYBRID-NEXT:    sc ca1, 0(sp)
+; HYBRID-NEXT:    sc a1, 0(sp)
 ; HYBRID-NEXT:    mv a1, sp
 ; HYBRID-NEXT:    li a3, 4
 ; HYBRID-NEXT:    li a4, 2
 ; HYBRID-NEXT:    call __atomic_compare_exchange_cap_c
-; HYBRID-NEXT:    lc ca1, 0(sp)
+; HYBRID-NEXT:    lc a1, 0(sp)
 ; HYBRID-NEXT:    mv a2, a0
-; HYBRID-NEXT:    cmove ca0, ca1
+; HYBRID-NEXT:    cmove a0, a1
 ; HYBRID-NEXT:    mv a1, a2
 ; HYBRID-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; HYBRID-NEXT:    addi sp, sp, 16
@@ -345,10 +345,10 @@ define { i8, i1 } @test_cmpxchg_weak_i8(ptr addrspace(200) %ptr, i8 %exp, i8 %ne
 ; PURECAP-ATOMICS-NEXT:    slli a1, a1, 24
 ; PURECAP-ATOMICS-NEXT:    srai a1, a1, 24
 ; PURECAP-ATOMICS-NEXT:  .LBB6_1: # =>This Inner Loop Header: Depth=1
-; PURECAP-ATOMICS-NEXT:    clr.b.aq a3, (ca0)
+; PURECAP-ATOMICS-NEXT:    clr.b.aq a3, (a0)
 ; PURECAP-ATOMICS-NEXT:    bne a3, a1, .LBB6_3
 ; PURECAP-ATOMICS-NEXT:  # %bb.2: # in Loop: Header=BB6_1 Depth=1
-; PURECAP-ATOMICS-NEXT:    csc.b.rl a4, a2, (ca0)
+; PURECAP-ATOMICS-NEXT:    csc.b.rl a4, a2, (a0)
 ; PURECAP-ATOMICS-NEXT:    bnez a4, .LBB6_1
 ; PURECAP-ATOMICS-NEXT:  .LBB6_3:
 ; PURECAP-ATOMICS-NEXT:    xor a1, a3, a1
@@ -358,20 +358,20 @@ define { i8, i1 } @test_cmpxchg_weak_i8(ptr addrspace(200) %ptr, i8 %exp, i8 %ne
 ;
 ; PURECAP-LIBCALLS-LABEL: test_cmpxchg_weak_i8:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -16
-; PURECAP-LIBCALLS-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csb a1, 7(csp)
-; PURECAP-LIBCALLS-NEXT:    cincoffset ca1, csp, 7
-; PURECAP-LIBCALLS-NEXT:    csetbounds ca1, ca1, 1
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -16
+; PURECAP-LIBCALLS-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csb a1, 7(sp)
+; PURECAP-LIBCALLS-NEXT:    cincoffset a1, sp, 7
+; PURECAP-LIBCALLS-NEXT:    csetbounds a1, a1, 1
 ; PURECAP-LIBCALLS-NEXT:    li a3, 4
 ; PURECAP-LIBCALLS-NEXT:    li a4, 2
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_compare_exchange_1
-; PURECAP-LIBCALLS-NEXT:    clb a1, 7(csp)
+; PURECAP-LIBCALLS-NEXT:    clb a1, 7(sp)
 ; PURECAP-LIBCALLS-NEXT:    mv a2, a0
 ; PURECAP-LIBCALLS-NEXT:    mv a0, a1
 ; PURECAP-LIBCALLS-NEXT:    mv a1, a2
-; PURECAP-LIBCALLS-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 16
+; PURECAP-LIBCALLS-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 16
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: test_cmpxchg_weak_i8:
@@ -400,10 +400,10 @@ define { i16, i1 } @test_cmpxchg_weak_i16(ptr addrspace(200) %ptr, i16 %exp, i16
 ; PURECAP-ATOMICS-NEXT:    slli a1, a1, 16
 ; PURECAP-ATOMICS-NEXT:    srai a1, a1, 16
 ; PURECAP-ATOMICS-NEXT:  .LBB7_1: # =>This Inner Loop Header: Depth=1
-; PURECAP-ATOMICS-NEXT:    clr.h.aq a3, (ca0)
+; PURECAP-ATOMICS-NEXT:    clr.h.aq a3, (a0)
 ; PURECAP-ATOMICS-NEXT:    bne a3, a1, .LBB7_3
 ; PURECAP-ATOMICS-NEXT:  # %bb.2: # in Loop: Header=BB7_1 Depth=1
-; PURECAP-ATOMICS-NEXT:    csc.h.rl a4, a2, (ca0)
+; PURECAP-ATOMICS-NEXT:    csc.h.rl a4, a2, (a0)
 ; PURECAP-ATOMICS-NEXT:    bnez a4, .LBB7_1
 ; PURECAP-ATOMICS-NEXT:  .LBB7_3:
 ; PURECAP-ATOMICS-NEXT:    xor a1, a3, a1
@@ -413,20 +413,20 @@ define { i16, i1 } @test_cmpxchg_weak_i16(ptr addrspace(200) %ptr, i16 %exp, i16
 ;
 ; PURECAP-LIBCALLS-LABEL: test_cmpxchg_weak_i16:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -16
-; PURECAP-LIBCALLS-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csh a1, 6(csp)
-; PURECAP-LIBCALLS-NEXT:    cincoffset ca1, csp, 6
-; PURECAP-LIBCALLS-NEXT:    csetbounds ca1, ca1, 2
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -16
+; PURECAP-LIBCALLS-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csh a1, 6(sp)
+; PURECAP-LIBCALLS-NEXT:    cincoffset a1, sp, 6
+; PURECAP-LIBCALLS-NEXT:    csetbounds a1, a1, 2
 ; PURECAP-LIBCALLS-NEXT:    li a3, 4
 ; PURECAP-LIBCALLS-NEXT:    li a4, 2
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_compare_exchange_2
-; PURECAP-LIBCALLS-NEXT:    clh a1, 6(csp)
+; PURECAP-LIBCALLS-NEXT:    clh a1, 6(sp)
 ; PURECAP-LIBCALLS-NEXT:    mv a2, a0
 ; PURECAP-LIBCALLS-NEXT:    mv a0, a1
 ; PURECAP-LIBCALLS-NEXT:    mv a1, a2
-; PURECAP-LIBCALLS-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 16
+; PURECAP-LIBCALLS-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 16
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: test_cmpxchg_weak_i16:
@@ -453,10 +453,10 @@ define { i32, i1 } @test_cmpxchg_weak_i32(ptr addrspace(200) %ptr, i32 %exp, i32
 ; PURECAP-ATOMICS-LABEL: test_cmpxchg_weak_i32:
 ; PURECAP-ATOMICS:       # %bb.0:
 ; PURECAP-ATOMICS-NEXT:  .LBB8_1: # =>This Inner Loop Header: Depth=1
-; PURECAP-ATOMICS-NEXT:    clr.w.aq a3, (ca0)
+; PURECAP-ATOMICS-NEXT:    clr.w.aq a3, (a0)
 ; PURECAP-ATOMICS-NEXT:    bne a3, a1, .LBB8_3
 ; PURECAP-ATOMICS-NEXT:  # %bb.2: # in Loop: Header=BB8_1 Depth=1
-; PURECAP-ATOMICS-NEXT:    csc.w.rl a4, a2, (ca0)
+; PURECAP-ATOMICS-NEXT:    csc.w.rl a4, a2, (a0)
 ; PURECAP-ATOMICS-NEXT:    bnez a4, .LBB8_1
 ; PURECAP-ATOMICS-NEXT:  .LBB8_3:
 ; PURECAP-ATOMICS-NEXT:    xor a1, a3, a1
@@ -466,20 +466,20 @@ define { i32, i1 } @test_cmpxchg_weak_i32(ptr addrspace(200) %ptr, i32 %exp, i32
 ;
 ; PURECAP-LIBCALLS-LABEL: test_cmpxchg_weak_i32:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -16
-; PURECAP-LIBCALLS-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csw a1, 4(csp)
-; PURECAP-LIBCALLS-NEXT:    cincoffset ca1, csp, 4
-; PURECAP-LIBCALLS-NEXT:    csetbounds ca1, ca1, 4
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -16
+; PURECAP-LIBCALLS-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csw a1, 4(sp)
+; PURECAP-LIBCALLS-NEXT:    cincoffset a1, sp, 4
+; PURECAP-LIBCALLS-NEXT:    csetbounds a1, a1, 4
 ; PURECAP-LIBCALLS-NEXT:    li a3, 4
 ; PURECAP-LIBCALLS-NEXT:    li a4, 2
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_compare_exchange_4
-; PURECAP-LIBCALLS-NEXT:    clw a1, 4(csp)
+; PURECAP-LIBCALLS-NEXT:    clw a1, 4(sp)
 ; PURECAP-LIBCALLS-NEXT:    mv a2, a0
 ; PURECAP-LIBCALLS-NEXT:    mv a0, a1
 ; PURECAP-LIBCALLS-NEXT:    mv a1, a2
-; PURECAP-LIBCALLS-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 16
+; PURECAP-LIBCALLS-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 16
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: test_cmpxchg_weak_i32:
@@ -505,31 +505,31 @@ define { i32, i1 } @test_cmpxchg_weak_i32(ptr addrspace(200) %ptr, i32 %exp, i32
 define { i64, i1 } @test_cmpxchg_weak_i64(ptr addrspace(200) %ptr, i64 %exp, i64 %new) nounwind {
 ; PURECAP-LABEL: test_cmpxchg_weak_i64:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    cincoffset csp, csp, -32
-; PURECAP-NEXT:    csc cra, 24(csp) # 8-byte Folded Spill
-; PURECAP-NEXT:    csc cs0, 16(csp) # 8-byte Folded Spill
+; PURECAP-NEXT:    cincoffset sp, sp, -32
+; PURECAP-NEXT:    csc ra, 24(sp) # 8-byte Folded Spill
+; PURECAP-NEXT:    csc s0, 16(sp) # 8-byte Folded Spill
 ; PURECAP-NEXT:    mv a6, a5
 ; PURECAP-NEXT:    mv a7, a4
-; PURECAP-NEXT:    cmove ct0, ca1
-; PURECAP-NEXT:    cmove cs0, ca0
-; PURECAP-NEXT:    csw a3, 12(csp)
-; PURECAP-NEXT:    csw a2, 8(csp)
-; PURECAP-NEXT:    cincoffset ca0, csp, 8
-; PURECAP-NEXT:    csetbounds ca1, ca0, 8
+; PURECAP-NEXT:    cmove t0, a1
+; PURECAP-NEXT:    cmove s0, a0
+; PURECAP-NEXT:    csw a3, 12(sp)
+; PURECAP-NEXT:    csw a2, 8(sp)
+; PURECAP-NEXT:    cincoffset a0, sp, 8
+; PURECAP-NEXT:    csetbounds a1, a0, 8
 ; PURECAP-NEXT:    li a4, 4
 ; PURECAP-NEXT:    li a5, 2
-; PURECAP-NEXT:    cmove ca0, ct0
+; PURECAP-NEXT:    cmove a0, t0
 ; PURECAP-NEXT:    mv a2, a7
 ; PURECAP-NEXT:    mv a3, a6
 ; PURECAP-NEXT:    ccall __atomic_compare_exchange_8
-; PURECAP-NEXT:    clw a1, 12(csp)
-; PURECAP-NEXT:    clw a2, 8(csp)
-; PURECAP-NEXT:    csw a1, 4(cs0)
-; PURECAP-NEXT:    csw a2, 0(cs0)
-; PURECAP-NEXT:    csb a0, 8(cs0)
-; PURECAP-NEXT:    clc cra, 24(csp) # 8-byte Folded Reload
-; PURECAP-NEXT:    clc cs0, 16(csp) # 8-byte Folded Reload
-; PURECAP-NEXT:    cincoffset csp, csp, 32
+; PURECAP-NEXT:    clw a1, 12(sp)
+; PURECAP-NEXT:    clw a2, 8(sp)
+; PURECAP-NEXT:    csw a1, 4(s0)
+; PURECAP-NEXT:    csw a2, 0(s0)
+; PURECAP-NEXT:    csb a0, 8(s0)
+; PURECAP-NEXT:    clc ra, 24(sp) # 8-byte Folded Reload
+; PURECAP-NEXT:    clc s0, 16(sp) # 8-byte Folded Reload
+; PURECAP-NEXT:    cincoffset sp, sp, 32
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: test_cmpxchg_weak_i64:
@@ -539,14 +539,14 @@ define { i64, i1 } @test_cmpxchg_weak_i64(ptr addrspace(200) %ptr, i64 %exp, i64
 ; HYBRID-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; HYBRID-NEXT:    mv a6, a5
 ; HYBRID-NEXT:    mv a7, a4
-; HYBRID-NEXT:    cmove ct0, ca1
+; HYBRID-NEXT:    cmove t0, a1
 ; HYBRID-NEXT:    mv s0, a0
 ; HYBRID-NEXT:    sw a2, 0(sp)
 ; HYBRID-NEXT:    sw a3, 4(sp)
 ; HYBRID-NEXT:    mv a1, sp
 ; HYBRID-NEXT:    li a4, 4
 ; HYBRID-NEXT:    li a5, 2
-; HYBRID-NEXT:    cmove ca0, ct0
+; HYBRID-NEXT:    cmove a0, t0
 ; HYBRID-NEXT:    mv a2, a7
 ; HYBRID-NEXT:    mv a3, a6
 ; HYBRID-NEXT:    call __atomic_compare_exchange_8_c
@@ -567,47 +567,47 @@ define { ptr addrspace(200), i1 } @test_cmpxchg_weak_cap(ptr addrspace(200) %ptr
 ; PURECAP-ATOMICS-LABEL: test_cmpxchg_weak_cap:
 ; PURECAP-ATOMICS:       # %bb.0:
 ; PURECAP-ATOMICS-NEXT:  .LBB10_1: # =>This Inner Loop Header: Depth=1
-; PURECAP-ATOMICS-NEXT:    clr.c.aq ca3, (ca0)
+; PURECAP-ATOMICS-NEXT:    clr.c.aq a3, (a0)
 ; PURECAP-ATOMICS-NEXT:    bne a3, a1, .LBB10_3
 ; PURECAP-ATOMICS-NEXT:  # %bb.2: # in Loop: Header=BB10_1 Depth=1
-; PURECAP-ATOMICS-NEXT:    csc.c.aq a4, ca2, (ca0)
+; PURECAP-ATOMICS-NEXT:    csc.c.aq a4, a2, (a0)
 ; PURECAP-ATOMICS-NEXT:    bnez a4, .LBB10_1
 ; PURECAP-ATOMICS-NEXT:  .LBB10_3:
 ; PURECAP-ATOMICS-NEXT:    xor a0, a3, a1
 ; PURECAP-ATOMICS-NEXT:    seqz a1, a0
-; PURECAP-ATOMICS-NEXT:    cmove ca0, ca3
+; PURECAP-ATOMICS-NEXT:    cmove a0, a3
 ; PURECAP-ATOMICS-NEXT:    cret
 ;
 ; PURECAP-LIBCALLS-LABEL: test_cmpxchg_weak_cap:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -16
-; PURECAP-LIBCALLS-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc ca1, 0(csp)
-; PURECAP-LIBCALLS-NEXT:    cincoffset ca1, csp, 0
-; PURECAP-LIBCALLS-NEXT:    csetbounds ca1, ca1, 8
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -16
+; PURECAP-LIBCALLS-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc a1, 0(sp)
+; PURECAP-LIBCALLS-NEXT:    cincoffset a1, sp, 0
+; PURECAP-LIBCALLS-NEXT:    csetbounds a1, a1, 8
 ; PURECAP-LIBCALLS-NEXT:    li a3, 4
 ; PURECAP-LIBCALLS-NEXT:    li a4, 2
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_compare_exchange_cap
-; PURECAP-LIBCALLS-NEXT:    clc ca1, 0(csp)
+; PURECAP-LIBCALLS-NEXT:    clc a1, 0(sp)
 ; PURECAP-LIBCALLS-NEXT:    mv a2, a0
-; PURECAP-LIBCALLS-NEXT:    cmove ca0, ca1
+; PURECAP-LIBCALLS-NEXT:    cmove a0, a1
 ; PURECAP-LIBCALLS-NEXT:    mv a1, a2
-; PURECAP-LIBCALLS-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 16
+; PURECAP-LIBCALLS-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 16
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: test_cmpxchg_weak_cap:
 ; HYBRID:       # %bb.0:
 ; HYBRID-NEXT:    addi sp, sp, -16
 ; HYBRID-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
-; HYBRID-NEXT:    sc ca1, 0(sp)
+; HYBRID-NEXT:    sc a1, 0(sp)
 ; HYBRID-NEXT:    mv a1, sp
 ; HYBRID-NEXT:    li a3, 4
 ; HYBRID-NEXT:    li a4, 2
 ; HYBRID-NEXT:    call __atomic_compare_exchange_cap_c
-; HYBRID-NEXT:    lc ca1, 0(sp)
+; HYBRID-NEXT:    lc a1, 0(sp)
 ; HYBRID-NEXT:    mv a2, a0
-; HYBRID-NEXT:    cmove ca0, ca1
+; HYBRID-NEXT:    cmove a0, a1
 ; HYBRID-NEXT:    mv a1, a2
 ; HYBRID-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; HYBRID-NEXT:    addi sp, sp, 16
@@ -620,47 +620,47 @@ define { ptr addrspace(200), i1 } @test_cmpxchg_weak_cap_i32(ptr addrspace(200)
 ; PURECAP-ATOMICS-LABEL: test_cmpxchg_weak_cap_i32:
 ; PURECAP-ATOMICS:       # %bb.0:
 ; PURECAP-ATOMICS-NEXT:  .LBB11_1: # =>This Inner Loop Header: Depth=1
-; PURECAP-ATOMICS-NEXT:    clr.c.aq ca3, (ca0)
+; PURECAP-ATOMICS-NEXT:    clr.c.aq a3, (a0)
 ; PURECAP-ATOMICS-NEXT:    bne a3, a1, .LBB11_3
 ; PURECAP-ATOMICS-NEXT:  # %bb.2: # in Loop: Header=BB11_1 Depth=1
-; PURECAP-ATOMICS-NEXT:    csc.c.aq a4, ca2, (ca0)
+; PURECAP-ATOMICS-NEXT:    csc.c.aq a4, a2, (a0)
 ; PURECAP-ATOMICS-NEXT:    bnez a4, .LBB11_1
 ; PURECAP-ATOMICS-NEXT:  .LBB11_3:
 ; PURECAP-ATOMICS-NEXT:    xor a0, a3, a1
 ; PURECAP-ATOMICS-NEXT:    seqz a1, a0
-; PURECAP-ATOMICS-NEXT:    cmove ca0, ca3
+; PURECAP-ATOMICS-NEXT:    cmove a0, a3
 ; PURECAP-ATOMICS-NEXT:    cret
 ;
 ; PURECAP-LIBCALLS-LABEL: test_cmpxchg_weak_cap_i32:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -16
-; PURECAP-LIBCALLS-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc ca1, 0(csp)
-; PURECAP-LIBCALLS-NEXT:    cincoffset ca1, csp, 0
-; PURECAP-LIBCALLS-NEXT:    csetbounds ca1, ca1, 8
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -16
+; PURECAP-LIBCALLS-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc a1, 0(sp)
+; PURECAP-LIBCALLS-NEXT:    cincoffset a1, sp, 0
+; PURECAP-LIBCALLS-NEXT:    csetbounds a1, a1, 8
 ; PURECAP-LIBCALLS-NEXT:    li a3, 4
 ; PURECAP-LIBCALLS-NEXT:    li a4, 2
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_compare_exchange_cap
-; PURECAP-LIBCALLS-NEXT:    clc ca1, 0(csp)
+; PURECAP-LIBCALLS-NEXT:    clc a1, 0(sp)
 ; PURECAP-LIBCALLS-NEXT:    mv a2, a0
-; PURECAP-LIBCALLS-NEXT:    cmove ca0, ca1
+; PURECAP-LIBCALLS-NEXT:    cmove a0, a1
 ; PURECAP-LIBCALLS-NEXT:    mv a1, a2
-; PURECAP-LIBCALLS-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 16
+; PURECAP-LIBCALLS-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 16
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: test_cmpxchg_weak_cap_i32:
 ; HYBRID:       # %bb.0:
 ; HYBRID-NEXT:    addi sp, sp, -16
 ; HYBRID-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
-; HYBRID-NEXT:    sc ca1, 0(sp)
+; HYBRID-NEXT:    sc a1, 0(sp)
 ; HYBRID-NEXT:    mv a1, sp
 ; HYBRID-NEXT:    li a3, 4
 ; HYBRID-NEXT:    li a4, 2
 ; HYBRID-NEXT:    call __atomic_compare_exchange_cap_c
-; HYBRID-NEXT:    lc ca1, 0(sp)
+; HYBRID-NEXT:    lc a1, 0(sp)
 ; HYBRID-NEXT:    mv a2, a0
-; HYBRID-NEXT:    cmove ca0, ca1
+; HYBRID-NEXT:    cmove a0, a1
 ; HYBRID-NEXT:    mv a1, a2
 ; HYBRID-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; HYBRID-NEXT:    addi sp, sp, 16
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/dagcombine-ptradd-deleted-regression.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/dagcombine-ptradd-deleted-regression.ll
index 88ab85881772a..75f567d0a92f0 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/dagcombine-ptradd-deleted-regression.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/dagcombine-ptradd-deleted-regression.ll
@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --scrub-attributes --version 2
 ; DO NOT EDIT -- This file was generated from test/CodeGen/CHERI-Generic/Inputs/dagcombine-ptradd-deleted-regression.ll
-; This would previously crash DAGCombiner::visitPTRADD since the PTRADD
+; This would previously rash DAGCombiner::visitPTRADD since the PTRADD
 ; corresponding to the second GEP would be collapsed to a no-op when
 ; reassociated and delete the synthesised PTRADD node, not just the ADD, which
 ; the folding code was not prepared for.
@@ -14,23 +14,23 @@ define internal i32 @foo(i32 addrspace(200)* %a, i32 addrspace(200)* %b) nounwin
 ; HYBRID:       # %bb.0: # %entry
 ; HYBRID-NEXT:    addi sp, sp, -16
 ; HYBRID-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
-; HYBRID-NEXT:    cincoffset ca0, ca0, 4
-; HYBRID-NEXT:    sc ca0, 0(sp) # 8-byte Folded Spill
+; HYBRID-NEXT:    cincoffset a0, a0, 4
+; HYBRID-NEXT:    sc a0, 0(sp) # 8-byte Folded Spill
 ; HYBRID-NEXT:  .LBB0_1: # %loop
 ; HYBRID-NEXT:    # =>This Inner Loop Header: Depth=1
-; HYBRID-NEXT:    lc ca0, 0(sp) # 8-byte Folded Reload
+; HYBRID-NEXT:    lc a0, 0(sp) # 8-byte Folded Reload
 ; HYBRID-NEXT:    call bar
 ; HYBRID-NEXT:    j .LBB0_1
 ;
 ; PURECAP-LABEL: foo:
 ; PURECAP:       # %bb.0: # %entry
-; PURECAP-NEXT:    cincoffset csp, csp, -16
-; PURECAP-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; PURECAP-NEXT:    csc cs0, 0(csp) # 8-byte Folded Spill
-; PURECAP-NEXT:    cincoffset cs0, ca0, 4
+; PURECAP-NEXT:    cincoffset sp, sp, -16
+; PURECAP-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; PURECAP-NEXT:    csc s0, 0(sp) # 8-byte Folded Spill
+; PURECAP-NEXT:    cincoffset s0, a0, 4
 ; PURECAP-NEXT:  .LBB0_1: # %loop
 ; PURECAP-NEXT:    # =>This Inner Loop Header: Depth=1
-; PURECAP-NEXT:    cmove ca0, cs0
+; PURECAP-NEXT:    cmove a0, s0
 ; PURECAP-NEXT:    ccall bar
 ; PURECAP-NEXT:    j .LBB0_1
 entry:
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/frameindex-arith.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/frameindex-arith.ll
index aee3426edc30a..1acfd17af6876 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/frameindex-arith.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/frameindex-arith.ll
@@ -11,13 +11,13 @@
 define void @foo() nounwind {
 ; CHECK-LABEL: foo:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    cincoffset csp, csp, -16
-; CHECK-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; CHECK-NEXT:    cincoffset ca0, csp, 7
-; CHECK-NEXT:    csetbounds ca0, ca0, 0
+; CHECK-NEXT:    cincoffset sp, sp, -16
+; CHECK-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    cincoffset a0, sp, 7
+; CHECK-NEXT:    csetbounds a0, a0, 0
 ; CHECK-NEXT:    ccall bar
-; CHECK-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; CHECK-NEXT:    cincoffset csp, csp, 16
+; CHECK-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    cincoffset sp, sp, 16
 ; CHECK-NEXT:    cret
   %x = alloca [2 x i8], align 1, addrspace(200)
   %x_plus_1 = getelementptr inbounds [2 x i8], [2 x i8] addrspace(200)* %x, i32 0, i32 1
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/gvn-capability-store-to-load-fwd.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/gvn-capability-store-to-load-fwd.ll
index f8ece3981fd0f..731b3f51a7227 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/gvn-capability-store-to-load-fwd.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/gvn-capability-store-to-load-fwd.ll
@@ -24,10 +24,10 @@ target datalayout = "e-m:e-pf200:64:64:64:32-p:32:32-i64:64-n32-S128-A200-P200-G
 define i32 @first_i32_store_to_load_fwd(ptr addrspace(200) %arg) local_unnamed_addr addrspace(200) nounwind {
 ; ASM-LABEL: first_i32_store_to_load_fwd:
 ; ASM:       # %bb.0:
-; ASM-NEXT:    cincoffset csp, csp, -48
-; ASM-NEXT:    csc ca0, 0(csp)
-; ASM-NEXT:    clw a0, 0(csp)
-; ASM-NEXT:    cincoffset csp, csp, 48
+; ASM-NEXT:    cincoffset sp, sp, -48
+; ASM-NEXT:    csc a0, 0(sp)
+; ASM-NEXT:    clw a0, 0(sp)
+; ASM-NEXT:    cincoffset sp, sp, 48
 ; ASM-NEXT:    cret
 ; CHECK-LABEL: define i32 @first_i32_store_to_load_fwd
 ; CHECK-SAME: (ptr addrspace(200) [[ARG:%.*]]) local_unnamed_addr addrspace(200) #[[ATTR0:[0-9]+]] {
@@ -46,10 +46,10 @@ define i32 @first_i32_store_to_load_fwd(ptr addrspace(200) %arg) local_unnamed_a
 define i32 @second_i32_store_to_load_fwd(ptr addrspace(200) %arg) local_unnamed_addr addrspace(200) nounwind {
 ; ASM-LABEL: second_i32_store_to_load_fwd:
 ; ASM:       # %bb.0:
-; ASM-NEXT:    cincoffset csp, csp, -48
-; ASM-NEXT:    csc ca0, 0(csp)
-; ASM-NEXT:    clw a0, 4(csp)
-; ASM-NEXT:    cincoffset csp, csp, 48
+; ASM-NEXT:    cincoffset sp, sp, -48
+; ASM-NEXT:    csc a0, 0(sp)
+; ASM-NEXT:    clw a0, 4(sp)
+; ASM-NEXT:    cincoffset sp, sp, 48
 ; ASM-NEXT:    cret
 ; CHECK-LABEL: define i32 @second_i32_store_to_load_fwd
 ; CHECK-SAME: (ptr addrspace(200) [[ARG:%.*]]) local_unnamed_addr addrspace(200) #[[ATTR0]] {
@@ -69,10 +69,10 @@ define i32 @second_i32_store_to_load_fwd(ptr addrspace(200) %arg) local_unnamed_
 define i32 @third_i32_store_to_load_fwd(ptr addrspace(200) %arg) local_unnamed_addr addrspace(200) nounwind {
 ; ASM-LABEL: third_i32_store_to_load_fwd:
 ; ASM:       # %bb.0:
-; ASM-NEXT:    cincoffset csp, csp, -48
-; ASM-NEXT:    csc ca0, 0(csp)
+; ASM-NEXT:    cincoffset sp, sp, -48
+; ASM-NEXT:    csc a0, 0(sp)
 ; ASM-NEXT:    # implicit-def: $x10
-; ASM-NEXT:    cincoffset csp, csp, 48
+; ASM-NEXT:    cincoffset sp, sp, 48
 ; ASM-NEXT:    cret
 ; CHECK-LABEL: define i32 @third_i32_store_to_load_fwd
 ; CHECK-SAME: (ptr addrspace(200) [[ARG:%.*]]) local_unnamed_addr addrspace(200) #[[ATTR0]] {
@@ -91,10 +91,10 @@ define i32 @third_i32_store_to_load_fwd(ptr addrspace(200) %arg) local_unnamed_a
 define i32 @fourth_i32_store_to_load_fwd(ptr addrspace(200) %arg) local_unnamed_addr addrspace(200) nounwind {
 ; ASM-LABEL: fourth_i32_store_to_load_fwd:
 ; ASM:       # %bb.0:
-; ASM-NEXT:    cincoffset csp, csp, -48
-; ASM-NEXT:    csc ca0, 0(csp)
+; ASM-NEXT:    cincoffset sp, sp, -48
+; ASM-NEXT:    csc a0, 0(sp)
 ; ASM-NEXT:    # implicit-def: $x10
-; ASM-NEXT:    cincoffset csp, csp, 48
+; ASM-NEXT:    cincoffset sp, sp, 48
 ; ASM-NEXT:    cret
 ; CHECK-LABEL: define i32 @fourth_i32_store_to_load_fwd
 ; CHECK-SAME: (ptr addrspace(200) [[ARG:%.*]]) local_unnamed_addr addrspace(200) #[[ATTR0]] {
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/hoist-alloca.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/hoist-alloca.ll
index 4abc0c392efd7..79379e5ac2183 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/hoist-alloca.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/hoist-alloca.ll
@@ -34,22 +34,22 @@
 ; RUN: FileCheck --input-file=%t.dbg --check-prefix=MACHINELICM-DBG %s
 ; Check that MachineLICM hoists the CheriBoundedStackPseudoImm (MIPS) / IncOffset+SetBoundsImm (RISCV) instructions
 ; MACHINELICM-DBG-LABEL: ******** Pre-regalloc Machine LICM: hoist_alloca_uncond
-; MACHINELICM-DBG: Hoisting [[INC:%[0-9]+]]:gpcr = CIncOffsetImm %stack.0.buf1, 0
+; MACHINELICM-DBG: Hoisting [[INC:%[0-9]+]]:ygpr = CIncOffsetImm %stack.0.buf1, 0
 ; MACHINELICM-DBG-NEXT:  from %bb.2 to %bb.0
-; MACHINELICM-DBG: Hoisting [[BOUNDS:%[0-9]+]]:gpcr = CSetBoundsImm [[INC]]:gpcr, 512
+; MACHINELICM-DBG: Hoisting [[BOUNDS:%[0-9]+]]:ygpr = CSetBoundsImm [[INC]]:ygpr, 512
 ; MACHINELICM-DBG-NEXT:  from %bb.2 to %bb.0
-; MACHINELICM-DBG: Hoisting [[INC:%[0-9]+]]:gpcr = CIncOffsetImm %stack.1.buf2, 0
+; MACHINELICM-DBG: Hoisting [[INC:%[0-9]+]]:ygpr = CIncOffsetImm %stack.1.buf2, 0
 ; MACHINELICM-DBG-NEXT:  from %bb.2 to %bb.0
-; MACHINELICM-DBG: Hoisting [[BOUNDS:%[0-9]+]]:gpcr = CSetBoundsImm [[INC]]:gpcr, 88
+; MACHINELICM-DBG: Hoisting [[BOUNDS:%[0-9]+]]:ygpr = CSetBoundsImm [[INC]]:ygpr, 88
 ; MACHINELICM-DBG-NEXT:  from %bb.2 to %bb.0
 ; MACHINELICM-DBG-LABEL: ******** Pre-regalloc Machine LICM: hoist_alloca_cond
-; MACHINELICM-DBG: Hoisting [[INC:%[0-9]+]]:gpcr = CIncOffsetImm %stack.0.buf1, 0
+; MACHINELICM-DBG: Hoisting [[INC:%[0-9]+]]:ygpr = CIncOffsetImm %stack.0.buf1, 0
 ; MACHINELICM-DBG-NEXT:  from %bb.3 to %bb.0
-; MACHINELICM-DBG: Hoisting [[BOUNDS:%[0-9]+]]:gpcr = CSetBoundsImm [[INC]]:gpcr, 512
+; MACHINELICM-DBG: Hoisting [[BOUNDS:%[0-9]+]]:ygpr = CSetBoundsImm [[INC]]:ygpr, 512
 ; MACHINELICM-DBG-NEXT:  from %bb.3 to %bb.0
-; MACHINELICM-DBG: Hoisting [[INC:%[0-9]+]]:gpcr = CIncOffsetImm %stack.1.buf2, 0
+; MACHINELICM-DBG: Hoisting [[INC:%[0-9]+]]:ygpr = CIncOffsetImm %stack.1.buf2, 0
 ; MACHINELICM-DBG-NEXT:  from %bb.3 to %bb.0
-; MACHINELICM-DBG: Hoisting [[BOUNDS:%[0-9]+]]:gpcr = CSetBoundsImm [[INC]]:gpcr, 88
+; MACHINELICM-DBG: Hoisting [[BOUNDS:%[0-9]+]]:ygpr = CSetBoundsImm [[INC]]:ygpr, 88
 ; MACHINELICM-DBG-NEXT:  from %bb.3 to %bb.0
 
 ; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+xcheripurecap,+f -O1 -o - < %s | FileCheck %s
@@ -57,35 +57,35 @@
 define void @hoist_alloca_uncond(i32 signext %cond) local_unnamed_addr addrspace(200) nounwind {
 ; CHECK-LABEL: hoist_alloca_uncond:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    cincoffset csp, csp, -704
-; CHECK-NEXT:    csc cra, 696(csp) # 8-byte Folded Spill
-; CHECK-NEXT:    csc cs0, 688(csp) # 8-byte Folded Spill
-; CHECK-NEXT:    csc cs1, 680(csp) # 8-byte Folded Spill
-; CHECK-NEXT:    csc cs2, 672(csp) # 8-byte Folded Spill
-; CHECK-NEXT:    csc cs3, 664(csp) # 8-byte Folded Spill
-; CHECK-NEXT:    cincoffset cs0, csp, 704
+; CHECK-NEXT:    cincoffset sp, sp, -704
+; CHECK-NEXT:    csc ra, 696(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    csc s0, 688(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    csc s1, 680(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    csc s2, 672(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    csc s3, 664(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    cincoffset s0, sp, 704
 ; CHECK-NEXT:    andi a0, sp, -64
-; CHECK-NEXT:    csetaddr csp, csp, a0
+; CHECK-NEXT:    csetaddr sp, sp, a0
 ; CHECK-NEXT:    li s3, 100
-; CHECK-NEXT:    cincoffset ca0, csp, 128
-; CHECK-NEXT:    cincoffset ca1, csp, 40
-; CHECK-NEXT:    csetbounds cs2, ca0, 512
-; CHECK-NEXT:    csetbounds cs1, ca1, 88
+; CHECK-NEXT:    cincoffset a0, sp, 128
+; CHECK-NEXT:    cincoffset a1, sp, 40
+; CHECK-NEXT:    csetbounds s1, a0, 512
+; CHECK-NEXT:    csetbounds s2, a1, 88
 ; CHECK-NEXT:  .LBB0_1: # %for.body
 ; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT:    cmove ca0, cs2
-; CHECK-NEXT:    cmove ca1, cs1
+; CHECK-NEXT:    cmove a0, s1
+; CHECK-NEXT:    cmove a1, s2
 ; CHECK-NEXT:    ccall call
 ; CHECK-NEXT:    addi s3, s3, -1
 ; CHECK-NEXT:    bnez s3, .LBB0_1
 ; CHECK-NEXT:  # %bb.2: # %for.cond.cleanup
-; CHECK-NEXT:    cincoffset csp, cs0, -704
-; CHECK-NEXT:    clc cra, 696(csp) # 8-byte Folded Reload
-; CHECK-NEXT:    clc cs0, 688(csp) # 8-byte Folded Reload
-; CHECK-NEXT:    clc cs1, 680(csp) # 8-byte Folded Reload
-; CHECK-NEXT:    clc cs2, 672(csp) # 8-byte Folded Reload
-; CHECK-NEXT:    clc cs3, 664(csp) # 8-byte Folded Reload
-; CHECK-NEXT:    cincoffset csp, csp, 704
+; CHECK-NEXT:    cincoffset sp, s0, -704
+; CHECK-NEXT:    clc ra, 696(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    clc s0, 688(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    clc s1, 680(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    clc s2, 672(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    clc s3, 664(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    cincoffset sp, sp, 704
 ; CHECK-NEXT:    cret
 entry:
   %buf1 = alloca [123 x i32], align 4, addrspace(200)
@@ -110,22 +110,22 @@ declare void @call(i32 addrspace(200)*, i32 addrspace(200)*) local_unnamed_addr
 define void @hoist_alloca_cond(i32 signext %cond) local_unnamed_addr addrspace(200) nounwind {
 ; CHECK-LABEL: hoist_alloca_cond:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    cincoffset csp, csp, -704
-; CHECK-NEXT:    csc cra, 696(csp) # 8-byte Folded Spill
-; CHECK-NEXT:    csc cs0, 688(csp) # 8-byte Folded Spill
-; CHECK-NEXT:    csc cs1, 680(csp) # 8-byte Folded Spill
-; CHECK-NEXT:    csc cs2, 672(csp) # 8-byte Folded Spill
-; CHECK-NEXT:    csc cs3, 664(csp) # 8-byte Folded Spill
-; CHECK-NEXT:    csc cs4, 656(csp) # 8-byte Folded Spill
-; CHECK-NEXT:    cincoffset cs0, csp, 704
+; CHECK-NEXT:    cincoffset sp, sp, -704
+; CHECK-NEXT:    csc ra, 696(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    csc s0, 688(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    csc s1, 680(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    csc s2, 672(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    csc s3, 664(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    csc s4, 656(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    cincoffset s0, sp, 704
 ; CHECK-NEXT:    andi a1, sp, -64
-; CHECK-NEXT:    csetaddr csp, csp, a1
+; CHECK-NEXT:    csetaddr sp, sp, a1
 ; CHECK-NEXT:    mv s1, a0
 ; CHECK-NEXT:    li s4, 100
-; CHECK-NEXT:    cincoffset ca0, csp, 128
-; CHECK-NEXT:    cincoffset ca1, csp, 40
-; CHECK-NEXT:    csetbounds cs2, ca0, 512
-; CHECK-NEXT:    csetbounds cs3, ca1, 88
+; CHECK-NEXT:    cincoffset a0, sp, 128
+; CHECK-NEXT:    cincoffset a1, sp, 40
+; CHECK-NEXT:    csetbounds s2, a0, 512
+; CHECK-NEXT:    csetbounds s3, a1, 88
 ; CHECK-NEXT:    j .LBB1_2
 ; CHECK-NEXT:  .LBB1_1: # %for.inc
 ; CHECK-NEXT:    # in Loop: Header=BB1_2 Depth=1
@@ -136,19 +136,19 @@ define void @hoist_alloca_cond(i32 signext %cond) local_unnamed_addr addrspace(2
 ; CHECK-NEXT:    beqz s1, .LBB1_1
 ; CHECK-NEXT:  # %bb.3: # %if.then
 ; CHECK-NEXT:    # in Loop: Header=BB1_2 Depth=1
-; CHECK-NEXT:    cmove ca0, cs2
-; CHECK-NEXT:    cmove ca1, cs3
+; CHECK-NEXT:    cmove a0, s2
+; CHECK-NEXT:    cmove a1, s3
 ; CHECK-NEXT:    ccall call
 ; CHECK-NEXT:    j .LBB1_1
 ; CHECK-NEXT:  .LBB1_4: # %for.cond.cleanup
-; CHECK-NEXT:    cincoffset csp, cs0, -704
-; CHECK-NEXT:    clc cra, 696(csp) # 8-byte Folded Reload
-; CHECK-NEXT:    clc cs0, 688(csp) # 8-byte Folded Reload
-; CHECK-NEXT:    clc cs1, 680(csp) # 8-byte Folded Reload
-; CHECK-NEXT:    clc cs2, 672(csp) # 8-byte Folded Reload
-; CHECK-NEXT:    clc cs3, 664(csp) # 8-byte Folded Reload
-; CHECK-NEXT:    clc cs4, 656(csp) # 8-byte Folded Reload
-; CHECK-NEXT:    cincoffset csp, csp, 704
+; CHECK-NEXT:    cincoffset sp, s0, -704
+; CHECK-NEXT:    clc ra, 696(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    clc s0, 688(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    clc s1, 680(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    clc s2, 672(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    clc s3, 664(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    clc s4, 656(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    cincoffset sp, sp, 704
 ; CHECK-NEXT:    cret
 entry:
   %buf1 = alloca [123 x i32], align 4, addrspace(200)
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/intrinsics-purecap-only.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/intrinsics-purecap-only.ll
index fe560712d6bc1..d1b22cb2a2538 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/intrinsics-purecap-only.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/intrinsics-purecap-only.ll
@@ -10,7 +10,7 @@ declare i8 addrspace(200)* @llvm.cheri.stack.cap.get()
 define i8 addrspace(200)* @stack_get() nounwind {
 ; PURECAP-LABEL: stack_get:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    cmove ca0, csp
+; PURECAP-NEXT:    cmove a0, sp
 ; PURECAP-NEXT:    cret
   %cap = call i8 addrspace(200)* @llvm.cheri.stack.cap.get()
   ret i8 addrspace(200)* %cap
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/intrinsics.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/intrinsics.ll
index 35676e1311adc..be45aea185c76 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/intrinsics.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/intrinsics.ll
@@ -23,12 +23,12 @@ declare i32 @llvm.cheri.cap.high.get.i32(i8 addrspace(200)*)
 define i32 @perms_get(i8 addrspace(200)* %cap) nounwind {
 ; PURECAP-LABEL: perms_get:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    cgetperm a0, ca0
+; PURECAP-NEXT:    cgetperm a0, a0
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: perms_get:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    cgetperm a0, ca0
+; HYBRID-NEXT:    cgetperm a0, a0
 ; HYBRID-NEXT:    ret
   %perms = call i32 @llvm.cheri.cap.perms.get.i32(i8 addrspace(200)* %cap)
   ret i32 %perms
@@ -37,12 +37,12 @@ define i32 @perms_get(i8 addrspace(200)* %cap) nounwind {
 define i32 @type_get(i8 addrspace(200)* %cap) nounwind {
 ; PURECAP-LABEL: type_get:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    cgettype a0, ca0
+; PURECAP-NEXT:    cgettype a0, a0
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: type_get:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    cgettype a0, ca0
+; HYBRID-NEXT:    cgettype a0, a0
 ; HYBRID-NEXT:    ret
   %type = call i32 @llvm.cheri.cap.type.get.i32(i8 addrspace(200)* %cap)
   ret i32 %type
@@ -51,12 +51,12 @@ define i32 @type_get(i8 addrspace(200)* %cap) nounwind {
 define i32 @base_get(i8 addrspace(200)* %cap) nounwind {
 ; PURECAP-LABEL: base_get:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    cgetbase a0, ca0
+; PURECAP-NEXT:    cgetbase a0, a0
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: base_get:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    cgetbase a0, ca0
+; HYBRID-NEXT:    cgetbase a0, a0
 ; HYBRID-NEXT:    ret
   %base = call i32 @llvm.cheri.cap.base.get.i32(i8 addrspace(200)* %cap)
   ret i32 %base
@@ -65,12 +65,12 @@ define i32 @base_get(i8 addrspace(200)* %cap) nounwind {
 define i32 @length_get(i8 addrspace(200)* %cap) nounwind {
 ; PURECAP-LABEL: length_get:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    cgetlen a0, ca0
+; PURECAP-NEXT:    cgetlen a0, a0
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: length_get:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    cgetlen a0, ca0
+; HYBRID-NEXT:    cgetlen a0, a0
 ; HYBRID-NEXT:    ret
   %length = call i32 @llvm.cheri.cap.length.get.i32(i8 addrspace(200)* %cap)
   ret i32 %length
@@ -79,12 +79,12 @@ define i32 @length_get(i8 addrspace(200)* %cap) nounwind {
 define i32 @tag_get(i8 addrspace(200)* %cap) nounwind {
 ; PURECAP-LABEL: tag_get:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    cgettag a0, ca0
+; PURECAP-NEXT:    cgettag a0, a0
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: tag_get:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    cgettag a0, ca0
+; HYBRID-NEXT:    cgettag a0, a0
 ; HYBRID-NEXT:    ret
   %tag = call i1 @llvm.cheri.cap.tag.get(i8 addrspace(200)* %cap)
   %tag.zext = zext i1 %tag to i32
@@ -94,12 +94,12 @@ define i32 @tag_get(i8 addrspace(200)* %cap) nounwind {
 define i32 @tag_get_temporal(i8 addrspace(200)* %cap) nounwind {
 ; PURECAP-LABEL: tag_get_temporal:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    cgettag a0, ca0
+; PURECAP-NEXT:    cgettag a0, a0
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: tag_get_temporal:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    cgettag a0, ca0
+; HYBRID-NEXT:    cgettag a0, a0
 ; HYBRID-NEXT:    ret
   %tag = call i1 @llvm.cheri.cap.tag.get.temporal(i8 addrspace(200)* %cap)
   %tag.zext = zext i1 %tag to i32
@@ -110,12 +110,12 @@ define i32 @tag_get_temporal(i8 addrspace(200)* %cap) nounwind {
 define i32 @sealed_get(i8 addrspace(200)* %cap) nounwind {
 ; PURECAP-LABEL: sealed_get:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    cgetsealed a0, ca0
+; PURECAP-NEXT:    cgetsealed a0, a0
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: sealed_get:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    cgetsealed a0, ca0
+; HYBRID-NEXT:    cgetsealed a0, a0
 ; HYBRID-NEXT:    ret
   %sealed = call i1 @llvm.cheri.cap.sealed.get(i8 addrspace(200)* %cap)
   %sealed.zext = zext i1 %sealed to i32
@@ -125,12 +125,12 @@ define i32 @sealed_get(i8 addrspace(200)* %cap) nounwind {
 define i32 @offset_get(i8 addrspace(200)* %cap) nounwind {
 ; PURECAP-LABEL: offset_get:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    cgetoffset a0, ca0
+; PURECAP-NEXT:    cgetoffset a0, a0
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: offset_get:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    cgetoffset a0, ca0
+; HYBRID-NEXT:    cgetoffset a0, a0
 ; HYBRID-NEXT:    ret
   %offset = call i32 @llvm.cheri.cap.offset.get.i32(i8 addrspace(200)* %cap)
   ret i32 %offset
@@ -139,12 +139,12 @@ define i32 @offset_get(i8 addrspace(200)* %cap) nounwind {
 define i32 @flags_get(i8 addrspace(200)* %cap) nounwind {
 ; PURECAP-LABEL: flags_get:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    cgetflags a0, ca0
+; PURECAP-NEXT:    cgetflags a0, a0
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: flags_get:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    cgetflags a0, ca0
+; HYBRID-NEXT:    cgetflags a0, a0
 ; HYBRID-NEXT:    ret
   %flags = call i32 @llvm.cheri.cap.flags.get.i32(i8 addrspace(200)* %cap)
   ret i32 %flags
@@ -167,12 +167,12 @@ define i32 @address_get(i8 addrspace(200)* %cap) nounwind {
 define i32 @high_get(i8 addrspace(200)* %cap) nounwind {
 ; PURECAP-LABEL: high_get:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    cgethigh a0, ca0
+; PURECAP-NEXT:    cgethigh a0, a0
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: high_get:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    cgethigh a0, ca0
+; HYBRID-NEXT:    cgethigh a0, a0
 ; HYBRID-NEXT:    ret
   %high = call i32 @llvm.cheri.cap.high.get.i32(i8 addrspace(200)* %cap)
   ret i32 %high
@@ -198,12 +198,12 @@ declare i8 addrspace(200)* @llvm.cheri.cap.seal.entry(i8 addrspace(200)*)
 define i8 addrspace(200)* @seal(i8 addrspace(200)* %cap1, i8 addrspace(200)* %cap2) nounwind {
 ; PURECAP-LABEL: seal:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    cseal ca0, ca0, ca1
+; PURECAP-NEXT:    cseal a0, a0, a1
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: seal:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    cseal ca0, ca0, ca1
+; HYBRID-NEXT:    cseal a0, a0, a1
 ; HYBRID-NEXT:    ret
   %sealed = call i8 addrspace(200)* @llvm.cheri.cap.seal(i8 addrspace(200)* %cap1, i8 addrspace(200)* %cap2)
   ret i8 addrspace(200)* %sealed
@@ -212,12 +212,12 @@ define i8 addrspace(200)* @seal(i8 addrspace(200)* %cap1, i8 addrspace(200)* %ca
 define i8 addrspace(200)* @unseal(i8 addrspace(200)* %cap1, i8 addrspace(200)* %cap2) nounwind {
 ; PURECAP-LABEL: unseal:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    cunseal ca0, ca0, ca1
+; PURECAP-NEXT:    cunseal a0, a0, a1
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: unseal:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    cunseal ca0, ca0, ca1
+; HYBRID-NEXT:    cunseal a0, a0, a1
 ; HYBRID-NEXT:    ret
   %unsealed = call i8 addrspace(200)* @llvm.cheri.cap.unseal(i8 addrspace(200)* %cap1, i8 addrspace(200)* %cap2)
   ret i8 addrspace(200)* %unsealed
@@ -226,12 +226,12 @@ define i8 addrspace(200)* @unseal(i8 addrspace(200)* %cap1, i8 addrspace(200)* %
 define i8 addrspace(200)* @perms_and(i8 addrspace(200)* %cap, i32 %perms) nounwind {
 ; PURECAP-LABEL: perms_and:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    candperm ca0, ca0, a1
+; PURECAP-NEXT:    candperm a0, a0, a1
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: perms_and:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    candperm ca0, ca0, a1
+; HYBRID-NEXT:    candperm a0, a0, a1
 ; HYBRID-NEXT:    ret
   %newcap = call i8 addrspace(200)* @llvm.cheri.cap.perms.and.i32(i8 addrspace(200)* %cap, i32 %perms)
   ret i8 addrspace(200)* %newcap
@@ -240,12 +240,12 @@ define i8 addrspace(200)* @perms_and(i8 addrspace(200)* %cap, i32 %perms) nounwi
 define i8 addrspace(200)* @flags_set(i8 addrspace(200)* %cap, i32 %flags) nounwind {
 ; PURECAP-LABEL: flags_set:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    csetflags ca0, ca0, a1
+; PURECAP-NEXT:    csetflags a0, a0, a1
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: flags_set:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    csetflags ca0, ca0, a1
+; HYBRID-NEXT:    csetflags a0, a0, a1
 ; HYBRID-NEXT:    ret
   %newcap = call i8 addrspace(200)* @llvm.cheri.cap.flags.set.i32(i8 addrspace(200)* %cap, i32 %flags)
   ret i8 addrspace(200)* %newcap
@@ -254,12 +254,12 @@ define i8 addrspace(200)* @flags_set(i8 addrspace(200)* %cap, i32 %flags) nounwi
 define i8 addrspace(200)* @offset_set(i8 addrspace(200)* %cap, i32 %offset) nounwind {
 ; PURECAP-LABEL: offset_set:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    csetoffset ca0, ca0, a1
+; PURECAP-NEXT:    csetoffset a0, a0, a1
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: offset_set:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    csetoffset ca0, ca0, a1
+; HYBRID-NEXT:    csetoffset a0, a0, a1
 ; HYBRID-NEXT:    ret
   %newcap = call i8 addrspace(200)* @llvm.cheri.cap.offset.set.i32(i8 addrspace(200)* %cap, i32 %offset)
   ret i8 addrspace(200)* %newcap
@@ -268,12 +268,12 @@ define i8 addrspace(200)* @offset_set(i8 addrspace(200)* %cap, i32 %offset) noun
 define i8 addrspace(200)* @address_set(i8 addrspace(200)* %cap, i32 %address) nounwind {
 ; PURECAP-LABEL: address_set:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    csetaddr ca0, ca0, a1
+; PURECAP-NEXT:    csetaddr a0, a0, a1
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: address_set:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    csetaddr ca0, ca0, a1
+; HYBRID-NEXT:    csetaddr a0, a0, a1
 ; HYBRID-NEXT:    ret
   %newcap = call i8 addrspace(200)* @llvm.cheri.cap.address.set.i32(i8 addrspace(200)* %cap, i32 %address)
   ret i8 addrspace(200)* %newcap
@@ -282,12 +282,12 @@ define i8 addrspace(200)* @address_set(i8 addrspace(200)* %cap, i32 %address) no
 define i8 addrspace(200)* @bounds_set(i8 addrspace(200)* %cap, i32 %bounds) nounwind {
 ; PURECAP-LABEL: bounds_set:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    csetbounds ca0, ca0, a1
+; PURECAP-NEXT:    csetbounds a0, a0, a1
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: bounds_set:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    csetbounds ca0, ca0, a1
+; HYBRID-NEXT:    csetbounds a0, a0, a1
 ; HYBRID-NEXT:    ret
   %newcap = call i8 addrspace(200)* @llvm.cheri.cap.bounds.set.i32(i8 addrspace(200)* %cap, i32 %bounds)
   ret i8 addrspace(200)* %newcap
@@ -296,12 +296,12 @@ define i8 addrspace(200)* @bounds_set(i8 addrspace(200)* %cap, i32 %bounds) noun
 define i8 addrspace(200)* @bounds_set_exact(i8 addrspace(200)* %cap, i32 %bounds) nounwind {
 ; PURECAP-LABEL: bounds_set_exact:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    csetboundsexact ca0, ca0, a1
+; PURECAP-NEXT:    csetboundsexact a0, a0, a1
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: bounds_set_exact:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    csetboundsexact ca0, ca0, a1
+; HYBRID-NEXT:    csetboundsexact a0, a0, a1
 ; HYBRID-NEXT:    ret
   %newcap = call i8 addrspace(200)* @llvm.cheri.cap.bounds.set.exact.i32(i8 addrspace(200)* %cap, i32 %bounds)
   ret i8 addrspace(200)* %newcap
@@ -310,12 +310,12 @@ define i8 addrspace(200)* @bounds_set_exact(i8 addrspace(200)* %cap, i32 %bounds
 define i8 addrspace(200)* @high_set(i8 addrspace(200)* %cap, i32 %high) nounwind {
 ; PURECAP-LABEL: high_set:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    csethigh ca0, ca0, a1
+; PURECAP-NEXT:    csethigh a0, a0, a1
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: high_set:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    csethigh ca0, ca0, a1
+; HYBRID-NEXT:    csethigh a0, a0, a1
 ; HYBRID-NEXT:    ret
   %newcap = call i8 addrspace(200)* @llvm.cheri.cap.high.set.i32(i8 addrspace(200)* %cap, i32 %high)
   ret i8 addrspace(200)* %newcap
@@ -324,12 +324,12 @@ define i8 addrspace(200)* @high_set(i8 addrspace(200)* %cap, i32 %high) nounwind
 define i8 addrspace(200)* @bounds_set_immediate(i8 addrspace(200)* %cap) nounwind {
 ; PURECAP-LABEL: bounds_set_immediate:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    csetbounds ca0, ca0, 42
+; PURECAP-NEXT:    csetbounds a0, a0, 42
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: bounds_set_immediate:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    csetbounds ca0, ca0, 42
+; HYBRID-NEXT:    csetbounds a0, a0, 42
 ; HYBRID-NEXT:    ret
   %newcap = call i8 addrspace(200)* @llvm.cheri.cap.bounds.set.i32(i8 addrspace(200)* %cap, i32 42)
   ret i8 addrspace(200)* %newcap
@@ -338,12 +338,12 @@ define i8 addrspace(200)* @bounds_set_immediate(i8 addrspace(200)* %cap) nounwin
 define i8 addrspace(200)* @tag_clear(i8 addrspace(200)* %cap) nounwind {
 ; PURECAP-LABEL: tag_clear:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    ccleartag ca0, ca0
+; PURECAP-NEXT:    ccleartag a0, a0
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: tag_clear:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    ccleartag ca0, ca0
+; HYBRID-NEXT:    ccleartag a0, a0
 ; HYBRID-NEXT:    ret
   %untagged = call i8 addrspace(200)* @llvm.cheri.cap.tag.clear(i8 addrspace(200)* %cap)
   ret i8 addrspace(200)* %untagged
@@ -352,12 +352,12 @@ define i8 addrspace(200)* @tag_clear(i8 addrspace(200)* %cap) nounwind {
 define i8 addrspace(200)* @build(i8 addrspace(200)* %cap1, i8 addrspace(200)* %cap2) nounwind {
 ; PURECAP-LABEL: build:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    cbuildcap ca0, ca0, ca1
+; PURECAP-NEXT:    cbuildcap a0, a0, a1
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: build:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    cbuildcap ca0, ca0, ca1
+; HYBRID-NEXT:    cbuildcap a0, a0, a1
 ; HYBRID-NEXT:    ret
   %built = call i8 addrspace(200)* @llvm.cheri.cap.build(i8 addrspace(200)* %cap1, i8 addrspace(200)* %cap2)
   ret i8 addrspace(200)* %built
@@ -366,12 +366,12 @@ define i8 addrspace(200)* @build(i8 addrspace(200)* %cap1, i8 addrspace(200)* %c
 define i8 addrspace(200)* @type_copy(i8 addrspace(200)* %cap1, i8 addrspace(200)* %cap2) nounwind {
 ; PURECAP-LABEL: type_copy:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    ccopytype ca0, ca0, ca1
+; PURECAP-NEXT:    ccopytype a0, a0, a1
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: type_copy:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    ccopytype ca0, ca0, ca1
+; HYBRID-NEXT:    ccopytype a0, a0, a1
 ; HYBRID-NEXT:    ret
   %newcap = call i8 addrspace(200)* @llvm.cheri.cap.type.copy(i8 addrspace(200)* %cap1, i8 addrspace(200)* %cap2)
   ret i8 addrspace(200)* %newcap
@@ -380,12 +380,12 @@ define i8 addrspace(200)* @type_copy(i8 addrspace(200)* %cap1, i8 addrspace(200)
 define i8 addrspace(200)* @conditional_seal(i8 addrspace(200)* %cap1, i8 addrspace(200)* %cap2) nounwind {
 ; PURECAP-LABEL: conditional_seal:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    ccseal ca0, ca0, ca1
+; PURECAP-NEXT:    ccseal a0, a0, a1
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: conditional_seal:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    ccseal ca0, ca0, ca1
+; HYBRID-NEXT:    ccseal a0, a0, a1
 ; HYBRID-NEXT:    ret
   %newcap = call i8 addrspace(200)* @llvm.cheri.cap.conditional.seal(i8 addrspace(200)* %cap1, i8 addrspace(200)* %cap2)
   ret i8 addrspace(200)* %newcap
@@ -394,12 +394,12 @@ define i8 addrspace(200)* @conditional_seal(i8 addrspace(200)* %cap1, i8 addrspa
 define i8 addrspace(200)* @seal_entry(i8 addrspace(200)* %cap) nounwind {
 ; PURECAP-LABEL: seal_entry:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    csealentry ca0, ca0
+; PURECAP-NEXT:    csealentry a0, a0
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: seal_entry:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    csealentry ca0, ca0
+; HYBRID-NEXT:    csealentry a0, a0
 ; HYBRID-NEXT:    ret
   %newcap = call i8 addrspace(200)* @llvm.cheri.cap.seal.entry(i8 addrspace(200)* %cap)
   ret i8 addrspace(200)* %newcap
@@ -416,14 +416,14 @@ declare i8 addrspace(200)* @llvm.cheri.pcc.get()
 define i32 @to_pointer(i8 addrspace(200)* %cap1, i8 addrspace(200)* %cap2) nounwind {
 ; PURECAP-LABEL: to_pointer:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    cgettag a0, ca1
+; PURECAP-NEXT:    cgettag a0, a1
 ; PURECAP-NEXT:    neg a0, a0
 ; PURECAP-NEXT:    and a0, a1, a0
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: to_pointer:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    cgettag a0, ca1
+; HYBRID-NEXT:    cgettag a0, a1
 ; HYBRID-NEXT:    neg a0, a0
 ; HYBRID-NEXT:    and a0, a1, a0
 ; HYBRID-NEXT:    ret
@@ -434,14 +434,14 @@ define i32 @to_pointer(i8 addrspace(200)* %cap1, i8 addrspace(200)* %cap2) nounw
 define i32 @to_pointer_ddc_relative(i8 addrspace(200)* %cap) nounwind {
 ; PURECAP-LABEL: to_pointer_ddc_relative:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    cgettag a1, ca0
+; PURECAP-NEXT:    cgettag a1, a0
 ; PURECAP-NEXT:    neg a1, a1
 ; PURECAP-NEXT:    and a0, a0, a1
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: to_pointer_ddc_relative:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    cgettag a1, ca0
+; HYBRID-NEXT:    cgettag a1, a0
 ; HYBRID-NEXT:    neg a1, a1
 ; HYBRID-NEXT:    and a0, a0, a1
 ; HYBRID-NEXT:    ret
@@ -455,20 +455,20 @@ define i8 addrspace(200)* @from_pointer(i8 addrspace(200)* %cap, i32 %ptr) nounw
 ; PURECAP:       # %bb.0:
 ; PURECAP-NEXT:    bnez a1, .LBB28_2
 ; PURECAP-NEXT:  # %bb.1:
-; PURECAP-NEXT:    cmove ca0, cnull
+; PURECAP-NEXT:    cmove a0, zero
 ; PURECAP-NEXT:    cret
 ; PURECAP-NEXT:  .LBB28_2:
-; PURECAP-NEXT:    csetaddr ca0, ca0, a1
+; PURECAP-NEXT:    csetaddr a0, a0, a1
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: from_pointer:
 ; HYBRID:       # %bb.0:
 ; HYBRID-NEXT:    bnez a1, .LBB28_2
 ; HYBRID-NEXT:  # %bb.1:
-; HYBRID-NEXT:    cmove ca0, cnull
+; HYBRID-NEXT:    cmove a0, zero
 ; HYBRID-NEXT:    ret
 ; HYBRID-NEXT:  .LBB28_2:
-; HYBRID-NEXT:    csetaddr ca0, ca0, a1
+; HYBRID-NEXT:    csetaddr a0, a0, a1
 ; HYBRID-NEXT:    ret
   %newcap = call i8 addrspace(200)* @llvm.cheri.cap.from.pointer(i8 addrspace(200)* %cap, i32 %ptr)
   ret i8 addrspace(200)* %newcap
@@ -477,24 +477,24 @@ define i8 addrspace(200)* @from_pointer(i8 addrspace(200)* %cap, i32 %ptr) nounw
 define i8 addrspace(200)* @from_ddc(i32 %ptr) nounwind {
 ; PURECAP-LABEL: from_ddc:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    cspecialr ca1, ddc
+; PURECAP-NEXT:    cspecialr a1, ddc
 ; PURECAP-NEXT:    bnez a0, .LBB29_2
 ; PURECAP-NEXT:  # %bb.1:
-; PURECAP-NEXT:    cmove ca0, cnull
+; PURECAP-NEXT:    cmove a0, zero
 ; PURECAP-NEXT:    cret
 ; PURECAP-NEXT:  .LBB29_2:
-; PURECAP-NEXT:    csetaddr ca0, ca1, a0
+; PURECAP-NEXT:    csetaddr a0, a1, a0
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: from_ddc:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    cspecialr ca1, ddc
+; HYBRID-NEXT:    cspecialr a1, ddc
 ; HYBRID-NEXT:    bnez a0, .LBB29_2
 ; HYBRID-NEXT:  # %bb.1:
-; HYBRID-NEXT:    cmove ca0, cnull
+; HYBRID-NEXT:    cmove a0, zero
 ; HYBRID-NEXT:    ret
 ; HYBRID-NEXT:  .LBB29_2:
-; HYBRID-NEXT:    csetaddr ca0, ca1, a0
+; HYBRID-NEXT:    csetaddr a0, a1, a0
 ; HYBRID-NEXT:    ret
   %ddc = call i8 addrspace(200)* @llvm.cheri.ddc.get()
   %cap = call i8 addrspace(200)* @llvm.cheri.cap.from.pointer(i8 addrspace(200)* %ddc, i32 %ptr)
@@ -518,12 +518,12 @@ define i32 @diff(i8 addrspace(200)* %cap1, i8 addrspace(200)* %cap2) nounwind {
 define i8 addrspace(200)* @ddc_get() nounwind {
 ; PURECAP-LABEL: ddc_get:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    cspecialr ca0, ddc
+; PURECAP-NEXT:    cspecialr a0, ddc
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: ddc_get:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    cspecialr ca0, ddc
+; HYBRID-NEXT:    cspecialr a0, ddc
 ; HYBRID-NEXT:    ret
   %cap = call i8 addrspace(200)* @llvm.cheri.ddc.get()
   ret i8 addrspace(200)* %cap
@@ -532,12 +532,12 @@ define i8 addrspace(200)* @ddc_get() nounwind {
 define i8 addrspace(200)* @pcc_get() nounwind {
 ; PURECAP-LABEL: pcc_get:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    auipcc ca0, 0
+; PURECAP-NEXT:    auipcc a0, 0
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: pcc_get:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    cspecialr ca0, pcc
+; HYBRID-NEXT:    cspecialr a0, pcc
 ; HYBRID-NEXT:    ret
   %cap = call i8 addrspace(200)* @llvm.cheri.pcc.get()
   ret i8 addrspace(200)* %cap
@@ -550,12 +550,12 @@ declare i1 @llvm.cheri.cap.subset.test(i8 addrspace(200)* %cap1, i8 addrspace(20
 define i32 @subset_test(i8 addrspace(200)* %cap1, i8 addrspace(200)* %cap2) nounwind {
 ; PURECAP-LABEL: subset_test:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    ctestsubset a0, ca0, ca1
+; PURECAP-NEXT:    ctestsubset a0, a0, a1
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: subset_test:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    ctestsubset a0, ca0, ca1
+; HYBRID-NEXT:    ctestsubset a0, a0, a1
 ; HYBRID-NEXT:    ret
   %subset = call i1 @llvm.cheri.cap.subset.test(i8 addrspace(200)* %cap1, i8 addrspace(200)* %cap2)
   %subset.zext = zext i1 %subset to i32
@@ -567,12 +567,12 @@ declare i1 @llvm.cheri.cap.equal.exact(i8 addrspace(200)* %cap1, i8 addrspace(20
 define i32 @equal_exact(i8 addrspace(200)* %cap1, i8 addrspace(200)* %cap2) nounwind {
 ; PURECAP-LABEL: equal_exact:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    cseqx a0, ca0, ca1
+; PURECAP-NEXT:    cseqx a0, a0, a1
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: equal_exact:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    cseqx a0, ca0, ca1
+; HYBRID-NEXT:    cseqx a0, a0, a1
 ; HYBRID-NEXT:    ret
   %eqex = call i1 @llvm.cheri.cap.equal.exact(i8 addrspace(200)* %cap1, i8 addrspace(200)* %cap2)
   %eqex.zext = zext i1 %eqex to i32
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/landingpad-non-preemptible.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/landingpad-non-preemptible.ll
index 821b845c73ddf..afcf07abbc15c 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/landingpad-non-preemptible.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/landingpad-non-preemptible.ll
@@ -21,10 +21,10 @@
 define dso_local noundef signext i32 @_Z8do_catchv() local_unnamed_addr addrspace(200) #0 personality ptr addrspace(200) @__gxx_personality_v0 {
 ; CHECK-LABEL: _Z8do_catchv:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    cincoffset csp, csp, -16
+; CHECK-NEXT:    cincoffset sp, sp, -16
 ; CHECK-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; CHECK-NEXT:    csc cs0, 0(csp) # 8-byte Folded Spill
+; CHECK-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    csc s0, 0(sp) # 8-byte Folded Spill
 ; CHECK-NEXT:    .cfi_offset ra, -8
 ; CHECK-NEXT:    .cfi_offset s0, -16
 ; CHECK-NEXT:    .cfi_remember_state
@@ -32,11 +32,11 @@ define dso_local noundef signext i32 @_Z8do_catchv() local_unnamed_addr addrspac
 ; CHECK-NEXT:    ccall _Z3foov
 ; CHECK-NEXT:  .Ltmp1:
 ; CHECK-NEXT:  .LBB0_1: # %return
-; CHECK-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; CHECK-NEXT:    clc cs0, 0(csp) # 8-byte Folded Reload
+; CHECK-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    clc s0, 0(sp) # 8-byte Folded Reload
 ; CHECK-NEXT:    .cfi_restore ra
 ; CHECK-NEXT:    .cfi_restore s0
-; CHECK-NEXT:    cincoffset csp, csp, 16
+; CHECK-NEXT:    cincoffset sp, sp, 16
 ; CHECK-NEXT:    .cfi_def_cfa_offset 0
 ; CHECK-NEXT:    cret
 ; CHECK-NEXT:  .LBB0_2: # %lpad
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/machinelicm-hoist-csetbounds.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/machinelicm-hoist-csetbounds.ll
index 62fba6134d3a8..91d5ac35d7cc3 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/machinelicm-hoist-csetbounds.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/machinelicm-hoist-csetbounds.ll
@@ -32,19 +32,19 @@ declare ptr addrspace(200) @llvm.cheri.cap.bounds.set.i32(ptr addrspace(200), i3
 define dso_local void @hoist_csetbounds(i32 signext %cond, ptr addrspace(200) %f) local_unnamed_addr addrspace(200) nounwind {
 ; CHECK-LABEL: hoist_csetbounds:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    cincoffset csp, csp, -48
-; CHECK-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; CHECK-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; CHECK-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; CHECK-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; CHECK-NEXT:    csc cs3, 8(csp) # 8-byte Folded Spill
-; CHECK-NEXT:    csc cs4, 0(csp) # 8-byte Folded Spill
-; CHECK-NEXT:    cmove cs0, ca1
-; CHECK-NEXT:    cincoffset ca0, ca1, 4
+; CHECK-NEXT:    cincoffset sp, sp, -48
+; CHECK-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    csc s3, 8(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    csc s4, 0(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    cmove s0, a1
+; CHECK-NEXT:    cincoffset a0, a1, 4
 ; CHECK-NEXT:    li s3, -1
 ; CHECK-NEXT:    li s4, 99
-; CHECK-NEXT:    csetbounds cs2, ca1, 4
-; CHECK-NEXT:    csetbounds cs1, ca0, 4
+; CHECK-NEXT:    csetbounds s1, a1, 4
+; CHECK-NEXT:    csetbounds s2, a0, 4
 ; CHECK-NEXT:    j .LBB0_2
 ; CHECK-NEXT:  .LBB0_1: # %for.inc
 ; CHECK-NEXT:    # in Loop: Header=BB0_2 Depth=1
@@ -55,18 +55,18 @@ define dso_local void @hoist_csetbounds(i32 signext %cond, ptr addrspace(200) %f
 ; CHECK-NEXT:    beqz s0, .LBB0_1
 ; CHECK-NEXT:  # %bb.3: # %if.then
 ; CHECK-NEXT:    # in Loop: Header=BB0_2 Depth=1
-; CHECK-NEXT:    cmove ca0, cs2
-; CHECK-NEXT:    cmove ca1, cs1
+; CHECK-NEXT:    cmove a0, s1
+; CHECK-NEXT:    cmove a1, s2
 ; CHECK-NEXT:    ccall call
 ; CHECK-NEXT:    j .LBB0_1
 ; CHECK-NEXT:  .LBB0_4: # %for.cond.cleanup
-; CHECK-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; CHECK-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; CHECK-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; CHECK-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; CHECK-NEXT:    clc cs3, 8(csp) # 8-byte Folded Reload
-; CHECK-NEXT:    clc cs4, 0(csp) # 8-byte Folded Reload
-; CHECK-NEXT:    cincoffset csp, csp, 48
+; CHECK-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    clc s3, 8(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    clc s4, 0(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    cincoffset sp, sp, 48
 ; CHECK-NEXT:    cret
 ; HOIST-OPT-LABEL: define dso_local void @hoist_csetbounds
 ; HOIST-OPT-SAME: (i32 signext [[COND:%.*]], ptr addrspace(200) [[F:%.*]]) local_unnamed_addr addrspace(200) #[[ATTR0:[0-9]+]] {
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/memcpy-from-constant.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/memcpy-from-constant.ll
index 9c49cca9353f5..0e5268d6da6ec 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/memcpy-from-constant.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/memcpy-from-constant.ll
@@ -13,7 +13,7 @@ declare void @llvm.memcpy.p200.p200.i64(ptr addrspace(200) noalias nocapture wri
 define linkonce_odr void @copy_from_zero_constant(ptr addrspace(200) %dst) addrspace(200) {
 ; CHECK-LABEL: copy_from_zero_constant:
 ; CHECK:       # %bb.0: # %do.body
-; CHECK-NEXT:    csc cnull, 0(ca0)
+; CHECK-NEXT:    csc zero, 0(a0)
 ; CHECK-NEXT:    cret
 do.body:
   call void @llvm.memcpy.p200.p200.i64(ptr addrspace(200) align 8 %dst, ptr addrspace(200) align 8 @zero_constant, i64 8, i1 false)
@@ -23,7 +23,7 @@ do.body:
 define linkonce_odr void @copy_from_zero_constant_with_offset(ptr addrspace(200) %dst) addrspace(200) {
 ; CHECK-LABEL: copy_from_zero_constant_with_offset:
 ; CHECK:       # %bb.0: # %do.body
-; CHECK-NEXT:    csc cnull, 0(ca0)
+; CHECK-NEXT:    csc zero, 0(a0)
 ; CHECK-NEXT:    cret
 do.body:
   %src = getelementptr inbounds i8, ptr addrspace(200) @zero_constant, i64 8
@@ -34,7 +34,7 @@ do.body:
 define linkonce_odr void @copy_from_large_zero_constant(ptr addrspace(200) %dst) addrspace(200) {
 ; CHECK-LABEL: copy_from_large_zero_constant:
 ; CHECK:       # %bb.0: # %do.body
-; CHECK-NEXT:    csw zero, 0(ca0)
+; CHECK-NEXT:    csw zero, 0(a0)
 ; CHECK-NEXT:    cret
 do.body:
   call void @llvm.memcpy.p200.p200.i64(ptr addrspace(200) align 8 %dst, ptr addrspace(200) align 8 @zero_constant, i64 4, i1 false)
@@ -46,10 +46,10 @@ define linkonce_odr void @copy_from_ptr_constant(ptr addrspace(200) %dst) addrsp
 ; CHECK:       # %bb.0: # %do.body
 ; CHECK-NEXT:  .LBB3_1: # %do.body
 ; CHECK-NEXT:    # Label of block must be emitted
-; CHECK-NEXT:    auipcc ca1, %captab_pcrel_hi(constant_ptrs)
-; CHECK-NEXT:    clc ca1, %pcrel_lo(.LBB3_1)(ca1)
-; CHECK-NEXT:    clc ca1, 0(ca1)
-; CHECK-NEXT:    csc ca1, 0(ca0)
+; CHECK-NEXT:    auipcc a1, %captab_pcrel_hi(constant_ptrs)
+; CHECK-NEXT:    clc a1, %pcrel_lo(.LBB3_1)(a1)
+; CHECK-NEXT:    clc a1, 0(a1)
+; CHECK-NEXT:    csc a1, 0(a0)
 ; CHECK-NEXT:    cret
 do.body:
   call void @llvm.memcpy.p200.p200.i64(ptr addrspace(200) align 8 %dst, ptr addrspace(200) align 8 @constant_ptrs, i64 8, i1 false)
@@ -61,10 +61,10 @@ define linkonce_odr void @copy_from_ptr_constant_with_offset(ptr addrspace(200)
 ; CHECK:       # %bb.0: # %do.body
 ; CHECK-NEXT:  .LBB4_1: # %do.body
 ; CHECK-NEXT:    # Label of block must be emitted
-; CHECK-NEXT:    auipcc ca1, %captab_pcrel_hi(constant_ptrs)
-; CHECK-NEXT:    clc ca1, %pcrel_lo(.LBB4_1)(ca1)
-; CHECK-NEXT:    clc ca1, 8(ca1)
-; CHECK-NEXT:    csc ca1, 0(ca0)
+; CHECK-NEXT:    auipcc a1, %captab_pcrel_hi(constant_ptrs)
+; CHECK-NEXT:    clc a1, %pcrel_lo(.LBB4_1)(a1)
+; CHECK-NEXT:    clc a1, 8(a1)
+; CHECK-NEXT:    csc a1, 0(a0)
 ; CHECK-NEXT:    cret
 do.body:
   %src = getelementptr inbounds i8, ptr addrspace(200) @constant_ptrs, i64 8
@@ -77,7 +77,7 @@ do.body:
 define linkonce_odr void @copy_from_zero_constant_preserve(ptr addrspace(200) %dst) addrspace(200) {
 ; CHECK-LABEL: copy_from_zero_constant_preserve:
 ; CHECK:       # %bb.0: # %do.body
-; CHECK-NEXT:    csc cnull, 0(ca0)
+; CHECK-NEXT:    csc zero, 0(a0)
 ; CHECK-NEXT:    cret
 do.body:
   call void @llvm.memcpy.p200.p200.i64(ptr addrspace(200) align 8 %dst, ptr addrspace(200) align 8 @zero_constant, i64 8, i1 false) #1
@@ -87,7 +87,7 @@ do.body:
 define linkonce_odr void @copy_from_zero_constant_with_offset_preserve(ptr addrspace(200) %dst) addrspace(200) {
 ; CHECK-LABEL: copy_from_zero_constant_with_offset_preserve:
 ; CHECK:       # %bb.0: # %do.body
-; CHECK-NEXT:    csc cnull, 0(ca0)
+; CHECK-NEXT:    csc zero, 0(a0)
 ; CHECK-NEXT:    cret
 do.body:
   %src = getelementptr inbounds i8, ptr addrspace(200) @zero_constant, i64 8
@@ -98,7 +98,7 @@ do.body:
 define linkonce_odr void @copy_from_large_zero_constant_preserve(ptr addrspace(200) %dst) addrspace(200) {
 ; CHECK-LABEL: copy_from_large_zero_constant_preserve:
 ; CHECK:       # %bb.0: # %do.body
-; CHECK-NEXT:    csw zero, 0(ca0)
+; CHECK-NEXT:    csw zero, 0(a0)
 ; CHECK-NEXT:    cret
 do.body:
   call void @llvm.memcpy.p200.p200.i64(ptr addrspace(200) align 8 %dst, ptr addrspace(200) align 8 @zero_constant, i64 4, i1 false) #1
@@ -110,10 +110,10 @@ define linkonce_odr void @copy_from_ptr_constant_preserve(ptr addrspace(200) %ds
 ; CHECK:       # %bb.0: # %do.body
 ; CHECK-NEXT:  .LBB8_1: # %do.body
 ; CHECK-NEXT:    # Label of block must be emitted
-; CHECK-NEXT:    auipcc ca1, %captab_pcrel_hi(constant_ptrs)
-; CHECK-NEXT:    clc ca1, %pcrel_lo(.LBB8_1)(ca1)
-; CHECK-NEXT:    clc ca1, 0(ca1)
-; CHECK-NEXT:    csc ca1, 0(ca0)
+; CHECK-NEXT:    auipcc a1, %captab_pcrel_hi(constant_ptrs)
+; CHECK-NEXT:    clc a1, %pcrel_lo(.LBB8_1)(a1)
+; CHECK-NEXT:    clc a1, 0(a1)
+; CHECK-NEXT:    csc a1, 0(a0)
 ; CHECK-NEXT:    cret
 do.body:
   call void @llvm.memcpy.p200.p200.i64(ptr addrspace(200) align 8 %dst, ptr addrspace(200) align 8 @constant_ptrs, i64 8, i1 false) #1
@@ -125,10 +125,10 @@ define linkonce_odr void @copy_from_ptr_constant_with_offset_preserve(ptr addrsp
 ; CHECK:       # %bb.0: # %do.body
 ; CHECK-NEXT:  .LBB9_1: # %do.body
 ; CHECK-NEXT:    # Label of block must be emitted
-; CHECK-NEXT:    auipcc ca1, %captab_pcrel_hi(constant_ptrs)
-; CHECK-NEXT:    clc ca1, %pcrel_lo(.LBB9_1)(ca1)
-; CHECK-NEXT:    clc ca1, 8(ca1)
-; CHECK-NEXT:    csc ca1, 0(ca0)
+; CHECK-NEXT:    auipcc a1, %captab_pcrel_hi(constant_ptrs)
+; CHECK-NEXT:    clc a1, %pcrel_lo(.LBB9_1)(a1)
+; CHECK-NEXT:    clc a1, 8(a1)
+; CHECK-NEXT:    csc a1, 0(a0)
 ; CHECK-NEXT:    cret
 do.body:
   %src = getelementptr inbounds i8, ptr addrspace(200) @constant_ptrs, i64 8
@@ -142,8 +142,8 @@ do.body:
 define linkonce_odr void @copy_from_underaligned_zero_constant(ptr addrspace(200) %dst) addrspace(200) {
 ; CHECK-LABEL: copy_from_underaligned_zero_constant:
 ; CHECK:       # %bb.0: # %do.body
-; CHECK-NEXT:    csw zero, 4(ca0)
-; CHECK-NEXT:    csw zero, 0(ca0)
+; CHECK-NEXT:    csw zero, 4(a0)
+; CHECK-NEXT:    csw zero, 0(a0)
 ; CHECK-NEXT:    cret
 do.body:
   call void @llvm.memcpy.p200.p200.i64(ptr addrspace(200) align 4 %dst, ptr addrspace(200) align 4 @zero_constant, i64 8, i1 false) #1
@@ -153,8 +153,8 @@ do.body:
 define linkonce_odr void @copy_from_underaligned_zero_constant_preserve(ptr addrspace(200) %dst) addrspace(200) {
 ; CHECK-LABEL: copy_from_underaligned_zero_constant_preserve:
 ; CHECK:       # %bb.0: # %do.body
-; CHECK-NEXT:    csw zero, 4(ca0)
-; CHECK-NEXT:    csw zero, 0(ca0)
+; CHECK-NEXT:    csw zero, 4(a0)
+; CHECK-NEXT:    csw zero, 0(a0)
 ; CHECK-NEXT:    cret
 do.body:
   call void @llvm.memcpy.p200.p200.i64(ptr addrspace(200) align 4 %dst, ptr addrspace(200) align 4 @zero_constant, i64 8, i1 false) #1
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/memcpy-no-preserve-tags-attr.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/memcpy-no-preserve-tags-attr.ll
index 38d3fe7cd6b00..d79bbce8d28dc 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/memcpy-no-preserve-tags-attr.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/memcpy-no-preserve-tags-attr.ll
@@ -15,13 +15,13 @@ declare void @llvm.memmove.p200i8.p200i8.i64(i8 addrspace(200)* nocapture writeo
 define void @memcpy_no_attr(%struct.pair addrspace(200)* %a, %struct.pair addrspace(200)* %b) addrspace(200) nounwind {
 ; CHECK-LABEL: memcpy_no_attr:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    cincoffset csp, csp, -16
-; CHECK-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; CHECK-NEXT:    cincoffset sp, sp, -16
+; CHECK-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; CHECK-NEXT:    li a2, 16
 ; CHECK-NEXT:    li a3, 0
 ; CHECK-NEXT:    ccall memcpy
-; CHECK-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; CHECK-NEXT:    cincoffset csp, csp, 16
+; CHECK-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    cincoffset sp, sp, 16
 ; CHECK-NEXT:    cret
 entry:
   %a_i8 = bitcast %struct.pair addrspace(200)* %a to i8 addrspace(200)*
@@ -33,13 +33,13 @@ entry:
 define void @memmove_no_attr(%struct.pair addrspace(200)* %a, %struct.pair addrspace(200)* %b) addrspace(200) nounwind {
 ; CHECK-LABEL: memmove_no_attr:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    cincoffset csp, csp, -16
-; CHECK-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; CHECK-NEXT:    cincoffset sp, sp, -16
+; CHECK-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; CHECK-NEXT:    li a2, 16
 ; CHECK-NEXT:    li a3, 0
 ; CHECK-NEXT:    ccall memmove
-; CHECK-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; CHECK-NEXT:    cincoffset csp, csp, 16
+; CHECK-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    cincoffset sp, sp, 16
 ; CHECK-NEXT:    cret
 entry:
   %a_i8 = bitcast %struct.pair addrspace(200)* %a to i8 addrspace(200)*
@@ -52,13 +52,13 @@ entry:
 define void @memcpy_must_preserve(%struct.pair addrspace(200)* %a, %struct.pair addrspace(200)* %b) addrspace(200) nounwind {
 ; CHECK-LABEL: memcpy_must_preserve:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    cincoffset csp, csp, -16
-; CHECK-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; CHECK-NEXT:    cincoffset sp, sp, -16
+; CHECK-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; CHECK-NEXT:    li a2, 16
 ; CHECK-NEXT:    li a3, 0
 ; CHECK-NEXT:    ccall memcpy
-; CHECK-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; CHECK-NEXT:    cincoffset csp, csp, 16
+; CHECK-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    cincoffset sp, sp, 16
 ; CHECK-NEXT:    cret
 entry:
   %a_i8 = bitcast %struct.pair addrspace(200)* %a to i8 addrspace(200)*
@@ -70,13 +70,13 @@ entry:
 define void @memmove_must_preserve(%struct.pair addrspace(200)* %a, %struct.pair addrspace(200)* %b) addrspace(200) nounwind {
 ; CHECK-LABEL: memmove_must_preserve:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    cincoffset csp, csp, -16
-; CHECK-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; CHECK-NEXT:    cincoffset sp, sp, -16
+; CHECK-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; CHECK-NEXT:    li a2, 16
 ; CHECK-NEXT:    li a3, 0
 ; CHECK-NEXT:    ccall memmove
-; CHECK-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; CHECK-NEXT:    cincoffset csp, csp, 16
+; CHECK-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    cincoffset sp, sp, 16
 ; CHECK-NEXT:    cret
 entry:
   %a_i8 = bitcast %struct.pair addrspace(200)* %a to i8 addrspace(200)*
@@ -89,14 +89,14 @@ entry:
 define void @memcpy_no_preserve(%struct.pair addrspace(200)* %a, %struct.pair addrspace(200)* %b) addrspace(200) nounwind {
 ; CHECK-LABEL: memcpy_no_preserve:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    clw a2, 12(ca1)
-; CHECK-NEXT:    csw a2, 12(ca0)
-; CHECK-NEXT:    clw a2, 8(ca1)
-; CHECK-NEXT:    csw a2, 8(ca0)
-; CHECK-NEXT:    clw a2, 4(ca1)
-; CHECK-NEXT:    csw a2, 4(ca0)
-; CHECK-NEXT:    clw a1, 0(ca1)
-; CHECK-NEXT:    csw a1, 0(ca0)
+; CHECK-NEXT:    clw a2, 12(a1)
+; CHECK-NEXT:    csw a2, 12(a0)
+; CHECK-NEXT:    clw a2, 8(a1)
+; CHECK-NEXT:    csw a2, 8(a0)
+; CHECK-NEXT:    clw a2, 4(a1)
+; CHECK-NEXT:    csw a2, 4(a0)
+; CHECK-NEXT:    clw a1, 0(a1)
+; CHECK-NEXT:    csw a1, 0(a0)
 ; CHECK-NEXT:    cret
 entry:
   %a_i8 = bitcast %struct.pair addrspace(200)* %a to i8 addrspace(200)*
@@ -108,14 +108,14 @@ entry:
 define void @memmove_no_preserve(%struct.pair addrspace(200)* %a, %struct.pair addrspace(200)* %b) addrspace(200) nounwind {
 ; CHECK-LABEL: memmove_no_preserve:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    clw a2, 12(ca1)
-; CHECK-NEXT:    clw a3, 8(ca1)
-; CHECK-NEXT:    clw a4, 4(ca1)
-; CHECK-NEXT:    clw a1, 0(ca1)
-; CHECK-NEXT:    csw a2, 12(ca0)
-; CHECK-NEXT:    csw a3, 8(ca0)
-; CHECK-NEXT:    csw a4, 4(ca0)
-; CHECK-NEXT:    csw a1, 0(ca0)
+; CHECK-NEXT:    clw a2, 12(a1)
+; CHECK-NEXT:    clw a3, 8(a1)
+; CHECK-NEXT:    clw a4, 4(a1)
+; CHECK-NEXT:    clw a1, 0(a1)
+; CHECK-NEXT:    csw a2, 12(a0)
+; CHECK-NEXT:    csw a3, 8(a0)
+; CHECK-NEXT:    csw a4, 4(a0)
+; CHECK-NEXT:    csw a1, 0(a0)
 ; CHECK-NEXT:    cret
 entry:
   %a_i8 = bitcast %struct.pair addrspace(200)* %a to i8 addrspace(200)*
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/memcpy-preserve-tags-assume-aligned.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/memcpy-preserve-tags-assume-aligned.ll
index a84f0746ab029..91c01536e7321 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/memcpy-preserve-tags-assume-aligned.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/memcpy-preserve-tags-assume-aligned.ll
@@ -12,14 +12,14 @@ declare void @llvm.assume(i1) addrspace(200)
 define void @memcpy_assume(i8 addrspace(200)* addrspace(200)* %local_cap_ptr, i8 addrspace(200)* %align1) addrspace(200) nounwind {
 ; CHECK-LABEL: memcpy_assume:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    clc ca2, 24(ca0)
-; CHECK-NEXT:    csc ca2, 24(ca1)
-; CHECK-NEXT:    clc ca2, 16(ca0)
-; CHECK-NEXT:    csc ca2, 16(ca1)
-; CHECK-NEXT:    clc ca2, 8(ca0)
-; CHECK-NEXT:    csc ca2, 8(ca1)
-; CHECK-NEXT:    clc ca0, 0(ca0)
-; CHECK-NEXT:    csc ca0, 0(ca1)
+; CHECK-NEXT:    clc a2, 24(a0)
+; CHECK-NEXT:    csc a2, 24(a1)
+; CHECK-NEXT:    clc a2, 16(a0)
+; CHECK-NEXT:    csc a2, 16(a1)
+; CHECK-NEXT:    clc a2, 8(a0)
+; CHECK-NEXT:    csc a2, 8(a1)
+; CHECK-NEXT:    clc a0, 0(a0)
+; CHECK-NEXT:    csc a0, 0(a1)
 ; CHECK-NEXT:    cret
   %ptrint = ptrtoint i8 addrspace(200)* %align1 to i32
   %maskedptr = and i32 %ptrint, 15
@@ -33,14 +33,14 @@ define void @memcpy_assume(i8 addrspace(200)* addrspace(200)* %local_cap_ptr, i8
 define void @memmove_assume(i8 addrspace(200)* addrspace(200)* %local_cap_ptr, i8 addrspace(200)* %align1) addrspace(200) nounwind {
 ; CHECK-LABEL: memmove_assume:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    clc ca2, 0(ca0)
-; CHECK-NEXT:    clc ca3, 16(ca0)
-; CHECK-NEXT:    csc ca2, 0(ca1)
-; CHECK-NEXT:    clc ca2, 8(ca0)
-; CHECK-NEXT:    clc ca0, 24(ca0)
-; CHECK-NEXT:    csc ca3, 16(ca1)
-; CHECK-NEXT:    csc ca2, 8(ca1)
-; CHECK-NEXT:    csc ca0, 24(ca1)
+; CHECK-NEXT:    clc a2, 0(a0)
+; CHECK-NEXT:    clc a3, 16(a0)
+; CHECK-NEXT:    csc a2, 0(a1)
+; CHECK-NEXT:    clc a2, 8(a0)
+; CHECK-NEXT:    clc a0, 24(a0)
+; CHECK-NEXT:    csc a3, 16(a1)
+; CHECK-NEXT:    csc a2, 8(a1)
+; CHECK-NEXT:    csc a0, 24(a1)
 ; CHECK-NEXT:    cret
   %ptrint = ptrtoint i8 addrspace(200)* %align1 to i32
   %maskedptr = and i32 %ptrint, 15
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/memcpy-preserve-tags-size-not-multiple.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/memcpy-preserve-tags-size-not-multiple.ll
index 68d0978f39722..15e655b5e93f1 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/memcpy-preserve-tags-size-not-multiple.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/memcpy-preserve-tags-size-not-multiple.ll
@@ -11,22 +11,22 @@ define void @test_string_memmove(i8 addrspace(200)* %dst, i8 addrspace(200)* %sr
   ; Note: has must_preserve_cheri_tags, but this memmove can still be inlined since it's aligned
 ; CHECK-LABEL: test_string_memmove:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    cmove ca7, ca1
-; CHECK-NEXT:    cmove ca1, ca0
-; CHECK-NEXT:    clc ca0, 0(ca7)
-; CHECK-NEXT:    clc ca2, 8(ca7)
-; CHECK-NEXT:    clc ca3, 16(ca7)
-; CHECK-NEXT:    clc ca4, 24(ca7)
-; CHECK-NEXT:    clc ca5, 32(ca7)
-; CHECK-NEXT:    clw a6, 40(ca7)
-; CHECK-NEXT:    clb a7, 44(ca7)
-; CHECK-NEXT:    csb a7, 44(ca1)
-; CHECK-NEXT:    csw a6, 40(ca1)
-; CHECK-NEXT:    csc ca5, 32(ca1)
-; CHECK-NEXT:    csc ca4, 24(ca1)
-; CHECK-NEXT:    csc ca3, 16(ca1)
-; CHECK-NEXT:    csc ca2, 8(ca1)
-; CHECK-NEXT:    csc ca0, 0(ca1)
+; CHECK-NEXT:    cmove a7, a1
+; CHECK-NEXT:    cmove a1, a0
+; CHECK-NEXT:    clc a0, 0(a7)
+; CHECK-NEXT:    clc a2, 8(a7)
+; CHECK-NEXT:    clc a3, 16(a7)
+; CHECK-NEXT:    clc a4, 24(a7)
+; CHECK-NEXT:    clc a5, 32(a7)
+; CHECK-NEXT:    clw a6, 40(a7)
+; CHECK-NEXT:    clb a7, 44(a7)
+; CHECK-NEXT:    csb a7, 44(a1)
+; CHECK-NEXT:    csw a6, 40(a1)
+; CHECK-NEXT:    csc a5, 32(a1)
+; CHECK-NEXT:    csc a4, 24(a1)
+; CHECK-NEXT:    csc a3, 16(a1)
+; CHECK-NEXT:    csc a2, 8(a1)
+; CHECK-NEXT:    csc a0, 0(a1)
 ; CHECK-NEXT:    cret
   call void @llvm.memmove.p200i8.p200i8.i64(i8 addrspace(200)* align 16 %dst, i8 addrspace(200)* align 16 %src, i64 45, i1 false) must_preserve_cheri_tags
   ret void
@@ -36,25 +36,25 @@ define void @test_string_memcpy(i8 addrspace(200)* %dst, i8 addrspace(200)* %src
   ; Note: has must_preserve_cheri_tags, but this memcpy can still be inlined since it's aligned
 ; CHECK-LABEL: test_string_memcpy:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    cincoffset csp, csp, -16
-; CHECK-NEXT:    csc ca1, 8(csp) # 8-byte Folded Spill
-; CHECK-NEXT:    cmove ca1, ca0
-; CHECK-NEXT:    clc ca0, 8(csp) # 8-byte Folded Reload
-; CHECK-NEXT:    clb a2, 44(ca0)
-; CHECK-NEXT:    csb a2, 44(ca1)
-; CHECK-NEXT:    clw a2, 40(ca0)
-; CHECK-NEXT:    csw a2, 40(ca1)
-; CHECK-NEXT:    clc ca2, 32(ca0)
-; CHECK-NEXT:    csc ca2, 32(ca1)
-; CHECK-NEXT:    clc ca2, 24(ca0)
-; CHECK-NEXT:    csc ca2, 24(ca1)
-; CHECK-NEXT:    clc ca2, 16(ca0)
-; CHECK-NEXT:    csc ca2, 16(ca1)
-; CHECK-NEXT:    clc ca2, 8(ca0)
-; CHECK-NEXT:    csc ca2, 8(ca1)
-; CHECK-NEXT:    clc ca0, 0(ca0)
-; CHECK-NEXT:    csc ca0, 0(ca1)
-; CHECK-NEXT:    cincoffset csp, csp, 16
+; CHECK-NEXT:    cincoffset sp, sp, -16
+; CHECK-NEXT:    csc a1, 8(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    cmove a1, a0
+; CHECK-NEXT:    clc a0, 8(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    clb a2, 44(a0)
+; CHECK-NEXT:    csb a2, 44(a1)
+; CHECK-NEXT:    clw a2, 40(a0)
+; CHECK-NEXT:    csw a2, 40(a1)
+; CHECK-NEXT:    clc a2, 32(a0)
+; CHECK-NEXT:    csc a2, 32(a1)
+; CHECK-NEXT:    clc a2, 24(a0)
+; CHECK-NEXT:    csc a2, 24(a1)
+; CHECK-NEXT:    clc a2, 16(a0)
+; CHECK-NEXT:    csc a2, 16(a1)
+; CHECK-NEXT:    clc a2, 8(a0)
+; CHECK-NEXT:    csc a2, 8(a1)
+; CHECK-NEXT:    clc a0, 0(a0)
+; CHECK-NEXT:    csc a0, 0(a1)
+; CHECK-NEXT:    cincoffset sp, sp, 16
 ; CHECK-NEXT:    cret
   call void @llvm.memcpy.p200i8.p200i8.i64(i8 addrspace(200)* align 16 %dst, i8 addrspace(200)* align 16 %src, i64 45, i1 false) must_preserve_cheri_tags
   ret void
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/memcpy-zeroinit.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/memcpy-zeroinit.ll
index 8f46f4916a60d..3e39289f2e679 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/memcpy-zeroinit.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/memcpy-zeroinit.ll
@@ -11,12 +11,12 @@
 define void @_thr_umutex_init(%struct.umutex addrspace(200)* %mtx) local_unnamed_addr addrspace(200) nounwind "frame-pointer"="none" {
 ; CHECK-LABEL: _thr_umutex_init:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    csc cnull, 40(ca0)
-; CHECK-NEXT:    csc cnull, 32(ca0)
-; CHECK-NEXT:    csc cnull, 24(ca0)
-; CHECK-NEXT:    csc cnull, 16(ca0)
-; CHECK-NEXT:    csc cnull, 8(ca0)
-; CHECK-NEXT:    csc cnull, 0(ca0)
+; CHECK-NEXT:    csc zero, 40(a0)
+; CHECK-NEXT:    csc zero, 32(a0)
+; CHECK-NEXT:    csc zero, 24(a0)
+; CHECK-NEXT:    csc zero, 16(a0)
+; CHECK-NEXT:    csc zero, 8(a0)
+; CHECK-NEXT:    csc zero, 0(a0)
 ; CHECK-NEXT:    cret
   %1 = bitcast %struct.umutex addrspace(200)* %mtx to i8 addrspace(200)*
   tail call void @llvm.memcpy.p200i8.p200i8.i64(i8 addrspace(200)* align 16 %1, i8 addrspace(200)* align 16 bitcast (%struct.umutex addrspace(200)* @_thr_umutex_init.default_mtx to i8 addrspace(200)*), i64 48, i1 false)
@@ -27,20 +27,20 @@ define void @_thr_umutex_init_volatile(%struct.umutex addrspace(200)* %mtx) loca
 ; CHECK-LABEL: _thr_umutex_init_volatile:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:  .LBB1_1: # Label of block must be emitted
-; CHECK-NEXT:    auipcc ca1, %captab_pcrel_hi(_thr_umutex_init.default_mtx)
-; CHECK-NEXT:    clc ca1, %pcrel_lo(.LBB1_1)(ca1)
-; CHECK-NEXT:    clc ca2, 40(ca1)
-; CHECK-NEXT:    csc ca2, 40(ca0)
-; CHECK-NEXT:    clc ca2, 32(ca1)
-; CHECK-NEXT:    csc ca2, 32(ca0)
-; CHECK-NEXT:    clc ca2, 24(ca1)
-; CHECK-NEXT:    csc ca2, 24(ca0)
-; CHECK-NEXT:    clc ca2, 16(ca1)
-; CHECK-NEXT:    csc ca2, 16(ca0)
-; CHECK-NEXT:    clc ca2, 8(ca1)
-; CHECK-NEXT:    csc ca2, 8(ca0)
-; CHECK-NEXT:    clc ca1, 0(ca1)
-; CHECK-NEXT:    csc ca1, 0(ca0)
+; CHECK-NEXT:    auipcc a1, %captab_pcrel_hi(_thr_umutex_init.default_mtx)
+; CHECK-NEXT:    clc a1, %pcrel_lo(.LBB1_1)(a1)
+; CHECK-NEXT:    clc a2, 40(a1)
+; CHECK-NEXT:    csc a2, 40(a0)
+; CHECK-NEXT:    clc a2, 32(a1)
+; CHECK-NEXT:    csc a2, 32(a0)
+; CHECK-NEXT:    clc a2, 24(a1)
+; CHECK-NEXT:    csc a2, 24(a0)
+; CHECK-NEXT:    clc a2, 16(a1)
+; CHECK-NEXT:    csc a2, 16(a0)
+; CHECK-NEXT:    clc a2, 8(a1)
+; CHECK-NEXT:    csc a2, 8(a0)
+; CHECK-NEXT:    clc a1, 0(a1)
+; CHECK-NEXT:    csc a1, 0(a0)
 ; CHECK-NEXT:    cret
   %1 = bitcast %struct.umutex addrspace(200)* %mtx to i8 addrspace(200)*
   tail call void @llvm.memcpy.p200i8.p200i8.i64(i8 addrspace(200)* align 16 %1, i8 addrspace(200)* align 16 bitcast (%struct.umutex addrspace(200)* @_thr_umutex_init.default_mtx to i8 addrspace(200)*), i64 48, i1 true)
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/optsize-preserve-tags-memcpy-crash.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/optsize-preserve-tags-memcpy-crash.ll
index 09db63e59c7f0..67f7beaf11eec 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/optsize-preserve-tags-memcpy-crash.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/optsize-preserve-tags-memcpy-crash.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --scrub-attributes --version 2
-; DO NOT EDIT -- This file was generated from test/CodeGen/CHERI-Generic/Inputs/optsize-preserve-tags-memcpy-crash.ll
+; DO NOT EDIT -- This file was generated from test/CodeGen/CHERI-Generic/Inputs/optsize-preserve-tags-memcpy-rash.ll
 ; RUN: llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+xcheripurecap,+f < %s -o - | FileCheck %s
 ; The following code copying 31 bytes (with capability alignment) using the
 ; must_preserve_tags attribute used to trigger a "(Align < CapSize)" assertion
@@ -13,18 +13,18 @@
 define hidden void @optnone_preserve_tags_memcpy(i8 addrspace(200)* %dst, i8 addrspace(200)* %src) optnone noinline nounwind {
 ; CHECK-LABEL: optnone_preserve_tags_memcpy:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    clb a2, 30(ca1)
-; CHECK-NEXT:    csb a2, 30(ca0)
-; CHECK-NEXT:    clh a2, 28(ca1)
-; CHECK-NEXT:    csh a2, 28(ca0)
-; CHECK-NEXT:    clw a2, 24(ca1)
-; CHECK-NEXT:    csw a2, 24(ca0)
-; CHECK-NEXT:    clc ca2, 16(ca1)
-; CHECK-NEXT:    csc ca2, 16(ca0)
-; CHECK-NEXT:    clc ca2, 8(ca1)
-; CHECK-NEXT:    csc ca2, 8(ca0)
-; CHECK-NEXT:    clc ca1, 0(ca1)
-; CHECK-NEXT:    csc ca1, 0(ca0)
+; CHECK-NEXT:    clb a2, 30(a1)
+; CHECK-NEXT:    csb a2, 30(a0)
+; CHECK-NEXT:    clh a2, 28(a1)
+; CHECK-NEXT:    csh a2, 28(a0)
+; CHECK-NEXT:    clw a2, 24(a1)
+; CHECK-NEXT:    csw a2, 24(a0)
+; CHECK-NEXT:    clc a2, 16(a1)
+; CHECK-NEXT:    csc a2, 16(a0)
+; CHECK-NEXT:    clc a2, 8(a1)
+; CHECK-NEXT:    csc a2, 8(a0)
+; CHECK-NEXT:    clc a1, 0(a1)
+; CHECK-NEXT:    csc a1, 0(a0)
 ; CHECK-NEXT:    cret
   tail call void @llvm.memcpy.p200i8.p200i8.i64(i8 addrspace(200)* noundef nonnull align 16 dereferenceable(31) %dst, i8 addrspace(200)* noundef nonnull align 16 dereferenceable(31) %src, i64 31, i1 false) must_preserve_cheri_tags
   ret void
@@ -33,13 +33,13 @@ define hidden void @optnone_preserve_tags_memcpy(i8 addrspace(200)* %dst, i8 add
 define hidden void @optsize_preserve_tags_memcpy(i8 addrspace(200)* %dst, i8 addrspace(200)* %src) optsize nounwind {
 ; CHECK-LABEL: optsize_preserve_tags_memcpy:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    cincoffset csp, csp, -16
-; CHECK-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; CHECK-NEXT:    cincoffset sp, sp, -16
+; CHECK-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; CHECK-NEXT:    li a2, 31
 ; CHECK-NEXT:    li a3, 0
 ; CHECK-NEXT:    ccall memcpy
-; CHECK-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; CHECK-NEXT:    cincoffset csp, csp, 16
+; CHECK-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    cincoffset sp, sp, 16
 ; CHECK-NEXT:    cret
   tail call void @llvm.memcpy.p200i8.p200i8.i64(i8 addrspace(200)* noundef nonnull align 16 dereferenceable(31) %dst, i8 addrspace(200)* noundef nonnull align 16 dereferenceable(31) %src, i64 31, i1 false) must_preserve_cheri_tags
   ret void
@@ -48,18 +48,18 @@ define hidden void @optsize_preserve_tags_memcpy(i8 addrspace(200)* %dst, i8 add
 define hidden void @default_preserve_tags_memcpy(i8 addrspace(200)* %dst, i8 addrspace(200)* %src) nounwind {
 ; CHECK-LABEL: default_preserve_tags_memcpy:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    clb a2, 30(ca1)
-; CHECK-NEXT:    csb a2, 30(ca0)
-; CHECK-NEXT:    clh a2, 28(ca1)
-; CHECK-NEXT:    csh a2, 28(ca0)
-; CHECK-NEXT:    clw a2, 24(ca1)
-; CHECK-NEXT:    csw a2, 24(ca0)
-; CHECK-NEXT:    clc ca2, 16(ca1)
-; CHECK-NEXT:    csc ca2, 16(ca0)
-; CHECK-NEXT:    clc ca2, 8(ca1)
-; CHECK-NEXT:    csc ca2, 8(ca0)
-; CHECK-NEXT:    clc ca1, 0(ca1)
-; CHECK-NEXT:    csc ca1, 0(ca0)
+; CHECK-NEXT:    clb a2, 30(a1)
+; CHECK-NEXT:    csb a2, 30(a0)
+; CHECK-NEXT:    clh a2, 28(a1)
+; CHECK-NEXT:    csh a2, 28(a0)
+; CHECK-NEXT:    clw a2, 24(a1)
+; CHECK-NEXT:    csw a2, 24(a0)
+; CHECK-NEXT:    clc a2, 16(a1)
+; CHECK-NEXT:    csc a2, 16(a0)
+; CHECK-NEXT:    clc a2, 8(a1)
+; CHECK-NEXT:    csc a2, 8(a0)
+; CHECK-NEXT:    clc a1, 0(a1)
+; CHECK-NEXT:    csc a1, 0(a0)
 ; CHECK-NEXT:    cret
   tail call void @llvm.memcpy.p200i8.p200i8.i64(i8 addrspace(200)* noundef nonnull align 16 dereferenceable(31) %dst, i8 addrspace(200)* noundef nonnull align 16 dereferenceable(31) %src, i64 31, i1 false) must_preserve_cheri_tags
   ret void
@@ -68,18 +68,18 @@ define hidden void @default_preserve_tags_memcpy(i8 addrspace(200)* %dst, i8 add
 define hidden void @optnone_preserve_tags_memmove(i8 addrspace(200)* %dst, i8 addrspace(200)* %src) optnone noinline nounwind {
 ; CHECK-LABEL: optnone_preserve_tags_memmove:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    clc ca2, 0(ca1)
-; CHECK-NEXT:    clc ca3, 8(ca1)
-; CHECK-NEXT:    clc ca4, 16(ca1)
-; CHECK-NEXT:    clw a5, 24(ca1)
-; CHECK-NEXT:    clh a6, 28(ca1)
-; CHECK-NEXT:    clb a1, 30(ca1)
-; CHECK-NEXT:    csb a1, 30(ca0)
-; CHECK-NEXT:    csh a6, 28(ca0)
-; CHECK-NEXT:    csw a5, 24(ca0)
-; CHECK-NEXT:    csc ca4, 16(ca0)
-; CHECK-NEXT:    csc ca3, 8(ca0)
-; CHECK-NEXT:    csc ca2, 0(ca0)
+; CHECK-NEXT:    clc a2, 0(a1)
+; CHECK-NEXT:    clc a3, 8(a1)
+; CHECK-NEXT:    clc a4, 16(a1)
+; CHECK-NEXT:    clw a5, 24(a1)
+; CHECK-NEXT:    clh a6, 28(a1)
+; CHECK-NEXT:    clb a1, 30(a1)
+; CHECK-NEXT:    csb a1, 30(a0)
+; CHECK-NEXT:    csh a6, 28(a0)
+; CHECK-NEXT:    csw a5, 24(a0)
+; CHECK-NEXT:    csc a4, 16(a0)
+; CHECK-NEXT:    csc a3, 8(a0)
+; CHECK-NEXT:    csc a2, 0(a0)
 ; CHECK-NEXT:    cret
   tail call void @llvm.memmove.p200i8.p200i8.i64(i8 addrspace(200)* noundef nonnull align 16 dereferenceable(31) %dst, i8 addrspace(200)* noundef nonnull align 16 dereferenceable(31) %src, i64 31, i1 false) must_preserve_cheri_tags
   ret void
@@ -88,13 +88,13 @@ define hidden void @optnone_preserve_tags_memmove(i8 addrspace(200)* %dst, i8 ad
 define hidden void @optsize_preserve_tags_memmove(i8 addrspace(200)* %dst, i8 addrspace(200)* %src) optsize nounwind {
 ; CHECK-LABEL: optsize_preserve_tags_memmove:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    cincoffset csp, csp, -16
-; CHECK-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; CHECK-NEXT:    cincoffset sp, sp, -16
+; CHECK-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; CHECK-NEXT:    li a2, 31
 ; CHECK-NEXT:    li a3, 0
 ; CHECK-NEXT:    ccall memmove
-; CHECK-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; CHECK-NEXT:    cincoffset csp, csp, 16
+; CHECK-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    cincoffset sp, sp, 16
 ; CHECK-NEXT:    cret
   tail call void @llvm.memmove.p200i8.p200i8.i64(i8 addrspace(200)* noundef nonnull align 16 dereferenceable(31) %dst, i8 addrspace(200)* noundef nonnull align 16 dereferenceable(31) %src, i64 31, i1 false) must_preserve_cheri_tags
   ret void
@@ -103,18 +103,18 @@ define hidden void @optsize_preserve_tags_memmove(i8 addrspace(200)* %dst, i8 ad
 define hidden void @default_preserve_tags_memmove(i8 addrspace(200)* %dst, i8 addrspace(200)* %src) nounwind{
 ; CHECK-LABEL: default_preserve_tags_memmove:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    clw a2, 24(ca1)
-; CHECK-NEXT:    clc ca3, 0(ca1)
-; CHECK-NEXT:    clh a4, 28(ca1)
-; CHECK-NEXT:    clc ca5, 16(ca1)
-; CHECK-NEXT:    clb a6, 30(ca1)
-; CHECK-NEXT:    csc ca3, 0(ca0)
-; CHECK-NEXT:    clc ca1, 8(ca1)
-; CHECK-NEXT:    csc ca5, 16(ca0)
-; CHECK-NEXT:    csb a6, 30(ca0)
-; CHECK-NEXT:    csh a4, 28(ca0)
-; CHECK-NEXT:    csc ca1, 8(ca0)
-; CHECK-NEXT:    csw a2, 24(ca0)
+; CHECK-NEXT:    clw a2, 24(a1)
+; CHECK-NEXT:    clc a3, 0(a1)
+; CHECK-NEXT:    clh a4, 28(a1)
+; CHECK-NEXT:    clc a5, 16(a1)
+; CHECK-NEXT:    clb a6, 30(a1)
+; CHECK-NEXT:    csc a3, 0(a0)
+; CHECK-NEXT:    clc a1, 8(a1)
+; CHECK-NEXT:    csc a5, 16(a0)
+; CHECK-NEXT:    csb a6, 30(a0)
+; CHECK-NEXT:    csh a4, 28(a0)
+; CHECK-NEXT:    csc a1, 8(a0)
+; CHECK-NEXT:    csw a2, 24(a0)
 ; CHECK-NEXT:    cret
   tail call void @llvm.memmove.p200i8.p200i8.i64(i8 addrspace(200)* noundef nonnull align 16 dereferenceable(31) %dst, i8 addrspace(200)* noundef nonnull align 16 dereferenceable(31) %src, i64 31, i1 false) must_preserve_cheri_tags
   ret void
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/ptrtoint.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/ptrtoint.ll
index f5f6952bb9f37..a58b84e5bb2d4 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/ptrtoint.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/ptrtoint.ll
@@ -12,7 +12,7 @@ define internal i32 @ptrtoint(i8 addrspace(200)* %cap) addrspace(200) nounwind {
 ;
 ; HYBRID-LABEL: ptrtoint:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    cgettag a1, ca0
+; HYBRID-NEXT:    cgettag a1, a0
 ; HYBRID-NEXT:    neg a1, a1
 ; HYBRID-NEXT:    and a0, a0, a1
 ; HYBRID-NEXT:    ret
@@ -28,7 +28,7 @@ define internal i32 @ptrtoint_plus_const(i8 addrspace(200)* %cap) addrspace(200)
 ;
 ; HYBRID-LABEL: ptrtoint_plus_const:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    cgettag a1, ca0
+; HYBRID-NEXT:    cgettag a1, a0
 ; HYBRID-NEXT:    neg a1, a1
 ; HYBRID-NEXT:    and a0, a0, a1
 ; HYBRID-NEXT:    addi a0, a0, 2
@@ -46,7 +46,7 @@ define internal i32 @ptrtoint_plus_var(i8 addrspace(200)* %cap, i32 %add) addrsp
 ;
 ; HYBRID-LABEL: ptrtoint_plus_var:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    cgettag a2, ca0
+; HYBRID-NEXT:    cgettag a2, a0
 ; HYBRID-NEXT:    neg a2, a2
 ; HYBRID-NEXT:    and a0, a0, a2
 ; HYBRID-NEXT:    add a0, a0, a1
@@ -64,7 +64,7 @@ define internal i32 @ptrtoint_null() addrspace(200) nounwind {
 ;
 ; HYBRID-LABEL: ptrtoint_null:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    cgettag a0, cnull
+; HYBRID-NEXT:    cgettag a0, zero
 ; HYBRID-NEXT:    neg a0, a0
 ; HYBRID-NEXT:    li a0, 0
 ; HYBRID-NEXT:    ret
@@ -80,7 +80,7 @@ define internal i32 @ptrtoint_null_plus_const() addrspace(200) nounwind {
 ;
 ; HYBRID-LABEL: ptrtoint_null_plus_const:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    cgettag a0, cnull
+; HYBRID-NEXT:    cgettag a0, zero
 ; HYBRID-NEXT:    neg a0, a0
 ; HYBRID-NEXT:    li a0, 2
 ; HYBRID-NEXT:    ret
@@ -96,7 +96,7 @@ define internal i32 @ptrtoint_null_plus_var(i32 %add) addrspace(200) nounwind {
 ;
 ; HYBRID-LABEL: ptrtoint_null_plus_var:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    cgettag a1, cnull
+; HYBRID-NEXT:    cgettag a1, zero
 ; HYBRID-NEXT:    neg a1, a1
 ; HYBRID-NEXT:    ret
   %zero = ptrtoint i8 addrspace(200)* null to i32
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/purecap-jumptable.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/purecap-jumptable.ll
index 4157f5eb032af..219c9d01d3a89 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/purecap-jumptable.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/purecap-jumptable.ll
@@ -19,7 +19,7 @@ define void @below_threshold(i32 %in, i32 addrspace(200)* %out) nounwind {
 ; CHECK-NEXT:  .LBB0_3: # %bb2
 ; CHECK-NEXT:    li a0, 3
 ; CHECK-NEXT:  .LBB0_4: # %exit
-; CHECK-NEXT:    csw a0, 0(ca1)
+; CHECK-NEXT:    csw a0, 0(a1)
 ; CHECK-NEXT:  .LBB0_5: # %exit
 ; CHECK-NEXT:    cret
 entry:
@@ -68,7 +68,7 @@ define void @above_threshold_mips(i32 %in, i32 addrspace(200)* %out) nounwind {
 ; CHECK-NEXT:  .LBB1_8: # %bb3
 ; CHECK-NEXT:    li a0, 2
 ; CHECK-NEXT:  .LBB1_9: # %exit
-; CHECK-NEXT:    csw a0, 0(ca1)
+; CHECK-NEXT:    csw a0, 0(a1)
 ; CHECK-NEXT:  .LBB1_10: # %exit
 ; CHECK-NEXT:    cret
 entry:
@@ -104,21 +104,21 @@ define void @above_threshold_all(i32 %in, i32 addrspace(200)* %out) nounwind {
 ; CHECK-NEXT:    li a2, 5
 ; CHECK-NEXT:    bltu a2, a0, .LBB2_9
 ; CHECK-NEXT:  # %bb.1: # %entry
-; CHECK-NEXT:    cincoffset csp, csp, -16
-; CHECK-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; CHECK-NEXT:    cincoffset sp, sp, -16
+; CHECK-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; CHECK-NEXT:    slli a0, a0, 2
 ; CHECK-NEXT:  .LBB2_10: # %entry
 ; CHECK-NEXT:    # Label of block must be emitted
-; CHECK-NEXT:    auipcc ca2, %pcrel_hi(.LJTI2_0)
-; CHECK-NEXT:    cincoffset ca2, ca2, %pcrel_lo(.LBB2_10)
-; CHECK-NEXT:    cincoffset ca0, ca2, a0
-; CHECK-NEXT:    clw a0, 0(ca0)
+; CHECK-NEXT:    auipcc a2, %pcrel_hi(.LJTI2_0)
+; CHECK-NEXT:    cincoffset a2, a2, %pcrel_lo(.LBB2_10)
+; CHECK-NEXT:    cincoffset a0, a2, a0
+; CHECK-NEXT:    clw a0, 0(a0)
 ; CHECK-NEXT:  .LBB2_11: # %entry
 ; CHECK-NEXT:    # Label of block must be emitted
-; CHECK-NEXT:    auipcc ca2, %pcrel_hi(.Labove_threshold_all$jump_table_base)
-; CHECK-NEXT:    cincoffset ca2, ca2, %pcrel_lo(.LBB2_11)
-; CHECK-NEXT:    cincoffset ca0, ca2, a0
-; CHECK-NEXT:    cjr ca0
+; CHECK-NEXT:    auipcc a2, %pcrel_hi(.Labove_threshold_all$jump_table_base)
+; CHECK-NEXT:    cincoffset a2, a2, %pcrel_lo(.LBB2_11)
+; CHECK-NEXT:    cincoffset a0, a2, a0
+; CHECK-NEXT:    cjr a0
 ; CHECK-NEXT:  .LBB2_2: # %bb1
 ; CHECK-NEXT:    li a0, 4
 ; CHECK-NEXT:    j .LBB2_8
@@ -137,9 +137,9 @@ define void @above_threshold_all(i32 %in, i32 addrspace(200)* %out) nounwind {
 ; CHECK-NEXT:  .LBB2_7: # %bb6
 ; CHECK-NEXT:    li a0, 200
 ; CHECK-NEXT:  .LBB2_8:
-; CHECK-NEXT:    csw a0, 0(ca1)
-; CHECK-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; CHECK-NEXT:    cincoffset csp, csp, 16
+; CHECK-NEXT:    csw a0, 0(a1)
+; CHECK-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    cincoffset sp, sp, 16
 ; CHECK-NEXT:  .LBB2_9: # %exit
 ; CHECK-NEXT:    cret
 entry:
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/setoffset-multiple-uses.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/setoffset-multiple-uses.ll
index 59fe0403b345c..b3f53ba06c373 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/setoffset-multiple-uses.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/setoffset-multiple-uses.ll
@@ -4,7 +4,7 @@
 ; RUN: opt -S -passes=instcombine -o - %s | llc -mtriple=riscv32 --relocation-model=pic -target-abi il32pc64f -mattr=+xcheri,+xcheripurecap,+f -O1 - -o - | %cheri_FileCheck %s --check-prefix ASM
 
 target datalayout = "e-m:e-pf200:64:64:64:32-p:32:32-i64:64-n32-S128-A200-P200-G200"
-; Reduced test case for a crash in the new optimization to fold multiple setoffset calls (orignally found when compiling libunwind)
+; Reduced test case for a rash in the new optimization to fold multiple setoffset calls (orignally found when compiling libunwind)
 
 declare i32 @check_fold(i32) addrspace(200)
 declare void @check_fold_i8ptr(ptr addrspace(200)) addrspace(200)
@@ -14,13 +14,13 @@ declare ptr addrspace(200) @llvm.cheri.cap.offset.set.i32(ptr addrspace(200), i3
 define void @infer_values_from_null_set_offset() addrspace(200) nounwind {
 ; ASM-LABEL: infer_values_from_null_set_offset:
 ; ASM:       # %bb.0:
-; ASM-NEXT:    cincoffset csp, csp, -16
-; ASM-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; ASM-NEXT:    cincoffset sp, sp, -16
+; ASM-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; ASM-NEXT:    lui a0, 30
 ; ASM-NEXT:    addi a0, a0, 576
 ; ASM-NEXT:    ccall check_fold
-; ASM-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; ASM-NEXT:    cincoffset csp, csp, 16
+; ASM-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; ASM-NEXT:    cincoffset sp, sp, 16
 ; ASM-NEXT:    cret
 ; CHECK-LABEL: define void @infer_values_from_null_set_offset
 ; CHECK-SAME: () addrspace(200) #[[ATTR1:[0-9]+]] {
@@ -36,21 +36,21 @@ define void @infer_values_from_null_set_offset() addrspace(200) nounwind {
 define void @multiple_uses_big_constant() addrspace(200) nounwind {
 ; ASM-LABEL: multiple_uses_big_constant:
 ; ASM:       # %bb.0:
-; ASM-NEXT:    cincoffset csp, csp, -16
-; ASM-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; ASM-NEXT:    csc cs0, 0(csp) # 8-byte Folded Spill
+; ASM-NEXT:    cincoffset sp, sp, -16
+; ASM-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; ASM-NEXT:    csc s0, 0(sp) # 8-byte Folded Spill
 ; ASM-NEXT:    lui a0, 30
 ; ASM-NEXT:    addi a0, a0, 576
-; ASM-NEXT:    cincoffset cs0, cnull, a0
-; ASM-NEXT:    cmove ca0, cs0
+; ASM-NEXT:    cincoffset s0, zero, a0
+; ASM-NEXT:    cmove a0, s0
 ; ASM-NEXT:    ccall check_fold_i8ptr
-; ASM-NEXT:    cmove ca0, cs0
+; ASM-NEXT:    cmove a0, s0
 ; ASM-NEXT:    ccall check_fold_i8ptr
-; ASM-NEXT:    cmove ca0, cs0
+; ASM-NEXT:    cmove a0, s0
 ; ASM-NEXT:    ccall check_fold_i8ptr
-; ASM-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; ASM-NEXT:    clc cs0, 0(csp) # 8-byte Folded Reload
-; ASM-NEXT:    cincoffset csp, csp, 16
+; ASM-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; ASM-NEXT:    clc s0, 0(sp) # 8-byte Folded Reload
+; ASM-NEXT:    cincoffset sp, sp, 16
 ; ASM-NEXT:    cret
 ; CHECK-LABEL: define void @multiple_uses_big_constant
 ; CHECK-SAME: () addrspace(200) #[[ATTR1]] {
@@ -70,16 +70,16 @@ define void @multiple_uses_big_constant() addrspace(200) nounwind {
 define void @multiple_uses_small_constant() addrspace(200) nounwind {
 ; ASM-LABEL: multiple_uses_small_constant:
 ; ASM:       # %bb.0:
-; ASM-NEXT:    cincoffset csp, csp, -16
-; ASM-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; ASM-NEXT:    cincoffset ca0, cnull, 123
+; ASM-NEXT:    cincoffset sp, sp, -16
+; ASM-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; ASM-NEXT:    cincoffset a0, zero, 123
 ; ASM-NEXT:    ccall check_fold_i8ptr
-; ASM-NEXT:    cincoffset ca0, cnull, 123
+; ASM-NEXT:    cincoffset a0, zero, 123
 ; ASM-NEXT:    ccall check_fold_i8ptr
-; ASM-NEXT:    cincoffset ca0, cnull, 123
+; ASM-NEXT:    cincoffset a0, zero, 123
 ; ASM-NEXT:    ccall check_fold_i8ptr
-; ASM-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; ASM-NEXT:    cincoffset csp, csp, 16
+; ASM-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; ASM-NEXT:    cincoffset sp, sp, 16
 ; ASM-NEXT:    cret
 ; CHECK-LABEL: define void @multiple_uses_small_constant
 ; CHECK-SAME: () addrspace(200) #[[ATTR1]] {
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/stack-bounds-dynamic-alloca.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/stack-bounds-dynamic-alloca.ll
index 85804365a6a64..ac074a9c53103 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/stack-bounds-dynamic-alloca.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/stack-bounds-dynamic-alloca.ll
@@ -19,8 +19,8 @@ declare i32 @use_alloca(ptr addrspace(200)) local_unnamed_addr addrspace(200)
 define i32 @alloca_in_entry(i1 %arg) local_unnamed_addr addrspace(200) nounwind {
 ; ASM-LABEL: alloca_in_entry:
 ; ASM:       # %bb.0: # %entry
-; ASM-NEXT:    cincoffset csp, csp, -32
-; ASM-NEXT:    csc cra, 24(csp) # 8-byte Folded Spill
+; ASM-NEXT:    cincoffset sp, sp, -32
+; ASM-NEXT:    csc ra, 24(sp) # 8-byte Folded Spill
 ; ASM-NEXT:    mv a1, a0
 ; ASM-NEXT:    andi a0, a1, 1
 ; ASM-NEXT:    beqz a0, .LBB0_4
@@ -29,19 +29,19 @@ define i32 @alloca_in_entry(i1 %arg) local_unnamed_addr addrspace(200) nounwind
 ; ASM-NEXT:    j .LBB0_2
 ; ASM-NEXT:  .LBB0_2: # %use_alloca_no_bounds
 ; ASM-NEXT:    li a0, 0
-; ASM-NEXT:    csw a0, 12(csp)
+; ASM-NEXT:    csw a0, 12(sp)
 ; ASM-NEXT:    li a0, 1234
-; ASM-NEXT:    csw a0, 8(csp)
+; ASM-NEXT:    csw a0, 8(sp)
 ; ASM-NEXT:    j .LBB0_3
 ; ASM-NEXT:  .LBB0_3: # %use_alloca_need_bounds
-; ASM-NEXT:    cincoffset ca0, csp, 0
-; ASM-NEXT:    csetbounds ca0, ca0, 16
+; ASM-NEXT:    cincoffset a0, sp, 0
+; ASM-NEXT:    csetbounds a0, a0, 16
 ; ASM-NEXT:    ccall use_alloca
 ; ASM-NEXT:    j .LBB0_4
 ; ASM-NEXT:  .LBB0_4: # %exit
 ; ASM-NEXT:    li a0, 123
-; ASM-NEXT:    clc cra, 24(csp) # 8-byte Folded Reload
-; ASM-NEXT:    cincoffset csp, csp, 32
+; ASM-NEXT:    clc ra, 24(sp) # 8-byte Folded Reload
+; ASM-NEXT:    cincoffset sp, sp, 32
 ; ASM-NEXT:    cret
 ;
 ; ASM-OPT-LABEL: alloca_in_entry:
@@ -49,16 +49,16 @@ define i32 @alloca_in_entry(i1 %arg) local_unnamed_addr addrspace(200) nounwind
 ; ASM-OPT-NEXT:    andi a0, a0, 1
 ; ASM-OPT-NEXT:    beqz a0, .LBB0_2
 ; ASM-OPT-NEXT:  # %bb.1: # %do_alloca
-; ASM-OPT-NEXT:    cincoffset csp, csp, -32
-; ASM-OPT-NEXT:    csc cra, 24(csp) # 8-byte Folded Spill
-; ASM-OPT-NEXT:    csw zero, 12(csp)
+; ASM-OPT-NEXT:    cincoffset sp, sp, -32
+; ASM-OPT-NEXT:    csc ra, 24(sp) # 8-byte Folded Spill
+; ASM-OPT-NEXT:    csw zero, 12(sp)
 ; ASM-OPT-NEXT:    li a0, 1234
-; ASM-OPT-NEXT:    csw a0, 8(csp)
-; ASM-OPT-NEXT:    cincoffset ca0, csp, 0
-; ASM-OPT-NEXT:    csetbounds ca0, ca0, 16
+; ASM-OPT-NEXT:    csw a0, 8(sp)
+; ASM-OPT-NEXT:    cincoffset a0, sp, 0
+; ASM-OPT-NEXT:    csetbounds a0, a0, 16
 ; ASM-OPT-NEXT:    ccall use_alloca
-; ASM-OPT-NEXT:    clc cra, 24(csp) # 8-byte Folded Reload
-; ASM-OPT-NEXT:    cincoffset csp, csp, 32
+; ASM-OPT-NEXT:    clc ra, 24(sp) # 8-byte Folded Reload
+; ASM-OPT-NEXT:    cincoffset sp, sp, 32
 ; ASM-OPT-NEXT:  .LBB0_2: # %exit
 ; ASM-OPT-NEXT:    li a0, 123
 ; ASM-OPT-NEXT:    cret
@@ -105,42 +105,42 @@ exit:                                             ; preds = %use_alloca_need_bou
 define i32 @alloca_not_in_entry(i1 %arg) local_unnamed_addr addrspace(200) nounwind {
 ; ASM-LABEL: alloca_not_in_entry:
 ; ASM:       # %bb.0: # %entry
-; ASM-NEXT:    cincoffset csp, csp, -32
-; ASM-NEXT:    csc cra, 24(csp) # 8-byte Folded Spill
-; ASM-NEXT:    csc cs0, 16(csp) # 8-byte Folded Spill
-; ASM-NEXT:    cincoffset cs0, csp, 32
+; ASM-NEXT:    cincoffset sp, sp, -32
+; ASM-NEXT:    csc ra, 24(sp) # 8-byte Folded Spill
+; ASM-NEXT:    csc s0, 16(sp) # 8-byte Folded Spill
+; ASM-NEXT:    cincoffset s0, sp, 32
 ; ASM-NEXT:    mv a1, a0
 ; ASM-NEXT:    andi a0, a1, 1
 ; ASM-NEXT:    beqz a0, .LBB1_4
 ; ASM-NEXT:    j .LBB1_1
 ; ASM-NEXT:  .LBB1_1: # %do_alloca
-; ASM-NEXT:    cmove ca0, csp
+; ASM-NEXT:    cmove a0, sp
 ; ASM-NEXT:    mv a1, a0
 ; ASM-NEXT:    addi a1, a1, -16
-; ASM-NEXT:    csetaddr ca1, ca0, a1
-; ASM-NEXT:    csetbounds ca0, ca1, 16
-; ASM-NEXT:    csc ca0, -32(cs0) # 8-byte Folded Spill
-; ASM-NEXT:    cmove csp, ca1
-; ASM-NEXT:    csetbounds ca0, ca0, 16
-; ASM-NEXT:    csc ca0, -24(cs0) # 8-byte Folded Spill
+; ASM-NEXT:    csetaddr a1, a0, a1
+; ASM-NEXT:    csetbounds a0, a1, 16
+; ASM-NEXT:    csc a0, -32(s0) # 8-byte Folded Spill
+; ASM-NEXT:    cmove sp, a1
+; ASM-NEXT:    csetbounds a0, a0, 16
+; ASM-NEXT:    csc a0, -24(s0) # 8-byte Folded Spill
 ; ASM-NEXT:    j .LBB1_2
 ; ASM-NEXT:  .LBB1_2: # %use_alloca_no_bounds
-; ASM-NEXT:    clc ca1, -32(cs0) # 8-byte Folded Reload
+; ASM-NEXT:    clc a1, -32(s0) # 8-byte Folded Reload
 ; ASM-NEXT:    li a0, 0
-; ASM-NEXT:    csw a0, 12(ca1)
+; ASM-NEXT:    csw a0, 12(a1)
 ; ASM-NEXT:    li a0, 1234
-; ASM-NEXT:    csw a0, 8(ca1)
+; ASM-NEXT:    csw a0, 8(a1)
 ; ASM-NEXT:    j .LBB1_3
 ; ASM-NEXT:  .LBB1_3: # %use_alloca_need_bounds
-; ASM-NEXT:    clc ca0, -24(cs0) # 8-byte Folded Reload
+; ASM-NEXT:    clc a0, -24(s0) # 8-byte Folded Reload
 ; ASM-NEXT:    ccall use_alloca
 ; ASM-NEXT:    j .LBB1_4
 ; ASM-NEXT:  .LBB1_4: # %exit
 ; ASM-NEXT:    li a0, 123
-; ASM-NEXT:    cincoffset csp, cs0, -32
-; ASM-NEXT:    clc cra, 24(csp) # 8-byte Folded Reload
-; ASM-NEXT:    clc cs0, 16(csp) # 8-byte Folded Reload
-; ASM-NEXT:    cincoffset csp, csp, 32
+; ASM-NEXT:    cincoffset sp, s0, -32
+; ASM-NEXT:    clc ra, 24(sp) # 8-byte Folded Reload
+; ASM-NEXT:    clc s0, 16(sp) # 8-byte Folded Reload
+; ASM-NEXT:    cincoffset sp, sp, 32
 ; ASM-NEXT:    cret
 ;
 ; ASM-OPT-LABEL: alloca_not_in_entry:
@@ -148,23 +148,23 @@ define i32 @alloca_not_in_entry(i1 %arg) local_unnamed_addr addrspace(200) nounw
 ; ASM-OPT-NEXT:    andi a0, a0, 1
 ; ASM-OPT-NEXT:    beqz a0, .LBB1_2
 ; ASM-OPT-NEXT:  # %bb.1: # %do_alloca
-; ASM-OPT-NEXT:    cincoffset csp, csp, -16
-; ASM-OPT-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; ASM-OPT-NEXT:    csc cs0, 0(csp) # 8-byte Folded Spill
-; ASM-OPT-NEXT:    cincoffset cs0, csp, 16
+; ASM-OPT-NEXT:    cincoffset sp, sp, -16
+; ASM-OPT-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; ASM-OPT-NEXT:    csc s0, 0(sp) # 8-byte Folded Spill
+; ASM-OPT-NEXT:    cincoffset s0, sp, 16
 ; ASM-OPT-NEXT:    addi a0, sp, -16
-; ASM-OPT-NEXT:    csetaddr ca0, csp, a0
-; ASM-OPT-NEXT:    csetbounds ca1, ca0, 16
-; ASM-OPT-NEXT:    cmove csp, ca0
-; ASM-OPT-NEXT:    csetbounds ca0, ca1, 16
-; ASM-OPT-NEXT:    csw zero, 12(ca1)
+; ASM-OPT-NEXT:    csetaddr a0, sp, a0
+; ASM-OPT-NEXT:    csetbounds a1, a0, 16
+; ASM-OPT-NEXT:    cmove sp, a0
+; ASM-OPT-NEXT:    csetbounds a0, a1, 16
+; ASM-OPT-NEXT:    csw zero, 12(a1)
 ; ASM-OPT-NEXT:    li a2, 1234
-; ASM-OPT-NEXT:    csw a2, 8(ca1)
+; ASM-OPT-NEXT:    csw a2, 8(a1)
 ; ASM-OPT-NEXT:    ccall use_alloca
-; ASM-OPT-NEXT:    cincoffset csp, cs0, -16
-; ASM-OPT-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; ASM-OPT-NEXT:    clc cs0, 0(csp) # 8-byte Folded Reload
-; ASM-OPT-NEXT:    cincoffset csp, csp, 16
+; ASM-OPT-NEXT:    cincoffset sp, s0, -16
+; ASM-OPT-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; ASM-OPT-NEXT:    clc s0, 0(sp) # 8-byte Folded Reload
+; ASM-OPT-NEXT:    cincoffset sp, sp, 16
 ; ASM-OPT-NEXT:  .LBB1_2: # %exit
 ; ASM-OPT-NEXT:    li a0, 123
 ; ASM-OPT-NEXT:    cret
@@ -210,65 +210,65 @@ exit:                                             ; preds = %use_alloca_need_bou
 
 ; The original reduced test case from libc/gen/exec.c
 ; We can't use llvm.cheri.bounded.stack.cap.i64 here, since that only works for static allocas:
-define i32 @crash_reproducer(i1 %arg) local_unnamed_addr addrspace(200) nounwind {
-; ASM-LABEL: crash_reproducer:
+define i32 @rash_reproducer(i1 %arg) local_unnamed_addr addrspace(200) nounwind {
+; ASM-LABEL: rash_reproducer:
 ; ASM:       # %bb.0: # %entry
-; ASM-NEXT:    cincoffset csp, csp, -32
-; ASM-NEXT:    csc cra, 24(csp) # 8-byte Folded Spill
-; ASM-NEXT:    csc cs0, 16(csp) # 8-byte Folded Spill
-; ASM-NEXT:    cincoffset cs0, csp, 32
+; ASM-NEXT:    cincoffset sp, sp, -32
+; ASM-NEXT:    csc ra, 24(sp) # 8-byte Folded Spill
+; ASM-NEXT:    csc s0, 16(sp) # 8-byte Folded Spill
+; ASM-NEXT:    cincoffset s0, sp, 32
 ; ASM-NEXT:    mv a1, a0
 ; ASM-NEXT:    andi a0, a1, 1
 ; ASM-NEXT:    beqz a0, .LBB2_2
 ; ASM-NEXT:    j .LBB2_1
 ; ASM-NEXT:  .LBB2_1: # %entry.while.end_crit_edge
 ; ASM-NEXT:  .LBB2_2: # %while.body
-; ASM-NEXT:    cmove ca0, csp
+; ASM-NEXT:    cmove a0, sp
 ; ASM-NEXT:    mv a1, a0
 ; ASM-NEXT:    addi a1, a1, -16
-; ASM-NEXT:    csetaddr ca1, ca0, a1
-; ASM-NEXT:    csetbounds ca0, ca1, 16
-; ASM-NEXT:    cmove csp, ca1
-; ASM-NEXT:    csetbounds ca0, ca0, 16
-; ASM-NEXT:    csc ca0, -24(cs0) # 8-byte Folded Spill
+; ASM-NEXT:    csetaddr a1, a0, a1
+; ASM-NEXT:    csetbounds a0, a1, 16
+; ASM-NEXT:    cmove sp, a1
+; ASM-NEXT:    csetbounds a0, a0, 16
+; ASM-NEXT:    csc a0, -24(s0) # 8-byte Folded Spill
 ; ASM-NEXT:    j .LBB2_3
 ; ASM-NEXT:  .LBB2_3: # %while.end.loopexit
-; ASM-NEXT:    clc ca0, -24(cs0) # 8-byte Folded Reload
-; ASM-NEXT:    csc ca0, -32(cs0) # 8-byte Folded Spill
+; ASM-NEXT:    clc a0, -24(s0) # 8-byte Folded Reload
+; ASM-NEXT:    csc a0, -32(s0) # 8-byte Folded Spill
 ; ASM-NEXT:    j .LBB2_4
 ; ASM-NEXT:  .LBB2_4: # %while.end
-; ASM-NEXT:    clc ca0, -32(cs0) # 8-byte Folded Reload
+; ASM-NEXT:    clc a0, -32(s0) # 8-byte Folded Reload
 ; ASM-NEXT:    ccall use_alloca
 ; ASM-NEXT:    addi a0, a0, 1234
-; ASM-NEXT:    cincoffset csp, cs0, -32
-; ASM-NEXT:    clc cra, 24(csp) # 8-byte Folded Reload
-; ASM-NEXT:    clc cs0, 16(csp) # 8-byte Folded Reload
-; ASM-NEXT:    cincoffset csp, csp, 32
+; ASM-NEXT:    cincoffset sp, s0, -32
+; ASM-NEXT:    clc ra, 24(sp) # 8-byte Folded Reload
+; ASM-NEXT:    clc s0, 16(sp) # 8-byte Folded Reload
+; ASM-NEXT:    cincoffset sp, sp, 32
 ; ASM-NEXT:    cret
 ;
-; ASM-OPT-LABEL: crash_reproducer:
+; ASM-OPT-LABEL: rash_reproducer:
 ; ASM-OPT:       # %bb.0: # %entry
 ; ASM-OPT-NEXT:    andi a0, a0, 1
 ; ASM-OPT-NEXT:    bnez a0, .LBB2_2
 ; ASM-OPT-NEXT:  # %bb.1: # %while.body
-; ASM-OPT-NEXT:    cincoffset csp, csp, -16
-; ASM-OPT-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; ASM-OPT-NEXT:    csc cs0, 0(csp) # 8-byte Folded Spill
-; ASM-OPT-NEXT:    cincoffset cs0, csp, 16
+; ASM-OPT-NEXT:    cincoffset sp, sp, -16
+; ASM-OPT-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; ASM-OPT-NEXT:    csc s0, 0(sp) # 8-byte Folded Spill
+; ASM-OPT-NEXT:    cincoffset s0, sp, 16
 ; ASM-OPT-NEXT:    addi a0, sp, -16
-; ASM-OPT-NEXT:    csetaddr ca0, csp, a0
-; ASM-OPT-NEXT:    csetbounds ca1, ca0, 16
-; ASM-OPT-NEXT:    cmove csp, ca0
-; ASM-OPT-NEXT:    csetbounds ca0, ca1, 16
+; ASM-OPT-NEXT:    csetaddr a0, sp, a0
+; ASM-OPT-NEXT:    csetbounds a1, a0, 16
+; ASM-OPT-NEXT:    cmove sp, a0
+; ASM-OPT-NEXT:    csetbounds a0, a1, 16
 ; ASM-OPT-NEXT:    ccall use_alloca
 ; ASM-OPT-NEXT:    addi a0, a0, 1234
-; ASM-OPT-NEXT:    cincoffset csp, cs0, -16
-; ASM-OPT-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; ASM-OPT-NEXT:    clc cs0, 0(csp) # 8-byte Folded Reload
-; ASM-OPT-NEXT:    cincoffset csp, csp, 16
+; ASM-OPT-NEXT:    cincoffset sp, s0, -16
+; ASM-OPT-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; ASM-OPT-NEXT:    clc s0, 0(sp) # 8-byte Folded Reload
+; ASM-OPT-NEXT:    cincoffset sp, sp, 16
 ; ASM-OPT-NEXT:    cret
 ; ASM-OPT-NEXT:  .LBB2_2: # %entry.while.end_crit_edge
-; CHECK-LABEL: define i32 @crash_reproducer
+; CHECK-LABEL: define i32 @rash_reproducer
 ; CHECK-SAME: (i1 [[ARG:%.*]]) local_unnamed_addr addrspace(200) #[[ATTR1]] {
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    br i1 [[ARG]], label [[ENTRY_WHILE_END_CRIT_EDGE:%.*]], label [[WHILE_BODY:%.*]]
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/stack-bounds-opaque-spill-too-early.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/stack-bounds-opaque-spill-too-early.ll
index 73413676b1e3a..51d33315ade9f 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/stack-bounds-opaque-spill-too-early.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/stack-bounds-opaque-spill-too-early.ll
@@ -34,19 +34,19 @@ declare void @cheribsdtest_check_cap_eq(ptr addrspace(200) noundef, ptr addrspac
 define dso_local void @lazy_bind_args() addrspace(200) nounwind {
 ; ASM-LABEL: lazy_bind_args:
 ; ASM:       # %bb.0: # %entry
-; ASM-NEXT:    cincoffset csp, csp, -16
-; ASM-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; ASM-NEXT:    cincoffset ca0, csp, 0
-; ASM-NEXT:    csetbounds ca0, ca0, 8
-; ASM-NEXT:    csc ca0, 0(csp)
+; ASM-NEXT:    cincoffset sp, sp, -16
+; ASM-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; ASM-NEXT:    cincoffset a0, sp, 0
+; ASM-NEXT:    csetbounds a0, a0, 8
+; ASM-NEXT:    csc a0, 0(sp)
 ; ASM-NEXT:    ccall cheribsdtest_dynamic_identity_cap
-; ASM-NEXT:    clc ca1, 0(csp)
-; ASM-NEXT:    cmove ca2, ca0
-; ASM-NEXT:    cmove ca0, ca1
-; ASM-NEXT:    cmove ca1, ca2
+; ASM-NEXT:    clc a1, 0(sp)
+; ASM-NEXT:    cmove a2, a0
+; ASM-NEXT:    cmove a0, a1
+; ASM-NEXT:    cmove a1, a2
 ; ASM-NEXT:    ccall cheribsdtest_check_cap_eq
-; ASM-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; ASM-NEXT:    cincoffset csp, csp, 16
+; ASM-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; ASM-NEXT:    cincoffset sp, sp, 16
 ; ASM-NEXT:    cret
 ; CHECK-LABEL: define dso_local void @lazy_bind_args
 ; CHECK-SAME: () addrspace(200) #[[ATTR2:[0-9]+]] {
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/stack-bounds-pass-phi.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/stack-bounds-pass-phi.ll
index 8c157d981db90..0303cf1a97fdc 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/stack-bounds-pass-phi.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/stack-bounds-pass-phi.ll
@@ -13,59 +13,59 @@ declare void @foo(ptr addrspace(200)) addrspace(200)
 define void @test_phi(i1 %cond) addrspace(200) nounwind {
 ; ASM-LABEL: test_phi:
 ; ASM:       # %bb.0: # %entry
-; ASM-NEXT:    cincoffset csp, csp, -32
-; ASM-NEXT:    csc cra, 24(csp) # 8-byte Folded Spill
-; ASM-NEXT:    csc cs0, 16(csp) # 8-byte Folded Spill
+; ASM-NEXT:    cincoffset sp, sp, -32
+; ASM-NEXT:    csc ra, 24(sp) # 8-byte Folded Spill
+; ASM-NEXT:    csc s0, 16(sp) # 8-byte Folded Spill
 ; ASM-NEXT:    andi a0, a0, 1
 ; ASM-NEXT:    beqz a0, .LBB0_2
 ; ASM-NEXT:  # %bb.1: # %block1
-; ASM-NEXT:    cmove ca0, cnull
+; ASM-NEXT:    cmove a0, zero
 ; ASM-NEXT:    li a1, 1
-; ASM-NEXT:    csw a1, 12(csp)
+; ASM-NEXT:    csw a1, 12(sp)
 ; ASM-NEXT:    li a1, 2
-; ASM-NEXT:    csw a1, 8(csp)
+; ASM-NEXT:    csw a1, 8(sp)
 ; ASM-NEXT:    li a1, 3
-; ASM-NEXT:    csw a1, 4(csp)
-; ASM-NEXT:    cincoffset ca1, csp, 8
-; ASM-NEXT:    csetbounds cs0, ca1, 4
+; ASM-NEXT:    csw a1, 4(sp)
+; ASM-NEXT:    cincoffset a1, sp, 8
+; ASM-NEXT:    csetbounds s0, a1, 4
 ; ASM-NEXT:    j .LBB0_3
 ; ASM-NEXT:  .LBB0_2: # %block2
 ; ASM-NEXT:    li a0, 4
 ; ASM-NEXT:    li a1, 5
-; ASM-NEXT:    csw a0, 12(csp)
+; ASM-NEXT:    csw a0, 12(sp)
 ; ASM-NEXT:    li a0, 6
-; ASM-NEXT:    csw a1, 8(csp)
-; ASM-NEXT:    cincoffset ca1, csp, 12
-; ASM-NEXT:    csw a0, 4(csp)
-; ASM-NEXT:    cincoffset ca2, csp, 4
-; ASM-NEXT:    csetbounds ca0, ca1, 4
-; ASM-NEXT:    csetbounds cs0, ca2, 4
+; ASM-NEXT:    csw a1, 8(sp)
+; ASM-NEXT:    cincoffset a1, sp, 12
+; ASM-NEXT:    csw a0, 4(sp)
+; ASM-NEXT:    cincoffset a2, sp, 4
+; ASM-NEXT:    csetbounds a0, a1, 4
+; ASM-NEXT:    csetbounds s0, a2, 4
 ; ASM-NEXT:  .LBB0_3: # %phi_block
 ; ASM-NEXT:    ccall foo
-; ASM-NEXT:    cmove ca0, cs0
+; ASM-NEXT:    cmove a0, s0
 ; ASM-NEXT:    ccall foo
-; ASM-NEXT:    clc cra, 24(csp) # 8-byte Folded Reload
-; ASM-NEXT:    clc cs0, 16(csp) # 8-byte Folded Reload
-; ASM-NEXT:    cincoffset csp, csp, 32
+; ASM-NEXT:    clc ra, 24(sp) # 8-byte Folded Reload
+; ASM-NEXT:    clc s0, 16(sp) # 8-byte Folded Reload
+; ASM-NEXT:    cincoffset sp, sp, 32
 ; ASM-NEXT:    cret
 ; CHECK-LABEL: define void @test_phi
 ; CHECK-SAME: (i1 [[COND:%.*]]) addrspace(200) #[[ATTR1:[0-9]+]] {
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[ALLOCA1:%.*]] = alloca i32, align 4, addrspace(200)
-; CHECK-NEXT:    [[ALLOCA2:%.*]] = alloca i32, align 4, addrspace(200)
+; CHECK-NEXT:    [[ALLOa1:%.*]] = alloca i32, align 4, addrspace(200)
+; CHECK-NEXT:    [[ALLOa2:%.*]] = alloca i32, align 4, addrspace(200)
 ; CHECK-NEXT:    [[ALLOCA3:%.*]] = alloca i32, align 4, addrspace(200)
 ; CHECK-NEXT:    br i1 [[COND]], label [[BLOCK1:%.*]], label [[BLOCK2:%.*]]
 ; CHECK:       block1:
-; CHECK-NEXT:    store i32 1, ptr addrspace(200) [[ALLOCA1]], align 4
-; CHECK-NEXT:    store i32 2, ptr addrspace(200) [[ALLOCA2]], align 4
+; CHECK-NEXT:    store i32 1, ptr addrspace(200) [[ALLOa1]], align 4
+; CHECK-NEXT:    store i32 2, ptr addrspace(200) [[ALLOa2]], align 4
 ; CHECK-NEXT:    store i32 3, ptr addrspace(200) [[ALLOCA3]], align 4
-; CHECK-NEXT:    [[TMP0:%.*]] = call ptr addrspace(200) @llvm.cheri.bounded.stack.cap.i32(ptr addrspace(200) [[ALLOCA2]], i32 4)
+; CHECK-NEXT:    [[TMP0:%.*]] = call ptr addrspace(200) @llvm.cheri.bounded.stack.cap.i32(ptr addrspace(200) [[ALLOa2]], i32 4)
 ; CHECK-NEXT:    br label [[PHI_BLOCK:%.*]]
 ; CHECK:       block2:
-; CHECK-NEXT:    store i32 4, ptr addrspace(200) [[ALLOCA1]], align 4
-; CHECK-NEXT:    store i32 5, ptr addrspace(200) [[ALLOCA2]], align 4
+; CHECK-NEXT:    store i32 4, ptr addrspace(200) [[ALLOa1]], align 4
+; CHECK-NEXT:    store i32 5, ptr addrspace(200) [[ALLOa2]], align 4
 ; CHECK-NEXT:    store i32 6, ptr addrspace(200) [[ALLOCA3]], align 4
-; CHECK-NEXT:    [[TMP1:%.*]] = call ptr addrspace(200) @llvm.cheri.bounded.stack.cap.i32(ptr addrspace(200) [[ALLOCA1]], i32 4)
+; CHECK-NEXT:    [[TMP1:%.*]] = call ptr addrspace(200) @llvm.cheri.bounded.stack.cap.i32(ptr addrspace(200) [[ALLOa1]], i32 4)
 ; CHECK-NEXT:    [[TMP2:%.*]] = call ptr addrspace(200) @llvm.cheri.bounded.stack.cap.i32(ptr addrspace(200) [[ALLOCA3]], i32 4)
 ; CHECK-NEXT:    br label [[PHI_BLOCK]]
 ; CHECK:       phi_block:
@@ -75,26 +75,26 @@ define void @test_phi(i1 %cond) addrspace(200) nounwind {
 ; CHECK-NEXT:    call void @foo(ptr addrspace(200) [[VAL2]])
 ; CHECK-NEXT:    ret void
 entry:
-  %alloca1 = alloca i32, align 4, addrspace(200)
-  %alloca2 = alloca i32, align 4, addrspace(200)
+  %alloa1 = alloca i32, align 4, addrspace(200)
+  %alloa2 = alloca i32, align 4, addrspace(200)
   %alloca3 = alloca i32, align 4, addrspace(200)
   br i1 %cond, label %block1, label %block2
 
 block1:
-  store i32 1, ptr addrspace(200) %alloca1, align 4
-  store i32 2, ptr addrspace(200) %alloca2, align 4
+  store i32 1, ptr addrspace(200) %alloa1, align 4
+  store i32 2, ptr addrspace(200) %alloa2, align 4
   store i32 3, ptr addrspace(200) %alloca3, align 4
   br label %phi_block
 
 block2:
-  store i32 4, ptr addrspace(200) %alloca1, align 4
-  store i32 5, ptr addrspace(200) %alloca2, align 4
+  store i32 4, ptr addrspace(200) %alloa1, align 4
+  store i32 5, ptr addrspace(200) %alloa2, align 4
   store i32 6, ptr addrspace(200) %alloca3, align 4
   br label %phi_block
 
 phi_block:
-  %val1 = phi ptr addrspace(200) [ null, %block1 ], [ %alloca1, %block2 ]
-  %val2 = phi ptr addrspace(200) [ %alloca2, %block1 ], [ %alloca3, %block2 ]
+  %val1 = phi ptr addrspace(200) [ null, %block1 ], [ %alloa1, %block2 ]
+  %val2 = phi ptr addrspace(200) [ %alloa2, %block1 ], [ %alloca3, %block2 ]
   call void @foo(ptr addrspace(200) %val1)
   call void @foo(ptr addrspace(200) %val2)
   ret void
@@ -104,65 +104,65 @@ phi_block:
 define void @test_only_created_in_predecessor_block(i1 %cond) addrspace(200) nounwind {
 ; ASM-LABEL: test_only_created_in_predecessor_block:
 ; ASM:       # %bb.0: # %entry
-; ASM-NEXT:    cincoffset csp, csp, -16
-; ASM-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; ASM-NEXT:    cincoffset sp, sp, -16
+; ASM-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; ASM-NEXT:    andi a0, a0, 1
 ; ASM-NEXT:    beqz a0, .LBB1_2
 ; ASM-NEXT:  # %bb.1: # %block1
 ; ASM-NEXT:    li a0, 1
-; ASM-NEXT:    csw a0, 4(csp)
-; ASM-NEXT:    cincoffset ca0, csp, 4
+; ASM-NEXT:    csw a0, 4(sp)
+; ASM-NEXT:    cincoffset a0, sp, 4
 ; ASM-NEXT:    j .LBB1_3
 ; ASM-NEXT:  .LBB1_2: # %block2
 ; ASM-NEXT:    li a0, 5
-; ASM-NEXT:    csw a0, 0(csp)
-; ASM-NEXT:    cincoffset ca0, csp, 0
+; ASM-NEXT:    csw a0, 0(sp)
+; ASM-NEXT:    cincoffset a0, sp, 0
 ; ASM-NEXT:  .LBB1_3: # %phi_block
-; ASM-NEXT:    csetbounds ca0, ca0, 4
+; ASM-NEXT:    csetbounds a0, a0, 4
 ; ASM-NEXT:    ccall foo
-; ASM-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; ASM-NEXT:    cincoffset csp, csp, 16
+; ASM-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; ASM-NEXT:    cincoffset sp, sp, 16
 ; ASM-NEXT:    cret
 ; CHECK-LABEL: define void @test_only_created_in_predecessor_block
 ; CHECK-SAME: (i1 [[COND:%.*]]) addrspace(200) #[[ATTR1]] {
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[ALLOCA1:%.*]] = alloca i32, align 4, addrspace(200)
-; CHECK-NEXT:    [[ALLOCA2:%.*]] = alloca i32, align 4, addrspace(200)
+; CHECK-NEXT:    [[ALLOa1:%.*]] = alloca i32, align 4, addrspace(200)
+; CHECK-NEXT:    [[ALLOa2:%.*]] = alloca i32, align 4, addrspace(200)
 ; CHECK-NEXT:    br i1 [[COND]], label [[BLOCK1:%.*]], label [[BLOCK2:%.*]]
 ; CHECK:       block1:
-; CHECK-NEXT:    store i32 1, ptr addrspace(200) [[ALLOCA1]], align 4
-; CHECK-NEXT:    [[TMP0:%.*]] = call ptr addrspace(200) @llvm.cheri.bounded.stack.cap.i32(ptr addrspace(200) [[ALLOCA1]], i32 4)
+; CHECK-NEXT:    store i32 1, ptr addrspace(200) [[ALLOa1]], align 4
+; CHECK-NEXT:    [[TMP0:%.*]] = call ptr addrspace(200) @llvm.cheri.bounded.stack.cap.i32(ptr addrspace(200) [[ALLOa1]], i32 4)
 ; CHECK-NEXT:    br label [[PHI_BLOCK:%.*]]
 ; CHECK:       block2:
-; CHECK-NEXT:    store i32 5, ptr addrspace(200) [[ALLOCA2]], align 4
-; CHECK-NEXT:    [[TMP1:%.*]] = call ptr addrspace(200) @llvm.cheri.bounded.stack.cap.i32(ptr addrspace(200) [[ALLOCA2]], i32 4)
+; CHECK-NEXT:    store i32 5, ptr addrspace(200) [[ALLOa2]], align 4
+; CHECK-NEXT:    [[TMP1:%.*]] = call ptr addrspace(200) @llvm.cheri.bounded.stack.cap.i32(ptr addrspace(200) [[ALLOa2]], i32 4)
 ; CHECK-NEXT:    br label [[PHI_BLOCK]]
 ; CHECK:       phi_block:
 ; CHECK-NEXT:    [[VAL1:%.*]] = phi ptr addrspace(200) [ [[TMP0]], [[BLOCK1]] ], [ [[TMP1]], [[BLOCK2]] ]
 ; CHECK-NEXT:    call void @foo(ptr addrspace(200) [[VAL1]])
 ; CHECK-NEXT:    ret void
 entry:
-  %alloca1 = alloca i32, align 4, addrspace(200)
-  %alloca2 = alloca i32, align 4, addrspace(200)
+  %alloa1 = alloca i32, align 4, addrspace(200)
+  %alloa2 = alloca i32, align 4, addrspace(200)
   br i1 %cond, label %block1, label %block2
 
 block1:
-  store i32 1, ptr addrspace(200) %alloca1, align 4
+  store i32 1, ptr addrspace(200) %alloa1, align 4
   br label %phi_block
 
 block2:
-  store i32 5, ptr addrspace(200) %alloca2, align 4
+  store i32 5, ptr addrspace(200) %alloa2, align 4
   br label %phi_block
 
 phi_block:
-  %val1 = phi ptr addrspace(200) [ %alloca1, %block1 ], [ %alloca2, %block2 ]
+  %val1 = phi ptr addrspace(200) [ %alloa1, %block1 ], [ %alloa2, %block2 ]
   call void @foo(ptr addrspace(200) %val1)
   ret void
 }
 
 ; DBG: -Adding stack bounds since phi user needs bounds:   call void @foo(ptr addrspace(200) %val1)
-; DBG: test_phi: 1 of 3 users need bounds for   %alloca1 = alloca i32, align 4, addrspace(200)
+; DBG: test_phi: 1 of 3 users need bounds for   %alloa1 = alloca i32, align 4, addrspace(200)
 ; DBG: -Adding stack bounds since phi user needs bounds:   call void @foo(ptr addrspace(200) %val2)
-; DBG: test_phi: 1 of 3 users need bounds for   %alloca2 = alloca i32, align 4, addrspace(200)
+; DBG: test_phi: 1 of 3 users need bounds for   %alloa2 = alloca i32, align 4, addrspace(200)
 ; DBG: -Adding stack bounds since phi user needs bounds:   call void @foo(ptr addrspace(200) %val2)
 ; DBG: test_phi: 1 of 3 users need bounds for   %alloca3 = alloca i32, align 4, addrspace(200)
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/stack-spill-unnecessary.c.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/stack-spill-unnecessary.c.ll
index 33e440994739d..1cdac5d0fcf86 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/stack-spill-unnecessary.c.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/stack-spill-unnecessary.c.ll
@@ -18,19 +18,19 @@ declare void @multi_arg(i32 addrspace(200)* %start, i32 addrspace(200)* %end, i8
 define void @use_after_call() addrspace(200) nounwind {
 ; CHECK-LABEL: use_after_call:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    cincoffset csp, csp, -32
-; CHECK-NEXT:    csc cra, 24(csp) # 8-byte Folded Spill
-; CHECK-NEXT:    csc cs0, 16(csp) # 8-byte Folded Spill
-; CHECK-NEXT:    cincoffset ca0, csp, 12
+; CHECK-NEXT:    cincoffset sp, sp, -32
+; CHECK-NEXT:    csc ra, 24(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    csc s0, 16(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    cincoffset a0, sp, 12
 ; CHECK-NEXT:    li a1, 123
-; CHECK-NEXT:    csetbounds cs0, ca0, 4
-; CHECK-NEXT:    csw a1, 12(csp)
+; CHECK-NEXT:    csetbounds s0, a0, 4
+; CHECK-NEXT:    csw a1, 12(sp)
 ; CHECK-NEXT:    ccall foo
-; CHECK-NEXT:    cmove ca0, cs0
+; CHECK-NEXT:    cmove a0, s0
 ; CHECK-NEXT:    ccall one_arg
-; CHECK-NEXT:    clc cra, 24(csp) # 8-byte Folded Reload
-; CHECK-NEXT:    clc cs0, 16(csp) # 8-byte Folded Reload
-; CHECK-NEXT:    cincoffset csp, csp, 32
+; CHECK-NEXT:    clc ra, 24(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    clc s0, 16(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    cincoffset sp, sp, 32
 ; CHECK-NEXT:    cret
 ;
 ; HYBRID-LABEL: use_after_call:
@@ -55,23 +55,23 @@ define void @use_after_call() addrspace(200) nounwind {
 define void @use_after_call_no_store() addrspace(200) nounwind {
 ; CHECK-LABEL: use_after_call_no_store:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    cincoffset csp, csp, -32
-; CHECK-NEXT:    csc cra, 24(csp) # 8-byte Folded Spill
-; CHECK-NEXT:    csc cs0, 16(csp) # 8-byte Folded Spill
-; CHECK-NEXT:    csc cs1, 8(csp) # 8-byte Folded Spill
-; CHECK-NEXT:    cincoffset ca0, csp, 4
-; CHECK-NEXT:    cincoffset ca1, csp, 0
-; CHECK-NEXT:    csetbounds cs0, ca0, 4
-; CHECK-NEXT:    csetbounds cs1, ca1, 4
+; CHECK-NEXT:    cincoffset sp, sp, -32
+; CHECK-NEXT:    csc ra, 24(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    csc s0, 16(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    csc s1, 8(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    cincoffset a0, sp, 4
+; CHECK-NEXT:    cincoffset a1, sp, 0
+; CHECK-NEXT:    csetbounds s0, a0, 4
+; CHECK-NEXT:    csetbounds s1, a1, 4
 ; CHECK-NEXT:    ccall foo
-; CHECK-NEXT:    cmove ca0, cs0
+; CHECK-NEXT:    cmove a0, s0
 ; CHECK-NEXT:    ccall one_arg
-; CHECK-NEXT:    cmove ca0, cs1
+; CHECK-NEXT:    cmove a0, s1
 ; CHECK-NEXT:    ccall one_arg
-; CHECK-NEXT:    clc cra, 24(csp) # 8-byte Folded Reload
-; CHECK-NEXT:    clc cs0, 16(csp) # 8-byte Folded Reload
-; CHECK-NEXT:    clc cs1, 8(csp) # 8-byte Folded Reload
-; CHECK-NEXT:    cincoffset csp, csp, 32
+; CHECK-NEXT:    clc ra, 24(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    clc s0, 16(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    clc s1, 8(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    cincoffset sp, sp, 32
 ; CHECK-NEXT:    cret
 ;
 ; HYBRID-LABEL: use_after_call_no_store:
@@ -97,27 +97,27 @@ define void @use_after_call_no_store() addrspace(200) nounwind {
 define void @multi_use() addrspace(200) nounwind {
 ; CHECK-LABEL: multi_use:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    cincoffset csp, csp, -32
-; CHECK-NEXT:    csc cra, 24(csp) # 8-byte Folded Spill
-; CHECK-NEXT:    csc cs0, 16(csp) # 8-byte Folded Spill
-; CHECK-NEXT:    csc cs1, 8(csp) # 8-byte Folded Spill
-; CHECK-NEXT:    cincoffset ca0, csp, 4
-; CHECK-NEXT:    cincoffset ca1, csp, 0
-; CHECK-NEXT:    csetbounds cs0, ca0, 4
-; CHECK-NEXT:    csetbounds cs1, ca1, 4
+; CHECK-NEXT:    cincoffset sp, sp, -32
+; CHECK-NEXT:    csc ra, 24(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    csc s0, 16(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    csc s1, 8(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    cincoffset a0, sp, 4
+; CHECK-NEXT:    cincoffset a1, sp, 0
+; CHECK-NEXT:    csetbounds s0, a0, 4
+; CHECK-NEXT:    csetbounds s1, a1, 4
 ; CHECK-NEXT:    ccall foo
-; CHECK-NEXT:    cincoffset ca1, cs1, 4
-; CHECK-NEXT:    cincoffset ca2, cs1, 1
-; CHECK-NEXT:    cmove ca0, cs1
+; CHECK-NEXT:    cincoffset a1, s1, 4
+; CHECK-NEXT:    cincoffset a2, s1, 1
+; CHECK-NEXT:    cmove a0, s1
 ; CHECK-NEXT:    ccall multi_arg
-; CHECK-NEXT:    cmove ca0, cs0
+; CHECK-NEXT:    cmove a0, s0
 ; CHECK-NEXT:    ccall one_arg
-; CHECK-NEXT:    cmove ca0, cs1
+; CHECK-NEXT:    cmove a0, s1
 ; CHECK-NEXT:    ccall one_arg
-; CHECK-NEXT:    clc cra, 24(csp) # 8-byte Folded Reload
-; CHECK-NEXT:    clc cs0, 16(csp) # 8-byte Folded Reload
-; CHECK-NEXT:    clc cs1, 8(csp) # 8-byte Folded Reload
-; CHECK-NEXT:    cincoffset csp, csp, 32
+; CHECK-NEXT:    clc ra, 24(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    clc s0, 16(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    clc s1, 8(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    cincoffset sp, sp, 32
 ; CHECK-NEXT:    cret
 ;
 ; HYBRID-LABEL: multi_use:
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/stackframe-intrinsics.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/stackframe-intrinsics.ll
index a4a9fac07da78..3fa3940924c80 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/stackframe-intrinsics.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/stackframe-intrinsics.ll
@@ -9,15 +9,15 @@
 define dso_local ptr addrspace(200) @frameaddr() addrspace(200) nounwind {
 ; PURECAP-LABEL: frameaddr:
 ; PURECAP:       # %bb.0: # %entry
-; PURECAP-NEXT:    cincoffset csp, csp, -32
-; PURECAP-NEXT:    csc cra, 24(csp) # 8-byte Folded Spill
-; PURECAP-NEXT:    csc cs0, 16(csp) # 8-byte Folded Spill
-; PURECAP-NEXT:    cincoffset cs0, csp, 32
-; PURECAP-NEXT:    csc cs0, -32(cs0)
-; PURECAP-NEXT:    cmove ca0, cs0
-; PURECAP-NEXT:    clc cra, 24(csp) # 8-byte Folded Reload
-; PURECAP-NEXT:    clc cs0, 16(csp) # 8-byte Folded Reload
-; PURECAP-NEXT:    cincoffset csp, csp, 32
+; PURECAP-NEXT:    cincoffset sp, sp, -32
+; PURECAP-NEXT:    csc ra, 24(sp) # 8-byte Folded Spill
+; PURECAP-NEXT:    csc s0, 16(sp) # 8-byte Folded Spill
+; PURECAP-NEXT:    cincoffset s0, sp, 32
+; PURECAP-NEXT:    csc s0, -32(s0)
+; PURECAP-NEXT:    cmove a0, s0
+; PURECAP-NEXT:    clc ra, 24(sp) # 8-byte Folded Reload
+; PURECAP-NEXT:    clc s0, 16(sp) # 8-byte Folded Reload
+; PURECAP-NEXT:    cincoffset sp, sp, 32
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: frameaddr:
@@ -45,10 +45,10 @@ declare ptr addrspace(200) @llvm.frameaddress.p200(i32 immarg) addrspace(200)
 define dso_local ptr addrspace(200) @retaddr() addrspace(200) nounwind {
 ; PURECAP-LABEL: retaddr:
 ; PURECAP:       # %bb.0: # %entry
-; PURECAP-NEXT:    cincoffset csp, csp, -16
-; PURECAP-NEXT:    cmove ca0, cra
-; PURECAP-NEXT:    csc cra, 0(csp)
-; PURECAP-NEXT:    cincoffset csp, csp, 16
+; PURECAP-NEXT:    cincoffset sp, sp, -16
+; PURECAP-NEXT:    cmove a0, ra
+; PURECAP-NEXT:    csc ra, 0(sp)
+; PURECAP-NEXT:    cincoffset sp, sp, 16
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: retaddr:
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/strcpy-to-memcpy-no-tags.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/strcpy-to-memcpy-no-tags.ll
index c385acaf07e65..aa4ccd78c957b 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/strcpy-to-memcpy-no-tags.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/strcpy-to-memcpy-no-tags.ll
@@ -20,19 +20,19 @@ declare ptr addrspace(200) @stpncpy(ptr addrspace(200), ptr addrspace(200), i64)
 define void @test_strcpy_to_memcpy(ptr addrspace(200) align 4 %dst) addrspace(200) nounwind {
 ; CHECK-ASM-LABEL: test_strcpy_to_memcpy:
 ; CHECK-ASM:       # %bb.0: # %entry
-; CHECK-ASM-NEXT:    csb zero, 16(ca0)
+; CHECK-ASM-NEXT:    csb zero, 16(a0)
 ; CHECK-ASM-NEXT:    lui a1, 472870
 ; CHECK-ASM-NEXT:    addi a1, a1, 360
-; CHECK-ASM-NEXT:    csw a1, 12(ca0)
+; CHECK-ASM-NEXT:    csw a1, 12(a0)
 ; CHECK-ASM-NEXT:    lui a1, 406019
 ; CHECK-ASM-NEXT:    addi a1, a1, 1585
-; CHECK-ASM-NEXT:    csw a1, 8(ca0)
+; CHECK-ASM-NEXT:    csw a1, 8(a0)
 ; CHECK-ASM-NEXT:    lui a1, 133015
 ; CHECK-ASM-NEXT:    addi a1, a1, -908
-; CHECK-ASM-NEXT:    csw a1, 4(ca0)
+; CHECK-ASM-NEXT:    csw a1, 4(a0)
 ; CHECK-ASM-NEXT:    lui a1, 407064
 ; CHECK-ASM-NEXT:    addi a1, a1, -1947
-; CHECK-ASM-NEXT:    csw a1, 0(ca0)
+; CHECK-ASM-NEXT:    csw a1, 0(a0)
 ; CHECK-ASM-NEXT:    cret
 ; CHECK-IR-LABEL: define void @test_strcpy_to_memcpy
 ; CHECK-IR-SAME: (ptr addrspace(200) align 4 [[DST:%.*]]) addrspace(200) #[[ATTR1:[0-9]+]] {
@@ -48,19 +48,19 @@ entry:
 define void @test_stpcpy_to_memcpy(ptr addrspace(200) align 4 %dst) addrspace(200) nounwind {
 ; CHECK-ASM-LABEL: test_stpcpy_to_memcpy:
 ; CHECK-ASM:       # %bb.0: # %entry
-; CHECK-ASM-NEXT:    csb zero, 16(ca0)
+; CHECK-ASM-NEXT:    csb zero, 16(a0)
 ; CHECK-ASM-NEXT:    lui a1, 472870
 ; CHECK-ASM-NEXT:    addi a1, a1, 360
-; CHECK-ASM-NEXT:    csw a1, 12(ca0)
+; CHECK-ASM-NEXT:    csw a1, 12(a0)
 ; CHECK-ASM-NEXT:    lui a1, 406019
 ; CHECK-ASM-NEXT:    addi a1, a1, 1585
-; CHECK-ASM-NEXT:    csw a1, 8(ca0)
+; CHECK-ASM-NEXT:    csw a1, 8(a0)
 ; CHECK-ASM-NEXT:    lui a1, 133015
 ; CHECK-ASM-NEXT:    addi a1, a1, -908
-; CHECK-ASM-NEXT:    csw a1, 4(ca0)
+; CHECK-ASM-NEXT:    csw a1, 4(a0)
 ; CHECK-ASM-NEXT:    lui a1, 407064
 ; CHECK-ASM-NEXT:    addi a1, a1, -1947
-; CHECK-ASM-NEXT:    csw a1, 0(ca0)
+; CHECK-ASM-NEXT:    csw a1, 0(a0)
 ; CHECK-ASM-NEXT:    cret
 ; CHECK-IR-LABEL: define void @test_stpcpy_to_memcpy
 ; CHECK-IR-SAME: (ptr addrspace(200) align 4 [[DST:%.*]]) addrspace(200) #[[ATTR1]] {
@@ -76,21 +76,21 @@ entry:
 define void @test_strcat_to_memcpy(ptr addrspace(200) align 4 %dst) addrspace(200) nounwind {
 ; CHECK-ASM-LABEL: test_strcat_to_memcpy:
 ; CHECK-ASM:       # %bb.0: # %entry
-; CHECK-ASM-NEXT:    cincoffset csp, csp, -16
-; CHECK-ASM-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; CHECK-ASM-NEXT:    csc cs0, 0(csp) # 8-byte Folded Spill
-; CHECK-ASM-NEXT:    cmove cs0, ca0
+; CHECK-ASM-NEXT:    cincoffset sp, sp, -16
+; CHECK-ASM-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; CHECK-ASM-NEXT:    csc s0, 0(sp) # 8-byte Folded Spill
+; CHECK-ASM-NEXT:    cmove s0, a0
 ; CHECK-ASM-NEXT:    ccall strlen
-; CHECK-ASM-NEXT:    cincoffset ca0, cs0, a0
+; CHECK-ASM-NEXT:    cincoffset a0, s0, a0
 ; CHECK-ASM-NEXT:  .LBB2_1: # %entry
 ; CHECK-ASM-NEXT:    # Label of block must be emitted
-; CHECK-ASM-NEXT:    auipcc ca1, %captab_pcrel_hi(.Lstr)
-; CHECK-ASM-NEXT:    clc ca1, %pcrel_lo(.LBB2_1)(ca1)
+; CHECK-ASM-NEXT:    auipcc a1, %captab_pcrel_hi(.Lstr)
+; CHECK-ASM-NEXT:    clc a1, %pcrel_lo(.LBB2_1)(a1)
 ; CHECK-ASM-NEXT:    li a2, 17
 ; CHECK-ASM-NEXT:    ccall memcpy
-; CHECK-ASM-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; CHECK-ASM-NEXT:    clc cs0, 0(csp) # 8-byte Folded Reload
-; CHECK-ASM-NEXT:    cincoffset csp, csp, 16
+; CHECK-ASM-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; CHECK-ASM-NEXT:    clc s0, 0(sp) # 8-byte Folded Reload
+; CHECK-ASM-NEXT:    cincoffset sp, sp, 16
 ; CHECK-ASM-NEXT:    cret
 ; CHECK-IR-LABEL: define void @test_strcat_to_memcpy
 ; CHECK-IR-SAME: (ptr addrspace(200) align 4 [[DST:%.*]]) addrspace(200) #[[ATTR1]] {
@@ -109,17 +109,17 @@ entry:
 define void @test_strncpy_to_memcpy(ptr addrspace(200) align 4 %dst) addrspace(200) nounwind {
 ; CHECK-ASM-LABEL: test_strncpy_to_memcpy:
 ; CHECK-ASM:       # %bb.0: # %entry
-; CHECK-ASM-NEXT:    cincoffset csp, csp, -16
-; CHECK-ASM-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; CHECK-ASM-NEXT:    cincoffset sp, sp, -16
+; CHECK-ASM-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; CHECK-ASM-NEXT:  .LBB3_1: # %entry
 ; CHECK-ASM-NEXT:    # Label of block must be emitted
-; CHECK-ASM-NEXT:    auipcc ca1, %captab_pcrel_hi(.Lstr)
-; CHECK-ASM-NEXT:    clc ca1, %pcrel_lo(.LBB3_1)(ca1)
+; CHECK-ASM-NEXT:    auipcc a1, %captab_pcrel_hi(.Lstr)
+; CHECK-ASM-NEXT:    clc a1, %pcrel_lo(.LBB3_1)(a1)
 ; CHECK-ASM-NEXT:    li a2, 17
 ; CHECK-ASM-NEXT:    li a3, 0
 ; CHECK-ASM-NEXT:    ccall strncpy
-; CHECK-ASM-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; CHECK-ASM-NEXT:    cincoffset csp, csp, 16
+; CHECK-ASM-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; CHECK-ASM-NEXT:    cincoffset sp, sp, 16
 ; CHECK-ASM-NEXT:    cret
 ; CHECK-IR-LABEL: define void @test_strncpy_to_memcpy
 ; CHECK-IR-SAME: (ptr addrspace(200) align 4 [[DST:%.*]]) addrspace(200) #[[ATTR1]] {
@@ -136,17 +136,17 @@ entry:
 define void @test_stpncpy_to_memcpy(ptr addrspace(200) align 4 %dst) addrspace(200) nounwind {
 ; CHECK-ASM-LABEL: test_stpncpy_to_memcpy:
 ; CHECK-ASM:       # %bb.0: # %entry
-; CHECK-ASM-NEXT:    cincoffset csp, csp, -16
-; CHECK-ASM-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; CHECK-ASM-NEXT:    cincoffset sp, sp, -16
+; CHECK-ASM-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; CHECK-ASM-NEXT:  .LBB4_1: # %entry
 ; CHECK-ASM-NEXT:    # Label of block must be emitted
-; CHECK-ASM-NEXT:    auipcc ca1, %captab_pcrel_hi(.Lstr)
-; CHECK-ASM-NEXT:    clc ca1, %pcrel_lo(.LBB4_1)(ca1)
+; CHECK-ASM-NEXT:    auipcc a1, %captab_pcrel_hi(.Lstr)
+; CHECK-ASM-NEXT:    clc a1, %pcrel_lo(.LBB4_1)(a1)
 ; CHECK-ASM-NEXT:    li a2, 17
 ; CHECK-ASM-NEXT:    li a3, 0
 ; CHECK-ASM-NEXT:    ccall stpncpy
-; CHECK-ASM-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; CHECK-ASM-NEXT:    cincoffset csp, csp, 16
+; CHECK-ASM-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; CHECK-ASM-NEXT:    cincoffset sp, sp, 16
 ; CHECK-ASM-NEXT:    cret
 ; CHECK-IR-LABEL: define void @test_stpncpy_to_memcpy
 ; CHECK-IR-SAME: (ptr addrspace(200) align 4 [[DST:%.*]]) addrspace(200) #[[ATTR1]] {
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/subobject-bounds-redundant-setbounds.c.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/subobject-bounds-redundant-setbounds.c.ll
index 21dc45b7c520d..7aca22da5fd3d 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/subobject-bounds-redundant-setbounds.c.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/subobject-bounds-redundant-setbounds.c.ll
@@ -38,7 +38,7 @@ define void @use_inline(ptr addrspace(200) captures(none) %arg) local_unnamed_ad
 ; ASM-LABEL: use_inline:
 ; ASM:       # %bb.0:
 ; ASM-NEXT:    li a1, 2
-; ASM-NEXT:    csw a1, 0(ca0)
+; ASM-NEXT:    csw a1, 0(a0)
 ; ASM-NEXT:    cret
 ; CHECK-LABEL: define {{[^@]+}}@use_inline
 ; CHECK-SAME: (ptr addrspace(200) captures(none) [[ARG:%.*]]) local_unnamed_addr addrspace(200) #[[ATTR0:[0-9]+]] {
@@ -52,17 +52,17 @@ define void @use_inline(ptr addrspace(200) captures(none) %arg) local_unnamed_ad
 define signext i32 @stack_array() local_unnamed_addr addrspace(200) nounwind {
 ; ASM-LABEL: stack_array:
 ; ASM:       # %bb.0:
-; ASM-NEXT:    cincoffset csp, csp, -64
-; ASM-NEXT:    csc cra, 56(csp) # 8-byte Folded Spill
-; ASM-NEXT:    csc cs0, 48(csp) # 8-byte Folded Spill
-; ASM-NEXT:    cincoffset ca0, csp, 8
-; ASM-NEXT:    csetbounds cs0, ca0, 40
-; ASM-NEXT:    cmove ca0, cs0
+; ASM-NEXT:    cincoffset sp, sp, -64
+; ASM-NEXT:    csc ra, 56(sp) # 8-byte Folded Spill
+; ASM-NEXT:    csc s0, 48(sp) # 8-byte Folded Spill
+; ASM-NEXT:    cincoffset a0, sp, 8
+; ASM-NEXT:    csetbounds s0, a0, 40
+; ASM-NEXT:    cmove a0, s0
 ; ASM-NEXT:    ccall use
-; ASM-NEXT:    clw a0, 20(cs0)
-; ASM-NEXT:    clc cra, 56(csp) # 8-byte Folded Reload
-; ASM-NEXT:    clc cs0, 48(csp) # 8-byte Folded Reload
-; ASM-NEXT:    cincoffset csp, csp, 64
+; ASM-NEXT:    clw a0, 20(s0)
+; ASM-NEXT:    clc ra, 56(sp) # 8-byte Folded Reload
+; ASM-NEXT:    clc s0, 48(sp) # 8-byte Folded Reload
+; ASM-NEXT:    cincoffset sp, sp, 64
 ; ASM-NEXT:    cret
 ; CHECK-LABEL: define signext i32 @stack_array
 ; CHECK-SAME: () local_unnamed_addr addrspace(200) #[[ATTR1:[0-9]+]] {
@@ -104,16 +104,16 @@ declare void @llvm.lifetime.end.p200(i64 immarg, ptr addrspace(200) captures(non
 define signext i32 @stack_int() local_unnamed_addr addrspace(200) nounwind {
 ; ASM-LABEL: stack_int:
 ; ASM:       # %bb.0:
-; ASM-NEXT:    cincoffset csp, csp, -16
-; ASM-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; ASM-NEXT:    cincoffset sp, sp, -16
+; ASM-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; ASM-NEXT:    li a0, 1
-; ASM-NEXT:    csw a0, 4(csp)
-; ASM-NEXT:    cincoffset ca0, csp, 4
-; ASM-NEXT:    csetbounds ca0, ca0, 4
+; ASM-NEXT:    csw a0, 4(sp)
+; ASM-NEXT:    cincoffset a0, sp, 4
+; ASM-NEXT:    csetbounds a0, a0, 4
 ; ASM-NEXT:    ccall use
-; ASM-NEXT:    clw a0, 4(csp)
-; ASM-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; ASM-NEXT:    cincoffset csp, csp, 16
+; ASM-NEXT:    clw a0, 4(sp)
+; ASM-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; ASM-NEXT:    cincoffset sp, sp, 16
 ; ASM-NEXT:    cret
 ; CHECK-LABEL: define signext i32 @stack_int
 ; CHECK-SAME: () local_unnamed_addr addrspace(200) #[[ATTR1]] {
@@ -153,15 +153,15 @@ define signext i32 @stack_int() local_unnamed_addr addrspace(200) nounwind {
 define signext i32 @stack_int_inlined() local_unnamed_addr addrspace(200) nounwind {
 ; ASM-LABEL: stack_int_inlined:
 ; ASM:       # %bb.0:
-; ASM-NEXT:    cincoffset csp, csp, -16
+; ASM-NEXT:    cincoffset sp, sp, -16
 ; ASM-NEXT:    li a0, 1
-; ASM-NEXT:    cincoffset ca1, csp, 12
-; ASM-NEXT:    csw a0, 12(csp)
-; ASM-NEXT:    csetbounds ca0, ca1, 4
+; ASM-NEXT:    cincoffset a1, sp, 12
+; ASM-NEXT:    csw a0, 12(sp)
+; ASM-NEXT:    csetbounds a0, a1, 4
 ; ASM-NEXT:    li a1, 2
-; ASM-NEXT:    csw a1, 0(ca0)
-; ASM-NEXT:    clw a0, 12(csp)
-; ASM-NEXT:    cincoffset csp, csp, 16
+; ASM-NEXT:    csw a1, 0(a0)
+; ASM-NEXT:    clw a0, 12(sp)
+; ASM-NEXT:    cincoffset sp, sp, 16
 ; ASM-NEXT:    cret
 ; CHECK-LABEL: define signext i32 @stack_int_inlined
 ; CHECK-SAME: () local_unnamed_addr addrspace(200) #[[ATTR1]] {
@@ -201,14 +201,14 @@ define signext i32 @stack_int_inlined() local_unnamed_addr addrspace(200) nounwi
 define signext i32 @out_of_bounds_setbounds() local_unnamed_addr addrspace(200) nounwind {
 ; ASM-LABEL: out_of_bounds_setbounds:
 ; ASM:       # %bb.0:
-; ASM-NEXT:    cincoffset csp, csp, -16
-; ASM-NEXT:    cincoffset ca0, csp, 12
-; ASM-NEXT:    csetbounds ca0, ca0, 4
-; ASM-NEXT:    csetbounds ca0, ca0, 5
+; ASM-NEXT:    cincoffset sp, sp, -16
+; ASM-NEXT:    cincoffset a0, sp, 12
+; ASM-NEXT:    csetbounds a0, a0, 4
+; ASM-NEXT:    csetbounds a0, a0, 5
 ; ASM-NEXT:    li a1, 2
-; ASM-NEXT:    csw a1, 0(ca0)
-; ASM-NEXT:    clw a0, 12(csp)
-; ASM-NEXT:    cincoffset csp, csp, 16
+; ASM-NEXT:    csw a1, 0(a0)
+; ASM-NEXT:    clw a0, 12(sp)
+; ASM-NEXT:    cincoffset sp, sp, 16
 ; ASM-NEXT:    cret
 ; CHECK-LABEL: define signext i32 @out_of_bounds_setbounds
 ; CHECK-SAME: () local_unnamed_addr addrspace(200) #[[ATTR1]] {
@@ -240,16 +240,16 @@ define signext i32 @out_of_bounds_setbounds() local_unnamed_addr addrspace(200)
 define signext i32 @setbounds_escapes() local_unnamed_addr addrspace(200) nounwind {
 ; ASM-LABEL: setbounds_escapes:
 ; ASM:       # %bb.0:
-; ASM-NEXT:    cincoffset csp, csp, -16
-; ASM-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; ASM-NEXT:    cincoffset ca0, csp, 4
-; ASM-NEXT:    csetbounds ca0, ca0, 4
+; ASM-NEXT:    cincoffset sp, sp, -16
+; ASM-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; ASM-NEXT:    cincoffset a0, sp, 4
+; ASM-NEXT:    csetbounds a0, a0, 4
 ; ASM-NEXT:    li a1, 2
-; ASM-NEXT:    csw a1, 0(ca0)
+; ASM-NEXT:    csw a1, 0(a0)
 ; ASM-NEXT:    ccall use
-; ASM-NEXT:    clw a0, 4(csp)
-; ASM-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; ASM-NEXT:    cincoffset csp, csp, 16
+; ASM-NEXT:    clw a0, 4(sp)
+; ASM-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; ASM-NEXT:    cincoffset sp, sp, 16
 ; ASM-NEXT:    cret
 ; CHECK-LABEL: define signext i32 @setbounds_escapes
 ; CHECK-SAME: () local_unnamed_addr addrspace(200) #[[ATTR1]] {
@@ -282,10 +282,10 @@ define signext i32 @setbounds_escapes() local_unnamed_addr addrspace(200) nounwi
 define void @assume_aligned() local_unnamed_addr addrspace(200) nounwind {
 ; ASM-LABEL: assume_aligned:
 ; ASM:       # %bb.0:
-; ASM-NEXT:    cincoffset csp, csp, -16
+; ASM-NEXT:    cincoffset sp, sp, -16
 ; ASM-NEXT:    li a0, 1
-; ASM-NEXT:    csw a0, 12(csp)
-; ASM-NEXT:    cincoffset csp, csp, 16
+; ASM-NEXT:    csw a0, 12(sp)
+; ASM-NEXT:    cincoffset sp, sp, 16
 ; ASM-NEXT:    cret
 ; CHECK-LABEL: define void @assume_aligned
 ; CHECK-SAME: () local_unnamed_addr addrspace(200) #[[ATTR1]] {
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/trunc-load.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/trunc-load.ll
index bba2cc391d1a0..c48d6e157a081 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/trunc-load.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/trunc-load.ll
@@ -6,12 +6,12 @@
 define zeroext i16 @trunc_load_zext(i32 addrspace(200)* %p) {
 ; PURECAP-LABEL: trunc_load_zext:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    clhu a0, 0(ca0)
+; PURECAP-NEXT:    clhu a0, 0(a0)
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: trunc_load_zext:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    lhu.cap a0, (ca0)
+; HYBRID-NEXT:    lhu.cap a0, (a0)
 ; HYBRID-NEXT:    ret
   %1 = load i32, i32 addrspace(200)* %p
   %2 = trunc i32 %1 to i16
@@ -21,12 +21,12 @@ define zeroext i16 @trunc_load_zext(i32 addrspace(200)* %p) {
 define signext i16 @trunc_load_sext(i32 addrspace(200)* %p) {
 ; PURECAP-LABEL: trunc_load_sext:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    clh a0, 0(ca0)
+; PURECAP-NEXT:    clh a0, 0(a0)
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: trunc_load_sext:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    lh.cap a0, (ca0)
+; HYBRID-NEXT:    lh.cap a0, (a0)
 ; HYBRID-NEXT:    ret
   %1 = load i32, i32 addrspace(200)* %p
   %2 = trunc i32 %1 to i16
@@ -36,13 +36,13 @@ define signext i16 @trunc_load_sext(i32 addrspace(200)* %p) {
 define zeroext i16 @trunc_load_gep_zext(i32 addrspace(200)* %p) {
 ; PURECAP-LABEL: trunc_load_gep_zext:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    clhu a0, 4(ca0)
+; PURECAP-NEXT:    clhu a0, 4(a0)
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: trunc_load_gep_zext:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    cincoffset ca0, ca0, 4
-; HYBRID-NEXT:    lhu.cap a0, (ca0)
+; HYBRID-NEXT:    cincoffset a0, a0, 4
+; HYBRID-NEXT:    lhu.cap a0, (a0)
 ; HYBRID-NEXT:    ret
   %1 = getelementptr i32, i32 addrspace(200)* %p, i32 1
   %2 = load i32, i32 addrspace(200)* %1
@@ -53,13 +53,13 @@ define zeroext i16 @trunc_load_gep_zext(i32 addrspace(200)* %p) {
 define signext i16 @trunc_load_gep_sext(i32 addrspace(200)* %p) {
 ; PURECAP-LABEL: trunc_load_gep_sext:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    clh a0, 4(ca0)
+; PURECAP-NEXT:    clh a0, 4(a0)
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: trunc_load_gep_sext:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    cincoffset ca0, ca0, 4
-; HYBRID-NEXT:    lh.cap a0, (ca0)
+; HYBRID-NEXT:    cincoffset a0, a0, 4
+; HYBRID-NEXT:    lh.cap a0, (a0)
 ; HYBRID-NEXT:    ret
   %1 = getelementptr i32, i32 addrspace(200)* %p, i32 1
   %2 = load i32, i32 addrspace(200)* %1
@@ -70,13 +70,13 @@ define signext i16 @trunc_load_gep_sext(i32 addrspace(200)* %p) {
 define zeroext i16 @trunc_lshr_load_zext(i32 addrspace(200)* %p) {
 ; PURECAP-LABEL: trunc_lshr_load_zext:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    clhu a0, 2(ca0)
+; PURECAP-NEXT:    clhu a0, 2(a0)
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: trunc_lshr_load_zext:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    cincoffset ca0, ca0, 2
-; HYBRID-NEXT:    lhu.cap a0, (ca0)
+; HYBRID-NEXT:    cincoffset a0, a0, 2
+; HYBRID-NEXT:    lhu.cap a0, (a0)
 ; HYBRID-NEXT:    ret
   %1 = load i32, i32 addrspace(200)* %p
   %2 = lshr i32 %1, 16
@@ -87,13 +87,13 @@ define zeroext i16 @trunc_lshr_load_zext(i32 addrspace(200)* %p) {
 define signext i16 @trunc_lshr_load_sext(i32 addrspace(200)* %p) {
 ; PURECAP-LABEL: trunc_lshr_load_sext:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    clh a0, 2(ca0)
+; PURECAP-NEXT:    clh a0, 2(a0)
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: trunc_lshr_load_sext:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    cincoffset ca0, ca0, 2
-; HYBRID-NEXT:    lh.cap a0, (ca0)
+; HYBRID-NEXT:    cincoffset a0, a0, 2
+; HYBRID-NEXT:    lh.cap a0, (a0)
 ; HYBRID-NEXT:    ret
   %1 = load i32, i32 addrspace(200)* %p
   %2 = lshr i32 %1, 16
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/unaligned-loads-stores-hybrid.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/unaligned-loads-stores-hybrid.ll
index 4589ffe5a6707..266652b037063 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/unaligned-loads-stores-hybrid.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/unaligned-loads-stores-hybrid.ll
@@ -13,34 +13,34 @@ define i64 @load_global_i64_align_1(i64 %y) addrspace(200) nounwind {
 ; CHECK-NEXT:  .Lpcrel_hi0:
 ; CHECK-NEXT:    auipc a0, %got_pcrel_hi(a1)
 ; CHECK-NEXT:    lw a0, %pcrel_lo(.Lpcrel_hi0)(a0)
-; CHECK-NEXT:    cspecialr ca1, ddc
+; CHECK-NEXT:    cspecialr a1, ddc
 ; CHECK-NEXT:    bnez a0, .LBB0_2
 ; CHECK-NEXT:  # %bb.1:
-; CHECK-NEXT:    cmove ca0, cnull
+; CHECK-NEXT:    cmove a0, zero
 ; CHECK-NEXT:    j .LBB0_3
 ; CHECK-NEXT:  .LBB0_2:
-; CHECK-NEXT:    csetaddr ca0, ca1, a0
+; CHECK-NEXT:    csetaddr a0, a1, a0
 ; CHECK-NEXT:  .LBB0_3:
-; CHECK-NEXT:    lbu.cap a1, (ca0)
-; CHECK-NEXT:    cincoffset ca2, ca0, 1
-; CHECK-NEXT:    cincoffset ca3, ca0, 2
-; CHECK-NEXT:    cincoffset ca4, ca0, 3
-; CHECK-NEXT:    lbu.cap a2, (ca2)
-; CHECK-NEXT:    cincoffset ca5, ca0, 4
-; CHECK-NEXT:    lbu.cap a3, (ca3)
-; CHECK-NEXT:    lbu.cap a4, (ca4)
+; CHECK-NEXT:    lbu.cap a1, (a0)
+; CHECK-NEXT:    cincoffset a2, a0, 1
+; CHECK-NEXT:    cincoffset a3, a0, 2
+; CHECK-NEXT:    cincoffset a4, a0, 3
+; CHECK-NEXT:    lbu.cap a2, (a2)
+; CHECK-NEXT:    cincoffset a5, a0, 4
+; CHECK-NEXT:    lbu.cap a3, (a3)
+; CHECK-NEXT:    lbu.cap a4, (a4)
 ; CHECK-NEXT:    slli a2, a2, 8
 ; CHECK-NEXT:    or a1, a2, a1
-; CHECK-NEXT:    cincoffset ca2, ca0, 5
+; CHECK-NEXT:    cincoffset a2, a0, 5
 ; CHECK-NEXT:    slli a3, a3, 16
 ; CHECK-NEXT:    slli a4, a4, 24
 ; CHECK-NEXT:    or a3, a4, a3
-; CHECK-NEXT:    cincoffset ca4, ca0, 6
-; CHECK-NEXT:    cincoffset ca0, ca0, 7
-; CHECK-NEXT:    lbu.cap a2, (ca2)
-; CHECK-NEXT:    lbu.cap a5, (ca5)
-; CHECK-NEXT:    lbu.cap a4, (ca4)
-; CHECK-NEXT:    lbu.cap a0, (ca0)
+; CHECK-NEXT:    cincoffset a4, a0, 6
+; CHECK-NEXT:    cincoffset a0, a0, 7
+; CHECK-NEXT:    lbu.cap a2, (a2)
+; CHECK-NEXT:    lbu.cap a5, (a5)
+; CHECK-NEXT:    lbu.cap a4, (a4)
+; CHECK-NEXT:    lbu.cap a0, (a0)
 ; CHECK-NEXT:    slli a2, a2, 8
 ; CHECK-NEXT:    or a2, a2, a5
 ; CHECK-NEXT:    slli a4, a4, 16
@@ -59,21 +59,21 @@ define i64 @load_global_i64_align_2(i64 %y) addrspace(200) nounwind {
 ; CHECK-NEXT:  .Lpcrel_hi1:
 ; CHECK-NEXT:    auipc a0, %got_pcrel_hi(a2)
 ; CHECK-NEXT:    lw a0, %pcrel_lo(.Lpcrel_hi1)(a0)
-; CHECK-NEXT:    cspecialr ca1, ddc
+; CHECK-NEXT:    cspecialr a1, ddc
 ; CHECK-NEXT:    bnez a0, .LBB1_2
 ; CHECK-NEXT:  # %bb.1:
-; CHECK-NEXT:    cmove ca0, cnull
+; CHECK-NEXT:    cmove a0, zero
 ; CHECK-NEXT:    j .LBB1_3
 ; CHECK-NEXT:  .LBB1_2:
-; CHECK-NEXT:    csetaddr ca0, ca1, a0
+; CHECK-NEXT:    csetaddr a0, a1, a0
 ; CHECK-NEXT:  .LBB1_3:
-; CHECK-NEXT:    lhu.cap a1, (ca0)
-; CHECK-NEXT:    cincoffset ca2, ca0, 2
-; CHECK-NEXT:    cincoffset ca3, ca0, 4
-; CHECK-NEXT:    lhu.cap a2, (ca2)
-; CHECK-NEXT:    cincoffset ca0, ca0, 6
-; CHECK-NEXT:    lhu.cap a4, (ca0)
-; CHECK-NEXT:    lhu.cap a3, (ca3)
+; CHECK-NEXT:    lhu.cap a1, (a0)
+; CHECK-NEXT:    cincoffset a2, a0, 2
+; CHECK-NEXT:    cincoffset a3, a0, 4
+; CHECK-NEXT:    lhu.cap a2, (a2)
+; CHECK-NEXT:    cincoffset a0, a0, 6
+; CHECK-NEXT:    lhu.cap a4, (a0)
+; CHECK-NEXT:    lhu.cap a3, (a3)
 ; CHECK-NEXT:    slli a0, a2, 16
 ; CHECK-NEXT:    or a0, a0, a1
 ; CHECK-NEXT:    slli a1, a4, 16
@@ -89,17 +89,17 @@ define i64 @load_global_i64_align_4(i64 %y) addrspace(200) nounwind {
 ; CHECK-NEXT:  .Lpcrel_hi2:
 ; CHECK-NEXT:    auipc a0, %got_pcrel_hi(a4)
 ; CHECK-NEXT:    lw a0, %pcrel_lo(.Lpcrel_hi2)(a0)
-; CHECK-NEXT:    cspecialr ca1, ddc
+; CHECK-NEXT:    cspecialr a1, ddc
 ; CHECK-NEXT:    bnez a0, .LBB2_2
 ; CHECK-NEXT:  # %bb.1:
-; CHECK-NEXT:    cmove ca1, cnull
+; CHECK-NEXT:    cmove a1, zero
 ; CHECK-NEXT:    j .LBB2_3
 ; CHECK-NEXT:  .LBB2_2:
-; CHECK-NEXT:    csetaddr ca1, ca1, a0
+; CHECK-NEXT:    csetaddr a1, a1, a0
 ; CHECK-NEXT:  .LBB2_3:
-; CHECK-NEXT:    lw.cap a0, (ca1)
-; CHECK-NEXT:    cincoffset ca1, ca1, 4
-; CHECK-NEXT:    lw.cap a1, (ca1)
+; CHECK-NEXT:    lw.cap a0, (a1)
+; CHECK-NEXT:    cincoffset a1, a1, 4
+; CHECK-NEXT:    lw.cap a1, (a1)
 ; CHECK-NEXT:    ret
   %ret = load i64, i64 addrspace(200)* addrspacecast(i64* @a4 to i64 addrspace(200)*), align 4
   ret i64 %ret
@@ -111,17 +111,17 @@ define i64 @load_global_i64_align_8(i64 %y) addrspace(200) nounwind {
 ; CHECK-NEXT:  .Lpcrel_hi3:
 ; CHECK-NEXT:    auipc a0, %got_pcrel_hi(a8)
 ; CHECK-NEXT:    lw a0, %pcrel_lo(.Lpcrel_hi3)(a0)
-; CHECK-NEXT:    cspecialr ca1, ddc
+; CHECK-NEXT:    cspecialr a1, ddc
 ; CHECK-NEXT:    bnez a0, .LBB3_2
 ; CHECK-NEXT:  # %bb.1:
-; CHECK-NEXT:    cmove ca1, cnull
+; CHECK-NEXT:    cmove a1, zero
 ; CHECK-NEXT:    j .LBB3_3
 ; CHECK-NEXT:  .LBB3_2:
-; CHECK-NEXT:    csetaddr ca1, ca1, a0
+; CHECK-NEXT:    csetaddr a1, a1, a0
 ; CHECK-NEXT:  .LBB3_3:
-; CHECK-NEXT:    lw.cap a0, (ca1)
-; CHECK-NEXT:    cincoffset ca1, ca1, 4
-; CHECK-NEXT:    lw.cap a1, (ca1)
+; CHECK-NEXT:    lw.cap a0, (a1)
+; CHECK-NEXT:    cincoffset a1, a1, 4
+; CHECK-NEXT:    lw.cap a1, (a1)
 ; CHECK-NEXT:    ret
   %ret = load i64, i64 addrspace(200)* addrspacecast(i64* @a8 to i64 addrspace(200)*), align 8
   ret i64 %ret
@@ -133,35 +133,35 @@ define void @store_global_i64_align_1(i64 %y) addrspace(200) nounwind {
 ; CHECK-NEXT:  .Lpcrel_hi4:
 ; CHECK-NEXT:    auipc a2, %got_pcrel_hi(a1)
 ; CHECK-NEXT:    lw a2, %pcrel_lo(.Lpcrel_hi4)(a2)
-; CHECK-NEXT:    cspecialr ca3, ddc
+; CHECK-NEXT:    cspecialr a3, ddc
 ; CHECK-NEXT:    bnez a2, .LBB4_2
 ; CHECK-NEXT:  # %bb.1:
-; CHECK-NEXT:    cmove ca2, cnull
+; CHECK-NEXT:    cmove a2, zero
 ; CHECK-NEXT:    j .LBB4_3
 ; CHECK-NEXT:  .LBB4_2:
-; CHECK-NEXT:    csetaddr ca2, ca3, a2
+; CHECK-NEXT:    csetaddr a2, a3, a2
 ; CHECK-NEXT:  .LBB4_3:
-; CHECK-NEXT:    sb.cap a0, (ca2)
-; CHECK-NEXT:    cincoffset ca3, ca2, 7
+; CHECK-NEXT:    sb.cap a0, (a2)
+; CHECK-NEXT:    cincoffset a3, a2, 7
 ; CHECK-NEXT:    srli a4, a1, 24
-; CHECK-NEXT:    sb.cap a4, (ca3)
-; CHECK-NEXT:    cincoffset ca3, ca2, 6
+; CHECK-NEXT:    sb.cap a4, (a3)
+; CHECK-NEXT:    cincoffset a3, a2, 6
 ; CHECK-NEXT:    srli a4, a1, 16
-; CHECK-NEXT:    sb.cap a4, (ca3)
-; CHECK-NEXT:    cincoffset ca3, ca2, 5
+; CHECK-NEXT:    sb.cap a4, (a3)
+; CHECK-NEXT:    cincoffset a3, a2, 5
 ; CHECK-NEXT:    srli a4, a1, 8
-; CHECK-NEXT:    sb.cap a4, (ca3)
-; CHECK-NEXT:    cincoffset ca3, ca2, 4
-; CHECK-NEXT:    cincoffset ca4, ca2, 3
-; CHECK-NEXT:    sb.cap a1, (ca3)
+; CHECK-NEXT:    sb.cap a4, (a3)
+; CHECK-NEXT:    cincoffset a3, a2, 4
+; CHECK-NEXT:    cincoffset a4, a2, 3
+; CHECK-NEXT:    sb.cap a1, (a3)
 ; CHECK-NEXT:    srli a1, a0, 24
-; CHECK-NEXT:    cincoffset ca3, ca2, 2
-; CHECK-NEXT:    sb.cap a1, (ca4)
+; CHECK-NEXT:    cincoffset a3, a2, 2
+; CHECK-NEXT:    sb.cap a1, (a4)
 ; CHECK-NEXT:    srli a1, a0, 16
-; CHECK-NEXT:    cincoffset ca2, ca2, 1
+; CHECK-NEXT:    cincoffset a2, a2, 1
 ; CHECK-NEXT:    srli a0, a0, 8
-; CHECK-NEXT:    sb.cap a1, (ca3)
-; CHECK-NEXT:    sb.cap a0, (ca2)
+; CHECK-NEXT:    sb.cap a1, (a3)
+; CHECK-NEXT:    sb.cap a0, (a2)
 ; CHECK-NEXT:    ret
   store i64 %y, i64 addrspace(200)* addrspacecast(i64* @a1 to i64 addrspace(200)*), align 1
   ret void
@@ -173,23 +173,23 @@ define void @store_global_i64_align_2(i64 %y) addrspace(200) nounwind {
 ; CHECK-NEXT:  .Lpcrel_hi5:
 ; CHECK-NEXT:    auipc a2, %got_pcrel_hi(a2)
 ; CHECK-NEXT:    lw a2, %pcrel_lo(.Lpcrel_hi5)(a2)
-; CHECK-NEXT:    cspecialr ca3, ddc
+; CHECK-NEXT:    cspecialr a3, ddc
 ; CHECK-NEXT:    bnez a2, .LBB5_2
 ; CHECK-NEXT:  # %bb.1:
-; CHECK-NEXT:    cmove ca2, cnull
+; CHECK-NEXT:    cmove a2, zero
 ; CHECK-NEXT:    j .LBB5_3
 ; CHECK-NEXT:  .LBB5_2:
-; CHECK-NEXT:    csetaddr ca2, ca3, a2
+; CHECK-NEXT:    csetaddr a2, a3, a2
 ; CHECK-NEXT:  .LBB5_3:
-; CHECK-NEXT:    sh.cap a0, (ca2)
-; CHECK-NEXT:    cincoffset ca3, ca2, 6
+; CHECK-NEXT:    sh.cap a0, (a2)
+; CHECK-NEXT:    cincoffset a3, a2, 6
 ; CHECK-NEXT:    srli a4, a1, 16
-; CHECK-NEXT:    sh.cap a4, (ca3)
-; CHECK-NEXT:    cincoffset ca3, ca2, 4
-; CHECK-NEXT:    cincoffset ca2, ca2, 2
+; CHECK-NEXT:    sh.cap a4, (a3)
+; CHECK-NEXT:    cincoffset a3, a2, 4
+; CHECK-NEXT:    cincoffset a2, a2, 2
 ; CHECK-NEXT:    srli a0, a0, 16
-; CHECK-NEXT:    sh.cap a1, (ca3)
-; CHECK-NEXT:    sh.cap a0, (ca2)
+; CHECK-NEXT:    sh.cap a1, (a3)
+; CHECK-NEXT:    sh.cap a0, (a2)
 ; CHECK-NEXT:    ret
   store i64 %y, i64 addrspace(200)* addrspacecast(i64* @a2 to i64 addrspace(200)*), align 2
   ret void
@@ -201,17 +201,17 @@ define void @store_global_i64_align_4(i64 %y) addrspace(200) nounwind {
 ; CHECK-NEXT:  .Lpcrel_hi6:
 ; CHECK-NEXT:    auipc a2, %got_pcrel_hi(a4)
 ; CHECK-NEXT:    lw a2, %pcrel_lo(.Lpcrel_hi6)(a2)
-; CHECK-NEXT:    cspecialr ca3, ddc
+; CHECK-NEXT:    cspecialr a3, ddc
 ; CHECK-NEXT:    bnez a2, .LBB6_2
 ; CHECK-NEXT:  # %bb.1:
-; CHECK-NEXT:    cmove ca2, cnull
+; CHECK-NEXT:    cmove a2, zero
 ; CHECK-NEXT:    j .LBB6_3
 ; CHECK-NEXT:  .LBB6_2:
-; CHECK-NEXT:    csetaddr ca2, ca3, a2
+; CHECK-NEXT:    csetaddr a2, a3, a2
 ; CHECK-NEXT:  .LBB6_3:
-; CHECK-NEXT:    sw.cap a0, (ca2)
-; CHECK-NEXT:    cincoffset ca0, ca2, 4
-; CHECK-NEXT:    sw.cap a1, (ca0)
+; CHECK-NEXT:    sw.cap a0, (a2)
+; CHECK-NEXT:    cincoffset a0, a2, 4
+; CHECK-NEXT:    sw.cap a1, (a0)
 ; CHECK-NEXT:    ret
   store i64 %y, i64 addrspace(200)* addrspacecast(i64* @a4 to i64 addrspace(200)*), align 4
   ret void
@@ -223,17 +223,17 @@ define void @store_global_i64_align_8(i64 %y) addrspace(200) nounwind {
 ; CHECK-NEXT:  .Lpcrel_hi7:
 ; CHECK-NEXT:    auipc a2, %got_pcrel_hi(a8)
 ; CHECK-NEXT:    lw a2, %pcrel_lo(.Lpcrel_hi7)(a2)
-; CHECK-NEXT:    cspecialr ca3, ddc
+; CHECK-NEXT:    cspecialr a3, ddc
 ; CHECK-NEXT:    bnez a2, .LBB7_2
 ; CHECK-NEXT:  # %bb.1:
-; CHECK-NEXT:    cmove ca2, cnull
+; CHECK-NEXT:    cmove a2, zero
 ; CHECK-NEXT:    j .LBB7_3
 ; CHECK-NEXT:  .LBB7_2:
-; CHECK-NEXT:    csetaddr ca2, ca3, a2
+; CHECK-NEXT:    csetaddr a2, a3, a2
 ; CHECK-NEXT:  .LBB7_3:
-; CHECK-NEXT:    sw.cap a0, (ca2)
-; CHECK-NEXT:    cincoffset ca0, ca2, 4
-; CHECK-NEXT:    sw.cap a1, (ca0)
+; CHECK-NEXT:    sw.cap a0, (a2)
+; CHECK-NEXT:    cincoffset a0, a2, 4
+; CHECK-NEXT:    sw.cap a1, (a0)
 ; CHECK-NEXT:    ret
   store i64 %y, i64 addrspace(200)* addrspacecast(i64* @a8 to i64 addrspace(200)*), align 8
   ret void
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/unaligned-loads-stores-purecap.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/unaligned-loads-stores-purecap.ll
index ac6165170b5da..37c1870da0a42 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/unaligned-loads-stores-purecap.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/unaligned-loads-stores-purecap.ll
@@ -11,21 +11,21 @@ define i64 @load_global_i64_align_1(i64 %y) addrspace(200) nounwind {
 ; CHECK-LABEL: load_global_i64_align_1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:  .LBB0_1: # Label of block must be emitted
-; CHECK-NEXT:    auipcc ca0, %captab_pcrel_hi(a1)
-; CHECK-NEXT:    clc ca0, %pcrel_lo(.LBB0_1)(ca0)
-; CHECK-NEXT:    clbu a1, 0(ca0)
-; CHECK-NEXT:    clbu a2, 1(ca0)
-; CHECK-NEXT:    clbu a3, 2(ca0)
-; CHECK-NEXT:    clbu a4, 3(ca0)
-; CHECK-NEXT:    clbu a5, 4(ca0)
+; CHECK-NEXT:    auipcc a0, %captab_pcrel_hi(a1)
+; CHECK-NEXT:    clc a0, %pcrel_lo(.LBB0_1)(a0)
+; CHECK-NEXT:    clbu a1, 0(a0)
+; CHECK-NEXT:    clbu a2, 1(a0)
+; CHECK-NEXT:    clbu a3, 2(a0)
+; CHECK-NEXT:    clbu a4, 3(a0)
+; CHECK-NEXT:    clbu a5, 4(a0)
 ; CHECK-NEXT:    slli a2, a2, 8
 ; CHECK-NEXT:    or a1, a2, a1
-; CHECK-NEXT:    clbu a2, 5(ca0)
+; CHECK-NEXT:    clbu a2, 5(a0)
 ; CHECK-NEXT:    slli a3, a3, 16
 ; CHECK-NEXT:    slli a4, a4, 24
 ; CHECK-NEXT:    or a3, a4, a3
-; CHECK-NEXT:    clbu a4, 6(ca0)
-; CHECK-NEXT:    clbu a0, 7(ca0)
+; CHECK-NEXT:    clbu a4, 6(a0)
+; CHECK-NEXT:    clbu a0, 7(a0)
 ; CHECK-NEXT:    slli a2, a2, 8
 ; CHECK-NEXT:    or a2, a2, a5
 ; CHECK-NEXT:    slli a4, a4, 16
@@ -42,12 +42,12 @@ define i64 @load_global_i64_align_2(i64 %y) addrspace(200) nounwind {
 ; CHECK-LABEL: load_global_i64_align_2:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:  .LBB1_1: # Label of block must be emitted
-; CHECK-NEXT:    auipcc ca0, %captab_pcrel_hi(a2)
-; CHECK-NEXT:    clc ca0, %pcrel_lo(.LBB1_1)(ca0)
-; CHECK-NEXT:    clhu a1, 2(ca0)
-; CHECK-NEXT:    clhu a2, 0(ca0)
-; CHECK-NEXT:    clhu a3, 6(ca0)
-; CHECK-NEXT:    clhu a4, 4(ca0)
+; CHECK-NEXT:    auipcc a0, %captab_pcrel_hi(a2)
+; CHECK-NEXT:    clc a0, %pcrel_lo(.LBB1_1)(a0)
+; CHECK-NEXT:    clhu a1, 2(a0)
+; CHECK-NEXT:    clhu a2, 0(a0)
+; CHECK-NEXT:    clhu a3, 6(a0)
+; CHECK-NEXT:    clhu a4, 4(a0)
 ; CHECK-NEXT:    slli a0, a1, 16
 ; CHECK-NEXT:    or a0, a0, a2
 ; CHECK-NEXT:    slli a1, a3, 16
@@ -61,10 +61,10 @@ define i64 @load_global_i64_align_4(i64 %y) addrspace(200) nounwind {
 ; CHECK-LABEL: load_global_i64_align_4:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:  .LBB2_1: # Label of block must be emitted
-; CHECK-NEXT:    auipcc ca1, %captab_pcrel_hi(a4)
-; CHECK-NEXT:    clc ca1, %pcrel_lo(.LBB2_1)(ca1)
-; CHECK-NEXT:    clw a0, 0(ca1)
-; CHECK-NEXT:    clw a1, 4(ca1)
+; CHECK-NEXT:    auipcc a1, %captab_pcrel_hi(a4)
+; CHECK-NEXT:    clc a1, %pcrel_lo(.LBB2_1)(a1)
+; CHECK-NEXT:    clw a0, 0(a1)
+; CHECK-NEXT:    clw a1, 4(a1)
 ; CHECK-NEXT:    cret
   %ret = load i64, i64 addrspace(200)* @a4, align 4
   ret i64 %ret
@@ -74,10 +74,10 @@ define i64 @load_global_i64_align_8(i64 %y) addrspace(200) nounwind {
 ; CHECK-LABEL: load_global_i64_align_8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:  .LBB3_1: # Label of block must be emitted
-; CHECK-NEXT:    auipcc ca1, %captab_pcrel_hi(a8)
-; CHECK-NEXT:    clc ca1, %pcrel_lo(.LBB3_1)(ca1)
-; CHECK-NEXT:    clw a0, 0(ca1)
-; CHECK-NEXT:    clw a1, 4(ca1)
+; CHECK-NEXT:    auipcc a1, %captab_pcrel_hi(a8)
+; CHECK-NEXT:    clc a1, %pcrel_lo(.LBB3_1)(a1)
+; CHECK-NEXT:    clw a0, 0(a1)
+; CHECK-NEXT:    clw a1, 4(a1)
 ; CHECK-NEXT:    cret
   %ret = load i64, i64 addrspace(200)* @a8, align 8
   ret i64 %ret
@@ -87,22 +87,22 @@ define void @store_global_i64_align_1(i64 %y) addrspace(200) nounwind {
 ; CHECK-LABEL: store_global_i64_align_1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:  .LBB4_1: # Label of block must be emitted
-; CHECK-NEXT:    auipcc ca2, %captab_pcrel_hi(a1)
-; CHECK-NEXT:    clc ca2, %pcrel_lo(.LBB4_1)(ca2)
+; CHECK-NEXT:    auipcc a2, %captab_pcrel_hi(a1)
+; CHECK-NEXT:    clc a2, %pcrel_lo(.LBB4_1)(a2)
 ; CHECK-NEXT:    srli a3, a1, 24
-; CHECK-NEXT:    csb a3, 7(ca2)
+; CHECK-NEXT:    csb a3, 7(a2)
 ; CHECK-NEXT:    srli a3, a1, 16
-; CHECK-NEXT:    csb a1, 4(ca2)
+; CHECK-NEXT:    csb a1, 4(a2)
 ; CHECK-NEXT:    srli a1, a1, 8
-; CHECK-NEXT:    csb a3, 6(ca2)
+; CHECK-NEXT:    csb a3, 6(a2)
 ; CHECK-NEXT:    srli a3, a0, 24
-; CHECK-NEXT:    csb a1, 5(ca2)
+; CHECK-NEXT:    csb a1, 5(a2)
 ; CHECK-NEXT:    srli a1, a0, 16
-; CHECK-NEXT:    csb a0, 0(ca2)
+; CHECK-NEXT:    csb a0, 0(a2)
 ; CHECK-NEXT:    srli a0, a0, 8
-; CHECK-NEXT:    csb a3, 3(ca2)
-; CHECK-NEXT:    csb a1, 2(ca2)
-; CHECK-NEXT:    csb a0, 1(ca2)
+; CHECK-NEXT:    csb a3, 3(a2)
+; CHECK-NEXT:    csb a1, 2(a2)
+; CHECK-NEXT:    csb a0, 1(a2)
 ; CHECK-NEXT:    cret
   store i64 %y, i64 addrspace(200)* @a1, align 1
   ret void
@@ -112,14 +112,14 @@ define void @store_global_i64_align_2(i64 %y) addrspace(200) nounwind {
 ; CHECK-LABEL: store_global_i64_align_2:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:  .LBB5_1: # Label of block must be emitted
-; CHECK-NEXT:    auipcc ca2, %captab_pcrel_hi(a2)
-; CHECK-NEXT:    clc ca2, %pcrel_lo(.LBB5_1)(ca2)
-; CHECK-NEXT:    csh a1, 4(ca2)
+; CHECK-NEXT:    auipcc a2, %captab_pcrel_hi(a2)
+; CHECK-NEXT:    clc a2, %pcrel_lo(.LBB5_1)(a2)
+; CHECK-NEXT:    csh a1, 4(a2)
 ; CHECK-NEXT:    srli a1, a1, 16
-; CHECK-NEXT:    csh a0, 0(ca2)
+; CHECK-NEXT:    csh a0, 0(a2)
 ; CHECK-NEXT:    srli a0, a0, 16
-; CHECK-NEXT:    csh a1, 6(ca2)
-; CHECK-NEXT:    csh a0, 2(ca2)
+; CHECK-NEXT:    csh a1, 6(a2)
+; CHECK-NEXT:    csh a0, 2(a2)
 ; CHECK-NEXT:    cret
   store i64 %y, i64 addrspace(200)* @a2, align 2
   ret void
@@ -129,10 +129,10 @@ define void @store_global_i64_align_4(i64 %y) addrspace(200) nounwind {
 ; CHECK-LABEL: store_global_i64_align_4:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:  .LBB6_1: # Label of block must be emitted
-; CHECK-NEXT:    auipcc ca2, %captab_pcrel_hi(a4)
-; CHECK-NEXT:    clc ca2, %pcrel_lo(.LBB6_1)(ca2)
-; CHECK-NEXT:    csw a1, 4(ca2)
-; CHECK-NEXT:    csw a0, 0(ca2)
+; CHECK-NEXT:    auipcc a2, %captab_pcrel_hi(a4)
+; CHECK-NEXT:    clc a2, %pcrel_lo(.LBB6_1)(a2)
+; CHECK-NEXT:    csw a1, 4(a2)
+; CHECK-NEXT:    csw a0, 0(a2)
 ; CHECK-NEXT:    cret
   store i64 %y, i64 addrspace(200)* @a4, align 4
   ret void
@@ -142,10 +142,10 @@ define void @store_global_i64_align_8(i64 %y) addrspace(200) nounwind {
 ; CHECK-LABEL: store_global_i64_align_8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:  .LBB7_1: # Label of block must be emitted
-; CHECK-NEXT:    auipcc ca2, %captab_pcrel_hi(a8)
-; CHECK-NEXT:    clc ca2, %pcrel_lo(.LBB7_1)(ca2)
-; CHECK-NEXT:    csw a1, 4(ca2)
-; CHECK-NEXT:    csw a0, 0(ca2)
+; CHECK-NEXT:    auipcc a2, %captab_pcrel_hi(a8)
+; CHECK-NEXT:    clc a2, %pcrel_lo(.LBB7_1)(a2)
+; CHECK-NEXT:    csw a1, 4(a2)
+; CHECK-NEXT:    csw a0, 0(a2)
 ; CHECK-NEXT:    cret
   store i64 %y, i64 addrspace(200)* @a8, align 8
   ret void
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/atomic-rmw-cap-ptr-arg.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/atomic-rmw-cap-ptr-arg.ll
index 6654ea98b03ac..1ec2bcd699aa1 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/atomic-rmw-cap-ptr-arg.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/atomic-rmw-cap-ptr-arg.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --scrub-attributes --version 2
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
 ; DO NOT EDIT -- This file was generated from test/CodeGen/CHERI-Generic/Inputs/atomic-rmw-cap-ptr-arg.ll
 ; Check that we can generate sensible code for atomic operations using capability pointers on capabilities
 ; See https://github.com/CTSRD-CHERI/llvm-project/issues/470
@@ -10,17 +10,17 @@
 define i32 addrspace(200)* @atomic_cap_ptr_xchg_sc(i32 addrspace(200)* addrspace(200)* %ptr, i32 addrspace(200)* %val) nounwind {
 ; PURECAP-ATOMICS-LABEL: atomic_cap_ptr_xchg_sc:
 ; PURECAP-ATOMICS:       # %bb.0:
-; PURECAP-ATOMICS-NEXT:    camoswap.c.aqrl ca0, ca1, (ca0)
+; PURECAP-ATOMICS-NEXT:    camoswap.c.aqrl a0, a1, (a0)
 ; PURECAP-ATOMICS-NEXT:    cret
 ;
 ; PURECAP-LIBCALLS-LABEL: atomic_cap_ptr_xchg_sc:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -16
-; PURECAP-LIBCALLS-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -16
+; PURECAP-LIBCALLS-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; PURECAP-LIBCALLS-NEXT:    li a2, 5
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_exchange_cap
-; PURECAP-LIBCALLS-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 16
+; PURECAP-LIBCALLS-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 16
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: atomic_cap_ptr_xchg_sc:
@@ -39,17 +39,17 @@ define i32 addrspace(200)* @atomic_cap_ptr_xchg_sc(i32 addrspace(200)* addrspace
 define i32 addrspace(200)* @atomic_cap_ptr_xchg_relaxed(i32 addrspace(200)* addrspace(200)* %ptr, i32 addrspace(200)* %val) nounwind {
 ; PURECAP-ATOMICS-LABEL: atomic_cap_ptr_xchg_relaxed:
 ; PURECAP-ATOMICS:       # %bb.0:
-; PURECAP-ATOMICS-NEXT:    camoswap.c ca0, ca1, (ca0)
+; PURECAP-ATOMICS-NEXT:    camoswap.c a0, a1, (a0)
 ; PURECAP-ATOMICS-NEXT:    cret
 ;
 ; PURECAP-LIBCALLS-LABEL: atomic_cap_ptr_xchg_relaxed:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -16
-; PURECAP-LIBCALLS-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -16
+; PURECAP-LIBCALLS-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; PURECAP-LIBCALLS-NEXT:    li a2, 0
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_exchange_cap
-; PURECAP-LIBCALLS-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 16
+; PURECAP-LIBCALLS-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 16
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: atomic_cap_ptr_xchg_relaxed:
@@ -68,17 +68,17 @@ define i32 addrspace(200)* @atomic_cap_ptr_xchg_relaxed(i32 addrspace(200)* addr
 define i32 addrspace(200)* @atomic_cap_ptr_xchg_acquire(i32 addrspace(200)* addrspace(200)* %ptr, i32 addrspace(200)* %val) nounwind {
 ; PURECAP-ATOMICS-LABEL: atomic_cap_ptr_xchg_acquire:
 ; PURECAP-ATOMICS:       # %bb.0:
-; PURECAP-ATOMICS-NEXT:    camoswap.c.aq ca0, ca1, (ca0)
+; PURECAP-ATOMICS-NEXT:    camoswap.c.aq a0, a1, (a0)
 ; PURECAP-ATOMICS-NEXT:    cret
 ;
 ; PURECAP-LIBCALLS-LABEL: atomic_cap_ptr_xchg_acquire:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -16
-; PURECAP-LIBCALLS-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -16
+; PURECAP-LIBCALLS-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; PURECAP-LIBCALLS-NEXT:    li a2, 2
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_exchange_cap
-; PURECAP-LIBCALLS-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 16
+; PURECAP-LIBCALLS-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 16
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: atomic_cap_ptr_xchg_acquire:
@@ -97,17 +97,17 @@ define i32 addrspace(200)* @atomic_cap_ptr_xchg_acquire(i32 addrspace(200)* addr
 define i32 addrspace(200)* @atomic_cap_ptr_xchg_rel(i32 addrspace(200)* addrspace(200)* %ptr, i32 addrspace(200)* %val) nounwind {
 ; PURECAP-ATOMICS-LABEL: atomic_cap_ptr_xchg_rel:
 ; PURECAP-ATOMICS:       # %bb.0:
-; PURECAP-ATOMICS-NEXT:    camoswap.c.rl ca0, ca1, (ca0)
+; PURECAP-ATOMICS-NEXT:    camoswap.c.rl a0, a1, (a0)
 ; PURECAP-ATOMICS-NEXT:    cret
 ;
 ; PURECAP-LIBCALLS-LABEL: atomic_cap_ptr_xchg_rel:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -16
-; PURECAP-LIBCALLS-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -16
+; PURECAP-LIBCALLS-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; PURECAP-LIBCALLS-NEXT:    li a2, 3
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_exchange_cap
-; PURECAP-LIBCALLS-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 16
+; PURECAP-LIBCALLS-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 16
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: atomic_cap_ptr_xchg_rel:
@@ -126,17 +126,17 @@ define i32 addrspace(200)* @atomic_cap_ptr_xchg_rel(i32 addrspace(200)* addrspac
 define i32 addrspace(200)* @atomic_cap_ptr_xchg_acq_rel(i32 addrspace(200)* addrspace(200)* %ptr, i32 addrspace(200)* %val) nounwind {
 ; PURECAP-ATOMICS-LABEL: atomic_cap_ptr_xchg_acq_rel:
 ; PURECAP-ATOMICS:       # %bb.0:
-; PURECAP-ATOMICS-NEXT:    camoswap.c.aqrl ca0, ca1, (ca0)
+; PURECAP-ATOMICS-NEXT:    camoswap.c.aqrl a0, a1, (a0)
 ; PURECAP-ATOMICS-NEXT:    cret
 ;
 ; PURECAP-LIBCALLS-LABEL: atomic_cap_ptr_xchg_acq_rel:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -16
-; PURECAP-LIBCALLS-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -16
+; PURECAP-LIBCALLS-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; PURECAP-LIBCALLS-NEXT:    li a2, 4
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_exchange_cap
-; PURECAP-LIBCALLS-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 16
+; PURECAP-LIBCALLS-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 16
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: atomic_cap_ptr_xchg_acq_rel:
@@ -156,17 +156,17 @@ define i32 addrspace(200)* @atomic_cap_ptr_xchg_acq_rel(i32 addrspace(200)* addr
 define i32 addrspace(200)* @atomic_cap_ptr_xchg_i32ptr(i32 addrspace(200)* addrspace(200)* %ptr, i32 addrspace(200)* %val) nounwind {
 ; PURECAP-ATOMICS-LABEL: atomic_cap_ptr_xchg_i32ptr:
 ; PURECAP-ATOMICS:       # %bb.0:
-; PURECAP-ATOMICS-NEXT:    camoswap.c.aqrl ca0, ca1, (ca0)
+; PURECAP-ATOMICS-NEXT:    camoswap.c.aqrl a0, a1, (a0)
 ; PURECAP-ATOMICS-NEXT:    cret
 ;
 ; PURECAP-LIBCALLS-LABEL: atomic_cap_ptr_xchg_i32ptr:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -16
-; PURECAP-LIBCALLS-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -16
+; PURECAP-LIBCALLS-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; PURECAP-LIBCALLS-NEXT:    li a2, 4
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_exchange_cap
-; PURECAP-LIBCALLS-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 16
+; PURECAP-LIBCALLS-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 16
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: atomic_cap_ptr_xchg_i32ptr:
@@ -186,69 +186,69 @@ define i32 addrspace(200)* @atomic_cap_ptr_add(i32 addrspace(200)* addrspace(200
 ; PURECAP-ATOMICS-LABEL: atomic_cap_ptr_add:
 ; PURECAP-ATOMICS:       # %bb.0:
 ; PURECAP-ATOMICS-NEXT:  .LBB6_1: # =>This Inner Loop Header: Depth=1
-; PURECAP-ATOMICS-NEXT:    clr.c.aqrl ca2, (ca0)
-; PURECAP-ATOMICS-NEXT:    cincoffset ca3, ca2, a1
-; PURECAP-ATOMICS-NEXT:    csc.c.aqrl a3, ca3, (ca0)
+; PURECAP-ATOMICS-NEXT:    clr.c.aqrl a2, (a0)
+; PURECAP-ATOMICS-NEXT:    cincoffset a3, a2, a1
+; PURECAP-ATOMICS-NEXT:    csc.c.aqrl a3, a3, (a0)
 ; PURECAP-ATOMICS-NEXT:    bnez a3, .LBB6_1
 ; PURECAP-ATOMICS-NEXT:  # %bb.2:
-; PURECAP-ATOMICS-NEXT:    cmove ca0, ca2
+; PURECAP-ATOMICS-NEXT:    cmove a0, a2
 ; PURECAP-ATOMICS-NEXT:    cret
 ;
 ; PURECAP-LIBCALLS-LABEL: atomic_cap_ptr_add:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -80
-; PURECAP-LIBCALLS-NEXT:    csc cra, 64(csp) # 16-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs0, 48(csp) # 16-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs1, 32(csp) # 16-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs2, 16(csp) # 16-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    cmove cs2, ca1
-; PURECAP-LIBCALLS-NEXT:    cmove cs1, ca0
-; PURECAP-LIBCALLS-NEXT:    clc ca1, 0(ca0)
-; PURECAP-LIBCALLS-NEXT:    cincoffset ca0, csp, 0
-; PURECAP-LIBCALLS-NEXT:    csetbounds cs0, ca0, 16
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -80
+; PURECAP-LIBCALLS-NEXT:    csc ra, 64(sp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s0, 48(sp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s1, 32(sp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s2, 16(sp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    cmove s0, a1
+; PURECAP-LIBCALLS-NEXT:    cmove s1, a0
+; PURECAP-LIBCALLS-NEXT:    clc a1, 0(a0)
+; PURECAP-LIBCALLS-NEXT:    cincoffset a0, sp, 0
+; PURECAP-LIBCALLS-NEXT:    csetbounds s2, a0, 16
 ; PURECAP-LIBCALLS-NEXT:  .LBB6_1: # %atomicrmw.start
 ; PURECAP-LIBCALLS-NEXT:    # =>This Inner Loop Header: Depth=1
-; PURECAP-LIBCALLS-NEXT:    add a0, a1, s2
-; PURECAP-LIBCALLS-NEXT:    csetaddr ca2, ca1, a0
-; PURECAP-LIBCALLS-NEXT:    csc ca1, 0(csp)
+; PURECAP-LIBCALLS-NEXT:    add a0, a1, s0
+; PURECAP-LIBCALLS-NEXT:    csetaddr a2, a1, a0
+; PURECAP-LIBCALLS-NEXT:    csc a1, 0(sp)
 ; PURECAP-LIBCALLS-NEXT:    li a3, 5
 ; PURECAP-LIBCALLS-NEXT:    li a4, 5
-; PURECAP-LIBCALLS-NEXT:    cmove ca0, cs1
-; PURECAP-LIBCALLS-NEXT:    cmove ca1, cs0
+; PURECAP-LIBCALLS-NEXT:    cmove a0, s1
+; PURECAP-LIBCALLS-NEXT:    cmove a1, s2
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_compare_exchange_cap
-; PURECAP-LIBCALLS-NEXT:    clc ca1, 0(csp)
+; PURECAP-LIBCALLS-NEXT:    clc a1, 0(sp)
 ; PURECAP-LIBCALLS-NEXT:    beqz a0, .LBB6_1
 ; PURECAP-LIBCALLS-NEXT:  # %bb.2: # %atomicrmw.end
-; PURECAP-LIBCALLS-NEXT:    cmove ca0, ca1
-; PURECAP-LIBCALLS-NEXT:    clc cra, 64(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs0, 48(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs1, 32(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs2, 16(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 80
+; PURECAP-LIBCALLS-NEXT:    cmove a0, a1
+; PURECAP-LIBCALLS-NEXT:    clc ra, 64(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s0, 48(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s1, 32(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s2, 16(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 80
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: atomic_cap_ptr_add:
 ; HYBRID:       # %bb.0:
 ; HYBRID-NEXT:    addi sp, sp, -64
 ; HYBRID-NEXT:    sd ra, 56(sp) # 8-byte Folded Spill
-; HYBRID-NEXT:    sc ca0, 16(sp) # 16-byte Folded Spill
-; HYBRID-NEXT:    lc.cap ca3, (ca0)
-; HYBRID-NEXT:    sc ca1, 0(sp) # 16-byte Folded Spill
+; HYBRID-NEXT:    sc a0, 16(sp) # 16-byte Folded Spill
+; HYBRID-NEXT:    lc.cap a3, (a0)
+; HYBRID-NEXT:    sc a1, 0(sp) # 16-byte Folded Spill
 ; HYBRID-NEXT:  .LBB6_1: # %atomicrmw.start
 ; HYBRID-NEXT:    # =>This Inner Loop Header: Depth=1
-; HYBRID-NEXT:    lc ca0, 0(sp) # 16-byte Folded Reload
+; HYBRID-NEXT:    lc a0, 0(sp) # 16-byte Folded Reload
 ; HYBRID-NEXT:    add a0, a3, a0
-; HYBRID-NEXT:    csetaddr ca2, ca3, a0
-; HYBRID-NEXT:    sc ca3, 32(sp)
+; HYBRID-NEXT:    csetaddr a2, a3, a0
+; HYBRID-NEXT:    sc a3, 32(sp)
 ; HYBRID-NEXT:    addi a1, sp, 32
 ; HYBRID-NEXT:    li a3, 5
 ; HYBRID-NEXT:    li a4, 5
-; HYBRID-NEXT:    lc ca0, 16(sp) # 16-byte Folded Reload
+; HYBRID-NEXT:    lc a0, 16(sp) # 16-byte Folded Reload
 ; HYBRID-NEXT:    call __atomic_compare_exchange_cap_c
-; HYBRID-NEXT:    lc ca3, 32(sp)
+; HYBRID-NEXT:    lc a3, 32(sp)
 ; HYBRID-NEXT:    beqz a0, .LBB6_1
 ; HYBRID-NEXT:  # %bb.2: # %atomicrmw.end
-; HYBRID-NEXT:    cmove ca0, ca3
+; HYBRID-NEXT:    cmove a0, a3
 ; HYBRID-NEXT:    ld ra, 56(sp) # 8-byte Folded Reload
 ; HYBRID-NEXT:    addi sp, sp, 64
 ; HYBRID-NEXT:    ret
@@ -260,70 +260,70 @@ define i32 addrspace(200)* @atomic_cap_ptr_sub(i32 addrspace(200)* addrspace(200
 ; PURECAP-ATOMICS-LABEL: atomic_cap_ptr_sub:
 ; PURECAP-ATOMICS:       # %bb.0:
 ; PURECAP-ATOMICS-NEXT:  .LBB7_1: # =>This Inner Loop Header: Depth=1
-; PURECAP-ATOMICS-NEXT:    clr.c.aqrl ca2, (ca0)
+; PURECAP-ATOMICS-NEXT:    clr.c.aqrl a2, (a0)
 ; PURECAP-ATOMICS-NEXT:    sub a3, a2, a1
-; PURECAP-ATOMICS-NEXT:    csetaddr ca3, ca2, a3
-; PURECAP-ATOMICS-NEXT:    csc.c.aqrl a3, ca3, (ca0)
+; PURECAP-ATOMICS-NEXT:    csetaddr a3, a2, a3
+; PURECAP-ATOMICS-NEXT:    csc.c.aqrl a3, a3, (a0)
 ; PURECAP-ATOMICS-NEXT:    bnez a3, .LBB7_1
 ; PURECAP-ATOMICS-NEXT:  # %bb.2:
-; PURECAP-ATOMICS-NEXT:    cmove ca0, ca2
+; PURECAP-ATOMICS-NEXT:    cmove a0, a2
 ; PURECAP-ATOMICS-NEXT:    cret
 ;
 ; PURECAP-LIBCALLS-LABEL: atomic_cap_ptr_sub:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -80
-; PURECAP-LIBCALLS-NEXT:    csc cra, 64(csp) # 16-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs0, 48(csp) # 16-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs1, 32(csp) # 16-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs2, 16(csp) # 16-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    cmove cs2, ca1
-; PURECAP-LIBCALLS-NEXT:    cmove cs1, ca0
-; PURECAP-LIBCALLS-NEXT:    clc ca1, 0(ca0)
-; PURECAP-LIBCALLS-NEXT:    cincoffset ca0, csp, 0
-; PURECAP-LIBCALLS-NEXT:    csetbounds cs0, ca0, 16
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -80
+; PURECAP-LIBCALLS-NEXT:    csc ra, 64(sp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s0, 48(sp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s1, 32(sp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s2, 16(sp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    cmove s0, a1
+; PURECAP-LIBCALLS-NEXT:    cmove s1, a0
+; PURECAP-LIBCALLS-NEXT:    clc a1, 0(a0)
+; PURECAP-LIBCALLS-NEXT:    cincoffset a0, sp, 0
+; PURECAP-LIBCALLS-NEXT:    csetbounds s2, a0, 16
 ; PURECAP-LIBCALLS-NEXT:  .LBB7_1: # %atomicrmw.start
 ; PURECAP-LIBCALLS-NEXT:    # =>This Inner Loop Header: Depth=1
-; PURECAP-LIBCALLS-NEXT:    sub a0, a1, s2
-; PURECAP-LIBCALLS-NEXT:    csetaddr ca2, ca1, a0
-; PURECAP-LIBCALLS-NEXT:    csc ca1, 0(csp)
+; PURECAP-LIBCALLS-NEXT:    sub a0, a1, s0
+; PURECAP-LIBCALLS-NEXT:    csetaddr a2, a1, a0
+; PURECAP-LIBCALLS-NEXT:    csc a1, 0(sp)
 ; PURECAP-LIBCALLS-NEXT:    li a3, 5
 ; PURECAP-LIBCALLS-NEXT:    li a4, 5
-; PURECAP-LIBCALLS-NEXT:    cmove ca0, cs1
-; PURECAP-LIBCALLS-NEXT:    cmove ca1, cs0
+; PURECAP-LIBCALLS-NEXT:    cmove a0, s1
+; PURECAP-LIBCALLS-NEXT:    cmove a1, s2
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_compare_exchange_cap
-; PURECAP-LIBCALLS-NEXT:    clc ca1, 0(csp)
+; PURECAP-LIBCALLS-NEXT:    clc a1, 0(sp)
 ; PURECAP-LIBCALLS-NEXT:    beqz a0, .LBB7_1
 ; PURECAP-LIBCALLS-NEXT:  # %bb.2: # %atomicrmw.end
-; PURECAP-LIBCALLS-NEXT:    cmove ca0, ca1
-; PURECAP-LIBCALLS-NEXT:    clc cra, 64(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs0, 48(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs1, 32(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs2, 16(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 80
+; PURECAP-LIBCALLS-NEXT:    cmove a0, a1
+; PURECAP-LIBCALLS-NEXT:    clc ra, 64(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s0, 48(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s1, 32(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s2, 16(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 80
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: atomic_cap_ptr_sub:
 ; HYBRID:       # %bb.0:
 ; HYBRID-NEXT:    addi sp, sp, -64
 ; HYBRID-NEXT:    sd ra, 56(sp) # 8-byte Folded Spill
-; HYBRID-NEXT:    sc ca0, 16(sp) # 16-byte Folded Spill
-; HYBRID-NEXT:    lc.cap ca3, (ca0)
-; HYBRID-NEXT:    sc ca1, 0(sp) # 16-byte Folded Spill
+; HYBRID-NEXT:    sc a0, 16(sp) # 16-byte Folded Spill
+; HYBRID-NEXT:    lc.cap a3, (a0)
+; HYBRID-NEXT:    sc a1, 0(sp) # 16-byte Folded Spill
 ; HYBRID-NEXT:  .LBB7_1: # %atomicrmw.start
 ; HYBRID-NEXT:    # =>This Inner Loop Header: Depth=1
-; HYBRID-NEXT:    lc ca0, 0(sp) # 16-byte Folded Reload
+; HYBRID-NEXT:    lc a0, 0(sp) # 16-byte Folded Reload
 ; HYBRID-NEXT:    sub a0, a3, a0
-; HYBRID-NEXT:    csetaddr ca2, ca3, a0
-; HYBRID-NEXT:    sc ca3, 32(sp)
+; HYBRID-NEXT:    csetaddr a2, a3, a0
+; HYBRID-NEXT:    sc a3, 32(sp)
 ; HYBRID-NEXT:    addi a1, sp, 32
 ; HYBRID-NEXT:    li a3, 5
 ; HYBRID-NEXT:    li a4, 5
-; HYBRID-NEXT:    lc ca0, 16(sp) # 16-byte Folded Reload
+; HYBRID-NEXT:    lc a0, 16(sp) # 16-byte Folded Reload
 ; HYBRID-NEXT:    call __atomic_compare_exchange_cap_c
-; HYBRID-NEXT:    lc ca3, 32(sp)
+; HYBRID-NEXT:    lc a3, 32(sp)
 ; HYBRID-NEXT:    beqz a0, .LBB7_1
 ; HYBRID-NEXT:  # %bb.2: # %atomicrmw.end
-; HYBRID-NEXT:    cmove ca0, ca3
+; HYBRID-NEXT:    cmove a0, a3
 ; HYBRID-NEXT:    ld ra, 56(sp) # 8-byte Folded Reload
 ; HYBRID-NEXT:    addi sp, sp, 64
 ; HYBRID-NEXT:    ret
@@ -335,70 +335,70 @@ define i32 addrspace(200)* @atomic_cap_ptr_and(i32 addrspace(200)* addrspace(200
 ; PURECAP-ATOMICS-LABEL: atomic_cap_ptr_and:
 ; PURECAP-ATOMICS:       # %bb.0:
 ; PURECAP-ATOMICS-NEXT:  .LBB8_1: # =>This Inner Loop Header: Depth=1
-; PURECAP-ATOMICS-NEXT:    clr.c.aqrl ca2, (ca0)
+; PURECAP-ATOMICS-NEXT:    clr.c.aqrl a2, (a0)
 ; PURECAP-ATOMICS-NEXT:    and a3, a2, a1
-; PURECAP-ATOMICS-NEXT:    csetaddr ca3, ca2, a3
-; PURECAP-ATOMICS-NEXT:    csc.c.aqrl a3, ca3, (ca0)
+; PURECAP-ATOMICS-NEXT:    csetaddr a3, a2, a3
+; PURECAP-ATOMICS-NEXT:    csc.c.aqrl a3, a3, (a0)
 ; PURECAP-ATOMICS-NEXT:    bnez a3, .LBB8_1
 ; PURECAP-ATOMICS-NEXT:  # %bb.2:
-; PURECAP-ATOMICS-NEXT:    cmove ca0, ca2
+; PURECAP-ATOMICS-NEXT:    cmove a0, a2
 ; PURECAP-ATOMICS-NEXT:    cret
 ;
 ; PURECAP-LIBCALLS-LABEL: atomic_cap_ptr_and:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -80
-; PURECAP-LIBCALLS-NEXT:    csc cra, 64(csp) # 16-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs0, 48(csp) # 16-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs1, 32(csp) # 16-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs2, 16(csp) # 16-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    cmove cs2, ca1
-; PURECAP-LIBCALLS-NEXT:    cmove cs1, ca0
-; PURECAP-LIBCALLS-NEXT:    clc ca1, 0(ca0)
-; PURECAP-LIBCALLS-NEXT:    cincoffset ca0, csp, 0
-; PURECAP-LIBCALLS-NEXT:    csetbounds cs0, ca0, 16
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -80
+; PURECAP-LIBCALLS-NEXT:    csc ra, 64(sp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s0, 48(sp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s1, 32(sp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s2, 16(sp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    cmove s0, a1
+; PURECAP-LIBCALLS-NEXT:    cmove s1, a0
+; PURECAP-LIBCALLS-NEXT:    clc a1, 0(a0)
+; PURECAP-LIBCALLS-NEXT:    cincoffset a0, sp, 0
+; PURECAP-LIBCALLS-NEXT:    csetbounds s2, a0, 16
 ; PURECAP-LIBCALLS-NEXT:  .LBB8_1: # %atomicrmw.start
 ; PURECAP-LIBCALLS-NEXT:    # =>This Inner Loop Header: Depth=1
-; PURECAP-LIBCALLS-NEXT:    and a0, a1, s2
-; PURECAP-LIBCALLS-NEXT:    csetaddr ca2, ca1, a0
-; PURECAP-LIBCALLS-NEXT:    csc ca1, 0(csp)
+; PURECAP-LIBCALLS-NEXT:    and a0, a1, s0
+; PURECAP-LIBCALLS-NEXT:    csetaddr a2, a1, a0
+; PURECAP-LIBCALLS-NEXT:    csc a1, 0(sp)
 ; PURECAP-LIBCALLS-NEXT:    li a3, 5
 ; PURECAP-LIBCALLS-NEXT:    li a4, 5
-; PURECAP-LIBCALLS-NEXT:    cmove ca0, cs1
-; PURECAP-LIBCALLS-NEXT:    cmove ca1, cs0
+; PURECAP-LIBCALLS-NEXT:    cmove a0, s1
+; PURECAP-LIBCALLS-NEXT:    cmove a1, s2
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_compare_exchange_cap
-; PURECAP-LIBCALLS-NEXT:    clc ca1, 0(csp)
+; PURECAP-LIBCALLS-NEXT:    clc a1, 0(sp)
 ; PURECAP-LIBCALLS-NEXT:    beqz a0, .LBB8_1
 ; PURECAP-LIBCALLS-NEXT:  # %bb.2: # %atomicrmw.end
-; PURECAP-LIBCALLS-NEXT:    cmove ca0, ca1
-; PURECAP-LIBCALLS-NEXT:    clc cra, 64(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs0, 48(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs1, 32(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs2, 16(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 80
+; PURECAP-LIBCALLS-NEXT:    cmove a0, a1
+; PURECAP-LIBCALLS-NEXT:    clc ra, 64(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s0, 48(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s1, 32(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s2, 16(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 80
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: atomic_cap_ptr_and:
 ; HYBRID:       # %bb.0:
 ; HYBRID-NEXT:    addi sp, sp, -64
 ; HYBRID-NEXT:    sd ra, 56(sp) # 8-byte Folded Spill
-; HYBRID-NEXT:    sc ca0, 16(sp) # 16-byte Folded Spill
-; HYBRID-NEXT:    lc.cap ca3, (ca0)
-; HYBRID-NEXT:    sc ca1, 0(sp) # 16-byte Folded Spill
+; HYBRID-NEXT:    sc a0, 16(sp) # 16-byte Folded Spill
+; HYBRID-NEXT:    lc.cap a3, (a0)
+; HYBRID-NEXT:    sc a1, 0(sp) # 16-byte Folded Spill
 ; HYBRID-NEXT:  .LBB8_1: # %atomicrmw.start
 ; HYBRID-NEXT:    # =>This Inner Loop Header: Depth=1
-; HYBRID-NEXT:    lc ca0, 0(sp) # 16-byte Folded Reload
+; HYBRID-NEXT:    lc a0, 0(sp) # 16-byte Folded Reload
 ; HYBRID-NEXT:    and a0, a3, a0
-; HYBRID-NEXT:    csetaddr ca2, ca3, a0
-; HYBRID-NEXT:    sc ca3, 32(sp)
+; HYBRID-NEXT:    csetaddr a2, a3, a0
+; HYBRID-NEXT:    sc a3, 32(sp)
 ; HYBRID-NEXT:    addi a1, sp, 32
 ; HYBRID-NEXT:    li a3, 5
 ; HYBRID-NEXT:    li a4, 5
-; HYBRID-NEXT:    lc ca0, 16(sp) # 16-byte Folded Reload
+; HYBRID-NEXT:    lc a0, 16(sp) # 16-byte Folded Reload
 ; HYBRID-NEXT:    call __atomic_compare_exchange_cap_c
-; HYBRID-NEXT:    lc ca3, 32(sp)
+; HYBRID-NEXT:    lc a3, 32(sp)
 ; HYBRID-NEXT:    beqz a0, .LBB8_1
 ; HYBRID-NEXT:  # %bb.2: # %atomicrmw.end
-; HYBRID-NEXT:    cmove ca0, ca3
+; HYBRID-NEXT:    cmove a0, a3
 ; HYBRID-NEXT:    ld ra, 56(sp) # 8-byte Folded Reload
 ; HYBRID-NEXT:    addi sp, sp, 64
 ; HYBRID-NEXT:    ret
@@ -410,73 +410,73 @@ define i32 addrspace(200)* @atomic_cap_ptr_nand(i32 addrspace(200)* addrspace(20
 ; PURECAP-ATOMICS-LABEL: atomic_cap_ptr_nand:
 ; PURECAP-ATOMICS:       # %bb.0:
 ; PURECAP-ATOMICS-NEXT:  .LBB9_1: # =>This Inner Loop Header: Depth=1
-; PURECAP-ATOMICS-NEXT:    clr.c.aqrl ca2, (ca0)
+; PURECAP-ATOMICS-NEXT:    clr.c.aqrl a2, (a0)
 ; PURECAP-ATOMICS-NEXT:    and a3, a2, a1
 ; PURECAP-ATOMICS-NEXT:    not a3, a3
-; PURECAP-ATOMICS-NEXT:    csetaddr ca3, ca2, a3
-; PURECAP-ATOMICS-NEXT:    csc.c.aqrl a3, ca3, (ca0)
+; PURECAP-ATOMICS-NEXT:    csetaddr a3, a2, a3
+; PURECAP-ATOMICS-NEXT:    csc.c.aqrl a3, a3, (a0)
 ; PURECAP-ATOMICS-NEXT:    bnez a3, .LBB9_1
 ; PURECAP-ATOMICS-NEXT:  # %bb.2:
-; PURECAP-ATOMICS-NEXT:    cmove ca0, ca2
+; PURECAP-ATOMICS-NEXT:    cmove a0, a2
 ; PURECAP-ATOMICS-NEXT:    cret
 ;
 ; PURECAP-LIBCALLS-LABEL: atomic_cap_ptr_nand:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -80
-; PURECAP-LIBCALLS-NEXT:    csc cra, 64(csp) # 16-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs0, 48(csp) # 16-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs1, 32(csp) # 16-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs2, 16(csp) # 16-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    cmove cs2, ca1
-; PURECAP-LIBCALLS-NEXT:    cmove cs1, ca0
-; PURECAP-LIBCALLS-NEXT:    clc ca1, 0(ca0)
-; PURECAP-LIBCALLS-NEXT:    cincoffset ca0, csp, 0
-; PURECAP-LIBCALLS-NEXT:    csetbounds cs0, ca0, 16
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -80
+; PURECAP-LIBCALLS-NEXT:    csc ra, 64(sp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s0, 48(sp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s1, 32(sp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s2, 16(sp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    cmove s0, a1
+; PURECAP-LIBCALLS-NEXT:    cmove s1, a0
+; PURECAP-LIBCALLS-NEXT:    clc a1, 0(a0)
+; PURECAP-LIBCALLS-NEXT:    cincoffset a0, sp, 0
+; PURECAP-LIBCALLS-NEXT:    csetbounds s2, a0, 16
 ; PURECAP-LIBCALLS-NEXT:  .LBB9_1: # %atomicrmw.start
 ; PURECAP-LIBCALLS-NEXT:    # =>This Inner Loop Header: Depth=1
-; PURECAP-LIBCALLS-NEXT:    and a0, a1, s2
+; PURECAP-LIBCALLS-NEXT:    and a0, a1, s0
 ; PURECAP-LIBCALLS-NEXT:    not a0, a0
-; PURECAP-LIBCALLS-NEXT:    csetaddr ca2, ca1, a0
-; PURECAP-LIBCALLS-NEXT:    csc ca1, 0(csp)
+; PURECAP-LIBCALLS-NEXT:    csetaddr a2, a1, a0
+; PURECAP-LIBCALLS-NEXT:    csc a1, 0(sp)
 ; PURECAP-LIBCALLS-NEXT:    li a3, 5
 ; PURECAP-LIBCALLS-NEXT:    li a4, 5
-; PURECAP-LIBCALLS-NEXT:    cmove ca0, cs1
-; PURECAP-LIBCALLS-NEXT:    cmove ca1, cs0
+; PURECAP-LIBCALLS-NEXT:    cmove a0, s1
+; PURECAP-LIBCALLS-NEXT:    cmove a1, s2
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_compare_exchange_cap
-; PURECAP-LIBCALLS-NEXT:    clc ca1, 0(csp)
+; PURECAP-LIBCALLS-NEXT:    clc a1, 0(sp)
 ; PURECAP-LIBCALLS-NEXT:    beqz a0, .LBB9_1
 ; PURECAP-LIBCALLS-NEXT:  # %bb.2: # %atomicrmw.end
-; PURECAP-LIBCALLS-NEXT:    cmove ca0, ca1
-; PURECAP-LIBCALLS-NEXT:    clc cra, 64(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs0, 48(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs1, 32(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs2, 16(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 80
+; PURECAP-LIBCALLS-NEXT:    cmove a0, a1
+; PURECAP-LIBCALLS-NEXT:    clc ra, 64(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s0, 48(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s1, 32(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s2, 16(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 80
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: atomic_cap_ptr_nand:
 ; HYBRID:       # %bb.0:
 ; HYBRID-NEXT:    addi sp, sp, -64
 ; HYBRID-NEXT:    sd ra, 56(sp) # 8-byte Folded Spill
-; HYBRID-NEXT:    sc ca0, 16(sp) # 16-byte Folded Spill
-; HYBRID-NEXT:    lc.cap ca3, (ca0)
-; HYBRID-NEXT:    sc ca1, 0(sp) # 16-byte Folded Spill
+; HYBRID-NEXT:    sc a0, 16(sp) # 16-byte Folded Spill
+; HYBRID-NEXT:    lc.cap a3, (a0)
+; HYBRID-NEXT:    sc a1, 0(sp) # 16-byte Folded Spill
 ; HYBRID-NEXT:  .LBB9_1: # %atomicrmw.start
 ; HYBRID-NEXT:    # =>This Inner Loop Header: Depth=1
-; HYBRID-NEXT:    lc ca0, 0(sp) # 16-byte Folded Reload
+; HYBRID-NEXT:    lc a0, 0(sp) # 16-byte Folded Reload
 ; HYBRID-NEXT:    and a0, a3, a0
 ; HYBRID-NEXT:    not a0, a0
-; HYBRID-NEXT:    csetaddr ca2, ca3, a0
-; HYBRID-NEXT:    sc ca3, 32(sp)
+; HYBRID-NEXT:    csetaddr a2, a3, a0
+; HYBRID-NEXT:    sc a3, 32(sp)
 ; HYBRID-NEXT:    addi a1, sp, 32
 ; HYBRID-NEXT:    li a3, 5
 ; HYBRID-NEXT:    li a4, 5
-; HYBRID-NEXT:    lc ca0, 16(sp) # 16-byte Folded Reload
+; HYBRID-NEXT:    lc a0, 16(sp) # 16-byte Folded Reload
 ; HYBRID-NEXT:    call __atomic_compare_exchange_cap_c
-; HYBRID-NEXT:    lc ca3, 32(sp)
+; HYBRID-NEXT:    lc a3, 32(sp)
 ; HYBRID-NEXT:    beqz a0, .LBB9_1
 ; HYBRID-NEXT:  # %bb.2: # %atomicrmw.end
-; HYBRID-NEXT:    cmove ca0, ca3
+; HYBRID-NEXT:    cmove a0, a3
 ; HYBRID-NEXT:    ld ra, 56(sp) # 8-byte Folded Reload
 ; HYBRID-NEXT:    addi sp, sp, 64
 ; HYBRID-NEXT:    ret
@@ -488,70 +488,70 @@ define i32 addrspace(200)* @atomic_cap_ptr_or(i32 addrspace(200)* addrspace(200)
 ; PURECAP-ATOMICS-LABEL: atomic_cap_ptr_or:
 ; PURECAP-ATOMICS:       # %bb.0:
 ; PURECAP-ATOMICS-NEXT:  .LBB10_1: # =>This Inner Loop Header: Depth=1
-; PURECAP-ATOMICS-NEXT:    clr.c.aqrl ca2, (ca0)
+; PURECAP-ATOMICS-NEXT:    clr.c.aqrl a2, (a0)
 ; PURECAP-ATOMICS-NEXT:    or a3, a2, a1
-; PURECAP-ATOMICS-NEXT:    csetaddr ca3, ca2, a3
-; PURECAP-ATOMICS-NEXT:    csc.c.aqrl a3, ca3, (ca0)
+; PURECAP-ATOMICS-NEXT:    csetaddr a3, a2, a3
+; PURECAP-ATOMICS-NEXT:    csc.c.aqrl a3, a3, (a0)
 ; PURECAP-ATOMICS-NEXT:    bnez a3, .LBB10_1
 ; PURECAP-ATOMICS-NEXT:  # %bb.2:
-; PURECAP-ATOMICS-NEXT:    cmove ca0, ca2
+; PURECAP-ATOMICS-NEXT:    cmove a0, a2
 ; PURECAP-ATOMICS-NEXT:    cret
 ;
 ; PURECAP-LIBCALLS-LABEL: atomic_cap_ptr_or:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -80
-; PURECAP-LIBCALLS-NEXT:    csc cra, 64(csp) # 16-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs0, 48(csp) # 16-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs1, 32(csp) # 16-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs2, 16(csp) # 16-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    cmove cs2, ca1
-; PURECAP-LIBCALLS-NEXT:    cmove cs1, ca0
-; PURECAP-LIBCALLS-NEXT:    clc ca1, 0(ca0)
-; PURECAP-LIBCALLS-NEXT:    cincoffset ca0, csp, 0
-; PURECAP-LIBCALLS-NEXT:    csetbounds cs0, ca0, 16
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -80
+; PURECAP-LIBCALLS-NEXT:    csc ra, 64(sp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s0, 48(sp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s1, 32(sp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s2, 16(sp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    cmove s0, a1
+; PURECAP-LIBCALLS-NEXT:    cmove s1, a0
+; PURECAP-LIBCALLS-NEXT:    clc a1, 0(a0)
+; PURECAP-LIBCALLS-NEXT:    cincoffset a0, sp, 0
+; PURECAP-LIBCALLS-NEXT:    csetbounds s2, a0, 16
 ; PURECAP-LIBCALLS-NEXT:  .LBB10_1: # %atomicrmw.start
 ; PURECAP-LIBCALLS-NEXT:    # =>This Inner Loop Header: Depth=1
-; PURECAP-LIBCALLS-NEXT:    or a0, a1, s2
-; PURECAP-LIBCALLS-NEXT:    csetaddr ca2, ca1, a0
-; PURECAP-LIBCALLS-NEXT:    csc ca1, 0(csp)
+; PURECAP-LIBCALLS-NEXT:    or a0, a1, s0
+; PURECAP-LIBCALLS-NEXT:    csetaddr a2, a1, a0
+; PURECAP-LIBCALLS-NEXT:    csc a1, 0(sp)
 ; PURECAP-LIBCALLS-NEXT:    li a3, 5
 ; PURECAP-LIBCALLS-NEXT:    li a4, 5
-; PURECAP-LIBCALLS-NEXT:    cmove ca0, cs1
-; PURECAP-LIBCALLS-NEXT:    cmove ca1, cs0
+; PURECAP-LIBCALLS-NEXT:    cmove a0, s1
+; PURECAP-LIBCALLS-NEXT:    cmove a1, s2
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_compare_exchange_cap
-; PURECAP-LIBCALLS-NEXT:    clc ca1, 0(csp)
+; PURECAP-LIBCALLS-NEXT:    clc a1, 0(sp)
 ; PURECAP-LIBCALLS-NEXT:    beqz a0, .LBB10_1
 ; PURECAP-LIBCALLS-NEXT:  # %bb.2: # %atomicrmw.end
-; PURECAP-LIBCALLS-NEXT:    cmove ca0, ca1
-; PURECAP-LIBCALLS-NEXT:    clc cra, 64(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs0, 48(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs1, 32(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs2, 16(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 80
+; PURECAP-LIBCALLS-NEXT:    cmove a0, a1
+; PURECAP-LIBCALLS-NEXT:    clc ra, 64(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s0, 48(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s1, 32(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s2, 16(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 80
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: atomic_cap_ptr_or:
 ; HYBRID:       # %bb.0:
 ; HYBRID-NEXT:    addi sp, sp, -64
 ; HYBRID-NEXT:    sd ra, 56(sp) # 8-byte Folded Spill
-; HYBRID-NEXT:    sc ca0, 16(sp) # 16-byte Folded Spill
-; HYBRID-NEXT:    lc.cap ca3, (ca0)
-; HYBRID-NEXT:    sc ca1, 0(sp) # 16-byte Folded Spill
+; HYBRID-NEXT:    sc a0, 16(sp) # 16-byte Folded Spill
+; HYBRID-NEXT:    lc.cap a3, (a0)
+; HYBRID-NEXT:    sc a1, 0(sp) # 16-byte Folded Spill
 ; HYBRID-NEXT:  .LBB10_1: # %atomicrmw.start
 ; HYBRID-NEXT:    # =>This Inner Loop Header: Depth=1
-; HYBRID-NEXT:    lc ca0, 0(sp) # 16-byte Folded Reload
+; HYBRID-NEXT:    lc a0, 0(sp) # 16-byte Folded Reload
 ; HYBRID-NEXT:    or a0, a3, a0
-; HYBRID-NEXT:    csetaddr ca2, ca3, a0
-; HYBRID-NEXT:    sc ca3, 32(sp)
+; HYBRID-NEXT:    csetaddr a2, a3, a0
+; HYBRID-NEXT:    sc a3, 32(sp)
 ; HYBRID-NEXT:    addi a1, sp, 32
 ; HYBRID-NEXT:    li a3, 5
 ; HYBRID-NEXT:    li a4, 5
-; HYBRID-NEXT:    lc ca0, 16(sp) # 16-byte Folded Reload
+; HYBRID-NEXT:    lc a0, 16(sp) # 16-byte Folded Reload
 ; HYBRID-NEXT:    call __atomic_compare_exchange_cap_c
-; HYBRID-NEXT:    lc ca3, 32(sp)
+; HYBRID-NEXT:    lc a3, 32(sp)
 ; HYBRID-NEXT:    beqz a0, .LBB10_1
 ; HYBRID-NEXT:  # %bb.2: # %atomicrmw.end
-; HYBRID-NEXT:    cmove ca0, ca3
+; HYBRID-NEXT:    cmove a0, a3
 ; HYBRID-NEXT:    ld ra, 56(sp) # 8-byte Folded Reload
 ; HYBRID-NEXT:    addi sp, sp, 64
 ; HYBRID-NEXT:    ret
@@ -563,70 +563,70 @@ define i32 addrspace(200)* @atomic_cap_ptr_xor(i32 addrspace(200)* addrspace(200
 ; PURECAP-ATOMICS-LABEL: atomic_cap_ptr_xor:
 ; PURECAP-ATOMICS:       # %bb.0:
 ; PURECAP-ATOMICS-NEXT:  .LBB11_1: # =>This Inner Loop Header: Depth=1
-; PURECAP-ATOMICS-NEXT:    clr.c.aqrl ca2, (ca0)
+; PURECAP-ATOMICS-NEXT:    clr.c.aqrl a2, (a0)
 ; PURECAP-ATOMICS-NEXT:    xor a3, a2, a1
-; PURECAP-ATOMICS-NEXT:    csetaddr ca3, ca2, a3
-; PURECAP-ATOMICS-NEXT:    csc.c.aqrl a3, ca3, (ca0)
+; PURECAP-ATOMICS-NEXT:    csetaddr a3, a2, a3
+; PURECAP-ATOMICS-NEXT:    csc.c.aqrl a3, a3, (a0)
 ; PURECAP-ATOMICS-NEXT:    bnez a3, .LBB11_1
 ; PURECAP-ATOMICS-NEXT:  # %bb.2:
-; PURECAP-ATOMICS-NEXT:    cmove ca0, ca2
+; PURECAP-ATOMICS-NEXT:    cmove a0, a2
 ; PURECAP-ATOMICS-NEXT:    cret
 ;
 ; PURECAP-LIBCALLS-LABEL: atomic_cap_ptr_xor:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -80
-; PURECAP-LIBCALLS-NEXT:    csc cra, 64(csp) # 16-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs0, 48(csp) # 16-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs1, 32(csp) # 16-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs2, 16(csp) # 16-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    cmove cs2, ca1
-; PURECAP-LIBCALLS-NEXT:    cmove cs1, ca0
-; PURECAP-LIBCALLS-NEXT:    clc ca1, 0(ca0)
-; PURECAP-LIBCALLS-NEXT:    cincoffset ca0, csp, 0
-; PURECAP-LIBCALLS-NEXT:    csetbounds cs0, ca0, 16
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -80
+; PURECAP-LIBCALLS-NEXT:    csc ra, 64(sp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s0, 48(sp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s1, 32(sp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s2, 16(sp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    cmove s0, a1
+; PURECAP-LIBCALLS-NEXT:    cmove s1, a0
+; PURECAP-LIBCALLS-NEXT:    clc a1, 0(a0)
+; PURECAP-LIBCALLS-NEXT:    cincoffset a0, sp, 0
+; PURECAP-LIBCALLS-NEXT:    csetbounds s2, a0, 16
 ; PURECAP-LIBCALLS-NEXT:  .LBB11_1: # %atomicrmw.start
 ; PURECAP-LIBCALLS-NEXT:    # =>This Inner Loop Header: Depth=1
-; PURECAP-LIBCALLS-NEXT:    xor a0, a1, s2
-; PURECAP-LIBCALLS-NEXT:    csetaddr ca2, ca1, a0
-; PURECAP-LIBCALLS-NEXT:    csc ca1, 0(csp)
+; PURECAP-LIBCALLS-NEXT:    xor a0, a1, s0
+; PURECAP-LIBCALLS-NEXT:    csetaddr a2, a1, a0
+; PURECAP-LIBCALLS-NEXT:    csc a1, 0(sp)
 ; PURECAP-LIBCALLS-NEXT:    li a3, 5
 ; PURECAP-LIBCALLS-NEXT:    li a4, 5
-; PURECAP-LIBCALLS-NEXT:    cmove ca0, cs1
-; PURECAP-LIBCALLS-NEXT:    cmove ca1, cs0
+; PURECAP-LIBCALLS-NEXT:    cmove a0, s1
+; PURECAP-LIBCALLS-NEXT:    cmove a1, s2
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_compare_exchange_cap
-; PURECAP-LIBCALLS-NEXT:    clc ca1, 0(csp)
+; PURECAP-LIBCALLS-NEXT:    clc a1, 0(sp)
 ; PURECAP-LIBCALLS-NEXT:    beqz a0, .LBB11_1
 ; PURECAP-LIBCALLS-NEXT:  # %bb.2: # %atomicrmw.end
-; PURECAP-LIBCALLS-NEXT:    cmove ca0, ca1
-; PURECAP-LIBCALLS-NEXT:    clc cra, 64(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs0, 48(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs1, 32(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs2, 16(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 80
+; PURECAP-LIBCALLS-NEXT:    cmove a0, a1
+; PURECAP-LIBCALLS-NEXT:    clc ra, 64(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s0, 48(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s1, 32(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s2, 16(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 80
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: atomic_cap_ptr_xor:
 ; HYBRID:       # %bb.0:
 ; HYBRID-NEXT:    addi sp, sp, -64
 ; HYBRID-NEXT:    sd ra, 56(sp) # 8-byte Folded Spill
-; HYBRID-NEXT:    sc ca0, 16(sp) # 16-byte Folded Spill
-; HYBRID-NEXT:    lc.cap ca3, (ca0)
-; HYBRID-NEXT:    sc ca1, 0(sp) # 16-byte Folded Spill
+; HYBRID-NEXT:    sc a0, 16(sp) # 16-byte Folded Spill
+; HYBRID-NEXT:    lc.cap a3, (a0)
+; HYBRID-NEXT:    sc a1, 0(sp) # 16-byte Folded Spill
 ; HYBRID-NEXT:  .LBB11_1: # %atomicrmw.start
 ; HYBRID-NEXT:    # =>This Inner Loop Header: Depth=1
-; HYBRID-NEXT:    lc ca0, 0(sp) # 16-byte Folded Reload
+; HYBRID-NEXT:    lc a0, 0(sp) # 16-byte Folded Reload
 ; HYBRID-NEXT:    xor a0, a3, a0
-; HYBRID-NEXT:    csetaddr ca2, ca3, a0
-; HYBRID-NEXT:    sc ca3, 32(sp)
+; HYBRID-NEXT:    csetaddr a2, a3, a0
+; HYBRID-NEXT:    sc a3, 32(sp)
 ; HYBRID-NEXT:    addi a1, sp, 32
 ; HYBRID-NEXT:    li a3, 5
 ; HYBRID-NEXT:    li a4, 5
-; HYBRID-NEXT:    lc ca0, 16(sp) # 16-byte Folded Reload
+; HYBRID-NEXT:    lc a0, 16(sp) # 16-byte Folded Reload
 ; HYBRID-NEXT:    call __atomic_compare_exchange_cap_c
-; HYBRID-NEXT:    lc ca3, 32(sp)
+; HYBRID-NEXT:    lc a3, 32(sp)
 ; HYBRID-NEXT:    beqz a0, .LBB11_1
 ; HYBRID-NEXT:  # %bb.2: # %atomicrmw.end
-; HYBRID-NEXT:    cmove ca0, ca3
+; HYBRID-NEXT:    cmove a0, a3
 ; HYBRID-NEXT:    ld ra, 56(sp) # 8-byte Folded Reload
 ; HYBRID-NEXT:    addi sp, sp, 64
 ; HYBRID-NEXT:    ret
@@ -638,87 +638,87 @@ define i32 addrspace(200)* @atomic_cap_ptr_max(i32 addrspace(200)* addrspace(200
 ; PURECAP-ATOMICS-LABEL: atomic_cap_ptr_max:
 ; PURECAP-ATOMICS:       # %bb.0:
 ; PURECAP-ATOMICS-NEXT:  .LBB12_1: # =>This Inner Loop Header: Depth=1
-; PURECAP-ATOMICS-NEXT:    clr.c.aqrl ca2, (ca0)
-; PURECAP-ATOMICS-NEXT:    cmove ca3, ca2
+; PURECAP-ATOMICS-NEXT:    clr.c.aqrl a2, (a0)
+; PURECAP-ATOMICS-NEXT:    cmove a3, a2
 ; PURECAP-ATOMICS-NEXT:    bge a3, a1, .LBB12_3
 ; PURECAP-ATOMICS-NEXT:  # %bb.2: # in Loop: Header=BB12_1 Depth=1
-; PURECAP-ATOMICS-NEXT:    cmove ca3, ca2
+; PURECAP-ATOMICS-NEXT:    cmove a3, a2
 ; PURECAP-ATOMICS-NEXT:  .LBB12_3: # in Loop: Header=BB12_1 Depth=1
-; PURECAP-ATOMICS-NEXT:    csc.c.aqrl a3, ca3, (ca0)
+; PURECAP-ATOMICS-NEXT:    csc.c.aqrl a3, a3, (a0)
 ; PURECAP-ATOMICS-NEXT:    bnez a3, .LBB12_1
 ; PURECAP-ATOMICS-NEXT:  # %bb.4:
-; PURECAP-ATOMICS-NEXT:    cmove ca0, ca2
+; PURECAP-ATOMICS-NEXT:    cmove a0, a2
 ; PURECAP-ATOMICS-NEXT:    cret
 ;
 ; PURECAP-LIBCALLS-LABEL: atomic_cap_ptr_max:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -80
-; PURECAP-LIBCALLS-NEXT:    csc cra, 64(csp) # 16-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs0, 48(csp) # 16-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs1, 32(csp) # 16-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs2, 16(csp) # 16-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    cmove cs0, ca1
-; PURECAP-LIBCALLS-NEXT:    cmove cs2, ca0
-; PURECAP-LIBCALLS-NEXT:    clc ca1, 0(ca0)
-; PURECAP-LIBCALLS-NEXT:    cincoffset ca0, csp, 0
-; PURECAP-LIBCALLS-NEXT:    csetbounds cs1, ca0, 16
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -80
+; PURECAP-LIBCALLS-NEXT:    csc ra, 64(sp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s0, 48(sp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s1, 32(sp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s2, 16(sp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    cmove s0, a1
+; PURECAP-LIBCALLS-NEXT:    cmove s1, a0
+; PURECAP-LIBCALLS-NEXT:    clc a1, 0(a0)
+; PURECAP-LIBCALLS-NEXT:    cincoffset a0, sp, 0
+; PURECAP-LIBCALLS-NEXT:    csetbounds s2, a0, 16
 ; PURECAP-LIBCALLS-NEXT:    j .LBB12_2
 ; PURECAP-LIBCALLS-NEXT:  .LBB12_1: # %atomicrmw.start
 ; PURECAP-LIBCALLS-NEXT:    # in Loop: Header=BB12_2 Depth=1
-; PURECAP-LIBCALLS-NEXT:    csc ca1, 0(csp)
+; PURECAP-LIBCALLS-NEXT:    csc a1, 0(sp)
 ; PURECAP-LIBCALLS-NEXT:    li a3, 5
 ; PURECAP-LIBCALLS-NEXT:    li a4, 5
-; PURECAP-LIBCALLS-NEXT:    cmove ca0, cs2
-; PURECAP-LIBCALLS-NEXT:    cmove ca1, cs1
+; PURECAP-LIBCALLS-NEXT:    cmove a0, s1
+; PURECAP-LIBCALLS-NEXT:    cmove a1, s2
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_compare_exchange_cap
-; PURECAP-LIBCALLS-NEXT:    clc ca1, 0(csp)
+; PURECAP-LIBCALLS-NEXT:    clc a1, 0(sp)
 ; PURECAP-LIBCALLS-NEXT:    bnez a0, .LBB12_4
 ; PURECAP-LIBCALLS-NEXT:  .LBB12_2: # %atomicrmw.start
 ; PURECAP-LIBCALLS-NEXT:    # =>This Inner Loop Header: Depth=1
-; PURECAP-LIBCALLS-NEXT:    cmove ca2, ca1
+; PURECAP-LIBCALLS-NEXT:    cmove a2, a1
 ; PURECAP-LIBCALLS-NEXT:    blt s0, a1, .LBB12_1
 ; PURECAP-LIBCALLS-NEXT:  # %bb.3: # %atomicrmw.start
 ; PURECAP-LIBCALLS-NEXT:    # in Loop: Header=BB12_2 Depth=1
-; PURECAP-LIBCALLS-NEXT:    cmove ca2, cs0
+; PURECAP-LIBCALLS-NEXT:    cmove a2, s0
 ; PURECAP-LIBCALLS-NEXT:    j .LBB12_1
 ; PURECAP-LIBCALLS-NEXT:  .LBB12_4: # %atomicrmw.end
-; PURECAP-LIBCALLS-NEXT:    cmove ca0, ca1
-; PURECAP-LIBCALLS-NEXT:    clc cra, 64(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs0, 48(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs1, 32(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs2, 16(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 80
+; PURECAP-LIBCALLS-NEXT:    cmove a0, a1
+; PURECAP-LIBCALLS-NEXT:    clc ra, 64(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s0, 48(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s1, 32(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s2, 16(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 80
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: atomic_cap_ptr_max:
 ; HYBRID:       # %bb.0:
 ; HYBRID-NEXT:    addi sp, sp, -64
 ; HYBRID-NEXT:    sd ra, 56(sp) # 8-byte Folded Spill
-; HYBRID-NEXT:    sc ca0, 0(sp) # 16-byte Folded Spill
-; HYBRID-NEXT:    lc.cap ca3, (ca0)
-; HYBRID-NEXT:    sc ca1, 16(sp) # 16-byte Folded Spill
+; HYBRID-NEXT:    sc a0, 0(sp) # 16-byte Folded Spill
+; HYBRID-NEXT:    lc.cap a3, (a0)
+; HYBRID-NEXT:    sc a1, 16(sp) # 16-byte Folded Spill
 ; HYBRID-NEXT:    j .LBB12_2
 ; HYBRID-NEXT:  .LBB12_1: # %atomicrmw.start
 ; HYBRID-NEXT:    # in Loop: Header=BB12_2 Depth=1
-; HYBRID-NEXT:    sc ca3, 32(sp)
+; HYBRID-NEXT:    sc a3, 32(sp)
 ; HYBRID-NEXT:    addi a1, sp, 32
 ; HYBRID-NEXT:    li a3, 5
 ; HYBRID-NEXT:    li a4, 5
-; HYBRID-NEXT:    lc ca0, 0(sp) # 16-byte Folded Reload
+; HYBRID-NEXT:    lc a0, 0(sp) # 16-byte Folded Reload
 ; HYBRID-NEXT:    call __atomic_compare_exchange_cap_c
-; HYBRID-NEXT:    lc ca3, 32(sp)
+; HYBRID-NEXT:    lc a3, 32(sp)
 ; HYBRID-NEXT:    bnez a0, .LBB12_4
 ; HYBRID-NEXT:  .LBB12_2: # %atomicrmw.start
 ; HYBRID-NEXT:    # =>This Inner Loop Header: Depth=1
-; HYBRID-NEXT:    cmove ca2, ca3
-; HYBRID-NEXT:    lc ca0, 16(sp) # 16-byte Folded Reload
+; HYBRID-NEXT:    cmove a2, a3
+; HYBRID-NEXT:    lc a0, 16(sp) # 16-byte Folded Reload
 ; HYBRID-NEXT:    blt a0, a3, .LBB12_1
 ; HYBRID-NEXT:  # %bb.3: # %atomicrmw.start
 ; HYBRID-NEXT:    # in Loop: Header=BB12_2 Depth=1
-; HYBRID-NEXT:    lc ca2, 16(sp) # 16-byte Folded Reload
+; HYBRID-NEXT:    lc a2, 16(sp) # 16-byte Folded Reload
 ; HYBRID-NEXT:    j .LBB12_1
 ; HYBRID-NEXT:  .LBB12_4: # %atomicrmw.end
-; HYBRID-NEXT:    cmove ca0, ca3
+; HYBRID-NEXT:    cmove a0, a3
 ; HYBRID-NEXT:    ld ra, 56(sp) # 8-byte Folded Reload
 ; HYBRID-NEXT:    addi sp, sp, 64
 ; HYBRID-NEXT:    ret
@@ -730,87 +730,87 @@ define i32 addrspace(200)* @atomic_cap_ptr_min(i32 addrspace(200)* addrspace(200
 ; PURECAP-ATOMICS-LABEL: atomic_cap_ptr_min:
 ; PURECAP-ATOMICS:       # %bb.0:
 ; PURECAP-ATOMICS-NEXT:  .LBB13_1: # =>This Inner Loop Header: Depth=1
-; PURECAP-ATOMICS-NEXT:    clr.c.aqrl ca2, (ca0)
-; PURECAP-ATOMICS-NEXT:    cmove ca3, ca2
+; PURECAP-ATOMICS-NEXT:    clr.c.aqrl a2, (a0)
+; PURECAP-ATOMICS-NEXT:    cmove a3, a2
 ; PURECAP-ATOMICS-NEXT:    bge a1, a3, .LBB13_3
 ; PURECAP-ATOMICS-NEXT:  # %bb.2: # in Loop: Header=BB13_1 Depth=1
-; PURECAP-ATOMICS-NEXT:    cmove ca3, ca2
+; PURECAP-ATOMICS-NEXT:    cmove a3, a2
 ; PURECAP-ATOMICS-NEXT:  .LBB13_3: # in Loop: Header=BB13_1 Depth=1
-; PURECAP-ATOMICS-NEXT:    csc.c.aqrl a3, ca3, (ca0)
+; PURECAP-ATOMICS-NEXT:    csc.c.aqrl a3, a3, (a0)
 ; PURECAP-ATOMICS-NEXT:    bnez a3, .LBB13_1
 ; PURECAP-ATOMICS-NEXT:  # %bb.4:
-; PURECAP-ATOMICS-NEXT:    cmove ca0, ca2
+; PURECAP-ATOMICS-NEXT:    cmove a0, a2
 ; PURECAP-ATOMICS-NEXT:    cret
 ;
 ; PURECAP-LIBCALLS-LABEL: atomic_cap_ptr_min:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -80
-; PURECAP-LIBCALLS-NEXT:    csc cra, 64(csp) # 16-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs0, 48(csp) # 16-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs1, 32(csp) # 16-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs2, 16(csp) # 16-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    cmove cs0, ca1
-; PURECAP-LIBCALLS-NEXT:    cmove cs2, ca0
-; PURECAP-LIBCALLS-NEXT:    clc ca1, 0(ca0)
-; PURECAP-LIBCALLS-NEXT:    cincoffset ca0, csp, 0
-; PURECAP-LIBCALLS-NEXT:    csetbounds cs1, ca0, 16
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -80
+; PURECAP-LIBCALLS-NEXT:    csc ra, 64(sp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s0, 48(sp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s1, 32(sp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s2, 16(sp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    cmove s0, a1
+; PURECAP-LIBCALLS-NEXT:    cmove s1, a0
+; PURECAP-LIBCALLS-NEXT:    clc a1, 0(a0)
+; PURECAP-LIBCALLS-NEXT:    cincoffset a0, sp, 0
+; PURECAP-LIBCALLS-NEXT:    csetbounds s2, a0, 16
 ; PURECAP-LIBCALLS-NEXT:    j .LBB13_2
 ; PURECAP-LIBCALLS-NEXT:  .LBB13_1: # %atomicrmw.start
 ; PURECAP-LIBCALLS-NEXT:    # in Loop: Header=BB13_2 Depth=1
-; PURECAP-LIBCALLS-NEXT:    csc ca1, 0(csp)
+; PURECAP-LIBCALLS-NEXT:    csc a1, 0(sp)
 ; PURECAP-LIBCALLS-NEXT:    li a3, 5
 ; PURECAP-LIBCALLS-NEXT:    li a4, 5
-; PURECAP-LIBCALLS-NEXT:    cmove ca0, cs2
-; PURECAP-LIBCALLS-NEXT:    cmove ca1, cs1
+; PURECAP-LIBCALLS-NEXT:    cmove a0, s1
+; PURECAP-LIBCALLS-NEXT:    cmove a1, s2
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_compare_exchange_cap
-; PURECAP-LIBCALLS-NEXT:    clc ca1, 0(csp)
+; PURECAP-LIBCALLS-NEXT:    clc a1, 0(sp)
 ; PURECAP-LIBCALLS-NEXT:    bnez a0, .LBB13_4
 ; PURECAP-LIBCALLS-NEXT:  .LBB13_2: # %atomicrmw.start
 ; PURECAP-LIBCALLS-NEXT:    # =>This Inner Loop Header: Depth=1
-; PURECAP-LIBCALLS-NEXT:    cmove ca2, ca1
+; PURECAP-LIBCALLS-NEXT:    cmove a2, a1
 ; PURECAP-LIBCALLS-NEXT:    bge s0, a1, .LBB13_1
 ; PURECAP-LIBCALLS-NEXT:  # %bb.3: # %atomicrmw.start
 ; PURECAP-LIBCALLS-NEXT:    # in Loop: Header=BB13_2 Depth=1
-; PURECAP-LIBCALLS-NEXT:    cmove ca2, cs0
+; PURECAP-LIBCALLS-NEXT:    cmove a2, s0
 ; PURECAP-LIBCALLS-NEXT:    j .LBB13_1
 ; PURECAP-LIBCALLS-NEXT:  .LBB13_4: # %atomicrmw.end
-; PURECAP-LIBCALLS-NEXT:    cmove ca0, ca1
-; PURECAP-LIBCALLS-NEXT:    clc cra, 64(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs0, 48(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs1, 32(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs2, 16(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 80
+; PURECAP-LIBCALLS-NEXT:    cmove a0, a1
+; PURECAP-LIBCALLS-NEXT:    clc ra, 64(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s0, 48(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s1, 32(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s2, 16(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 80
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: atomic_cap_ptr_min:
 ; HYBRID:       # %bb.0:
 ; HYBRID-NEXT:    addi sp, sp, -64
 ; HYBRID-NEXT:    sd ra, 56(sp) # 8-byte Folded Spill
-; HYBRID-NEXT:    sc ca0, 0(sp) # 16-byte Folded Spill
-; HYBRID-NEXT:    lc.cap ca3, (ca0)
-; HYBRID-NEXT:    sc ca1, 16(sp) # 16-byte Folded Spill
+; HYBRID-NEXT:    sc a0, 0(sp) # 16-byte Folded Spill
+; HYBRID-NEXT:    lc.cap a3, (a0)
+; HYBRID-NEXT:    sc a1, 16(sp) # 16-byte Folded Spill
 ; HYBRID-NEXT:    j .LBB13_2
 ; HYBRID-NEXT:  .LBB13_1: # %atomicrmw.start
 ; HYBRID-NEXT:    # in Loop: Header=BB13_2 Depth=1
-; HYBRID-NEXT:    sc ca3, 32(sp)
+; HYBRID-NEXT:    sc a3, 32(sp)
 ; HYBRID-NEXT:    addi a1, sp, 32
 ; HYBRID-NEXT:    li a3, 5
 ; HYBRID-NEXT:    li a4, 5
-; HYBRID-NEXT:    lc ca0, 0(sp) # 16-byte Folded Reload
+; HYBRID-NEXT:    lc a0, 0(sp) # 16-byte Folded Reload
 ; HYBRID-NEXT:    call __atomic_compare_exchange_cap_c
-; HYBRID-NEXT:    lc ca3, 32(sp)
+; HYBRID-NEXT:    lc a3, 32(sp)
 ; HYBRID-NEXT:    bnez a0, .LBB13_4
 ; HYBRID-NEXT:  .LBB13_2: # %atomicrmw.start
 ; HYBRID-NEXT:    # =>This Inner Loop Header: Depth=1
-; HYBRID-NEXT:    cmove ca2, ca3
-; HYBRID-NEXT:    lc ca0, 16(sp) # 16-byte Folded Reload
+; HYBRID-NEXT:    cmove a2, a3
+; HYBRID-NEXT:    lc a0, 16(sp) # 16-byte Folded Reload
 ; HYBRID-NEXT:    bge a0, a3, .LBB13_1
 ; HYBRID-NEXT:  # %bb.3: # %atomicrmw.start
 ; HYBRID-NEXT:    # in Loop: Header=BB13_2 Depth=1
-; HYBRID-NEXT:    lc ca2, 16(sp) # 16-byte Folded Reload
+; HYBRID-NEXT:    lc a2, 16(sp) # 16-byte Folded Reload
 ; HYBRID-NEXT:    j .LBB13_1
 ; HYBRID-NEXT:  .LBB13_4: # %atomicrmw.end
-; HYBRID-NEXT:    cmove ca0, ca3
+; HYBRID-NEXT:    cmove a0, a3
 ; HYBRID-NEXT:    ld ra, 56(sp) # 8-byte Folded Reload
 ; HYBRID-NEXT:    addi sp, sp, 64
 ; HYBRID-NEXT:    ret
@@ -822,87 +822,87 @@ define i32 addrspace(200)* @atomic_cap_ptr_umax(i32 addrspace(200)* addrspace(20
 ; PURECAP-ATOMICS-LABEL: atomic_cap_ptr_umax:
 ; PURECAP-ATOMICS:       # %bb.0:
 ; PURECAP-ATOMICS-NEXT:  .LBB14_1: # =>This Inner Loop Header: Depth=1
-; PURECAP-ATOMICS-NEXT:    clr.c.aqrl ca2, (ca0)
-; PURECAP-ATOMICS-NEXT:    cmove ca3, ca2
+; PURECAP-ATOMICS-NEXT:    clr.c.aqrl a2, (a0)
+; PURECAP-ATOMICS-NEXT:    cmove a3, a2
 ; PURECAP-ATOMICS-NEXT:    bgeu a3, a1, .LBB14_3
 ; PURECAP-ATOMICS-NEXT:  # %bb.2: # in Loop: Header=BB14_1 Depth=1
-; PURECAP-ATOMICS-NEXT:    cmove ca3, ca2
+; PURECAP-ATOMICS-NEXT:    cmove a3, a2
 ; PURECAP-ATOMICS-NEXT:  .LBB14_3: # in Loop: Header=BB14_1 Depth=1
-; PURECAP-ATOMICS-NEXT:    csc.c.aqrl a3, ca3, (ca0)
+; PURECAP-ATOMICS-NEXT:    csc.c.aqrl a3, a3, (a0)
 ; PURECAP-ATOMICS-NEXT:    bnez a3, .LBB14_1
 ; PURECAP-ATOMICS-NEXT:  # %bb.4:
-; PURECAP-ATOMICS-NEXT:    cmove ca0, ca2
+; PURECAP-ATOMICS-NEXT:    cmove a0, a2
 ; PURECAP-ATOMICS-NEXT:    cret
 ;
 ; PURECAP-LIBCALLS-LABEL: atomic_cap_ptr_umax:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -80
-; PURECAP-LIBCALLS-NEXT:    csc cra, 64(csp) # 16-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs0, 48(csp) # 16-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs1, 32(csp) # 16-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs2, 16(csp) # 16-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    cmove cs0, ca1
-; PURECAP-LIBCALLS-NEXT:    cmove cs2, ca0
-; PURECAP-LIBCALLS-NEXT:    clc ca1, 0(ca0)
-; PURECAP-LIBCALLS-NEXT:    cincoffset ca0, csp, 0
-; PURECAP-LIBCALLS-NEXT:    csetbounds cs1, ca0, 16
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -80
+; PURECAP-LIBCALLS-NEXT:    csc ra, 64(sp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s0, 48(sp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s1, 32(sp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s2, 16(sp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    cmove s0, a1
+; PURECAP-LIBCALLS-NEXT:    cmove s1, a0
+; PURECAP-LIBCALLS-NEXT:    clc a1, 0(a0)
+; PURECAP-LIBCALLS-NEXT:    cincoffset a0, sp, 0
+; PURECAP-LIBCALLS-NEXT:    csetbounds s2, a0, 16
 ; PURECAP-LIBCALLS-NEXT:    j .LBB14_2
 ; PURECAP-LIBCALLS-NEXT:  .LBB14_1: # %atomicrmw.start
 ; PURECAP-LIBCALLS-NEXT:    # in Loop: Header=BB14_2 Depth=1
-; PURECAP-LIBCALLS-NEXT:    csc ca1, 0(csp)
+; PURECAP-LIBCALLS-NEXT:    csc a1, 0(sp)
 ; PURECAP-LIBCALLS-NEXT:    li a3, 5
 ; PURECAP-LIBCALLS-NEXT:    li a4, 5
-; PURECAP-LIBCALLS-NEXT:    cmove ca0, cs2
-; PURECAP-LIBCALLS-NEXT:    cmove ca1, cs1
+; PURECAP-LIBCALLS-NEXT:    cmove a0, s1
+; PURECAP-LIBCALLS-NEXT:    cmove a1, s2
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_compare_exchange_cap
-; PURECAP-LIBCALLS-NEXT:    clc ca1, 0(csp)
+; PURECAP-LIBCALLS-NEXT:    clc a1, 0(sp)
 ; PURECAP-LIBCALLS-NEXT:    bnez a0, .LBB14_4
 ; PURECAP-LIBCALLS-NEXT:  .LBB14_2: # %atomicrmw.start
 ; PURECAP-LIBCALLS-NEXT:    # =>This Inner Loop Header: Depth=1
-; PURECAP-LIBCALLS-NEXT:    cmove ca2, ca1
+; PURECAP-LIBCALLS-NEXT:    cmove a2, a1
 ; PURECAP-LIBCALLS-NEXT:    bltu s0, a1, .LBB14_1
 ; PURECAP-LIBCALLS-NEXT:  # %bb.3: # %atomicrmw.start
 ; PURECAP-LIBCALLS-NEXT:    # in Loop: Header=BB14_2 Depth=1
-; PURECAP-LIBCALLS-NEXT:    cmove ca2, cs0
+; PURECAP-LIBCALLS-NEXT:    cmove a2, s0
 ; PURECAP-LIBCALLS-NEXT:    j .LBB14_1
 ; PURECAP-LIBCALLS-NEXT:  .LBB14_4: # %atomicrmw.end
-; PURECAP-LIBCALLS-NEXT:    cmove ca0, ca1
-; PURECAP-LIBCALLS-NEXT:    clc cra, 64(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs0, 48(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs1, 32(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs2, 16(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 80
+; PURECAP-LIBCALLS-NEXT:    cmove a0, a1
+; PURECAP-LIBCALLS-NEXT:    clc ra, 64(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s0, 48(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s1, 32(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s2, 16(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 80
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: atomic_cap_ptr_umax:
 ; HYBRID:       # %bb.0:
 ; HYBRID-NEXT:    addi sp, sp, -64
 ; HYBRID-NEXT:    sd ra, 56(sp) # 8-byte Folded Spill
-; HYBRID-NEXT:    sc ca0, 0(sp) # 16-byte Folded Spill
-; HYBRID-NEXT:    lc.cap ca3, (ca0)
-; HYBRID-NEXT:    sc ca1, 16(sp) # 16-byte Folded Spill
+; HYBRID-NEXT:    sc a0, 0(sp) # 16-byte Folded Spill
+; HYBRID-NEXT:    lc.cap a3, (a0)
+; HYBRID-NEXT:    sc a1, 16(sp) # 16-byte Folded Spill
 ; HYBRID-NEXT:    j .LBB14_2
 ; HYBRID-NEXT:  .LBB14_1: # %atomicrmw.start
 ; HYBRID-NEXT:    # in Loop: Header=BB14_2 Depth=1
-; HYBRID-NEXT:    sc ca3, 32(sp)
+; HYBRID-NEXT:    sc a3, 32(sp)
 ; HYBRID-NEXT:    addi a1, sp, 32
 ; HYBRID-NEXT:    li a3, 5
 ; HYBRID-NEXT:    li a4, 5
-; HYBRID-NEXT:    lc ca0, 0(sp) # 16-byte Folded Reload
+; HYBRID-NEXT:    lc a0, 0(sp) # 16-byte Folded Reload
 ; HYBRID-NEXT:    call __atomic_compare_exchange_cap_c
-; HYBRID-NEXT:    lc ca3, 32(sp)
+; HYBRID-NEXT:    lc a3, 32(sp)
 ; HYBRID-NEXT:    bnez a0, .LBB14_4
 ; HYBRID-NEXT:  .LBB14_2: # %atomicrmw.start
 ; HYBRID-NEXT:    # =>This Inner Loop Header: Depth=1
-; HYBRID-NEXT:    cmove ca2, ca3
-; HYBRID-NEXT:    lc ca0, 16(sp) # 16-byte Folded Reload
+; HYBRID-NEXT:    cmove a2, a3
+; HYBRID-NEXT:    lc a0, 16(sp) # 16-byte Folded Reload
 ; HYBRID-NEXT:    bltu a0, a3, .LBB14_1
 ; HYBRID-NEXT:  # %bb.3: # %atomicrmw.start
 ; HYBRID-NEXT:    # in Loop: Header=BB14_2 Depth=1
-; HYBRID-NEXT:    lc ca2, 16(sp) # 16-byte Folded Reload
+; HYBRID-NEXT:    lc a2, 16(sp) # 16-byte Folded Reload
 ; HYBRID-NEXT:    j .LBB14_1
 ; HYBRID-NEXT:  .LBB14_4: # %atomicrmw.end
-; HYBRID-NEXT:    cmove ca0, ca3
+; HYBRID-NEXT:    cmove a0, a3
 ; HYBRID-NEXT:    ld ra, 56(sp) # 8-byte Folded Reload
 ; HYBRID-NEXT:    addi sp, sp, 64
 ; HYBRID-NEXT:    ret
@@ -914,87 +914,87 @@ define i32 addrspace(200)* @atomic_cap_ptr_umin(i32 addrspace(200)* addrspace(20
 ; PURECAP-ATOMICS-LABEL: atomic_cap_ptr_umin:
 ; PURECAP-ATOMICS:       # %bb.0:
 ; PURECAP-ATOMICS-NEXT:  .LBB15_1: # =>This Inner Loop Header: Depth=1
-; PURECAP-ATOMICS-NEXT:    clr.c.aqrl ca2, (ca0)
-; PURECAP-ATOMICS-NEXT:    cmove ca3, ca2
+; PURECAP-ATOMICS-NEXT:    clr.c.aqrl a2, (a0)
+; PURECAP-ATOMICS-NEXT:    cmove a3, a2
 ; PURECAP-ATOMICS-NEXT:    bgeu a1, a3, .LBB15_3
 ; PURECAP-ATOMICS-NEXT:  # %bb.2: # in Loop: Header=BB15_1 Depth=1
-; PURECAP-ATOMICS-NEXT:    cmove ca3, ca2
+; PURECAP-ATOMICS-NEXT:    cmove a3, a2
 ; PURECAP-ATOMICS-NEXT:  .LBB15_3: # in Loop: Header=BB15_1 Depth=1
-; PURECAP-ATOMICS-NEXT:    csc.c.aqrl a3, ca3, (ca0)
+; PURECAP-ATOMICS-NEXT:    csc.c.aqrl a3, a3, (a0)
 ; PURECAP-ATOMICS-NEXT:    bnez a3, .LBB15_1
 ; PURECAP-ATOMICS-NEXT:  # %bb.4:
-; PURECAP-ATOMICS-NEXT:    cmove ca0, ca2
+; PURECAP-ATOMICS-NEXT:    cmove a0, a2
 ; PURECAP-ATOMICS-NEXT:    cret
 ;
 ; PURECAP-LIBCALLS-LABEL: atomic_cap_ptr_umin:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -80
-; PURECAP-LIBCALLS-NEXT:    csc cra, 64(csp) # 16-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs0, 48(csp) # 16-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs1, 32(csp) # 16-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs2, 16(csp) # 16-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    cmove cs0, ca1
-; PURECAP-LIBCALLS-NEXT:    cmove cs2, ca0
-; PURECAP-LIBCALLS-NEXT:    clc ca1, 0(ca0)
-; PURECAP-LIBCALLS-NEXT:    cincoffset ca0, csp, 0
-; PURECAP-LIBCALLS-NEXT:    csetbounds cs1, ca0, 16
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -80
+; PURECAP-LIBCALLS-NEXT:    csc ra, 64(sp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s0, 48(sp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s1, 32(sp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s2, 16(sp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    cmove s0, a1
+; PURECAP-LIBCALLS-NEXT:    cmove s1, a0
+; PURECAP-LIBCALLS-NEXT:    clc a1, 0(a0)
+; PURECAP-LIBCALLS-NEXT:    cincoffset a0, sp, 0
+; PURECAP-LIBCALLS-NEXT:    csetbounds s2, a0, 16
 ; PURECAP-LIBCALLS-NEXT:    j .LBB15_2
 ; PURECAP-LIBCALLS-NEXT:  .LBB15_1: # %atomicrmw.start
 ; PURECAP-LIBCALLS-NEXT:    # in Loop: Header=BB15_2 Depth=1
-; PURECAP-LIBCALLS-NEXT:    csc ca1, 0(csp)
+; PURECAP-LIBCALLS-NEXT:    csc a1, 0(sp)
 ; PURECAP-LIBCALLS-NEXT:    li a3, 5
 ; PURECAP-LIBCALLS-NEXT:    li a4, 5
-; PURECAP-LIBCALLS-NEXT:    cmove ca0, cs2
-; PURECAP-LIBCALLS-NEXT:    cmove ca1, cs1
+; PURECAP-LIBCALLS-NEXT:    cmove a0, s1
+; PURECAP-LIBCALLS-NEXT:    cmove a1, s2
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_compare_exchange_cap
-; PURECAP-LIBCALLS-NEXT:    clc ca1, 0(csp)
+; PURECAP-LIBCALLS-NEXT:    clc a1, 0(sp)
 ; PURECAP-LIBCALLS-NEXT:    bnez a0, .LBB15_4
 ; PURECAP-LIBCALLS-NEXT:  .LBB15_2: # %atomicrmw.start
 ; PURECAP-LIBCALLS-NEXT:    # =>This Inner Loop Header: Depth=1
-; PURECAP-LIBCALLS-NEXT:    cmove ca2, ca1
+; PURECAP-LIBCALLS-NEXT:    cmove a2, a1
 ; PURECAP-LIBCALLS-NEXT:    bgeu s0, a1, .LBB15_1
 ; PURECAP-LIBCALLS-NEXT:  # %bb.3: # %atomicrmw.start
 ; PURECAP-LIBCALLS-NEXT:    # in Loop: Header=BB15_2 Depth=1
-; PURECAP-LIBCALLS-NEXT:    cmove ca2, cs0
+; PURECAP-LIBCALLS-NEXT:    cmove a2, s0
 ; PURECAP-LIBCALLS-NEXT:    j .LBB15_1
 ; PURECAP-LIBCALLS-NEXT:  .LBB15_4: # %atomicrmw.end
-; PURECAP-LIBCALLS-NEXT:    cmove ca0, ca1
-; PURECAP-LIBCALLS-NEXT:    clc cra, 64(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs0, 48(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs1, 32(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs2, 16(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 80
+; PURECAP-LIBCALLS-NEXT:    cmove a0, a1
+; PURECAP-LIBCALLS-NEXT:    clc ra, 64(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s0, 48(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s1, 32(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s2, 16(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 80
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: atomic_cap_ptr_umin:
 ; HYBRID:       # %bb.0:
 ; HYBRID-NEXT:    addi sp, sp, -64
 ; HYBRID-NEXT:    sd ra, 56(sp) # 8-byte Folded Spill
-; HYBRID-NEXT:    sc ca0, 0(sp) # 16-byte Folded Spill
-; HYBRID-NEXT:    lc.cap ca3, (ca0)
-; HYBRID-NEXT:    sc ca1, 16(sp) # 16-byte Folded Spill
+; HYBRID-NEXT:    sc a0, 0(sp) # 16-byte Folded Spill
+; HYBRID-NEXT:    lc.cap a3, (a0)
+; HYBRID-NEXT:    sc a1, 16(sp) # 16-byte Folded Spill
 ; HYBRID-NEXT:    j .LBB15_2
 ; HYBRID-NEXT:  .LBB15_1: # %atomicrmw.start
 ; HYBRID-NEXT:    # in Loop: Header=BB15_2 Depth=1
-; HYBRID-NEXT:    sc ca3, 32(sp)
+; HYBRID-NEXT:    sc a3, 32(sp)
 ; HYBRID-NEXT:    addi a1, sp, 32
 ; HYBRID-NEXT:    li a3, 5
 ; HYBRID-NEXT:    li a4, 5
-; HYBRID-NEXT:    lc ca0, 0(sp) # 16-byte Folded Reload
+; HYBRID-NEXT:    lc a0, 0(sp) # 16-byte Folded Reload
 ; HYBRID-NEXT:    call __atomic_compare_exchange_cap_c
-; HYBRID-NEXT:    lc ca3, 32(sp)
+; HYBRID-NEXT:    lc a3, 32(sp)
 ; HYBRID-NEXT:    bnez a0, .LBB15_4
 ; HYBRID-NEXT:  .LBB15_2: # %atomicrmw.start
 ; HYBRID-NEXT:    # =>This Inner Loop Header: Depth=1
-; HYBRID-NEXT:    cmove ca2, ca3
-; HYBRID-NEXT:    lc ca0, 16(sp) # 16-byte Folded Reload
+; HYBRID-NEXT:    cmove a2, a3
+; HYBRID-NEXT:    lc a0, 16(sp) # 16-byte Folded Reload
 ; HYBRID-NEXT:    bgeu a0, a3, .LBB15_1
 ; HYBRID-NEXT:  # %bb.3: # %atomicrmw.start
 ; HYBRID-NEXT:    # in Loop: Header=BB15_2 Depth=1
-; HYBRID-NEXT:    lc ca2, 16(sp) # 16-byte Folded Reload
+; HYBRID-NEXT:    lc a2, 16(sp) # 16-byte Folded Reload
 ; HYBRID-NEXT:    j .LBB15_1
 ; HYBRID-NEXT:  .LBB15_4: # %atomicrmw.end
-; HYBRID-NEXT:    cmove ca0, ca3
+; HYBRID-NEXT:    cmove a0, a3
 ; HYBRID-NEXT:    ld ra, 56(sp) # 8-byte Folded Reload
 ; HYBRID-NEXT:    addi sp, sp, 64
 ; HYBRID-NEXT:    ret
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/atomic-rmw-cap-ptr.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/atomic-rmw-cap-ptr.ll
index 2b39924b669e2..e5208c6f4b945 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/atomic-rmw-cap-ptr.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/atomic-rmw-cap-ptr.ll
@@ -10,17 +10,17 @@
 define i64 @atomic_cap_ptr_xchg(i64 addrspace(200)* %ptr, i64 %val) nounwind {
 ; PURECAP-ATOMICS-LABEL: atomic_cap_ptr_xchg:
 ; PURECAP-ATOMICS:       # %bb.0:
-; PURECAP-ATOMICS-NEXT:    camoswap.d.aqrl a0, a1, (ca0)
+; PURECAP-ATOMICS-NEXT:    camoswap.d.aqrl a0, a1, (a0)
 ; PURECAP-ATOMICS-NEXT:    cret
 ;
 ; PURECAP-LIBCALLS-LABEL: atomic_cap_ptr_xchg:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -16
-; PURECAP-LIBCALLS-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -16
+; PURECAP-LIBCALLS-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; PURECAP-LIBCALLS-NEXT:    li a2, 5
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_exchange_8
-; PURECAP-LIBCALLS-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 16
+; PURECAP-LIBCALLS-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 16
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: atomic_cap_ptr_xchg:
@@ -39,17 +39,17 @@ define i64 @atomic_cap_ptr_xchg(i64 addrspace(200)* %ptr, i64 %val) nounwind {
 define i64 @atomic_cap_ptr_add(i64 addrspace(200)* %ptr, i64 %val) nounwind {
 ; PURECAP-ATOMICS-LABEL: atomic_cap_ptr_add:
 ; PURECAP-ATOMICS:       # %bb.0:
-; PURECAP-ATOMICS-NEXT:    camoadd.d.aqrl a0, a1, (ca0)
+; PURECAP-ATOMICS-NEXT:    camoadd.d.aqrl a0, a1, (a0)
 ; PURECAP-ATOMICS-NEXT:    cret
 ;
 ; PURECAP-LIBCALLS-LABEL: atomic_cap_ptr_add:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -16
-; PURECAP-LIBCALLS-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -16
+; PURECAP-LIBCALLS-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; PURECAP-LIBCALLS-NEXT:    li a2, 5
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_fetch_add_8
-; PURECAP-LIBCALLS-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 16
+; PURECAP-LIBCALLS-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 16
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: atomic_cap_ptr_add:
@@ -69,17 +69,17 @@ define i64 @atomic_cap_ptr_sub(i64 addrspace(200)* %ptr, i64 %val) nounwind {
 ; PURECAP-ATOMICS-LABEL: atomic_cap_ptr_sub:
 ; PURECAP-ATOMICS:       # %bb.0:
 ; PURECAP-ATOMICS-NEXT:    neg a1, a1
-; PURECAP-ATOMICS-NEXT:    camoadd.d.aqrl a0, a1, (ca0)
+; PURECAP-ATOMICS-NEXT:    camoadd.d.aqrl a0, a1, (a0)
 ; PURECAP-ATOMICS-NEXT:    cret
 ;
 ; PURECAP-LIBCALLS-LABEL: atomic_cap_ptr_sub:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -16
-; PURECAP-LIBCALLS-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -16
+; PURECAP-LIBCALLS-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; PURECAP-LIBCALLS-NEXT:    li a2, 5
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_fetch_sub_8
-; PURECAP-LIBCALLS-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 16
+; PURECAP-LIBCALLS-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 16
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: atomic_cap_ptr_sub:
@@ -98,17 +98,17 @@ define i64 @atomic_cap_ptr_sub(i64 addrspace(200)* %ptr, i64 %val) nounwind {
 define i64 @atomic_cap_ptr_and(i64 addrspace(200)* %ptr, i64 %val) nounwind {
 ; PURECAP-ATOMICS-LABEL: atomic_cap_ptr_and:
 ; PURECAP-ATOMICS:       # %bb.0:
-; PURECAP-ATOMICS-NEXT:    camoand.d.aqrl a0, a1, (ca0)
+; PURECAP-ATOMICS-NEXT:    camoand.d.aqrl a0, a1, (a0)
 ; PURECAP-ATOMICS-NEXT:    cret
 ;
 ; PURECAP-LIBCALLS-LABEL: atomic_cap_ptr_and:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -16
-; PURECAP-LIBCALLS-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -16
+; PURECAP-LIBCALLS-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; PURECAP-LIBCALLS-NEXT:    li a2, 5
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_fetch_and_8
-; PURECAP-LIBCALLS-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 16
+; PURECAP-LIBCALLS-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 16
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: atomic_cap_ptr_and:
@@ -128,10 +128,10 @@ define i64 @atomic_cap_ptr_nand(i64 addrspace(200)* %ptr, i64 %val) nounwind {
 ; PURECAP-ATOMICS-LABEL: atomic_cap_ptr_nand:
 ; PURECAP-ATOMICS:       # %bb.0:
 ; PURECAP-ATOMICS-NEXT:  .LBB4_1: # =>This Inner Loop Header: Depth=1
-; PURECAP-ATOMICS-NEXT:    clr.d.aqrl a2, (ca0)
+; PURECAP-ATOMICS-NEXT:    clr.d.aqrl a2, (a0)
 ; PURECAP-ATOMICS-NEXT:    and a3, a2, a1
 ; PURECAP-ATOMICS-NEXT:    not a3, a3
-; PURECAP-ATOMICS-NEXT:    csc.d.rl a3, a3, (ca0)
+; PURECAP-ATOMICS-NEXT:    csc.d.rl a3, a3, (a0)
 ; PURECAP-ATOMICS-NEXT:    bnez a3, .LBB4_1
 ; PURECAP-ATOMICS-NEXT:  # %bb.2:
 ; PURECAP-ATOMICS-NEXT:    mv a0, a2
@@ -139,12 +139,12 @@ define i64 @atomic_cap_ptr_nand(i64 addrspace(200)* %ptr, i64 %val) nounwind {
 ;
 ; PURECAP-LIBCALLS-LABEL: atomic_cap_ptr_nand:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -16
-; PURECAP-LIBCALLS-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -16
+; PURECAP-LIBCALLS-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; PURECAP-LIBCALLS-NEXT:    li a2, 5
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_fetch_nand_8
-; PURECAP-LIBCALLS-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 16
+; PURECAP-LIBCALLS-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 16
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: atomic_cap_ptr_nand:
@@ -163,17 +163,17 @@ define i64 @atomic_cap_ptr_nand(i64 addrspace(200)* %ptr, i64 %val) nounwind {
 define i64 @atomic_cap_ptr_or(i64 addrspace(200)* %ptr, i64 %val) nounwind {
 ; PURECAP-ATOMICS-LABEL: atomic_cap_ptr_or:
 ; PURECAP-ATOMICS:       # %bb.0:
-; PURECAP-ATOMICS-NEXT:    camoor.d.aqrl a0, a1, (ca0)
+; PURECAP-ATOMICS-NEXT:    camoor.d.aqrl a0, a1, (a0)
 ; PURECAP-ATOMICS-NEXT:    cret
 ;
 ; PURECAP-LIBCALLS-LABEL: atomic_cap_ptr_or:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -16
-; PURECAP-LIBCALLS-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -16
+; PURECAP-LIBCALLS-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; PURECAP-LIBCALLS-NEXT:    li a2, 5
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_fetch_or_8
-; PURECAP-LIBCALLS-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 16
+; PURECAP-LIBCALLS-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 16
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: atomic_cap_ptr_or:
@@ -192,17 +192,17 @@ define i64 @atomic_cap_ptr_or(i64 addrspace(200)* %ptr, i64 %val) nounwind {
 define i64 @atomic_cap_ptr_xor(i64 addrspace(200)* %ptr, i64 %val) nounwind {
 ; PURECAP-ATOMICS-LABEL: atomic_cap_ptr_xor:
 ; PURECAP-ATOMICS:       # %bb.0:
-; PURECAP-ATOMICS-NEXT:    camoxor.d.aqrl a0, a1, (ca0)
+; PURECAP-ATOMICS-NEXT:    camoxor.d.aqrl a0, a1, (a0)
 ; PURECAP-ATOMICS-NEXT:    cret
 ;
 ; PURECAP-LIBCALLS-LABEL: atomic_cap_ptr_xor:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -16
-; PURECAP-LIBCALLS-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -16
+; PURECAP-LIBCALLS-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; PURECAP-LIBCALLS-NEXT:    li a2, 5
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_fetch_xor_8
-; PURECAP-LIBCALLS-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 16
+; PURECAP-LIBCALLS-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 16
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: atomic_cap_ptr_xor:
@@ -221,31 +221,31 @@ define i64 @atomic_cap_ptr_xor(i64 addrspace(200)* %ptr, i64 %val) nounwind {
 define i64 @atomic_cap_ptr_max(i64 addrspace(200)* %ptr, i64 %val) nounwind {
 ; PURECAP-ATOMICS-LABEL: atomic_cap_ptr_max:
 ; PURECAP-ATOMICS:       # %bb.0:
-; PURECAP-ATOMICS-NEXT:    camomax.d.aqrl a0, a1, (ca0)
+; PURECAP-ATOMICS-NEXT:    camomax.d.aqrl a0, a1, (a0)
 ; PURECAP-ATOMICS-NEXT:    cret
 ;
 ; PURECAP-LIBCALLS-LABEL: atomic_cap_ptr_max:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -80
-; PURECAP-LIBCALLS-NEXT:    csc cra, 64(csp) # 16-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs0, 48(csp) # 16-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs1, 32(csp) # 16-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs2, 16(csp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -80
+; PURECAP-LIBCALLS-NEXT:    csc ra, 64(sp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s0, 48(sp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s1, 32(sp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s2, 16(sp) # 16-byte Folded Spill
 ; PURECAP-LIBCALLS-NEXT:    mv s0, a1
-; PURECAP-LIBCALLS-NEXT:    cmove cs2, ca0
-; PURECAP-LIBCALLS-NEXT:    cld a1, 0(ca0)
-; PURECAP-LIBCALLS-NEXT:    cincoffset ca0, csp, 8
-; PURECAP-LIBCALLS-NEXT:    csetbounds cs1, ca0, 8
+; PURECAP-LIBCALLS-NEXT:    cmove s1, a0
+; PURECAP-LIBCALLS-NEXT:    cld a1, 0(a0)
+; PURECAP-LIBCALLS-NEXT:    cincoffset a0, sp, 8
+; PURECAP-LIBCALLS-NEXT:    csetbounds s2, a0, 8
 ; PURECAP-LIBCALLS-NEXT:    j .LBB7_2
 ; PURECAP-LIBCALLS-NEXT:  .LBB7_1: # %atomicrmw.start
 ; PURECAP-LIBCALLS-NEXT:    # in Loop: Header=BB7_2 Depth=1
-; PURECAP-LIBCALLS-NEXT:    csd a1, 8(csp)
+; PURECAP-LIBCALLS-NEXT:    csd a1, 8(sp)
 ; PURECAP-LIBCALLS-NEXT:    li a3, 5
 ; PURECAP-LIBCALLS-NEXT:    li a4, 5
-; PURECAP-LIBCALLS-NEXT:    cmove ca0, cs2
-; PURECAP-LIBCALLS-NEXT:    cmove ca1, cs1
+; PURECAP-LIBCALLS-NEXT:    cmove a0, s1
+; PURECAP-LIBCALLS-NEXT:    cmove a1, s2
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_compare_exchange_8
-; PURECAP-LIBCALLS-NEXT:    cld a1, 8(csp)
+; PURECAP-LIBCALLS-NEXT:    cld a1, 8(sp)
 ; PURECAP-LIBCALLS-NEXT:    bnez a0, .LBB7_4
 ; PURECAP-LIBCALLS-NEXT:  .LBB7_2: # %atomicrmw.start
 ; PURECAP-LIBCALLS-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -257,11 +257,11 @@ define i64 @atomic_cap_ptr_max(i64 addrspace(200)* %ptr, i64 %val) nounwind {
 ; PURECAP-LIBCALLS-NEXT:    j .LBB7_1
 ; PURECAP-LIBCALLS-NEXT:  .LBB7_4: # %atomicrmw.end
 ; PURECAP-LIBCALLS-NEXT:    mv a0, a1
-; PURECAP-LIBCALLS-NEXT:    clc cra, 64(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs0, 48(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs1, 32(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs2, 16(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 80
+; PURECAP-LIBCALLS-NEXT:    clc ra, 64(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s0, 48(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s1, 32(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s2, 16(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 80
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: atomic_cap_ptr_max:
@@ -269,8 +269,8 @@ define i64 @atomic_cap_ptr_max(i64 addrspace(200)* %ptr, i64 %val) nounwind {
 ; HYBRID-NEXT:    addi sp, sp, -48
 ; HYBRID-NEXT:    sd ra, 40(sp) # 8-byte Folded Spill
 ; HYBRID-NEXT:    sd s0, 32(sp) # 8-byte Folded Spill
-; HYBRID-NEXT:    sc ca0, 0(sp) # 16-byte Folded Spill
-; HYBRID-NEXT:    ld.cap a3, (ca0)
+; HYBRID-NEXT:    sc a0, 0(sp) # 16-byte Folded Spill
+; HYBRID-NEXT:    ld.cap a3, (a0)
 ; HYBRID-NEXT:    mv s0, a1
 ; HYBRID-NEXT:    j .LBB7_2
 ; HYBRID-NEXT:  .LBB7_1: # %atomicrmw.start
@@ -279,7 +279,7 @@ define i64 @atomic_cap_ptr_max(i64 addrspace(200)* %ptr, i64 %val) nounwind {
 ; HYBRID-NEXT:    addi a1, sp, 24
 ; HYBRID-NEXT:    li a3, 5
 ; HYBRID-NEXT:    li a4, 5
-; HYBRID-NEXT:    lc ca0, 0(sp) # 16-byte Folded Reload
+; HYBRID-NEXT:    lc a0, 0(sp) # 16-byte Folded Reload
 ; HYBRID-NEXT:    call __atomic_compare_exchange_8_c
 ; HYBRID-NEXT:    ld a3, 24(sp)
 ; HYBRID-NEXT:    bnez a0, .LBB7_4
@@ -304,31 +304,31 @@ define i64 @atomic_cap_ptr_max(i64 addrspace(200)* %ptr, i64 %val) nounwind {
 define i64 @atomic_cap_ptr_min(i64 addrspace(200)* %ptr, i64 %val) nounwind {
 ; PURECAP-ATOMICS-LABEL: atomic_cap_ptr_min:
 ; PURECAP-ATOMICS:       # %bb.0:
-; PURECAP-ATOMICS-NEXT:    camomin.d.aqrl a0, a1, (ca0)
+; PURECAP-ATOMICS-NEXT:    camomin.d.aqrl a0, a1, (a0)
 ; PURECAP-ATOMICS-NEXT:    cret
 ;
 ; PURECAP-LIBCALLS-LABEL: atomic_cap_ptr_min:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -80
-; PURECAP-LIBCALLS-NEXT:    csc cra, 64(csp) # 16-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs0, 48(csp) # 16-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs1, 32(csp) # 16-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs2, 16(csp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -80
+; PURECAP-LIBCALLS-NEXT:    csc ra, 64(sp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s0, 48(sp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s1, 32(sp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s2, 16(sp) # 16-byte Folded Spill
 ; PURECAP-LIBCALLS-NEXT:    mv s0, a1
-; PURECAP-LIBCALLS-NEXT:    cmove cs2, ca0
-; PURECAP-LIBCALLS-NEXT:    cld a1, 0(ca0)
-; PURECAP-LIBCALLS-NEXT:    cincoffset ca0, csp, 8
-; PURECAP-LIBCALLS-NEXT:    csetbounds cs1, ca0, 8
+; PURECAP-LIBCALLS-NEXT:    cmove s1, a0
+; PURECAP-LIBCALLS-NEXT:    cld a1, 0(a0)
+; PURECAP-LIBCALLS-NEXT:    cincoffset a0, sp, 8
+; PURECAP-LIBCALLS-NEXT:    csetbounds s2, a0, 8
 ; PURECAP-LIBCALLS-NEXT:    j .LBB8_2
 ; PURECAP-LIBCALLS-NEXT:  .LBB8_1: # %atomicrmw.start
 ; PURECAP-LIBCALLS-NEXT:    # in Loop: Header=BB8_2 Depth=1
-; PURECAP-LIBCALLS-NEXT:    csd a1, 8(csp)
+; PURECAP-LIBCALLS-NEXT:    csd a1, 8(sp)
 ; PURECAP-LIBCALLS-NEXT:    li a3, 5
 ; PURECAP-LIBCALLS-NEXT:    li a4, 5
-; PURECAP-LIBCALLS-NEXT:    cmove ca0, cs2
-; PURECAP-LIBCALLS-NEXT:    cmove ca1, cs1
+; PURECAP-LIBCALLS-NEXT:    cmove a0, s1
+; PURECAP-LIBCALLS-NEXT:    cmove a1, s2
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_compare_exchange_8
-; PURECAP-LIBCALLS-NEXT:    cld a1, 8(csp)
+; PURECAP-LIBCALLS-NEXT:    cld a1, 8(sp)
 ; PURECAP-LIBCALLS-NEXT:    bnez a0, .LBB8_4
 ; PURECAP-LIBCALLS-NEXT:  .LBB8_2: # %atomicrmw.start
 ; PURECAP-LIBCALLS-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -340,11 +340,11 @@ define i64 @atomic_cap_ptr_min(i64 addrspace(200)* %ptr, i64 %val) nounwind {
 ; PURECAP-LIBCALLS-NEXT:    j .LBB8_1
 ; PURECAP-LIBCALLS-NEXT:  .LBB8_4: # %atomicrmw.end
 ; PURECAP-LIBCALLS-NEXT:    mv a0, a1
-; PURECAP-LIBCALLS-NEXT:    clc cra, 64(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs0, 48(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs1, 32(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs2, 16(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 80
+; PURECAP-LIBCALLS-NEXT:    clc ra, 64(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s0, 48(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s1, 32(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s2, 16(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 80
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: atomic_cap_ptr_min:
@@ -352,8 +352,8 @@ define i64 @atomic_cap_ptr_min(i64 addrspace(200)* %ptr, i64 %val) nounwind {
 ; HYBRID-NEXT:    addi sp, sp, -48
 ; HYBRID-NEXT:    sd ra, 40(sp) # 8-byte Folded Spill
 ; HYBRID-NEXT:    sd s0, 32(sp) # 8-byte Folded Spill
-; HYBRID-NEXT:    sc ca0, 0(sp) # 16-byte Folded Spill
-; HYBRID-NEXT:    ld.cap a3, (ca0)
+; HYBRID-NEXT:    sc a0, 0(sp) # 16-byte Folded Spill
+; HYBRID-NEXT:    ld.cap a3, (a0)
 ; HYBRID-NEXT:    mv s0, a1
 ; HYBRID-NEXT:    j .LBB8_2
 ; HYBRID-NEXT:  .LBB8_1: # %atomicrmw.start
@@ -362,7 +362,7 @@ define i64 @atomic_cap_ptr_min(i64 addrspace(200)* %ptr, i64 %val) nounwind {
 ; HYBRID-NEXT:    addi a1, sp, 24
 ; HYBRID-NEXT:    li a3, 5
 ; HYBRID-NEXT:    li a4, 5
-; HYBRID-NEXT:    lc ca0, 0(sp) # 16-byte Folded Reload
+; HYBRID-NEXT:    lc a0, 0(sp) # 16-byte Folded Reload
 ; HYBRID-NEXT:    call __atomic_compare_exchange_8_c
 ; HYBRID-NEXT:    ld a3, 24(sp)
 ; HYBRID-NEXT:    bnez a0, .LBB8_4
@@ -387,31 +387,31 @@ define i64 @atomic_cap_ptr_min(i64 addrspace(200)* %ptr, i64 %val) nounwind {
 define i64 @atomic_cap_ptr_umax(i64 addrspace(200)* %ptr, i64 %val) nounwind {
 ; PURECAP-ATOMICS-LABEL: atomic_cap_ptr_umax:
 ; PURECAP-ATOMICS:       # %bb.0:
-; PURECAP-ATOMICS-NEXT:    camomaxu.d.aqrl a0, a1, (ca0)
+; PURECAP-ATOMICS-NEXT:    camomaxu.d.aqrl a0, a1, (a0)
 ; PURECAP-ATOMICS-NEXT:    cret
 ;
 ; PURECAP-LIBCALLS-LABEL: atomic_cap_ptr_umax:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -80
-; PURECAP-LIBCALLS-NEXT:    csc cra, 64(csp) # 16-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs0, 48(csp) # 16-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs1, 32(csp) # 16-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs2, 16(csp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -80
+; PURECAP-LIBCALLS-NEXT:    csc ra, 64(sp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s0, 48(sp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s1, 32(sp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s2, 16(sp) # 16-byte Folded Spill
 ; PURECAP-LIBCALLS-NEXT:    mv s0, a1
-; PURECAP-LIBCALLS-NEXT:    cmove cs2, ca0
-; PURECAP-LIBCALLS-NEXT:    cld a1, 0(ca0)
-; PURECAP-LIBCALLS-NEXT:    cincoffset ca0, csp, 8
-; PURECAP-LIBCALLS-NEXT:    csetbounds cs1, ca0, 8
+; PURECAP-LIBCALLS-NEXT:    cmove s1, a0
+; PURECAP-LIBCALLS-NEXT:    cld a1, 0(a0)
+; PURECAP-LIBCALLS-NEXT:    cincoffset a0, sp, 8
+; PURECAP-LIBCALLS-NEXT:    csetbounds s2, a0, 8
 ; PURECAP-LIBCALLS-NEXT:    j .LBB9_2
 ; PURECAP-LIBCALLS-NEXT:  .LBB9_1: # %atomicrmw.start
 ; PURECAP-LIBCALLS-NEXT:    # in Loop: Header=BB9_2 Depth=1
-; PURECAP-LIBCALLS-NEXT:    csd a1, 8(csp)
+; PURECAP-LIBCALLS-NEXT:    csd a1, 8(sp)
 ; PURECAP-LIBCALLS-NEXT:    li a3, 5
 ; PURECAP-LIBCALLS-NEXT:    li a4, 5
-; PURECAP-LIBCALLS-NEXT:    cmove ca0, cs2
-; PURECAP-LIBCALLS-NEXT:    cmove ca1, cs1
+; PURECAP-LIBCALLS-NEXT:    cmove a0, s1
+; PURECAP-LIBCALLS-NEXT:    cmove a1, s2
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_compare_exchange_8
-; PURECAP-LIBCALLS-NEXT:    cld a1, 8(csp)
+; PURECAP-LIBCALLS-NEXT:    cld a1, 8(sp)
 ; PURECAP-LIBCALLS-NEXT:    bnez a0, .LBB9_4
 ; PURECAP-LIBCALLS-NEXT:  .LBB9_2: # %atomicrmw.start
 ; PURECAP-LIBCALLS-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -423,11 +423,11 @@ define i64 @atomic_cap_ptr_umax(i64 addrspace(200)* %ptr, i64 %val) nounwind {
 ; PURECAP-LIBCALLS-NEXT:    j .LBB9_1
 ; PURECAP-LIBCALLS-NEXT:  .LBB9_4: # %atomicrmw.end
 ; PURECAP-LIBCALLS-NEXT:    mv a0, a1
-; PURECAP-LIBCALLS-NEXT:    clc cra, 64(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs0, 48(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs1, 32(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs2, 16(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 80
+; PURECAP-LIBCALLS-NEXT:    clc ra, 64(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s0, 48(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s1, 32(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s2, 16(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 80
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: atomic_cap_ptr_umax:
@@ -435,8 +435,8 @@ define i64 @atomic_cap_ptr_umax(i64 addrspace(200)* %ptr, i64 %val) nounwind {
 ; HYBRID-NEXT:    addi sp, sp, -48
 ; HYBRID-NEXT:    sd ra, 40(sp) # 8-byte Folded Spill
 ; HYBRID-NEXT:    sd s0, 32(sp) # 8-byte Folded Spill
-; HYBRID-NEXT:    sc ca0, 0(sp) # 16-byte Folded Spill
-; HYBRID-NEXT:    ld.cap a3, (ca0)
+; HYBRID-NEXT:    sc a0, 0(sp) # 16-byte Folded Spill
+; HYBRID-NEXT:    ld.cap a3, (a0)
 ; HYBRID-NEXT:    mv s0, a1
 ; HYBRID-NEXT:    j .LBB9_2
 ; HYBRID-NEXT:  .LBB9_1: # %atomicrmw.start
@@ -445,7 +445,7 @@ define i64 @atomic_cap_ptr_umax(i64 addrspace(200)* %ptr, i64 %val) nounwind {
 ; HYBRID-NEXT:    addi a1, sp, 24
 ; HYBRID-NEXT:    li a3, 5
 ; HYBRID-NEXT:    li a4, 5
-; HYBRID-NEXT:    lc ca0, 0(sp) # 16-byte Folded Reload
+; HYBRID-NEXT:    lc a0, 0(sp) # 16-byte Folded Reload
 ; HYBRID-NEXT:    call __atomic_compare_exchange_8_c
 ; HYBRID-NEXT:    ld a3, 24(sp)
 ; HYBRID-NEXT:    bnez a0, .LBB9_4
@@ -470,31 +470,31 @@ define i64 @atomic_cap_ptr_umax(i64 addrspace(200)* %ptr, i64 %val) nounwind {
 define i64 @atomic_cap_ptr_umin(i64 addrspace(200)* %ptr, i64 %val) nounwind {
 ; PURECAP-ATOMICS-LABEL: atomic_cap_ptr_umin:
 ; PURECAP-ATOMICS:       # %bb.0:
-; PURECAP-ATOMICS-NEXT:    camominu.d.aqrl a0, a1, (ca0)
+; PURECAP-ATOMICS-NEXT:    camominu.d.aqrl a0, a1, (a0)
 ; PURECAP-ATOMICS-NEXT:    cret
 ;
 ; PURECAP-LIBCALLS-LABEL: atomic_cap_ptr_umin:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -80
-; PURECAP-LIBCALLS-NEXT:    csc cra, 64(csp) # 16-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs0, 48(csp) # 16-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs1, 32(csp) # 16-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs2, 16(csp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -80
+; PURECAP-LIBCALLS-NEXT:    csc ra, 64(sp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s0, 48(sp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s1, 32(sp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s2, 16(sp) # 16-byte Folded Spill
 ; PURECAP-LIBCALLS-NEXT:    mv s0, a1
-; PURECAP-LIBCALLS-NEXT:    cmove cs2, ca0
-; PURECAP-LIBCALLS-NEXT:    cld a1, 0(ca0)
-; PURECAP-LIBCALLS-NEXT:    cincoffset ca0, csp, 8
-; PURECAP-LIBCALLS-NEXT:    csetbounds cs1, ca0, 8
+; PURECAP-LIBCALLS-NEXT:    cmove s1, a0
+; PURECAP-LIBCALLS-NEXT:    cld a1, 0(a0)
+; PURECAP-LIBCALLS-NEXT:    cincoffset a0, sp, 8
+; PURECAP-LIBCALLS-NEXT:    csetbounds s2, a0, 8
 ; PURECAP-LIBCALLS-NEXT:    j .LBB10_2
 ; PURECAP-LIBCALLS-NEXT:  .LBB10_1: # %atomicrmw.start
 ; PURECAP-LIBCALLS-NEXT:    # in Loop: Header=BB10_2 Depth=1
-; PURECAP-LIBCALLS-NEXT:    csd a1, 8(csp)
+; PURECAP-LIBCALLS-NEXT:    csd a1, 8(sp)
 ; PURECAP-LIBCALLS-NEXT:    li a3, 5
 ; PURECAP-LIBCALLS-NEXT:    li a4, 5
-; PURECAP-LIBCALLS-NEXT:    cmove ca0, cs2
-; PURECAP-LIBCALLS-NEXT:    cmove ca1, cs1
+; PURECAP-LIBCALLS-NEXT:    cmove a0, s1
+; PURECAP-LIBCALLS-NEXT:    cmove a1, s2
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_compare_exchange_8
-; PURECAP-LIBCALLS-NEXT:    cld a1, 8(csp)
+; PURECAP-LIBCALLS-NEXT:    cld a1, 8(sp)
 ; PURECAP-LIBCALLS-NEXT:    bnez a0, .LBB10_4
 ; PURECAP-LIBCALLS-NEXT:  .LBB10_2: # %atomicrmw.start
 ; PURECAP-LIBCALLS-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -506,11 +506,11 @@ define i64 @atomic_cap_ptr_umin(i64 addrspace(200)* %ptr, i64 %val) nounwind {
 ; PURECAP-LIBCALLS-NEXT:    j .LBB10_1
 ; PURECAP-LIBCALLS-NEXT:  .LBB10_4: # %atomicrmw.end
 ; PURECAP-LIBCALLS-NEXT:    mv a0, a1
-; PURECAP-LIBCALLS-NEXT:    clc cra, 64(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs0, 48(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs1, 32(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs2, 16(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 80
+; PURECAP-LIBCALLS-NEXT:    clc ra, 64(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s0, 48(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s1, 32(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s2, 16(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 80
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: atomic_cap_ptr_umin:
@@ -518,8 +518,8 @@ define i64 @atomic_cap_ptr_umin(i64 addrspace(200)* %ptr, i64 %val) nounwind {
 ; HYBRID-NEXT:    addi sp, sp, -48
 ; HYBRID-NEXT:    sd ra, 40(sp) # 8-byte Folded Spill
 ; HYBRID-NEXT:    sd s0, 32(sp) # 8-byte Folded Spill
-; HYBRID-NEXT:    sc ca0, 0(sp) # 16-byte Folded Spill
-; HYBRID-NEXT:    ld.cap a3, (ca0)
+; HYBRID-NEXT:    sc a0, 0(sp) # 16-byte Folded Spill
+; HYBRID-NEXT:    ld.cap a3, (a0)
 ; HYBRID-NEXT:    mv s0, a1
 ; HYBRID-NEXT:    j .LBB10_2
 ; HYBRID-NEXT:  .LBB10_1: # %atomicrmw.start
@@ -528,7 +528,7 @@ define i64 @atomic_cap_ptr_umin(i64 addrspace(200)* %ptr, i64 %val) nounwind {
 ; HYBRID-NEXT:    addi a1, sp, 24
 ; HYBRID-NEXT:    li a3, 5
 ; HYBRID-NEXT:    li a4, 5
-; HYBRID-NEXT:    lc ca0, 0(sp) # 16-byte Folded Reload
+; HYBRID-NEXT:    lc a0, 0(sp) # 16-byte Folded Reload
 ; HYBRID-NEXT:    call __atomic_compare_exchange_8_c
 ; HYBRID-NEXT:    ld a3, 24(sp)
 ; HYBRID-NEXT:    bnez a0, .LBB10_4
@@ -553,7 +553,7 @@ define i64 @atomic_cap_ptr_umin(i64 addrspace(200)* %ptr, i64 %val) nounwind {
 define float @atomic_cap_ptr_fadd(float addrspace(200)* %ptr, float %val) nounwind {
 ; PURECAP-ATOMICS-LABEL: atomic_cap_ptr_fadd:
 ; PURECAP-ATOMICS:       # %bb.0:
-; PURECAP-ATOMICS-NEXT:    cflw fa5, 0(ca0)
+; PURECAP-ATOMICS-NEXT:    cflw fa5, 0(a0)
 ; PURECAP-ATOMICS-NEXT:  .LBB11_1: # %atomicrmw.start
 ; PURECAP-ATOMICS-NEXT:    # =>This Loop Header: Depth=1
 ; PURECAP-ATOMICS-NEXT:    # Child Loop BB11_3 Depth 2
@@ -563,11 +563,11 @@ define float @atomic_cap_ptr_fadd(float addrspace(200)* %ptr, float %val) nounwi
 ; PURECAP-ATOMICS-NEXT:  .LBB11_3: # %atomicrmw.start
 ; PURECAP-ATOMICS-NEXT:    # Parent Loop BB11_1 Depth=1
 ; PURECAP-ATOMICS-NEXT:    # => This Inner Loop Header: Depth=2
-; PURECAP-ATOMICS-NEXT:    clr.w.aqrl a3, (ca0)
+; PURECAP-ATOMICS-NEXT:    clr.w.aqrl a3, (a0)
 ; PURECAP-ATOMICS-NEXT:    bne a3, a2, .LBB11_5
 ; PURECAP-ATOMICS-NEXT:  # %bb.4: # %atomicrmw.start
 ; PURECAP-ATOMICS-NEXT:    # in Loop: Header=BB11_3 Depth=2
-; PURECAP-ATOMICS-NEXT:    csc.w.rl a4, a1, (ca0)
+; PURECAP-ATOMICS-NEXT:    csc.w.rl a4, a1, (a0)
 ; PURECAP-ATOMICS-NEXT:    bnez a4, .LBB11_3
 ; PURECAP-ATOMICS-NEXT:  .LBB11_5: # %atomicrmw.start
 ; PURECAP-ATOMICS-NEXT:    # in Loop: Header=BB11_1 Depth=1
@@ -579,34 +579,34 @@ define float @atomic_cap_ptr_fadd(float addrspace(200)* %ptr, float %val) nounwi
 ;
 ; PURECAP-LIBCALLS-LABEL: atomic_cap_ptr_fadd:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -64
-; PURECAP-LIBCALLS-NEXT:    csc cra, 48(csp) # 16-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs0, 32(csp) # 16-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs1, 16(csp) # 16-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    cfsd fs0, 8(csp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -64
+; PURECAP-LIBCALLS-NEXT:    csc ra, 48(sp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s0, 32(sp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s1, 16(sp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    cfsd fs0, 8(sp) # 8-byte Folded Spill
 ; PURECAP-LIBCALLS-NEXT:    fmv.s fs0, fa0
-; PURECAP-LIBCALLS-NEXT:    cmove cs0, ca0
-; PURECAP-LIBCALLS-NEXT:    cflw fa0, 0(ca0)
-; PURECAP-LIBCALLS-NEXT:    cincoffset ca0, csp, 4
-; PURECAP-LIBCALLS-NEXT:    csetbounds cs1, ca0, 4
+; PURECAP-LIBCALLS-NEXT:    cmove s0, a0
+; PURECAP-LIBCALLS-NEXT:    cflw fa0, 0(a0)
+; PURECAP-LIBCALLS-NEXT:    cincoffset a0, sp, 4
+; PURECAP-LIBCALLS-NEXT:    csetbounds s1, a0, 4
 ; PURECAP-LIBCALLS-NEXT:  .LBB11_1: # %atomicrmw.start
 ; PURECAP-LIBCALLS-NEXT:    # =>This Inner Loop Header: Depth=1
 ; PURECAP-LIBCALLS-NEXT:    fadd.s fa5, fa0, fs0
-; PURECAP-LIBCALLS-NEXT:    cfsw fa0, 4(csp)
+; PURECAP-LIBCALLS-NEXT:    cfsw fa0, 4(sp)
 ; PURECAP-LIBCALLS-NEXT:    fmv.x.w a2, fa5
 ; PURECAP-LIBCALLS-NEXT:    li a3, 5
 ; PURECAP-LIBCALLS-NEXT:    li a4, 5
-; PURECAP-LIBCALLS-NEXT:    cmove ca0, cs0
-; PURECAP-LIBCALLS-NEXT:    cmove ca1, cs1
+; PURECAP-LIBCALLS-NEXT:    cmove a0, s0
+; PURECAP-LIBCALLS-NEXT:    cmove a1, s1
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_compare_exchange_4
-; PURECAP-LIBCALLS-NEXT:    cflw fa0, 4(csp)
+; PURECAP-LIBCALLS-NEXT:    cflw fa0, 4(sp)
 ; PURECAP-LIBCALLS-NEXT:    beqz a0, .LBB11_1
 ; PURECAP-LIBCALLS-NEXT:  # %bb.2: # %atomicrmw.end
-; PURECAP-LIBCALLS-NEXT:    clc cra, 48(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs0, 32(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs1, 16(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cfld fs0, 8(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 64
+; PURECAP-LIBCALLS-NEXT:    clc ra, 48(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s0, 32(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s1, 16(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cfld fs0, 8(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 64
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: atomic_cap_ptr_fadd:
@@ -615,8 +615,8 @@ define float @atomic_cap_ptr_fadd(float addrspace(200)* %ptr, float %val) nounwi
 ; HYBRID-NEXT:    sd ra, 40(sp) # 8-byte Folded Spill
 ; HYBRID-NEXT:    fsd fs0, 32(sp) # 8-byte Folded Spill
 ; HYBRID-NEXT:    fmv.s fs0, fa0
-; HYBRID-NEXT:    sc ca0, 0(sp) # 16-byte Folded Spill
-; HYBRID-NEXT:    lw.cap a0, (ca0)
+; HYBRID-NEXT:    sc a0, 0(sp) # 16-byte Folded Spill
+; HYBRID-NEXT:    lw.cap a0, (a0)
 ; HYBRID-NEXT:    fmv.w.x fa0, a0
 ; HYBRID-NEXT:  .LBB11_1: # %atomicrmw.start
 ; HYBRID-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -626,7 +626,7 @@ define float @atomic_cap_ptr_fadd(float addrspace(200)* %ptr, float %val) nounwi
 ; HYBRID-NEXT:    addi a1, sp, 28
 ; HYBRID-NEXT:    li a3, 5
 ; HYBRID-NEXT:    li a4, 5
-; HYBRID-NEXT:    lc ca0, 0(sp) # 16-byte Folded Reload
+; HYBRID-NEXT:    lc a0, 0(sp) # 16-byte Folded Reload
 ; HYBRID-NEXT:    call __atomic_compare_exchange_4_c
 ; HYBRID-NEXT:    flw fa0, 28(sp)
 ; HYBRID-NEXT:    beqz a0, .LBB11_1
@@ -642,7 +642,7 @@ define float @atomic_cap_ptr_fadd(float addrspace(200)* %ptr, float %val) nounwi
 define float @atomic_cap_ptr_fsub(float addrspace(200)* %ptr, float %val) nounwind {
 ; PURECAP-ATOMICS-LABEL: atomic_cap_ptr_fsub:
 ; PURECAP-ATOMICS:       # %bb.0:
-; PURECAP-ATOMICS-NEXT:    cflw fa5, 0(ca0)
+; PURECAP-ATOMICS-NEXT:    cflw fa5, 0(a0)
 ; PURECAP-ATOMICS-NEXT:  .LBB12_1: # %atomicrmw.start
 ; PURECAP-ATOMICS-NEXT:    # =>This Loop Header: Depth=1
 ; PURECAP-ATOMICS-NEXT:    # Child Loop BB12_3 Depth 2
@@ -652,11 +652,11 @@ define float @atomic_cap_ptr_fsub(float addrspace(200)* %ptr, float %val) nounwi
 ; PURECAP-ATOMICS-NEXT:  .LBB12_3: # %atomicrmw.start
 ; PURECAP-ATOMICS-NEXT:    # Parent Loop BB12_1 Depth=1
 ; PURECAP-ATOMICS-NEXT:    # => This Inner Loop Header: Depth=2
-; PURECAP-ATOMICS-NEXT:    clr.w.aqrl a3, (ca0)
+; PURECAP-ATOMICS-NEXT:    clr.w.aqrl a3, (a0)
 ; PURECAP-ATOMICS-NEXT:    bne a3, a2, .LBB12_5
 ; PURECAP-ATOMICS-NEXT:  # %bb.4: # %atomicrmw.start
 ; PURECAP-ATOMICS-NEXT:    # in Loop: Header=BB12_3 Depth=2
-; PURECAP-ATOMICS-NEXT:    csc.w.rl a4, a1, (ca0)
+; PURECAP-ATOMICS-NEXT:    csc.w.rl a4, a1, (a0)
 ; PURECAP-ATOMICS-NEXT:    bnez a4, .LBB12_3
 ; PURECAP-ATOMICS-NEXT:  .LBB12_5: # %atomicrmw.start
 ; PURECAP-ATOMICS-NEXT:    # in Loop: Header=BB12_1 Depth=1
@@ -668,34 +668,34 @@ define float @atomic_cap_ptr_fsub(float addrspace(200)* %ptr, float %val) nounwi
 ;
 ; PURECAP-LIBCALLS-LABEL: atomic_cap_ptr_fsub:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -64
-; PURECAP-LIBCALLS-NEXT:    csc cra, 48(csp) # 16-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs0, 32(csp) # 16-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc cs1, 16(csp) # 16-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    cfsd fs0, 8(csp) # 8-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -64
+; PURECAP-LIBCALLS-NEXT:    csc ra, 48(sp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s0, 32(sp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc s1, 16(sp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    cfsd fs0, 8(sp) # 8-byte Folded Spill
 ; PURECAP-LIBCALLS-NEXT:    fmv.s fs0, fa0
-; PURECAP-LIBCALLS-NEXT:    cmove cs0, ca0
-; PURECAP-LIBCALLS-NEXT:    cflw fa0, 0(ca0)
-; PURECAP-LIBCALLS-NEXT:    cincoffset ca0, csp, 4
-; PURECAP-LIBCALLS-NEXT:    csetbounds cs1, ca0, 4
+; PURECAP-LIBCALLS-NEXT:    cmove s0, a0
+; PURECAP-LIBCALLS-NEXT:    cflw fa0, 0(a0)
+; PURECAP-LIBCALLS-NEXT:    cincoffset a0, sp, 4
+; PURECAP-LIBCALLS-NEXT:    csetbounds s1, a0, 4
 ; PURECAP-LIBCALLS-NEXT:  .LBB12_1: # %atomicrmw.start
 ; PURECAP-LIBCALLS-NEXT:    # =>This Inner Loop Header: Depth=1
 ; PURECAP-LIBCALLS-NEXT:    fsub.s fa5, fa0, fs0
-; PURECAP-LIBCALLS-NEXT:    cfsw fa0, 4(csp)
+; PURECAP-LIBCALLS-NEXT:    cfsw fa0, 4(sp)
 ; PURECAP-LIBCALLS-NEXT:    fmv.x.w a2, fa5
 ; PURECAP-LIBCALLS-NEXT:    li a3, 5
 ; PURECAP-LIBCALLS-NEXT:    li a4, 5
-; PURECAP-LIBCALLS-NEXT:    cmove ca0, cs0
-; PURECAP-LIBCALLS-NEXT:    cmove ca1, cs1
+; PURECAP-LIBCALLS-NEXT:    cmove a0, s0
+; PURECAP-LIBCALLS-NEXT:    cmove a1, s1
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_compare_exchange_4
-; PURECAP-LIBCALLS-NEXT:    cflw fa0, 4(csp)
+; PURECAP-LIBCALLS-NEXT:    cflw fa0, 4(sp)
 ; PURECAP-LIBCALLS-NEXT:    beqz a0, .LBB12_1
 ; PURECAP-LIBCALLS-NEXT:  # %bb.2: # %atomicrmw.end
-; PURECAP-LIBCALLS-NEXT:    clc cra, 48(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs0, 32(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    clc cs1, 16(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cfld fs0, 8(csp) # 8-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 64
+; PURECAP-LIBCALLS-NEXT:    clc ra, 48(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s0, 32(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    clc s1, 16(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cfld fs0, 8(sp) # 8-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 64
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: atomic_cap_ptr_fsub:
@@ -704,8 +704,8 @@ define float @atomic_cap_ptr_fsub(float addrspace(200)* %ptr, float %val) nounwi
 ; HYBRID-NEXT:    sd ra, 40(sp) # 8-byte Folded Spill
 ; HYBRID-NEXT:    fsd fs0, 32(sp) # 8-byte Folded Spill
 ; HYBRID-NEXT:    fmv.s fs0, fa0
-; HYBRID-NEXT:    sc ca0, 0(sp) # 16-byte Folded Spill
-; HYBRID-NEXT:    lw.cap a0, (ca0)
+; HYBRID-NEXT:    sc a0, 0(sp) # 16-byte Folded Spill
+; HYBRID-NEXT:    lw.cap a0, (a0)
 ; HYBRID-NEXT:    fmv.w.x fa0, a0
 ; HYBRID-NEXT:  .LBB12_1: # %atomicrmw.start
 ; HYBRID-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -715,7 +715,7 @@ define float @atomic_cap_ptr_fsub(float addrspace(200)* %ptr, float %val) nounwi
 ; HYBRID-NEXT:    addi a1, sp, 28
 ; HYBRID-NEXT:    li a3, 5
 ; HYBRID-NEXT:    li a4, 5
-; HYBRID-NEXT:    lc ca0, 0(sp) # 16-byte Folded Reload
+; HYBRID-NEXT:    lc a0, 0(sp) # 16-byte Folded Reload
 ; HYBRID-NEXT:    call __atomic_compare_exchange_4_c
 ; HYBRID-NEXT:    flw fa0, 28(sp)
 ; HYBRID-NEXT:    beqz a0, .LBB12_1
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/bounded-allocas-lifetimes.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/bounded-allocas-lifetimes.ll
index a43b8a98d945a..a9757df5df533 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/bounded-allocas-lifetimes.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/bounded-allocas-lifetimes.ll
@@ -12,13 +12,13 @@ declare void @use(i8 addrspace(200)*)
 define void @static_alloca() {
   ; CHECK-LABEL: name: static_alloca
   ; CHECK: bb.0 (%ir-block.0):
-  ; CHECK-NEXT:   [[CIncOffsetImm:%[0-9]+]]:gpcr = CIncOffsetImm %stack.0, 0
-  ; CHECK-NEXT:   [[CSetBoundsImm:%[0-9]+]]:gpcr = CSetBoundsImm killed [[CIncOffsetImm]], 4
+  ; CHECK-NEXT:   [[CIncOffsetImm:%[0-9]+]]:ygpr = CIncOffsetImm %stack.0, 0
+  ; CHECK-NEXT:   [[CSetBoundsImm:%[0-9]+]]:ygpr = CSetBoundsImm killed [[CIncOffsetImm]], 4
   ; CHECK-NEXT:   LIFETIME_START %stack.0
-  ; CHECK-NEXT:   ADJCALLSTACKDOWNCAP 0, 0, implicit-def dead $c2, implicit $c2
-  ; CHECK-NEXT:   $c10 = COPY [[CSetBoundsImm]]
-  ; CHECK-NEXT:   PseudoCCALL target-flags(riscv-ccall) @use, csr_il32pc64d_l64pc128d, implicit-def dead $c1, implicit $c10, implicit-def $c2
-  ; CHECK-NEXT:   ADJCALLSTACKUPCAP 0, 0, implicit-def dead $c2, implicit $c2
+  ; CHECK-NEXT:   ADJCALLSTACKDOWNCAP 0, 0, implicit-def dead $x2_y, implicit $x2_y
+  ; CHECK-NEXT:   $x10_y = COPY [[CSetBoundsImm]]
+  ; CHECK-NEXT:   PseudoCCALL target-flags(riscv-ccall) @use, csr_il32pc64d_l64pc128d, implicit-def dead $x1_y, implicit $x10_y, implicit-def $x2_y
+  ; CHECK-NEXT:   ADJCALLSTACKUPCAP 0, 0, implicit-def dead $x2_y, implicit $x2_y
   ; CHECK-NEXT:   LIFETIME_END %stack.0
   ; CHECK-NEXT:   PseudoCRET
   %1 = alloca i32, align 4, addrspace(200)
@@ -37,8 +37,8 @@ define void @dynamic_alloca(i64 zeroext %n) {
   ; CHECK-NEXT:   liveins: $x10
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr = COPY $x10
-  ; CHECK-NEXT:   ADJCALLSTACKDOWNCAP 0, 0, implicit-def dead $c2, implicit $c2
-  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpcr = COPY $c2
+  ; CHECK-NEXT:   ADJCALLSTACKDOWNCAP 0, 0, implicit-def dead $x2_y, implicit $x2_y
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:ygpr = COPY $x2_y
   ; CHECK-NEXT:   [[PseudoCGetAddr:%[0-9]+]]:gpr = PseudoCGetAddr [[COPY1]]
   ; CHECK-NEXT:   [[SLLI:%[0-9]+]]:gpr = SLLI [[COPY]], 2
   ; CHECK-NEXT:   [[ADDI:%[0-9]+]]:gpr = nuw ADDI [[SLLI]], 15
@@ -47,15 +47,15 @@ define void @dynamic_alloca(i64 zeroext %n) {
   ; CHECK-NEXT:   [[SUB:%[0-9]+]]:gpr = SUB killed [[PseudoCGetAddr]], [[CRRL]]
   ; CHECK-NEXT:   [[CRAM:%[0-9]+]]:gpr = CRAM [[ANDI]]
   ; CHECK-NEXT:   [[AND:%[0-9]+]]:gpr = AND killed [[SUB]], killed [[CRAM]]
-  ; CHECK-NEXT:   [[CSetAddr:%[0-9]+]]:gpcr = CSetAddr [[COPY1]], killed [[AND]]
-  ; CHECK-NEXT:   [[CSetBounds:%[0-9]+]]:gpcr = CSetBounds [[CSetAddr]], [[CRRL]]
-  ; CHECK-NEXT:   $c2 = COPY [[CSetAddr]]
-  ; CHECK-NEXT:   ADJCALLSTACKUPCAP 0, 0, implicit-def dead $c2, implicit $c2
-  ; CHECK-NEXT:   [[CSetBounds1:%[0-9]+]]:gpcr = CSetBounds killed [[CSetBounds]], [[SLLI]]
-  ; CHECK-NEXT:   ADJCALLSTACKDOWNCAP 0, 0, implicit-def dead $c2, implicit $c2
-  ; CHECK-NEXT:   $c10 = COPY [[CSetBounds1]]
-  ; CHECK-NEXT:   PseudoCCALL target-flags(riscv-ccall) @use, csr_il32pc64d_l64pc128d, implicit-def dead $c1, implicit $c10, implicit-def $c2
-  ; CHECK-NEXT:   ADJCALLSTACKUPCAP 0, 0, implicit-def dead $c2, implicit $c2
+  ; CHECK-NEXT:   [[CSetAddr:%[0-9]+]]:ygpr = CSetAddr [[COPY1]], killed [[AND]]
+  ; CHECK-NEXT:   [[CSetBounds:%[0-9]+]]:ygpr = CSetBounds [[CSetAddr]], [[CRRL]]
+  ; CHECK-NEXT:   $x2_y = COPY [[CSetAddr]]
+  ; CHECK-NEXT:   ADJCALLSTACKUPCAP 0, 0, implicit-def dead $x2_y, implicit $x2_y
+  ; CHECK-NEXT:   [[CSetBounds1:%[0-9]+]]:ygpr = CSetBounds killed [[CSetBounds]], [[SLLI]]
+  ; CHECK-NEXT:   ADJCALLSTACKDOWNCAP 0, 0, implicit-def dead $x2_y, implicit $x2_y
+  ; CHECK-NEXT:   $x10_y = COPY [[CSetBounds1]]
+  ; CHECK-NEXT:   PseudoCCALL target-flags(riscv-ccall) @use, csr_il32pc64d_l64pc128d, implicit-def dead $x1_y, implicit $x10_y, implicit-def $x2_y
+  ; CHECK-NEXT:   ADJCALLSTACKUPCAP 0, 0, implicit-def dead $x2_y, implicit $x2_y
   ; CHECK-NEXT:   PseudoCRET
   %1 = alloca i32, i64 %n, align 4, addrspace(200)
   %2 = bitcast i32 addrspace(200)* %1 to i8 addrspace(200)*
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/cap-from-ptr.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/cap-from-ptr.ll
index 5b57a41fd7d2e..19cb1fd61668c 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/cap-from-ptr.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/cap-from-ptr.ll
@@ -12,26 +12,26 @@ define internal ptr addrspace(200) @test(ptr addrspace(200) %ptr, ptr addrspace(
 ; PURECAP:       # %bb.0: # %entry
 ; PURECAP-NEXT:    bnez a2, .LBB0_2
 ; PURECAP-NEXT:  # %bb.1: # %entry
-; PURECAP-NEXT:    cmove ca1, cnull
+; PURECAP-NEXT:    cmove a1, zero
 ; PURECAP-NEXT:    j .LBB0_3
 ; PURECAP-NEXT:  .LBB0_2:
-; PURECAP-NEXT:    csetaddr ca1, ca1, a2
+; PURECAP-NEXT:    csetaddr a1, a1, a2
 ; PURECAP-NEXT:  .LBB0_3: # %entry
-; PURECAP-NEXT:    csc ca1, 0(ca0)
-; PURECAP-NEXT:    cmove ca0, ca1
+; PURECAP-NEXT:    csc a1, 0(a0)
+; PURECAP-NEXT:    cmove a0, a1
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: test:
 ; HYBRID:       # %bb.0: # %entry
 ; HYBRID-NEXT:    bnez a2, .LBB0_2
 ; HYBRID-NEXT:  # %bb.1: # %entry
-; HYBRID-NEXT:    cmove ca1, cnull
+; HYBRID-NEXT:    cmove a1, zero
 ; HYBRID-NEXT:    j .LBB0_3
 ; HYBRID-NEXT:  .LBB0_2:
-; HYBRID-NEXT:    csetaddr ca1, ca1, a2
+; HYBRID-NEXT:    csetaddr a1, a1, a2
 ; HYBRID-NEXT:  .LBB0_3: # %entry
-; HYBRID-NEXT:    sc.cap ca1, (ca0)
-; HYBRID-NEXT:    cmove ca0, ca1
+; HYBRID-NEXT:    sc.cap a1, (a0)
+; HYBRID-NEXT:    cmove a0, a1
 ; HYBRID-NEXT:    ret
 ; CHECK-IR-LABEL: define {{[^@]+}}@test
 ; CHECK-IR-SAME: (ptr addrspace(200) [[PTR:%.*]], ptr addrspace(200) [[CAP:%.*]], i64 [[OFFSET:%.*]]) addrspace(200) #[[ATTR0:[0-9]+]] {
@@ -50,14 +50,14 @@ entry:
 define internal ptr addrspace(200) @cap_from_ptr_zero(ptr addrspace(200) %ptr, ptr addrspace(200) %cap) nounwind {
 ; PURECAP-LABEL: cap_from_ptr_zero:
 ; PURECAP:       # %bb.0: # %entry
-; PURECAP-NEXT:    csc cnull, 0(ca0)
-; PURECAP-NEXT:    cmove ca0, cnull
+; PURECAP-NEXT:    csc zero, 0(a0)
+; PURECAP-NEXT:    cmove a0, zero
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: cap_from_ptr_zero:
 ; HYBRID:       # %bb.0: # %entry
-; HYBRID-NEXT:    sc.cap cnull, (ca0)
-; HYBRID-NEXT:    cmove ca0, cnull
+; HYBRID-NEXT:    sc.cap zero, (a0)
+; HYBRID-NEXT:    cmove a0, zero
 ; HYBRID-NEXT:    ret
 ; CHECK-IR-LABEL: define internal ptr addrspace(200) @cap_from_ptr_zero
 ; CHECK-IR-SAME: (ptr addrspace(200) [[PTR:%.*]], ptr addrspace(200) [[CAP:%.*]]) #[[ATTR0]] {
@@ -75,30 +75,30 @@ entry:
 define internal ptr addrspace(200) @cap_from_ptr_ddc(ptr addrspace(200) %ptr, i64 %offset) addrspace(200) nounwind {
 ; PURECAP-LABEL: cap_from_ptr_ddc:
 ; PURECAP:       # %bb.0: # %entry
-; PURECAP-NEXT:    cspecialr ca2, ddc
+; PURECAP-NEXT:    cspecialr a2, ddc
 ; PURECAP-NEXT:    bnez a1, .LBB2_2
 ; PURECAP-NEXT:  # %bb.1: # %entry
-; PURECAP-NEXT:    cmove ca1, cnull
+; PURECAP-NEXT:    cmove a1, zero
 ; PURECAP-NEXT:    j .LBB2_3
 ; PURECAP-NEXT:  .LBB2_2:
-; PURECAP-NEXT:    csetaddr ca1, ca2, a1
+; PURECAP-NEXT:    csetaddr a1, a2, a1
 ; PURECAP-NEXT:  .LBB2_3: # %entry
-; PURECAP-NEXT:    csc ca1, 0(ca0)
-; PURECAP-NEXT:    cmove ca0, ca1
+; PURECAP-NEXT:    csc a1, 0(a0)
+; PURECAP-NEXT:    cmove a0, a1
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: cap_from_ptr_ddc:
 ; HYBRID:       # %bb.0: # %entry
-; HYBRID-NEXT:    cspecialr ca2, ddc
+; HYBRID-NEXT:    cspecialr a2, ddc
 ; HYBRID-NEXT:    bnez a1, .LBB2_2
 ; HYBRID-NEXT:  # %bb.1: # %entry
-; HYBRID-NEXT:    cmove ca1, cnull
+; HYBRID-NEXT:    cmove a1, zero
 ; HYBRID-NEXT:    j .LBB2_3
 ; HYBRID-NEXT:  .LBB2_2:
-; HYBRID-NEXT:    csetaddr ca1, ca2, a1
+; HYBRID-NEXT:    csetaddr a1, a2, a1
 ; HYBRID-NEXT:  .LBB2_3: # %entry
-; HYBRID-NEXT:    sc.cap ca1, (ca0)
-; HYBRID-NEXT:    cmove ca0, ca1
+; HYBRID-NEXT:    sc.cap a1, (a0)
+; HYBRID-NEXT:    cmove a0, a1
 ; HYBRID-NEXT:    ret
 ; CHECK-IR-LABEL: define {{[^@]+}}@cap_from_ptr_ddc
 ; CHECK-IR-SAME: (ptr addrspace(200) [[PTR:%.*]], i64 [[OFFSET:%.*]]) addrspace(200) #[[ATTR0]] {
@@ -119,14 +119,14 @@ entry:
 define internal ptr addrspace(200) @cap_from_ptr_ddc_zero(ptr addrspace(200) %ptr) addrspace(200) nounwind {
 ; PURECAP-LABEL: cap_from_ptr_ddc_zero:
 ; PURECAP:       # %bb.0: # %entry
-; PURECAP-NEXT:    csc cnull, 0(ca0)
-; PURECAP-NEXT:    cmove ca0, cnull
+; PURECAP-NEXT:    csc zero, 0(a0)
+; PURECAP-NEXT:    cmove a0, zero
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: cap_from_ptr_ddc_zero:
 ; HYBRID:       # %bb.0: # %entry
-; HYBRID-NEXT:    sc.cap cnull, (ca0)
-; HYBRID-NEXT:    cmove ca0, cnull
+; HYBRID-NEXT:    sc.cap zero, (a0)
+; HYBRID-NEXT:    cmove a0, zero
 ; HYBRID-NEXT:    ret
 ; CHECK-IR-LABEL: define {{[^@]+}}@cap_from_ptr_ddc_zero
 ; CHECK-IR-SAME: (ptr addrspace(200) [[PTR:%.*]]) addrspace(200) #[[ATTR0]] {
@@ -147,26 +147,26 @@ define internal ptr addrspace(200) @cap_from_ptr_null(ptr addrspace(200) %ptr, i
 ; PURECAP:       # %bb.0: # %entry
 ; PURECAP-NEXT:    bnez a1, .LBB4_2
 ; PURECAP-NEXT:  # %bb.1: # %entry
-; PURECAP-NEXT:    cmove ca1, cnull
+; PURECAP-NEXT:    cmove a1, zero
 ; PURECAP-NEXT:    j .LBB4_3
 ; PURECAP-NEXT:  .LBB4_2:
-; PURECAP-NEXT:    csetaddr ca1, cnull, a1
+; PURECAP-NEXT:    csetaddr a1, zero, a1
 ; PURECAP-NEXT:  .LBB4_3: # %entry
-; PURECAP-NEXT:    csc ca1, 0(ca0)
-; PURECAP-NEXT:    cmove ca0, ca1
+; PURECAP-NEXT:    csc a1, 0(a0)
+; PURECAP-NEXT:    cmove a0, a1
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: cap_from_ptr_null:
 ; HYBRID:       # %bb.0: # %entry
 ; HYBRID-NEXT:    bnez a1, .LBB4_2
 ; HYBRID-NEXT:  # %bb.1: # %entry
-; HYBRID-NEXT:    cmove ca1, cnull
+; HYBRID-NEXT:    cmove a1, zero
 ; HYBRID-NEXT:    j .LBB4_3
 ; HYBRID-NEXT:  .LBB4_2:
-; HYBRID-NEXT:    csetaddr ca1, cnull, a1
+; HYBRID-NEXT:    csetaddr a1, zero, a1
 ; HYBRID-NEXT:  .LBB4_3: # %entry
-; HYBRID-NEXT:    sc.cap ca1, (ca0)
-; HYBRID-NEXT:    cmove ca0, ca1
+; HYBRID-NEXT:    sc.cap a1, (a0)
+; HYBRID-NEXT:    cmove a0, a1
 ; HYBRID-NEXT:    ret
 ; CHECK-IR-LABEL: define {{[^@]+}}@cap_from_ptr_null
 ; CHECK-IR-SAME: (ptr addrspace(200) [[PTR:%.*]], i64 [[OFFSET:%.*]]) addrspace(200) #[[ATTR0]] {
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/cheri-intrinsics-folding-broken-module-regression.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/cheri-intrinsics-folding-broken-module-regression.ll
index 52538fdca0eb7..25f0998e2ab39 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/cheri-intrinsics-folding-broken-module-regression.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/cheri-intrinsics-folding-broken-module-regression.ll
@@ -21,17 +21,17 @@ define void @g(i64 %x, i64 %y) addrspace(200) nounwind {
 ; ASM-LABEL: g:
 ; ASM:       # %bb.0:
 ; ASM-NEXT:  .LBB0_1: # Label of block must be emitted
-; ASM-NEXT:    auipcc ca2, %captab_pcrel_hi(d)
-; ASM-NEXT:    clc ca2, %pcrel_lo(.LBB0_1)(ca2)
+; ASM-NEXT:    auipcc a2, %captab_pcrel_hi(d)
+; ASM-NEXT:    clc a2, %pcrel_lo(.LBB0_1)(a2)
 ; ASM-NEXT:    add a1, a1, a0
 ; ASM-NEXT:  .LBB0_2: # Label of block must be emitted
-; ASM-NEXT:    auipcc ca3, %captab_pcrel_hi(e)
-; ASM-NEXT:    clc ca3, %pcrel_lo(.LBB0_2)(ca3)
-; ASM-NEXT:    cincoffset ca0, ca2, a0
-; ASM-NEXT:    cgetoffset a2, ca2
+; ASM-NEXT:    auipcc a3, %captab_pcrel_hi(e)
+; ASM-NEXT:    clc a3, %pcrel_lo(.LBB0_2)(a3)
+; ASM-NEXT:    cincoffset a0, a2, a0
+; ASM-NEXT:    cgetoffset a2, a2
 ; ASM-NEXT:    add a1, a1, a2
-; ASM-NEXT:    csetoffset ca0, ca0, a1
-; ASM-NEXT:    csc ca0, 0(ca3)
+; ASM-NEXT:    csetoffset a0, a0, a1
+; ASM-NEXT:    csc a0, 0(a3)
 ; ASM-NEXT:    cret
 ; CHECK-LABEL: define void @g
 ; CHECK-SAME: (i64 [[X:%.*]], i64 [[Y:%.*]]) addrspace(200) #[[ATTR0:[0-9]+]] {
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/cheri-memfn-call.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/cheri-memfn-call.ll
index 0098660981577..92029d8b48028 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/cheri-memfn-call.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/cheri-memfn-call.ll
@@ -12,13 +12,13 @@ declare void @llvm.memcpy.p200.p200.i64(ptr addrspace(200) nocapture, ptr addrsp
 define void @call_memset(ptr addrspace(200) align 4 %dst) nounwind {
 ; PURECAP-LABEL: call_memset:
 ; PURECAP:       # %bb.0: # %entry
-; PURECAP-NEXT:    cincoffset csp, csp, -16
-; PURECAP-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; PURECAP-NEXT:    cincoffset sp, sp, -16
+; PURECAP-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; PURECAP-NEXT:    li a2, 40
 ; PURECAP-NEXT:    li a1, 0
 ; PURECAP-NEXT:    ccall memset
-; PURECAP-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; PURECAP-NEXT:    cincoffset csp, csp, 16
+; PURECAP-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; PURECAP-NEXT:    cincoffset sp, sp, 16
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: call_memset:
@@ -39,12 +39,12 @@ entry:
 define void @call_memcpy(ptr addrspace(200) align 4 %dst, ptr addrspace(200) align 4 %src) nounwind {
 ; PURECAP-LABEL: call_memcpy:
 ; PURECAP:       # %bb.0: # %entry
-; PURECAP-NEXT:    cincoffset csp, csp, -16
-; PURECAP-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; PURECAP-NEXT:    cincoffset sp, sp, -16
+; PURECAP-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; PURECAP-NEXT:    li a2, 40
 ; PURECAP-NEXT:    ccall memcpy
-; PURECAP-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; PURECAP-NEXT:    cincoffset csp, csp, 16
+; PURECAP-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; PURECAP-NEXT:    cincoffset sp, sp, 16
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: call_memcpy:
@@ -64,12 +64,12 @@ entry:
 define void @call_memmove(ptr addrspace(200) align 4 %dst, ptr addrspace(200) align 4 %src) nounwind {
 ; PURECAP-LABEL: call_memmove:
 ; PURECAP:       # %bb.0: # %entry
-; PURECAP-NEXT:    cincoffset csp, csp, -16
-; PURECAP-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; PURECAP-NEXT:    cincoffset sp, sp, -16
+; PURECAP-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; PURECAP-NEXT:    li a2, 40
 ; PURECAP-NEXT:    ccall memmove
-; PURECAP-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; PURECAP-NEXT:    cincoffset csp, csp, 16
+; PURECAP-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; PURECAP-NEXT:    cincoffset sp, sp, 16
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: call_memmove:
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/cheri-pointer-comparison.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/cheri-pointer-comparison.ll
index 7b784307e9008..8bad7adebdea7 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/cheri-pointer-comparison.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/cheri-pointer-comparison.ll
@@ -365,7 +365,7 @@ define i8 addrspace(200)* @select_eq(i8 addrspace(200)* %a, i8 addrspace(200)* %
 ; HYBRID:       # %bb.0:
 ; HYBRID-NEXT:    beq a0, a1, .LBB20_2
 ; HYBRID-NEXT:  # %bb.1:
-; HYBRID-NEXT:    cmove ca0, ca1
+; HYBRID-NEXT:    cmove a0, a1
 ; HYBRID-NEXT:  .LBB20_2:
 ; HYBRID-NEXT:    ret
 ;
@@ -373,7 +373,7 @@ define i8 addrspace(200)* @select_eq(i8 addrspace(200)* %a, i8 addrspace(200)* %
 ; PURECAP:       # %bb.0:
 ; PURECAP-NEXT:    beq a0, a1, .LBB20_2
 ; PURECAP-NEXT:  # %bb.1:
-; PURECAP-NEXT:    cmove ca0, ca1
+; PURECAP-NEXT:    cmove a0, a1
 ; PURECAP-NEXT:  .LBB20_2:
 ; PURECAP-NEXT:    cret
   %cmp = icmp eq i8 addrspace(200)* %a, %b
@@ -386,7 +386,7 @@ define i8 addrspace(200)* @select_ne(i8 addrspace(200)* %a, i8 addrspace(200)* %
 ; HYBRID:       # %bb.0:
 ; HYBRID-NEXT:    bne a0, a1, .LBB21_2
 ; HYBRID-NEXT:  # %bb.1:
-; HYBRID-NEXT:    cmove ca0, ca1
+; HYBRID-NEXT:    cmove a0, a1
 ; HYBRID-NEXT:  .LBB21_2:
 ; HYBRID-NEXT:    ret
 ;
@@ -394,7 +394,7 @@ define i8 addrspace(200)* @select_ne(i8 addrspace(200)* %a, i8 addrspace(200)* %
 ; PURECAP:       # %bb.0:
 ; PURECAP-NEXT:    bne a0, a1, .LBB21_2
 ; PURECAP-NEXT:  # %bb.1:
-; PURECAP-NEXT:    cmove ca0, ca1
+; PURECAP-NEXT:    cmove a0, a1
 ; PURECAP-NEXT:  .LBB21_2:
 ; PURECAP-NEXT:    cret
   %cmp = icmp ne i8 addrspace(200)* %a, %b
@@ -407,7 +407,7 @@ define i8 addrspace(200)* @select_ugt(i8 addrspace(200)* %a, i8 addrspace(200)*
 ; HYBRID:       # %bb.0:
 ; HYBRID-NEXT:    bltu a1, a0, .LBB22_2
 ; HYBRID-NEXT:  # %bb.1:
-; HYBRID-NEXT:    cmove ca0, ca1
+; HYBRID-NEXT:    cmove a0, a1
 ; HYBRID-NEXT:  .LBB22_2:
 ; HYBRID-NEXT:    ret
 ;
@@ -415,7 +415,7 @@ define i8 addrspace(200)* @select_ugt(i8 addrspace(200)* %a, i8 addrspace(200)*
 ; PURECAP:       # %bb.0:
 ; PURECAP-NEXT:    bltu a1, a0, .LBB22_2
 ; PURECAP-NEXT:  # %bb.1:
-; PURECAP-NEXT:    cmove ca0, ca1
+; PURECAP-NEXT:    cmove a0, a1
 ; PURECAP-NEXT:  .LBB22_2:
 ; PURECAP-NEXT:    cret
   %cmp = icmp ugt i8 addrspace(200)* %a, %b
@@ -428,7 +428,7 @@ define i8 addrspace(200)* @select_uge(i8 addrspace(200)* %a, i8 addrspace(200)*
 ; HYBRID:       # %bb.0:
 ; HYBRID-NEXT:    bgeu a0, a1, .LBB23_2
 ; HYBRID-NEXT:  # %bb.1:
-; HYBRID-NEXT:    cmove ca0, ca1
+; HYBRID-NEXT:    cmove a0, a1
 ; HYBRID-NEXT:  .LBB23_2:
 ; HYBRID-NEXT:    ret
 ;
@@ -436,7 +436,7 @@ define i8 addrspace(200)* @select_uge(i8 addrspace(200)* %a, i8 addrspace(200)*
 ; PURECAP:       # %bb.0:
 ; PURECAP-NEXT:    bgeu a0, a1, .LBB23_2
 ; PURECAP-NEXT:  # %bb.1:
-; PURECAP-NEXT:    cmove ca0, ca1
+; PURECAP-NEXT:    cmove a0, a1
 ; PURECAP-NEXT:  .LBB23_2:
 ; PURECAP-NEXT:    cret
   %cmp = icmp uge i8 addrspace(200)* %a, %b
@@ -449,7 +449,7 @@ define i8 addrspace(200)* @select_ult(i8 addrspace(200)* %a, i8 addrspace(200)*
 ; HYBRID:       # %bb.0:
 ; HYBRID-NEXT:    bltu a0, a1, .LBB24_2
 ; HYBRID-NEXT:  # %bb.1:
-; HYBRID-NEXT:    cmove ca0, ca1
+; HYBRID-NEXT:    cmove a0, a1
 ; HYBRID-NEXT:  .LBB24_2:
 ; HYBRID-NEXT:    ret
 ;
@@ -457,7 +457,7 @@ define i8 addrspace(200)* @select_ult(i8 addrspace(200)* %a, i8 addrspace(200)*
 ; PURECAP:       # %bb.0:
 ; PURECAP-NEXT:    bltu a0, a1, .LBB24_2
 ; PURECAP-NEXT:  # %bb.1:
-; PURECAP-NEXT:    cmove ca0, ca1
+; PURECAP-NEXT:    cmove a0, a1
 ; PURECAP-NEXT:  .LBB24_2:
 ; PURECAP-NEXT:    cret
   %cmp = icmp ult i8 addrspace(200)* %a, %b
@@ -470,7 +470,7 @@ define i8 addrspace(200)* @select_ule(i8 addrspace(200)* %a, i8 addrspace(200)*
 ; HYBRID:       # %bb.0:
 ; HYBRID-NEXT:    bgeu a1, a0, .LBB25_2
 ; HYBRID-NEXT:  # %bb.1:
-; HYBRID-NEXT:    cmove ca0, ca1
+; HYBRID-NEXT:    cmove a0, a1
 ; HYBRID-NEXT:  .LBB25_2:
 ; HYBRID-NEXT:    ret
 ;
@@ -478,7 +478,7 @@ define i8 addrspace(200)* @select_ule(i8 addrspace(200)* %a, i8 addrspace(200)*
 ; PURECAP:       # %bb.0:
 ; PURECAP-NEXT:    bgeu a1, a0, .LBB25_2
 ; PURECAP-NEXT:  # %bb.1:
-; PURECAP-NEXT:    cmove ca0, ca1
+; PURECAP-NEXT:    cmove a0, a1
 ; PURECAP-NEXT:  .LBB25_2:
 ; PURECAP-NEXT:    cret
   %cmp = icmp ule i8 addrspace(200)* %a, %b
@@ -491,7 +491,7 @@ define i8 addrspace(200)* @select_sgt(i8 addrspace(200)* %a, i8 addrspace(200)*
 ; HYBRID:       # %bb.0:
 ; HYBRID-NEXT:    blt a1, a0, .LBB26_2
 ; HYBRID-NEXT:  # %bb.1:
-; HYBRID-NEXT:    cmove ca0, ca1
+; HYBRID-NEXT:    cmove a0, a1
 ; HYBRID-NEXT:  .LBB26_2:
 ; HYBRID-NEXT:    ret
 ;
@@ -499,7 +499,7 @@ define i8 addrspace(200)* @select_sgt(i8 addrspace(200)* %a, i8 addrspace(200)*
 ; PURECAP:       # %bb.0:
 ; PURECAP-NEXT:    blt a1, a0, .LBB26_2
 ; PURECAP-NEXT:  # %bb.1:
-; PURECAP-NEXT:    cmove ca0, ca1
+; PURECAP-NEXT:    cmove a0, a1
 ; PURECAP-NEXT:  .LBB26_2:
 ; PURECAP-NEXT:    cret
   %cmp = icmp sgt i8 addrspace(200)* %a, %b
@@ -512,7 +512,7 @@ define i8 addrspace(200)* @select_sge(i8 addrspace(200)* %a, i8 addrspace(200)*
 ; HYBRID:       # %bb.0:
 ; HYBRID-NEXT:    bge a0, a1, .LBB27_2
 ; HYBRID-NEXT:  # %bb.1:
-; HYBRID-NEXT:    cmove ca0, ca1
+; HYBRID-NEXT:    cmove a0, a1
 ; HYBRID-NEXT:  .LBB27_2:
 ; HYBRID-NEXT:    ret
 ;
@@ -520,7 +520,7 @@ define i8 addrspace(200)* @select_sge(i8 addrspace(200)* %a, i8 addrspace(200)*
 ; PURECAP:       # %bb.0:
 ; PURECAP-NEXT:    bge a0, a1, .LBB27_2
 ; PURECAP-NEXT:  # %bb.1:
-; PURECAP-NEXT:    cmove ca0, ca1
+; PURECAP-NEXT:    cmove a0, a1
 ; PURECAP-NEXT:  .LBB27_2:
 ; PURECAP-NEXT:    cret
   %cmp = icmp sge i8 addrspace(200)* %a, %b
@@ -533,7 +533,7 @@ define i8 addrspace(200)* @select_slt(i8 addrspace(200)* %a, i8 addrspace(200)*
 ; HYBRID:       # %bb.0:
 ; HYBRID-NEXT:    blt a0, a1, .LBB28_2
 ; HYBRID-NEXT:  # %bb.1:
-; HYBRID-NEXT:    cmove ca0, ca1
+; HYBRID-NEXT:    cmove a0, a1
 ; HYBRID-NEXT:  .LBB28_2:
 ; HYBRID-NEXT:    ret
 ;
@@ -541,7 +541,7 @@ define i8 addrspace(200)* @select_slt(i8 addrspace(200)* %a, i8 addrspace(200)*
 ; PURECAP:       # %bb.0:
 ; PURECAP-NEXT:    blt a0, a1, .LBB28_2
 ; PURECAP-NEXT:  # %bb.1:
-; PURECAP-NEXT:    cmove ca0, ca1
+; PURECAP-NEXT:    cmove a0, a1
 ; PURECAP-NEXT:  .LBB28_2:
 ; PURECAP-NEXT:    cret
   %cmp = icmp slt i8 addrspace(200)* %a, %b
@@ -554,7 +554,7 @@ define i8 addrspace(200)* @select_sle(i8 addrspace(200)* %a, i8 addrspace(200)*
 ; HYBRID:       # %bb.0:
 ; HYBRID-NEXT:    bge a1, a0, .LBB29_2
 ; HYBRID-NEXT:  # %bb.1:
-; HYBRID-NEXT:    cmove ca0, ca1
+; HYBRID-NEXT:    cmove a0, a1
 ; HYBRID-NEXT:  .LBB29_2:
 ; HYBRID-NEXT:    ret
 ;
@@ -562,7 +562,7 @@ define i8 addrspace(200)* @select_sle(i8 addrspace(200)* %a, i8 addrspace(200)*
 ; PURECAP:       # %bb.0:
 ; PURECAP-NEXT:    bge a1, a0, .LBB29_2
 ; PURECAP-NEXT:  # %bb.1:
-; PURECAP-NEXT:    cmove ca0, ca1
+; PURECAP-NEXT:    cmove a0, a1
 ; PURECAP-NEXT:  .LBB29_2:
 ; PURECAP-NEXT:    cret
   %cmp = icmp sle i8 addrspace(200)* %a, %b
@@ -575,7 +575,7 @@ define i8 addrspace(200)* @select_eq_null(i8 addrspace(200)* %a, i8 addrspace(20
 ; HYBRID:       # %bb.0:
 ; HYBRID-NEXT:    beqz a0, .LBB30_2
 ; HYBRID-NEXT:  # %bb.1:
-; HYBRID-NEXT:    cmove ca0, ca1
+; HYBRID-NEXT:    cmove a0, a1
 ; HYBRID-NEXT:  .LBB30_2:
 ; HYBRID-NEXT:    ret
 ;
@@ -583,7 +583,7 @@ define i8 addrspace(200)* @select_eq_null(i8 addrspace(200)* %a, i8 addrspace(20
 ; PURECAP:       # %bb.0:
 ; PURECAP-NEXT:    beqz a0, .LBB30_2
 ; PURECAP-NEXT:  # %bb.1:
-; PURECAP-NEXT:    cmove ca0, ca1
+; PURECAP-NEXT:    cmove a0, a1
 ; PURECAP-NEXT:  .LBB30_2:
 ; PURECAP-NEXT:    cret
   %cmp = icmp eq i8 addrspace(200)* %a, null
@@ -596,7 +596,7 @@ define i8 addrspace(200)* @select_ne_null(i8 addrspace(200)* %a, i8 addrspace(20
 ; HYBRID:       # %bb.0:
 ; HYBRID-NEXT:    bnez a0, .LBB31_2
 ; HYBRID-NEXT:  # %bb.1:
-; HYBRID-NEXT:    cmove ca0, ca1
+; HYBRID-NEXT:    cmove a0, a1
 ; HYBRID-NEXT:  .LBB31_2:
 ; HYBRID-NEXT:    ret
 ;
@@ -604,7 +604,7 @@ define i8 addrspace(200)* @select_ne_null(i8 addrspace(200)* %a, i8 addrspace(20
 ; PURECAP:       # %bb.0:
 ; PURECAP-NEXT:    bnez a0, .LBB31_2
 ; PURECAP-NEXT:  # %bb.1:
-; PURECAP-NEXT:    cmove ca0, ca1
+; PURECAP-NEXT:    cmove a0, a1
 ; PURECAP-NEXT:  .LBB31_2:
 ; PURECAP-NEXT:    cret
   %cmp = icmp ne i8 addrspace(200)* %a, null
@@ -617,7 +617,7 @@ define i8 addrspace(200)* @select_ugt_null(i8 addrspace(200)* %a, i8 addrspace(2
 ; HYBRID:       # %bb.0:
 ; HYBRID-NEXT:    bnez a0, .LBB32_2
 ; HYBRID-NEXT:  # %bb.1:
-; HYBRID-NEXT:    cmove ca0, ca1
+; HYBRID-NEXT:    cmove a0, a1
 ; HYBRID-NEXT:  .LBB32_2:
 ; HYBRID-NEXT:    ret
 ;
@@ -625,7 +625,7 @@ define i8 addrspace(200)* @select_ugt_null(i8 addrspace(200)* %a, i8 addrspace(2
 ; PURECAP:       # %bb.0:
 ; PURECAP-NEXT:    bnez a0, .LBB32_2
 ; PURECAP-NEXT:  # %bb.1:
-; PURECAP-NEXT:    cmove ca0, ca1
+; PURECAP-NEXT:    cmove a0, a1
 ; PURECAP-NEXT:  .LBB32_2:
 ; PURECAP-NEXT:    cret
   %cmp = icmp ugt i8 addrspace(200)* %a, null
@@ -638,7 +638,7 @@ define i8 addrspace(200)* @select_uge_null(i8 addrspace(200)* %a, i8 addrspace(2
 ; HYBRID:       # %bb.0:
 ; HYBRID-NEXT:    bgeu a0, zero, .LBB33_2
 ; HYBRID-NEXT:  # %bb.1:
-; HYBRID-NEXT:    cmove ca0, ca1
+; HYBRID-NEXT:    cmove a0, a1
 ; HYBRID-NEXT:  .LBB33_2:
 ; HYBRID-NEXT:    ret
 ;
@@ -646,7 +646,7 @@ define i8 addrspace(200)* @select_uge_null(i8 addrspace(200)* %a, i8 addrspace(2
 ; PURECAP:       # %bb.0:
 ; PURECAP-NEXT:    bgeu a0, zero, .LBB33_2
 ; PURECAP-NEXT:  # %bb.1:
-; PURECAP-NEXT:    cmove ca0, ca1
+; PURECAP-NEXT:    cmove a0, a1
 ; PURECAP-NEXT:  .LBB33_2:
 ; PURECAP-NEXT:    cret
   %cmp = icmp uge i8 addrspace(200)* %a, null
@@ -659,7 +659,7 @@ define i8 addrspace(200)* @select_ult_null(i8 addrspace(200)* %a, i8 addrspace(2
 ; HYBRID:       # %bb.0:
 ; HYBRID-NEXT:    bltu a0, zero, .LBB34_2
 ; HYBRID-NEXT:  # %bb.1:
-; HYBRID-NEXT:    cmove ca0, ca1
+; HYBRID-NEXT:    cmove a0, a1
 ; HYBRID-NEXT:  .LBB34_2:
 ; HYBRID-NEXT:    ret
 ;
@@ -667,7 +667,7 @@ define i8 addrspace(200)* @select_ult_null(i8 addrspace(200)* %a, i8 addrspace(2
 ; PURECAP:       # %bb.0:
 ; PURECAP-NEXT:    bltu a0, zero, .LBB34_2
 ; PURECAP-NEXT:  # %bb.1:
-; PURECAP-NEXT:    cmove ca0, ca1
+; PURECAP-NEXT:    cmove a0, a1
 ; PURECAP-NEXT:  .LBB34_2:
 ; PURECAP-NEXT:    cret
   %cmp = icmp ult i8 addrspace(200)* %a, null
@@ -680,7 +680,7 @@ define i8 addrspace(200)* @select_ule_null(i8 addrspace(200)* %a, i8 addrspace(2
 ; HYBRID:       # %bb.0:
 ; HYBRID-NEXT:    beqz a0, .LBB35_2
 ; HYBRID-NEXT:  # %bb.1:
-; HYBRID-NEXT:    cmove ca0, ca1
+; HYBRID-NEXT:    cmove a0, a1
 ; HYBRID-NEXT:  .LBB35_2:
 ; HYBRID-NEXT:    ret
 ;
@@ -688,7 +688,7 @@ define i8 addrspace(200)* @select_ule_null(i8 addrspace(200)* %a, i8 addrspace(2
 ; PURECAP:       # %bb.0:
 ; PURECAP-NEXT:    beqz a0, .LBB35_2
 ; PURECAP-NEXT:  # %bb.1:
-; PURECAP-NEXT:    cmove ca0, ca1
+; PURECAP-NEXT:    cmove a0, a1
 ; PURECAP-NEXT:  .LBB35_2:
 ; PURECAP-NEXT:    cret
   %cmp = icmp ule i8 addrspace(200)* %a, null
@@ -701,7 +701,7 @@ define i8 addrspace(200)* @select_sgt_null(i8 addrspace(200)* %a, i8 addrspace(2
 ; HYBRID:       # %bb.0:
 ; HYBRID-NEXT:    bgtz a0, .LBB36_2
 ; HYBRID-NEXT:  # %bb.1:
-; HYBRID-NEXT:    cmove ca0, ca1
+; HYBRID-NEXT:    cmove a0, a1
 ; HYBRID-NEXT:  .LBB36_2:
 ; HYBRID-NEXT:    ret
 ;
@@ -709,7 +709,7 @@ define i8 addrspace(200)* @select_sgt_null(i8 addrspace(200)* %a, i8 addrspace(2
 ; PURECAP:       # %bb.0:
 ; PURECAP-NEXT:    bgtz a0, .LBB36_2
 ; PURECAP-NEXT:  # %bb.1:
-; PURECAP-NEXT:    cmove ca0, ca1
+; PURECAP-NEXT:    cmove a0, a1
 ; PURECAP-NEXT:  .LBB36_2:
 ; PURECAP-NEXT:    cret
   %cmp = icmp sgt i8 addrspace(200)* %a, null
@@ -722,7 +722,7 @@ define i8 addrspace(200)* @select_sge_null(i8 addrspace(200)* %a, i8 addrspace(2
 ; HYBRID:       # %bb.0:
 ; HYBRID-NEXT:    bgez a0, .LBB37_2
 ; HYBRID-NEXT:  # %bb.1:
-; HYBRID-NEXT:    cmove ca0, ca1
+; HYBRID-NEXT:    cmove a0, a1
 ; HYBRID-NEXT:  .LBB37_2:
 ; HYBRID-NEXT:    ret
 ;
@@ -730,7 +730,7 @@ define i8 addrspace(200)* @select_sge_null(i8 addrspace(200)* %a, i8 addrspace(2
 ; PURECAP:       # %bb.0:
 ; PURECAP-NEXT:    bgez a0, .LBB37_2
 ; PURECAP-NEXT:  # %bb.1:
-; PURECAP-NEXT:    cmove ca0, ca1
+; PURECAP-NEXT:    cmove a0, a1
 ; PURECAP-NEXT:  .LBB37_2:
 ; PURECAP-NEXT:    cret
   %cmp = icmp sge i8 addrspace(200)* %a, null
@@ -743,7 +743,7 @@ define i8 addrspace(200)* @select_slt_null(i8 addrspace(200)* %a, i8 addrspace(2
 ; HYBRID:       # %bb.0:
 ; HYBRID-NEXT:    bltz a0, .LBB38_2
 ; HYBRID-NEXT:  # %bb.1:
-; HYBRID-NEXT:    cmove ca0, ca1
+; HYBRID-NEXT:    cmove a0, a1
 ; HYBRID-NEXT:  .LBB38_2:
 ; HYBRID-NEXT:    ret
 ;
@@ -751,7 +751,7 @@ define i8 addrspace(200)* @select_slt_null(i8 addrspace(200)* %a, i8 addrspace(2
 ; PURECAP:       # %bb.0:
 ; PURECAP-NEXT:    bltz a0, .LBB38_2
 ; PURECAP-NEXT:  # %bb.1:
-; PURECAP-NEXT:    cmove ca0, ca1
+; PURECAP-NEXT:    cmove a0, a1
 ; PURECAP-NEXT:  .LBB38_2:
 ; PURECAP-NEXT:    cret
   %cmp = icmp slt i8 addrspace(200)* %a, null
@@ -764,7 +764,7 @@ define i8 addrspace(200)* @select_sle_null(i8 addrspace(200)* %a, i8 addrspace(2
 ; HYBRID:       # %bb.0:
 ; HYBRID-NEXT:    blez a0, .LBB39_2
 ; HYBRID-NEXT:  # %bb.1:
-; HYBRID-NEXT:    cmove ca0, ca1
+; HYBRID-NEXT:    cmove a0, a1
 ; HYBRID-NEXT:  .LBB39_2:
 ; HYBRID-NEXT:    ret
 ;
@@ -772,7 +772,7 @@ define i8 addrspace(200)* @select_sle_null(i8 addrspace(200)* %a, i8 addrspace(2
 ; PURECAP:       # %bb.0:
 ; PURECAP-NEXT:    blez a0, .LBB39_2
 ; PURECAP-NEXT:  # %bb.1:
-; PURECAP-NEXT:    cmove ca0, ca1
+; PURECAP-NEXT:    cmove a0, a1
 ; PURECAP-NEXT:  .LBB39_2:
 ; PURECAP-NEXT:    cret
   %cmp = icmp sle i8 addrspace(200)* %a, null
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/cmpxchg-cap-ptr.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/cmpxchg-cap-ptr.ll
index 6934cd220fc3c..101b6d9dd4f4a 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/cmpxchg-cap-ptr.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/cmpxchg-cap-ptr.ll
@@ -14,10 +14,10 @@ define { i8, i1 } @test_cmpxchg_strong_i8(ptr addrspace(200) %ptr, i8 %exp, i8 %
 ; PURECAP-ATOMICS-NEXT:    slli a1, a1, 56
 ; PURECAP-ATOMICS-NEXT:    srai a1, a1, 56
 ; PURECAP-ATOMICS-NEXT:  .LBB0_1: # =>This Inner Loop Header: Depth=1
-; PURECAP-ATOMICS-NEXT:    clr.b.aq a3, (ca0)
+; PURECAP-ATOMICS-NEXT:    clr.b.aq a3, (a0)
 ; PURECAP-ATOMICS-NEXT:    bne a3, a1, .LBB0_3
 ; PURECAP-ATOMICS-NEXT:  # %bb.2: # in Loop: Header=BB0_1 Depth=1
-; PURECAP-ATOMICS-NEXT:    csc.b.rl a4, a2, (ca0)
+; PURECAP-ATOMICS-NEXT:    csc.b.rl a4, a2, (a0)
 ; PURECAP-ATOMICS-NEXT:    bnez a4, .LBB0_1
 ; PURECAP-ATOMICS-NEXT:  .LBB0_3:
 ; PURECAP-ATOMICS-NEXT:    xor a1, a3, a1
@@ -27,20 +27,20 @@ define { i8, i1 } @test_cmpxchg_strong_i8(ptr addrspace(200) %ptr, i8 %exp, i8 %
 ;
 ; PURECAP-LIBCALLS-LABEL: test_cmpxchg_strong_i8:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -32
-; PURECAP-LIBCALLS-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csb a1, 15(csp)
-; PURECAP-LIBCALLS-NEXT:    cincoffset ca1, csp, 15
-; PURECAP-LIBCALLS-NEXT:    csetbounds ca1, ca1, 1
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -32
+; PURECAP-LIBCALLS-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csb a1, 15(sp)
+; PURECAP-LIBCALLS-NEXT:    cincoffset a1, sp, 15
+; PURECAP-LIBCALLS-NEXT:    csetbounds a1, a1, 1
 ; PURECAP-LIBCALLS-NEXT:    li a3, 4
 ; PURECAP-LIBCALLS-NEXT:    li a4, 2
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_compare_exchange_1
-; PURECAP-LIBCALLS-NEXT:    clb a1, 15(csp)
+; PURECAP-LIBCALLS-NEXT:    clb a1, 15(sp)
 ; PURECAP-LIBCALLS-NEXT:    mv a2, a0
 ; PURECAP-LIBCALLS-NEXT:    mv a0, a1
 ; PURECAP-LIBCALLS-NEXT:    mv a1, a2
-; PURECAP-LIBCALLS-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 32
+; PURECAP-LIBCALLS-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 32
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: test_cmpxchg_strong_i8:
@@ -69,10 +69,10 @@ define { i16, i1 } @test_cmpxchg_strong_i16(ptr addrspace(200) %ptr, i16 %exp, i
 ; PURECAP-ATOMICS-NEXT:    slli a1, a1, 48
 ; PURECAP-ATOMICS-NEXT:    srai a1, a1, 48
 ; PURECAP-ATOMICS-NEXT:  .LBB1_1: # =>This Inner Loop Header: Depth=1
-; PURECAP-ATOMICS-NEXT:    clr.h.aq a3, (ca0)
+; PURECAP-ATOMICS-NEXT:    clr.h.aq a3, (a0)
 ; PURECAP-ATOMICS-NEXT:    bne a3, a1, .LBB1_3
 ; PURECAP-ATOMICS-NEXT:  # %bb.2: # in Loop: Header=BB1_1 Depth=1
-; PURECAP-ATOMICS-NEXT:    csc.h.rl a4, a2, (ca0)
+; PURECAP-ATOMICS-NEXT:    csc.h.rl a4, a2, (a0)
 ; PURECAP-ATOMICS-NEXT:    bnez a4, .LBB1_1
 ; PURECAP-ATOMICS-NEXT:  .LBB1_3:
 ; PURECAP-ATOMICS-NEXT:    xor a1, a3, a1
@@ -82,20 +82,20 @@ define { i16, i1 } @test_cmpxchg_strong_i16(ptr addrspace(200) %ptr, i16 %exp, i
 ;
 ; PURECAP-LIBCALLS-LABEL: test_cmpxchg_strong_i16:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -32
-; PURECAP-LIBCALLS-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csh a1, 14(csp)
-; PURECAP-LIBCALLS-NEXT:    cincoffset ca1, csp, 14
-; PURECAP-LIBCALLS-NEXT:    csetbounds ca1, ca1, 2
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -32
+; PURECAP-LIBCALLS-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csh a1, 14(sp)
+; PURECAP-LIBCALLS-NEXT:    cincoffset a1, sp, 14
+; PURECAP-LIBCALLS-NEXT:    csetbounds a1, a1, 2
 ; PURECAP-LIBCALLS-NEXT:    li a3, 4
 ; PURECAP-LIBCALLS-NEXT:    li a4, 2
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_compare_exchange_2
-; PURECAP-LIBCALLS-NEXT:    clh a1, 14(csp)
+; PURECAP-LIBCALLS-NEXT:    clh a1, 14(sp)
 ; PURECAP-LIBCALLS-NEXT:    mv a2, a0
 ; PURECAP-LIBCALLS-NEXT:    mv a0, a1
 ; PURECAP-LIBCALLS-NEXT:    mv a1, a2
-; PURECAP-LIBCALLS-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 32
+; PURECAP-LIBCALLS-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 32
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: test_cmpxchg_strong_i16:
@@ -123,10 +123,10 @@ define { i32, i1 } @test_cmpxchg_strong_i32(ptr addrspace(200) %ptr, i32 %exp, i
 ; PURECAP-ATOMICS:       # %bb.0:
 ; PURECAP-ATOMICS-NEXT:    sext.w a1, a1
 ; PURECAP-ATOMICS-NEXT:  .LBB2_1: # =>This Inner Loop Header: Depth=1
-; PURECAP-ATOMICS-NEXT:    clr.w.aq a3, (ca0)
+; PURECAP-ATOMICS-NEXT:    clr.w.aq a3, (a0)
 ; PURECAP-ATOMICS-NEXT:    bne a3, a1, .LBB2_3
 ; PURECAP-ATOMICS-NEXT:  # %bb.2: # in Loop: Header=BB2_1 Depth=1
-; PURECAP-ATOMICS-NEXT:    csc.w.rl a4, a2, (ca0)
+; PURECAP-ATOMICS-NEXT:    csc.w.rl a4, a2, (a0)
 ; PURECAP-ATOMICS-NEXT:    bnez a4, .LBB2_1
 ; PURECAP-ATOMICS-NEXT:  .LBB2_3:
 ; PURECAP-ATOMICS-NEXT:    xor a1, a3, a1
@@ -136,20 +136,20 @@ define { i32, i1 } @test_cmpxchg_strong_i32(ptr addrspace(200) %ptr, i32 %exp, i
 ;
 ; PURECAP-LIBCALLS-LABEL: test_cmpxchg_strong_i32:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -32
-; PURECAP-LIBCALLS-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csw a1, 12(csp)
-; PURECAP-LIBCALLS-NEXT:    cincoffset ca1, csp, 12
-; PURECAP-LIBCALLS-NEXT:    csetbounds ca1, ca1, 4
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -32
+; PURECAP-LIBCALLS-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csw a1, 12(sp)
+; PURECAP-LIBCALLS-NEXT:    cincoffset a1, sp, 12
+; PURECAP-LIBCALLS-NEXT:    csetbounds a1, a1, 4
 ; PURECAP-LIBCALLS-NEXT:    li a3, 4
 ; PURECAP-LIBCALLS-NEXT:    li a4, 2
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_compare_exchange_4
-; PURECAP-LIBCALLS-NEXT:    clw a1, 12(csp)
+; PURECAP-LIBCALLS-NEXT:    clw a1, 12(sp)
 ; PURECAP-LIBCALLS-NEXT:    mv a2, a0
 ; PURECAP-LIBCALLS-NEXT:    mv a0, a1
 ; PURECAP-LIBCALLS-NEXT:    mv a1, a2
-; PURECAP-LIBCALLS-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 32
+; PURECAP-LIBCALLS-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 32
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: test_cmpxchg_strong_i32:
@@ -176,10 +176,10 @@ define { i64, i1 } @test_cmpxchg_strong_i64(ptr addrspace(200) %ptr, i64 %exp, i
 ; PURECAP-ATOMICS-LABEL: test_cmpxchg_strong_i64:
 ; PURECAP-ATOMICS:       # %bb.0:
 ; PURECAP-ATOMICS-NEXT:  .LBB3_1: # =>This Inner Loop Header: Depth=1
-; PURECAP-ATOMICS-NEXT:    clr.d.aq a3, (ca0)
+; PURECAP-ATOMICS-NEXT:    clr.d.aq a3, (a0)
 ; PURECAP-ATOMICS-NEXT:    bne a3, a1, .LBB3_3
 ; PURECAP-ATOMICS-NEXT:  # %bb.2: # in Loop: Header=BB3_1 Depth=1
-; PURECAP-ATOMICS-NEXT:    csc.d.rl a4, a2, (ca0)
+; PURECAP-ATOMICS-NEXT:    csc.d.rl a4, a2, (a0)
 ; PURECAP-ATOMICS-NEXT:    bnez a4, .LBB3_1
 ; PURECAP-ATOMICS-NEXT:  .LBB3_3:
 ; PURECAP-ATOMICS-NEXT:    xor a1, a3, a1
@@ -189,20 +189,20 @@ define { i64, i1 } @test_cmpxchg_strong_i64(ptr addrspace(200) %ptr, i64 %exp, i
 ;
 ; PURECAP-LIBCALLS-LABEL: test_cmpxchg_strong_i64:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -32
-; PURECAP-LIBCALLS-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csd a1, 8(csp)
-; PURECAP-LIBCALLS-NEXT:    cincoffset ca1, csp, 8
-; PURECAP-LIBCALLS-NEXT:    csetbounds ca1, ca1, 8
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -32
+; PURECAP-LIBCALLS-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csd a1, 8(sp)
+; PURECAP-LIBCALLS-NEXT:    cincoffset a1, sp, 8
+; PURECAP-LIBCALLS-NEXT:    csetbounds a1, a1, 8
 ; PURECAP-LIBCALLS-NEXT:    li a3, 4
 ; PURECAP-LIBCALLS-NEXT:    li a4, 2
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_compare_exchange_8
-; PURECAP-LIBCALLS-NEXT:    cld a1, 8(csp)
+; PURECAP-LIBCALLS-NEXT:    cld a1, 8(sp)
 ; PURECAP-LIBCALLS-NEXT:    mv a2, a0
 ; PURECAP-LIBCALLS-NEXT:    mv a0, a1
 ; PURECAP-LIBCALLS-NEXT:    mv a1, a2
-; PURECAP-LIBCALLS-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 32
+; PURECAP-LIBCALLS-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 32
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: test_cmpxchg_strong_i64:
@@ -229,47 +229,47 @@ define { ptr addrspace(200), i1 } @test_cmpxchg_strong_cap(ptr addrspace(200) %p
 ; PURECAP-ATOMICS-LABEL: test_cmpxchg_strong_cap:
 ; PURECAP-ATOMICS:       # %bb.0:
 ; PURECAP-ATOMICS-NEXT:  .LBB4_1: # =>This Inner Loop Header: Depth=1
-; PURECAP-ATOMICS-NEXT:    clr.c.aq ca3, (ca0)
+; PURECAP-ATOMICS-NEXT:    clr.c.aq a3, (a0)
 ; PURECAP-ATOMICS-NEXT:    bne a3, a1, .LBB4_3
 ; PURECAP-ATOMICS-NEXT:  # %bb.2: # in Loop: Header=BB4_1 Depth=1
-; PURECAP-ATOMICS-NEXT:    csc.c.aq a4, ca2, (ca0)
+; PURECAP-ATOMICS-NEXT:    csc.c.aq a4, a2, (a0)
 ; PURECAP-ATOMICS-NEXT:    bnez a4, .LBB4_1
 ; PURECAP-ATOMICS-NEXT:  .LBB4_3:
 ; PURECAP-ATOMICS-NEXT:    xor a0, a3, a1
 ; PURECAP-ATOMICS-NEXT:    seqz a1, a0
-; PURECAP-ATOMICS-NEXT:    cmove ca0, ca3
+; PURECAP-ATOMICS-NEXT:    cmove a0, a3
 ; PURECAP-ATOMICS-NEXT:    cret
 ;
 ; PURECAP-LIBCALLS-LABEL: test_cmpxchg_strong_cap:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -32
-; PURECAP-LIBCALLS-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc ca1, 0(csp)
-; PURECAP-LIBCALLS-NEXT:    cincoffset ca1, csp, 0
-; PURECAP-LIBCALLS-NEXT:    csetbounds ca1, ca1, 16
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -32
+; PURECAP-LIBCALLS-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc a1, 0(sp)
+; PURECAP-LIBCALLS-NEXT:    cincoffset a1, sp, 0
+; PURECAP-LIBCALLS-NEXT:    csetbounds a1, a1, 16
 ; PURECAP-LIBCALLS-NEXT:    li a3, 4
 ; PURECAP-LIBCALLS-NEXT:    li a4, 2
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_compare_exchange_cap
-; PURECAP-LIBCALLS-NEXT:    clc ca1, 0(csp)
+; PURECAP-LIBCALLS-NEXT:    clc a1, 0(sp)
 ; PURECAP-LIBCALLS-NEXT:    mv a2, a0
-; PURECAP-LIBCALLS-NEXT:    cmove ca0, ca1
+; PURECAP-LIBCALLS-NEXT:    cmove a0, a1
 ; PURECAP-LIBCALLS-NEXT:    mv a1, a2
-; PURECAP-LIBCALLS-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 32
+; PURECAP-LIBCALLS-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 32
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: test_cmpxchg_strong_cap:
 ; HYBRID:       # %bb.0:
 ; HYBRID-NEXT:    addi sp, sp, -32
 ; HYBRID-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
-; HYBRID-NEXT:    sc ca1, 0(sp)
+; HYBRID-NEXT:    sc a1, 0(sp)
 ; HYBRID-NEXT:    mv a1, sp
 ; HYBRID-NEXT:    li a3, 4
 ; HYBRID-NEXT:    li a4, 2
 ; HYBRID-NEXT:    call __atomic_compare_exchange_cap_c
-; HYBRID-NEXT:    lc ca1, 0(sp)
+; HYBRID-NEXT:    lc a1, 0(sp)
 ; HYBRID-NEXT:    mv a2, a0
-; HYBRID-NEXT:    cmove ca0, ca1
+; HYBRID-NEXT:    cmove a0, a1
 ; HYBRID-NEXT:    mv a1, a2
 ; HYBRID-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; HYBRID-NEXT:    addi sp, sp, 32
@@ -282,47 +282,47 @@ define { ptr addrspace(200), i1 } @test_cmpxchg_strong_cap_i32(ptr addrspace(200
 ; PURECAP-ATOMICS-LABEL: test_cmpxchg_strong_cap_i32:
 ; PURECAP-ATOMICS:       # %bb.0:
 ; PURECAP-ATOMICS-NEXT:  .LBB5_1: # =>This Inner Loop Header: Depth=1
-; PURECAP-ATOMICS-NEXT:    clr.c.aq ca3, (ca0)
+; PURECAP-ATOMICS-NEXT:    clr.c.aq a3, (a0)
 ; PURECAP-ATOMICS-NEXT:    bne a3, a1, .LBB5_3
 ; PURECAP-ATOMICS-NEXT:  # %bb.2: # in Loop: Header=BB5_1 Depth=1
-; PURECAP-ATOMICS-NEXT:    csc.c.aq a4, ca2, (ca0)
+; PURECAP-ATOMICS-NEXT:    csc.c.aq a4, a2, (a0)
 ; PURECAP-ATOMICS-NEXT:    bnez a4, .LBB5_1
 ; PURECAP-ATOMICS-NEXT:  .LBB5_3:
 ; PURECAP-ATOMICS-NEXT:    xor a0, a3, a1
 ; PURECAP-ATOMICS-NEXT:    seqz a1, a0
-; PURECAP-ATOMICS-NEXT:    cmove ca0, ca3
+; PURECAP-ATOMICS-NEXT:    cmove a0, a3
 ; PURECAP-ATOMICS-NEXT:    cret
 ;
 ; PURECAP-LIBCALLS-LABEL: test_cmpxchg_strong_cap_i32:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -32
-; PURECAP-LIBCALLS-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc ca1, 0(csp)
-; PURECAP-LIBCALLS-NEXT:    cincoffset ca1, csp, 0
-; PURECAP-LIBCALLS-NEXT:    csetbounds ca1, ca1, 16
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -32
+; PURECAP-LIBCALLS-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc a1, 0(sp)
+; PURECAP-LIBCALLS-NEXT:    cincoffset a1, sp, 0
+; PURECAP-LIBCALLS-NEXT:    csetbounds a1, a1, 16
 ; PURECAP-LIBCALLS-NEXT:    li a3, 4
 ; PURECAP-LIBCALLS-NEXT:    li a4, 2
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_compare_exchange_cap
-; PURECAP-LIBCALLS-NEXT:    clc ca1, 0(csp)
+; PURECAP-LIBCALLS-NEXT:    clc a1, 0(sp)
 ; PURECAP-LIBCALLS-NEXT:    mv a2, a0
-; PURECAP-LIBCALLS-NEXT:    cmove ca0, ca1
+; PURECAP-LIBCALLS-NEXT:    cmove a0, a1
 ; PURECAP-LIBCALLS-NEXT:    mv a1, a2
-; PURECAP-LIBCALLS-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 32
+; PURECAP-LIBCALLS-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 32
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: test_cmpxchg_strong_cap_i32:
 ; HYBRID:       # %bb.0:
 ; HYBRID-NEXT:    addi sp, sp, -32
 ; HYBRID-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
-; HYBRID-NEXT:    sc ca1, 0(sp)
+; HYBRID-NEXT:    sc a1, 0(sp)
 ; HYBRID-NEXT:    mv a1, sp
 ; HYBRID-NEXT:    li a3, 4
 ; HYBRID-NEXT:    li a4, 2
 ; HYBRID-NEXT:    call __atomic_compare_exchange_cap_c
-; HYBRID-NEXT:    lc ca1, 0(sp)
+; HYBRID-NEXT:    lc a1, 0(sp)
 ; HYBRID-NEXT:    mv a2, a0
-; HYBRID-NEXT:    cmove ca0, ca1
+; HYBRID-NEXT:    cmove a0, a1
 ; HYBRID-NEXT:    mv a1, a2
 ; HYBRID-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; HYBRID-NEXT:    addi sp, sp, 32
@@ -338,10 +338,10 @@ define { i8, i1 } @test_cmpxchg_weak_i8(ptr addrspace(200) %ptr, i8 %exp, i8 %ne
 ; PURECAP-ATOMICS-NEXT:    slli a1, a1, 56
 ; PURECAP-ATOMICS-NEXT:    srai a1, a1, 56
 ; PURECAP-ATOMICS-NEXT:  .LBB6_1: # =>This Inner Loop Header: Depth=1
-; PURECAP-ATOMICS-NEXT:    clr.b.aq a3, (ca0)
+; PURECAP-ATOMICS-NEXT:    clr.b.aq a3, (a0)
 ; PURECAP-ATOMICS-NEXT:    bne a3, a1, .LBB6_3
 ; PURECAP-ATOMICS-NEXT:  # %bb.2: # in Loop: Header=BB6_1 Depth=1
-; PURECAP-ATOMICS-NEXT:    csc.b.rl a4, a2, (ca0)
+; PURECAP-ATOMICS-NEXT:    csc.b.rl a4, a2, (a0)
 ; PURECAP-ATOMICS-NEXT:    bnez a4, .LBB6_1
 ; PURECAP-ATOMICS-NEXT:  .LBB6_3:
 ; PURECAP-ATOMICS-NEXT:    xor a1, a3, a1
@@ -351,20 +351,20 @@ define { i8, i1 } @test_cmpxchg_weak_i8(ptr addrspace(200) %ptr, i8 %exp, i8 %ne
 ;
 ; PURECAP-LIBCALLS-LABEL: test_cmpxchg_weak_i8:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -32
-; PURECAP-LIBCALLS-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csb a1, 15(csp)
-; PURECAP-LIBCALLS-NEXT:    cincoffset ca1, csp, 15
-; PURECAP-LIBCALLS-NEXT:    csetbounds ca1, ca1, 1
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -32
+; PURECAP-LIBCALLS-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csb a1, 15(sp)
+; PURECAP-LIBCALLS-NEXT:    cincoffset a1, sp, 15
+; PURECAP-LIBCALLS-NEXT:    csetbounds a1, a1, 1
 ; PURECAP-LIBCALLS-NEXT:    li a3, 4
 ; PURECAP-LIBCALLS-NEXT:    li a4, 2
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_compare_exchange_1
-; PURECAP-LIBCALLS-NEXT:    clb a1, 15(csp)
+; PURECAP-LIBCALLS-NEXT:    clb a1, 15(sp)
 ; PURECAP-LIBCALLS-NEXT:    mv a2, a0
 ; PURECAP-LIBCALLS-NEXT:    mv a0, a1
 ; PURECAP-LIBCALLS-NEXT:    mv a1, a2
-; PURECAP-LIBCALLS-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 32
+; PURECAP-LIBCALLS-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 32
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: test_cmpxchg_weak_i8:
@@ -393,10 +393,10 @@ define { i16, i1 } @test_cmpxchg_weak_i16(ptr addrspace(200) %ptr, i16 %exp, i16
 ; PURECAP-ATOMICS-NEXT:    slli a1, a1, 48
 ; PURECAP-ATOMICS-NEXT:    srai a1, a1, 48
 ; PURECAP-ATOMICS-NEXT:  .LBB7_1: # =>This Inner Loop Header: Depth=1
-; PURECAP-ATOMICS-NEXT:    clr.h.aq a3, (ca0)
+; PURECAP-ATOMICS-NEXT:    clr.h.aq a3, (a0)
 ; PURECAP-ATOMICS-NEXT:    bne a3, a1, .LBB7_3
 ; PURECAP-ATOMICS-NEXT:  # %bb.2: # in Loop: Header=BB7_1 Depth=1
-; PURECAP-ATOMICS-NEXT:    csc.h.rl a4, a2, (ca0)
+; PURECAP-ATOMICS-NEXT:    csc.h.rl a4, a2, (a0)
 ; PURECAP-ATOMICS-NEXT:    bnez a4, .LBB7_1
 ; PURECAP-ATOMICS-NEXT:  .LBB7_3:
 ; PURECAP-ATOMICS-NEXT:    xor a1, a3, a1
@@ -406,20 +406,20 @@ define { i16, i1 } @test_cmpxchg_weak_i16(ptr addrspace(200) %ptr, i16 %exp, i16
 ;
 ; PURECAP-LIBCALLS-LABEL: test_cmpxchg_weak_i16:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -32
-; PURECAP-LIBCALLS-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csh a1, 14(csp)
-; PURECAP-LIBCALLS-NEXT:    cincoffset ca1, csp, 14
-; PURECAP-LIBCALLS-NEXT:    csetbounds ca1, ca1, 2
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -32
+; PURECAP-LIBCALLS-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csh a1, 14(sp)
+; PURECAP-LIBCALLS-NEXT:    cincoffset a1, sp, 14
+; PURECAP-LIBCALLS-NEXT:    csetbounds a1, a1, 2
 ; PURECAP-LIBCALLS-NEXT:    li a3, 4
 ; PURECAP-LIBCALLS-NEXT:    li a4, 2
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_compare_exchange_2
-; PURECAP-LIBCALLS-NEXT:    clh a1, 14(csp)
+; PURECAP-LIBCALLS-NEXT:    clh a1, 14(sp)
 ; PURECAP-LIBCALLS-NEXT:    mv a2, a0
 ; PURECAP-LIBCALLS-NEXT:    mv a0, a1
 ; PURECAP-LIBCALLS-NEXT:    mv a1, a2
-; PURECAP-LIBCALLS-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 32
+; PURECAP-LIBCALLS-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 32
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: test_cmpxchg_weak_i16:
@@ -447,10 +447,10 @@ define { i32, i1 } @test_cmpxchg_weak_i32(ptr addrspace(200) %ptr, i32 %exp, i32
 ; PURECAP-ATOMICS:       # %bb.0:
 ; PURECAP-ATOMICS-NEXT:    sext.w a1, a1
 ; PURECAP-ATOMICS-NEXT:  .LBB8_1: # =>This Inner Loop Header: Depth=1
-; PURECAP-ATOMICS-NEXT:    clr.w.aq a3, (ca0)
+; PURECAP-ATOMICS-NEXT:    clr.w.aq a3, (a0)
 ; PURECAP-ATOMICS-NEXT:    bne a3, a1, .LBB8_3
 ; PURECAP-ATOMICS-NEXT:  # %bb.2: # in Loop: Header=BB8_1 Depth=1
-; PURECAP-ATOMICS-NEXT:    csc.w.rl a4, a2, (ca0)
+; PURECAP-ATOMICS-NEXT:    csc.w.rl a4, a2, (a0)
 ; PURECAP-ATOMICS-NEXT:    bnez a4, .LBB8_1
 ; PURECAP-ATOMICS-NEXT:  .LBB8_3:
 ; PURECAP-ATOMICS-NEXT:    xor a1, a3, a1
@@ -460,20 +460,20 @@ define { i32, i1 } @test_cmpxchg_weak_i32(ptr addrspace(200) %ptr, i32 %exp, i32
 ;
 ; PURECAP-LIBCALLS-LABEL: test_cmpxchg_weak_i32:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -32
-; PURECAP-LIBCALLS-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csw a1, 12(csp)
-; PURECAP-LIBCALLS-NEXT:    cincoffset ca1, csp, 12
-; PURECAP-LIBCALLS-NEXT:    csetbounds ca1, ca1, 4
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -32
+; PURECAP-LIBCALLS-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csw a1, 12(sp)
+; PURECAP-LIBCALLS-NEXT:    cincoffset a1, sp, 12
+; PURECAP-LIBCALLS-NEXT:    csetbounds a1, a1, 4
 ; PURECAP-LIBCALLS-NEXT:    li a3, 4
 ; PURECAP-LIBCALLS-NEXT:    li a4, 2
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_compare_exchange_4
-; PURECAP-LIBCALLS-NEXT:    clw a1, 12(csp)
+; PURECAP-LIBCALLS-NEXT:    clw a1, 12(sp)
 ; PURECAP-LIBCALLS-NEXT:    mv a2, a0
 ; PURECAP-LIBCALLS-NEXT:    mv a0, a1
 ; PURECAP-LIBCALLS-NEXT:    mv a1, a2
-; PURECAP-LIBCALLS-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 32
+; PURECAP-LIBCALLS-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 32
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: test_cmpxchg_weak_i32:
@@ -500,10 +500,10 @@ define { i64, i1 } @test_cmpxchg_weak_i64(ptr addrspace(200) %ptr, i64 %exp, i64
 ; PURECAP-ATOMICS-LABEL: test_cmpxchg_weak_i64:
 ; PURECAP-ATOMICS:       # %bb.0:
 ; PURECAP-ATOMICS-NEXT:  .LBB9_1: # =>This Inner Loop Header: Depth=1
-; PURECAP-ATOMICS-NEXT:    clr.d.aq a3, (ca0)
+; PURECAP-ATOMICS-NEXT:    clr.d.aq a3, (a0)
 ; PURECAP-ATOMICS-NEXT:    bne a3, a1, .LBB9_3
 ; PURECAP-ATOMICS-NEXT:  # %bb.2: # in Loop: Header=BB9_1 Depth=1
-; PURECAP-ATOMICS-NEXT:    csc.d.rl a4, a2, (ca0)
+; PURECAP-ATOMICS-NEXT:    csc.d.rl a4, a2, (a0)
 ; PURECAP-ATOMICS-NEXT:    bnez a4, .LBB9_1
 ; PURECAP-ATOMICS-NEXT:  .LBB9_3:
 ; PURECAP-ATOMICS-NEXT:    xor a1, a3, a1
@@ -513,20 +513,20 @@ define { i64, i1 } @test_cmpxchg_weak_i64(ptr addrspace(200) %ptr, i64 %exp, i64
 ;
 ; PURECAP-LIBCALLS-LABEL: test_cmpxchg_weak_i64:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -32
-; PURECAP-LIBCALLS-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csd a1, 8(csp)
-; PURECAP-LIBCALLS-NEXT:    cincoffset ca1, csp, 8
-; PURECAP-LIBCALLS-NEXT:    csetbounds ca1, ca1, 8
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -32
+; PURECAP-LIBCALLS-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csd a1, 8(sp)
+; PURECAP-LIBCALLS-NEXT:    cincoffset a1, sp, 8
+; PURECAP-LIBCALLS-NEXT:    csetbounds a1, a1, 8
 ; PURECAP-LIBCALLS-NEXT:    li a3, 4
 ; PURECAP-LIBCALLS-NEXT:    li a4, 2
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_compare_exchange_8
-; PURECAP-LIBCALLS-NEXT:    cld a1, 8(csp)
+; PURECAP-LIBCALLS-NEXT:    cld a1, 8(sp)
 ; PURECAP-LIBCALLS-NEXT:    mv a2, a0
 ; PURECAP-LIBCALLS-NEXT:    mv a0, a1
 ; PURECAP-LIBCALLS-NEXT:    mv a1, a2
-; PURECAP-LIBCALLS-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 32
+; PURECAP-LIBCALLS-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 32
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: test_cmpxchg_weak_i64:
@@ -553,47 +553,47 @@ define { ptr addrspace(200), i1 } @test_cmpxchg_weak_cap(ptr addrspace(200) %ptr
 ; PURECAP-ATOMICS-LABEL: test_cmpxchg_weak_cap:
 ; PURECAP-ATOMICS:       # %bb.0:
 ; PURECAP-ATOMICS-NEXT:  .LBB10_1: # =>This Inner Loop Header: Depth=1
-; PURECAP-ATOMICS-NEXT:    clr.c.aq ca3, (ca0)
+; PURECAP-ATOMICS-NEXT:    clr.c.aq a3, (a0)
 ; PURECAP-ATOMICS-NEXT:    bne a3, a1, .LBB10_3
 ; PURECAP-ATOMICS-NEXT:  # %bb.2: # in Loop: Header=BB10_1 Depth=1
-; PURECAP-ATOMICS-NEXT:    csc.c.aq a4, ca2, (ca0)
+; PURECAP-ATOMICS-NEXT:    csc.c.aq a4, a2, (a0)
 ; PURECAP-ATOMICS-NEXT:    bnez a4, .LBB10_1
 ; PURECAP-ATOMICS-NEXT:  .LBB10_3:
 ; PURECAP-ATOMICS-NEXT:    xor a0, a3, a1
 ; PURECAP-ATOMICS-NEXT:    seqz a1, a0
-; PURECAP-ATOMICS-NEXT:    cmove ca0, ca3
+; PURECAP-ATOMICS-NEXT:    cmove a0, a3
 ; PURECAP-ATOMICS-NEXT:    cret
 ;
 ; PURECAP-LIBCALLS-LABEL: test_cmpxchg_weak_cap:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -32
-; PURECAP-LIBCALLS-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc ca1, 0(csp)
-; PURECAP-LIBCALLS-NEXT:    cincoffset ca1, csp, 0
-; PURECAP-LIBCALLS-NEXT:    csetbounds ca1, ca1, 16
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -32
+; PURECAP-LIBCALLS-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc a1, 0(sp)
+; PURECAP-LIBCALLS-NEXT:    cincoffset a1, sp, 0
+; PURECAP-LIBCALLS-NEXT:    csetbounds a1, a1, 16
 ; PURECAP-LIBCALLS-NEXT:    li a3, 4
 ; PURECAP-LIBCALLS-NEXT:    li a4, 2
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_compare_exchange_cap
-; PURECAP-LIBCALLS-NEXT:    clc ca1, 0(csp)
+; PURECAP-LIBCALLS-NEXT:    clc a1, 0(sp)
 ; PURECAP-LIBCALLS-NEXT:    mv a2, a0
-; PURECAP-LIBCALLS-NEXT:    cmove ca0, ca1
+; PURECAP-LIBCALLS-NEXT:    cmove a0, a1
 ; PURECAP-LIBCALLS-NEXT:    mv a1, a2
-; PURECAP-LIBCALLS-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 32
+; PURECAP-LIBCALLS-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 32
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: test_cmpxchg_weak_cap:
 ; HYBRID:       # %bb.0:
 ; HYBRID-NEXT:    addi sp, sp, -32
 ; HYBRID-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
-; HYBRID-NEXT:    sc ca1, 0(sp)
+; HYBRID-NEXT:    sc a1, 0(sp)
 ; HYBRID-NEXT:    mv a1, sp
 ; HYBRID-NEXT:    li a3, 4
 ; HYBRID-NEXT:    li a4, 2
 ; HYBRID-NEXT:    call __atomic_compare_exchange_cap_c
-; HYBRID-NEXT:    lc ca1, 0(sp)
+; HYBRID-NEXT:    lc a1, 0(sp)
 ; HYBRID-NEXT:    mv a2, a0
-; HYBRID-NEXT:    cmove ca0, ca1
+; HYBRID-NEXT:    cmove a0, a1
 ; HYBRID-NEXT:    mv a1, a2
 ; HYBRID-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; HYBRID-NEXT:    addi sp, sp, 32
@@ -606,47 +606,47 @@ define { ptr addrspace(200), i1 } @test_cmpxchg_weak_cap_i32(ptr addrspace(200)
 ; PURECAP-ATOMICS-LABEL: test_cmpxchg_weak_cap_i32:
 ; PURECAP-ATOMICS:       # %bb.0:
 ; PURECAP-ATOMICS-NEXT:  .LBB11_1: # =>This Inner Loop Header: Depth=1
-; PURECAP-ATOMICS-NEXT:    clr.c.aq ca3, (ca0)
+; PURECAP-ATOMICS-NEXT:    clr.c.aq a3, (a0)
 ; PURECAP-ATOMICS-NEXT:    bne a3, a1, .LBB11_3
 ; PURECAP-ATOMICS-NEXT:  # %bb.2: # in Loop: Header=BB11_1 Depth=1
-; PURECAP-ATOMICS-NEXT:    csc.c.aq a4, ca2, (ca0)
+; PURECAP-ATOMICS-NEXT:    csc.c.aq a4, a2, (a0)
 ; PURECAP-ATOMICS-NEXT:    bnez a4, .LBB11_1
 ; PURECAP-ATOMICS-NEXT:  .LBB11_3:
 ; PURECAP-ATOMICS-NEXT:    xor a0, a3, a1
 ; PURECAP-ATOMICS-NEXT:    seqz a1, a0
-; PURECAP-ATOMICS-NEXT:    cmove ca0, ca3
+; PURECAP-ATOMICS-NEXT:    cmove a0, a3
 ; PURECAP-ATOMICS-NEXT:    cret
 ;
 ; PURECAP-LIBCALLS-LABEL: test_cmpxchg_weak_cap_i32:
 ; PURECAP-LIBCALLS:       # %bb.0:
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, -32
-; PURECAP-LIBCALLS-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; PURECAP-LIBCALLS-NEXT:    csc ca1, 0(csp)
-; PURECAP-LIBCALLS-NEXT:    cincoffset ca1, csp, 0
-; PURECAP-LIBCALLS-NEXT:    csetbounds ca1, ca1, 16
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, -32
+; PURECAP-LIBCALLS-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; PURECAP-LIBCALLS-NEXT:    csc a1, 0(sp)
+; PURECAP-LIBCALLS-NEXT:    cincoffset a1, sp, 0
+; PURECAP-LIBCALLS-NEXT:    csetbounds a1, a1, 16
 ; PURECAP-LIBCALLS-NEXT:    li a3, 4
 ; PURECAP-LIBCALLS-NEXT:    li a4, 2
 ; PURECAP-LIBCALLS-NEXT:    ccall __atomic_compare_exchange_cap
-; PURECAP-LIBCALLS-NEXT:    clc ca1, 0(csp)
+; PURECAP-LIBCALLS-NEXT:    clc a1, 0(sp)
 ; PURECAP-LIBCALLS-NEXT:    mv a2, a0
-; PURECAP-LIBCALLS-NEXT:    cmove ca0, ca1
+; PURECAP-LIBCALLS-NEXT:    cmove a0, a1
 ; PURECAP-LIBCALLS-NEXT:    mv a1, a2
-; PURECAP-LIBCALLS-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; PURECAP-LIBCALLS-NEXT:    cincoffset csp, csp, 32
+; PURECAP-LIBCALLS-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; PURECAP-LIBCALLS-NEXT:    cincoffset sp, sp, 32
 ; PURECAP-LIBCALLS-NEXT:    cret
 ;
 ; HYBRID-LABEL: test_cmpxchg_weak_cap_i32:
 ; HYBRID:       # %bb.0:
 ; HYBRID-NEXT:    addi sp, sp, -32
 ; HYBRID-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
-; HYBRID-NEXT:    sc ca1, 0(sp)
+; HYBRID-NEXT:    sc a1, 0(sp)
 ; HYBRID-NEXT:    mv a1, sp
 ; HYBRID-NEXT:    li a3, 4
 ; HYBRID-NEXT:    li a4, 2
 ; HYBRID-NEXT:    call __atomic_compare_exchange_cap_c
-; HYBRID-NEXT:    lc ca1, 0(sp)
+; HYBRID-NEXT:    lc a1, 0(sp)
 ; HYBRID-NEXT:    mv a2, a0
-; HYBRID-NEXT:    cmove ca0, ca1
+; HYBRID-NEXT:    cmove a0, a1
 ; HYBRID-NEXT:    mv a1, a2
 ; HYBRID-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; HYBRID-NEXT:    addi sp, sp, 32
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/dagcombine-ptradd-deleted-regression.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/dagcombine-ptradd-deleted-regression.ll
index 4b0c3f6e6c579..b329d6607d406 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/dagcombine-ptradd-deleted-regression.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/dagcombine-ptradd-deleted-regression.ll
@@ -14,23 +14,23 @@ define internal i32 @foo(i32 addrspace(200)* %a, i64 addrspace(200)* %b) nounwin
 ; HYBRID:       # %bb.0: # %entry
 ; HYBRID-NEXT:    addi sp, sp, -32
 ; HYBRID-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
-; HYBRID-NEXT:    cincoffset ca0, ca0, 4
-; HYBRID-NEXT:    sc ca0, 0(sp) # 16-byte Folded Spill
+; HYBRID-NEXT:    cincoffset a0, a0, 4
+; HYBRID-NEXT:    sc a0, 0(sp) # 16-byte Folded Spill
 ; HYBRID-NEXT:  .LBB0_1: # %loop
 ; HYBRID-NEXT:    # =>This Inner Loop Header: Depth=1
-; HYBRID-NEXT:    lc ca0, 0(sp) # 16-byte Folded Reload
+; HYBRID-NEXT:    lc a0, 0(sp) # 16-byte Folded Reload
 ; HYBRID-NEXT:    call bar
 ; HYBRID-NEXT:    j .LBB0_1
 ;
 ; PURECAP-LABEL: foo:
 ; PURECAP:       # %bb.0: # %entry
-; PURECAP-NEXT:    cincoffset csp, csp, -32
-; PURECAP-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; PURECAP-NEXT:    csc cs0, 0(csp) # 16-byte Folded Spill
-; PURECAP-NEXT:    cincoffset cs0, ca0, 4
+; PURECAP-NEXT:    cincoffset sp, sp, -32
+; PURECAP-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; PURECAP-NEXT:    csc s0, 0(sp) # 16-byte Folded Spill
+; PURECAP-NEXT:    cincoffset s0, a0, 4
 ; PURECAP-NEXT:  .LBB0_1: # %loop
 ; PURECAP-NEXT:    # =>This Inner Loop Header: Depth=1
-; PURECAP-NEXT:    cmove ca0, cs0
+; PURECAP-NEXT:    cmove a0, s0
 ; PURECAP-NEXT:    ccall bar
 ; PURECAP-NEXT:    j .LBB0_1
 entry:
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/frameindex-arith.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/frameindex-arith.ll
index 3bea36d98ea4c..df5fc50ee467a 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/frameindex-arith.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/frameindex-arith.ll
@@ -11,13 +11,13 @@
 define void @foo() nounwind {
 ; CHECK-LABEL: foo:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    cincoffset csp, csp, -32
-; CHECK-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; CHECK-NEXT:    cincoffset ca0, csp, 15
-; CHECK-NEXT:    csetbounds ca0, ca0, 0
+; CHECK-NEXT:    cincoffset sp, sp, -32
+; CHECK-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; CHECK-NEXT:    cincoffset a0, sp, 15
+; CHECK-NEXT:    csetbounds a0, a0, 0
 ; CHECK-NEXT:    ccall bar
-; CHECK-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; CHECK-NEXT:    cincoffset csp, csp, 32
+; CHECK-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; CHECK-NEXT:    cincoffset sp, sp, 32
 ; CHECK-NEXT:    cret
   %x = alloca [2 x i8], align 1, addrspace(200)
   %x_plus_1 = getelementptr inbounds [2 x i8], [2 x i8] addrspace(200)* %x, i64 0, i64 1
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/gvn-capability-store-to-load-fwd.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/gvn-capability-store-to-load-fwd.ll
index 8f29ad64e83f9..ce5bf7797ec29 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/gvn-capability-store-to-load-fwd.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/gvn-capability-store-to-load-fwd.ll
@@ -24,10 +24,10 @@ target datalayout = "e-m:e-pf200:128:128:128:64-p:64:64-i64:64-i128:128-n64-S128
 define i32 @first_i32_store_to_load_fwd(ptr addrspace(200) %arg) local_unnamed_addr addrspace(200) nounwind {
 ; ASM-LABEL: first_i32_store_to_load_fwd:
 ; ASM:       # %bb.0:
-; ASM-NEXT:    cincoffset csp, csp, -80
-; ASM-NEXT:    csc ca0, 0(csp)
-; ASM-NEXT:    clw a0, 0(csp)
-; ASM-NEXT:    cincoffset csp, csp, 80
+; ASM-NEXT:    cincoffset sp, sp, -80
+; ASM-NEXT:    csc a0, 0(sp)
+; ASM-NEXT:    clw a0, 0(sp)
+; ASM-NEXT:    cincoffset sp, sp, 80
 ; ASM-NEXT:    cret
 ; CHECK-LABEL: define i32 @first_i32_store_to_load_fwd
 ; CHECK-SAME: (ptr addrspace(200) [[ARG:%.*]]) local_unnamed_addr addrspace(200) #[[ATTR0:[0-9]+]] {
@@ -46,10 +46,10 @@ define i32 @first_i32_store_to_load_fwd(ptr addrspace(200) %arg) local_unnamed_a
 define i32 @second_i32_store_to_load_fwd(ptr addrspace(200) %arg) local_unnamed_addr addrspace(200) nounwind {
 ; ASM-LABEL: second_i32_store_to_load_fwd:
 ; ASM:       # %bb.0:
-; ASM-NEXT:    cincoffset csp, csp, -80
-; ASM-NEXT:    csc ca0, 0(csp)
-; ASM-NEXT:    clw a0, 4(csp)
-; ASM-NEXT:    cincoffset csp, csp, 80
+; ASM-NEXT:    cincoffset sp, sp, -80
+; ASM-NEXT:    csc a0, 0(sp)
+; ASM-NEXT:    clw a0, 4(sp)
+; ASM-NEXT:    cincoffset sp, sp, 80
 ; ASM-NEXT:    cret
 ; CHECK-LABEL: define i32 @second_i32_store_to_load_fwd
 ; CHECK-SAME: (ptr addrspace(200) [[ARG:%.*]]) local_unnamed_addr addrspace(200) #[[ATTR0]] {
@@ -69,10 +69,10 @@ define i32 @second_i32_store_to_load_fwd(ptr addrspace(200) %arg) local_unnamed_
 define i32 @third_i32_store_to_load_fwd(ptr addrspace(200) %arg) local_unnamed_addr addrspace(200) nounwind {
 ; ASM-LABEL: third_i32_store_to_load_fwd:
 ; ASM:       # %bb.0:
-; ASM-NEXT:    cincoffset csp, csp, -80
-; ASM-NEXT:    csc ca0, 0(csp)
-; ASM-NEXT:    clw a0, 8(csp)
-; ASM-NEXT:    cincoffset csp, csp, 80
+; ASM-NEXT:    cincoffset sp, sp, -80
+; ASM-NEXT:    csc a0, 0(sp)
+; ASM-NEXT:    clw a0, 8(sp)
+; ASM-NEXT:    cincoffset sp, sp, 80
 ; ASM-NEXT:    cret
 ; CHECK-LABEL: define i32 @third_i32_store_to_load_fwd
 ; CHECK-SAME: (ptr addrspace(200) [[ARG:%.*]]) local_unnamed_addr addrspace(200) #[[ATTR0]] {
@@ -92,10 +92,10 @@ define i32 @third_i32_store_to_load_fwd(ptr addrspace(200) %arg) local_unnamed_a
 define i32 @fourth_i32_store_to_load_fwd(ptr addrspace(200) %arg) local_unnamed_addr addrspace(200) nounwind {
 ; ASM-LABEL: fourth_i32_store_to_load_fwd:
 ; ASM:       # %bb.0:
-; ASM-NEXT:    cincoffset csp, csp, -80
-; ASM-NEXT:    csc ca0, 0(csp)
-; ASM-NEXT:    clw a0, 12(csp)
-; ASM-NEXT:    cincoffset csp, csp, 80
+; ASM-NEXT:    cincoffset sp, sp, -80
+; ASM-NEXT:    csc a0, 0(sp)
+; ASM-NEXT:    clw a0, 12(sp)
+; ASM-NEXT:    cincoffset sp, sp, 80
 ; ASM-NEXT:    cret
 ; CHECK-LABEL: define i32 @fourth_i32_store_to_load_fwd
 ; CHECK-SAME: (ptr addrspace(200) [[ARG:%.*]]) local_unnamed_addr addrspace(200) #[[ATTR0]] {
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/hoist-alloca.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/hoist-alloca.ll
index b16c202ea2f40..bf6a2dfd9e629 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/hoist-alloca.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/hoist-alloca.ll
@@ -34,22 +34,22 @@
 ; RUN: FileCheck --input-file=%t.dbg --check-prefix=MACHINELICM-DBG %s
 ; Check that MachineLICM hoists the CheriBoundedStackPseudoImm (MIPS) / IncOffset+SetBoundsImm (RISCV) instructions
 ; MACHINELICM-DBG-LABEL: ******** Pre-regalloc Machine LICM: hoist_alloca_uncond
-; MACHINELICM-DBG: Hoisting [[INC:%[0-9]+]]:gpcr = CIncOffsetImm %stack.0.buf1, 0
+; MACHINELICM-DBG: Hoisting [[INC:%[0-9]+]]:ygpr = CIncOffsetImm %stack.0.buf1, 0
 ; MACHINELICM-DBG-NEXT:  from %bb.2 to %bb.0
-; MACHINELICM-DBG: Hoisting [[BOUNDS:%[0-9]+]]:gpcr = CSetBoundsImm [[INC]]:gpcr, 492
+; MACHINELICM-DBG: Hoisting [[BOUNDS:%[0-9]+]]:ygpr = CSetBoundsImm [[INC]]:ygpr, 492
 ; MACHINELICM-DBG-NEXT:  from %bb.2 to %bb.0
-; MACHINELICM-DBG: Hoisting [[INC:%[0-9]+]]:gpcr = CIncOffsetImm %stack.1.buf2, 0
+; MACHINELICM-DBG: Hoisting [[INC:%[0-9]+]]:ygpr = CIncOffsetImm %stack.1.buf2, 0
 ; MACHINELICM-DBG-NEXT:  from %bb.2 to %bb.0
-; MACHINELICM-DBG: Hoisting [[BOUNDS:%[0-9]+]]:gpcr = CSetBoundsImm [[INC]]:gpcr, 88
+; MACHINELICM-DBG: Hoisting [[BOUNDS:%[0-9]+]]:ygpr = CSetBoundsImm [[INC]]:ygpr, 88
 ; MACHINELICM-DBG-NEXT:  from %bb.2 to %bb.0
 ; MACHINELICM-DBG-LABEL: ******** Pre-regalloc Machine LICM: hoist_alloca_cond
-; MACHINELICM-DBG: Hoisting [[INC:%[0-9]+]]:gpcr = CIncOffsetImm %stack.0.buf1, 0
+; MACHINELICM-DBG: Hoisting [[INC:%[0-9]+]]:ygpr = CIncOffsetImm %stack.0.buf1, 0
 ; MACHINELICM-DBG-NEXT:  from %bb.3 to %bb.0
-; MACHINELICM-DBG: Hoisting [[BOUNDS:%[0-9]+]]:gpcr = CSetBoundsImm [[INC]]:gpcr, 492
+; MACHINELICM-DBG: Hoisting [[BOUNDS:%[0-9]+]]:ygpr = CSetBoundsImm [[INC]]:ygpr, 492
 ; MACHINELICM-DBG-NEXT:  from %bb.3 to %bb.0
-; MACHINELICM-DBG: Hoisting [[INC:%[0-9]+]]:gpcr = CIncOffsetImm %stack.1.buf2, 0
+; MACHINELICM-DBG: Hoisting [[INC:%[0-9]+]]:ygpr = CIncOffsetImm %stack.1.buf2, 0
 ; MACHINELICM-DBG-NEXT:  from %bb.3 to %bb.0
-; MACHINELICM-DBG: Hoisting [[BOUNDS:%[0-9]+]]:gpcr = CSetBoundsImm [[INC]]:gpcr, 88
+; MACHINELICM-DBG: Hoisting [[BOUNDS:%[0-9]+]]:ygpr = CSetBoundsImm [[INC]]:ygpr, 88
 ; MACHINELICM-DBG-NEXT:  from %bb.3 to %bb.0
 
 ; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+xcheripurecap,+f,+d -O1 -o - < %s | FileCheck %s
@@ -57,29 +57,29 @@
 define void @hoist_alloca_uncond(i32 signext %cond) local_unnamed_addr addrspace(200) nounwind {
 ; CHECK-LABEL: hoist_alloca_uncond:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    cincoffset csp, csp, -656
-; CHECK-NEXT:    csc cra, 640(csp) # 16-byte Folded Spill
-; CHECK-NEXT:    csc cs0, 624(csp) # 16-byte Folded Spill
-; CHECK-NEXT:    csc cs1, 608(csp) # 16-byte Folded Spill
-; CHECK-NEXT:    csc cs2, 592(csp) # 16-byte Folded Spill
+; CHECK-NEXT:    cincoffset sp, sp, -656
+; CHECK-NEXT:    csc ra, 640(sp) # 16-byte Folded Spill
+; CHECK-NEXT:    csc s0, 624(sp) # 16-byte Folded Spill
+; CHECK-NEXT:    csc s1, 608(sp) # 16-byte Folded Spill
+; CHECK-NEXT:    csc s2, 592(sp) # 16-byte Folded Spill
 ; CHECK-NEXT:    li s2, 100
-; CHECK-NEXT:    cincoffset ca0, csp, 100
-; CHECK-NEXT:    cincoffset ca1, csp, 12
-; CHECK-NEXT:    csetbounds cs0, ca0, 492
-; CHECK-NEXT:    csetbounds cs1, ca1, 88
+; CHECK-NEXT:    cincoffset a0, sp, 100
+; CHECK-NEXT:    cincoffset a1, sp, 12
+; CHECK-NEXT:    csetbounds s0, a0, 492
+; CHECK-NEXT:    csetbounds s1, a1, 88
 ; CHECK-NEXT:  .LBB0_1: # %for.body
 ; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT:    cmove ca0, cs0
-; CHECK-NEXT:    cmove ca1, cs1
+; CHECK-NEXT:    cmove a0, s0
+; CHECK-NEXT:    cmove a1, s1
 ; CHECK-NEXT:    ccall call
 ; CHECK-NEXT:    addiw s2, s2, -1
 ; CHECK-NEXT:    bnez s2, .LBB0_1
 ; CHECK-NEXT:  # %bb.2: # %for.cond.cleanup
-; CHECK-NEXT:    clc cra, 640(csp) # 16-byte Folded Reload
-; CHECK-NEXT:    clc cs0, 624(csp) # 16-byte Folded Reload
-; CHECK-NEXT:    clc cs1, 608(csp) # 16-byte Folded Reload
-; CHECK-NEXT:    clc cs2, 592(csp) # 16-byte Folded Reload
-; CHECK-NEXT:    cincoffset csp, csp, 656
+; CHECK-NEXT:    clc ra, 640(sp) # 16-byte Folded Reload
+; CHECK-NEXT:    clc s0, 624(sp) # 16-byte Folded Reload
+; CHECK-NEXT:    clc s1, 608(sp) # 16-byte Folded Reload
+; CHECK-NEXT:    clc s2, 592(sp) # 16-byte Folded Reload
+; CHECK-NEXT:    cincoffset sp, sp, 656
 ; CHECK-NEXT:    cret
 entry:
   %buf1 = alloca [123 x i32], align 4, addrspace(200)
@@ -104,18 +104,18 @@ declare void @call(i32 addrspace(200)*, i32 addrspace(200)*) local_unnamed_addr
 define void @hoist_alloca_cond(i32 signext %cond) local_unnamed_addr addrspace(200) nounwind {
 ; CHECK-LABEL: hoist_alloca_cond:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    cincoffset csp, csp, -672
-; CHECK-NEXT:    csc cra, 656(csp) # 16-byte Folded Spill
-; CHECK-NEXT:    csc cs0, 640(csp) # 16-byte Folded Spill
-; CHECK-NEXT:    csc cs1, 624(csp) # 16-byte Folded Spill
-; CHECK-NEXT:    csc cs2, 608(csp) # 16-byte Folded Spill
-; CHECK-NEXT:    csc cs3, 592(csp) # 16-byte Folded Spill
+; CHECK-NEXT:    cincoffset sp, sp, -672
+; CHECK-NEXT:    csc ra, 656(sp) # 16-byte Folded Spill
+; CHECK-NEXT:    csc s0, 640(sp) # 16-byte Folded Spill
+; CHECK-NEXT:    csc s1, 624(sp) # 16-byte Folded Spill
+; CHECK-NEXT:    csc s2, 608(sp) # 16-byte Folded Spill
+; CHECK-NEXT:    csc s3, 592(sp) # 16-byte Folded Spill
 ; CHECK-NEXT:    mv s0, a0
 ; CHECK-NEXT:    li s3, 100
-; CHECK-NEXT:    cincoffset ca0, csp, 100
-; CHECK-NEXT:    cincoffset ca1, csp, 12
-; CHECK-NEXT:    csetbounds cs2, ca0, 492
-; CHECK-NEXT:    csetbounds cs1, ca1, 88
+; CHECK-NEXT:    cincoffset a0, sp, 100
+; CHECK-NEXT:    cincoffset a1, sp, 12
+; CHECK-NEXT:    csetbounds s1, a0, 492
+; CHECK-NEXT:    csetbounds s2, a1, 88
 ; CHECK-NEXT:    j .LBB1_2
 ; CHECK-NEXT:  .LBB1_1: # %for.inc
 ; CHECK-NEXT:    # in Loop: Header=BB1_2 Depth=1
@@ -126,17 +126,17 @@ define void @hoist_alloca_cond(i32 signext %cond) local_unnamed_addr addrspace(2
 ; CHECK-NEXT:    beqz s0, .LBB1_1
 ; CHECK-NEXT:  # %bb.3: # %if.then
 ; CHECK-NEXT:    # in Loop: Header=BB1_2 Depth=1
-; CHECK-NEXT:    cmove ca0, cs2
-; CHECK-NEXT:    cmove ca1, cs1
+; CHECK-NEXT:    cmove a0, s1
+; CHECK-NEXT:    cmove a1, s2
 ; CHECK-NEXT:    ccall call
 ; CHECK-NEXT:    j .LBB1_1
 ; CHECK-NEXT:  .LBB1_4: # %for.cond.cleanup
-; CHECK-NEXT:    clc cra, 656(csp) # 16-byte Folded Reload
-; CHECK-NEXT:    clc cs0, 640(csp) # 16-byte Folded Reload
-; CHECK-NEXT:    clc cs1, 624(csp) # 16-byte Folded Reload
-; CHECK-NEXT:    clc cs2, 608(csp) # 16-byte Folded Reload
-; CHECK-NEXT:    clc cs3, 592(csp) # 16-byte Folded Reload
-; CHECK-NEXT:    cincoffset csp, csp, 672
+; CHECK-NEXT:    clc ra, 656(sp) # 16-byte Folded Reload
+; CHECK-NEXT:    clc s0, 640(sp) # 16-byte Folded Reload
+; CHECK-NEXT:    clc s1, 624(sp) # 16-byte Folded Reload
+; CHECK-NEXT:    clc s2, 608(sp) # 16-byte Folded Reload
+; CHECK-NEXT:    clc s3, 592(sp) # 16-byte Folded Reload
+; CHECK-NEXT:    cincoffset sp, sp, 672
 ; CHECK-NEXT:    cret
 entry:
   %buf1 = alloca [123 x i32], align 4, addrspace(200)
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/intrinsics-purecap-only.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/intrinsics-purecap-only.ll
index 34e69b3cbf827..f2444c8b1c79e 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/intrinsics-purecap-only.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/intrinsics-purecap-only.ll
@@ -10,7 +10,7 @@ declare i8 addrspace(200)* @llvm.cheri.stack.cap.get()
 define i8 addrspace(200)* @stack_get() nounwind {
 ; PURECAP-LABEL: stack_get:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    cmove ca0, csp
+; PURECAP-NEXT:    cmove a0, sp
 ; PURECAP-NEXT:    cret
   %cap = call i8 addrspace(200)* @llvm.cheri.stack.cap.get()
   ret i8 addrspace(200)* %cap
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/intrinsics.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/intrinsics.ll
index 2f382347f19e4..8655c48bdbdd8 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/intrinsics.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/intrinsics.ll
@@ -23,12 +23,12 @@ declare i64 @llvm.cheri.cap.high.get.i64(i8 addrspace(200)*)
 define i64 @perms_get(i8 addrspace(200)* %cap) nounwind {
 ; PURECAP-LABEL: perms_get:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    cgetperm a0, ca0
+; PURECAP-NEXT:    cgetperm a0, a0
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: perms_get:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    cgetperm a0, ca0
+; HYBRID-NEXT:    cgetperm a0, a0
 ; HYBRID-NEXT:    ret
   %perms = call i64 @llvm.cheri.cap.perms.get.i64(i8 addrspace(200)* %cap)
   ret i64 %perms
@@ -37,12 +37,12 @@ define i64 @perms_get(i8 addrspace(200)* %cap) nounwind {
 define i64 @type_get(i8 addrspace(200)* %cap) nounwind {
 ; PURECAP-LABEL: type_get:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    cgettype a0, ca0
+; PURECAP-NEXT:    cgettype a0, a0
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: type_get:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    cgettype a0, ca0
+; HYBRID-NEXT:    cgettype a0, a0
 ; HYBRID-NEXT:    ret
   %type = call i64 @llvm.cheri.cap.type.get.i64(i8 addrspace(200)* %cap)
   ret i64 %type
@@ -51,12 +51,12 @@ define i64 @type_get(i8 addrspace(200)* %cap) nounwind {
 define i64 @base_get(i8 addrspace(200)* %cap) nounwind {
 ; PURECAP-LABEL: base_get:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    cgetbase a0, ca0
+; PURECAP-NEXT:    cgetbase a0, a0
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: base_get:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    cgetbase a0, ca0
+; HYBRID-NEXT:    cgetbase a0, a0
 ; HYBRID-NEXT:    ret
   %base = call i64 @llvm.cheri.cap.base.get.i64(i8 addrspace(200)* %cap)
   ret i64 %base
@@ -65,12 +65,12 @@ define i64 @base_get(i8 addrspace(200)* %cap) nounwind {
 define i64 @length_get(i8 addrspace(200)* %cap) nounwind {
 ; PURECAP-LABEL: length_get:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    cgetlen a0, ca0
+; PURECAP-NEXT:    cgetlen a0, a0
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: length_get:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    cgetlen a0, ca0
+; HYBRID-NEXT:    cgetlen a0, a0
 ; HYBRID-NEXT:    ret
   %length = call i64 @llvm.cheri.cap.length.get.i64(i8 addrspace(200)* %cap)
   ret i64 %length
@@ -79,12 +79,12 @@ define i64 @length_get(i8 addrspace(200)* %cap) nounwind {
 define i64 @tag_get(i8 addrspace(200)* %cap) nounwind {
 ; PURECAP-LABEL: tag_get:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    cgettag a0, ca0
+; PURECAP-NEXT:    cgettag a0, a0
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: tag_get:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    cgettag a0, ca0
+; HYBRID-NEXT:    cgettag a0, a0
 ; HYBRID-NEXT:    ret
   %tag = call i1 @llvm.cheri.cap.tag.get(i8 addrspace(200)* %cap)
   %tag.zext = zext i1 %tag to i64
@@ -94,12 +94,12 @@ define i64 @tag_get(i8 addrspace(200)* %cap) nounwind {
 define i64 @tag_get_temporal(i8 addrspace(200)* %cap) nounwind {
 ; PURECAP-LABEL: tag_get_temporal:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    cgettag a0, ca0
+; PURECAP-NEXT:    cgettag a0, a0
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: tag_get_temporal:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    cgettag a0, ca0
+; HYBRID-NEXT:    cgettag a0, a0
 ; HYBRID-NEXT:    ret
   %tag = call i1 @llvm.cheri.cap.tag.get.temporal(i8 addrspace(200)* %cap)
   %tag.zext = zext i1 %tag to i64
@@ -109,12 +109,12 @@ define i64 @tag_get_temporal(i8 addrspace(200)* %cap) nounwind {
 define i64 @sealed_get(i8 addrspace(200)* %cap) nounwind {
 ; PURECAP-LABEL: sealed_get:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    cgetsealed a0, ca0
+; PURECAP-NEXT:    cgetsealed a0, a0
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: sealed_get:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    cgetsealed a0, ca0
+; HYBRID-NEXT:    cgetsealed a0, a0
 ; HYBRID-NEXT:    ret
   %sealed = call i1 @llvm.cheri.cap.sealed.get(i8 addrspace(200)* %cap)
   %sealed.zext = zext i1 %sealed to i64
@@ -124,12 +124,12 @@ define i64 @sealed_get(i8 addrspace(200)* %cap) nounwind {
 define i64 @offset_get(i8 addrspace(200)* %cap) nounwind {
 ; PURECAP-LABEL: offset_get:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    cgetoffset a0, ca0
+; PURECAP-NEXT:    cgetoffset a0, a0
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: offset_get:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    cgetoffset a0, ca0
+; HYBRID-NEXT:    cgetoffset a0, a0
 ; HYBRID-NEXT:    ret
   %offset = call i64 @llvm.cheri.cap.offset.get.i64(i8 addrspace(200)* %cap)
   ret i64 %offset
@@ -138,12 +138,12 @@ define i64 @offset_get(i8 addrspace(200)* %cap) nounwind {
 define i64 @flags_get(i8 addrspace(200)* %cap) nounwind {
 ; PURECAP-LABEL: flags_get:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    cgetflags a0, ca0
+; PURECAP-NEXT:    cgetflags a0, a0
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: flags_get:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    cgetflags a0, ca0
+; HYBRID-NEXT:    cgetflags a0, a0
 ; HYBRID-NEXT:    ret
   %flags = call i64 @llvm.cheri.cap.flags.get.i64(i8 addrspace(200)* %cap)
   ret i64 %flags
@@ -166,12 +166,12 @@ define i64 @address_get(i8 addrspace(200)* %cap) nounwind {
 define i64 @high_get(i8 addrspace(200)* %cap) nounwind {
 ; PURECAP-LABEL: high_get:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    cgethigh a0, ca0
+; PURECAP-NEXT:    cgethigh a0, a0
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: high_get:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    cgethigh a0, ca0
+; HYBRID-NEXT:    cgethigh a0, a0
 ; HYBRID-NEXT:    ret
   %high = call i64 @llvm.cheri.cap.high.get.i64(i8 addrspace(200)* %cap)
   ret i64 %high
@@ -197,12 +197,12 @@ declare i8 addrspace(200)* @llvm.cheri.cap.seal.entry(i8 addrspace(200)*)
 define i8 addrspace(200)* @seal(i8 addrspace(200)* %cap1, i8 addrspace(200)* %cap2) nounwind {
 ; PURECAP-LABEL: seal:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    cseal ca0, ca0, ca1
+; PURECAP-NEXT:    cseal a0, a0, a1
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: seal:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    cseal ca0, ca0, ca1
+; HYBRID-NEXT:    cseal a0, a0, a1
 ; HYBRID-NEXT:    ret
   %sealed = call i8 addrspace(200)* @llvm.cheri.cap.seal(i8 addrspace(200)* %cap1, i8 addrspace(200)* %cap2)
   ret i8 addrspace(200)* %sealed
@@ -211,12 +211,12 @@ define i8 addrspace(200)* @seal(i8 addrspace(200)* %cap1, i8 addrspace(200)* %ca
 define i8 addrspace(200)* @unseal(i8 addrspace(200)* %cap1, i8 addrspace(200)* %cap2) nounwind {
 ; PURECAP-LABEL: unseal:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    cunseal ca0, ca0, ca1
+; PURECAP-NEXT:    cunseal a0, a0, a1
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: unseal:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    cunseal ca0, ca0, ca1
+; HYBRID-NEXT:    cunseal a0, a0, a1
 ; HYBRID-NEXT:    ret
   %unsealed = call i8 addrspace(200)* @llvm.cheri.cap.unseal(i8 addrspace(200)* %cap1, i8 addrspace(200)* %cap2)
   ret i8 addrspace(200)* %unsealed
@@ -225,12 +225,12 @@ define i8 addrspace(200)* @unseal(i8 addrspace(200)* %cap1, i8 addrspace(200)* %
 define i8 addrspace(200)* @perms_and(i8 addrspace(200)* %cap, i64 %perms) nounwind {
 ; PURECAP-LABEL: perms_and:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    candperm ca0, ca0, a1
+; PURECAP-NEXT:    candperm a0, a0, a1
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: perms_and:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    candperm ca0, ca0, a1
+; HYBRID-NEXT:    candperm a0, a0, a1
 ; HYBRID-NEXT:    ret
   %newcap = call i8 addrspace(200)* @llvm.cheri.cap.perms.and.i64(i8 addrspace(200)* %cap, i64 %perms)
   ret i8 addrspace(200)* %newcap
@@ -239,12 +239,12 @@ define i8 addrspace(200)* @perms_and(i8 addrspace(200)* %cap, i64 %perms) nounwi
 define i8 addrspace(200)* @flags_set(i8 addrspace(200)* %cap, i64 %flags) nounwind {
 ; PURECAP-LABEL: flags_set:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    csetflags ca0, ca0, a1
+; PURECAP-NEXT:    csetflags a0, a0, a1
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: flags_set:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    csetflags ca0, ca0, a1
+; HYBRID-NEXT:    csetflags a0, a0, a1
 ; HYBRID-NEXT:    ret
   %newcap = call i8 addrspace(200)* @llvm.cheri.cap.flags.set.i64(i8 addrspace(200)* %cap, i64 %flags)
   ret i8 addrspace(200)* %newcap
@@ -253,12 +253,12 @@ define i8 addrspace(200)* @flags_set(i8 addrspace(200)* %cap, i64 %flags) nounwi
 define i8 addrspace(200)* @offset_set(i8 addrspace(200)* %cap, i64 %offset) nounwind {
 ; PURECAP-LABEL: offset_set:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    csetoffset ca0, ca0, a1
+; PURECAP-NEXT:    csetoffset a0, a0, a1
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: offset_set:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    csetoffset ca0, ca0, a1
+; HYBRID-NEXT:    csetoffset a0, a0, a1
 ; HYBRID-NEXT:    ret
   %newcap = call i8 addrspace(200)* @llvm.cheri.cap.offset.set.i64(i8 addrspace(200)* %cap, i64 %offset)
   ret i8 addrspace(200)* %newcap
@@ -267,12 +267,12 @@ define i8 addrspace(200)* @offset_set(i8 addrspace(200)* %cap, i64 %offset) noun
 define i8 addrspace(200)* @address_set(i8 addrspace(200)* %cap, i64 %address) nounwind {
 ; PURECAP-LABEL: address_set:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    csetaddr ca0, ca0, a1
+; PURECAP-NEXT:    csetaddr a0, a0, a1
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: address_set:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    csetaddr ca0, ca0, a1
+; HYBRID-NEXT:    csetaddr a0, a0, a1
 ; HYBRID-NEXT:    ret
   %newcap = call i8 addrspace(200)* @llvm.cheri.cap.address.set.i64(i8 addrspace(200)* %cap, i64 %address)
   ret i8 addrspace(200)* %newcap
@@ -281,12 +281,12 @@ define i8 addrspace(200)* @address_set(i8 addrspace(200)* %cap, i64 %address) no
 define i8 addrspace(200)* @bounds_set(i8 addrspace(200)* %cap, i64 %bounds) nounwind {
 ; PURECAP-LABEL: bounds_set:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    csetbounds ca0, ca0, a1
+; PURECAP-NEXT:    csetbounds a0, a0, a1
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: bounds_set:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    csetbounds ca0, ca0, a1
+; HYBRID-NEXT:    csetbounds a0, a0, a1
 ; HYBRID-NEXT:    ret
   %newcap = call i8 addrspace(200)* @llvm.cheri.cap.bounds.set.i64(i8 addrspace(200)* %cap, i64 %bounds)
   ret i8 addrspace(200)* %newcap
@@ -295,12 +295,12 @@ define i8 addrspace(200)* @bounds_set(i8 addrspace(200)* %cap, i64 %bounds) noun
 define i8 addrspace(200)* @bounds_set_exact(i8 addrspace(200)* %cap, i64 %bounds) nounwind {
 ; PURECAP-LABEL: bounds_set_exact:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    csetboundsexact ca0, ca0, a1
+; PURECAP-NEXT:    csetboundsexact a0, a0, a1
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: bounds_set_exact:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    csetboundsexact ca0, ca0, a1
+; HYBRID-NEXT:    csetboundsexact a0, a0, a1
 ; HYBRID-NEXT:    ret
   %newcap = call i8 addrspace(200)* @llvm.cheri.cap.bounds.set.exact.i64(i8 addrspace(200)* %cap, i64 %bounds)
   ret i8 addrspace(200)* %newcap
@@ -309,12 +309,12 @@ define i8 addrspace(200)* @bounds_set_exact(i8 addrspace(200)* %cap, i64 %bounds
 define i8 addrspace(200)* @high_set(i8 addrspace(200)* %cap, i64 %high) nounwind {
 ; PURECAP-LABEL: high_set:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    csethigh ca0, ca0, a1
+; PURECAP-NEXT:    csethigh a0, a0, a1
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: high_set:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    csethigh ca0, ca0, a1
+; HYBRID-NEXT:    csethigh a0, a0, a1
 ; HYBRID-NEXT:    ret
   %newcap = call i8 addrspace(200)* @llvm.cheri.cap.high.set.i64(i8 addrspace(200)* %cap, i64 %high)
   ret i8 addrspace(200)* %newcap
@@ -323,12 +323,12 @@ define i8 addrspace(200)* @high_set(i8 addrspace(200)* %cap, i64 %high) nounwind
 define i8 addrspace(200)* @bounds_set_immediate(i8 addrspace(200)* %cap) nounwind {
 ; PURECAP-LABEL: bounds_set_immediate:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    csetbounds ca0, ca0, 42
+; PURECAP-NEXT:    csetbounds a0, a0, 42
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: bounds_set_immediate:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    csetbounds ca0, ca0, 42
+; HYBRID-NEXT:    csetbounds a0, a0, 42
 ; HYBRID-NEXT:    ret
   %newcap = call i8 addrspace(200)* @llvm.cheri.cap.bounds.set.i64(i8 addrspace(200)* %cap, i64 42)
   ret i8 addrspace(200)* %newcap
@@ -337,12 +337,12 @@ define i8 addrspace(200)* @bounds_set_immediate(i8 addrspace(200)* %cap) nounwin
 define i8 addrspace(200)* @tag_clear(i8 addrspace(200)* %cap) nounwind {
 ; PURECAP-LABEL: tag_clear:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    ccleartag ca0, ca0
+; PURECAP-NEXT:    ccleartag a0, a0
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: tag_clear:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    ccleartag ca0, ca0
+; HYBRID-NEXT:    ccleartag a0, a0
 ; HYBRID-NEXT:    ret
   %untagged = call i8 addrspace(200)* @llvm.cheri.cap.tag.clear(i8 addrspace(200)* %cap)
   ret i8 addrspace(200)* %untagged
@@ -351,12 +351,12 @@ define i8 addrspace(200)* @tag_clear(i8 addrspace(200)* %cap) nounwind {
 define i8 addrspace(200)* @build(i8 addrspace(200)* %cap1, i8 addrspace(200)* %cap2) nounwind {
 ; PURECAP-LABEL: build:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    cbuildcap ca0, ca0, ca1
+; PURECAP-NEXT:    cbuildcap a0, a0, a1
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: build:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    cbuildcap ca0, ca0, ca1
+; HYBRID-NEXT:    cbuildcap a0, a0, a1
 ; HYBRID-NEXT:    ret
   %built = call i8 addrspace(200)* @llvm.cheri.cap.build(i8 addrspace(200)* %cap1, i8 addrspace(200)* %cap2)
   ret i8 addrspace(200)* %built
@@ -365,12 +365,12 @@ define i8 addrspace(200)* @build(i8 addrspace(200)* %cap1, i8 addrspace(200)* %c
 define i8 addrspace(200)* @type_copy(i8 addrspace(200)* %cap1, i8 addrspace(200)* %cap2) nounwind {
 ; PURECAP-LABEL: type_copy:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    ccopytype ca0, ca0, ca1
+; PURECAP-NEXT:    ccopytype a0, a0, a1
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: type_copy:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    ccopytype ca0, ca0, ca1
+; HYBRID-NEXT:    ccopytype a0, a0, a1
 ; HYBRID-NEXT:    ret
   %newcap = call i8 addrspace(200)* @llvm.cheri.cap.type.copy(i8 addrspace(200)* %cap1, i8 addrspace(200)* %cap2)
   ret i8 addrspace(200)* %newcap
@@ -379,12 +379,12 @@ define i8 addrspace(200)* @type_copy(i8 addrspace(200)* %cap1, i8 addrspace(200)
 define i8 addrspace(200)* @conditional_seal(i8 addrspace(200)* %cap1, i8 addrspace(200)* %cap2) nounwind {
 ; PURECAP-LABEL: conditional_seal:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    ccseal ca0, ca0, ca1
+; PURECAP-NEXT:    ccseal a0, a0, a1
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: conditional_seal:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    ccseal ca0, ca0, ca1
+; HYBRID-NEXT:    ccseal a0, a0, a1
 ; HYBRID-NEXT:    ret
   %newcap = call i8 addrspace(200)* @llvm.cheri.cap.conditional.seal(i8 addrspace(200)* %cap1, i8 addrspace(200)* %cap2)
   ret i8 addrspace(200)* %newcap
@@ -393,12 +393,12 @@ define i8 addrspace(200)* @conditional_seal(i8 addrspace(200)* %cap1, i8 addrspa
 define i8 addrspace(200)* @seal_entry(i8 addrspace(200)* %cap) nounwind {
 ; PURECAP-LABEL: seal_entry:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    csealentry ca0, ca0
+; PURECAP-NEXT:    csealentry a0, a0
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: seal_entry:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    csealentry ca0, ca0
+; HYBRID-NEXT:    csealentry a0, a0
 ; HYBRID-NEXT:    ret
   %newcap = call i8 addrspace(200)* @llvm.cheri.cap.seal.entry(i8 addrspace(200)* %cap)
   ret i8 addrspace(200)* %newcap
@@ -415,14 +415,14 @@ declare i8 addrspace(200)* @llvm.cheri.pcc.get()
 define i64 @to_pointer(i8 addrspace(200)* %cap1, i8 addrspace(200)* %cap2) nounwind {
 ; PURECAP-LABEL: to_pointer:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    cgettag a0, ca1
+; PURECAP-NEXT:    cgettag a0, a1
 ; PURECAP-NEXT:    neg a0, a0
 ; PURECAP-NEXT:    and a0, a1, a0
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: to_pointer:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    cgettag a0, ca1
+; HYBRID-NEXT:    cgettag a0, a1
 ; HYBRID-NEXT:    neg a0, a0
 ; HYBRID-NEXT:    and a0, a1, a0
 ; HYBRID-NEXT:    ret
@@ -433,14 +433,14 @@ define i64 @to_pointer(i8 addrspace(200)* %cap1, i8 addrspace(200)* %cap2) nounw
 define i64 @to_pointer_ddc_relative(i8 addrspace(200)* %cap) nounwind {
 ; PURECAP-LABEL: to_pointer_ddc_relative:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    cgettag a1, ca0
+; PURECAP-NEXT:    cgettag a1, a0
 ; PURECAP-NEXT:    neg a1, a1
 ; PURECAP-NEXT:    and a0, a0, a1
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: to_pointer_ddc_relative:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    cgettag a1, ca0
+; HYBRID-NEXT:    cgettag a1, a0
 ; HYBRID-NEXT:    neg a1, a1
 ; HYBRID-NEXT:    and a0, a0, a1
 ; HYBRID-NEXT:    ret
@@ -454,20 +454,20 @@ define i8 addrspace(200)* @from_pointer(i8 addrspace(200)* %cap, i64 %ptr) nounw
 ; PURECAP:       # %bb.0:
 ; PURECAP-NEXT:    bnez a1, .LBB28_2
 ; PURECAP-NEXT:  # %bb.1:
-; PURECAP-NEXT:    cmove ca0, cnull
+; PURECAP-NEXT:    cmove a0, zero
 ; PURECAP-NEXT:    cret
 ; PURECAP-NEXT:  .LBB28_2:
-; PURECAP-NEXT:    csetaddr ca0, ca0, a1
+; PURECAP-NEXT:    csetaddr a0, a0, a1
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: from_pointer:
 ; HYBRID:       # %bb.0:
 ; HYBRID-NEXT:    bnez a1, .LBB28_2
 ; HYBRID-NEXT:  # %bb.1:
-; HYBRID-NEXT:    cmove ca0, cnull
+; HYBRID-NEXT:    cmove a0, zero
 ; HYBRID-NEXT:    ret
 ; HYBRID-NEXT:  .LBB28_2:
-; HYBRID-NEXT:    csetaddr ca0, ca0, a1
+; HYBRID-NEXT:    csetaddr a0, a0, a1
 ; HYBRID-NEXT:    ret
   %newcap = call i8 addrspace(200)* @llvm.cheri.cap.from.pointer(i8 addrspace(200)* %cap, i64 %ptr)
   ret i8 addrspace(200)* %newcap
@@ -476,24 +476,24 @@ define i8 addrspace(200)* @from_pointer(i8 addrspace(200)* %cap, i64 %ptr) nounw
 define i8 addrspace(200)* @from_ddc(i64 %ptr) nounwind {
 ; PURECAP-LABEL: from_ddc:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    cspecialr ca1, ddc
+; PURECAP-NEXT:    cspecialr a1, ddc
 ; PURECAP-NEXT:    bnez a0, .LBB29_2
 ; PURECAP-NEXT:  # %bb.1:
-; PURECAP-NEXT:    cmove ca0, cnull
+; PURECAP-NEXT:    cmove a0, zero
 ; PURECAP-NEXT:    cret
 ; PURECAP-NEXT:  .LBB29_2:
-; PURECAP-NEXT:    csetaddr ca0, ca1, a0
+; PURECAP-NEXT:    csetaddr a0, a1, a0
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: from_ddc:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    cspecialr ca1, ddc
+; HYBRID-NEXT:    cspecialr a1, ddc
 ; HYBRID-NEXT:    bnez a0, .LBB29_2
 ; HYBRID-NEXT:  # %bb.1:
-; HYBRID-NEXT:    cmove ca0, cnull
+; HYBRID-NEXT:    cmove a0, zero
 ; HYBRID-NEXT:    ret
 ; HYBRID-NEXT:  .LBB29_2:
-; HYBRID-NEXT:    csetaddr ca0, ca1, a0
+; HYBRID-NEXT:    csetaddr a0, a1, a0
 ; HYBRID-NEXT:    ret
   %ddc = call i8 addrspace(200)* @llvm.cheri.ddc.get()
   %cap = call i8 addrspace(200)* @llvm.cheri.cap.from.pointer(i8 addrspace(200)* %ddc, i64 %ptr)
@@ -517,12 +517,12 @@ define i64 @diff(i8 addrspace(200)* %cap1, i8 addrspace(200)* %cap2) nounwind {
 define i8 addrspace(200)* @ddc_get() nounwind {
 ; PURECAP-LABEL: ddc_get:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    cspecialr ca0, ddc
+; PURECAP-NEXT:    cspecialr a0, ddc
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: ddc_get:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    cspecialr ca0, ddc
+; HYBRID-NEXT:    cspecialr a0, ddc
 ; HYBRID-NEXT:    ret
   %cap = call i8 addrspace(200)* @llvm.cheri.ddc.get()
   ret i8 addrspace(200)* %cap
@@ -531,12 +531,12 @@ define i8 addrspace(200)* @ddc_get() nounwind {
 define i8 addrspace(200)* @pcc_get() nounwind {
 ; PURECAP-LABEL: pcc_get:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    auipcc ca0, 0
+; PURECAP-NEXT:    auipcc a0, 0
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: pcc_get:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    cspecialr ca0, pcc
+; HYBRID-NEXT:    cspecialr a0, pcc
 ; HYBRID-NEXT:    ret
   %cap = call i8 addrspace(200)* @llvm.cheri.pcc.get()
   ret i8 addrspace(200)* %cap
@@ -549,12 +549,12 @@ declare i1 @llvm.cheri.cap.subset.test(i8 addrspace(200)* %cap1, i8 addrspace(20
 define i64 @subset_test(i8 addrspace(200)* %cap1, i8 addrspace(200)* %cap2) nounwind {
 ; PURECAP-LABEL: subset_test:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    ctestsubset a0, ca0, ca1
+; PURECAP-NEXT:    ctestsubset a0, a0, a1
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: subset_test:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    ctestsubset a0, ca0, ca1
+; HYBRID-NEXT:    ctestsubset a0, a0, a1
 ; HYBRID-NEXT:    ret
   %subset = call i1 @llvm.cheri.cap.subset.test(i8 addrspace(200)* %cap1, i8 addrspace(200)* %cap2)
   %subset.zext = zext i1 %subset to i64
@@ -566,12 +566,12 @@ declare i1 @llvm.cheri.cap.equal.exact(i8 addrspace(200)* %cap1, i8 addrspace(20
 define i64 @equal_exact(i8 addrspace(200)* %cap1, i8 addrspace(200)* %cap2) nounwind {
 ; PURECAP-LABEL: equal_exact:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    cseqx a0, ca0, ca1
+; PURECAP-NEXT:    cseqx a0, a0, a1
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: equal_exact:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    cseqx a0, ca0, ca1
+; HYBRID-NEXT:    cseqx a0, a0, a1
 ; HYBRID-NEXT:    ret
   %eqex = call i1 @llvm.cheri.cap.equal.exact(i8 addrspace(200)* %cap1, i8 addrspace(200)* %cap2)
   %eqex.zext = zext i1 %eqex to i64
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/landingpad-non-preemptible.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/landingpad-non-preemptible.ll
index 6ae51d806818d..248dd2035ca9d 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/landingpad-non-preemptible.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/landingpad-non-preemptible.ll
@@ -21,10 +21,10 @@
 define dso_local noundef signext i32 @_Z8do_catchv() local_unnamed_addr addrspace(200) #0 personality ptr addrspace(200) @__gxx_personality_v0 {
 ; CHECK-LABEL: _Z8do_catchv:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    cincoffset csp, csp, -32
+; CHECK-NEXT:    cincoffset sp, sp, -32
 ; CHECK-NEXT:    .cfi_def_cfa_offset 32
-; CHECK-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; CHECK-NEXT:    csc cs0, 0(csp) # 16-byte Folded Spill
+; CHECK-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; CHECK-NEXT:    csc s0, 0(sp) # 16-byte Folded Spill
 ; CHECK-NEXT:    .cfi_offset ra, -16
 ; CHECK-NEXT:    .cfi_offset s0, -32
 ; CHECK-NEXT:    .cfi_remember_state
@@ -32,11 +32,11 @@ define dso_local noundef signext i32 @_Z8do_catchv() local_unnamed_addr addrspac
 ; CHECK-NEXT:    ccall _Z3foov
 ; CHECK-NEXT:  .Ltmp1:
 ; CHECK-NEXT:  .LBB0_1: # %return
-; CHECK-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; CHECK-NEXT:    clc cs0, 0(csp) # 16-byte Folded Reload
+; CHECK-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; CHECK-NEXT:    clc s0, 0(sp) # 16-byte Folded Reload
 ; CHECK-NEXT:    .cfi_restore ra
 ; CHECK-NEXT:    .cfi_restore s0
-; CHECK-NEXT:    cincoffset csp, csp, 32
+; CHECK-NEXT:    cincoffset sp, sp, 32
 ; CHECK-NEXT:    .cfi_def_cfa_offset 0
 ; CHECK-NEXT:    cret
 ; CHECK-NEXT:  .LBB0_2: # %lpad
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/machinelicm-hoist-csetbounds.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/machinelicm-hoist-csetbounds.ll
index 1ae74f27507bc..ca27a8d52a750 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/machinelicm-hoist-csetbounds.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/machinelicm-hoist-csetbounds.ll
@@ -32,19 +32,19 @@ declare ptr addrspace(200) @llvm.cheri.cap.bounds.set.i64(ptr addrspace(200), i6
 define dso_local void @hoist_csetbounds(i32 signext %cond, ptr addrspace(200) %f) local_unnamed_addr addrspace(200) nounwind {
 ; CHECK-LABEL: hoist_csetbounds:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    cincoffset csp, csp, -96
-; CHECK-NEXT:    csc cra, 80(csp) # 16-byte Folded Spill
-; CHECK-NEXT:    csc cs0, 64(csp) # 16-byte Folded Spill
-; CHECK-NEXT:    csc cs1, 48(csp) # 16-byte Folded Spill
-; CHECK-NEXT:    csc cs2, 32(csp) # 16-byte Folded Spill
-; CHECK-NEXT:    csc cs3, 16(csp) # 16-byte Folded Spill
-; CHECK-NEXT:    csc cs4, 0(csp) # 16-byte Folded Spill
-; CHECK-NEXT:    cmove cs0, ca1
-; CHECK-NEXT:    cincoffset ca0, ca1, 4
+; CHECK-NEXT:    cincoffset sp, sp, -96
+; CHECK-NEXT:    csc ra, 80(sp) # 16-byte Folded Spill
+; CHECK-NEXT:    csc s0, 64(sp) # 16-byte Folded Spill
+; CHECK-NEXT:    csc s1, 48(sp) # 16-byte Folded Spill
+; CHECK-NEXT:    csc s2, 32(sp) # 16-byte Folded Spill
+; CHECK-NEXT:    csc s3, 16(sp) # 16-byte Folded Spill
+; CHECK-NEXT:    csc s4, 0(sp) # 16-byte Folded Spill
+; CHECK-NEXT:    cmove s0, a1
+; CHECK-NEXT:    cincoffset a0, a1, 4
 ; CHECK-NEXT:    li s3, -1
 ; CHECK-NEXT:    li s4, 99
-; CHECK-NEXT:    csetbounds cs2, ca1, 4
-; CHECK-NEXT:    csetbounds cs1, ca0, 4
+; CHECK-NEXT:    csetbounds s1, a1, 4
+; CHECK-NEXT:    csetbounds s2, a0, 4
 ; CHECK-NEXT:    j .LBB0_2
 ; CHECK-NEXT:  .LBB0_1: # %for.inc
 ; CHECK-NEXT:    # in Loop: Header=BB0_2 Depth=1
@@ -55,18 +55,18 @@ define dso_local void @hoist_csetbounds(i32 signext %cond, ptr addrspace(200) %f
 ; CHECK-NEXT:    beqz s0, .LBB0_1
 ; CHECK-NEXT:  # %bb.3: # %if.then
 ; CHECK-NEXT:    # in Loop: Header=BB0_2 Depth=1
-; CHECK-NEXT:    cmove ca0, cs2
-; CHECK-NEXT:    cmove ca1, cs1
+; CHECK-NEXT:    cmove a0, s1
+; CHECK-NEXT:    cmove a1, s2
 ; CHECK-NEXT:    ccall call
 ; CHECK-NEXT:    j .LBB0_1
 ; CHECK-NEXT:  .LBB0_4: # %for.cond.cleanup
-; CHECK-NEXT:    clc cra, 80(csp) # 16-byte Folded Reload
-; CHECK-NEXT:    clc cs0, 64(csp) # 16-byte Folded Reload
-; CHECK-NEXT:    clc cs1, 48(csp) # 16-byte Folded Reload
-; CHECK-NEXT:    clc cs2, 32(csp) # 16-byte Folded Reload
-; CHECK-NEXT:    clc cs3, 16(csp) # 16-byte Folded Reload
-; CHECK-NEXT:    clc cs4, 0(csp) # 16-byte Folded Reload
-; CHECK-NEXT:    cincoffset csp, csp, 96
+; CHECK-NEXT:    clc ra, 80(sp) # 16-byte Folded Reload
+; CHECK-NEXT:    clc s0, 64(sp) # 16-byte Folded Reload
+; CHECK-NEXT:    clc s1, 48(sp) # 16-byte Folded Reload
+; CHECK-NEXT:    clc s2, 32(sp) # 16-byte Folded Reload
+; CHECK-NEXT:    clc s3, 16(sp) # 16-byte Folded Reload
+; CHECK-NEXT:    clc s4, 0(sp) # 16-byte Folded Reload
+; CHECK-NEXT:    cincoffset sp, sp, 96
 ; CHECK-NEXT:    cret
 ; HOIST-OPT-LABEL: define dso_local void @hoist_csetbounds
 ; HOIST-OPT-SAME: (i32 signext [[COND:%.*]], ptr addrspace(200) [[F:%.*]]) local_unnamed_addr addrspace(200) #[[ATTR0:[0-9]+]] {
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/memcpy-from-constant.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/memcpy-from-constant.ll
index 90e9c6fbed407..a41d6347e2361 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/memcpy-from-constant.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/memcpy-from-constant.ll
@@ -13,7 +13,7 @@ declare void @llvm.memcpy.p200.p200.i64(ptr addrspace(200) noalias nocapture wri
 define linkonce_odr void @copy_from_zero_constant(ptr addrspace(200) %dst) addrspace(200) {
 ; CHECK-LABEL: copy_from_zero_constant:
 ; CHECK:       # %bb.0: # %do.body
-; CHECK-NEXT:    csc cnull, 0(ca0)
+; CHECK-NEXT:    csc zero, 0(a0)
 ; CHECK-NEXT:    cret
 do.body:
   call void @llvm.memcpy.p200.p200.i64(ptr addrspace(200) align 16 %dst, ptr addrspace(200) align 16 @zero_constant, i64 16, i1 false)
@@ -23,7 +23,7 @@ do.body:
 define linkonce_odr void @copy_from_zero_constant_with_offset(ptr addrspace(200) %dst) addrspace(200) {
 ; CHECK-LABEL: copy_from_zero_constant_with_offset:
 ; CHECK:       # %bb.0: # %do.body
-; CHECK-NEXT:    csc cnull, 0(ca0)
+; CHECK-NEXT:    csc zero, 0(a0)
 ; CHECK-NEXT:    cret
 do.body:
   %src = getelementptr inbounds i8, ptr addrspace(200) @zero_constant, i64 16
@@ -34,7 +34,7 @@ do.body:
 define linkonce_odr void @copy_from_large_zero_constant(ptr addrspace(200) %dst) addrspace(200) {
 ; CHECK-LABEL: copy_from_large_zero_constant:
 ; CHECK:       # %bb.0: # %do.body
-; CHECK-NEXT:    csd zero, 0(ca0)
+; CHECK-NEXT:    csd zero, 0(a0)
 ; CHECK-NEXT:    cret
 do.body:
   call void @llvm.memcpy.p200.p200.i64(ptr addrspace(200) align 16 %dst, ptr addrspace(200) align 16 @zero_constant, i64 8, i1 false)
@@ -46,10 +46,10 @@ define linkonce_odr void @copy_from_ptr_constant(ptr addrspace(200) %dst) addrsp
 ; CHECK:       # %bb.0: # %do.body
 ; CHECK-NEXT:  .LBB3_1: # %do.body
 ; CHECK-NEXT:    # Label of block must be emitted
-; CHECK-NEXT:    auipcc ca1, %captab_pcrel_hi(constant_ptrs)
-; CHECK-NEXT:    clc ca1, %pcrel_lo(.LBB3_1)(ca1)
-; CHECK-NEXT:    clc ca1, 0(ca1)
-; CHECK-NEXT:    csc ca1, 0(ca0)
+; CHECK-NEXT:    auipcc a1, %captab_pcrel_hi(constant_ptrs)
+; CHECK-NEXT:    clc a1, %pcrel_lo(.LBB3_1)(a1)
+; CHECK-NEXT:    clc a1, 0(a1)
+; CHECK-NEXT:    csc a1, 0(a0)
 ; CHECK-NEXT:    cret
 do.body:
   call void @llvm.memcpy.p200.p200.i64(ptr addrspace(200) align 16 %dst, ptr addrspace(200) align 16 @constant_ptrs, i64 16, i1 false)
@@ -61,10 +61,10 @@ define linkonce_odr void @copy_from_ptr_constant_with_offset(ptr addrspace(200)
 ; CHECK:       # %bb.0: # %do.body
 ; CHECK-NEXT:  .LBB4_1: # %do.body
 ; CHECK-NEXT:    # Label of block must be emitted
-; CHECK-NEXT:    auipcc ca1, %captab_pcrel_hi(constant_ptrs)
-; CHECK-NEXT:    clc ca1, %pcrel_lo(.LBB4_1)(ca1)
-; CHECK-NEXT:    clc ca1, 16(ca1)
-; CHECK-NEXT:    csc ca1, 0(ca0)
+; CHECK-NEXT:    auipcc a1, %captab_pcrel_hi(constant_ptrs)
+; CHECK-NEXT:    clc a1, %pcrel_lo(.LBB4_1)(a1)
+; CHECK-NEXT:    clc a1, 16(a1)
+; CHECK-NEXT:    csc a1, 0(a0)
 ; CHECK-NEXT:    cret
 do.body:
   %src = getelementptr inbounds i8, ptr addrspace(200) @constant_ptrs, i64 16
@@ -77,7 +77,7 @@ do.body:
 define linkonce_odr void @copy_from_zero_constant_preserve(ptr addrspace(200) %dst) addrspace(200) {
 ; CHECK-LABEL: copy_from_zero_constant_preserve:
 ; CHECK:       # %bb.0: # %do.body
-; CHECK-NEXT:    csc cnull, 0(ca0)
+; CHECK-NEXT:    csc zero, 0(a0)
 ; CHECK-NEXT:    cret
 do.body:
   call void @llvm.memcpy.p200.p200.i64(ptr addrspace(200) align 16 %dst, ptr addrspace(200) align 16 @zero_constant, i64 16, i1 false) #1
@@ -87,7 +87,7 @@ do.body:
 define linkonce_odr void @copy_from_zero_constant_with_offset_preserve(ptr addrspace(200) %dst) addrspace(200) {
 ; CHECK-LABEL: copy_from_zero_constant_with_offset_preserve:
 ; CHECK:       # %bb.0: # %do.body
-; CHECK-NEXT:    csc cnull, 0(ca0)
+; CHECK-NEXT:    csc zero, 0(a0)
 ; CHECK-NEXT:    cret
 do.body:
   %src = getelementptr inbounds i8, ptr addrspace(200) @zero_constant, i64 16
@@ -98,7 +98,7 @@ do.body:
 define linkonce_odr void @copy_from_large_zero_constant_preserve(ptr addrspace(200) %dst) addrspace(200) {
 ; CHECK-LABEL: copy_from_large_zero_constant_preserve:
 ; CHECK:       # %bb.0: # %do.body
-; CHECK-NEXT:    csd zero, 0(ca0)
+; CHECK-NEXT:    csd zero, 0(a0)
 ; CHECK-NEXT:    cret
 do.body:
   call void @llvm.memcpy.p200.p200.i64(ptr addrspace(200) align 16 %dst, ptr addrspace(200) align 16 @zero_constant, i64 8, i1 false) #1
@@ -110,10 +110,10 @@ define linkonce_odr void @copy_from_ptr_constant_preserve(ptr addrspace(200) %ds
 ; CHECK:       # %bb.0: # %do.body
 ; CHECK-NEXT:  .LBB8_1: # %do.body
 ; CHECK-NEXT:    # Label of block must be emitted
-; CHECK-NEXT:    auipcc ca1, %captab_pcrel_hi(constant_ptrs)
-; CHECK-NEXT:    clc ca1, %pcrel_lo(.LBB8_1)(ca1)
-; CHECK-NEXT:    clc ca1, 0(ca1)
-; CHECK-NEXT:    csc ca1, 0(ca0)
+; CHECK-NEXT:    auipcc a1, %captab_pcrel_hi(constant_ptrs)
+; CHECK-NEXT:    clc a1, %pcrel_lo(.LBB8_1)(a1)
+; CHECK-NEXT:    clc a1, 0(a1)
+; CHECK-NEXT:    csc a1, 0(a0)
 ; CHECK-NEXT:    cret
 do.body:
   call void @llvm.memcpy.p200.p200.i64(ptr addrspace(200) align 16 %dst, ptr addrspace(200) align 16 @constant_ptrs, i64 16, i1 false) #1
@@ -125,10 +125,10 @@ define linkonce_odr void @copy_from_ptr_constant_with_offset_preserve(ptr addrsp
 ; CHECK:       # %bb.0: # %do.body
 ; CHECK-NEXT:  .LBB9_1: # %do.body
 ; CHECK-NEXT:    # Label of block must be emitted
-; CHECK-NEXT:    auipcc ca1, %captab_pcrel_hi(constant_ptrs)
-; CHECK-NEXT:    clc ca1, %pcrel_lo(.LBB9_1)(ca1)
-; CHECK-NEXT:    clc ca1, 16(ca1)
-; CHECK-NEXT:    csc ca1, 0(ca0)
+; CHECK-NEXT:    auipcc a1, %captab_pcrel_hi(constant_ptrs)
+; CHECK-NEXT:    clc a1, %pcrel_lo(.LBB9_1)(a1)
+; CHECK-NEXT:    clc a1, 16(a1)
+; CHECK-NEXT:    csc a1, 0(a0)
 ; CHECK-NEXT:    cret
 do.body:
   %src = getelementptr inbounds i8, ptr addrspace(200) @constant_ptrs, i64 16
@@ -142,8 +142,8 @@ do.body:
 define linkonce_odr void @copy_from_underaligned_zero_constant(ptr addrspace(200) %dst) addrspace(200) {
 ; CHECK-LABEL: copy_from_underaligned_zero_constant:
 ; CHECK:       # %bb.0: # %do.body
-; CHECK-NEXT:    csd zero, 8(ca0)
-; CHECK-NEXT:    csd zero, 0(ca0)
+; CHECK-NEXT:    csd zero, 8(a0)
+; CHECK-NEXT:    csd zero, 0(a0)
 ; CHECK-NEXT:    cret
 do.body:
   call void @llvm.memcpy.p200.p200.i64(ptr addrspace(200) align 8 %dst, ptr addrspace(200) align 8 @zero_constant, i64 16, i1 false) #1
@@ -153,8 +153,8 @@ do.body:
 define linkonce_odr void @copy_from_underaligned_zero_constant_preserve(ptr addrspace(200) %dst) addrspace(200) {
 ; CHECK-LABEL: copy_from_underaligned_zero_constant_preserve:
 ; CHECK:       # %bb.0: # %do.body
-; CHECK-NEXT:    csd zero, 8(ca0)
-; CHECK-NEXT:    csd zero, 0(ca0)
+; CHECK-NEXT:    csd zero, 8(a0)
+; CHECK-NEXT:    csd zero, 0(a0)
 ; CHECK-NEXT:    cret
 do.body:
   call void @llvm.memcpy.p200.p200.i64(ptr addrspace(200) align 8 %dst, ptr addrspace(200) align 8 @zero_constant, i64 16, i1 false) #1
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/memcpy-no-preserve-tags-attr.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/memcpy-no-preserve-tags-attr.ll
index 87b139083f98b..abba6d146d02b 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/memcpy-no-preserve-tags-attr.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/memcpy-no-preserve-tags-attr.ll
@@ -15,12 +15,12 @@ declare void @llvm.memmove.p200i8.p200i8.i64(i8 addrspace(200)* nocapture writeo
 define void @memcpy_no_attr(%struct.pair addrspace(200)* %a, %struct.pair addrspace(200)* %b) addrspace(200) nounwind {
 ; CHECK-LABEL: memcpy_no_attr:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    cincoffset csp, csp, -16
-; CHECK-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; CHECK-NEXT:    cincoffset sp, sp, -16
+; CHECK-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; CHECK-NEXT:    li a2, 16
 ; CHECK-NEXT:    ccall memcpy
-; CHECK-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; CHECK-NEXT:    cincoffset csp, csp, 16
+; CHECK-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; CHECK-NEXT:    cincoffset sp, sp, 16
 ; CHECK-NEXT:    cret
 entry:
   %a_i8 = bitcast %struct.pair addrspace(200)* %a to i8 addrspace(200)*
@@ -32,12 +32,12 @@ entry:
 define void @memmove_no_attr(%struct.pair addrspace(200)* %a, %struct.pair addrspace(200)* %b) addrspace(200) nounwind {
 ; CHECK-LABEL: memmove_no_attr:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    cincoffset csp, csp, -16
-; CHECK-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; CHECK-NEXT:    cincoffset sp, sp, -16
+; CHECK-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; CHECK-NEXT:    li a2, 16
 ; CHECK-NEXT:    ccall memmove
-; CHECK-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; CHECK-NEXT:    cincoffset csp, csp, 16
+; CHECK-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; CHECK-NEXT:    cincoffset sp, sp, 16
 ; CHECK-NEXT:    cret
 entry:
   %a_i8 = bitcast %struct.pair addrspace(200)* %a to i8 addrspace(200)*
@@ -50,12 +50,12 @@ entry:
 define void @memcpy_must_preserve(%struct.pair addrspace(200)* %a, %struct.pair addrspace(200)* %b) addrspace(200) nounwind {
 ; CHECK-LABEL: memcpy_must_preserve:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    cincoffset csp, csp, -16
-; CHECK-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; CHECK-NEXT:    cincoffset sp, sp, -16
+; CHECK-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; CHECK-NEXT:    li a2, 16
 ; CHECK-NEXT:    ccall memcpy
-; CHECK-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; CHECK-NEXT:    cincoffset csp, csp, 16
+; CHECK-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; CHECK-NEXT:    cincoffset sp, sp, 16
 ; CHECK-NEXT:    cret
 entry:
   %a_i8 = bitcast %struct.pair addrspace(200)* %a to i8 addrspace(200)*
@@ -67,12 +67,12 @@ entry:
 define void @memmove_must_preserve(%struct.pair addrspace(200)* %a, %struct.pair addrspace(200)* %b) addrspace(200) nounwind {
 ; CHECK-LABEL: memmove_must_preserve:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    cincoffset csp, csp, -16
-; CHECK-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; CHECK-NEXT:    cincoffset sp, sp, -16
+; CHECK-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; CHECK-NEXT:    li a2, 16
 ; CHECK-NEXT:    ccall memmove
-; CHECK-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; CHECK-NEXT:    cincoffset csp, csp, 16
+; CHECK-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; CHECK-NEXT:    cincoffset sp, sp, 16
 ; CHECK-NEXT:    cret
 entry:
   %a_i8 = bitcast %struct.pair addrspace(200)* %a to i8 addrspace(200)*
@@ -85,10 +85,10 @@ entry:
 define void @memcpy_no_preserve(%struct.pair addrspace(200)* %a, %struct.pair addrspace(200)* %b) addrspace(200) nounwind {
 ; CHECK-LABEL: memcpy_no_preserve:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    cld a2, 8(ca1)
-; CHECK-NEXT:    csd a2, 8(ca0)
-; CHECK-NEXT:    cld a1, 0(ca1)
-; CHECK-NEXT:    csd a1, 0(ca0)
+; CHECK-NEXT:    cld a2, 8(a1)
+; CHECK-NEXT:    csd a2, 8(a0)
+; CHECK-NEXT:    cld a1, 0(a1)
+; CHECK-NEXT:    csd a1, 0(a0)
 ; CHECK-NEXT:    cret
 entry:
   %a_i8 = bitcast %struct.pair addrspace(200)* %a to i8 addrspace(200)*
@@ -100,10 +100,10 @@ entry:
 define void @memmove_no_preserve(%struct.pair addrspace(200)* %a, %struct.pair addrspace(200)* %b) addrspace(200) nounwind {
 ; CHECK-LABEL: memmove_no_preserve:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    cld a2, 8(ca1)
-; CHECK-NEXT:    cld a1, 0(ca1)
-; CHECK-NEXT:    csd a2, 8(ca0)
-; CHECK-NEXT:    csd a1, 0(ca0)
+; CHECK-NEXT:    cld a2, 8(a1)
+; CHECK-NEXT:    cld a1, 0(a1)
+; CHECK-NEXT:    csd a2, 8(a0)
+; CHECK-NEXT:    csd a1, 0(a0)
 ; CHECK-NEXT:    cret
 entry:
   %a_i8 = bitcast %struct.pair addrspace(200)* %a to i8 addrspace(200)*
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/memcpy-preserve-tags-assume-aligned.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/memcpy-preserve-tags-assume-aligned.ll
index 3b2733910bdd8..a2c7311bbd7a4 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/memcpy-preserve-tags-assume-aligned.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/memcpy-preserve-tags-assume-aligned.ll
@@ -12,10 +12,10 @@ declare void @llvm.assume(i1) addrspace(200)
 define void @memcpy_assume(i8 addrspace(200)* addrspace(200)* %local_cap_ptr, i8 addrspace(200)* %align1) addrspace(200) nounwind {
 ; CHECK-LABEL: memcpy_assume:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    clc ca2, 16(ca0)
-; CHECK-NEXT:    csc ca2, 16(ca1)
-; CHECK-NEXT:    clc ca0, 0(ca0)
-; CHECK-NEXT:    csc ca0, 0(ca1)
+; CHECK-NEXT:    clc a2, 16(a0)
+; CHECK-NEXT:    csc a2, 16(a1)
+; CHECK-NEXT:    clc a0, 0(a0)
+; CHECK-NEXT:    csc a0, 0(a1)
 ; CHECK-NEXT:    cret
   %ptrint = ptrtoint i8 addrspace(200)* %align1 to i64
   %maskedptr = and i64 %ptrint, 15
@@ -29,10 +29,10 @@ define void @memcpy_assume(i8 addrspace(200)* addrspace(200)* %local_cap_ptr, i8
 define void @memmove_assume(i8 addrspace(200)* addrspace(200)* %local_cap_ptr, i8 addrspace(200)* %align1) addrspace(200) nounwind {
 ; CHECK-LABEL: memmove_assume:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    clc ca2, 16(ca0)
-; CHECK-NEXT:    clc ca0, 0(ca0)
-; CHECK-NEXT:    csc ca2, 16(ca1)
-; CHECK-NEXT:    csc ca0, 0(ca1)
+; CHECK-NEXT:    clc a2, 16(a0)
+; CHECK-NEXT:    clc a0, 0(a0)
+; CHECK-NEXT:    csc a2, 16(a1)
+; CHECK-NEXT:    csc a0, 0(a1)
 ; CHECK-NEXT:    cret
   %ptrint = ptrtoint i8 addrspace(200)* %align1 to i64
   %maskedptr = and i64 %ptrint, 15
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/memcpy-preserve-tags-size-not-multiple.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/memcpy-preserve-tags-size-not-multiple.ll
index 95930fdd1cc83..673998cc431ba 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/memcpy-preserve-tags-size-not-multiple.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/memcpy-preserve-tags-size-not-multiple.ll
@@ -11,18 +11,18 @@ define void @test_string_memmove(i8 addrspace(200)* %dst, i8 addrspace(200)* %sr
   ; Note: has must_preserve_cheri_tags, but this memmove can still be inlined since it's aligned
 ; CHECK-LABEL: test_string_memmove:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    cmove ca5, ca1
-; CHECK-NEXT:    cmove ca1, ca0
-; CHECK-NEXT:    clc ca0, 0(ca5)
-; CHECK-NEXT:    clc ca2, 16(ca5)
-; CHECK-NEXT:    cld a3, 32(ca5)
-; CHECK-NEXT:    clw a4, 40(ca5)
-; CHECK-NEXT:    clb a5, 44(ca5)
-; CHECK-NEXT:    csb a5, 44(ca1)
-; CHECK-NEXT:    csw a4, 40(ca1)
-; CHECK-NEXT:    csd a3, 32(ca1)
-; CHECK-NEXT:    csc ca2, 16(ca1)
-; CHECK-NEXT:    csc ca0, 0(ca1)
+; CHECK-NEXT:    cmove a5, a1
+; CHECK-NEXT:    cmove a1, a0
+; CHECK-NEXT:    clc a0, 0(a5)
+; CHECK-NEXT:    clc a2, 16(a5)
+; CHECK-NEXT:    cld a3, 32(a5)
+; CHECK-NEXT:    clw a4, 40(a5)
+; CHECK-NEXT:    clb a5, 44(a5)
+; CHECK-NEXT:    csb a5, 44(a1)
+; CHECK-NEXT:    csw a4, 40(a1)
+; CHECK-NEXT:    csd a3, 32(a1)
+; CHECK-NEXT:    csc a2, 16(a1)
+; CHECK-NEXT:    csc a0, 0(a1)
 ; CHECK-NEXT:    cret
   call void @llvm.memmove.p200i8.p200i8.i64(i8 addrspace(200)* align 16 %dst, i8 addrspace(200)* align 16 %src, i64 45, i1 false) must_preserve_cheri_tags
   ret void
@@ -32,21 +32,21 @@ define void @test_string_memcpy(i8 addrspace(200)* %dst, i8 addrspace(200)* %src
   ; Note: has must_preserve_cheri_tags, but this memcpy can still be inlined since it's aligned
 ; CHECK-LABEL: test_string_memcpy:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    cincoffset csp, csp, -16
-; CHECK-NEXT:    csc ca1, 0(csp) # 16-byte Folded Spill
-; CHECK-NEXT:    cmove ca1, ca0
-; CHECK-NEXT:    clc ca0, 0(csp) # 16-byte Folded Reload
-; CHECK-NEXT:    clb a2, 44(ca0)
-; CHECK-NEXT:    csb a2, 44(ca1)
-; CHECK-NEXT:    clw a2, 40(ca0)
-; CHECK-NEXT:    csw a2, 40(ca1)
-; CHECK-NEXT:    cld a2, 32(ca0)
-; CHECK-NEXT:    csd a2, 32(ca1)
-; CHECK-NEXT:    clc ca2, 16(ca0)
-; CHECK-NEXT:    csc ca2, 16(ca1)
-; CHECK-NEXT:    clc ca0, 0(ca0)
-; CHECK-NEXT:    csc ca0, 0(ca1)
-; CHECK-NEXT:    cincoffset csp, csp, 16
+; CHECK-NEXT:    cincoffset sp, sp, -16
+; CHECK-NEXT:    csc a1, 0(sp) # 16-byte Folded Spill
+; CHECK-NEXT:    cmove a1, a0
+; CHECK-NEXT:    clc a0, 0(sp) # 16-byte Folded Reload
+; CHECK-NEXT:    clb a2, 44(a0)
+; CHECK-NEXT:    csb a2, 44(a1)
+; CHECK-NEXT:    clw a2, 40(a0)
+; CHECK-NEXT:    csw a2, 40(a1)
+; CHECK-NEXT:    cld a2, 32(a0)
+; CHECK-NEXT:    csd a2, 32(a1)
+; CHECK-NEXT:    clc a2, 16(a0)
+; CHECK-NEXT:    csc a2, 16(a1)
+; CHECK-NEXT:    clc a0, 0(a0)
+; CHECK-NEXT:    csc a0, 0(a1)
+; CHECK-NEXT:    cincoffset sp, sp, 16
 ; CHECK-NEXT:    cret
   call void @llvm.memcpy.p200i8.p200i8.i64(i8 addrspace(200)* align 16 %dst, i8 addrspace(200)* align 16 %src, i64 45, i1 false) must_preserve_cheri_tags
   ret void
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/memcpy-zeroinit.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/memcpy-zeroinit.ll
index a185a54ee8395..fad24ba659133 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/memcpy-zeroinit.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/memcpy-zeroinit.ll
@@ -11,9 +11,9 @@
 define void @_thr_umutex_init(%struct.umutex addrspace(200)* %mtx) local_unnamed_addr addrspace(200) nounwind "frame-pointer"="none" {
 ; CHECK-LABEL: _thr_umutex_init:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    csc cnull, 32(ca0)
-; CHECK-NEXT:    csc cnull, 16(ca0)
-; CHECK-NEXT:    csc cnull, 0(ca0)
+; CHECK-NEXT:    csc zero, 32(a0)
+; CHECK-NEXT:    csc zero, 16(a0)
+; CHECK-NEXT:    csc zero, 0(a0)
 ; CHECK-NEXT:    cret
   %1 = bitcast %struct.umutex addrspace(200)* %mtx to i8 addrspace(200)*
   tail call void @llvm.memcpy.p200i8.p200i8.i64(i8 addrspace(200)* align 16 %1, i8 addrspace(200)* align 16 bitcast (%struct.umutex addrspace(200)* @_thr_umutex_init.default_mtx to i8 addrspace(200)*), i64 48, i1 false)
@@ -24,14 +24,14 @@ define void @_thr_umutex_init_volatile(%struct.umutex addrspace(200)* %mtx) loca
 ; CHECK-LABEL: _thr_umutex_init_volatile:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:  .LBB1_1: # Label of block must be emitted
-; CHECK-NEXT:    auipcc ca1, %captab_pcrel_hi(_thr_umutex_init.default_mtx)
-; CHECK-NEXT:    clc ca1, %pcrel_lo(.LBB1_1)(ca1)
-; CHECK-NEXT:    clc ca2, 32(ca1)
-; CHECK-NEXT:    csc ca2, 32(ca0)
-; CHECK-NEXT:    clc ca2, 16(ca1)
-; CHECK-NEXT:    csc ca2, 16(ca0)
-; CHECK-NEXT:    clc ca1, 0(ca1)
-; CHECK-NEXT:    csc ca1, 0(ca0)
+; CHECK-NEXT:    auipcc a1, %captab_pcrel_hi(_thr_umutex_init.default_mtx)
+; CHECK-NEXT:    clc a1, %pcrel_lo(.LBB1_1)(a1)
+; CHECK-NEXT:    clc a2, 32(a1)
+; CHECK-NEXT:    csc a2, 32(a0)
+; CHECK-NEXT:    clc a2, 16(a1)
+; CHECK-NEXT:    csc a2, 16(a0)
+; CHECK-NEXT:    clc a1, 0(a1)
+; CHECK-NEXT:    csc a1, 0(a0)
 ; CHECK-NEXT:    cret
   %1 = bitcast %struct.umutex addrspace(200)* %mtx to i8 addrspace(200)*
   tail call void @llvm.memcpy.p200i8.p200i8.i64(i8 addrspace(200)* align 16 %1, i8 addrspace(200)* align 16 bitcast (%struct.umutex addrspace(200)* @_thr_umutex_init.default_mtx to i8 addrspace(200)*), i64 48, i1 true)
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/optsize-preserve-tags-memcpy-crash.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/optsize-preserve-tags-memcpy-crash.ll
index 7afb2edf005f9..da40b5b9a480c 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/optsize-preserve-tags-memcpy-crash.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/optsize-preserve-tags-memcpy-crash.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; DO NOT EDIT -- This file was generated from test/CodeGen/CHERI-Generic/Inputs/optsize-preserve-tags-memcpy-crash.ll
+; DO NOT EDIT -- This file was generated from test/CodeGen/CHERI-Generic/Inputs/optsize-preserve-tags-memcpy-rash.ll
 ; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+xcheripurecap,+f,+d < %s -o - | FileCheck %s
 ; The following code copying 31 bytes (with capability alignment) using the
 ; must_preserve_tags attribute used to trigger a "(Align < CapSize)" assertion
@@ -13,16 +13,16 @@
 define hidden void @optnone_preserve_tags_memcpy(i8 addrspace(200)* %dst, i8 addrspace(200)* %src) optnone noinline nounwind {
 ; CHECK-LABEL: optnone_preserve_tags_memcpy:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    clb a2, 30(ca1)
-; CHECK-NEXT:    csb a2, 30(ca0)
-; CHECK-NEXT:    clh a2, 28(ca1)
-; CHECK-NEXT:    csh a2, 28(ca0)
-; CHECK-NEXT:    clw a2, 24(ca1)
-; CHECK-NEXT:    csw a2, 24(ca0)
-; CHECK-NEXT:    cld a2, 16(ca1)
-; CHECK-NEXT:    csd a2, 16(ca0)
-; CHECK-NEXT:    clc ca1, 0(ca1)
-; CHECK-NEXT:    csc ca1, 0(ca0)
+; CHECK-NEXT:    clb a2, 30(a1)
+; CHECK-NEXT:    csb a2, 30(a0)
+; CHECK-NEXT:    clh a2, 28(a1)
+; CHECK-NEXT:    csh a2, 28(a0)
+; CHECK-NEXT:    clw a2, 24(a1)
+; CHECK-NEXT:    csw a2, 24(a0)
+; CHECK-NEXT:    cld a2, 16(a1)
+; CHECK-NEXT:    csd a2, 16(a0)
+; CHECK-NEXT:    clc a1, 0(a1)
+; CHECK-NEXT:    csc a1, 0(a0)
 ; CHECK-NEXT:    cret
   tail call void @llvm.memcpy.p200i8.p200i8.i64(i8 addrspace(200)* noundef nonnull align 16 dereferenceable(31) %dst, i8 addrspace(200)* noundef nonnull align 16 dereferenceable(31) %src, i64 31, i1 false) must_preserve_cheri_tags
   ret void
@@ -31,12 +31,12 @@ define hidden void @optnone_preserve_tags_memcpy(i8 addrspace(200)* %dst, i8 add
 define hidden void @optsize_preserve_tags_memcpy(i8 addrspace(200)* %dst, i8 addrspace(200)* %src) optsize nounwind {
 ; CHECK-LABEL: optsize_preserve_tags_memcpy:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    cincoffset csp, csp, -16
-; CHECK-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; CHECK-NEXT:    cincoffset sp, sp, -16
+; CHECK-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; CHECK-NEXT:    li a2, 31
 ; CHECK-NEXT:    ccall memcpy
-; CHECK-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; CHECK-NEXT:    cincoffset csp, csp, 16
+; CHECK-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; CHECK-NEXT:    cincoffset sp, sp, 16
 ; CHECK-NEXT:    cret
   tail call void @llvm.memcpy.p200i8.p200i8.i64(i8 addrspace(200)* noundef nonnull align 16 dereferenceable(31) %dst, i8 addrspace(200)* noundef nonnull align 16 dereferenceable(31) %src, i64 31, i1 false) must_preserve_cheri_tags
   ret void
@@ -45,16 +45,16 @@ define hidden void @optsize_preserve_tags_memcpy(i8 addrspace(200)* %dst, i8 add
 define hidden void @default_preserve_tags_memcpy(i8 addrspace(200)* %dst, i8 addrspace(200)* %src) nounwind {
 ; CHECK-LABEL: default_preserve_tags_memcpy:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    clb a2, 30(ca1)
-; CHECK-NEXT:    csb a2, 30(ca0)
-; CHECK-NEXT:    clh a2, 28(ca1)
-; CHECK-NEXT:    csh a2, 28(ca0)
-; CHECK-NEXT:    clw a2, 24(ca1)
-; CHECK-NEXT:    csw a2, 24(ca0)
-; CHECK-NEXT:    cld a2, 16(ca1)
-; CHECK-NEXT:    csd a2, 16(ca0)
-; CHECK-NEXT:    clc ca1, 0(ca1)
-; CHECK-NEXT:    csc ca1, 0(ca0)
+; CHECK-NEXT:    clb a2, 30(a1)
+; CHECK-NEXT:    csb a2, 30(a0)
+; CHECK-NEXT:    clh a2, 28(a1)
+; CHECK-NEXT:    csh a2, 28(a0)
+; CHECK-NEXT:    clw a2, 24(a1)
+; CHECK-NEXT:    csw a2, 24(a0)
+; CHECK-NEXT:    cld a2, 16(a1)
+; CHECK-NEXT:    csd a2, 16(a0)
+; CHECK-NEXT:    clc a1, 0(a1)
+; CHECK-NEXT:    csc a1, 0(a0)
 ; CHECK-NEXT:    cret
   tail call void @llvm.memcpy.p200i8.p200i8.i64(i8 addrspace(200)* noundef nonnull align 16 dereferenceable(31) %dst, i8 addrspace(200)* noundef nonnull align 16 dereferenceable(31) %src, i64 31, i1 false) must_preserve_cheri_tags
   ret void
@@ -63,16 +63,16 @@ define hidden void @default_preserve_tags_memcpy(i8 addrspace(200)* %dst, i8 add
 define hidden void @optnone_preserve_tags_memmove(i8 addrspace(200)* %dst, i8 addrspace(200)* %src) optnone noinline nounwind {
 ; CHECK-LABEL: optnone_preserve_tags_memmove:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    clc ca2, 0(ca1)
-; CHECK-NEXT:    cld a3, 16(ca1)
-; CHECK-NEXT:    clw a4, 24(ca1)
-; CHECK-NEXT:    clh a5, 28(ca1)
-; CHECK-NEXT:    clb a1, 30(ca1)
-; CHECK-NEXT:    csb a1, 30(ca0)
-; CHECK-NEXT:    csh a5, 28(ca0)
-; CHECK-NEXT:    csw a4, 24(ca0)
-; CHECK-NEXT:    csd a3, 16(ca0)
-; CHECK-NEXT:    csc ca2, 0(ca0)
+; CHECK-NEXT:    clc a2, 0(a1)
+; CHECK-NEXT:    cld a3, 16(a1)
+; CHECK-NEXT:    clw a4, 24(a1)
+; CHECK-NEXT:    clh a5, 28(a1)
+; CHECK-NEXT:    clb a1, 30(a1)
+; CHECK-NEXT:    csb a1, 30(a0)
+; CHECK-NEXT:    csh a5, 28(a0)
+; CHECK-NEXT:    csw a4, 24(a0)
+; CHECK-NEXT:    csd a3, 16(a0)
+; CHECK-NEXT:    csc a2, 0(a0)
 ; CHECK-NEXT:    cret
   tail call void @llvm.memmove.p200i8.p200i8.i64(i8 addrspace(200)* noundef nonnull align 16 dereferenceable(31) %dst, i8 addrspace(200)* noundef nonnull align 16 dereferenceable(31) %src, i64 31, i1 false) must_preserve_cheri_tags
   ret void
@@ -81,12 +81,12 @@ define hidden void @optnone_preserve_tags_memmove(i8 addrspace(200)* %dst, i8 ad
 define hidden void @optsize_preserve_tags_memmove(i8 addrspace(200)* %dst, i8 addrspace(200)* %src) optsize nounwind {
 ; CHECK-LABEL: optsize_preserve_tags_memmove:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    cincoffset csp, csp, -16
-; CHECK-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; CHECK-NEXT:    cincoffset sp, sp, -16
+; CHECK-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; CHECK-NEXT:    li a2, 31
 ; CHECK-NEXT:    ccall memmove
-; CHECK-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; CHECK-NEXT:    cincoffset csp, csp, 16
+; CHECK-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; CHECK-NEXT:    cincoffset sp, sp, 16
 ; CHECK-NEXT:    cret
   tail call void @llvm.memmove.p200i8.p200i8.i64(i8 addrspace(200)* noundef nonnull align 16 dereferenceable(31) %dst, i8 addrspace(200)* noundef nonnull align 16 dereferenceable(31) %src, i64 31, i1 false) must_preserve_cheri_tags
   ret void
@@ -95,16 +95,16 @@ define hidden void @optsize_preserve_tags_memmove(i8 addrspace(200)* %dst, i8 ad
 define hidden void @default_preserve_tags_memmove(i8 addrspace(200)* %dst, i8 addrspace(200)* %src) nounwind{
 ; CHECK-LABEL: default_preserve_tags_memmove:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    clc ca2, 0(ca1)
-; CHECK-NEXT:    clb a3, 30(ca1)
-; CHECK-NEXT:    clh a4, 28(ca1)
-; CHECK-NEXT:    clw a5, 24(ca1)
-; CHECK-NEXT:    cld a1, 16(ca1)
-; CHECK-NEXT:    csb a3, 30(ca0)
-; CHECK-NEXT:    csh a4, 28(ca0)
-; CHECK-NEXT:    csw a5, 24(ca0)
-; CHECK-NEXT:    csd a1, 16(ca0)
-; CHECK-NEXT:    csc ca2, 0(ca0)
+; CHECK-NEXT:    clc a2, 0(a1)
+; CHECK-NEXT:    clb a3, 30(a1)
+; CHECK-NEXT:    clh a4, 28(a1)
+; CHECK-NEXT:    clw a5, 24(a1)
+; CHECK-NEXT:    cld a1, 16(a1)
+; CHECK-NEXT:    csb a3, 30(a0)
+; CHECK-NEXT:    csh a4, 28(a0)
+; CHECK-NEXT:    csw a5, 24(a0)
+; CHECK-NEXT:    csd a1, 16(a0)
+; CHECK-NEXT:    csc a2, 0(a0)
 ; CHECK-NEXT:    cret
   tail call void @llvm.memmove.p200i8.p200i8.i64(i8 addrspace(200)* noundef nonnull align 16 dereferenceable(31) %dst, i8 addrspace(200)* noundef nonnull align 16 dereferenceable(31) %src, i64 31, i1 false) must_preserve_cheri_tags
   ret void
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/ptrtoint.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/ptrtoint.ll
index b1ce19e55aed4..c70d867bbf5bb 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/ptrtoint.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/ptrtoint.ll
@@ -12,7 +12,7 @@ define internal i64 @ptrtoint(i8 addrspace(200)* %cap) addrspace(200) nounwind {
 ;
 ; HYBRID-LABEL: ptrtoint:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    cgettag a1, ca0
+; HYBRID-NEXT:    cgettag a1, a0
 ; HYBRID-NEXT:    neg a1, a1
 ; HYBRID-NEXT:    and a0, a0, a1
 ; HYBRID-NEXT:    ret
@@ -28,7 +28,7 @@ define internal i64 @ptrtoint_plus_const(i8 addrspace(200)* %cap) addrspace(200)
 ;
 ; HYBRID-LABEL: ptrtoint_plus_const:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    cgettag a1, ca0
+; HYBRID-NEXT:    cgettag a1, a0
 ; HYBRID-NEXT:    neg a1, a1
 ; HYBRID-NEXT:    and a0, a0, a1
 ; HYBRID-NEXT:    addi a0, a0, 2
@@ -46,7 +46,7 @@ define internal i64 @ptrtoint_plus_var(i8 addrspace(200)* %cap, i64 %add) addrsp
 ;
 ; HYBRID-LABEL: ptrtoint_plus_var:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    cgettag a2, ca0
+; HYBRID-NEXT:    cgettag a2, a0
 ; HYBRID-NEXT:    neg a2, a2
 ; HYBRID-NEXT:    and a0, a0, a2
 ; HYBRID-NEXT:    add a0, a0, a1
@@ -64,7 +64,7 @@ define internal i64 @ptrtoint_null() addrspace(200) nounwind {
 ;
 ; HYBRID-LABEL: ptrtoint_null:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    cgettag a0, cnull
+; HYBRID-NEXT:    cgettag a0, zero
 ; HYBRID-NEXT:    neg a0, a0
 ; HYBRID-NEXT:    li a0, 0
 ; HYBRID-NEXT:    ret
@@ -80,7 +80,7 @@ define internal i64 @ptrtoint_null_plus_const() addrspace(200) nounwind {
 ;
 ; HYBRID-LABEL: ptrtoint_null_plus_const:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    cgettag a0, cnull
+; HYBRID-NEXT:    cgettag a0, zero
 ; HYBRID-NEXT:    neg a0, a0
 ; HYBRID-NEXT:    li a0, 2
 ; HYBRID-NEXT:    ret
@@ -96,7 +96,7 @@ define internal i64 @ptrtoint_null_plus_var(i64 %add) addrspace(200) nounwind {
 ;
 ; HYBRID-LABEL: ptrtoint_null_plus_var:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    cgettag a1, cnull
+; HYBRID-NEXT:    cgettag a1, zero
 ; HYBRID-NEXT:    neg a1, a1
 ; HYBRID-NEXT:    ret
   %zero = ptrtoint i8 addrspace(200)* null to i64
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/purecap-jumptable.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/purecap-jumptable.ll
index 5c0c427a89f36..31b03f2b51c8f 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/purecap-jumptable.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/purecap-jumptable.ll
@@ -20,7 +20,7 @@ define void @below_threshold(i32 %in, i32 addrspace(200)* %out) nounwind {
 ; CHECK-NEXT:  .LBB0_3: # %bb2
 ; CHECK-NEXT:    li a0, 3
 ; CHECK-NEXT:  .LBB0_4: # %exit
-; CHECK-NEXT:    csw a0, 0(ca1)
+; CHECK-NEXT:    csw a0, 0(a1)
 ; CHECK-NEXT:  .LBB0_5: # %exit
 ; CHECK-NEXT:    cret
 entry:
@@ -70,7 +70,7 @@ define void @above_threshold_mips(i32 %in, i32 addrspace(200)* %out) nounwind {
 ; CHECK-NEXT:  .LBB1_8: # %bb3
 ; CHECK-NEXT:    li a0, 2
 ; CHECK-NEXT:  .LBB1_9: # %exit
-; CHECK-NEXT:    csw a0, 0(ca1)
+; CHECK-NEXT:    csw a0, 0(a1)
 ; CHECK-NEXT:  .LBB1_10: # %exit
 ; CHECK-NEXT:    cret
 entry:
@@ -107,21 +107,21 @@ define void @above_threshold_all(i32 %in, i32 addrspace(200)* %out) nounwind {
 ; CHECK-NEXT:    li a2, 5
 ; CHECK-NEXT:    bltu a2, a0, .LBB2_9
 ; CHECK-NEXT:  # %bb.1: # %entry
-; CHECK-NEXT:    cincoffset csp, csp, -16
-; CHECK-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; CHECK-NEXT:    cincoffset sp, sp, -16
+; CHECK-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; CHECK-NEXT:    slli a0, a0, 2
 ; CHECK-NEXT:  .LBB2_10: # %entry
 ; CHECK-NEXT:    # Label of block must be emitted
-; CHECK-NEXT:    auipcc ca2, %pcrel_hi(.LJTI2_0)
-; CHECK-NEXT:    cincoffset ca2, ca2, %pcrel_lo(.LBB2_10)
-; CHECK-NEXT:    cincoffset ca0, ca2, a0
-; CHECK-NEXT:    clw a0, 0(ca0)
+; CHECK-NEXT:    auipcc a2, %pcrel_hi(.LJTI2_0)
+; CHECK-NEXT:    cincoffset a2, a2, %pcrel_lo(.LBB2_10)
+; CHECK-NEXT:    cincoffset a0, a2, a0
+; CHECK-NEXT:    clw a0, 0(a0)
 ; CHECK-NEXT:  .LBB2_11: # %entry
 ; CHECK-NEXT:    # Label of block must be emitted
-; CHECK-NEXT:    auipcc ca2, %pcrel_hi(.Labove_threshold_all$jump_table_base)
-; CHECK-NEXT:    cincoffset ca2, ca2, %pcrel_lo(.LBB2_11)
-; CHECK-NEXT:    cincoffset ca0, ca2, a0
-; CHECK-NEXT:    cjr ca0
+; CHECK-NEXT:    auipcc a2, %pcrel_hi(.Labove_threshold_all$jump_table_base)
+; CHECK-NEXT:    cincoffset a2, a2, %pcrel_lo(.LBB2_11)
+; CHECK-NEXT:    cincoffset a0, a2, a0
+; CHECK-NEXT:    cjr a0
 ; CHECK-NEXT:  .LBB2_2: # %bb1
 ; CHECK-NEXT:    li a0, 4
 ; CHECK-NEXT:    j .LBB2_8
@@ -140,9 +140,9 @@ define void @above_threshold_all(i32 %in, i32 addrspace(200)* %out) nounwind {
 ; CHECK-NEXT:  .LBB2_7: # %bb6
 ; CHECK-NEXT:    li a0, 200
 ; CHECK-NEXT:  .LBB2_8:
-; CHECK-NEXT:    csw a0, 0(ca1)
-; CHECK-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; CHECK-NEXT:    cincoffset csp, csp, 16
+; CHECK-NEXT:    csw a0, 0(a1)
+; CHECK-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; CHECK-NEXT:    cincoffset sp, sp, 16
 ; CHECK-NEXT:  .LBB2_9: # %exit
 ; CHECK-NEXT:    cret
 entry:
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/setoffset-multiple-uses.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/setoffset-multiple-uses.ll
index 170e1d2cd476b..186d6b2f2632c 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/setoffset-multiple-uses.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/setoffset-multiple-uses.ll
@@ -4,7 +4,7 @@
 ; RUN: opt -S -passes=instcombine -o - %s | llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+xcheripurecap,+f,+d -O1 - -o - | %cheri_FileCheck %s --check-prefix ASM
 
 target datalayout = "e-m:e-pf200:128:128:128:64-p:64:64-i64:64-i128:128-n64-S128-A200-P200-G200"
-; Reduced test case for a crash in the new optimization to fold multiple setoffset calls (orignally found when compiling libunwind)
+; Reduced test case for a rash in the new optimization to fold multiple setoffset calls (orignally found when compiling libunwind)
 
 declare i64 @check_fold(i64) addrspace(200)
 declare void @check_fold_i8ptr(ptr addrspace(200)) addrspace(200)
@@ -14,13 +14,13 @@ declare ptr addrspace(200) @llvm.cheri.cap.offset.set.i64(ptr addrspace(200), i6
 define void @infer_values_from_null_set_offset() addrspace(200) nounwind {
 ; ASM-LABEL: infer_values_from_null_set_offset:
 ; ASM:       # %bb.0:
-; ASM-NEXT:    cincoffset csp, csp, -16
-; ASM-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; ASM-NEXT:    cincoffset sp, sp, -16
+; ASM-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; ASM-NEXT:    lui a0, 30
 ; ASM-NEXT:    addi a0, a0, 576
 ; ASM-NEXT:    ccall check_fold
-; ASM-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; ASM-NEXT:    cincoffset csp, csp, 16
+; ASM-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; ASM-NEXT:    cincoffset sp, sp, 16
 ; ASM-NEXT:    cret
 ; CHECK-LABEL: define void @infer_values_from_null_set_offset
 ; CHECK-SAME: () addrspace(200) #[[ATTR1:[0-9]+]] {
@@ -36,21 +36,21 @@ define void @infer_values_from_null_set_offset() addrspace(200) nounwind {
 define void @multiple_uses_big_constant() addrspace(200) nounwind {
 ; ASM-LABEL: multiple_uses_big_constant:
 ; ASM:       # %bb.0:
-; ASM-NEXT:    cincoffset csp, csp, -32
-; ASM-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; ASM-NEXT:    csc cs0, 0(csp) # 16-byte Folded Spill
+; ASM-NEXT:    cincoffset sp, sp, -32
+; ASM-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; ASM-NEXT:    csc s0, 0(sp) # 16-byte Folded Spill
 ; ASM-NEXT:    lui a0, 30
 ; ASM-NEXT:    addi a0, a0, 576
-; ASM-NEXT:    cincoffset cs0, cnull, a0
-; ASM-NEXT:    cmove ca0, cs0
+; ASM-NEXT:    cincoffset s0, zero, a0
+; ASM-NEXT:    cmove a0, s0
 ; ASM-NEXT:    ccall check_fold_i8ptr
-; ASM-NEXT:    cmove ca0, cs0
+; ASM-NEXT:    cmove a0, s0
 ; ASM-NEXT:    ccall check_fold_i8ptr
-; ASM-NEXT:    cmove ca0, cs0
+; ASM-NEXT:    cmove a0, s0
 ; ASM-NEXT:    ccall check_fold_i8ptr
-; ASM-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; ASM-NEXT:    clc cs0, 0(csp) # 16-byte Folded Reload
-; ASM-NEXT:    cincoffset csp, csp, 32
+; ASM-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; ASM-NEXT:    clc s0, 0(sp) # 16-byte Folded Reload
+; ASM-NEXT:    cincoffset sp, sp, 32
 ; ASM-NEXT:    cret
 ; CHECK-LABEL: define void @multiple_uses_big_constant
 ; CHECK-SAME: () addrspace(200) #[[ATTR1]] {
@@ -70,16 +70,16 @@ define void @multiple_uses_big_constant() addrspace(200) nounwind {
 define void @multiple_uses_small_constant() addrspace(200) nounwind {
 ; ASM-LABEL: multiple_uses_small_constant:
 ; ASM:       # %bb.0:
-; ASM-NEXT:    cincoffset csp, csp, -16
-; ASM-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
-; ASM-NEXT:    cincoffset ca0, cnull, 123
+; ASM-NEXT:    cincoffset sp, sp, -16
+; ASM-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
+; ASM-NEXT:    cincoffset a0, zero, 123
 ; ASM-NEXT:    ccall check_fold_i8ptr
-; ASM-NEXT:    cincoffset ca0, cnull, 123
+; ASM-NEXT:    cincoffset a0, zero, 123
 ; ASM-NEXT:    ccall check_fold_i8ptr
-; ASM-NEXT:    cincoffset ca0, cnull, 123
+; ASM-NEXT:    cincoffset a0, zero, 123
 ; ASM-NEXT:    ccall check_fold_i8ptr
-; ASM-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; ASM-NEXT:    cincoffset csp, csp, 16
+; ASM-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; ASM-NEXT:    cincoffset sp, sp, 16
 ; ASM-NEXT:    cret
 ; CHECK-LABEL: define void @multiple_uses_small_constant
 ; CHECK-SAME: () addrspace(200) #[[ATTR1]] {
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/stack-bounds-dynamic-alloca.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/stack-bounds-dynamic-alloca.ll
index 4f21e35062506..3282375bb7c8c 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/stack-bounds-dynamic-alloca.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/stack-bounds-dynamic-alloca.ll
@@ -19,8 +19,8 @@ declare i32 @use_alloca(ptr addrspace(200)) local_unnamed_addr addrspace(200)
 define i32 @alloca_in_entry(i1 %arg) local_unnamed_addr addrspace(200) nounwind {
 ; ASM-LABEL: alloca_in_entry:
 ; ASM:       # %bb.0: # %entry
-; ASM-NEXT:    cincoffset csp, csp, -32
-; ASM-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
+; ASM-NEXT:    cincoffset sp, sp, -32
+; ASM-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
 ; ASM-NEXT:    mv a1, a0
 ; ASM-NEXT:    andi a0, a1, 1
 ; ASM-NEXT:    beqz a0, .LBB0_4
@@ -29,17 +29,17 @@ define i32 @alloca_in_entry(i1 %arg) local_unnamed_addr addrspace(200) nounwind
 ; ASM-NEXT:    j .LBB0_2
 ; ASM-NEXT:  .LBB0_2: # %use_alloca_no_bounds
 ; ASM-NEXT:    li a0, 1234
-; ASM-NEXT:    csd a0, 8(csp)
+; ASM-NEXT:    csd a0, 8(sp)
 ; ASM-NEXT:    j .LBB0_3
 ; ASM-NEXT:  .LBB0_3: # %use_alloca_need_bounds
-; ASM-NEXT:    cincoffset ca0, csp, 0
-; ASM-NEXT:    csetbounds ca0, ca0, 16
+; ASM-NEXT:    cincoffset a0, sp, 0
+; ASM-NEXT:    csetbounds a0, a0, 16
 ; ASM-NEXT:    ccall use_alloca
 ; ASM-NEXT:    j .LBB0_4
 ; ASM-NEXT:  .LBB0_4: # %exit
 ; ASM-NEXT:    li a0, 123
-; ASM-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; ASM-NEXT:    cincoffset csp, csp, 32
+; ASM-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; ASM-NEXT:    cincoffset sp, sp, 32
 ; ASM-NEXT:    cret
 ;
 ; ASM-OPT-LABEL: alloca_in_entry:
@@ -47,15 +47,15 @@ define i32 @alloca_in_entry(i1 %arg) local_unnamed_addr addrspace(200) nounwind
 ; ASM-OPT-NEXT:    andi a0, a0, 1
 ; ASM-OPT-NEXT:    beqz a0, .LBB0_2
 ; ASM-OPT-NEXT:  # %bb.1: # %do_alloca
-; ASM-OPT-NEXT:    cincoffset csp, csp, -32
-; ASM-OPT-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
+; ASM-OPT-NEXT:    cincoffset sp, sp, -32
+; ASM-OPT-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
 ; ASM-OPT-NEXT:    li a0, 1234
-; ASM-OPT-NEXT:    csd a0, 8(csp)
-; ASM-OPT-NEXT:    cincoffset ca0, csp, 0
-; ASM-OPT-NEXT:    csetbounds ca0, ca0, 16
+; ASM-OPT-NEXT:    csd a0, 8(sp)
+; ASM-OPT-NEXT:    cincoffset a0, sp, 0
+; ASM-OPT-NEXT:    csetbounds a0, a0, 16
 ; ASM-OPT-NEXT:    ccall use_alloca
-; ASM-OPT-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; ASM-OPT-NEXT:    cincoffset csp, csp, 32
+; ASM-OPT-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; ASM-OPT-NEXT:    cincoffset sp, sp, 32
 ; ASM-OPT-NEXT:  .LBB0_2: # %exit
 ; ASM-OPT-NEXT:    li a0, 123
 ; ASM-OPT-NEXT:    cret
@@ -102,40 +102,40 @@ exit:                                             ; preds = %use_alloca_need_bou
 define i32 @alloca_not_in_entry(i1 %arg) local_unnamed_addr addrspace(200) nounwind {
 ; ASM-LABEL: alloca_not_in_entry:
 ; ASM:       # %bb.0: # %entry
-; ASM-NEXT:    cincoffset csp, csp, -64
-; ASM-NEXT:    csc cra, 48(csp) # 16-byte Folded Spill
-; ASM-NEXT:    csc cs0, 32(csp) # 16-byte Folded Spill
-; ASM-NEXT:    cincoffset cs0, csp, 64
+; ASM-NEXT:    cincoffset sp, sp, -64
+; ASM-NEXT:    csc ra, 48(sp) # 16-byte Folded Spill
+; ASM-NEXT:    csc s0, 32(sp) # 16-byte Folded Spill
+; ASM-NEXT:    cincoffset s0, sp, 64
 ; ASM-NEXT:    mv a1, a0
 ; ASM-NEXT:    andi a0, a1, 1
 ; ASM-NEXT:    beqz a0, .LBB1_4
 ; ASM-NEXT:    j .LBB1_1
 ; ASM-NEXT:  .LBB1_1: # %do_alloca
-; ASM-NEXT:    cmove ca0, csp
+; ASM-NEXT:    cmove a0, sp
 ; ASM-NEXT:    mv a1, a0
 ; ASM-NEXT:    addi a1, a1, -16
-; ASM-NEXT:    csetaddr ca1, ca0, a1
-; ASM-NEXT:    csetbounds ca0, ca1, 16
-; ASM-NEXT:    csc ca0, -64(cs0) # 16-byte Folded Spill
-; ASM-NEXT:    cmove csp, ca1
-; ASM-NEXT:    csetbounds ca0, ca0, 16
-; ASM-NEXT:    csc ca0, -48(cs0) # 16-byte Folded Spill
+; ASM-NEXT:    csetaddr a1, a0, a1
+; ASM-NEXT:    csetbounds a0, a1, 16
+; ASM-NEXT:    csc a0, -64(s0) # 16-byte Folded Spill
+; ASM-NEXT:    cmove sp, a1
+; ASM-NEXT:    csetbounds a0, a0, 16
+; ASM-NEXT:    csc a0, -48(s0) # 16-byte Folded Spill
 ; ASM-NEXT:    j .LBB1_2
 ; ASM-NEXT:  .LBB1_2: # %use_alloca_no_bounds
-; ASM-NEXT:    clc ca1, -64(cs0) # 16-byte Folded Reload
+; ASM-NEXT:    clc a1, -64(s0) # 16-byte Folded Reload
 ; ASM-NEXT:    li a0, 1234
-; ASM-NEXT:    csd a0, 8(ca1)
+; ASM-NEXT:    csd a0, 8(a1)
 ; ASM-NEXT:    j .LBB1_3
 ; ASM-NEXT:  .LBB1_3: # %use_alloca_need_bounds
-; ASM-NEXT:    clc ca0, -48(cs0) # 16-byte Folded Reload
+; ASM-NEXT:    clc a0, -48(s0) # 16-byte Folded Reload
 ; ASM-NEXT:    ccall use_alloca
 ; ASM-NEXT:    j .LBB1_4
 ; ASM-NEXT:  .LBB1_4: # %exit
 ; ASM-NEXT:    li a0, 123
-; ASM-NEXT:    cincoffset csp, cs0, -64
-; ASM-NEXT:    clc cra, 48(csp) # 16-byte Folded Reload
-; ASM-NEXT:    clc cs0, 32(csp) # 16-byte Folded Reload
-; ASM-NEXT:    cincoffset csp, csp, 64
+; ASM-NEXT:    cincoffset sp, s0, -64
+; ASM-NEXT:    clc ra, 48(sp) # 16-byte Folded Reload
+; ASM-NEXT:    clc s0, 32(sp) # 16-byte Folded Reload
+; ASM-NEXT:    cincoffset sp, sp, 64
 ; ASM-NEXT:    cret
 ;
 ; ASM-OPT-LABEL: alloca_not_in_entry:
@@ -143,22 +143,22 @@ define i32 @alloca_not_in_entry(i1 %arg) local_unnamed_addr addrspace(200) nounw
 ; ASM-OPT-NEXT:    andi a0, a0, 1
 ; ASM-OPT-NEXT:    beqz a0, .LBB1_2
 ; ASM-OPT-NEXT:  # %bb.1: # %do_alloca
-; ASM-OPT-NEXT:    cincoffset csp, csp, -32
-; ASM-OPT-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; ASM-OPT-NEXT:    csc cs0, 0(csp) # 16-byte Folded Spill
-; ASM-OPT-NEXT:    cincoffset cs0, csp, 32
+; ASM-OPT-NEXT:    cincoffset sp, sp, -32
+; ASM-OPT-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; ASM-OPT-NEXT:    csc s0, 0(sp) # 16-byte Folded Spill
+; ASM-OPT-NEXT:    cincoffset s0, sp, 32
 ; ASM-OPT-NEXT:    addi a0, sp, -16
-; ASM-OPT-NEXT:    csetaddr ca0, csp, a0
-; ASM-OPT-NEXT:    csetbounds ca1, ca0, 16
-; ASM-OPT-NEXT:    cmove csp, ca0
-; ASM-OPT-NEXT:    csetbounds ca0, ca1, 16
+; ASM-OPT-NEXT:    csetaddr a0, sp, a0
+; ASM-OPT-NEXT:    csetbounds a1, a0, 16
+; ASM-OPT-NEXT:    cmove sp, a0
+; ASM-OPT-NEXT:    csetbounds a0, a1, 16
 ; ASM-OPT-NEXT:    li a2, 1234
-; ASM-OPT-NEXT:    csd a2, 8(ca1)
+; ASM-OPT-NEXT:    csd a2, 8(a1)
 ; ASM-OPT-NEXT:    ccall use_alloca
-; ASM-OPT-NEXT:    cincoffset csp, cs0, -32
-; ASM-OPT-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; ASM-OPT-NEXT:    clc cs0, 0(csp) # 16-byte Folded Reload
-; ASM-OPT-NEXT:    cincoffset csp, csp, 32
+; ASM-OPT-NEXT:    cincoffset sp, s0, -32
+; ASM-OPT-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; ASM-OPT-NEXT:    clc s0, 0(sp) # 16-byte Folded Reload
+; ASM-OPT-NEXT:    cincoffset sp, sp, 32
 ; ASM-OPT-NEXT:  .LBB1_2: # %exit
 ; ASM-OPT-NEXT:    li a0, 123
 ; ASM-OPT-NEXT:    cret
@@ -204,65 +204,65 @@ exit:                                             ; preds = %use_alloca_need_bou
 
 ; The original reduced test case from libc/gen/exec.c
 ; We can't use llvm.cheri.bounded.stack.cap.i64 here, since that only works for static allocas:
-define i32 @crash_reproducer(i1 %arg) local_unnamed_addr addrspace(200) nounwind {
-; ASM-LABEL: crash_reproducer:
+define i32 @rash_reproducer(i1 %arg) local_unnamed_addr addrspace(200) nounwind {
+; ASM-LABEL: rash_reproducer:
 ; ASM:       # %bb.0: # %entry
-; ASM-NEXT:    cincoffset csp, csp, -64
-; ASM-NEXT:    csc cra, 48(csp) # 16-byte Folded Spill
-; ASM-NEXT:    csc cs0, 32(csp) # 16-byte Folded Spill
-; ASM-NEXT:    cincoffset cs0, csp, 64
+; ASM-NEXT:    cincoffset sp, sp, -64
+; ASM-NEXT:    csc ra, 48(sp) # 16-byte Folded Spill
+; ASM-NEXT:    csc s0, 32(sp) # 16-byte Folded Spill
+; ASM-NEXT:    cincoffset s0, sp, 64
 ; ASM-NEXT:    mv a1, a0
 ; ASM-NEXT:    andi a0, a1, 1
 ; ASM-NEXT:    beqz a0, .LBB2_2
 ; ASM-NEXT:    j .LBB2_1
 ; ASM-NEXT:  .LBB2_1: # %entry.while.end_crit_edge
 ; ASM-NEXT:  .LBB2_2: # %while.body
-; ASM-NEXT:    cmove ca0, csp
+; ASM-NEXT:    cmove a0, sp
 ; ASM-NEXT:    mv a1, a0
 ; ASM-NEXT:    addi a1, a1, -16
-; ASM-NEXT:    csetaddr ca1, ca0, a1
-; ASM-NEXT:    csetbounds ca0, ca1, 16
-; ASM-NEXT:    cmove csp, ca1
-; ASM-NEXT:    csetbounds ca0, ca0, 16
-; ASM-NEXT:    csc ca0, -48(cs0) # 16-byte Folded Spill
+; ASM-NEXT:    csetaddr a1, a0, a1
+; ASM-NEXT:    csetbounds a0, a1, 16
+; ASM-NEXT:    cmove sp, a1
+; ASM-NEXT:    csetbounds a0, a0, 16
+; ASM-NEXT:    csc a0, -48(s0) # 16-byte Folded Spill
 ; ASM-NEXT:    j .LBB2_3
 ; ASM-NEXT:  .LBB2_3: # %while.end.loopexit
-; ASM-NEXT:    clc ca0, -48(cs0) # 16-byte Folded Reload
-; ASM-NEXT:    csc ca0, -64(cs0) # 16-byte Folded Spill
+; ASM-NEXT:    clc a0, -48(s0) # 16-byte Folded Reload
+; ASM-NEXT:    csc a0, -64(s0) # 16-byte Folded Spill
 ; ASM-NEXT:    j .LBB2_4
 ; ASM-NEXT:  .LBB2_4: # %while.end
-; ASM-NEXT:    clc ca0, -64(cs0) # 16-byte Folded Reload
+; ASM-NEXT:    clc a0, -64(s0) # 16-byte Folded Reload
 ; ASM-NEXT:    ccall use_alloca
 ; ASM-NEXT:    addiw a0, a0, 1234
-; ASM-NEXT:    cincoffset csp, cs0, -64
-; ASM-NEXT:    clc cra, 48(csp) # 16-byte Folded Reload
-; ASM-NEXT:    clc cs0, 32(csp) # 16-byte Folded Reload
-; ASM-NEXT:    cincoffset csp, csp, 64
+; ASM-NEXT:    cincoffset sp, s0, -64
+; ASM-NEXT:    clc ra, 48(sp) # 16-byte Folded Reload
+; ASM-NEXT:    clc s0, 32(sp) # 16-byte Folded Reload
+; ASM-NEXT:    cincoffset sp, sp, 64
 ; ASM-NEXT:    cret
 ;
-; ASM-OPT-LABEL: crash_reproducer:
+; ASM-OPT-LABEL: rash_reproducer:
 ; ASM-OPT:       # %bb.0: # %entry
 ; ASM-OPT-NEXT:    andi a0, a0, 1
 ; ASM-OPT-NEXT:    bnez a0, .LBB2_2
 ; ASM-OPT-NEXT:  # %bb.1: # %while.body
-; ASM-OPT-NEXT:    cincoffset csp, csp, -32
-; ASM-OPT-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; ASM-OPT-NEXT:    csc cs0, 0(csp) # 16-byte Folded Spill
-; ASM-OPT-NEXT:    cincoffset cs0, csp, 32
+; ASM-OPT-NEXT:    cincoffset sp, sp, -32
+; ASM-OPT-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; ASM-OPT-NEXT:    csc s0, 0(sp) # 16-byte Folded Spill
+; ASM-OPT-NEXT:    cincoffset s0, sp, 32
 ; ASM-OPT-NEXT:    addi a0, sp, -16
-; ASM-OPT-NEXT:    csetaddr ca0, csp, a0
-; ASM-OPT-NEXT:    csetbounds ca1, ca0, 16
-; ASM-OPT-NEXT:    cmove csp, ca0
-; ASM-OPT-NEXT:    csetbounds ca0, ca1, 16
+; ASM-OPT-NEXT:    csetaddr a0, sp, a0
+; ASM-OPT-NEXT:    csetbounds a1, a0, 16
+; ASM-OPT-NEXT:    cmove sp, a0
+; ASM-OPT-NEXT:    csetbounds a0, a1, 16
 ; ASM-OPT-NEXT:    ccall use_alloca
 ; ASM-OPT-NEXT:    addiw a0, a0, 1234
-; ASM-OPT-NEXT:    cincoffset csp, cs0, -32
-; ASM-OPT-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; ASM-OPT-NEXT:    clc cs0, 0(csp) # 16-byte Folded Reload
-; ASM-OPT-NEXT:    cincoffset csp, csp, 32
+; ASM-OPT-NEXT:    cincoffset sp, s0, -32
+; ASM-OPT-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; ASM-OPT-NEXT:    clc s0, 0(sp) # 16-byte Folded Reload
+; ASM-OPT-NEXT:    cincoffset sp, sp, 32
 ; ASM-OPT-NEXT:    cret
 ; ASM-OPT-NEXT:  .LBB2_2: # %entry.while.end_crit_edge
-; CHECK-LABEL: define i32 @crash_reproducer
+; CHECK-LABEL: define i32 @rash_reproducer
 ; CHECK-SAME: (i1 [[ARG:%.*]]) local_unnamed_addr addrspace(200) #[[ATTR1]] {
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    br i1 [[ARG]], label [[ENTRY_WHILE_END_CRIT_EDGE:%.*]], label [[WHILE_BODY:%.*]]
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/stack-bounds-opaque-spill-too-early.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/stack-bounds-opaque-spill-too-early.ll
index 0e23d4faae811..51a7154eee3b9 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/stack-bounds-opaque-spill-too-early.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/stack-bounds-opaque-spill-too-early.ll
@@ -34,19 +34,19 @@ declare void @cheribsdtest_check_cap_eq(ptr addrspace(200) noundef, ptr addrspac
 define dso_local void @lazy_bind_args() addrspace(200) nounwind {
 ; ASM-LABEL: lazy_bind_args:
 ; ASM:       # %bb.0: # %entry
-; ASM-NEXT:    cincoffset csp, csp, -32
-; ASM-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; ASM-NEXT:    cincoffset ca0, csp, 0
-; ASM-NEXT:    csetbounds ca0, ca0, 16
-; ASM-NEXT:    csc ca0, 0(csp)
+; ASM-NEXT:    cincoffset sp, sp, -32
+; ASM-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; ASM-NEXT:    cincoffset a0, sp, 0
+; ASM-NEXT:    csetbounds a0, a0, 16
+; ASM-NEXT:    csc a0, 0(sp)
 ; ASM-NEXT:    ccall cheribsdtest_dynamic_identity_cap
-; ASM-NEXT:    clc ca1, 0(csp)
-; ASM-NEXT:    cmove ca2, ca0
-; ASM-NEXT:    cmove ca0, ca1
-; ASM-NEXT:    cmove ca1, ca2
+; ASM-NEXT:    clc a1, 0(sp)
+; ASM-NEXT:    cmove a2, a0
+; ASM-NEXT:    cmove a0, a1
+; ASM-NEXT:    cmove a1, a2
 ; ASM-NEXT:    ccall cheribsdtest_check_cap_eq
-; ASM-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; ASM-NEXT:    cincoffset csp, csp, 32
+; ASM-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; ASM-NEXT:    cincoffset sp, sp, 32
 ; ASM-NEXT:    cret
 ; CHECK-LABEL: define dso_local void @lazy_bind_args
 ; CHECK-SAME: () addrspace(200) #[[ATTR2:[0-9]+]] {
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/stack-bounds-pass-phi.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/stack-bounds-pass-phi.ll
index 8216ebb59e8f5..b9d2055c76450 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/stack-bounds-pass-phi.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/stack-bounds-pass-phi.ll
@@ -13,40 +13,40 @@ declare void @foo(ptr addrspace(200)) addrspace(200)
 define void @test_phi(i1 %cond) addrspace(200) nounwind {
 ; ASM-LABEL: test_phi:
 ; ASM:       # %bb.0: # %entry
-; ASM-NEXT:    cincoffset csp, csp, -48
-; ASM-NEXT:    csc cra, 32(csp) # 16-byte Folded Spill
-; ASM-NEXT:    csc cs0, 16(csp) # 16-byte Folded Spill
+; ASM-NEXT:    cincoffset sp, sp, -48
+; ASM-NEXT:    csc ra, 32(sp) # 16-byte Folded Spill
+; ASM-NEXT:    csc s0, 16(sp) # 16-byte Folded Spill
 ; ASM-NEXT:    andi a0, a0, 1
 ; ASM-NEXT:    beqz a0, .LBB0_2
 ; ASM-NEXT:  # %bb.1: # %block1
-; ASM-NEXT:    cmove ca0, cnull
+; ASM-NEXT:    cmove a0, zero
 ; ASM-NEXT:    li a1, 1
-; ASM-NEXT:    csw a1, 12(csp)
+; ASM-NEXT:    csw a1, 12(sp)
 ; ASM-NEXT:    li a1, 2
-; ASM-NEXT:    csw a1, 8(csp)
+; ASM-NEXT:    csw a1, 8(sp)
 ; ASM-NEXT:    li a1, 3
-; ASM-NEXT:    csw a1, 4(csp)
-; ASM-NEXT:    cincoffset ca1, csp, 8
-; ASM-NEXT:    csetbounds cs0, ca1, 4
+; ASM-NEXT:    csw a1, 4(sp)
+; ASM-NEXT:    cincoffset a1, sp, 8
+; ASM-NEXT:    csetbounds s0, a1, 4
 ; ASM-NEXT:    j .LBB0_3
 ; ASM-NEXT:  .LBB0_2: # %block2
 ; ASM-NEXT:    li a0, 4
 ; ASM-NEXT:    li a1, 5
-; ASM-NEXT:    csw a0, 12(csp)
+; ASM-NEXT:    csw a0, 12(sp)
 ; ASM-NEXT:    li a0, 6
-; ASM-NEXT:    csw a1, 8(csp)
-; ASM-NEXT:    cincoffset ca1, csp, 12
-; ASM-NEXT:    csw a0, 4(csp)
-; ASM-NEXT:    cincoffset ca2, csp, 4
-; ASM-NEXT:    csetbounds ca0, ca1, 4
-; ASM-NEXT:    csetbounds cs0, ca2, 4
+; ASM-NEXT:    csw a1, 8(sp)
+; ASM-NEXT:    cincoffset a1, sp, 12
+; ASM-NEXT:    csw a0, 4(sp)
+; ASM-NEXT:    cincoffset a2, sp, 4
+; ASM-NEXT:    csetbounds a0, a1, 4
+; ASM-NEXT:    csetbounds s0, a2, 4
 ; ASM-NEXT:  .LBB0_3: # %phi_block
 ; ASM-NEXT:    ccall foo
-; ASM-NEXT:    cmove ca0, cs0
+; ASM-NEXT:    cmove a0, s0
 ; ASM-NEXT:    ccall foo
-; ASM-NEXT:    clc cra, 32(csp) # 16-byte Folded Reload
-; ASM-NEXT:    clc cs0, 16(csp) # 16-byte Folded Reload
-; ASM-NEXT:    cincoffset csp, csp, 48
+; ASM-NEXT:    clc ra, 32(sp) # 16-byte Folded Reload
+; ASM-NEXT:    clc s0, 16(sp) # 16-byte Folded Reload
+; ASM-NEXT:    cincoffset sp, sp, 48
 ; ASM-NEXT:    cret
 ; CHECK-LABEL: define void @test_phi
 ; CHECK-SAME: (i1 [[COND:%.*]]) addrspace(200) #[[ATTR1:[0-9]+]] {
@@ -104,24 +104,24 @@ phi_block:
 define void @test_only_created_in_predecessor_block(i1 %cond) addrspace(200) nounwind {
 ; ASM-LABEL: test_only_created_in_predecessor_block:
 ; ASM:       # %bb.0: # %entry
-; ASM-NEXT:    cincoffset csp, csp, -32
-; ASM-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
+; ASM-NEXT:    cincoffset sp, sp, -32
+; ASM-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
 ; ASM-NEXT:    andi a0, a0, 1
 ; ASM-NEXT:    beqz a0, .LBB1_2
 ; ASM-NEXT:  # %bb.1: # %block1
 ; ASM-NEXT:    li a0, 1
-; ASM-NEXT:    csw a0, 12(csp)
-; ASM-NEXT:    cincoffset ca0, csp, 12
+; ASM-NEXT:    csw a0, 12(sp)
+; ASM-NEXT:    cincoffset a0, sp, 12
 ; ASM-NEXT:    j .LBB1_3
 ; ASM-NEXT:  .LBB1_2: # %block2
 ; ASM-NEXT:    li a0, 5
-; ASM-NEXT:    csw a0, 8(csp)
-; ASM-NEXT:    cincoffset ca0, csp, 8
+; ASM-NEXT:    csw a0, 8(sp)
+; ASM-NEXT:    cincoffset a0, sp, 8
 ; ASM-NEXT:  .LBB1_3: # %phi_block
-; ASM-NEXT:    csetbounds ca0, ca0, 4
+; ASM-NEXT:    csetbounds a0, a0, 4
 ; ASM-NEXT:    ccall foo
-; ASM-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; ASM-NEXT:    cincoffset csp, csp, 32
+; ASM-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; ASM-NEXT:    cincoffset sp, sp, 32
 ; ASM-NEXT:    cret
 ; CHECK-LABEL: define void @test_only_created_in_predecessor_block
 ; CHECK-SAME: (i1 [[COND:%.*]]) addrspace(200) #[[ATTR1]] {
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/stack-spill-unnecessary.c.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/stack-spill-unnecessary.c.ll
index a5adb5172577b..975951a3dd42c 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/stack-spill-unnecessary.c.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/stack-spill-unnecessary.c.ll
@@ -18,19 +18,19 @@ declare void @multi_arg(i32 addrspace(200)* %start, i32 addrspace(200)* %end, i8
 define void @use_after_call() addrspace(200) nounwind {
 ; CHECK-LABEL: use_after_call:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    cincoffset csp, csp, -48
-; CHECK-NEXT:    csc cra, 32(csp) # 16-byte Folded Spill
-; CHECK-NEXT:    csc cs0, 16(csp) # 16-byte Folded Spill
-; CHECK-NEXT:    cincoffset ca0, csp, 12
+; CHECK-NEXT:    cincoffset sp, sp, -48
+; CHECK-NEXT:    csc ra, 32(sp) # 16-byte Folded Spill
+; CHECK-NEXT:    csc s0, 16(sp) # 16-byte Folded Spill
+; CHECK-NEXT:    cincoffset a0, sp, 12
 ; CHECK-NEXT:    li a1, 123
-; CHECK-NEXT:    csetbounds cs0, ca0, 4
-; CHECK-NEXT:    csw a1, 12(csp)
+; CHECK-NEXT:    csetbounds s0, a0, 4
+; CHECK-NEXT:    csw a1, 12(sp)
 ; CHECK-NEXT:    ccall foo
-; CHECK-NEXT:    cmove ca0, cs0
+; CHECK-NEXT:    cmove a0, s0
 ; CHECK-NEXT:    ccall one_arg
-; CHECK-NEXT:    clc cra, 32(csp) # 16-byte Folded Reload
-; CHECK-NEXT:    clc cs0, 16(csp) # 16-byte Folded Reload
-; CHECK-NEXT:    cincoffset csp, csp, 48
+; CHECK-NEXT:    clc ra, 32(sp) # 16-byte Folded Reload
+; CHECK-NEXT:    clc s0, 16(sp) # 16-byte Folded Reload
+; CHECK-NEXT:    cincoffset sp, sp, 48
 ; CHECK-NEXT:    cret
 ;
 ; HYBRID-LABEL: use_after_call:
@@ -55,23 +55,23 @@ define void @use_after_call() addrspace(200) nounwind {
 define void @use_after_call_no_store() addrspace(200) nounwind {
 ; CHECK-LABEL: use_after_call_no_store:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    cincoffset csp, csp, -64
-; CHECK-NEXT:    csc cra, 48(csp) # 16-byte Folded Spill
-; CHECK-NEXT:    csc cs0, 32(csp) # 16-byte Folded Spill
-; CHECK-NEXT:    csc cs1, 16(csp) # 16-byte Folded Spill
-; CHECK-NEXT:    cincoffset ca0, csp, 12
-; CHECK-NEXT:    cincoffset ca1, csp, 8
-; CHECK-NEXT:    csetbounds cs0, ca0, 4
-; CHECK-NEXT:    csetbounds cs1, ca1, 4
+; CHECK-NEXT:    cincoffset sp, sp, -64
+; CHECK-NEXT:    csc ra, 48(sp) # 16-byte Folded Spill
+; CHECK-NEXT:    csc s0, 32(sp) # 16-byte Folded Spill
+; CHECK-NEXT:    csc s1, 16(sp) # 16-byte Folded Spill
+; CHECK-NEXT:    cincoffset a0, sp, 12
+; CHECK-NEXT:    cincoffset a1, sp, 8
+; CHECK-NEXT:    csetbounds s0, a0, 4
+; CHECK-NEXT:    csetbounds s1, a1, 4
 ; CHECK-NEXT:    ccall foo
-; CHECK-NEXT:    cmove ca0, cs0
+; CHECK-NEXT:    cmove a0, s0
 ; CHECK-NEXT:    ccall one_arg
-; CHECK-NEXT:    cmove ca0, cs1
+; CHECK-NEXT:    cmove a0, s1
 ; CHECK-NEXT:    ccall one_arg
-; CHECK-NEXT:    clc cra, 48(csp) # 16-byte Folded Reload
-; CHECK-NEXT:    clc cs0, 32(csp) # 16-byte Folded Reload
-; CHECK-NEXT:    clc cs1, 16(csp) # 16-byte Folded Reload
-; CHECK-NEXT:    cincoffset csp, csp, 64
+; CHECK-NEXT:    clc ra, 48(sp) # 16-byte Folded Reload
+; CHECK-NEXT:    clc s0, 32(sp) # 16-byte Folded Reload
+; CHECK-NEXT:    clc s1, 16(sp) # 16-byte Folded Reload
+; CHECK-NEXT:    cincoffset sp, sp, 64
 ; CHECK-NEXT:    cret
 ;
 ; HYBRID-LABEL: use_after_call_no_store:
@@ -97,27 +97,27 @@ define void @use_after_call_no_store() addrspace(200) nounwind {
 define void @multi_use() addrspace(200) nounwind {
 ; CHECK-LABEL: multi_use:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    cincoffset csp, csp, -64
-; CHECK-NEXT:    csc cra, 48(csp) # 16-byte Folded Spill
-; CHECK-NEXT:    csc cs0, 32(csp) # 16-byte Folded Spill
-; CHECK-NEXT:    csc cs1, 16(csp) # 16-byte Folded Spill
-; CHECK-NEXT:    cincoffset ca0, csp, 12
-; CHECK-NEXT:    cincoffset ca1, csp, 8
-; CHECK-NEXT:    csetbounds cs0, ca0, 4
-; CHECK-NEXT:    csetbounds cs1, ca1, 4
+; CHECK-NEXT:    cincoffset sp, sp, -64
+; CHECK-NEXT:    csc ra, 48(sp) # 16-byte Folded Spill
+; CHECK-NEXT:    csc s0, 32(sp) # 16-byte Folded Spill
+; CHECK-NEXT:    csc s1, 16(sp) # 16-byte Folded Spill
+; CHECK-NEXT:    cincoffset a0, sp, 12
+; CHECK-NEXT:    cincoffset a1, sp, 8
+; CHECK-NEXT:    csetbounds s0, a0, 4
+; CHECK-NEXT:    csetbounds s1, a1, 4
 ; CHECK-NEXT:    ccall foo
-; CHECK-NEXT:    cincoffset ca1, cs1, 4
-; CHECK-NEXT:    cincoffset ca2, cs1, 1
-; CHECK-NEXT:    cmove ca0, cs1
+; CHECK-NEXT:    cincoffset a1, s1, 4
+; CHECK-NEXT:    cincoffset a2, s1, 1
+; CHECK-NEXT:    cmove a0, s1
 ; CHECK-NEXT:    ccall multi_arg
-; CHECK-NEXT:    cmove ca0, cs0
+; CHECK-NEXT:    cmove a0, s0
 ; CHECK-NEXT:    ccall one_arg
-; CHECK-NEXT:    cmove ca0, cs1
+; CHECK-NEXT:    cmove a0, s1
 ; CHECK-NEXT:    ccall one_arg
-; CHECK-NEXT:    clc cra, 48(csp) # 16-byte Folded Reload
-; CHECK-NEXT:    clc cs0, 32(csp) # 16-byte Folded Reload
-; CHECK-NEXT:    clc cs1, 16(csp) # 16-byte Folded Reload
-; CHECK-NEXT:    cincoffset csp, csp, 64
+; CHECK-NEXT:    clc ra, 48(sp) # 16-byte Folded Reload
+; CHECK-NEXT:    clc s0, 32(sp) # 16-byte Folded Reload
+; CHECK-NEXT:    clc s1, 16(sp) # 16-byte Folded Reload
+; CHECK-NEXT:    cincoffset sp, sp, 64
 ; CHECK-NEXT:    cret
 ;
 ; HYBRID-LABEL: multi_use:
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/stackframe-intrinsics.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/stackframe-intrinsics.ll
index 5cd100abf1b79..293c600c91c25 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/stackframe-intrinsics.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/stackframe-intrinsics.ll
@@ -9,15 +9,15 @@
 define dso_local ptr addrspace(200) @frameaddr() addrspace(200) nounwind {
 ; PURECAP-LABEL: frameaddr:
 ; PURECAP:       # %bb.0: # %entry
-; PURECAP-NEXT:    cincoffset csp, csp, -48
-; PURECAP-NEXT:    csc cra, 32(csp) # 16-byte Folded Spill
-; PURECAP-NEXT:    csc cs0, 16(csp) # 16-byte Folded Spill
-; PURECAP-NEXT:    cincoffset cs0, csp, 48
-; PURECAP-NEXT:    csc cs0, -48(cs0)
-; PURECAP-NEXT:    cmove ca0, cs0
-; PURECAP-NEXT:    clc cra, 32(csp) # 16-byte Folded Reload
-; PURECAP-NEXT:    clc cs0, 16(csp) # 16-byte Folded Reload
-; PURECAP-NEXT:    cincoffset csp, csp, 48
+; PURECAP-NEXT:    cincoffset sp, sp, -48
+; PURECAP-NEXT:    csc ra, 32(sp) # 16-byte Folded Spill
+; PURECAP-NEXT:    csc s0, 16(sp) # 16-byte Folded Spill
+; PURECAP-NEXT:    cincoffset s0, sp, 48
+; PURECAP-NEXT:    csc s0, -48(s0)
+; PURECAP-NEXT:    cmove a0, s0
+; PURECAP-NEXT:    clc ra, 32(sp) # 16-byte Folded Reload
+; PURECAP-NEXT:    clc s0, 16(sp) # 16-byte Folded Reload
+; PURECAP-NEXT:    cincoffset sp, sp, 48
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: frameaddr:
@@ -45,10 +45,10 @@ declare ptr addrspace(200) @llvm.frameaddress.p200(i32 immarg) addrspace(200)
 define dso_local ptr addrspace(200) @retaddr() addrspace(200) nounwind {
 ; PURECAP-LABEL: retaddr:
 ; PURECAP:       # %bb.0: # %entry
-; PURECAP-NEXT:    cincoffset csp, csp, -16
-; PURECAP-NEXT:    cmove ca0, cra
-; PURECAP-NEXT:    csc cra, 0(csp)
-; PURECAP-NEXT:    cincoffset csp, csp, 16
+; PURECAP-NEXT:    cincoffset sp, sp, -16
+; PURECAP-NEXT:    cmove a0, ra
+; PURECAP-NEXT:    csc ra, 0(sp)
+; PURECAP-NEXT:    cincoffset sp, sp, 16
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: retaddr:
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/strcpy-to-memcpy-no-tags.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/strcpy-to-memcpy-no-tags.ll
index b1799b55e698c..e2f965e3449b8 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/strcpy-to-memcpy-no-tags.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/strcpy-to-memcpy-no-tags.ll
@@ -22,17 +22,17 @@ define void @test_strcpy_to_memcpy(ptr addrspace(200) align 8 %dst) addrspace(20
 ; CHECK-ASM:       # %bb.0: # %entry
 ; CHECK-ASM-NEXT:  .LBB0_1: # %entry
 ; CHECK-ASM-NEXT:    # Label of block must be emitted
-; CHECK-ASM-NEXT:    auipcc ca1, %pcrel_hi(.LCPI0_0)
-; CHECK-ASM-NEXT:    cincoffset ca1, ca1, %pcrel_lo(.LBB0_1)
-; CHECK-ASM-NEXT:    cld a1, 0(ca1)
+; CHECK-ASM-NEXT:    auipcc a1, %pcrel_hi(.LCPI0_0)
+; CHECK-ASM-NEXT:    cincoffset a1, a1, %pcrel_lo(.LBB0_1)
+; CHECK-ASM-NEXT:    cld a1, 0(a1)
 ; CHECK-ASM-NEXT:  .LBB0_2: # %entry
 ; CHECK-ASM-NEXT:    # Label of block must be emitted
-; CHECK-ASM-NEXT:    auipcc ca2, %pcrel_hi(.LCPI0_1)
-; CHECK-ASM-NEXT:    cincoffset ca2, ca2, %pcrel_lo(.LBB0_2)
-; CHECK-ASM-NEXT:    cld a2, 0(ca2)
-; CHECK-ASM-NEXT:    csd a1, 8(ca0)
-; CHECK-ASM-NEXT:    csb zero, 16(ca0)
-; CHECK-ASM-NEXT:    csd a2, 0(ca0)
+; CHECK-ASM-NEXT:    auipcc a2, %pcrel_hi(.LCPI0_1)
+; CHECK-ASM-NEXT:    cincoffset a2, a2, %pcrel_lo(.LBB0_2)
+; CHECK-ASM-NEXT:    cld a2, 0(a2)
+; CHECK-ASM-NEXT:    csd a1, 8(a0)
+; CHECK-ASM-NEXT:    csb zero, 16(a0)
+; CHECK-ASM-NEXT:    csd a2, 0(a0)
 ; CHECK-ASM-NEXT:    cret
 ; CHECK-IR-LABEL: define void @test_strcpy_to_memcpy
 ; CHECK-IR-SAME: (ptr addrspace(200) align 8 [[DST:%.*]]) addrspace(200) #[[ATTR1:[0-9]+]] {
@@ -49,17 +49,17 @@ define void @test_stpcpy_to_memcpy(ptr addrspace(200) align 8 %dst) addrspace(20
 ; CHECK-ASM:       # %bb.0: # %entry
 ; CHECK-ASM-NEXT:  .LBB1_1: # %entry
 ; CHECK-ASM-NEXT:    # Label of block must be emitted
-; CHECK-ASM-NEXT:    auipcc ca1, %pcrel_hi(.LCPI1_0)
-; CHECK-ASM-NEXT:    cincoffset ca1, ca1, %pcrel_lo(.LBB1_1)
-; CHECK-ASM-NEXT:    cld a1, 0(ca1)
+; CHECK-ASM-NEXT:    auipcc a1, %pcrel_hi(.LCPI1_0)
+; CHECK-ASM-NEXT:    cincoffset a1, a1, %pcrel_lo(.LBB1_1)
+; CHECK-ASM-NEXT:    cld a1, 0(a1)
 ; CHECK-ASM-NEXT:  .LBB1_2: # %entry
 ; CHECK-ASM-NEXT:    # Label of block must be emitted
-; CHECK-ASM-NEXT:    auipcc ca2, %pcrel_hi(.LCPI1_1)
-; CHECK-ASM-NEXT:    cincoffset ca2, ca2, %pcrel_lo(.LBB1_2)
-; CHECK-ASM-NEXT:    cld a2, 0(ca2)
-; CHECK-ASM-NEXT:    csd a1, 8(ca0)
-; CHECK-ASM-NEXT:    csb zero, 16(ca0)
-; CHECK-ASM-NEXT:    csd a2, 0(ca0)
+; CHECK-ASM-NEXT:    auipcc a2, %pcrel_hi(.LCPI1_1)
+; CHECK-ASM-NEXT:    cincoffset a2, a2, %pcrel_lo(.LBB1_2)
+; CHECK-ASM-NEXT:    cld a2, 0(a2)
+; CHECK-ASM-NEXT:    csd a1, 8(a0)
+; CHECK-ASM-NEXT:    csb zero, 16(a0)
+; CHECK-ASM-NEXT:    csd a2, 0(a0)
 ; CHECK-ASM-NEXT:    cret
 ; CHECK-IR-LABEL: define void @test_stpcpy_to_memcpy
 ; CHECK-IR-SAME: (ptr addrspace(200) align 8 [[DST:%.*]]) addrspace(200) #[[ATTR1]] {
@@ -74,21 +74,21 @@ entry:
 define void @test_strcat_to_memcpy(ptr addrspace(200) align 8 %dst) addrspace(200) nounwind {
 ; CHECK-ASM-LABEL: test_strcat_to_memcpy:
 ; CHECK-ASM:       # %bb.0: # %entry
-; CHECK-ASM-NEXT:    cincoffset csp, csp, -32
-; CHECK-ASM-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; CHECK-ASM-NEXT:    csc cs0, 0(csp) # 16-byte Folded Spill
-; CHECK-ASM-NEXT:    cmove cs0, ca0
+; CHECK-ASM-NEXT:    cincoffset sp, sp, -32
+; CHECK-ASM-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; CHECK-ASM-NEXT:    csc s0, 0(sp) # 16-byte Folded Spill
+; CHECK-ASM-NEXT:    cmove s0, a0
 ; CHECK-ASM-NEXT:    ccall strlen
-; CHECK-ASM-NEXT:    cincoffset ca0, cs0, a0
+; CHECK-ASM-NEXT:    cincoffset a0, s0, a0
 ; CHECK-ASM-NEXT:  .LBB2_1: # %entry
 ; CHECK-ASM-NEXT:    # Label of block must be emitted
-; CHECK-ASM-NEXT:    auipcc ca1, %captab_pcrel_hi(.Lstr)
-; CHECK-ASM-NEXT:    clc ca1, %pcrel_lo(.LBB2_1)(ca1)
+; CHECK-ASM-NEXT:    auipcc a1, %captab_pcrel_hi(.Lstr)
+; CHECK-ASM-NEXT:    clc a1, %pcrel_lo(.LBB2_1)(a1)
 ; CHECK-ASM-NEXT:    li a2, 17
 ; CHECK-ASM-NEXT:    ccall memcpy
-; CHECK-ASM-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; CHECK-ASM-NEXT:    clc cs0, 0(csp) # 16-byte Folded Reload
-; CHECK-ASM-NEXT:    cincoffset csp, csp, 32
+; CHECK-ASM-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; CHECK-ASM-NEXT:    clc s0, 0(sp) # 16-byte Folded Reload
+; CHECK-ASM-NEXT:    cincoffset sp, sp, 32
 ; CHECK-ASM-NEXT:    cret
 ; CHECK-IR-LABEL: define void @test_strcat_to_memcpy
 ; CHECK-IR-SAME: (ptr addrspace(200) align 8 [[DST:%.*]]) addrspace(200) #[[ATTR1]] {
@@ -108,17 +108,17 @@ define void @test_strncpy_to_memcpy(ptr addrspace(200) align 8 %dst) addrspace(2
 ; CHECK-ASM:       # %bb.0: # %entry
 ; CHECK-ASM-NEXT:  .LBB3_1: # %entry
 ; CHECK-ASM-NEXT:    # Label of block must be emitted
-; CHECK-ASM-NEXT:    auipcc ca1, %pcrel_hi(.LCPI3_0)
-; CHECK-ASM-NEXT:    cincoffset ca1, ca1, %pcrel_lo(.LBB3_1)
-; CHECK-ASM-NEXT:    cld a1, 0(ca1)
+; CHECK-ASM-NEXT:    auipcc a1, %pcrel_hi(.LCPI3_0)
+; CHECK-ASM-NEXT:    cincoffset a1, a1, %pcrel_lo(.LBB3_1)
+; CHECK-ASM-NEXT:    cld a1, 0(a1)
 ; CHECK-ASM-NEXT:  .LBB3_2: # %entry
 ; CHECK-ASM-NEXT:    # Label of block must be emitted
-; CHECK-ASM-NEXT:    auipcc ca2, %pcrel_hi(.LCPI3_1)
-; CHECK-ASM-NEXT:    cincoffset ca2, ca2, %pcrel_lo(.LBB3_2)
-; CHECK-ASM-NEXT:    cld a2, 0(ca2)
-; CHECK-ASM-NEXT:    csd a1, 8(ca0)
-; CHECK-ASM-NEXT:    csb zero, 16(ca0)
-; CHECK-ASM-NEXT:    csd a2, 0(ca0)
+; CHECK-ASM-NEXT:    auipcc a2, %pcrel_hi(.LCPI3_1)
+; CHECK-ASM-NEXT:    cincoffset a2, a2, %pcrel_lo(.LBB3_2)
+; CHECK-ASM-NEXT:    cld a2, 0(a2)
+; CHECK-ASM-NEXT:    csd a1, 8(a0)
+; CHECK-ASM-NEXT:    csb zero, 16(a0)
+; CHECK-ASM-NEXT:    csd a2, 0(a0)
 ; CHECK-ASM-NEXT:    cret
 ; CHECK-IR-LABEL: define void @test_strncpy_to_memcpy
 ; CHECK-IR-SAME: (ptr addrspace(200) align 8 [[DST:%.*]]) addrspace(200) #[[ATTR1]] {
@@ -136,17 +136,17 @@ define void @test_stpncpy_to_memcpy(ptr addrspace(200) align 8 %dst) addrspace(2
 ; CHECK-ASM:       # %bb.0: # %entry
 ; CHECK-ASM-NEXT:  .LBB4_1: # %entry
 ; CHECK-ASM-NEXT:    # Label of block must be emitted
-; CHECK-ASM-NEXT:    auipcc ca1, %pcrel_hi(.LCPI4_0)
-; CHECK-ASM-NEXT:    cincoffset ca1, ca1, %pcrel_lo(.LBB4_1)
-; CHECK-ASM-NEXT:    cld a1, 0(ca1)
+; CHECK-ASM-NEXT:    auipcc a1, %pcrel_hi(.LCPI4_0)
+; CHECK-ASM-NEXT:    cincoffset a1, a1, %pcrel_lo(.LBB4_1)
+; CHECK-ASM-NEXT:    cld a1, 0(a1)
 ; CHECK-ASM-NEXT:  .LBB4_2: # %entry
 ; CHECK-ASM-NEXT:    # Label of block must be emitted
-; CHECK-ASM-NEXT:    auipcc ca2, %pcrel_hi(.LCPI4_1)
-; CHECK-ASM-NEXT:    cincoffset ca2, ca2, %pcrel_lo(.LBB4_2)
-; CHECK-ASM-NEXT:    cld a2, 0(ca2)
-; CHECK-ASM-NEXT:    csd a1, 8(ca0)
-; CHECK-ASM-NEXT:    csb zero, 16(ca0)
-; CHECK-ASM-NEXT:    csd a2, 0(ca0)
+; CHECK-ASM-NEXT:    auipcc a2, %pcrel_hi(.LCPI4_1)
+; CHECK-ASM-NEXT:    cincoffset a2, a2, %pcrel_lo(.LBB4_2)
+; CHECK-ASM-NEXT:    cld a2, 0(a2)
+; CHECK-ASM-NEXT:    csd a1, 8(a0)
+; CHECK-ASM-NEXT:    csb zero, 16(a0)
+; CHECK-ASM-NEXT:    csd a2, 0(a0)
 ; CHECK-ASM-NEXT:    cret
 ; CHECK-IR-LABEL: define void @test_stpncpy_to_memcpy
 ; CHECK-IR-SAME: (ptr addrspace(200) align 8 [[DST:%.*]]) addrspace(200) #[[ATTR1]] {
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/subobject-bounds-redundant-setbounds.c.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/subobject-bounds-redundant-setbounds.c.ll
index e51e3e2dce577..3e653d5d0adac 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/subobject-bounds-redundant-setbounds.c.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/subobject-bounds-redundant-setbounds.c.ll
@@ -38,7 +38,7 @@ define void @use_inline(ptr addrspace(200) captures(none) %arg) local_unnamed_ad
 ; ASM-LABEL: use_inline:
 ; ASM:       # %bb.0:
 ; ASM-NEXT:    li a1, 2
-; ASM-NEXT:    csw a1, 0(ca0)
+; ASM-NEXT:    csw a1, 0(a0)
 ; ASM-NEXT:    cret
 ; CHECK-LABEL: define {{[^@]+}}@use_inline
 ; CHECK-SAME: (ptr addrspace(200) captures(none) [[ARG:%.*]]) local_unnamed_addr addrspace(200) #[[ATTR0:[0-9]+]] {
@@ -51,17 +51,17 @@ define void @use_inline(ptr addrspace(200) captures(none) %arg) local_unnamed_ad
 define signext i32 @stack_array() local_unnamed_addr addrspace(200) nounwind {
 ; ASM-LABEL: stack_array:
 ; ASM:       # %bb.0:
-; ASM-NEXT:    cincoffset csp, csp, -80
-; ASM-NEXT:    csc cra, 64(csp) # 16-byte Folded Spill
-; ASM-NEXT:    csc cs0, 48(csp) # 16-byte Folded Spill
-; ASM-NEXT:    cincoffset ca0, csp, 8
-; ASM-NEXT:    csetbounds cs0, ca0, 40
-; ASM-NEXT:    cmove ca0, cs0
+; ASM-NEXT:    cincoffset sp, sp, -80
+; ASM-NEXT:    csc ra, 64(sp) # 16-byte Folded Spill
+; ASM-NEXT:    csc s0, 48(sp) # 16-byte Folded Spill
+; ASM-NEXT:    cincoffset a0, sp, 8
+; ASM-NEXT:    csetbounds s0, a0, 40
+; ASM-NEXT:    cmove a0, s0
 ; ASM-NEXT:    ccall use
-; ASM-NEXT:    clw a0, 20(cs0)
-; ASM-NEXT:    clc cra, 64(csp) # 16-byte Folded Reload
-; ASM-NEXT:    clc cs0, 48(csp) # 16-byte Folded Reload
-; ASM-NEXT:    cincoffset csp, csp, 80
+; ASM-NEXT:    clw a0, 20(s0)
+; ASM-NEXT:    clc ra, 64(sp) # 16-byte Folded Reload
+; ASM-NEXT:    clc s0, 48(sp) # 16-byte Folded Reload
+; ASM-NEXT:    cincoffset sp, sp, 80
 ; ASM-NEXT:    cret
 ; CHECK-LABEL: define signext i32 @stack_array
 ; CHECK-SAME: () local_unnamed_addr addrspace(200) #[[ATTR1:[0-9]+]] {
@@ -102,16 +102,16 @@ declare void @llvm.lifetime.end.p200(i64 immarg, ptr addrspace(200) captures(non
 define signext i32 @stack_int() local_unnamed_addr addrspace(200) nounwind {
 ; ASM-LABEL: stack_int:
 ; ASM:       # %bb.0:
-; ASM-NEXT:    cincoffset csp, csp, -32
-; ASM-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
+; ASM-NEXT:    cincoffset sp, sp, -32
+; ASM-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
 ; ASM-NEXT:    li a0, 1
-; ASM-NEXT:    csw a0, 12(csp)
-; ASM-NEXT:    cincoffset ca0, csp, 12
-; ASM-NEXT:    csetbounds ca0, ca0, 4
+; ASM-NEXT:    csw a0, 12(sp)
+; ASM-NEXT:    cincoffset a0, sp, 12
+; ASM-NEXT:    csetbounds a0, a0, 4
 ; ASM-NEXT:    ccall use
-; ASM-NEXT:    clw a0, 12(csp)
-; ASM-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; ASM-NEXT:    cincoffset csp, csp, 32
+; ASM-NEXT:    clw a0, 12(sp)
+; ASM-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; ASM-NEXT:    cincoffset sp, sp, 32
 ; ASM-NEXT:    cret
 ; CHECK-LABEL: define signext i32 @stack_int
 ; CHECK-SAME: () local_unnamed_addr addrspace(200) #[[ATTR1]] {
@@ -150,15 +150,15 @@ define signext i32 @stack_int() local_unnamed_addr addrspace(200) nounwind {
 define signext i32 @stack_int_inlined() local_unnamed_addr addrspace(200) nounwind {
 ; ASM-LABEL: stack_int_inlined:
 ; ASM:       # %bb.0:
-; ASM-NEXT:    cincoffset csp, csp, -16
+; ASM-NEXT:    cincoffset sp, sp, -16
 ; ASM-NEXT:    li a0, 1
-; ASM-NEXT:    cincoffset ca1, csp, 12
-; ASM-NEXT:    csw a0, 12(csp)
-; ASM-NEXT:    csetbounds ca0, ca1, 4
+; ASM-NEXT:    cincoffset a1, sp, 12
+; ASM-NEXT:    csw a0, 12(sp)
+; ASM-NEXT:    csetbounds a0, a1, 4
 ; ASM-NEXT:    li a1, 2
-; ASM-NEXT:    csw a1, 0(ca0)
-; ASM-NEXT:    clw a0, 12(csp)
-; ASM-NEXT:    cincoffset csp, csp, 16
+; ASM-NEXT:    csw a1, 0(a0)
+; ASM-NEXT:    clw a0, 12(sp)
+; ASM-NEXT:    cincoffset sp, sp, 16
 ; ASM-NEXT:    cret
 ; CHECK-LABEL: define signext i32 @stack_int_inlined
 ; CHECK-SAME: () local_unnamed_addr addrspace(200) #[[ATTR1]] {
@@ -197,14 +197,14 @@ define signext i32 @stack_int_inlined() local_unnamed_addr addrspace(200) nounwi
 define signext i32 @out_of_bounds_setbounds() local_unnamed_addr addrspace(200) nounwind {
 ; ASM-LABEL: out_of_bounds_setbounds:
 ; ASM:       # %bb.0:
-; ASM-NEXT:    cincoffset csp, csp, -16
-; ASM-NEXT:    cincoffset ca0, csp, 12
-; ASM-NEXT:    csetbounds ca0, ca0, 4
-; ASM-NEXT:    csetbounds ca0, ca0, 5
+; ASM-NEXT:    cincoffset sp, sp, -16
+; ASM-NEXT:    cincoffset a0, sp, 12
+; ASM-NEXT:    csetbounds a0, a0, 4
+; ASM-NEXT:    csetbounds a0, a0, 5
 ; ASM-NEXT:    li a1, 2
-; ASM-NEXT:    csw a1, 0(ca0)
-; ASM-NEXT:    clw a0, 12(csp)
-; ASM-NEXT:    cincoffset csp, csp, 16
+; ASM-NEXT:    csw a1, 0(a0)
+; ASM-NEXT:    clw a0, 12(sp)
+; ASM-NEXT:    cincoffset sp, sp, 16
 ; ASM-NEXT:    cret
 ; CHECK-LABEL: define signext i32 @out_of_bounds_setbounds
 ; CHECK-SAME: () local_unnamed_addr addrspace(200) #[[ATTR1]] {
@@ -235,16 +235,16 @@ define signext i32 @out_of_bounds_setbounds() local_unnamed_addr addrspace(200)
 define signext i32 @setbounds_escapes() local_unnamed_addr addrspace(200) nounwind {
 ; ASM-LABEL: setbounds_escapes:
 ; ASM:       # %bb.0:
-; ASM-NEXT:    cincoffset csp, csp, -32
-; ASM-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; ASM-NEXT:    cincoffset ca0, csp, 12
-; ASM-NEXT:    csetbounds ca0, ca0, 4
+; ASM-NEXT:    cincoffset sp, sp, -32
+; ASM-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; ASM-NEXT:    cincoffset a0, sp, 12
+; ASM-NEXT:    csetbounds a0, a0, 4
 ; ASM-NEXT:    li a1, 2
-; ASM-NEXT:    csw a1, 0(ca0)
+; ASM-NEXT:    csw a1, 0(a0)
 ; ASM-NEXT:    ccall use
-; ASM-NEXT:    clw a0, 12(csp)
-; ASM-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; ASM-NEXT:    cincoffset csp, csp, 32
+; ASM-NEXT:    clw a0, 12(sp)
+; ASM-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; ASM-NEXT:    cincoffset sp, sp, 32
 ; ASM-NEXT:    cret
 ; CHECK-LABEL: define signext i32 @setbounds_escapes
 ; CHECK-SAME: () local_unnamed_addr addrspace(200) #[[ATTR1]] {
@@ -276,10 +276,10 @@ define signext i32 @setbounds_escapes() local_unnamed_addr addrspace(200) nounwi
 define void @assume_aligned() local_unnamed_addr addrspace(200) nounwind {
 ; ASM-LABEL: assume_aligned:
 ; ASM:       # %bb.0:
-; ASM-NEXT:    cincoffset csp, csp, -16
+; ASM-NEXT:    cincoffset sp, sp, -16
 ; ASM-NEXT:    li a0, 1
-; ASM-NEXT:    csw a0, 12(csp)
-; ASM-NEXT:    cincoffset csp, csp, 16
+; ASM-NEXT:    csw a0, 12(sp)
+; ASM-NEXT:    cincoffset sp, sp, 16
 ; ASM-NEXT:    cret
 ; CHECK-LABEL: define void @assume_aligned
 ; CHECK-SAME: () local_unnamed_addr addrspace(200) #[[ATTR1]] {
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/trunc-load.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/trunc-load.ll
index 1e8cd650ed7e3..92e74ad2598bd 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/trunc-load.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/trunc-load.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --scrub-attributes --version 2
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
 ; DO NOT EDIT -- This file was generated from test/CodeGen/CHERI-Generic/Inputs/trunc-load.ll
 ; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+xcheripurecap,+f,+d %s -o - < %s | FileCheck %s --check-prefix=PURECAP
 ; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi lp64d -mattr=+xcheri,+f,+d -o - < %s | FileCheck %s --check-prefix=HYBRID
@@ -6,12 +6,12 @@
 define zeroext i16 @trunc_load_zext(i32 addrspace(200)* %p) {
 ; PURECAP-LABEL: trunc_load_zext:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    clhu a0, 0(ca0)
+; PURECAP-NEXT:    clhu a0, 0(a0)
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: trunc_load_zext:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    lhu.cap a0, (ca0)
+; HYBRID-NEXT:    lhu.cap a0, (a0)
 ; HYBRID-NEXT:    ret
   %1 = load i32, i32 addrspace(200)* %p
   %2 = trunc i32 %1 to i16
@@ -21,12 +21,12 @@ define zeroext i16 @trunc_load_zext(i32 addrspace(200)* %p) {
 define signext i16 @trunc_load_sext(i32 addrspace(200)* %p) {
 ; PURECAP-LABEL: trunc_load_sext:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    clh a0, 0(ca0)
+; PURECAP-NEXT:    clh a0, 0(a0)
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: trunc_load_sext:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    lh.cap a0, (ca0)
+; HYBRID-NEXT:    lh.cap a0, (a0)
 ; HYBRID-NEXT:    ret
   %1 = load i32, i32 addrspace(200)* %p
   %2 = trunc i32 %1 to i16
@@ -36,13 +36,13 @@ define signext i16 @trunc_load_sext(i32 addrspace(200)* %p) {
 define zeroext i16 @trunc_load_gep_zext(i32 addrspace(200)* %p) {
 ; PURECAP-LABEL: trunc_load_gep_zext:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    clhu a0, 4(ca0)
+; PURECAP-NEXT:    clhu a0, 4(a0)
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: trunc_load_gep_zext:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    cincoffset ca0, ca0, 4
-; HYBRID-NEXT:    lhu.cap a0, (ca0)
+; HYBRID-NEXT:    cincoffset a0, a0, 4
+; HYBRID-NEXT:    lhu.cap a0, (a0)
 ; HYBRID-NEXT:    ret
   %1 = getelementptr i32, i32 addrspace(200)* %p, i64 1
   %2 = load i32, i32 addrspace(200)* %1
@@ -53,13 +53,13 @@ define zeroext i16 @trunc_load_gep_zext(i32 addrspace(200)* %p) {
 define signext i16 @trunc_load_gep_sext(i32 addrspace(200)* %p) {
 ; PURECAP-LABEL: trunc_load_gep_sext:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    clh a0, 4(ca0)
+; PURECAP-NEXT:    clh a0, 4(a0)
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: trunc_load_gep_sext:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    cincoffset ca0, ca0, 4
-; HYBRID-NEXT:    lh.cap a0, (ca0)
+; HYBRID-NEXT:    cincoffset a0, a0, 4
+; HYBRID-NEXT:    lh.cap a0, (a0)
 ; HYBRID-NEXT:    ret
   %1 = getelementptr i32, i32 addrspace(200)* %p, i64 1
   %2 = load i32, i32 addrspace(200)* %1
@@ -70,13 +70,13 @@ define signext i16 @trunc_load_gep_sext(i32 addrspace(200)* %p) {
 define zeroext i16 @trunc_lshr_load_zext(i32 addrspace(200)* %p) {
 ; PURECAP-LABEL: trunc_lshr_load_zext:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    clhu a0, 2(ca0)
+; PURECAP-NEXT:    clhu a0, 2(a0)
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: trunc_lshr_load_zext:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    cincoffset ca0, ca0, 2
-; HYBRID-NEXT:    lhu.cap a0, (ca0)
+; HYBRID-NEXT:    cincoffset a0, a0, 2
+; HYBRID-NEXT:    lhu.cap a0, (a0)
 ; HYBRID-NEXT:    ret
   %1 = load i32, i32 addrspace(200)* %p
   %2 = lshr i32 %1, 16
@@ -87,13 +87,13 @@ define zeroext i16 @trunc_lshr_load_zext(i32 addrspace(200)* %p) {
 define signext i16 @trunc_lshr_load_sext(i32 addrspace(200)* %p) {
 ; PURECAP-LABEL: trunc_lshr_load_sext:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    clh a0, 2(ca0)
+; PURECAP-NEXT:    clh a0, 2(a0)
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: trunc_lshr_load_sext:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    cincoffset ca0, ca0, 2
-; HYBRID-NEXT:    lh.cap a0, (ca0)
+; HYBRID-NEXT:    cincoffset a0, a0, 2
+; HYBRID-NEXT:    lh.cap a0, (a0)
 ; HYBRID-NEXT:    ret
   %1 = load i32, i32 addrspace(200)* %p
   %2 = lshr i32 %1, 16
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/unaligned-loads-stores-hybrid.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/unaligned-loads-stores-hybrid.ll
index 08a047319ab3a..5fec206cf0aa1 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/unaligned-loads-stores-hybrid.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/unaligned-loads-stores-hybrid.ll
@@ -13,34 +13,34 @@ define i64 @load_global_i64_align_1(i64 %y) addrspace(200) nounwind {
 ; CHECK-NEXT:  .Lpcrel_hi0:
 ; CHECK-NEXT:    auipc a0, %got_pcrel_hi(a1)
 ; CHECK-NEXT:    ld a0, %pcrel_lo(.Lpcrel_hi0)(a0)
-; CHECK-NEXT:    cspecialr ca1, ddc
+; CHECK-NEXT:    cspecialr a1, ddc
 ; CHECK-NEXT:    bnez a0, .LBB0_2
 ; CHECK-NEXT:  # %bb.1:
-; CHECK-NEXT:    cmove ca0, cnull
+; CHECK-NEXT:    cmove a0, zero
 ; CHECK-NEXT:    j .LBB0_3
 ; CHECK-NEXT:  .LBB0_2:
-; CHECK-NEXT:    csetaddr ca0, ca1, a0
+; CHECK-NEXT:    csetaddr a0, a1, a0
 ; CHECK-NEXT:  .LBB0_3:
-; CHECK-NEXT:    lbu.cap a1, (ca0)
-; CHECK-NEXT:    cincoffset ca2, ca0, 1
-; CHECK-NEXT:    cincoffset ca3, ca0, 2
-; CHECK-NEXT:    cincoffset ca4, ca0, 3
-; CHECK-NEXT:    lbu.cap a2, (ca2)
-; CHECK-NEXT:    cincoffset ca5, ca0, 4
-; CHECK-NEXT:    lbu.cap a3, (ca3)
-; CHECK-NEXT:    lbu.cap a4, (ca4)
+; CHECK-NEXT:    lbu.cap a1, (a0)
+; CHECK-NEXT:    cincoffset a2, a0, 1
+; CHECK-NEXT:    cincoffset a3, a0, 2
+; CHECK-NEXT:    cincoffset a4, a0, 3
+; CHECK-NEXT:    lbu.cap a2, (a2)
+; CHECK-NEXT:    cincoffset a5, a0, 4
+; CHECK-NEXT:    lbu.cap a3, (a3)
+; CHECK-NEXT:    lbu.cap a4, (a4)
 ; CHECK-NEXT:    slli a2, a2, 8
 ; CHECK-NEXT:    or a1, a2, a1
-; CHECK-NEXT:    cincoffset ca2, ca0, 5
+; CHECK-NEXT:    cincoffset a2, a0, 5
 ; CHECK-NEXT:    slli a3, a3, 16
 ; CHECK-NEXT:    slli a4, a4, 24
 ; CHECK-NEXT:    or a3, a4, a3
-; CHECK-NEXT:    cincoffset ca4, ca0, 6
-; CHECK-NEXT:    cincoffset ca0, ca0, 7
-; CHECK-NEXT:    lbu.cap a2, (ca2)
-; CHECK-NEXT:    lbu.cap a5, (ca5)
-; CHECK-NEXT:    lbu.cap a4, (ca4)
-; CHECK-NEXT:    lbu.cap a0, (ca0)
+; CHECK-NEXT:    cincoffset a4, a0, 6
+; CHECK-NEXT:    cincoffset a0, a0, 7
+; CHECK-NEXT:    lbu.cap a2, (a2)
+; CHECK-NEXT:    lbu.cap a5, (a5)
+; CHECK-NEXT:    lbu.cap a4, (a4)
+; CHECK-NEXT:    lbu.cap a0, (a0)
 ; CHECK-NEXT:    slli a2, a2, 8
 ; CHECK-NEXT:    or a2, a2, a5
 ; CHECK-NEXT:    slli a4, a4, 16
@@ -61,21 +61,21 @@ define i64 @load_global_i64_align_2(i64 %y) addrspace(200) nounwind {
 ; CHECK-NEXT:  .Lpcrel_hi1:
 ; CHECK-NEXT:    auipc a0, %got_pcrel_hi(a2)
 ; CHECK-NEXT:    ld a0, %pcrel_lo(.Lpcrel_hi1)(a0)
-; CHECK-NEXT:    cspecialr ca1, ddc
+; CHECK-NEXT:    cspecialr a1, ddc
 ; CHECK-NEXT:    bnez a0, .LBB1_2
 ; CHECK-NEXT:  # %bb.1:
-; CHECK-NEXT:    cmove ca0, cnull
+; CHECK-NEXT:    cmove a0, zero
 ; CHECK-NEXT:    j .LBB1_3
 ; CHECK-NEXT:  .LBB1_2:
-; CHECK-NEXT:    csetaddr ca0, ca1, a0
+; CHECK-NEXT:    csetaddr a0, a1, a0
 ; CHECK-NEXT:  .LBB1_3:
-; CHECK-NEXT:    lhu.cap a1, (ca0)
-; CHECK-NEXT:    cincoffset ca2, ca0, 2
-; CHECK-NEXT:    cincoffset ca3, ca0, 4
-; CHECK-NEXT:    lhu.cap a2, (ca2)
-; CHECK-NEXT:    cincoffset ca0, ca0, 6
-; CHECK-NEXT:    lhu.cap a3, (ca3)
-; CHECK-NEXT:    lhu.cap a0, (ca0)
+; CHECK-NEXT:    lhu.cap a1, (a0)
+; CHECK-NEXT:    cincoffset a2, a0, 2
+; CHECK-NEXT:    cincoffset a3, a0, 4
+; CHECK-NEXT:    lhu.cap a2, (a2)
+; CHECK-NEXT:    cincoffset a0, a0, 6
+; CHECK-NEXT:    lhu.cap a3, (a3)
+; CHECK-NEXT:    lhu.cap a0, (a0)
 ; CHECK-NEXT:    slli a2, a2, 16
 ; CHECK-NEXT:    or a1, a2, a1
 ; CHECK-NEXT:    slli a3, a3, 32
@@ -93,17 +93,17 @@ define i64 @load_global_i64_align_4(i64 %y) addrspace(200) nounwind {
 ; CHECK-NEXT:  .Lpcrel_hi2:
 ; CHECK-NEXT:    auipc a0, %got_pcrel_hi(a4)
 ; CHECK-NEXT:    ld a0, %pcrel_lo(.Lpcrel_hi2)(a0)
-; CHECK-NEXT:    cspecialr ca1, ddc
+; CHECK-NEXT:    cspecialr a1, ddc
 ; CHECK-NEXT:    bnez a0, .LBB2_2
 ; CHECK-NEXT:  # %bb.1:
-; CHECK-NEXT:    cmove ca0, cnull
+; CHECK-NEXT:    cmove a0, zero
 ; CHECK-NEXT:    j .LBB2_3
 ; CHECK-NEXT:  .LBB2_2:
-; CHECK-NEXT:    csetaddr ca0, ca1, a0
+; CHECK-NEXT:    csetaddr a0, a1, a0
 ; CHECK-NEXT:  .LBB2_3:
-; CHECK-NEXT:    cincoffset ca1, ca0, 4
-; CHECK-NEXT:    lwu.cap a1, (ca1)
-; CHECK-NEXT:    lwu.cap a0, (ca0)
+; CHECK-NEXT:    cincoffset a1, a0, 4
+; CHECK-NEXT:    lwu.cap a1, (a1)
+; CHECK-NEXT:    lwu.cap a0, (a0)
 ; CHECK-NEXT:    slli a1, a1, 32
 ; CHECK-NEXT:    or a0, a1, a0
 ; CHECK-NEXT:    ret
@@ -117,14 +117,14 @@ define i64 @load_global_i64_align_8(i64 %y) addrspace(200) nounwind {
 ; CHECK-NEXT:  .Lpcrel_hi3:
 ; CHECK-NEXT:    auipc a0, %got_pcrel_hi(a8)
 ; CHECK-NEXT:    ld a0, %pcrel_lo(.Lpcrel_hi3)(a0)
-; CHECK-NEXT:    cspecialr ca1, ddc
+; CHECK-NEXT:    cspecialr a1, ddc
 ; CHECK-NEXT:    bnez a0, .LBB3_2
 ; CHECK-NEXT:  # %bb.1:
-; CHECK-NEXT:    ld.cap a0, (cnull)
+; CHECK-NEXT:    ld.cap a0, (zero)
 ; CHECK-NEXT:    ret
 ; CHECK-NEXT:  .LBB3_2:
-; CHECK-NEXT:    csetaddr ca0, ca1, a0
-; CHECK-NEXT:    ld.cap a0, (ca0)
+; CHECK-NEXT:    csetaddr a0, a1, a0
+; CHECK-NEXT:    ld.cap a0, (a0)
 ; CHECK-NEXT:    ret
   %ret = load i64, i64 addrspace(200)* addrspacecast(i64* @a8 to i64 addrspace(200)*), align 8
   ret i64 %ret
@@ -136,36 +136,36 @@ define void @store_global_i64_align_1(i64 %y) addrspace(200) nounwind {
 ; CHECK-NEXT:  .Lpcrel_hi4:
 ; CHECK-NEXT:    auipc a1, %got_pcrel_hi(a1)
 ; CHECK-NEXT:    ld a1, %pcrel_lo(.Lpcrel_hi4)(a1)
-; CHECK-NEXT:    cspecialr ca2, ddc
+; CHECK-NEXT:    cspecialr a2, ddc
 ; CHECK-NEXT:    bnez a1, .LBB4_2
 ; CHECK-NEXT:  # %bb.1:
-; CHECK-NEXT:    cmove ca1, cnull
+; CHECK-NEXT:    cmove a1, zero
 ; CHECK-NEXT:    j .LBB4_3
 ; CHECK-NEXT:  .LBB4_2:
-; CHECK-NEXT:    csetaddr ca1, ca2, a1
+; CHECK-NEXT:    csetaddr a1, a2, a1
 ; CHECK-NEXT:  .LBB4_3:
-; CHECK-NEXT:    sb.cap a0, (ca1)
-; CHECK-NEXT:    cincoffset ca2, ca1, 7
+; CHECK-NEXT:    sb.cap a0, (a1)
+; CHECK-NEXT:    cincoffset a2, a1, 7
 ; CHECK-NEXT:    srli a3, a0, 56
-; CHECK-NEXT:    sb.cap a3, (ca2)
-; CHECK-NEXT:    cincoffset ca2, ca1, 6
+; CHECK-NEXT:    sb.cap a3, (a2)
+; CHECK-NEXT:    cincoffset a2, a1, 6
 ; CHECK-NEXT:    srli a3, a0, 48
-; CHECK-NEXT:    sb.cap a3, (ca2)
-; CHECK-NEXT:    cincoffset ca2, ca1, 5
+; CHECK-NEXT:    sb.cap a3, (a2)
+; CHECK-NEXT:    cincoffset a2, a1, 5
 ; CHECK-NEXT:    srli a3, a0, 40
-; CHECK-NEXT:    sb.cap a3, (ca2)
-; CHECK-NEXT:    cincoffset ca2, ca1, 4
+; CHECK-NEXT:    sb.cap a3, (a2)
+; CHECK-NEXT:    cincoffset a2, a1, 4
 ; CHECK-NEXT:    srli a3, a0, 32
-; CHECK-NEXT:    sb.cap a3, (ca2)
-; CHECK-NEXT:    cincoffset ca2, ca1, 3
+; CHECK-NEXT:    sb.cap a3, (a2)
+; CHECK-NEXT:    cincoffset a2, a1, 3
 ; CHECK-NEXT:    srli a3, a0, 24
-; CHECK-NEXT:    sb.cap a3, (ca2)
-; CHECK-NEXT:    cincoffset ca2, ca1, 2
+; CHECK-NEXT:    sb.cap a3, (a2)
+; CHECK-NEXT:    cincoffset a2, a1, 2
 ; CHECK-NEXT:    srli a3, a0, 16
-; CHECK-NEXT:    cincoffset ca1, ca1, 1
+; CHECK-NEXT:    cincoffset a1, a1, 1
 ; CHECK-NEXT:    srli a0, a0, 8
-; CHECK-NEXT:    sb.cap a3, (ca2)
-; CHECK-NEXT:    sb.cap a0, (ca1)
+; CHECK-NEXT:    sb.cap a3, (a2)
+; CHECK-NEXT:    sb.cap a0, (a1)
 ; CHECK-NEXT:    ret
   store i64 %y, i64 addrspace(200)* addrspacecast(i64* @a1 to i64 addrspace(200)*), align 1
   ret void
@@ -177,24 +177,24 @@ define void @store_global_i64_align_2(i64 %y) addrspace(200) nounwind {
 ; CHECK-NEXT:  .Lpcrel_hi5:
 ; CHECK-NEXT:    auipc a1, %got_pcrel_hi(a2)
 ; CHECK-NEXT:    ld a1, %pcrel_lo(.Lpcrel_hi5)(a1)
-; CHECK-NEXT:    cspecialr ca2, ddc
+; CHECK-NEXT:    cspecialr a2, ddc
 ; CHECK-NEXT:    bnez a1, .LBB5_2
 ; CHECK-NEXT:  # %bb.1:
-; CHECK-NEXT:    cmove ca1, cnull
+; CHECK-NEXT:    cmove a1, zero
 ; CHECK-NEXT:    j .LBB5_3
 ; CHECK-NEXT:  .LBB5_2:
-; CHECK-NEXT:    csetaddr ca1, ca2, a1
+; CHECK-NEXT:    csetaddr a1, a2, a1
 ; CHECK-NEXT:  .LBB5_3:
-; CHECK-NEXT:    sh.cap a0, (ca1)
-; CHECK-NEXT:    cincoffset ca2, ca1, 6
+; CHECK-NEXT:    sh.cap a0, (a1)
+; CHECK-NEXT:    cincoffset a2, a1, 6
 ; CHECK-NEXT:    srli a3, a0, 48
-; CHECK-NEXT:    sh.cap a3, (ca2)
-; CHECK-NEXT:    cincoffset ca2, ca1, 4
+; CHECK-NEXT:    sh.cap a3, (a2)
+; CHECK-NEXT:    cincoffset a2, a1, 4
 ; CHECK-NEXT:    srli a3, a0, 32
-; CHECK-NEXT:    cincoffset ca1, ca1, 2
+; CHECK-NEXT:    cincoffset a1, a1, 2
 ; CHECK-NEXT:    srli a0, a0, 16
-; CHECK-NEXT:    sh.cap a3, (ca2)
-; CHECK-NEXT:    sh.cap a0, (ca1)
+; CHECK-NEXT:    sh.cap a3, (a2)
+; CHECK-NEXT:    sh.cap a0, (a1)
 ; CHECK-NEXT:    ret
   store i64 %y, i64 addrspace(200)* addrspacecast(i64* @a2 to i64 addrspace(200)*), align 2
   ret void
@@ -206,18 +206,18 @@ define void @store_global_i64_align_4(i64 %y) addrspace(200) nounwind {
 ; CHECK-NEXT:  .Lpcrel_hi6:
 ; CHECK-NEXT:    auipc a1, %got_pcrel_hi(a4)
 ; CHECK-NEXT:    ld a1, %pcrel_lo(.Lpcrel_hi6)(a1)
-; CHECK-NEXT:    cspecialr ca2, ddc
+; CHECK-NEXT:    cspecialr a2, ddc
 ; CHECK-NEXT:    bnez a1, .LBB6_2
 ; CHECK-NEXT:  # %bb.1:
-; CHECK-NEXT:    cmove ca1, cnull
+; CHECK-NEXT:    cmove a1, zero
 ; CHECK-NEXT:    j .LBB6_3
 ; CHECK-NEXT:  .LBB6_2:
-; CHECK-NEXT:    csetaddr ca1, ca2, a1
+; CHECK-NEXT:    csetaddr a1, a2, a1
 ; CHECK-NEXT:  .LBB6_3:
-; CHECK-NEXT:    sw.cap a0, (ca1)
-; CHECK-NEXT:    cincoffset ca1, ca1, 4
+; CHECK-NEXT:    sw.cap a0, (a1)
+; CHECK-NEXT:    cincoffset a1, a1, 4
 ; CHECK-NEXT:    srli a0, a0, 32
-; CHECK-NEXT:    sw.cap a0, (ca1)
+; CHECK-NEXT:    sw.cap a0, (a1)
 ; CHECK-NEXT:    ret
   store i64 %y, i64 addrspace(200)* addrspacecast(i64* @a4 to i64 addrspace(200)*), align 4
   ret void
@@ -229,14 +229,14 @@ define void @store_global_i64_align_8(i64 %y) addrspace(200) nounwind {
 ; CHECK-NEXT:  .Lpcrel_hi7:
 ; CHECK-NEXT:    auipc a1, %got_pcrel_hi(a8)
 ; CHECK-NEXT:    ld a1, %pcrel_lo(.Lpcrel_hi7)(a1)
-; CHECK-NEXT:    cspecialr ca2, ddc
+; CHECK-NEXT:    cspecialr a2, ddc
 ; CHECK-NEXT:    bnez a1, .LBB7_2
 ; CHECK-NEXT:  # %bb.1:
-; CHECK-NEXT:    sd.cap a0, (cnull)
+; CHECK-NEXT:    sd.cap a0, (zero)
 ; CHECK-NEXT:    ret
 ; CHECK-NEXT:  .LBB7_2:
-; CHECK-NEXT:    csetaddr ca1, ca2, a1
-; CHECK-NEXT:    sd.cap a0, (ca1)
+; CHECK-NEXT:    csetaddr a1, a2, a1
+; CHECK-NEXT:    sd.cap a0, (a1)
 ; CHECK-NEXT:    ret
   store i64 %y, i64 addrspace(200)* addrspacecast(i64* @a8 to i64 addrspace(200)*), align 8
   ret void
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/unaligned-loads-stores-purecap.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/unaligned-loads-stores-purecap.ll
index be1f0a74fdb4b..fd06c66749db4 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/unaligned-loads-stores-purecap.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/unaligned-loads-stores-purecap.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --scrub-attributes --version 2
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
 ; DO NOT EDIT -- This file was generated from test/CodeGen/CHERI-Generic/Inputs/unaligned-loads-stores-purecap.ll
 ; RUN: llc -mtriple=riscv64 --relocation-model=pic -target-abi l64pc128d -mattr=+xcheri,+xcheripurecap,+f,+d %s -o - | FileCheck %s
 
@@ -11,21 +11,21 @@ define i64 @load_global_i64_align_1(i64 %y) addrspace(200) nounwind {
 ; CHECK-LABEL: load_global_i64_align_1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:  .LBB0_1: # Label of block must be emitted
-; CHECK-NEXT:    auipcc ca0, %captab_pcrel_hi(a1)
-; CHECK-NEXT:    clc ca0, %pcrel_lo(.LBB0_1)(ca0)
-; CHECK-NEXT:    clbu a1, 0(ca0)
-; CHECK-NEXT:    clbu a2, 1(ca0)
-; CHECK-NEXT:    clbu a3, 2(ca0)
-; CHECK-NEXT:    clbu a4, 3(ca0)
-; CHECK-NEXT:    clbu a5, 4(ca0)
+; CHECK-NEXT:    auipcc a0, %captab_pcrel_hi(a1)
+; CHECK-NEXT:    clc a0, %pcrel_lo(.LBB0_1)(a0)
+; CHECK-NEXT:    clbu a1, 0(a0)
+; CHECK-NEXT:    clbu a2, 1(a0)
+; CHECK-NEXT:    clbu a3, 2(a0)
+; CHECK-NEXT:    clbu a4, 3(a0)
+; CHECK-NEXT:    clbu a5, 4(a0)
 ; CHECK-NEXT:    slli a2, a2, 8
 ; CHECK-NEXT:    or a1, a2, a1
-; CHECK-NEXT:    clbu a2, 5(ca0)
+; CHECK-NEXT:    clbu a2, 5(a0)
 ; CHECK-NEXT:    slli a3, a3, 16
 ; CHECK-NEXT:    slli a4, a4, 24
 ; CHECK-NEXT:    or a3, a4, a3
-; CHECK-NEXT:    clbu a4, 6(ca0)
-; CHECK-NEXT:    clbu a0, 7(ca0)
+; CHECK-NEXT:    clbu a4, 6(a0)
+; CHECK-NEXT:    clbu a0, 7(a0)
 ; CHECK-NEXT:    slli a2, a2, 8
 ; CHECK-NEXT:    or a2, a2, a5
 ; CHECK-NEXT:    slli a4, a4, 16
@@ -44,12 +44,12 @@ define i64 @load_global_i64_align_2(i64 %y) addrspace(200) nounwind {
 ; CHECK-LABEL: load_global_i64_align_2:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:  .LBB1_1: # Label of block must be emitted
-; CHECK-NEXT:    auipcc ca0, %captab_pcrel_hi(a2)
-; CHECK-NEXT:    clc ca0, %pcrel_lo(.LBB1_1)(ca0)
-; CHECK-NEXT:    clhu a1, 2(ca0)
-; CHECK-NEXT:    clhu a2, 0(ca0)
-; CHECK-NEXT:    clhu a3, 4(ca0)
-; CHECK-NEXT:    clhu a0, 6(ca0)
+; CHECK-NEXT:    auipcc a0, %captab_pcrel_hi(a2)
+; CHECK-NEXT:    clc a0, %pcrel_lo(.LBB1_1)(a0)
+; CHECK-NEXT:    clhu a1, 2(a0)
+; CHECK-NEXT:    clhu a2, 0(a0)
+; CHECK-NEXT:    clhu a3, 4(a0)
+; CHECK-NEXT:    clhu a0, 6(a0)
 ; CHECK-NEXT:    slli a1, a1, 16
 ; CHECK-NEXT:    or a1, a1, a2
 ; CHECK-NEXT:    slli a3, a3, 32
@@ -65,10 +65,10 @@ define i64 @load_global_i64_align_4(i64 %y) addrspace(200) nounwind {
 ; CHECK-LABEL: load_global_i64_align_4:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:  .LBB2_1: # Label of block must be emitted
-; CHECK-NEXT:    auipcc ca0, %captab_pcrel_hi(a4)
-; CHECK-NEXT:    clc ca0, %pcrel_lo(.LBB2_1)(ca0)
-; CHECK-NEXT:    clwu a1, 4(ca0)
-; CHECK-NEXT:    clwu a0, 0(ca0)
+; CHECK-NEXT:    auipcc a0, %captab_pcrel_hi(a4)
+; CHECK-NEXT:    clc a0, %pcrel_lo(.LBB2_1)(a0)
+; CHECK-NEXT:    clwu a1, 4(a0)
+; CHECK-NEXT:    clwu a0, 0(a0)
 ; CHECK-NEXT:    slli a1, a1, 32
 ; CHECK-NEXT:    or a0, a1, a0
 ; CHECK-NEXT:    cret
@@ -80,9 +80,9 @@ define i64 @load_global_i64_align_8(i64 %y) addrspace(200) nounwind {
 ; CHECK-LABEL: load_global_i64_align_8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:  .LBB3_1: # Label of block must be emitted
-; CHECK-NEXT:    auipcc ca0, %captab_pcrel_hi(a8)
-; CHECK-NEXT:    clc ca0, %pcrel_lo(.LBB3_1)(ca0)
-; CHECK-NEXT:    cld a0, 0(ca0)
+; CHECK-NEXT:    auipcc a0, %captab_pcrel_hi(a8)
+; CHECK-NEXT:    clc a0, %pcrel_lo(.LBB3_1)(a0)
+; CHECK-NEXT:    cld a0, 0(a0)
 ; CHECK-NEXT:    cret
   %ret = load i64, i64 addrspace(200)* @a8, align 8
   ret i64 %ret
@@ -92,23 +92,23 @@ define void @store_global_i64_align_1(i64 %y) addrspace(200) nounwind {
 ; CHECK-LABEL: store_global_i64_align_1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:  .LBB4_1: # Label of block must be emitted
-; CHECK-NEXT:    auipcc ca1, %captab_pcrel_hi(a1)
-; CHECK-NEXT:    clc ca1, %pcrel_lo(.LBB4_1)(ca1)
+; CHECK-NEXT:    auipcc a1, %captab_pcrel_hi(a1)
+; CHECK-NEXT:    clc a1, %pcrel_lo(.LBB4_1)(a1)
 ; CHECK-NEXT:    srli a2, a0, 56
-; CHECK-NEXT:    csb a2, 7(ca1)
+; CHECK-NEXT:    csb a2, 7(a1)
 ; CHECK-NEXT:    srli a2, a0, 48
-; CHECK-NEXT:    csb a2, 6(ca1)
+; CHECK-NEXT:    csb a2, 6(a1)
 ; CHECK-NEXT:    srli a2, a0, 40
-; CHECK-NEXT:    csb a2, 5(ca1)
+; CHECK-NEXT:    csb a2, 5(a1)
 ; CHECK-NEXT:    srli a2, a0, 32
-; CHECK-NEXT:    csb a2, 4(ca1)
+; CHECK-NEXT:    csb a2, 4(a1)
 ; CHECK-NEXT:    srli a2, a0, 24
-; CHECK-NEXT:    csb a2, 3(ca1)
+; CHECK-NEXT:    csb a2, 3(a1)
 ; CHECK-NEXT:    srli a2, a0, 16
-; CHECK-NEXT:    csb a0, 0(ca1)
+; CHECK-NEXT:    csb a0, 0(a1)
 ; CHECK-NEXT:    srli a0, a0, 8
-; CHECK-NEXT:    csb a2, 2(ca1)
-; CHECK-NEXT:    csb a0, 1(ca1)
+; CHECK-NEXT:    csb a2, 2(a1)
+; CHECK-NEXT:    csb a0, 1(a1)
 ; CHECK-NEXT:    cret
   store i64 %y, i64 addrspace(200)* @a1, align 1
   ret void
@@ -118,15 +118,15 @@ define void @store_global_i64_align_2(i64 %y) addrspace(200) nounwind {
 ; CHECK-LABEL: store_global_i64_align_2:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:  .LBB5_1: # Label of block must be emitted
-; CHECK-NEXT:    auipcc ca1, %captab_pcrel_hi(a2)
-; CHECK-NEXT:    clc ca1, %pcrel_lo(.LBB5_1)(ca1)
+; CHECK-NEXT:    auipcc a1, %captab_pcrel_hi(a2)
+; CHECK-NEXT:    clc a1, %pcrel_lo(.LBB5_1)(a1)
 ; CHECK-NEXT:    srli a2, a0, 48
-; CHECK-NEXT:    csh a2, 6(ca1)
+; CHECK-NEXT:    csh a2, 6(a1)
 ; CHECK-NEXT:    srli a2, a0, 32
-; CHECK-NEXT:    csh a0, 0(ca1)
+; CHECK-NEXT:    csh a0, 0(a1)
 ; CHECK-NEXT:    srli a0, a0, 16
-; CHECK-NEXT:    csh a2, 4(ca1)
-; CHECK-NEXT:    csh a0, 2(ca1)
+; CHECK-NEXT:    csh a2, 4(a1)
+; CHECK-NEXT:    csh a0, 2(a1)
 ; CHECK-NEXT:    cret
   store i64 %y, i64 addrspace(200)* @a2, align 2
   ret void
@@ -136,11 +136,11 @@ define void @store_global_i64_align_4(i64 %y) addrspace(200) nounwind {
 ; CHECK-LABEL: store_global_i64_align_4:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:  .LBB6_1: # Label of block must be emitted
-; CHECK-NEXT:    auipcc ca1, %captab_pcrel_hi(a4)
-; CHECK-NEXT:    clc ca1, %pcrel_lo(.LBB6_1)(ca1)
-; CHECK-NEXT:    csw a0, 0(ca1)
+; CHECK-NEXT:    auipcc a1, %captab_pcrel_hi(a4)
+; CHECK-NEXT:    clc a1, %pcrel_lo(.LBB6_1)(a1)
+; CHECK-NEXT:    csw a0, 0(a1)
 ; CHECK-NEXT:    srli a0, a0, 32
-; CHECK-NEXT:    csw a0, 4(ca1)
+; CHECK-NEXT:    csw a0, 4(a1)
 ; CHECK-NEXT:    cret
   store i64 %y, i64 addrspace(200)* @a4, align 4
   ret void
@@ -150,9 +150,9 @@ define void @store_global_i64_align_8(i64 %y) addrspace(200) nounwind {
 ; CHECK-LABEL: store_global_i64_align_8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:  .LBB7_1: # Label of block must be emitted
-; CHECK-NEXT:    auipcc ca1, %captab_pcrel_hi(a8)
-; CHECK-NEXT:    clc ca1, %pcrel_lo(.LBB7_1)(ca1)
-; CHECK-NEXT:    csd a0, 0(ca1)
+; CHECK-NEXT:    auipcc a1, %captab_pcrel_hi(a8)
+; CHECK-NEXT:    clc a1, %pcrel_lo(.LBB7_1)(a1)
+; CHECK-NEXT:    csd a0, 0(a1)
 ; CHECK-NEXT:    cret
   store i64 %y, i64 addrspace(200)* @a8, align 8
   ret void
diff --git a/llvm/test/CodeGen/CHERI-Generic/byval-buffer.ll b/llvm/test/CodeGen/CHERI-Generic/byval-buffer.ll
index f0e417dd06104..97b0cc387e1e1 100644
--- a/llvm/test/CodeGen/CHERI-Generic/byval-buffer.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/byval-buffer.ll
@@ -165,32 +165,32 @@ define dso_local void @clang_purecap_byval_args() local_unnamed_addr addrspace(2
 ;
 ; PURECAP-RV64-LABEL: clang_purecap_byval_args:
 ; PURECAP-RV64:       # %bb.0: # %entry
-; PURECAP-RV64-NEXT:    cincoffset csp, csp, -1072
-; PURECAP-RV64-NEXT:    csc cra, 1056(csp) # 16-byte Folded Spill
-; PURECAP-RV64-NEXT:    csc cs0, 1040(csp) # 16-byte Folded Spill
+; PURECAP-RV64-NEXT:    cincoffset sp, sp, -1072
+; PURECAP-RV64-NEXT:    csc ra, 1056(sp) # 16-byte Folded Spill
+; PURECAP-RV64-NEXT:    csc s0, 1040(sp) # 16-byte Folded Spill
 ; PURECAP-RV64-NEXT:  .LBB0_1: # %entry
 ; PURECAP-RV64-NEXT:    # Label of block must be emitted
-; PURECAP-RV64-NEXT:    auipcc cs0, %captab_pcrel_hi(global_foo)
-; PURECAP-RV64-NEXT:    clc cs0, %pcrel_lo(.LBB0_1)(cs0)
+; PURECAP-RV64-NEXT:    auipcc s0, %captab_pcrel_hi(global_foo)
+; PURECAP-RV64-NEXT:    clc s0, %pcrel_lo(.LBB0_1)(s0)
 ; PURECAP-RV64-NEXT:    li a2, 1024
-; PURECAP-RV64-NEXT:    cmove ca0, cs0
+; PURECAP-RV64-NEXT:    cmove a0, s0
 ; PURECAP-RV64-NEXT:    li a1, 0
 ; PURECAP-RV64-NEXT:    ccall memset
-; PURECAP-RV64-NEXT:    clb a0, 0(cs0)
+; PURECAP-RV64-NEXT:    clb a0, 0(s0)
 ; PURECAP-RV64-NEXT:    li a1, 0
 ; PURECAP-RV64-NEXT:    ccall assert_eq
-; PURECAP-RV64-NEXT:    cincoffset ca0, csp, 16
+; PURECAP-RV64-NEXT:    cincoffset a0, sp, 16
 ; PURECAP-RV64-NEXT:    li a2, 1024
-; PURECAP-RV64-NEXT:    cmove ca1, cs0
+; PURECAP-RV64-NEXT:    cmove a1, s0
 ; PURECAP-RV64-NEXT:    ccall memcpy
-; PURECAP-RV64-NEXT:    cincoffset ca0, csp, 16
+; PURECAP-RV64-NEXT:    cincoffset a0, sp, 16
 ; PURECAP-RV64-NEXT:    ccall foo_byval
-; PURECAP-RV64-NEXT:    clb a0, 0(cs0)
+; PURECAP-RV64-NEXT:    clb a0, 0(s0)
 ; PURECAP-RV64-NEXT:    li a1, 0
 ; PURECAP-RV64-NEXT:    ccall assert_eq
-; PURECAP-RV64-NEXT:    clc cra, 1056(csp) # 16-byte Folded Reload
-; PURECAP-RV64-NEXT:    clc cs0, 1040(csp) # 16-byte Folded Reload
-; PURECAP-RV64-NEXT:    cincoffset csp, csp, 1072
+; PURECAP-RV64-NEXT:    clc ra, 1056(sp) # 16-byte Folded Reload
+; PURECAP-RV64-NEXT:    clc s0, 1040(sp) # 16-byte Folded Reload
+; PURECAP-RV64-NEXT:    cincoffset sp, sp, 1072
 ; PURECAP-RV64-NEXT:    cret
 ;
 ; PURECAP-MIPS-LABEL: clang_purecap_byval_args:
diff --git a/llvm/test/CodeGen/CHERI-Generic/byval-varargs.ll b/llvm/test/CodeGen/CHERI-Generic/byval-varargs.ll
index c58d84691e30b..2cb883ce3a246 100644
--- a/llvm/test/CodeGen/CHERI-Generic/byval-varargs.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/byval-varargs.ll
@@ -96,33 +96,33 @@ define signext i32 @test_alloca() local_unnamed_addr addrspace(200) nounwind {
 ;
 ; PURECAP-RV64-LABEL: test_alloca:
 ; PURECAP-RV64:       # %bb.0: # %entry
-; PURECAP-RV64-NEXT:    cincoffset csp, csp, -2032
-; PURECAP-RV64-NEXT:    csc cra, 2016(csp) # 16-byte Folded Spill
-; PURECAP-RV64-NEXT:    csc cs0, 2000(csp) # 16-byte Folded Spill
-; PURECAP-RV64-NEXT:    csc cs1, 1984(csp) # 16-byte Folded Spill
-; PURECAP-RV64-NEXT:    cincoffset csp, csp, -96
-; PURECAP-RV64-NEXT:    cincoffset ca0, csp, 1056
-; PURECAP-RV64-NEXT:    csetbounds cs0, ca0, 1024
+; PURECAP-RV64-NEXT:    cincoffset sp, sp, -2032
+; PURECAP-RV64-NEXT:    csc ra, 2016(sp) # 16-byte Folded Spill
+; PURECAP-RV64-NEXT:    csc s0, 2000(sp) # 16-byte Folded Spill
+; PURECAP-RV64-NEXT:    csc s1, 1984(sp) # 16-byte Folded Spill
+; PURECAP-RV64-NEXT:    cincoffset sp, sp, -96
+; PURECAP-RV64-NEXT:    cincoffset a0, sp, 1056
+; PURECAP-RV64-NEXT:    csetbounds s0, a0, 1024
 ; PURECAP-RV64-NEXT:    li a2, 1024
-; PURECAP-RV64-NEXT:    cmove ca0, cs0
+; PURECAP-RV64-NEXT:    cmove a0, s0
 ; PURECAP-RV64-NEXT:    li a1, 0
 ; PURECAP-RV64-NEXT:    ccall memset
-; PURECAP-RV64-NEXT:    cmove ca0, cs0
+; PURECAP-RV64-NEXT:    cmove a0, s0
 ; PURECAP-RV64-NEXT:    ccall byref
-; PURECAP-RV64-NEXT:    cincoffset ca0, csp, 32
-; PURECAP-RV64-NEXT:    csetbounds cs1, ca0, 1024
+; PURECAP-RV64-NEXT:    cincoffset a0, sp, 32
+; PURECAP-RV64-NEXT:    csetbounds s1, a0, 1024
 ; PURECAP-RV64-NEXT:    li a2, 1024
-; PURECAP-RV64-NEXT:    cmove ca0, cs1
-; PURECAP-RV64-NEXT:    cmove ca1, cs0
+; PURECAP-RV64-NEXT:    cmove a0, s1
+; PURECAP-RV64-NEXT:    cmove a1, s0
 ; PURECAP-RV64-NEXT:    ccall memcpy
 ; PURECAP-RV64-NEXT:    li a0, 1024
-; PURECAP-RV64-NEXT:    csc cs1, 0(csp)
+; PURECAP-RV64-NEXT:    csc s1, 0(sp)
 ; PURECAP-RV64-NEXT:    ccall varargs
-; PURECAP-RV64-NEXT:    cincoffset csp, csp, 96
-; PURECAP-RV64-NEXT:    clc cra, 2016(csp) # 16-byte Folded Reload
-; PURECAP-RV64-NEXT:    clc cs0, 2000(csp) # 16-byte Folded Reload
-; PURECAP-RV64-NEXT:    clc cs1, 1984(csp) # 16-byte Folded Reload
-; PURECAP-RV64-NEXT:    cincoffset csp, csp, 2032
+; PURECAP-RV64-NEXT:    cincoffset sp, sp, 96
+; PURECAP-RV64-NEXT:    clc ra, 2016(sp) # 16-byte Folded Reload
+; PURECAP-RV64-NEXT:    clc s0, 2000(sp) # 16-byte Folded Reload
+; PURECAP-RV64-NEXT:    clc s1, 1984(sp) # 16-byte Folded Reload
+; PURECAP-RV64-NEXT:    cincoffset sp, sp, 2032
 ; PURECAP-RV64-NEXT:    cret
 ;
 ; PURECAP-MIPS-LABEL: test_alloca:
@@ -274,34 +274,34 @@ define signext i32 @test_byval() local_unnamed_addr addrspace(200) nounwind {
 ; PURECAP-RV64-LABEL: test_byval:
 ; Stack frame size should be > 2048 (split into two instructions)
 ; PURECAP-RV64:       # %bb.0: # %entry
-; PURECAP-RV64-NEXT:    cincoffset csp, csp, -2032
-; PURECAP-RV64-NEXT:    csc cra, 2016(csp) # 16-byte Folded Spill
-; PURECAP-RV64-NEXT:    csc cs0, 2000(csp) # 16-byte Folded Spill
-; PURECAP-RV64-NEXT:    csc cs1, 1984(csp) # 16-byte Folded Spill
-; PURECAP-RV64-NEXT:    cincoffset csp, csp, -96
-; PURECAP-RV64-NEXT:    cincoffset ca0, csp, 1056
-; PURECAP-RV64-NEXT:    csetbounds cs0, ca0, 1024
+; PURECAP-RV64-NEXT:    cincoffset sp, sp, -2032
+; PURECAP-RV64-NEXT:    csc ra, 2016(sp) # 16-byte Folded Spill
+; PURECAP-RV64-NEXT:    csc s0, 2000(sp) # 16-byte Folded Spill
+; PURECAP-RV64-NEXT:    csc s1, 1984(sp) # 16-byte Folded Spill
+; PURECAP-RV64-NEXT:    cincoffset sp, sp, -96
+; PURECAP-RV64-NEXT:    cincoffset a0, sp, 1056
+; PURECAP-RV64-NEXT:    csetbounds s0, a0, 1024
 ; PURECAP-RV64-NEXT:    li a2, 1024
-; PURECAP-RV64-NEXT:    cmove ca0, cs0
+; PURECAP-RV64-NEXT:    cmove a0, s0
 ; PURECAP-RV64-NEXT:    li a1, 0
 ; PURECAP-RV64-NEXT:    ccall memset
-; PURECAP-RV64-NEXT:    cmove ca0, cs0
+; PURECAP-RV64-NEXT:    cmove a0, s0
 ; PURECAP-RV64-NEXT:    ccall byref
-; PURECAP-RV64-NEXT:    cincoffset ca0, csp, 32
+; PURECAP-RV64-NEXT:    cincoffset a0, sp, 32
 ; PURECAP-RV64-NEXT:    li a2, 1024
-; PURECAP-RV64-NEXT:    cincoffset cs1, csp, 32
-; PURECAP-RV64-NEXT:    cmove ca1, cs0
+; PURECAP-RV64-NEXT:    cincoffset s1, sp, 32
+; PURECAP-RV64-NEXT:    cmove a1, s0
 ; Note: no bounds for implicit byval arg memcpy()
 ; TODO: should we add the csetbounds here? Not really necessary if we trust memcpy().
 ; PURECAP-RV64-NEXT:    ccall memcpy
 ; PURECAP-RV64-NEXT:    li a0, 1024
-; PURECAP-RV64-NEXT:    csc cs1, 0(csp)
+; PURECAP-RV64-NEXT:    csc s1, 0(sp)
 ; PURECAP-RV64-NEXT:    ccall varargs
-; PURECAP-RV64-NEXT:    cincoffset csp, csp, 96
-; PURECAP-RV64-NEXT:    clc cra, 2016(csp) # 16-byte Folded Reload
-; PURECAP-RV64-NEXT:    clc cs0, 2000(csp) # 16-byte Folded Reload
-; PURECAP-RV64-NEXT:    clc cs1, 1984(csp) # 16-byte Folded Reload
-; PURECAP-RV64-NEXT:    cincoffset csp, csp, 2032
+; PURECAP-RV64-NEXT:    cincoffset sp, sp, 96
+; PURECAP-RV64-NEXT:    clc ra, 2016(sp) # 16-byte Folded Reload
+; PURECAP-RV64-NEXT:    clc s0, 2000(sp) # 16-byte Folded Reload
+; PURECAP-RV64-NEXT:    clc s1, 1984(sp) # 16-byte Folded Reload
+; PURECAP-RV64-NEXT:    cincoffset sp, sp, 2032
 ; PURECAP-RV64-NEXT:    cret
 ;
 ; PURECAP-MIPS-LABEL: test_byval:
diff --git a/llvm/test/CodeGen/RISCV/cheri/atomic-cmpxchg-hybrid.ll b/llvm/test/CodeGen/RISCV/cheri/atomic-cmpxchg-hybrid.ll
index 20c08c6c7cf1d..e7265011732ba 100644
--- a/llvm/test/CodeGen/RISCV/cheri/atomic-cmpxchg-hybrid.ll
+++ b/llvm/test/CodeGen/RISCV/cheri/atomic-cmpxchg-hybrid.ll
@@ -13,7 +13,7 @@ define void @cmpxchg_cap_monotonic_monotonic(i8 addrspace(200)** %ptr, i8 addrsp
 ; RV32IXCHERI:       # %bb.0:
 ; RV32IXCHERI-NEXT:    addi sp, sp, -16
 ; RV32IXCHERI-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IXCHERI-NEXT:    sc ca1, 0(sp)
+; RV32IXCHERI-NEXT:    sc a1, 0(sp)
 ; RV32IXCHERI-NEXT:    mv a1, sp
 ; RV32IXCHERI-NEXT:    li a3, 0
 ; RV32IXCHERI-NEXT:    li a4, 0
@@ -25,10 +25,10 @@ define void @cmpxchg_cap_monotonic_monotonic(i8 addrspace(200)** %ptr, i8 addrsp
 ; RV32IAXCHERI-LABEL: cmpxchg_cap_monotonic_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB0_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    lr.c ca3, (a0)
+; RV32IAXCHERI-NEXT:    lr.c a3, (a0)
 ; RV32IAXCHERI-NEXT:    bne a3, a1, .LBB0_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB0_1 Depth=1
-; RV32IAXCHERI-NEXT:    sc.c a4, ca2, (a0)
+; RV32IAXCHERI-NEXT:    sc.c a4, a2, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a4, .LBB0_1
 ; RV32IAXCHERI-NEXT:  .LBB0_3:
 ; RV32IAXCHERI-NEXT:    ret
@@ -37,7 +37,7 @@ define void @cmpxchg_cap_monotonic_monotonic(i8 addrspace(200)** %ptr, i8 addrsp
 ; RV64IXCHERI:       # %bb.0:
 ; RV64IXCHERI-NEXT:    addi sp, sp, -32
 ; RV64IXCHERI-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
-; RV64IXCHERI-NEXT:    sc ca1, 0(sp)
+; RV64IXCHERI-NEXT:    sc a1, 0(sp)
 ; RV64IXCHERI-NEXT:    mv a1, sp
 ; RV64IXCHERI-NEXT:    li a3, 0
 ; RV64IXCHERI-NEXT:    li a4, 0
@@ -49,10 +49,10 @@ define void @cmpxchg_cap_monotonic_monotonic(i8 addrspace(200)** %ptr, i8 addrsp
 ; RV64IAXCHERI-LABEL: cmpxchg_cap_monotonic_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB0_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    lr.c ca3, (a0)
+; RV64IAXCHERI-NEXT:    lr.c a3, (a0)
 ; RV64IAXCHERI-NEXT:    bne a3, a1, .LBB0_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB0_1 Depth=1
-; RV64IAXCHERI-NEXT:    sc.c a4, ca2, (a0)
+; RV64IAXCHERI-NEXT:    sc.c a4, a2, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a4, .LBB0_1
 ; RV64IAXCHERI-NEXT:  .LBB0_3:
 ; RV64IAXCHERI-NEXT:    ret
@@ -65,7 +65,7 @@ define void @cmpxchg_cap_acquire_monotonic(i8 addrspace(200)** %ptr, i8 addrspac
 ; RV32IXCHERI:       # %bb.0:
 ; RV32IXCHERI-NEXT:    addi sp, sp, -16
 ; RV32IXCHERI-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IXCHERI-NEXT:    sc ca1, 0(sp)
+; RV32IXCHERI-NEXT:    sc a1, 0(sp)
 ; RV32IXCHERI-NEXT:    mv a1, sp
 ; RV32IXCHERI-NEXT:    li a3, 2
 ; RV32IXCHERI-NEXT:    li a4, 0
@@ -77,10 +77,10 @@ define void @cmpxchg_cap_acquire_monotonic(i8 addrspace(200)** %ptr, i8 addrspac
 ; RV32IAXCHERI-LABEL: cmpxchg_cap_acquire_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB1_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    lr.c.aq ca3, (a0)
+; RV32IAXCHERI-NEXT:    lr.c.aq a3, (a0)
 ; RV32IAXCHERI-NEXT:    bne a3, a1, .LBB1_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB1_1 Depth=1
-; RV32IAXCHERI-NEXT:    sc.c.aq a4, ca2, (a0)
+; RV32IAXCHERI-NEXT:    sc.c.aq a4, a2, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a4, .LBB1_1
 ; RV32IAXCHERI-NEXT:  .LBB1_3:
 ; RV32IAXCHERI-NEXT:    ret
@@ -89,7 +89,7 @@ define void @cmpxchg_cap_acquire_monotonic(i8 addrspace(200)** %ptr, i8 addrspac
 ; RV64IXCHERI:       # %bb.0:
 ; RV64IXCHERI-NEXT:    addi sp, sp, -32
 ; RV64IXCHERI-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
-; RV64IXCHERI-NEXT:    sc ca1, 0(sp)
+; RV64IXCHERI-NEXT:    sc a1, 0(sp)
 ; RV64IXCHERI-NEXT:    mv a1, sp
 ; RV64IXCHERI-NEXT:    li a3, 2
 ; RV64IXCHERI-NEXT:    li a4, 0
@@ -101,10 +101,10 @@ define void @cmpxchg_cap_acquire_monotonic(i8 addrspace(200)** %ptr, i8 addrspac
 ; RV64IAXCHERI-LABEL: cmpxchg_cap_acquire_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB1_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    lr.c.aq ca3, (a0)
+; RV64IAXCHERI-NEXT:    lr.c.aq a3, (a0)
 ; RV64IAXCHERI-NEXT:    bne a3, a1, .LBB1_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB1_1 Depth=1
-; RV64IAXCHERI-NEXT:    sc.c.aq a4, ca2, (a0)
+; RV64IAXCHERI-NEXT:    sc.c.aq a4, a2, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a4, .LBB1_1
 ; RV64IAXCHERI-NEXT:  .LBB1_3:
 ; RV64IAXCHERI-NEXT:    ret
@@ -117,7 +117,7 @@ define void @cmpxchg_cap_acquire_acquire(i8 addrspace(200)** %ptr, i8 addrspace(
 ; RV32IXCHERI:       # %bb.0:
 ; RV32IXCHERI-NEXT:    addi sp, sp, -16
 ; RV32IXCHERI-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IXCHERI-NEXT:    sc ca1, 0(sp)
+; RV32IXCHERI-NEXT:    sc a1, 0(sp)
 ; RV32IXCHERI-NEXT:    mv a1, sp
 ; RV32IXCHERI-NEXT:    li a3, 2
 ; RV32IXCHERI-NEXT:    li a4, 2
@@ -129,10 +129,10 @@ define void @cmpxchg_cap_acquire_acquire(i8 addrspace(200)** %ptr, i8 addrspace(
 ; RV32IAXCHERI-LABEL: cmpxchg_cap_acquire_acquire:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB2_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    lr.c.aq ca3, (a0)
+; RV32IAXCHERI-NEXT:    lr.c.aq a3, (a0)
 ; RV32IAXCHERI-NEXT:    bne a3, a1, .LBB2_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB2_1 Depth=1
-; RV32IAXCHERI-NEXT:    sc.c.aq a4, ca2, (a0)
+; RV32IAXCHERI-NEXT:    sc.c.aq a4, a2, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a4, .LBB2_1
 ; RV32IAXCHERI-NEXT:  .LBB2_3:
 ; RV32IAXCHERI-NEXT:    ret
@@ -141,7 +141,7 @@ define void @cmpxchg_cap_acquire_acquire(i8 addrspace(200)** %ptr, i8 addrspace(
 ; RV64IXCHERI:       # %bb.0:
 ; RV64IXCHERI-NEXT:    addi sp, sp, -32
 ; RV64IXCHERI-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
-; RV64IXCHERI-NEXT:    sc ca1, 0(sp)
+; RV64IXCHERI-NEXT:    sc a1, 0(sp)
 ; RV64IXCHERI-NEXT:    mv a1, sp
 ; RV64IXCHERI-NEXT:    li a3, 2
 ; RV64IXCHERI-NEXT:    li a4, 2
@@ -153,10 +153,10 @@ define void @cmpxchg_cap_acquire_acquire(i8 addrspace(200)** %ptr, i8 addrspace(
 ; RV64IAXCHERI-LABEL: cmpxchg_cap_acquire_acquire:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB2_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    lr.c.aq ca3, (a0)
+; RV64IAXCHERI-NEXT:    lr.c.aq a3, (a0)
 ; RV64IAXCHERI-NEXT:    bne a3, a1, .LBB2_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB2_1 Depth=1
-; RV64IAXCHERI-NEXT:    sc.c.aq a4, ca2, (a0)
+; RV64IAXCHERI-NEXT:    sc.c.aq a4, a2, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a4, .LBB2_1
 ; RV64IAXCHERI-NEXT:  .LBB2_3:
 ; RV64IAXCHERI-NEXT:    ret
@@ -169,7 +169,7 @@ define void @cmpxchg_cap_release_monotonic(i8 addrspace(200)** %ptr, i8 addrspac
 ; RV32IXCHERI:       # %bb.0:
 ; RV32IXCHERI-NEXT:    addi sp, sp, -16
 ; RV32IXCHERI-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IXCHERI-NEXT:    sc ca1, 0(sp)
+; RV32IXCHERI-NEXT:    sc a1, 0(sp)
 ; RV32IXCHERI-NEXT:    mv a1, sp
 ; RV32IXCHERI-NEXT:    li a3, 3
 ; RV32IXCHERI-NEXT:    li a4, 0
@@ -181,10 +181,10 @@ define void @cmpxchg_cap_release_monotonic(i8 addrspace(200)** %ptr, i8 addrspac
 ; RV32IAXCHERI-LABEL: cmpxchg_cap_release_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB3_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    lr.c.rl ca3, (a0)
+; RV32IAXCHERI-NEXT:    lr.c.rl a3, (a0)
 ; RV32IAXCHERI-NEXT:    bne a3, a1, .LBB3_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB3_1 Depth=1
-; RV32IAXCHERI-NEXT:    sc.c a4, ca2, (a0)
+; RV32IAXCHERI-NEXT:    sc.c a4, a2, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a4, .LBB3_1
 ; RV32IAXCHERI-NEXT:  .LBB3_3:
 ; RV32IAXCHERI-NEXT:    ret
@@ -193,7 +193,7 @@ define void @cmpxchg_cap_release_monotonic(i8 addrspace(200)** %ptr, i8 addrspac
 ; RV64IXCHERI:       # %bb.0:
 ; RV64IXCHERI-NEXT:    addi sp, sp, -32
 ; RV64IXCHERI-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
-; RV64IXCHERI-NEXT:    sc ca1, 0(sp)
+; RV64IXCHERI-NEXT:    sc a1, 0(sp)
 ; RV64IXCHERI-NEXT:    mv a1, sp
 ; RV64IXCHERI-NEXT:    li a3, 3
 ; RV64IXCHERI-NEXT:    li a4, 0
@@ -205,10 +205,10 @@ define void @cmpxchg_cap_release_monotonic(i8 addrspace(200)** %ptr, i8 addrspac
 ; RV64IAXCHERI-LABEL: cmpxchg_cap_release_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB3_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    lr.c.rl ca3, (a0)
+; RV64IAXCHERI-NEXT:    lr.c.rl a3, (a0)
 ; RV64IAXCHERI-NEXT:    bne a3, a1, .LBB3_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB3_1 Depth=1
-; RV64IAXCHERI-NEXT:    sc.c a4, ca2, (a0)
+; RV64IAXCHERI-NEXT:    sc.c a4, a2, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a4, .LBB3_1
 ; RV64IAXCHERI-NEXT:  .LBB3_3:
 ; RV64IAXCHERI-NEXT:    ret
@@ -221,7 +221,7 @@ define void @cmpxchg_cap_release_acquire(i8 addrspace(200)** %ptr, i8 addrspace(
 ; RV32IXCHERI:       # %bb.0:
 ; RV32IXCHERI-NEXT:    addi sp, sp, -16
 ; RV32IXCHERI-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IXCHERI-NEXT:    sc ca1, 0(sp)
+; RV32IXCHERI-NEXT:    sc a1, 0(sp)
 ; RV32IXCHERI-NEXT:    mv a1, sp
 ; RV32IXCHERI-NEXT:    li a3, 3
 ; RV32IXCHERI-NEXT:    li a4, 2
@@ -233,10 +233,10 @@ define void @cmpxchg_cap_release_acquire(i8 addrspace(200)** %ptr, i8 addrspace(
 ; RV32IAXCHERI-LABEL: cmpxchg_cap_release_acquire:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB4_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    lr.c.aq ca3, (a0)
+; RV32IAXCHERI-NEXT:    lr.c.aq a3, (a0)
 ; RV32IAXCHERI-NEXT:    bne a3, a1, .LBB4_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB4_1 Depth=1
-; RV32IAXCHERI-NEXT:    sc.c.aq a4, ca2, (a0)
+; RV32IAXCHERI-NEXT:    sc.c.aq a4, a2, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a4, .LBB4_1
 ; RV32IAXCHERI-NEXT:  .LBB4_3:
 ; RV32IAXCHERI-NEXT:    ret
@@ -245,7 +245,7 @@ define void @cmpxchg_cap_release_acquire(i8 addrspace(200)** %ptr, i8 addrspace(
 ; RV64IXCHERI:       # %bb.0:
 ; RV64IXCHERI-NEXT:    addi sp, sp, -32
 ; RV64IXCHERI-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
-; RV64IXCHERI-NEXT:    sc ca1, 0(sp)
+; RV64IXCHERI-NEXT:    sc a1, 0(sp)
 ; RV64IXCHERI-NEXT:    mv a1, sp
 ; RV64IXCHERI-NEXT:    li a3, 3
 ; RV64IXCHERI-NEXT:    li a4, 2
@@ -257,10 +257,10 @@ define void @cmpxchg_cap_release_acquire(i8 addrspace(200)** %ptr, i8 addrspace(
 ; RV64IAXCHERI-LABEL: cmpxchg_cap_release_acquire:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB4_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    lr.c.aq ca3, (a0)
+; RV64IAXCHERI-NEXT:    lr.c.aq a3, (a0)
 ; RV64IAXCHERI-NEXT:    bne a3, a1, .LBB4_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB4_1 Depth=1
-; RV64IAXCHERI-NEXT:    sc.c.aq a4, ca2, (a0)
+; RV64IAXCHERI-NEXT:    sc.c.aq a4, a2, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a4, .LBB4_1
 ; RV64IAXCHERI-NEXT:  .LBB4_3:
 ; RV64IAXCHERI-NEXT:    ret
@@ -273,7 +273,7 @@ define void @cmpxchg_cap_acq_rel_monotonic(i8 addrspace(200)** %ptr, i8 addrspac
 ; RV32IXCHERI:       # %bb.0:
 ; RV32IXCHERI-NEXT:    addi sp, sp, -16
 ; RV32IXCHERI-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IXCHERI-NEXT:    sc ca1, 0(sp)
+; RV32IXCHERI-NEXT:    sc a1, 0(sp)
 ; RV32IXCHERI-NEXT:    mv a1, sp
 ; RV32IXCHERI-NEXT:    li a3, 4
 ; RV32IXCHERI-NEXT:    li a4, 0
@@ -285,10 +285,10 @@ define void @cmpxchg_cap_acq_rel_monotonic(i8 addrspace(200)** %ptr, i8 addrspac
 ; RV32IAXCHERI-LABEL: cmpxchg_cap_acq_rel_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB5_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    lr.c.aq ca3, (a0)
+; RV32IAXCHERI-NEXT:    lr.c.aq a3, (a0)
 ; RV32IAXCHERI-NEXT:    bne a3, a1, .LBB5_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB5_1 Depth=1
-; RV32IAXCHERI-NEXT:    sc.c.aq a4, ca2, (a0)
+; RV32IAXCHERI-NEXT:    sc.c.aq a4, a2, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a4, .LBB5_1
 ; RV32IAXCHERI-NEXT:  .LBB5_3:
 ; RV32IAXCHERI-NEXT:    ret
@@ -297,7 +297,7 @@ define void @cmpxchg_cap_acq_rel_monotonic(i8 addrspace(200)** %ptr, i8 addrspac
 ; RV64IXCHERI:       # %bb.0:
 ; RV64IXCHERI-NEXT:    addi sp, sp, -32
 ; RV64IXCHERI-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
-; RV64IXCHERI-NEXT:    sc ca1, 0(sp)
+; RV64IXCHERI-NEXT:    sc a1, 0(sp)
 ; RV64IXCHERI-NEXT:    mv a1, sp
 ; RV64IXCHERI-NEXT:    li a3, 4
 ; RV64IXCHERI-NEXT:    li a4, 0
@@ -309,10 +309,10 @@ define void @cmpxchg_cap_acq_rel_monotonic(i8 addrspace(200)** %ptr, i8 addrspac
 ; RV64IAXCHERI-LABEL: cmpxchg_cap_acq_rel_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB5_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    lr.c.aq ca3, (a0)
+; RV64IAXCHERI-NEXT:    lr.c.aq a3, (a0)
 ; RV64IAXCHERI-NEXT:    bne a3, a1, .LBB5_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB5_1 Depth=1
-; RV64IAXCHERI-NEXT:    sc.c.aq a4, ca2, (a0)
+; RV64IAXCHERI-NEXT:    sc.c.aq a4, a2, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a4, .LBB5_1
 ; RV64IAXCHERI-NEXT:  .LBB5_3:
 ; RV64IAXCHERI-NEXT:    ret
@@ -325,7 +325,7 @@ define void @cmpxchg_cap_acq_rel_acquire(i8 addrspace(200)** %ptr, i8 addrspace(
 ; RV32IXCHERI:       # %bb.0:
 ; RV32IXCHERI-NEXT:    addi sp, sp, -16
 ; RV32IXCHERI-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IXCHERI-NEXT:    sc ca1, 0(sp)
+; RV32IXCHERI-NEXT:    sc a1, 0(sp)
 ; RV32IXCHERI-NEXT:    mv a1, sp
 ; RV32IXCHERI-NEXT:    li a3, 4
 ; RV32IXCHERI-NEXT:    li a4, 2
@@ -337,10 +337,10 @@ define void @cmpxchg_cap_acq_rel_acquire(i8 addrspace(200)** %ptr, i8 addrspace(
 ; RV32IAXCHERI-LABEL: cmpxchg_cap_acq_rel_acquire:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB6_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    lr.c.aq ca3, (a0)
+; RV32IAXCHERI-NEXT:    lr.c.aq a3, (a0)
 ; RV32IAXCHERI-NEXT:    bne a3, a1, .LBB6_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB6_1 Depth=1
-; RV32IAXCHERI-NEXT:    sc.c.aq a4, ca2, (a0)
+; RV32IAXCHERI-NEXT:    sc.c.aq a4, a2, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a4, .LBB6_1
 ; RV32IAXCHERI-NEXT:  .LBB6_3:
 ; RV32IAXCHERI-NEXT:    ret
@@ -349,7 +349,7 @@ define void @cmpxchg_cap_acq_rel_acquire(i8 addrspace(200)** %ptr, i8 addrspace(
 ; RV64IXCHERI:       # %bb.0:
 ; RV64IXCHERI-NEXT:    addi sp, sp, -32
 ; RV64IXCHERI-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
-; RV64IXCHERI-NEXT:    sc ca1, 0(sp)
+; RV64IXCHERI-NEXT:    sc a1, 0(sp)
 ; RV64IXCHERI-NEXT:    mv a1, sp
 ; RV64IXCHERI-NEXT:    li a3, 4
 ; RV64IXCHERI-NEXT:    li a4, 2
@@ -361,10 +361,10 @@ define void @cmpxchg_cap_acq_rel_acquire(i8 addrspace(200)** %ptr, i8 addrspace(
 ; RV64IAXCHERI-LABEL: cmpxchg_cap_acq_rel_acquire:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB6_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    lr.c.aq ca3, (a0)
+; RV64IAXCHERI-NEXT:    lr.c.aq a3, (a0)
 ; RV64IAXCHERI-NEXT:    bne a3, a1, .LBB6_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB6_1 Depth=1
-; RV64IAXCHERI-NEXT:    sc.c.aq a4, ca2, (a0)
+; RV64IAXCHERI-NEXT:    sc.c.aq a4, a2, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a4, .LBB6_1
 ; RV64IAXCHERI-NEXT:  .LBB6_3:
 ; RV64IAXCHERI-NEXT:    ret
@@ -377,7 +377,7 @@ define void @cmpxchg_cap_seq_cst_monotonic(i8 addrspace(200)** %ptr, i8 addrspac
 ; RV32IXCHERI:       # %bb.0:
 ; RV32IXCHERI-NEXT:    addi sp, sp, -16
 ; RV32IXCHERI-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IXCHERI-NEXT:    sc ca1, 0(sp)
+; RV32IXCHERI-NEXT:    sc a1, 0(sp)
 ; RV32IXCHERI-NEXT:    mv a1, sp
 ; RV32IXCHERI-NEXT:    li a3, 5
 ; RV32IXCHERI-NEXT:    li a4, 0
@@ -389,10 +389,10 @@ define void @cmpxchg_cap_seq_cst_monotonic(i8 addrspace(200)** %ptr, i8 addrspac
 ; RV32IAXCHERI-LABEL: cmpxchg_cap_seq_cst_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB7_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    lr.c.aqrl ca3, (a0)
+; RV32IAXCHERI-NEXT:    lr.c.aqrl a3, (a0)
 ; RV32IAXCHERI-NEXT:    bne a3, a1, .LBB7_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB7_1 Depth=1
-; RV32IAXCHERI-NEXT:    sc.c.aqrl a4, ca2, (a0)
+; RV32IAXCHERI-NEXT:    sc.c.aqrl a4, a2, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a4, .LBB7_1
 ; RV32IAXCHERI-NEXT:  .LBB7_3:
 ; RV32IAXCHERI-NEXT:    ret
@@ -401,7 +401,7 @@ define void @cmpxchg_cap_seq_cst_monotonic(i8 addrspace(200)** %ptr, i8 addrspac
 ; RV64IXCHERI:       # %bb.0:
 ; RV64IXCHERI-NEXT:    addi sp, sp, -32
 ; RV64IXCHERI-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
-; RV64IXCHERI-NEXT:    sc ca1, 0(sp)
+; RV64IXCHERI-NEXT:    sc a1, 0(sp)
 ; RV64IXCHERI-NEXT:    mv a1, sp
 ; RV64IXCHERI-NEXT:    li a3, 5
 ; RV64IXCHERI-NEXT:    li a4, 0
@@ -413,10 +413,10 @@ define void @cmpxchg_cap_seq_cst_monotonic(i8 addrspace(200)** %ptr, i8 addrspac
 ; RV64IAXCHERI-LABEL: cmpxchg_cap_seq_cst_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB7_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    lr.c.aqrl ca3, (a0)
+; RV64IAXCHERI-NEXT:    lr.c.aqrl a3, (a0)
 ; RV64IAXCHERI-NEXT:    bne a3, a1, .LBB7_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB7_1 Depth=1
-; RV64IAXCHERI-NEXT:    sc.c.aqrl a4, ca2, (a0)
+; RV64IAXCHERI-NEXT:    sc.c.aqrl a4, a2, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a4, .LBB7_1
 ; RV64IAXCHERI-NEXT:  .LBB7_3:
 ; RV64IAXCHERI-NEXT:    ret
@@ -429,7 +429,7 @@ define void @cmpxchg_cap_seq_cst_acquire(i8 addrspace(200)** %ptr, i8 addrspace(
 ; RV32IXCHERI:       # %bb.0:
 ; RV32IXCHERI-NEXT:    addi sp, sp, -16
 ; RV32IXCHERI-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IXCHERI-NEXT:    sc ca1, 0(sp)
+; RV32IXCHERI-NEXT:    sc a1, 0(sp)
 ; RV32IXCHERI-NEXT:    mv a1, sp
 ; RV32IXCHERI-NEXT:    li a3, 5
 ; RV32IXCHERI-NEXT:    li a4, 2
@@ -441,10 +441,10 @@ define void @cmpxchg_cap_seq_cst_acquire(i8 addrspace(200)** %ptr, i8 addrspace(
 ; RV32IAXCHERI-LABEL: cmpxchg_cap_seq_cst_acquire:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB8_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    lr.c.aqrl ca3, (a0)
+; RV32IAXCHERI-NEXT:    lr.c.aqrl a3, (a0)
 ; RV32IAXCHERI-NEXT:    bne a3, a1, .LBB8_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB8_1 Depth=1
-; RV32IAXCHERI-NEXT:    sc.c.aqrl a4, ca2, (a0)
+; RV32IAXCHERI-NEXT:    sc.c.aqrl a4, a2, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a4, .LBB8_1
 ; RV32IAXCHERI-NEXT:  .LBB8_3:
 ; RV32IAXCHERI-NEXT:    ret
@@ -453,7 +453,7 @@ define void @cmpxchg_cap_seq_cst_acquire(i8 addrspace(200)** %ptr, i8 addrspace(
 ; RV64IXCHERI:       # %bb.0:
 ; RV64IXCHERI-NEXT:    addi sp, sp, -32
 ; RV64IXCHERI-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
-; RV64IXCHERI-NEXT:    sc ca1, 0(sp)
+; RV64IXCHERI-NEXT:    sc a1, 0(sp)
 ; RV64IXCHERI-NEXT:    mv a1, sp
 ; RV64IXCHERI-NEXT:    li a3, 5
 ; RV64IXCHERI-NEXT:    li a4, 2
@@ -465,10 +465,10 @@ define void @cmpxchg_cap_seq_cst_acquire(i8 addrspace(200)** %ptr, i8 addrspace(
 ; RV64IAXCHERI-LABEL: cmpxchg_cap_seq_cst_acquire:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB8_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    lr.c.aqrl ca3, (a0)
+; RV64IAXCHERI-NEXT:    lr.c.aqrl a3, (a0)
 ; RV64IAXCHERI-NEXT:    bne a3, a1, .LBB8_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB8_1 Depth=1
-; RV64IAXCHERI-NEXT:    sc.c.aqrl a4, ca2, (a0)
+; RV64IAXCHERI-NEXT:    sc.c.aqrl a4, a2, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a4, .LBB8_1
 ; RV64IAXCHERI-NEXT:  .LBB8_3:
 ; RV64IAXCHERI-NEXT:    ret
@@ -481,7 +481,7 @@ define void @cmpxchg_cap_seq_cst_seq_cst(i8 addrspace(200)** %ptr, i8 addrspace(
 ; RV32IXCHERI:       # %bb.0:
 ; RV32IXCHERI-NEXT:    addi sp, sp, -16
 ; RV32IXCHERI-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IXCHERI-NEXT:    sc ca1, 0(sp)
+; RV32IXCHERI-NEXT:    sc a1, 0(sp)
 ; RV32IXCHERI-NEXT:    mv a1, sp
 ; RV32IXCHERI-NEXT:    li a3, 5
 ; RV32IXCHERI-NEXT:    li a4, 5
@@ -493,10 +493,10 @@ define void @cmpxchg_cap_seq_cst_seq_cst(i8 addrspace(200)** %ptr, i8 addrspace(
 ; RV32IAXCHERI-LABEL: cmpxchg_cap_seq_cst_seq_cst:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB9_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    lr.c.aqrl ca3, (a0)
+; RV32IAXCHERI-NEXT:    lr.c.aqrl a3, (a0)
 ; RV32IAXCHERI-NEXT:    bne a3, a1, .LBB9_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB9_1 Depth=1
-; RV32IAXCHERI-NEXT:    sc.c.aqrl a4, ca2, (a0)
+; RV32IAXCHERI-NEXT:    sc.c.aqrl a4, a2, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a4, .LBB9_1
 ; RV32IAXCHERI-NEXT:  .LBB9_3:
 ; RV32IAXCHERI-NEXT:    ret
@@ -505,7 +505,7 @@ define void @cmpxchg_cap_seq_cst_seq_cst(i8 addrspace(200)** %ptr, i8 addrspace(
 ; RV64IXCHERI:       # %bb.0:
 ; RV64IXCHERI-NEXT:    addi sp, sp, -32
 ; RV64IXCHERI-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
-; RV64IXCHERI-NEXT:    sc ca1, 0(sp)
+; RV64IXCHERI-NEXT:    sc a1, 0(sp)
 ; RV64IXCHERI-NEXT:    mv a1, sp
 ; RV64IXCHERI-NEXT:    li a3, 5
 ; RV64IXCHERI-NEXT:    li a4, 5
@@ -517,10 +517,10 @@ define void @cmpxchg_cap_seq_cst_seq_cst(i8 addrspace(200)** %ptr, i8 addrspace(
 ; RV64IAXCHERI-LABEL: cmpxchg_cap_seq_cst_seq_cst:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB9_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    lr.c.aqrl ca3, (a0)
+; RV64IAXCHERI-NEXT:    lr.c.aqrl a3, (a0)
 ; RV64IAXCHERI-NEXT:    bne a3, a1, .LBB9_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB9_1 Depth=1
-; RV64IAXCHERI-NEXT:    sc.c.aqrl a4, ca2, (a0)
+; RV64IAXCHERI-NEXT:    sc.c.aqrl a4, a2, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a4, .LBB9_1
 ; RV64IAXCHERI-NEXT:  .LBB9_3:
 ; RV64IAXCHERI-NEXT:    ret
diff --git a/llvm/test/CodeGen/RISCV/cheri/atomic-cmpxchg.ll b/llvm/test/CodeGen/RISCV/cheri/atomic-cmpxchg.ll
index 7180ab4551bf9..871dfdab2b62a 100644
--- a/llvm/test/CodeGen/RISCV/cheri/atomic-cmpxchg.ll
+++ b/llvm/test/CodeGen/RISCV/cheri/atomic-cmpxchg.ll
@@ -11,16 +11,16 @@
 define void @cmpxchg_i8_monotonic_monotonic(ptr addrspace(200) %ptr, i8 %cmp, i8 %val) addrspace(200) nounwind {
 ; RV32IXCHERI-LABEL: cmpxchg_i8_monotonic_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csb a1, 7(csp)
-; RV32IXCHERI-NEXT:    cincoffset ca1, csp, 7
-; RV32IXCHERI-NEXT:    csetbounds ca1, ca1, 1
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csb a1, 7(sp)
+; RV32IXCHERI-NEXT:    cincoffset a1, sp, 7
+; RV32IXCHERI-NEXT:    csetbounds a1, a1, 1
 ; RV32IXCHERI-NEXT:    li a3, 0
 ; RV32IXCHERI-NEXT:    li a4, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_1
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: cmpxchg_i8_monotonic_monotonic:
@@ -28,26 +28,26 @@ define void @cmpxchg_i8_monotonic_monotonic(ptr addrspace(200) %ptr, i8 %cmp, i8
 ; RV32IAXCHERI-NEXT:    slli a1, a1, 24
 ; RV32IAXCHERI-NEXT:    srai a1, a1, 24
 ; RV32IAXCHERI-NEXT:  .LBB0_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.b a3, (ca0)
+; RV32IAXCHERI-NEXT:    clr.b a3, (a0)
 ; RV32IAXCHERI-NEXT:    bne a3, a1, .LBB0_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB0_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.b a4, a2, (ca0)
+; RV32IAXCHERI-NEXT:    csc.b a4, a2, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a4, .LBB0_1
 ; RV32IAXCHERI-NEXT:  .LBB0_3:
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: cmpxchg_i8_monotonic_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -32
-; RV64IXCHERI-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csb a1, 15(csp)
-; RV64IXCHERI-NEXT:    cincoffset ca1, csp, 15
-; RV64IXCHERI-NEXT:    csetbounds ca1, ca1, 1
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -32
+; RV64IXCHERI-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csb a1, 15(sp)
+; RV64IXCHERI-NEXT:    cincoffset a1, sp, 15
+; RV64IXCHERI-NEXT:    csetbounds a1, a1, 1
 ; RV64IXCHERI-NEXT:    li a3, 0
 ; RV64IXCHERI-NEXT:    li a4, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_1
-; RV64IXCHERI-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 32
+; RV64IXCHERI-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 32
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: cmpxchg_i8_monotonic_monotonic:
@@ -55,10 +55,10 @@ define void @cmpxchg_i8_monotonic_monotonic(ptr addrspace(200) %ptr, i8 %cmp, i8
 ; RV64IAXCHERI-NEXT:    slli a1, a1, 56
 ; RV64IAXCHERI-NEXT:    srai a1, a1, 56
 ; RV64IAXCHERI-NEXT:  .LBB0_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.b a3, (ca0)
+; RV64IAXCHERI-NEXT:    clr.b a3, (a0)
 ; RV64IAXCHERI-NEXT:    bne a3, a1, .LBB0_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB0_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.b a4, a2, (ca0)
+; RV64IAXCHERI-NEXT:    csc.b a4, a2, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a4, .LBB0_1
 ; RV64IAXCHERI-NEXT:  .LBB0_3:
 ; RV64IAXCHERI-NEXT:    cret
@@ -69,16 +69,16 @@ define void @cmpxchg_i8_monotonic_monotonic(ptr addrspace(200) %ptr, i8 %cmp, i8
 define void @cmpxchg_i8_acquire_monotonic(ptr addrspace(200) %ptr, i8 %cmp, i8 %val) addrspace(200) nounwind {
 ; RV32IXCHERI-LABEL: cmpxchg_i8_acquire_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csb a1, 7(csp)
-; RV32IXCHERI-NEXT:    cincoffset ca1, csp, 7
-; RV32IXCHERI-NEXT:    csetbounds ca1, ca1, 1
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csb a1, 7(sp)
+; RV32IXCHERI-NEXT:    cincoffset a1, sp, 7
+; RV32IXCHERI-NEXT:    csetbounds a1, a1, 1
 ; RV32IXCHERI-NEXT:    li a3, 2
 ; RV32IXCHERI-NEXT:    li a4, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_1
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: cmpxchg_i8_acquire_monotonic:
@@ -86,26 +86,26 @@ define void @cmpxchg_i8_acquire_monotonic(ptr addrspace(200) %ptr, i8 %cmp, i8 %
 ; RV32IAXCHERI-NEXT:    slli a1, a1, 24
 ; RV32IAXCHERI-NEXT:    srai a1, a1, 24
 ; RV32IAXCHERI-NEXT:  .LBB1_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.b.aq a3, (ca0)
+; RV32IAXCHERI-NEXT:    clr.b.aq a3, (a0)
 ; RV32IAXCHERI-NEXT:    bne a3, a1, .LBB1_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB1_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.b a4, a2, (ca0)
+; RV32IAXCHERI-NEXT:    csc.b a4, a2, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a4, .LBB1_1
 ; RV32IAXCHERI-NEXT:  .LBB1_3:
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: cmpxchg_i8_acquire_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -32
-; RV64IXCHERI-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csb a1, 15(csp)
-; RV64IXCHERI-NEXT:    cincoffset ca1, csp, 15
-; RV64IXCHERI-NEXT:    csetbounds ca1, ca1, 1
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -32
+; RV64IXCHERI-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csb a1, 15(sp)
+; RV64IXCHERI-NEXT:    cincoffset a1, sp, 15
+; RV64IXCHERI-NEXT:    csetbounds a1, a1, 1
 ; RV64IXCHERI-NEXT:    li a3, 2
 ; RV64IXCHERI-NEXT:    li a4, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_1
-; RV64IXCHERI-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 32
+; RV64IXCHERI-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 32
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: cmpxchg_i8_acquire_monotonic:
@@ -113,10 +113,10 @@ define void @cmpxchg_i8_acquire_monotonic(ptr addrspace(200) %ptr, i8 %cmp, i8 %
 ; RV64IAXCHERI-NEXT:    slli a1, a1, 56
 ; RV64IAXCHERI-NEXT:    srai a1, a1, 56
 ; RV64IAXCHERI-NEXT:  .LBB1_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.b.aq a3, (ca0)
+; RV64IAXCHERI-NEXT:    clr.b.aq a3, (a0)
 ; RV64IAXCHERI-NEXT:    bne a3, a1, .LBB1_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB1_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.b a4, a2, (ca0)
+; RV64IAXCHERI-NEXT:    csc.b a4, a2, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a4, .LBB1_1
 ; RV64IAXCHERI-NEXT:  .LBB1_3:
 ; RV64IAXCHERI-NEXT:    cret
@@ -127,16 +127,16 @@ define void @cmpxchg_i8_acquire_monotonic(ptr addrspace(200) %ptr, i8 %cmp, i8 %
 define void @cmpxchg_i8_acquire_acquire(ptr addrspace(200) %ptr, i8 %cmp, i8 %val) addrspace(200) nounwind {
 ; RV32IXCHERI-LABEL: cmpxchg_i8_acquire_acquire:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csb a1, 7(csp)
-; RV32IXCHERI-NEXT:    cincoffset ca1, csp, 7
-; RV32IXCHERI-NEXT:    csetbounds ca1, ca1, 1
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csb a1, 7(sp)
+; RV32IXCHERI-NEXT:    cincoffset a1, sp, 7
+; RV32IXCHERI-NEXT:    csetbounds a1, a1, 1
 ; RV32IXCHERI-NEXT:    li a3, 2
 ; RV32IXCHERI-NEXT:    li a4, 2
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_1
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: cmpxchg_i8_acquire_acquire:
@@ -144,26 +144,26 @@ define void @cmpxchg_i8_acquire_acquire(ptr addrspace(200) %ptr, i8 %cmp, i8 %va
 ; RV32IAXCHERI-NEXT:    slli a1, a1, 24
 ; RV32IAXCHERI-NEXT:    srai a1, a1, 24
 ; RV32IAXCHERI-NEXT:  .LBB2_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.b.aq a3, (ca0)
+; RV32IAXCHERI-NEXT:    clr.b.aq a3, (a0)
 ; RV32IAXCHERI-NEXT:    bne a3, a1, .LBB2_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB2_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.b a4, a2, (ca0)
+; RV32IAXCHERI-NEXT:    csc.b a4, a2, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a4, .LBB2_1
 ; RV32IAXCHERI-NEXT:  .LBB2_3:
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: cmpxchg_i8_acquire_acquire:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -32
-; RV64IXCHERI-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csb a1, 15(csp)
-; RV64IXCHERI-NEXT:    cincoffset ca1, csp, 15
-; RV64IXCHERI-NEXT:    csetbounds ca1, ca1, 1
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -32
+; RV64IXCHERI-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csb a1, 15(sp)
+; RV64IXCHERI-NEXT:    cincoffset a1, sp, 15
+; RV64IXCHERI-NEXT:    csetbounds a1, a1, 1
 ; RV64IXCHERI-NEXT:    li a3, 2
 ; RV64IXCHERI-NEXT:    li a4, 2
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_1
-; RV64IXCHERI-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 32
+; RV64IXCHERI-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 32
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: cmpxchg_i8_acquire_acquire:
@@ -171,10 +171,10 @@ define void @cmpxchg_i8_acquire_acquire(ptr addrspace(200) %ptr, i8 %cmp, i8 %va
 ; RV64IAXCHERI-NEXT:    slli a1, a1, 56
 ; RV64IAXCHERI-NEXT:    srai a1, a1, 56
 ; RV64IAXCHERI-NEXT:  .LBB2_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.b.aq a3, (ca0)
+; RV64IAXCHERI-NEXT:    clr.b.aq a3, (a0)
 ; RV64IAXCHERI-NEXT:    bne a3, a1, .LBB2_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB2_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.b a4, a2, (ca0)
+; RV64IAXCHERI-NEXT:    csc.b a4, a2, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a4, .LBB2_1
 ; RV64IAXCHERI-NEXT:  .LBB2_3:
 ; RV64IAXCHERI-NEXT:    cret
@@ -185,16 +185,16 @@ define void @cmpxchg_i8_acquire_acquire(ptr addrspace(200) %ptr, i8 %cmp, i8 %va
 define void @cmpxchg_i8_release_monotonic(ptr addrspace(200) %ptr, i8 %cmp, i8 %val) addrspace(200) nounwind {
 ; RV32IXCHERI-LABEL: cmpxchg_i8_release_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csb a1, 7(csp)
-; RV32IXCHERI-NEXT:    cincoffset ca1, csp, 7
-; RV32IXCHERI-NEXT:    csetbounds ca1, ca1, 1
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csb a1, 7(sp)
+; RV32IXCHERI-NEXT:    cincoffset a1, sp, 7
+; RV32IXCHERI-NEXT:    csetbounds a1, a1, 1
 ; RV32IXCHERI-NEXT:    li a3, 3
 ; RV32IXCHERI-NEXT:    li a4, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_1
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: cmpxchg_i8_release_monotonic:
@@ -202,26 +202,26 @@ define void @cmpxchg_i8_release_monotonic(ptr addrspace(200) %ptr, i8 %cmp, i8 %
 ; RV32IAXCHERI-NEXT:    slli a1, a1, 24
 ; RV32IAXCHERI-NEXT:    srai a1, a1, 24
 ; RV32IAXCHERI-NEXT:  .LBB3_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.b a3, (ca0)
+; RV32IAXCHERI-NEXT:    clr.b a3, (a0)
 ; RV32IAXCHERI-NEXT:    bne a3, a1, .LBB3_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB3_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.b.rl a4, a2, (ca0)
+; RV32IAXCHERI-NEXT:    csc.b.rl a4, a2, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a4, .LBB3_1
 ; RV32IAXCHERI-NEXT:  .LBB3_3:
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: cmpxchg_i8_release_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -32
-; RV64IXCHERI-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csb a1, 15(csp)
-; RV64IXCHERI-NEXT:    cincoffset ca1, csp, 15
-; RV64IXCHERI-NEXT:    csetbounds ca1, ca1, 1
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -32
+; RV64IXCHERI-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csb a1, 15(sp)
+; RV64IXCHERI-NEXT:    cincoffset a1, sp, 15
+; RV64IXCHERI-NEXT:    csetbounds a1, a1, 1
 ; RV64IXCHERI-NEXT:    li a3, 3
 ; RV64IXCHERI-NEXT:    li a4, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_1
-; RV64IXCHERI-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 32
+; RV64IXCHERI-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 32
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: cmpxchg_i8_release_monotonic:
@@ -229,10 +229,10 @@ define void @cmpxchg_i8_release_monotonic(ptr addrspace(200) %ptr, i8 %cmp, i8 %
 ; RV64IAXCHERI-NEXT:    slli a1, a1, 56
 ; RV64IAXCHERI-NEXT:    srai a1, a1, 56
 ; RV64IAXCHERI-NEXT:  .LBB3_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.b a3, (ca0)
+; RV64IAXCHERI-NEXT:    clr.b a3, (a0)
 ; RV64IAXCHERI-NEXT:    bne a3, a1, .LBB3_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB3_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.b.rl a4, a2, (ca0)
+; RV64IAXCHERI-NEXT:    csc.b.rl a4, a2, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a4, .LBB3_1
 ; RV64IAXCHERI-NEXT:  .LBB3_3:
 ; RV64IAXCHERI-NEXT:    cret
@@ -243,16 +243,16 @@ define void @cmpxchg_i8_release_monotonic(ptr addrspace(200) %ptr, i8 %cmp, i8 %
 define void @cmpxchg_i8_release_acquire(ptr addrspace(200) %ptr, i8 %cmp, i8 %val) addrspace(200) nounwind {
 ; RV32IXCHERI-LABEL: cmpxchg_i8_release_acquire:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csb a1, 7(csp)
-; RV32IXCHERI-NEXT:    cincoffset ca1, csp, 7
-; RV32IXCHERI-NEXT:    csetbounds ca1, ca1, 1
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csb a1, 7(sp)
+; RV32IXCHERI-NEXT:    cincoffset a1, sp, 7
+; RV32IXCHERI-NEXT:    csetbounds a1, a1, 1
 ; RV32IXCHERI-NEXT:    li a3, 3
 ; RV32IXCHERI-NEXT:    li a4, 2
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_1
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: cmpxchg_i8_release_acquire:
@@ -260,26 +260,26 @@ define void @cmpxchg_i8_release_acquire(ptr addrspace(200) %ptr, i8 %cmp, i8 %va
 ; RV32IAXCHERI-NEXT:    slli a1, a1, 24
 ; RV32IAXCHERI-NEXT:    srai a1, a1, 24
 ; RV32IAXCHERI-NEXT:  .LBB4_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.b.aq a3, (ca0)
+; RV32IAXCHERI-NEXT:    clr.b.aq a3, (a0)
 ; RV32IAXCHERI-NEXT:    bne a3, a1, .LBB4_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB4_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.b.rl a4, a2, (ca0)
+; RV32IAXCHERI-NEXT:    csc.b.rl a4, a2, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a4, .LBB4_1
 ; RV32IAXCHERI-NEXT:  .LBB4_3:
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: cmpxchg_i8_release_acquire:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -32
-; RV64IXCHERI-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csb a1, 15(csp)
-; RV64IXCHERI-NEXT:    cincoffset ca1, csp, 15
-; RV64IXCHERI-NEXT:    csetbounds ca1, ca1, 1
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -32
+; RV64IXCHERI-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csb a1, 15(sp)
+; RV64IXCHERI-NEXT:    cincoffset a1, sp, 15
+; RV64IXCHERI-NEXT:    csetbounds a1, a1, 1
 ; RV64IXCHERI-NEXT:    li a3, 3
 ; RV64IXCHERI-NEXT:    li a4, 2
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_1
-; RV64IXCHERI-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 32
+; RV64IXCHERI-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 32
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: cmpxchg_i8_release_acquire:
@@ -287,10 +287,10 @@ define void @cmpxchg_i8_release_acquire(ptr addrspace(200) %ptr, i8 %cmp, i8 %va
 ; RV64IAXCHERI-NEXT:    slli a1, a1, 56
 ; RV64IAXCHERI-NEXT:    srai a1, a1, 56
 ; RV64IAXCHERI-NEXT:  .LBB4_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.b.aq a3, (ca0)
+; RV64IAXCHERI-NEXT:    clr.b.aq a3, (a0)
 ; RV64IAXCHERI-NEXT:    bne a3, a1, .LBB4_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB4_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.b.rl a4, a2, (ca0)
+; RV64IAXCHERI-NEXT:    csc.b.rl a4, a2, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a4, .LBB4_1
 ; RV64IAXCHERI-NEXT:  .LBB4_3:
 ; RV64IAXCHERI-NEXT:    cret
@@ -301,16 +301,16 @@ define void @cmpxchg_i8_release_acquire(ptr addrspace(200) %ptr, i8 %cmp, i8 %va
 define void @cmpxchg_i8_acq_rel_monotonic(ptr addrspace(200) %ptr, i8 %cmp, i8 %val) addrspace(200) nounwind {
 ; RV32IXCHERI-LABEL: cmpxchg_i8_acq_rel_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csb a1, 7(csp)
-; RV32IXCHERI-NEXT:    cincoffset ca1, csp, 7
-; RV32IXCHERI-NEXT:    csetbounds ca1, ca1, 1
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csb a1, 7(sp)
+; RV32IXCHERI-NEXT:    cincoffset a1, sp, 7
+; RV32IXCHERI-NEXT:    csetbounds a1, a1, 1
 ; RV32IXCHERI-NEXT:    li a3, 4
 ; RV32IXCHERI-NEXT:    li a4, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_1
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: cmpxchg_i8_acq_rel_monotonic:
@@ -318,26 +318,26 @@ define void @cmpxchg_i8_acq_rel_monotonic(ptr addrspace(200) %ptr, i8 %cmp, i8 %
 ; RV32IAXCHERI-NEXT:    slli a1, a1, 24
 ; RV32IAXCHERI-NEXT:    srai a1, a1, 24
 ; RV32IAXCHERI-NEXT:  .LBB5_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.b.aq a3, (ca0)
+; RV32IAXCHERI-NEXT:    clr.b.aq a3, (a0)
 ; RV32IAXCHERI-NEXT:    bne a3, a1, .LBB5_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB5_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.b.rl a4, a2, (ca0)
+; RV32IAXCHERI-NEXT:    csc.b.rl a4, a2, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a4, .LBB5_1
 ; RV32IAXCHERI-NEXT:  .LBB5_3:
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: cmpxchg_i8_acq_rel_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -32
-; RV64IXCHERI-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csb a1, 15(csp)
-; RV64IXCHERI-NEXT:    cincoffset ca1, csp, 15
-; RV64IXCHERI-NEXT:    csetbounds ca1, ca1, 1
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -32
+; RV64IXCHERI-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csb a1, 15(sp)
+; RV64IXCHERI-NEXT:    cincoffset a1, sp, 15
+; RV64IXCHERI-NEXT:    csetbounds a1, a1, 1
 ; RV64IXCHERI-NEXT:    li a3, 4
 ; RV64IXCHERI-NEXT:    li a4, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_1
-; RV64IXCHERI-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 32
+; RV64IXCHERI-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 32
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: cmpxchg_i8_acq_rel_monotonic:
@@ -345,10 +345,10 @@ define void @cmpxchg_i8_acq_rel_monotonic(ptr addrspace(200) %ptr, i8 %cmp, i8 %
 ; RV64IAXCHERI-NEXT:    slli a1, a1, 56
 ; RV64IAXCHERI-NEXT:    srai a1, a1, 56
 ; RV64IAXCHERI-NEXT:  .LBB5_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.b.aq a3, (ca0)
+; RV64IAXCHERI-NEXT:    clr.b.aq a3, (a0)
 ; RV64IAXCHERI-NEXT:    bne a3, a1, .LBB5_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB5_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.b.rl a4, a2, (ca0)
+; RV64IAXCHERI-NEXT:    csc.b.rl a4, a2, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a4, .LBB5_1
 ; RV64IAXCHERI-NEXT:  .LBB5_3:
 ; RV64IAXCHERI-NEXT:    cret
@@ -359,16 +359,16 @@ define void @cmpxchg_i8_acq_rel_monotonic(ptr addrspace(200) %ptr, i8 %cmp, i8 %
 define void @cmpxchg_i8_acq_rel_acquire(ptr addrspace(200) %ptr, i8 %cmp, i8 %val) addrspace(200) nounwind {
 ; RV32IXCHERI-LABEL: cmpxchg_i8_acq_rel_acquire:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csb a1, 7(csp)
-; RV32IXCHERI-NEXT:    cincoffset ca1, csp, 7
-; RV32IXCHERI-NEXT:    csetbounds ca1, ca1, 1
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csb a1, 7(sp)
+; RV32IXCHERI-NEXT:    cincoffset a1, sp, 7
+; RV32IXCHERI-NEXT:    csetbounds a1, a1, 1
 ; RV32IXCHERI-NEXT:    li a3, 4
 ; RV32IXCHERI-NEXT:    li a4, 2
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_1
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: cmpxchg_i8_acq_rel_acquire:
@@ -376,26 +376,26 @@ define void @cmpxchg_i8_acq_rel_acquire(ptr addrspace(200) %ptr, i8 %cmp, i8 %va
 ; RV32IAXCHERI-NEXT:    slli a1, a1, 24
 ; RV32IAXCHERI-NEXT:    srai a1, a1, 24
 ; RV32IAXCHERI-NEXT:  .LBB6_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.b.aq a3, (ca0)
+; RV32IAXCHERI-NEXT:    clr.b.aq a3, (a0)
 ; RV32IAXCHERI-NEXT:    bne a3, a1, .LBB6_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB6_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.b.rl a4, a2, (ca0)
+; RV32IAXCHERI-NEXT:    csc.b.rl a4, a2, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a4, .LBB6_1
 ; RV32IAXCHERI-NEXT:  .LBB6_3:
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: cmpxchg_i8_acq_rel_acquire:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -32
-; RV64IXCHERI-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csb a1, 15(csp)
-; RV64IXCHERI-NEXT:    cincoffset ca1, csp, 15
-; RV64IXCHERI-NEXT:    csetbounds ca1, ca1, 1
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -32
+; RV64IXCHERI-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csb a1, 15(sp)
+; RV64IXCHERI-NEXT:    cincoffset a1, sp, 15
+; RV64IXCHERI-NEXT:    csetbounds a1, a1, 1
 ; RV64IXCHERI-NEXT:    li a3, 4
 ; RV64IXCHERI-NEXT:    li a4, 2
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_1
-; RV64IXCHERI-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 32
+; RV64IXCHERI-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 32
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: cmpxchg_i8_acq_rel_acquire:
@@ -403,10 +403,10 @@ define void @cmpxchg_i8_acq_rel_acquire(ptr addrspace(200) %ptr, i8 %cmp, i8 %va
 ; RV64IAXCHERI-NEXT:    slli a1, a1, 56
 ; RV64IAXCHERI-NEXT:    srai a1, a1, 56
 ; RV64IAXCHERI-NEXT:  .LBB6_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.b.aq a3, (ca0)
+; RV64IAXCHERI-NEXT:    clr.b.aq a3, (a0)
 ; RV64IAXCHERI-NEXT:    bne a3, a1, .LBB6_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB6_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.b.rl a4, a2, (ca0)
+; RV64IAXCHERI-NEXT:    csc.b.rl a4, a2, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a4, .LBB6_1
 ; RV64IAXCHERI-NEXT:  .LBB6_3:
 ; RV64IAXCHERI-NEXT:    cret
@@ -417,16 +417,16 @@ define void @cmpxchg_i8_acq_rel_acquire(ptr addrspace(200) %ptr, i8 %cmp, i8 %va
 define void @cmpxchg_i8_seq_cst_monotonic(ptr addrspace(200) %ptr, i8 %cmp, i8 %val) addrspace(200) nounwind {
 ; RV32IXCHERI-LABEL: cmpxchg_i8_seq_cst_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csb a1, 7(csp)
-; RV32IXCHERI-NEXT:    cincoffset ca1, csp, 7
-; RV32IXCHERI-NEXT:    csetbounds ca1, ca1, 1
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csb a1, 7(sp)
+; RV32IXCHERI-NEXT:    cincoffset a1, sp, 7
+; RV32IXCHERI-NEXT:    csetbounds a1, a1, 1
 ; RV32IXCHERI-NEXT:    li a3, 5
 ; RV32IXCHERI-NEXT:    li a4, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_1
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: cmpxchg_i8_seq_cst_monotonic:
@@ -434,26 +434,26 @@ define void @cmpxchg_i8_seq_cst_monotonic(ptr addrspace(200) %ptr, i8 %cmp, i8 %
 ; RV32IAXCHERI-NEXT:    slli a1, a1, 24
 ; RV32IAXCHERI-NEXT:    srai a1, a1, 24
 ; RV32IAXCHERI-NEXT:  .LBB7_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.b.aqrl a3, (ca0)
+; RV32IAXCHERI-NEXT:    clr.b.aqrl a3, (a0)
 ; RV32IAXCHERI-NEXT:    bne a3, a1, .LBB7_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB7_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.b.aqrl a4, a2, (ca0)
+; RV32IAXCHERI-NEXT:    csc.b.aqrl a4, a2, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a4, .LBB7_1
 ; RV32IAXCHERI-NEXT:  .LBB7_3:
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: cmpxchg_i8_seq_cst_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -32
-; RV64IXCHERI-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csb a1, 15(csp)
-; RV64IXCHERI-NEXT:    cincoffset ca1, csp, 15
-; RV64IXCHERI-NEXT:    csetbounds ca1, ca1, 1
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -32
+; RV64IXCHERI-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csb a1, 15(sp)
+; RV64IXCHERI-NEXT:    cincoffset a1, sp, 15
+; RV64IXCHERI-NEXT:    csetbounds a1, a1, 1
 ; RV64IXCHERI-NEXT:    li a3, 5
 ; RV64IXCHERI-NEXT:    li a4, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_1
-; RV64IXCHERI-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 32
+; RV64IXCHERI-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 32
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: cmpxchg_i8_seq_cst_monotonic:
@@ -461,10 +461,10 @@ define void @cmpxchg_i8_seq_cst_monotonic(ptr addrspace(200) %ptr, i8 %cmp, i8 %
 ; RV64IAXCHERI-NEXT:    slli a1, a1, 56
 ; RV64IAXCHERI-NEXT:    srai a1, a1, 56
 ; RV64IAXCHERI-NEXT:  .LBB7_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.b.aqrl a3, (ca0)
+; RV64IAXCHERI-NEXT:    clr.b.aqrl a3, (a0)
 ; RV64IAXCHERI-NEXT:    bne a3, a1, .LBB7_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB7_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.b.aqrl a4, a2, (ca0)
+; RV64IAXCHERI-NEXT:    csc.b.aqrl a4, a2, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a4, .LBB7_1
 ; RV64IAXCHERI-NEXT:  .LBB7_3:
 ; RV64IAXCHERI-NEXT:    cret
@@ -475,16 +475,16 @@ define void @cmpxchg_i8_seq_cst_monotonic(ptr addrspace(200) %ptr, i8 %cmp, i8 %
 define void @cmpxchg_i8_seq_cst_acquire(ptr addrspace(200) %ptr, i8 %cmp, i8 %val) addrspace(200) nounwind {
 ; RV32IXCHERI-LABEL: cmpxchg_i8_seq_cst_acquire:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csb a1, 7(csp)
-; RV32IXCHERI-NEXT:    cincoffset ca1, csp, 7
-; RV32IXCHERI-NEXT:    csetbounds ca1, ca1, 1
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csb a1, 7(sp)
+; RV32IXCHERI-NEXT:    cincoffset a1, sp, 7
+; RV32IXCHERI-NEXT:    csetbounds a1, a1, 1
 ; RV32IXCHERI-NEXT:    li a3, 5
 ; RV32IXCHERI-NEXT:    li a4, 2
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_1
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: cmpxchg_i8_seq_cst_acquire:
@@ -492,26 +492,26 @@ define void @cmpxchg_i8_seq_cst_acquire(ptr addrspace(200) %ptr, i8 %cmp, i8 %va
 ; RV32IAXCHERI-NEXT:    slli a1, a1, 24
 ; RV32IAXCHERI-NEXT:    srai a1, a1, 24
 ; RV32IAXCHERI-NEXT:  .LBB8_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.b.aqrl a3, (ca0)
+; RV32IAXCHERI-NEXT:    clr.b.aqrl a3, (a0)
 ; RV32IAXCHERI-NEXT:    bne a3, a1, .LBB8_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB8_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.b.aqrl a4, a2, (ca0)
+; RV32IAXCHERI-NEXT:    csc.b.aqrl a4, a2, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a4, .LBB8_1
 ; RV32IAXCHERI-NEXT:  .LBB8_3:
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: cmpxchg_i8_seq_cst_acquire:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -32
-; RV64IXCHERI-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csb a1, 15(csp)
-; RV64IXCHERI-NEXT:    cincoffset ca1, csp, 15
-; RV64IXCHERI-NEXT:    csetbounds ca1, ca1, 1
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -32
+; RV64IXCHERI-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csb a1, 15(sp)
+; RV64IXCHERI-NEXT:    cincoffset a1, sp, 15
+; RV64IXCHERI-NEXT:    csetbounds a1, a1, 1
 ; RV64IXCHERI-NEXT:    li a3, 5
 ; RV64IXCHERI-NEXT:    li a4, 2
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_1
-; RV64IXCHERI-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 32
+; RV64IXCHERI-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 32
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: cmpxchg_i8_seq_cst_acquire:
@@ -519,10 +519,10 @@ define void @cmpxchg_i8_seq_cst_acquire(ptr addrspace(200) %ptr, i8 %cmp, i8 %va
 ; RV64IAXCHERI-NEXT:    slli a1, a1, 56
 ; RV64IAXCHERI-NEXT:    srai a1, a1, 56
 ; RV64IAXCHERI-NEXT:  .LBB8_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.b.aqrl a3, (ca0)
+; RV64IAXCHERI-NEXT:    clr.b.aqrl a3, (a0)
 ; RV64IAXCHERI-NEXT:    bne a3, a1, .LBB8_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB8_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.b.aqrl a4, a2, (ca0)
+; RV64IAXCHERI-NEXT:    csc.b.aqrl a4, a2, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a4, .LBB8_1
 ; RV64IAXCHERI-NEXT:  .LBB8_3:
 ; RV64IAXCHERI-NEXT:    cret
@@ -533,16 +533,16 @@ define void @cmpxchg_i8_seq_cst_acquire(ptr addrspace(200) %ptr, i8 %cmp, i8 %va
 define void @cmpxchg_i8_seq_cst_seq_cst(ptr addrspace(200) %ptr, i8 %cmp, i8 %val) addrspace(200) nounwind {
 ; RV32IXCHERI-LABEL: cmpxchg_i8_seq_cst_seq_cst:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csb a1, 7(csp)
-; RV32IXCHERI-NEXT:    cincoffset ca1, csp, 7
-; RV32IXCHERI-NEXT:    csetbounds ca1, ca1, 1
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csb a1, 7(sp)
+; RV32IXCHERI-NEXT:    cincoffset a1, sp, 7
+; RV32IXCHERI-NEXT:    csetbounds a1, a1, 1
 ; RV32IXCHERI-NEXT:    li a3, 5
 ; RV32IXCHERI-NEXT:    li a4, 5
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_1
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: cmpxchg_i8_seq_cst_seq_cst:
@@ -550,26 +550,26 @@ define void @cmpxchg_i8_seq_cst_seq_cst(ptr addrspace(200) %ptr, i8 %cmp, i8 %va
 ; RV32IAXCHERI-NEXT:    slli a1, a1, 24
 ; RV32IAXCHERI-NEXT:    srai a1, a1, 24
 ; RV32IAXCHERI-NEXT:  .LBB9_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.b.aqrl a3, (ca0)
+; RV32IAXCHERI-NEXT:    clr.b.aqrl a3, (a0)
 ; RV32IAXCHERI-NEXT:    bne a3, a1, .LBB9_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB9_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.b.aqrl a4, a2, (ca0)
+; RV32IAXCHERI-NEXT:    csc.b.aqrl a4, a2, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a4, .LBB9_1
 ; RV32IAXCHERI-NEXT:  .LBB9_3:
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: cmpxchg_i8_seq_cst_seq_cst:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -32
-; RV64IXCHERI-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csb a1, 15(csp)
-; RV64IXCHERI-NEXT:    cincoffset ca1, csp, 15
-; RV64IXCHERI-NEXT:    csetbounds ca1, ca1, 1
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -32
+; RV64IXCHERI-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csb a1, 15(sp)
+; RV64IXCHERI-NEXT:    cincoffset a1, sp, 15
+; RV64IXCHERI-NEXT:    csetbounds a1, a1, 1
 ; RV64IXCHERI-NEXT:    li a3, 5
 ; RV64IXCHERI-NEXT:    li a4, 5
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_1
-; RV64IXCHERI-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 32
+; RV64IXCHERI-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 32
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: cmpxchg_i8_seq_cst_seq_cst:
@@ -577,10 +577,10 @@ define void @cmpxchg_i8_seq_cst_seq_cst(ptr addrspace(200) %ptr, i8 %cmp, i8 %va
 ; RV64IAXCHERI-NEXT:    slli a1, a1, 56
 ; RV64IAXCHERI-NEXT:    srai a1, a1, 56
 ; RV64IAXCHERI-NEXT:  .LBB9_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.b.aqrl a3, (ca0)
+; RV64IAXCHERI-NEXT:    clr.b.aqrl a3, (a0)
 ; RV64IAXCHERI-NEXT:    bne a3, a1, .LBB9_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB9_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.b.aqrl a4, a2, (ca0)
+; RV64IAXCHERI-NEXT:    csc.b.aqrl a4, a2, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a4, .LBB9_1
 ; RV64IAXCHERI-NEXT:  .LBB9_3:
 ; RV64IAXCHERI-NEXT:    cret
@@ -591,16 +591,16 @@ define void @cmpxchg_i8_seq_cst_seq_cst(ptr addrspace(200) %ptr, i8 %cmp, i8 %va
 define void @cmpxchg_i16_monotonic_monotonic(ptr addrspace(200) %ptr, i16 %cmp, i16 %val) addrspace(200) nounwind {
 ; RV32IXCHERI-LABEL: cmpxchg_i16_monotonic_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csh a1, 6(csp)
-; RV32IXCHERI-NEXT:    cincoffset ca1, csp, 6
-; RV32IXCHERI-NEXT:    csetbounds ca1, ca1, 2
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csh a1, 6(sp)
+; RV32IXCHERI-NEXT:    cincoffset a1, sp, 6
+; RV32IXCHERI-NEXT:    csetbounds a1, a1, 2
 ; RV32IXCHERI-NEXT:    li a3, 0
 ; RV32IXCHERI-NEXT:    li a4, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_2
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: cmpxchg_i16_monotonic_monotonic:
@@ -608,26 +608,26 @@ define void @cmpxchg_i16_monotonic_monotonic(ptr addrspace(200) %ptr, i16 %cmp,
 ; RV32IAXCHERI-NEXT:    slli a1, a1, 16
 ; RV32IAXCHERI-NEXT:    srai a1, a1, 16
 ; RV32IAXCHERI-NEXT:  .LBB10_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.h a3, (ca0)
+; RV32IAXCHERI-NEXT:    clr.h a3, (a0)
 ; RV32IAXCHERI-NEXT:    bne a3, a1, .LBB10_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB10_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.h a4, a2, (ca0)
+; RV32IAXCHERI-NEXT:    csc.h a4, a2, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a4, .LBB10_1
 ; RV32IAXCHERI-NEXT:  .LBB10_3:
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: cmpxchg_i16_monotonic_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -32
-; RV64IXCHERI-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csh a1, 14(csp)
-; RV64IXCHERI-NEXT:    cincoffset ca1, csp, 14
-; RV64IXCHERI-NEXT:    csetbounds ca1, ca1, 2
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -32
+; RV64IXCHERI-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csh a1, 14(sp)
+; RV64IXCHERI-NEXT:    cincoffset a1, sp, 14
+; RV64IXCHERI-NEXT:    csetbounds a1, a1, 2
 ; RV64IXCHERI-NEXT:    li a3, 0
 ; RV64IXCHERI-NEXT:    li a4, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_2
-; RV64IXCHERI-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 32
+; RV64IXCHERI-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 32
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: cmpxchg_i16_monotonic_monotonic:
@@ -635,10 +635,10 @@ define void @cmpxchg_i16_monotonic_monotonic(ptr addrspace(200) %ptr, i16 %cmp,
 ; RV64IAXCHERI-NEXT:    slli a1, a1, 48
 ; RV64IAXCHERI-NEXT:    srai a1, a1, 48
 ; RV64IAXCHERI-NEXT:  .LBB10_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.h a3, (ca0)
+; RV64IAXCHERI-NEXT:    clr.h a3, (a0)
 ; RV64IAXCHERI-NEXT:    bne a3, a1, .LBB10_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB10_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.h a4, a2, (ca0)
+; RV64IAXCHERI-NEXT:    csc.h a4, a2, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a4, .LBB10_1
 ; RV64IAXCHERI-NEXT:  .LBB10_3:
 ; RV64IAXCHERI-NEXT:    cret
@@ -649,16 +649,16 @@ define void @cmpxchg_i16_monotonic_monotonic(ptr addrspace(200) %ptr, i16 %cmp,
 define void @cmpxchg_i16_acquire_monotonic(ptr addrspace(200) %ptr, i16 %cmp, i16 %val) addrspace(200) nounwind {
 ; RV32IXCHERI-LABEL: cmpxchg_i16_acquire_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csh a1, 6(csp)
-; RV32IXCHERI-NEXT:    cincoffset ca1, csp, 6
-; RV32IXCHERI-NEXT:    csetbounds ca1, ca1, 2
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csh a1, 6(sp)
+; RV32IXCHERI-NEXT:    cincoffset a1, sp, 6
+; RV32IXCHERI-NEXT:    csetbounds a1, a1, 2
 ; RV32IXCHERI-NEXT:    li a3, 2
 ; RV32IXCHERI-NEXT:    li a4, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_2
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: cmpxchg_i16_acquire_monotonic:
@@ -666,26 +666,26 @@ define void @cmpxchg_i16_acquire_monotonic(ptr addrspace(200) %ptr, i16 %cmp, i1
 ; RV32IAXCHERI-NEXT:    slli a1, a1, 16
 ; RV32IAXCHERI-NEXT:    srai a1, a1, 16
 ; RV32IAXCHERI-NEXT:  .LBB11_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.h.aq a3, (ca0)
+; RV32IAXCHERI-NEXT:    clr.h.aq a3, (a0)
 ; RV32IAXCHERI-NEXT:    bne a3, a1, .LBB11_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB11_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.h a4, a2, (ca0)
+; RV32IAXCHERI-NEXT:    csc.h a4, a2, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a4, .LBB11_1
 ; RV32IAXCHERI-NEXT:  .LBB11_3:
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: cmpxchg_i16_acquire_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -32
-; RV64IXCHERI-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csh a1, 14(csp)
-; RV64IXCHERI-NEXT:    cincoffset ca1, csp, 14
-; RV64IXCHERI-NEXT:    csetbounds ca1, ca1, 2
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -32
+; RV64IXCHERI-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csh a1, 14(sp)
+; RV64IXCHERI-NEXT:    cincoffset a1, sp, 14
+; RV64IXCHERI-NEXT:    csetbounds a1, a1, 2
 ; RV64IXCHERI-NEXT:    li a3, 2
 ; RV64IXCHERI-NEXT:    li a4, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_2
-; RV64IXCHERI-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 32
+; RV64IXCHERI-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 32
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: cmpxchg_i16_acquire_monotonic:
@@ -693,10 +693,10 @@ define void @cmpxchg_i16_acquire_monotonic(ptr addrspace(200) %ptr, i16 %cmp, i1
 ; RV64IAXCHERI-NEXT:    slli a1, a1, 48
 ; RV64IAXCHERI-NEXT:    srai a1, a1, 48
 ; RV64IAXCHERI-NEXT:  .LBB11_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.h.aq a3, (ca0)
+; RV64IAXCHERI-NEXT:    clr.h.aq a3, (a0)
 ; RV64IAXCHERI-NEXT:    bne a3, a1, .LBB11_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB11_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.h a4, a2, (ca0)
+; RV64IAXCHERI-NEXT:    csc.h a4, a2, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a4, .LBB11_1
 ; RV64IAXCHERI-NEXT:  .LBB11_3:
 ; RV64IAXCHERI-NEXT:    cret
@@ -707,16 +707,16 @@ define void @cmpxchg_i16_acquire_monotonic(ptr addrspace(200) %ptr, i16 %cmp, i1
 define void @cmpxchg_i16_acquire_acquire(ptr addrspace(200) %ptr, i16 %cmp, i16 %val) addrspace(200) nounwind {
 ; RV32IXCHERI-LABEL: cmpxchg_i16_acquire_acquire:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csh a1, 6(csp)
-; RV32IXCHERI-NEXT:    cincoffset ca1, csp, 6
-; RV32IXCHERI-NEXT:    csetbounds ca1, ca1, 2
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csh a1, 6(sp)
+; RV32IXCHERI-NEXT:    cincoffset a1, sp, 6
+; RV32IXCHERI-NEXT:    csetbounds a1, a1, 2
 ; RV32IXCHERI-NEXT:    li a3, 2
 ; RV32IXCHERI-NEXT:    li a4, 2
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_2
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: cmpxchg_i16_acquire_acquire:
@@ -724,26 +724,26 @@ define void @cmpxchg_i16_acquire_acquire(ptr addrspace(200) %ptr, i16 %cmp, i16
 ; RV32IAXCHERI-NEXT:    slli a1, a1, 16
 ; RV32IAXCHERI-NEXT:    srai a1, a1, 16
 ; RV32IAXCHERI-NEXT:  .LBB12_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.h.aq a3, (ca0)
+; RV32IAXCHERI-NEXT:    clr.h.aq a3, (a0)
 ; RV32IAXCHERI-NEXT:    bne a3, a1, .LBB12_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB12_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.h a4, a2, (ca0)
+; RV32IAXCHERI-NEXT:    csc.h a4, a2, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a4, .LBB12_1
 ; RV32IAXCHERI-NEXT:  .LBB12_3:
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: cmpxchg_i16_acquire_acquire:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -32
-; RV64IXCHERI-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csh a1, 14(csp)
-; RV64IXCHERI-NEXT:    cincoffset ca1, csp, 14
-; RV64IXCHERI-NEXT:    csetbounds ca1, ca1, 2
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -32
+; RV64IXCHERI-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csh a1, 14(sp)
+; RV64IXCHERI-NEXT:    cincoffset a1, sp, 14
+; RV64IXCHERI-NEXT:    csetbounds a1, a1, 2
 ; RV64IXCHERI-NEXT:    li a3, 2
 ; RV64IXCHERI-NEXT:    li a4, 2
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_2
-; RV64IXCHERI-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 32
+; RV64IXCHERI-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 32
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: cmpxchg_i16_acquire_acquire:
@@ -751,10 +751,10 @@ define void @cmpxchg_i16_acquire_acquire(ptr addrspace(200) %ptr, i16 %cmp, i16
 ; RV64IAXCHERI-NEXT:    slli a1, a1, 48
 ; RV64IAXCHERI-NEXT:    srai a1, a1, 48
 ; RV64IAXCHERI-NEXT:  .LBB12_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.h.aq a3, (ca0)
+; RV64IAXCHERI-NEXT:    clr.h.aq a3, (a0)
 ; RV64IAXCHERI-NEXT:    bne a3, a1, .LBB12_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB12_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.h a4, a2, (ca0)
+; RV64IAXCHERI-NEXT:    csc.h a4, a2, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a4, .LBB12_1
 ; RV64IAXCHERI-NEXT:  .LBB12_3:
 ; RV64IAXCHERI-NEXT:    cret
@@ -765,16 +765,16 @@ define void @cmpxchg_i16_acquire_acquire(ptr addrspace(200) %ptr, i16 %cmp, i16
 define void @cmpxchg_i16_release_monotonic(ptr addrspace(200) %ptr, i16 %cmp, i16 %val) addrspace(200) nounwind {
 ; RV32IXCHERI-LABEL: cmpxchg_i16_release_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csh a1, 6(csp)
-; RV32IXCHERI-NEXT:    cincoffset ca1, csp, 6
-; RV32IXCHERI-NEXT:    csetbounds ca1, ca1, 2
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csh a1, 6(sp)
+; RV32IXCHERI-NEXT:    cincoffset a1, sp, 6
+; RV32IXCHERI-NEXT:    csetbounds a1, a1, 2
 ; RV32IXCHERI-NEXT:    li a3, 3
 ; RV32IXCHERI-NEXT:    li a4, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_2
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: cmpxchg_i16_release_monotonic:
@@ -782,26 +782,26 @@ define void @cmpxchg_i16_release_monotonic(ptr addrspace(200) %ptr, i16 %cmp, i1
 ; RV32IAXCHERI-NEXT:    slli a1, a1, 16
 ; RV32IAXCHERI-NEXT:    srai a1, a1, 16
 ; RV32IAXCHERI-NEXT:  .LBB13_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.h a3, (ca0)
+; RV32IAXCHERI-NEXT:    clr.h a3, (a0)
 ; RV32IAXCHERI-NEXT:    bne a3, a1, .LBB13_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB13_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.h.rl a4, a2, (ca0)
+; RV32IAXCHERI-NEXT:    csc.h.rl a4, a2, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a4, .LBB13_1
 ; RV32IAXCHERI-NEXT:  .LBB13_3:
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: cmpxchg_i16_release_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -32
-; RV64IXCHERI-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csh a1, 14(csp)
-; RV64IXCHERI-NEXT:    cincoffset ca1, csp, 14
-; RV64IXCHERI-NEXT:    csetbounds ca1, ca1, 2
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -32
+; RV64IXCHERI-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csh a1, 14(sp)
+; RV64IXCHERI-NEXT:    cincoffset a1, sp, 14
+; RV64IXCHERI-NEXT:    csetbounds a1, a1, 2
 ; RV64IXCHERI-NEXT:    li a3, 3
 ; RV64IXCHERI-NEXT:    li a4, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_2
-; RV64IXCHERI-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 32
+; RV64IXCHERI-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 32
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: cmpxchg_i16_release_monotonic:
@@ -809,10 +809,10 @@ define void @cmpxchg_i16_release_monotonic(ptr addrspace(200) %ptr, i16 %cmp, i1
 ; RV64IAXCHERI-NEXT:    slli a1, a1, 48
 ; RV64IAXCHERI-NEXT:    srai a1, a1, 48
 ; RV64IAXCHERI-NEXT:  .LBB13_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.h a3, (ca0)
+; RV64IAXCHERI-NEXT:    clr.h a3, (a0)
 ; RV64IAXCHERI-NEXT:    bne a3, a1, .LBB13_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB13_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.h.rl a4, a2, (ca0)
+; RV64IAXCHERI-NEXT:    csc.h.rl a4, a2, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a4, .LBB13_1
 ; RV64IAXCHERI-NEXT:  .LBB13_3:
 ; RV64IAXCHERI-NEXT:    cret
@@ -823,16 +823,16 @@ define void @cmpxchg_i16_release_monotonic(ptr addrspace(200) %ptr, i16 %cmp, i1
 define void @cmpxchg_i16_release_acquire(ptr addrspace(200) %ptr, i16 %cmp, i16 %val) addrspace(200) nounwind {
 ; RV32IXCHERI-LABEL: cmpxchg_i16_release_acquire:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csh a1, 6(csp)
-; RV32IXCHERI-NEXT:    cincoffset ca1, csp, 6
-; RV32IXCHERI-NEXT:    csetbounds ca1, ca1, 2
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csh a1, 6(sp)
+; RV32IXCHERI-NEXT:    cincoffset a1, sp, 6
+; RV32IXCHERI-NEXT:    csetbounds a1, a1, 2
 ; RV32IXCHERI-NEXT:    li a3, 3
 ; RV32IXCHERI-NEXT:    li a4, 2
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_2
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: cmpxchg_i16_release_acquire:
@@ -840,26 +840,26 @@ define void @cmpxchg_i16_release_acquire(ptr addrspace(200) %ptr, i16 %cmp, i16
 ; RV32IAXCHERI-NEXT:    slli a1, a1, 16
 ; RV32IAXCHERI-NEXT:    srai a1, a1, 16
 ; RV32IAXCHERI-NEXT:  .LBB14_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.h.aq a3, (ca0)
+; RV32IAXCHERI-NEXT:    clr.h.aq a3, (a0)
 ; RV32IAXCHERI-NEXT:    bne a3, a1, .LBB14_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB14_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.h.rl a4, a2, (ca0)
+; RV32IAXCHERI-NEXT:    csc.h.rl a4, a2, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a4, .LBB14_1
 ; RV32IAXCHERI-NEXT:  .LBB14_3:
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: cmpxchg_i16_release_acquire:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -32
-; RV64IXCHERI-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csh a1, 14(csp)
-; RV64IXCHERI-NEXT:    cincoffset ca1, csp, 14
-; RV64IXCHERI-NEXT:    csetbounds ca1, ca1, 2
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -32
+; RV64IXCHERI-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csh a1, 14(sp)
+; RV64IXCHERI-NEXT:    cincoffset a1, sp, 14
+; RV64IXCHERI-NEXT:    csetbounds a1, a1, 2
 ; RV64IXCHERI-NEXT:    li a3, 3
 ; RV64IXCHERI-NEXT:    li a4, 2
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_2
-; RV64IXCHERI-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 32
+; RV64IXCHERI-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 32
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: cmpxchg_i16_release_acquire:
@@ -867,10 +867,10 @@ define void @cmpxchg_i16_release_acquire(ptr addrspace(200) %ptr, i16 %cmp, i16
 ; RV64IAXCHERI-NEXT:    slli a1, a1, 48
 ; RV64IAXCHERI-NEXT:    srai a1, a1, 48
 ; RV64IAXCHERI-NEXT:  .LBB14_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.h.aq a3, (ca0)
+; RV64IAXCHERI-NEXT:    clr.h.aq a3, (a0)
 ; RV64IAXCHERI-NEXT:    bne a3, a1, .LBB14_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB14_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.h.rl a4, a2, (ca0)
+; RV64IAXCHERI-NEXT:    csc.h.rl a4, a2, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a4, .LBB14_1
 ; RV64IAXCHERI-NEXT:  .LBB14_3:
 ; RV64IAXCHERI-NEXT:    cret
@@ -881,16 +881,16 @@ define void @cmpxchg_i16_release_acquire(ptr addrspace(200) %ptr, i16 %cmp, i16
 define void @cmpxchg_i16_acq_rel_monotonic(ptr addrspace(200) %ptr, i16 %cmp, i16 %val) addrspace(200) nounwind {
 ; RV32IXCHERI-LABEL: cmpxchg_i16_acq_rel_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csh a1, 6(csp)
-; RV32IXCHERI-NEXT:    cincoffset ca1, csp, 6
-; RV32IXCHERI-NEXT:    csetbounds ca1, ca1, 2
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csh a1, 6(sp)
+; RV32IXCHERI-NEXT:    cincoffset a1, sp, 6
+; RV32IXCHERI-NEXT:    csetbounds a1, a1, 2
 ; RV32IXCHERI-NEXT:    li a3, 4
 ; RV32IXCHERI-NEXT:    li a4, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_2
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: cmpxchg_i16_acq_rel_monotonic:
@@ -898,26 +898,26 @@ define void @cmpxchg_i16_acq_rel_monotonic(ptr addrspace(200) %ptr, i16 %cmp, i1
 ; RV32IAXCHERI-NEXT:    slli a1, a1, 16
 ; RV32IAXCHERI-NEXT:    srai a1, a1, 16
 ; RV32IAXCHERI-NEXT:  .LBB15_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.h.aq a3, (ca0)
+; RV32IAXCHERI-NEXT:    clr.h.aq a3, (a0)
 ; RV32IAXCHERI-NEXT:    bne a3, a1, .LBB15_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB15_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.h.rl a4, a2, (ca0)
+; RV32IAXCHERI-NEXT:    csc.h.rl a4, a2, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a4, .LBB15_1
 ; RV32IAXCHERI-NEXT:  .LBB15_3:
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: cmpxchg_i16_acq_rel_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -32
-; RV64IXCHERI-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csh a1, 14(csp)
-; RV64IXCHERI-NEXT:    cincoffset ca1, csp, 14
-; RV64IXCHERI-NEXT:    csetbounds ca1, ca1, 2
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -32
+; RV64IXCHERI-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csh a1, 14(sp)
+; RV64IXCHERI-NEXT:    cincoffset a1, sp, 14
+; RV64IXCHERI-NEXT:    csetbounds a1, a1, 2
 ; RV64IXCHERI-NEXT:    li a3, 4
 ; RV64IXCHERI-NEXT:    li a4, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_2
-; RV64IXCHERI-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 32
+; RV64IXCHERI-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 32
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: cmpxchg_i16_acq_rel_monotonic:
@@ -925,10 +925,10 @@ define void @cmpxchg_i16_acq_rel_monotonic(ptr addrspace(200) %ptr, i16 %cmp, i1
 ; RV64IAXCHERI-NEXT:    slli a1, a1, 48
 ; RV64IAXCHERI-NEXT:    srai a1, a1, 48
 ; RV64IAXCHERI-NEXT:  .LBB15_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.h.aq a3, (ca0)
+; RV64IAXCHERI-NEXT:    clr.h.aq a3, (a0)
 ; RV64IAXCHERI-NEXT:    bne a3, a1, .LBB15_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB15_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.h.rl a4, a2, (ca0)
+; RV64IAXCHERI-NEXT:    csc.h.rl a4, a2, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a4, .LBB15_1
 ; RV64IAXCHERI-NEXT:  .LBB15_3:
 ; RV64IAXCHERI-NEXT:    cret
@@ -939,16 +939,16 @@ define void @cmpxchg_i16_acq_rel_monotonic(ptr addrspace(200) %ptr, i16 %cmp, i1
 define void @cmpxchg_i16_acq_rel_acquire(ptr addrspace(200) %ptr, i16 %cmp, i16 %val) addrspace(200) nounwind {
 ; RV32IXCHERI-LABEL: cmpxchg_i16_acq_rel_acquire:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csh a1, 6(csp)
-; RV32IXCHERI-NEXT:    cincoffset ca1, csp, 6
-; RV32IXCHERI-NEXT:    csetbounds ca1, ca1, 2
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csh a1, 6(sp)
+; RV32IXCHERI-NEXT:    cincoffset a1, sp, 6
+; RV32IXCHERI-NEXT:    csetbounds a1, a1, 2
 ; RV32IXCHERI-NEXT:    li a3, 4
 ; RV32IXCHERI-NEXT:    li a4, 2
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_2
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: cmpxchg_i16_acq_rel_acquire:
@@ -956,26 +956,26 @@ define void @cmpxchg_i16_acq_rel_acquire(ptr addrspace(200) %ptr, i16 %cmp, i16
 ; RV32IAXCHERI-NEXT:    slli a1, a1, 16
 ; RV32IAXCHERI-NEXT:    srai a1, a1, 16
 ; RV32IAXCHERI-NEXT:  .LBB16_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.h.aq a3, (ca0)
+; RV32IAXCHERI-NEXT:    clr.h.aq a3, (a0)
 ; RV32IAXCHERI-NEXT:    bne a3, a1, .LBB16_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB16_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.h.rl a4, a2, (ca0)
+; RV32IAXCHERI-NEXT:    csc.h.rl a4, a2, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a4, .LBB16_1
 ; RV32IAXCHERI-NEXT:  .LBB16_3:
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: cmpxchg_i16_acq_rel_acquire:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -32
-; RV64IXCHERI-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csh a1, 14(csp)
-; RV64IXCHERI-NEXT:    cincoffset ca1, csp, 14
-; RV64IXCHERI-NEXT:    csetbounds ca1, ca1, 2
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -32
+; RV64IXCHERI-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csh a1, 14(sp)
+; RV64IXCHERI-NEXT:    cincoffset a1, sp, 14
+; RV64IXCHERI-NEXT:    csetbounds a1, a1, 2
 ; RV64IXCHERI-NEXT:    li a3, 4
 ; RV64IXCHERI-NEXT:    li a4, 2
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_2
-; RV64IXCHERI-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 32
+; RV64IXCHERI-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 32
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: cmpxchg_i16_acq_rel_acquire:
@@ -983,10 +983,10 @@ define void @cmpxchg_i16_acq_rel_acquire(ptr addrspace(200) %ptr, i16 %cmp, i16
 ; RV64IAXCHERI-NEXT:    slli a1, a1, 48
 ; RV64IAXCHERI-NEXT:    srai a1, a1, 48
 ; RV64IAXCHERI-NEXT:  .LBB16_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.h.aq a3, (ca0)
+; RV64IAXCHERI-NEXT:    clr.h.aq a3, (a0)
 ; RV64IAXCHERI-NEXT:    bne a3, a1, .LBB16_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB16_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.h.rl a4, a2, (ca0)
+; RV64IAXCHERI-NEXT:    csc.h.rl a4, a2, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a4, .LBB16_1
 ; RV64IAXCHERI-NEXT:  .LBB16_3:
 ; RV64IAXCHERI-NEXT:    cret
@@ -997,16 +997,16 @@ define void @cmpxchg_i16_acq_rel_acquire(ptr addrspace(200) %ptr, i16 %cmp, i16
 define void @cmpxchg_i16_seq_cst_monotonic(ptr addrspace(200) %ptr, i16 %cmp, i16 %val) addrspace(200) nounwind {
 ; RV32IXCHERI-LABEL: cmpxchg_i16_seq_cst_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csh a1, 6(csp)
-; RV32IXCHERI-NEXT:    cincoffset ca1, csp, 6
-; RV32IXCHERI-NEXT:    csetbounds ca1, ca1, 2
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csh a1, 6(sp)
+; RV32IXCHERI-NEXT:    cincoffset a1, sp, 6
+; RV32IXCHERI-NEXT:    csetbounds a1, a1, 2
 ; RV32IXCHERI-NEXT:    li a3, 5
 ; RV32IXCHERI-NEXT:    li a4, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_2
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: cmpxchg_i16_seq_cst_monotonic:
@@ -1014,26 +1014,26 @@ define void @cmpxchg_i16_seq_cst_monotonic(ptr addrspace(200) %ptr, i16 %cmp, i1
 ; RV32IAXCHERI-NEXT:    slli a1, a1, 16
 ; RV32IAXCHERI-NEXT:    srai a1, a1, 16
 ; RV32IAXCHERI-NEXT:  .LBB17_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.h.aqrl a3, (ca0)
+; RV32IAXCHERI-NEXT:    clr.h.aqrl a3, (a0)
 ; RV32IAXCHERI-NEXT:    bne a3, a1, .LBB17_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB17_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.h.aqrl a4, a2, (ca0)
+; RV32IAXCHERI-NEXT:    csc.h.aqrl a4, a2, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a4, .LBB17_1
 ; RV32IAXCHERI-NEXT:  .LBB17_3:
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: cmpxchg_i16_seq_cst_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -32
-; RV64IXCHERI-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csh a1, 14(csp)
-; RV64IXCHERI-NEXT:    cincoffset ca1, csp, 14
-; RV64IXCHERI-NEXT:    csetbounds ca1, ca1, 2
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -32
+; RV64IXCHERI-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csh a1, 14(sp)
+; RV64IXCHERI-NEXT:    cincoffset a1, sp, 14
+; RV64IXCHERI-NEXT:    csetbounds a1, a1, 2
 ; RV64IXCHERI-NEXT:    li a3, 5
 ; RV64IXCHERI-NEXT:    li a4, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_2
-; RV64IXCHERI-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 32
+; RV64IXCHERI-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 32
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: cmpxchg_i16_seq_cst_monotonic:
@@ -1041,10 +1041,10 @@ define void @cmpxchg_i16_seq_cst_monotonic(ptr addrspace(200) %ptr, i16 %cmp, i1
 ; RV64IAXCHERI-NEXT:    slli a1, a1, 48
 ; RV64IAXCHERI-NEXT:    srai a1, a1, 48
 ; RV64IAXCHERI-NEXT:  .LBB17_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.h.aqrl a3, (ca0)
+; RV64IAXCHERI-NEXT:    clr.h.aqrl a3, (a0)
 ; RV64IAXCHERI-NEXT:    bne a3, a1, .LBB17_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB17_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.h.aqrl a4, a2, (ca0)
+; RV64IAXCHERI-NEXT:    csc.h.aqrl a4, a2, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a4, .LBB17_1
 ; RV64IAXCHERI-NEXT:  .LBB17_3:
 ; RV64IAXCHERI-NEXT:    cret
@@ -1055,16 +1055,16 @@ define void @cmpxchg_i16_seq_cst_monotonic(ptr addrspace(200) %ptr, i16 %cmp, i1
 define void @cmpxchg_i16_seq_cst_acquire(ptr addrspace(200) %ptr, i16 %cmp, i16 %val) addrspace(200) nounwind {
 ; RV32IXCHERI-LABEL: cmpxchg_i16_seq_cst_acquire:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csh a1, 6(csp)
-; RV32IXCHERI-NEXT:    cincoffset ca1, csp, 6
-; RV32IXCHERI-NEXT:    csetbounds ca1, ca1, 2
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csh a1, 6(sp)
+; RV32IXCHERI-NEXT:    cincoffset a1, sp, 6
+; RV32IXCHERI-NEXT:    csetbounds a1, a1, 2
 ; RV32IXCHERI-NEXT:    li a3, 5
 ; RV32IXCHERI-NEXT:    li a4, 2
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_2
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: cmpxchg_i16_seq_cst_acquire:
@@ -1072,26 +1072,26 @@ define void @cmpxchg_i16_seq_cst_acquire(ptr addrspace(200) %ptr, i16 %cmp, i16
 ; RV32IAXCHERI-NEXT:    slli a1, a1, 16
 ; RV32IAXCHERI-NEXT:    srai a1, a1, 16
 ; RV32IAXCHERI-NEXT:  .LBB18_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.h.aqrl a3, (ca0)
+; RV32IAXCHERI-NEXT:    clr.h.aqrl a3, (a0)
 ; RV32IAXCHERI-NEXT:    bne a3, a1, .LBB18_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB18_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.h.aqrl a4, a2, (ca0)
+; RV32IAXCHERI-NEXT:    csc.h.aqrl a4, a2, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a4, .LBB18_1
 ; RV32IAXCHERI-NEXT:  .LBB18_3:
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: cmpxchg_i16_seq_cst_acquire:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -32
-; RV64IXCHERI-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csh a1, 14(csp)
-; RV64IXCHERI-NEXT:    cincoffset ca1, csp, 14
-; RV64IXCHERI-NEXT:    csetbounds ca1, ca1, 2
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -32
+; RV64IXCHERI-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csh a1, 14(sp)
+; RV64IXCHERI-NEXT:    cincoffset a1, sp, 14
+; RV64IXCHERI-NEXT:    csetbounds a1, a1, 2
 ; RV64IXCHERI-NEXT:    li a3, 5
 ; RV64IXCHERI-NEXT:    li a4, 2
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_2
-; RV64IXCHERI-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 32
+; RV64IXCHERI-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 32
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: cmpxchg_i16_seq_cst_acquire:
@@ -1099,10 +1099,10 @@ define void @cmpxchg_i16_seq_cst_acquire(ptr addrspace(200) %ptr, i16 %cmp, i16
 ; RV64IAXCHERI-NEXT:    slli a1, a1, 48
 ; RV64IAXCHERI-NEXT:    srai a1, a1, 48
 ; RV64IAXCHERI-NEXT:  .LBB18_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.h.aqrl a3, (ca0)
+; RV64IAXCHERI-NEXT:    clr.h.aqrl a3, (a0)
 ; RV64IAXCHERI-NEXT:    bne a3, a1, .LBB18_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB18_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.h.aqrl a4, a2, (ca0)
+; RV64IAXCHERI-NEXT:    csc.h.aqrl a4, a2, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a4, .LBB18_1
 ; RV64IAXCHERI-NEXT:  .LBB18_3:
 ; RV64IAXCHERI-NEXT:    cret
@@ -1113,16 +1113,16 @@ define void @cmpxchg_i16_seq_cst_acquire(ptr addrspace(200) %ptr, i16 %cmp, i16
 define void @cmpxchg_i16_seq_cst_seq_cst(ptr addrspace(200) %ptr, i16 %cmp, i16 %val) addrspace(200) nounwind {
 ; RV32IXCHERI-LABEL: cmpxchg_i16_seq_cst_seq_cst:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csh a1, 6(csp)
-; RV32IXCHERI-NEXT:    cincoffset ca1, csp, 6
-; RV32IXCHERI-NEXT:    csetbounds ca1, ca1, 2
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csh a1, 6(sp)
+; RV32IXCHERI-NEXT:    cincoffset a1, sp, 6
+; RV32IXCHERI-NEXT:    csetbounds a1, a1, 2
 ; RV32IXCHERI-NEXT:    li a3, 5
 ; RV32IXCHERI-NEXT:    li a4, 5
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_2
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: cmpxchg_i16_seq_cst_seq_cst:
@@ -1130,26 +1130,26 @@ define void @cmpxchg_i16_seq_cst_seq_cst(ptr addrspace(200) %ptr, i16 %cmp, i16
 ; RV32IAXCHERI-NEXT:    slli a1, a1, 16
 ; RV32IAXCHERI-NEXT:    srai a1, a1, 16
 ; RV32IAXCHERI-NEXT:  .LBB19_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.h.aqrl a3, (ca0)
+; RV32IAXCHERI-NEXT:    clr.h.aqrl a3, (a0)
 ; RV32IAXCHERI-NEXT:    bne a3, a1, .LBB19_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB19_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.h.aqrl a4, a2, (ca0)
+; RV32IAXCHERI-NEXT:    csc.h.aqrl a4, a2, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a4, .LBB19_1
 ; RV32IAXCHERI-NEXT:  .LBB19_3:
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: cmpxchg_i16_seq_cst_seq_cst:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -32
-; RV64IXCHERI-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csh a1, 14(csp)
-; RV64IXCHERI-NEXT:    cincoffset ca1, csp, 14
-; RV64IXCHERI-NEXT:    csetbounds ca1, ca1, 2
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -32
+; RV64IXCHERI-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csh a1, 14(sp)
+; RV64IXCHERI-NEXT:    cincoffset a1, sp, 14
+; RV64IXCHERI-NEXT:    csetbounds a1, a1, 2
 ; RV64IXCHERI-NEXT:    li a3, 5
 ; RV64IXCHERI-NEXT:    li a4, 5
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_2
-; RV64IXCHERI-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 32
+; RV64IXCHERI-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 32
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: cmpxchg_i16_seq_cst_seq_cst:
@@ -1157,10 +1157,10 @@ define void @cmpxchg_i16_seq_cst_seq_cst(ptr addrspace(200) %ptr, i16 %cmp, i16
 ; RV64IAXCHERI-NEXT:    slli a1, a1, 48
 ; RV64IAXCHERI-NEXT:    srai a1, a1, 48
 ; RV64IAXCHERI-NEXT:  .LBB19_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.h.aqrl a3, (ca0)
+; RV64IAXCHERI-NEXT:    clr.h.aqrl a3, (a0)
 ; RV64IAXCHERI-NEXT:    bne a3, a1, .LBB19_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB19_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.h.aqrl a4, a2, (ca0)
+; RV64IAXCHERI-NEXT:    csc.h.aqrl a4, a2, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a4, .LBB19_1
 ; RV64IAXCHERI-NEXT:  .LBB19_3:
 ; RV64IAXCHERI-NEXT:    cret
@@ -1171,51 +1171,51 @@ define void @cmpxchg_i16_seq_cst_seq_cst(ptr addrspace(200) %ptr, i16 %cmp, i16
 define void @cmpxchg_i32_monotonic_monotonic(ptr addrspace(200) %ptr, i32 %cmp, i32 %val) addrspace(200) nounwind {
 ; RV32IXCHERI-LABEL: cmpxchg_i32_monotonic_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csw a1, 4(csp)
-; RV32IXCHERI-NEXT:    cincoffset ca1, csp, 4
-; RV32IXCHERI-NEXT:    csetbounds ca1, ca1, 4
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csw a1, 4(sp)
+; RV32IXCHERI-NEXT:    cincoffset a1, sp, 4
+; RV32IXCHERI-NEXT:    csetbounds a1, a1, 4
 ; RV32IXCHERI-NEXT:    li a3, 0
 ; RV32IXCHERI-NEXT:    li a4, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_4
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: cmpxchg_i32_monotonic_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB20_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.w a3, (ca0)
+; RV32IAXCHERI-NEXT:    clr.w a3, (a0)
 ; RV32IAXCHERI-NEXT:    bne a3, a1, .LBB20_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB20_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.w a4, a2, (ca0)
+; RV32IAXCHERI-NEXT:    csc.w a4, a2, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a4, .LBB20_1
 ; RV32IAXCHERI-NEXT:  .LBB20_3:
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: cmpxchg_i32_monotonic_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -32
-; RV64IXCHERI-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csw a1, 12(csp)
-; RV64IXCHERI-NEXT:    cincoffset ca1, csp, 12
-; RV64IXCHERI-NEXT:    csetbounds ca1, ca1, 4
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -32
+; RV64IXCHERI-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csw a1, 12(sp)
+; RV64IXCHERI-NEXT:    cincoffset a1, sp, 12
+; RV64IXCHERI-NEXT:    csetbounds a1, a1, 4
 ; RV64IXCHERI-NEXT:    li a3, 0
 ; RV64IXCHERI-NEXT:    li a4, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_4
-; RV64IXCHERI-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 32
+; RV64IXCHERI-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 32
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: cmpxchg_i32_monotonic_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:    sext.w a1, a1
 ; RV64IAXCHERI-NEXT:  .LBB20_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.w a3, (ca0)
+; RV64IAXCHERI-NEXT:    clr.w a3, (a0)
 ; RV64IAXCHERI-NEXT:    bne a3, a1, .LBB20_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB20_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.w a4, a2, (ca0)
+; RV64IAXCHERI-NEXT:    csc.w a4, a2, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a4, .LBB20_1
 ; RV64IAXCHERI-NEXT:  .LBB20_3:
 ; RV64IAXCHERI-NEXT:    cret
@@ -1226,51 +1226,51 @@ define void @cmpxchg_i32_monotonic_monotonic(ptr addrspace(200) %ptr, i32 %cmp,
 define void @cmpxchg_i32_acquire_monotonic(ptr addrspace(200) %ptr, i32 %cmp, i32 %val) addrspace(200) nounwind {
 ; RV32IXCHERI-LABEL: cmpxchg_i32_acquire_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csw a1, 4(csp)
-; RV32IXCHERI-NEXT:    cincoffset ca1, csp, 4
-; RV32IXCHERI-NEXT:    csetbounds ca1, ca1, 4
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csw a1, 4(sp)
+; RV32IXCHERI-NEXT:    cincoffset a1, sp, 4
+; RV32IXCHERI-NEXT:    csetbounds a1, a1, 4
 ; RV32IXCHERI-NEXT:    li a3, 2
 ; RV32IXCHERI-NEXT:    li a4, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_4
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: cmpxchg_i32_acquire_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB21_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.w.aq a3, (ca0)
+; RV32IAXCHERI-NEXT:    clr.w.aq a3, (a0)
 ; RV32IAXCHERI-NEXT:    bne a3, a1, .LBB21_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB21_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.w a4, a2, (ca0)
+; RV32IAXCHERI-NEXT:    csc.w a4, a2, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a4, .LBB21_1
 ; RV32IAXCHERI-NEXT:  .LBB21_3:
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: cmpxchg_i32_acquire_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -32
-; RV64IXCHERI-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csw a1, 12(csp)
-; RV64IXCHERI-NEXT:    cincoffset ca1, csp, 12
-; RV64IXCHERI-NEXT:    csetbounds ca1, ca1, 4
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -32
+; RV64IXCHERI-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csw a1, 12(sp)
+; RV64IXCHERI-NEXT:    cincoffset a1, sp, 12
+; RV64IXCHERI-NEXT:    csetbounds a1, a1, 4
 ; RV64IXCHERI-NEXT:    li a3, 2
 ; RV64IXCHERI-NEXT:    li a4, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_4
-; RV64IXCHERI-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 32
+; RV64IXCHERI-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 32
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: cmpxchg_i32_acquire_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:    sext.w a1, a1
 ; RV64IAXCHERI-NEXT:  .LBB21_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.w.aq a3, (ca0)
+; RV64IAXCHERI-NEXT:    clr.w.aq a3, (a0)
 ; RV64IAXCHERI-NEXT:    bne a3, a1, .LBB21_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB21_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.w a4, a2, (ca0)
+; RV64IAXCHERI-NEXT:    csc.w a4, a2, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a4, .LBB21_1
 ; RV64IAXCHERI-NEXT:  .LBB21_3:
 ; RV64IAXCHERI-NEXT:    cret
@@ -1281,51 +1281,51 @@ define void @cmpxchg_i32_acquire_monotonic(ptr addrspace(200) %ptr, i32 %cmp, i3
 define void @cmpxchg_i32_acquire_acquire(ptr addrspace(200) %ptr, i32 %cmp, i32 %val) addrspace(200) nounwind {
 ; RV32IXCHERI-LABEL: cmpxchg_i32_acquire_acquire:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csw a1, 4(csp)
-; RV32IXCHERI-NEXT:    cincoffset ca1, csp, 4
-; RV32IXCHERI-NEXT:    csetbounds ca1, ca1, 4
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csw a1, 4(sp)
+; RV32IXCHERI-NEXT:    cincoffset a1, sp, 4
+; RV32IXCHERI-NEXT:    csetbounds a1, a1, 4
 ; RV32IXCHERI-NEXT:    li a3, 2
 ; RV32IXCHERI-NEXT:    li a4, 2
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_4
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: cmpxchg_i32_acquire_acquire:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB22_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.w.aq a3, (ca0)
+; RV32IAXCHERI-NEXT:    clr.w.aq a3, (a0)
 ; RV32IAXCHERI-NEXT:    bne a3, a1, .LBB22_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB22_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.w a4, a2, (ca0)
+; RV32IAXCHERI-NEXT:    csc.w a4, a2, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a4, .LBB22_1
 ; RV32IAXCHERI-NEXT:  .LBB22_3:
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: cmpxchg_i32_acquire_acquire:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -32
-; RV64IXCHERI-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csw a1, 12(csp)
-; RV64IXCHERI-NEXT:    cincoffset ca1, csp, 12
-; RV64IXCHERI-NEXT:    csetbounds ca1, ca1, 4
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -32
+; RV64IXCHERI-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csw a1, 12(sp)
+; RV64IXCHERI-NEXT:    cincoffset a1, sp, 12
+; RV64IXCHERI-NEXT:    csetbounds a1, a1, 4
 ; RV64IXCHERI-NEXT:    li a3, 2
 ; RV64IXCHERI-NEXT:    li a4, 2
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_4
-; RV64IXCHERI-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 32
+; RV64IXCHERI-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 32
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: cmpxchg_i32_acquire_acquire:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:    sext.w a1, a1
 ; RV64IAXCHERI-NEXT:  .LBB22_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.w.aq a3, (ca0)
+; RV64IAXCHERI-NEXT:    clr.w.aq a3, (a0)
 ; RV64IAXCHERI-NEXT:    bne a3, a1, .LBB22_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB22_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.w a4, a2, (ca0)
+; RV64IAXCHERI-NEXT:    csc.w a4, a2, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a4, .LBB22_1
 ; RV64IAXCHERI-NEXT:  .LBB22_3:
 ; RV64IAXCHERI-NEXT:    cret
@@ -1336,51 +1336,51 @@ define void @cmpxchg_i32_acquire_acquire(ptr addrspace(200) %ptr, i32 %cmp, i32
 define void @cmpxchg_i32_release_monotonic(ptr addrspace(200) %ptr, i32 %cmp, i32 %val) addrspace(200) nounwind {
 ; RV32IXCHERI-LABEL: cmpxchg_i32_release_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csw a1, 4(csp)
-; RV32IXCHERI-NEXT:    cincoffset ca1, csp, 4
-; RV32IXCHERI-NEXT:    csetbounds ca1, ca1, 4
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csw a1, 4(sp)
+; RV32IXCHERI-NEXT:    cincoffset a1, sp, 4
+; RV32IXCHERI-NEXT:    csetbounds a1, a1, 4
 ; RV32IXCHERI-NEXT:    li a3, 3
 ; RV32IXCHERI-NEXT:    li a4, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_4
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: cmpxchg_i32_release_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB23_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.w a3, (ca0)
+; RV32IAXCHERI-NEXT:    clr.w a3, (a0)
 ; RV32IAXCHERI-NEXT:    bne a3, a1, .LBB23_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB23_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.w.rl a4, a2, (ca0)
+; RV32IAXCHERI-NEXT:    csc.w.rl a4, a2, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a4, .LBB23_1
 ; RV32IAXCHERI-NEXT:  .LBB23_3:
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: cmpxchg_i32_release_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -32
-; RV64IXCHERI-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csw a1, 12(csp)
-; RV64IXCHERI-NEXT:    cincoffset ca1, csp, 12
-; RV64IXCHERI-NEXT:    csetbounds ca1, ca1, 4
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -32
+; RV64IXCHERI-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csw a1, 12(sp)
+; RV64IXCHERI-NEXT:    cincoffset a1, sp, 12
+; RV64IXCHERI-NEXT:    csetbounds a1, a1, 4
 ; RV64IXCHERI-NEXT:    li a3, 3
 ; RV64IXCHERI-NEXT:    li a4, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_4
-; RV64IXCHERI-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 32
+; RV64IXCHERI-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 32
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: cmpxchg_i32_release_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:    sext.w a1, a1
 ; RV64IAXCHERI-NEXT:  .LBB23_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.w a3, (ca0)
+; RV64IAXCHERI-NEXT:    clr.w a3, (a0)
 ; RV64IAXCHERI-NEXT:    bne a3, a1, .LBB23_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB23_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.w.rl a4, a2, (ca0)
+; RV64IAXCHERI-NEXT:    csc.w.rl a4, a2, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a4, .LBB23_1
 ; RV64IAXCHERI-NEXT:  .LBB23_3:
 ; RV64IAXCHERI-NEXT:    cret
@@ -1391,51 +1391,51 @@ define void @cmpxchg_i32_release_monotonic(ptr addrspace(200) %ptr, i32 %cmp, i3
 define void @cmpxchg_i32_release_acquire(ptr addrspace(200) %ptr, i32 %cmp, i32 %val) addrspace(200) nounwind {
 ; RV32IXCHERI-LABEL: cmpxchg_i32_release_acquire:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csw a1, 4(csp)
-; RV32IXCHERI-NEXT:    cincoffset ca1, csp, 4
-; RV32IXCHERI-NEXT:    csetbounds ca1, ca1, 4
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csw a1, 4(sp)
+; RV32IXCHERI-NEXT:    cincoffset a1, sp, 4
+; RV32IXCHERI-NEXT:    csetbounds a1, a1, 4
 ; RV32IXCHERI-NEXT:    li a3, 3
 ; RV32IXCHERI-NEXT:    li a4, 2
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_4
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: cmpxchg_i32_release_acquire:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB24_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.w.aq a3, (ca0)
+; RV32IAXCHERI-NEXT:    clr.w.aq a3, (a0)
 ; RV32IAXCHERI-NEXT:    bne a3, a1, .LBB24_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB24_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.w.rl a4, a2, (ca0)
+; RV32IAXCHERI-NEXT:    csc.w.rl a4, a2, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a4, .LBB24_1
 ; RV32IAXCHERI-NEXT:  .LBB24_3:
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: cmpxchg_i32_release_acquire:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -32
-; RV64IXCHERI-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csw a1, 12(csp)
-; RV64IXCHERI-NEXT:    cincoffset ca1, csp, 12
-; RV64IXCHERI-NEXT:    csetbounds ca1, ca1, 4
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -32
+; RV64IXCHERI-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csw a1, 12(sp)
+; RV64IXCHERI-NEXT:    cincoffset a1, sp, 12
+; RV64IXCHERI-NEXT:    csetbounds a1, a1, 4
 ; RV64IXCHERI-NEXT:    li a3, 3
 ; RV64IXCHERI-NEXT:    li a4, 2
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_4
-; RV64IXCHERI-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 32
+; RV64IXCHERI-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 32
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: cmpxchg_i32_release_acquire:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:    sext.w a1, a1
 ; RV64IAXCHERI-NEXT:  .LBB24_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.w.aq a3, (ca0)
+; RV64IAXCHERI-NEXT:    clr.w.aq a3, (a0)
 ; RV64IAXCHERI-NEXT:    bne a3, a1, .LBB24_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB24_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.w.rl a4, a2, (ca0)
+; RV64IAXCHERI-NEXT:    csc.w.rl a4, a2, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a4, .LBB24_1
 ; RV64IAXCHERI-NEXT:  .LBB24_3:
 ; RV64IAXCHERI-NEXT:    cret
@@ -1446,51 +1446,51 @@ define void @cmpxchg_i32_release_acquire(ptr addrspace(200) %ptr, i32 %cmp, i32
 define void @cmpxchg_i32_acq_rel_monotonic(ptr addrspace(200) %ptr, i32 %cmp, i32 %val) addrspace(200) nounwind {
 ; RV32IXCHERI-LABEL: cmpxchg_i32_acq_rel_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csw a1, 4(csp)
-; RV32IXCHERI-NEXT:    cincoffset ca1, csp, 4
-; RV32IXCHERI-NEXT:    csetbounds ca1, ca1, 4
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csw a1, 4(sp)
+; RV32IXCHERI-NEXT:    cincoffset a1, sp, 4
+; RV32IXCHERI-NEXT:    csetbounds a1, a1, 4
 ; RV32IXCHERI-NEXT:    li a3, 4
 ; RV32IXCHERI-NEXT:    li a4, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_4
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: cmpxchg_i32_acq_rel_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB25_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.w.aq a3, (ca0)
+; RV32IAXCHERI-NEXT:    clr.w.aq a3, (a0)
 ; RV32IAXCHERI-NEXT:    bne a3, a1, .LBB25_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB25_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.w.rl a4, a2, (ca0)
+; RV32IAXCHERI-NEXT:    csc.w.rl a4, a2, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a4, .LBB25_1
 ; RV32IAXCHERI-NEXT:  .LBB25_3:
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: cmpxchg_i32_acq_rel_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -32
-; RV64IXCHERI-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csw a1, 12(csp)
-; RV64IXCHERI-NEXT:    cincoffset ca1, csp, 12
-; RV64IXCHERI-NEXT:    csetbounds ca1, ca1, 4
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -32
+; RV64IXCHERI-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csw a1, 12(sp)
+; RV64IXCHERI-NEXT:    cincoffset a1, sp, 12
+; RV64IXCHERI-NEXT:    csetbounds a1, a1, 4
 ; RV64IXCHERI-NEXT:    li a3, 4
 ; RV64IXCHERI-NEXT:    li a4, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_4
-; RV64IXCHERI-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 32
+; RV64IXCHERI-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 32
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: cmpxchg_i32_acq_rel_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:    sext.w a1, a1
 ; RV64IAXCHERI-NEXT:  .LBB25_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.w.aq a3, (ca0)
+; RV64IAXCHERI-NEXT:    clr.w.aq a3, (a0)
 ; RV64IAXCHERI-NEXT:    bne a3, a1, .LBB25_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB25_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.w.rl a4, a2, (ca0)
+; RV64IAXCHERI-NEXT:    csc.w.rl a4, a2, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a4, .LBB25_1
 ; RV64IAXCHERI-NEXT:  .LBB25_3:
 ; RV64IAXCHERI-NEXT:    cret
@@ -1501,51 +1501,51 @@ define void @cmpxchg_i32_acq_rel_monotonic(ptr addrspace(200) %ptr, i32 %cmp, i3
 define void @cmpxchg_i32_acq_rel_acquire(ptr addrspace(200) %ptr, i32 %cmp, i32 %val) addrspace(200) nounwind {
 ; RV32IXCHERI-LABEL: cmpxchg_i32_acq_rel_acquire:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csw a1, 4(csp)
-; RV32IXCHERI-NEXT:    cincoffset ca1, csp, 4
-; RV32IXCHERI-NEXT:    csetbounds ca1, ca1, 4
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csw a1, 4(sp)
+; RV32IXCHERI-NEXT:    cincoffset a1, sp, 4
+; RV32IXCHERI-NEXT:    csetbounds a1, a1, 4
 ; RV32IXCHERI-NEXT:    li a3, 4
 ; RV32IXCHERI-NEXT:    li a4, 2
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_4
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: cmpxchg_i32_acq_rel_acquire:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB26_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.w.aq a3, (ca0)
+; RV32IAXCHERI-NEXT:    clr.w.aq a3, (a0)
 ; RV32IAXCHERI-NEXT:    bne a3, a1, .LBB26_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB26_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.w.rl a4, a2, (ca0)
+; RV32IAXCHERI-NEXT:    csc.w.rl a4, a2, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a4, .LBB26_1
 ; RV32IAXCHERI-NEXT:  .LBB26_3:
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: cmpxchg_i32_acq_rel_acquire:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -32
-; RV64IXCHERI-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csw a1, 12(csp)
-; RV64IXCHERI-NEXT:    cincoffset ca1, csp, 12
-; RV64IXCHERI-NEXT:    csetbounds ca1, ca1, 4
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -32
+; RV64IXCHERI-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csw a1, 12(sp)
+; RV64IXCHERI-NEXT:    cincoffset a1, sp, 12
+; RV64IXCHERI-NEXT:    csetbounds a1, a1, 4
 ; RV64IXCHERI-NEXT:    li a3, 4
 ; RV64IXCHERI-NEXT:    li a4, 2
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_4
-; RV64IXCHERI-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 32
+; RV64IXCHERI-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 32
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: cmpxchg_i32_acq_rel_acquire:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:    sext.w a1, a1
 ; RV64IAXCHERI-NEXT:  .LBB26_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.w.aq a3, (ca0)
+; RV64IAXCHERI-NEXT:    clr.w.aq a3, (a0)
 ; RV64IAXCHERI-NEXT:    bne a3, a1, .LBB26_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB26_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.w.rl a4, a2, (ca0)
+; RV64IAXCHERI-NEXT:    csc.w.rl a4, a2, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a4, .LBB26_1
 ; RV64IAXCHERI-NEXT:  .LBB26_3:
 ; RV64IAXCHERI-NEXT:    cret
@@ -1556,51 +1556,51 @@ define void @cmpxchg_i32_acq_rel_acquire(ptr addrspace(200) %ptr, i32 %cmp, i32
 define void @cmpxchg_i32_seq_cst_monotonic(ptr addrspace(200) %ptr, i32 %cmp, i32 %val) addrspace(200) nounwind {
 ; RV32IXCHERI-LABEL: cmpxchg_i32_seq_cst_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csw a1, 4(csp)
-; RV32IXCHERI-NEXT:    cincoffset ca1, csp, 4
-; RV32IXCHERI-NEXT:    csetbounds ca1, ca1, 4
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csw a1, 4(sp)
+; RV32IXCHERI-NEXT:    cincoffset a1, sp, 4
+; RV32IXCHERI-NEXT:    csetbounds a1, a1, 4
 ; RV32IXCHERI-NEXT:    li a3, 5
 ; RV32IXCHERI-NEXT:    li a4, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_4
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: cmpxchg_i32_seq_cst_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB27_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.w.aqrl a3, (ca0)
+; RV32IAXCHERI-NEXT:    clr.w.aqrl a3, (a0)
 ; RV32IAXCHERI-NEXT:    bne a3, a1, .LBB27_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB27_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.w.rl a4, a2, (ca0)
+; RV32IAXCHERI-NEXT:    csc.w.rl a4, a2, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a4, .LBB27_1
 ; RV32IAXCHERI-NEXT:  .LBB27_3:
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: cmpxchg_i32_seq_cst_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -32
-; RV64IXCHERI-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csw a1, 12(csp)
-; RV64IXCHERI-NEXT:    cincoffset ca1, csp, 12
-; RV64IXCHERI-NEXT:    csetbounds ca1, ca1, 4
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -32
+; RV64IXCHERI-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csw a1, 12(sp)
+; RV64IXCHERI-NEXT:    cincoffset a1, sp, 12
+; RV64IXCHERI-NEXT:    csetbounds a1, a1, 4
 ; RV64IXCHERI-NEXT:    li a3, 5
 ; RV64IXCHERI-NEXT:    li a4, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_4
-; RV64IXCHERI-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 32
+; RV64IXCHERI-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 32
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: cmpxchg_i32_seq_cst_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:    sext.w a1, a1
 ; RV64IAXCHERI-NEXT:  .LBB27_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.w.aqrl a3, (ca0)
+; RV64IAXCHERI-NEXT:    clr.w.aqrl a3, (a0)
 ; RV64IAXCHERI-NEXT:    bne a3, a1, .LBB27_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB27_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.w.rl a4, a2, (ca0)
+; RV64IAXCHERI-NEXT:    csc.w.rl a4, a2, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a4, .LBB27_1
 ; RV64IAXCHERI-NEXT:  .LBB27_3:
 ; RV64IAXCHERI-NEXT:    cret
@@ -1611,51 +1611,51 @@ define void @cmpxchg_i32_seq_cst_monotonic(ptr addrspace(200) %ptr, i32 %cmp, i3
 define void @cmpxchg_i32_seq_cst_acquire(ptr addrspace(200) %ptr, i32 %cmp, i32 %val) addrspace(200) nounwind {
 ; RV32IXCHERI-LABEL: cmpxchg_i32_seq_cst_acquire:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csw a1, 4(csp)
-; RV32IXCHERI-NEXT:    cincoffset ca1, csp, 4
-; RV32IXCHERI-NEXT:    csetbounds ca1, ca1, 4
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csw a1, 4(sp)
+; RV32IXCHERI-NEXT:    cincoffset a1, sp, 4
+; RV32IXCHERI-NEXT:    csetbounds a1, a1, 4
 ; RV32IXCHERI-NEXT:    li a3, 5
 ; RV32IXCHERI-NEXT:    li a4, 2
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_4
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: cmpxchg_i32_seq_cst_acquire:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB28_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.w.aqrl a3, (ca0)
+; RV32IAXCHERI-NEXT:    clr.w.aqrl a3, (a0)
 ; RV32IAXCHERI-NEXT:    bne a3, a1, .LBB28_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB28_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.w.rl a4, a2, (ca0)
+; RV32IAXCHERI-NEXT:    csc.w.rl a4, a2, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a4, .LBB28_1
 ; RV32IAXCHERI-NEXT:  .LBB28_3:
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: cmpxchg_i32_seq_cst_acquire:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -32
-; RV64IXCHERI-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csw a1, 12(csp)
-; RV64IXCHERI-NEXT:    cincoffset ca1, csp, 12
-; RV64IXCHERI-NEXT:    csetbounds ca1, ca1, 4
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -32
+; RV64IXCHERI-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csw a1, 12(sp)
+; RV64IXCHERI-NEXT:    cincoffset a1, sp, 12
+; RV64IXCHERI-NEXT:    csetbounds a1, a1, 4
 ; RV64IXCHERI-NEXT:    li a3, 5
 ; RV64IXCHERI-NEXT:    li a4, 2
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_4
-; RV64IXCHERI-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 32
+; RV64IXCHERI-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 32
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: cmpxchg_i32_seq_cst_acquire:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:    sext.w a1, a1
 ; RV64IAXCHERI-NEXT:  .LBB28_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.w.aqrl a3, (ca0)
+; RV64IAXCHERI-NEXT:    clr.w.aqrl a3, (a0)
 ; RV64IAXCHERI-NEXT:    bne a3, a1, .LBB28_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB28_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.w.rl a4, a2, (ca0)
+; RV64IAXCHERI-NEXT:    csc.w.rl a4, a2, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a4, .LBB28_1
 ; RV64IAXCHERI-NEXT:  .LBB28_3:
 ; RV64IAXCHERI-NEXT:    cret
@@ -1666,51 +1666,51 @@ define void @cmpxchg_i32_seq_cst_acquire(ptr addrspace(200) %ptr, i32 %cmp, i32
 define void @cmpxchg_i32_seq_cst_seq_cst(ptr addrspace(200) %ptr, i32 %cmp, i32 %val) addrspace(200) nounwind {
 ; RV32IXCHERI-LABEL: cmpxchg_i32_seq_cst_seq_cst:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csw a1, 4(csp)
-; RV32IXCHERI-NEXT:    cincoffset ca1, csp, 4
-; RV32IXCHERI-NEXT:    csetbounds ca1, ca1, 4
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csw a1, 4(sp)
+; RV32IXCHERI-NEXT:    cincoffset a1, sp, 4
+; RV32IXCHERI-NEXT:    csetbounds a1, a1, 4
 ; RV32IXCHERI-NEXT:    li a3, 5
 ; RV32IXCHERI-NEXT:    li a4, 5
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_4
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: cmpxchg_i32_seq_cst_seq_cst:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB29_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.w.aqrl a3, (ca0)
+; RV32IAXCHERI-NEXT:    clr.w.aqrl a3, (a0)
 ; RV32IAXCHERI-NEXT:    bne a3, a1, .LBB29_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB29_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.w.rl a4, a2, (ca0)
+; RV32IAXCHERI-NEXT:    csc.w.rl a4, a2, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a4, .LBB29_1
 ; RV32IAXCHERI-NEXT:  .LBB29_3:
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: cmpxchg_i32_seq_cst_seq_cst:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -32
-; RV64IXCHERI-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csw a1, 12(csp)
-; RV64IXCHERI-NEXT:    cincoffset ca1, csp, 12
-; RV64IXCHERI-NEXT:    csetbounds ca1, ca1, 4
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -32
+; RV64IXCHERI-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csw a1, 12(sp)
+; RV64IXCHERI-NEXT:    cincoffset a1, sp, 12
+; RV64IXCHERI-NEXT:    csetbounds a1, a1, 4
 ; RV64IXCHERI-NEXT:    li a3, 5
 ; RV64IXCHERI-NEXT:    li a4, 5
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_4
-; RV64IXCHERI-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 32
+; RV64IXCHERI-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 32
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: cmpxchg_i32_seq_cst_seq_cst:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:    sext.w a1, a1
 ; RV64IAXCHERI-NEXT:  .LBB29_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.w.aqrl a3, (ca0)
+; RV64IAXCHERI-NEXT:    clr.w.aqrl a3, (a0)
 ; RV64IAXCHERI-NEXT:    bne a3, a1, .LBB29_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB29_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.w.rl a4, a2, (ca0)
+; RV64IAXCHERI-NEXT:    csc.w.rl a4, a2, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a4, .LBB29_1
 ; RV64IAXCHERI-NEXT:  .LBB29_3:
 ; RV64IAXCHERI-NEXT:    cret
@@ -1721,59 +1721,59 @@ define void @cmpxchg_i32_seq_cst_seq_cst(ptr addrspace(200) %ptr, i32 %cmp, i32
 define void @cmpxchg_i64_monotonic_monotonic(ptr addrspace(200) %ptr, i64 %cmp, i64 %val) addrspace(200) nounwind {
 ; RV32IXCHERI-LABEL: cmpxchg_i64_monotonic_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csw a2, 4(csp)
-; RV32IXCHERI-NEXT:    csw a1, 0(csp)
-; RV32IXCHERI-NEXT:    cincoffset ca1, csp, 0
-; RV32IXCHERI-NEXT:    csetbounds ca1, ca1, 8
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csw a2, 4(sp)
+; RV32IXCHERI-NEXT:    csw a1, 0(sp)
+; RV32IXCHERI-NEXT:    cincoffset a1, sp, 0
+; RV32IXCHERI-NEXT:    csetbounds a1, a1, 8
 ; RV32IXCHERI-NEXT:    mv a2, a3
 ; RV32IXCHERI-NEXT:    mv a3, a4
 ; RV32IXCHERI-NEXT:    li a4, 0
 ; RV32IXCHERI-NEXT:    li a5, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: cmpxchg_i64_monotonic_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IAXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csw a2, 4(csp)
-; RV32IAXCHERI-NEXT:    csw a1, 0(csp)
-; RV32IAXCHERI-NEXT:    cincoffset ca1, csp, 0
-; RV32IAXCHERI-NEXT:    csetbounds ca1, ca1, 8
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IAXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csw a2, 4(sp)
+; RV32IAXCHERI-NEXT:    csw a1, 0(sp)
+; RV32IAXCHERI-NEXT:    cincoffset a1, sp, 0
+; RV32IAXCHERI-NEXT:    csetbounds a1, a1, 8
 ; RV32IAXCHERI-NEXT:    mv a2, a3
 ; RV32IAXCHERI-NEXT:    mv a3, a4
 ; RV32IAXCHERI-NEXT:    li a4, 0
 ; RV32IAXCHERI-NEXT:    li a5, 0
 ; RV32IAXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV32IAXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IAXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: cmpxchg_i64_monotonic_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -32
-; RV64IXCHERI-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csd a1, 8(csp)
-; RV64IXCHERI-NEXT:    cincoffset ca1, csp, 8
-; RV64IXCHERI-NEXT:    csetbounds ca1, ca1, 8
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -32
+; RV64IXCHERI-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csd a1, 8(sp)
+; RV64IXCHERI-NEXT:    cincoffset a1, sp, 8
+; RV64IXCHERI-NEXT:    csetbounds a1, a1, 8
 ; RV64IXCHERI-NEXT:    li a3, 0
 ; RV64IXCHERI-NEXT:    li a4, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV64IXCHERI-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 32
+; RV64IXCHERI-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 32
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: cmpxchg_i64_monotonic_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB30_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.d a3, (ca0)
+; RV64IAXCHERI-NEXT:    clr.d a3, (a0)
 ; RV64IAXCHERI-NEXT:    bne a3, a1, .LBB30_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB30_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.d a4, a2, (ca0)
+; RV64IAXCHERI-NEXT:    csc.d a4, a2, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a4, .LBB30_1
 ; RV64IAXCHERI-NEXT:  .LBB30_3:
 ; RV64IAXCHERI-NEXT:    cret
@@ -1784,61 +1784,61 @@ define void @cmpxchg_i64_monotonic_monotonic(ptr addrspace(200) %ptr, i64 %cmp,
 define void @cmpxchg_i64_acquire_monotonic(ptr addrspace(200) %ptr, i64 %cmp, i64 %val) addrspace(200) nounwind {
 ; RV32IXCHERI-LABEL: cmpxchg_i64_acquire_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    mv a5, a4
-; RV32IXCHERI-NEXT:    csw a2, 4(csp)
-; RV32IXCHERI-NEXT:    csw a1, 0(csp)
-; RV32IXCHERI-NEXT:    cincoffset ca1, csp, 0
-; RV32IXCHERI-NEXT:    csetbounds ca1, ca1, 8
+; RV32IXCHERI-NEXT:    csw a2, 4(sp)
+; RV32IXCHERI-NEXT:    csw a1, 0(sp)
+; RV32IXCHERI-NEXT:    cincoffset a1, sp, 0
+; RV32IXCHERI-NEXT:    csetbounds a1, a1, 8
 ; RV32IXCHERI-NEXT:    li a4, 2
 ; RV32IXCHERI-NEXT:    mv a2, a3
 ; RV32IXCHERI-NEXT:    mv a3, a5
 ; RV32IXCHERI-NEXT:    li a5, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: cmpxchg_i64_acquire_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IAXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IAXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    mv a5, a4
-; RV32IAXCHERI-NEXT:    csw a2, 4(csp)
-; RV32IAXCHERI-NEXT:    csw a1, 0(csp)
-; RV32IAXCHERI-NEXT:    cincoffset ca1, csp, 0
-; RV32IAXCHERI-NEXT:    csetbounds ca1, ca1, 8
+; RV32IAXCHERI-NEXT:    csw a2, 4(sp)
+; RV32IAXCHERI-NEXT:    csw a1, 0(sp)
+; RV32IAXCHERI-NEXT:    cincoffset a1, sp, 0
+; RV32IAXCHERI-NEXT:    csetbounds a1, a1, 8
 ; RV32IAXCHERI-NEXT:    li a4, 2
 ; RV32IAXCHERI-NEXT:    mv a2, a3
 ; RV32IAXCHERI-NEXT:    mv a3, a5
 ; RV32IAXCHERI-NEXT:    li a5, 0
 ; RV32IAXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV32IAXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IAXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: cmpxchg_i64_acquire_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -32
-; RV64IXCHERI-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csd a1, 8(csp)
-; RV64IXCHERI-NEXT:    cincoffset ca1, csp, 8
-; RV64IXCHERI-NEXT:    csetbounds ca1, ca1, 8
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -32
+; RV64IXCHERI-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csd a1, 8(sp)
+; RV64IXCHERI-NEXT:    cincoffset a1, sp, 8
+; RV64IXCHERI-NEXT:    csetbounds a1, a1, 8
 ; RV64IXCHERI-NEXT:    li a3, 2
 ; RV64IXCHERI-NEXT:    li a4, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV64IXCHERI-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 32
+; RV64IXCHERI-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 32
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: cmpxchg_i64_acquire_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB31_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.d.aq a3, (ca0)
+; RV64IAXCHERI-NEXT:    clr.d.aq a3, (a0)
 ; RV64IAXCHERI-NEXT:    bne a3, a1, .LBB31_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB31_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.d a4, a2, (ca0)
+; RV64IAXCHERI-NEXT:    csc.d a4, a2, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a4, .LBB31_1
 ; RV64IAXCHERI-NEXT:  .LBB31_3:
 ; RV64IAXCHERI-NEXT:    cret
@@ -1849,61 +1849,61 @@ define void @cmpxchg_i64_acquire_monotonic(ptr addrspace(200) %ptr, i64 %cmp, i6
 define void @cmpxchg_i64_acquire_acquire(ptr addrspace(200) %ptr, i64 %cmp, i64 %val) addrspace(200) nounwind {
 ; RV32IXCHERI-LABEL: cmpxchg_i64_acquire_acquire:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    mv a6, a4
-; RV32IXCHERI-NEXT:    csw a2, 4(csp)
-; RV32IXCHERI-NEXT:    csw a1, 0(csp)
-; RV32IXCHERI-NEXT:    cincoffset ca1, csp, 0
-; RV32IXCHERI-NEXT:    csetbounds ca1, ca1, 8
+; RV32IXCHERI-NEXT:    csw a2, 4(sp)
+; RV32IXCHERI-NEXT:    csw a1, 0(sp)
+; RV32IXCHERI-NEXT:    cincoffset a1, sp, 0
+; RV32IXCHERI-NEXT:    csetbounds a1, a1, 8
 ; RV32IXCHERI-NEXT:    li a4, 2
 ; RV32IXCHERI-NEXT:    li a5, 2
 ; RV32IXCHERI-NEXT:    mv a2, a3
 ; RV32IXCHERI-NEXT:    mv a3, a6
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: cmpxchg_i64_acquire_acquire:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IAXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IAXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    mv a6, a4
-; RV32IAXCHERI-NEXT:    csw a2, 4(csp)
-; RV32IAXCHERI-NEXT:    csw a1, 0(csp)
-; RV32IAXCHERI-NEXT:    cincoffset ca1, csp, 0
-; RV32IAXCHERI-NEXT:    csetbounds ca1, ca1, 8
+; RV32IAXCHERI-NEXT:    csw a2, 4(sp)
+; RV32IAXCHERI-NEXT:    csw a1, 0(sp)
+; RV32IAXCHERI-NEXT:    cincoffset a1, sp, 0
+; RV32IAXCHERI-NEXT:    csetbounds a1, a1, 8
 ; RV32IAXCHERI-NEXT:    li a4, 2
 ; RV32IAXCHERI-NEXT:    li a5, 2
 ; RV32IAXCHERI-NEXT:    mv a2, a3
 ; RV32IAXCHERI-NEXT:    mv a3, a6
 ; RV32IAXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV32IAXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IAXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: cmpxchg_i64_acquire_acquire:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -32
-; RV64IXCHERI-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csd a1, 8(csp)
-; RV64IXCHERI-NEXT:    cincoffset ca1, csp, 8
-; RV64IXCHERI-NEXT:    csetbounds ca1, ca1, 8
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -32
+; RV64IXCHERI-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csd a1, 8(sp)
+; RV64IXCHERI-NEXT:    cincoffset a1, sp, 8
+; RV64IXCHERI-NEXT:    csetbounds a1, a1, 8
 ; RV64IXCHERI-NEXT:    li a3, 2
 ; RV64IXCHERI-NEXT:    li a4, 2
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV64IXCHERI-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 32
+; RV64IXCHERI-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 32
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: cmpxchg_i64_acquire_acquire:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB32_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.d.aq a3, (ca0)
+; RV64IAXCHERI-NEXT:    clr.d.aq a3, (a0)
 ; RV64IAXCHERI-NEXT:    bne a3, a1, .LBB32_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB32_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.d a4, a2, (ca0)
+; RV64IAXCHERI-NEXT:    csc.d a4, a2, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a4, .LBB32_1
 ; RV64IAXCHERI-NEXT:  .LBB32_3:
 ; RV64IAXCHERI-NEXT:    cret
@@ -1914,61 +1914,61 @@ define void @cmpxchg_i64_acquire_acquire(ptr addrspace(200) %ptr, i64 %cmp, i64
 define void @cmpxchg_i64_release_monotonic(ptr addrspace(200) %ptr, i64 %cmp, i64 %val) addrspace(200) nounwind {
 ; RV32IXCHERI-LABEL: cmpxchg_i64_release_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    mv a5, a4
-; RV32IXCHERI-NEXT:    csw a2, 4(csp)
-; RV32IXCHERI-NEXT:    csw a1, 0(csp)
-; RV32IXCHERI-NEXT:    cincoffset ca1, csp, 0
-; RV32IXCHERI-NEXT:    csetbounds ca1, ca1, 8
+; RV32IXCHERI-NEXT:    csw a2, 4(sp)
+; RV32IXCHERI-NEXT:    csw a1, 0(sp)
+; RV32IXCHERI-NEXT:    cincoffset a1, sp, 0
+; RV32IXCHERI-NEXT:    csetbounds a1, a1, 8
 ; RV32IXCHERI-NEXT:    li a4, 3
 ; RV32IXCHERI-NEXT:    mv a2, a3
 ; RV32IXCHERI-NEXT:    mv a3, a5
 ; RV32IXCHERI-NEXT:    li a5, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: cmpxchg_i64_release_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IAXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IAXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    mv a5, a4
-; RV32IAXCHERI-NEXT:    csw a2, 4(csp)
-; RV32IAXCHERI-NEXT:    csw a1, 0(csp)
-; RV32IAXCHERI-NEXT:    cincoffset ca1, csp, 0
-; RV32IAXCHERI-NEXT:    csetbounds ca1, ca1, 8
+; RV32IAXCHERI-NEXT:    csw a2, 4(sp)
+; RV32IAXCHERI-NEXT:    csw a1, 0(sp)
+; RV32IAXCHERI-NEXT:    cincoffset a1, sp, 0
+; RV32IAXCHERI-NEXT:    csetbounds a1, a1, 8
 ; RV32IAXCHERI-NEXT:    li a4, 3
 ; RV32IAXCHERI-NEXT:    mv a2, a3
 ; RV32IAXCHERI-NEXT:    mv a3, a5
 ; RV32IAXCHERI-NEXT:    li a5, 0
 ; RV32IAXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV32IAXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IAXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: cmpxchg_i64_release_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -32
-; RV64IXCHERI-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csd a1, 8(csp)
-; RV64IXCHERI-NEXT:    cincoffset ca1, csp, 8
-; RV64IXCHERI-NEXT:    csetbounds ca1, ca1, 8
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -32
+; RV64IXCHERI-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csd a1, 8(sp)
+; RV64IXCHERI-NEXT:    cincoffset a1, sp, 8
+; RV64IXCHERI-NEXT:    csetbounds a1, a1, 8
 ; RV64IXCHERI-NEXT:    li a3, 3
 ; RV64IXCHERI-NEXT:    li a4, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV64IXCHERI-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 32
+; RV64IXCHERI-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 32
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: cmpxchg_i64_release_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB33_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.d a3, (ca0)
+; RV64IAXCHERI-NEXT:    clr.d a3, (a0)
 ; RV64IAXCHERI-NEXT:    bne a3, a1, .LBB33_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB33_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.d.rl a4, a2, (ca0)
+; RV64IAXCHERI-NEXT:    csc.d.rl a4, a2, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a4, .LBB33_1
 ; RV64IAXCHERI-NEXT:  .LBB33_3:
 ; RV64IAXCHERI-NEXT:    cret
@@ -1979,61 +1979,61 @@ define void @cmpxchg_i64_release_monotonic(ptr addrspace(200) %ptr, i64 %cmp, i6
 define void @cmpxchg_i64_release_acquire(ptr addrspace(200) %ptr, i64 %cmp, i64 %val) addrspace(200) nounwind {
 ; RV32IXCHERI-LABEL: cmpxchg_i64_release_acquire:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    mv a6, a4
-; RV32IXCHERI-NEXT:    csw a2, 4(csp)
-; RV32IXCHERI-NEXT:    csw a1, 0(csp)
-; RV32IXCHERI-NEXT:    cincoffset ca1, csp, 0
-; RV32IXCHERI-NEXT:    csetbounds ca1, ca1, 8
+; RV32IXCHERI-NEXT:    csw a2, 4(sp)
+; RV32IXCHERI-NEXT:    csw a1, 0(sp)
+; RV32IXCHERI-NEXT:    cincoffset a1, sp, 0
+; RV32IXCHERI-NEXT:    csetbounds a1, a1, 8
 ; RV32IXCHERI-NEXT:    li a4, 3
 ; RV32IXCHERI-NEXT:    li a5, 2
 ; RV32IXCHERI-NEXT:    mv a2, a3
 ; RV32IXCHERI-NEXT:    mv a3, a6
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: cmpxchg_i64_release_acquire:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IAXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IAXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    mv a6, a4
-; RV32IAXCHERI-NEXT:    csw a2, 4(csp)
-; RV32IAXCHERI-NEXT:    csw a1, 0(csp)
-; RV32IAXCHERI-NEXT:    cincoffset ca1, csp, 0
-; RV32IAXCHERI-NEXT:    csetbounds ca1, ca1, 8
+; RV32IAXCHERI-NEXT:    csw a2, 4(sp)
+; RV32IAXCHERI-NEXT:    csw a1, 0(sp)
+; RV32IAXCHERI-NEXT:    cincoffset a1, sp, 0
+; RV32IAXCHERI-NEXT:    csetbounds a1, a1, 8
 ; RV32IAXCHERI-NEXT:    li a4, 3
 ; RV32IAXCHERI-NEXT:    li a5, 2
 ; RV32IAXCHERI-NEXT:    mv a2, a3
 ; RV32IAXCHERI-NEXT:    mv a3, a6
 ; RV32IAXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV32IAXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IAXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: cmpxchg_i64_release_acquire:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -32
-; RV64IXCHERI-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csd a1, 8(csp)
-; RV64IXCHERI-NEXT:    cincoffset ca1, csp, 8
-; RV64IXCHERI-NEXT:    csetbounds ca1, ca1, 8
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -32
+; RV64IXCHERI-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csd a1, 8(sp)
+; RV64IXCHERI-NEXT:    cincoffset a1, sp, 8
+; RV64IXCHERI-NEXT:    csetbounds a1, a1, 8
 ; RV64IXCHERI-NEXT:    li a3, 3
 ; RV64IXCHERI-NEXT:    li a4, 2
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV64IXCHERI-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 32
+; RV64IXCHERI-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 32
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: cmpxchg_i64_release_acquire:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB34_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.d.aq a3, (ca0)
+; RV64IAXCHERI-NEXT:    clr.d.aq a3, (a0)
 ; RV64IAXCHERI-NEXT:    bne a3, a1, .LBB34_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB34_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.d.rl a4, a2, (ca0)
+; RV64IAXCHERI-NEXT:    csc.d.rl a4, a2, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a4, .LBB34_1
 ; RV64IAXCHERI-NEXT:  .LBB34_3:
 ; RV64IAXCHERI-NEXT:    cret
@@ -2044,61 +2044,61 @@ define void @cmpxchg_i64_release_acquire(ptr addrspace(200) %ptr, i64 %cmp, i64
 define void @cmpxchg_i64_acq_rel_monotonic(ptr addrspace(200) %ptr, i64 %cmp, i64 %val) addrspace(200) nounwind {
 ; RV32IXCHERI-LABEL: cmpxchg_i64_acq_rel_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    mv a5, a4
-; RV32IXCHERI-NEXT:    csw a2, 4(csp)
-; RV32IXCHERI-NEXT:    csw a1, 0(csp)
-; RV32IXCHERI-NEXT:    cincoffset ca1, csp, 0
-; RV32IXCHERI-NEXT:    csetbounds ca1, ca1, 8
+; RV32IXCHERI-NEXT:    csw a2, 4(sp)
+; RV32IXCHERI-NEXT:    csw a1, 0(sp)
+; RV32IXCHERI-NEXT:    cincoffset a1, sp, 0
+; RV32IXCHERI-NEXT:    csetbounds a1, a1, 8
 ; RV32IXCHERI-NEXT:    li a4, 4
 ; RV32IXCHERI-NEXT:    mv a2, a3
 ; RV32IXCHERI-NEXT:    mv a3, a5
 ; RV32IXCHERI-NEXT:    li a5, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: cmpxchg_i64_acq_rel_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IAXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IAXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    mv a5, a4
-; RV32IAXCHERI-NEXT:    csw a2, 4(csp)
-; RV32IAXCHERI-NEXT:    csw a1, 0(csp)
-; RV32IAXCHERI-NEXT:    cincoffset ca1, csp, 0
-; RV32IAXCHERI-NEXT:    csetbounds ca1, ca1, 8
+; RV32IAXCHERI-NEXT:    csw a2, 4(sp)
+; RV32IAXCHERI-NEXT:    csw a1, 0(sp)
+; RV32IAXCHERI-NEXT:    cincoffset a1, sp, 0
+; RV32IAXCHERI-NEXT:    csetbounds a1, a1, 8
 ; RV32IAXCHERI-NEXT:    li a4, 4
 ; RV32IAXCHERI-NEXT:    mv a2, a3
 ; RV32IAXCHERI-NEXT:    mv a3, a5
 ; RV32IAXCHERI-NEXT:    li a5, 0
 ; RV32IAXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV32IAXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IAXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: cmpxchg_i64_acq_rel_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -32
-; RV64IXCHERI-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csd a1, 8(csp)
-; RV64IXCHERI-NEXT:    cincoffset ca1, csp, 8
-; RV64IXCHERI-NEXT:    csetbounds ca1, ca1, 8
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -32
+; RV64IXCHERI-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csd a1, 8(sp)
+; RV64IXCHERI-NEXT:    cincoffset a1, sp, 8
+; RV64IXCHERI-NEXT:    csetbounds a1, a1, 8
 ; RV64IXCHERI-NEXT:    li a3, 4
 ; RV64IXCHERI-NEXT:    li a4, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV64IXCHERI-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 32
+; RV64IXCHERI-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 32
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: cmpxchg_i64_acq_rel_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB35_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.d.aq a3, (ca0)
+; RV64IAXCHERI-NEXT:    clr.d.aq a3, (a0)
 ; RV64IAXCHERI-NEXT:    bne a3, a1, .LBB35_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB35_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.d.rl a4, a2, (ca0)
+; RV64IAXCHERI-NEXT:    csc.d.rl a4, a2, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a4, .LBB35_1
 ; RV64IAXCHERI-NEXT:  .LBB35_3:
 ; RV64IAXCHERI-NEXT:    cret
@@ -2109,61 +2109,61 @@ define void @cmpxchg_i64_acq_rel_monotonic(ptr addrspace(200) %ptr, i64 %cmp, i6
 define void @cmpxchg_i64_acq_rel_acquire(ptr addrspace(200) %ptr, i64 %cmp, i64 %val) addrspace(200) nounwind {
 ; RV32IXCHERI-LABEL: cmpxchg_i64_acq_rel_acquire:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    mv a6, a4
-; RV32IXCHERI-NEXT:    csw a2, 4(csp)
-; RV32IXCHERI-NEXT:    csw a1, 0(csp)
-; RV32IXCHERI-NEXT:    cincoffset ca1, csp, 0
-; RV32IXCHERI-NEXT:    csetbounds ca1, ca1, 8
+; RV32IXCHERI-NEXT:    csw a2, 4(sp)
+; RV32IXCHERI-NEXT:    csw a1, 0(sp)
+; RV32IXCHERI-NEXT:    cincoffset a1, sp, 0
+; RV32IXCHERI-NEXT:    csetbounds a1, a1, 8
 ; RV32IXCHERI-NEXT:    li a4, 4
 ; RV32IXCHERI-NEXT:    li a5, 2
 ; RV32IXCHERI-NEXT:    mv a2, a3
 ; RV32IXCHERI-NEXT:    mv a3, a6
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: cmpxchg_i64_acq_rel_acquire:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IAXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IAXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    mv a6, a4
-; RV32IAXCHERI-NEXT:    csw a2, 4(csp)
-; RV32IAXCHERI-NEXT:    csw a1, 0(csp)
-; RV32IAXCHERI-NEXT:    cincoffset ca1, csp, 0
-; RV32IAXCHERI-NEXT:    csetbounds ca1, ca1, 8
+; RV32IAXCHERI-NEXT:    csw a2, 4(sp)
+; RV32IAXCHERI-NEXT:    csw a1, 0(sp)
+; RV32IAXCHERI-NEXT:    cincoffset a1, sp, 0
+; RV32IAXCHERI-NEXT:    csetbounds a1, a1, 8
 ; RV32IAXCHERI-NEXT:    li a4, 4
 ; RV32IAXCHERI-NEXT:    li a5, 2
 ; RV32IAXCHERI-NEXT:    mv a2, a3
 ; RV32IAXCHERI-NEXT:    mv a3, a6
 ; RV32IAXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV32IAXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IAXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: cmpxchg_i64_acq_rel_acquire:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -32
-; RV64IXCHERI-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csd a1, 8(csp)
-; RV64IXCHERI-NEXT:    cincoffset ca1, csp, 8
-; RV64IXCHERI-NEXT:    csetbounds ca1, ca1, 8
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -32
+; RV64IXCHERI-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csd a1, 8(sp)
+; RV64IXCHERI-NEXT:    cincoffset a1, sp, 8
+; RV64IXCHERI-NEXT:    csetbounds a1, a1, 8
 ; RV64IXCHERI-NEXT:    li a3, 4
 ; RV64IXCHERI-NEXT:    li a4, 2
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV64IXCHERI-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 32
+; RV64IXCHERI-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 32
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: cmpxchg_i64_acq_rel_acquire:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB36_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.d.aq a3, (ca0)
+; RV64IAXCHERI-NEXT:    clr.d.aq a3, (a0)
 ; RV64IAXCHERI-NEXT:    bne a3, a1, .LBB36_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB36_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.d.rl a4, a2, (ca0)
+; RV64IAXCHERI-NEXT:    csc.d.rl a4, a2, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a4, .LBB36_1
 ; RV64IAXCHERI-NEXT:  .LBB36_3:
 ; RV64IAXCHERI-NEXT:    cret
@@ -2174,61 +2174,61 @@ define void @cmpxchg_i64_acq_rel_acquire(ptr addrspace(200) %ptr, i64 %cmp, i64
 define void @cmpxchg_i64_seq_cst_monotonic(ptr addrspace(200) %ptr, i64 %cmp, i64 %val) addrspace(200) nounwind {
 ; RV32IXCHERI-LABEL: cmpxchg_i64_seq_cst_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    mv a5, a4
-; RV32IXCHERI-NEXT:    csw a2, 4(csp)
-; RV32IXCHERI-NEXT:    csw a1, 0(csp)
-; RV32IXCHERI-NEXT:    cincoffset ca1, csp, 0
-; RV32IXCHERI-NEXT:    csetbounds ca1, ca1, 8
+; RV32IXCHERI-NEXT:    csw a2, 4(sp)
+; RV32IXCHERI-NEXT:    csw a1, 0(sp)
+; RV32IXCHERI-NEXT:    cincoffset a1, sp, 0
+; RV32IXCHERI-NEXT:    csetbounds a1, a1, 8
 ; RV32IXCHERI-NEXT:    li a4, 5
 ; RV32IXCHERI-NEXT:    mv a2, a3
 ; RV32IXCHERI-NEXT:    mv a3, a5
 ; RV32IXCHERI-NEXT:    li a5, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: cmpxchg_i64_seq_cst_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IAXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IAXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    mv a5, a4
-; RV32IAXCHERI-NEXT:    csw a2, 4(csp)
-; RV32IAXCHERI-NEXT:    csw a1, 0(csp)
-; RV32IAXCHERI-NEXT:    cincoffset ca1, csp, 0
-; RV32IAXCHERI-NEXT:    csetbounds ca1, ca1, 8
+; RV32IAXCHERI-NEXT:    csw a2, 4(sp)
+; RV32IAXCHERI-NEXT:    csw a1, 0(sp)
+; RV32IAXCHERI-NEXT:    cincoffset a1, sp, 0
+; RV32IAXCHERI-NEXT:    csetbounds a1, a1, 8
 ; RV32IAXCHERI-NEXT:    li a4, 5
 ; RV32IAXCHERI-NEXT:    mv a2, a3
 ; RV32IAXCHERI-NEXT:    mv a3, a5
 ; RV32IAXCHERI-NEXT:    li a5, 0
 ; RV32IAXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV32IAXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IAXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: cmpxchg_i64_seq_cst_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -32
-; RV64IXCHERI-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csd a1, 8(csp)
-; RV64IXCHERI-NEXT:    cincoffset ca1, csp, 8
-; RV64IXCHERI-NEXT:    csetbounds ca1, ca1, 8
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -32
+; RV64IXCHERI-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csd a1, 8(sp)
+; RV64IXCHERI-NEXT:    cincoffset a1, sp, 8
+; RV64IXCHERI-NEXT:    csetbounds a1, a1, 8
 ; RV64IXCHERI-NEXT:    li a3, 5
 ; RV64IXCHERI-NEXT:    li a4, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV64IXCHERI-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 32
+; RV64IXCHERI-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 32
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: cmpxchg_i64_seq_cst_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB37_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.d.aqrl a3, (ca0)
+; RV64IAXCHERI-NEXT:    clr.d.aqrl a3, (a0)
 ; RV64IAXCHERI-NEXT:    bne a3, a1, .LBB37_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB37_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.d.rl a4, a2, (ca0)
+; RV64IAXCHERI-NEXT:    csc.d.rl a4, a2, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a4, .LBB37_1
 ; RV64IAXCHERI-NEXT:  .LBB37_3:
 ; RV64IAXCHERI-NEXT:    cret
@@ -2239,61 +2239,61 @@ define void @cmpxchg_i64_seq_cst_monotonic(ptr addrspace(200) %ptr, i64 %cmp, i6
 define void @cmpxchg_i64_seq_cst_acquire(ptr addrspace(200) %ptr, i64 %cmp, i64 %val) addrspace(200) nounwind {
 ; RV32IXCHERI-LABEL: cmpxchg_i64_seq_cst_acquire:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    mv a6, a4
-; RV32IXCHERI-NEXT:    csw a2, 4(csp)
-; RV32IXCHERI-NEXT:    csw a1, 0(csp)
-; RV32IXCHERI-NEXT:    cincoffset ca1, csp, 0
-; RV32IXCHERI-NEXT:    csetbounds ca1, ca1, 8
+; RV32IXCHERI-NEXT:    csw a2, 4(sp)
+; RV32IXCHERI-NEXT:    csw a1, 0(sp)
+; RV32IXCHERI-NEXT:    cincoffset a1, sp, 0
+; RV32IXCHERI-NEXT:    csetbounds a1, a1, 8
 ; RV32IXCHERI-NEXT:    li a4, 5
 ; RV32IXCHERI-NEXT:    li a5, 2
 ; RV32IXCHERI-NEXT:    mv a2, a3
 ; RV32IXCHERI-NEXT:    mv a3, a6
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: cmpxchg_i64_seq_cst_acquire:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IAXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IAXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    mv a6, a4
-; RV32IAXCHERI-NEXT:    csw a2, 4(csp)
-; RV32IAXCHERI-NEXT:    csw a1, 0(csp)
-; RV32IAXCHERI-NEXT:    cincoffset ca1, csp, 0
-; RV32IAXCHERI-NEXT:    csetbounds ca1, ca1, 8
+; RV32IAXCHERI-NEXT:    csw a2, 4(sp)
+; RV32IAXCHERI-NEXT:    csw a1, 0(sp)
+; RV32IAXCHERI-NEXT:    cincoffset a1, sp, 0
+; RV32IAXCHERI-NEXT:    csetbounds a1, a1, 8
 ; RV32IAXCHERI-NEXT:    li a4, 5
 ; RV32IAXCHERI-NEXT:    li a5, 2
 ; RV32IAXCHERI-NEXT:    mv a2, a3
 ; RV32IAXCHERI-NEXT:    mv a3, a6
 ; RV32IAXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV32IAXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IAXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: cmpxchg_i64_seq_cst_acquire:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -32
-; RV64IXCHERI-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csd a1, 8(csp)
-; RV64IXCHERI-NEXT:    cincoffset ca1, csp, 8
-; RV64IXCHERI-NEXT:    csetbounds ca1, ca1, 8
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -32
+; RV64IXCHERI-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csd a1, 8(sp)
+; RV64IXCHERI-NEXT:    cincoffset a1, sp, 8
+; RV64IXCHERI-NEXT:    csetbounds a1, a1, 8
 ; RV64IXCHERI-NEXT:    li a3, 5
 ; RV64IXCHERI-NEXT:    li a4, 2
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV64IXCHERI-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 32
+; RV64IXCHERI-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 32
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: cmpxchg_i64_seq_cst_acquire:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB38_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.d.aqrl a3, (ca0)
+; RV64IAXCHERI-NEXT:    clr.d.aqrl a3, (a0)
 ; RV64IAXCHERI-NEXT:    bne a3, a1, .LBB38_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB38_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.d.rl a4, a2, (ca0)
+; RV64IAXCHERI-NEXT:    csc.d.rl a4, a2, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a4, .LBB38_1
 ; RV64IAXCHERI-NEXT:  .LBB38_3:
 ; RV64IAXCHERI-NEXT:    cret
@@ -2304,61 +2304,61 @@ define void @cmpxchg_i64_seq_cst_acquire(ptr addrspace(200) %ptr, i64 %cmp, i64
 define void @cmpxchg_i64_seq_cst_seq_cst(ptr addrspace(200) %ptr, i64 %cmp, i64 %val) addrspace(200) nounwind {
 ; RV32IXCHERI-LABEL: cmpxchg_i64_seq_cst_seq_cst:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    mv a6, a4
-; RV32IXCHERI-NEXT:    csw a2, 4(csp)
-; RV32IXCHERI-NEXT:    csw a1, 0(csp)
-; RV32IXCHERI-NEXT:    cincoffset ca1, csp, 0
-; RV32IXCHERI-NEXT:    csetbounds ca1, ca1, 8
+; RV32IXCHERI-NEXT:    csw a2, 4(sp)
+; RV32IXCHERI-NEXT:    csw a1, 0(sp)
+; RV32IXCHERI-NEXT:    cincoffset a1, sp, 0
+; RV32IXCHERI-NEXT:    csetbounds a1, a1, 8
 ; RV32IXCHERI-NEXT:    li a4, 5
 ; RV32IXCHERI-NEXT:    li a5, 5
 ; RV32IXCHERI-NEXT:    mv a2, a3
 ; RV32IXCHERI-NEXT:    mv a3, a6
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: cmpxchg_i64_seq_cst_seq_cst:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IAXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IAXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    mv a6, a4
-; RV32IAXCHERI-NEXT:    csw a2, 4(csp)
-; RV32IAXCHERI-NEXT:    csw a1, 0(csp)
-; RV32IAXCHERI-NEXT:    cincoffset ca1, csp, 0
-; RV32IAXCHERI-NEXT:    csetbounds ca1, ca1, 8
+; RV32IAXCHERI-NEXT:    csw a2, 4(sp)
+; RV32IAXCHERI-NEXT:    csw a1, 0(sp)
+; RV32IAXCHERI-NEXT:    cincoffset a1, sp, 0
+; RV32IAXCHERI-NEXT:    csetbounds a1, a1, 8
 ; RV32IAXCHERI-NEXT:    li a4, 5
 ; RV32IAXCHERI-NEXT:    li a5, 5
 ; RV32IAXCHERI-NEXT:    mv a2, a3
 ; RV32IAXCHERI-NEXT:    mv a3, a6
 ; RV32IAXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV32IAXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IAXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: cmpxchg_i64_seq_cst_seq_cst:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -32
-; RV64IXCHERI-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csd a1, 8(csp)
-; RV64IXCHERI-NEXT:    cincoffset ca1, csp, 8
-; RV64IXCHERI-NEXT:    csetbounds ca1, ca1, 8
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -32
+; RV64IXCHERI-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csd a1, 8(sp)
+; RV64IXCHERI-NEXT:    cincoffset a1, sp, 8
+; RV64IXCHERI-NEXT:    csetbounds a1, a1, 8
 ; RV64IXCHERI-NEXT:    li a3, 5
 ; RV64IXCHERI-NEXT:    li a4, 5
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV64IXCHERI-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 32
+; RV64IXCHERI-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 32
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: cmpxchg_i64_seq_cst_seq_cst:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB39_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.d.aqrl a3, (ca0)
+; RV64IAXCHERI-NEXT:    clr.d.aqrl a3, (a0)
 ; RV64IAXCHERI-NEXT:    bne a3, a1, .LBB39_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB39_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.d.rl a4, a2, (ca0)
+; RV64IAXCHERI-NEXT:    csc.d.rl a4, a2, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a4, .LBB39_1
 ; RV64IAXCHERI-NEXT:  .LBB39_3:
 ; RV64IAXCHERI-NEXT:    cret
@@ -2369,50 +2369,50 @@ define void @cmpxchg_i64_seq_cst_seq_cst(ptr addrspace(200) %ptr, i64 %cmp, i64
 define void @cmpxchg_cap_monotonic_monotonic(ptr addrspace(200) %ptr, ptr addrspace(200) %cmp, ptr addrspace(200) %val) addrspace(200) nounwind {
 ; RV32IXCHERI-LABEL: cmpxchg_cap_monotonic_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc ca1, 0(csp)
-; RV32IXCHERI-NEXT:    cincoffset ca1, csp, 0
-; RV32IXCHERI-NEXT:    csetbounds ca1, ca1, 8
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc a1, 0(sp)
+; RV32IXCHERI-NEXT:    cincoffset a1, sp, 0
+; RV32IXCHERI-NEXT:    csetbounds a1, a1, 8
 ; RV32IXCHERI-NEXT:    li a3, 0
 ; RV32IXCHERI-NEXT:    li a4, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_cap
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: cmpxchg_cap_monotonic_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB40_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.c ca3, (ca0)
+; RV32IAXCHERI-NEXT:    clr.c a3, (a0)
 ; RV32IAXCHERI-NEXT:    bne a3, a1, .LBB40_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB40_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.c a4, ca2, (ca0)
+; RV32IAXCHERI-NEXT:    csc.c a4, a2, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a4, .LBB40_1
 ; RV32IAXCHERI-NEXT:  .LBB40_3:
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: cmpxchg_cap_monotonic_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -32
-; RV64IXCHERI-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc ca1, 0(csp)
-; RV64IXCHERI-NEXT:    cincoffset ca1, csp, 0
-; RV64IXCHERI-NEXT:    csetbounds ca1, ca1, 16
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -32
+; RV64IXCHERI-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc a1, 0(sp)
+; RV64IXCHERI-NEXT:    cincoffset a1, sp, 0
+; RV64IXCHERI-NEXT:    csetbounds a1, a1, 16
 ; RV64IXCHERI-NEXT:    li a3, 0
 ; RV64IXCHERI-NEXT:    li a4, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_cap
-; RV64IXCHERI-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 32
+; RV64IXCHERI-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 32
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: cmpxchg_cap_monotonic_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB40_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.c ca3, (ca0)
+; RV64IAXCHERI-NEXT:    clr.c a3, (a0)
 ; RV64IAXCHERI-NEXT:    bne a3, a1, .LBB40_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB40_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.c a4, ca2, (ca0)
+; RV64IAXCHERI-NEXT:    csc.c a4, a2, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a4, .LBB40_1
 ; RV64IAXCHERI-NEXT:  .LBB40_3:
 ; RV64IAXCHERI-NEXT:    cret
@@ -2423,50 +2423,50 @@ define void @cmpxchg_cap_monotonic_monotonic(ptr addrspace(200) %ptr, ptr addrsp
 define void @cmpxchg_cap_acquire_monotonic(ptr addrspace(200) %ptr, ptr addrspace(200) %cmp, ptr addrspace(200) %val) addrspace(200) nounwind {
 ; RV32IXCHERI-LABEL: cmpxchg_cap_acquire_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc ca1, 0(csp)
-; RV32IXCHERI-NEXT:    cincoffset ca1, csp, 0
-; RV32IXCHERI-NEXT:    csetbounds ca1, ca1, 8
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc a1, 0(sp)
+; RV32IXCHERI-NEXT:    cincoffset a1, sp, 0
+; RV32IXCHERI-NEXT:    csetbounds a1, a1, 8
 ; RV32IXCHERI-NEXT:    li a3, 2
 ; RV32IXCHERI-NEXT:    li a4, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_cap
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: cmpxchg_cap_acquire_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB41_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.c.aq ca3, (ca0)
+; RV32IAXCHERI-NEXT:    clr.c.aq a3, (a0)
 ; RV32IAXCHERI-NEXT:    bne a3, a1, .LBB41_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB41_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.c.aq a4, ca2, (ca0)
+; RV32IAXCHERI-NEXT:    csc.c.aq a4, a2, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a4, .LBB41_1
 ; RV32IAXCHERI-NEXT:  .LBB41_3:
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: cmpxchg_cap_acquire_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -32
-; RV64IXCHERI-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc ca1, 0(csp)
-; RV64IXCHERI-NEXT:    cincoffset ca1, csp, 0
-; RV64IXCHERI-NEXT:    csetbounds ca1, ca1, 16
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -32
+; RV64IXCHERI-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc a1, 0(sp)
+; RV64IXCHERI-NEXT:    cincoffset a1, sp, 0
+; RV64IXCHERI-NEXT:    csetbounds a1, a1, 16
 ; RV64IXCHERI-NEXT:    li a3, 2
 ; RV64IXCHERI-NEXT:    li a4, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_cap
-; RV64IXCHERI-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 32
+; RV64IXCHERI-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 32
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: cmpxchg_cap_acquire_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB41_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.c.aq ca3, (ca0)
+; RV64IAXCHERI-NEXT:    clr.c.aq a3, (a0)
 ; RV64IAXCHERI-NEXT:    bne a3, a1, .LBB41_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB41_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.c.aq a4, ca2, (ca0)
+; RV64IAXCHERI-NEXT:    csc.c.aq a4, a2, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a4, .LBB41_1
 ; RV64IAXCHERI-NEXT:  .LBB41_3:
 ; RV64IAXCHERI-NEXT:    cret
@@ -2477,50 +2477,50 @@ define void @cmpxchg_cap_acquire_monotonic(ptr addrspace(200) %ptr, ptr addrspac
 define void @cmpxchg_cap_acquire_acquire(ptr addrspace(200) %ptr, ptr addrspace(200) %cmp, ptr addrspace(200) %val) addrspace(200) nounwind {
 ; RV32IXCHERI-LABEL: cmpxchg_cap_acquire_acquire:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc ca1, 0(csp)
-; RV32IXCHERI-NEXT:    cincoffset ca1, csp, 0
-; RV32IXCHERI-NEXT:    csetbounds ca1, ca1, 8
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc a1, 0(sp)
+; RV32IXCHERI-NEXT:    cincoffset a1, sp, 0
+; RV32IXCHERI-NEXT:    csetbounds a1, a1, 8
 ; RV32IXCHERI-NEXT:    li a3, 2
 ; RV32IXCHERI-NEXT:    li a4, 2
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_cap
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: cmpxchg_cap_acquire_acquire:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB42_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.c.aq ca3, (ca0)
+; RV32IAXCHERI-NEXT:    clr.c.aq a3, (a0)
 ; RV32IAXCHERI-NEXT:    bne a3, a1, .LBB42_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB42_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.c.aq a4, ca2, (ca0)
+; RV32IAXCHERI-NEXT:    csc.c.aq a4, a2, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a4, .LBB42_1
 ; RV32IAXCHERI-NEXT:  .LBB42_3:
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: cmpxchg_cap_acquire_acquire:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -32
-; RV64IXCHERI-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc ca1, 0(csp)
-; RV64IXCHERI-NEXT:    cincoffset ca1, csp, 0
-; RV64IXCHERI-NEXT:    csetbounds ca1, ca1, 16
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -32
+; RV64IXCHERI-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc a1, 0(sp)
+; RV64IXCHERI-NEXT:    cincoffset a1, sp, 0
+; RV64IXCHERI-NEXT:    csetbounds a1, a1, 16
 ; RV64IXCHERI-NEXT:    li a3, 2
 ; RV64IXCHERI-NEXT:    li a4, 2
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_cap
-; RV64IXCHERI-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 32
+; RV64IXCHERI-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 32
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: cmpxchg_cap_acquire_acquire:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB42_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.c.aq ca3, (ca0)
+; RV64IAXCHERI-NEXT:    clr.c.aq a3, (a0)
 ; RV64IAXCHERI-NEXT:    bne a3, a1, .LBB42_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB42_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.c.aq a4, ca2, (ca0)
+; RV64IAXCHERI-NEXT:    csc.c.aq a4, a2, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a4, .LBB42_1
 ; RV64IAXCHERI-NEXT:  .LBB42_3:
 ; RV64IAXCHERI-NEXT:    cret
@@ -2531,50 +2531,50 @@ define void @cmpxchg_cap_acquire_acquire(ptr addrspace(200) %ptr, ptr addrspace(
 define void @cmpxchg_cap_release_monotonic(ptr addrspace(200) %ptr, ptr addrspace(200) %cmp, ptr addrspace(200) %val) addrspace(200) nounwind {
 ; RV32IXCHERI-LABEL: cmpxchg_cap_release_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc ca1, 0(csp)
-; RV32IXCHERI-NEXT:    cincoffset ca1, csp, 0
-; RV32IXCHERI-NEXT:    csetbounds ca1, ca1, 8
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc a1, 0(sp)
+; RV32IXCHERI-NEXT:    cincoffset a1, sp, 0
+; RV32IXCHERI-NEXT:    csetbounds a1, a1, 8
 ; RV32IXCHERI-NEXT:    li a3, 3
 ; RV32IXCHERI-NEXT:    li a4, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_cap
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: cmpxchg_cap_release_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB43_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.c.rl ca3, (ca0)
+; RV32IAXCHERI-NEXT:    clr.c.rl a3, (a0)
 ; RV32IAXCHERI-NEXT:    bne a3, a1, .LBB43_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB43_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.c a4, ca2, (ca0)
+; RV32IAXCHERI-NEXT:    csc.c a4, a2, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a4, .LBB43_1
 ; RV32IAXCHERI-NEXT:  .LBB43_3:
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: cmpxchg_cap_release_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -32
-; RV64IXCHERI-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc ca1, 0(csp)
-; RV64IXCHERI-NEXT:    cincoffset ca1, csp, 0
-; RV64IXCHERI-NEXT:    csetbounds ca1, ca1, 16
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -32
+; RV64IXCHERI-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc a1, 0(sp)
+; RV64IXCHERI-NEXT:    cincoffset a1, sp, 0
+; RV64IXCHERI-NEXT:    csetbounds a1, a1, 16
 ; RV64IXCHERI-NEXT:    li a3, 3
 ; RV64IXCHERI-NEXT:    li a4, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_cap
-; RV64IXCHERI-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 32
+; RV64IXCHERI-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 32
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: cmpxchg_cap_release_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB43_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.c.rl ca3, (ca0)
+; RV64IAXCHERI-NEXT:    clr.c.rl a3, (a0)
 ; RV64IAXCHERI-NEXT:    bne a3, a1, .LBB43_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB43_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.c a4, ca2, (ca0)
+; RV64IAXCHERI-NEXT:    csc.c a4, a2, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a4, .LBB43_1
 ; RV64IAXCHERI-NEXT:  .LBB43_3:
 ; RV64IAXCHERI-NEXT:    cret
@@ -2585,50 +2585,50 @@ define void @cmpxchg_cap_release_monotonic(ptr addrspace(200) %ptr, ptr addrspac
 define void @cmpxchg_cap_release_acquire(ptr addrspace(200) %ptr, ptr addrspace(200) %cmp, ptr addrspace(200) %val) addrspace(200) nounwind {
 ; RV32IXCHERI-LABEL: cmpxchg_cap_release_acquire:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc ca1, 0(csp)
-; RV32IXCHERI-NEXT:    cincoffset ca1, csp, 0
-; RV32IXCHERI-NEXT:    csetbounds ca1, ca1, 8
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc a1, 0(sp)
+; RV32IXCHERI-NEXT:    cincoffset a1, sp, 0
+; RV32IXCHERI-NEXT:    csetbounds a1, a1, 8
 ; RV32IXCHERI-NEXT:    li a3, 3
 ; RV32IXCHERI-NEXT:    li a4, 2
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_cap
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: cmpxchg_cap_release_acquire:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB44_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.c.aq ca3, (ca0)
+; RV32IAXCHERI-NEXT:    clr.c.aq a3, (a0)
 ; RV32IAXCHERI-NEXT:    bne a3, a1, .LBB44_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB44_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.c.aq a4, ca2, (ca0)
+; RV32IAXCHERI-NEXT:    csc.c.aq a4, a2, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a4, .LBB44_1
 ; RV32IAXCHERI-NEXT:  .LBB44_3:
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: cmpxchg_cap_release_acquire:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -32
-; RV64IXCHERI-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc ca1, 0(csp)
-; RV64IXCHERI-NEXT:    cincoffset ca1, csp, 0
-; RV64IXCHERI-NEXT:    csetbounds ca1, ca1, 16
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -32
+; RV64IXCHERI-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc a1, 0(sp)
+; RV64IXCHERI-NEXT:    cincoffset a1, sp, 0
+; RV64IXCHERI-NEXT:    csetbounds a1, a1, 16
 ; RV64IXCHERI-NEXT:    li a3, 3
 ; RV64IXCHERI-NEXT:    li a4, 2
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_cap
-; RV64IXCHERI-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 32
+; RV64IXCHERI-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 32
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: cmpxchg_cap_release_acquire:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB44_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.c.aq ca3, (ca0)
+; RV64IAXCHERI-NEXT:    clr.c.aq a3, (a0)
 ; RV64IAXCHERI-NEXT:    bne a3, a1, .LBB44_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB44_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.c.aq a4, ca2, (ca0)
+; RV64IAXCHERI-NEXT:    csc.c.aq a4, a2, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a4, .LBB44_1
 ; RV64IAXCHERI-NEXT:  .LBB44_3:
 ; RV64IAXCHERI-NEXT:    cret
@@ -2639,50 +2639,50 @@ define void @cmpxchg_cap_release_acquire(ptr addrspace(200) %ptr, ptr addrspace(
 define void @cmpxchg_cap_acq_rel_monotonic(ptr addrspace(200) %ptr, ptr addrspace(200) %cmp, ptr addrspace(200) %val) addrspace(200) nounwind {
 ; RV32IXCHERI-LABEL: cmpxchg_cap_acq_rel_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc ca1, 0(csp)
-; RV32IXCHERI-NEXT:    cincoffset ca1, csp, 0
-; RV32IXCHERI-NEXT:    csetbounds ca1, ca1, 8
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc a1, 0(sp)
+; RV32IXCHERI-NEXT:    cincoffset a1, sp, 0
+; RV32IXCHERI-NEXT:    csetbounds a1, a1, 8
 ; RV32IXCHERI-NEXT:    li a3, 4
 ; RV32IXCHERI-NEXT:    li a4, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_cap
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: cmpxchg_cap_acq_rel_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB45_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.c.aq ca3, (ca0)
+; RV32IAXCHERI-NEXT:    clr.c.aq a3, (a0)
 ; RV32IAXCHERI-NEXT:    bne a3, a1, .LBB45_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB45_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.c.aq a4, ca2, (ca0)
+; RV32IAXCHERI-NEXT:    csc.c.aq a4, a2, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a4, .LBB45_1
 ; RV32IAXCHERI-NEXT:  .LBB45_3:
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: cmpxchg_cap_acq_rel_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -32
-; RV64IXCHERI-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc ca1, 0(csp)
-; RV64IXCHERI-NEXT:    cincoffset ca1, csp, 0
-; RV64IXCHERI-NEXT:    csetbounds ca1, ca1, 16
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -32
+; RV64IXCHERI-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc a1, 0(sp)
+; RV64IXCHERI-NEXT:    cincoffset a1, sp, 0
+; RV64IXCHERI-NEXT:    csetbounds a1, a1, 16
 ; RV64IXCHERI-NEXT:    li a3, 4
 ; RV64IXCHERI-NEXT:    li a4, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_cap
-; RV64IXCHERI-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 32
+; RV64IXCHERI-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 32
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: cmpxchg_cap_acq_rel_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB45_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.c.aq ca3, (ca0)
+; RV64IAXCHERI-NEXT:    clr.c.aq a3, (a0)
 ; RV64IAXCHERI-NEXT:    bne a3, a1, .LBB45_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB45_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.c.aq a4, ca2, (ca0)
+; RV64IAXCHERI-NEXT:    csc.c.aq a4, a2, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a4, .LBB45_1
 ; RV64IAXCHERI-NEXT:  .LBB45_3:
 ; RV64IAXCHERI-NEXT:    cret
@@ -2693,50 +2693,50 @@ define void @cmpxchg_cap_acq_rel_monotonic(ptr addrspace(200) %ptr, ptr addrspac
 define void @cmpxchg_cap_acq_rel_acquire(ptr addrspace(200) %ptr, ptr addrspace(200) %cmp, ptr addrspace(200) %val) addrspace(200) nounwind {
 ; RV32IXCHERI-LABEL: cmpxchg_cap_acq_rel_acquire:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc ca1, 0(csp)
-; RV32IXCHERI-NEXT:    cincoffset ca1, csp, 0
-; RV32IXCHERI-NEXT:    csetbounds ca1, ca1, 8
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc a1, 0(sp)
+; RV32IXCHERI-NEXT:    cincoffset a1, sp, 0
+; RV32IXCHERI-NEXT:    csetbounds a1, a1, 8
 ; RV32IXCHERI-NEXT:    li a3, 4
 ; RV32IXCHERI-NEXT:    li a4, 2
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_cap
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: cmpxchg_cap_acq_rel_acquire:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB46_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.c.aq ca3, (ca0)
+; RV32IAXCHERI-NEXT:    clr.c.aq a3, (a0)
 ; RV32IAXCHERI-NEXT:    bne a3, a1, .LBB46_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB46_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.c.aq a4, ca2, (ca0)
+; RV32IAXCHERI-NEXT:    csc.c.aq a4, a2, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a4, .LBB46_1
 ; RV32IAXCHERI-NEXT:  .LBB46_3:
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: cmpxchg_cap_acq_rel_acquire:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -32
-; RV64IXCHERI-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc ca1, 0(csp)
-; RV64IXCHERI-NEXT:    cincoffset ca1, csp, 0
-; RV64IXCHERI-NEXT:    csetbounds ca1, ca1, 16
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -32
+; RV64IXCHERI-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc a1, 0(sp)
+; RV64IXCHERI-NEXT:    cincoffset a1, sp, 0
+; RV64IXCHERI-NEXT:    csetbounds a1, a1, 16
 ; RV64IXCHERI-NEXT:    li a3, 4
 ; RV64IXCHERI-NEXT:    li a4, 2
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_cap
-; RV64IXCHERI-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 32
+; RV64IXCHERI-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 32
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: cmpxchg_cap_acq_rel_acquire:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB46_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.c.aq ca3, (ca0)
+; RV64IAXCHERI-NEXT:    clr.c.aq a3, (a0)
 ; RV64IAXCHERI-NEXT:    bne a3, a1, .LBB46_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB46_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.c.aq a4, ca2, (ca0)
+; RV64IAXCHERI-NEXT:    csc.c.aq a4, a2, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a4, .LBB46_1
 ; RV64IAXCHERI-NEXT:  .LBB46_3:
 ; RV64IAXCHERI-NEXT:    cret
@@ -2747,50 +2747,50 @@ define void @cmpxchg_cap_acq_rel_acquire(ptr addrspace(200) %ptr, ptr addrspace(
 define void @cmpxchg_cap_seq_cst_monotonic(ptr addrspace(200) %ptr, ptr addrspace(200) %cmp, ptr addrspace(200) %val) addrspace(200) nounwind {
 ; RV32IXCHERI-LABEL: cmpxchg_cap_seq_cst_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc ca1, 0(csp)
-; RV32IXCHERI-NEXT:    cincoffset ca1, csp, 0
-; RV32IXCHERI-NEXT:    csetbounds ca1, ca1, 8
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc a1, 0(sp)
+; RV32IXCHERI-NEXT:    cincoffset a1, sp, 0
+; RV32IXCHERI-NEXT:    csetbounds a1, a1, 8
 ; RV32IXCHERI-NEXT:    li a3, 5
 ; RV32IXCHERI-NEXT:    li a4, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_cap
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: cmpxchg_cap_seq_cst_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB47_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.c.aqrl ca3, (ca0)
+; RV32IAXCHERI-NEXT:    clr.c.aqrl a3, (a0)
 ; RV32IAXCHERI-NEXT:    bne a3, a1, .LBB47_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB47_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.c.aqrl a4, ca2, (ca0)
+; RV32IAXCHERI-NEXT:    csc.c.aqrl a4, a2, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a4, .LBB47_1
 ; RV32IAXCHERI-NEXT:  .LBB47_3:
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: cmpxchg_cap_seq_cst_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -32
-; RV64IXCHERI-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc ca1, 0(csp)
-; RV64IXCHERI-NEXT:    cincoffset ca1, csp, 0
-; RV64IXCHERI-NEXT:    csetbounds ca1, ca1, 16
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -32
+; RV64IXCHERI-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc a1, 0(sp)
+; RV64IXCHERI-NEXT:    cincoffset a1, sp, 0
+; RV64IXCHERI-NEXT:    csetbounds a1, a1, 16
 ; RV64IXCHERI-NEXT:    li a3, 5
 ; RV64IXCHERI-NEXT:    li a4, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_cap
-; RV64IXCHERI-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 32
+; RV64IXCHERI-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 32
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: cmpxchg_cap_seq_cst_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB47_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.c.aqrl ca3, (ca0)
+; RV64IAXCHERI-NEXT:    clr.c.aqrl a3, (a0)
 ; RV64IAXCHERI-NEXT:    bne a3, a1, .LBB47_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB47_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.c.aqrl a4, ca2, (ca0)
+; RV64IAXCHERI-NEXT:    csc.c.aqrl a4, a2, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a4, .LBB47_1
 ; RV64IAXCHERI-NEXT:  .LBB47_3:
 ; RV64IAXCHERI-NEXT:    cret
@@ -2801,50 +2801,50 @@ define void @cmpxchg_cap_seq_cst_monotonic(ptr addrspace(200) %ptr, ptr addrspac
 define void @cmpxchg_cap_seq_cst_acquire(ptr addrspace(200) %ptr, ptr addrspace(200) %cmp, ptr addrspace(200) %val) addrspace(200) nounwind {
 ; RV32IXCHERI-LABEL: cmpxchg_cap_seq_cst_acquire:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc ca1, 0(csp)
-; RV32IXCHERI-NEXT:    cincoffset ca1, csp, 0
-; RV32IXCHERI-NEXT:    csetbounds ca1, ca1, 8
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc a1, 0(sp)
+; RV32IXCHERI-NEXT:    cincoffset a1, sp, 0
+; RV32IXCHERI-NEXT:    csetbounds a1, a1, 8
 ; RV32IXCHERI-NEXT:    li a3, 5
 ; RV32IXCHERI-NEXT:    li a4, 2
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_cap
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: cmpxchg_cap_seq_cst_acquire:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB48_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.c.aqrl ca3, (ca0)
+; RV32IAXCHERI-NEXT:    clr.c.aqrl a3, (a0)
 ; RV32IAXCHERI-NEXT:    bne a3, a1, .LBB48_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB48_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.c.aqrl a4, ca2, (ca0)
+; RV32IAXCHERI-NEXT:    csc.c.aqrl a4, a2, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a4, .LBB48_1
 ; RV32IAXCHERI-NEXT:  .LBB48_3:
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: cmpxchg_cap_seq_cst_acquire:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -32
-; RV64IXCHERI-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc ca1, 0(csp)
-; RV64IXCHERI-NEXT:    cincoffset ca1, csp, 0
-; RV64IXCHERI-NEXT:    csetbounds ca1, ca1, 16
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -32
+; RV64IXCHERI-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc a1, 0(sp)
+; RV64IXCHERI-NEXT:    cincoffset a1, sp, 0
+; RV64IXCHERI-NEXT:    csetbounds a1, a1, 16
 ; RV64IXCHERI-NEXT:    li a3, 5
 ; RV64IXCHERI-NEXT:    li a4, 2
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_cap
-; RV64IXCHERI-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 32
+; RV64IXCHERI-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 32
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: cmpxchg_cap_seq_cst_acquire:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB48_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.c.aqrl ca3, (ca0)
+; RV64IAXCHERI-NEXT:    clr.c.aqrl a3, (a0)
 ; RV64IAXCHERI-NEXT:    bne a3, a1, .LBB48_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB48_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.c.aqrl a4, ca2, (ca0)
+; RV64IAXCHERI-NEXT:    csc.c.aqrl a4, a2, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a4, .LBB48_1
 ; RV64IAXCHERI-NEXT:  .LBB48_3:
 ; RV64IAXCHERI-NEXT:    cret
@@ -2855,50 +2855,50 @@ define void @cmpxchg_cap_seq_cst_acquire(ptr addrspace(200) %ptr, ptr addrspace(
 define void @cmpxchg_cap_seq_cst_seq_cst(ptr addrspace(200) %ptr, ptr addrspace(200) %cmp, ptr addrspace(200) %val) addrspace(200) nounwind {
 ; RV32IXCHERI-LABEL: cmpxchg_cap_seq_cst_seq_cst:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc ca1, 0(csp)
-; RV32IXCHERI-NEXT:    cincoffset ca1, csp, 0
-; RV32IXCHERI-NEXT:    csetbounds ca1, ca1, 8
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc a1, 0(sp)
+; RV32IXCHERI-NEXT:    cincoffset a1, sp, 0
+; RV32IXCHERI-NEXT:    csetbounds a1, a1, 8
 ; RV32IXCHERI-NEXT:    li a3, 5
 ; RV32IXCHERI-NEXT:    li a4, 5
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_cap
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: cmpxchg_cap_seq_cst_seq_cst:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB49_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.c.aqrl ca3, (ca0)
+; RV32IAXCHERI-NEXT:    clr.c.aqrl a3, (a0)
 ; RV32IAXCHERI-NEXT:    bne a3, a1, .LBB49_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB49_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.c.aqrl a4, ca2, (ca0)
+; RV32IAXCHERI-NEXT:    csc.c.aqrl a4, a2, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a4, .LBB49_1
 ; RV32IAXCHERI-NEXT:  .LBB49_3:
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: cmpxchg_cap_seq_cst_seq_cst:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -32
-; RV64IXCHERI-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc ca1, 0(csp)
-; RV64IXCHERI-NEXT:    cincoffset ca1, csp, 0
-; RV64IXCHERI-NEXT:    csetbounds ca1, ca1, 16
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -32
+; RV64IXCHERI-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc a1, 0(sp)
+; RV64IXCHERI-NEXT:    cincoffset a1, sp, 0
+; RV64IXCHERI-NEXT:    csetbounds a1, a1, 16
 ; RV64IXCHERI-NEXT:    li a3, 5
 ; RV64IXCHERI-NEXT:    li a4, 5
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_cap
-; RV64IXCHERI-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 32
+; RV64IXCHERI-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 32
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: cmpxchg_cap_seq_cst_seq_cst:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB49_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.c.aqrl ca3, (ca0)
+; RV64IAXCHERI-NEXT:    clr.c.aqrl a3, (a0)
 ; RV64IAXCHERI-NEXT:    bne a3, a1, .LBB49_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB49_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.c.aqrl a4, ca2, (ca0)
+; RV64IAXCHERI-NEXT:    csc.c.aqrl a4, a2, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a4, .LBB49_1
 ; RV64IAXCHERI-NEXT:  .LBB49_3:
 ; RV64IAXCHERI-NEXT:    cret
diff --git a/llvm/test/CodeGen/RISCV/cheri/atomic-load-store.ll b/llvm/test/CodeGen/RISCV/cheri/atomic-load-store.ll
index 57ebb37722c27..4d3bf3778870c 100644
--- a/llvm/test/CodeGen/RISCV/cheri/atomic-load-store.ll
+++ b/llvm/test/CodeGen/RISCV/cheri/atomic-load-store.ll
@@ -11,32 +11,32 @@
 define i8 @atomic_load_i8_unordered(i8 addrspace(200)* %a) nounwind {
 ; RV32IXCHERI-LABEL: atomic_load_i8_unordered:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a1, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_load_1
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomic_load_i8_unordered:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    clb a0, 0(ca0)
+; RV32IAXCHERI-NEXT:    clb a0, 0(a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomic_load_i8_unordered:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a1, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_load_1
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomic_load_i8_unordered:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    clb a0, 0(ca0)
+; RV64IAXCHERI-NEXT:    clb a0, 0(a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = load atomic i8, i8 addrspace(200)* %a unordered, align 1
   ret i8 %1
@@ -45,32 +45,32 @@ define i8 @atomic_load_i8_unordered(i8 addrspace(200)* %a) nounwind {
 define i8 @atomic_load_i8_monotonic(i8 addrspace(200)* %a) nounwind {
 ; RV32IXCHERI-LABEL: atomic_load_i8_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a1, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_load_1
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomic_load_i8_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    clb a0, 0(ca0)
+; RV32IAXCHERI-NEXT:    clb a0, 0(a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomic_load_i8_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a1, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_load_1
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomic_load_i8_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    clb a0, 0(ca0)
+; RV64IAXCHERI-NEXT:    clb a0, 0(a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = load atomic i8, i8 addrspace(200)* %a monotonic, align 1
   ret i8 %1
@@ -79,33 +79,33 @@ define i8 @atomic_load_i8_monotonic(i8 addrspace(200)* %a) nounwind {
 define i8 @atomic_load_i8_acquire(i8 addrspace(200)* %a) nounwind {
 ; RV32IXCHERI-LABEL: atomic_load_i8_acquire:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a1, 2
 ; RV32IXCHERI-NEXT:    ccall __atomic_load_1
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomic_load_i8_acquire:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    clb a0, 0(ca0)
+; RV32IAXCHERI-NEXT:    clb a0, 0(a0)
 ; RV32IAXCHERI-NEXT:    fence r, rw
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomic_load_i8_acquire:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a1, 2
 ; RV64IXCHERI-NEXT:    ccall __atomic_load_1
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomic_load_i8_acquire:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    clb a0, 0(ca0)
+; RV64IAXCHERI-NEXT:    clb a0, 0(a0)
 ; RV64IAXCHERI-NEXT:    fence r, rw
 ; RV64IAXCHERI-NEXT:    cret
   %1 = load atomic i8, i8 addrspace(200)* %a acquire, align 1
@@ -115,35 +115,35 @@ define i8 @atomic_load_i8_acquire(i8 addrspace(200)* %a) nounwind {
 define i8 @atomic_load_i8_seq_cst(i8 addrspace(200)* %a) nounwind {
 ; RV32IXCHERI-LABEL: atomic_load_i8_seq_cst:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a1, 5
 ; RV32IXCHERI-NEXT:    ccall __atomic_load_1
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomic_load_i8_seq_cst:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:    fence rw, rw
-; RV32IAXCHERI-NEXT:    clb a0, 0(ca0)
+; RV32IAXCHERI-NEXT:    clb a0, 0(a0)
 ; RV32IAXCHERI-NEXT:    fence r, rw
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomic_load_i8_seq_cst:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a1, 5
 ; RV64IXCHERI-NEXT:    ccall __atomic_load_1
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomic_load_i8_seq_cst:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:    fence rw, rw
-; RV64IAXCHERI-NEXT:    clb a0, 0(ca0)
+; RV64IAXCHERI-NEXT:    clb a0, 0(a0)
 ; RV64IAXCHERI-NEXT:    fence r, rw
 ; RV64IAXCHERI-NEXT:    cret
   %1 = load atomic i8, i8 addrspace(200)* %a seq_cst, align 1
@@ -153,32 +153,32 @@ define i8 @atomic_load_i8_seq_cst(i8 addrspace(200)* %a) nounwind {
 define i16 @atomic_load_i16_unordered(i16 addrspace(200)* %a) nounwind {
 ; RV32IXCHERI-LABEL: atomic_load_i16_unordered:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a1, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_load_2
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomic_load_i16_unordered:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    clh a0, 0(ca0)
+; RV32IAXCHERI-NEXT:    clh a0, 0(a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomic_load_i16_unordered:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a1, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_load_2
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomic_load_i16_unordered:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    clh a0, 0(ca0)
+; RV64IAXCHERI-NEXT:    clh a0, 0(a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = load atomic i16, i16 addrspace(200)* %a unordered, align 2
   ret i16 %1
@@ -187,32 +187,32 @@ define i16 @atomic_load_i16_unordered(i16 addrspace(200)* %a) nounwind {
 define i16 @atomic_load_i16_monotonic(i16 addrspace(200)* %a) nounwind {
 ; RV32IXCHERI-LABEL: atomic_load_i16_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a1, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_load_2
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomic_load_i16_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    clh a0, 0(ca0)
+; RV32IAXCHERI-NEXT:    clh a0, 0(a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomic_load_i16_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a1, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_load_2
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomic_load_i16_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    clh a0, 0(ca0)
+; RV64IAXCHERI-NEXT:    clh a0, 0(a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = load atomic i16, i16 addrspace(200)* %a monotonic, align 2
   ret i16 %1
@@ -221,33 +221,33 @@ define i16 @atomic_load_i16_monotonic(i16 addrspace(200)* %a) nounwind {
 define i16 @atomic_load_i16_acquire(i16 addrspace(200)* %a) nounwind {
 ; RV32IXCHERI-LABEL: atomic_load_i16_acquire:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a1, 2
 ; RV32IXCHERI-NEXT:    ccall __atomic_load_2
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomic_load_i16_acquire:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    clh a0, 0(ca0)
+; RV32IAXCHERI-NEXT:    clh a0, 0(a0)
 ; RV32IAXCHERI-NEXT:    fence r, rw
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomic_load_i16_acquire:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a1, 2
 ; RV64IXCHERI-NEXT:    ccall __atomic_load_2
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomic_load_i16_acquire:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    clh a0, 0(ca0)
+; RV64IAXCHERI-NEXT:    clh a0, 0(a0)
 ; RV64IAXCHERI-NEXT:    fence r, rw
 ; RV64IAXCHERI-NEXT:    cret
   %1 = load atomic i16, i16 addrspace(200)* %a acquire, align 2
@@ -257,35 +257,35 @@ define i16 @atomic_load_i16_acquire(i16 addrspace(200)* %a) nounwind {
 define i16 @atomic_load_i16_seq_cst(i16 addrspace(200)* %a) nounwind {
 ; RV32IXCHERI-LABEL: atomic_load_i16_seq_cst:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a1, 5
 ; RV32IXCHERI-NEXT:    ccall __atomic_load_2
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomic_load_i16_seq_cst:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:    fence rw, rw
-; RV32IAXCHERI-NEXT:    clh a0, 0(ca0)
+; RV32IAXCHERI-NEXT:    clh a0, 0(a0)
 ; RV32IAXCHERI-NEXT:    fence r, rw
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomic_load_i16_seq_cst:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a1, 5
 ; RV64IXCHERI-NEXT:    ccall __atomic_load_2
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomic_load_i16_seq_cst:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:    fence rw, rw
-; RV64IAXCHERI-NEXT:    clh a0, 0(ca0)
+; RV64IAXCHERI-NEXT:    clh a0, 0(a0)
 ; RV64IAXCHERI-NEXT:    fence r, rw
 ; RV64IAXCHERI-NEXT:    cret
   %1 = load atomic i16, i16 addrspace(200)* %a seq_cst, align 2
@@ -295,32 +295,32 @@ define i16 @atomic_load_i16_seq_cst(i16 addrspace(200)* %a) nounwind {
 define i32 @atomic_load_i32_unordered(i32 addrspace(200)* %a) nounwind {
 ; RV32IXCHERI-LABEL: atomic_load_i32_unordered:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a1, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_load_4
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomic_load_i32_unordered:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    clw a0, 0(ca0)
+; RV32IAXCHERI-NEXT:    clw a0, 0(a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomic_load_i32_unordered:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a1, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_load_4
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomic_load_i32_unordered:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    clw a0, 0(ca0)
+; RV64IAXCHERI-NEXT:    clw a0, 0(a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = load atomic i32, i32 addrspace(200)* %a unordered, align 4
   ret i32 %1
@@ -329,32 +329,32 @@ define i32 @atomic_load_i32_unordered(i32 addrspace(200)* %a) nounwind {
 define i32 @atomic_load_i32_monotonic(i32 addrspace(200)* %a) nounwind {
 ; RV32IXCHERI-LABEL: atomic_load_i32_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a1, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_load_4
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomic_load_i32_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    clw a0, 0(ca0)
+; RV32IAXCHERI-NEXT:    clw a0, 0(a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomic_load_i32_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a1, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_load_4
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomic_load_i32_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    clw a0, 0(ca0)
+; RV64IAXCHERI-NEXT:    clw a0, 0(a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = load atomic i32, i32 addrspace(200)* %a monotonic, align 4
   ret i32 %1
@@ -363,33 +363,33 @@ define i32 @atomic_load_i32_monotonic(i32 addrspace(200)* %a) nounwind {
 define i32 @atomic_load_i32_acquire(i32 addrspace(200)* %a) nounwind {
 ; RV32IXCHERI-LABEL: atomic_load_i32_acquire:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a1, 2
 ; RV32IXCHERI-NEXT:    ccall __atomic_load_4
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomic_load_i32_acquire:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    clw a0, 0(ca0)
+; RV32IAXCHERI-NEXT:    clw a0, 0(a0)
 ; RV32IAXCHERI-NEXT:    fence r, rw
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomic_load_i32_acquire:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a1, 2
 ; RV64IXCHERI-NEXT:    ccall __atomic_load_4
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomic_load_i32_acquire:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    clw a0, 0(ca0)
+; RV64IAXCHERI-NEXT:    clw a0, 0(a0)
 ; RV64IAXCHERI-NEXT:    fence r, rw
 ; RV64IAXCHERI-NEXT:    cret
   %1 = load atomic i32, i32 addrspace(200)* %a acquire, align 4
@@ -399,35 +399,35 @@ define i32 @atomic_load_i32_acquire(i32 addrspace(200)* %a) nounwind {
 define i32 @atomic_load_i32_seq_cst(i32 addrspace(200)* %a) nounwind {
 ; RV32IXCHERI-LABEL: atomic_load_i32_seq_cst:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a1, 5
 ; RV32IXCHERI-NEXT:    ccall __atomic_load_4
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomic_load_i32_seq_cst:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:    fence rw, rw
-; RV32IAXCHERI-NEXT:    clw a0, 0(ca0)
+; RV32IAXCHERI-NEXT:    clw a0, 0(a0)
 ; RV32IAXCHERI-NEXT:    fence r, rw
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomic_load_i32_seq_cst:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a1, 5
 ; RV64IXCHERI-NEXT:    ccall __atomic_load_4
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomic_load_i32_seq_cst:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:    fence rw, rw
-; RV64IAXCHERI-NEXT:    clw a0, 0(ca0)
+; RV64IAXCHERI-NEXT:    clw a0, 0(a0)
 ; RV64IAXCHERI-NEXT:    fence r, rw
 ; RV64IAXCHERI-NEXT:    cret
   %1 = load atomic i32, i32 addrspace(200)* %a seq_cst, align 4
@@ -437,37 +437,37 @@ define i32 @atomic_load_i32_seq_cst(i32 addrspace(200)* %a) nounwind {
 define i64 @atomic_load_i64_unordered(i64 addrspace(200)* %a) nounwind {
 ; RV32IXCHERI-LABEL: atomic_load_i64_unordered:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a1, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_load_8
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomic_load_i64_unordered:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IAXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IAXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    li a1, 0
 ; RV32IAXCHERI-NEXT:    ccall __atomic_load_8
-; RV32IAXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IAXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomic_load_i64_unordered:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a1, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_load_8
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomic_load_i64_unordered:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    cld a0, 0(ca0)
+; RV64IAXCHERI-NEXT:    cld a0, 0(a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = load atomic i64, i64 addrspace(200)* %a unordered, align 8
   ret i64 %1
@@ -476,37 +476,37 @@ define i64 @atomic_load_i64_unordered(i64 addrspace(200)* %a) nounwind {
 define i64 @atomic_load_i64_monotonic(i64 addrspace(200)* %a) nounwind {
 ; RV32IXCHERI-LABEL: atomic_load_i64_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a1, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_load_8
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomic_load_i64_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IAXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IAXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    li a1, 0
 ; RV32IAXCHERI-NEXT:    ccall __atomic_load_8
-; RV32IAXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IAXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomic_load_i64_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a1, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_load_8
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomic_load_i64_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    cld a0, 0(ca0)
+; RV64IAXCHERI-NEXT:    cld a0, 0(a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = load atomic i64, i64 addrspace(200)* %a monotonic, align 8
   ret i64 %1
@@ -515,37 +515,37 @@ define i64 @atomic_load_i64_monotonic(i64 addrspace(200)* %a) nounwind {
 define i64 @atomic_load_i64_acquire(i64 addrspace(200)* %a) nounwind {
 ; RV32IXCHERI-LABEL: atomic_load_i64_acquire:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a1, 2
 ; RV32IXCHERI-NEXT:    ccall __atomic_load_8
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomic_load_i64_acquire:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IAXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IAXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    li a1, 2
 ; RV32IAXCHERI-NEXT:    ccall __atomic_load_8
-; RV32IAXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IAXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomic_load_i64_acquire:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a1, 2
 ; RV64IXCHERI-NEXT:    ccall __atomic_load_8
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomic_load_i64_acquire:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    cld a0, 0(ca0)
+; RV64IAXCHERI-NEXT:    cld a0, 0(a0)
 ; RV64IAXCHERI-NEXT:    fence r, rw
 ; RV64IAXCHERI-NEXT:    cret
   %1 = load atomic i64, i64 addrspace(200)* %a acquire, align 8
@@ -555,38 +555,38 @@ define i64 @atomic_load_i64_acquire(i64 addrspace(200)* %a) nounwind {
 define i64 @atomic_load_i64_seq_cst(i64 addrspace(200)* %a) nounwind {
 ; RV32IXCHERI-LABEL: atomic_load_i64_seq_cst:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a1, 5
 ; RV32IXCHERI-NEXT:    ccall __atomic_load_8
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomic_load_i64_seq_cst:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IAXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IAXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    li a1, 5
 ; RV32IAXCHERI-NEXT:    ccall __atomic_load_8
-; RV32IAXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IAXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomic_load_i64_seq_cst:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a1, 5
 ; RV64IXCHERI-NEXT:    ccall __atomic_load_8
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomic_load_i64_seq_cst:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:    fence rw, rw
-; RV64IAXCHERI-NEXT:    cld a0, 0(ca0)
+; RV64IAXCHERI-NEXT:    cld a0, 0(a0)
 ; RV64IAXCHERI-NEXT:    fence r, rw
 ; RV64IAXCHERI-NEXT:    cret
   %1 = load atomic i64, i64 addrspace(200)* %a seq_cst, align 8
@@ -596,32 +596,32 @@ define i64 @atomic_load_i64_seq_cst(i64 addrspace(200)* %a) nounwind {
 define void @atomic_store_i8_unordered(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomic_store_i8_unordered:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_store_1
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomic_store_i8_unordered:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    csb a1, 0(ca0)
+; RV32IAXCHERI-NEXT:    csb a1, 0(a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomic_store_i8_unordered:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_store_1
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomic_store_i8_unordered:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    csb a1, 0(ca0)
+; RV64IAXCHERI-NEXT:    csb a1, 0(a0)
 ; RV64IAXCHERI-NEXT:    cret
   store atomic i8 %b, i8 addrspace(200)* %a unordered, align 1
   ret void
@@ -630,32 +630,32 @@ define void @atomic_store_i8_unordered(i8 addrspace(200)* %a, i8 %b) nounwind {
 define void @atomic_store_i8_monotonic(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomic_store_i8_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_store_1
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomic_store_i8_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    csb a1, 0(ca0)
+; RV32IAXCHERI-NEXT:    csb a1, 0(a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomic_store_i8_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_store_1
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomic_store_i8_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    csb a1, 0(ca0)
+; RV64IAXCHERI-NEXT:    csb a1, 0(a0)
 ; RV64IAXCHERI-NEXT:    cret
   store atomic i8 %b, i8 addrspace(200)* %a monotonic, align 1
   ret void
@@ -664,34 +664,34 @@ define void @atomic_store_i8_monotonic(i8 addrspace(200)* %a, i8 %b) nounwind {
 define void @atomic_store_i8_release(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomic_store_i8_release:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 3
 ; RV32IXCHERI-NEXT:    ccall __atomic_store_1
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomic_store_i8_release:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:    fence rw, w
-; RV32IAXCHERI-NEXT:    csb a1, 0(ca0)
+; RV32IAXCHERI-NEXT:    csb a1, 0(a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomic_store_i8_release:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 3
 ; RV64IXCHERI-NEXT:    ccall __atomic_store_1
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomic_store_i8_release:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:    fence rw, w
-; RV64IAXCHERI-NEXT:    csb a1, 0(ca0)
+; RV64IAXCHERI-NEXT:    csb a1, 0(a0)
 ; RV64IAXCHERI-NEXT:    cret
   store atomic i8 %b, i8 addrspace(200)* %a release, align 1
   ret void
@@ -700,35 +700,35 @@ define void @atomic_store_i8_release(i8 addrspace(200)* %a, i8 %b) nounwind {
 define void @atomic_store_i8_seq_cst(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomic_store_i8_seq_cst:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 5
 ; RV32IXCHERI-NEXT:    ccall __atomic_store_1
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomic_store_i8_seq_cst:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:    fence rw, w
-; RV32IAXCHERI-NEXT:    csb a1, 0(ca0)
+; RV32IAXCHERI-NEXT:    csb a1, 0(a0)
 ; RV32IAXCHERI-NEXT:    fence rw, rw
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomic_store_i8_seq_cst:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 5
 ; RV64IXCHERI-NEXT:    ccall __atomic_store_1
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomic_store_i8_seq_cst:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:    fence rw, w
-; RV64IAXCHERI-NEXT:    csb a1, 0(ca0)
+; RV64IAXCHERI-NEXT:    csb a1, 0(a0)
 ; RV64IAXCHERI-NEXT:    fence rw, rw
 ; RV64IAXCHERI-NEXT:    cret
   store atomic i8 %b, i8 addrspace(200)* %a seq_cst, align 1
@@ -738,32 +738,32 @@ define void @atomic_store_i8_seq_cst(i8 addrspace(200)* %a, i8 %b) nounwind {
 define void @atomic_store_i16_unordered(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomic_store_i16_unordered:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_store_2
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomic_store_i16_unordered:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    csh a1, 0(ca0)
+; RV32IAXCHERI-NEXT:    csh a1, 0(a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomic_store_i16_unordered:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_store_2
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomic_store_i16_unordered:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    csh a1, 0(ca0)
+; RV64IAXCHERI-NEXT:    csh a1, 0(a0)
 ; RV64IAXCHERI-NEXT:    cret
   store atomic i16 %b, i16 addrspace(200)* %a unordered, align 2
   ret void
@@ -772,32 +772,32 @@ define void @atomic_store_i16_unordered(i16 addrspace(200)* %a, i16 %b) nounwind
 define void @atomic_store_i16_monotonic(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomic_store_i16_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_store_2
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomic_store_i16_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    csh a1, 0(ca0)
+; RV32IAXCHERI-NEXT:    csh a1, 0(a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomic_store_i16_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_store_2
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomic_store_i16_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    csh a1, 0(ca0)
+; RV64IAXCHERI-NEXT:    csh a1, 0(a0)
 ; RV64IAXCHERI-NEXT:    cret
   store atomic i16 %b, i16 addrspace(200)* %a monotonic, align 2
   ret void
@@ -806,34 +806,34 @@ define void @atomic_store_i16_monotonic(i16 addrspace(200)* %a, i16 %b) nounwind
 define void @atomic_store_i16_release(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomic_store_i16_release:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 3
 ; RV32IXCHERI-NEXT:    ccall __atomic_store_2
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomic_store_i16_release:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:    fence rw, w
-; RV32IAXCHERI-NEXT:    csh a1, 0(ca0)
+; RV32IAXCHERI-NEXT:    csh a1, 0(a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomic_store_i16_release:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 3
 ; RV64IXCHERI-NEXT:    ccall __atomic_store_2
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomic_store_i16_release:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:    fence rw, w
-; RV64IAXCHERI-NEXT:    csh a1, 0(ca0)
+; RV64IAXCHERI-NEXT:    csh a1, 0(a0)
 ; RV64IAXCHERI-NEXT:    cret
   store atomic i16 %b, i16 addrspace(200)* %a release, align 2
   ret void
@@ -842,35 +842,35 @@ define void @atomic_store_i16_release(i16 addrspace(200)* %a, i16 %b) nounwind {
 define void @atomic_store_i16_seq_cst(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomic_store_i16_seq_cst:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 5
 ; RV32IXCHERI-NEXT:    ccall __atomic_store_2
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomic_store_i16_seq_cst:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:    fence rw, w
-; RV32IAXCHERI-NEXT:    csh a1, 0(ca0)
+; RV32IAXCHERI-NEXT:    csh a1, 0(a0)
 ; RV32IAXCHERI-NEXT:    fence rw, rw
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomic_store_i16_seq_cst:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 5
 ; RV64IXCHERI-NEXT:    ccall __atomic_store_2
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomic_store_i16_seq_cst:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:    fence rw, w
-; RV64IAXCHERI-NEXT:    csh a1, 0(ca0)
+; RV64IAXCHERI-NEXT:    csh a1, 0(a0)
 ; RV64IAXCHERI-NEXT:    fence rw, rw
 ; RV64IAXCHERI-NEXT:    cret
   store atomic i16 %b, i16 addrspace(200)* %a seq_cst, align 2
@@ -880,32 +880,32 @@ define void @atomic_store_i16_seq_cst(i16 addrspace(200)* %a, i16 %b) nounwind {
 define void @atomic_store_i32_unordered(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomic_store_i32_unordered:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_store_4
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomic_store_i32_unordered:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    csw a1, 0(ca0)
+; RV32IAXCHERI-NEXT:    csw a1, 0(a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomic_store_i32_unordered:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_store_4
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomic_store_i32_unordered:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    csw a1, 0(ca0)
+; RV64IAXCHERI-NEXT:    csw a1, 0(a0)
 ; RV64IAXCHERI-NEXT:    cret
   store atomic i32 %b, i32 addrspace(200)* %a unordered, align 4
   ret void
@@ -914,32 +914,32 @@ define void @atomic_store_i32_unordered(i32 addrspace(200)* %a, i32 %b) nounwind
 define void @atomic_store_i32_monotonic(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomic_store_i32_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_store_4
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomic_store_i32_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    csw a1, 0(ca0)
+; RV32IAXCHERI-NEXT:    csw a1, 0(a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomic_store_i32_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_store_4
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomic_store_i32_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    csw a1, 0(ca0)
+; RV64IAXCHERI-NEXT:    csw a1, 0(a0)
 ; RV64IAXCHERI-NEXT:    cret
   store atomic i32 %b, i32 addrspace(200)* %a monotonic, align 4
   ret void
@@ -948,34 +948,34 @@ define void @atomic_store_i32_monotonic(i32 addrspace(200)* %a, i32 %b) nounwind
 define void @atomic_store_i32_release(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomic_store_i32_release:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 3
 ; RV32IXCHERI-NEXT:    ccall __atomic_store_4
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomic_store_i32_release:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:    fence rw, w
-; RV32IAXCHERI-NEXT:    csw a1, 0(ca0)
+; RV32IAXCHERI-NEXT:    csw a1, 0(a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomic_store_i32_release:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 3
 ; RV64IXCHERI-NEXT:    ccall __atomic_store_4
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomic_store_i32_release:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:    fence rw, w
-; RV64IAXCHERI-NEXT:    csw a1, 0(ca0)
+; RV64IAXCHERI-NEXT:    csw a1, 0(a0)
 ; RV64IAXCHERI-NEXT:    cret
   store atomic i32 %b, i32 addrspace(200)* %a release, align 4
   ret void
@@ -984,35 +984,35 @@ define void @atomic_store_i32_release(i32 addrspace(200)* %a, i32 %b) nounwind {
 define void @atomic_store_i32_seq_cst(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomic_store_i32_seq_cst:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 5
 ; RV32IXCHERI-NEXT:    ccall __atomic_store_4
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomic_store_i32_seq_cst:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:    fence rw, w
-; RV32IAXCHERI-NEXT:    csw a1, 0(ca0)
+; RV32IAXCHERI-NEXT:    csw a1, 0(a0)
 ; RV32IAXCHERI-NEXT:    fence rw, rw
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomic_store_i32_seq_cst:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 5
 ; RV64IXCHERI-NEXT:    ccall __atomic_store_4
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomic_store_i32_seq_cst:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:    fence rw, w
-; RV64IAXCHERI-NEXT:    csw a1, 0(ca0)
+; RV64IAXCHERI-NEXT:    csw a1, 0(a0)
 ; RV64IAXCHERI-NEXT:    fence rw, rw
 ; RV64IAXCHERI-NEXT:    cret
   store atomic i32 %b, i32 addrspace(200)* %a seq_cst, align 4
@@ -1022,37 +1022,37 @@ define void @atomic_store_i32_seq_cst(i32 addrspace(200)* %a, i32 %b) nounwind {
 define void @atomic_store_i64_unordered(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomic_store_i64_unordered:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a3, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_store_8
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomic_store_i64_unordered:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IAXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IAXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    li a3, 0
 ; RV32IAXCHERI-NEXT:    ccall __atomic_store_8
-; RV32IAXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IAXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomic_store_i64_unordered:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_store_8
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomic_store_i64_unordered:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    csd a1, 0(ca0)
+; RV64IAXCHERI-NEXT:    csd a1, 0(a0)
 ; RV64IAXCHERI-NEXT:    cret
   store atomic i64 %b, i64 addrspace(200)* %a unordered, align 8
   ret void
@@ -1061,37 +1061,37 @@ define void @atomic_store_i64_unordered(i64 addrspace(200)* %a, i64 %b) nounwind
 define void @atomic_store_i64_monotonic(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomic_store_i64_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a3, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_store_8
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomic_store_i64_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IAXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IAXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    li a3, 0
 ; RV32IAXCHERI-NEXT:    ccall __atomic_store_8
-; RV32IAXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IAXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomic_store_i64_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_store_8
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomic_store_i64_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    csd a1, 0(ca0)
+; RV64IAXCHERI-NEXT:    csd a1, 0(a0)
 ; RV64IAXCHERI-NEXT:    cret
   store atomic i64 %b, i64 addrspace(200)* %a monotonic, align 8
   ret void
@@ -1100,38 +1100,38 @@ define void @atomic_store_i64_monotonic(i64 addrspace(200)* %a, i64 %b) nounwind
 define void @atomic_store_i64_release(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomic_store_i64_release:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a3, 3
 ; RV32IXCHERI-NEXT:    ccall __atomic_store_8
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomic_store_i64_release:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IAXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IAXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    li a3, 3
 ; RV32IAXCHERI-NEXT:    ccall __atomic_store_8
-; RV32IAXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IAXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomic_store_i64_release:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 3
 ; RV64IXCHERI-NEXT:    ccall __atomic_store_8
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomic_store_i64_release:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:    fence rw, w
-; RV64IAXCHERI-NEXT:    csd a1, 0(ca0)
+; RV64IAXCHERI-NEXT:    csd a1, 0(a0)
 ; RV64IAXCHERI-NEXT:    cret
   store atomic i64 %b, i64 addrspace(200)* %a release, align 8
   ret void
@@ -1140,38 +1140,38 @@ define void @atomic_store_i64_release(i64 addrspace(200)* %a, i64 %b) nounwind {
 define void @atomic_store_i64_seq_cst(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomic_store_i64_seq_cst:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a3, 5
 ; RV32IXCHERI-NEXT:    ccall __atomic_store_8
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomic_store_i64_seq_cst:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IAXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IAXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    li a3, 5
 ; RV32IAXCHERI-NEXT:    ccall __atomic_store_8
-; RV32IAXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IAXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomic_store_i64_seq_cst:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 5
 ; RV64IXCHERI-NEXT:    ccall __atomic_store_8
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomic_store_i64_seq_cst:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:    fence rw, w
-; RV64IAXCHERI-NEXT:    csd a1, 0(ca0)
+; RV64IAXCHERI-NEXT:    csd a1, 0(a0)
 ; RV64IAXCHERI-NEXT:    fence rw, rw
 ; RV64IAXCHERI-NEXT:    cret
   store atomic i64 %b, i64 addrspace(200)* %a seq_cst, align 8
diff --git a/llvm/test/CodeGen/RISCV/cheri/atomic-load-store32.ll b/llvm/test/CodeGen/RISCV/cheri/atomic-load-store32.ll
index ca8606fba3daa..31e37815afc48 100644
--- a/llvm/test/CodeGen/RISCV/cheri/atomic-load-store32.ll
+++ b/llvm/test/CodeGen/RISCV/cheri/atomic-load-store32.ll
@@ -7,17 +7,17 @@
 define i8 addrspace(200)* @atomic_load_cap_unordered(i8 addrspace(200)* addrspace(200)* %a) nounwind {
 ; RV32IXCHERI-LABEL: atomic_load_cap_unordered:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a1, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_load_cap
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomic_load_cap_unordered:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    clc ca0, 0(ca0)
+; RV32IAXCHERI-NEXT:    clc a0, 0(a0)
 ; RV32IAXCHERI-NEXT:    cret
   %1 = load atomic i8 addrspace(200)*, i8 addrspace(200)* addrspace(200)* %a unordered, align 8
   ret i8 addrspace(200)* %1
@@ -26,17 +26,17 @@ define i8 addrspace(200)* @atomic_load_cap_unordered(i8 addrspace(200)* addrspac
 define i8 addrspace(200)* @atomic_load_cap_monotonic(i8 addrspace(200)* addrspace(200)* %a) nounwind {
 ; RV32IXCHERI-LABEL: atomic_load_cap_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a1, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_load_cap
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomic_load_cap_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    clc ca0, 0(ca0)
+; RV32IAXCHERI-NEXT:    clc a0, 0(a0)
 ; RV32IAXCHERI-NEXT:    cret
   %1 = load atomic i8 addrspace(200)*, i8 addrspace(200)* addrspace(200)* %a monotonic, align 8
   ret i8 addrspace(200)* %1
@@ -45,17 +45,17 @@ define i8 addrspace(200)* @atomic_load_cap_monotonic(i8 addrspace(200)* addrspac
 define i8 addrspace(200)* @atomic_load_cap_acquire(i8 addrspace(200)* addrspace(200)* %a) nounwind {
 ; RV32IXCHERI-LABEL: atomic_load_cap_acquire:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a1, 2
 ; RV32IXCHERI-NEXT:    ccall __atomic_load_cap
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomic_load_cap_acquire:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    clc ca0, 0(ca0)
+; RV32IAXCHERI-NEXT:    clc a0, 0(a0)
 ; RV32IAXCHERI-NEXT:    fence r, rw
 ; RV32IAXCHERI-NEXT:    cret
   %1 = load atomic i8 addrspace(200)*, i8 addrspace(200)* addrspace(200)* %a acquire, align 8
@@ -65,18 +65,18 @@ define i8 addrspace(200)* @atomic_load_cap_acquire(i8 addrspace(200)* addrspace(
 define i8 addrspace(200)* @atomic_load_cap_seq_cst(i8 addrspace(200)* addrspace(200)* %a) nounwind {
 ; RV32IXCHERI-LABEL: atomic_load_cap_seq_cst:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a1, 5
 ; RV32IXCHERI-NEXT:    ccall __atomic_load_cap
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomic_load_cap_seq_cst:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:    fence rw, rw
-; RV32IAXCHERI-NEXT:    clc ca0, 0(ca0)
+; RV32IAXCHERI-NEXT:    clc a0, 0(a0)
 ; RV32IAXCHERI-NEXT:    fence r, rw
 ; RV32IAXCHERI-NEXT:    cret
   %1 = load atomic i8 addrspace(200)*, i8 addrspace(200)* addrspace(200)* %a seq_cst, align 8
@@ -86,17 +86,17 @@ define i8 addrspace(200)* @atomic_load_cap_seq_cst(i8 addrspace(200)* addrspace(
 define void @atomic_store_cap_unordered(i8 addrspace(200)* addrspace(200)* %a, i8 addrspace(200)* %b) nounwind {
 ; RV32IXCHERI-LABEL: atomic_store_cap_unordered:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_store_cap
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomic_store_cap_unordered:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    csc ca1, 0(ca0)
+; RV32IAXCHERI-NEXT:    csc a1, 0(a0)
 ; RV32IAXCHERI-NEXT:    cret
   store atomic i8 addrspace(200)* %b, i8 addrspace(200)* addrspace(200)* %a unordered, align 8
   ret void
@@ -105,17 +105,17 @@ define void @atomic_store_cap_unordered(i8 addrspace(200)* addrspace(200)* %a, i
 define void @atomic_store_cap_monotonic(i8 addrspace(200)* addrspace(200)* %a, i8 addrspace(200)* %b) nounwind {
 ; RV32IXCHERI-LABEL: atomic_store_cap_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_store_cap
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomic_store_cap_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    csc ca1, 0(ca0)
+; RV32IAXCHERI-NEXT:    csc a1, 0(a0)
 ; RV32IAXCHERI-NEXT:    cret
   store atomic i8 addrspace(200)* %b, i8 addrspace(200)* addrspace(200)* %a monotonic, align 8
   ret void
@@ -124,18 +124,18 @@ define void @atomic_store_cap_monotonic(i8 addrspace(200)* addrspace(200)* %a, i
 define void @atomic_store_cap_release(i8 addrspace(200)* addrspace(200)* %a, i8 addrspace(200)* %b) nounwind {
 ; RV32IXCHERI-LABEL: atomic_store_cap_release:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 3
 ; RV32IXCHERI-NEXT:    ccall __atomic_store_cap
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomic_store_cap_release:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:    fence rw, w
-; RV32IAXCHERI-NEXT:    csc ca1, 0(ca0)
+; RV32IAXCHERI-NEXT:    csc a1, 0(a0)
 ; RV32IAXCHERI-NEXT:    cret
   store atomic i8 addrspace(200)* %b, i8 addrspace(200)* addrspace(200)* %a release, align 8
   ret void
@@ -144,18 +144,18 @@ define void @atomic_store_cap_release(i8 addrspace(200)* addrspace(200)* %a, i8
 define void @atomic_store_cap_seq_cst(i8 addrspace(200)* addrspace(200)* %a, i8 addrspace(200)* %b) nounwind {
 ; RV32IXCHERI-LABEL: atomic_store_cap_seq_cst:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 5
 ; RV32IXCHERI-NEXT:    ccall __atomic_store_cap
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomic_store_cap_seq_cst:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:    fence rw, w
-; RV32IAXCHERI-NEXT:    csc ca1, 0(ca0)
+; RV32IAXCHERI-NEXT:    csc a1, 0(a0)
 ; RV32IAXCHERI-NEXT:    fence rw, rw
 ; RV32IAXCHERI-NEXT:    cret
   store atomic i8 addrspace(200)* %b, i8 addrspace(200)* addrspace(200)* %a seq_cst, align 8
diff --git a/llvm/test/CodeGen/RISCV/cheri/atomic-load-store64.ll b/llvm/test/CodeGen/RISCV/cheri/atomic-load-store64.ll
index 57ebb37722c27..4d3bf3778870c 100644
--- a/llvm/test/CodeGen/RISCV/cheri/atomic-load-store64.ll
+++ b/llvm/test/CodeGen/RISCV/cheri/atomic-load-store64.ll
@@ -11,32 +11,32 @@
 define i8 @atomic_load_i8_unordered(i8 addrspace(200)* %a) nounwind {
 ; RV32IXCHERI-LABEL: atomic_load_i8_unordered:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a1, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_load_1
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomic_load_i8_unordered:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    clb a0, 0(ca0)
+; RV32IAXCHERI-NEXT:    clb a0, 0(a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomic_load_i8_unordered:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a1, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_load_1
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomic_load_i8_unordered:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    clb a0, 0(ca0)
+; RV64IAXCHERI-NEXT:    clb a0, 0(a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = load atomic i8, i8 addrspace(200)* %a unordered, align 1
   ret i8 %1
@@ -45,32 +45,32 @@ define i8 @atomic_load_i8_unordered(i8 addrspace(200)* %a) nounwind {
 define i8 @atomic_load_i8_monotonic(i8 addrspace(200)* %a) nounwind {
 ; RV32IXCHERI-LABEL: atomic_load_i8_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a1, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_load_1
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomic_load_i8_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    clb a0, 0(ca0)
+; RV32IAXCHERI-NEXT:    clb a0, 0(a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomic_load_i8_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a1, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_load_1
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomic_load_i8_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    clb a0, 0(ca0)
+; RV64IAXCHERI-NEXT:    clb a0, 0(a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = load atomic i8, i8 addrspace(200)* %a monotonic, align 1
   ret i8 %1
@@ -79,33 +79,33 @@ define i8 @atomic_load_i8_monotonic(i8 addrspace(200)* %a) nounwind {
 define i8 @atomic_load_i8_acquire(i8 addrspace(200)* %a) nounwind {
 ; RV32IXCHERI-LABEL: atomic_load_i8_acquire:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a1, 2
 ; RV32IXCHERI-NEXT:    ccall __atomic_load_1
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomic_load_i8_acquire:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    clb a0, 0(ca0)
+; RV32IAXCHERI-NEXT:    clb a0, 0(a0)
 ; RV32IAXCHERI-NEXT:    fence r, rw
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomic_load_i8_acquire:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a1, 2
 ; RV64IXCHERI-NEXT:    ccall __atomic_load_1
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomic_load_i8_acquire:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    clb a0, 0(ca0)
+; RV64IAXCHERI-NEXT:    clb a0, 0(a0)
 ; RV64IAXCHERI-NEXT:    fence r, rw
 ; RV64IAXCHERI-NEXT:    cret
   %1 = load atomic i8, i8 addrspace(200)* %a acquire, align 1
@@ -115,35 +115,35 @@ define i8 @atomic_load_i8_acquire(i8 addrspace(200)* %a) nounwind {
 define i8 @atomic_load_i8_seq_cst(i8 addrspace(200)* %a) nounwind {
 ; RV32IXCHERI-LABEL: atomic_load_i8_seq_cst:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a1, 5
 ; RV32IXCHERI-NEXT:    ccall __atomic_load_1
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomic_load_i8_seq_cst:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:    fence rw, rw
-; RV32IAXCHERI-NEXT:    clb a0, 0(ca0)
+; RV32IAXCHERI-NEXT:    clb a0, 0(a0)
 ; RV32IAXCHERI-NEXT:    fence r, rw
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomic_load_i8_seq_cst:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a1, 5
 ; RV64IXCHERI-NEXT:    ccall __atomic_load_1
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomic_load_i8_seq_cst:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:    fence rw, rw
-; RV64IAXCHERI-NEXT:    clb a0, 0(ca0)
+; RV64IAXCHERI-NEXT:    clb a0, 0(a0)
 ; RV64IAXCHERI-NEXT:    fence r, rw
 ; RV64IAXCHERI-NEXT:    cret
   %1 = load atomic i8, i8 addrspace(200)* %a seq_cst, align 1
@@ -153,32 +153,32 @@ define i8 @atomic_load_i8_seq_cst(i8 addrspace(200)* %a) nounwind {
 define i16 @atomic_load_i16_unordered(i16 addrspace(200)* %a) nounwind {
 ; RV32IXCHERI-LABEL: atomic_load_i16_unordered:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a1, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_load_2
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomic_load_i16_unordered:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    clh a0, 0(ca0)
+; RV32IAXCHERI-NEXT:    clh a0, 0(a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomic_load_i16_unordered:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a1, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_load_2
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomic_load_i16_unordered:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    clh a0, 0(ca0)
+; RV64IAXCHERI-NEXT:    clh a0, 0(a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = load atomic i16, i16 addrspace(200)* %a unordered, align 2
   ret i16 %1
@@ -187,32 +187,32 @@ define i16 @atomic_load_i16_unordered(i16 addrspace(200)* %a) nounwind {
 define i16 @atomic_load_i16_monotonic(i16 addrspace(200)* %a) nounwind {
 ; RV32IXCHERI-LABEL: atomic_load_i16_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a1, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_load_2
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomic_load_i16_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    clh a0, 0(ca0)
+; RV32IAXCHERI-NEXT:    clh a0, 0(a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomic_load_i16_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a1, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_load_2
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomic_load_i16_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    clh a0, 0(ca0)
+; RV64IAXCHERI-NEXT:    clh a0, 0(a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = load atomic i16, i16 addrspace(200)* %a monotonic, align 2
   ret i16 %1
@@ -221,33 +221,33 @@ define i16 @atomic_load_i16_monotonic(i16 addrspace(200)* %a) nounwind {
 define i16 @atomic_load_i16_acquire(i16 addrspace(200)* %a) nounwind {
 ; RV32IXCHERI-LABEL: atomic_load_i16_acquire:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a1, 2
 ; RV32IXCHERI-NEXT:    ccall __atomic_load_2
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomic_load_i16_acquire:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    clh a0, 0(ca0)
+; RV32IAXCHERI-NEXT:    clh a0, 0(a0)
 ; RV32IAXCHERI-NEXT:    fence r, rw
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomic_load_i16_acquire:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a1, 2
 ; RV64IXCHERI-NEXT:    ccall __atomic_load_2
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomic_load_i16_acquire:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    clh a0, 0(ca0)
+; RV64IAXCHERI-NEXT:    clh a0, 0(a0)
 ; RV64IAXCHERI-NEXT:    fence r, rw
 ; RV64IAXCHERI-NEXT:    cret
   %1 = load atomic i16, i16 addrspace(200)* %a acquire, align 2
@@ -257,35 +257,35 @@ define i16 @atomic_load_i16_acquire(i16 addrspace(200)* %a) nounwind {
 define i16 @atomic_load_i16_seq_cst(i16 addrspace(200)* %a) nounwind {
 ; RV32IXCHERI-LABEL: atomic_load_i16_seq_cst:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a1, 5
 ; RV32IXCHERI-NEXT:    ccall __atomic_load_2
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomic_load_i16_seq_cst:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:    fence rw, rw
-; RV32IAXCHERI-NEXT:    clh a0, 0(ca0)
+; RV32IAXCHERI-NEXT:    clh a0, 0(a0)
 ; RV32IAXCHERI-NEXT:    fence r, rw
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomic_load_i16_seq_cst:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a1, 5
 ; RV64IXCHERI-NEXT:    ccall __atomic_load_2
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomic_load_i16_seq_cst:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:    fence rw, rw
-; RV64IAXCHERI-NEXT:    clh a0, 0(ca0)
+; RV64IAXCHERI-NEXT:    clh a0, 0(a0)
 ; RV64IAXCHERI-NEXT:    fence r, rw
 ; RV64IAXCHERI-NEXT:    cret
   %1 = load atomic i16, i16 addrspace(200)* %a seq_cst, align 2
@@ -295,32 +295,32 @@ define i16 @atomic_load_i16_seq_cst(i16 addrspace(200)* %a) nounwind {
 define i32 @atomic_load_i32_unordered(i32 addrspace(200)* %a) nounwind {
 ; RV32IXCHERI-LABEL: atomic_load_i32_unordered:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a1, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_load_4
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomic_load_i32_unordered:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    clw a0, 0(ca0)
+; RV32IAXCHERI-NEXT:    clw a0, 0(a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomic_load_i32_unordered:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a1, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_load_4
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomic_load_i32_unordered:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    clw a0, 0(ca0)
+; RV64IAXCHERI-NEXT:    clw a0, 0(a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = load atomic i32, i32 addrspace(200)* %a unordered, align 4
   ret i32 %1
@@ -329,32 +329,32 @@ define i32 @atomic_load_i32_unordered(i32 addrspace(200)* %a) nounwind {
 define i32 @atomic_load_i32_monotonic(i32 addrspace(200)* %a) nounwind {
 ; RV32IXCHERI-LABEL: atomic_load_i32_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a1, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_load_4
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomic_load_i32_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    clw a0, 0(ca0)
+; RV32IAXCHERI-NEXT:    clw a0, 0(a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomic_load_i32_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a1, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_load_4
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomic_load_i32_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    clw a0, 0(ca0)
+; RV64IAXCHERI-NEXT:    clw a0, 0(a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = load atomic i32, i32 addrspace(200)* %a monotonic, align 4
   ret i32 %1
@@ -363,33 +363,33 @@ define i32 @atomic_load_i32_monotonic(i32 addrspace(200)* %a) nounwind {
 define i32 @atomic_load_i32_acquire(i32 addrspace(200)* %a) nounwind {
 ; RV32IXCHERI-LABEL: atomic_load_i32_acquire:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a1, 2
 ; RV32IXCHERI-NEXT:    ccall __atomic_load_4
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomic_load_i32_acquire:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    clw a0, 0(ca0)
+; RV32IAXCHERI-NEXT:    clw a0, 0(a0)
 ; RV32IAXCHERI-NEXT:    fence r, rw
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomic_load_i32_acquire:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a1, 2
 ; RV64IXCHERI-NEXT:    ccall __atomic_load_4
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomic_load_i32_acquire:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    clw a0, 0(ca0)
+; RV64IAXCHERI-NEXT:    clw a0, 0(a0)
 ; RV64IAXCHERI-NEXT:    fence r, rw
 ; RV64IAXCHERI-NEXT:    cret
   %1 = load atomic i32, i32 addrspace(200)* %a acquire, align 4
@@ -399,35 +399,35 @@ define i32 @atomic_load_i32_acquire(i32 addrspace(200)* %a) nounwind {
 define i32 @atomic_load_i32_seq_cst(i32 addrspace(200)* %a) nounwind {
 ; RV32IXCHERI-LABEL: atomic_load_i32_seq_cst:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a1, 5
 ; RV32IXCHERI-NEXT:    ccall __atomic_load_4
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomic_load_i32_seq_cst:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:    fence rw, rw
-; RV32IAXCHERI-NEXT:    clw a0, 0(ca0)
+; RV32IAXCHERI-NEXT:    clw a0, 0(a0)
 ; RV32IAXCHERI-NEXT:    fence r, rw
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomic_load_i32_seq_cst:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a1, 5
 ; RV64IXCHERI-NEXT:    ccall __atomic_load_4
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomic_load_i32_seq_cst:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:    fence rw, rw
-; RV64IAXCHERI-NEXT:    clw a0, 0(ca0)
+; RV64IAXCHERI-NEXT:    clw a0, 0(a0)
 ; RV64IAXCHERI-NEXT:    fence r, rw
 ; RV64IAXCHERI-NEXT:    cret
   %1 = load atomic i32, i32 addrspace(200)* %a seq_cst, align 4
@@ -437,37 +437,37 @@ define i32 @atomic_load_i32_seq_cst(i32 addrspace(200)* %a) nounwind {
 define i64 @atomic_load_i64_unordered(i64 addrspace(200)* %a) nounwind {
 ; RV32IXCHERI-LABEL: atomic_load_i64_unordered:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a1, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_load_8
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomic_load_i64_unordered:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IAXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IAXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    li a1, 0
 ; RV32IAXCHERI-NEXT:    ccall __atomic_load_8
-; RV32IAXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IAXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomic_load_i64_unordered:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a1, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_load_8
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomic_load_i64_unordered:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    cld a0, 0(ca0)
+; RV64IAXCHERI-NEXT:    cld a0, 0(a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = load atomic i64, i64 addrspace(200)* %a unordered, align 8
   ret i64 %1
@@ -476,37 +476,37 @@ define i64 @atomic_load_i64_unordered(i64 addrspace(200)* %a) nounwind {
 define i64 @atomic_load_i64_monotonic(i64 addrspace(200)* %a) nounwind {
 ; RV32IXCHERI-LABEL: atomic_load_i64_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a1, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_load_8
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomic_load_i64_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IAXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IAXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    li a1, 0
 ; RV32IAXCHERI-NEXT:    ccall __atomic_load_8
-; RV32IAXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IAXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomic_load_i64_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a1, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_load_8
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomic_load_i64_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    cld a0, 0(ca0)
+; RV64IAXCHERI-NEXT:    cld a0, 0(a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = load atomic i64, i64 addrspace(200)* %a monotonic, align 8
   ret i64 %1
@@ -515,37 +515,37 @@ define i64 @atomic_load_i64_monotonic(i64 addrspace(200)* %a) nounwind {
 define i64 @atomic_load_i64_acquire(i64 addrspace(200)* %a) nounwind {
 ; RV32IXCHERI-LABEL: atomic_load_i64_acquire:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a1, 2
 ; RV32IXCHERI-NEXT:    ccall __atomic_load_8
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomic_load_i64_acquire:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IAXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IAXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    li a1, 2
 ; RV32IAXCHERI-NEXT:    ccall __atomic_load_8
-; RV32IAXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IAXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomic_load_i64_acquire:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a1, 2
 ; RV64IXCHERI-NEXT:    ccall __atomic_load_8
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomic_load_i64_acquire:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    cld a0, 0(ca0)
+; RV64IAXCHERI-NEXT:    cld a0, 0(a0)
 ; RV64IAXCHERI-NEXT:    fence r, rw
 ; RV64IAXCHERI-NEXT:    cret
   %1 = load atomic i64, i64 addrspace(200)* %a acquire, align 8
@@ -555,38 +555,38 @@ define i64 @atomic_load_i64_acquire(i64 addrspace(200)* %a) nounwind {
 define i64 @atomic_load_i64_seq_cst(i64 addrspace(200)* %a) nounwind {
 ; RV32IXCHERI-LABEL: atomic_load_i64_seq_cst:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a1, 5
 ; RV32IXCHERI-NEXT:    ccall __atomic_load_8
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomic_load_i64_seq_cst:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IAXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IAXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    li a1, 5
 ; RV32IAXCHERI-NEXT:    ccall __atomic_load_8
-; RV32IAXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IAXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomic_load_i64_seq_cst:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a1, 5
 ; RV64IXCHERI-NEXT:    ccall __atomic_load_8
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomic_load_i64_seq_cst:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:    fence rw, rw
-; RV64IAXCHERI-NEXT:    cld a0, 0(ca0)
+; RV64IAXCHERI-NEXT:    cld a0, 0(a0)
 ; RV64IAXCHERI-NEXT:    fence r, rw
 ; RV64IAXCHERI-NEXT:    cret
   %1 = load atomic i64, i64 addrspace(200)* %a seq_cst, align 8
@@ -596,32 +596,32 @@ define i64 @atomic_load_i64_seq_cst(i64 addrspace(200)* %a) nounwind {
 define void @atomic_store_i8_unordered(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomic_store_i8_unordered:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_store_1
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomic_store_i8_unordered:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    csb a1, 0(ca0)
+; RV32IAXCHERI-NEXT:    csb a1, 0(a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomic_store_i8_unordered:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_store_1
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomic_store_i8_unordered:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    csb a1, 0(ca0)
+; RV64IAXCHERI-NEXT:    csb a1, 0(a0)
 ; RV64IAXCHERI-NEXT:    cret
   store atomic i8 %b, i8 addrspace(200)* %a unordered, align 1
   ret void
@@ -630,32 +630,32 @@ define void @atomic_store_i8_unordered(i8 addrspace(200)* %a, i8 %b) nounwind {
 define void @atomic_store_i8_monotonic(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomic_store_i8_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_store_1
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomic_store_i8_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    csb a1, 0(ca0)
+; RV32IAXCHERI-NEXT:    csb a1, 0(a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomic_store_i8_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_store_1
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomic_store_i8_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    csb a1, 0(ca0)
+; RV64IAXCHERI-NEXT:    csb a1, 0(a0)
 ; RV64IAXCHERI-NEXT:    cret
   store atomic i8 %b, i8 addrspace(200)* %a monotonic, align 1
   ret void
@@ -664,34 +664,34 @@ define void @atomic_store_i8_monotonic(i8 addrspace(200)* %a, i8 %b) nounwind {
 define void @atomic_store_i8_release(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomic_store_i8_release:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 3
 ; RV32IXCHERI-NEXT:    ccall __atomic_store_1
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomic_store_i8_release:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:    fence rw, w
-; RV32IAXCHERI-NEXT:    csb a1, 0(ca0)
+; RV32IAXCHERI-NEXT:    csb a1, 0(a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomic_store_i8_release:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 3
 ; RV64IXCHERI-NEXT:    ccall __atomic_store_1
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomic_store_i8_release:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:    fence rw, w
-; RV64IAXCHERI-NEXT:    csb a1, 0(ca0)
+; RV64IAXCHERI-NEXT:    csb a1, 0(a0)
 ; RV64IAXCHERI-NEXT:    cret
   store atomic i8 %b, i8 addrspace(200)* %a release, align 1
   ret void
@@ -700,35 +700,35 @@ define void @atomic_store_i8_release(i8 addrspace(200)* %a, i8 %b) nounwind {
 define void @atomic_store_i8_seq_cst(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomic_store_i8_seq_cst:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 5
 ; RV32IXCHERI-NEXT:    ccall __atomic_store_1
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomic_store_i8_seq_cst:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:    fence rw, w
-; RV32IAXCHERI-NEXT:    csb a1, 0(ca0)
+; RV32IAXCHERI-NEXT:    csb a1, 0(a0)
 ; RV32IAXCHERI-NEXT:    fence rw, rw
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomic_store_i8_seq_cst:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 5
 ; RV64IXCHERI-NEXT:    ccall __atomic_store_1
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomic_store_i8_seq_cst:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:    fence rw, w
-; RV64IAXCHERI-NEXT:    csb a1, 0(ca0)
+; RV64IAXCHERI-NEXT:    csb a1, 0(a0)
 ; RV64IAXCHERI-NEXT:    fence rw, rw
 ; RV64IAXCHERI-NEXT:    cret
   store atomic i8 %b, i8 addrspace(200)* %a seq_cst, align 1
@@ -738,32 +738,32 @@ define void @atomic_store_i8_seq_cst(i8 addrspace(200)* %a, i8 %b) nounwind {
 define void @atomic_store_i16_unordered(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomic_store_i16_unordered:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_store_2
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomic_store_i16_unordered:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    csh a1, 0(ca0)
+; RV32IAXCHERI-NEXT:    csh a1, 0(a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomic_store_i16_unordered:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_store_2
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomic_store_i16_unordered:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    csh a1, 0(ca0)
+; RV64IAXCHERI-NEXT:    csh a1, 0(a0)
 ; RV64IAXCHERI-NEXT:    cret
   store atomic i16 %b, i16 addrspace(200)* %a unordered, align 2
   ret void
@@ -772,32 +772,32 @@ define void @atomic_store_i16_unordered(i16 addrspace(200)* %a, i16 %b) nounwind
 define void @atomic_store_i16_monotonic(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomic_store_i16_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_store_2
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomic_store_i16_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    csh a1, 0(ca0)
+; RV32IAXCHERI-NEXT:    csh a1, 0(a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomic_store_i16_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_store_2
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomic_store_i16_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    csh a1, 0(ca0)
+; RV64IAXCHERI-NEXT:    csh a1, 0(a0)
 ; RV64IAXCHERI-NEXT:    cret
   store atomic i16 %b, i16 addrspace(200)* %a monotonic, align 2
   ret void
@@ -806,34 +806,34 @@ define void @atomic_store_i16_monotonic(i16 addrspace(200)* %a, i16 %b) nounwind
 define void @atomic_store_i16_release(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomic_store_i16_release:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 3
 ; RV32IXCHERI-NEXT:    ccall __atomic_store_2
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomic_store_i16_release:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:    fence rw, w
-; RV32IAXCHERI-NEXT:    csh a1, 0(ca0)
+; RV32IAXCHERI-NEXT:    csh a1, 0(a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomic_store_i16_release:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 3
 ; RV64IXCHERI-NEXT:    ccall __atomic_store_2
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomic_store_i16_release:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:    fence rw, w
-; RV64IAXCHERI-NEXT:    csh a1, 0(ca0)
+; RV64IAXCHERI-NEXT:    csh a1, 0(a0)
 ; RV64IAXCHERI-NEXT:    cret
   store atomic i16 %b, i16 addrspace(200)* %a release, align 2
   ret void
@@ -842,35 +842,35 @@ define void @atomic_store_i16_release(i16 addrspace(200)* %a, i16 %b) nounwind {
 define void @atomic_store_i16_seq_cst(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomic_store_i16_seq_cst:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 5
 ; RV32IXCHERI-NEXT:    ccall __atomic_store_2
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomic_store_i16_seq_cst:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:    fence rw, w
-; RV32IAXCHERI-NEXT:    csh a1, 0(ca0)
+; RV32IAXCHERI-NEXT:    csh a1, 0(a0)
 ; RV32IAXCHERI-NEXT:    fence rw, rw
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomic_store_i16_seq_cst:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 5
 ; RV64IXCHERI-NEXT:    ccall __atomic_store_2
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomic_store_i16_seq_cst:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:    fence rw, w
-; RV64IAXCHERI-NEXT:    csh a1, 0(ca0)
+; RV64IAXCHERI-NEXT:    csh a1, 0(a0)
 ; RV64IAXCHERI-NEXT:    fence rw, rw
 ; RV64IAXCHERI-NEXT:    cret
   store atomic i16 %b, i16 addrspace(200)* %a seq_cst, align 2
@@ -880,32 +880,32 @@ define void @atomic_store_i16_seq_cst(i16 addrspace(200)* %a, i16 %b) nounwind {
 define void @atomic_store_i32_unordered(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomic_store_i32_unordered:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_store_4
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomic_store_i32_unordered:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    csw a1, 0(ca0)
+; RV32IAXCHERI-NEXT:    csw a1, 0(a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomic_store_i32_unordered:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_store_4
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomic_store_i32_unordered:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    csw a1, 0(ca0)
+; RV64IAXCHERI-NEXT:    csw a1, 0(a0)
 ; RV64IAXCHERI-NEXT:    cret
   store atomic i32 %b, i32 addrspace(200)* %a unordered, align 4
   ret void
@@ -914,32 +914,32 @@ define void @atomic_store_i32_unordered(i32 addrspace(200)* %a, i32 %b) nounwind
 define void @atomic_store_i32_monotonic(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomic_store_i32_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_store_4
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomic_store_i32_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    csw a1, 0(ca0)
+; RV32IAXCHERI-NEXT:    csw a1, 0(a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomic_store_i32_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_store_4
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomic_store_i32_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    csw a1, 0(ca0)
+; RV64IAXCHERI-NEXT:    csw a1, 0(a0)
 ; RV64IAXCHERI-NEXT:    cret
   store atomic i32 %b, i32 addrspace(200)* %a monotonic, align 4
   ret void
@@ -948,34 +948,34 @@ define void @atomic_store_i32_monotonic(i32 addrspace(200)* %a, i32 %b) nounwind
 define void @atomic_store_i32_release(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomic_store_i32_release:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 3
 ; RV32IXCHERI-NEXT:    ccall __atomic_store_4
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomic_store_i32_release:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:    fence rw, w
-; RV32IAXCHERI-NEXT:    csw a1, 0(ca0)
+; RV32IAXCHERI-NEXT:    csw a1, 0(a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomic_store_i32_release:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 3
 ; RV64IXCHERI-NEXT:    ccall __atomic_store_4
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomic_store_i32_release:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:    fence rw, w
-; RV64IAXCHERI-NEXT:    csw a1, 0(ca0)
+; RV64IAXCHERI-NEXT:    csw a1, 0(a0)
 ; RV64IAXCHERI-NEXT:    cret
   store atomic i32 %b, i32 addrspace(200)* %a release, align 4
   ret void
@@ -984,35 +984,35 @@ define void @atomic_store_i32_release(i32 addrspace(200)* %a, i32 %b) nounwind {
 define void @atomic_store_i32_seq_cst(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomic_store_i32_seq_cst:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 5
 ; RV32IXCHERI-NEXT:    ccall __atomic_store_4
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomic_store_i32_seq_cst:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:    fence rw, w
-; RV32IAXCHERI-NEXT:    csw a1, 0(ca0)
+; RV32IAXCHERI-NEXT:    csw a1, 0(a0)
 ; RV32IAXCHERI-NEXT:    fence rw, rw
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomic_store_i32_seq_cst:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 5
 ; RV64IXCHERI-NEXT:    ccall __atomic_store_4
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomic_store_i32_seq_cst:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:    fence rw, w
-; RV64IAXCHERI-NEXT:    csw a1, 0(ca0)
+; RV64IAXCHERI-NEXT:    csw a1, 0(a0)
 ; RV64IAXCHERI-NEXT:    fence rw, rw
 ; RV64IAXCHERI-NEXT:    cret
   store atomic i32 %b, i32 addrspace(200)* %a seq_cst, align 4
@@ -1022,37 +1022,37 @@ define void @atomic_store_i32_seq_cst(i32 addrspace(200)* %a, i32 %b) nounwind {
 define void @atomic_store_i64_unordered(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomic_store_i64_unordered:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a3, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_store_8
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomic_store_i64_unordered:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IAXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IAXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    li a3, 0
 ; RV32IAXCHERI-NEXT:    ccall __atomic_store_8
-; RV32IAXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IAXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomic_store_i64_unordered:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_store_8
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomic_store_i64_unordered:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    csd a1, 0(ca0)
+; RV64IAXCHERI-NEXT:    csd a1, 0(a0)
 ; RV64IAXCHERI-NEXT:    cret
   store atomic i64 %b, i64 addrspace(200)* %a unordered, align 8
   ret void
@@ -1061,37 +1061,37 @@ define void @atomic_store_i64_unordered(i64 addrspace(200)* %a, i64 %b) nounwind
 define void @atomic_store_i64_monotonic(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomic_store_i64_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a3, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_store_8
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomic_store_i64_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IAXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IAXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    li a3, 0
 ; RV32IAXCHERI-NEXT:    ccall __atomic_store_8
-; RV32IAXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IAXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomic_store_i64_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_store_8
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomic_store_i64_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    csd a1, 0(ca0)
+; RV64IAXCHERI-NEXT:    csd a1, 0(a0)
 ; RV64IAXCHERI-NEXT:    cret
   store atomic i64 %b, i64 addrspace(200)* %a monotonic, align 8
   ret void
@@ -1100,38 +1100,38 @@ define void @atomic_store_i64_monotonic(i64 addrspace(200)* %a, i64 %b) nounwind
 define void @atomic_store_i64_release(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomic_store_i64_release:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a3, 3
 ; RV32IXCHERI-NEXT:    ccall __atomic_store_8
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomic_store_i64_release:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IAXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IAXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    li a3, 3
 ; RV32IAXCHERI-NEXT:    ccall __atomic_store_8
-; RV32IAXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IAXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomic_store_i64_release:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 3
 ; RV64IXCHERI-NEXT:    ccall __atomic_store_8
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomic_store_i64_release:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:    fence rw, w
-; RV64IAXCHERI-NEXT:    csd a1, 0(ca0)
+; RV64IAXCHERI-NEXT:    csd a1, 0(a0)
 ; RV64IAXCHERI-NEXT:    cret
   store atomic i64 %b, i64 addrspace(200)* %a release, align 8
   ret void
@@ -1140,38 +1140,38 @@ define void @atomic_store_i64_release(i64 addrspace(200)* %a, i64 %b) nounwind {
 define void @atomic_store_i64_seq_cst(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomic_store_i64_seq_cst:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a3, 5
 ; RV32IXCHERI-NEXT:    ccall __atomic_store_8
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomic_store_i64_seq_cst:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IAXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IAXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    li a3, 5
 ; RV32IAXCHERI-NEXT:    ccall __atomic_store_8
-; RV32IAXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IAXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomic_store_i64_seq_cst:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 5
 ; RV64IXCHERI-NEXT:    ccall __atomic_store_8
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomic_store_i64_seq_cst:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:    fence rw, w
-; RV64IAXCHERI-NEXT:    csd a1, 0(ca0)
+; RV64IAXCHERI-NEXT:    csd a1, 0(a0)
 ; RV64IAXCHERI-NEXT:    fence rw, rw
 ; RV64IAXCHERI-NEXT:    cret
   store atomic i64 %b, i64 addrspace(200)* %a seq_cst, align 8
diff --git a/llvm/test/CodeGen/RISCV/cheri/atomic-rmw-hybrid.ll b/llvm/test/CodeGen/RISCV/cheri/atomic-rmw-hybrid.ll
index 8d6ad3fdd1ecc..db68349213cb2 100644
--- a/llvm/test/CodeGen/RISCV/cheri/atomic-rmw-hybrid.ll
+++ b/llvm/test/CodeGen/RISCV/cheri/atomic-rmw-hybrid.ll
@@ -21,7 +21,7 @@ define i8 addrspace(200)* @atomicrmw_xchg_cap_monotonic(i8 addrspace(200)** %a,
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_xchg_cap_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    amoswap.c ca0, ca1, (a0)
+; RV32IAXCHERI-NEXT:    amoswap.c a0, a1, (a0)
 ; RV32IAXCHERI-NEXT:    ret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_xchg_cap_monotonic:
@@ -36,7 +36,7 @@ define i8 addrspace(200)* @atomicrmw_xchg_cap_monotonic(i8 addrspace(200)** %a,
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_xchg_cap_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    amoswap.c ca0, ca1, (a0)
+; RV64IAXCHERI-NEXT:    amoswap.c a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    ret
   %1 = atomicrmw xchg i8 addrspace(200)** %a, i8 addrspace(200)* %b monotonic
   ret i8 addrspace(200)* %1
@@ -55,7 +55,7 @@ define i8 addrspace(200)* @atomicrmw_xchg_cap_acquire(i8 addrspace(200)** %a, i8
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_xchg_cap_acquire:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    amoswap.c.aq ca0, ca1, (a0)
+; RV32IAXCHERI-NEXT:    amoswap.c.aq a0, a1, (a0)
 ; RV32IAXCHERI-NEXT:    ret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_xchg_cap_acquire:
@@ -70,7 +70,7 @@ define i8 addrspace(200)* @atomicrmw_xchg_cap_acquire(i8 addrspace(200)** %a, i8
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_xchg_cap_acquire:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    amoswap.c.aq ca0, ca1, (a0)
+; RV64IAXCHERI-NEXT:    amoswap.c.aq a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    ret
   %1 = atomicrmw xchg i8 addrspace(200)** %a, i8 addrspace(200)* %b acquire
   ret i8 addrspace(200)* %1
@@ -89,7 +89,7 @@ define i8 addrspace(200)* @atomicrmw_xchg_cap_release(i8 addrspace(200)** %a, i8
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_xchg_cap_release:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    amoswap.c.rl ca0, ca1, (a0)
+; RV32IAXCHERI-NEXT:    amoswap.c.rl a0, a1, (a0)
 ; RV32IAXCHERI-NEXT:    ret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_xchg_cap_release:
@@ -104,7 +104,7 @@ define i8 addrspace(200)* @atomicrmw_xchg_cap_release(i8 addrspace(200)** %a, i8
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_xchg_cap_release:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    amoswap.c.rl ca0, ca1, (a0)
+; RV64IAXCHERI-NEXT:    amoswap.c.rl a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    ret
   %1 = atomicrmw xchg i8 addrspace(200)** %a, i8 addrspace(200)* %b release
   ret i8 addrspace(200)* %1
@@ -123,7 +123,7 @@ define i8 addrspace(200)* @atomicrmw_xchg_cap_acq_rel(i8 addrspace(200)** %a, i8
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_xchg_cap_acq_rel:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    amoswap.c.aqrl ca0, ca1, (a0)
+; RV32IAXCHERI-NEXT:    amoswap.c.aqrl a0, a1, (a0)
 ; RV32IAXCHERI-NEXT:    ret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_xchg_cap_acq_rel:
@@ -138,7 +138,7 @@ define i8 addrspace(200)* @atomicrmw_xchg_cap_acq_rel(i8 addrspace(200)** %a, i8
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_xchg_cap_acq_rel:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    amoswap.c.aqrl ca0, ca1, (a0)
+; RV64IAXCHERI-NEXT:    amoswap.c.aqrl a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    ret
   %1 = atomicrmw xchg i8 addrspace(200)** %a, i8 addrspace(200)* %b acq_rel
   ret i8 addrspace(200)* %1
@@ -157,7 +157,7 @@ define i8 addrspace(200)* @atomicrmw_xchg_cap_seq_cst(i8 addrspace(200)** %a, i8
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_xchg_cap_seq_cst:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    amoswap.c.aqrl ca0, ca1, (a0)
+; RV32IAXCHERI-NEXT:    amoswap.c.aqrl a0, a1, (a0)
 ; RV32IAXCHERI-NEXT:    ret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_xchg_cap_seq_cst:
@@ -172,7 +172,7 @@ define i8 addrspace(200)* @atomicrmw_xchg_cap_seq_cst(i8 addrspace(200)** %a, i8
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_xchg_cap_seq_cst:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    amoswap.c.aqrl ca0, ca1, (a0)
+; RV64IAXCHERI-NEXT:    amoswap.c.aqrl a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    ret
   %1 = atomicrmw xchg i8 addrspace(200)** %a, i8 addrspace(200)* %b seq_cst
   ret i8 addrspace(200)* %1
diff --git a/llvm/test/CodeGen/RISCV/cheri/atomic-rmw.ll b/llvm/test/CodeGen/RISCV/cheri/atomic-rmw.ll
index 3f74e85c2aa10..49a02d5843a5f 100644
--- a/llvm/test/CodeGen/RISCV/cheri/atomic-rmw.ll
+++ b/llvm/test/CodeGen/RISCV/cheri/atomic-rmw.ll
@@ -11,20 +11,20 @@
 define i8 @atomicrmw_xchg_i8_monotonic(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_xchg_i8_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_exchange_1
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_xchg_i8_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB0_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.b a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.b a2, (a0)
 ; RV32IAXCHERI-NEXT:    add a3, zero, a1
-; RV32IAXCHERI-NEXT:    csc.b a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.b a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB0_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -32,20 +32,20 @@ define i8 @atomicrmw_xchg_i8_monotonic(i8 addrspace(200)* %a, i8 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_xchg_i8_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_exchange_1
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_xchg_i8_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB0_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.b a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.b a2, (a0)
 ; RV64IAXCHERI-NEXT:    add a3, zero, a1
-; RV64IAXCHERI-NEXT:    csc.b a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.b a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB0_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -57,20 +57,20 @@ define i8 @atomicrmw_xchg_i8_monotonic(i8 addrspace(200)* %a, i8 %b) nounwind {
 define i8 @atomicrmw_xchg_i8_acquire(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_xchg_i8_acquire:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 2
 ; RV32IXCHERI-NEXT:    ccall __atomic_exchange_1
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_xchg_i8_acquire:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB1_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.b.aq a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.b.aq a2, (a0)
 ; RV32IAXCHERI-NEXT:    add a3, zero, a1
-; RV32IAXCHERI-NEXT:    csc.b a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.b a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB1_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -78,20 +78,20 @@ define i8 @atomicrmw_xchg_i8_acquire(i8 addrspace(200)* %a, i8 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_xchg_i8_acquire:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 2
 ; RV64IXCHERI-NEXT:    ccall __atomic_exchange_1
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_xchg_i8_acquire:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB1_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.b.aq a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.b.aq a2, (a0)
 ; RV64IAXCHERI-NEXT:    add a3, zero, a1
-; RV64IAXCHERI-NEXT:    csc.b a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.b a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB1_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -103,20 +103,20 @@ define i8 @atomicrmw_xchg_i8_acquire(i8 addrspace(200)* %a, i8 %b) nounwind {
 define i8 @atomicrmw_xchg_i8_release(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_xchg_i8_release:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 3
 ; RV32IXCHERI-NEXT:    ccall __atomic_exchange_1
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_xchg_i8_release:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB2_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.b a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.b a2, (a0)
 ; RV32IAXCHERI-NEXT:    add a3, zero, a1
-; RV32IAXCHERI-NEXT:    csc.b.rl a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.b.rl a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB2_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -124,20 +124,20 @@ define i8 @atomicrmw_xchg_i8_release(i8 addrspace(200)* %a, i8 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_xchg_i8_release:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 3
 ; RV64IXCHERI-NEXT:    ccall __atomic_exchange_1
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_xchg_i8_release:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB2_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.b a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.b a2, (a0)
 ; RV64IAXCHERI-NEXT:    add a3, zero, a1
-; RV64IAXCHERI-NEXT:    csc.b.rl a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.b.rl a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB2_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -149,20 +149,20 @@ define i8 @atomicrmw_xchg_i8_release(i8 addrspace(200)* %a, i8 %b) nounwind {
 define i8 @atomicrmw_xchg_i8_acq_rel(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_xchg_i8_acq_rel:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 4
 ; RV32IXCHERI-NEXT:    ccall __atomic_exchange_1
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_xchg_i8_acq_rel:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB3_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.b.aq a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.b.aq a2, (a0)
 ; RV32IAXCHERI-NEXT:    add a3, zero, a1
-; RV32IAXCHERI-NEXT:    csc.b.rl a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.b.rl a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB3_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -170,20 +170,20 @@ define i8 @atomicrmw_xchg_i8_acq_rel(i8 addrspace(200)* %a, i8 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_xchg_i8_acq_rel:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 4
 ; RV64IXCHERI-NEXT:    ccall __atomic_exchange_1
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_xchg_i8_acq_rel:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB3_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.b.aq a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.b.aq a2, (a0)
 ; RV64IAXCHERI-NEXT:    add a3, zero, a1
-; RV64IAXCHERI-NEXT:    csc.b.rl a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.b.rl a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB3_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -195,20 +195,20 @@ define i8 @atomicrmw_xchg_i8_acq_rel(i8 addrspace(200)* %a, i8 %b) nounwind {
 define i8 @atomicrmw_xchg_i8_seq_cst(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_xchg_i8_seq_cst:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 5
 ; RV32IXCHERI-NEXT:    ccall __atomic_exchange_1
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_xchg_i8_seq_cst:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB4_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.b.aqrl a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.b.aqrl a2, (a0)
 ; RV32IAXCHERI-NEXT:    add a3, zero, a1
-; RV32IAXCHERI-NEXT:    csc.b.aqrl a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.b.aqrl a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB4_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -216,20 +216,20 @@ define i8 @atomicrmw_xchg_i8_seq_cst(i8 addrspace(200)* %a, i8 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_xchg_i8_seq_cst:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 5
 ; RV64IXCHERI-NEXT:    ccall __atomic_exchange_1
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_xchg_i8_seq_cst:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB4_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.b.aqrl a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.b.aqrl a2, (a0)
 ; RV64IAXCHERI-NEXT:    add a3, zero, a1
-; RV64IAXCHERI-NEXT:    csc.b.aqrl a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.b.aqrl a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB4_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -241,20 +241,20 @@ define i8 @atomicrmw_xchg_i8_seq_cst(i8 addrspace(200)* %a, i8 %b) nounwind {
 define i8 @atomicrmw_add_i8_monotonic(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_add_i8_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_add_1
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_add_i8_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB5_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.b a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.b a2, (a0)
 ; RV32IAXCHERI-NEXT:    add a3, a2, a1
-; RV32IAXCHERI-NEXT:    csc.b a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.b a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB5_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -262,20 +262,20 @@ define i8 @atomicrmw_add_i8_monotonic(i8 addrspace(200)* %a, i8 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_add_i8_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_add_1
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_add_i8_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB5_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.b a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.b a2, (a0)
 ; RV64IAXCHERI-NEXT:    add a3, a2, a1
-; RV64IAXCHERI-NEXT:    csc.b a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.b a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB5_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -287,20 +287,20 @@ define i8 @atomicrmw_add_i8_monotonic(i8 addrspace(200)* %a, i8 %b) nounwind {
 define i8 @atomicrmw_add_i8_acquire(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_add_i8_acquire:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 2
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_add_1
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_add_i8_acquire:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB6_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.b.aq a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.b.aq a2, (a0)
 ; RV32IAXCHERI-NEXT:    add a3, a2, a1
-; RV32IAXCHERI-NEXT:    csc.b a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.b a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB6_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -308,20 +308,20 @@ define i8 @atomicrmw_add_i8_acquire(i8 addrspace(200)* %a, i8 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_add_i8_acquire:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 2
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_add_1
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_add_i8_acquire:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB6_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.b.aq a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.b.aq a2, (a0)
 ; RV64IAXCHERI-NEXT:    add a3, a2, a1
-; RV64IAXCHERI-NEXT:    csc.b a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.b a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB6_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -333,20 +333,20 @@ define i8 @atomicrmw_add_i8_acquire(i8 addrspace(200)* %a, i8 %b) nounwind {
 define i8 @atomicrmw_add_i8_release(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_add_i8_release:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 3
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_add_1
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_add_i8_release:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB7_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.b a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.b a2, (a0)
 ; RV32IAXCHERI-NEXT:    add a3, a2, a1
-; RV32IAXCHERI-NEXT:    csc.b.rl a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.b.rl a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB7_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -354,20 +354,20 @@ define i8 @atomicrmw_add_i8_release(i8 addrspace(200)* %a, i8 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_add_i8_release:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 3
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_add_1
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_add_i8_release:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB7_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.b a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.b a2, (a0)
 ; RV64IAXCHERI-NEXT:    add a3, a2, a1
-; RV64IAXCHERI-NEXT:    csc.b.rl a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.b.rl a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB7_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -379,20 +379,20 @@ define i8 @atomicrmw_add_i8_release(i8 addrspace(200)* %a, i8 %b) nounwind {
 define i8 @atomicrmw_add_i8_acq_rel(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_add_i8_acq_rel:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 4
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_add_1
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_add_i8_acq_rel:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB8_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.b.aq a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.b.aq a2, (a0)
 ; RV32IAXCHERI-NEXT:    add a3, a2, a1
-; RV32IAXCHERI-NEXT:    csc.b.rl a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.b.rl a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB8_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -400,20 +400,20 @@ define i8 @atomicrmw_add_i8_acq_rel(i8 addrspace(200)* %a, i8 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_add_i8_acq_rel:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 4
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_add_1
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_add_i8_acq_rel:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB8_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.b.aq a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.b.aq a2, (a0)
 ; RV64IAXCHERI-NEXT:    add a3, a2, a1
-; RV64IAXCHERI-NEXT:    csc.b.rl a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.b.rl a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB8_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -425,20 +425,20 @@ define i8 @atomicrmw_add_i8_acq_rel(i8 addrspace(200)* %a, i8 %b) nounwind {
 define i8 @atomicrmw_add_i8_seq_cst(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_add_i8_seq_cst:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 5
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_add_1
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_add_i8_seq_cst:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB9_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.b.aqrl a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.b.aqrl a2, (a0)
 ; RV32IAXCHERI-NEXT:    add a3, a2, a1
-; RV32IAXCHERI-NEXT:    csc.b.aqrl a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.b.aqrl a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB9_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -446,20 +446,20 @@ define i8 @atomicrmw_add_i8_seq_cst(i8 addrspace(200)* %a, i8 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_add_i8_seq_cst:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 5
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_add_1
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_add_i8_seq_cst:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB9_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.b.aqrl a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.b.aqrl a2, (a0)
 ; RV64IAXCHERI-NEXT:    add a3, a2, a1
-; RV64IAXCHERI-NEXT:    csc.b.aqrl a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.b.aqrl a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB9_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -471,21 +471,21 @@ define i8 @atomicrmw_add_i8_seq_cst(i8 addrspace(200)* %a, i8 %b) nounwind {
 define i8 @atomicrmw_sub_i8_monotonic(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_sub_i8_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_sub_1
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_sub_i8_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:    neg a2, a1
 ; RV32IAXCHERI-NEXT:  .LBB10_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.b a1, (ca0)
+; RV32IAXCHERI-NEXT:    clr.b a1, (a0)
 ; RV32IAXCHERI-NEXT:    add a3, a1, a2
-; RV32IAXCHERI-NEXT:    csc.b a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.b a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB10_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a1
@@ -493,21 +493,21 @@ define i8 @atomicrmw_sub_i8_monotonic(i8 addrspace(200)* %a, i8 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_sub_i8_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_sub_1
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_sub_i8_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:    neg a2, a1
 ; RV64IAXCHERI-NEXT:  .LBB10_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.b a1, (ca0)
+; RV64IAXCHERI-NEXT:    clr.b a1, (a0)
 ; RV64IAXCHERI-NEXT:    add a3, a1, a2
-; RV64IAXCHERI-NEXT:    csc.b a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.b a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB10_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a1
@@ -519,21 +519,21 @@ define i8 @atomicrmw_sub_i8_monotonic(i8 addrspace(200)* %a, i8 %b) nounwind {
 define i8 @atomicrmw_sub_i8_acquire(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_sub_i8_acquire:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 2
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_sub_1
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_sub_i8_acquire:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:    neg a2, a1
 ; RV32IAXCHERI-NEXT:  .LBB11_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.b.aq a1, (ca0)
+; RV32IAXCHERI-NEXT:    clr.b.aq a1, (a0)
 ; RV32IAXCHERI-NEXT:    add a3, a1, a2
-; RV32IAXCHERI-NEXT:    csc.b a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.b a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB11_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a1
@@ -541,21 +541,21 @@ define i8 @atomicrmw_sub_i8_acquire(i8 addrspace(200)* %a, i8 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_sub_i8_acquire:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 2
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_sub_1
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_sub_i8_acquire:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:    neg a2, a1
 ; RV64IAXCHERI-NEXT:  .LBB11_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.b.aq a1, (ca0)
+; RV64IAXCHERI-NEXT:    clr.b.aq a1, (a0)
 ; RV64IAXCHERI-NEXT:    add a3, a1, a2
-; RV64IAXCHERI-NEXT:    csc.b a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.b a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB11_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a1
@@ -567,21 +567,21 @@ define i8 @atomicrmw_sub_i8_acquire(i8 addrspace(200)* %a, i8 %b) nounwind {
 define i8 @atomicrmw_sub_i8_release(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_sub_i8_release:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 3
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_sub_1
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_sub_i8_release:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:    neg a2, a1
 ; RV32IAXCHERI-NEXT:  .LBB12_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.b a1, (ca0)
+; RV32IAXCHERI-NEXT:    clr.b a1, (a0)
 ; RV32IAXCHERI-NEXT:    add a3, a1, a2
-; RV32IAXCHERI-NEXT:    csc.b.rl a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.b.rl a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB12_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a1
@@ -589,21 +589,21 @@ define i8 @atomicrmw_sub_i8_release(i8 addrspace(200)* %a, i8 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_sub_i8_release:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 3
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_sub_1
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_sub_i8_release:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:    neg a2, a1
 ; RV64IAXCHERI-NEXT:  .LBB12_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.b a1, (ca0)
+; RV64IAXCHERI-NEXT:    clr.b a1, (a0)
 ; RV64IAXCHERI-NEXT:    add a3, a1, a2
-; RV64IAXCHERI-NEXT:    csc.b.rl a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.b.rl a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB12_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a1
@@ -615,21 +615,21 @@ define i8 @atomicrmw_sub_i8_release(i8 addrspace(200)* %a, i8 %b) nounwind {
 define i8 @atomicrmw_sub_i8_acq_rel(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_sub_i8_acq_rel:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 4
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_sub_1
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_sub_i8_acq_rel:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:    neg a2, a1
 ; RV32IAXCHERI-NEXT:  .LBB13_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.b.aq a1, (ca0)
+; RV32IAXCHERI-NEXT:    clr.b.aq a1, (a0)
 ; RV32IAXCHERI-NEXT:    add a3, a1, a2
-; RV32IAXCHERI-NEXT:    csc.b.rl a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.b.rl a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB13_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a1
@@ -637,21 +637,21 @@ define i8 @atomicrmw_sub_i8_acq_rel(i8 addrspace(200)* %a, i8 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_sub_i8_acq_rel:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 4
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_sub_1
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_sub_i8_acq_rel:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:    neg a2, a1
 ; RV64IAXCHERI-NEXT:  .LBB13_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.b.aq a1, (ca0)
+; RV64IAXCHERI-NEXT:    clr.b.aq a1, (a0)
 ; RV64IAXCHERI-NEXT:    add a3, a1, a2
-; RV64IAXCHERI-NEXT:    csc.b.rl a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.b.rl a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB13_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a1
@@ -663,21 +663,21 @@ define i8 @atomicrmw_sub_i8_acq_rel(i8 addrspace(200)* %a, i8 %b) nounwind {
 define i8 @atomicrmw_sub_i8_seq_cst(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_sub_i8_seq_cst:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 5
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_sub_1
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_sub_i8_seq_cst:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:    neg a2, a1
 ; RV32IAXCHERI-NEXT:  .LBB14_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.b.aqrl a1, (ca0)
+; RV32IAXCHERI-NEXT:    clr.b.aqrl a1, (a0)
 ; RV32IAXCHERI-NEXT:    add a3, a1, a2
-; RV32IAXCHERI-NEXT:    csc.b.aqrl a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.b.aqrl a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB14_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a1
@@ -685,21 +685,21 @@ define i8 @atomicrmw_sub_i8_seq_cst(i8 addrspace(200)* %a, i8 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_sub_i8_seq_cst:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 5
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_sub_1
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_sub_i8_seq_cst:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:    neg a2, a1
 ; RV64IAXCHERI-NEXT:  .LBB14_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.b.aqrl a1, (ca0)
+; RV64IAXCHERI-NEXT:    clr.b.aqrl a1, (a0)
 ; RV64IAXCHERI-NEXT:    add a3, a1, a2
-; RV64IAXCHERI-NEXT:    csc.b.aqrl a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.b.aqrl a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB14_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a1
@@ -711,20 +711,20 @@ define i8 @atomicrmw_sub_i8_seq_cst(i8 addrspace(200)* %a, i8 %b) nounwind {
 define i8 @atomicrmw_and_i8_monotonic(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_and_i8_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_and_1
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_and_i8_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB15_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.b a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.b a2, (a0)
 ; RV32IAXCHERI-NEXT:    and a3, a2, a1
-; RV32IAXCHERI-NEXT:    csc.b a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.b a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB15_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -732,20 +732,20 @@ define i8 @atomicrmw_and_i8_monotonic(i8 addrspace(200)* %a, i8 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_and_i8_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_and_1
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_and_i8_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB15_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.b a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.b a2, (a0)
 ; RV64IAXCHERI-NEXT:    and a3, a2, a1
-; RV64IAXCHERI-NEXT:    csc.b a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.b a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB15_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -757,20 +757,20 @@ define i8 @atomicrmw_and_i8_monotonic(i8 addrspace(200)* %a, i8 %b) nounwind {
 define i8 @atomicrmw_and_i8_acquire(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_and_i8_acquire:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 2
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_and_1
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_and_i8_acquire:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB16_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.b.aq a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.b.aq a2, (a0)
 ; RV32IAXCHERI-NEXT:    and a3, a2, a1
-; RV32IAXCHERI-NEXT:    csc.b a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.b a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB16_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -778,20 +778,20 @@ define i8 @atomicrmw_and_i8_acquire(i8 addrspace(200)* %a, i8 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_and_i8_acquire:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 2
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_and_1
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_and_i8_acquire:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB16_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.b.aq a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.b.aq a2, (a0)
 ; RV64IAXCHERI-NEXT:    and a3, a2, a1
-; RV64IAXCHERI-NEXT:    csc.b a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.b a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB16_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -803,20 +803,20 @@ define i8 @atomicrmw_and_i8_acquire(i8 addrspace(200)* %a, i8 %b) nounwind {
 define i8 @atomicrmw_and_i8_release(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_and_i8_release:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 3
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_and_1
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_and_i8_release:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB17_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.b a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.b a2, (a0)
 ; RV32IAXCHERI-NEXT:    and a3, a2, a1
-; RV32IAXCHERI-NEXT:    csc.b.rl a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.b.rl a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB17_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -824,20 +824,20 @@ define i8 @atomicrmw_and_i8_release(i8 addrspace(200)* %a, i8 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_and_i8_release:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 3
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_and_1
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_and_i8_release:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB17_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.b a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.b a2, (a0)
 ; RV64IAXCHERI-NEXT:    and a3, a2, a1
-; RV64IAXCHERI-NEXT:    csc.b.rl a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.b.rl a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB17_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -849,20 +849,20 @@ define i8 @atomicrmw_and_i8_release(i8 addrspace(200)* %a, i8 %b) nounwind {
 define i8 @atomicrmw_and_i8_acq_rel(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_and_i8_acq_rel:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 4
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_and_1
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_and_i8_acq_rel:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB18_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.b.aq a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.b.aq a2, (a0)
 ; RV32IAXCHERI-NEXT:    and a3, a2, a1
-; RV32IAXCHERI-NEXT:    csc.b.rl a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.b.rl a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB18_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -870,20 +870,20 @@ define i8 @atomicrmw_and_i8_acq_rel(i8 addrspace(200)* %a, i8 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_and_i8_acq_rel:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 4
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_and_1
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_and_i8_acq_rel:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB18_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.b.aq a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.b.aq a2, (a0)
 ; RV64IAXCHERI-NEXT:    and a3, a2, a1
-; RV64IAXCHERI-NEXT:    csc.b.rl a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.b.rl a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB18_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -895,20 +895,20 @@ define i8 @atomicrmw_and_i8_acq_rel(i8 addrspace(200)* %a, i8 %b) nounwind {
 define i8 @atomicrmw_and_i8_seq_cst(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_and_i8_seq_cst:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 5
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_and_1
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_and_i8_seq_cst:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB19_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.b.aqrl a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.b.aqrl a2, (a0)
 ; RV32IAXCHERI-NEXT:    and a3, a2, a1
-; RV32IAXCHERI-NEXT:    csc.b.aqrl a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.b.aqrl a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB19_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -916,20 +916,20 @@ define i8 @atomicrmw_and_i8_seq_cst(i8 addrspace(200)* %a, i8 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_and_i8_seq_cst:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 5
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_and_1
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_and_i8_seq_cst:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB19_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.b.aqrl a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.b.aqrl a2, (a0)
 ; RV64IAXCHERI-NEXT:    and a3, a2, a1
-; RV64IAXCHERI-NEXT:    csc.b.aqrl a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.b.aqrl a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB19_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -941,21 +941,21 @@ define i8 @atomicrmw_and_i8_seq_cst(i8 addrspace(200)* %a, i8 %b) nounwind {
 define i8 @atomicrmw_nand_i8_monotonic(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_nand_i8_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_nand_1
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_nand_i8_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB20_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.b a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.b a2, (a0)
 ; RV32IAXCHERI-NEXT:    and a3, a2, a1
 ; RV32IAXCHERI-NEXT:    not a3, a3
-; RV32IAXCHERI-NEXT:    csc.b a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.b a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB20_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -963,21 +963,21 @@ define i8 @atomicrmw_nand_i8_monotonic(i8 addrspace(200)* %a, i8 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_nand_i8_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_nand_1
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_nand_i8_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB20_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.b a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.b a2, (a0)
 ; RV64IAXCHERI-NEXT:    and a3, a2, a1
 ; RV64IAXCHERI-NEXT:    not a3, a3
-; RV64IAXCHERI-NEXT:    csc.b a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.b a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB20_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -989,21 +989,21 @@ define i8 @atomicrmw_nand_i8_monotonic(i8 addrspace(200)* %a, i8 %b) nounwind {
 define i8 @atomicrmw_nand_i8_acquire(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_nand_i8_acquire:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 2
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_nand_1
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_nand_i8_acquire:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB21_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.b.aq a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.b.aq a2, (a0)
 ; RV32IAXCHERI-NEXT:    and a3, a2, a1
 ; RV32IAXCHERI-NEXT:    not a3, a3
-; RV32IAXCHERI-NEXT:    csc.b a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.b a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB21_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -1011,21 +1011,21 @@ define i8 @atomicrmw_nand_i8_acquire(i8 addrspace(200)* %a, i8 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_nand_i8_acquire:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 2
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_nand_1
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_nand_i8_acquire:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB21_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.b.aq a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.b.aq a2, (a0)
 ; RV64IAXCHERI-NEXT:    and a3, a2, a1
 ; RV64IAXCHERI-NEXT:    not a3, a3
-; RV64IAXCHERI-NEXT:    csc.b a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.b a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB21_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -1037,21 +1037,21 @@ define i8 @atomicrmw_nand_i8_acquire(i8 addrspace(200)* %a, i8 %b) nounwind {
 define i8 @atomicrmw_nand_i8_release(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_nand_i8_release:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 3
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_nand_1
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_nand_i8_release:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB22_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.b a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.b a2, (a0)
 ; RV32IAXCHERI-NEXT:    and a3, a2, a1
 ; RV32IAXCHERI-NEXT:    not a3, a3
-; RV32IAXCHERI-NEXT:    csc.b.rl a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.b.rl a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB22_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -1059,21 +1059,21 @@ define i8 @atomicrmw_nand_i8_release(i8 addrspace(200)* %a, i8 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_nand_i8_release:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 3
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_nand_1
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_nand_i8_release:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB22_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.b a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.b a2, (a0)
 ; RV64IAXCHERI-NEXT:    and a3, a2, a1
 ; RV64IAXCHERI-NEXT:    not a3, a3
-; RV64IAXCHERI-NEXT:    csc.b.rl a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.b.rl a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB22_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -1085,21 +1085,21 @@ define i8 @atomicrmw_nand_i8_release(i8 addrspace(200)* %a, i8 %b) nounwind {
 define i8 @atomicrmw_nand_i8_acq_rel(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_nand_i8_acq_rel:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 4
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_nand_1
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_nand_i8_acq_rel:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB23_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.b.aq a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.b.aq a2, (a0)
 ; RV32IAXCHERI-NEXT:    and a3, a2, a1
 ; RV32IAXCHERI-NEXT:    not a3, a3
-; RV32IAXCHERI-NEXT:    csc.b.rl a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.b.rl a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB23_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -1107,21 +1107,21 @@ define i8 @atomicrmw_nand_i8_acq_rel(i8 addrspace(200)* %a, i8 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_nand_i8_acq_rel:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 4
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_nand_1
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_nand_i8_acq_rel:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB23_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.b.aq a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.b.aq a2, (a0)
 ; RV64IAXCHERI-NEXT:    and a3, a2, a1
 ; RV64IAXCHERI-NEXT:    not a3, a3
-; RV64IAXCHERI-NEXT:    csc.b.rl a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.b.rl a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB23_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -1133,21 +1133,21 @@ define i8 @atomicrmw_nand_i8_acq_rel(i8 addrspace(200)* %a, i8 %b) nounwind {
 define i8 @atomicrmw_nand_i8_seq_cst(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_nand_i8_seq_cst:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 5
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_nand_1
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_nand_i8_seq_cst:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB24_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.b.aqrl a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.b.aqrl a2, (a0)
 ; RV32IAXCHERI-NEXT:    and a3, a2, a1
 ; RV32IAXCHERI-NEXT:    not a3, a3
-; RV32IAXCHERI-NEXT:    csc.b.aqrl a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.b.aqrl a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB24_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -1155,21 +1155,21 @@ define i8 @atomicrmw_nand_i8_seq_cst(i8 addrspace(200)* %a, i8 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_nand_i8_seq_cst:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 5
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_nand_1
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_nand_i8_seq_cst:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB24_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.b.aqrl a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.b.aqrl a2, (a0)
 ; RV64IAXCHERI-NEXT:    and a3, a2, a1
 ; RV64IAXCHERI-NEXT:    not a3, a3
-; RV64IAXCHERI-NEXT:    csc.b.aqrl a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.b.aqrl a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB24_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -1181,20 +1181,20 @@ define i8 @atomicrmw_nand_i8_seq_cst(i8 addrspace(200)* %a, i8 %b) nounwind {
 define i8 @atomicrmw_or_i8_monotonic(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_or_i8_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_or_1
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_or_i8_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB25_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.b a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.b a2, (a0)
 ; RV32IAXCHERI-NEXT:    or a3, a2, a1
-; RV32IAXCHERI-NEXT:    csc.b a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.b a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB25_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -1202,20 +1202,20 @@ define i8 @atomicrmw_or_i8_monotonic(i8 addrspace(200)* %a, i8 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_or_i8_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_or_1
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_or_i8_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB25_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.b a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.b a2, (a0)
 ; RV64IAXCHERI-NEXT:    or a3, a2, a1
-; RV64IAXCHERI-NEXT:    csc.b a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.b a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB25_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -1227,20 +1227,20 @@ define i8 @atomicrmw_or_i8_monotonic(i8 addrspace(200)* %a, i8 %b) nounwind {
 define i8 @atomicrmw_or_i8_acquire(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_or_i8_acquire:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 2
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_or_1
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_or_i8_acquire:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB26_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.b.aq a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.b.aq a2, (a0)
 ; RV32IAXCHERI-NEXT:    or a3, a2, a1
-; RV32IAXCHERI-NEXT:    csc.b a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.b a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB26_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -1248,20 +1248,20 @@ define i8 @atomicrmw_or_i8_acquire(i8 addrspace(200)* %a, i8 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_or_i8_acquire:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 2
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_or_1
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_or_i8_acquire:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB26_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.b.aq a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.b.aq a2, (a0)
 ; RV64IAXCHERI-NEXT:    or a3, a2, a1
-; RV64IAXCHERI-NEXT:    csc.b a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.b a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB26_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -1273,20 +1273,20 @@ define i8 @atomicrmw_or_i8_acquire(i8 addrspace(200)* %a, i8 %b) nounwind {
 define i8 @atomicrmw_or_i8_release(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_or_i8_release:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 3
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_or_1
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_or_i8_release:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB27_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.b a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.b a2, (a0)
 ; RV32IAXCHERI-NEXT:    or a3, a2, a1
-; RV32IAXCHERI-NEXT:    csc.b.rl a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.b.rl a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB27_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -1294,20 +1294,20 @@ define i8 @atomicrmw_or_i8_release(i8 addrspace(200)* %a, i8 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_or_i8_release:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 3
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_or_1
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_or_i8_release:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB27_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.b a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.b a2, (a0)
 ; RV64IAXCHERI-NEXT:    or a3, a2, a1
-; RV64IAXCHERI-NEXT:    csc.b.rl a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.b.rl a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB27_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -1319,20 +1319,20 @@ define i8 @atomicrmw_or_i8_release(i8 addrspace(200)* %a, i8 %b) nounwind {
 define i8 @atomicrmw_or_i8_acq_rel(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_or_i8_acq_rel:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 4
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_or_1
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_or_i8_acq_rel:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB28_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.b.aq a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.b.aq a2, (a0)
 ; RV32IAXCHERI-NEXT:    or a3, a2, a1
-; RV32IAXCHERI-NEXT:    csc.b.rl a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.b.rl a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB28_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -1340,20 +1340,20 @@ define i8 @atomicrmw_or_i8_acq_rel(i8 addrspace(200)* %a, i8 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_or_i8_acq_rel:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 4
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_or_1
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_or_i8_acq_rel:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB28_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.b.aq a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.b.aq a2, (a0)
 ; RV64IAXCHERI-NEXT:    or a3, a2, a1
-; RV64IAXCHERI-NEXT:    csc.b.rl a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.b.rl a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB28_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -1365,20 +1365,20 @@ define i8 @atomicrmw_or_i8_acq_rel(i8 addrspace(200)* %a, i8 %b) nounwind {
 define i8 @atomicrmw_or_i8_seq_cst(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_or_i8_seq_cst:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 5
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_or_1
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_or_i8_seq_cst:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB29_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.b.aqrl a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.b.aqrl a2, (a0)
 ; RV32IAXCHERI-NEXT:    or a3, a2, a1
-; RV32IAXCHERI-NEXT:    csc.b.aqrl a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.b.aqrl a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB29_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -1386,20 +1386,20 @@ define i8 @atomicrmw_or_i8_seq_cst(i8 addrspace(200)* %a, i8 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_or_i8_seq_cst:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 5
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_or_1
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_or_i8_seq_cst:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB29_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.b.aqrl a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.b.aqrl a2, (a0)
 ; RV64IAXCHERI-NEXT:    or a3, a2, a1
-; RV64IAXCHERI-NEXT:    csc.b.aqrl a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.b.aqrl a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB29_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -1411,20 +1411,20 @@ define i8 @atomicrmw_or_i8_seq_cst(i8 addrspace(200)* %a, i8 %b) nounwind {
 define i8 @atomicrmw_xor_i8_monotonic(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_xor_i8_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_xor_1
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_xor_i8_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB30_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.b a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.b a2, (a0)
 ; RV32IAXCHERI-NEXT:    xor a3, a2, a1
-; RV32IAXCHERI-NEXT:    csc.b a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.b a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB30_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -1432,20 +1432,20 @@ define i8 @atomicrmw_xor_i8_monotonic(i8 addrspace(200)* %a, i8 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_xor_i8_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_xor_1
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_xor_i8_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB30_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.b a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.b a2, (a0)
 ; RV64IAXCHERI-NEXT:    xor a3, a2, a1
-; RV64IAXCHERI-NEXT:    csc.b a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.b a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB30_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -1457,20 +1457,20 @@ define i8 @atomicrmw_xor_i8_monotonic(i8 addrspace(200)* %a, i8 %b) nounwind {
 define i8 @atomicrmw_xor_i8_acquire(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_xor_i8_acquire:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 2
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_xor_1
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_xor_i8_acquire:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB31_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.b.aq a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.b.aq a2, (a0)
 ; RV32IAXCHERI-NEXT:    xor a3, a2, a1
-; RV32IAXCHERI-NEXT:    csc.b a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.b a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB31_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -1478,20 +1478,20 @@ define i8 @atomicrmw_xor_i8_acquire(i8 addrspace(200)* %a, i8 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_xor_i8_acquire:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 2
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_xor_1
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_xor_i8_acquire:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB31_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.b.aq a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.b.aq a2, (a0)
 ; RV64IAXCHERI-NEXT:    xor a3, a2, a1
-; RV64IAXCHERI-NEXT:    csc.b a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.b a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB31_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -1503,20 +1503,20 @@ define i8 @atomicrmw_xor_i8_acquire(i8 addrspace(200)* %a, i8 %b) nounwind {
 define i8 @atomicrmw_xor_i8_release(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_xor_i8_release:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 3
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_xor_1
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_xor_i8_release:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB32_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.b a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.b a2, (a0)
 ; RV32IAXCHERI-NEXT:    xor a3, a2, a1
-; RV32IAXCHERI-NEXT:    csc.b.rl a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.b.rl a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB32_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -1524,20 +1524,20 @@ define i8 @atomicrmw_xor_i8_release(i8 addrspace(200)* %a, i8 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_xor_i8_release:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 3
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_xor_1
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_xor_i8_release:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB32_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.b a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.b a2, (a0)
 ; RV64IAXCHERI-NEXT:    xor a3, a2, a1
-; RV64IAXCHERI-NEXT:    csc.b.rl a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.b.rl a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB32_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -1549,20 +1549,20 @@ define i8 @atomicrmw_xor_i8_release(i8 addrspace(200)* %a, i8 %b) nounwind {
 define i8 @atomicrmw_xor_i8_acq_rel(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_xor_i8_acq_rel:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 4
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_xor_1
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_xor_i8_acq_rel:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB33_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.b.aq a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.b.aq a2, (a0)
 ; RV32IAXCHERI-NEXT:    xor a3, a2, a1
-; RV32IAXCHERI-NEXT:    csc.b.rl a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.b.rl a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB33_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -1570,20 +1570,20 @@ define i8 @atomicrmw_xor_i8_acq_rel(i8 addrspace(200)* %a, i8 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_xor_i8_acq_rel:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 4
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_xor_1
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_xor_i8_acq_rel:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB33_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.b.aq a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.b.aq a2, (a0)
 ; RV64IAXCHERI-NEXT:    xor a3, a2, a1
-; RV64IAXCHERI-NEXT:    csc.b.rl a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.b.rl a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB33_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -1595,20 +1595,20 @@ define i8 @atomicrmw_xor_i8_acq_rel(i8 addrspace(200)* %a, i8 %b) nounwind {
 define i8 @atomicrmw_xor_i8_seq_cst(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_xor_i8_seq_cst:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 5
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_xor_1
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_xor_i8_seq_cst:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB34_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.b.aqrl a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.b.aqrl a2, (a0)
 ; RV32IAXCHERI-NEXT:    xor a3, a2, a1
-; RV32IAXCHERI-NEXT:    csc.b.aqrl a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.b.aqrl a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB34_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -1616,20 +1616,20 @@ define i8 @atomicrmw_xor_i8_seq_cst(i8 addrspace(200)* %a, i8 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_xor_i8_seq_cst:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 5
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_xor_1
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_xor_i8_seq_cst:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB34_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.b.aqrl a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.b.aqrl a2, (a0)
 ; RV64IAXCHERI-NEXT:    xor a3, a2, a1
-; RV64IAXCHERI-NEXT:    csc.b.aqrl a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.b.aqrl a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB34_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -1641,29 +1641,29 @@ define i8 @atomicrmw_xor_i8_seq_cst(i8 addrspace(200)* %a, i8 %b) nounwind {
 define i8 @atomicrmw_max_i8_monotonic(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_max_i8_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs3, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    mv s2, a1
-; RV32IXCHERI-NEXT:    cmove cs1, ca0
-; RV32IXCHERI-NEXT:    clbu a1, 0(ca0)
-; RV32IXCHERI-NEXT:    slli a0, s2, 24
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s3, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    mv s0, a1
+; RV32IXCHERI-NEXT:    cmove s1, a0
+; RV32IXCHERI-NEXT:    clbu a1, 0(a0)
+; RV32IXCHERI-NEXT:    slli a0, s0, 24
 ; RV32IXCHERI-NEXT:    srai s3, a0, 24
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 7
-; RV32IXCHERI-NEXT:    csetbounds cs0, ca0, 1
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 7
+; RV32IXCHERI-NEXT:    csetbounds s2, a0, 1
 ; RV32IXCHERI-NEXT:    j .LBB35_2
 ; RV32IXCHERI-NEXT:  .LBB35_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB35_2 Depth=1
-; RV32IXCHERI-NEXT:    csb a1, 7(csp)
-; RV32IXCHERI-NEXT:    cmove ca0, cs1
-; RV32IXCHERI-NEXT:    cmove ca1, cs0
+; RV32IXCHERI-NEXT:    csb a1, 7(sp)
+; RV32IXCHERI-NEXT:    cmove a0, s1
+; RV32IXCHERI-NEXT:    cmove a1, s2
 ; RV32IXCHERI-NEXT:    li a3, 0
 ; RV32IXCHERI-NEXT:    li a4, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_1
-; RV32IXCHERI-NEXT:    clb a1, 7(csp)
+; RV32IXCHERI-NEXT:    clb a1, 7(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB35_4
 ; RV32IXCHERI-NEXT:  .LBB35_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -1673,28 +1673,28 @@ define i8 @atomicrmw_max_i8_monotonic(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-NEXT:    blt s3, a0, .LBB35_1
 ; RV32IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB35_2 Depth=1
-; RV32IXCHERI-NEXT:    mv a2, s2
+; RV32IXCHERI-NEXT:    mv a2, s0
 ; RV32IXCHERI-NEXT:    j .LBB35_1
 ; RV32IXCHERI-NEXT:  .LBB35_4: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a1
-; RV32IXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs3, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s3, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_max_i8_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB35_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.b a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.b a2, (a0)
 ; RV32IAXCHERI-NEXT:    mv a3, a2
 ; RV32IAXCHERI-NEXT:    bge a3, a1, .LBB35_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB35_1 Depth=1
 ; RV32IAXCHERI-NEXT:    mv a3, a1
 ; RV32IAXCHERI-NEXT:  .LBB35_3: # in Loop: Header=BB35_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.b a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.b a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB35_1
 ; RV32IAXCHERI-NEXT:  # %bb.4:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -1702,29 +1702,29 @@ define i8 @atomicrmw_max_i8_monotonic(i8 addrspace(200)* %a, i8 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_max_i8_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -96
-; RV64IXCHERI-NEXT:    csc cra, 80(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs3, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    mv s2, a1
-; RV64IXCHERI-NEXT:    cmove cs1, ca0
-; RV64IXCHERI-NEXT:    clbu a1, 0(ca0)
-; RV64IXCHERI-NEXT:    slli a0, s2, 56
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -96
+; RV64IXCHERI-NEXT:    csc ra, 80(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s3, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    mv s0, a1
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    clbu a1, 0(a0)
+; RV64IXCHERI-NEXT:    slli a0, s0, 56
 ; RV64IXCHERI-NEXT:    srai s3, a0, 56
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 15
-; RV64IXCHERI-NEXT:    csetbounds cs0, ca0, 1
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 15
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 1
 ; RV64IXCHERI-NEXT:    j .LBB35_2
 ; RV64IXCHERI-NEXT:  .LBB35_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB35_2 Depth=1
-; RV64IXCHERI-NEXT:    csb a1, 15(csp)
-; RV64IXCHERI-NEXT:    cmove ca0, cs1
-; RV64IXCHERI-NEXT:    cmove ca1, cs0
+; RV64IXCHERI-NEXT:    csb a1, 15(sp)
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    li a3, 0
 ; RV64IXCHERI-NEXT:    li a4, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_1
-; RV64IXCHERI-NEXT:    clb a1, 15(csp)
+; RV64IXCHERI-NEXT:    clb a1, 15(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB35_4
 ; RV64IXCHERI-NEXT:  .LBB35_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -1734,28 +1734,28 @@ define i8 @atomicrmw_max_i8_monotonic(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV64IXCHERI-NEXT:    blt s3, a0, .LBB35_1
 ; RV64IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB35_2 Depth=1
-; RV64IXCHERI-NEXT:    mv a2, s2
+; RV64IXCHERI-NEXT:    mv a2, s0
 ; RV64IXCHERI-NEXT:    j .LBB35_1
 ; RV64IXCHERI-NEXT:  .LBB35_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 80(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs3, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 96
+; RV64IXCHERI-NEXT:    clc ra, 80(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s3, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 96
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_max_i8_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB35_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.b a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.b a2, (a0)
 ; RV64IAXCHERI-NEXT:    mv a3, a2
 ; RV64IAXCHERI-NEXT:    bge a3, a1, .LBB35_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB35_1 Depth=1
 ; RV64IAXCHERI-NEXT:    mv a3, a1
 ; RV64IAXCHERI-NEXT:  .LBB35_3: # in Loop: Header=BB35_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.b a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.b a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB35_1
 ; RV64IAXCHERI-NEXT:  # %bb.4:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -1767,29 +1767,29 @@ define i8 @atomicrmw_max_i8_monotonic(i8 addrspace(200)* %a, i8 %b) nounwind {
 define i8 @atomicrmw_max_i8_acquire(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_max_i8_acquire:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs3, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    mv s2, a1
-; RV32IXCHERI-NEXT:    cmove cs1, ca0
-; RV32IXCHERI-NEXT:    clbu a1, 0(ca0)
-; RV32IXCHERI-NEXT:    slli a0, s2, 24
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s3, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    mv s0, a1
+; RV32IXCHERI-NEXT:    cmove s1, a0
+; RV32IXCHERI-NEXT:    clbu a1, 0(a0)
+; RV32IXCHERI-NEXT:    slli a0, s0, 24
 ; RV32IXCHERI-NEXT:    srai s3, a0, 24
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 7
-; RV32IXCHERI-NEXT:    csetbounds cs0, ca0, 1
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 7
+; RV32IXCHERI-NEXT:    csetbounds s2, a0, 1
 ; RV32IXCHERI-NEXT:    j .LBB36_2
 ; RV32IXCHERI-NEXT:  .LBB36_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB36_2 Depth=1
-; RV32IXCHERI-NEXT:    csb a1, 7(csp)
+; RV32IXCHERI-NEXT:    csb a1, 7(sp)
 ; RV32IXCHERI-NEXT:    li a3, 2
 ; RV32IXCHERI-NEXT:    li a4, 2
-; RV32IXCHERI-NEXT:    cmove ca0, cs1
-; RV32IXCHERI-NEXT:    cmove ca1, cs0
+; RV32IXCHERI-NEXT:    cmove a0, s1
+; RV32IXCHERI-NEXT:    cmove a1, s2
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_1
-; RV32IXCHERI-NEXT:    clb a1, 7(csp)
+; RV32IXCHERI-NEXT:    clb a1, 7(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB36_4
 ; RV32IXCHERI-NEXT:  .LBB36_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -1799,28 +1799,28 @@ define i8 @atomicrmw_max_i8_acquire(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-NEXT:    blt s3, a0, .LBB36_1
 ; RV32IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB36_2 Depth=1
-; RV32IXCHERI-NEXT:    mv a2, s2
+; RV32IXCHERI-NEXT:    mv a2, s0
 ; RV32IXCHERI-NEXT:    j .LBB36_1
 ; RV32IXCHERI-NEXT:  .LBB36_4: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a1
-; RV32IXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs3, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s3, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_max_i8_acquire:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB36_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.b.aq a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.b.aq a2, (a0)
 ; RV32IAXCHERI-NEXT:    mv a3, a2
 ; RV32IAXCHERI-NEXT:    bge a3, a1, .LBB36_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB36_1 Depth=1
 ; RV32IAXCHERI-NEXT:    mv a3, a1
 ; RV32IAXCHERI-NEXT:  .LBB36_3: # in Loop: Header=BB36_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.b a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.b a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB36_1
 ; RV32IAXCHERI-NEXT:  # %bb.4:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -1828,29 +1828,29 @@ define i8 @atomicrmw_max_i8_acquire(i8 addrspace(200)* %a, i8 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_max_i8_acquire:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -96
-; RV64IXCHERI-NEXT:    csc cra, 80(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs3, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    mv s2, a1
-; RV64IXCHERI-NEXT:    cmove cs1, ca0
-; RV64IXCHERI-NEXT:    clbu a1, 0(ca0)
-; RV64IXCHERI-NEXT:    slli a0, s2, 56
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -96
+; RV64IXCHERI-NEXT:    csc ra, 80(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s3, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    mv s0, a1
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    clbu a1, 0(a0)
+; RV64IXCHERI-NEXT:    slli a0, s0, 56
 ; RV64IXCHERI-NEXT:    srai s3, a0, 56
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 15
-; RV64IXCHERI-NEXT:    csetbounds cs0, ca0, 1
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 15
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 1
 ; RV64IXCHERI-NEXT:    j .LBB36_2
 ; RV64IXCHERI-NEXT:  .LBB36_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB36_2 Depth=1
-; RV64IXCHERI-NEXT:    csb a1, 15(csp)
+; RV64IXCHERI-NEXT:    csb a1, 15(sp)
 ; RV64IXCHERI-NEXT:    li a3, 2
 ; RV64IXCHERI-NEXT:    li a4, 2
-; RV64IXCHERI-NEXT:    cmove ca0, cs1
-; RV64IXCHERI-NEXT:    cmove ca1, cs0
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_1
-; RV64IXCHERI-NEXT:    clb a1, 15(csp)
+; RV64IXCHERI-NEXT:    clb a1, 15(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB36_4
 ; RV64IXCHERI-NEXT:  .LBB36_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -1860,28 +1860,28 @@ define i8 @atomicrmw_max_i8_acquire(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV64IXCHERI-NEXT:    blt s3, a0, .LBB36_1
 ; RV64IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB36_2 Depth=1
-; RV64IXCHERI-NEXT:    mv a2, s2
+; RV64IXCHERI-NEXT:    mv a2, s0
 ; RV64IXCHERI-NEXT:    j .LBB36_1
 ; RV64IXCHERI-NEXT:  .LBB36_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 80(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs3, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 96
+; RV64IXCHERI-NEXT:    clc ra, 80(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s3, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 96
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_max_i8_acquire:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB36_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.b.aq a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.b.aq a2, (a0)
 ; RV64IAXCHERI-NEXT:    mv a3, a2
 ; RV64IAXCHERI-NEXT:    bge a3, a1, .LBB36_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB36_1 Depth=1
 ; RV64IAXCHERI-NEXT:    mv a3, a1
 ; RV64IAXCHERI-NEXT:  .LBB36_3: # in Loop: Header=BB36_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.b a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.b a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB36_1
 ; RV64IAXCHERI-NEXT:  # %bb.4:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -1893,29 +1893,29 @@ define i8 @atomicrmw_max_i8_acquire(i8 addrspace(200)* %a, i8 %b) nounwind {
 define i8 @atomicrmw_max_i8_release(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_max_i8_release:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs3, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    mv s2, a1
-; RV32IXCHERI-NEXT:    cmove cs1, ca0
-; RV32IXCHERI-NEXT:    clbu a1, 0(ca0)
-; RV32IXCHERI-NEXT:    slli a0, s2, 24
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s3, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    mv s0, a1
+; RV32IXCHERI-NEXT:    cmove s1, a0
+; RV32IXCHERI-NEXT:    clbu a1, 0(a0)
+; RV32IXCHERI-NEXT:    slli a0, s0, 24
 ; RV32IXCHERI-NEXT:    srai s3, a0, 24
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 7
-; RV32IXCHERI-NEXT:    csetbounds cs0, ca0, 1
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 7
+; RV32IXCHERI-NEXT:    csetbounds s2, a0, 1
 ; RV32IXCHERI-NEXT:    j .LBB37_2
 ; RV32IXCHERI-NEXT:  .LBB37_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB37_2 Depth=1
-; RV32IXCHERI-NEXT:    csb a1, 7(csp)
+; RV32IXCHERI-NEXT:    csb a1, 7(sp)
 ; RV32IXCHERI-NEXT:    li a3, 3
-; RV32IXCHERI-NEXT:    cmove ca0, cs1
-; RV32IXCHERI-NEXT:    cmove ca1, cs0
+; RV32IXCHERI-NEXT:    cmove a0, s1
+; RV32IXCHERI-NEXT:    cmove a1, s2
 ; RV32IXCHERI-NEXT:    li a4, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_1
-; RV32IXCHERI-NEXT:    clb a1, 7(csp)
+; RV32IXCHERI-NEXT:    clb a1, 7(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB37_4
 ; RV32IXCHERI-NEXT:  .LBB37_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -1925,28 +1925,28 @@ define i8 @atomicrmw_max_i8_release(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-NEXT:    blt s3, a0, .LBB37_1
 ; RV32IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB37_2 Depth=1
-; RV32IXCHERI-NEXT:    mv a2, s2
+; RV32IXCHERI-NEXT:    mv a2, s0
 ; RV32IXCHERI-NEXT:    j .LBB37_1
 ; RV32IXCHERI-NEXT:  .LBB37_4: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a1
-; RV32IXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs3, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s3, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_max_i8_release:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB37_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.b a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.b a2, (a0)
 ; RV32IAXCHERI-NEXT:    mv a3, a2
 ; RV32IAXCHERI-NEXT:    bge a3, a1, .LBB37_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB37_1 Depth=1
 ; RV32IAXCHERI-NEXT:    mv a3, a1
 ; RV32IAXCHERI-NEXT:  .LBB37_3: # in Loop: Header=BB37_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.b.rl a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.b.rl a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB37_1
 ; RV32IAXCHERI-NEXT:  # %bb.4:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -1954,29 +1954,29 @@ define i8 @atomicrmw_max_i8_release(i8 addrspace(200)* %a, i8 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_max_i8_release:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -96
-; RV64IXCHERI-NEXT:    csc cra, 80(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs3, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    mv s2, a1
-; RV64IXCHERI-NEXT:    cmove cs1, ca0
-; RV64IXCHERI-NEXT:    clbu a1, 0(ca0)
-; RV64IXCHERI-NEXT:    slli a0, s2, 56
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -96
+; RV64IXCHERI-NEXT:    csc ra, 80(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s3, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    mv s0, a1
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    clbu a1, 0(a0)
+; RV64IXCHERI-NEXT:    slli a0, s0, 56
 ; RV64IXCHERI-NEXT:    srai s3, a0, 56
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 15
-; RV64IXCHERI-NEXT:    csetbounds cs0, ca0, 1
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 15
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 1
 ; RV64IXCHERI-NEXT:    j .LBB37_2
 ; RV64IXCHERI-NEXT:  .LBB37_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB37_2 Depth=1
-; RV64IXCHERI-NEXT:    csb a1, 15(csp)
+; RV64IXCHERI-NEXT:    csb a1, 15(sp)
 ; RV64IXCHERI-NEXT:    li a3, 3
-; RV64IXCHERI-NEXT:    cmove ca0, cs1
-; RV64IXCHERI-NEXT:    cmove ca1, cs0
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    li a4, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_1
-; RV64IXCHERI-NEXT:    clb a1, 15(csp)
+; RV64IXCHERI-NEXT:    clb a1, 15(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB37_4
 ; RV64IXCHERI-NEXT:  .LBB37_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -1986,28 +1986,28 @@ define i8 @atomicrmw_max_i8_release(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV64IXCHERI-NEXT:    blt s3, a0, .LBB37_1
 ; RV64IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB37_2 Depth=1
-; RV64IXCHERI-NEXT:    mv a2, s2
+; RV64IXCHERI-NEXT:    mv a2, s0
 ; RV64IXCHERI-NEXT:    j .LBB37_1
 ; RV64IXCHERI-NEXT:  .LBB37_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 80(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs3, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 96
+; RV64IXCHERI-NEXT:    clc ra, 80(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s3, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 96
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_max_i8_release:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB37_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.b a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.b a2, (a0)
 ; RV64IAXCHERI-NEXT:    mv a3, a2
 ; RV64IAXCHERI-NEXT:    bge a3, a1, .LBB37_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB37_1 Depth=1
 ; RV64IAXCHERI-NEXT:    mv a3, a1
 ; RV64IAXCHERI-NEXT:  .LBB37_3: # in Loop: Header=BB37_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.b.rl a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.b.rl a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB37_1
 ; RV64IAXCHERI-NEXT:  # %bb.4:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -2019,29 +2019,29 @@ define i8 @atomicrmw_max_i8_release(i8 addrspace(200)* %a, i8 %b) nounwind {
 define i8 @atomicrmw_max_i8_acq_rel(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_max_i8_acq_rel:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs3, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    mv s2, a1
-; RV32IXCHERI-NEXT:    cmove cs1, ca0
-; RV32IXCHERI-NEXT:    clbu a1, 0(ca0)
-; RV32IXCHERI-NEXT:    slli a0, s2, 24
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s3, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    mv s0, a1
+; RV32IXCHERI-NEXT:    cmove s1, a0
+; RV32IXCHERI-NEXT:    clbu a1, 0(a0)
+; RV32IXCHERI-NEXT:    slli a0, s0, 24
 ; RV32IXCHERI-NEXT:    srai s3, a0, 24
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 7
-; RV32IXCHERI-NEXT:    csetbounds cs0, ca0, 1
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 7
+; RV32IXCHERI-NEXT:    csetbounds s2, a0, 1
 ; RV32IXCHERI-NEXT:    j .LBB38_2
 ; RV32IXCHERI-NEXT:  .LBB38_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB38_2 Depth=1
-; RV32IXCHERI-NEXT:    csb a1, 7(csp)
+; RV32IXCHERI-NEXT:    csb a1, 7(sp)
 ; RV32IXCHERI-NEXT:    li a3, 4
 ; RV32IXCHERI-NEXT:    li a4, 2
-; RV32IXCHERI-NEXT:    cmove ca0, cs1
-; RV32IXCHERI-NEXT:    cmove ca1, cs0
+; RV32IXCHERI-NEXT:    cmove a0, s1
+; RV32IXCHERI-NEXT:    cmove a1, s2
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_1
-; RV32IXCHERI-NEXT:    clb a1, 7(csp)
+; RV32IXCHERI-NEXT:    clb a1, 7(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB38_4
 ; RV32IXCHERI-NEXT:  .LBB38_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -2051,28 +2051,28 @@ define i8 @atomicrmw_max_i8_acq_rel(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-NEXT:    blt s3, a0, .LBB38_1
 ; RV32IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB38_2 Depth=1
-; RV32IXCHERI-NEXT:    mv a2, s2
+; RV32IXCHERI-NEXT:    mv a2, s0
 ; RV32IXCHERI-NEXT:    j .LBB38_1
 ; RV32IXCHERI-NEXT:  .LBB38_4: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a1
-; RV32IXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs3, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s3, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_max_i8_acq_rel:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB38_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.b.aq a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.b.aq a2, (a0)
 ; RV32IAXCHERI-NEXT:    mv a3, a2
 ; RV32IAXCHERI-NEXT:    bge a3, a1, .LBB38_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB38_1 Depth=1
 ; RV32IAXCHERI-NEXT:    mv a3, a1
 ; RV32IAXCHERI-NEXT:  .LBB38_3: # in Loop: Header=BB38_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.b.rl a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.b.rl a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB38_1
 ; RV32IAXCHERI-NEXT:  # %bb.4:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -2080,29 +2080,29 @@ define i8 @atomicrmw_max_i8_acq_rel(i8 addrspace(200)* %a, i8 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_max_i8_acq_rel:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -96
-; RV64IXCHERI-NEXT:    csc cra, 80(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs3, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    mv s2, a1
-; RV64IXCHERI-NEXT:    cmove cs1, ca0
-; RV64IXCHERI-NEXT:    clbu a1, 0(ca0)
-; RV64IXCHERI-NEXT:    slli a0, s2, 56
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -96
+; RV64IXCHERI-NEXT:    csc ra, 80(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s3, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    mv s0, a1
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    clbu a1, 0(a0)
+; RV64IXCHERI-NEXT:    slli a0, s0, 56
 ; RV64IXCHERI-NEXT:    srai s3, a0, 56
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 15
-; RV64IXCHERI-NEXT:    csetbounds cs0, ca0, 1
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 15
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 1
 ; RV64IXCHERI-NEXT:    j .LBB38_2
 ; RV64IXCHERI-NEXT:  .LBB38_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB38_2 Depth=1
-; RV64IXCHERI-NEXT:    csb a1, 15(csp)
+; RV64IXCHERI-NEXT:    csb a1, 15(sp)
 ; RV64IXCHERI-NEXT:    li a3, 4
 ; RV64IXCHERI-NEXT:    li a4, 2
-; RV64IXCHERI-NEXT:    cmove ca0, cs1
-; RV64IXCHERI-NEXT:    cmove ca1, cs0
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_1
-; RV64IXCHERI-NEXT:    clb a1, 15(csp)
+; RV64IXCHERI-NEXT:    clb a1, 15(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB38_4
 ; RV64IXCHERI-NEXT:  .LBB38_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -2112,28 +2112,28 @@ define i8 @atomicrmw_max_i8_acq_rel(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV64IXCHERI-NEXT:    blt s3, a0, .LBB38_1
 ; RV64IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB38_2 Depth=1
-; RV64IXCHERI-NEXT:    mv a2, s2
+; RV64IXCHERI-NEXT:    mv a2, s0
 ; RV64IXCHERI-NEXT:    j .LBB38_1
 ; RV64IXCHERI-NEXT:  .LBB38_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 80(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs3, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 96
+; RV64IXCHERI-NEXT:    clc ra, 80(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s3, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 96
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_max_i8_acq_rel:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB38_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.b.aq a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.b.aq a2, (a0)
 ; RV64IAXCHERI-NEXT:    mv a3, a2
 ; RV64IAXCHERI-NEXT:    bge a3, a1, .LBB38_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB38_1 Depth=1
 ; RV64IAXCHERI-NEXT:    mv a3, a1
 ; RV64IAXCHERI-NEXT:  .LBB38_3: # in Loop: Header=BB38_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.b.rl a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.b.rl a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB38_1
 ; RV64IAXCHERI-NEXT:  # %bb.4:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -2145,29 +2145,29 @@ define i8 @atomicrmw_max_i8_acq_rel(i8 addrspace(200)* %a, i8 %b) nounwind {
 define i8 @atomicrmw_max_i8_seq_cst(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_max_i8_seq_cst:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs3, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    mv s2, a1
-; RV32IXCHERI-NEXT:    cmove cs1, ca0
-; RV32IXCHERI-NEXT:    clbu a1, 0(ca0)
-; RV32IXCHERI-NEXT:    slli a0, s2, 24
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s3, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    mv s0, a1
+; RV32IXCHERI-NEXT:    cmove s1, a0
+; RV32IXCHERI-NEXT:    clbu a1, 0(a0)
+; RV32IXCHERI-NEXT:    slli a0, s0, 24
 ; RV32IXCHERI-NEXT:    srai s3, a0, 24
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 7
-; RV32IXCHERI-NEXT:    csetbounds cs0, ca0, 1
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 7
+; RV32IXCHERI-NEXT:    csetbounds s2, a0, 1
 ; RV32IXCHERI-NEXT:    j .LBB39_2
 ; RV32IXCHERI-NEXT:  .LBB39_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB39_2 Depth=1
-; RV32IXCHERI-NEXT:    csb a1, 7(csp)
+; RV32IXCHERI-NEXT:    csb a1, 7(sp)
 ; RV32IXCHERI-NEXT:    li a3, 5
 ; RV32IXCHERI-NEXT:    li a4, 5
-; RV32IXCHERI-NEXT:    cmove ca0, cs1
-; RV32IXCHERI-NEXT:    cmove ca1, cs0
+; RV32IXCHERI-NEXT:    cmove a0, s1
+; RV32IXCHERI-NEXT:    cmove a1, s2
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_1
-; RV32IXCHERI-NEXT:    clb a1, 7(csp)
+; RV32IXCHERI-NEXT:    clb a1, 7(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB39_4
 ; RV32IXCHERI-NEXT:  .LBB39_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -2177,28 +2177,28 @@ define i8 @atomicrmw_max_i8_seq_cst(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-NEXT:    blt s3, a0, .LBB39_1
 ; RV32IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB39_2 Depth=1
-; RV32IXCHERI-NEXT:    mv a2, s2
+; RV32IXCHERI-NEXT:    mv a2, s0
 ; RV32IXCHERI-NEXT:    j .LBB39_1
 ; RV32IXCHERI-NEXT:  .LBB39_4: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a1
-; RV32IXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs3, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s3, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_max_i8_seq_cst:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB39_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.b.aqrl a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.b.aqrl a2, (a0)
 ; RV32IAXCHERI-NEXT:    mv a3, a2
 ; RV32IAXCHERI-NEXT:    bge a3, a1, .LBB39_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB39_1 Depth=1
 ; RV32IAXCHERI-NEXT:    mv a3, a1
 ; RV32IAXCHERI-NEXT:  .LBB39_3: # in Loop: Header=BB39_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.b.aqrl a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.b.aqrl a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB39_1
 ; RV32IAXCHERI-NEXT:  # %bb.4:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -2206,29 +2206,29 @@ define i8 @atomicrmw_max_i8_seq_cst(i8 addrspace(200)* %a, i8 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_max_i8_seq_cst:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -96
-; RV64IXCHERI-NEXT:    csc cra, 80(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs3, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    mv s2, a1
-; RV64IXCHERI-NEXT:    cmove cs1, ca0
-; RV64IXCHERI-NEXT:    clbu a1, 0(ca0)
-; RV64IXCHERI-NEXT:    slli a0, s2, 56
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -96
+; RV64IXCHERI-NEXT:    csc ra, 80(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s3, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    mv s0, a1
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    clbu a1, 0(a0)
+; RV64IXCHERI-NEXT:    slli a0, s0, 56
 ; RV64IXCHERI-NEXT:    srai s3, a0, 56
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 15
-; RV64IXCHERI-NEXT:    csetbounds cs0, ca0, 1
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 15
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 1
 ; RV64IXCHERI-NEXT:    j .LBB39_2
 ; RV64IXCHERI-NEXT:  .LBB39_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB39_2 Depth=1
-; RV64IXCHERI-NEXT:    csb a1, 15(csp)
+; RV64IXCHERI-NEXT:    csb a1, 15(sp)
 ; RV64IXCHERI-NEXT:    li a3, 5
 ; RV64IXCHERI-NEXT:    li a4, 5
-; RV64IXCHERI-NEXT:    cmove ca0, cs1
-; RV64IXCHERI-NEXT:    cmove ca1, cs0
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_1
-; RV64IXCHERI-NEXT:    clb a1, 15(csp)
+; RV64IXCHERI-NEXT:    clb a1, 15(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB39_4
 ; RV64IXCHERI-NEXT:  .LBB39_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -2238,28 +2238,28 @@ define i8 @atomicrmw_max_i8_seq_cst(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV64IXCHERI-NEXT:    blt s3, a0, .LBB39_1
 ; RV64IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB39_2 Depth=1
-; RV64IXCHERI-NEXT:    mv a2, s2
+; RV64IXCHERI-NEXT:    mv a2, s0
 ; RV64IXCHERI-NEXT:    j .LBB39_1
 ; RV64IXCHERI-NEXT:  .LBB39_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 80(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs3, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 96
+; RV64IXCHERI-NEXT:    clc ra, 80(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s3, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 96
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_max_i8_seq_cst:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB39_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.b.aqrl a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.b.aqrl a2, (a0)
 ; RV64IAXCHERI-NEXT:    mv a3, a2
 ; RV64IAXCHERI-NEXT:    bge a3, a1, .LBB39_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB39_1 Depth=1
 ; RV64IAXCHERI-NEXT:    mv a3, a1
 ; RV64IAXCHERI-NEXT:  .LBB39_3: # in Loop: Header=BB39_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.b.aqrl a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.b.aqrl a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB39_1
 ; RV64IAXCHERI-NEXT:  # %bb.4:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -2271,29 +2271,29 @@ define i8 @atomicrmw_max_i8_seq_cst(i8 addrspace(200)* %a, i8 %b) nounwind {
 define i8 @atomicrmw_min_i8_monotonic(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_min_i8_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs3, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    mv s2, a1
-; RV32IXCHERI-NEXT:    cmove cs1, ca0
-; RV32IXCHERI-NEXT:    clbu a1, 0(ca0)
-; RV32IXCHERI-NEXT:    slli a0, s2, 24
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s3, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    mv s0, a1
+; RV32IXCHERI-NEXT:    cmove s1, a0
+; RV32IXCHERI-NEXT:    clbu a1, 0(a0)
+; RV32IXCHERI-NEXT:    slli a0, s0, 24
 ; RV32IXCHERI-NEXT:    srai s3, a0, 24
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 7
-; RV32IXCHERI-NEXT:    csetbounds cs0, ca0, 1
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 7
+; RV32IXCHERI-NEXT:    csetbounds s2, a0, 1
 ; RV32IXCHERI-NEXT:    j .LBB40_2
 ; RV32IXCHERI-NEXT:  .LBB40_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB40_2 Depth=1
-; RV32IXCHERI-NEXT:    csb a1, 7(csp)
-; RV32IXCHERI-NEXT:    cmove ca0, cs1
-; RV32IXCHERI-NEXT:    cmove ca1, cs0
+; RV32IXCHERI-NEXT:    csb a1, 7(sp)
+; RV32IXCHERI-NEXT:    cmove a0, s1
+; RV32IXCHERI-NEXT:    cmove a1, s2
 ; RV32IXCHERI-NEXT:    li a3, 0
 ; RV32IXCHERI-NEXT:    li a4, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_1
-; RV32IXCHERI-NEXT:    clb a1, 7(csp)
+; RV32IXCHERI-NEXT:    clb a1, 7(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB40_4
 ; RV32IXCHERI-NEXT:  .LBB40_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -2303,28 +2303,28 @@ define i8 @atomicrmw_min_i8_monotonic(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-NEXT:    bge s3, a0, .LBB40_1
 ; RV32IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB40_2 Depth=1
-; RV32IXCHERI-NEXT:    mv a2, s2
+; RV32IXCHERI-NEXT:    mv a2, s0
 ; RV32IXCHERI-NEXT:    j .LBB40_1
 ; RV32IXCHERI-NEXT:  .LBB40_4: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a1
-; RV32IXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs3, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s3, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_min_i8_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB40_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.b a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.b a2, (a0)
 ; RV32IAXCHERI-NEXT:    mv a3, a2
 ; RV32IAXCHERI-NEXT:    bge a1, a3, .LBB40_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB40_1 Depth=1
 ; RV32IAXCHERI-NEXT:    mv a3, a1
 ; RV32IAXCHERI-NEXT:  .LBB40_3: # in Loop: Header=BB40_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.b a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.b a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB40_1
 ; RV32IAXCHERI-NEXT:  # %bb.4:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -2332,29 +2332,29 @@ define i8 @atomicrmw_min_i8_monotonic(i8 addrspace(200)* %a, i8 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_min_i8_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -96
-; RV64IXCHERI-NEXT:    csc cra, 80(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs3, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    mv s2, a1
-; RV64IXCHERI-NEXT:    cmove cs1, ca0
-; RV64IXCHERI-NEXT:    clbu a1, 0(ca0)
-; RV64IXCHERI-NEXT:    slli a0, s2, 56
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -96
+; RV64IXCHERI-NEXT:    csc ra, 80(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s3, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    mv s0, a1
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    clbu a1, 0(a0)
+; RV64IXCHERI-NEXT:    slli a0, s0, 56
 ; RV64IXCHERI-NEXT:    srai s3, a0, 56
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 15
-; RV64IXCHERI-NEXT:    csetbounds cs0, ca0, 1
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 15
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 1
 ; RV64IXCHERI-NEXT:    j .LBB40_2
 ; RV64IXCHERI-NEXT:  .LBB40_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB40_2 Depth=1
-; RV64IXCHERI-NEXT:    csb a1, 15(csp)
-; RV64IXCHERI-NEXT:    cmove ca0, cs1
-; RV64IXCHERI-NEXT:    cmove ca1, cs0
+; RV64IXCHERI-NEXT:    csb a1, 15(sp)
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    li a3, 0
 ; RV64IXCHERI-NEXT:    li a4, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_1
-; RV64IXCHERI-NEXT:    clb a1, 15(csp)
+; RV64IXCHERI-NEXT:    clb a1, 15(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB40_4
 ; RV64IXCHERI-NEXT:  .LBB40_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -2364,28 +2364,28 @@ define i8 @atomicrmw_min_i8_monotonic(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV64IXCHERI-NEXT:    bge s3, a0, .LBB40_1
 ; RV64IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB40_2 Depth=1
-; RV64IXCHERI-NEXT:    mv a2, s2
+; RV64IXCHERI-NEXT:    mv a2, s0
 ; RV64IXCHERI-NEXT:    j .LBB40_1
 ; RV64IXCHERI-NEXT:  .LBB40_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 80(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs3, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 96
+; RV64IXCHERI-NEXT:    clc ra, 80(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s3, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 96
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_min_i8_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB40_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.b a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.b a2, (a0)
 ; RV64IAXCHERI-NEXT:    mv a3, a2
 ; RV64IAXCHERI-NEXT:    bge a1, a3, .LBB40_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB40_1 Depth=1
 ; RV64IAXCHERI-NEXT:    mv a3, a1
 ; RV64IAXCHERI-NEXT:  .LBB40_3: # in Loop: Header=BB40_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.b a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.b a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB40_1
 ; RV64IAXCHERI-NEXT:  # %bb.4:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -2397,29 +2397,29 @@ define i8 @atomicrmw_min_i8_monotonic(i8 addrspace(200)* %a, i8 %b) nounwind {
 define i8 @atomicrmw_min_i8_acquire(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_min_i8_acquire:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs3, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    mv s2, a1
-; RV32IXCHERI-NEXT:    cmove cs1, ca0
-; RV32IXCHERI-NEXT:    clbu a1, 0(ca0)
-; RV32IXCHERI-NEXT:    slli a0, s2, 24
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s3, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    mv s0, a1
+; RV32IXCHERI-NEXT:    cmove s1, a0
+; RV32IXCHERI-NEXT:    clbu a1, 0(a0)
+; RV32IXCHERI-NEXT:    slli a0, s0, 24
 ; RV32IXCHERI-NEXT:    srai s3, a0, 24
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 7
-; RV32IXCHERI-NEXT:    csetbounds cs0, ca0, 1
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 7
+; RV32IXCHERI-NEXT:    csetbounds s2, a0, 1
 ; RV32IXCHERI-NEXT:    j .LBB41_2
 ; RV32IXCHERI-NEXT:  .LBB41_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB41_2 Depth=1
-; RV32IXCHERI-NEXT:    csb a1, 7(csp)
+; RV32IXCHERI-NEXT:    csb a1, 7(sp)
 ; RV32IXCHERI-NEXT:    li a3, 2
 ; RV32IXCHERI-NEXT:    li a4, 2
-; RV32IXCHERI-NEXT:    cmove ca0, cs1
-; RV32IXCHERI-NEXT:    cmove ca1, cs0
+; RV32IXCHERI-NEXT:    cmove a0, s1
+; RV32IXCHERI-NEXT:    cmove a1, s2
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_1
-; RV32IXCHERI-NEXT:    clb a1, 7(csp)
+; RV32IXCHERI-NEXT:    clb a1, 7(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB41_4
 ; RV32IXCHERI-NEXT:  .LBB41_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -2429,28 +2429,28 @@ define i8 @atomicrmw_min_i8_acquire(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-NEXT:    bge s3, a0, .LBB41_1
 ; RV32IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB41_2 Depth=1
-; RV32IXCHERI-NEXT:    mv a2, s2
+; RV32IXCHERI-NEXT:    mv a2, s0
 ; RV32IXCHERI-NEXT:    j .LBB41_1
 ; RV32IXCHERI-NEXT:  .LBB41_4: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a1
-; RV32IXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs3, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s3, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_min_i8_acquire:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB41_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.b.aq a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.b.aq a2, (a0)
 ; RV32IAXCHERI-NEXT:    mv a3, a2
 ; RV32IAXCHERI-NEXT:    bge a1, a3, .LBB41_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB41_1 Depth=1
 ; RV32IAXCHERI-NEXT:    mv a3, a1
 ; RV32IAXCHERI-NEXT:  .LBB41_3: # in Loop: Header=BB41_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.b a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.b a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB41_1
 ; RV32IAXCHERI-NEXT:  # %bb.4:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -2458,29 +2458,29 @@ define i8 @atomicrmw_min_i8_acquire(i8 addrspace(200)* %a, i8 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_min_i8_acquire:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -96
-; RV64IXCHERI-NEXT:    csc cra, 80(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs3, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    mv s2, a1
-; RV64IXCHERI-NEXT:    cmove cs1, ca0
-; RV64IXCHERI-NEXT:    clbu a1, 0(ca0)
-; RV64IXCHERI-NEXT:    slli a0, s2, 56
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -96
+; RV64IXCHERI-NEXT:    csc ra, 80(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s3, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    mv s0, a1
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    clbu a1, 0(a0)
+; RV64IXCHERI-NEXT:    slli a0, s0, 56
 ; RV64IXCHERI-NEXT:    srai s3, a0, 56
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 15
-; RV64IXCHERI-NEXT:    csetbounds cs0, ca0, 1
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 15
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 1
 ; RV64IXCHERI-NEXT:    j .LBB41_2
 ; RV64IXCHERI-NEXT:  .LBB41_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB41_2 Depth=1
-; RV64IXCHERI-NEXT:    csb a1, 15(csp)
+; RV64IXCHERI-NEXT:    csb a1, 15(sp)
 ; RV64IXCHERI-NEXT:    li a3, 2
 ; RV64IXCHERI-NEXT:    li a4, 2
-; RV64IXCHERI-NEXT:    cmove ca0, cs1
-; RV64IXCHERI-NEXT:    cmove ca1, cs0
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_1
-; RV64IXCHERI-NEXT:    clb a1, 15(csp)
+; RV64IXCHERI-NEXT:    clb a1, 15(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB41_4
 ; RV64IXCHERI-NEXT:  .LBB41_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -2490,28 +2490,28 @@ define i8 @atomicrmw_min_i8_acquire(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV64IXCHERI-NEXT:    bge s3, a0, .LBB41_1
 ; RV64IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB41_2 Depth=1
-; RV64IXCHERI-NEXT:    mv a2, s2
+; RV64IXCHERI-NEXT:    mv a2, s0
 ; RV64IXCHERI-NEXT:    j .LBB41_1
 ; RV64IXCHERI-NEXT:  .LBB41_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 80(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs3, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 96
+; RV64IXCHERI-NEXT:    clc ra, 80(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s3, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 96
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_min_i8_acquire:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB41_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.b.aq a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.b.aq a2, (a0)
 ; RV64IAXCHERI-NEXT:    mv a3, a2
 ; RV64IAXCHERI-NEXT:    bge a1, a3, .LBB41_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB41_1 Depth=1
 ; RV64IAXCHERI-NEXT:    mv a3, a1
 ; RV64IAXCHERI-NEXT:  .LBB41_3: # in Loop: Header=BB41_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.b a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.b a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB41_1
 ; RV64IAXCHERI-NEXT:  # %bb.4:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -2523,29 +2523,29 @@ define i8 @atomicrmw_min_i8_acquire(i8 addrspace(200)* %a, i8 %b) nounwind {
 define i8 @atomicrmw_min_i8_release(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_min_i8_release:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs3, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    mv s2, a1
-; RV32IXCHERI-NEXT:    cmove cs1, ca0
-; RV32IXCHERI-NEXT:    clbu a1, 0(ca0)
-; RV32IXCHERI-NEXT:    slli a0, s2, 24
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s3, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    mv s0, a1
+; RV32IXCHERI-NEXT:    cmove s1, a0
+; RV32IXCHERI-NEXT:    clbu a1, 0(a0)
+; RV32IXCHERI-NEXT:    slli a0, s0, 24
 ; RV32IXCHERI-NEXT:    srai s3, a0, 24
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 7
-; RV32IXCHERI-NEXT:    csetbounds cs0, ca0, 1
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 7
+; RV32IXCHERI-NEXT:    csetbounds s2, a0, 1
 ; RV32IXCHERI-NEXT:    j .LBB42_2
 ; RV32IXCHERI-NEXT:  .LBB42_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB42_2 Depth=1
-; RV32IXCHERI-NEXT:    csb a1, 7(csp)
+; RV32IXCHERI-NEXT:    csb a1, 7(sp)
 ; RV32IXCHERI-NEXT:    li a3, 3
-; RV32IXCHERI-NEXT:    cmove ca0, cs1
-; RV32IXCHERI-NEXT:    cmove ca1, cs0
+; RV32IXCHERI-NEXT:    cmove a0, s1
+; RV32IXCHERI-NEXT:    cmove a1, s2
 ; RV32IXCHERI-NEXT:    li a4, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_1
-; RV32IXCHERI-NEXT:    clb a1, 7(csp)
+; RV32IXCHERI-NEXT:    clb a1, 7(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB42_4
 ; RV32IXCHERI-NEXT:  .LBB42_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -2555,28 +2555,28 @@ define i8 @atomicrmw_min_i8_release(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-NEXT:    bge s3, a0, .LBB42_1
 ; RV32IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB42_2 Depth=1
-; RV32IXCHERI-NEXT:    mv a2, s2
+; RV32IXCHERI-NEXT:    mv a2, s0
 ; RV32IXCHERI-NEXT:    j .LBB42_1
 ; RV32IXCHERI-NEXT:  .LBB42_4: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a1
-; RV32IXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs3, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s3, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_min_i8_release:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB42_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.b a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.b a2, (a0)
 ; RV32IAXCHERI-NEXT:    mv a3, a2
 ; RV32IAXCHERI-NEXT:    bge a1, a3, .LBB42_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB42_1 Depth=1
 ; RV32IAXCHERI-NEXT:    mv a3, a1
 ; RV32IAXCHERI-NEXT:  .LBB42_3: # in Loop: Header=BB42_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.b.rl a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.b.rl a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB42_1
 ; RV32IAXCHERI-NEXT:  # %bb.4:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -2584,29 +2584,29 @@ define i8 @atomicrmw_min_i8_release(i8 addrspace(200)* %a, i8 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_min_i8_release:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -96
-; RV64IXCHERI-NEXT:    csc cra, 80(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs3, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    mv s2, a1
-; RV64IXCHERI-NEXT:    cmove cs1, ca0
-; RV64IXCHERI-NEXT:    clbu a1, 0(ca0)
-; RV64IXCHERI-NEXT:    slli a0, s2, 56
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -96
+; RV64IXCHERI-NEXT:    csc ra, 80(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s3, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    mv s0, a1
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    clbu a1, 0(a0)
+; RV64IXCHERI-NEXT:    slli a0, s0, 56
 ; RV64IXCHERI-NEXT:    srai s3, a0, 56
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 15
-; RV64IXCHERI-NEXT:    csetbounds cs0, ca0, 1
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 15
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 1
 ; RV64IXCHERI-NEXT:    j .LBB42_2
 ; RV64IXCHERI-NEXT:  .LBB42_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB42_2 Depth=1
-; RV64IXCHERI-NEXT:    csb a1, 15(csp)
+; RV64IXCHERI-NEXT:    csb a1, 15(sp)
 ; RV64IXCHERI-NEXT:    li a3, 3
-; RV64IXCHERI-NEXT:    cmove ca0, cs1
-; RV64IXCHERI-NEXT:    cmove ca1, cs0
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    li a4, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_1
-; RV64IXCHERI-NEXT:    clb a1, 15(csp)
+; RV64IXCHERI-NEXT:    clb a1, 15(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB42_4
 ; RV64IXCHERI-NEXT:  .LBB42_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -2616,28 +2616,28 @@ define i8 @atomicrmw_min_i8_release(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV64IXCHERI-NEXT:    bge s3, a0, .LBB42_1
 ; RV64IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB42_2 Depth=1
-; RV64IXCHERI-NEXT:    mv a2, s2
+; RV64IXCHERI-NEXT:    mv a2, s0
 ; RV64IXCHERI-NEXT:    j .LBB42_1
 ; RV64IXCHERI-NEXT:  .LBB42_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 80(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs3, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 96
+; RV64IXCHERI-NEXT:    clc ra, 80(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s3, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 96
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_min_i8_release:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB42_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.b a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.b a2, (a0)
 ; RV64IAXCHERI-NEXT:    mv a3, a2
 ; RV64IAXCHERI-NEXT:    bge a1, a3, .LBB42_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB42_1 Depth=1
 ; RV64IAXCHERI-NEXT:    mv a3, a1
 ; RV64IAXCHERI-NEXT:  .LBB42_3: # in Loop: Header=BB42_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.b.rl a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.b.rl a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB42_1
 ; RV64IAXCHERI-NEXT:  # %bb.4:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -2649,29 +2649,29 @@ define i8 @atomicrmw_min_i8_release(i8 addrspace(200)* %a, i8 %b) nounwind {
 define i8 @atomicrmw_min_i8_acq_rel(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_min_i8_acq_rel:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs3, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    mv s2, a1
-; RV32IXCHERI-NEXT:    cmove cs1, ca0
-; RV32IXCHERI-NEXT:    clbu a1, 0(ca0)
-; RV32IXCHERI-NEXT:    slli a0, s2, 24
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s3, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    mv s0, a1
+; RV32IXCHERI-NEXT:    cmove s1, a0
+; RV32IXCHERI-NEXT:    clbu a1, 0(a0)
+; RV32IXCHERI-NEXT:    slli a0, s0, 24
 ; RV32IXCHERI-NEXT:    srai s3, a0, 24
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 7
-; RV32IXCHERI-NEXT:    csetbounds cs0, ca0, 1
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 7
+; RV32IXCHERI-NEXT:    csetbounds s2, a0, 1
 ; RV32IXCHERI-NEXT:    j .LBB43_2
 ; RV32IXCHERI-NEXT:  .LBB43_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB43_2 Depth=1
-; RV32IXCHERI-NEXT:    csb a1, 7(csp)
+; RV32IXCHERI-NEXT:    csb a1, 7(sp)
 ; RV32IXCHERI-NEXT:    li a3, 4
 ; RV32IXCHERI-NEXT:    li a4, 2
-; RV32IXCHERI-NEXT:    cmove ca0, cs1
-; RV32IXCHERI-NEXT:    cmove ca1, cs0
+; RV32IXCHERI-NEXT:    cmove a0, s1
+; RV32IXCHERI-NEXT:    cmove a1, s2
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_1
-; RV32IXCHERI-NEXT:    clb a1, 7(csp)
+; RV32IXCHERI-NEXT:    clb a1, 7(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB43_4
 ; RV32IXCHERI-NEXT:  .LBB43_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -2681,28 +2681,28 @@ define i8 @atomicrmw_min_i8_acq_rel(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-NEXT:    bge s3, a0, .LBB43_1
 ; RV32IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB43_2 Depth=1
-; RV32IXCHERI-NEXT:    mv a2, s2
+; RV32IXCHERI-NEXT:    mv a2, s0
 ; RV32IXCHERI-NEXT:    j .LBB43_1
 ; RV32IXCHERI-NEXT:  .LBB43_4: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a1
-; RV32IXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs3, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s3, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_min_i8_acq_rel:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB43_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.b.aq a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.b.aq a2, (a0)
 ; RV32IAXCHERI-NEXT:    mv a3, a2
 ; RV32IAXCHERI-NEXT:    bge a1, a3, .LBB43_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB43_1 Depth=1
 ; RV32IAXCHERI-NEXT:    mv a3, a1
 ; RV32IAXCHERI-NEXT:  .LBB43_3: # in Loop: Header=BB43_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.b.rl a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.b.rl a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB43_1
 ; RV32IAXCHERI-NEXT:  # %bb.4:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -2710,29 +2710,29 @@ define i8 @atomicrmw_min_i8_acq_rel(i8 addrspace(200)* %a, i8 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_min_i8_acq_rel:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -96
-; RV64IXCHERI-NEXT:    csc cra, 80(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs3, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    mv s2, a1
-; RV64IXCHERI-NEXT:    cmove cs1, ca0
-; RV64IXCHERI-NEXT:    clbu a1, 0(ca0)
-; RV64IXCHERI-NEXT:    slli a0, s2, 56
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -96
+; RV64IXCHERI-NEXT:    csc ra, 80(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s3, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    mv s0, a1
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    clbu a1, 0(a0)
+; RV64IXCHERI-NEXT:    slli a0, s0, 56
 ; RV64IXCHERI-NEXT:    srai s3, a0, 56
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 15
-; RV64IXCHERI-NEXT:    csetbounds cs0, ca0, 1
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 15
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 1
 ; RV64IXCHERI-NEXT:    j .LBB43_2
 ; RV64IXCHERI-NEXT:  .LBB43_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB43_2 Depth=1
-; RV64IXCHERI-NEXT:    csb a1, 15(csp)
+; RV64IXCHERI-NEXT:    csb a1, 15(sp)
 ; RV64IXCHERI-NEXT:    li a3, 4
 ; RV64IXCHERI-NEXT:    li a4, 2
-; RV64IXCHERI-NEXT:    cmove ca0, cs1
-; RV64IXCHERI-NEXT:    cmove ca1, cs0
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_1
-; RV64IXCHERI-NEXT:    clb a1, 15(csp)
+; RV64IXCHERI-NEXT:    clb a1, 15(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB43_4
 ; RV64IXCHERI-NEXT:  .LBB43_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -2742,28 +2742,28 @@ define i8 @atomicrmw_min_i8_acq_rel(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV64IXCHERI-NEXT:    bge s3, a0, .LBB43_1
 ; RV64IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB43_2 Depth=1
-; RV64IXCHERI-NEXT:    mv a2, s2
+; RV64IXCHERI-NEXT:    mv a2, s0
 ; RV64IXCHERI-NEXT:    j .LBB43_1
 ; RV64IXCHERI-NEXT:  .LBB43_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 80(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs3, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 96
+; RV64IXCHERI-NEXT:    clc ra, 80(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s3, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 96
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_min_i8_acq_rel:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB43_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.b.aq a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.b.aq a2, (a0)
 ; RV64IAXCHERI-NEXT:    mv a3, a2
 ; RV64IAXCHERI-NEXT:    bge a1, a3, .LBB43_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB43_1 Depth=1
 ; RV64IAXCHERI-NEXT:    mv a3, a1
 ; RV64IAXCHERI-NEXT:  .LBB43_3: # in Loop: Header=BB43_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.b.rl a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.b.rl a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB43_1
 ; RV64IAXCHERI-NEXT:  # %bb.4:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -2775,29 +2775,29 @@ define i8 @atomicrmw_min_i8_acq_rel(i8 addrspace(200)* %a, i8 %b) nounwind {
 define i8 @atomicrmw_min_i8_seq_cst(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_min_i8_seq_cst:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs3, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    mv s2, a1
-; RV32IXCHERI-NEXT:    cmove cs1, ca0
-; RV32IXCHERI-NEXT:    clbu a1, 0(ca0)
-; RV32IXCHERI-NEXT:    slli a0, s2, 24
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s3, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    mv s0, a1
+; RV32IXCHERI-NEXT:    cmove s1, a0
+; RV32IXCHERI-NEXT:    clbu a1, 0(a0)
+; RV32IXCHERI-NEXT:    slli a0, s0, 24
 ; RV32IXCHERI-NEXT:    srai s3, a0, 24
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 7
-; RV32IXCHERI-NEXT:    csetbounds cs0, ca0, 1
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 7
+; RV32IXCHERI-NEXT:    csetbounds s2, a0, 1
 ; RV32IXCHERI-NEXT:    j .LBB44_2
 ; RV32IXCHERI-NEXT:  .LBB44_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB44_2 Depth=1
-; RV32IXCHERI-NEXT:    csb a1, 7(csp)
+; RV32IXCHERI-NEXT:    csb a1, 7(sp)
 ; RV32IXCHERI-NEXT:    li a3, 5
 ; RV32IXCHERI-NEXT:    li a4, 5
-; RV32IXCHERI-NEXT:    cmove ca0, cs1
-; RV32IXCHERI-NEXT:    cmove ca1, cs0
+; RV32IXCHERI-NEXT:    cmove a0, s1
+; RV32IXCHERI-NEXT:    cmove a1, s2
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_1
-; RV32IXCHERI-NEXT:    clb a1, 7(csp)
+; RV32IXCHERI-NEXT:    clb a1, 7(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB44_4
 ; RV32IXCHERI-NEXT:  .LBB44_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -2807,28 +2807,28 @@ define i8 @atomicrmw_min_i8_seq_cst(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-NEXT:    bge s3, a0, .LBB44_1
 ; RV32IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB44_2 Depth=1
-; RV32IXCHERI-NEXT:    mv a2, s2
+; RV32IXCHERI-NEXT:    mv a2, s0
 ; RV32IXCHERI-NEXT:    j .LBB44_1
 ; RV32IXCHERI-NEXT:  .LBB44_4: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a1
-; RV32IXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs3, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s3, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_min_i8_seq_cst:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB44_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.b.aqrl a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.b.aqrl a2, (a0)
 ; RV32IAXCHERI-NEXT:    mv a3, a2
 ; RV32IAXCHERI-NEXT:    bge a1, a3, .LBB44_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB44_1 Depth=1
 ; RV32IAXCHERI-NEXT:    mv a3, a1
 ; RV32IAXCHERI-NEXT:  .LBB44_3: # in Loop: Header=BB44_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.b.aqrl a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.b.aqrl a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB44_1
 ; RV32IAXCHERI-NEXT:  # %bb.4:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -2836,29 +2836,29 @@ define i8 @atomicrmw_min_i8_seq_cst(i8 addrspace(200)* %a, i8 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_min_i8_seq_cst:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -96
-; RV64IXCHERI-NEXT:    csc cra, 80(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs3, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    mv s2, a1
-; RV64IXCHERI-NEXT:    cmove cs1, ca0
-; RV64IXCHERI-NEXT:    clbu a1, 0(ca0)
-; RV64IXCHERI-NEXT:    slli a0, s2, 56
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -96
+; RV64IXCHERI-NEXT:    csc ra, 80(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s3, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    mv s0, a1
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    clbu a1, 0(a0)
+; RV64IXCHERI-NEXT:    slli a0, s0, 56
 ; RV64IXCHERI-NEXT:    srai s3, a0, 56
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 15
-; RV64IXCHERI-NEXT:    csetbounds cs0, ca0, 1
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 15
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 1
 ; RV64IXCHERI-NEXT:    j .LBB44_2
 ; RV64IXCHERI-NEXT:  .LBB44_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB44_2 Depth=1
-; RV64IXCHERI-NEXT:    csb a1, 15(csp)
+; RV64IXCHERI-NEXT:    csb a1, 15(sp)
 ; RV64IXCHERI-NEXT:    li a3, 5
 ; RV64IXCHERI-NEXT:    li a4, 5
-; RV64IXCHERI-NEXT:    cmove ca0, cs1
-; RV64IXCHERI-NEXT:    cmove ca1, cs0
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_1
-; RV64IXCHERI-NEXT:    clb a1, 15(csp)
+; RV64IXCHERI-NEXT:    clb a1, 15(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB44_4
 ; RV64IXCHERI-NEXT:  .LBB44_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -2868,28 +2868,28 @@ define i8 @atomicrmw_min_i8_seq_cst(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV64IXCHERI-NEXT:    bge s3, a0, .LBB44_1
 ; RV64IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB44_2 Depth=1
-; RV64IXCHERI-NEXT:    mv a2, s2
+; RV64IXCHERI-NEXT:    mv a2, s0
 ; RV64IXCHERI-NEXT:    j .LBB44_1
 ; RV64IXCHERI-NEXT:  .LBB44_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 80(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs3, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 96
+; RV64IXCHERI-NEXT:    clc ra, 80(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s3, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 96
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_min_i8_seq_cst:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB44_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.b.aqrl a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.b.aqrl a2, (a0)
 ; RV64IAXCHERI-NEXT:    mv a3, a2
 ; RV64IAXCHERI-NEXT:    bge a1, a3, .LBB44_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB44_1 Depth=1
 ; RV64IAXCHERI-NEXT:    mv a3, a1
 ; RV64IAXCHERI-NEXT:  .LBB44_3: # in Loop: Header=BB44_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.b.aqrl a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.b.aqrl a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB44_1
 ; RV64IAXCHERI-NEXT:  # %bb.4:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -2901,28 +2901,28 @@ define i8 @atomicrmw_min_i8_seq_cst(i8 addrspace(200)* %a, i8 %b) nounwind {
 define i8 @atomicrmw_umax_i8_monotonic(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_umax_i8_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs3, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    mv s2, a1
-; RV32IXCHERI-NEXT:    cmove cs1, ca0
-; RV32IXCHERI-NEXT:    clbu a1, 0(ca0)
-; RV32IXCHERI-NEXT:    zext.b s3, s2
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 7
-; RV32IXCHERI-NEXT:    csetbounds cs0, ca0, 1
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s3, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    mv s0, a1
+; RV32IXCHERI-NEXT:    cmove s1, a0
+; RV32IXCHERI-NEXT:    clbu a1, 0(a0)
+; RV32IXCHERI-NEXT:    zext.b s3, s0
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 7
+; RV32IXCHERI-NEXT:    csetbounds s2, a0, 1
 ; RV32IXCHERI-NEXT:    j .LBB45_2
 ; RV32IXCHERI-NEXT:  .LBB45_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB45_2 Depth=1
-; RV32IXCHERI-NEXT:    csb a1, 7(csp)
-; RV32IXCHERI-NEXT:    cmove ca0, cs1
-; RV32IXCHERI-NEXT:    cmove ca1, cs0
+; RV32IXCHERI-NEXT:    csb a1, 7(sp)
+; RV32IXCHERI-NEXT:    cmove a0, s1
+; RV32IXCHERI-NEXT:    cmove a1, s2
 ; RV32IXCHERI-NEXT:    li a3, 0
 ; RV32IXCHERI-NEXT:    li a4, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_1
-; RV32IXCHERI-NEXT:    clb a1, 7(csp)
+; RV32IXCHERI-NEXT:    clb a1, 7(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB45_4
 ; RV32IXCHERI-NEXT:  .LBB45_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -2931,28 +2931,28 @@ define i8 @atomicrmw_umax_i8_monotonic(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-NEXT:    bltu s3, a0, .LBB45_1
 ; RV32IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB45_2 Depth=1
-; RV32IXCHERI-NEXT:    mv a2, s2
+; RV32IXCHERI-NEXT:    mv a2, s0
 ; RV32IXCHERI-NEXT:    j .LBB45_1
 ; RV32IXCHERI-NEXT:  .LBB45_4: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a1
-; RV32IXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs3, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s3, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_umax_i8_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB45_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.b a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.b a2, (a0)
 ; RV32IAXCHERI-NEXT:    mv a3, a2
 ; RV32IAXCHERI-NEXT:    bgeu a3, a1, .LBB45_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB45_1 Depth=1
 ; RV32IAXCHERI-NEXT:    mv a3, a1
 ; RV32IAXCHERI-NEXT:  .LBB45_3: # in Loop: Header=BB45_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.b a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.b a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB45_1
 ; RV32IAXCHERI-NEXT:  # %bb.4:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -2960,28 +2960,28 @@ define i8 @atomicrmw_umax_i8_monotonic(i8 addrspace(200)* %a, i8 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_umax_i8_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -96
-; RV64IXCHERI-NEXT:    csc cra, 80(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs3, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    mv s2, a1
-; RV64IXCHERI-NEXT:    cmove cs1, ca0
-; RV64IXCHERI-NEXT:    clbu a1, 0(ca0)
-; RV64IXCHERI-NEXT:    zext.b s3, s2
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 15
-; RV64IXCHERI-NEXT:    csetbounds cs0, ca0, 1
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -96
+; RV64IXCHERI-NEXT:    csc ra, 80(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s3, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    mv s0, a1
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    clbu a1, 0(a0)
+; RV64IXCHERI-NEXT:    zext.b s3, s0
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 15
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 1
 ; RV64IXCHERI-NEXT:    j .LBB45_2
 ; RV64IXCHERI-NEXT:  .LBB45_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB45_2 Depth=1
-; RV64IXCHERI-NEXT:    csb a1, 15(csp)
-; RV64IXCHERI-NEXT:    cmove ca0, cs1
-; RV64IXCHERI-NEXT:    cmove ca1, cs0
+; RV64IXCHERI-NEXT:    csb a1, 15(sp)
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    li a3, 0
 ; RV64IXCHERI-NEXT:    li a4, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_1
-; RV64IXCHERI-NEXT:    clb a1, 15(csp)
+; RV64IXCHERI-NEXT:    clb a1, 15(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB45_4
 ; RV64IXCHERI-NEXT:  .LBB45_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -2990,28 +2990,28 @@ define i8 @atomicrmw_umax_i8_monotonic(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV64IXCHERI-NEXT:    bltu s3, a0, .LBB45_1
 ; RV64IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB45_2 Depth=1
-; RV64IXCHERI-NEXT:    mv a2, s2
+; RV64IXCHERI-NEXT:    mv a2, s0
 ; RV64IXCHERI-NEXT:    j .LBB45_1
 ; RV64IXCHERI-NEXT:  .LBB45_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 80(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs3, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 96
+; RV64IXCHERI-NEXT:    clc ra, 80(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s3, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 96
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_umax_i8_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB45_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.b a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.b a2, (a0)
 ; RV64IAXCHERI-NEXT:    mv a3, a2
 ; RV64IAXCHERI-NEXT:    bgeu a3, a1, .LBB45_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB45_1 Depth=1
 ; RV64IAXCHERI-NEXT:    mv a3, a1
 ; RV64IAXCHERI-NEXT:  .LBB45_3: # in Loop: Header=BB45_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.b a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.b a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB45_1
 ; RV64IAXCHERI-NEXT:  # %bb.4:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -3023,28 +3023,28 @@ define i8 @atomicrmw_umax_i8_monotonic(i8 addrspace(200)* %a, i8 %b) nounwind {
 define i8 @atomicrmw_umax_i8_acquire(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_umax_i8_acquire:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs3, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    mv s2, a1
-; RV32IXCHERI-NEXT:    cmove cs1, ca0
-; RV32IXCHERI-NEXT:    clbu a1, 0(ca0)
-; RV32IXCHERI-NEXT:    zext.b s3, s2
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 7
-; RV32IXCHERI-NEXT:    csetbounds cs0, ca0, 1
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s3, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    mv s0, a1
+; RV32IXCHERI-NEXT:    cmove s1, a0
+; RV32IXCHERI-NEXT:    clbu a1, 0(a0)
+; RV32IXCHERI-NEXT:    zext.b s3, s0
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 7
+; RV32IXCHERI-NEXT:    csetbounds s2, a0, 1
 ; RV32IXCHERI-NEXT:    j .LBB46_2
 ; RV32IXCHERI-NEXT:  .LBB46_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB46_2 Depth=1
-; RV32IXCHERI-NEXT:    csb a1, 7(csp)
+; RV32IXCHERI-NEXT:    csb a1, 7(sp)
 ; RV32IXCHERI-NEXT:    li a3, 2
 ; RV32IXCHERI-NEXT:    li a4, 2
-; RV32IXCHERI-NEXT:    cmove ca0, cs1
-; RV32IXCHERI-NEXT:    cmove ca1, cs0
+; RV32IXCHERI-NEXT:    cmove a0, s1
+; RV32IXCHERI-NEXT:    cmove a1, s2
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_1
-; RV32IXCHERI-NEXT:    clb a1, 7(csp)
+; RV32IXCHERI-NEXT:    clb a1, 7(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB46_4
 ; RV32IXCHERI-NEXT:  .LBB46_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -3053,28 +3053,28 @@ define i8 @atomicrmw_umax_i8_acquire(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-NEXT:    bltu s3, a0, .LBB46_1
 ; RV32IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB46_2 Depth=1
-; RV32IXCHERI-NEXT:    mv a2, s2
+; RV32IXCHERI-NEXT:    mv a2, s0
 ; RV32IXCHERI-NEXT:    j .LBB46_1
 ; RV32IXCHERI-NEXT:  .LBB46_4: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a1
-; RV32IXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs3, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s3, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_umax_i8_acquire:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB46_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.b.aq a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.b.aq a2, (a0)
 ; RV32IAXCHERI-NEXT:    mv a3, a2
 ; RV32IAXCHERI-NEXT:    bgeu a3, a1, .LBB46_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB46_1 Depth=1
 ; RV32IAXCHERI-NEXT:    mv a3, a1
 ; RV32IAXCHERI-NEXT:  .LBB46_3: # in Loop: Header=BB46_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.b a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.b a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB46_1
 ; RV32IAXCHERI-NEXT:  # %bb.4:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -3082,28 +3082,28 @@ define i8 @atomicrmw_umax_i8_acquire(i8 addrspace(200)* %a, i8 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_umax_i8_acquire:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -96
-; RV64IXCHERI-NEXT:    csc cra, 80(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs3, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    mv s2, a1
-; RV64IXCHERI-NEXT:    cmove cs1, ca0
-; RV64IXCHERI-NEXT:    clbu a1, 0(ca0)
-; RV64IXCHERI-NEXT:    zext.b s3, s2
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 15
-; RV64IXCHERI-NEXT:    csetbounds cs0, ca0, 1
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -96
+; RV64IXCHERI-NEXT:    csc ra, 80(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s3, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    mv s0, a1
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    clbu a1, 0(a0)
+; RV64IXCHERI-NEXT:    zext.b s3, s0
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 15
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 1
 ; RV64IXCHERI-NEXT:    j .LBB46_2
 ; RV64IXCHERI-NEXT:  .LBB46_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB46_2 Depth=1
-; RV64IXCHERI-NEXT:    csb a1, 15(csp)
+; RV64IXCHERI-NEXT:    csb a1, 15(sp)
 ; RV64IXCHERI-NEXT:    li a3, 2
 ; RV64IXCHERI-NEXT:    li a4, 2
-; RV64IXCHERI-NEXT:    cmove ca0, cs1
-; RV64IXCHERI-NEXT:    cmove ca1, cs0
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_1
-; RV64IXCHERI-NEXT:    clb a1, 15(csp)
+; RV64IXCHERI-NEXT:    clb a1, 15(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB46_4
 ; RV64IXCHERI-NEXT:  .LBB46_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -3112,28 +3112,28 @@ define i8 @atomicrmw_umax_i8_acquire(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV64IXCHERI-NEXT:    bltu s3, a0, .LBB46_1
 ; RV64IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB46_2 Depth=1
-; RV64IXCHERI-NEXT:    mv a2, s2
+; RV64IXCHERI-NEXT:    mv a2, s0
 ; RV64IXCHERI-NEXT:    j .LBB46_1
 ; RV64IXCHERI-NEXT:  .LBB46_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 80(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs3, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 96
+; RV64IXCHERI-NEXT:    clc ra, 80(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s3, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 96
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_umax_i8_acquire:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB46_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.b.aq a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.b.aq a2, (a0)
 ; RV64IAXCHERI-NEXT:    mv a3, a2
 ; RV64IAXCHERI-NEXT:    bgeu a3, a1, .LBB46_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB46_1 Depth=1
 ; RV64IAXCHERI-NEXT:    mv a3, a1
 ; RV64IAXCHERI-NEXT:  .LBB46_3: # in Loop: Header=BB46_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.b a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.b a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB46_1
 ; RV64IAXCHERI-NEXT:  # %bb.4:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -3145,28 +3145,28 @@ define i8 @atomicrmw_umax_i8_acquire(i8 addrspace(200)* %a, i8 %b) nounwind {
 define i8 @atomicrmw_umax_i8_release(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_umax_i8_release:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs3, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    mv s2, a1
-; RV32IXCHERI-NEXT:    cmove cs1, ca0
-; RV32IXCHERI-NEXT:    clbu a1, 0(ca0)
-; RV32IXCHERI-NEXT:    zext.b s3, s2
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 7
-; RV32IXCHERI-NEXT:    csetbounds cs0, ca0, 1
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s3, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    mv s0, a1
+; RV32IXCHERI-NEXT:    cmove s1, a0
+; RV32IXCHERI-NEXT:    clbu a1, 0(a0)
+; RV32IXCHERI-NEXT:    zext.b s3, s0
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 7
+; RV32IXCHERI-NEXT:    csetbounds s2, a0, 1
 ; RV32IXCHERI-NEXT:    j .LBB47_2
 ; RV32IXCHERI-NEXT:  .LBB47_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB47_2 Depth=1
-; RV32IXCHERI-NEXT:    csb a1, 7(csp)
+; RV32IXCHERI-NEXT:    csb a1, 7(sp)
 ; RV32IXCHERI-NEXT:    li a3, 3
-; RV32IXCHERI-NEXT:    cmove ca0, cs1
-; RV32IXCHERI-NEXT:    cmove ca1, cs0
+; RV32IXCHERI-NEXT:    cmove a0, s1
+; RV32IXCHERI-NEXT:    cmove a1, s2
 ; RV32IXCHERI-NEXT:    li a4, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_1
-; RV32IXCHERI-NEXT:    clb a1, 7(csp)
+; RV32IXCHERI-NEXT:    clb a1, 7(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB47_4
 ; RV32IXCHERI-NEXT:  .LBB47_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -3175,28 +3175,28 @@ define i8 @atomicrmw_umax_i8_release(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-NEXT:    bltu s3, a0, .LBB47_1
 ; RV32IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB47_2 Depth=1
-; RV32IXCHERI-NEXT:    mv a2, s2
+; RV32IXCHERI-NEXT:    mv a2, s0
 ; RV32IXCHERI-NEXT:    j .LBB47_1
 ; RV32IXCHERI-NEXT:  .LBB47_4: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a1
-; RV32IXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs3, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s3, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_umax_i8_release:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB47_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.b a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.b a2, (a0)
 ; RV32IAXCHERI-NEXT:    mv a3, a2
 ; RV32IAXCHERI-NEXT:    bgeu a3, a1, .LBB47_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB47_1 Depth=1
 ; RV32IAXCHERI-NEXT:    mv a3, a1
 ; RV32IAXCHERI-NEXT:  .LBB47_3: # in Loop: Header=BB47_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.b.rl a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.b.rl a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB47_1
 ; RV32IAXCHERI-NEXT:  # %bb.4:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -3204,28 +3204,28 @@ define i8 @atomicrmw_umax_i8_release(i8 addrspace(200)* %a, i8 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_umax_i8_release:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -96
-; RV64IXCHERI-NEXT:    csc cra, 80(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs3, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    mv s2, a1
-; RV64IXCHERI-NEXT:    cmove cs1, ca0
-; RV64IXCHERI-NEXT:    clbu a1, 0(ca0)
-; RV64IXCHERI-NEXT:    zext.b s3, s2
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 15
-; RV64IXCHERI-NEXT:    csetbounds cs0, ca0, 1
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -96
+; RV64IXCHERI-NEXT:    csc ra, 80(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s3, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    mv s0, a1
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    clbu a1, 0(a0)
+; RV64IXCHERI-NEXT:    zext.b s3, s0
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 15
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 1
 ; RV64IXCHERI-NEXT:    j .LBB47_2
 ; RV64IXCHERI-NEXT:  .LBB47_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB47_2 Depth=1
-; RV64IXCHERI-NEXT:    csb a1, 15(csp)
+; RV64IXCHERI-NEXT:    csb a1, 15(sp)
 ; RV64IXCHERI-NEXT:    li a3, 3
-; RV64IXCHERI-NEXT:    cmove ca0, cs1
-; RV64IXCHERI-NEXT:    cmove ca1, cs0
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    li a4, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_1
-; RV64IXCHERI-NEXT:    clb a1, 15(csp)
+; RV64IXCHERI-NEXT:    clb a1, 15(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB47_4
 ; RV64IXCHERI-NEXT:  .LBB47_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -3234,28 +3234,28 @@ define i8 @atomicrmw_umax_i8_release(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV64IXCHERI-NEXT:    bltu s3, a0, .LBB47_1
 ; RV64IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB47_2 Depth=1
-; RV64IXCHERI-NEXT:    mv a2, s2
+; RV64IXCHERI-NEXT:    mv a2, s0
 ; RV64IXCHERI-NEXT:    j .LBB47_1
 ; RV64IXCHERI-NEXT:  .LBB47_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 80(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs3, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 96
+; RV64IXCHERI-NEXT:    clc ra, 80(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s3, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 96
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_umax_i8_release:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB47_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.b a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.b a2, (a0)
 ; RV64IAXCHERI-NEXT:    mv a3, a2
 ; RV64IAXCHERI-NEXT:    bgeu a3, a1, .LBB47_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB47_1 Depth=1
 ; RV64IAXCHERI-NEXT:    mv a3, a1
 ; RV64IAXCHERI-NEXT:  .LBB47_3: # in Loop: Header=BB47_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.b.rl a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.b.rl a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB47_1
 ; RV64IAXCHERI-NEXT:  # %bb.4:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -3267,28 +3267,28 @@ define i8 @atomicrmw_umax_i8_release(i8 addrspace(200)* %a, i8 %b) nounwind {
 define i8 @atomicrmw_umax_i8_acq_rel(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_umax_i8_acq_rel:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs3, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    mv s2, a1
-; RV32IXCHERI-NEXT:    cmove cs1, ca0
-; RV32IXCHERI-NEXT:    clbu a1, 0(ca0)
-; RV32IXCHERI-NEXT:    zext.b s3, s2
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 7
-; RV32IXCHERI-NEXT:    csetbounds cs0, ca0, 1
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s3, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    mv s0, a1
+; RV32IXCHERI-NEXT:    cmove s1, a0
+; RV32IXCHERI-NEXT:    clbu a1, 0(a0)
+; RV32IXCHERI-NEXT:    zext.b s3, s0
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 7
+; RV32IXCHERI-NEXT:    csetbounds s2, a0, 1
 ; RV32IXCHERI-NEXT:    j .LBB48_2
 ; RV32IXCHERI-NEXT:  .LBB48_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB48_2 Depth=1
-; RV32IXCHERI-NEXT:    csb a1, 7(csp)
+; RV32IXCHERI-NEXT:    csb a1, 7(sp)
 ; RV32IXCHERI-NEXT:    li a3, 4
 ; RV32IXCHERI-NEXT:    li a4, 2
-; RV32IXCHERI-NEXT:    cmove ca0, cs1
-; RV32IXCHERI-NEXT:    cmove ca1, cs0
+; RV32IXCHERI-NEXT:    cmove a0, s1
+; RV32IXCHERI-NEXT:    cmove a1, s2
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_1
-; RV32IXCHERI-NEXT:    clb a1, 7(csp)
+; RV32IXCHERI-NEXT:    clb a1, 7(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB48_4
 ; RV32IXCHERI-NEXT:  .LBB48_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -3297,28 +3297,28 @@ define i8 @atomicrmw_umax_i8_acq_rel(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-NEXT:    bltu s3, a0, .LBB48_1
 ; RV32IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB48_2 Depth=1
-; RV32IXCHERI-NEXT:    mv a2, s2
+; RV32IXCHERI-NEXT:    mv a2, s0
 ; RV32IXCHERI-NEXT:    j .LBB48_1
 ; RV32IXCHERI-NEXT:  .LBB48_4: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a1
-; RV32IXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs3, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s3, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_umax_i8_acq_rel:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB48_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.b.aq a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.b.aq a2, (a0)
 ; RV32IAXCHERI-NEXT:    mv a3, a2
 ; RV32IAXCHERI-NEXT:    bgeu a3, a1, .LBB48_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB48_1 Depth=1
 ; RV32IAXCHERI-NEXT:    mv a3, a1
 ; RV32IAXCHERI-NEXT:  .LBB48_3: # in Loop: Header=BB48_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.b.rl a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.b.rl a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB48_1
 ; RV32IAXCHERI-NEXT:  # %bb.4:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -3326,28 +3326,28 @@ define i8 @atomicrmw_umax_i8_acq_rel(i8 addrspace(200)* %a, i8 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_umax_i8_acq_rel:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -96
-; RV64IXCHERI-NEXT:    csc cra, 80(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs3, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    mv s2, a1
-; RV64IXCHERI-NEXT:    cmove cs1, ca0
-; RV64IXCHERI-NEXT:    clbu a1, 0(ca0)
-; RV64IXCHERI-NEXT:    zext.b s3, s2
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 15
-; RV64IXCHERI-NEXT:    csetbounds cs0, ca0, 1
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -96
+; RV64IXCHERI-NEXT:    csc ra, 80(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s3, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    mv s0, a1
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    clbu a1, 0(a0)
+; RV64IXCHERI-NEXT:    zext.b s3, s0
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 15
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 1
 ; RV64IXCHERI-NEXT:    j .LBB48_2
 ; RV64IXCHERI-NEXT:  .LBB48_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB48_2 Depth=1
-; RV64IXCHERI-NEXT:    csb a1, 15(csp)
+; RV64IXCHERI-NEXT:    csb a1, 15(sp)
 ; RV64IXCHERI-NEXT:    li a3, 4
 ; RV64IXCHERI-NEXT:    li a4, 2
-; RV64IXCHERI-NEXT:    cmove ca0, cs1
-; RV64IXCHERI-NEXT:    cmove ca1, cs0
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_1
-; RV64IXCHERI-NEXT:    clb a1, 15(csp)
+; RV64IXCHERI-NEXT:    clb a1, 15(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB48_4
 ; RV64IXCHERI-NEXT:  .LBB48_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -3356,28 +3356,28 @@ define i8 @atomicrmw_umax_i8_acq_rel(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV64IXCHERI-NEXT:    bltu s3, a0, .LBB48_1
 ; RV64IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB48_2 Depth=1
-; RV64IXCHERI-NEXT:    mv a2, s2
+; RV64IXCHERI-NEXT:    mv a2, s0
 ; RV64IXCHERI-NEXT:    j .LBB48_1
 ; RV64IXCHERI-NEXT:  .LBB48_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 80(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs3, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 96
+; RV64IXCHERI-NEXT:    clc ra, 80(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s3, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 96
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_umax_i8_acq_rel:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB48_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.b.aq a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.b.aq a2, (a0)
 ; RV64IAXCHERI-NEXT:    mv a3, a2
 ; RV64IAXCHERI-NEXT:    bgeu a3, a1, .LBB48_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB48_1 Depth=1
 ; RV64IAXCHERI-NEXT:    mv a3, a1
 ; RV64IAXCHERI-NEXT:  .LBB48_3: # in Loop: Header=BB48_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.b.rl a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.b.rl a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB48_1
 ; RV64IAXCHERI-NEXT:  # %bb.4:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -3389,28 +3389,28 @@ define i8 @atomicrmw_umax_i8_acq_rel(i8 addrspace(200)* %a, i8 %b) nounwind {
 define i8 @atomicrmw_umax_i8_seq_cst(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_umax_i8_seq_cst:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs3, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    mv s2, a1
-; RV32IXCHERI-NEXT:    cmove cs1, ca0
-; RV32IXCHERI-NEXT:    clbu a1, 0(ca0)
-; RV32IXCHERI-NEXT:    zext.b s3, s2
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 7
-; RV32IXCHERI-NEXT:    csetbounds cs0, ca0, 1
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s3, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    mv s0, a1
+; RV32IXCHERI-NEXT:    cmove s1, a0
+; RV32IXCHERI-NEXT:    clbu a1, 0(a0)
+; RV32IXCHERI-NEXT:    zext.b s3, s0
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 7
+; RV32IXCHERI-NEXT:    csetbounds s2, a0, 1
 ; RV32IXCHERI-NEXT:    j .LBB49_2
 ; RV32IXCHERI-NEXT:  .LBB49_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB49_2 Depth=1
-; RV32IXCHERI-NEXT:    csb a1, 7(csp)
+; RV32IXCHERI-NEXT:    csb a1, 7(sp)
 ; RV32IXCHERI-NEXT:    li a3, 5
 ; RV32IXCHERI-NEXT:    li a4, 5
-; RV32IXCHERI-NEXT:    cmove ca0, cs1
-; RV32IXCHERI-NEXT:    cmove ca1, cs0
+; RV32IXCHERI-NEXT:    cmove a0, s1
+; RV32IXCHERI-NEXT:    cmove a1, s2
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_1
-; RV32IXCHERI-NEXT:    clb a1, 7(csp)
+; RV32IXCHERI-NEXT:    clb a1, 7(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB49_4
 ; RV32IXCHERI-NEXT:  .LBB49_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -3419,28 +3419,28 @@ define i8 @atomicrmw_umax_i8_seq_cst(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-NEXT:    bltu s3, a0, .LBB49_1
 ; RV32IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB49_2 Depth=1
-; RV32IXCHERI-NEXT:    mv a2, s2
+; RV32IXCHERI-NEXT:    mv a2, s0
 ; RV32IXCHERI-NEXT:    j .LBB49_1
 ; RV32IXCHERI-NEXT:  .LBB49_4: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a1
-; RV32IXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs3, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s3, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_umax_i8_seq_cst:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB49_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.b.aqrl a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.b.aqrl a2, (a0)
 ; RV32IAXCHERI-NEXT:    mv a3, a2
 ; RV32IAXCHERI-NEXT:    bgeu a3, a1, .LBB49_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB49_1 Depth=1
 ; RV32IAXCHERI-NEXT:    mv a3, a1
 ; RV32IAXCHERI-NEXT:  .LBB49_3: # in Loop: Header=BB49_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.b.aqrl a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.b.aqrl a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB49_1
 ; RV32IAXCHERI-NEXT:  # %bb.4:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -3448,28 +3448,28 @@ define i8 @atomicrmw_umax_i8_seq_cst(i8 addrspace(200)* %a, i8 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_umax_i8_seq_cst:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -96
-; RV64IXCHERI-NEXT:    csc cra, 80(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs3, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    mv s2, a1
-; RV64IXCHERI-NEXT:    cmove cs1, ca0
-; RV64IXCHERI-NEXT:    clbu a1, 0(ca0)
-; RV64IXCHERI-NEXT:    zext.b s3, s2
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 15
-; RV64IXCHERI-NEXT:    csetbounds cs0, ca0, 1
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -96
+; RV64IXCHERI-NEXT:    csc ra, 80(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s3, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    mv s0, a1
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    clbu a1, 0(a0)
+; RV64IXCHERI-NEXT:    zext.b s3, s0
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 15
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 1
 ; RV64IXCHERI-NEXT:    j .LBB49_2
 ; RV64IXCHERI-NEXT:  .LBB49_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB49_2 Depth=1
-; RV64IXCHERI-NEXT:    csb a1, 15(csp)
+; RV64IXCHERI-NEXT:    csb a1, 15(sp)
 ; RV64IXCHERI-NEXT:    li a3, 5
 ; RV64IXCHERI-NEXT:    li a4, 5
-; RV64IXCHERI-NEXT:    cmove ca0, cs1
-; RV64IXCHERI-NEXT:    cmove ca1, cs0
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_1
-; RV64IXCHERI-NEXT:    clb a1, 15(csp)
+; RV64IXCHERI-NEXT:    clb a1, 15(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB49_4
 ; RV64IXCHERI-NEXT:  .LBB49_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -3478,28 +3478,28 @@ define i8 @atomicrmw_umax_i8_seq_cst(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV64IXCHERI-NEXT:    bltu s3, a0, .LBB49_1
 ; RV64IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB49_2 Depth=1
-; RV64IXCHERI-NEXT:    mv a2, s2
+; RV64IXCHERI-NEXT:    mv a2, s0
 ; RV64IXCHERI-NEXT:    j .LBB49_1
 ; RV64IXCHERI-NEXT:  .LBB49_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 80(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs3, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 96
+; RV64IXCHERI-NEXT:    clc ra, 80(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s3, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 96
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_umax_i8_seq_cst:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB49_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.b.aqrl a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.b.aqrl a2, (a0)
 ; RV64IAXCHERI-NEXT:    mv a3, a2
 ; RV64IAXCHERI-NEXT:    bgeu a3, a1, .LBB49_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB49_1 Depth=1
 ; RV64IAXCHERI-NEXT:    mv a3, a1
 ; RV64IAXCHERI-NEXT:  .LBB49_3: # in Loop: Header=BB49_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.b.aqrl a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.b.aqrl a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB49_1
 ; RV64IAXCHERI-NEXT:  # %bb.4:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -3511,28 +3511,28 @@ define i8 @atomicrmw_umax_i8_seq_cst(i8 addrspace(200)* %a, i8 %b) nounwind {
 define i8 @atomicrmw_umin_i8_monotonic(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_umin_i8_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs3, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    mv s2, a1
-; RV32IXCHERI-NEXT:    cmove cs1, ca0
-; RV32IXCHERI-NEXT:    clbu a1, 0(ca0)
-; RV32IXCHERI-NEXT:    zext.b s3, s2
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 7
-; RV32IXCHERI-NEXT:    csetbounds cs0, ca0, 1
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s3, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    mv s0, a1
+; RV32IXCHERI-NEXT:    cmove s1, a0
+; RV32IXCHERI-NEXT:    clbu a1, 0(a0)
+; RV32IXCHERI-NEXT:    zext.b s3, s0
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 7
+; RV32IXCHERI-NEXT:    csetbounds s2, a0, 1
 ; RV32IXCHERI-NEXT:    j .LBB50_2
 ; RV32IXCHERI-NEXT:  .LBB50_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB50_2 Depth=1
-; RV32IXCHERI-NEXT:    csb a1, 7(csp)
-; RV32IXCHERI-NEXT:    cmove ca0, cs1
-; RV32IXCHERI-NEXT:    cmove ca1, cs0
+; RV32IXCHERI-NEXT:    csb a1, 7(sp)
+; RV32IXCHERI-NEXT:    cmove a0, s1
+; RV32IXCHERI-NEXT:    cmove a1, s2
 ; RV32IXCHERI-NEXT:    li a3, 0
 ; RV32IXCHERI-NEXT:    li a4, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_1
-; RV32IXCHERI-NEXT:    clb a1, 7(csp)
+; RV32IXCHERI-NEXT:    clb a1, 7(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB50_4
 ; RV32IXCHERI-NEXT:  .LBB50_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -3541,28 +3541,28 @@ define i8 @atomicrmw_umin_i8_monotonic(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-NEXT:    bgeu s3, a0, .LBB50_1
 ; RV32IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB50_2 Depth=1
-; RV32IXCHERI-NEXT:    mv a2, s2
+; RV32IXCHERI-NEXT:    mv a2, s0
 ; RV32IXCHERI-NEXT:    j .LBB50_1
 ; RV32IXCHERI-NEXT:  .LBB50_4: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a1
-; RV32IXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs3, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s3, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_umin_i8_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB50_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.b a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.b a2, (a0)
 ; RV32IAXCHERI-NEXT:    mv a3, a2
 ; RV32IAXCHERI-NEXT:    bgeu a1, a3, .LBB50_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB50_1 Depth=1
 ; RV32IAXCHERI-NEXT:    mv a3, a1
 ; RV32IAXCHERI-NEXT:  .LBB50_3: # in Loop: Header=BB50_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.b a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.b a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB50_1
 ; RV32IAXCHERI-NEXT:  # %bb.4:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -3570,28 +3570,28 @@ define i8 @atomicrmw_umin_i8_monotonic(i8 addrspace(200)* %a, i8 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_umin_i8_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -96
-; RV64IXCHERI-NEXT:    csc cra, 80(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs3, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    mv s2, a1
-; RV64IXCHERI-NEXT:    cmove cs1, ca0
-; RV64IXCHERI-NEXT:    clbu a1, 0(ca0)
-; RV64IXCHERI-NEXT:    zext.b s3, s2
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 15
-; RV64IXCHERI-NEXT:    csetbounds cs0, ca0, 1
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -96
+; RV64IXCHERI-NEXT:    csc ra, 80(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s3, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    mv s0, a1
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    clbu a1, 0(a0)
+; RV64IXCHERI-NEXT:    zext.b s3, s0
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 15
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 1
 ; RV64IXCHERI-NEXT:    j .LBB50_2
 ; RV64IXCHERI-NEXT:  .LBB50_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB50_2 Depth=1
-; RV64IXCHERI-NEXT:    csb a1, 15(csp)
-; RV64IXCHERI-NEXT:    cmove ca0, cs1
-; RV64IXCHERI-NEXT:    cmove ca1, cs0
+; RV64IXCHERI-NEXT:    csb a1, 15(sp)
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    li a3, 0
 ; RV64IXCHERI-NEXT:    li a4, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_1
-; RV64IXCHERI-NEXT:    clb a1, 15(csp)
+; RV64IXCHERI-NEXT:    clb a1, 15(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB50_4
 ; RV64IXCHERI-NEXT:  .LBB50_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -3600,28 +3600,28 @@ define i8 @atomicrmw_umin_i8_monotonic(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV64IXCHERI-NEXT:    bgeu s3, a0, .LBB50_1
 ; RV64IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB50_2 Depth=1
-; RV64IXCHERI-NEXT:    mv a2, s2
+; RV64IXCHERI-NEXT:    mv a2, s0
 ; RV64IXCHERI-NEXT:    j .LBB50_1
 ; RV64IXCHERI-NEXT:  .LBB50_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 80(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs3, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 96
+; RV64IXCHERI-NEXT:    clc ra, 80(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s3, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 96
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_umin_i8_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB50_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.b a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.b a2, (a0)
 ; RV64IAXCHERI-NEXT:    mv a3, a2
 ; RV64IAXCHERI-NEXT:    bgeu a1, a3, .LBB50_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB50_1 Depth=1
 ; RV64IAXCHERI-NEXT:    mv a3, a1
 ; RV64IAXCHERI-NEXT:  .LBB50_3: # in Loop: Header=BB50_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.b a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.b a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB50_1
 ; RV64IAXCHERI-NEXT:  # %bb.4:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -3633,28 +3633,28 @@ define i8 @atomicrmw_umin_i8_monotonic(i8 addrspace(200)* %a, i8 %b) nounwind {
 define i8 @atomicrmw_umin_i8_acquire(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_umin_i8_acquire:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs3, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    mv s2, a1
-; RV32IXCHERI-NEXT:    cmove cs1, ca0
-; RV32IXCHERI-NEXT:    clbu a1, 0(ca0)
-; RV32IXCHERI-NEXT:    zext.b s3, s2
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 7
-; RV32IXCHERI-NEXT:    csetbounds cs0, ca0, 1
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s3, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    mv s0, a1
+; RV32IXCHERI-NEXT:    cmove s1, a0
+; RV32IXCHERI-NEXT:    clbu a1, 0(a0)
+; RV32IXCHERI-NEXT:    zext.b s3, s0
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 7
+; RV32IXCHERI-NEXT:    csetbounds s2, a0, 1
 ; RV32IXCHERI-NEXT:    j .LBB51_2
 ; RV32IXCHERI-NEXT:  .LBB51_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB51_2 Depth=1
-; RV32IXCHERI-NEXT:    csb a1, 7(csp)
+; RV32IXCHERI-NEXT:    csb a1, 7(sp)
 ; RV32IXCHERI-NEXT:    li a3, 2
 ; RV32IXCHERI-NEXT:    li a4, 2
-; RV32IXCHERI-NEXT:    cmove ca0, cs1
-; RV32IXCHERI-NEXT:    cmove ca1, cs0
+; RV32IXCHERI-NEXT:    cmove a0, s1
+; RV32IXCHERI-NEXT:    cmove a1, s2
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_1
-; RV32IXCHERI-NEXT:    clb a1, 7(csp)
+; RV32IXCHERI-NEXT:    clb a1, 7(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB51_4
 ; RV32IXCHERI-NEXT:  .LBB51_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -3663,28 +3663,28 @@ define i8 @atomicrmw_umin_i8_acquire(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-NEXT:    bgeu s3, a0, .LBB51_1
 ; RV32IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB51_2 Depth=1
-; RV32IXCHERI-NEXT:    mv a2, s2
+; RV32IXCHERI-NEXT:    mv a2, s0
 ; RV32IXCHERI-NEXT:    j .LBB51_1
 ; RV32IXCHERI-NEXT:  .LBB51_4: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a1
-; RV32IXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs3, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s3, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_umin_i8_acquire:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB51_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.b.aq a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.b.aq a2, (a0)
 ; RV32IAXCHERI-NEXT:    mv a3, a2
 ; RV32IAXCHERI-NEXT:    bgeu a1, a3, .LBB51_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB51_1 Depth=1
 ; RV32IAXCHERI-NEXT:    mv a3, a1
 ; RV32IAXCHERI-NEXT:  .LBB51_3: # in Loop: Header=BB51_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.b a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.b a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB51_1
 ; RV32IAXCHERI-NEXT:  # %bb.4:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -3692,28 +3692,28 @@ define i8 @atomicrmw_umin_i8_acquire(i8 addrspace(200)* %a, i8 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_umin_i8_acquire:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -96
-; RV64IXCHERI-NEXT:    csc cra, 80(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs3, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    mv s2, a1
-; RV64IXCHERI-NEXT:    cmove cs1, ca0
-; RV64IXCHERI-NEXT:    clbu a1, 0(ca0)
-; RV64IXCHERI-NEXT:    zext.b s3, s2
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 15
-; RV64IXCHERI-NEXT:    csetbounds cs0, ca0, 1
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -96
+; RV64IXCHERI-NEXT:    csc ra, 80(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s3, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    mv s0, a1
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    clbu a1, 0(a0)
+; RV64IXCHERI-NEXT:    zext.b s3, s0
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 15
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 1
 ; RV64IXCHERI-NEXT:    j .LBB51_2
 ; RV64IXCHERI-NEXT:  .LBB51_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB51_2 Depth=1
-; RV64IXCHERI-NEXT:    csb a1, 15(csp)
+; RV64IXCHERI-NEXT:    csb a1, 15(sp)
 ; RV64IXCHERI-NEXT:    li a3, 2
 ; RV64IXCHERI-NEXT:    li a4, 2
-; RV64IXCHERI-NEXT:    cmove ca0, cs1
-; RV64IXCHERI-NEXT:    cmove ca1, cs0
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_1
-; RV64IXCHERI-NEXT:    clb a1, 15(csp)
+; RV64IXCHERI-NEXT:    clb a1, 15(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB51_4
 ; RV64IXCHERI-NEXT:  .LBB51_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -3722,28 +3722,28 @@ define i8 @atomicrmw_umin_i8_acquire(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV64IXCHERI-NEXT:    bgeu s3, a0, .LBB51_1
 ; RV64IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB51_2 Depth=1
-; RV64IXCHERI-NEXT:    mv a2, s2
+; RV64IXCHERI-NEXT:    mv a2, s0
 ; RV64IXCHERI-NEXT:    j .LBB51_1
 ; RV64IXCHERI-NEXT:  .LBB51_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 80(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs3, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 96
+; RV64IXCHERI-NEXT:    clc ra, 80(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s3, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 96
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_umin_i8_acquire:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB51_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.b.aq a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.b.aq a2, (a0)
 ; RV64IAXCHERI-NEXT:    mv a3, a2
 ; RV64IAXCHERI-NEXT:    bgeu a1, a3, .LBB51_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB51_1 Depth=1
 ; RV64IAXCHERI-NEXT:    mv a3, a1
 ; RV64IAXCHERI-NEXT:  .LBB51_3: # in Loop: Header=BB51_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.b a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.b a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB51_1
 ; RV64IAXCHERI-NEXT:  # %bb.4:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -3755,28 +3755,28 @@ define i8 @atomicrmw_umin_i8_acquire(i8 addrspace(200)* %a, i8 %b) nounwind {
 define i8 @atomicrmw_umin_i8_release(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_umin_i8_release:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs3, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    mv s2, a1
-; RV32IXCHERI-NEXT:    cmove cs1, ca0
-; RV32IXCHERI-NEXT:    clbu a1, 0(ca0)
-; RV32IXCHERI-NEXT:    zext.b s3, s2
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 7
-; RV32IXCHERI-NEXT:    csetbounds cs0, ca0, 1
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s3, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    mv s0, a1
+; RV32IXCHERI-NEXT:    cmove s1, a0
+; RV32IXCHERI-NEXT:    clbu a1, 0(a0)
+; RV32IXCHERI-NEXT:    zext.b s3, s0
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 7
+; RV32IXCHERI-NEXT:    csetbounds s2, a0, 1
 ; RV32IXCHERI-NEXT:    j .LBB52_2
 ; RV32IXCHERI-NEXT:  .LBB52_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB52_2 Depth=1
-; RV32IXCHERI-NEXT:    csb a1, 7(csp)
+; RV32IXCHERI-NEXT:    csb a1, 7(sp)
 ; RV32IXCHERI-NEXT:    li a3, 3
-; RV32IXCHERI-NEXT:    cmove ca0, cs1
-; RV32IXCHERI-NEXT:    cmove ca1, cs0
+; RV32IXCHERI-NEXT:    cmove a0, s1
+; RV32IXCHERI-NEXT:    cmove a1, s2
 ; RV32IXCHERI-NEXT:    li a4, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_1
-; RV32IXCHERI-NEXT:    clb a1, 7(csp)
+; RV32IXCHERI-NEXT:    clb a1, 7(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB52_4
 ; RV32IXCHERI-NEXT:  .LBB52_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -3785,28 +3785,28 @@ define i8 @atomicrmw_umin_i8_release(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-NEXT:    bgeu s3, a0, .LBB52_1
 ; RV32IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB52_2 Depth=1
-; RV32IXCHERI-NEXT:    mv a2, s2
+; RV32IXCHERI-NEXT:    mv a2, s0
 ; RV32IXCHERI-NEXT:    j .LBB52_1
 ; RV32IXCHERI-NEXT:  .LBB52_4: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a1
-; RV32IXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs3, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s3, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_umin_i8_release:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB52_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.b a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.b a2, (a0)
 ; RV32IAXCHERI-NEXT:    mv a3, a2
 ; RV32IAXCHERI-NEXT:    bgeu a1, a3, .LBB52_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB52_1 Depth=1
 ; RV32IAXCHERI-NEXT:    mv a3, a1
 ; RV32IAXCHERI-NEXT:  .LBB52_3: # in Loop: Header=BB52_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.b.rl a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.b.rl a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB52_1
 ; RV32IAXCHERI-NEXT:  # %bb.4:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -3814,28 +3814,28 @@ define i8 @atomicrmw_umin_i8_release(i8 addrspace(200)* %a, i8 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_umin_i8_release:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -96
-; RV64IXCHERI-NEXT:    csc cra, 80(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs3, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    mv s2, a1
-; RV64IXCHERI-NEXT:    cmove cs1, ca0
-; RV64IXCHERI-NEXT:    clbu a1, 0(ca0)
-; RV64IXCHERI-NEXT:    zext.b s3, s2
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 15
-; RV64IXCHERI-NEXT:    csetbounds cs0, ca0, 1
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -96
+; RV64IXCHERI-NEXT:    csc ra, 80(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s3, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    mv s0, a1
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    clbu a1, 0(a0)
+; RV64IXCHERI-NEXT:    zext.b s3, s0
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 15
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 1
 ; RV64IXCHERI-NEXT:    j .LBB52_2
 ; RV64IXCHERI-NEXT:  .LBB52_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB52_2 Depth=1
-; RV64IXCHERI-NEXT:    csb a1, 15(csp)
+; RV64IXCHERI-NEXT:    csb a1, 15(sp)
 ; RV64IXCHERI-NEXT:    li a3, 3
-; RV64IXCHERI-NEXT:    cmove ca0, cs1
-; RV64IXCHERI-NEXT:    cmove ca1, cs0
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    li a4, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_1
-; RV64IXCHERI-NEXT:    clb a1, 15(csp)
+; RV64IXCHERI-NEXT:    clb a1, 15(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB52_4
 ; RV64IXCHERI-NEXT:  .LBB52_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -3844,28 +3844,28 @@ define i8 @atomicrmw_umin_i8_release(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV64IXCHERI-NEXT:    bgeu s3, a0, .LBB52_1
 ; RV64IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB52_2 Depth=1
-; RV64IXCHERI-NEXT:    mv a2, s2
+; RV64IXCHERI-NEXT:    mv a2, s0
 ; RV64IXCHERI-NEXT:    j .LBB52_1
 ; RV64IXCHERI-NEXT:  .LBB52_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 80(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs3, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 96
+; RV64IXCHERI-NEXT:    clc ra, 80(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s3, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 96
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_umin_i8_release:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB52_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.b a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.b a2, (a0)
 ; RV64IAXCHERI-NEXT:    mv a3, a2
 ; RV64IAXCHERI-NEXT:    bgeu a1, a3, .LBB52_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB52_1 Depth=1
 ; RV64IAXCHERI-NEXT:    mv a3, a1
 ; RV64IAXCHERI-NEXT:  .LBB52_3: # in Loop: Header=BB52_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.b.rl a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.b.rl a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB52_1
 ; RV64IAXCHERI-NEXT:  # %bb.4:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -3877,28 +3877,28 @@ define i8 @atomicrmw_umin_i8_release(i8 addrspace(200)* %a, i8 %b) nounwind {
 define i8 @atomicrmw_umin_i8_acq_rel(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_umin_i8_acq_rel:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs3, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    mv s2, a1
-; RV32IXCHERI-NEXT:    cmove cs1, ca0
-; RV32IXCHERI-NEXT:    clbu a1, 0(ca0)
-; RV32IXCHERI-NEXT:    zext.b s3, s2
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 7
-; RV32IXCHERI-NEXT:    csetbounds cs0, ca0, 1
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s3, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    mv s0, a1
+; RV32IXCHERI-NEXT:    cmove s1, a0
+; RV32IXCHERI-NEXT:    clbu a1, 0(a0)
+; RV32IXCHERI-NEXT:    zext.b s3, s0
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 7
+; RV32IXCHERI-NEXT:    csetbounds s2, a0, 1
 ; RV32IXCHERI-NEXT:    j .LBB53_2
 ; RV32IXCHERI-NEXT:  .LBB53_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB53_2 Depth=1
-; RV32IXCHERI-NEXT:    csb a1, 7(csp)
+; RV32IXCHERI-NEXT:    csb a1, 7(sp)
 ; RV32IXCHERI-NEXT:    li a3, 4
 ; RV32IXCHERI-NEXT:    li a4, 2
-; RV32IXCHERI-NEXT:    cmove ca0, cs1
-; RV32IXCHERI-NEXT:    cmove ca1, cs0
+; RV32IXCHERI-NEXT:    cmove a0, s1
+; RV32IXCHERI-NEXT:    cmove a1, s2
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_1
-; RV32IXCHERI-NEXT:    clb a1, 7(csp)
+; RV32IXCHERI-NEXT:    clb a1, 7(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB53_4
 ; RV32IXCHERI-NEXT:  .LBB53_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -3907,28 +3907,28 @@ define i8 @atomicrmw_umin_i8_acq_rel(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-NEXT:    bgeu s3, a0, .LBB53_1
 ; RV32IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB53_2 Depth=1
-; RV32IXCHERI-NEXT:    mv a2, s2
+; RV32IXCHERI-NEXT:    mv a2, s0
 ; RV32IXCHERI-NEXT:    j .LBB53_1
 ; RV32IXCHERI-NEXT:  .LBB53_4: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a1
-; RV32IXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs3, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s3, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_umin_i8_acq_rel:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB53_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.b.aq a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.b.aq a2, (a0)
 ; RV32IAXCHERI-NEXT:    mv a3, a2
 ; RV32IAXCHERI-NEXT:    bgeu a1, a3, .LBB53_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB53_1 Depth=1
 ; RV32IAXCHERI-NEXT:    mv a3, a1
 ; RV32IAXCHERI-NEXT:  .LBB53_3: # in Loop: Header=BB53_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.b.rl a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.b.rl a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB53_1
 ; RV32IAXCHERI-NEXT:  # %bb.4:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -3936,28 +3936,28 @@ define i8 @atomicrmw_umin_i8_acq_rel(i8 addrspace(200)* %a, i8 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_umin_i8_acq_rel:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -96
-; RV64IXCHERI-NEXT:    csc cra, 80(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs3, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    mv s2, a1
-; RV64IXCHERI-NEXT:    cmove cs1, ca0
-; RV64IXCHERI-NEXT:    clbu a1, 0(ca0)
-; RV64IXCHERI-NEXT:    zext.b s3, s2
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 15
-; RV64IXCHERI-NEXT:    csetbounds cs0, ca0, 1
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -96
+; RV64IXCHERI-NEXT:    csc ra, 80(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s3, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    mv s0, a1
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    clbu a1, 0(a0)
+; RV64IXCHERI-NEXT:    zext.b s3, s0
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 15
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 1
 ; RV64IXCHERI-NEXT:    j .LBB53_2
 ; RV64IXCHERI-NEXT:  .LBB53_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB53_2 Depth=1
-; RV64IXCHERI-NEXT:    csb a1, 15(csp)
+; RV64IXCHERI-NEXT:    csb a1, 15(sp)
 ; RV64IXCHERI-NEXT:    li a3, 4
 ; RV64IXCHERI-NEXT:    li a4, 2
-; RV64IXCHERI-NEXT:    cmove ca0, cs1
-; RV64IXCHERI-NEXT:    cmove ca1, cs0
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_1
-; RV64IXCHERI-NEXT:    clb a1, 15(csp)
+; RV64IXCHERI-NEXT:    clb a1, 15(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB53_4
 ; RV64IXCHERI-NEXT:  .LBB53_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -3966,28 +3966,28 @@ define i8 @atomicrmw_umin_i8_acq_rel(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV64IXCHERI-NEXT:    bgeu s3, a0, .LBB53_1
 ; RV64IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB53_2 Depth=1
-; RV64IXCHERI-NEXT:    mv a2, s2
+; RV64IXCHERI-NEXT:    mv a2, s0
 ; RV64IXCHERI-NEXT:    j .LBB53_1
 ; RV64IXCHERI-NEXT:  .LBB53_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 80(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs3, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 96
+; RV64IXCHERI-NEXT:    clc ra, 80(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s3, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 96
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_umin_i8_acq_rel:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB53_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.b.aq a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.b.aq a2, (a0)
 ; RV64IAXCHERI-NEXT:    mv a3, a2
 ; RV64IAXCHERI-NEXT:    bgeu a1, a3, .LBB53_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB53_1 Depth=1
 ; RV64IAXCHERI-NEXT:    mv a3, a1
 ; RV64IAXCHERI-NEXT:  .LBB53_3: # in Loop: Header=BB53_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.b.rl a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.b.rl a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB53_1
 ; RV64IAXCHERI-NEXT:  # %bb.4:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -3999,28 +3999,28 @@ define i8 @atomicrmw_umin_i8_acq_rel(i8 addrspace(200)* %a, i8 %b) nounwind {
 define i8 @atomicrmw_umin_i8_seq_cst(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_umin_i8_seq_cst:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs3, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    mv s2, a1
-; RV32IXCHERI-NEXT:    cmove cs1, ca0
-; RV32IXCHERI-NEXT:    clbu a1, 0(ca0)
-; RV32IXCHERI-NEXT:    zext.b s3, s2
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 7
-; RV32IXCHERI-NEXT:    csetbounds cs0, ca0, 1
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s3, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    mv s0, a1
+; RV32IXCHERI-NEXT:    cmove s1, a0
+; RV32IXCHERI-NEXT:    clbu a1, 0(a0)
+; RV32IXCHERI-NEXT:    zext.b s3, s0
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 7
+; RV32IXCHERI-NEXT:    csetbounds s2, a0, 1
 ; RV32IXCHERI-NEXT:    j .LBB54_2
 ; RV32IXCHERI-NEXT:  .LBB54_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB54_2 Depth=1
-; RV32IXCHERI-NEXT:    csb a1, 7(csp)
+; RV32IXCHERI-NEXT:    csb a1, 7(sp)
 ; RV32IXCHERI-NEXT:    li a3, 5
 ; RV32IXCHERI-NEXT:    li a4, 5
-; RV32IXCHERI-NEXT:    cmove ca0, cs1
-; RV32IXCHERI-NEXT:    cmove ca1, cs0
+; RV32IXCHERI-NEXT:    cmove a0, s1
+; RV32IXCHERI-NEXT:    cmove a1, s2
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_1
-; RV32IXCHERI-NEXT:    clb a1, 7(csp)
+; RV32IXCHERI-NEXT:    clb a1, 7(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB54_4
 ; RV32IXCHERI-NEXT:  .LBB54_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -4029,28 +4029,28 @@ define i8 @atomicrmw_umin_i8_seq_cst(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV32IXCHERI-NEXT:    bgeu s3, a0, .LBB54_1
 ; RV32IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB54_2 Depth=1
-; RV32IXCHERI-NEXT:    mv a2, s2
+; RV32IXCHERI-NEXT:    mv a2, s0
 ; RV32IXCHERI-NEXT:    j .LBB54_1
 ; RV32IXCHERI-NEXT:  .LBB54_4: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a1
-; RV32IXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs3, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s3, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_umin_i8_seq_cst:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB54_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.b.aqrl a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.b.aqrl a2, (a0)
 ; RV32IAXCHERI-NEXT:    mv a3, a2
 ; RV32IAXCHERI-NEXT:    bgeu a1, a3, .LBB54_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB54_1 Depth=1
 ; RV32IAXCHERI-NEXT:    mv a3, a1
 ; RV32IAXCHERI-NEXT:  .LBB54_3: # in Loop: Header=BB54_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.b.aqrl a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.b.aqrl a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB54_1
 ; RV32IAXCHERI-NEXT:  # %bb.4:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -4058,28 +4058,28 @@ define i8 @atomicrmw_umin_i8_seq_cst(i8 addrspace(200)* %a, i8 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_umin_i8_seq_cst:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -96
-; RV64IXCHERI-NEXT:    csc cra, 80(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs3, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    mv s2, a1
-; RV64IXCHERI-NEXT:    cmove cs1, ca0
-; RV64IXCHERI-NEXT:    clbu a1, 0(ca0)
-; RV64IXCHERI-NEXT:    zext.b s3, s2
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 15
-; RV64IXCHERI-NEXT:    csetbounds cs0, ca0, 1
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -96
+; RV64IXCHERI-NEXT:    csc ra, 80(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s3, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    mv s0, a1
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    clbu a1, 0(a0)
+; RV64IXCHERI-NEXT:    zext.b s3, s0
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 15
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 1
 ; RV64IXCHERI-NEXT:    j .LBB54_2
 ; RV64IXCHERI-NEXT:  .LBB54_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB54_2 Depth=1
-; RV64IXCHERI-NEXT:    csb a1, 15(csp)
+; RV64IXCHERI-NEXT:    csb a1, 15(sp)
 ; RV64IXCHERI-NEXT:    li a3, 5
 ; RV64IXCHERI-NEXT:    li a4, 5
-; RV64IXCHERI-NEXT:    cmove ca0, cs1
-; RV64IXCHERI-NEXT:    cmove ca1, cs0
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_1
-; RV64IXCHERI-NEXT:    clb a1, 15(csp)
+; RV64IXCHERI-NEXT:    clb a1, 15(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB54_4
 ; RV64IXCHERI-NEXT:  .LBB54_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -4088,28 +4088,28 @@ define i8 @atomicrmw_umin_i8_seq_cst(i8 addrspace(200)* %a, i8 %b) nounwind {
 ; RV64IXCHERI-NEXT:    bgeu s3, a0, .LBB54_1
 ; RV64IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB54_2 Depth=1
-; RV64IXCHERI-NEXT:    mv a2, s2
+; RV64IXCHERI-NEXT:    mv a2, s0
 ; RV64IXCHERI-NEXT:    j .LBB54_1
 ; RV64IXCHERI-NEXT:  .LBB54_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 80(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs3, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 96
+; RV64IXCHERI-NEXT:    clc ra, 80(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s3, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 96
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_umin_i8_seq_cst:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB54_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.b.aqrl a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.b.aqrl a2, (a0)
 ; RV64IAXCHERI-NEXT:    mv a3, a2
 ; RV64IAXCHERI-NEXT:    bgeu a1, a3, .LBB54_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB54_1 Depth=1
 ; RV64IAXCHERI-NEXT:    mv a3, a1
 ; RV64IAXCHERI-NEXT:  .LBB54_3: # in Loop: Header=BB54_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.b.aqrl a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.b.aqrl a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB54_1
 ; RV64IAXCHERI-NEXT:  # %bb.4:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -4121,20 +4121,20 @@ define i8 @atomicrmw_umin_i8_seq_cst(i8 addrspace(200)* %a, i8 %b) nounwind {
 define i16 @atomicrmw_xchg_i16_monotonic(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_xchg_i16_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_exchange_2
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_xchg_i16_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB55_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.h a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.h a2, (a0)
 ; RV32IAXCHERI-NEXT:    add a3, zero, a1
-; RV32IAXCHERI-NEXT:    csc.h a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.h a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB55_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -4142,20 +4142,20 @@ define i16 @atomicrmw_xchg_i16_monotonic(i16 addrspace(200)* %a, i16 %b) nounwin
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_xchg_i16_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_exchange_2
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_xchg_i16_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB55_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.h a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.h a2, (a0)
 ; RV64IAXCHERI-NEXT:    add a3, zero, a1
-; RV64IAXCHERI-NEXT:    csc.h a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.h a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB55_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -4167,20 +4167,20 @@ define i16 @atomicrmw_xchg_i16_monotonic(i16 addrspace(200)* %a, i16 %b) nounwin
 define i16 @atomicrmw_xchg_i16_acquire(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_xchg_i16_acquire:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 2
 ; RV32IXCHERI-NEXT:    ccall __atomic_exchange_2
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_xchg_i16_acquire:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB56_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.h.aq a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.h.aq a2, (a0)
 ; RV32IAXCHERI-NEXT:    add a3, zero, a1
-; RV32IAXCHERI-NEXT:    csc.h a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.h a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB56_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -4188,20 +4188,20 @@ define i16 @atomicrmw_xchg_i16_acquire(i16 addrspace(200)* %a, i16 %b) nounwind
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_xchg_i16_acquire:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 2
 ; RV64IXCHERI-NEXT:    ccall __atomic_exchange_2
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_xchg_i16_acquire:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB56_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.h.aq a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.h.aq a2, (a0)
 ; RV64IAXCHERI-NEXT:    add a3, zero, a1
-; RV64IAXCHERI-NEXT:    csc.h a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.h a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB56_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -4213,20 +4213,20 @@ define i16 @atomicrmw_xchg_i16_acquire(i16 addrspace(200)* %a, i16 %b) nounwind
 define i16 @atomicrmw_xchg_i16_release(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_xchg_i16_release:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 3
 ; RV32IXCHERI-NEXT:    ccall __atomic_exchange_2
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_xchg_i16_release:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB57_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.h a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.h a2, (a0)
 ; RV32IAXCHERI-NEXT:    add a3, zero, a1
-; RV32IAXCHERI-NEXT:    csc.h.rl a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.h.rl a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB57_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -4234,20 +4234,20 @@ define i16 @atomicrmw_xchg_i16_release(i16 addrspace(200)* %a, i16 %b) nounwind
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_xchg_i16_release:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 3
 ; RV64IXCHERI-NEXT:    ccall __atomic_exchange_2
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_xchg_i16_release:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB57_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.h a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.h a2, (a0)
 ; RV64IAXCHERI-NEXT:    add a3, zero, a1
-; RV64IAXCHERI-NEXT:    csc.h.rl a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.h.rl a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB57_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -4259,20 +4259,20 @@ define i16 @atomicrmw_xchg_i16_release(i16 addrspace(200)* %a, i16 %b) nounwind
 define i16 @atomicrmw_xchg_i16_acq_rel(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_xchg_i16_acq_rel:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 4
 ; RV32IXCHERI-NEXT:    ccall __atomic_exchange_2
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_xchg_i16_acq_rel:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB58_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.h.aq a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.h.aq a2, (a0)
 ; RV32IAXCHERI-NEXT:    add a3, zero, a1
-; RV32IAXCHERI-NEXT:    csc.h.rl a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.h.rl a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB58_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -4280,20 +4280,20 @@ define i16 @atomicrmw_xchg_i16_acq_rel(i16 addrspace(200)* %a, i16 %b) nounwind
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_xchg_i16_acq_rel:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 4
 ; RV64IXCHERI-NEXT:    ccall __atomic_exchange_2
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_xchg_i16_acq_rel:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB58_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.h.aq a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.h.aq a2, (a0)
 ; RV64IAXCHERI-NEXT:    add a3, zero, a1
-; RV64IAXCHERI-NEXT:    csc.h.rl a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.h.rl a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB58_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -4305,20 +4305,20 @@ define i16 @atomicrmw_xchg_i16_acq_rel(i16 addrspace(200)* %a, i16 %b) nounwind
 define i16 @atomicrmw_xchg_i16_seq_cst(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_xchg_i16_seq_cst:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 5
 ; RV32IXCHERI-NEXT:    ccall __atomic_exchange_2
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_xchg_i16_seq_cst:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB59_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.h.aqrl a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.h.aqrl a2, (a0)
 ; RV32IAXCHERI-NEXT:    add a3, zero, a1
-; RV32IAXCHERI-NEXT:    csc.h.aqrl a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.h.aqrl a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB59_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -4326,20 +4326,20 @@ define i16 @atomicrmw_xchg_i16_seq_cst(i16 addrspace(200)* %a, i16 %b) nounwind
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_xchg_i16_seq_cst:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 5
 ; RV64IXCHERI-NEXT:    ccall __atomic_exchange_2
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_xchg_i16_seq_cst:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB59_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.h.aqrl a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.h.aqrl a2, (a0)
 ; RV64IAXCHERI-NEXT:    add a3, zero, a1
-; RV64IAXCHERI-NEXT:    csc.h.aqrl a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.h.aqrl a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB59_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -4351,20 +4351,20 @@ define i16 @atomicrmw_xchg_i16_seq_cst(i16 addrspace(200)* %a, i16 %b) nounwind
 define i16 @atomicrmw_add_i16_monotonic(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_add_i16_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_add_2
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_add_i16_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB60_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.h a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.h a2, (a0)
 ; RV32IAXCHERI-NEXT:    add a3, a2, a1
-; RV32IAXCHERI-NEXT:    csc.h a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.h a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB60_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -4372,20 +4372,20 @@ define i16 @atomicrmw_add_i16_monotonic(i16 addrspace(200)* %a, i16 %b) nounwind
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_add_i16_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_add_2
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_add_i16_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB60_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.h a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.h a2, (a0)
 ; RV64IAXCHERI-NEXT:    add a3, a2, a1
-; RV64IAXCHERI-NEXT:    csc.h a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.h a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB60_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -4397,20 +4397,20 @@ define i16 @atomicrmw_add_i16_monotonic(i16 addrspace(200)* %a, i16 %b) nounwind
 define i16 @atomicrmw_add_i16_acquire(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_add_i16_acquire:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 2
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_add_2
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_add_i16_acquire:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB61_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.h.aq a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.h.aq a2, (a0)
 ; RV32IAXCHERI-NEXT:    add a3, a2, a1
-; RV32IAXCHERI-NEXT:    csc.h a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.h a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB61_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -4418,20 +4418,20 @@ define i16 @atomicrmw_add_i16_acquire(i16 addrspace(200)* %a, i16 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_add_i16_acquire:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 2
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_add_2
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_add_i16_acquire:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB61_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.h.aq a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.h.aq a2, (a0)
 ; RV64IAXCHERI-NEXT:    add a3, a2, a1
-; RV64IAXCHERI-NEXT:    csc.h a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.h a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB61_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -4443,20 +4443,20 @@ define i16 @atomicrmw_add_i16_acquire(i16 addrspace(200)* %a, i16 %b) nounwind {
 define i16 @atomicrmw_add_i16_release(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_add_i16_release:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 3
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_add_2
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_add_i16_release:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB62_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.h a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.h a2, (a0)
 ; RV32IAXCHERI-NEXT:    add a3, a2, a1
-; RV32IAXCHERI-NEXT:    csc.h.rl a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.h.rl a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB62_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -4464,20 +4464,20 @@ define i16 @atomicrmw_add_i16_release(i16 addrspace(200)* %a, i16 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_add_i16_release:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 3
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_add_2
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_add_i16_release:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB62_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.h a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.h a2, (a0)
 ; RV64IAXCHERI-NEXT:    add a3, a2, a1
-; RV64IAXCHERI-NEXT:    csc.h.rl a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.h.rl a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB62_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -4489,20 +4489,20 @@ define i16 @atomicrmw_add_i16_release(i16 addrspace(200)* %a, i16 %b) nounwind {
 define i16 @atomicrmw_add_i16_acq_rel(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_add_i16_acq_rel:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 4
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_add_2
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_add_i16_acq_rel:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB63_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.h.aq a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.h.aq a2, (a0)
 ; RV32IAXCHERI-NEXT:    add a3, a2, a1
-; RV32IAXCHERI-NEXT:    csc.h.rl a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.h.rl a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB63_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -4510,20 +4510,20 @@ define i16 @atomicrmw_add_i16_acq_rel(i16 addrspace(200)* %a, i16 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_add_i16_acq_rel:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 4
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_add_2
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_add_i16_acq_rel:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB63_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.h.aq a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.h.aq a2, (a0)
 ; RV64IAXCHERI-NEXT:    add a3, a2, a1
-; RV64IAXCHERI-NEXT:    csc.h.rl a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.h.rl a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB63_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -4535,20 +4535,20 @@ define i16 @atomicrmw_add_i16_acq_rel(i16 addrspace(200)* %a, i16 %b) nounwind {
 define i16 @atomicrmw_add_i16_seq_cst(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_add_i16_seq_cst:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 5
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_add_2
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_add_i16_seq_cst:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB64_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.h.aqrl a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.h.aqrl a2, (a0)
 ; RV32IAXCHERI-NEXT:    add a3, a2, a1
-; RV32IAXCHERI-NEXT:    csc.h.aqrl a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.h.aqrl a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB64_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -4556,20 +4556,20 @@ define i16 @atomicrmw_add_i16_seq_cst(i16 addrspace(200)* %a, i16 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_add_i16_seq_cst:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 5
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_add_2
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_add_i16_seq_cst:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB64_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.h.aqrl a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.h.aqrl a2, (a0)
 ; RV64IAXCHERI-NEXT:    add a3, a2, a1
-; RV64IAXCHERI-NEXT:    csc.h.aqrl a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.h.aqrl a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB64_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -4581,21 +4581,21 @@ define i16 @atomicrmw_add_i16_seq_cst(i16 addrspace(200)* %a, i16 %b) nounwind {
 define i16 @atomicrmw_sub_i16_monotonic(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_sub_i16_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_sub_2
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_sub_i16_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:    neg a2, a1
 ; RV32IAXCHERI-NEXT:  .LBB65_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.h a1, (ca0)
+; RV32IAXCHERI-NEXT:    clr.h a1, (a0)
 ; RV32IAXCHERI-NEXT:    add a3, a1, a2
-; RV32IAXCHERI-NEXT:    csc.h a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.h a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB65_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a1
@@ -4603,21 +4603,21 @@ define i16 @atomicrmw_sub_i16_monotonic(i16 addrspace(200)* %a, i16 %b) nounwind
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_sub_i16_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_sub_2
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_sub_i16_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:    neg a2, a1
 ; RV64IAXCHERI-NEXT:  .LBB65_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.h a1, (ca0)
+; RV64IAXCHERI-NEXT:    clr.h a1, (a0)
 ; RV64IAXCHERI-NEXT:    add a3, a1, a2
-; RV64IAXCHERI-NEXT:    csc.h a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.h a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB65_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a1
@@ -4629,21 +4629,21 @@ define i16 @atomicrmw_sub_i16_monotonic(i16 addrspace(200)* %a, i16 %b) nounwind
 define i16 @atomicrmw_sub_i16_acquire(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_sub_i16_acquire:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 2
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_sub_2
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_sub_i16_acquire:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:    neg a2, a1
 ; RV32IAXCHERI-NEXT:  .LBB66_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.h.aq a1, (ca0)
+; RV32IAXCHERI-NEXT:    clr.h.aq a1, (a0)
 ; RV32IAXCHERI-NEXT:    add a3, a1, a2
-; RV32IAXCHERI-NEXT:    csc.h a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.h a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB66_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a1
@@ -4651,21 +4651,21 @@ define i16 @atomicrmw_sub_i16_acquire(i16 addrspace(200)* %a, i16 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_sub_i16_acquire:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 2
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_sub_2
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_sub_i16_acquire:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:    neg a2, a1
 ; RV64IAXCHERI-NEXT:  .LBB66_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.h.aq a1, (ca0)
+; RV64IAXCHERI-NEXT:    clr.h.aq a1, (a0)
 ; RV64IAXCHERI-NEXT:    add a3, a1, a2
-; RV64IAXCHERI-NEXT:    csc.h a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.h a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB66_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a1
@@ -4677,21 +4677,21 @@ define i16 @atomicrmw_sub_i16_acquire(i16 addrspace(200)* %a, i16 %b) nounwind {
 define i16 @atomicrmw_sub_i16_release(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_sub_i16_release:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 3
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_sub_2
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_sub_i16_release:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:    neg a2, a1
 ; RV32IAXCHERI-NEXT:  .LBB67_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.h a1, (ca0)
+; RV32IAXCHERI-NEXT:    clr.h a1, (a0)
 ; RV32IAXCHERI-NEXT:    add a3, a1, a2
-; RV32IAXCHERI-NEXT:    csc.h.rl a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.h.rl a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB67_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a1
@@ -4699,21 +4699,21 @@ define i16 @atomicrmw_sub_i16_release(i16 addrspace(200)* %a, i16 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_sub_i16_release:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 3
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_sub_2
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_sub_i16_release:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:    neg a2, a1
 ; RV64IAXCHERI-NEXT:  .LBB67_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.h a1, (ca0)
+; RV64IAXCHERI-NEXT:    clr.h a1, (a0)
 ; RV64IAXCHERI-NEXT:    add a3, a1, a2
-; RV64IAXCHERI-NEXT:    csc.h.rl a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.h.rl a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB67_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a1
@@ -4725,21 +4725,21 @@ define i16 @atomicrmw_sub_i16_release(i16 addrspace(200)* %a, i16 %b) nounwind {
 define i16 @atomicrmw_sub_i16_acq_rel(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_sub_i16_acq_rel:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 4
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_sub_2
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_sub_i16_acq_rel:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:    neg a2, a1
 ; RV32IAXCHERI-NEXT:  .LBB68_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.h.aq a1, (ca0)
+; RV32IAXCHERI-NEXT:    clr.h.aq a1, (a0)
 ; RV32IAXCHERI-NEXT:    add a3, a1, a2
-; RV32IAXCHERI-NEXT:    csc.h.rl a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.h.rl a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB68_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a1
@@ -4747,21 +4747,21 @@ define i16 @atomicrmw_sub_i16_acq_rel(i16 addrspace(200)* %a, i16 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_sub_i16_acq_rel:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 4
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_sub_2
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_sub_i16_acq_rel:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:    neg a2, a1
 ; RV64IAXCHERI-NEXT:  .LBB68_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.h.aq a1, (ca0)
+; RV64IAXCHERI-NEXT:    clr.h.aq a1, (a0)
 ; RV64IAXCHERI-NEXT:    add a3, a1, a2
-; RV64IAXCHERI-NEXT:    csc.h.rl a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.h.rl a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB68_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a1
@@ -4773,21 +4773,21 @@ define i16 @atomicrmw_sub_i16_acq_rel(i16 addrspace(200)* %a, i16 %b) nounwind {
 define i16 @atomicrmw_sub_i16_seq_cst(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_sub_i16_seq_cst:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 5
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_sub_2
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_sub_i16_seq_cst:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:    neg a2, a1
 ; RV32IAXCHERI-NEXT:  .LBB69_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.h.aqrl a1, (ca0)
+; RV32IAXCHERI-NEXT:    clr.h.aqrl a1, (a0)
 ; RV32IAXCHERI-NEXT:    add a3, a1, a2
-; RV32IAXCHERI-NEXT:    csc.h.aqrl a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.h.aqrl a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB69_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a1
@@ -4795,21 +4795,21 @@ define i16 @atomicrmw_sub_i16_seq_cst(i16 addrspace(200)* %a, i16 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_sub_i16_seq_cst:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 5
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_sub_2
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_sub_i16_seq_cst:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:    neg a2, a1
 ; RV64IAXCHERI-NEXT:  .LBB69_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.h.aqrl a1, (ca0)
+; RV64IAXCHERI-NEXT:    clr.h.aqrl a1, (a0)
 ; RV64IAXCHERI-NEXT:    add a3, a1, a2
-; RV64IAXCHERI-NEXT:    csc.h.aqrl a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.h.aqrl a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB69_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a1
@@ -4821,20 +4821,20 @@ define i16 @atomicrmw_sub_i16_seq_cst(i16 addrspace(200)* %a, i16 %b) nounwind {
 define i16 @atomicrmw_and_i16_monotonic(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_and_i16_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_and_2
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_and_i16_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB70_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.h a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.h a2, (a0)
 ; RV32IAXCHERI-NEXT:    and a3, a2, a1
-; RV32IAXCHERI-NEXT:    csc.h a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.h a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB70_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -4842,20 +4842,20 @@ define i16 @atomicrmw_and_i16_monotonic(i16 addrspace(200)* %a, i16 %b) nounwind
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_and_i16_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_and_2
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_and_i16_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB70_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.h a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.h a2, (a0)
 ; RV64IAXCHERI-NEXT:    and a3, a2, a1
-; RV64IAXCHERI-NEXT:    csc.h a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.h a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB70_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -4867,20 +4867,20 @@ define i16 @atomicrmw_and_i16_monotonic(i16 addrspace(200)* %a, i16 %b) nounwind
 define i16 @atomicrmw_and_i16_acquire(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_and_i16_acquire:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 2
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_and_2
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_and_i16_acquire:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB71_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.h.aq a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.h.aq a2, (a0)
 ; RV32IAXCHERI-NEXT:    and a3, a2, a1
-; RV32IAXCHERI-NEXT:    csc.h a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.h a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB71_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -4888,20 +4888,20 @@ define i16 @atomicrmw_and_i16_acquire(i16 addrspace(200)* %a, i16 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_and_i16_acquire:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 2
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_and_2
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_and_i16_acquire:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB71_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.h.aq a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.h.aq a2, (a0)
 ; RV64IAXCHERI-NEXT:    and a3, a2, a1
-; RV64IAXCHERI-NEXT:    csc.h a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.h a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB71_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -4913,20 +4913,20 @@ define i16 @atomicrmw_and_i16_acquire(i16 addrspace(200)* %a, i16 %b) nounwind {
 define i16 @atomicrmw_and_i16_release(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_and_i16_release:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 3
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_and_2
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_and_i16_release:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB72_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.h a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.h a2, (a0)
 ; RV32IAXCHERI-NEXT:    and a3, a2, a1
-; RV32IAXCHERI-NEXT:    csc.h.rl a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.h.rl a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB72_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -4934,20 +4934,20 @@ define i16 @atomicrmw_and_i16_release(i16 addrspace(200)* %a, i16 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_and_i16_release:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 3
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_and_2
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_and_i16_release:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB72_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.h a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.h a2, (a0)
 ; RV64IAXCHERI-NEXT:    and a3, a2, a1
-; RV64IAXCHERI-NEXT:    csc.h.rl a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.h.rl a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB72_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -4959,20 +4959,20 @@ define i16 @atomicrmw_and_i16_release(i16 addrspace(200)* %a, i16 %b) nounwind {
 define i16 @atomicrmw_and_i16_acq_rel(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_and_i16_acq_rel:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 4
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_and_2
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_and_i16_acq_rel:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB73_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.h.aq a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.h.aq a2, (a0)
 ; RV32IAXCHERI-NEXT:    and a3, a2, a1
-; RV32IAXCHERI-NEXT:    csc.h.rl a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.h.rl a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB73_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -4980,20 +4980,20 @@ define i16 @atomicrmw_and_i16_acq_rel(i16 addrspace(200)* %a, i16 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_and_i16_acq_rel:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 4
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_and_2
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_and_i16_acq_rel:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB73_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.h.aq a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.h.aq a2, (a0)
 ; RV64IAXCHERI-NEXT:    and a3, a2, a1
-; RV64IAXCHERI-NEXT:    csc.h.rl a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.h.rl a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB73_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -5005,20 +5005,20 @@ define i16 @atomicrmw_and_i16_acq_rel(i16 addrspace(200)* %a, i16 %b) nounwind {
 define i16 @atomicrmw_and_i16_seq_cst(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_and_i16_seq_cst:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 5
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_and_2
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_and_i16_seq_cst:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB74_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.h.aqrl a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.h.aqrl a2, (a0)
 ; RV32IAXCHERI-NEXT:    and a3, a2, a1
-; RV32IAXCHERI-NEXT:    csc.h.aqrl a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.h.aqrl a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB74_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -5026,20 +5026,20 @@ define i16 @atomicrmw_and_i16_seq_cst(i16 addrspace(200)* %a, i16 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_and_i16_seq_cst:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 5
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_and_2
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_and_i16_seq_cst:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB74_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.h.aqrl a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.h.aqrl a2, (a0)
 ; RV64IAXCHERI-NEXT:    and a3, a2, a1
-; RV64IAXCHERI-NEXT:    csc.h.aqrl a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.h.aqrl a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB74_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -5051,21 +5051,21 @@ define i16 @atomicrmw_and_i16_seq_cst(i16 addrspace(200)* %a, i16 %b) nounwind {
 define i16 @atomicrmw_nand_i16_monotonic(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_nand_i16_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_nand_2
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_nand_i16_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB75_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.h a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.h a2, (a0)
 ; RV32IAXCHERI-NEXT:    and a3, a2, a1
 ; RV32IAXCHERI-NEXT:    not a3, a3
-; RV32IAXCHERI-NEXT:    csc.h a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.h a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB75_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -5073,21 +5073,21 @@ define i16 @atomicrmw_nand_i16_monotonic(i16 addrspace(200)* %a, i16 %b) nounwin
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_nand_i16_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_nand_2
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_nand_i16_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB75_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.h a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.h a2, (a0)
 ; RV64IAXCHERI-NEXT:    and a3, a2, a1
 ; RV64IAXCHERI-NEXT:    not a3, a3
-; RV64IAXCHERI-NEXT:    csc.h a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.h a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB75_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -5099,21 +5099,21 @@ define i16 @atomicrmw_nand_i16_monotonic(i16 addrspace(200)* %a, i16 %b) nounwin
 define i16 @atomicrmw_nand_i16_acquire(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_nand_i16_acquire:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 2
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_nand_2
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_nand_i16_acquire:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB76_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.h.aq a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.h.aq a2, (a0)
 ; RV32IAXCHERI-NEXT:    and a3, a2, a1
 ; RV32IAXCHERI-NEXT:    not a3, a3
-; RV32IAXCHERI-NEXT:    csc.h a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.h a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB76_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -5121,21 +5121,21 @@ define i16 @atomicrmw_nand_i16_acquire(i16 addrspace(200)* %a, i16 %b) nounwind
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_nand_i16_acquire:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 2
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_nand_2
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_nand_i16_acquire:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB76_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.h.aq a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.h.aq a2, (a0)
 ; RV64IAXCHERI-NEXT:    and a3, a2, a1
 ; RV64IAXCHERI-NEXT:    not a3, a3
-; RV64IAXCHERI-NEXT:    csc.h a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.h a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB76_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -5147,21 +5147,21 @@ define i16 @atomicrmw_nand_i16_acquire(i16 addrspace(200)* %a, i16 %b) nounwind
 define i16 @atomicrmw_nand_i16_release(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_nand_i16_release:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 3
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_nand_2
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_nand_i16_release:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB77_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.h a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.h a2, (a0)
 ; RV32IAXCHERI-NEXT:    and a3, a2, a1
 ; RV32IAXCHERI-NEXT:    not a3, a3
-; RV32IAXCHERI-NEXT:    csc.h.rl a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.h.rl a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB77_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -5169,21 +5169,21 @@ define i16 @atomicrmw_nand_i16_release(i16 addrspace(200)* %a, i16 %b) nounwind
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_nand_i16_release:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 3
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_nand_2
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_nand_i16_release:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB77_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.h a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.h a2, (a0)
 ; RV64IAXCHERI-NEXT:    and a3, a2, a1
 ; RV64IAXCHERI-NEXT:    not a3, a3
-; RV64IAXCHERI-NEXT:    csc.h.rl a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.h.rl a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB77_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -5195,21 +5195,21 @@ define i16 @atomicrmw_nand_i16_release(i16 addrspace(200)* %a, i16 %b) nounwind
 define i16 @atomicrmw_nand_i16_acq_rel(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_nand_i16_acq_rel:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 4
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_nand_2
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_nand_i16_acq_rel:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB78_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.h.aq a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.h.aq a2, (a0)
 ; RV32IAXCHERI-NEXT:    and a3, a2, a1
 ; RV32IAXCHERI-NEXT:    not a3, a3
-; RV32IAXCHERI-NEXT:    csc.h.rl a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.h.rl a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB78_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -5217,21 +5217,21 @@ define i16 @atomicrmw_nand_i16_acq_rel(i16 addrspace(200)* %a, i16 %b) nounwind
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_nand_i16_acq_rel:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 4
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_nand_2
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_nand_i16_acq_rel:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB78_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.h.aq a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.h.aq a2, (a0)
 ; RV64IAXCHERI-NEXT:    and a3, a2, a1
 ; RV64IAXCHERI-NEXT:    not a3, a3
-; RV64IAXCHERI-NEXT:    csc.h.rl a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.h.rl a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB78_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -5243,21 +5243,21 @@ define i16 @atomicrmw_nand_i16_acq_rel(i16 addrspace(200)* %a, i16 %b) nounwind
 define i16 @atomicrmw_nand_i16_seq_cst(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_nand_i16_seq_cst:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 5
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_nand_2
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_nand_i16_seq_cst:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB79_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.h.aqrl a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.h.aqrl a2, (a0)
 ; RV32IAXCHERI-NEXT:    and a3, a2, a1
 ; RV32IAXCHERI-NEXT:    not a3, a3
-; RV32IAXCHERI-NEXT:    csc.h.aqrl a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.h.aqrl a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB79_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -5265,21 +5265,21 @@ define i16 @atomicrmw_nand_i16_seq_cst(i16 addrspace(200)* %a, i16 %b) nounwind
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_nand_i16_seq_cst:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 5
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_nand_2
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_nand_i16_seq_cst:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB79_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.h.aqrl a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.h.aqrl a2, (a0)
 ; RV64IAXCHERI-NEXT:    and a3, a2, a1
 ; RV64IAXCHERI-NEXT:    not a3, a3
-; RV64IAXCHERI-NEXT:    csc.h.aqrl a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.h.aqrl a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB79_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -5291,20 +5291,20 @@ define i16 @atomicrmw_nand_i16_seq_cst(i16 addrspace(200)* %a, i16 %b) nounwind
 define i16 @atomicrmw_or_i16_monotonic(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_or_i16_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_or_2
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_or_i16_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB80_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.h a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.h a2, (a0)
 ; RV32IAXCHERI-NEXT:    or a3, a2, a1
-; RV32IAXCHERI-NEXT:    csc.h a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.h a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB80_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -5312,20 +5312,20 @@ define i16 @atomicrmw_or_i16_monotonic(i16 addrspace(200)* %a, i16 %b) nounwind
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_or_i16_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_or_2
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_or_i16_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB80_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.h a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.h a2, (a0)
 ; RV64IAXCHERI-NEXT:    or a3, a2, a1
-; RV64IAXCHERI-NEXT:    csc.h a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.h a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB80_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -5337,20 +5337,20 @@ define i16 @atomicrmw_or_i16_monotonic(i16 addrspace(200)* %a, i16 %b) nounwind
 define i16 @atomicrmw_or_i16_acquire(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_or_i16_acquire:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 2
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_or_2
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_or_i16_acquire:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB81_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.h.aq a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.h.aq a2, (a0)
 ; RV32IAXCHERI-NEXT:    or a3, a2, a1
-; RV32IAXCHERI-NEXT:    csc.h a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.h a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB81_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -5358,20 +5358,20 @@ define i16 @atomicrmw_or_i16_acquire(i16 addrspace(200)* %a, i16 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_or_i16_acquire:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 2
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_or_2
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_or_i16_acquire:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB81_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.h.aq a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.h.aq a2, (a0)
 ; RV64IAXCHERI-NEXT:    or a3, a2, a1
-; RV64IAXCHERI-NEXT:    csc.h a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.h a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB81_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -5383,20 +5383,20 @@ define i16 @atomicrmw_or_i16_acquire(i16 addrspace(200)* %a, i16 %b) nounwind {
 define i16 @atomicrmw_or_i16_release(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_or_i16_release:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 3
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_or_2
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_or_i16_release:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB82_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.h a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.h a2, (a0)
 ; RV32IAXCHERI-NEXT:    or a3, a2, a1
-; RV32IAXCHERI-NEXT:    csc.h.rl a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.h.rl a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB82_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -5404,20 +5404,20 @@ define i16 @atomicrmw_or_i16_release(i16 addrspace(200)* %a, i16 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_or_i16_release:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 3
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_or_2
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_or_i16_release:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB82_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.h a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.h a2, (a0)
 ; RV64IAXCHERI-NEXT:    or a3, a2, a1
-; RV64IAXCHERI-NEXT:    csc.h.rl a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.h.rl a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB82_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -5429,20 +5429,20 @@ define i16 @atomicrmw_or_i16_release(i16 addrspace(200)* %a, i16 %b) nounwind {
 define i16 @atomicrmw_or_i16_acq_rel(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_or_i16_acq_rel:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 4
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_or_2
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_or_i16_acq_rel:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB83_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.h.aq a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.h.aq a2, (a0)
 ; RV32IAXCHERI-NEXT:    or a3, a2, a1
-; RV32IAXCHERI-NEXT:    csc.h.rl a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.h.rl a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB83_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -5450,20 +5450,20 @@ define i16 @atomicrmw_or_i16_acq_rel(i16 addrspace(200)* %a, i16 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_or_i16_acq_rel:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 4
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_or_2
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_or_i16_acq_rel:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB83_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.h.aq a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.h.aq a2, (a0)
 ; RV64IAXCHERI-NEXT:    or a3, a2, a1
-; RV64IAXCHERI-NEXT:    csc.h.rl a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.h.rl a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB83_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -5475,20 +5475,20 @@ define i16 @atomicrmw_or_i16_acq_rel(i16 addrspace(200)* %a, i16 %b) nounwind {
 define i16 @atomicrmw_or_i16_seq_cst(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_or_i16_seq_cst:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 5
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_or_2
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_or_i16_seq_cst:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB84_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.h.aqrl a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.h.aqrl a2, (a0)
 ; RV32IAXCHERI-NEXT:    or a3, a2, a1
-; RV32IAXCHERI-NEXT:    csc.h.aqrl a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.h.aqrl a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB84_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -5496,20 +5496,20 @@ define i16 @atomicrmw_or_i16_seq_cst(i16 addrspace(200)* %a, i16 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_or_i16_seq_cst:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 5
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_or_2
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_or_i16_seq_cst:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB84_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.h.aqrl a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.h.aqrl a2, (a0)
 ; RV64IAXCHERI-NEXT:    or a3, a2, a1
-; RV64IAXCHERI-NEXT:    csc.h.aqrl a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.h.aqrl a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB84_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -5521,20 +5521,20 @@ define i16 @atomicrmw_or_i16_seq_cst(i16 addrspace(200)* %a, i16 %b) nounwind {
 define i16 @atomicrmw_xor_i16_monotonic(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_xor_i16_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_xor_2
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_xor_i16_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB85_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.h a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.h a2, (a0)
 ; RV32IAXCHERI-NEXT:    xor a3, a2, a1
-; RV32IAXCHERI-NEXT:    csc.h a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.h a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB85_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -5542,20 +5542,20 @@ define i16 @atomicrmw_xor_i16_monotonic(i16 addrspace(200)* %a, i16 %b) nounwind
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_xor_i16_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_xor_2
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_xor_i16_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB85_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.h a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.h a2, (a0)
 ; RV64IAXCHERI-NEXT:    xor a3, a2, a1
-; RV64IAXCHERI-NEXT:    csc.h a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.h a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB85_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -5567,20 +5567,20 @@ define i16 @atomicrmw_xor_i16_monotonic(i16 addrspace(200)* %a, i16 %b) nounwind
 define i16 @atomicrmw_xor_i16_acquire(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_xor_i16_acquire:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 2
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_xor_2
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_xor_i16_acquire:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB86_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.h.aq a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.h.aq a2, (a0)
 ; RV32IAXCHERI-NEXT:    xor a3, a2, a1
-; RV32IAXCHERI-NEXT:    csc.h a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.h a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB86_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -5588,20 +5588,20 @@ define i16 @atomicrmw_xor_i16_acquire(i16 addrspace(200)* %a, i16 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_xor_i16_acquire:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 2
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_xor_2
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_xor_i16_acquire:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB86_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.h.aq a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.h.aq a2, (a0)
 ; RV64IAXCHERI-NEXT:    xor a3, a2, a1
-; RV64IAXCHERI-NEXT:    csc.h a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.h a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB86_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -5613,20 +5613,20 @@ define i16 @atomicrmw_xor_i16_acquire(i16 addrspace(200)* %a, i16 %b) nounwind {
 define i16 @atomicrmw_xor_i16_release(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_xor_i16_release:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 3
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_xor_2
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_xor_i16_release:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB87_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.h a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.h a2, (a0)
 ; RV32IAXCHERI-NEXT:    xor a3, a2, a1
-; RV32IAXCHERI-NEXT:    csc.h.rl a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.h.rl a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB87_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -5634,20 +5634,20 @@ define i16 @atomicrmw_xor_i16_release(i16 addrspace(200)* %a, i16 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_xor_i16_release:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 3
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_xor_2
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_xor_i16_release:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB87_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.h a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.h a2, (a0)
 ; RV64IAXCHERI-NEXT:    xor a3, a2, a1
-; RV64IAXCHERI-NEXT:    csc.h.rl a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.h.rl a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB87_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -5659,20 +5659,20 @@ define i16 @atomicrmw_xor_i16_release(i16 addrspace(200)* %a, i16 %b) nounwind {
 define i16 @atomicrmw_xor_i16_acq_rel(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_xor_i16_acq_rel:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 4
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_xor_2
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_xor_i16_acq_rel:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB88_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.h.aq a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.h.aq a2, (a0)
 ; RV32IAXCHERI-NEXT:    xor a3, a2, a1
-; RV32IAXCHERI-NEXT:    csc.h.rl a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.h.rl a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB88_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -5680,20 +5680,20 @@ define i16 @atomicrmw_xor_i16_acq_rel(i16 addrspace(200)* %a, i16 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_xor_i16_acq_rel:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 4
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_xor_2
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_xor_i16_acq_rel:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB88_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.h.aq a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.h.aq a2, (a0)
 ; RV64IAXCHERI-NEXT:    xor a3, a2, a1
-; RV64IAXCHERI-NEXT:    csc.h.rl a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.h.rl a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB88_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -5705,20 +5705,20 @@ define i16 @atomicrmw_xor_i16_acq_rel(i16 addrspace(200)* %a, i16 %b) nounwind {
 define i16 @atomicrmw_xor_i16_seq_cst(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_xor_i16_seq_cst:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 5
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_xor_2
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_xor_i16_seq_cst:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB89_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.h.aqrl a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.h.aqrl a2, (a0)
 ; RV32IAXCHERI-NEXT:    xor a3, a2, a1
-; RV32IAXCHERI-NEXT:    csc.h.aqrl a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.h.aqrl a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB89_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -5726,20 +5726,20 @@ define i16 @atomicrmw_xor_i16_seq_cst(i16 addrspace(200)* %a, i16 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_xor_i16_seq_cst:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 5
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_xor_2
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_xor_i16_seq_cst:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB89_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.h.aqrl a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.h.aqrl a2, (a0)
 ; RV64IAXCHERI-NEXT:    xor a3, a2, a1
-; RV64IAXCHERI-NEXT:    csc.h.aqrl a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.h.aqrl a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB89_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -5751,29 +5751,29 @@ define i16 @atomicrmw_xor_i16_seq_cst(i16 addrspace(200)* %a, i16 %b) nounwind {
 define i16 @atomicrmw_max_i16_monotonic(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_max_i16_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs3, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    mv s2, a1
-; RV32IXCHERI-NEXT:    cmove cs1, ca0
-; RV32IXCHERI-NEXT:    clhu a1, 0(ca0)
-; RV32IXCHERI-NEXT:    slli a0, s2, 16
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s3, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    mv s0, a1
+; RV32IXCHERI-NEXT:    cmove s1, a0
+; RV32IXCHERI-NEXT:    clhu a1, 0(a0)
+; RV32IXCHERI-NEXT:    slli a0, s0, 16
 ; RV32IXCHERI-NEXT:    srai s3, a0, 16
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 6
-; RV32IXCHERI-NEXT:    csetbounds cs0, ca0, 2
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 6
+; RV32IXCHERI-NEXT:    csetbounds s2, a0, 2
 ; RV32IXCHERI-NEXT:    j .LBB90_2
 ; RV32IXCHERI-NEXT:  .LBB90_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB90_2 Depth=1
-; RV32IXCHERI-NEXT:    csh a1, 6(csp)
-; RV32IXCHERI-NEXT:    cmove ca0, cs1
-; RV32IXCHERI-NEXT:    cmove ca1, cs0
+; RV32IXCHERI-NEXT:    csh a1, 6(sp)
+; RV32IXCHERI-NEXT:    cmove a0, s1
+; RV32IXCHERI-NEXT:    cmove a1, s2
 ; RV32IXCHERI-NEXT:    li a3, 0
 ; RV32IXCHERI-NEXT:    li a4, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_2
-; RV32IXCHERI-NEXT:    clh a1, 6(csp)
+; RV32IXCHERI-NEXT:    clh a1, 6(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB90_4
 ; RV32IXCHERI-NEXT:  .LBB90_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -5783,28 +5783,28 @@ define i16 @atomicrmw_max_i16_monotonic(i16 addrspace(200)* %a, i16 %b) nounwind
 ; RV32IXCHERI-NEXT:    blt s3, a0, .LBB90_1
 ; RV32IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB90_2 Depth=1
-; RV32IXCHERI-NEXT:    mv a2, s2
+; RV32IXCHERI-NEXT:    mv a2, s0
 ; RV32IXCHERI-NEXT:    j .LBB90_1
 ; RV32IXCHERI-NEXT:  .LBB90_4: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a1
-; RV32IXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs3, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s3, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_max_i16_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB90_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.h a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.h a2, (a0)
 ; RV32IAXCHERI-NEXT:    mv a3, a2
 ; RV32IAXCHERI-NEXT:    bge a3, a1, .LBB90_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB90_1 Depth=1
 ; RV32IAXCHERI-NEXT:    mv a3, a1
 ; RV32IAXCHERI-NEXT:  .LBB90_3: # in Loop: Header=BB90_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.h a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.h a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB90_1
 ; RV32IAXCHERI-NEXT:  # %bb.4:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -5812,29 +5812,29 @@ define i16 @atomicrmw_max_i16_monotonic(i16 addrspace(200)* %a, i16 %b) nounwind
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_max_i16_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -96
-; RV64IXCHERI-NEXT:    csc cra, 80(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs3, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    mv s2, a1
-; RV64IXCHERI-NEXT:    cmove cs1, ca0
-; RV64IXCHERI-NEXT:    clhu a1, 0(ca0)
-; RV64IXCHERI-NEXT:    slli a0, s2, 48
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -96
+; RV64IXCHERI-NEXT:    csc ra, 80(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s3, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    mv s0, a1
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    clhu a1, 0(a0)
+; RV64IXCHERI-NEXT:    slli a0, s0, 48
 ; RV64IXCHERI-NEXT:    srai s3, a0, 48
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 14
-; RV64IXCHERI-NEXT:    csetbounds cs0, ca0, 2
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 14
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 2
 ; RV64IXCHERI-NEXT:    j .LBB90_2
 ; RV64IXCHERI-NEXT:  .LBB90_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB90_2 Depth=1
-; RV64IXCHERI-NEXT:    csh a1, 14(csp)
-; RV64IXCHERI-NEXT:    cmove ca0, cs1
-; RV64IXCHERI-NEXT:    cmove ca1, cs0
+; RV64IXCHERI-NEXT:    csh a1, 14(sp)
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    li a3, 0
 ; RV64IXCHERI-NEXT:    li a4, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_2
-; RV64IXCHERI-NEXT:    clh a1, 14(csp)
+; RV64IXCHERI-NEXT:    clh a1, 14(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB90_4
 ; RV64IXCHERI-NEXT:  .LBB90_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -5844,28 +5844,28 @@ define i16 @atomicrmw_max_i16_monotonic(i16 addrspace(200)* %a, i16 %b) nounwind
 ; RV64IXCHERI-NEXT:    blt s3, a0, .LBB90_1
 ; RV64IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB90_2 Depth=1
-; RV64IXCHERI-NEXT:    mv a2, s2
+; RV64IXCHERI-NEXT:    mv a2, s0
 ; RV64IXCHERI-NEXT:    j .LBB90_1
 ; RV64IXCHERI-NEXT:  .LBB90_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 80(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs3, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 96
+; RV64IXCHERI-NEXT:    clc ra, 80(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s3, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 96
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_max_i16_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB90_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.h a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.h a2, (a0)
 ; RV64IAXCHERI-NEXT:    mv a3, a2
 ; RV64IAXCHERI-NEXT:    bge a3, a1, .LBB90_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB90_1 Depth=1
 ; RV64IAXCHERI-NEXT:    mv a3, a1
 ; RV64IAXCHERI-NEXT:  .LBB90_3: # in Loop: Header=BB90_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.h a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.h a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB90_1
 ; RV64IAXCHERI-NEXT:  # %bb.4:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -5877,29 +5877,29 @@ define i16 @atomicrmw_max_i16_monotonic(i16 addrspace(200)* %a, i16 %b) nounwind
 define i16 @atomicrmw_max_i16_acquire(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_max_i16_acquire:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs3, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    mv s2, a1
-; RV32IXCHERI-NEXT:    cmove cs1, ca0
-; RV32IXCHERI-NEXT:    clhu a1, 0(ca0)
-; RV32IXCHERI-NEXT:    slli a0, s2, 16
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s3, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    mv s0, a1
+; RV32IXCHERI-NEXT:    cmove s1, a0
+; RV32IXCHERI-NEXT:    clhu a1, 0(a0)
+; RV32IXCHERI-NEXT:    slli a0, s0, 16
 ; RV32IXCHERI-NEXT:    srai s3, a0, 16
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 6
-; RV32IXCHERI-NEXT:    csetbounds cs0, ca0, 2
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 6
+; RV32IXCHERI-NEXT:    csetbounds s2, a0, 2
 ; RV32IXCHERI-NEXT:    j .LBB91_2
 ; RV32IXCHERI-NEXT:  .LBB91_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB91_2 Depth=1
-; RV32IXCHERI-NEXT:    csh a1, 6(csp)
+; RV32IXCHERI-NEXT:    csh a1, 6(sp)
 ; RV32IXCHERI-NEXT:    li a3, 2
 ; RV32IXCHERI-NEXT:    li a4, 2
-; RV32IXCHERI-NEXT:    cmove ca0, cs1
-; RV32IXCHERI-NEXT:    cmove ca1, cs0
+; RV32IXCHERI-NEXT:    cmove a0, s1
+; RV32IXCHERI-NEXT:    cmove a1, s2
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_2
-; RV32IXCHERI-NEXT:    clh a1, 6(csp)
+; RV32IXCHERI-NEXT:    clh a1, 6(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB91_4
 ; RV32IXCHERI-NEXT:  .LBB91_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -5909,28 +5909,28 @@ define i16 @atomicrmw_max_i16_acquire(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV32IXCHERI-NEXT:    blt s3, a0, .LBB91_1
 ; RV32IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB91_2 Depth=1
-; RV32IXCHERI-NEXT:    mv a2, s2
+; RV32IXCHERI-NEXT:    mv a2, s0
 ; RV32IXCHERI-NEXT:    j .LBB91_1
 ; RV32IXCHERI-NEXT:  .LBB91_4: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a1
-; RV32IXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs3, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s3, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_max_i16_acquire:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB91_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.h.aq a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.h.aq a2, (a0)
 ; RV32IAXCHERI-NEXT:    mv a3, a2
 ; RV32IAXCHERI-NEXT:    bge a3, a1, .LBB91_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB91_1 Depth=1
 ; RV32IAXCHERI-NEXT:    mv a3, a1
 ; RV32IAXCHERI-NEXT:  .LBB91_3: # in Loop: Header=BB91_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.h a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.h a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB91_1
 ; RV32IAXCHERI-NEXT:  # %bb.4:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -5938,29 +5938,29 @@ define i16 @atomicrmw_max_i16_acquire(i16 addrspace(200)* %a, i16 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_max_i16_acquire:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -96
-; RV64IXCHERI-NEXT:    csc cra, 80(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs3, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    mv s2, a1
-; RV64IXCHERI-NEXT:    cmove cs1, ca0
-; RV64IXCHERI-NEXT:    clhu a1, 0(ca0)
-; RV64IXCHERI-NEXT:    slli a0, s2, 48
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -96
+; RV64IXCHERI-NEXT:    csc ra, 80(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s3, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    mv s0, a1
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    clhu a1, 0(a0)
+; RV64IXCHERI-NEXT:    slli a0, s0, 48
 ; RV64IXCHERI-NEXT:    srai s3, a0, 48
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 14
-; RV64IXCHERI-NEXT:    csetbounds cs0, ca0, 2
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 14
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 2
 ; RV64IXCHERI-NEXT:    j .LBB91_2
 ; RV64IXCHERI-NEXT:  .LBB91_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB91_2 Depth=1
-; RV64IXCHERI-NEXT:    csh a1, 14(csp)
+; RV64IXCHERI-NEXT:    csh a1, 14(sp)
 ; RV64IXCHERI-NEXT:    li a3, 2
 ; RV64IXCHERI-NEXT:    li a4, 2
-; RV64IXCHERI-NEXT:    cmove ca0, cs1
-; RV64IXCHERI-NEXT:    cmove ca1, cs0
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_2
-; RV64IXCHERI-NEXT:    clh a1, 14(csp)
+; RV64IXCHERI-NEXT:    clh a1, 14(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB91_4
 ; RV64IXCHERI-NEXT:  .LBB91_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -5970,28 +5970,28 @@ define i16 @atomicrmw_max_i16_acquire(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV64IXCHERI-NEXT:    blt s3, a0, .LBB91_1
 ; RV64IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB91_2 Depth=1
-; RV64IXCHERI-NEXT:    mv a2, s2
+; RV64IXCHERI-NEXT:    mv a2, s0
 ; RV64IXCHERI-NEXT:    j .LBB91_1
 ; RV64IXCHERI-NEXT:  .LBB91_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 80(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs3, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 96
+; RV64IXCHERI-NEXT:    clc ra, 80(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s3, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 96
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_max_i16_acquire:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB91_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.h.aq a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.h.aq a2, (a0)
 ; RV64IAXCHERI-NEXT:    mv a3, a2
 ; RV64IAXCHERI-NEXT:    bge a3, a1, .LBB91_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB91_1 Depth=1
 ; RV64IAXCHERI-NEXT:    mv a3, a1
 ; RV64IAXCHERI-NEXT:  .LBB91_3: # in Loop: Header=BB91_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.h a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.h a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB91_1
 ; RV64IAXCHERI-NEXT:  # %bb.4:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -6003,29 +6003,29 @@ define i16 @atomicrmw_max_i16_acquire(i16 addrspace(200)* %a, i16 %b) nounwind {
 define i16 @atomicrmw_max_i16_release(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_max_i16_release:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs3, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    mv s2, a1
-; RV32IXCHERI-NEXT:    cmove cs1, ca0
-; RV32IXCHERI-NEXT:    clhu a1, 0(ca0)
-; RV32IXCHERI-NEXT:    slli a0, s2, 16
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s3, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    mv s0, a1
+; RV32IXCHERI-NEXT:    cmove s1, a0
+; RV32IXCHERI-NEXT:    clhu a1, 0(a0)
+; RV32IXCHERI-NEXT:    slli a0, s0, 16
 ; RV32IXCHERI-NEXT:    srai s3, a0, 16
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 6
-; RV32IXCHERI-NEXT:    csetbounds cs0, ca0, 2
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 6
+; RV32IXCHERI-NEXT:    csetbounds s2, a0, 2
 ; RV32IXCHERI-NEXT:    j .LBB92_2
 ; RV32IXCHERI-NEXT:  .LBB92_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB92_2 Depth=1
-; RV32IXCHERI-NEXT:    csh a1, 6(csp)
+; RV32IXCHERI-NEXT:    csh a1, 6(sp)
 ; RV32IXCHERI-NEXT:    li a3, 3
-; RV32IXCHERI-NEXT:    cmove ca0, cs1
-; RV32IXCHERI-NEXT:    cmove ca1, cs0
+; RV32IXCHERI-NEXT:    cmove a0, s1
+; RV32IXCHERI-NEXT:    cmove a1, s2
 ; RV32IXCHERI-NEXT:    li a4, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_2
-; RV32IXCHERI-NEXT:    clh a1, 6(csp)
+; RV32IXCHERI-NEXT:    clh a1, 6(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB92_4
 ; RV32IXCHERI-NEXT:  .LBB92_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -6035,28 +6035,28 @@ define i16 @atomicrmw_max_i16_release(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV32IXCHERI-NEXT:    blt s3, a0, .LBB92_1
 ; RV32IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB92_2 Depth=1
-; RV32IXCHERI-NEXT:    mv a2, s2
+; RV32IXCHERI-NEXT:    mv a2, s0
 ; RV32IXCHERI-NEXT:    j .LBB92_1
 ; RV32IXCHERI-NEXT:  .LBB92_4: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a1
-; RV32IXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs3, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s3, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_max_i16_release:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB92_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.h a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.h a2, (a0)
 ; RV32IAXCHERI-NEXT:    mv a3, a2
 ; RV32IAXCHERI-NEXT:    bge a3, a1, .LBB92_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB92_1 Depth=1
 ; RV32IAXCHERI-NEXT:    mv a3, a1
 ; RV32IAXCHERI-NEXT:  .LBB92_3: # in Loop: Header=BB92_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.h.rl a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.h.rl a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB92_1
 ; RV32IAXCHERI-NEXT:  # %bb.4:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -6064,29 +6064,29 @@ define i16 @atomicrmw_max_i16_release(i16 addrspace(200)* %a, i16 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_max_i16_release:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -96
-; RV64IXCHERI-NEXT:    csc cra, 80(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs3, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    mv s2, a1
-; RV64IXCHERI-NEXT:    cmove cs1, ca0
-; RV64IXCHERI-NEXT:    clhu a1, 0(ca0)
-; RV64IXCHERI-NEXT:    slli a0, s2, 48
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -96
+; RV64IXCHERI-NEXT:    csc ra, 80(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s3, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    mv s0, a1
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    clhu a1, 0(a0)
+; RV64IXCHERI-NEXT:    slli a0, s0, 48
 ; RV64IXCHERI-NEXT:    srai s3, a0, 48
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 14
-; RV64IXCHERI-NEXT:    csetbounds cs0, ca0, 2
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 14
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 2
 ; RV64IXCHERI-NEXT:    j .LBB92_2
 ; RV64IXCHERI-NEXT:  .LBB92_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB92_2 Depth=1
-; RV64IXCHERI-NEXT:    csh a1, 14(csp)
+; RV64IXCHERI-NEXT:    csh a1, 14(sp)
 ; RV64IXCHERI-NEXT:    li a3, 3
-; RV64IXCHERI-NEXT:    cmove ca0, cs1
-; RV64IXCHERI-NEXT:    cmove ca1, cs0
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    li a4, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_2
-; RV64IXCHERI-NEXT:    clh a1, 14(csp)
+; RV64IXCHERI-NEXT:    clh a1, 14(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB92_4
 ; RV64IXCHERI-NEXT:  .LBB92_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -6096,28 +6096,28 @@ define i16 @atomicrmw_max_i16_release(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV64IXCHERI-NEXT:    blt s3, a0, .LBB92_1
 ; RV64IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB92_2 Depth=1
-; RV64IXCHERI-NEXT:    mv a2, s2
+; RV64IXCHERI-NEXT:    mv a2, s0
 ; RV64IXCHERI-NEXT:    j .LBB92_1
 ; RV64IXCHERI-NEXT:  .LBB92_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 80(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs3, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 96
+; RV64IXCHERI-NEXT:    clc ra, 80(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s3, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 96
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_max_i16_release:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB92_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.h a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.h a2, (a0)
 ; RV64IAXCHERI-NEXT:    mv a3, a2
 ; RV64IAXCHERI-NEXT:    bge a3, a1, .LBB92_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB92_1 Depth=1
 ; RV64IAXCHERI-NEXT:    mv a3, a1
 ; RV64IAXCHERI-NEXT:  .LBB92_3: # in Loop: Header=BB92_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.h.rl a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.h.rl a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB92_1
 ; RV64IAXCHERI-NEXT:  # %bb.4:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -6129,29 +6129,29 @@ define i16 @atomicrmw_max_i16_release(i16 addrspace(200)* %a, i16 %b) nounwind {
 define i16 @atomicrmw_max_i16_acq_rel(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_max_i16_acq_rel:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs3, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    mv s2, a1
-; RV32IXCHERI-NEXT:    cmove cs1, ca0
-; RV32IXCHERI-NEXT:    clhu a1, 0(ca0)
-; RV32IXCHERI-NEXT:    slli a0, s2, 16
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s3, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    mv s0, a1
+; RV32IXCHERI-NEXT:    cmove s1, a0
+; RV32IXCHERI-NEXT:    clhu a1, 0(a0)
+; RV32IXCHERI-NEXT:    slli a0, s0, 16
 ; RV32IXCHERI-NEXT:    srai s3, a0, 16
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 6
-; RV32IXCHERI-NEXT:    csetbounds cs0, ca0, 2
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 6
+; RV32IXCHERI-NEXT:    csetbounds s2, a0, 2
 ; RV32IXCHERI-NEXT:    j .LBB93_2
 ; RV32IXCHERI-NEXT:  .LBB93_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB93_2 Depth=1
-; RV32IXCHERI-NEXT:    csh a1, 6(csp)
+; RV32IXCHERI-NEXT:    csh a1, 6(sp)
 ; RV32IXCHERI-NEXT:    li a3, 4
 ; RV32IXCHERI-NEXT:    li a4, 2
-; RV32IXCHERI-NEXT:    cmove ca0, cs1
-; RV32IXCHERI-NEXT:    cmove ca1, cs0
+; RV32IXCHERI-NEXT:    cmove a0, s1
+; RV32IXCHERI-NEXT:    cmove a1, s2
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_2
-; RV32IXCHERI-NEXT:    clh a1, 6(csp)
+; RV32IXCHERI-NEXT:    clh a1, 6(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB93_4
 ; RV32IXCHERI-NEXT:  .LBB93_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -6161,28 +6161,28 @@ define i16 @atomicrmw_max_i16_acq_rel(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV32IXCHERI-NEXT:    blt s3, a0, .LBB93_1
 ; RV32IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB93_2 Depth=1
-; RV32IXCHERI-NEXT:    mv a2, s2
+; RV32IXCHERI-NEXT:    mv a2, s0
 ; RV32IXCHERI-NEXT:    j .LBB93_1
 ; RV32IXCHERI-NEXT:  .LBB93_4: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a1
-; RV32IXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs3, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s3, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_max_i16_acq_rel:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB93_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.h.aq a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.h.aq a2, (a0)
 ; RV32IAXCHERI-NEXT:    mv a3, a2
 ; RV32IAXCHERI-NEXT:    bge a3, a1, .LBB93_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB93_1 Depth=1
 ; RV32IAXCHERI-NEXT:    mv a3, a1
 ; RV32IAXCHERI-NEXT:  .LBB93_3: # in Loop: Header=BB93_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.h.rl a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.h.rl a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB93_1
 ; RV32IAXCHERI-NEXT:  # %bb.4:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -6190,29 +6190,29 @@ define i16 @atomicrmw_max_i16_acq_rel(i16 addrspace(200)* %a, i16 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_max_i16_acq_rel:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -96
-; RV64IXCHERI-NEXT:    csc cra, 80(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs3, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    mv s2, a1
-; RV64IXCHERI-NEXT:    cmove cs1, ca0
-; RV64IXCHERI-NEXT:    clhu a1, 0(ca0)
-; RV64IXCHERI-NEXT:    slli a0, s2, 48
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -96
+; RV64IXCHERI-NEXT:    csc ra, 80(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s3, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    mv s0, a1
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    clhu a1, 0(a0)
+; RV64IXCHERI-NEXT:    slli a0, s0, 48
 ; RV64IXCHERI-NEXT:    srai s3, a0, 48
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 14
-; RV64IXCHERI-NEXT:    csetbounds cs0, ca0, 2
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 14
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 2
 ; RV64IXCHERI-NEXT:    j .LBB93_2
 ; RV64IXCHERI-NEXT:  .LBB93_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB93_2 Depth=1
-; RV64IXCHERI-NEXT:    csh a1, 14(csp)
+; RV64IXCHERI-NEXT:    csh a1, 14(sp)
 ; RV64IXCHERI-NEXT:    li a3, 4
 ; RV64IXCHERI-NEXT:    li a4, 2
-; RV64IXCHERI-NEXT:    cmove ca0, cs1
-; RV64IXCHERI-NEXT:    cmove ca1, cs0
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_2
-; RV64IXCHERI-NEXT:    clh a1, 14(csp)
+; RV64IXCHERI-NEXT:    clh a1, 14(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB93_4
 ; RV64IXCHERI-NEXT:  .LBB93_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -6222,28 +6222,28 @@ define i16 @atomicrmw_max_i16_acq_rel(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV64IXCHERI-NEXT:    blt s3, a0, .LBB93_1
 ; RV64IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB93_2 Depth=1
-; RV64IXCHERI-NEXT:    mv a2, s2
+; RV64IXCHERI-NEXT:    mv a2, s0
 ; RV64IXCHERI-NEXT:    j .LBB93_1
 ; RV64IXCHERI-NEXT:  .LBB93_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 80(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs3, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 96
+; RV64IXCHERI-NEXT:    clc ra, 80(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s3, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 96
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_max_i16_acq_rel:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB93_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.h.aq a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.h.aq a2, (a0)
 ; RV64IAXCHERI-NEXT:    mv a3, a2
 ; RV64IAXCHERI-NEXT:    bge a3, a1, .LBB93_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB93_1 Depth=1
 ; RV64IAXCHERI-NEXT:    mv a3, a1
 ; RV64IAXCHERI-NEXT:  .LBB93_3: # in Loop: Header=BB93_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.h.rl a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.h.rl a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB93_1
 ; RV64IAXCHERI-NEXT:  # %bb.4:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -6255,29 +6255,29 @@ define i16 @atomicrmw_max_i16_acq_rel(i16 addrspace(200)* %a, i16 %b) nounwind {
 define i16 @atomicrmw_max_i16_seq_cst(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_max_i16_seq_cst:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs3, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    mv s2, a1
-; RV32IXCHERI-NEXT:    cmove cs1, ca0
-; RV32IXCHERI-NEXT:    clhu a1, 0(ca0)
-; RV32IXCHERI-NEXT:    slli a0, s2, 16
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s3, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    mv s0, a1
+; RV32IXCHERI-NEXT:    cmove s1, a0
+; RV32IXCHERI-NEXT:    clhu a1, 0(a0)
+; RV32IXCHERI-NEXT:    slli a0, s0, 16
 ; RV32IXCHERI-NEXT:    srai s3, a0, 16
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 6
-; RV32IXCHERI-NEXT:    csetbounds cs0, ca0, 2
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 6
+; RV32IXCHERI-NEXT:    csetbounds s2, a0, 2
 ; RV32IXCHERI-NEXT:    j .LBB94_2
 ; RV32IXCHERI-NEXT:  .LBB94_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB94_2 Depth=1
-; RV32IXCHERI-NEXT:    csh a1, 6(csp)
+; RV32IXCHERI-NEXT:    csh a1, 6(sp)
 ; RV32IXCHERI-NEXT:    li a3, 5
 ; RV32IXCHERI-NEXT:    li a4, 5
-; RV32IXCHERI-NEXT:    cmove ca0, cs1
-; RV32IXCHERI-NEXT:    cmove ca1, cs0
+; RV32IXCHERI-NEXT:    cmove a0, s1
+; RV32IXCHERI-NEXT:    cmove a1, s2
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_2
-; RV32IXCHERI-NEXT:    clh a1, 6(csp)
+; RV32IXCHERI-NEXT:    clh a1, 6(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB94_4
 ; RV32IXCHERI-NEXT:  .LBB94_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -6287,28 +6287,28 @@ define i16 @atomicrmw_max_i16_seq_cst(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV32IXCHERI-NEXT:    blt s3, a0, .LBB94_1
 ; RV32IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB94_2 Depth=1
-; RV32IXCHERI-NEXT:    mv a2, s2
+; RV32IXCHERI-NEXT:    mv a2, s0
 ; RV32IXCHERI-NEXT:    j .LBB94_1
 ; RV32IXCHERI-NEXT:  .LBB94_4: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a1
-; RV32IXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs3, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s3, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_max_i16_seq_cst:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB94_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.h.aqrl a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.h.aqrl a2, (a0)
 ; RV32IAXCHERI-NEXT:    mv a3, a2
 ; RV32IAXCHERI-NEXT:    bge a3, a1, .LBB94_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB94_1 Depth=1
 ; RV32IAXCHERI-NEXT:    mv a3, a1
 ; RV32IAXCHERI-NEXT:  .LBB94_3: # in Loop: Header=BB94_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.h.aqrl a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.h.aqrl a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB94_1
 ; RV32IAXCHERI-NEXT:  # %bb.4:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -6316,29 +6316,29 @@ define i16 @atomicrmw_max_i16_seq_cst(i16 addrspace(200)* %a, i16 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_max_i16_seq_cst:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -96
-; RV64IXCHERI-NEXT:    csc cra, 80(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs3, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    mv s2, a1
-; RV64IXCHERI-NEXT:    cmove cs1, ca0
-; RV64IXCHERI-NEXT:    clhu a1, 0(ca0)
-; RV64IXCHERI-NEXT:    slli a0, s2, 48
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -96
+; RV64IXCHERI-NEXT:    csc ra, 80(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s3, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    mv s0, a1
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    clhu a1, 0(a0)
+; RV64IXCHERI-NEXT:    slli a0, s0, 48
 ; RV64IXCHERI-NEXT:    srai s3, a0, 48
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 14
-; RV64IXCHERI-NEXT:    csetbounds cs0, ca0, 2
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 14
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 2
 ; RV64IXCHERI-NEXT:    j .LBB94_2
 ; RV64IXCHERI-NEXT:  .LBB94_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB94_2 Depth=1
-; RV64IXCHERI-NEXT:    csh a1, 14(csp)
+; RV64IXCHERI-NEXT:    csh a1, 14(sp)
 ; RV64IXCHERI-NEXT:    li a3, 5
 ; RV64IXCHERI-NEXT:    li a4, 5
-; RV64IXCHERI-NEXT:    cmove ca0, cs1
-; RV64IXCHERI-NEXT:    cmove ca1, cs0
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_2
-; RV64IXCHERI-NEXT:    clh a1, 14(csp)
+; RV64IXCHERI-NEXT:    clh a1, 14(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB94_4
 ; RV64IXCHERI-NEXT:  .LBB94_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -6348,28 +6348,28 @@ define i16 @atomicrmw_max_i16_seq_cst(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV64IXCHERI-NEXT:    blt s3, a0, .LBB94_1
 ; RV64IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB94_2 Depth=1
-; RV64IXCHERI-NEXT:    mv a2, s2
+; RV64IXCHERI-NEXT:    mv a2, s0
 ; RV64IXCHERI-NEXT:    j .LBB94_1
 ; RV64IXCHERI-NEXT:  .LBB94_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 80(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs3, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 96
+; RV64IXCHERI-NEXT:    clc ra, 80(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s3, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 96
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_max_i16_seq_cst:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB94_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.h.aqrl a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.h.aqrl a2, (a0)
 ; RV64IAXCHERI-NEXT:    mv a3, a2
 ; RV64IAXCHERI-NEXT:    bge a3, a1, .LBB94_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB94_1 Depth=1
 ; RV64IAXCHERI-NEXT:    mv a3, a1
 ; RV64IAXCHERI-NEXT:  .LBB94_3: # in Loop: Header=BB94_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.h.aqrl a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.h.aqrl a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB94_1
 ; RV64IAXCHERI-NEXT:  # %bb.4:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -6381,29 +6381,29 @@ define i16 @atomicrmw_max_i16_seq_cst(i16 addrspace(200)* %a, i16 %b) nounwind {
 define i16 @atomicrmw_min_i16_monotonic(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_min_i16_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs3, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    mv s2, a1
-; RV32IXCHERI-NEXT:    cmove cs1, ca0
-; RV32IXCHERI-NEXT:    clhu a1, 0(ca0)
-; RV32IXCHERI-NEXT:    slli a0, s2, 16
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s3, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    mv s0, a1
+; RV32IXCHERI-NEXT:    cmove s1, a0
+; RV32IXCHERI-NEXT:    clhu a1, 0(a0)
+; RV32IXCHERI-NEXT:    slli a0, s0, 16
 ; RV32IXCHERI-NEXT:    srai s3, a0, 16
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 6
-; RV32IXCHERI-NEXT:    csetbounds cs0, ca0, 2
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 6
+; RV32IXCHERI-NEXT:    csetbounds s2, a0, 2
 ; RV32IXCHERI-NEXT:    j .LBB95_2
 ; RV32IXCHERI-NEXT:  .LBB95_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB95_2 Depth=1
-; RV32IXCHERI-NEXT:    csh a1, 6(csp)
-; RV32IXCHERI-NEXT:    cmove ca0, cs1
-; RV32IXCHERI-NEXT:    cmove ca1, cs0
+; RV32IXCHERI-NEXT:    csh a1, 6(sp)
+; RV32IXCHERI-NEXT:    cmove a0, s1
+; RV32IXCHERI-NEXT:    cmove a1, s2
 ; RV32IXCHERI-NEXT:    li a3, 0
 ; RV32IXCHERI-NEXT:    li a4, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_2
-; RV32IXCHERI-NEXT:    clh a1, 6(csp)
+; RV32IXCHERI-NEXT:    clh a1, 6(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB95_4
 ; RV32IXCHERI-NEXT:  .LBB95_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -6413,28 +6413,28 @@ define i16 @atomicrmw_min_i16_monotonic(i16 addrspace(200)* %a, i16 %b) nounwind
 ; RV32IXCHERI-NEXT:    bge s3, a0, .LBB95_1
 ; RV32IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB95_2 Depth=1
-; RV32IXCHERI-NEXT:    mv a2, s2
+; RV32IXCHERI-NEXT:    mv a2, s0
 ; RV32IXCHERI-NEXT:    j .LBB95_1
 ; RV32IXCHERI-NEXT:  .LBB95_4: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a1
-; RV32IXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs3, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s3, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_min_i16_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB95_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.h a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.h a2, (a0)
 ; RV32IAXCHERI-NEXT:    mv a3, a2
 ; RV32IAXCHERI-NEXT:    bge a1, a3, .LBB95_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB95_1 Depth=1
 ; RV32IAXCHERI-NEXT:    mv a3, a1
 ; RV32IAXCHERI-NEXT:  .LBB95_3: # in Loop: Header=BB95_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.h a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.h a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB95_1
 ; RV32IAXCHERI-NEXT:  # %bb.4:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -6442,29 +6442,29 @@ define i16 @atomicrmw_min_i16_monotonic(i16 addrspace(200)* %a, i16 %b) nounwind
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_min_i16_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -96
-; RV64IXCHERI-NEXT:    csc cra, 80(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs3, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    mv s2, a1
-; RV64IXCHERI-NEXT:    cmove cs1, ca0
-; RV64IXCHERI-NEXT:    clhu a1, 0(ca0)
-; RV64IXCHERI-NEXT:    slli a0, s2, 48
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -96
+; RV64IXCHERI-NEXT:    csc ra, 80(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s3, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    mv s0, a1
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    clhu a1, 0(a0)
+; RV64IXCHERI-NEXT:    slli a0, s0, 48
 ; RV64IXCHERI-NEXT:    srai s3, a0, 48
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 14
-; RV64IXCHERI-NEXT:    csetbounds cs0, ca0, 2
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 14
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 2
 ; RV64IXCHERI-NEXT:    j .LBB95_2
 ; RV64IXCHERI-NEXT:  .LBB95_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB95_2 Depth=1
-; RV64IXCHERI-NEXT:    csh a1, 14(csp)
-; RV64IXCHERI-NEXT:    cmove ca0, cs1
-; RV64IXCHERI-NEXT:    cmove ca1, cs0
+; RV64IXCHERI-NEXT:    csh a1, 14(sp)
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    li a3, 0
 ; RV64IXCHERI-NEXT:    li a4, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_2
-; RV64IXCHERI-NEXT:    clh a1, 14(csp)
+; RV64IXCHERI-NEXT:    clh a1, 14(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB95_4
 ; RV64IXCHERI-NEXT:  .LBB95_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -6474,28 +6474,28 @@ define i16 @atomicrmw_min_i16_monotonic(i16 addrspace(200)* %a, i16 %b) nounwind
 ; RV64IXCHERI-NEXT:    bge s3, a0, .LBB95_1
 ; RV64IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB95_2 Depth=1
-; RV64IXCHERI-NEXT:    mv a2, s2
+; RV64IXCHERI-NEXT:    mv a2, s0
 ; RV64IXCHERI-NEXT:    j .LBB95_1
 ; RV64IXCHERI-NEXT:  .LBB95_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 80(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs3, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 96
+; RV64IXCHERI-NEXT:    clc ra, 80(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s3, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 96
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_min_i16_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB95_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.h a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.h a2, (a0)
 ; RV64IAXCHERI-NEXT:    mv a3, a2
 ; RV64IAXCHERI-NEXT:    bge a1, a3, .LBB95_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB95_1 Depth=1
 ; RV64IAXCHERI-NEXT:    mv a3, a1
 ; RV64IAXCHERI-NEXT:  .LBB95_3: # in Loop: Header=BB95_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.h a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.h a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB95_1
 ; RV64IAXCHERI-NEXT:  # %bb.4:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -6507,29 +6507,29 @@ define i16 @atomicrmw_min_i16_monotonic(i16 addrspace(200)* %a, i16 %b) nounwind
 define i16 @atomicrmw_min_i16_acquire(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_min_i16_acquire:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs3, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    mv s2, a1
-; RV32IXCHERI-NEXT:    cmove cs1, ca0
-; RV32IXCHERI-NEXT:    clhu a1, 0(ca0)
-; RV32IXCHERI-NEXT:    slli a0, s2, 16
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s3, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    mv s0, a1
+; RV32IXCHERI-NEXT:    cmove s1, a0
+; RV32IXCHERI-NEXT:    clhu a1, 0(a0)
+; RV32IXCHERI-NEXT:    slli a0, s0, 16
 ; RV32IXCHERI-NEXT:    srai s3, a0, 16
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 6
-; RV32IXCHERI-NEXT:    csetbounds cs0, ca0, 2
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 6
+; RV32IXCHERI-NEXT:    csetbounds s2, a0, 2
 ; RV32IXCHERI-NEXT:    j .LBB96_2
 ; RV32IXCHERI-NEXT:  .LBB96_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB96_2 Depth=1
-; RV32IXCHERI-NEXT:    csh a1, 6(csp)
+; RV32IXCHERI-NEXT:    csh a1, 6(sp)
 ; RV32IXCHERI-NEXT:    li a3, 2
 ; RV32IXCHERI-NEXT:    li a4, 2
-; RV32IXCHERI-NEXT:    cmove ca0, cs1
-; RV32IXCHERI-NEXT:    cmove ca1, cs0
+; RV32IXCHERI-NEXT:    cmove a0, s1
+; RV32IXCHERI-NEXT:    cmove a1, s2
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_2
-; RV32IXCHERI-NEXT:    clh a1, 6(csp)
+; RV32IXCHERI-NEXT:    clh a1, 6(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB96_4
 ; RV32IXCHERI-NEXT:  .LBB96_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -6539,28 +6539,28 @@ define i16 @atomicrmw_min_i16_acquire(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV32IXCHERI-NEXT:    bge s3, a0, .LBB96_1
 ; RV32IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB96_2 Depth=1
-; RV32IXCHERI-NEXT:    mv a2, s2
+; RV32IXCHERI-NEXT:    mv a2, s0
 ; RV32IXCHERI-NEXT:    j .LBB96_1
 ; RV32IXCHERI-NEXT:  .LBB96_4: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a1
-; RV32IXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs3, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s3, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_min_i16_acquire:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB96_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.h.aq a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.h.aq a2, (a0)
 ; RV32IAXCHERI-NEXT:    mv a3, a2
 ; RV32IAXCHERI-NEXT:    bge a1, a3, .LBB96_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB96_1 Depth=1
 ; RV32IAXCHERI-NEXT:    mv a3, a1
 ; RV32IAXCHERI-NEXT:  .LBB96_3: # in Loop: Header=BB96_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.h a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.h a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB96_1
 ; RV32IAXCHERI-NEXT:  # %bb.4:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -6568,29 +6568,29 @@ define i16 @atomicrmw_min_i16_acquire(i16 addrspace(200)* %a, i16 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_min_i16_acquire:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -96
-; RV64IXCHERI-NEXT:    csc cra, 80(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs3, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    mv s2, a1
-; RV64IXCHERI-NEXT:    cmove cs1, ca0
-; RV64IXCHERI-NEXT:    clhu a1, 0(ca0)
-; RV64IXCHERI-NEXT:    slli a0, s2, 48
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -96
+; RV64IXCHERI-NEXT:    csc ra, 80(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s3, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    mv s0, a1
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    clhu a1, 0(a0)
+; RV64IXCHERI-NEXT:    slli a0, s0, 48
 ; RV64IXCHERI-NEXT:    srai s3, a0, 48
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 14
-; RV64IXCHERI-NEXT:    csetbounds cs0, ca0, 2
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 14
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 2
 ; RV64IXCHERI-NEXT:    j .LBB96_2
 ; RV64IXCHERI-NEXT:  .LBB96_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB96_2 Depth=1
-; RV64IXCHERI-NEXT:    csh a1, 14(csp)
+; RV64IXCHERI-NEXT:    csh a1, 14(sp)
 ; RV64IXCHERI-NEXT:    li a3, 2
 ; RV64IXCHERI-NEXT:    li a4, 2
-; RV64IXCHERI-NEXT:    cmove ca0, cs1
-; RV64IXCHERI-NEXT:    cmove ca1, cs0
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_2
-; RV64IXCHERI-NEXT:    clh a1, 14(csp)
+; RV64IXCHERI-NEXT:    clh a1, 14(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB96_4
 ; RV64IXCHERI-NEXT:  .LBB96_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -6600,28 +6600,28 @@ define i16 @atomicrmw_min_i16_acquire(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV64IXCHERI-NEXT:    bge s3, a0, .LBB96_1
 ; RV64IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB96_2 Depth=1
-; RV64IXCHERI-NEXT:    mv a2, s2
+; RV64IXCHERI-NEXT:    mv a2, s0
 ; RV64IXCHERI-NEXT:    j .LBB96_1
 ; RV64IXCHERI-NEXT:  .LBB96_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 80(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs3, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 96
+; RV64IXCHERI-NEXT:    clc ra, 80(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s3, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 96
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_min_i16_acquire:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB96_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.h.aq a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.h.aq a2, (a0)
 ; RV64IAXCHERI-NEXT:    mv a3, a2
 ; RV64IAXCHERI-NEXT:    bge a1, a3, .LBB96_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB96_1 Depth=1
 ; RV64IAXCHERI-NEXT:    mv a3, a1
 ; RV64IAXCHERI-NEXT:  .LBB96_3: # in Loop: Header=BB96_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.h a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.h a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB96_1
 ; RV64IAXCHERI-NEXT:  # %bb.4:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -6633,29 +6633,29 @@ define i16 @atomicrmw_min_i16_acquire(i16 addrspace(200)* %a, i16 %b) nounwind {
 define i16 @atomicrmw_min_i16_release(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_min_i16_release:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs3, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    mv s2, a1
-; RV32IXCHERI-NEXT:    cmove cs1, ca0
-; RV32IXCHERI-NEXT:    clhu a1, 0(ca0)
-; RV32IXCHERI-NEXT:    slli a0, s2, 16
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s3, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    mv s0, a1
+; RV32IXCHERI-NEXT:    cmove s1, a0
+; RV32IXCHERI-NEXT:    clhu a1, 0(a0)
+; RV32IXCHERI-NEXT:    slli a0, s0, 16
 ; RV32IXCHERI-NEXT:    srai s3, a0, 16
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 6
-; RV32IXCHERI-NEXT:    csetbounds cs0, ca0, 2
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 6
+; RV32IXCHERI-NEXT:    csetbounds s2, a0, 2
 ; RV32IXCHERI-NEXT:    j .LBB97_2
 ; RV32IXCHERI-NEXT:  .LBB97_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB97_2 Depth=1
-; RV32IXCHERI-NEXT:    csh a1, 6(csp)
+; RV32IXCHERI-NEXT:    csh a1, 6(sp)
 ; RV32IXCHERI-NEXT:    li a3, 3
-; RV32IXCHERI-NEXT:    cmove ca0, cs1
-; RV32IXCHERI-NEXT:    cmove ca1, cs0
+; RV32IXCHERI-NEXT:    cmove a0, s1
+; RV32IXCHERI-NEXT:    cmove a1, s2
 ; RV32IXCHERI-NEXT:    li a4, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_2
-; RV32IXCHERI-NEXT:    clh a1, 6(csp)
+; RV32IXCHERI-NEXT:    clh a1, 6(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB97_4
 ; RV32IXCHERI-NEXT:  .LBB97_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -6665,28 +6665,28 @@ define i16 @atomicrmw_min_i16_release(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV32IXCHERI-NEXT:    bge s3, a0, .LBB97_1
 ; RV32IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB97_2 Depth=1
-; RV32IXCHERI-NEXT:    mv a2, s2
+; RV32IXCHERI-NEXT:    mv a2, s0
 ; RV32IXCHERI-NEXT:    j .LBB97_1
 ; RV32IXCHERI-NEXT:  .LBB97_4: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a1
-; RV32IXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs3, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s3, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_min_i16_release:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB97_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.h a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.h a2, (a0)
 ; RV32IAXCHERI-NEXT:    mv a3, a2
 ; RV32IAXCHERI-NEXT:    bge a1, a3, .LBB97_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB97_1 Depth=1
 ; RV32IAXCHERI-NEXT:    mv a3, a1
 ; RV32IAXCHERI-NEXT:  .LBB97_3: # in Loop: Header=BB97_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.h.rl a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.h.rl a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB97_1
 ; RV32IAXCHERI-NEXT:  # %bb.4:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -6694,29 +6694,29 @@ define i16 @atomicrmw_min_i16_release(i16 addrspace(200)* %a, i16 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_min_i16_release:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -96
-; RV64IXCHERI-NEXT:    csc cra, 80(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs3, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    mv s2, a1
-; RV64IXCHERI-NEXT:    cmove cs1, ca0
-; RV64IXCHERI-NEXT:    clhu a1, 0(ca0)
-; RV64IXCHERI-NEXT:    slli a0, s2, 48
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -96
+; RV64IXCHERI-NEXT:    csc ra, 80(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s3, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    mv s0, a1
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    clhu a1, 0(a0)
+; RV64IXCHERI-NEXT:    slli a0, s0, 48
 ; RV64IXCHERI-NEXT:    srai s3, a0, 48
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 14
-; RV64IXCHERI-NEXT:    csetbounds cs0, ca0, 2
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 14
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 2
 ; RV64IXCHERI-NEXT:    j .LBB97_2
 ; RV64IXCHERI-NEXT:  .LBB97_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB97_2 Depth=1
-; RV64IXCHERI-NEXT:    csh a1, 14(csp)
+; RV64IXCHERI-NEXT:    csh a1, 14(sp)
 ; RV64IXCHERI-NEXT:    li a3, 3
-; RV64IXCHERI-NEXT:    cmove ca0, cs1
-; RV64IXCHERI-NEXT:    cmove ca1, cs0
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    li a4, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_2
-; RV64IXCHERI-NEXT:    clh a1, 14(csp)
+; RV64IXCHERI-NEXT:    clh a1, 14(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB97_4
 ; RV64IXCHERI-NEXT:  .LBB97_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -6726,28 +6726,28 @@ define i16 @atomicrmw_min_i16_release(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV64IXCHERI-NEXT:    bge s3, a0, .LBB97_1
 ; RV64IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB97_2 Depth=1
-; RV64IXCHERI-NEXT:    mv a2, s2
+; RV64IXCHERI-NEXT:    mv a2, s0
 ; RV64IXCHERI-NEXT:    j .LBB97_1
 ; RV64IXCHERI-NEXT:  .LBB97_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 80(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs3, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 96
+; RV64IXCHERI-NEXT:    clc ra, 80(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s3, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 96
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_min_i16_release:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB97_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.h a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.h a2, (a0)
 ; RV64IAXCHERI-NEXT:    mv a3, a2
 ; RV64IAXCHERI-NEXT:    bge a1, a3, .LBB97_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB97_1 Depth=1
 ; RV64IAXCHERI-NEXT:    mv a3, a1
 ; RV64IAXCHERI-NEXT:  .LBB97_3: # in Loop: Header=BB97_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.h.rl a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.h.rl a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB97_1
 ; RV64IAXCHERI-NEXT:  # %bb.4:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -6759,29 +6759,29 @@ define i16 @atomicrmw_min_i16_release(i16 addrspace(200)* %a, i16 %b) nounwind {
 define i16 @atomicrmw_min_i16_acq_rel(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_min_i16_acq_rel:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs3, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    mv s2, a1
-; RV32IXCHERI-NEXT:    cmove cs1, ca0
-; RV32IXCHERI-NEXT:    clhu a1, 0(ca0)
-; RV32IXCHERI-NEXT:    slli a0, s2, 16
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s3, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    mv s0, a1
+; RV32IXCHERI-NEXT:    cmove s1, a0
+; RV32IXCHERI-NEXT:    clhu a1, 0(a0)
+; RV32IXCHERI-NEXT:    slli a0, s0, 16
 ; RV32IXCHERI-NEXT:    srai s3, a0, 16
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 6
-; RV32IXCHERI-NEXT:    csetbounds cs0, ca0, 2
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 6
+; RV32IXCHERI-NEXT:    csetbounds s2, a0, 2
 ; RV32IXCHERI-NEXT:    j .LBB98_2
 ; RV32IXCHERI-NEXT:  .LBB98_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB98_2 Depth=1
-; RV32IXCHERI-NEXT:    csh a1, 6(csp)
+; RV32IXCHERI-NEXT:    csh a1, 6(sp)
 ; RV32IXCHERI-NEXT:    li a3, 4
 ; RV32IXCHERI-NEXT:    li a4, 2
-; RV32IXCHERI-NEXT:    cmove ca0, cs1
-; RV32IXCHERI-NEXT:    cmove ca1, cs0
+; RV32IXCHERI-NEXT:    cmove a0, s1
+; RV32IXCHERI-NEXT:    cmove a1, s2
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_2
-; RV32IXCHERI-NEXT:    clh a1, 6(csp)
+; RV32IXCHERI-NEXT:    clh a1, 6(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB98_4
 ; RV32IXCHERI-NEXT:  .LBB98_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -6791,28 +6791,28 @@ define i16 @atomicrmw_min_i16_acq_rel(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV32IXCHERI-NEXT:    bge s3, a0, .LBB98_1
 ; RV32IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB98_2 Depth=1
-; RV32IXCHERI-NEXT:    mv a2, s2
+; RV32IXCHERI-NEXT:    mv a2, s0
 ; RV32IXCHERI-NEXT:    j .LBB98_1
 ; RV32IXCHERI-NEXT:  .LBB98_4: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a1
-; RV32IXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs3, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s3, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_min_i16_acq_rel:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB98_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.h.aq a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.h.aq a2, (a0)
 ; RV32IAXCHERI-NEXT:    mv a3, a2
 ; RV32IAXCHERI-NEXT:    bge a1, a3, .LBB98_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB98_1 Depth=1
 ; RV32IAXCHERI-NEXT:    mv a3, a1
 ; RV32IAXCHERI-NEXT:  .LBB98_3: # in Loop: Header=BB98_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.h.rl a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.h.rl a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB98_1
 ; RV32IAXCHERI-NEXT:  # %bb.4:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -6820,29 +6820,29 @@ define i16 @atomicrmw_min_i16_acq_rel(i16 addrspace(200)* %a, i16 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_min_i16_acq_rel:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -96
-; RV64IXCHERI-NEXT:    csc cra, 80(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs3, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    mv s2, a1
-; RV64IXCHERI-NEXT:    cmove cs1, ca0
-; RV64IXCHERI-NEXT:    clhu a1, 0(ca0)
-; RV64IXCHERI-NEXT:    slli a0, s2, 48
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -96
+; RV64IXCHERI-NEXT:    csc ra, 80(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s3, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    mv s0, a1
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    clhu a1, 0(a0)
+; RV64IXCHERI-NEXT:    slli a0, s0, 48
 ; RV64IXCHERI-NEXT:    srai s3, a0, 48
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 14
-; RV64IXCHERI-NEXT:    csetbounds cs0, ca0, 2
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 14
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 2
 ; RV64IXCHERI-NEXT:    j .LBB98_2
 ; RV64IXCHERI-NEXT:  .LBB98_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB98_2 Depth=1
-; RV64IXCHERI-NEXT:    csh a1, 14(csp)
+; RV64IXCHERI-NEXT:    csh a1, 14(sp)
 ; RV64IXCHERI-NEXT:    li a3, 4
 ; RV64IXCHERI-NEXT:    li a4, 2
-; RV64IXCHERI-NEXT:    cmove ca0, cs1
-; RV64IXCHERI-NEXT:    cmove ca1, cs0
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_2
-; RV64IXCHERI-NEXT:    clh a1, 14(csp)
+; RV64IXCHERI-NEXT:    clh a1, 14(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB98_4
 ; RV64IXCHERI-NEXT:  .LBB98_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -6852,28 +6852,28 @@ define i16 @atomicrmw_min_i16_acq_rel(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV64IXCHERI-NEXT:    bge s3, a0, .LBB98_1
 ; RV64IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB98_2 Depth=1
-; RV64IXCHERI-NEXT:    mv a2, s2
+; RV64IXCHERI-NEXT:    mv a2, s0
 ; RV64IXCHERI-NEXT:    j .LBB98_1
 ; RV64IXCHERI-NEXT:  .LBB98_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 80(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs3, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 96
+; RV64IXCHERI-NEXT:    clc ra, 80(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s3, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 96
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_min_i16_acq_rel:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB98_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.h.aq a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.h.aq a2, (a0)
 ; RV64IAXCHERI-NEXT:    mv a3, a2
 ; RV64IAXCHERI-NEXT:    bge a1, a3, .LBB98_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB98_1 Depth=1
 ; RV64IAXCHERI-NEXT:    mv a3, a1
 ; RV64IAXCHERI-NEXT:  .LBB98_3: # in Loop: Header=BB98_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.h.rl a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.h.rl a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB98_1
 ; RV64IAXCHERI-NEXT:  # %bb.4:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -6885,29 +6885,29 @@ define i16 @atomicrmw_min_i16_acq_rel(i16 addrspace(200)* %a, i16 %b) nounwind {
 define i16 @atomicrmw_min_i16_seq_cst(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_min_i16_seq_cst:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs3, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    mv s2, a1
-; RV32IXCHERI-NEXT:    cmove cs1, ca0
-; RV32IXCHERI-NEXT:    clhu a1, 0(ca0)
-; RV32IXCHERI-NEXT:    slli a0, s2, 16
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s3, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    mv s0, a1
+; RV32IXCHERI-NEXT:    cmove s1, a0
+; RV32IXCHERI-NEXT:    clhu a1, 0(a0)
+; RV32IXCHERI-NEXT:    slli a0, s0, 16
 ; RV32IXCHERI-NEXT:    srai s3, a0, 16
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 6
-; RV32IXCHERI-NEXT:    csetbounds cs0, ca0, 2
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 6
+; RV32IXCHERI-NEXT:    csetbounds s2, a0, 2
 ; RV32IXCHERI-NEXT:    j .LBB99_2
 ; RV32IXCHERI-NEXT:  .LBB99_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB99_2 Depth=1
-; RV32IXCHERI-NEXT:    csh a1, 6(csp)
+; RV32IXCHERI-NEXT:    csh a1, 6(sp)
 ; RV32IXCHERI-NEXT:    li a3, 5
 ; RV32IXCHERI-NEXT:    li a4, 5
-; RV32IXCHERI-NEXT:    cmove ca0, cs1
-; RV32IXCHERI-NEXT:    cmove ca1, cs0
+; RV32IXCHERI-NEXT:    cmove a0, s1
+; RV32IXCHERI-NEXT:    cmove a1, s2
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_2
-; RV32IXCHERI-NEXT:    clh a1, 6(csp)
+; RV32IXCHERI-NEXT:    clh a1, 6(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB99_4
 ; RV32IXCHERI-NEXT:  .LBB99_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -6917,28 +6917,28 @@ define i16 @atomicrmw_min_i16_seq_cst(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV32IXCHERI-NEXT:    bge s3, a0, .LBB99_1
 ; RV32IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB99_2 Depth=1
-; RV32IXCHERI-NEXT:    mv a2, s2
+; RV32IXCHERI-NEXT:    mv a2, s0
 ; RV32IXCHERI-NEXT:    j .LBB99_1
 ; RV32IXCHERI-NEXT:  .LBB99_4: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a1
-; RV32IXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs3, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s3, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_min_i16_seq_cst:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB99_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.h.aqrl a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.h.aqrl a2, (a0)
 ; RV32IAXCHERI-NEXT:    mv a3, a2
 ; RV32IAXCHERI-NEXT:    bge a1, a3, .LBB99_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB99_1 Depth=1
 ; RV32IAXCHERI-NEXT:    mv a3, a1
 ; RV32IAXCHERI-NEXT:  .LBB99_3: # in Loop: Header=BB99_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.h.aqrl a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.h.aqrl a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB99_1
 ; RV32IAXCHERI-NEXT:  # %bb.4:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -6946,29 +6946,29 @@ define i16 @atomicrmw_min_i16_seq_cst(i16 addrspace(200)* %a, i16 %b) nounwind {
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_min_i16_seq_cst:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -96
-; RV64IXCHERI-NEXT:    csc cra, 80(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs3, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    mv s2, a1
-; RV64IXCHERI-NEXT:    cmove cs1, ca0
-; RV64IXCHERI-NEXT:    clhu a1, 0(ca0)
-; RV64IXCHERI-NEXT:    slli a0, s2, 48
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -96
+; RV64IXCHERI-NEXT:    csc ra, 80(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s3, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    mv s0, a1
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    clhu a1, 0(a0)
+; RV64IXCHERI-NEXT:    slli a0, s0, 48
 ; RV64IXCHERI-NEXT:    srai s3, a0, 48
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 14
-; RV64IXCHERI-NEXT:    csetbounds cs0, ca0, 2
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 14
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 2
 ; RV64IXCHERI-NEXT:    j .LBB99_2
 ; RV64IXCHERI-NEXT:  .LBB99_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB99_2 Depth=1
-; RV64IXCHERI-NEXT:    csh a1, 14(csp)
+; RV64IXCHERI-NEXT:    csh a1, 14(sp)
 ; RV64IXCHERI-NEXT:    li a3, 5
 ; RV64IXCHERI-NEXT:    li a4, 5
-; RV64IXCHERI-NEXT:    cmove ca0, cs1
-; RV64IXCHERI-NEXT:    cmove ca1, cs0
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_2
-; RV64IXCHERI-NEXT:    clh a1, 14(csp)
+; RV64IXCHERI-NEXT:    clh a1, 14(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB99_4
 ; RV64IXCHERI-NEXT:  .LBB99_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -6978,28 +6978,28 @@ define i16 @atomicrmw_min_i16_seq_cst(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV64IXCHERI-NEXT:    bge s3, a0, .LBB99_1
 ; RV64IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB99_2 Depth=1
-; RV64IXCHERI-NEXT:    mv a2, s2
+; RV64IXCHERI-NEXT:    mv a2, s0
 ; RV64IXCHERI-NEXT:    j .LBB99_1
 ; RV64IXCHERI-NEXT:  .LBB99_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 80(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs3, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 96
+; RV64IXCHERI-NEXT:    clc ra, 80(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s3, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 96
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_min_i16_seq_cst:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB99_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.h.aqrl a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.h.aqrl a2, (a0)
 ; RV64IAXCHERI-NEXT:    mv a3, a2
 ; RV64IAXCHERI-NEXT:    bge a1, a3, .LBB99_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB99_1 Depth=1
 ; RV64IAXCHERI-NEXT:    mv a3, a1
 ; RV64IAXCHERI-NEXT:  .LBB99_3: # in Loop: Header=BB99_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.h.aqrl a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.h.aqrl a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB99_1
 ; RV64IAXCHERI-NEXT:  # %bb.4:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -7011,31 +7011,31 @@ define i16 @atomicrmw_min_i16_seq_cst(i16 addrspace(200)* %a, i16 %b) nounwind {
 define i16 @atomicrmw_umax_i16_monotonic(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_umax_i16_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -64
-; RV32IXCHERI-NEXT:    csc cra, 56(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 48(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs3, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs4, 16(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    mv s2, a1
-; RV32IXCHERI-NEXT:    cmove cs1, ca0
-; RV32IXCHERI-NEXT:    clhu a1, 0(ca0)
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -64
+; RV32IXCHERI-NEXT:    csc ra, 56(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 48(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s3, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s4, 16(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    mv s0, a1
+; RV32IXCHERI-NEXT:    cmove s1, a0
+; RV32IXCHERI-NEXT:    clhu a1, 0(a0)
 ; RV32IXCHERI-NEXT:    lui s3, 16
 ; RV32IXCHERI-NEXT:    addi s3, s3, -1
-; RV32IXCHERI-NEXT:    and s4, s2, s3
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 14
-; RV32IXCHERI-NEXT:    csetbounds cs0, ca0, 2
+; RV32IXCHERI-NEXT:    and s4, s0, s3
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 14
+; RV32IXCHERI-NEXT:    csetbounds s2, a0, 2
 ; RV32IXCHERI-NEXT:    j .LBB100_2
 ; RV32IXCHERI-NEXT:  .LBB100_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB100_2 Depth=1
-; RV32IXCHERI-NEXT:    csh a1, 14(csp)
-; RV32IXCHERI-NEXT:    cmove ca0, cs1
-; RV32IXCHERI-NEXT:    cmove ca1, cs0
+; RV32IXCHERI-NEXT:    csh a1, 14(sp)
+; RV32IXCHERI-NEXT:    cmove a0, s1
+; RV32IXCHERI-NEXT:    cmove a1, s2
 ; RV32IXCHERI-NEXT:    li a3, 0
 ; RV32IXCHERI-NEXT:    li a4, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_2
-; RV32IXCHERI-NEXT:    clh a1, 14(csp)
+; RV32IXCHERI-NEXT:    clh a1, 14(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB100_4
 ; RV32IXCHERI-NEXT:  .LBB100_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -7044,29 +7044,29 @@ define i16 @atomicrmw_umax_i16_monotonic(i16 addrspace(200)* %a, i16 %b) nounwin
 ; RV32IXCHERI-NEXT:    bltu s4, a0, .LBB100_1
 ; RV32IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB100_2 Depth=1
-; RV32IXCHERI-NEXT:    mv a2, s2
+; RV32IXCHERI-NEXT:    mv a2, s0
 ; RV32IXCHERI-NEXT:    j .LBB100_1
 ; RV32IXCHERI-NEXT:  .LBB100_4: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a1
-; RV32IXCHERI-NEXT:    clc cra, 56(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 48(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs3, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs4, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 64
+; RV32IXCHERI-NEXT:    clc ra, 56(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 48(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s3, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s4, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 64
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_umax_i16_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB100_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.h a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.h a2, (a0)
 ; RV32IAXCHERI-NEXT:    mv a3, a2
 ; RV32IAXCHERI-NEXT:    bgeu a3, a1, .LBB100_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB100_1 Depth=1
 ; RV32IAXCHERI-NEXT:    mv a3, a1
 ; RV32IAXCHERI-NEXT:  .LBB100_3: # in Loop: Header=BB100_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.h a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.h a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB100_1
 ; RV32IAXCHERI-NEXT:  # %bb.4:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -7074,31 +7074,31 @@ define i16 @atomicrmw_umax_i16_monotonic(i16 addrspace(200)* %a, i16 %b) nounwin
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_umax_i16_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -112
-; RV64IXCHERI-NEXT:    csc cra, 96(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 80(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs3, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs4, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    mv s2, a1
-; RV64IXCHERI-NEXT:    cmove cs1, ca0
-; RV64IXCHERI-NEXT:    clhu a1, 0(ca0)
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -112
+; RV64IXCHERI-NEXT:    csc ra, 96(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 80(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s3, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s4, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    mv s0, a1
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    clhu a1, 0(a0)
 ; RV64IXCHERI-NEXT:    lui s3, 16
 ; RV64IXCHERI-NEXT:    addi s3, s3, -1
-; RV64IXCHERI-NEXT:    and s4, s2, s3
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 14
-; RV64IXCHERI-NEXT:    csetbounds cs0, ca0, 2
+; RV64IXCHERI-NEXT:    and s4, s0, s3
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 14
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 2
 ; RV64IXCHERI-NEXT:    j .LBB100_2
 ; RV64IXCHERI-NEXT:  .LBB100_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB100_2 Depth=1
-; RV64IXCHERI-NEXT:    csh a1, 14(csp)
-; RV64IXCHERI-NEXT:    cmove ca0, cs1
-; RV64IXCHERI-NEXT:    cmove ca1, cs0
+; RV64IXCHERI-NEXT:    csh a1, 14(sp)
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    li a3, 0
 ; RV64IXCHERI-NEXT:    li a4, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_2
-; RV64IXCHERI-NEXT:    clh a1, 14(csp)
+; RV64IXCHERI-NEXT:    clh a1, 14(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB100_4
 ; RV64IXCHERI-NEXT:  .LBB100_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -7107,29 +7107,29 @@ define i16 @atomicrmw_umax_i16_monotonic(i16 addrspace(200)* %a, i16 %b) nounwin
 ; RV64IXCHERI-NEXT:    bltu s4, a0, .LBB100_1
 ; RV64IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB100_2 Depth=1
-; RV64IXCHERI-NEXT:    mv a2, s2
+; RV64IXCHERI-NEXT:    mv a2, s0
 ; RV64IXCHERI-NEXT:    j .LBB100_1
 ; RV64IXCHERI-NEXT:  .LBB100_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 96(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 80(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs3, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs4, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 112
+; RV64IXCHERI-NEXT:    clc ra, 96(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 80(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s3, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s4, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 112
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_umax_i16_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB100_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.h a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.h a2, (a0)
 ; RV64IAXCHERI-NEXT:    mv a3, a2
 ; RV64IAXCHERI-NEXT:    bgeu a3, a1, .LBB100_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB100_1 Depth=1
 ; RV64IAXCHERI-NEXT:    mv a3, a1
 ; RV64IAXCHERI-NEXT:  .LBB100_3: # in Loop: Header=BB100_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.h a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.h a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB100_1
 ; RV64IAXCHERI-NEXT:  # %bb.4:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -7141,31 +7141,31 @@ define i16 @atomicrmw_umax_i16_monotonic(i16 addrspace(200)* %a, i16 %b) nounwin
 define i16 @atomicrmw_umax_i16_acquire(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_umax_i16_acquire:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -64
-; RV32IXCHERI-NEXT:    csc cra, 56(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 48(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs3, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs4, 16(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    mv s2, a1
-; RV32IXCHERI-NEXT:    cmove cs1, ca0
-; RV32IXCHERI-NEXT:    clhu a1, 0(ca0)
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -64
+; RV32IXCHERI-NEXT:    csc ra, 56(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 48(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s3, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s4, 16(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    mv s0, a1
+; RV32IXCHERI-NEXT:    cmove s1, a0
+; RV32IXCHERI-NEXT:    clhu a1, 0(a0)
 ; RV32IXCHERI-NEXT:    lui s3, 16
 ; RV32IXCHERI-NEXT:    addi s3, s3, -1
-; RV32IXCHERI-NEXT:    and s4, s2, s3
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 14
-; RV32IXCHERI-NEXT:    csetbounds cs0, ca0, 2
+; RV32IXCHERI-NEXT:    and s4, s0, s3
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 14
+; RV32IXCHERI-NEXT:    csetbounds s2, a0, 2
 ; RV32IXCHERI-NEXT:    j .LBB101_2
 ; RV32IXCHERI-NEXT:  .LBB101_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB101_2 Depth=1
-; RV32IXCHERI-NEXT:    csh a1, 14(csp)
+; RV32IXCHERI-NEXT:    csh a1, 14(sp)
 ; RV32IXCHERI-NEXT:    li a3, 2
 ; RV32IXCHERI-NEXT:    li a4, 2
-; RV32IXCHERI-NEXT:    cmove ca0, cs1
-; RV32IXCHERI-NEXT:    cmove ca1, cs0
+; RV32IXCHERI-NEXT:    cmove a0, s1
+; RV32IXCHERI-NEXT:    cmove a1, s2
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_2
-; RV32IXCHERI-NEXT:    clh a1, 14(csp)
+; RV32IXCHERI-NEXT:    clh a1, 14(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB101_4
 ; RV32IXCHERI-NEXT:  .LBB101_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -7174,29 +7174,29 @@ define i16 @atomicrmw_umax_i16_acquire(i16 addrspace(200)* %a, i16 %b) nounwind
 ; RV32IXCHERI-NEXT:    bltu s4, a0, .LBB101_1
 ; RV32IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB101_2 Depth=1
-; RV32IXCHERI-NEXT:    mv a2, s2
+; RV32IXCHERI-NEXT:    mv a2, s0
 ; RV32IXCHERI-NEXT:    j .LBB101_1
 ; RV32IXCHERI-NEXT:  .LBB101_4: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a1
-; RV32IXCHERI-NEXT:    clc cra, 56(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 48(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs3, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs4, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 64
+; RV32IXCHERI-NEXT:    clc ra, 56(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 48(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s3, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s4, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 64
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_umax_i16_acquire:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB101_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.h.aq a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.h.aq a2, (a0)
 ; RV32IAXCHERI-NEXT:    mv a3, a2
 ; RV32IAXCHERI-NEXT:    bgeu a3, a1, .LBB101_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB101_1 Depth=1
 ; RV32IAXCHERI-NEXT:    mv a3, a1
 ; RV32IAXCHERI-NEXT:  .LBB101_3: # in Loop: Header=BB101_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.h a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.h a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB101_1
 ; RV32IAXCHERI-NEXT:  # %bb.4:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -7204,31 +7204,31 @@ define i16 @atomicrmw_umax_i16_acquire(i16 addrspace(200)* %a, i16 %b) nounwind
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_umax_i16_acquire:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -112
-; RV64IXCHERI-NEXT:    csc cra, 96(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 80(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs3, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs4, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    mv s2, a1
-; RV64IXCHERI-NEXT:    cmove cs1, ca0
-; RV64IXCHERI-NEXT:    clhu a1, 0(ca0)
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -112
+; RV64IXCHERI-NEXT:    csc ra, 96(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 80(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s3, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s4, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    mv s0, a1
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    clhu a1, 0(a0)
 ; RV64IXCHERI-NEXT:    lui s3, 16
 ; RV64IXCHERI-NEXT:    addi s3, s3, -1
-; RV64IXCHERI-NEXT:    and s4, s2, s3
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 14
-; RV64IXCHERI-NEXT:    csetbounds cs0, ca0, 2
+; RV64IXCHERI-NEXT:    and s4, s0, s3
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 14
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 2
 ; RV64IXCHERI-NEXT:    j .LBB101_2
 ; RV64IXCHERI-NEXT:  .LBB101_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB101_2 Depth=1
-; RV64IXCHERI-NEXT:    csh a1, 14(csp)
+; RV64IXCHERI-NEXT:    csh a1, 14(sp)
 ; RV64IXCHERI-NEXT:    li a3, 2
 ; RV64IXCHERI-NEXT:    li a4, 2
-; RV64IXCHERI-NEXT:    cmove ca0, cs1
-; RV64IXCHERI-NEXT:    cmove ca1, cs0
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_2
-; RV64IXCHERI-NEXT:    clh a1, 14(csp)
+; RV64IXCHERI-NEXT:    clh a1, 14(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB101_4
 ; RV64IXCHERI-NEXT:  .LBB101_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -7237,29 +7237,29 @@ define i16 @atomicrmw_umax_i16_acquire(i16 addrspace(200)* %a, i16 %b) nounwind
 ; RV64IXCHERI-NEXT:    bltu s4, a0, .LBB101_1
 ; RV64IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB101_2 Depth=1
-; RV64IXCHERI-NEXT:    mv a2, s2
+; RV64IXCHERI-NEXT:    mv a2, s0
 ; RV64IXCHERI-NEXT:    j .LBB101_1
 ; RV64IXCHERI-NEXT:  .LBB101_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 96(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 80(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs3, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs4, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 112
+; RV64IXCHERI-NEXT:    clc ra, 96(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 80(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s3, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s4, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 112
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_umax_i16_acquire:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB101_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.h.aq a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.h.aq a2, (a0)
 ; RV64IAXCHERI-NEXT:    mv a3, a2
 ; RV64IAXCHERI-NEXT:    bgeu a3, a1, .LBB101_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB101_1 Depth=1
 ; RV64IAXCHERI-NEXT:    mv a3, a1
 ; RV64IAXCHERI-NEXT:  .LBB101_3: # in Loop: Header=BB101_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.h a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.h a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB101_1
 ; RV64IAXCHERI-NEXT:  # %bb.4:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -7271,31 +7271,31 @@ define i16 @atomicrmw_umax_i16_acquire(i16 addrspace(200)* %a, i16 %b) nounwind
 define i16 @atomicrmw_umax_i16_release(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_umax_i16_release:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -64
-; RV32IXCHERI-NEXT:    csc cra, 56(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 48(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs3, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs4, 16(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    mv s2, a1
-; RV32IXCHERI-NEXT:    cmove cs1, ca0
-; RV32IXCHERI-NEXT:    clhu a1, 0(ca0)
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -64
+; RV32IXCHERI-NEXT:    csc ra, 56(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 48(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s3, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s4, 16(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    mv s0, a1
+; RV32IXCHERI-NEXT:    cmove s1, a0
+; RV32IXCHERI-NEXT:    clhu a1, 0(a0)
 ; RV32IXCHERI-NEXT:    lui s3, 16
 ; RV32IXCHERI-NEXT:    addi s3, s3, -1
-; RV32IXCHERI-NEXT:    and s4, s2, s3
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 14
-; RV32IXCHERI-NEXT:    csetbounds cs0, ca0, 2
+; RV32IXCHERI-NEXT:    and s4, s0, s3
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 14
+; RV32IXCHERI-NEXT:    csetbounds s2, a0, 2
 ; RV32IXCHERI-NEXT:    j .LBB102_2
 ; RV32IXCHERI-NEXT:  .LBB102_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB102_2 Depth=1
-; RV32IXCHERI-NEXT:    csh a1, 14(csp)
+; RV32IXCHERI-NEXT:    csh a1, 14(sp)
 ; RV32IXCHERI-NEXT:    li a3, 3
-; RV32IXCHERI-NEXT:    cmove ca0, cs1
-; RV32IXCHERI-NEXT:    cmove ca1, cs0
+; RV32IXCHERI-NEXT:    cmove a0, s1
+; RV32IXCHERI-NEXT:    cmove a1, s2
 ; RV32IXCHERI-NEXT:    li a4, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_2
-; RV32IXCHERI-NEXT:    clh a1, 14(csp)
+; RV32IXCHERI-NEXT:    clh a1, 14(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB102_4
 ; RV32IXCHERI-NEXT:  .LBB102_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -7304,29 +7304,29 @@ define i16 @atomicrmw_umax_i16_release(i16 addrspace(200)* %a, i16 %b) nounwind
 ; RV32IXCHERI-NEXT:    bltu s4, a0, .LBB102_1
 ; RV32IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB102_2 Depth=1
-; RV32IXCHERI-NEXT:    mv a2, s2
+; RV32IXCHERI-NEXT:    mv a2, s0
 ; RV32IXCHERI-NEXT:    j .LBB102_1
 ; RV32IXCHERI-NEXT:  .LBB102_4: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a1
-; RV32IXCHERI-NEXT:    clc cra, 56(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 48(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs3, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs4, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 64
+; RV32IXCHERI-NEXT:    clc ra, 56(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 48(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s3, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s4, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 64
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_umax_i16_release:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB102_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.h a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.h a2, (a0)
 ; RV32IAXCHERI-NEXT:    mv a3, a2
 ; RV32IAXCHERI-NEXT:    bgeu a3, a1, .LBB102_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB102_1 Depth=1
 ; RV32IAXCHERI-NEXT:    mv a3, a1
 ; RV32IAXCHERI-NEXT:  .LBB102_3: # in Loop: Header=BB102_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.h.rl a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.h.rl a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB102_1
 ; RV32IAXCHERI-NEXT:  # %bb.4:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -7334,31 +7334,31 @@ define i16 @atomicrmw_umax_i16_release(i16 addrspace(200)* %a, i16 %b) nounwind
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_umax_i16_release:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -112
-; RV64IXCHERI-NEXT:    csc cra, 96(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 80(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs3, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs4, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    mv s2, a1
-; RV64IXCHERI-NEXT:    cmove cs1, ca0
-; RV64IXCHERI-NEXT:    clhu a1, 0(ca0)
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -112
+; RV64IXCHERI-NEXT:    csc ra, 96(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 80(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s3, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s4, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    mv s0, a1
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    clhu a1, 0(a0)
 ; RV64IXCHERI-NEXT:    lui s3, 16
 ; RV64IXCHERI-NEXT:    addi s3, s3, -1
-; RV64IXCHERI-NEXT:    and s4, s2, s3
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 14
-; RV64IXCHERI-NEXT:    csetbounds cs0, ca0, 2
+; RV64IXCHERI-NEXT:    and s4, s0, s3
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 14
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 2
 ; RV64IXCHERI-NEXT:    j .LBB102_2
 ; RV64IXCHERI-NEXT:  .LBB102_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB102_2 Depth=1
-; RV64IXCHERI-NEXT:    csh a1, 14(csp)
+; RV64IXCHERI-NEXT:    csh a1, 14(sp)
 ; RV64IXCHERI-NEXT:    li a3, 3
-; RV64IXCHERI-NEXT:    cmove ca0, cs1
-; RV64IXCHERI-NEXT:    cmove ca1, cs0
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    li a4, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_2
-; RV64IXCHERI-NEXT:    clh a1, 14(csp)
+; RV64IXCHERI-NEXT:    clh a1, 14(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB102_4
 ; RV64IXCHERI-NEXT:  .LBB102_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -7367,29 +7367,29 @@ define i16 @atomicrmw_umax_i16_release(i16 addrspace(200)* %a, i16 %b) nounwind
 ; RV64IXCHERI-NEXT:    bltu s4, a0, .LBB102_1
 ; RV64IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB102_2 Depth=1
-; RV64IXCHERI-NEXT:    mv a2, s2
+; RV64IXCHERI-NEXT:    mv a2, s0
 ; RV64IXCHERI-NEXT:    j .LBB102_1
 ; RV64IXCHERI-NEXT:  .LBB102_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 96(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 80(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs3, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs4, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 112
+; RV64IXCHERI-NEXT:    clc ra, 96(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 80(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s3, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s4, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 112
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_umax_i16_release:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB102_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.h a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.h a2, (a0)
 ; RV64IAXCHERI-NEXT:    mv a3, a2
 ; RV64IAXCHERI-NEXT:    bgeu a3, a1, .LBB102_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB102_1 Depth=1
 ; RV64IAXCHERI-NEXT:    mv a3, a1
 ; RV64IAXCHERI-NEXT:  .LBB102_3: # in Loop: Header=BB102_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.h.rl a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.h.rl a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB102_1
 ; RV64IAXCHERI-NEXT:  # %bb.4:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -7401,31 +7401,31 @@ define i16 @atomicrmw_umax_i16_release(i16 addrspace(200)* %a, i16 %b) nounwind
 define i16 @atomicrmw_umax_i16_acq_rel(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_umax_i16_acq_rel:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -64
-; RV32IXCHERI-NEXT:    csc cra, 56(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 48(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs3, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs4, 16(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    mv s2, a1
-; RV32IXCHERI-NEXT:    cmove cs1, ca0
-; RV32IXCHERI-NEXT:    clhu a1, 0(ca0)
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -64
+; RV32IXCHERI-NEXT:    csc ra, 56(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 48(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s3, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s4, 16(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    mv s0, a1
+; RV32IXCHERI-NEXT:    cmove s1, a0
+; RV32IXCHERI-NEXT:    clhu a1, 0(a0)
 ; RV32IXCHERI-NEXT:    lui s3, 16
 ; RV32IXCHERI-NEXT:    addi s3, s3, -1
-; RV32IXCHERI-NEXT:    and s4, s2, s3
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 14
-; RV32IXCHERI-NEXT:    csetbounds cs0, ca0, 2
+; RV32IXCHERI-NEXT:    and s4, s0, s3
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 14
+; RV32IXCHERI-NEXT:    csetbounds s2, a0, 2
 ; RV32IXCHERI-NEXT:    j .LBB103_2
 ; RV32IXCHERI-NEXT:  .LBB103_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB103_2 Depth=1
-; RV32IXCHERI-NEXT:    csh a1, 14(csp)
+; RV32IXCHERI-NEXT:    csh a1, 14(sp)
 ; RV32IXCHERI-NEXT:    li a3, 4
 ; RV32IXCHERI-NEXT:    li a4, 2
-; RV32IXCHERI-NEXT:    cmove ca0, cs1
-; RV32IXCHERI-NEXT:    cmove ca1, cs0
+; RV32IXCHERI-NEXT:    cmove a0, s1
+; RV32IXCHERI-NEXT:    cmove a1, s2
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_2
-; RV32IXCHERI-NEXT:    clh a1, 14(csp)
+; RV32IXCHERI-NEXT:    clh a1, 14(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB103_4
 ; RV32IXCHERI-NEXT:  .LBB103_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -7434,29 +7434,29 @@ define i16 @atomicrmw_umax_i16_acq_rel(i16 addrspace(200)* %a, i16 %b) nounwind
 ; RV32IXCHERI-NEXT:    bltu s4, a0, .LBB103_1
 ; RV32IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB103_2 Depth=1
-; RV32IXCHERI-NEXT:    mv a2, s2
+; RV32IXCHERI-NEXT:    mv a2, s0
 ; RV32IXCHERI-NEXT:    j .LBB103_1
 ; RV32IXCHERI-NEXT:  .LBB103_4: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a1
-; RV32IXCHERI-NEXT:    clc cra, 56(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 48(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs3, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs4, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 64
+; RV32IXCHERI-NEXT:    clc ra, 56(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 48(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s3, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s4, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 64
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_umax_i16_acq_rel:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB103_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.h.aq a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.h.aq a2, (a0)
 ; RV32IAXCHERI-NEXT:    mv a3, a2
 ; RV32IAXCHERI-NEXT:    bgeu a3, a1, .LBB103_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB103_1 Depth=1
 ; RV32IAXCHERI-NEXT:    mv a3, a1
 ; RV32IAXCHERI-NEXT:  .LBB103_3: # in Loop: Header=BB103_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.h.rl a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.h.rl a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB103_1
 ; RV32IAXCHERI-NEXT:  # %bb.4:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -7464,31 +7464,31 @@ define i16 @atomicrmw_umax_i16_acq_rel(i16 addrspace(200)* %a, i16 %b) nounwind
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_umax_i16_acq_rel:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -112
-; RV64IXCHERI-NEXT:    csc cra, 96(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 80(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs3, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs4, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    mv s2, a1
-; RV64IXCHERI-NEXT:    cmove cs1, ca0
-; RV64IXCHERI-NEXT:    clhu a1, 0(ca0)
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -112
+; RV64IXCHERI-NEXT:    csc ra, 96(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 80(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s3, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s4, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    mv s0, a1
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    clhu a1, 0(a0)
 ; RV64IXCHERI-NEXT:    lui s3, 16
 ; RV64IXCHERI-NEXT:    addi s3, s3, -1
-; RV64IXCHERI-NEXT:    and s4, s2, s3
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 14
-; RV64IXCHERI-NEXT:    csetbounds cs0, ca0, 2
+; RV64IXCHERI-NEXT:    and s4, s0, s3
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 14
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 2
 ; RV64IXCHERI-NEXT:    j .LBB103_2
 ; RV64IXCHERI-NEXT:  .LBB103_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB103_2 Depth=1
-; RV64IXCHERI-NEXT:    csh a1, 14(csp)
+; RV64IXCHERI-NEXT:    csh a1, 14(sp)
 ; RV64IXCHERI-NEXT:    li a3, 4
 ; RV64IXCHERI-NEXT:    li a4, 2
-; RV64IXCHERI-NEXT:    cmove ca0, cs1
-; RV64IXCHERI-NEXT:    cmove ca1, cs0
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_2
-; RV64IXCHERI-NEXT:    clh a1, 14(csp)
+; RV64IXCHERI-NEXT:    clh a1, 14(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB103_4
 ; RV64IXCHERI-NEXT:  .LBB103_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -7497,29 +7497,29 @@ define i16 @atomicrmw_umax_i16_acq_rel(i16 addrspace(200)* %a, i16 %b) nounwind
 ; RV64IXCHERI-NEXT:    bltu s4, a0, .LBB103_1
 ; RV64IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB103_2 Depth=1
-; RV64IXCHERI-NEXT:    mv a2, s2
+; RV64IXCHERI-NEXT:    mv a2, s0
 ; RV64IXCHERI-NEXT:    j .LBB103_1
 ; RV64IXCHERI-NEXT:  .LBB103_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 96(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 80(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs3, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs4, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 112
+; RV64IXCHERI-NEXT:    clc ra, 96(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 80(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s3, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s4, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 112
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_umax_i16_acq_rel:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB103_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.h.aq a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.h.aq a2, (a0)
 ; RV64IAXCHERI-NEXT:    mv a3, a2
 ; RV64IAXCHERI-NEXT:    bgeu a3, a1, .LBB103_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB103_1 Depth=1
 ; RV64IAXCHERI-NEXT:    mv a3, a1
 ; RV64IAXCHERI-NEXT:  .LBB103_3: # in Loop: Header=BB103_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.h.rl a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.h.rl a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB103_1
 ; RV64IAXCHERI-NEXT:  # %bb.4:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -7531,31 +7531,31 @@ define i16 @atomicrmw_umax_i16_acq_rel(i16 addrspace(200)* %a, i16 %b) nounwind
 define i16 @atomicrmw_umax_i16_seq_cst(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_umax_i16_seq_cst:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -64
-; RV32IXCHERI-NEXT:    csc cra, 56(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 48(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs3, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs4, 16(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    mv s2, a1
-; RV32IXCHERI-NEXT:    cmove cs1, ca0
-; RV32IXCHERI-NEXT:    clhu a1, 0(ca0)
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -64
+; RV32IXCHERI-NEXT:    csc ra, 56(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 48(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s3, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s4, 16(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    mv s0, a1
+; RV32IXCHERI-NEXT:    cmove s1, a0
+; RV32IXCHERI-NEXT:    clhu a1, 0(a0)
 ; RV32IXCHERI-NEXT:    lui s3, 16
 ; RV32IXCHERI-NEXT:    addi s3, s3, -1
-; RV32IXCHERI-NEXT:    and s4, s2, s3
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 14
-; RV32IXCHERI-NEXT:    csetbounds cs0, ca0, 2
+; RV32IXCHERI-NEXT:    and s4, s0, s3
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 14
+; RV32IXCHERI-NEXT:    csetbounds s2, a0, 2
 ; RV32IXCHERI-NEXT:    j .LBB104_2
 ; RV32IXCHERI-NEXT:  .LBB104_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB104_2 Depth=1
-; RV32IXCHERI-NEXT:    csh a1, 14(csp)
+; RV32IXCHERI-NEXT:    csh a1, 14(sp)
 ; RV32IXCHERI-NEXT:    li a3, 5
 ; RV32IXCHERI-NEXT:    li a4, 5
-; RV32IXCHERI-NEXT:    cmove ca0, cs1
-; RV32IXCHERI-NEXT:    cmove ca1, cs0
+; RV32IXCHERI-NEXT:    cmove a0, s1
+; RV32IXCHERI-NEXT:    cmove a1, s2
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_2
-; RV32IXCHERI-NEXT:    clh a1, 14(csp)
+; RV32IXCHERI-NEXT:    clh a1, 14(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB104_4
 ; RV32IXCHERI-NEXT:  .LBB104_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -7564,29 +7564,29 @@ define i16 @atomicrmw_umax_i16_seq_cst(i16 addrspace(200)* %a, i16 %b) nounwind
 ; RV32IXCHERI-NEXT:    bltu s4, a0, .LBB104_1
 ; RV32IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB104_2 Depth=1
-; RV32IXCHERI-NEXT:    mv a2, s2
+; RV32IXCHERI-NEXT:    mv a2, s0
 ; RV32IXCHERI-NEXT:    j .LBB104_1
 ; RV32IXCHERI-NEXT:  .LBB104_4: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a1
-; RV32IXCHERI-NEXT:    clc cra, 56(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 48(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs3, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs4, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 64
+; RV32IXCHERI-NEXT:    clc ra, 56(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 48(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s3, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s4, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 64
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_umax_i16_seq_cst:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB104_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.h.aqrl a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.h.aqrl a2, (a0)
 ; RV32IAXCHERI-NEXT:    mv a3, a2
 ; RV32IAXCHERI-NEXT:    bgeu a3, a1, .LBB104_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB104_1 Depth=1
 ; RV32IAXCHERI-NEXT:    mv a3, a1
 ; RV32IAXCHERI-NEXT:  .LBB104_3: # in Loop: Header=BB104_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.h.aqrl a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.h.aqrl a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB104_1
 ; RV32IAXCHERI-NEXT:  # %bb.4:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -7594,31 +7594,31 @@ define i16 @atomicrmw_umax_i16_seq_cst(i16 addrspace(200)* %a, i16 %b) nounwind
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_umax_i16_seq_cst:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -112
-; RV64IXCHERI-NEXT:    csc cra, 96(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 80(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs3, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs4, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    mv s2, a1
-; RV64IXCHERI-NEXT:    cmove cs1, ca0
-; RV64IXCHERI-NEXT:    clhu a1, 0(ca0)
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -112
+; RV64IXCHERI-NEXT:    csc ra, 96(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 80(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s3, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s4, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    mv s0, a1
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    clhu a1, 0(a0)
 ; RV64IXCHERI-NEXT:    lui s3, 16
 ; RV64IXCHERI-NEXT:    addi s3, s3, -1
-; RV64IXCHERI-NEXT:    and s4, s2, s3
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 14
-; RV64IXCHERI-NEXT:    csetbounds cs0, ca0, 2
+; RV64IXCHERI-NEXT:    and s4, s0, s3
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 14
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 2
 ; RV64IXCHERI-NEXT:    j .LBB104_2
 ; RV64IXCHERI-NEXT:  .LBB104_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB104_2 Depth=1
-; RV64IXCHERI-NEXT:    csh a1, 14(csp)
+; RV64IXCHERI-NEXT:    csh a1, 14(sp)
 ; RV64IXCHERI-NEXT:    li a3, 5
 ; RV64IXCHERI-NEXT:    li a4, 5
-; RV64IXCHERI-NEXT:    cmove ca0, cs1
-; RV64IXCHERI-NEXT:    cmove ca1, cs0
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_2
-; RV64IXCHERI-NEXT:    clh a1, 14(csp)
+; RV64IXCHERI-NEXT:    clh a1, 14(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB104_4
 ; RV64IXCHERI-NEXT:  .LBB104_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -7627,29 +7627,29 @@ define i16 @atomicrmw_umax_i16_seq_cst(i16 addrspace(200)* %a, i16 %b) nounwind
 ; RV64IXCHERI-NEXT:    bltu s4, a0, .LBB104_1
 ; RV64IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB104_2 Depth=1
-; RV64IXCHERI-NEXT:    mv a2, s2
+; RV64IXCHERI-NEXT:    mv a2, s0
 ; RV64IXCHERI-NEXT:    j .LBB104_1
 ; RV64IXCHERI-NEXT:  .LBB104_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 96(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 80(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs3, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs4, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 112
+; RV64IXCHERI-NEXT:    clc ra, 96(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 80(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s3, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s4, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 112
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_umax_i16_seq_cst:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB104_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.h.aqrl a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.h.aqrl a2, (a0)
 ; RV64IAXCHERI-NEXT:    mv a3, a2
 ; RV64IAXCHERI-NEXT:    bgeu a3, a1, .LBB104_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB104_1 Depth=1
 ; RV64IAXCHERI-NEXT:    mv a3, a1
 ; RV64IAXCHERI-NEXT:  .LBB104_3: # in Loop: Header=BB104_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.h.aqrl a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.h.aqrl a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB104_1
 ; RV64IAXCHERI-NEXT:  # %bb.4:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -7661,31 +7661,31 @@ define i16 @atomicrmw_umax_i16_seq_cst(i16 addrspace(200)* %a, i16 %b) nounwind
 define i16 @atomicrmw_umin_i16_monotonic(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_umin_i16_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -64
-; RV32IXCHERI-NEXT:    csc cra, 56(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 48(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs3, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs4, 16(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    mv s2, a1
-; RV32IXCHERI-NEXT:    cmove cs1, ca0
-; RV32IXCHERI-NEXT:    clhu a1, 0(ca0)
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -64
+; RV32IXCHERI-NEXT:    csc ra, 56(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 48(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s3, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s4, 16(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    mv s0, a1
+; RV32IXCHERI-NEXT:    cmove s1, a0
+; RV32IXCHERI-NEXT:    clhu a1, 0(a0)
 ; RV32IXCHERI-NEXT:    lui s3, 16
 ; RV32IXCHERI-NEXT:    addi s3, s3, -1
-; RV32IXCHERI-NEXT:    and s4, s2, s3
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 14
-; RV32IXCHERI-NEXT:    csetbounds cs0, ca0, 2
+; RV32IXCHERI-NEXT:    and s4, s0, s3
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 14
+; RV32IXCHERI-NEXT:    csetbounds s2, a0, 2
 ; RV32IXCHERI-NEXT:    j .LBB105_2
 ; RV32IXCHERI-NEXT:  .LBB105_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB105_2 Depth=1
-; RV32IXCHERI-NEXT:    csh a1, 14(csp)
-; RV32IXCHERI-NEXT:    cmove ca0, cs1
-; RV32IXCHERI-NEXT:    cmove ca1, cs0
+; RV32IXCHERI-NEXT:    csh a1, 14(sp)
+; RV32IXCHERI-NEXT:    cmove a0, s1
+; RV32IXCHERI-NEXT:    cmove a1, s2
 ; RV32IXCHERI-NEXT:    li a3, 0
 ; RV32IXCHERI-NEXT:    li a4, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_2
-; RV32IXCHERI-NEXT:    clh a1, 14(csp)
+; RV32IXCHERI-NEXT:    clh a1, 14(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB105_4
 ; RV32IXCHERI-NEXT:  .LBB105_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -7694,29 +7694,29 @@ define i16 @atomicrmw_umin_i16_monotonic(i16 addrspace(200)* %a, i16 %b) nounwin
 ; RV32IXCHERI-NEXT:    bgeu s4, a0, .LBB105_1
 ; RV32IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB105_2 Depth=1
-; RV32IXCHERI-NEXT:    mv a2, s2
+; RV32IXCHERI-NEXT:    mv a2, s0
 ; RV32IXCHERI-NEXT:    j .LBB105_1
 ; RV32IXCHERI-NEXT:  .LBB105_4: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a1
-; RV32IXCHERI-NEXT:    clc cra, 56(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 48(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs3, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs4, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 64
+; RV32IXCHERI-NEXT:    clc ra, 56(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 48(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s3, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s4, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 64
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_umin_i16_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB105_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.h a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.h a2, (a0)
 ; RV32IAXCHERI-NEXT:    mv a3, a2
 ; RV32IAXCHERI-NEXT:    bgeu a1, a3, .LBB105_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB105_1 Depth=1
 ; RV32IAXCHERI-NEXT:    mv a3, a1
 ; RV32IAXCHERI-NEXT:  .LBB105_3: # in Loop: Header=BB105_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.h a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.h a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB105_1
 ; RV32IAXCHERI-NEXT:  # %bb.4:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -7724,31 +7724,31 @@ define i16 @atomicrmw_umin_i16_monotonic(i16 addrspace(200)* %a, i16 %b) nounwin
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_umin_i16_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -112
-; RV64IXCHERI-NEXT:    csc cra, 96(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 80(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs3, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs4, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    mv s2, a1
-; RV64IXCHERI-NEXT:    cmove cs1, ca0
-; RV64IXCHERI-NEXT:    clhu a1, 0(ca0)
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -112
+; RV64IXCHERI-NEXT:    csc ra, 96(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 80(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s3, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s4, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    mv s0, a1
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    clhu a1, 0(a0)
 ; RV64IXCHERI-NEXT:    lui s3, 16
 ; RV64IXCHERI-NEXT:    addi s3, s3, -1
-; RV64IXCHERI-NEXT:    and s4, s2, s3
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 14
-; RV64IXCHERI-NEXT:    csetbounds cs0, ca0, 2
+; RV64IXCHERI-NEXT:    and s4, s0, s3
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 14
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 2
 ; RV64IXCHERI-NEXT:    j .LBB105_2
 ; RV64IXCHERI-NEXT:  .LBB105_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB105_2 Depth=1
-; RV64IXCHERI-NEXT:    csh a1, 14(csp)
-; RV64IXCHERI-NEXT:    cmove ca0, cs1
-; RV64IXCHERI-NEXT:    cmove ca1, cs0
+; RV64IXCHERI-NEXT:    csh a1, 14(sp)
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    li a3, 0
 ; RV64IXCHERI-NEXT:    li a4, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_2
-; RV64IXCHERI-NEXT:    clh a1, 14(csp)
+; RV64IXCHERI-NEXT:    clh a1, 14(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB105_4
 ; RV64IXCHERI-NEXT:  .LBB105_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -7757,29 +7757,29 @@ define i16 @atomicrmw_umin_i16_monotonic(i16 addrspace(200)* %a, i16 %b) nounwin
 ; RV64IXCHERI-NEXT:    bgeu s4, a0, .LBB105_1
 ; RV64IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB105_2 Depth=1
-; RV64IXCHERI-NEXT:    mv a2, s2
+; RV64IXCHERI-NEXT:    mv a2, s0
 ; RV64IXCHERI-NEXT:    j .LBB105_1
 ; RV64IXCHERI-NEXT:  .LBB105_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 96(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 80(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs3, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs4, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 112
+; RV64IXCHERI-NEXT:    clc ra, 96(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 80(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s3, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s4, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 112
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_umin_i16_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB105_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.h a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.h a2, (a0)
 ; RV64IAXCHERI-NEXT:    mv a3, a2
 ; RV64IAXCHERI-NEXT:    bgeu a1, a3, .LBB105_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB105_1 Depth=1
 ; RV64IAXCHERI-NEXT:    mv a3, a1
 ; RV64IAXCHERI-NEXT:  .LBB105_3: # in Loop: Header=BB105_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.h a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.h a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB105_1
 ; RV64IAXCHERI-NEXT:  # %bb.4:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -7791,31 +7791,31 @@ define i16 @atomicrmw_umin_i16_monotonic(i16 addrspace(200)* %a, i16 %b) nounwin
 define i16 @atomicrmw_umin_i16_acquire(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_umin_i16_acquire:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -64
-; RV32IXCHERI-NEXT:    csc cra, 56(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 48(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs3, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs4, 16(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    mv s2, a1
-; RV32IXCHERI-NEXT:    cmove cs1, ca0
-; RV32IXCHERI-NEXT:    clhu a1, 0(ca0)
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -64
+; RV32IXCHERI-NEXT:    csc ra, 56(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 48(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s3, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s4, 16(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    mv s0, a1
+; RV32IXCHERI-NEXT:    cmove s1, a0
+; RV32IXCHERI-NEXT:    clhu a1, 0(a0)
 ; RV32IXCHERI-NEXT:    lui s3, 16
 ; RV32IXCHERI-NEXT:    addi s3, s3, -1
-; RV32IXCHERI-NEXT:    and s4, s2, s3
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 14
-; RV32IXCHERI-NEXT:    csetbounds cs0, ca0, 2
+; RV32IXCHERI-NEXT:    and s4, s0, s3
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 14
+; RV32IXCHERI-NEXT:    csetbounds s2, a0, 2
 ; RV32IXCHERI-NEXT:    j .LBB106_2
 ; RV32IXCHERI-NEXT:  .LBB106_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB106_2 Depth=1
-; RV32IXCHERI-NEXT:    csh a1, 14(csp)
+; RV32IXCHERI-NEXT:    csh a1, 14(sp)
 ; RV32IXCHERI-NEXT:    li a3, 2
 ; RV32IXCHERI-NEXT:    li a4, 2
-; RV32IXCHERI-NEXT:    cmove ca0, cs1
-; RV32IXCHERI-NEXT:    cmove ca1, cs0
+; RV32IXCHERI-NEXT:    cmove a0, s1
+; RV32IXCHERI-NEXT:    cmove a1, s2
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_2
-; RV32IXCHERI-NEXT:    clh a1, 14(csp)
+; RV32IXCHERI-NEXT:    clh a1, 14(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB106_4
 ; RV32IXCHERI-NEXT:  .LBB106_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -7824,29 +7824,29 @@ define i16 @atomicrmw_umin_i16_acquire(i16 addrspace(200)* %a, i16 %b) nounwind
 ; RV32IXCHERI-NEXT:    bgeu s4, a0, .LBB106_1
 ; RV32IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB106_2 Depth=1
-; RV32IXCHERI-NEXT:    mv a2, s2
+; RV32IXCHERI-NEXT:    mv a2, s0
 ; RV32IXCHERI-NEXT:    j .LBB106_1
 ; RV32IXCHERI-NEXT:  .LBB106_4: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a1
-; RV32IXCHERI-NEXT:    clc cra, 56(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 48(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs3, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs4, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 64
+; RV32IXCHERI-NEXT:    clc ra, 56(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 48(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s3, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s4, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 64
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_umin_i16_acquire:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB106_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.h.aq a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.h.aq a2, (a0)
 ; RV32IAXCHERI-NEXT:    mv a3, a2
 ; RV32IAXCHERI-NEXT:    bgeu a1, a3, .LBB106_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB106_1 Depth=1
 ; RV32IAXCHERI-NEXT:    mv a3, a1
 ; RV32IAXCHERI-NEXT:  .LBB106_3: # in Loop: Header=BB106_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.h a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.h a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB106_1
 ; RV32IAXCHERI-NEXT:  # %bb.4:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -7854,31 +7854,31 @@ define i16 @atomicrmw_umin_i16_acquire(i16 addrspace(200)* %a, i16 %b) nounwind
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_umin_i16_acquire:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -112
-; RV64IXCHERI-NEXT:    csc cra, 96(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 80(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs3, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs4, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    mv s2, a1
-; RV64IXCHERI-NEXT:    cmove cs1, ca0
-; RV64IXCHERI-NEXT:    clhu a1, 0(ca0)
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -112
+; RV64IXCHERI-NEXT:    csc ra, 96(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 80(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s3, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s4, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    mv s0, a1
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    clhu a1, 0(a0)
 ; RV64IXCHERI-NEXT:    lui s3, 16
 ; RV64IXCHERI-NEXT:    addi s3, s3, -1
-; RV64IXCHERI-NEXT:    and s4, s2, s3
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 14
-; RV64IXCHERI-NEXT:    csetbounds cs0, ca0, 2
+; RV64IXCHERI-NEXT:    and s4, s0, s3
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 14
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 2
 ; RV64IXCHERI-NEXT:    j .LBB106_2
 ; RV64IXCHERI-NEXT:  .LBB106_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB106_2 Depth=1
-; RV64IXCHERI-NEXT:    csh a1, 14(csp)
+; RV64IXCHERI-NEXT:    csh a1, 14(sp)
 ; RV64IXCHERI-NEXT:    li a3, 2
 ; RV64IXCHERI-NEXT:    li a4, 2
-; RV64IXCHERI-NEXT:    cmove ca0, cs1
-; RV64IXCHERI-NEXT:    cmove ca1, cs0
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_2
-; RV64IXCHERI-NEXT:    clh a1, 14(csp)
+; RV64IXCHERI-NEXT:    clh a1, 14(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB106_4
 ; RV64IXCHERI-NEXT:  .LBB106_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -7887,29 +7887,29 @@ define i16 @atomicrmw_umin_i16_acquire(i16 addrspace(200)* %a, i16 %b) nounwind
 ; RV64IXCHERI-NEXT:    bgeu s4, a0, .LBB106_1
 ; RV64IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB106_2 Depth=1
-; RV64IXCHERI-NEXT:    mv a2, s2
+; RV64IXCHERI-NEXT:    mv a2, s0
 ; RV64IXCHERI-NEXT:    j .LBB106_1
 ; RV64IXCHERI-NEXT:  .LBB106_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 96(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 80(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs3, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs4, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 112
+; RV64IXCHERI-NEXT:    clc ra, 96(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 80(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s3, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s4, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 112
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_umin_i16_acquire:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB106_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.h.aq a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.h.aq a2, (a0)
 ; RV64IAXCHERI-NEXT:    mv a3, a2
 ; RV64IAXCHERI-NEXT:    bgeu a1, a3, .LBB106_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB106_1 Depth=1
 ; RV64IAXCHERI-NEXT:    mv a3, a1
 ; RV64IAXCHERI-NEXT:  .LBB106_3: # in Loop: Header=BB106_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.h a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.h a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB106_1
 ; RV64IAXCHERI-NEXT:  # %bb.4:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -7921,31 +7921,31 @@ define i16 @atomicrmw_umin_i16_acquire(i16 addrspace(200)* %a, i16 %b) nounwind
 define i16 @atomicrmw_umin_i16_release(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_umin_i16_release:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -64
-; RV32IXCHERI-NEXT:    csc cra, 56(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 48(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs3, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs4, 16(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    mv s2, a1
-; RV32IXCHERI-NEXT:    cmove cs1, ca0
-; RV32IXCHERI-NEXT:    clhu a1, 0(ca0)
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -64
+; RV32IXCHERI-NEXT:    csc ra, 56(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 48(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s3, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s4, 16(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    mv s0, a1
+; RV32IXCHERI-NEXT:    cmove s1, a0
+; RV32IXCHERI-NEXT:    clhu a1, 0(a0)
 ; RV32IXCHERI-NEXT:    lui s3, 16
 ; RV32IXCHERI-NEXT:    addi s3, s3, -1
-; RV32IXCHERI-NEXT:    and s4, s2, s3
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 14
-; RV32IXCHERI-NEXT:    csetbounds cs0, ca0, 2
+; RV32IXCHERI-NEXT:    and s4, s0, s3
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 14
+; RV32IXCHERI-NEXT:    csetbounds s2, a0, 2
 ; RV32IXCHERI-NEXT:    j .LBB107_2
 ; RV32IXCHERI-NEXT:  .LBB107_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB107_2 Depth=1
-; RV32IXCHERI-NEXT:    csh a1, 14(csp)
+; RV32IXCHERI-NEXT:    csh a1, 14(sp)
 ; RV32IXCHERI-NEXT:    li a3, 3
-; RV32IXCHERI-NEXT:    cmove ca0, cs1
-; RV32IXCHERI-NEXT:    cmove ca1, cs0
+; RV32IXCHERI-NEXT:    cmove a0, s1
+; RV32IXCHERI-NEXT:    cmove a1, s2
 ; RV32IXCHERI-NEXT:    li a4, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_2
-; RV32IXCHERI-NEXT:    clh a1, 14(csp)
+; RV32IXCHERI-NEXT:    clh a1, 14(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB107_4
 ; RV32IXCHERI-NEXT:  .LBB107_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -7954,29 +7954,29 @@ define i16 @atomicrmw_umin_i16_release(i16 addrspace(200)* %a, i16 %b) nounwind
 ; RV32IXCHERI-NEXT:    bgeu s4, a0, .LBB107_1
 ; RV32IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB107_2 Depth=1
-; RV32IXCHERI-NEXT:    mv a2, s2
+; RV32IXCHERI-NEXT:    mv a2, s0
 ; RV32IXCHERI-NEXT:    j .LBB107_1
 ; RV32IXCHERI-NEXT:  .LBB107_4: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a1
-; RV32IXCHERI-NEXT:    clc cra, 56(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 48(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs3, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs4, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 64
+; RV32IXCHERI-NEXT:    clc ra, 56(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 48(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s3, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s4, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 64
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_umin_i16_release:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB107_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.h a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.h a2, (a0)
 ; RV32IAXCHERI-NEXT:    mv a3, a2
 ; RV32IAXCHERI-NEXT:    bgeu a1, a3, .LBB107_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB107_1 Depth=1
 ; RV32IAXCHERI-NEXT:    mv a3, a1
 ; RV32IAXCHERI-NEXT:  .LBB107_3: # in Loop: Header=BB107_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.h.rl a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.h.rl a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB107_1
 ; RV32IAXCHERI-NEXT:  # %bb.4:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -7984,31 +7984,31 @@ define i16 @atomicrmw_umin_i16_release(i16 addrspace(200)* %a, i16 %b) nounwind
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_umin_i16_release:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -112
-; RV64IXCHERI-NEXT:    csc cra, 96(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 80(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs3, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs4, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    mv s2, a1
-; RV64IXCHERI-NEXT:    cmove cs1, ca0
-; RV64IXCHERI-NEXT:    clhu a1, 0(ca0)
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -112
+; RV64IXCHERI-NEXT:    csc ra, 96(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 80(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s3, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s4, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    mv s0, a1
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    clhu a1, 0(a0)
 ; RV64IXCHERI-NEXT:    lui s3, 16
 ; RV64IXCHERI-NEXT:    addi s3, s3, -1
-; RV64IXCHERI-NEXT:    and s4, s2, s3
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 14
-; RV64IXCHERI-NEXT:    csetbounds cs0, ca0, 2
+; RV64IXCHERI-NEXT:    and s4, s0, s3
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 14
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 2
 ; RV64IXCHERI-NEXT:    j .LBB107_2
 ; RV64IXCHERI-NEXT:  .LBB107_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB107_2 Depth=1
-; RV64IXCHERI-NEXT:    csh a1, 14(csp)
+; RV64IXCHERI-NEXT:    csh a1, 14(sp)
 ; RV64IXCHERI-NEXT:    li a3, 3
-; RV64IXCHERI-NEXT:    cmove ca0, cs1
-; RV64IXCHERI-NEXT:    cmove ca1, cs0
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    li a4, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_2
-; RV64IXCHERI-NEXT:    clh a1, 14(csp)
+; RV64IXCHERI-NEXT:    clh a1, 14(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB107_4
 ; RV64IXCHERI-NEXT:  .LBB107_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -8017,29 +8017,29 @@ define i16 @atomicrmw_umin_i16_release(i16 addrspace(200)* %a, i16 %b) nounwind
 ; RV64IXCHERI-NEXT:    bgeu s4, a0, .LBB107_1
 ; RV64IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB107_2 Depth=1
-; RV64IXCHERI-NEXT:    mv a2, s2
+; RV64IXCHERI-NEXT:    mv a2, s0
 ; RV64IXCHERI-NEXT:    j .LBB107_1
 ; RV64IXCHERI-NEXT:  .LBB107_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 96(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 80(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs3, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs4, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 112
+; RV64IXCHERI-NEXT:    clc ra, 96(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 80(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s3, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s4, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 112
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_umin_i16_release:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB107_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.h a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.h a2, (a0)
 ; RV64IAXCHERI-NEXT:    mv a3, a2
 ; RV64IAXCHERI-NEXT:    bgeu a1, a3, .LBB107_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB107_1 Depth=1
 ; RV64IAXCHERI-NEXT:    mv a3, a1
 ; RV64IAXCHERI-NEXT:  .LBB107_3: # in Loop: Header=BB107_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.h.rl a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.h.rl a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB107_1
 ; RV64IAXCHERI-NEXT:  # %bb.4:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -8051,31 +8051,31 @@ define i16 @atomicrmw_umin_i16_release(i16 addrspace(200)* %a, i16 %b) nounwind
 define i16 @atomicrmw_umin_i16_acq_rel(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_umin_i16_acq_rel:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -64
-; RV32IXCHERI-NEXT:    csc cra, 56(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 48(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs3, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs4, 16(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    mv s2, a1
-; RV32IXCHERI-NEXT:    cmove cs1, ca0
-; RV32IXCHERI-NEXT:    clhu a1, 0(ca0)
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -64
+; RV32IXCHERI-NEXT:    csc ra, 56(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 48(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s3, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s4, 16(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    mv s0, a1
+; RV32IXCHERI-NEXT:    cmove s1, a0
+; RV32IXCHERI-NEXT:    clhu a1, 0(a0)
 ; RV32IXCHERI-NEXT:    lui s3, 16
 ; RV32IXCHERI-NEXT:    addi s3, s3, -1
-; RV32IXCHERI-NEXT:    and s4, s2, s3
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 14
-; RV32IXCHERI-NEXT:    csetbounds cs0, ca0, 2
+; RV32IXCHERI-NEXT:    and s4, s0, s3
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 14
+; RV32IXCHERI-NEXT:    csetbounds s2, a0, 2
 ; RV32IXCHERI-NEXT:    j .LBB108_2
 ; RV32IXCHERI-NEXT:  .LBB108_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB108_2 Depth=1
-; RV32IXCHERI-NEXT:    csh a1, 14(csp)
+; RV32IXCHERI-NEXT:    csh a1, 14(sp)
 ; RV32IXCHERI-NEXT:    li a3, 4
 ; RV32IXCHERI-NEXT:    li a4, 2
-; RV32IXCHERI-NEXT:    cmove ca0, cs1
-; RV32IXCHERI-NEXT:    cmove ca1, cs0
+; RV32IXCHERI-NEXT:    cmove a0, s1
+; RV32IXCHERI-NEXT:    cmove a1, s2
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_2
-; RV32IXCHERI-NEXT:    clh a1, 14(csp)
+; RV32IXCHERI-NEXT:    clh a1, 14(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB108_4
 ; RV32IXCHERI-NEXT:  .LBB108_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -8084,29 +8084,29 @@ define i16 @atomicrmw_umin_i16_acq_rel(i16 addrspace(200)* %a, i16 %b) nounwind
 ; RV32IXCHERI-NEXT:    bgeu s4, a0, .LBB108_1
 ; RV32IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB108_2 Depth=1
-; RV32IXCHERI-NEXT:    mv a2, s2
+; RV32IXCHERI-NEXT:    mv a2, s0
 ; RV32IXCHERI-NEXT:    j .LBB108_1
 ; RV32IXCHERI-NEXT:  .LBB108_4: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a1
-; RV32IXCHERI-NEXT:    clc cra, 56(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 48(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs3, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs4, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 64
+; RV32IXCHERI-NEXT:    clc ra, 56(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 48(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s3, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s4, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 64
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_umin_i16_acq_rel:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB108_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.h.aq a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.h.aq a2, (a0)
 ; RV32IAXCHERI-NEXT:    mv a3, a2
 ; RV32IAXCHERI-NEXT:    bgeu a1, a3, .LBB108_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB108_1 Depth=1
 ; RV32IAXCHERI-NEXT:    mv a3, a1
 ; RV32IAXCHERI-NEXT:  .LBB108_3: # in Loop: Header=BB108_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.h.rl a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.h.rl a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB108_1
 ; RV32IAXCHERI-NEXT:  # %bb.4:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -8114,31 +8114,31 @@ define i16 @atomicrmw_umin_i16_acq_rel(i16 addrspace(200)* %a, i16 %b) nounwind
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_umin_i16_acq_rel:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -112
-; RV64IXCHERI-NEXT:    csc cra, 96(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 80(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs3, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs4, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    mv s2, a1
-; RV64IXCHERI-NEXT:    cmove cs1, ca0
-; RV64IXCHERI-NEXT:    clhu a1, 0(ca0)
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -112
+; RV64IXCHERI-NEXT:    csc ra, 96(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 80(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s3, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s4, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    mv s0, a1
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    clhu a1, 0(a0)
 ; RV64IXCHERI-NEXT:    lui s3, 16
 ; RV64IXCHERI-NEXT:    addi s3, s3, -1
-; RV64IXCHERI-NEXT:    and s4, s2, s3
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 14
-; RV64IXCHERI-NEXT:    csetbounds cs0, ca0, 2
+; RV64IXCHERI-NEXT:    and s4, s0, s3
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 14
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 2
 ; RV64IXCHERI-NEXT:    j .LBB108_2
 ; RV64IXCHERI-NEXT:  .LBB108_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB108_2 Depth=1
-; RV64IXCHERI-NEXT:    csh a1, 14(csp)
+; RV64IXCHERI-NEXT:    csh a1, 14(sp)
 ; RV64IXCHERI-NEXT:    li a3, 4
 ; RV64IXCHERI-NEXT:    li a4, 2
-; RV64IXCHERI-NEXT:    cmove ca0, cs1
-; RV64IXCHERI-NEXT:    cmove ca1, cs0
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_2
-; RV64IXCHERI-NEXT:    clh a1, 14(csp)
+; RV64IXCHERI-NEXT:    clh a1, 14(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB108_4
 ; RV64IXCHERI-NEXT:  .LBB108_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -8147,29 +8147,29 @@ define i16 @atomicrmw_umin_i16_acq_rel(i16 addrspace(200)* %a, i16 %b) nounwind
 ; RV64IXCHERI-NEXT:    bgeu s4, a0, .LBB108_1
 ; RV64IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB108_2 Depth=1
-; RV64IXCHERI-NEXT:    mv a2, s2
+; RV64IXCHERI-NEXT:    mv a2, s0
 ; RV64IXCHERI-NEXT:    j .LBB108_1
 ; RV64IXCHERI-NEXT:  .LBB108_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 96(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 80(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs3, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs4, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 112
+; RV64IXCHERI-NEXT:    clc ra, 96(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 80(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s3, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s4, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 112
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_umin_i16_acq_rel:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB108_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.h.aq a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.h.aq a2, (a0)
 ; RV64IAXCHERI-NEXT:    mv a3, a2
 ; RV64IAXCHERI-NEXT:    bgeu a1, a3, .LBB108_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB108_1 Depth=1
 ; RV64IAXCHERI-NEXT:    mv a3, a1
 ; RV64IAXCHERI-NEXT:  .LBB108_3: # in Loop: Header=BB108_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.h.rl a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.h.rl a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB108_1
 ; RV64IAXCHERI-NEXT:  # %bb.4:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -8181,31 +8181,31 @@ define i16 @atomicrmw_umin_i16_acq_rel(i16 addrspace(200)* %a, i16 %b) nounwind
 define i16 @atomicrmw_umin_i16_seq_cst(i16 addrspace(200)* %a, i16 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_umin_i16_seq_cst:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -64
-; RV32IXCHERI-NEXT:    csc cra, 56(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 48(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs3, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs4, 16(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    mv s2, a1
-; RV32IXCHERI-NEXT:    cmove cs1, ca0
-; RV32IXCHERI-NEXT:    clhu a1, 0(ca0)
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -64
+; RV32IXCHERI-NEXT:    csc ra, 56(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 48(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s3, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s4, 16(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    mv s0, a1
+; RV32IXCHERI-NEXT:    cmove s1, a0
+; RV32IXCHERI-NEXT:    clhu a1, 0(a0)
 ; RV32IXCHERI-NEXT:    lui s3, 16
 ; RV32IXCHERI-NEXT:    addi s3, s3, -1
-; RV32IXCHERI-NEXT:    and s4, s2, s3
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 14
-; RV32IXCHERI-NEXT:    csetbounds cs0, ca0, 2
+; RV32IXCHERI-NEXT:    and s4, s0, s3
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 14
+; RV32IXCHERI-NEXT:    csetbounds s2, a0, 2
 ; RV32IXCHERI-NEXT:    j .LBB109_2
 ; RV32IXCHERI-NEXT:  .LBB109_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB109_2 Depth=1
-; RV32IXCHERI-NEXT:    csh a1, 14(csp)
+; RV32IXCHERI-NEXT:    csh a1, 14(sp)
 ; RV32IXCHERI-NEXT:    li a3, 5
 ; RV32IXCHERI-NEXT:    li a4, 5
-; RV32IXCHERI-NEXT:    cmove ca0, cs1
-; RV32IXCHERI-NEXT:    cmove ca1, cs0
+; RV32IXCHERI-NEXT:    cmove a0, s1
+; RV32IXCHERI-NEXT:    cmove a1, s2
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_2
-; RV32IXCHERI-NEXT:    clh a1, 14(csp)
+; RV32IXCHERI-NEXT:    clh a1, 14(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB109_4
 ; RV32IXCHERI-NEXT:  .LBB109_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -8214,29 +8214,29 @@ define i16 @atomicrmw_umin_i16_seq_cst(i16 addrspace(200)* %a, i16 %b) nounwind
 ; RV32IXCHERI-NEXT:    bgeu s4, a0, .LBB109_1
 ; RV32IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB109_2 Depth=1
-; RV32IXCHERI-NEXT:    mv a2, s2
+; RV32IXCHERI-NEXT:    mv a2, s0
 ; RV32IXCHERI-NEXT:    j .LBB109_1
 ; RV32IXCHERI-NEXT:  .LBB109_4: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a1
-; RV32IXCHERI-NEXT:    clc cra, 56(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 48(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs3, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs4, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 64
+; RV32IXCHERI-NEXT:    clc ra, 56(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 48(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s3, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s4, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 64
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_umin_i16_seq_cst:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB109_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.h.aqrl a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.h.aqrl a2, (a0)
 ; RV32IAXCHERI-NEXT:    mv a3, a2
 ; RV32IAXCHERI-NEXT:    bgeu a1, a3, .LBB109_3
 ; RV32IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB109_1 Depth=1
 ; RV32IAXCHERI-NEXT:    mv a3, a1
 ; RV32IAXCHERI-NEXT:  .LBB109_3: # in Loop: Header=BB109_1 Depth=1
-; RV32IAXCHERI-NEXT:    csc.h.aqrl a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.h.aqrl a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB109_1
 ; RV32IAXCHERI-NEXT:  # %bb.4:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -8244,31 +8244,31 @@ define i16 @atomicrmw_umin_i16_seq_cst(i16 addrspace(200)* %a, i16 %b) nounwind
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_umin_i16_seq_cst:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -112
-; RV64IXCHERI-NEXT:    csc cra, 96(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 80(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs3, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs4, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    mv s2, a1
-; RV64IXCHERI-NEXT:    cmove cs1, ca0
-; RV64IXCHERI-NEXT:    clhu a1, 0(ca0)
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -112
+; RV64IXCHERI-NEXT:    csc ra, 96(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 80(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s3, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s4, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    mv s0, a1
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    clhu a1, 0(a0)
 ; RV64IXCHERI-NEXT:    lui s3, 16
 ; RV64IXCHERI-NEXT:    addi s3, s3, -1
-; RV64IXCHERI-NEXT:    and s4, s2, s3
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 14
-; RV64IXCHERI-NEXT:    csetbounds cs0, ca0, 2
+; RV64IXCHERI-NEXT:    and s4, s0, s3
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 14
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 2
 ; RV64IXCHERI-NEXT:    j .LBB109_2
 ; RV64IXCHERI-NEXT:  .LBB109_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB109_2 Depth=1
-; RV64IXCHERI-NEXT:    csh a1, 14(csp)
+; RV64IXCHERI-NEXT:    csh a1, 14(sp)
 ; RV64IXCHERI-NEXT:    li a3, 5
 ; RV64IXCHERI-NEXT:    li a4, 5
-; RV64IXCHERI-NEXT:    cmove ca0, cs1
-; RV64IXCHERI-NEXT:    cmove ca1, cs0
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_2
-; RV64IXCHERI-NEXT:    clh a1, 14(csp)
+; RV64IXCHERI-NEXT:    clh a1, 14(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB109_4
 ; RV64IXCHERI-NEXT:  .LBB109_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -8277,29 +8277,29 @@ define i16 @atomicrmw_umin_i16_seq_cst(i16 addrspace(200)* %a, i16 %b) nounwind
 ; RV64IXCHERI-NEXT:    bgeu s4, a0, .LBB109_1
 ; RV64IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB109_2 Depth=1
-; RV64IXCHERI-NEXT:    mv a2, s2
+; RV64IXCHERI-NEXT:    mv a2, s0
 ; RV64IXCHERI-NEXT:    j .LBB109_1
 ; RV64IXCHERI-NEXT:  .LBB109_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 96(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 80(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs3, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs4, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 112
+; RV64IXCHERI-NEXT:    clc ra, 96(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 80(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s3, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s4, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 112
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_umin_i16_seq_cst:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB109_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.h.aqrl a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.h.aqrl a2, (a0)
 ; RV64IAXCHERI-NEXT:    mv a3, a2
 ; RV64IAXCHERI-NEXT:    bgeu a1, a3, .LBB109_3
 ; RV64IAXCHERI-NEXT:  # %bb.2: # in Loop: Header=BB109_1 Depth=1
 ; RV64IAXCHERI-NEXT:    mv a3, a1
 ; RV64IAXCHERI-NEXT:  .LBB109_3: # in Loop: Header=BB109_1 Depth=1
-; RV64IAXCHERI-NEXT:    csc.h.aqrl a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.h.aqrl a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB109_1
 ; RV64IAXCHERI-NEXT:  # %bb.4:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -8311,32 +8311,32 @@ define i16 @atomicrmw_umin_i16_seq_cst(i16 addrspace(200)* %a, i16 %b) nounwind
 define i32 @atomicrmw_xchg_i32_monotonic(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_xchg_i32_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_exchange_4
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_xchg_i32_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    camoswap.w a0, a1, (ca0)
+; RV32IAXCHERI-NEXT:    camoswap.w a0, a1, (a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_xchg_i32_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_exchange_4
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_xchg_i32_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camoswap.w a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camoswap.w a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw xchg i32 addrspace(200)* %a, i32 %b monotonic
   ret i32 %1
@@ -8345,32 +8345,32 @@ define i32 @atomicrmw_xchg_i32_monotonic(i32 addrspace(200)* %a, i32 %b) nounwin
 define i32 @atomicrmw_xchg_i32_acquire(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_xchg_i32_acquire:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 2
 ; RV32IXCHERI-NEXT:    ccall __atomic_exchange_4
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_xchg_i32_acquire:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    camoswap.w.aq a0, a1, (ca0)
+; RV32IAXCHERI-NEXT:    camoswap.w.aq a0, a1, (a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_xchg_i32_acquire:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 2
 ; RV64IXCHERI-NEXT:    ccall __atomic_exchange_4
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_xchg_i32_acquire:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camoswap.w.aq a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camoswap.w.aq a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw xchg i32 addrspace(200)* %a, i32 %b acquire
   ret i32 %1
@@ -8379,32 +8379,32 @@ define i32 @atomicrmw_xchg_i32_acquire(i32 addrspace(200)* %a, i32 %b) nounwind
 define i32 @atomicrmw_xchg_i32_release(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_xchg_i32_release:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 3
 ; RV32IXCHERI-NEXT:    ccall __atomic_exchange_4
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_xchg_i32_release:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    camoswap.w.rl a0, a1, (ca0)
+; RV32IAXCHERI-NEXT:    camoswap.w.rl a0, a1, (a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_xchg_i32_release:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 3
 ; RV64IXCHERI-NEXT:    ccall __atomic_exchange_4
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_xchg_i32_release:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camoswap.w.rl a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camoswap.w.rl a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw xchg i32 addrspace(200)* %a, i32 %b release
   ret i32 %1
@@ -8413,32 +8413,32 @@ define i32 @atomicrmw_xchg_i32_release(i32 addrspace(200)* %a, i32 %b) nounwind
 define i32 @atomicrmw_xchg_i32_acq_rel(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_xchg_i32_acq_rel:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 4
 ; RV32IXCHERI-NEXT:    ccall __atomic_exchange_4
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_xchg_i32_acq_rel:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    camoswap.w.aqrl a0, a1, (ca0)
+; RV32IAXCHERI-NEXT:    camoswap.w.aqrl a0, a1, (a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_xchg_i32_acq_rel:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 4
 ; RV64IXCHERI-NEXT:    ccall __atomic_exchange_4
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_xchg_i32_acq_rel:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camoswap.w.aqrl a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camoswap.w.aqrl a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw xchg i32 addrspace(200)* %a, i32 %b acq_rel
   ret i32 %1
@@ -8447,32 +8447,32 @@ define i32 @atomicrmw_xchg_i32_acq_rel(i32 addrspace(200)* %a, i32 %b) nounwind
 define i32 @atomicrmw_xchg_i32_seq_cst(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_xchg_i32_seq_cst:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 5
 ; RV32IXCHERI-NEXT:    ccall __atomic_exchange_4
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_xchg_i32_seq_cst:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    camoswap.w.aqrl a0, a1, (ca0)
+; RV32IAXCHERI-NEXT:    camoswap.w.aqrl a0, a1, (a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_xchg_i32_seq_cst:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 5
 ; RV64IXCHERI-NEXT:    ccall __atomic_exchange_4
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_xchg_i32_seq_cst:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camoswap.w.aqrl a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camoswap.w.aqrl a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw xchg i32 addrspace(200)* %a, i32 %b seq_cst
   ret i32 %1
@@ -8481,32 +8481,32 @@ define i32 @atomicrmw_xchg_i32_seq_cst(i32 addrspace(200)* %a, i32 %b) nounwind
 define i32 @atomicrmw_add_i32_monotonic(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_add_i32_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_add_4
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_add_i32_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    camoadd.w a0, a1, (ca0)
+; RV32IAXCHERI-NEXT:    camoadd.w a0, a1, (a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_add_i32_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_add_4
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_add_i32_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camoadd.w a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camoadd.w a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw add i32 addrspace(200)* %a, i32 %b monotonic
   ret i32 %1
@@ -8515,32 +8515,32 @@ define i32 @atomicrmw_add_i32_monotonic(i32 addrspace(200)* %a, i32 %b) nounwind
 define i32 @atomicrmw_add_i32_acquire(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_add_i32_acquire:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 2
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_add_4
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_add_i32_acquire:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    camoadd.w.aq a0, a1, (ca0)
+; RV32IAXCHERI-NEXT:    camoadd.w.aq a0, a1, (a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_add_i32_acquire:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 2
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_add_4
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_add_i32_acquire:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camoadd.w.aq a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camoadd.w.aq a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw add i32 addrspace(200)* %a, i32 %b acquire
   ret i32 %1
@@ -8549,32 +8549,32 @@ define i32 @atomicrmw_add_i32_acquire(i32 addrspace(200)* %a, i32 %b) nounwind {
 define i32 @atomicrmw_add_i32_release(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_add_i32_release:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 3
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_add_4
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_add_i32_release:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    camoadd.w.rl a0, a1, (ca0)
+; RV32IAXCHERI-NEXT:    camoadd.w.rl a0, a1, (a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_add_i32_release:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 3
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_add_4
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_add_i32_release:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camoadd.w.rl a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camoadd.w.rl a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw add i32 addrspace(200)* %a, i32 %b release
   ret i32 %1
@@ -8583,32 +8583,32 @@ define i32 @atomicrmw_add_i32_release(i32 addrspace(200)* %a, i32 %b) nounwind {
 define i32 @atomicrmw_add_i32_acq_rel(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_add_i32_acq_rel:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 4
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_add_4
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_add_i32_acq_rel:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    camoadd.w.aqrl a0, a1, (ca0)
+; RV32IAXCHERI-NEXT:    camoadd.w.aqrl a0, a1, (a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_add_i32_acq_rel:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 4
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_add_4
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_add_i32_acq_rel:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camoadd.w.aqrl a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camoadd.w.aqrl a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw add i32 addrspace(200)* %a, i32 %b acq_rel
   ret i32 %1
@@ -8617,32 +8617,32 @@ define i32 @atomicrmw_add_i32_acq_rel(i32 addrspace(200)* %a, i32 %b) nounwind {
 define i32 @atomicrmw_add_i32_seq_cst(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_add_i32_seq_cst:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 5
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_add_4
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_add_i32_seq_cst:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    camoadd.w.aqrl a0, a1, (ca0)
+; RV32IAXCHERI-NEXT:    camoadd.w.aqrl a0, a1, (a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_add_i32_seq_cst:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 5
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_add_4
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_add_i32_seq_cst:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camoadd.w.aqrl a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camoadd.w.aqrl a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw add i32 addrspace(200)* %a, i32 %b seq_cst
   ret i32 %1
@@ -8651,34 +8651,34 @@ define i32 @atomicrmw_add_i32_seq_cst(i32 addrspace(200)* %a, i32 %b) nounwind {
 define i32 @atomicrmw_sub_i32_monotonic(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_sub_i32_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_sub_4
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_sub_i32_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:    neg a1, a1
-; RV32IAXCHERI-NEXT:    camoadd.w a0, a1, (ca0)
+; RV32IAXCHERI-NEXT:    camoadd.w a0, a1, (a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_sub_i32_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_sub_4
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_sub_i32_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:    neg a1, a1
-; RV64IAXCHERI-NEXT:    camoadd.w a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camoadd.w a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw sub i32 addrspace(200)* %a, i32 %b monotonic
   ret i32 %1
@@ -8687,34 +8687,34 @@ define i32 @atomicrmw_sub_i32_monotonic(i32 addrspace(200)* %a, i32 %b) nounwind
 define i32 @atomicrmw_sub_i32_acquire(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_sub_i32_acquire:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 2
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_sub_4
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_sub_i32_acquire:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:    neg a1, a1
-; RV32IAXCHERI-NEXT:    camoadd.w.aq a0, a1, (ca0)
+; RV32IAXCHERI-NEXT:    camoadd.w.aq a0, a1, (a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_sub_i32_acquire:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 2
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_sub_4
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_sub_i32_acquire:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:    neg a1, a1
-; RV64IAXCHERI-NEXT:    camoadd.w.aq a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camoadd.w.aq a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw sub i32 addrspace(200)* %a, i32 %b acquire
   ret i32 %1
@@ -8723,34 +8723,34 @@ define i32 @atomicrmw_sub_i32_acquire(i32 addrspace(200)* %a, i32 %b) nounwind {
 define i32 @atomicrmw_sub_i32_release(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_sub_i32_release:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 3
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_sub_4
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_sub_i32_release:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:    neg a1, a1
-; RV32IAXCHERI-NEXT:    camoadd.w.rl a0, a1, (ca0)
+; RV32IAXCHERI-NEXT:    camoadd.w.rl a0, a1, (a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_sub_i32_release:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 3
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_sub_4
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_sub_i32_release:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:    neg a1, a1
-; RV64IAXCHERI-NEXT:    camoadd.w.rl a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camoadd.w.rl a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw sub i32 addrspace(200)* %a, i32 %b release
   ret i32 %1
@@ -8759,34 +8759,34 @@ define i32 @atomicrmw_sub_i32_release(i32 addrspace(200)* %a, i32 %b) nounwind {
 define i32 @atomicrmw_sub_i32_acq_rel(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_sub_i32_acq_rel:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 4
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_sub_4
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_sub_i32_acq_rel:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:    neg a1, a1
-; RV32IAXCHERI-NEXT:    camoadd.w.aqrl a0, a1, (ca0)
+; RV32IAXCHERI-NEXT:    camoadd.w.aqrl a0, a1, (a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_sub_i32_acq_rel:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 4
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_sub_4
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_sub_i32_acq_rel:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:    neg a1, a1
-; RV64IAXCHERI-NEXT:    camoadd.w.aqrl a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camoadd.w.aqrl a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw sub i32 addrspace(200)* %a, i32 %b acq_rel
   ret i32 %1
@@ -8795,34 +8795,34 @@ define i32 @atomicrmw_sub_i32_acq_rel(i32 addrspace(200)* %a, i32 %b) nounwind {
 define i32 @atomicrmw_sub_i32_seq_cst(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_sub_i32_seq_cst:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 5
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_sub_4
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_sub_i32_seq_cst:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:    neg a1, a1
-; RV32IAXCHERI-NEXT:    camoadd.w.aqrl a0, a1, (ca0)
+; RV32IAXCHERI-NEXT:    camoadd.w.aqrl a0, a1, (a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_sub_i32_seq_cst:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 5
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_sub_4
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_sub_i32_seq_cst:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:    neg a1, a1
-; RV64IAXCHERI-NEXT:    camoadd.w.aqrl a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camoadd.w.aqrl a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw sub i32 addrspace(200)* %a, i32 %b seq_cst
   ret i32 %1
@@ -8831,32 +8831,32 @@ define i32 @atomicrmw_sub_i32_seq_cst(i32 addrspace(200)* %a, i32 %b) nounwind {
 define i32 @atomicrmw_and_i32_monotonic(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_and_i32_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_and_4
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_and_i32_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    camoand.w a0, a1, (ca0)
+; RV32IAXCHERI-NEXT:    camoand.w a0, a1, (a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_and_i32_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_and_4
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_and_i32_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camoand.w a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camoand.w a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw and i32 addrspace(200)* %a, i32 %b monotonic
   ret i32 %1
@@ -8865,32 +8865,32 @@ define i32 @atomicrmw_and_i32_monotonic(i32 addrspace(200)* %a, i32 %b) nounwind
 define i32 @atomicrmw_and_i32_acquire(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_and_i32_acquire:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 2
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_and_4
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_and_i32_acquire:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    camoand.w.aq a0, a1, (ca0)
+; RV32IAXCHERI-NEXT:    camoand.w.aq a0, a1, (a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_and_i32_acquire:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 2
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_and_4
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_and_i32_acquire:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camoand.w.aq a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camoand.w.aq a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw and i32 addrspace(200)* %a, i32 %b acquire
   ret i32 %1
@@ -8899,32 +8899,32 @@ define i32 @atomicrmw_and_i32_acquire(i32 addrspace(200)* %a, i32 %b) nounwind {
 define i32 @atomicrmw_and_i32_release(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_and_i32_release:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 3
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_and_4
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_and_i32_release:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    camoand.w.rl a0, a1, (ca0)
+; RV32IAXCHERI-NEXT:    camoand.w.rl a0, a1, (a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_and_i32_release:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 3
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_and_4
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_and_i32_release:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camoand.w.rl a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camoand.w.rl a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw and i32 addrspace(200)* %a, i32 %b release
   ret i32 %1
@@ -8933,32 +8933,32 @@ define i32 @atomicrmw_and_i32_release(i32 addrspace(200)* %a, i32 %b) nounwind {
 define i32 @atomicrmw_and_i32_acq_rel(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_and_i32_acq_rel:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 4
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_and_4
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_and_i32_acq_rel:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    camoand.w.aqrl a0, a1, (ca0)
+; RV32IAXCHERI-NEXT:    camoand.w.aqrl a0, a1, (a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_and_i32_acq_rel:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 4
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_and_4
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_and_i32_acq_rel:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camoand.w.aqrl a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camoand.w.aqrl a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw and i32 addrspace(200)* %a, i32 %b acq_rel
   ret i32 %1
@@ -8967,32 +8967,32 @@ define i32 @atomicrmw_and_i32_acq_rel(i32 addrspace(200)* %a, i32 %b) nounwind {
 define i32 @atomicrmw_and_i32_seq_cst(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_and_i32_seq_cst:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 5
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_and_4
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_and_i32_seq_cst:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    camoand.w.aqrl a0, a1, (ca0)
+; RV32IAXCHERI-NEXT:    camoand.w.aqrl a0, a1, (a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_and_i32_seq_cst:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 5
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_and_4
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_and_i32_seq_cst:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camoand.w.aqrl a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camoand.w.aqrl a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw and i32 addrspace(200)* %a, i32 %b seq_cst
   ret i32 %1
@@ -9001,21 +9001,21 @@ define i32 @atomicrmw_and_i32_seq_cst(i32 addrspace(200)* %a, i32 %b) nounwind {
 define i32 @atomicrmw_nand_i32_monotonic(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_nand_i32_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_nand_4
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_nand_i32_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB130_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.w a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.w a2, (a0)
 ; RV32IAXCHERI-NEXT:    and a3, a2, a1
 ; RV32IAXCHERI-NEXT:    not a3, a3
-; RV32IAXCHERI-NEXT:    csc.w a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.w a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB130_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -9023,21 +9023,21 @@ define i32 @atomicrmw_nand_i32_monotonic(i32 addrspace(200)* %a, i32 %b) nounwin
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_nand_i32_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_nand_4
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_nand_i32_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB130_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.w a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.w a2, (a0)
 ; RV64IAXCHERI-NEXT:    and a3, a2, a1
 ; RV64IAXCHERI-NEXT:    not a3, a3
-; RV64IAXCHERI-NEXT:    csc.w a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.w a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB130_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -9049,21 +9049,21 @@ define i32 @atomicrmw_nand_i32_monotonic(i32 addrspace(200)* %a, i32 %b) nounwin
 define i32 @atomicrmw_nand_i32_acquire(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_nand_i32_acquire:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 2
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_nand_4
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_nand_i32_acquire:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB131_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.w.aq a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.w.aq a2, (a0)
 ; RV32IAXCHERI-NEXT:    and a3, a2, a1
 ; RV32IAXCHERI-NEXT:    not a3, a3
-; RV32IAXCHERI-NEXT:    csc.w a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.w a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB131_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -9071,21 +9071,21 @@ define i32 @atomicrmw_nand_i32_acquire(i32 addrspace(200)* %a, i32 %b) nounwind
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_nand_i32_acquire:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 2
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_nand_4
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_nand_i32_acquire:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB131_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.w.aq a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.w.aq a2, (a0)
 ; RV64IAXCHERI-NEXT:    and a3, a2, a1
 ; RV64IAXCHERI-NEXT:    not a3, a3
-; RV64IAXCHERI-NEXT:    csc.w a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.w a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB131_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -9097,21 +9097,21 @@ define i32 @atomicrmw_nand_i32_acquire(i32 addrspace(200)* %a, i32 %b) nounwind
 define i32 @atomicrmw_nand_i32_release(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_nand_i32_release:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 3
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_nand_4
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_nand_i32_release:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB132_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.w a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.w a2, (a0)
 ; RV32IAXCHERI-NEXT:    and a3, a2, a1
 ; RV32IAXCHERI-NEXT:    not a3, a3
-; RV32IAXCHERI-NEXT:    csc.w.rl a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.w.rl a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB132_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -9119,21 +9119,21 @@ define i32 @atomicrmw_nand_i32_release(i32 addrspace(200)* %a, i32 %b) nounwind
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_nand_i32_release:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 3
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_nand_4
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_nand_i32_release:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB132_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.w a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.w a2, (a0)
 ; RV64IAXCHERI-NEXT:    and a3, a2, a1
 ; RV64IAXCHERI-NEXT:    not a3, a3
-; RV64IAXCHERI-NEXT:    csc.w.rl a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.w.rl a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB132_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -9145,21 +9145,21 @@ define i32 @atomicrmw_nand_i32_release(i32 addrspace(200)* %a, i32 %b) nounwind
 define i32 @atomicrmw_nand_i32_acq_rel(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_nand_i32_acq_rel:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 4
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_nand_4
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_nand_i32_acq_rel:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB133_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.w.aq a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.w.aq a2, (a0)
 ; RV32IAXCHERI-NEXT:    and a3, a2, a1
 ; RV32IAXCHERI-NEXT:    not a3, a3
-; RV32IAXCHERI-NEXT:    csc.w.rl a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.w.rl a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB133_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -9167,21 +9167,21 @@ define i32 @atomicrmw_nand_i32_acq_rel(i32 addrspace(200)* %a, i32 %b) nounwind
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_nand_i32_acq_rel:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 4
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_nand_4
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_nand_i32_acq_rel:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB133_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.w.aq a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.w.aq a2, (a0)
 ; RV64IAXCHERI-NEXT:    and a3, a2, a1
 ; RV64IAXCHERI-NEXT:    not a3, a3
-; RV64IAXCHERI-NEXT:    csc.w.rl a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.w.rl a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB133_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -9193,21 +9193,21 @@ define i32 @atomicrmw_nand_i32_acq_rel(i32 addrspace(200)* %a, i32 %b) nounwind
 define i32 @atomicrmw_nand_i32_seq_cst(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_nand_i32_seq_cst:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 5
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_nand_4
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_nand_i32_seq_cst:
 ; RV32IAXCHERI:       # %bb.0:
 ; RV32IAXCHERI-NEXT:  .LBB134_1: # =>This Inner Loop Header: Depth=1
-; RV32IAXCHERI-NEXT:    clr.w.aqrl a2, (ca0)
+; RV32IAXCHERI-NEXT:    clr.w.aqrl a2, (a0)
 ; RV32IAXCHERI-NEXT:    and a3, a2, a1
 ; RV32IAXCHERI-NEXT:    not a3, a3
-; RV32IAXCHERI-NEXT:    csc.w.rl a3, a3, (ca0)
+; RV32IAXCHERI-NEXT:    csc.w.rl a3, a3, (a0)
 ; RV32IAXCHERI-NEXT:    bnez a3, .LBB134_1
 ; RV32IAXCHERI-NEXT:  # %bb.2:
 ; RV32IAXCHERI-NEXT:    mv a0, a2
@@ -9215,21 +9215,21 @@ define i32 @atomicrmw_nand_i32_seq_cst(i32 addrspace(200)* %a, i32 %b) nounwind
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_nand_i32_seq_cst:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 5
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_nand_4
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_nand_i32_seq_cst:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB134_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.w.aqrl a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.w.aqrl a2, (a0)
 ; RV64IAXCHERI-NEXT:    and a3, a2, a1
 ; RV64IAXCHERI-NEXT:    not a3, a3
-; RV64IAXCHERI-NEXT:    csc.w.rl a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.w.rl a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB134_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -9241,32 +9241,32 @@ define i32 @atomicrmw_nand_i32_seq_cst(i32 addrspace(200)* %a, i32 %b) nounwind
 define i32 @atomicrmw_or_i32_monotonic(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_or_i32_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_or_4
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_or_i32_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    camoor.w a0, a1, (ca0)
+; RV32IAXCHERI-NEXT:    camoor.w a0, a1, (a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_or_i32_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_or_4
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_or_i32_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camoor.w a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camoor.w a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw or i32 addrspace(200)* %a, i32 %b monotonic
   ret i32 %1
@@ -9275,32 +9275,32 @@ define i32 @atomicrmw_or_i32_monotonic(i32 addrspace(200)* %a, i32 %b) nounwind
 define i32 @atomicrmw_or_i32_acquire(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_or_i32_acquire:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 2
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_or_4
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_or_i32_acquire:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    camoor.w.aq a0, a1, (ca0)
+; RV32IAXCHERI-NEXT:    camoor.w.aq a0, a1, (a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_or_i32_acquire:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 2
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_or_4
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_or_i32_acquire:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camoor.w.aq a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camoor.w.aq a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw or i32 addrspace(200)* %a, i32 %b acquire
   ret i32 %1
@@ -9309,32 +9309,32 @@ define i32 @atomicrmw_or_i32_acquire(i32 addrspace(200)* %a, i32 %b) nounwind {
 define i32 @atomicrmw_or_i32_release(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_or_i32_release:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 3
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_or_4
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_or_i32_release:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    camoor.w.rl a0, a1, (ca0)
+; RV32IAXCHERI-NEXT:    camoor.w.rl a0, a1, (a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_or_i32_release:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 3
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_or_4
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_or_i32_release:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camoor.w.rl a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camoor.w.rl a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw or i32 addrspace(200)* %a, i32 %b release
   ret i32 %1
@@ -9343,32 +9343,32 @@ define i32 @atomicrmw_or_i32_release(i32 addrspace(200)* %a, i32 %b) nounwind {
 define i32 @atomicrmw_or_i32_acq_rel(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_or_i32_acq_rel:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 4
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_or_4
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_or_i32_acq_rel:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    camoor.w.aqrl a0, a1, (ca0)
+; RV32IAXCHERI-NEXT:    camoor.w.aqrl a0, a1, (a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_or_i32_acq_rel:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 4
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_or_4
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_or_i32_acq_rel:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camoor.w.aqrl a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camoor.w.aqrl a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw or i32 addrspace(200)* %a, i32 %b acq_rel
   ret i32 %1
@@ -9377,32 +9377,32 @@ define i32 @atomicrmw_or_i32_acq_rel(i32 addrspace(200)* %a, i32 %b) nounwind {
 define i32 @atomicrmw_or_i32_seq_cst(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_or_i32_seq_cst:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 5
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_or_4
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_or_i32_seq_cst:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    camoor.w.aqrl a0, a1, (ca0)
+; RV32IAXCHERI-NEXT:    camoor.w.aqrl a0, a1, (a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_or_i32_seq_cst:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 5
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_or_4
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_or_i32_seq_cst:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camoor.w.aqrl a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camoor.w.aqrl a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw or i32 addrspace(200)* %a, i32 %b seq_cst
   ret i32 %1
@@ -9411,32 +9411,32 @@ define i32 @atomicrmw_or_i32_seq_cst(i32 addrspace(200)* %a, i32 %b) nounwind {
 define i32 @atomicrmw_xor_i32_monotonic(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_xor_i32_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_xor_4
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_xor_i32_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    camoxor.w a0, a1, (ca0)
+; RV32IAXCHERI-NEXT:    camoxor.w a0, a1, (a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_xor_i32_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_xor_4
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_xor_i32_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camoxor.w a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camoxor.w a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw xor i32 addrspace(200)* %a, i32 %b monotonic
   ret i32 %1
@@ -9445,32 +9445,32 @@ define i32 @atomicrmw_xor_i32_monotonic(i32 addrspace(200)* %a, i32 %b) nounwind
 define i32 @atomicrmw_xor_i32_acquire(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_xor_i32_acquire:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 2
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_xor_4
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_xor_i32_acquire:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    camoxor.w.aq a0, a1, (ca0)
+; RV32IAXCHERI-NEXT:    camoxor.w.aq a0, a1, (a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_xor_i32_acquire:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 2
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_xor_4
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_xor_i32_acquire:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camoxor.w.aq a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camoxor.w.aq a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw xor i32 addrspace(200)* %a, i32 %b acquire
   ret i32 %1
@@ -9479,32 +9479,32 @@ define i32 @atomicrmw_xor_i32_acquire(i32 addrspace(200)* %a, i32 %b) nounwind {
 define i32 @atomicrmw_xor_i32_release(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_xor_i32_release:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 3
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_xor_4
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_xor_i32_release:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    camoxor.w.rl a0, a1, (ca0)
+; RV32IAXCHERI-NEXT:    camoxor.w.rl a0, a1, (a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_xor_i32_release:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 3
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_xor_4
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_xor_i32_release:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camoxor.w.rl a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camoxor.w.rl a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw xor i32 addrspace(200)* %a, i32 %b release
   ret i32 %1
@@ -9513,32 +9513,32 @@ define i32 @atomicrmw_xor_i32_release(i32 addrspace(200)* %a, i32 %b) nounwind {
 define i32 @atomicrmw_xor_i32_acq_rel(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_xor_i32_acq_rel:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 4
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_xor_4
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_xor_i32_acq_rel:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    camoxor.w.aqrl a0, a1, (ca0)
+; RV32IAXCHERI-NEXT:    camoxor.w.aqrl a0, a1, (a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_xor_i32_acq_rel:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 4
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_xor_4
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_xor_i32_acq_rel:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camoxor.w.aqrl a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camoxor.w.aqrl a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw xor i32 addrspace(200)* %a, i32 %b acq_rel
   ret i32 %1
@@ -9547,32 +9547,32 @@ define i32 @atomicrmw_xor_i32_acq_rel(i32 addrspace(200)* %a, i32 %b) nounwind {
 define i32 @atomicrmw_xor_i32_seq_cst(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_xor_i32_seq_cst:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 5
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_xor_4
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_xor_i32_seq_cst:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    camoxor.w.aqrl a0, a1, (ca0)
+; RV32IAXCHERI-NEXT:    camoxor.w.aqrl a0, a1, (a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_xor_i32_seq_cst:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 5
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_xor_4
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_xor_i32_seq_cst:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camoxor.w.aqrl a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camoxor.w.aqrl a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw xor i32 addrspace(200)* %a, i32 %b seq_cst
   ret i32 %1
@@ -9581,26 +9581,26 @@ define i32 @atomicrmw_xor_i32_seq_cst(i32 addrspace(200)* %a, i32 %b) nounwind {
 define i32 @atomicrmw_max_i32_monotonic(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_max_i32_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    mv s0, a1
-; RV32IXCHERI-NEXT:    cmove cs2, ca0
-; RV32IXCHERI-NEXT:    clw a1, 0(ca0)
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 12
-; RV32IXCHERI-NEXT:    csetbounds cs1, ca0, 4
+; RV32IXCHERI-NEXT:    cmove s1, a0
+; RV32IXCHERI-NEXT:    clw a1, 0(a0)
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 12
+; RV32IXCHERI-NEXT:    csetbounds s2, a0, 4
 ; RV32IXCHERI-NEXT:    j .LBB145_2
 ; RV32IXCHERI-NEXT:  .LBB145_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB145_2 Depth=1
-; RV32IXCHERI-NEXT:    csw a1, 12(csp)
-; RV32IXCHERI-NEXT:    cmove ca0, cs2
-; RV32IXCHERI-NEXT:    cmove ca1, cs1
+; RV32IXCHERI-NEXT:    csw a1, 12(sp)
+; RV32IXCHERI-NEXT:    cmove a0, s1
+; RV32IXCHERI-NEXT:    cmove a1, s2
 ; RV32IXCHERI-NEXT:    li a3, 0
 ; RV32IXCHERI-NEXT:    li a4, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_4
-; RV32IXCHERI-NEXT:    clw a1, 12(csp)
+; RV32IXCHERI-NEXT:    clw a1, 12(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB145_4
 ; RV32IXCHERI-NEXT:  .LBB145_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -9612,42 +9612,42 @@ define i32 @atomicrmw_max_i32_monotonic(i32 addrspace(200)* %a, i32 %b) nounwind
 ; RV32IXCHERI-NEXT:    j .LBB145_1
 ; RV32IXCHERI-NEXT:  .LBB145_4: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a1
-; RV32IXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_max_i32_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    camomax.w a0, a1, (ca0)
+; RV32IAXCHERI-NEXT:    camomax.w a0, a1, (a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_max_i32_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -96
-; RV64IXCHERI-NEXT:    csc cra, 80(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs3, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    mv s2, a1
-; RV64IXCHERI-NEXT:    cmove cs1, ca0
-; RV64IXCHERI-NEXT:    clw a1, 0(ca0)
-; RV64IXCHERI-NEXT:    sext.w s3, s2
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 12
-; RV64IXCHERI-NEXT:    csetbounds cs0, ca0, 4
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -96
+; RV64IXCHERI-NEXT:    csc ra, 80(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s3, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    mv s0, a1
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    clw a1, 0(a0)
+; RV64IXCHERI-NEXT:    sext.w s3, s0
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 12
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 4
 ; RV64IXCHERI-NEXT:    j .LBB145_2
 ; RV64IXCHERI-NEXT:  .LBB145_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB145_2 Depth=1
-; RV64IXCHERI-NEXT:    csw a1, 12(csp)
-; RV64IXCHERI-NEXT:    cmove ca0, cs1
-; RV64IXCHERI-NEXT:    cmove ca1, cs0
+; RV64IXCHERI-NEXT:    csw a1, 12(sp)
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    li a3, 0
 ; RV64IXCHERI-NEXT:    li a4, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_4
-; RV64IXCHERI-NEXT:    clw a1, 12(csp)
+; RV64IXCHERI-NEXT:    clw a1, 12(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB145_4
 ; RV64IXCHERI-NEXT:  .LBB145_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -9656,21 +9656,21 @@ define i32 @atomicrmw_max_i32_monotonic(i32 addrspace(200)* %a, i32 %b) nounwind
 ; RV64IXCHERI-NEXT:    blt s3, a0, .LBB145_1
 ; RV64IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB145_2 Depth=1
-; RV64IXCHERI-NEXT:    mv a2, s2
+; RV64IXCHERI-NEXT:    mv a2, s0
 ; RV64IXCHERI-NEXT:    j .LBB145_1
 ; RV64IXCHERI-NEXT:  .LBB145_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 80(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs3, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 96
+; RV64IXCHERI-NEXT:    clc ra, 80(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s3, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 96
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_max_i32_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camomax.w a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camomax.w a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw max i32 addrspace(200)* %a, i32 %b monotonic
   ret i32 %1
@@ -9679,26 +9679,26 @@ define i32 @atomicrmw_max_i32_monotonic(i32 addrspace(200)* %a, i32 %b) nounwind
 define i32 @atomicrmw_max_i32_acquire(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_max_i32_acquire:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    mv s0, a1
-; RV32IXCHERI-NEXT:    cmove cs2, ca0
-; RV32IXCHERI-NEXT:    clw a1, 0(ca0)
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 12
-; RV32IXCHERI-NEXT:    csetbounds cs1, ca0, 4
+; RV32IXCHERI-NEXT:    cmove s1, a0
+; RV32IXCHERI-NEXT:    clw a1, 0(a0)
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 12
+; RV32IXCHERI-NEXT:    csetbounds s2, a0, 4
 ; RV32IXCHERI-NEXT:    j .LBB146_2
 ; RV32IXCHERI-NEXT:  .LBB146_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB146_2 Depth=1
-; RV32IXCHERI-NEXT:    csw a1, 12(csp)
+; RV32IXCHERI-NEXT:    csw a1, 12(sp)
 ; RV32IXCHERI-NEXT:    li a3, 2
 ; RV32IXCHERI-NEXT:    li a4, 2
-; RV32IXCHERI-NEXT:    cmove ca0, cs2
-; RV32IXCHERI-NEXT:    cmove ca1, cs1
+; RV32IXCHERI-NEXT:    cmove a0, s1
+; RV32IXCHERI-NEXT:    cmove a1, s2
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_4
-; RV32IXCHERI-NEXT:    clw a1, 12(csp)
+; RV32IXCHERI-NEXT:    clw a1, 12(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB146_4
 ; RV32IXCHERI-NEXT:  .LBB146_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -9710,42 +9710,42 @@ define i32 @atomicrmw_max_i32_acquire(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV32IXCHERI-NEXT:    j .LBB146_1
 ; RV32IXCHERI-NEXT:  .LBB146_4: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a1
-; RV32IXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_max_i32_acquire:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    camomax.w.aq a0, a1, (ca0)
+; RV32IAXCHERI-NEXT:    camomax.w.aq a0, a1, (a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_max_i32_acquire:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -96
-; RV64IXCHERI-NEXT:    csc cra, 80(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs3, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    mv s2, a1
-; RV64IXCHERI-NEXT:    cmove cs1, ca0
-; RV64IXCHERI-NEXT:    clw a1, 0(ca0)
-; RV64IXCHERI-NEXT:    sext.w s3, s2
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 12
-; RV64IXCHERI-NEXT:    csetbounds cs0, ca0, 4
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -96
+; RV64IXCHERI-NEXT:    csc ra, 80(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s3, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    mv s0, a1
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    clw a1, 0(a0)
+; RV64IXCHERI-NEXT:    sext.w s3, s0
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 12
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 4
 ; RV64IXCHERI-NEXT:    j .LBB146_2
 ; RV64IXCHERI-NEXT:  .LBB146_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB146_2 Depth=1
-; RV64IXCHERI-NEXT:    csw a1, 12(csp)
+; RV64IXCHERI-NEXT:    csw a1, 12(sp)
 ; RV64IXCHERI-NEXT:    li a3, 2
 ; RV64IXCHERI-NEXT:    li a4, 2
-; RV64IXCHERI-NEXT:    cmove ca0, cs1
-; RV64IXCHERI-NEXT:    cmove ca1, cs0
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_4
-; RV64IXCHERI-NEXT:    clw a1, 12(csp)
+; RV64IXCHERI-NEXT:    clw a1, 12(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB146_4
 ; RV64IXCHERI-NEXT:  .LBB146_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -9754,21 +9754,21 @@ define i32 @atomicrmw_max_i32_acquire(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV64IXCHERI-NEXT:    blt s3, a0, .LBB146_1
 ; RV64IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB146_2 Depth=1
-; RV64IXCHERI-NEXT:    mv a2, s2
+; RV64IXCHERI-NEXT:    mv a2, s0
 ; RV64IXCHERI-NEXT:    j .LBB146_1
 ; RV64IXCHERI-NEXT:  .LBB146_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 80(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs3, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 96
+; RV64IXCHERI-NEXT:    clc ra, 80(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s3, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 96
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_max_i32_acquire:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camomax.w.aq a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camomax.w.aq a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw max i32 addrspace(200)* %a, i32 %b acquire
   ret i32 %1
@@ -9777,26 +9777,26 @@ define i32 @atomicrmw_max_i32_acquire(i32 addrspace(200)* %a, i32 %b) nounwind {
 define i32 @atomicrmw_max_i32_release(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_max_i32_release:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    mv s0, a1
-; RV32IXCHERI-NEXT:    cmove cs2, ca0
-; RV32IXCHERI-NEXT:    clw a1, 0(ca0)
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 12
-; RV32IXCHERI-NEXT:    csetbounds cs1, ca0, 4
+; RV32IXCHERI-NEXT:    cmove s1, a0
+; RV32IXCHERI-NEXT:    clw a1, 0(a0)
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 12
+; RV32IXCHERI-NEXT:    csetbounds s2, a0, 4
 ; RV32IXCHERI-NEXT:    j .LBB147_2
 ; RV32IXCHERI-NEXT:  .LBB147_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB147_2 Depth=1
-; RV32IXCHERI-NEXT:    csw a1, 12(csp)
+; RV32IXCHERI-NEXT:    csw a1, 12(sp)
 ; RV32IXCHERI-NEXT:    li a3, 3
-; RV32IXCHERI-NEXT:    cmove ca0, cs2
-; RV32IXCHERI-NEXT:    cmove ca1, cs1
+; RV32IXCHERI-NEXT:    cmove a0, s1
+; RV32IXCHERI-NEXT:    cmove a1, s2
 ; RV32IXCHERI-NEXT:    li a4, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_4
-; RV32IXCHERI-NEXT:    clw a1, 12(csp)
+; RV32IXCHERI-NEXT:    clw a1, 12(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB147_4
 ; RV32IXCHERI-NEXT:  .LBB147_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -9808,42 +9808,42 @@ define i32 @atomicrmw_max_i32_release(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV32IXCHERI-NEXT:    j .LBB147_1
 ; RV32IXCHERI-NEXT:  .LBB147_4: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a1
-; RV32IXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_max_i32_release:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    camomax.w.rl a0, a1, (ca0)
+; RV32IAXCHERI-NEXT:    camomax.w.rl a0, a1, (a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_max_i32_release:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -96
-; RV64IXCHERI-NEXT:    csc cra, 80(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs3, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    mv s2, a1
-; RV64IXCHERI-NEXT:    cmove cs1, ca0
-; RV64IXCHERI-NEXT:    clw a1, 0(ca0)
-; RV64IXCHERI-NEXT:    sext.w s3, s2
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 12
-; RV64IXCHERI-NEXT:    csetbounds cs0, ca0, 4
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -96
+; RV64IXCHERI-NEXT:    csc ra, 80(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s3, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    mv s0, a1
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    clw a1, 0(a0)
+; RV64IXCHERI-NEXT:    sext.w s3, s0
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 12
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 4
 ; RV64IXCHERI-NEXT:    j .LBB147_2
 ; RV64IXCHERI-NEXT:  .LBB147_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB147_2 Depth=1
-; RV64IXCHERI-NEXT:    csw a1, 12(csp)
+; RV64IXCHERI-NEXT:    csw a1, 12(sp)
 ; RV64IXCHERI-NEXT:    li a3, 3
-; RV64IXCHERI-NEXT:    cmove ca0, cs1
-; RV64IXCHERI-NEXT:    cmove ca1, cs0
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    li a4, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_4
-; RV64IXCHERI-NEXT:    clw a1, 12(csp)
+; RV64IXCHERI-NEXT:    clw a1, 12(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB147_4
 ; RV64IXCHERI-NEXT:  .LBB147_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -9852,21 +9852,21 @@ define i32 @atomicrmw_max_i32_release(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV64IXCHERI-NEXT:    blt s3, a0, .LBB147_1
 ; RV64IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB147_2 Depth=1
-; RV64IXCHERI-NEXT:    mv a2, s2
+; RV64IXCHERI-NEXT:    mv a2, s0
 ; RV64IXCHERI-NEXT:    j .LBB147_1
 ; RV64IXCHERI-NEXT:  .LBB147_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 80(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs3, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 96
+; RV64IXCHERI-NEXT:    clc ra, 80(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s3, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 96
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_max_i32_release:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camomax.w.rl a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camomax.w.rl a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw max i32 addrspace(200)* %a, i32 %b release
   ret i32 %1
@@ -9875,26 +9875,26 @@ define i32 @atomicrmw_max_i32_release(i32 addrspace(200)* %a, i32 %b) nounwind {
 define i32 @atomicrmw_max_i32_acq_rel(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_max_i32_acq_rel:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    mv s0, a1
-; RV32IXCHERI-NEXT:    cmove cs2, ca0
-; RV32IXCHERI-NEXT:    clw a1, 0(ca0)
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 12
-; RV32IXCHERI-NEXT:    csetbounds cs1, ca0, 4
+; RV32IXCHERI-NEXT:    cmove s1, a0
+; RV32IXCHERI-NEXT:    clw a1, 0(a0)
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 12
+; RV32IXCHERI-NEXT:    csetbounds s2, a0, 4
 ; RV32IXCHERI-NEXT:    j .LBB148_2
 ; RV32IXCHERI-NEXT:  .LBB148_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB148_2 Depth=1
-; RV32IXCHERI-NEXT:    csw a1, 12(csp)
+; RV32IXCHERI-NEXT:    csw a1, 12(sp)
 ; RV32IXCHERI-NEXT:    li a3, 4
 ; RV32IXCHERI-NEXT:    li a4, 2
-; RV32IXCHERI-NEXT:    cmove ca0, cs2
-; RV32IXCHERI-NEXT:    cmove ca1, cs1
+; RV32IXCHERI-NEXT:    cmove a0, s1
+; RV32IXCHERI-NEXT:    cmove a1, s2
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_4
-; RV32IXCHERI-NEXT:    clw a1, 12(csp)
+; RV32IXCHERI-NEXT:    clw a1, 12(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB148_4
 ; RV32IXCHERI-NEXT:  .LBB148_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -9906,42 +9906,42 @@ define i32 @atomicrmw_max_i32_acq_rel(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV32IXCHERI-NEXT:    j .LBB148_1
 ; RV32IXCHERI-NEXT:  .LBB148_4: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a1
-; RV32IXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_max_i32_acq_rel:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    camomax.w.aqrl a0, a1, (ca0)
+; RV32IAXCHERI-NEXT:    camomax.w.aqrl a0, a1, (a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_max_i32_acq_rel:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -96
-; RV64IXCHERI-NEXT:    csc cra, 80(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs3, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    mv s2, a1
-; RV64IXCHERI-NEXT:    cmove cs1, ca0
-; RV64IXCHERI-NEXT:    clw a1, 0(ca0)
-; RV64IXCHERI-NEXT:    sext.w s3, s2
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 12
-; RV64IXCHERI-NEXT:    csetbounds cs0, ca0, 4
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -96
+; RV64IXCHERI-NEXT:    csc ra, 80(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s3, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    mv s0, a1
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    clw a1, 0(a0)
+; RV64IXCHERI-NEXT:    sext.w s3, s0
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 12
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 4
 ; RV64IXCHERI-NEXT:    j .LBB148_2
 ; RV64IXCHERI-NEXT:  .LBB148_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB148_2 Depth=1
-; RV64IXCHERI-NEXT:    csw a1, 12(csp)
+; RV64IXCHERI-NEXT:    csw a1, 12(sp)
 ; RV64IXCHERI-NEXT:    li a3, 4
 ; RV64IXCHERI-NEXT:    li a4, 2
-; RV64IXCHERI-NEXT:    cmove ca0, cs1
-; RV64IXCHERI-NEXT:    cmove ca1, cs0
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_4
-; RV64IXCHERI-NEXT:    clw a1, 12(csp)
+; RV64IXCHERI-NEXT:    clw a1, 12(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB148_4
 ; RV64IXCHERI-NEXT:  .LBB148_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -9950,21 +9950,21 @@ define i32 @atomicrmw_max_i32_acq_rel(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV64IXCHERI-NEXT:    blt s3, a0, .LBB148_1
 ; RV64IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB148_2 Depth=1
-; RV64IXCHERI-NEXT:    mv a2, s2
+; RV64IXCHERI-NEXT:    mv a2, s0
 ; RV64IXCHERI-NEXT:    j .LBB148_1
 ; RV64IXCHERI-NEXT:  .LBB148_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 80(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs3, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 96
+; RV64IXCHERI-NEXT:    clc ra, 80(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s3, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 96
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_max_i32_acq_rel:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camomax.w.aqrl a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camomax.w.aqrl a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw max i32 addrspace(200)* %a, i32 %b acq_rel
   ret i32 %1
@@ -9973,26 +9973,26 @@ define i32 @atomicrmw_max_i32_acq_rel(i32 addrspace(200)* %a, i32 %b) nounwind {
 define i32 @atomicrmw_max_i32_seq_cst(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_max_i32_seq_cst:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    mv s0, a1
-; RV32IXCHERI-NEXT:    cmove cs2, ca0
-; RV32IXCHERI-NEXT:    clw a1, 0(ca0)
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 12
-; RV32IXCHERI-NEXT:    csetbounds cs1, ca0, 4
+; RV32IXCHERI-NEXT:    cmove s1, a0
+; RV32IXCHERI-NEXT:    clw a1, 0(a0)
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 12
+; RV32IXCHERI-NEXT:    csetbounds s2, a0, 4
 ; RV32IXCHERI-NEXT:    j .LBB149_2
 ; RV32IXCHERI-NEXT:  .LBB149_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB149_2 Depth=1
-; RV32IXCHERI-NEXT:    csw a1, 12(csp)
+; RV32IXCHERI-NEXT:    csw a1, 12(sp)
 ; RV32IXCHERI-NEXT:    li a3, 5
 ; RV32IXCHERI-NEXT:    li a4, 5
-; RV32IXCHERI-NEXT:    cmove ca0, cs2
-; RV32IXCHERI-NEXT:    cmove ca1, cs1
+; RV32IXCHERI-NEXT:    cmove a0, s1
+; RV32IXCHERI-NEXT:    cmove a1, s2
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_4
-; RV32IXCHERI-NEXT:    clw a1, 12(csp)
+; RV32IXCHERI-NEXT:    clw a1, 12(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB149_4
 ; RV32IXCHERI-NEXT:  .LBB149_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -10004,42 +10004,42 @@ define i32 @atomicrmw_max_i32_seq_cst(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV32IXCHERI-NEXT:    j .LBB149_1
 ; RV32IXCHERI-NEXT:  .LBB149_4: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a1
-; RV32IXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_max_i32_seq_cst:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    camomax.w.aqrl a0, a1, (ca0)
+; RV32IAXCHERI-NEXT:    camomax.w.aqrl a0, a1, (a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_max_i32_seq_cst:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -96
-; RV64IXCHERI-NEXT:    csc cra, 80(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs3, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    mv s2, a1
-; RV64IXCHERI-NEXT:    cmove cs1, ca0
-; RV64IXCHERI-NEXT:    clw a1, 0(ca0)
-; RV64IXCHERI-NEXT:    sext.w s3, s2
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 12
-; RV64IXCHERI-NEXT:    csetbounds cs0, ca0, 4
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -96
+; RV64IXCHERI-NEXT:    csc ra, 80(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s3, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    mv s0, a1
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    clw a1, 0(a0)
+; RV64IXCHERI-NEXT:    sext.w s3, s0
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 12
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 4
 ; RV64IXCHERI-NEXT:    j .LBB149_2
 ; RV64IXCHERI-NEXT:  .LBB149_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB149_2 Depth=1
-; RV64IXCHERI-NEXT:    csw a1, 12(csp)
+; RV64IXCHERI-NEXT:    csw a1, 12(sp)
 ; RV64IXCHERI-NEXT:    li a3, 5
 ; RV64IXCHERI-NEXT:    li a4, 5
-; RV64IXCHERI-NEXT:    cmove ca0, cs1
-; RV64IXCHERI-NEXT:    cmove ca1, cs0
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_4
-; RV64IXCHERI-NEXT:    clw a1, 12(csp)
+; RV64IXCHERI-NEXT:    clw a1, 12(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB149_4
 ; RV64IXCHERI-NEXT:  .LBB149_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -10048,21 +10048,21 @@ define i32 @atomicrmw_max_i32_seq_cst(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV64IXCHERI-NEXT:    blt s3, a0, .LBB149_1
 ; RV64IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB149_2 Depth=1
-; RV64IXCHERI-NEXT:    mv a2, s2
+; RV64IXCHERI-NEXT:    mv a2, s0
 ; RV64IXCHERI-NEXT:    j .LBB149_1
 ; RV64IXCHERI-NEXT:  .LBB149_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 80(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs3, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 96
+; RV64IXCHERI-NEXT:    clc ra, 80(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s3, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 96
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_max_i32_seq_cst:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camomax.w.aqrl a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camomax.w.aqrl a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw max i32 addrspace(200)* %a, i32 %b seq_cst
   ret i32 %1
@@ -10071,26 +10071,26 @@ define i32 @atomicrmw_max_i32_seq_cst(i32 addrspace(200)* %a, i32 %b) nounwind {
 define i32 @atomicrmw_min_i32_monotonic(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_min_i32_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    mv s0, a1
-; RV32IXCHERI-NEXT:    cmove cs2, ca0
-; RV32IXCHERI-NEXT:    clw a1, 0(ca0)
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 12
-; RV32IXCHERI-NEXT:    csetbounds cs1, ca0, 4
+; RV32IXCHERI-NEXT:    cmove s1, a0
+; RV32IXCHERI-NEXT:    clw a1, 0(a0)
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 12
+; RV32IXCHERI-NEXT:    csetbounds s2, a0, 4
 ; RV32IXCHERI-NEXT:    j .LBB150_2
 ; RV32IXCHERI-NEXT:  .LBB150_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB150_2 Depth=1
-; RV32IXCHERI-NEXT:    csw a1, 12(csp)
-; RV32IXCHERI-NEXT:    cmove ca0, cs2
-; RV32IXCHERI-NEXT:    cmove ca1, cs1
+; RV32IXCHERI-NEXT:    csw a1, 12(sp)
+; RV32IXCHERI-NEXT:    cmove a0, s1
+; RV32IXCHERI-NEXT:    cmove a1, s2
 ; RV32IXCHERI-NEXT:    li a3, 0
 ; RV32IXCHERI-NEXT:    li a4, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_4
-; RV32IXCHERI-NEXT:    clw a1, 12(csp)
+; RV32IXCHERI-NEXT:    clw a1, 12(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB150_4
 ; RV32IXCHERI-NEXT:  .LBB150_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -10102,42 +10102,42 @@ define i32 @atomicrmw_min_i32_monotonic(i32 addrspace(200)* %a, i32 %b) nounwind
 ; RV32IXCHERI-NEXT:    j .LBB150_1
 ; RV32IXCHERI-NEXT:  .LBB150_4: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a1
-; RV32IXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_min_i32_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    camomin.w a0, a1, (ca0)
+; RV32IAXCHERI-NEXT:    camomin.w a0, a1, (a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_min_i32_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -96
-; RV64IXCHERI-NEXT:    csc cra, 80(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs3, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    mv s2, a1
-; RV64IXCHERI-NEXT:    cmove cs1, ca0
-; RV64IXCHERI-NEXT:    clw a1, 0(ca0)
-; RV64IXCHERI-NEXT:    sext.w s3, s2
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 12
-; RV64IXCHERI-NEXT:    csetbounds cs0, ca0, 4
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -96
+; RV64IXCHERI-NEXT:    csc ra, 80(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s3, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    mv s0, a1
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    clw a1, 0(a0)
+; RV64IXCHERI-NEXT:    sext.w s3, s0
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 12
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 4
 ; RV64IXCHERI-NEXT:    j .LBB150_2
 ; RV64IXCHERI-NEXT:  .LBB150_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB150_2 Depth=1
-; RV64IXCHERI-NEXT:    csw a1, 12(csp)
-; RV64IXCHERI-NEXT:    cmove ca0, cs1
-; RV64IXCHERI-NEXT:    cmove ca1, cs0
+; RV64IXCHERI-NEXT:    csw a1, 12(sp)
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    li a3, 0
 ; RV64IXCHERI-NEXT:    li a4, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_4
-; RV64IXCHERI-NEXT:    clw a1, 12(csp)
+; RV64IXCHERI-NEXT:    clw a1, 12(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB150_4
 ; RV64IXCHERI-NEXT:  .LBB150_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -10146,21 +10146,21 @@ define i32 @atomicrmw_min_i32_monotonic(i32 addrspace(200)* %a, i32 %b) nounwind
 ; RV64IXCHERI-NEXT:    bge s3, a0, .LBB150_1
 ; RV64IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB150_2 Depth=1
-; RV64IXCHERI-NEXT:    mv a2, s2
+; RV64IXCHERI-NEXT:    mv a2, s0
 ; RV64IXCHERI-NEXT:    j .LBB150_1
 ; RV64IXCHERI-NEXT:  .LBB150_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 80(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs3, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 96
+; RV64IXCHERI-NEXT:    clc ra, 80(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s3, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 96
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_min_i32_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camomin.w a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camomin.w a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw min i32 addrspace(200)* %a, i32 %b monotonic
   ret i32 %1
@@ -10169,26 +10169,26 @@ define i32 @atomicrmw_min_i32_monotonic(i32 addrspace(200)* %a, i32 %b) nounwind
 define i32 @atomicrmw_min_i32_acquire(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_min_i32_acquire:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    mv s0, a1
-; RV32IXCHERI-NEXT:    cmove cs2, ca0
-; RV32IXCHERI-NEXT:    clw a1, 0(ca0)
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 12
-; RV32IXCHERI-NEXT:    csetbounds cs1, ca0, 4
+; RV32IXCHERI-NEXT:    cmove s1, a0
+; RV32IXCHERI-NEXT:    clw a1, 0(a0)
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 12
+; RV32IXCHERI-NEXT:    csetbounds s2, a0, 4
 ; RV32IXCHERI-NEXT:    j .LBB151_2
 ; RV32IXCHERI-NEXT:  .LBB151_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB151_2 Depth=1
-; RV32IXCHERI-NEXT:    csw a1, 12(csp)
+; RV32IXCHERI-NEXT:    csw a1, 12(sp)
 ; RV32IXCHERI-NEXT:    li a3, 2
 ; RV32IXCHERI-NEXT:    li a4, 2
-; RV32IXCHERI-NEXT:    cmove ca0, cs2
-; RV32IXCHERI-NEXT:    cmove ca1, cs1
+; RV32IXCHERI-NEXT:    cmove a0, s1
+; RV32IXCHERI-NEXT:    cmove a1, s2
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_4
-; RV32IXCHERI-NEXT:    clw a1, 12(csp)
+; RV32IXCHERI-NEXT:    clw a1, 12(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB151_4
 ; RV32IXCHERI-NEXT:  .LBB151_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -10200,42 +10200,42 @@ define i32 @atomicrmw_min_i32_acquire(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV32IXCHERI-NEXT:    j .LBB151_1
 ; RV32IXCHERI-NEXT:  .LBB151_4: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a1
-; RV32IXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_min_i32_acquire:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    camomin.w.aq a0, a1, (ca0)
+; RV32IAXCHERI-NEXT:    camomin.w.aq a0, a1, (a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_min_i32_acquire:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -96
-; RV64IXCHERI-NEXT:    csc cra, 80(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs3, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    mv s2, a1
-; RV64IXCHERI-NEXT:    cmove cs1, ca0
-; RV64IXCHERI-NEXT:    clw a1, 0(ca0)
-; RV64IXCHERI-NEXT:    sext.w s3, s2
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 12
-; RV64IXCHERI-NEXT:    csetbounds cs0, ca0, 4
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -96
+; RV64IXCHERI-NEXT:    csc ra, 80(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s3, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    mv s0, a1
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    clw a1, 0(a0)
+; RV64IXCHERI-NEXT:    sext.w s3, s0
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 12
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 4
 ; RV64IXCHERI-NEXT:    j .LBB151_2
 ; RV64IXCHERI-NEXT:  .LBB151_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB151_2 Depth=1
-; RV64IXCHERI-NEXT:    csw a1, 12(csp)
+; RV64IXCHERI-NEXT:    csw a1, 12(sp)
 ; RV64IXCHERI-NEXT:    li a3, 2
 ; RV64IXCHERI-NEXT:    li a4, 2
-; RV64IXCHERI-NEXT:    cmove ca0, cs1
-; RV64IXCHERI-NEXT:    cmove ca1, cs0
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_4
-; RV64IXCHERI-NEXT:    clw a1, 12(csp)
+; RV64IXCHERI-NEXT:    clw a1, 12(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB151_4
 ; RV64IXCHERI-NEXT:  .LBB151_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -10244,21 +10244,21 @@ define i32 @atomicrmw_min_i32_acquire(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV64IXCHERI-NEXT:    bge s3, a0, .LBB151_1
 ; RV64IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB151_2 Depth=1
-; RV64IXCHERI-NEXT:    mv a2, s2
+; RV64IXCHERI-NEXT:    mv a2, s0
 ; RV64IXCHERI-NEXT:    j .LBB151_1
 ; RV64IXCHERI-NEXT:  .LBB151_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 80(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs3, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 96
+; RV64IXCHERI-NEXT:    clc ra, 80(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s3, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 96
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_min_i32_acquire:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camomin.w.aq a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camomin.w.aq a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw min i32 addrspace(200)* %a, i32 %b acquire
   ret i32 %1
@@ -10267,26 +10267,26 @@ define i32 @atomicrmw_min_i32_acquire(i32 addrspace(200)* %a, i32 %b) nounwind {
 define i32 @atomicrmw_min_i32_release(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_min_i32_release:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    mv s0, a1
-; RV32IXCHERI-NEXT:    cmove cs2, ca0
-; RV32IXCHERI-NEXT:    clw a1, 0(ca0)
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 12
-; RV32IXCHERI-NEXT:    csetbounds cs1, ca0, 4
+; RV32IXCHERI-NEXT:    cmove s1, a0
+; RV32IXCHERI-NEXT:    clw a1, 0(a0)
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 12
+; RV32IXCHERI-NEXT:    csetbounds s2, a0, 4
 ; RV32IXCHERI-NEXT:    j .LBB152_2
 ; RV32IXCHERI-NEXT:  .LBB152_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB152_2 Depth=1
-; RV32IXCHERI-NEXT:    csw a1, 12(csp)
+; RV32IXCHERI-NEXT:    csw a1, 12(sp)
 ; RV32IXCHERI-NEXT:    li a3, 3
-; RV32IXCHERI-NEXT:    cmove ca0, cs2
-; RV32IXCHERI-NEXT:    cmove ca1, cs1
+; RV32IXCHERI-NEXT:    cmove a0, s1
+; RV32IXCHERI-NEXT:    cmove a1, s2
 ; RV32IXCHERI-NEXT:    li a4, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_4
-; RV32IXCHERI-NEXT:    clw a1, 12(csp)
+; RV32IXCHERI-NEXT:    clw a1, 12(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB152_4
 ; RV32IXCHERI-NEXT:  .LBB152_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -10298,42 +10298,42 @@ define i32 @atomicrmw_min_i32_release(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV32IXCHERI-NEXT:    j .LBB152_1
 ; RV32IXCHERI-NEXT:  .LBB152_4: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a1
-; RV32IXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_min_i32_release:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    camomin.w.rl a0, a1, (ca0)
+; RV32IAXCHERI-NEXT:    camomin.w.rl a0, a1, (a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_min_i32_release:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -96
-; RV64IXCHERI-NEXT:    csc cra, 80(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs3, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    mv s2, a1
-; RV64IXCHERI-NEXT:    cmove cs1, ca0
-; RV64IXCHERI-NEXT:    clw a1, 0(ca0)
-; RV64IXCHERI-NEXT:    sext.w s3, s2
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 12
-; RV64IXCHERI-NEXT:    csetbounds cs0, ca0, 4
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -96
+; RV64IXCHERI-NEXT:    csc ra, 80(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s3, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    mv s0, a1
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    clw a1, 0(a0)
+; RV64IXCHERI-NEXT:    sext.w s3, s0
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 12
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 4
 ; RV64IXCHERI-NEXT:    j .LBB152_2
 ; RV64IXCHERI-NEXT:  .LBB152_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB152_2 Depth=1
-; RV64IXCHERI-NEXT:    csw a1, 12(csp)
+; RV64IXCHERI-NEXT:    csw a1, 12(sp)
 ; RV64IXCHERI-NEXT:    li a3, 3
-; RV64IXCHERI-NEXT:    cmove ca0, cs1
-; RV64IXCHERI-NEXT:    cmove ca1, cs0
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    li a4, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_4
-; RV64IXCHERI-NEXT:    clw a1, 12(csp)
+; RV64IXCHERI-NEXT:    clw a1, 12(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB152_4
 ; RV64IXCHERI-NEXT:  .LBB152_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -10342,21 +10342,21 @@ define i32 @atomicrmw_min_i32_release(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV64IXCHERI-NEXT:    bge s3, a0, .LBB152_1
 ; RV64IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB152_2 Depth=1
-; RV64IXCHERI-NEXT:    mv a2, s2
+; RV64IXCHERI-NEXT:    mv a2, s0
 ; RV64IXCHERI-NEXT:    j .LBB152_1
 ; RV64IXCHERI-NEXT:  .LBB152_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 80(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs3, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 96
+; RV64IXCHERI-NEXT:    clc ra, 80(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s3, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 96
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_min_i32_release:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camomin.w.rl a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camomin.w.rl a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw min i32 addrspace(200)* %a, i32 %b release
   ret i32 %1
@@ -10365,26 +10365,26 @@ define i32 @atomicrmw_min_i32_release(i32 addrspace(200)* %a, i32 %b) nounwind {
 define i32 @atomicrmw_min_i32_acq_rel(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_min_i32_acq_rel:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    mv s0, a1
-; RV32IXCHERI-NEXT:    cmove cs2, ca0
-; RV32IXCHERI-NEXT:    clw a1, 0(ca0)
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 12
-; RV32IXCHERI-NEXT:    csetbounds cs1, ca0, 4
+; RV32IXCHERI-NEXT:    cmove s1, a0
+; RV32IXCHERI-NEXT:    clw a1, 0(a0)
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 12
+; RV32IXCHERI-NEXT:    csetbounds s2, a0, 4
 ; RV32IXCHERI-NEXT:    j .LBB153_2
 ; RV32IXCHERI-NEXT:  .LBB153_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB153_2 Depth=1
-; RV32IXCHERI-NEXT:    csw a1, 12(csp)
+; RV32IXCHERI-NEXT:    csw a1, 12(sp)
 ; RV32IXCHERI-NEXT:    li a3, 4
 ; RV32IXCHERI-NEXT:    li a4, 2
-; RV32IXCHERI-NEXT:    cmove ca0, cs2
-; RV32IXCHERI-NEXT:    cmove ca1, cs1
+; RV32IXCHERI-NEXT:    cmove a0, s1
+; RV32IXCHERI-NEXT:    cmove a1, s2
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_4
-; RV32IXCHERI-NEXT:    clw a1, 12(csp)
+; RV32IXCHERI-NEXT:    clw a1, 12(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB153_4
 ; RV32IXCHERI-NEXT:  .LBB153_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -10396,42 +10396,42 @@ define i32 @atomicrmw_min_i32_acq_rel(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV32IXCHERI-NEXT:    j .LBB153_1
 ; RV32IXCHERI-NEXT:  .LBB153_4: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a1
-; RV32IXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_min_i32_acq_rel:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    camomin.w.aqrl a0, a1, (ca0)
+; RV32IAXCHERI-NEXT:    camomin.w.aqrl a0, a1, (a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_min_i32_acq_rel:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -96
-; RV64IXCHERI-NEXT:    csc cra, 80(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs3, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    mv s2, a1
-; RV64IXCHERI-NEXT:    cmove cs1, ca0
-; RV64IXCHERI-NEXT:    clw a1, 0(ca0)
-; RV64IXCHERI-NEXT:    sext.w s3, s2
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 12
-; RV64IXCHERI-NEXT:    csetbounds cs0, ca0, 4
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -96
+; RV64IXCHERI-NEXT:    csc ra, 80(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s3, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    mv s0, a1
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    clw a1, 0(a0)
+; RV64IXCHERI-NEXT:    sext.w s3, s0
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 12
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 4
 ; RV64IXCHERI-NEXT:    j .LBB153_2
 ; RV64IXCHERI-NEXT:  .LBB153_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB153_2 Depth=1
-; RV64IXCHERI-NEXT:    csw a1, 12(csp)
+; RV64IXCHERI-NEXT:    csw a1, 12(sp)
 ; RV64IXCHERI-NEXT:    li a3, 4
 ; RV64IXCHERI-NEXT:    li a4, 2
-; RV64IXCHERI-NEXT:    cmove ca0, cs1
-; RV64IXCHERI-NEXT:    cmove ca1, cs0
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_4
-; RV64IXCHERI-NEXT:    clw a1, 12(csp)
+; RV64IXCHERI-NEXT:    clw a1, 12(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB153_4
 ; RV64IXCHERI-NEXT:  .LBB153_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -10440,21 +10440,21 @@ define i32 @atomicrmw_min_i32_acq_rel(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV64IXCHERI-NEXT:    bge s3, a0, .LBB153_1
 ; RV64IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB153_2 Depth=1
-; RV64IXCHERI-NEXT:    mv a2, s2
+; RV64IXCHERI-NEXT:    mv a2, s0
 ; RV64IXCHERI-NEXT:    j .LBB153_1
 ; RV64IXCHERI-NEXT:  .LBB153_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 80(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs3, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 96
+; RV64IXCHERI-NEXT:    clc ra, 80(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s3, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 96
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_min_i32_acq_rel:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camomin.w.aqrl a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camomin.w.aqrl a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw min i32 addrspace(200)* %a, i32 %b acq_rel
   ret i32 %1
@@ -10463,26 +10463,26 @@ define i32 @atomicrmw_min_i32_acq_rel(i32 addrspace(200)* %a, i32 %b) nounwind {
 define i32 @atomicrmw_min_i32_seq_cst(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_min_i32_seq_cst:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    mv s0, a1
-; RV32IXCHERI-NEXT:    cmove cs2, ca0
-; RV32IXCHERI-NEXT:    clw a1, 0(ca0)
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 12
-; RV32IXCHERI-NEXT:    csetbounds cs1, ca0, 4
+; RV32IXCHERI-NEXT:    cmove s1, a0
+; RV32IXCHERI-NEXT:    clw a1, 0(a0)
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 12
+; RV32IXCHERI-NEXT:    csetbounds s2, a0, 4
 ; RV32IXCHERI-NEXT:    j .LBB154_2
 ; RV32IXCHERI-NEXT:  .LBB154_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB154_2 Depth=1
-; RV32IXCHERI-NEXT:    csw a1, 12(csp)
+; RV32IXCHERI-NEXT:    csw a1, 12(sp)
 ; RV32IXCHERI-NEXT:    li a3, 5
 ; RV32IXCHERI-NEXT:    li a4, 5
-; RV32IXCHERI-NEXT:    cmove ca0, cs2
-; RV32IXCHERI-NEXT:    cmove ca1, cs1
+; RV32IXCHERI-NEXT:    cmove a0, s1
+; RV32IXCHERI-NEXT:    cmove a1, s2
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_4
-; RV32IXCHERI-NEXT:    clw a1, 12(csp)
+; RV32IXCHERI-NEXT:    clw a1, 12(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB154_4
 ; RV32IXCHERI-NEXT:  .LBB154_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -10494,42 +10494,42 @@ define i32 @atomicrmw_min_i32_seq_cst(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV32IXCHERI-NEXT:    j .LBB154_1
 ; RV32IXCHERI-NEXT:  .LBB154_4: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a1
-; RV32IXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_min_i32_seq_cst:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    camomin.w.aqrl a0, a1, (ca0)
+; RV32IAXCHERI-NEXT:    camomin.w.aqrl a0, a1, (a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_min_i32_seq_cst:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -96
-; RV64IXCHERI-NEXT:    csc cra, 80(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs3, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    mv s2, a1
-; RV64IXCHERI-NEXT:    cmove cs1, ca0
-; RV64IXCHERI-NEXT:    clw a1, 0(ca0)
-; RV64IXCHERI-NEXT:    sext.w s3, s2
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 12
-; RV64IXCHERI-NEXT:    csetbounds cs0, ca0, 4
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -96
+; RV64IXCHERI-NEXT:    csc ra, 80(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s3, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    mv s0, a1
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    clw a1, 0(a0)
+; RV64IXCHERI-NEXT:    sext.w s3, s0
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 12
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 4
 ; RV64IXCHERI-NEXT:    j .LBB154_2
 ; RV64IXCHERI-NEXT:  .LBB154_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB154_2 Depth=1
-; RV64IXCHERI-NEXT:    csw a1, 12(csp)
+; RV64IXCHERI-NEXT:    csw a1, 12(sp)
 ; RV64IXCHERI-NEXT:    li a3, 5
 ; RV64IXCHERI-NEXT:    li a4, 5
-; RV64IXCHERI-NEXT:    cmove ca0, cs1
-; RV64IXCHERI-NEXT:    cmove ca1, cs0
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_4
-; RV64IXCHERI-NEXT:    clw a1, 12(csp)
+; RV64IXCHERI-NEXT:    clw a1, 12(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB154_4
 ; RV64IXCHERI-NEXT:  .LBB154_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -10538,21 +10538,21 @@ define i32 @atomicrmw_min_i32_seq_cst(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV64IXCHERI-NEXT:    bge s3, a0, .LBB154_1
 ; RV64IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB154_2 Depth=1
-; RV64IXCHERI-NEXT:    mv a2, s2
+; RV64IXCHERI-NEXT:    mv a2, s0
 ; RV64IXCHERI-NEXT:    j .LBB154_1
 ; RV64IXCHERI-NEXT:  .LBB154_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 80(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs3, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 96
+; RV64IXCHERI-NEXT:    clc ra, 80(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s3, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 96
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_min_i32_seq_cst:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camomin.w.aqrl a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camomin.w.aqrl a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw min i32 addrspace(200)* %a, i32 %b seq_cst
   ret i32 %1
@@ -10561,26 +10561,26 @@ define i32 @atomicrmw_min_i32_seq_cst(i32 addrspace(200)* %a, i32 %b) nounwind {
 define i32 @atomicrmw_umax_i32_monotonic(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_umax_i32_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    mv s0, a1
-; RV32IXCHERI-NEXT:    cmove cs2, ca0
-; RV32IXCHERI-NEXT:    clw a1, 0(ca0)
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 12
-; RV32IXCHERI-NEXT:    csetbounds cs1, ca0, 4
+; RV32IXCHERI-NEXT:    cmove s1, a0
+; RV32IXCHERI-NEXT:    clw a1, 0(a0)
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 12
+; RV32IXCHERI-NEXT:    csetbounds s2, a0, 4
 ; RV32IXCHERI-NEXT:    j .LBB155_2
 ; RV32IXCHERI-NEXT:  .LBB155_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB155_2 Depth=1
-; RV32IXCHERI-NEXT:    csw a1, 12(csp)
-; RV32IXCHERI-NEXT:    cmove ca0, cs2
-; RV32IXCHERI-NEXT:    cmove ca1, cs1
+; RV32IXCHERI-NEXT:    csw a1, 12(sp)
+; RV32IXCHERI-NEXT:    cmove a0, s1
+; RV32IXCHERI-NEXT:    cmove a1, s2
 ; RV32IXCHERI-NEXT:    li a3, 0
 ; RV32IXCHERI-NEXT:    li a4, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_4
-; RV32IXCHERI-NEXT:    clw a1, 12(csp)
+; RV32IXCHERI-NEXT:    clw a1, 12(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB155_4
 ; RV32IXCHERI-NEXT:  .LBB155_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -10592,42 +10592,42 @@ define i32 @atomicrmw_umax_i32_monotonic(i32 addrspace(200)* %a, i32 %b) nounwin
 ; RV32IXCHERI-NEXT:    j .LBB155_1
 ; RV32IXCHERI-NEXT:  .LBB155_4: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a1
-; RV32IXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_umax_i32_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    camomaxu.w a0, a1, (ca0)
+; RV32IAXCHERI-NEXT:    camomaxu.w a0, a1, (a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_umax_i32_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -96
-; RV64IXCHERI-NEXT:    csc cra, 80(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs3, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    mv s2, a1
-; RV64IXCHERI-NEXT:    cmove cs1, ca0
-; RV64IXCHERI-NEXT:    clw a1, 0(ca0)
-; RV64IXCHERI-NEXT:    sext.w s3, s2
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 12
-; RV64IXCHERI-NEXT:    csetbounds cs0, ca0, 4
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -96
+; RV64IXCHERI-NEXT:    csc ra, 80(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s3, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    mv s0, a1
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    clw a1, 0(a0)
+; RV64IXCHERI-NEXT:    sext.w s3, s0
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 12
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 4
 ; RV64IXCHERI-NEXT:    j .LBB155_2
 ; RV64IXCHERI-NEXT:  .LBB155_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB155_2 Depth=1
-; RV64IXCHERI-NEXT:    csw a1, 12(csp)
-; RV64IXCHERI-NEXT:    cmove ca0, cs1
-; RV64IXCHERI-NEXT:    cmove ca1, cs0
+; RV64IXCHERI-NEXT:    csw a1, 12(sp)
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    li a3, 0
 ; RV64IXCHERI-NEXT:    li a4, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_4
-; RV64IXCHERI-NEXT:    clw a1, 12(csp)
+; RV64IXCHERI-NEXT:    clw a1, 12(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB155_4
 ; RV64IXCHERI-NEXT:  .LBB155_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -10636,21 +10636,21 @@ define i32 @atomicrmw_umax_i32_monotonic(i32 addrspace(200)* %a, i32 %b) nounwin
 ; RV64IXCHERI-NEXT:    bltu s3, a0, .LBB155_1
 ; RV64IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB155_2 Depth=1
-; RV64IXCHERI-NEXT:    mv a2, s2
+; RV64IXCHERI-NEXT:    mv a2, s0
 ; RV64IXCHERI-NEXT:    j .LBB155_1
 ; RV64IXCHERI-NEXT:  .LBB155_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 80(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs3, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 96
+; RV64IXCHERI-NEXT:    clc ra, 80(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s3, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 96
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_umax_i32_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camomaxu.w a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camomaxu.w a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw umax i32 addrspace(200)* %a, i32 %b monotonic
   ret i32 %1
@@ -10659,26 +10659,26 @@ define i32 @atomicrmw_umax_i32_monotonic(i32 addrspace(200)* %a, i32 %b) nounwin
 define i32 @atomicrmw_umax_i32_acquire(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_umax_i32_acquire:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    mv s0, a1
-; RV32IXCHERI-NEXT:    cmove cs2, ca0
-; RV32IXCHERI-NEXT:    clw a1, 0(ca0)
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 12
-; RV32IXCHERI-NEXT:    csetbounds cs1, ca0, 4
+; RV32IXCHERI-NEXT:    cmove s1, a0
+; RV32IXCHERI-NEXT:    clw a1, 0(a0)
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 12
+; RV32IXCHERI-NEXT:    csetbounds s2, a0, 4
 ; RV32IXCHERI-NEXT:    j .LBB156_2
 ; RV32IXCHERI-NEXT:  .LBB156_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB156_2 Depth=1
-; RV32IXCHERI-NEXT:    csw a1, 12(csp)
+; RV32IXCHERI-NEXT:    csw a1, 12(sp)
 ; RV32IXCHERI-NEXT:    li a3, 2
 ; RV32IXCHERI-NEXT:    li a4, 2
-; RV32IXCHERI-NEXT:    cmove ca0, cs2
-; RV32IXCHERI-NEXT:    cmove ca1, cs1
+; RV32IXCHERI-NEXT:    cmove a0, s1
+; RV32IXCHERI-NEXT:    cmove a1, s2
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_4
-; RV32IXCHERI-NEXT:    clw a1, 12(csp)
+; RV32IXCHERI-NEXT:    clw a1, 12(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB156_4
 ; RV32IXCHERI-NEXT:  .LBB156_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -10690,42 +10690,42 @@ define i32 @atomicrmw_umax_i32_acquire(i32 addrspace(200)* %a, i32 %b) nounwind
 ; RV32IXCHERI-NEXT:    j .LBB156_1
 ; RV32IXCHERI-NEXT:  .LBB156_4: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a1
-; RV32IXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_umax_i32_acquire:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    camomaxu.w.aq a0, a1, (ca0)
+; RV32IAXCHERI-NEXT:    camomaxu.w.aq a0, a1, (a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_umax_i32_acquire:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -96
-; RV64IXCHERI-NEXT:    csc cra, 80(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs3, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    mv s2, a1
-; RV64IXCHERI-NEXT:    cmove cs1, ca0
-; RV64IXCHERI-NEXT:    clw a1, 0(ca0)
-; RV64IXCHERI-NEXT:    sext.w s3, s2
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 12
-; RV64IXCHERI-NEXT:    csetbounds cs0, ca0, 4
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -96
+; RV64IXCHERI-NEXT:    csc ra, 80(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s3, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    mv s0, a1
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    clw a1, 0(a0)
+; RV64IXCHERI-NEXT:    sext.w s3, s0
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 12
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 4
 ; RV64IXCHERI-NEXT:    j .LBB156_2
 ; RV64IXCHERI-NEXT:  .LBB156_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB156_2 Depth=1
-; RV64IXCHERI-NEXT:    csw a1, 12(csp)
+; RV64IXCHERI-NEXT:    csw a1, 12(sp)
 ; RV64IXCHERI-NEXT:    li a3, 2
 ; RV64IXCHERI-NEXT:    li a4, 2
-; RV64IXCHERI-NEXT:    cmove ca0, cs1
-; RV64IXCHERI-NEXT:    cmove ca1, cs0
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_4
-; RV64IXCHERI-NEXT:    clw a1, 12(csp)
+; RV64IXCHERI-NEXT:    clw a1, 12(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB156_4
 ; RV64IXCHERI-NEXT:  .LBB156_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -10734,21 +10734,21 @@ define i32 @atomicrmw_umax_i32_acquire(i32 addrspace(200)* %a, i32 %b) nounwind
 ; RV64IXCHERI-NEXT:    bltu s3, a0, .LBB156_1
 ; RV64IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB156_2 Depth=1
-; RV64IXCHERI-NEXT:    mv a2, s2
+; RV64IXCHERI-NEXT:    mv a2, s0
 ; RV64IXCHERI-NEXT:    j .LBB156_1
 ; RV64IXCHERI-NEXT:  .LBB156_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 80(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs3, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 96
+; RV64IXCHERI-NEXT:    clc ra, 80(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s3, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 96
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_umax_i32_acquire:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camomaxu.w.aq a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camomaxu.w.aq a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw umax i32 addrspace(200)* %a, i32 %b acquire
   ret i32 %1
@@ -10757,26 +10757,26 @@ define i32 @atomicrmw_umax_i32_acquire(i32 addrspace(200)* %a, i32 %b) nounwind
 define i32 @atomicrmw_umax_i32_release(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_umax_i32_release:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    mv s0, a1
-; RV32IXCHERI-NEXT:    cmove cs2, ca0
-; RV32IXCHERI-NEXT:    clw a1, 0(ca0)
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 12
-; RV32IXCHERI-NEXT:    csetbounds cs1, ca0, 4
+; RV32IXCHERI-NEXT:    cmove s1, a0
+; RV32IXCHERI-NEXT:    clw a1, 0(a0)
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 12
+; RV32IXCHERI-NEXT:    csetbounds s2, a0, 4
 ; RV32IXCHERI-NEXT:    j .LBB157_2
 ; RV32IXCHERI-NEXT:  .LBB157_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB157_2 Depth=1
-; RV32IXCHERI-NEXT:    csw a1, 12(csp)
+; RV32IXCHERI-NEXT:    csw a1, 12(sp)
 ; RV32IXCHERI-NEXT:    li a3, 3
-; RV32IXCHERI-NEXT:    cmove ca0, cs2
-; RV32IXCHERI-NEXT:    cmove ca1, cs1
+; RV32IXCHERI-NEXT:    cmove a0, s1
+; RV32IXCHERI-NEXT:    cmove a1, s2
 ; RV32IXCHERI-NEXT:    li a4, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_4
-; RV32IXCHERI-NEXT:    clw a1, 12(csp)
+; RV32IXCHERI-NEXT:    clw a1, 12(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB157_4
 ; RV32IXCHERI-NEXT:  .LBB157_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -10788,42 +10788,42 @@ define i32 @atomicrmw_umax_i32_release(i32 addrspace(200)* %a, i32 %b) nounwind
 ; RV32IXCHERI-NEXT:    j .LBB157_1
 ; RV32IXCHERI-NEXT:  .LBB157_4: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a1
-; RV32IXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_umax_i32_release:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    camomaxu.w.rl a0, a1, (ca0)
+; RV32IAXCHERI-NEXT:    camomaxu.w.rl a0, a1, (a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_umax_i32_release:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -96
-; RV64IXCHERI-NEXT:    csc cra, 80(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs3, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    mv s2, a1
-; RV64IXCHERI-NEXT:    cmove cs1, ca0
-; RV64IXCHERI-NEXT:    clw a1, 0(ca0)
-; RV64IXCHERI-NEXT:    sext.w s3, s2
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 12
-; RV64IXCHERI-NEXT:    csetbounds cs0, ca0, 4
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -96
+; RV64IXCHERI-NEXT:    csc ra, 80(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s3, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    mv s0, a1
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    clw a1, 0(a0)
+; RV64IXCHERI-NEXT:    sext.w s3, s0
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 12
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 4
 ; RV64IXCHERI-NEXT:    j .LBB157_2
 ; RV64IXCHERI-NEXT:  .LBB157_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB157_2 Depth=1
-; RV64IXCHERI-NEXT:    csw a1, 12(csp)
+; RV64IXCHERI-NEXT:    csw a1, 12(sp)
 ; RV64IXCHERI-NEXT:    li a3, 3
-; RV64IXCHERI-NEXT:    cmove ca0, cs1
-; RV64IXCHERI-NEXT:    cmove ca1, cs0
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    li a4, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_4
-; RV64IXCHERI-NEXT:    clw a1, 12(csp)
+; RV64IXCHERI-NEXT:    clw a1, 12(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB157_4
 ; RV64IXCHERI-NEXT:  .LBB157_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -10832,21 +10832,21 @@ define i32 @atomicrmw_umax_i32_release(i32 addrspace(200)* %a, i32 %b) nounwind
 ; RV64IXCHERI-NEXT:    bltu s3, a0, .LBB157_1
 ; RV64IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB157_2 Depth=1
-; RV64IXCHERI-NEXT:    mv a2, s2
+; RV64IXCHERI-NEXT:    mv a2, s0
 ; RV64IXCHERI-NEXT:    j .LBB157_1
 ; RV64IXCHERI-NEXT:  .LBB157_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 80(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs3, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 96
+; RV64IXCHERI-NEXT:    clc ra, 80(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s3, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 96
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_umax_i32_release:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camomaxu.w.rl a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camomaxu.w.rl a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw umax i32 addrspace(200)* %a, i32 %b release
   ret i32 %1
@@ -10855,26 +10855,26 @@ define i32 @atomicrmw_umax_i32_release(i32 addrspace(200)* %a, i32 %b) nounwind
 define i32 @atomicrmw_umax_i32_acq_rel(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_umax_i32_acq_rel:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    mv s0, a1
-; RV32IXCHERI-NEXT:    cmove cs2, ca0
-; RV32IXCHERI-NEXT:    clw a1, 0(ca0)
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 12
-; RV32IXCHERI-NEXT:    csetbounds cs1, ca0, 4
+; RV32IXCHERI-NEXT:    cmove s1, a0
+; RV32IXCHERI-NEXT:    clw a1, 0(a0)
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 12
+; RV32IXCHERI-NEXT:    csetbounds s2, a0, 4
 ; RV32IXCHERI-NEXT:    j .LBB158_2
 ; RV32IXCHERI-NEXT:  .LBB158_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB158_2 Depth=1
-; RV32IXCHERI-NEXT:    csw a1, 12(csp)
+; RV32IXCHERI-NEXT:    csw a1, 12(sp)
 ; RV32IXCHERI-NEXT:    li a3, 4
 ; RV32IXCHERI-NEXT:    li a4, 2
-; RV32IXCHERI-NEXT:    cmove ca0, cs2
-; RV32IXCHERI-NEXT:    cmove ca1, cs1
+; RV32IXCHERI-NEXT:    cmove a0, s1
+; RV32IXCHERI-NEXT:    cmove a1, s2
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_4
-; RV32IXCHERI-NEXT:    clw a1, 12(csp)
+; RV32IXCHERI-NEXT:    clw a1, 12(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB158_4
 ; RV32IXCHERI-NEXT:  .LBB158_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -10886,42 +10886,42 @@ define i32 @atomicrmw_umax_i32_acq_rel(i32 addrspace(200)* %a, i32 %b) nounwind
 ; RV32IXCHERI-NEXT:    j .LBB158_1
 ; RV32IXCHERI-NEXT:  .LBB158_4: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a1
-; RV32IXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_umax_i32_acq_rel:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    camomaxu.w.aqrl a0, a1, (ca0)
+; RV32IAXCHERI-NEXT:    camomaxu.w.aqrl a0, a1, (a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_umax_i32_acq_rel:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -96
-; RV64IXCHERI-NEXT:    csc cra, 80(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs3, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    mv s2, a1
-; RV64IXCHERI-NEXT:    cmove cs1, ca0
-; RV64IXCHERI-NEXT:    clw a1, 0(ca0)
-; RV64IXCHERI-NEXT:    sext.w s3, s2
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 12
-; RV64IXCHERI-NEXT:    csetbounds cs0, ca0, 4
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -96
+; RV64IXCHERI-NEXT:    csc ra, 80(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s3, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    mv s0, a1
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    clw a1, 0(a0)
+; RV64IXCHERI-NEXT:    sext.w s3, s0
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 12
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 4
 ; RV64IXCHERI-NEXT:    j .LBB158_2
 ; RV64IXCHERI-NEXT:  .LBB158_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB158_2 Depth=1
-; RV64IXCHERI-NEXT:    csw a1, 12(csp)
+; RV64IXCHERI-NEXT:    csw a1, 12(sp)
 ; RV64IXCHERI-NEXT:    li a3, 4
 ; RV64IXCHERI-NEXT:    li a4, 2
-; RV64IXCHERI-NEXT:    cmove ca0, cs1
-; RV64IXCHERI-NEXT:    cmove ca1, cs0
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_4
-; RV64IXCHERI-NEXT:    clw a1, 12(csp)
+; RV64IXCHERI-NEXT:    clw a1, 12(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB158_4
 ; RV64IXCHERI-NEXT:  .LBB158_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -10930,21 +10930,21 @@ define i32 @atomicrmw_umax_i32_acq_rel(i32 addrspace(200)* %a, i32 %b) nounwind
 ; RV64IXCHERI-NEXT:    bltu s3, a0, .LBB158_1
 ; RV64IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB158_2 Depth=1
-; RV64IXCHERI-NEXT:    mv a2, s2
+; RV64IXCHERI-NEXT:    mv a2, s0
 ; RV64IXCHERI-NEXT:    j .LBB158_1
 ; RV64IXCHERI-NEXT:  .LBB158_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 80(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs3, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 96
+; RV64IXCHERI-NEXT:    clc ra, 80(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s3, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 96
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_umax_i32_acq_rel:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camomaxu.w.aqrl a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camomaxu.w.aqrl a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw umax i32 addrspace(200)* %a, i32 %b acq_rel
   ret i32 %1
@@ -10953,26 +10953,26 @@ define i32 @atomicrmw_umax_i32_acq_rel(i32 addrspace(200)* %a, i32 %b) nounwind
 define i32 @atomicrmw_umax_i32_seq_cst(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_umax_i32_seq_cst:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    mv s0, a1
-; RV32IXCHERI-NEXT:    cmove cs2, ca0
-; RV32IXCHERI-NEXT:    clw a1, 0(ca0)
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 12
-; RV32IXCHERI-NEXT:    csetbounds cs1, ca0, 4
+; RV32IXCHERI-NEXT:    cmove s1, a0
+; RV32IXCHERI-NEXT:    clw a1, 0(a0)
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 12
+; RV32IXCHERI-NEXT:    csetbounds s2, a0, 4
 ; RV32IXCHERI-NEXT:    j .LBB159_2
 ; RV32IXCHERI-NEXT:  .LBB159_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB159_2 Depth=1
-; RV32IXCHERI-NEXT:    csw a1, 12(csp)
+; RV32IXCHERI-NEXT:    csw a1, 12(sp)
 ; RV32IXCHERI-NEXT:    li a3, 5
 ; RV32IXCHERI-NEXT:    li a4, 5
-; RV32IXCHERI-NEXT:    cmove ca0, cs2
-; RV32IXCHERI-NEXT:    cmove ca1, cs1
+; RV32IXCHERI-NEXT:    cmove a0, s1
+; RV32IXCHERI-NEXT:    cmove a1, s2
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_4
-; RV32IXCHERI-NEXT:    clw a1, 12(csp)
+; RV32IXCHERI-NEXT:    clw a1, 12(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB159_4
 ; RV32IXCHERI-NEXT:  .LBB159_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -10984,42 +10984,42 @@ define i32 @atomicrmw_umax_i32_seq_cst(i32 addrspace(200)* %a, i32 %b) nounwind
 ; RV32IXCHERI-NEXT:    j .LBB159_1
 ; RV32IXCHERI-NEXT:  .LBB159_4: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a1
-; RV32IXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_umax_i32_seq_cst:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    camomaxu.w.aqrl a0, a1, (ca0)
+; RV32IAXCHERI-NEXT:    camomaxu.w.aqrl a0, a1, (a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_umax_i32_seq_cst:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -96
-; RV64IXCHERI-NEXT:    csc cra, 80(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs3, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    mv s2, a1
-; RV64IXCHERI-NEXT:    cmove cs1, ca0
-; RV64IXCHERI-NEXT:    clw a1, 0(ca0)
-; RV64IXCHERI-NEXT:    sext.w s3, s2
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 12
-; RV64IXCHERI-NEXT:    csetbounds cs0, ca0, 4
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -96
+; RV64IXCHERI-NEXT:    csc ra, 80(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s3, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    mv s0, a1
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    clw a1, 0(a0)
+; RV64IXCHERI-NEXT:    sext.w s3, s0
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 12
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 4
 ; RV64IXCHERI-NEXT:    j .LBB159_2
 ; RV64IXCHERI-NEXT:  .LBB159_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB159_2 Depth=1
-; RV64IXCHERI-NEXT:    csw a1, 12(csp)
+; RV64IXCHERI-NEXT:    csw a1, 12(sp)
 ; RV64IXCHERI-NEXT:    li a3, 5
 ; RV64IXCHERI-NEXT:    li a4, 5
-; RV64IXCHERI-NEXT:    cmove ca0, cs1
-; RV64IXCHERI-NEXT:    cmove ca1, cs0
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_4
-; RV64IXCHERI-NEXT:    clw a1, 12(csp)
+; RV64IXCHERI-NEXT:    clw a1, 12(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB159_4
 ; RV64IXCHERI-NEXT:  .LBB159_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -11028,21 +11028,21 @@ define i32 @atomicrmw_umax_i32_seq_cst(i32 addrspace(200)* %a, i32 %b) nounwind
 ; RV64IXCHERI-NEXT:    bltu s3, a0, .LBB159_1
 ; RV64IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB159_2 Depth=1
-; RV64IXCHERI-NEXT:    mv a2, s2
+; RV64IXCHERI-NEXT:    mv a2, s0
 ; RV64IXCHERI-NEXT:    j .LBB159_1
 ; RV64IXCHERI-NEXT:  .LBB159_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 80(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs3, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 96
+; RV64IXCHERI-NEXT:    clc ra, 80(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s3, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 96
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_umax_i32_seq_cst:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camomaxu.w.aqrl a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camomaxu.w.aqrl a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw umax i32 addrspace(200)* %a, i32 %b seq_cst
   ret i32 %1
@@ -11051,26 +11051,26 @@ define i32 @atomicrmw_umax_i32_seq_cst(i32 addrspace(200)* %a, i32 %b) nounwind
 define i32 @atomicrmw_umin_i32_monotonic(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_umin_i32_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    mv s0, a1
-; RV32IXCHERI-NEXT:    cmove cs2, ca0
-; RV32IXCHERI-NEXT:    clw a1, 0(ca0)
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 12
-; RV32IXCHERI-NEXT:    csetbounds cs1, ca0, 4
+; RV32IXCHERI-NEXT:    cmove s1, a0
+; RV32IXCHERI-NEXT:    clw a1, 0(a0)
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 12
+; RV32IXCHERI-NEXT:    csetbounds s2, a0, 4
 ; RV32IXCHERI-NEXT:    j .LBB160_2
 ; RV32IXCHERI-NEXT:  .LBB160_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB160_2 Depth=1
-; RV32IXCHERI-NEXT:    csw a1, 12(csp)
-; RV32IXCHERI-NEXT:    cmove ca0, cs2
-; RV32IXCHERI-NEXT:    cmove ca1, cs1
+; RV32IXCHERI-NEXT:    csw a1, 12(sp)
+; RV32IXCHERI-NEXT:    cmove a0, s1
+; RV32IXCHERI-NEXT:    cmove a1, s2
 ; RV32IXCHERI-NEXT:    li a3, 0
 ; RV32IXCHERI-NEXT:    li a4, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_4
-; RV32IXCHERI-NEXT:    clw a1, 12(csp)
+; RV32IXCHERI-NEXT:    clw a1, 12(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB160_4
 ; RV32IXCHERI-NEXT:  .LBB160_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -11082,42 +11082,42 @@ define i32 @atomicrmw_umin_i32_monotonic(i32 addrspace(200)* %a, i32 %b) nounwin
 ; RV32IXCHERI-NEXT:    j .LBB160_1
 ; RV32IXCHERI-NEXT:  .LBB160_4: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a1
-; RV32IXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_umin_i32_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    camominu.w a0, a1, (ca0)
+; RV32IAXCHERI-NEXT:    camominu.w a0, a1, (a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_umin_i32_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -96
-; RV64IXCHERI-NEXT:    csc cra, 80(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs3, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    mv s2, a1
-; RV64IXCHERI-NEXT:    cmove cs1, ca0
-; RV64IXCHERI-NEXT:    clw a1, 0(ca0)
-; RV64IXCHERI-NEXT:    sext.w s3, s2
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 12
-; RV64IXCHERI-NEXT:    csetbounds cs0, ca0, 4
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -96
+; RV64IXCHERI-NEXT:    csc ra, 80(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s3, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    mv s0, a1
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    clw a1, 0(a0)
+; RV64IXCHERI-NEXT:    sext.w s3, s0
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 12
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 4
 ; RV64IXCHERI-NEXT:    j .LBB160_2
 ; RV64IXCHERI-NEXT:  .LBB160_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB160_2 Depth=1
-; RV64IXCHERI-NEXT:    csw a1, 12(csp)
-; RV64IXCHERI-NEXT:    cmove ca0, cs1
-; RV64IXCHERI-NEXT:    cmove ca1, cs0
+; RV64IXCHERI-NEXT:    csw a1, 12(sp)
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    li a3, 0
 ; RV64IXCHERI-NEXT:    li a4, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_4
-; RV64IXCHERI-NEXT:    clw a1, 12(csp)
+; RV64IXCHERI-NEXT:    clw a1, 12(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB160_4
 ; RV64IXCHERI-NEXT:  .LBB160_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -11126,21 +11126,21 @@ define i32 @atomicrmw_umin_i32_monotonic(i32 addrspace(200)* %a, i32 %b) nounwin
 ; RV64IXCHERI-NEXT:    bgeu s3, a0, .LBB160_1
 ; RV64IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB160_2 Depth=1
-; RV64IXCHERI-NEXT:    mv a2, s2
+; RV64IXCHERI-NEXT:    mv a2, s0
 ; RV64IXCHERI-NEXT:    j .LBB160_1
 ; RV64IXCHERI-NEXT:  .LBB160_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 80(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs3, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 96
+; RV64IXCHERI-NEXT:    clc ra, 80(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s3, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 96
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_umin_i32_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camominu.w a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camominu.w a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw umin i32 addrspace(200)* %a, i32 %b monotonic
   ret i32 %1
@@ -11149,26 +11149,26 @@ define i32 @atomicrmw_umin_i32_monotonic(i32 addrspace(200)* %a, i32 %b) nounwin
 define i32 @atomicrmw_umin_i32_acquire(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_umin_i32_acquire:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    mv s0, a1
-; RV32IXCHERI-NEXT:    cmove cs2, ca0
-; RV32IXCHERI-NEXT:    clw a1, 0(ca0)
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 12
-; RV32IXCHERI-NEXT:    csetbounds cs1, ca0, 4
+; RV32IXCHERI-NEXT:    cmove s1, a0
+; RV32IXCHERI-NEXT:    clw a1, 0(a0)
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 12
+; RV32IXCHERI-NEXT:    csetbounds s2, a0, 4
 ; RV32IXCHERI-NEXT:    j .LBB161_2
 ; RV32IXCHERI-NEXT:  .LBB161_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB161_2 Depth=1
-; RV32IXCHERI-NEXT:    csw a1, 12(csp)
+; RV32IXCHERI-NEXT:    csw a1, 12(sp)
 ; RV32IXCHERI-NEXT:    li a3, 2
 ; RV32IXCHERI-NEXT:    li a4, 2
-; RV32IXCHERI-NEXT:    cmove ca0, cs2
-; RV32IXCHERI-NEXT:    cmove ca1, cs1
+; RV32IXCHERI-NEXT:    cmove a0, s1
+; RV32IXCHERI-NEXT:    cmove a1, s2
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_4
-; RV32IXCHERI-NEXT:    clw a1, 12(csp)
+; RV32IXCHERI-NEXT:    clw a1, 12(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB161_4
 ; RV32IXCHERI-NEXT:  .LBB161_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -11180,42 +11180,42 @@ define i32 @atomicrmw_umin_i32_acquire(i32 addrspace(200)* %a, i32 %b) nounwind
 ; RV32IXCHERI-NEXT:    j .LBB161_1
 ; RV32IXCHERI-NEXT:  .LBB161_4: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a1
-; RV32IXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_umin_i32_acquire:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    camominu.w.aq a0, a1, (ca0)
+; RV32IAXCHERI-NEXT:    camominu.w.aq a0, a1, (a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_umin_i32_acquire:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -96
-; RV64IXCHERI-NEXT:    csc cra, 80(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs3, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    mv s2, a1
-; RV64IXCHERI-NEXT:    cmove cs1, ca0
-; RV64IXCHERI-NEXT:    clw a1, 0(ca0)
-; RV64IXCHERI-NEXT:    sext.w s3, s2
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 12
-; RV64IXCHERI-NEXT:    csetbounds cs0, ca0, 4
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -96
+; RV64IXCHERI-NEXT:    csc ra, 80(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s3, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    mv s0, a1
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    clw a1, 0(a0)
+; RV64IXCHERI-NEXT:    sext.w s3, s0
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 12
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 4
 ; RV64IXCHERI-NEXT:    j .LBB161_2
 ; RV64IXCHERI-NEXT:  .LBB161_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB161_2 Depth=1
-; RV64IXCHERI-NEXT:    csw a1, 12(csp)
+; RV64IXCHERI-NEXT:    csw a1, 12(sp)
 ; RV64IXCHERI-NEXT:    li a3, 2
 ; RV64IXCHERI-NEXT:    li a4, 2
-; RV64IXCHERI-NEXT:    cmove ca0, cs1
-; RV64IXCHERI-NEXT:    cmove ca1, cs0
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_4
-; RV64IXCHERI-NEXT:    clw a1, 12(csp)
+; RV64IXCHERI-NEXT:    clw a1, 12(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB161_4
 ; RV64IXCHERI-NEXT:  .LBB161_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -11224,21 +11224,21 @@ define i32 @atomicrmw_umin_i32_acquire(i32 addrspace(200)* %a, i32 %b) nounwind
 ; RV64IXCHERI-NEXT:    bgeu s3, a0, .LBB161_1
 ; RV64IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB161_2 Depth=1
-; RV64IXCHERI-NEXT:    mv a2, s2
+; RV64IXCHERI-NEXT:    mv a2, s0
 ; RV64IXCHERI-NEXT:    j .LBB161_1
 ; RV64IXCHERI-NEXT:  .LBB161_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 80(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs3, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 96
+; RV64IXCHERI-NEXT:    clc ra, 80(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s3, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 96
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_umin_i32_acquire:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camominu.w.aq a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camominu.w.aq a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw umin i32 addrspace(200)* %a, i32 %b acquire
   ret i32 %1
@@ -11247,26 +11247,26 @@ define i32 @atomicrmw_umin_i32_acquire(i32 addrspace(200)* %a, i32 %b) nounwind
 define i32 @atomicrmw_umin_i32_release(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_umin_i32_release:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    mv s0, a1
-; RV32IXCHERI-NEXT:    cmove cs2, ca0
-; RV32IXCHERI-NEXT:    clw a1, 0(ca0)
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 12
-; RV32IXCHERI-NEXT:    csetbounds cs1, ca0, 4
+; RV32IXCHERI-NEXT:    cmove s1, a0
+; RV32IXCHERI-NEXT:    clw a1, 0(a0)
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 12
+; RV32IXCHERI-NEXT:    csetbounds s2, a0, 4
 ; RV32IXCHERI-NEXT:    j .LBB162_2
 ; RV32IXCHERI-NEXT:  .LBB162_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB162_2 Depth=1
-; RV32IXCHERI-NEXT:    csw a1, 12(csp)
+; RV32IXCHERI-NEXT:    csw a1, 12(sp)
 ; RV32IXCHERI-NEXT:    li a3, 3
-; RV32IXCHERI-NEXT:    cmove ca0, cs2
-; RV32IXCHERI-NEXT:    cmove ca1, cs1
+; RV32IXCHERI-NEXT:    cmove a0, s1
+; RV32IXCHERI-NEXT:    cmove a1, s2
 ; RV32IXCHERI-NEXT:    li a4, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_4
-; RV32IXCHERI-NEXT:    clw a1, 12(csp)
+; RV32IXCHERI-NEXT:    clw a1, 12(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB162_4
 ; RV32IXCHERI-NEXT:  .LBB162_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -11278,42 +11278,42 @@ define i32 @atomicrmw_umin_i32_release(i32 addrspace(200)* %a, i32 %b) nounwind
 ; RV32IXCHERI-NEXT:    j .LBB162_1
 ; RV32IXCHERI-NEXT:  .LBB162_4: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a1
-; RV32IXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_umin_i32_release:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    camominu.w.rl a0, a1, (ca0)
+; RV32IAXCHERI-NEXT:    camominu.w.rl a0, a1, (a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_umin_i32_release:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -96
-; RV64IXCHERI-NEXT:    csc cra, 80(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs3, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    mv s2, a1
-; RV64IXCHERI-NEXT:    cmove cs1, ca0
-; RV64IXCHERI-NEXT:    clw a1, 0(ca0)
-; RV64IXCHERI-NEXT:    sext.w s3, s2
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 12
-; RV64IXCHERI-NEXT:    csetbounds cs0, ca0, 4
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -96
+; RV64IXCHERI-NEXT:    csc ra, 80(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s3, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    mv s0, a1
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    clw a1, 0(a0)
+; RV64IXCHERI-NEXT:    sext.w s3, s0
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 12
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 4
 ; RV64IXCHERI-NEXT:    j .LBB162_2
 ; RV64IXCHERI-NEXT:  .LBB162_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB162_2 Depth=1
-; RV64IXCHERI-NEXT:    csw a1, 12(csp)
+; RV64IXCHERI-NEXT:    csw a1, 12(sp)
 ; RV64IXCHERI-NEXT:    li a3, 3
-; RV64IXCHERI-NEXT:    cmove ca0, cs1
-; RV64IXCHERI-NEXT:    cmove ca1, cs0
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    li a4, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_4
-; RV64IXCHERI-NEXT:    clw a1, 12(csp)
+; RV64IXCHERI-NEXT:    clw a1, 12(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB162_4
 ; RV64IXCHERI-NEXT:  .LBB162_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -11322,21 +11322,21 @@ define i32 @atomicrmw_umin_i32_release(i32 addrspace(200)* %a, i32 %b) nounwind
 ; RV64IXCHERI-NEXT:    bgeu s3, a0, .LBB162_1
 ; RV64IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB162_2 Depth=1
-; RV64IXCHERI-NEXT:    mv a2, s2
+; RV64IXCHERI-NEXT:    mv a2, s0
 ; RV64IXCHERI-NEXT:    j .LBB162_1
 ; RV64IXCHERI-NEXT:  .LBB162_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 80(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs3, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 96
+; RV64IXCHERI-NEXT:    clc ra, 80(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s3, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 96
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_umin_i32_release:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camominu.w.rl a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camominu.w.rl a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw umin i32 addrspace(200)* %a, i32 %b release
   ret i32 %1
@@ -11345,26 +11345,26 @@ define i32 @atomicrmw_umin_i32_release(i32 addrspace(200)* %a, i32 %b) nounwind
 define i32 @atomicrmw_umin_i32_acq_rel(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_umin_i32_acq_rel:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    mv s0, a1
-; RV32IXCHERI-NEXT:    cmove cs2, ca0
-; RV32IXCHERI-NEXT:    clw a1, 0(ca0)
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 12
-; RV32IXCHERI-NEXT:    csetbounds cs1, ca0, 4
+; RV32IXCHERI-NEXT:    cmove s1, a0
+; RV32IXCHERI-NEXT:    clw a1, 0(a0)
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 12
+; RV32IXCHERI-NEXT:    csetbounds s2, a0, 4
 ; RV32IXCHERI-NEXT:    j .LBB163_2
 ; RV32IXCHERI-NEXT:  .LBB163_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB163_2 Depth=1
-; RV32IXCHERI-NEXT:    csw a1, 12(csp)
+; RV32IXCHERI-NEXT:    csw a1, 12(sp)
 ; RV32IXCHERI-NEXT:    li a3, 4
 ; RV32IXCHERI-NEXT:    li a4, 2
-; RV32IXCHERI-NEXT:    cmove ca0, cs2
-; RV32IXCHERI-NEXT:    cmove ca1, cs1
+; RV32IXCHERI-NEXT:    cmove a0, s1
+; RV32IXCHERI-NEXT:    cmove a1, s2
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_4
-; RV32IXCHERI-NEXT:    clw a1, 12(csp)
+; RV32IXCHERI-NEXT:    clw a1, 12(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB163_4
 ; RV32IXCHERI-NEXT:  .LBB163_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -11376,42 +11376,42 @@ define i32 @atomicrmw_umin_i32_acq_rel(i32 addrspace(200)* %a, i32 %b) nounwind
 ; RV32IXCHERI-NEXT:    j .LBB163_1
 ; RV32IXCHERI-NEXT:  .LBB163_4: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a1
-; RV32IXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_umin_i32_acq_rel:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    camominu.w.aqrl a0, a1, (ca0)
+; RV32IAXCHERI-NEXT:    camominu.w.aqrl a0, a1, (a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_umin_i32_acq_rel:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -96
-; RV64IXCHERI-NEXT:    csc cra, 80(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs3, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    mv s2, a1
-; RV64IXCHERI-NEXT:    cmove cs1, ca0
-; RV64IXCHERI-NEXT:    clw a1, 0(ca0)
-; RV64IXCHERI-NEXT:    sext.w s3, s2
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 12
-; RV64IXCHERI-NEXT:    csetbounds cs0, ca0, 4
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -96
+; RV64IXCHERI-NEXT:    csc ra, 80(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s3, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    mv s0, a1
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    clw a1, 0(a0)
+; RV64IXCHERI-NEXT:    sext.w s3, s0
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 12
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 4
 ; RV64IXCHERI-NEXT:    j .LBB163_2
 ; RV64IXCHERI-NEXT:  .LBB163_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB163_2 Depth=1
-; RV64IXCHERI-NEXT:    csw a1, 12(csp)
+; RV64IXCHERI-NEXT:    csw a1, 12(sp)
 ; RV64IXCHERI-NEXT:    li a3, 4
 ; RV64IXCHERI-NEXT:    li a4, 2
-; RV64IXCHERI-NEXT:    cmove ca0, cs1
-; RV64IXCHERI-NEXT:    cmove ca1, cs0
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_4
-; RV64IXCHERI-NEXT:    clw a1, 12(csp)
+; RV64IXCHERI-NEXT:    clw a1, 12(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB163_4
 ; RV64IXCHERI-NEXT:  .LBB163_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -11420,21 +11420,21 @@ define i32 @atomicrmw_umin_i32_acq_rel(i32 addrspace(200)* %a, i32 %b) nounwind
 ; RV64IXCHERI-NEXT:    bgeu s3, a0, .LBB163_1
 ; RV64IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB163_2 Depth=1
-; RV64IXCHERI-NEXT:    mv a2, s2
+; RV64IXCHERI-NEXT:    mv a2, s0
 ; RV64IXCHERI-NEXT:    j .LBB163_1
 ; RV64IXCHERI-NEXT:  .LBB163_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 80(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs3, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 96
+; RV64IXCHERI-NEXT:    clc ra, 80(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s3, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 96
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_umin_i32_acq_rel:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camominu.w.aqrl a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camominu.w.aqrl a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw umin i32 addrspace(200)* %a, i32 %b acq_rel
   ret i32 %1
@@ -11443,26 +11443,26 @@ define i32 @atomicrmw_umin_i32_acq_rel(i32 addrspace(200)* %a, i32 %b) nounwind
 define i32 @atomicrmw_umin_i32_seq_cst(i32 addrspace(200)* %a, i32 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_umin_i32_seq_cst:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    mv s0, a1
-; RV32IXCHERI-NEXT:    cmove cs2, ca0
-; RV32IXCHERI-NEXT:    clw a1, 0(ca0)
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 12
-; RV32IXCHERI-NEXT:    csetbounds cs1, ca0, 4
+; RV32IXCHERI-NEXT:    cmove s1, a0
+; RV32IXCHERI-NEXT:    clw a1, 0(a0)
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 12
+; RV32IXCHERI-NEXT:    csetbounds s2, a0, 4
 ; RV32IXCHERI-NEXT:    j .LBB164_2
 ; RV32IXCHERI-NEXT:  .LBB164_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB164_2 Depth=1
-; RV32IXCHERI-NEXT:    csw a1, 12(csp)
+; RV32IXCHERI-NEXT:    csw a1, 12(sp)
 ; RV32IXCHERI-NEXT:    li a3, 5
 ; RV32IXCHERI-NEXT:    li a4, 5
-; RV32IXCHERI-NEXT:    cmove ca0, cs2
-; RV32IXCHERI-NEXT:    cmove ca1, cs1
+; RV32IXCHERI-NEXT:    cmove a0, s1
+; RV32IXCHERI-NEXT:    cmove a1, s2
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_4
-; RV32IXCHERI-NEXT:    clw a1, 12(csp)
+; RV32IXCHERI-NEXT:    clw a1, 12(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB164_4
 ; RV32IXCHERI-NEXT:  .LBB164_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -11474,42 +11474,42 @@ define i32 @atomicrmw_umin_i32_seq_cst(i32 addrspace(200)* %a, i32 %b) nounwind
 ; RV32IXCHERI-NEXT:    j .LBB164_1
 ; RV32IXCHERI-NEXT:  .LBB164_4: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a1
-; RV32IXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_umin_i32_seq_cst:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    camominu.w.aqrl a0, a1, (ca0)
+; RV32IAXCHERI-NEXT:    camominu.w.aqrl a0, a1, (a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_umin_i32_seq_cst:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -96
-; RV64IXCHERI-NEXT:    csc cra, 80(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs3, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    mv s2, a1
-; RV64IXCHERI-NEXT:    cmove cs1, ca0
-; RV64IXCHERI-NEXT:    clw a1, 0(ca0)
-; RV64IXCHERI-NEXT:    sext.w s3, s2
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 12
-; RV64IXCHERI-NEXT:    csetbounds cs0, ca0, 4
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -96
+; RV64IXCHERI-NEXT:    csc ra, 80(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s3, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    mv s0, a1
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    clw a1, 0(a0)
+; RV64IXCHERI-NEXT:    sext.w s3, s0
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 12
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 4
 ; RV64IXCHERI-NEXT:    j .LBB164_2
 ; RV64IXCHERI-NEXT:  .LBB164_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB164_2 Depth=1
-; RV64IXCHERI-NEXT:    csw a1, 12(csp)
+; RV64IXCHERI-NEXT:    csw a1, 12(sp)
 ; RV64IXCHERI-NEXT:    li a3, 5
 ; RV64IXCHERI-NEXT:    li a4, 5
-; RV64IXCHERI-NEXT:    cmove ca0, cs1
-; RV64IXCHERI-NEXT:    cmove ca1, cs0
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_4
-; RV64IXCHERI-NEXT:    clw a1, 12(csp)
+; RV64IXCHERI-NEXT:    clw a1, 12(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB164_4
 ; RV64IXCHERI-NEXT:  .LBB164_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -11518,21 +11518,21 @@ define i32 @atomicrmw_umin_i32_seq_cst(i32 addrspace(200)* %a, i32 %b) nounwind
 ; RV64IXCHERI-NEXT:    bgeu s3, a0, .LBB164_1
 ; RV64IXCHERI-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB164_2 Depth=1
-; RV64IXCHERI-NEXT:    mv a2, s2
+; RV64IXCHERI-NEXT:    mv a2, s0
 ; RV64IXCHERI-NEXT:    j .LBB164_1
 ; RV64IXCHERI-NEXT:  .LBB164_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 80(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs3, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 96
+; RV64IXCHERI-NEXT:    clc ra, 80(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s3, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 96
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_umin_i32_seq_cst:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camominu.w.aqrl a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camominu.w.aqrl a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw umin i32 addrspace(200)* %a, i32 %b seq_cst
   ret i32 %1
@@ -11541,37 +11541,37 @@ define i32 @atomicrmw_umin_i32_seq_cst(i32 addrspace(200)* %a, i32 %b) nounwind
 define i64 @atomicrmw_xchg_i64_monotonic(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_xchg_i64_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a3, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_exchange_8
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_xchg_i64_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IAXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IAXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    li a3, 0
 ; RV32IAXCHERI-NEXT:    ccall __atomic_exchange_8
-; RV32IAXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IAXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_xchg_i64_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_exchange_8
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_xchg_i64_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camoswap.d a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camoswap.d a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw xchg i64 addrspace(200)* %a, i64 %b monotonic
   ret i64 %1
@@ -11580,37 +11580,37 @@ define i64 @atomicrmw_xchg_i64_monotonic(i64 addrspace(200)* %a, i64 %b) nounwin
 define i64 @atomicrmw_xchg_i64_acquire(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_xchg_i64_acquire:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a3, 2
 ; RV32IXCHERI-NEXT:    ccall __atomic_exchange_8
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_xchg_i64_acquire:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IAXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IAXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    li a3, 2
 ; RV32IAXCHERI-NEXT:    ccall __atomic_exchange_8
-; RV32IAXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IAXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_xchg_i64_acquire:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 2
 ; RV64IXCHERI-NEXT:    ccall __atomic_exchange_8
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_xchg_i64_acquire:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camoswap.d.aq a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camoswap.d.aq a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw xchg i64 addrspace(200)* %a, i64 %b acquire
   ret i64 %1
@@ -11619,37 +11619,37 @@ define i64 @atomicrmw_xchg_i64_acquire(i64 addrspace(200)* %a, i64 %b) nounwind
 define i64 @atomicrmw_xchg_i64_release(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_xchg_i64_release:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a3, 3
 ; RV32IXCHERI-NEXT:    ccall __atomic_exchange_8
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_xchg_i64_release:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IAXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IAXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    li a3, 3
 ; RV32IAXCHERI-NEXT:    ccall __atomic_exchange_8
-; RV32IAXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IAXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_xchg_i64_release:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 3
 ; RV64IXCHERI-NEXT:    ccall __atomic_exchange_8
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_xchg_i64_release:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camoswap.d.rl a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camoswap.d.rl a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw xchg i64 addrspace(200)* %a, i64 %b release
   ret i64 %1
@@ -11658,37 +11658,37 @@ define i64 @atomicrmw_xchg_i64_release(i64 addrspace(200)* %a, i64 %b) nounwind
 define i64 @atomicrmw_xchg_i64_acq_rel(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_xchg_i64_acq_rel:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a3, 4
 ; RV32IXCHERI-NEXT:    ccall __atomic_exchange_8
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_xchg_i64_acq_rel:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IAXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IAXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    li a3, 4
 ; RV32IAXCHERI-NEXT:    ccall __atomic_exchange_8
-; RV32IAXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IAXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_xchg_i64_acq_rel:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 4
 ; RV64IXCHERI-NEXT:    ccall __atomic_exchange_8
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_xchg_i64_acq_rel:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camoswap.d.aqrl a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camoswap.d.aqrl a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw xchg i64 addrspace(200)* %a, i64 %b acq_rel
   ret i64 %1
@@ -11697,37 +11697,37 @@ define i64 @atomicrmw_xchg_i64_acq_rel(i64 addrspace(200)* %a, i64 %b) nounwind
 define i64 @atomicrmw_xchg_i64_seq_cst(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_xchg_i64_seq_cst:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a3, 5
 ; RV32IXCHERI-NEXT:    ccall __atomic_exchange_8
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_xchg_i64_seq_cst:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IAXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IAXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    li a3, 5
 ; RV32IAXCHERI-NEXT:    ccall __atomic_exchange_8
-; RV32IAXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IAXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_xchg_i64_seq_cst:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 5
 ; RV64IXCHERI-NEXT:    ccall __atomic_exchange_8
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_xchg_i64_seq_cst:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camoswap.d.aqrl a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camoswap.d.aqrl a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw xchg i64 addrspace(200)* %a, i64 %b seq_cst
   ret i64 %1
@@ -11736,37 +11736,37 @@ define i64 @atomicrmw_xchg_i64_seq_cst(i64 addrspace(200)* %a, i64 %b) nounwind
 define i64 @atomicrmw_add_i64_monotonic(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_add_i64_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a3, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_add_8
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_add_i64_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IAXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IAXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    li a3, 0
 ; RV32IAXCHERI-NEXT:    ccall __atomic_fetch_add_8
-; RV32IAXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IAXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_add_i64_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_add_8
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_add_i64_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camoadd.d a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camoadd.d a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw add i64 addrspace(200)* %a, i64 %b monotonic
   ret i64 %1
@@ -11775,37 +11775,37 @@ define i64 @atomicrmw_add_i64_monotonic(i64 addrspace(200)* %a, i64 %b) nounwind
 define i64 @atomicrmw_add_i64_acquire(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_add_i64_acquire:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a3, 2
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_add_8
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_add_i64_acquire:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IAXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IAXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    li a3, 2
 ; RV32IAXCHERI-NEXT:    ccall __atomic_fetch_add_8
-; RV32IAXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IAXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_add_i64_acquire:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 2
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_add_8
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_add_i64_acquire:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camoadd.d.aq a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camoadd.d.aq a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw add i64 addrspace(200)* %a, i64 %b acquire
   ret i64 %1
@@ -11814,37 +11814,37 @@ define i64 @atomicrmw_add_i64_acquire(i64 addrspace(200)* %a, i64 %b) nounwind {
 define i64 @atomicrmw_add_i64_release(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_add_i64_release:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a3, 3
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_add_8
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_add_i64_release:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IAXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IAXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    li a3, 3
 ; RV32IAXCHERI-NEXT:    ccall __atomic_fetch_add_8
-; RV32IAXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IAXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_add_i64_release:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 3
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_add_8
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_add_i64_release:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camoadd.d.rl a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camoadd.d.rl a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw add i64 addrspace(200)* %a, i64 %b release
   ret i64 %1
@@ -11853,37 +11853,37 @@ define i64 @atomicrmw_add_i64_release(i64 addrspace(200)* %a, i64 %b) nounwind {
 define i64 @atomicrmw_add_i64_acq_rel(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_add_i64_acq_rel:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a3, 4
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_add_8
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_add_i64_acq_rel:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IAXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IAXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    li a3, 4
 ; RV32IAXCHERI-NEXT:    ccall __atomic_fetch_add_8
-; RV32IAXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IAXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_add_i64_acq_rel:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 4
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_add_8
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_add_i64_acq_rel:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camoadd.d.aqrl a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camoadd.d.aqrl a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw add i64 addrspace(200)* %a, i64 %b acq_rel
   ret i64 %1
@@ -11892,37 +11892,37 @@ define i64 @atomicrmw_add_i64_acq_rel(i64 addrspace(200)* %a, i64 %b) nounwind {
 define i64 @atomicrmw_add_i64_seq_cst(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_add_i64_seq_cst:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a3, 5
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_add_8
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_add_i64_seq_cst:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IAXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IAXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    li a3, 5
 ; RV32IAXCHERI-NEXT:    ccall __atomic_fetch_add_8
-; RV32IAXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IAXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_add_i64_seq_cst:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 5
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_add_8
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_add_i64_seq_cst:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camoadd.d.aqrl a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camoadd.d.aqrl a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw add i64 addrspace(200)* %a, i64 %b seq_cst
   ret i64 %1
@@ -11931,38 +11931,38 @@ define i64 @atomicrmw_add_i64_seq_cst(i64 addrspace(200)* %a, i64 %b) nounwind {
 define i64 @atomicrmw_sub_i64_monotonic(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_sub_i64_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a3, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_sub_8
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_sub_i64_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IAXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IAXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    li a3, 0
 ; RV32IAXCHERI-NEXT:    ccall __atomic_fetch_sub_8
-; RV32IAXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IAXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_sub_i64_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_sub_8
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_sub_i64_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:    neg a1, a1
-; RV64IAXCHERI-NEXT:    camoadd.d a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camoadd.d a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw sub i64 addrspace(200)* %a, i64 %b monotonic
   ret i64 %1
@@ -11971,38 +11971,38 @@ define i64 @atomicrmw_sub_i64_monotonic(i64 addrspace(200)* %a, i64 %b) nounwind
 define i64 @atomicrmw_sub_i64_acquire(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_sub_i64_acquire:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a3, 2
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_sub_8
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_sub_i64_acquire:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IAXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IAXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    li a3, 2
 ; RV32IAXCHERI-NEXT:    ccall __atomic_fetch_sub_8
-; RV32IAXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IAXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_sub_i64_acquire:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 2
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_sub_8
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_sub_i64_acquire:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:    neg a1, a1
-; RV64IAXCHERI-NEXT:    camoadd.d.aq a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camoadd.d.aq a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw sub i64 addrspace(200)* %a, i64 %b acquire
   ret i64 %1
@@ -12011,38 +12011,38 @@ define i64 @atomicrmw_sub_i64_acquire(i64 addrspace(200)* %a, i64 %b) nounwind {
 define i64 @atomicrmw_sub_i64_release(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_sub_i64_release:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a3, 3
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_sub_8
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_sub_i64_release:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IAXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IAXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    li a3, 3
 ; RV32IAXCHERI-NEXT:    ccall __atomic_fetch_sub_8
-; RV32IAXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IAXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_sub_i64_release:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 3
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_sub_8
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_sub_i64_release:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:    neg a1, a1
-; RV64IAXCHERI-NEXT:    camoadd.d.rl a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camoadd.d.rl a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw sub i64 addrspace(200)* %a, i64 %b release
   ret i64 %1
@@ -12051,38 +12051,38 @@ define i64 @atomicrmw_sub_i64_release(i64 addrspace(200)* %a, i64 %b) nounwind {
 define i64 @atomicrmw_sub_i64_acq_rel(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_sub_i64_acq_rel:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a3, 4
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_sub_8
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_sub_i64_acq_rel:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IAXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IAXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    li a3, 4
 ; RV32IAXCHERI-NEXT:    ccall __atomic_fetch_sub_8
-; RV32IAXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IAXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_sub_i64_acq_rel:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 4
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_sub_8
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_sub_i64_acq_rel:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:    neg a1, a1
-; RV64IAXCHERI-NEXT:    camoadd.d.aqrl a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camoadd.d.aqrl a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw sub i64 addrspace(200)* %a, i64 %b acq_rel
   ret i64 %1
@@ -12091,38 +12091,38 @@ define i64 @atomicrmw_sub_i64_acq_rel(i64 addrspace(200)* %a, i64 %b) nounwind {
 define i64 @atomicrmw_sub_i64_seq_cst(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_sub_i64_seq_cst:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a3, 5
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_sub_8
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_sub_i64_seq_cst:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IAXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IAXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    li a3, 5
 ; RV32IAXCHERI-NEXT:    ccall __atomic_fetch_sub_8
-; RV32IAXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IAXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_sub_i64_seq_cst:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 5
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_sub_8
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_sub_i64_seq_cst:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:    neg a1, a1
-; RV64IAXCHERI-NEXT:    camoadd.d.aqrl a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camoadd.d.aqrl a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw sub i64 addrspace(200)* %a, i64 %b seq_cst
   ret i64 %1
@@ -12131,37 +12131,37 @@ define i64 @atomicrmw_sub_i64_seq_cst(i64 addrspace(200)* %a, i64 %b) nounwind {
 define i64 @atomicrmw_and_i64_monotonic(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_and_i64_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a3, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_and_8
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_and_i64_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IAXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IAXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    li a3, 0
 ; RV32IAXCHERI-NEXT:    ccall __atomic_fetch_and_8
-; RV32IAXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IAXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_and_i64_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_and_8
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_and_i64_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camoand.d a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camoand.d a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw and i64 addrspace(200)* %a, i64 %b monotonic
   ret i64 %1
@@ -12170,37 +12170,37 @@ define i64 @atomicrmw_and_i64_monotonic(i64 addrspace(200)* %a, i64 %b) nounwind
 define i64 @atomicrmw_and_i64_acquire(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_and_i64_acquire:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a3, 2
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_and_8
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_and_i64_acquire:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IAXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IAXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    li a3, 2
 ; RV32IAXCHERI-NEXT:    ccall __atomic_fetch_and_8
-; RV32IAXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IAXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_and_i64_acquire:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 2
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_and_8
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_and_i64_acquire:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camoand.d.aq a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camoand.d.aq a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw and i64 addrspace(200)* %a, i64 %b acquire
   ret i64 %1
@@ -12209,37 +12209,37 @@ define i64 @atomicrmw_and_i64_acquire(i64 addrspace(200)* %a, i64 %b) nounwind {
 define i64 @atomicrmw_and_i64_release(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_and_i64_release:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a3, 3
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_and_8
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_and_i64_release:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IAXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IAXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    li a3, 3
 ; RV32IAXCHERI-NEXT:    ccall __atomic_fetch_and_8
-; RV32IAXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IAXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_and_i64_release:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 3
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_and_8
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_and_i64_release:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camoand.d.rl a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camoand.d.rl a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw and i64 addrspace(200)* %a, i64 %b release
   ret i64 %1
@@ -12248,37 +12248,37 @@ define i64 @atomicrmw_and_i64_release(i64 addrspace(200)* %a, i64 %b) nounwind {
 define i64 @atomicrmw_and_i64_acq_rel(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_and_i64_acq_rel:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a3, 4
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_and_8
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_and_i64_acq_rel:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IAXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IAXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    li a3, 4
 ; RV32IAXCHERI-NEXT:    ccall __atomic_fetch_and_8
-; RV32IAXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IAXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_and_i64_acq_rel:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 4
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_and_8
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_and_i64_acq_rel:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camoand.d.aqrl a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camoand.d.aqrl a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw and i64 addrspace(200)* %a, i64 %b acq_rel
   ret i64 %1
@@ -12287,37 +12287,37 @@ define i64 @atomicrmw_and_i64_acq_rel(i64 addrspace(200)* %a, i64 %b) nounwind {
 define i64 @atomicrmw_and_i64_seq_cst(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_and_i64_seq_cst:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a3, 5
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_and_8
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_and_i64_seq_cst:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IAXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IAXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    li a3, 5
 ; RV32IAXCHERI-NEXT:    ccall __atomic_fetch_and_8
-; RV32IAXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IAXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_and_i64_seq_cst:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 5
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_and_8
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_and_i64_seq_cst:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camoand.d.aqrl a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camoand.d.aqrl a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw and i64 addrspace(200)* %a, i64 %b seq_cst
   ret i64 %1
@@ -12326,41 +12326,41 @@ define i64 @atomicrmw_and_i64_seq_cst(i64 addrspace(200)* %a, i64 %b) nounwind {
 define i64 @atomicrmw_nand_i64_monotonic(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_nand_i64_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a3, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_nand_8
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_nand_i64_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IAXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IAXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    li a3, 0
 ; RV32IAXCHERI-NEXT:    ccall __atomic_fetch_nand_8
-; RV32IAXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IAXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_nand_i64_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_nand_8
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_nand_i64_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB185_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.d a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.d a2, (a0)
 ; RV64IAXCHERI-NEXT:    and a3, a2, a1
 ; RV64IAXCHERI-NEXT:    not a3, a3
-; RV64IAXCHERI-NEXT:    csc.d a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.d a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB185_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -12372,41 +12372,41 @@ define i64 @atomicrmw_nand_i64_monotonic(i64 addrspace(200)* %a, i64 %b) nounwin
 define i64 @atomicrmw_nand_i64_acquire(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_nand_i64_acquire:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a3, 2
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_nand_8
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_nand_i64_acquire:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IAXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IAXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    li a3, 2
 ; RV32IAXCHERI-NEXT:    ccall __atomic_fetch_nand_8
-; RV32IAXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IAXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_nand_i64_acquire:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 2
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_nand_8
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_nand_i64_acquire:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB186_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.d.aq a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.d.aq a2, (a0)
 ; RV64IAXCHERI-NEXT:    and a3, a2, a1
 ; RV64IAXCHERI-NEXT:    not a3, a3
-; RV64IAXCHERI-NEXT:    csc.d a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.d a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB186_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -12418,41 +12418,41 @@ define i64 @atomicrmw_nand_i64_acquire(i64 addrspace(200)* %a, i64 %b) nounwind
 define i64 @atomicrmw_nand_i64_release(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_nand_i64_release:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a3, 3
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_nand_8
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_nand_i64_release:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IAXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IAXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    li a3, 3
 ; RV32IAXCHERI-NEXT:    ccall __atomic_fetch_nand_8
-; RV32IAXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IAXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_nand_i64_release:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 3
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_nand_8
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_nand_i64_release:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB187_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.d a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.d a2, (a0)
 ; RV64IAXCHERI-NEXT:    and a3, a2, a1
 ; RV64IAXCHERI-NEXT:    not a3, a3
-; RV64IAXCHERI-NEXT:    csc.d.rl a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.d.rl a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB187_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -12464,41 +12464,41 @@ define i64 @atomicrmw_nand_i64_release(i64 addrspace(200)* %a, i64 %b) nounwind
 define i64 @atomicrmw_nand_i64_acq_rel(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_nand_i64_acq_rel:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a3, 4
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_nand_8
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_nand_i64_acq_rel:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IAXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IAXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    li a3, 4
 ; RV32IAXCHERI-NEXT:    ccall __atomic_fetch_nand_8
-; RV32IAXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IAXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_nand_i64_acq_rel:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 4
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_nand_8
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_nand_i64_acq_rel:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB188_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.d.aq a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.d.aq a2, (a0)
 ; RV64IAXCHERI-NEXT:    and a3, a2, a1
 ; RV64IAXCHERI-NEXT:    not a3, a3
-; RV64IAXCHERI-NEXT:    csc.d.rl a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.d.rl a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB188_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -12510,41 +12510,41 @@ define i64 @atomicrmw_nand_i64_acq_rel(i64 addrspace(200)* %a, i64 %b) nounwind
 define i64 @atomicrmw_nand_i64_seq_cst(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_nand_i64_seq_cst:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a3, 5
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_nand_8
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_nand_i64_seq_cst:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IAXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IAXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    li a3, 5
 ; RV32IAXCHERI-NEXT:    ccall __atomic_fetch_nand_8
-; RV32IAXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IAXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_nand_i64_seq_cst:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 5
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_nand_8
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_nand_i64_seq_cst:
 ; RV64IAXCHERI:       # %bb.0:
 ; RV64IAXCHERI-NEXT:  .LBB189_1: # =>This Inner Loop Header: Depth=1
-; RV64IAXCHERI-NEXT:    clr.d.aqrl a2, (ca0)
+; RV64IAXCHERI-NEXT:    clr.d.aqrl a2, (a0)
 ; RV64IAXCHERI-NEXT:    and a3, a2, a1
 ; RV64IAXCHERI-NEXT:    not a3, a3
-; RV64IAXCHERI-NEXT:    csc.d.rl a3, a3, (ca0)
+; RV64IAXCHERI-NEXT:    csc.d.rl a3, a3, (a0)
 ; RV64IAXCHERI-NEXT:    bnez a3, .LBB189_1
 ; RV64IAXCHERI-NEXT:  # %bb.2:
 ; RV64IAXCHERI-NEXT:    mv a0, a2
@@ -12556,37 +12556,37 @@ define i64 @atomicrmw_nand_i64_seq_cst(i64 addrspace(200)* %a, i64 %b) nounwind
 define i64 @atomicrmw_or_i64_monotonic(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_or_i64_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a3, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_or_8
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_or_i64_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IAXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IAXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    li a3, 0
 ; RV32IAXCHERI-NEXT:    ccall __atomic_fetch_or_8
-; RV32IAXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IAXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_or_i64_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_or_8
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_or_i64_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camoor.d a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camoor.d a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw or i64 addrspace(200)* %a, i64 %b monotonic
   ret i64 %1
@@ -12595,37 +12595,37 @@ define i64 @atomicrmw_or_i64_monotonic(i64 addrspace(200)* %a, i64 %b) nounwind
 define i64 @atomicrmw_or_i64_acquire(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_or_i64_acquire:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a3, 2
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_or_8
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_or_i64_acquire:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IAXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IAXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    li a3, 2
 ; RV32IAXCHERI-NEXT:    ccall __atomic_fetch_or_8
-; RV32IAXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IAXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_or_i64_acquire:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 2
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_or_8
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_or_i64_acquire:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camoor.d.aq a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camoor.d.aq a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw or i64 addrspace(200)* %a, i64 %b acquire
   ret i64 %1
@@ -12634,37 +12634,37 @@ define i64 @atomicrmw_or_i64_acquire(i64 addrspace(200)* %a, i64 %b) nounwind {
 define i64 @atomicrmw_or_i64_release(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_or_i64_release:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a3, 3
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_or_8
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_or_i64_release:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IAXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IAXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    li a3, 3
 ; RV32IAXCHERI-NEXT:    ccall __atomic_fetch_or_8
-; RV32IAXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IAXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_or_i64_release:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 3
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_or_8
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_or_i64_release:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camoor.d.rl a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camoor.d.rl a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw or i64 addrspace(200)* %a, i64 %b release
   ret i64 %1
@@ -12673,37 +12673,37 @@ define i64 @atomicrmw_or_i64_release(i64 addrspace(200)* %a, i64 %b) nounwind {
 define i64 @atomicrmw_or_i64_acq_rel(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_or_i64_acq_rel:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a3, 4
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_or_8
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_or_i64_acq_rel:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IAXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IAXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    li a3, 4
 ; RV32IAXCHERI-NEXT:    ccall __atomic_fetch_or_8
-; RV32IAXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IAXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_or_i64_acq_rel:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 4
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_or_8
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_or_i64_acq_rel:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camoor.d.aqrl a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camoor.d.aqrl a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw or i64 addrspace(200)* %a, i64 %b acq_rel
   ret i64 %1
@@ -12712,37 +12712,37 @@ define i64 @atomicrmw_or_i64_acq_rel(i64 addrspace(200)* %a, i64 %b) nounwind {
 define i64 @atomicrmw_or_i64_seq_cst(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_or_i64_seq_cst:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a3, 5
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_or_8
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_or_i64_seq_cst:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IAXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IAXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    li a3, 5
 ; RV32IAXCHERI-NEXT:    ccall __atomic_fetch_or_8
-; RV32IAXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IAXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_or_i64_seq_cst:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 5
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_or_8
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_or_i64_seq_cst:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camoor.d.aqrl a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camoor.d.aqrl a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw or i64 addrspace(200)* %a, i64 %b seq_cst
   ret i64 %1
@@ -12751,37 +12751,37 @@ define i64 @atomicrmw_or_i64_seq_cst(i64 addrspace(200)* %a, i64 %b) nounwind {
 define i64 @atomicrmw_xor_i64_monotonic(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_xor_i64_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a3, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_xor_8
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_xor_i64_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IAXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IAXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    li a3, 0
 ; RV32IAXCHERI-NEXT:    ccall __atomic_fetch_xor_8
-; RV32IAXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IAXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_xor_i64_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_xor_8
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_xor_i64_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camoxor.d a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camoxor.d a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw xor i64 addrspace(200)* %a, i64 %b monotonic
   ret i64 %1
@@ -12790,37 +12790,37 @@ define i64 @atomicrmw_xor_i64_monotonic(i64 addrspace(200)* %a, i64 %b) nounwind
 define i64 @atomicrmw_xor_i64_acquire(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_xor_i64_acquire:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a3, 2
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_xor_8
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_xor_i64_acquire:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IAXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IAXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    li a3, 2
 ; RV32IAXCHERI-NEXT:    ccall __atomic_fetch_xor_8
-; RV32IAXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IAXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_xor_i64_acquire:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 2
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_xor_8
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_xor_i64_acquire:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camoxor.d.aq a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camoxor.d.aq a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw xor i64 addrspace(200)* %a, i64 %b acquire
   ret i64 %1
@@ -12829,37 +12829,37 @@ define i64 @atomicrmw_xor_i64_acquire(i64 addrspace(200)* %a, i64 %b) nounwind {
 define i64 @atomicrmw_xor_i64_release(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_xor_i64_release:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a3, 3
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_xor_8
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_xor_i64_release:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IAXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IAXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    li a3, 3
 ; RV32IAXCHERI-NEXT:    ccall __atomic_fetch_xor_8
-; RV32IAXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IAXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_xor_i64_release:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 3
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_xor_8
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_xor_i64_release:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camoxor.d.rl a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camoxor.d.rl a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw xor i64 addrspace(200)* %a, i64 %b release
   ret i64 %1
@@ -12868,37 +12868,37 @@ define i64 @atomicrmw_xor_i64_release(i64 addrspace(200)* %a, i64 %b) nounwind {
 define i64 @atomicrmw_xor_i64_acq_rel(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_xor_i64_acq_rel:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a3, 4
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_xor_8
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_xor_i64_acq_rel:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IAXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IAXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    li a3, 4
 ; RV32IAXCHERI-NEXT:    ccall __atomic_fetch_xor_8
-; RV32IAXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IAXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_xor_i64_acq_rel:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 4
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_xor_8
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_xor_i64_acq_rel:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camoxor.d.aqrl a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camoxor.d.aqrl a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw xor i64 addrspace(200)* %a, i64 %b acq_rel
   ret i64 %1
@@ -12907,37 +12907,37 @@ define i64 @atomicrmw_xor_i64_acq_rel(i64 addrspace(200)* %a, i64 %b) nounwind {
 define i64 @atomicrmw_xor_i64_seq_cst(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_xor_i64_seq_cst:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a3, 5
 ; RV32IXCHERI-NEXT:    ccall __atomic_fetch_xor_8
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_xor_i64_seq_cst:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IAXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IAXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    li a3, 5
 ; RV32IAXCHERI-NEXT:    ccall __atomic_fetch_xor_8
-; RV32IAXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IAXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_xor_i64_seq_cst:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 5
 ; RV64IXCHERI-NEXT:    ccall __atomic_fetch_xor_8
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_xor_i64_seq_cst:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camoxor.d.aqrl a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camoxor.d.aqrl a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw xor i64 addrspace(200)* %a, i64 %b seq_cst
   ret i64 %1
@@ -12946,31 +12946,31 @@ define i64 @atomicrmw_xor_i64_seq_cst(i64 addrspace(200)* %a, i64 %b) nounwind {
 define i64 @atomicrmw_max_i64_monotonic(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_max_i64_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs3, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s3, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    mv s0, a2
-; RV32IXCHERI-NEXT:    mv s2, a1
-; RV32IXCHERI-NEXT:    cmove cs3, ca0
-; RV32IXCHERI-NEXT:    clw a1, 4(ca0)
-; RV32IXCHERI-NEXT:    clw a4, 0(ca0)
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 0
-; RV32IXCHERI-NEXT:    csetbounds cs1, ca0, 8
+; RV32IXCHERI-NEXT:    mv s1, a1
+; RV32IXCHERI-NEXT:    cmove s2, a0
+; RV32IXCHERI-NEXT:    clw a1, 4(a0)
+; RV32IXCHERI-NEXT:    clw a4, 0(a0)
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 0
+; RV32IXCHERI-NEXT:    csetbounds s3, a0, 8
 ; RV32IXCHERI-NEXT:    j .LBB200_2
 ; RV32IXCHERI-NEXT:  .LBB200_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB200_2 Depth=1
-; RV32IXCHERI-NEXT:    csw a4, 0(csp)
-; RV32IXCHERI-NEXT:    csw a1, 4(csp)
-; RV32IXCHERI-NEXT:    cmove ca0, cs3
-; RV32IXCHERI-NEXT:    cmove ca1, cs1
+; RV32IXCHERI-NEXT:    csw a4, 0(sp)
+; RV32IXCHERI-NEXT:    csw a1, 4(sp)
+; RV32IXCHERI-NEXT:    cmove a0, s2
+; RV32IXCHERI-NEXT:    cmove a1, s3
 ; RV32IXCHERI-NEXT:    li a4, 0
 ; RV32IXCHERI-NEXT:    li a5, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV32IXCHERI-NEXT:    clw a1, 4(csp)
-; RV32IXCHERI-NEXT:    clw a4, 0(csp)
+; RV32IXCHERI-NEXT:    clw a1, 4(sp)
+; RV32IXCHERI-NEXT:    clw a4, 0(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB200_7
 ; RV32IXCHERI-NEXT:  .LBB200_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -12980,7 +12980,7 @@ define i64 @atomicrmw_max_i64_monotonic(i64 addrspace(200)* %a, i64 %b) nounwind
 ; RV32IXCHERI-NEXT:    slt a0, s0, a1
 ; RV32IXCHERI-NEXT:    j .LBB200_5
 ; RV32IXCHERI-NEXT:  .LBB200_4: # in Loop: Header=BB200_2 Depth=1
-; RV32IXCHERI-NEXT:    sltu a0, s2, a4
+; RV32IXCHERI-NEXT:    sltu a0, s1, a4
 ; RV32IXCHERI-NEXT:  .LBB200_5: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB200_2 Depth=1
 ; RV32IXCHERI-NEXT:    mv a2, a4
@@ -12988,46 +12988,46 @@ define i64 @atomicrmw_max_i64_monotonic(i64 addrspace(200)* %a, i64 %b) nounwind
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB200_1
 ; RV32IXCHERI-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB200_2 Depth=1
-; RV32IXCHERI-NEXT:    mv a2, s2
+; RV32IXCHERI-NEXT:    mv a2, s1
 ; RV32IXCHERI-NEXT:    mv a3, s0
 ; RV32IXCHERI-NEXT:    j .LBB200_1
 ; RV32IXCHERI-NEXT:  .LBB200_7: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a4
-; RV32IXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs3, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s3, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_max_i64_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IAXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs3, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IAXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s3, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    mv s0, a2
-; RV32IAXCHERI-NEXT:    mv s2, a1
-; RV32IAXCHERI-NEXT:    cmove cs3, ca0
-; RV32IAXCHERI-NEXT:    clw a1, 4(ca0)
-; RV32IAXCHERI-NEXT:    clw a4, 0(ca0)
-; RV32IAXCHERI-NEXT:    cincoffset ca0, csp, 0
-; RV32IAXCHERI-NEXT:    csetbounds cs1, ca0, 8
+; RV32IAXCHERI-NEXT:    mv s1, a1
+; RV32IAXCHERI-NEXT:    cmove s2, a0
+; RV32IAXCHERI-NEXT:    clw a1, 4(a0)
+; RV32IAXCHERI-NEXT:    clw a4, 0(a0)
+; RV32IAXCHERI-NEXT:    cincoffset a0, sp, 0
+; RV32IAXCHERI-NEXT:    csetbounds s3, a0, 8
 ; RV32IAXCHERI-NEXT:    j .LBB200_2
 ; RV32IAXCHERI-NEXT:  .LBB200_1: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # in Loop: Header=BB200_2 Depth=1
-; RV32IAXCHERI-NEXT:    csw a4, 0(csp)
-; RV32IAXCHERI-NEXT:    csw a1, 4(csp)
-; RV32IAXCHERI-NEXT:    cmove ca0, cs3
-; RV32IAXCHERI-NEXT:    cmove ca1, cs1
+; RV32IAXCHERI-NEXT:    csw a4, 0(sp)
+; RV32IAXCHERI-NEXT:    csw a1, 4(sp)
+; RV32IAXCHERI-NEXT:    cmove a0, s2
+; RV32IAXCHERI-NEXT:    cmove a1, s3
 ; RV32IAXCHERI-NEXT:    li a4, 0
 ; RV32IAXCHERI-NEXT:    li a5, 0
 ; RV32IAXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV32IAXCHERI-NEXT:    clw a1, 4(csp)
-; RV32IAXCHERI-NEXT:    clw a4, 0(csp)
+; RV32IAXCHERI-NEXT:    clw a1, 4(sp)
+; RV32IAXCHERI-NEXT:    clw a4, 0(sp)
 ; RV32IAXCHERI-NEXT:    bnez a0, .LBB200_7
 ; RV32IAXCHERI-NEXT:  .LBB200_2: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -13037,7 +13037,7 @@ define i64 @atomicrmw_max_i64_monotonic(i64 addrspace(200)* %a, i64 %b) nounwind
 ; RV32IAXCHERI-NEXT:    slt a0, s0, a1
 ; RV32IAXCHERI-NEXT:    j .LBB200_5
 ; RV32IAXCHERI-NEXT:  .LBB200_4: # in Loop: Header=BB200_2 Depth=1
-; RV32IAXCHERI-NEXT:    sltu a0, s2, a4
+; RV32IAXCHERI-NEXT:    sltu a0, s1, a4
 ; RV32IAXCHERI-NEXT:  .LBB200_5: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # in Loop: Header=BB200_2 Depth=1
 ; RV32IAXCHERI-NEXT:    mv a2, a4
@@ -13045,41 +13045,41 @@ define i64 @atomicrmw_max_i64_monotonic(i64 addrspace(200)* %a, i64 %b) nounwind
 ; RV32IAXCHERI-NEXT:    bnez a0, .LBB200_1
 ; RV32IAXCHERI-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # in Loop: Header=BB200_2 Depth=1
-; RV32IAXCHERI-NEXT:    mv a2, s2
+; RV32IAXCHERI-NEXT:    mv a2, s1
 ; RV32IAXCHERI-NEXT:    mv a3, s0
 ; RV32IAXCHERI-NEXT:    j .LBB200_1
 ; RV32IAXCHERI-NEXT:  .LBB200_7: # %atomicrmw.end
 ; RV32IAXCHERI-NEXT:    mv a0, a4
-; RV32IAXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs3, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IAXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s3, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_max_i64_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -80
-; RV64IXCHERI-NEXT:    csc cra, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 16(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -80
+; RV64IXCHERI-NEXT:    csc ra, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 16(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    mv s0, a1
-; RV64IXCHERI-NEXT:    cmove cs2, ca0
-; RV64IXCHERI-NEXT:    cld a1, 0(ca0)
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 8
-; RV64IXCHERI-NEXT:    csetbounds cs1, ca0, 8
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    cld a1, 0(a0)
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 8
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 8
 ; RV64IXCHERI-NEXT:    j .LBB200_2
 ; RV64IXCHERI-NEXT:  .LBB200_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB200_2 Depth=1
-; RV64IXCHERI-NEXT:    csd a1, 8(csp)
-; RV64IXCHERI-NEXT:    cmove ca0, cs2
-; RV64IXCHERI-NEXT:    cmove ca1, cs1
+; RV64IXCHERI-NEXT:    csd a1, 8(sp)
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    li a3, 0
 ; RV64IXCHERI-NEXT:    li a4, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV64IXCHERI-NEXT:    cld a1, 8(csp)
+; RV64IXCHERI-NEXT:    cld a1, 8(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB200_4
 ; RV64IXCHERI-NEXT:  .LBB200_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -13091,16 +13091,16 @@ define i64 @atomicrmw_max_i64_monotonic(i64 addrspace(200)* %a, i64 %b) nounwind
 ; RV64IXCHERI-NEXT:    j .LBB200_1
 ; RV64IXCHERI-NEXT:  .LBB200_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 80
+; RV64IXCHERI-NEXT:    clc ra, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 80
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_max_i64_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camomax.d a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camomax.d a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw max i64 addrspace(200)* %a, i64 %b monotonic
   ret i64 %1
@@ -13109,31 +13109,31 @@ define i64 @atomicrmw_max_i64_monotonic(i64 addrspace(200)* %a, i64 %b) nounwind
 define i64 @atomicrmw_max_i64_acquire(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_max_i64_acquire:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs3, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s3, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    mv s0, a2
-; RV32IXCHERI-NEXT:    mv s2, a1
-; RV32IXCHERI-NEXT:    cmove cs3, ca0
-; RV32IXCHERI-NEXT:    clw a1, 4(ca0)
-; RV32IXCHERI-NEXT:    clw a4, 0(ca0)
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 0
-; RV32IXCHERI-NEXT:    csetbounds cs1, ca0, 8
+; RV32IXCHERI-NEXT:    mv s1, a1
+; RV32IXCHERI-NEXT:    cmove s2, a0
+; RV32IXCHERI-NEXT:    clw a1, 4(a0)
+; RV32IXCHERI-NEXT:    clw a4, 0(a0)
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 0
+; RV32IXCHERI-NEXT:    csetbounds s3, a0, 8
 ; RV32IXCHERI-NEXT:    j .LBB201_2
 ; RV32IXCHERI-NEXT:  .LBB201_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB201_2 Depth=1
-; RV32IXCHERI-NEXT:    csw a4, 0(csp)
-; RV32IXCHERI-NEXT:    csw a1, 4(csp)
+; RV32IXCHERI-NEXT:    csw a4, 0(sp)
+; RV32IXCHERI-NEXT:    csw a1, 4(sp)
 ; RV32IXCHERI-NEXT:    li a4, 2
 ; RV32IXCHERI-NEXT:    li a5, 2
-; RV32IXCHERI-NEXT:    cmove ca0, cs3
-; RV32IXCHERI-NEXT:    cmove ca1, cs1
+; RV32IXCHERI-NEXT:    cmove a0, s2
+; RV32IXCHERI-NEXT:    cmove a1, s3
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV32IXCHERI-NEXT:    clw a1, 4(csp)
-; RV32IXCHERI-NEXT:    clw a4, 0(csp)
+; RV32IXCHERI-NEXT:    clw a1, 4(sp)
+; RV32IXCHERI-NEXT:    clw a4, 0(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB201_7
 ; RV32IXCHERI-NEXT:  .LBB201_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -13143,7 +13143,7 @@ define i64 @atomicrmw_max_i64_acquire(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-NEXT:    slt a0, s0, a1
 ; RV32IXCHERI-NEXT:    j .LBB201_5
 ; RV32IXCHERI-NEXT:  .LBB201_4: # in Loop: Header=BB201_2 Depth=1
-; RV32IXCHERI-NEXT:    sltu a0, s2, a4
+; RV32IXCHERI-NEXT:    sltu a0, s1, a4
 ; RV32IXCHERI-NEXT:  .LBB201_5: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB201_2 Depth=1
 ; RV32IXCHERI-NEXT:    mv a2, a4
@@ -13151,46 +13151,46 @@ define i64 @atomicrmw_max_i64_acquire(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB201_1
 ; RV32IXCHERI-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB201_2 Depth=1
-; RV32IXCHERI-NEXT:    mv a2, s2
+; RV32IXCHERI-NEXT:    mv a2, s1
 ; RV32IXCHERI-NEXT:    mv a3, s0
 ; RV32IXCHERI-NEXT:    j .LBB201_1
 ; RV32IXCHERI-NEXT:  .LBB201_7: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a4
-; RV32IXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs3, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s3, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_max_i64_acquire:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IAXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs3, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IAXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s3, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    mv s0, a2
-; RV32IAXCHERI-NEXT:    mv s2, a1
-; RV32IAXCHERI-NEXT:    cmove cs3, ca0
-; RV32IAXCHERI-NEXT:    clw a1, 4(ca0)
-; RV32IAXCHERI-NEXT:    clw a4, 0(ca0)
-; RV32IAXCHERI-NEXT:    cincoffset ca0, csp, 0
-; RV32IAXCHERI-NEXT:    csetbounds cs1, ca0, 8
+; RV32IAXCHERI-NEXT:    mv s1, a1
+; RV32IAXCHERI-NEXT:    cmove s2, a0
+; RV32IAXCHERI-NEXT:    clw a1, 4(a0)
+; RV32IAXCHERI-NEXT:    clw a4, 0(a0)
+; RV32IAXCHERI-NEXT:    cincoffset a0, sp, 0
+; RV32IAXCHERI-NEXT:    csetbounds s3, a0, 8
 ; RV32IAXCHERI-NEXT:    j .LBB201_2
 ; RV32IAXCHERI-NEXT:  .LBB201_1: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # in Loop: Header=BB201_2 Depth=1
-; RV32IAXCHERI-NEXT:    csw a4, 0(csp)
-; RV32IAXCHERI-NEXT:    csw a1, 4(csp)
+; RV32IAXCHERI-NEXT:    csw a4, 0(sp)
+; RV32IAXCHERI-NEXT:    csw a1, 4(sp)
 ; RV32IAXCHERI-NEXT:    li a4, 2
 ; RV32IAXCHERI-NEXT:    li a5, 2
-; RV32IAXCHERI-NEXT:    cmove ca0, cs3
-; RV32IAXCHERI-NEXT:    cmove ca1, cs1
+; RV32IAXCHERI-NEXT:    cmove a0, s2
+; RV32IAXCHERI-NEXT:    cmove a1, s3
 ; RV32IAXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV32IAXCHERI-NEXT:    clw a1, 4(csp)
-; RV32IAXCHERI-NEXT:    clw a4, 0(csp)
+; RV32IAXCHERI-NEXT:    clw a1, 4(sp)
+; RV32IAXCHERI-NEXT:    clw a4, 0(sp)
 ; RV32IAXCHERI-NEXT:    bnez a0, .LBB201_7
 ; RV32IAXCHERI-NEXT:  .LBB201_2: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -13200,7 +13200,7 @@ define i64 @atomicrmw_max_i64_acquire(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IAXCHERI-NEXT:    slt a0, s0, a1
 ; RV32IAXCHERI-NEXT:    j .LBB201_5
 ; RV32IAXCHERI-NEXT:  .LBB201_4: # in Loop: Header=BB201_2 Depth=1
-; RV32IAXCHERI-NEXT:    sltu a0, s2, a4
+; RV32IAXCHERI-NEXT:    sltu a0, s1, a4
 ; RV32IAXCHERI-NEXT:  .LBB201_5: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # in Loop: Header=BB201_2 Depth=1
 ; RV32IAXCHERI-NEXT:    mv a2, a4
@@ -13208,41 +13208,41 @@ define i64 @atomicrmw_max_i64_acquire(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IAXCHERI-NEXT:    bnez a0, .LBB201_1
 ; RV32IAXCHERI-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # in Loop: Header=BB201_2 Depth=1
-; RV32IAXCHERI-NEXT:    mv a2, s2
+; RV32IAXCHERI-NEXT:    mv a2, s1
 ; RV32IAXCHERI-NEXT:    mv a3, s0
 ; RV32IAXCHERI-NEXT:    j .LBB201_1
 ; RV32IAXCHERI-NEXT:  .LBB201_7: # %atomicrmw.end
 ; RV32IAXCHERI-NEXT:    mv a0, a4
-; RV32IAXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs3, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IAXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s3, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_max_i64_acquire:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -80
-; RV64IXCHERI-NEXT:    csc cra, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 16(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -80
+; RV64IXCHERI-NEXT:    csc ra, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 16(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    mv s0, a1
-; RV64IXCHERI-NEXT:    cmove cs2, ca0
-; RV64IXCHERI-NEXT:    cld a1, 0(ca0)
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 8
-; RV64IXCHERI-NEXT:    csetbounds cs1, ca0, 8
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    cld a1, 0(a0)
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 8
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 8
 ; RV64IXCHERI-NEXT:    j .LBB201_2
 ; RV64IXCHERI-NEXT:  .LBB201_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB201_2 Depth=1
-; RV64IXCHERI-NEXT:    csd a1, 8(csp)
+; RV64IXCHERI-NEXT:    csd a1, 8(sp)
 ; RV64IXCHERI-NEXT:    li a3, 2
 ; RV64IXCHERI-NEXT:    li a4, 2
-; RV64IXCHERI-NEXT:    cmove ca0, cs2
-; RV64IXCHERI-NEXT:    cmove ca1, cs1
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV64IXCHERI-NEXT:    cld a1, 8(csp)
+; RV64IXCHERI-NEXT:    cld a1, 8(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB201_4
 ; RV64IXCHERI-NEXT:  .LBB201_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -13254,16 +13254,16 @@ define i64 @atomicrmw_max_i64_acquire(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV64IXCHERI-NEXT:    j .LBB201_1
 ; RV64IXCHERI-NEXT:  .LBB201_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 80
+; RV64IXCHERI-NEXT:    clc ra, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 80
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_max_i64_acquire:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camomax.d.aq a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camomax.d.aq a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw max i64 addrspace(200)* %a, i64 %b acquire
   ret i64 %1
@@ -13272,31 +13272,31 @@ define i64 @atomicrmw_max_i64_acquire(i64 addrspace(200)* %a, i64 %b) nounwind {
 define i64 @atomicrmw_max_i64_release(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_max_i64_release:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs3, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s3, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    mv s0, a2
-; RV32IXCHERI-NEXT:    mv s2, a1
-; RV32IXCHERI-NEXT:    cmove cs3, ca0
-; RV32IXCHERI-NEXT:    clw a1, 4(ca0)
-; RV32IXCHERI-NEXT:    clw a4, 0(ca0)
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 0
-; RV32IXCHERI-NEXT:    csetbounds cs1, ca0, 8
+; RV32IXCHERI-NEXT:    mv s1, a1
+; RV32IXCHERI-NEXT:    cmove s2, a0
+; RV32IXCHERI-NEXT:    clw a1, 4(a0)
+; RV32IXCHERI-NEXT:    clw a4, 0(a0)
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 0
+; RV32IXCHERI-NEXT:    csetbounds s3, a0, 8
 ; RV32IXCHERI-NEXT:    j .LBB202_2
 ; RV32IXCHERI-NEXT:  .LBB202_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB202_2 Depth=1
-; RV32IXCHERI-NEXT:    csw a4, 0(csp)
-; RV32IXCHERI-NEXT:    csw a1, 4(csp)
+; RV32IXCHERI-NEXT:    csw a4, 0(sp)
+; RV32IXCHERI-NEXT:    csw a1, 4(sp)
 ; RV32IXCHERI-NEXT:    li a4, 3
-; RV32IXCHERI-NEXT:    cmove ca0, cs3
-; RV32IXCHERI-NEXT:    cmove ca1, cs1
+; RV32IXCHERI-NEXT:    cmove a0, s2
+; RV32IXCHERI-NEXT:    cmove a1, s3
 ; RV32IXCHERI-NEXT:    li a5, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV32IXCHERI-NEXT:    clw a1, 4(csp)
-; RV32IXCHERI-NEXT:    clw a4, 0(csp)
+; RV32IXCHERI-NEXT:    clw a1, 4(sp)
+; RV32IXCHERI-NEXT:    clw a4, 0(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB202_7
 ; RV32IXCHERI-NEXT:  .LBB202_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -13306,7 +13306,7 @@ define i64 @atomicrmw_max_i64_release(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-NEXT:    slt a0, s0, a1
 ; RV32IXCHERI-NEXT:    j .LBB202_5
 ; RV32IXCHERI-NEXT:  .LBB202_4: # in Loop: Header=BB202_2 Depth=1
-; RV32IXCHERI-NEXT:    sltu a0, s2, a4
+; RV32IXCHERI-NEXT:    sltu a0, s1, a4
 ; RV32IXCHERI-NEXT:  .LBB202_5: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB202_2 Depth=1
 ; RV32IXCHERI-NEXT:    mv a2, a4
@@ -13314,46 +13314,46 @@ define i64 @atomicrmw_max_i64_release(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB202_1
 ; RV32IXCHERI-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB202_2 Depth=1
-; RV32IXCHERI-NEXT:    mv a2, s2
+; RV32IXCHERI-NEXT:    mv a2, s1
 ; RV32IXCHERI-NEXT:    mv a3, s0
 ; RV32IXCHERI-NEXT:    j .LBB202_1
 ; RV32IXCHERI-NEXT:  .LBB202_7: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a4
-; RV32IXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs3, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s3, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_max_i64_release:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IAXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs3, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IAXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s3, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    mv s0, a2
-; RV32IAXCHERI-NEXT:    mv s2, a1
-; RV32IAXCHERI-NEXT:    cmove cs3, ca0
-; RV32IAXCHERI-NEXT:    clw a1, 4(ca0)
-; RV32IAXCHERI-NEXT:    clw a4, 0(ca0)
-; RV32IAXCHERI-NEXT:    cincoffset ca0, csp, 0
-; RV32IAXCHERI-NEXT:    csetbounds cs1, ca0, 8
+; RV32IAXCHERI-NEXT:    mv s1, a1
+; RV32IAXCHERI-NEXT:    cmove s2, a0
+; RV32IAXCHERI-NEXT:    clw a1, 4(a0)
+; RV32IAXCHERI-NEXT:    clw a4, 0(a0)
+; RV32IAXCHERI-NEXT:    cincoffset a0, sp, 0
+; RV32IAXCHERI-NEXT:    csetbounds s3, a0, 8
 ; RV32IAXCHERI-NEXT:    j .LBB202_2
 ; RV32IAXCHERI-NEXT:  .LBB202_1: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # in Loop: Header=BB202_2 Depth=1
-; RV32IAXCHERI-NEXT:    csw a4, 0(csp)
-; RV32IAXCHERI-NEXT:    csw a1, 4(csp)
+; RV32IAXCHERI-NEXT:    csw a4, 0(sp)
+; RV32IAXCHERI-NEXT:    csw a1, 4(sp)
 ; RV32IAXCHERI-NEXT:    li a4, 3
-; RV32IAXCHERI-NEXT:    cmove ca0, cs3
-; RV32IAXCHERI-NEXT:    cmove ca1, cs1
+; RV32IAXCHERI-NEXT:    cmove a0, s2
+; RV32IAXCHERI-NEXT:    cmove a1, s3
 ; RV32IAXCHERI-NEXT:    li a5, 0
 ; RV32IAXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV32IAXCHERI-NEXT:    clw a1, 4(csp)
-; RV32IAXCHERI-NEXT:    clw a4, 0(csp)
+; RV32IAXCHERI-NEXT:    clw a1, 4(sp)
+; RV32IAXCHERI-NEXT:    clw a4, 0(sp)
 ; RV32IAXCHERI-NEXT:    bnez a0, .LBB202_7
 ; RV32IAXCHERI-NEXT:  .LBB202_2: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -13363,7 +13363,7 @@ define i64 @atomicrmw_max_i64_release(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IAXCHERI-NEXT:    slt a0, s0, a1
 ; RV32IAXCHERI-NEXT:    j .LBB202_5
 ; RV32IAXCHERI-NEXT:  .LBB202_4: # in Loop: Header=BB202_2 Depth=1
-; RV32IAXCHERI-NEXT:    sltu a0, s2, a4
+; RV32IAXCHERI-NEXT:    sltu a0, s1, a4
 ; RV32IAXCHERI-NEXT:  .LBB202_5: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # in Loop: Header=BB202_2 Depth=1
 ; RV32IAXCHERI-NEXT:    mv a2, a4
@@ -13371,41 +13371,41 @@ define i64 @atomicrmw_max_i64_release(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IAXCHERI-NEXT:    bnez a0, .LBB202_1
 ; RV32IAXCHERI-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # in Loop: Header=BB202_2 Depth=1
-; RV32IAXCHERI-NEXT:    mv a2, s2
+; RV32IAXCHERI-NEXT:    mv a2, s1
 ; RV32IAXCHERI-NEXT:    mv a3, s0
 ; RV32IAXCHERI-NEXT:    j .LBB202_1
 ; RV32IAXCHERI-NEXT:  .LBB202_7: # %atomicrmw.end
 ; RV32IAXCHERI-NEXT:    mv a0, a4
-; RV32IAXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs3, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IAXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s3, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_max_i64_release:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -80
-; RV64IXCHERI-NEXT:    csc cra, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 16(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -80
+; RV64IXCHERI-NEXT:    csc ra, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 16(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    mv s0, a1
-; RV64IXCHERI-NEXT:    cmove cs2, ca0
-; RV64IXCHERI-NEXT:    cld a1, 0(ca0)
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 8
-; RV64IXCHERI-NEXT:    csetbounds cs1, ca0, 8
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    cld a1, 0(a0)
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 8
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 8
 ; RV64IXCHERI-NEXT:    j .LBB202_2
 ; RV64IXCHERI-NEXT:  .LBB202_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB202_2 Depth=1
-; RV64IXCHERI-NEXT:    csd a1, 8(csp)
+; RV64IXCHERI-NEXT:    csd a1, 8(sp)
 ; RV64IXCHERI-NEXT:    li a3, 3
-; RV64IXCHERI-NEXT:    cmove ca0, cs2
-; RV64IXCHERI-NEXT:    cmove ca1, cs1
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    li a4, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV64IXCHERI-NEXT:    cld a1, 8(csp)
+; RV64IXCHERI-NEXT:    cld a1, 8(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB202_4
 ; RV64IXCHERI-NEXT:  .LBB202_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -13417,16 +13417,16 @@ define i64 @atomicrmw_max_i64_release(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV64IXCHERI-NEXT:    j .LBB202_1
 ; RV64IXCHERI-NEXT:  .LBB202_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 80
+; RV64IXCHERI-NEXT:    clc ra, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 80
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_max_i64_release:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camomax.d.rl a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camomax.d.rl a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw max i64 addrspace(200)* %a, i64 %b release
   ret i64 %1
@@ -13435,31 +13435,31 @@ define i64 @atomicrmw_max_i64_release(i64 addrspace(200)* %a, i64 %b) nounwind {
 define i64 @atomicrmw_max_i64_acq_rel(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_max_i64_acq_rel:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs3, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s3, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    mv s0, a2
-; RV32IXCHERI-NEXT:    mv s2, a1
-; RV32IXCHERI-NEXT:    cmove cs3, ca0
-; RV32IXCHERI-NEXT:    clw a1, 4(ca0)
-; RV32IXCHERI-NEXT:    clw a4, 0(ca0)
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 0
-; RV32IXCHERI-NEXT:    csetbounds cs1, ca0, 8
+; RV32IXCHERI-NEXT:    mv s1, a1
+; RV32IXCHERI-NEXT:    cmove s2, a0
+; RV32IXCHERI-NEXT:    clw a1, 4(a0)
+; RV32IXCHERI-NEXT:    clw a4, 0(a0)
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 0
+; RV32IXCHERI-NEXT:    csetbounds s3, a0, 8
 ; RV32IXCHERI-NEXT:    j .LBB203_2
 ; RV32IXCHERI-NEXT:  .LBB203_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB203_2 Depth=1
-; RV32IXCHERI-NEXT:    csw a4, 0(csp)
-; RV32IXCHERI-NEXT:    csw a1, 4(csp)
+; RV32IXCHERI-NEXT:    csw a4, 0(sp)
+; RV32IXCHERI-NEXT:    csw a1, 4(sp)
 ; RV32IXCHERI-NEXT:    li a4, 4
 ; RV32IXCHERI-NEXT:    li a5, 2
-; RV32IXCHERI-NEXT:    cmove ca0, cs3
-; RV32IXCHERI-NEXT:    cmove ca1, cs1
+; RV32IXCHERI-NEXT:    cmove a0, s2
+; RV32IXCHERI-NEXT:    cmove a1, s3
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV32IXCHERI-NEXT:    clw a1, 4(csp)
-; RV32IXCHERI-NEXT:    clw a4, 0(csp)
+; RV32IXCHERI-NEXT:    clw a1, 4(sp)
+; RV32IXCHERI-NEXT:    clw a4, 0(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB203_7
 ; RV32IXCHERI-NEXT:  .LBB203_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -13469,7 +13469,7 @@ define i64 @atomicrmw_max_i64_acq_rel(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-NEXT:    slt a0, s0, a1
 ; RV32IXCHERI-NEXT:    j .LBB203_5
 ; RV32IXCHERI-NEXT:  .LBB203_4: # in Loop: Header=BB203_2 Depth=1
-; RV32IXCHERI-NEXT:    sltu a0, s2, a4
+; RV32IXCHERI-NEXT:    sltu a0, s1, a4
 ; RV32IXCHERI-NEXT:  .LBB203_5: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB203_2 Depth=1
 ; RV32IXCHERI-NEXT:    mv a2, a4
@@ -13477,46 +13477,46 @@ define i64 @atomicrmw_max_i64_acq_rel(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB203_1
 ; RV32IXCHERI-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB203_2 Depth=1
-; RV32IXCHERI-NEXT:    mv a2, s2
+; RV32IXCHERI-NEXT:    mv a2, s1
 ; RV32IXCHERI-NEXT:    mv a3, s0
 ; RV32IXCHERI-NEXT:    j .LBB203_1
 ; RV32IXCHERI-NEXT:  .LBB203_7: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a4
-; RV32IXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs3, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s3, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_max_i64_acq_rel:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IAXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs3, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IAXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s3, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    mv s0, a2
-; RV32IAXCHERI-NEXT:    mv s2, a1
-; RV32IAXCHERI-NEXT:    cmove cs3, ca0
-; RV32IAXCHERI-NEXT:    clw a1, 4(ca0)
-; RV32IAXCHERI-NEXT:    clw a4, 0(ca0)
-; RV32IAXCHERI-NEXT:    cincoffset ca0, csp, 0
-; RV32IAXCHERI-NEXT:    csetbounds cs1, ca0, 8
+; RV32IAXCHERI-NEXT:    mv s1, a1
+; RV32IAXCHERI-NEXT:    cmove s2, a0
+; RV32IAXCHERI-NEXT:    clw a1, 4(a0)
+; RV32IAXCHERI-NEXT:    clw a4, 0(a0)
+; RV32IAXCHERI-NEXT:    cincoffset a0, sp, 0
+; RV32IAXCHERI-NEXT:    csetbounds s3, a0, 8
 ; RV32IAXCHERI-NEXT:    j .LBB203_2
 ; RV32IAXCHERI-NEXT:  .LBB203_1: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # in Loop: Header=BB203_2 Depth=1
-; RV32IAXCHERI-NEXT:    csw a4, 0(csp)
-; RV32IAXCHERI-NEXT:    csw a1, 4(csp)
+; RV32IAXCHERI-NEXT:    csw a4, 0(sp)
+; RV32IAXCHERI-NEXT:    csw a1, 4(sp)
 ; RV32IAXCHERI-NEXT:    li a4, 4
 ; RV32IAXCHERI-NEXT:    li a5, 2
-; RV32IAXCHERI-NEXT:    cmove ca0, cs3
-; RV32IAXCHERI-NEXT:    cmove ca1, cs1
+; RV32IAXCHERI-NEXT:    cmove a0, s2
+; RV32IAXCHERI-NEXT:    cmove a1, s3
 ; RV32IAXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV32IAXCHERI-NEXT:    clw a1, 4(csp)
-; RV32IAXCHERI-NEXT:    clw a4, 0(csp)
+; RV32IAXCHERI-NEXT:    clw a1, 4(sp)
+; RV32IAXCHERI-NEXT:    clw a4, 0(sp)
 ; RV32IAXCHERI-NEXT:    bnez a0, .LBB203_7
 ; RV32IAXCHERI-NEXT:  .LBB203_2: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -13526,7 +13526,7 @@ define i64 @atomicrmw_max_i64_acq_rel(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IAXCHERI-NEXT:    slt a0, s0, a1
 ; RV32IAXCHERI-NEXT:    j .LBB203_5
 ; RV32IAXCHERI-NEXT:  .LBB203_4: # in Loop: Header=BB203_2 Depth=1
-; RV32IAXCHERI-NEXT:    sltu a0, s2, a4
+; RV32IAXCHERI-NEXT:    sltu a0, s1, a4
 ; RV32IAXCHERI-NEXT:  .LBB203_5: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # in Loop: Header=BB203_2 Depth=1
 ; RV32IAXCHERI-NEXT:    mv a2, a4
@@ -13534,41 +13534,41 @@ define i64 @atomicrmw_max_i64_acq_rel(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IAXCHERI-NEXT:    bnez a0, .LBB203_1
 ; RV32IAXCHERI-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # in Loop: Header=BB203_2 Depth=1
-; RV32IAXCHERI-NEXT:    mv a2, s2
+; RV32IAXCHERI-NEXT:    mv a2, s1
 ; RV32IAXCHERI-NEXT:    mv a3, s0
 ; RV32IAXCHERI-NEXT:    j .LBB203_1
 ; RV32IAXCHERI-NEXT:  .LBB203_7: # %atomicrmw.end
 ; RV32IAXCHERI-NEXT:    mv a0, a4
-; RV32IAXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs3, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IAXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s3, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_max_i64_acq_rel:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -80
-; RV64IXCHERI-NEXT:    csc cra, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 16(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -80
+; RV64IXCHERI-NEXT:    csc ra, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 16(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    mv s0, a1
-; RV64IXCHERI-NEXT:    cmove cs2, ca0
-; RV64IXCHERI-NEXT:    cld a1, 0(ca0)
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 8
-; RV64IXCHERI-NEXT:    csetbounds cs1, ca0, 8
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    cld a1, 0(a0)
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 8
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 8
 ; RV64IXCHERI-NEXT:    j .LBB203_2
 ; RV64IXCHERI-NEXT:  .LBB203_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB203_2 Depth=1
-; RV64IXCHERI-NEXT:    csd a1, 8(csp)
+; RV64IXCHERI-NEXT:    csd a1, 8(sp)
 ; RV64IXCHERI-NEXT:    li a3, 4
 ; RV64IXCHERI-NEXT:    li a4, 2
-; RV64IXCHERI-NEXT:    cmove ca0, cs2
-; RV64IXCHERI-NEXT:    cmove ca1, cs1
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV64IXCHERI-NEXT:    cld a1, 8(csp)
+; RV64IXCHERI-NEXT:    cld a1, 8(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB203_4
 ; RV64IXCHERI-NEXT:  .LBB203_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -13580,16 +13580,16 @@ define i64 @atomicrmw_max_i64_acq_rel(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV64IXCHERI-NEXT:    j .LBB203_1
 ; RV64IXCHERI-NEXT:  .LBB203_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 80
+; RV64IXCHERI-NEXT:    clc ra, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 80
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_max_i64_acq_rel:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camomax.d.aqrl a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camomax.d.aqrl a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw max i64 addrspace(200)* %a, i64 %b acq_rel
   ret i64 %1
@@ -13598,31 +13598,31 @@ define i64 @atomicrmw_max_i64_acq_rel(i64 addrspace(200)* %a, i64 %b) nounwind {
 define i64 @atomicrmw_max_i64_seq_cst(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_max_i64_seq_cst:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs3, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s3, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    mv s0, a2
-; RV32IXCHERI-NEXT:    mv s2, a1
-; RV32IXCHERI-NEXT:    cmove cs3, ca0
-; RV32IXCHERI-NEXT:    clw a1, 4(ca0)
-; RV32IXCHERI-NEXT:    clw a4, 0(ca0)
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 0
-; RV32IXCHERI-NEXT:    csetbounds cs1, ca0, 8
+; RV32IXCHERI-NEXT:    mv s1, a1
+; RV32IXCHERI-NEXT:    cmove s2, a0
+; RV32IXCHERI-NEXT:    clw a1, 4(a0)
+; RV32IXCHERI-NEXT:    clw a4, 0(a0)
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 0
+; RV32IXCHERI-NEXT:    csetbounds s3, a0, 8
 ; RV32IXCHERI-NEXT:    j .LBB204_2
 ; RV32IXCHERI-NEXT:  .LBB204_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB204_2 Depth=1
-; RV32IXCHERI-NEXT:    csw a4, 0(csp)
-; RV32IXCHERI-NEXT:    csw a1, 4(csp)
+; RV32IXCHERI-NEXT:    csw a4, 0(sp)
+; RV32IXCHERI-NEXT:    csw a1, 4(sp)
 ; RV32IXCHERI-NEXT:    li a4, 5
 ; RV32IXCHERI-NEXT:    li a5, 5
-; RV32IXCHERI-NEXT:    cmove ca0, cs3
-; RV32IXCHERI-NEXT:    cmove ca1, cs1
+; RV32IXCHERI-NEXT:    cmove a0, s2
+; RV32IXCHERI-NEXT:    cmove a1, s3
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV32IXCHERI-NEXT:    clw a1, 4(csp)
-; RV32IXCHERI-NEXT:    clw a4, 0(csp)
+; RV32IXCHERI-NEXT:    clw a1, 4(sp)
+; RV32IXCHERI-NEXT:    clw a4, 0(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB204_7
 ; RV32IXCHERI-NEXT:  .LBB204_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -13632,7 +13632,7 @@ define i64 @atomicrmw_max_i64_seq_cst(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-NEXT:    slt a0, s0, a1
 ; RV32IXCHERI-NEXT:    j .LBB204_5
 ; RV32IXCHERI-NEXT:  .LBB204_4: # in Loop: Header=BB204_2 Depth=1
-; RV32IXCHERI-NEXT:    sltu a0, s2, a4
+; RV32IXCHERI-NEXT:    sltu a0, s1, a4
 ; RV32IXCHERI-NEXT:  .LBB204_5: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB204_2 Depth=1
 ; RV32IXCHERI-NEXT:    mv a2, a4
@@ -13640,46 +13640,46 @@ define i64 @atomicrmw_max_i64_seq_cst(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB204_1
 ; RV32IXCHERI-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB204_2 Depth=1
-; RV32IXCHERI-NEXT:    mv a2, s2
+; RV32IXCHERI-NEXT:    mv a2, s1
 ; RV32IXCHERI-NEXT:    mv a3, s0
 ; RV32IXCHERI-NEXT:    j .LBB204_1
 ; RV32IXCHERI-NEXT:  .LBB204_7: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a4
-; RV32IXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs3, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s3, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_max_i64_seq_cst:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IAXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs3, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IAXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s3, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    mv s0, a2
-; RV32IAXCHERI-NEXT:    mv s2, a1
-; RV32IAXCHERI-NEXT:    cmove cs3, ca0
-; RV32IAXCHERI-NEXT:    clw a1, 4(ca0)
-; RV32IAXCHERI-NEXT:    clw a4, 0(ca0)
-; RV32IAXCHERI-NEXT:    cincoffset ca0, csp, 0
-; RV32IAXCHERI-NEXT:    csetbounds cs1, ca0, 8
+; RV32IAXCHERI-NEXT:    mv s1, a1
+; RV32IAXCHERI-NEXT:    cmove s2, a0
+; RV32IAXCHERI-NEXT:    clw a1, 4(a0)
+; RV32IAXCHERI-NEXT:    clw a4, 0(a0)
+; RV32IAXCHERI-NEXT:    cincoffset a0, sp, 0
+; RV32IAXCHERI-NEXT:    csetbounds s3, a0, 8
 ; RV32IAXCHERI-NEXT:    j .LBB204_2
 ; RV32IAXCHERI-NEXT:  .LBB204_1: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # in Loop: Header=BB204_2 Depth=1
-; RV32IAXCHERI-NEXT:    csw a4, 0(csp)
-; RV32IAXCHERI-NEXT:    csw a1, 4(csp)
+; RV32IAXCHERI-NEXT:    csw a4, 0(sp)
+; RV32IAXCHERI-NEXT:    csw a1, 4(sp)
 ; RV32IAXCHERI-NEXT:    li a4, 5
 ; RV32IAXCHERI-NEXT:    li a5, 5
-; RV32IAXCHERI-NEXT:    cmove ca0, cs3
-; RV32IAXCHERI-NEXT:    cmove ca1, cs1
+; RV32IAXCHERI-NEXT:    cmove a0, s2
+; RV32IAXCHERI-NEXT:    cmove a1, s3
 ; RV32IAXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV32IAXCHERI-NEXT:    clw a1, 4(csp)
-; RV32IAXCHERI-NEXT:    clw a4, 0(csp)
+; RV32IAXCHERI-NEXT:    clw a1, 4(sp)
+; RV32IAXCHERI-NEXT:    clw a4, 0(sp)
 ; RV32IAXCHERI-NEXT:    bnez a0, .LBB204_7
 ; RV32IAXCHERI-NEXT:  .LBB204_2: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -13689,7 +13689,7 @@ define i64 @atomicrmw_max_i64_seq_cst(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IAXCHERI-NEXT:    slt a0, s0, a1
 ; RV32IAXCHERI-NEXT:    j .LBB204_5
 ; RV32IAXCHERI-NEXT:  .LBB204_4: # in Loop: Header=BB204_2 Depth=1
-; RV32IAXCHERI-NEXT:    sltu a0, s2, a4
+; RV32IAXCHERI-NEXT:    sltu a0, s1, a4
 ; RV32IAXCHERI-NEXT:  .LBB204_5: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # in Loop: Header=BB204_2 Depth=1
 ; RV32IAXCHERI-NEXT:    mv a2, a4
@@ -13697,41 +13697,41 @@ define i64 @atomicrmw_max_i64_seq_cst(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IAXCHERI-NEXT:    bnez a0, .LBB204_1
 ; RV32IAXCHERI-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # in Loop: Header=BB204_2 Depth=1
-; RV32IAXCHERI-NEXT:    mv a2, s2
+; RV32IAXCHERI-NEXT:    mv a2, s1
 ; RV32IAXCHERI-NEXT:    mv a3, s0
 ; RV32IAXCHERI-NEXT:    j .LBB204_1
 ; RV32IAXCHERI-NEXT:  .LBB204_7: # %atomicrmw.end
 ; RV32IAXCHERI-NEXT:    mv a0, a4
-; RV32IAXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs3, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IAXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s3, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_max_i64_seq_cst:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -80
-; RV64IXCHERI-NEXT:    csc cra, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 16(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -80
+; RV64IXCHERI-NEXT:    csc ra, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 16(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    mv s0, a1
-; RV64IXCHERI-NEXT:    cmove cs2, ca0
-; RV64IXCHERI-NEXT:    cld a1, 0(ca0)
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 8
-; RV64IXCHERI-NEXT:    csetbounds cs1, ca0, 8
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    cld a1, 0(a0)
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 8
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 8
 ; RV64IXCHERI-NEXT:    j .LBB204_2
 ; RV64IXCHERI-NEXT:  .LBB204_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB204_2 Depth=1
-; RV64IXCHERI-NEXT:    csd a1, 8(csp)
+; RV64IXCHERI-NEXT:    csd a1, 8(sp)
 ; RV64IXCHERI-NEXT:    li a3, 5
 ; RV64IXCHERI-NEXT:    li a4, 5
-; RV64IXCHERI-NEXT:    cmove ca0, cs2
-; RV64IXCHERI-NEXT:    cmove ca1, cs1
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV64IXCHERI-NEXT:    cld a1, 8(csp)
+; RV64IXCHERI-NEXT:    cld a1, 8(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB204_4
 ; RV64IXCHERI-NEXT:  .LBB204_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -13743,16 +13743,16 @@ define i64 @atomicrmw_max_i64_seq_cst(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV64IXCHERI-NEXT:    j .LBB204_1
 ; RV64IXCHERI-NEXT:  .LBB204_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 80
+; RV64IXCHERI-NEXT:    clc ra, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 80
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_max_i64_seq_cst:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camomax.d.aqrl a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camomax.d.aqrl a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw max i64 addrspace(200)* %a, i64 %b seq_cst
   ret i64 %1
@@ -13761,31 +13761,31 @@ define i64 @atomicrmw_max_i64_seq_cst(i64 addrspace(200)* %a, i64 %b) nounwind {
 define i64 @atomicrmw_min_i64_monotonic(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_min_i64_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs3, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s3, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    mv s0, a2
-; RV32IXCHERI-NEXT:    mv s2, a1
-; RV32IXCHERI-NEXT:    cmove cs3, ca0
-; RV32IXCHERI-NEXT:    clw a1, 4(ca0)
-; RV32IXCHERI-NEXT:    clw a4, 0(ca0)
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 0
-; RV32IXCHERI-NEXT:    csetbounds cs1, ca0, 8
+; RV32IXCHERI-NEXT:    mv s1, a1
+; RV32IXCHERI-NEXT:    cmove s2, a0
+; RV32IXCHERI-NEXT:    clw a1, 4(a0)
+; RV32IXCHERI-NEXT:    clw a4, 0(a0)
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 0
+; RV32IXCHERI-NEXT:    csetbounds s3, a0, 8
 ; RV32IXCHERI-NEXT:    j .LBB205_2
 ; RV32IXCHERI-NEXT:  .LBB205_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB205_2 Depth=1
-; RV32IXCHERI-NEXT:    csw a4, 0(csp)
-; RV32IXCHERI-NEXT:    csw a1, 4(csp)
-; RV32IXCHERI-NEXT:    cmove ca0, cs3
-; RV32IXCHERI-NEXT:    cmove ca1, cs1
+; RV32IXCHERI-NEXT:    csw a4, 0(sp)
+; RV32IXCHERI-NEXT:    csw a1, 4(sp)
+; RV32IXCHERI-NEXT:    cmove a0, s2
+; RV32IXCHERI-NEXT:    cmove a1, s3
 ; RV32IXCHERI-NEXT:    li a4, 0
 ; RV32IXCHERI-NEXT:    li a5, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV32IXCHERI-NEXT:    clw a1, 4(csp)
-; RV32IXCHERI-NEXT:    clw a4, 0(csp)
+; RV32IXCHERI-NEXT:    clw a1, 4(sp)
+; RV32IXCHERI-NEXT:    clw a4, 0(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB205_7
 ; RV32IXCHERI-NEXT:  .LBB205_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -13795,7 +13795,7 @@ define i64 @atomicrmw_min_i64_monotonic(i64 addrspace(200)* %a, i64 %b) nounwind
 ; RV32IXCHERI-NEXT:    slt a0, s0, a1
 ; RV32IXCHERI-NEXT:    j .LBB205_5
 ; RV32IXCHERI-NEXT:  .LBB205_4: # in Loop: Header=BB205_2 Depth=1
-; RV32IXCHERI-NEXT:    sltu a0, s2, a4
+; RV32IXCHERI-NEXT:    sltu a0, s1, a4
 ; RV32IXCHERI-NEXT:  .LBB205_5: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB205_2 Depth=1
 ; RV32IXCHERI-NEXT:    mv a2, a4
@@ -13803,46 +13803,46 @@ define i64 @atomicrmw_min_i64_monotonic(i64 addrspace(200)* %a, i64 %b) nounwind
 ; RV32IXCHERI-NEXT:    beqz a0, .LBB205_1
 ; RV32IXCHERI-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB205_2 Depth=1
-; RV32IXCHERI-NEXT:    mv a2, s2
+; RV32IXCHERI-NEXT:    mv a2, s1
 ; RV32IXCHERI-NEXT:    mv a3, s0
 ; RV32IXCHERI-NEXT:    j .LBB205_1
 ; RV32IXCHERI-NEXT:  .LBB205_7: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a4
-; RV32IXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs3, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s3, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_min_i64_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IAXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs3, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IAXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s3, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    mv s0, a2
-; RV32IAXCHERI-NEXT:    mv s2, a1
-; RV32IAXCHERI-NEXT:    cmove cs3, ca0
-; RV32IAXCHERI-NEXT:    clw a1, 4(ca0)
-; RV32IAXCHERI-NEXT:    clw a4, 0(ca0)
-; RV32IAXCHERI-NEXT:    cincoffset ca0, csp, 0
-; RV32IAXCHERI-NEXT:    csetbounds cs1, ca0, 8
+; RV32IAXCHERI-NEXT:    mv s1, a1
+; RV32IAXCHERI-NEXT:    cmove s2, a0
+; RV32IAXCHERI-NEXT:    clw a1, 4(a0)
+; RV32IAXCHERI-NEXT:    clw a4, 0(a0)
+; RV32IAXCHERI-NEXT:    cincoffset a0, sp, 0
+; RV32IAXCHERI-NEXT:    csetbounds s3, a0, 8
 ; RV32IAXCHERI-NEXT:    j .LBB205_2
 ; RV32IAXCHERI-NEXT:  .LBB205_1: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # in Loop: Header=BB205_2 Depth=1
-; RV32IAXCHERI-NEXT:    csw a4, 0(csp)
-; RV32IAXCHERI-NEXT:    csw a1, 4(csp)
-; RV32IAXCHERI-NEXT:    cmove ca0, cs3
-; RV32IAXCHERI-NEXT:    cmove ca1, cs1
+; RV32IAXCHERI-NEXT:    csw a4, 0(sp)
+; RV32IAXCHERI-NEXT:    csw a1, 4(sp)
+; RV32IAXCHERI-NEXT:    cmove a0, s2
+; RV32IAXCHERI-NEXT:    cmove a1, s3
 ; RV32IAXCHERI-NEXT:    li a4, 0
 ; RV32IAXCHERI-NEXT:    li a5, 0
 ; RV32IAXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV32IAXCHERI-NEXT:    clw a1, 4(csp)
-; RV32IAXCHERI-NEXT:    clw a4, 0(csp)
+; RV32IAXCHERI-NEXT:    clw a1, 4(sp)
+; RV32IAXCHERI-NEXT:    clw a4, 0(sp)
 ; RV32IAXCHERI-NEXT:    bnez a0, .LBB205_7
 ; RV32IAXCHERI-NEXT:  .LBB205_2: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -13852,7 +13852,7 @@ define i64 @atomicrmw_min_i64_monotonic(i64 addrspace(200)* %a, i64 %b) nounwind
 ; RV32IAXCHERI-NEXT:    slt a0, s0, a1
 ; RV32IAXCHERI-NEXT:    j .LBB205_5
 ; RV32IAXCHERI-NEXT:  .LBB205_4: # in Loop: Header=BB205_2 Depth=1
-; RV32IAXCHERI-NEXT:    sltu a0, s2, a4
+; RV32IAXCHERI-NEXT:    sltu a0, s1, a4
 ; RV32IAXCHERI-NEXT:  .LBB205_5: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # in Loop: Header=BB205_2 Depth=1
 ; RV32IAXCHERI-NEXT:    mv a2, a4
@@ -13860,41 +13860,41 @@ define i64 @atomicrmw_min_i64_monotonic(i64 addrspace(200)* %a, i64 %b) nounwind
 ; RV32IAXCHERI-NEXT:    beqz a0, .LBB205_1
 ; RV32IAXCHERI-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # in Loop: Header=BB205_2 Depth=1
-; RV32IAXCHERI-NEXT:    mv a2, s2
+; RV32IAXCHERI-NEXT:    mv a2, s1
 ; RV32IAXCHERI-NEXT:    mv a3, s0
 ; RV32IAXCHERI-NEXT:    j .LBB205_1
 ; RV32IAXCHERI-NEXT:  .LBB205_7: # %atomicrmw.end
 ; RV32IAXCHERI-NEXT:    mv a0, a4
-; RV32IAXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs3, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IAXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s3, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_min_i64_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -80
-; RV64IXCHERI-NEXT:    csc cra, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 16(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -80
+; RV64IXCHERI-NEXT:    csc ra, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 16(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    mv s0, a1
-; RV64IXCHERI-NEXT:    cmove cs2, ca0
-; RV64IXCHERI-NEXT:    cld a1, 0(ca0)
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 8
-; RV64IXCHERI-NEXT:    csetbounds cs1, ca0, 8
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    cld a1, 0(a0)
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 8
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 8
 ; RV64IXCHERI-NEXT:    j .LBB205_2
 ; RV64IXCHERI-NEXT:  .LBB205_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB205_2 Depth=1
-; RV64IXCHERI-NEXT:    csd a1, 8(csp)
-; RV64IXCHERI-NEXT:    cmove ca0, cs2
-; RV64IXCHERI-NEXT:    cmove ca1, cs1
+; RV64IXCHERI-NEXT:    csd a1, 8(sp)
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    li a3, 0
 ; RV64IXCHERI-NEXT:    li a4, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV64IXCHERI-NEXT:    cld a1, 8(csp)
+; RV64IXCHERI-NEXT:    cld a1, 8(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB205_4
 ; RV64IXCHERI-NEXT:  .LBB205_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -13906,16 +13906,16 @@ define i64 @atomicrmw_min_i64_monotonic(i64 addrspace(200)* %a, i64 %b) nounwind
 ; RV64IXCHERI-NEXT:    j .LBB205_1
 ; RV64IXCHERI-NEXT:  .LBB205_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 80
+; RV64IXCHERI-NEXT:    clc ra, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 80
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_min_i64_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camomin.d a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camomin.d a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw min i64 addrspace(200)* %a, i64 %b monotonic
   ret i64 %1
@@ -13924,31 +13924,31 @@ define i64 @atomicrmw_min_i64_monotonic(i64 addrspace(200)* %a, i64 %b) nounwind
 define i64 @atomicrmw_min_i64_acquire(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_min_i64_acquire:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs3, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s3, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    mv s0, a2
-; RV32IXCHERI-NEXT:    mv s2, a1
-; RV32IXCHERI-NEXT:    cmove cs3, ca0
-; RV32IXCHERI-NEXT:    clw a1, 4(ca0)
-; RV32IXCHERI-NEXT:    clw a4, 0(ca0)
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 0
-; RV32IXCHERI-NEXT:    csetbounds cs1, ca0, 8
+; RV32IXCHERI-NEXT:    mv s1, a1
+; RV32IXCHERI-NEXT:    cmove s2, a0
+; RV32IXCHERI-NEXT:    clw a1, 4(a0)
+; RV32IXCHERI-NEXT:    clw a4, 0(a0)
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 0
+; RV32IXCHERI-NEXT:    csetbounds s3, a0, 8
 ; RV32IXCHERI-NEXT:    j .LBB206_2
 ; RV32IXCHERI-NEXT:  .LBB206_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB206_2 Depth=1
-; RV32IXCHERI-NEXT:    csw a4, 0(csp)
-; RV32IXCHERI-NEXT:    csw a1, 4(csp)
+; RV32IXCHERI-NEXT:    csw a4, 0(sp)
+; RV32IXCHERI-NEXT:    csw a1, 4(sp)
 ; RV32IXCHERI-NEXT:    li a4, 2
 ; RV32IXCHERI-NEXT:    li a5, 2
-; RV32IXCHERI-NEXT:    cmove ca0, cs3
-; RV32IXCHERI-NEXT:    cmove ca1, cs1
+; RV32IXCHERI-NEXT:    cmove a0, s2
+; RV32IXCHERI-NEXT:    cmove a1, s3
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV32IXCHERI-NEXT:    clw a1, 4(csp)
-; RV32IXCHERI-NEXT:    clw a4, 0(csp)
+; RV32IXCHERI-NEXT:    clw a1, 4(sp)
+; RV32IXCHERI-NEXT:    clw a4, 0(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB206_7
 ; RV32IXCHERI-NEXT:  .LBB206_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -13958,7 +13958,7 @@ define i64 @atomicrmw_min_i64_acquire(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-NEXT:    slt a0, s0, a1
 ; RV32IXCHERI-NEXT:    j .LBB206_5
 ; RV32IXCHERI-NEXT:  .LBB206_4: # in Loop: Header=BB206_2 Depth=1
-; RV32IXCHERI-NEXT:    sltu a0, s2, a4
+; RV32IXCHERI-NEXT:    sltu a0, s1, a4
 ; RV32IXCHERI-NEXT:  .LBB206_5: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB206_2 Depth=1
 ; RV32IXCHERI-NEXT:    mv a2, a4
@@ -13966,46 +13966,46 @@ define i64 @atomicrmw_min_i64_acquire(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-NEXT:    beqz a0, .LBB206_1
 ; RV32IXCHERI-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB206_2 Depth=1
-; RV32IXCHERI-NEXT:    mv a2, s2
+; RV32IXCHERI-NEXT:    mv a2, s1
 ; RV32IXCHERI-NEXT:    mv a3, s0
 ; RV32IXCHERI-NEXT:    j .LBB206_1
 ; RV32IXCHERI-NEXT:  .LBB206_7: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a4
-; RV32IXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs3, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s3, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_min_i64_acquire:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IAXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs3, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IAXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s3, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    mv s0, a2
-; RV32IAXCHERI-NEXT:    mv s2, a1
-; RV32IAXCHERI-NEXT:    cmove cs3, ca0
-; RV32IAXCHERI-NEXT:    clw a1, 4(ca0)
-; RV32IAXCHERI-NEXT:    clw a4, 0(ca0)
-; RV32IAXCHERI-NEXT:    cincoffset ca0, csp, 0
-; RV32IAXCHERI-NEXT:    csetbounds cs1, ca0, 8
+; RV32IAXCHERI-NEXT:    mv s1, a1
+; RV32IAXCHERI-NEXT:    cmove s2, a0
+; RV32IAXCHERI-NEXT:    clw a1, 4(a0)
+; RV32IAXCHERI-NEXT:    clw a4, 0(a0)
+; RV32IAXCHERI-NEXT:    cincoffset a0, sp, 0
+; RV32IAXCHERI-NEXT:    csetbounds s3, a0, 8
 ; RV32IAXCHERI-NEXT:    j .LBB206_2
 ; RV32IAXCHERI-NEXT:  .LBB206_1: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # in Loop: Header=BB206_2 Depth=1
-; RV32IAXCHERI-NEXT:    csw a4, 0(csp)
-; RV32IAXCHERI-NEXT:    csw a1, 4(csp)
+; RV32IAXCHERI-NEXT:    csw a4, 0(sp)
+; RV32IAXCHERI-NEXT:    csw a1, 4(sp)
 ; RV32IAXCHERI-NEXT:    li a4, 2
 ; RV32IAXCHERI-NEXT:    li a5, 2
-; RV32IAXCHERI-NEXT:    cmove ca0, cs3
-; RV32IAXCHERI-NEXT:    cmove ca1, cs1
+; RV32IAXCHERI-NEXT:    cmove a0, s2
+; RV32IAXCHERI-NEXT:    cmove a1, s3
 ; RV32IAXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV32IAXCHERI-NEXT:    clw a1, 4(csp)
-; RV32IAXCHERI-NEXT:    clw a4, 0(csp)
+; RV32IAXCHERI-NEXT:    clw a1, 4(sp)
+; RV32IAXCHERI-NEXT:    clw a4, 0(sp)
 ; RV32IAXCHERI-NEXT:    bnez a0, .LBB206_7
 ; RV32IAXCHERI-NEXT:  .LBB206_2: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -14015,7 +14015,7 @@ define i64 @atomicrmw_min_i64_acquire(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IAXCHERI-NEXT:    slt a0, s0, a1
 ; RV32IAXCHERI-NEXT:    j .LBB206_5
 ; RV32IAXCHERI-NEXT:  .LBB206_4: # in Loop: Header=BB206_2 Depth=1
-; RV32IAXCHERI-NEXT:    sltu a0, s2, a4
+; RV32IAXCHERI-NEXT:    sltu a0, s1, a4
 ; RV32IAXCHERI-NEXT:  .LBB206_5: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # in Loop: Header=BB206_2 Depth=1
 ; RV32IAXCHERI-NEXT:    mv a2, a4
@@ -14023,41 +14023,41 @@ define i64 @atomicrmw_min_i64_acquire(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IAXCHERI-NEXT:    beqz a0, .LBB206_1
 ; RV32IAXCHERI-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # in Loop: Header=BB206_2 Depth=1
-; RV32IAXCHERI-NEXT:    mv a2, s2
+; RV32IAXCHERI-NEXT:    mv a2, s1
 ; RV32IAXCHERI-NEXT:    mv a3, s0
 ; RV32IAXCHERI-NEXT:    j .LBB206_1
 ; RV32IAXCHERI-NEXT:  .LBB206_7: # %atomicrmw.end
 ; RV32IAXCHERI-NEXT:    mv a0, a4
-; RV32IAXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs3, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IAXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s3, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_min_i64_acquire:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -80
-; RV64IXCHERI-NEXT:    csc cra, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 16(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -80
+; RV64IXCHERI-NEXT:    csc ra, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 16(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    mv s0, a1
-; RV64IXCHERI-NEXT:    cmove cs2, ca0
-; RV64IXCHERI-NEXT:    cld a1, 0(ca0)
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 8
-; RV64IXCHERI-NEXT:    csetbounds cs1, ca0, 8
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    cld a1, 0(a0)
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 8
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 8
 ; RV64IXCHERI-NEXT:    j .LBB206_2
 ; RV64IXCHERI-NEXT:  .LBB206_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB206_2 Depth=1
-; RV64IXCHERI-NEXT:    csd a1, 8(csp)
+; RV64IXCHERI-NEXT:    csd a1, 8(sp)
 ; RV64IXCHERI-NEXT:    li a3, 2
 ; RV64IXCHERI-NEXT:    li a4, 2
-; RV64IXCHERI-NEXT:    cmove ca0, cs2
-; RV64IXCHERI-NEXT:    cmove ca1, cs1
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV64IXCHERI-NEXT:    cld a1, 8(csp)
+; RV64IXCHERI-NEXT:    cld a1, 8(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB206_4
 ; RV64IXCHERI-NEXT:  .LBB206_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -14069,16 +14069,16 @@ define i64 @atomicrmw_min_i64_acquire(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV64IXCHERI-NEXT:    j .LBB206_1
 ; RV64IXCHERI-NEXT:  .LBB206_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 80
+; RV64IXCHERI-NEXT:    clc ra, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 80
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_min_i64_acquire:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camomin.d.aq a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camomin.d.aq a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw min i64 addrspace(200)* %a, i64 %b acquire
   ret i64 %1
@@ -14087,31 +14087,31 @@ define i64 @atomicrmw_min_i64_acquire(i64 addrspace(200)* %a, i64 %b) nounwind {
 define i64 @atomicrmw_min_i64_release(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_min_i64_release:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs3, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s3, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    mv s0, a2
-; RV32IXCHERI-NEXT:    mv s2, a1
-; RV32IXCHERI-NEXT:    cmove cs3, ca0
-; RV32IXCHERI-NEXT:    clw a1, 4(ca0)
-; RV32IXCHERI-NEXT:    clw a4, 0(ca0)
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 0
-; RV32IXCHERI-NEXT:    csetbounds cs1, ca0, 8
+; RV32IXCHERI-NEXT:    mv s1, a1
+; RV32IXCHERI-NEXT:    cmove s2, a0
+; RV32IXCHERI-NEXT:    clw a1, 4(a0)
+; RV32IXCHERI-NEXT:    clw a4, 0(a0)
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 0
+; RV32IXCHERI-NEXT:    csetbounds s3, a0, 8
 ; RV32IXCHERI-NEXT:    j .LBB207_2
 ; RV32IXCHERI-NEXT:  .LBB207_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB207_2 Depth=1
-; RV32IXCHERI-NEXT:    csw a4, 0(csp)
-; RV32IXCHERI-NEXT:    csw a1, 4(csp)
+; RV32IXCHERI-NEXT:    csw a4, 0(sp)
+; RV32IXCHERI-NEXT:    csw a1, 4(sp)
 ; RV32IXCHERI-NEXT:    li a4, 3
-; RV32IXCHERI-NEXT:    cmove ca0, cs3
-; RV32IXCHERI-NEXT:    cmove ca1, cs1
+; RV32IXCHERI-NEXT:    cmove a0, s2
+; RV32IXCHERI-NEXT:    cmove a1, s3
 ; RV32IXCHERI-NEXT:    li a5, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV32IXCHERI-NEXT:    clw a1, 4(csp)
-; RV32IXCHERI-NEXT:    clw a4, 0(csp)
+; RV32IXCHERI-NEXT:    clw a1, 4(sp)
+; RV32IXCHERI-NEXT:    clw a4, 0(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB207_7
 ; RV32IXCHERI-NEXT:  .LBB207_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -14121,7 +14121,7 @@ define i64 @atomicrmw_min_i64_release(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-NEXT:    slt a0, s0, a1
 ; RV32IXCHERI-NEXT:    j .LBB207_5
 ; RV32IXCHERI-NEXT:  .LBB207_4: # in Loop: Header=BB207_2 Depth=1
-; RV32IXCHERI-NEXT:    sltu a0, s2, a4
+; RV32IXCHERI-NEXT:    sltu a0, s1, a4
 ; RV32IXCHERI-NEXT:  .LBB207_5: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB207_2 Depth=1
 ; RV32IXCHERI-NEXT:    mv a2, a4
@@ -14129,46 +14129,46 @@ define i64 @atomicrmw_min_i64_release(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-NEXT:    beqz a0, .LBB207_1
 ; RV32IXCHERI-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB207_2 Depth=1
-; RV32IXCHERI-NEXT:    mv a2, s2
+; RV32IXCHERI-NEXT:    mv a2, s1
 ; RV32IXCHERI-NEXT:    mv a3, s0
 ; RV32IXCHERI-NEXT:    j .LBB207_1
 ; RV32IXCHERI-NEXT:  .LBB207_7: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a4
-; RV32IXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs3, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s3, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_min_i64_release:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IAXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs3, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IAXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s3, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    mv s0, a2
-; RV32IAXCHERI-NEXT:    mv s2, a1
-; RV32IAXCHERI-NEXT:    cmove cs3, ca0
-; RV32IAXCHERI-NEXT:    clw a1, 4(ca0)
-; RV32IAXCHERI-NEXT:    clw a4, 0(ca0)
-; RV32IAXCHERI-NEXT:    cincoffset ca0, csp, 0
-; RV32IAXCHERI-NEXT:    csetbounds cs1, ca0, 8
+; RV32IAXCHERI-NEXT:    mv s1, a1
+; RV32IAXCHERI-NEXT:    cmove s2, a0
+; RV32IAXCHERI-NEXT:    clw a1, 4(a0)
+; RV32IAXCHERI-NEXT:    clw a4, 0(a0)
+; RV32IAXCHERI-NEXT:    cincoffset a0, sp, 0
+; RV32IAXCHERI-NEXT:    csetbounds s3, a0, 8
 ; RV32IAXCHERI-NEXT:    j .LBB207_2
 ; RV32IAXCHERI-NEXT:  .LBB207_1: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # in Loop: Header=BB207_2 Depth=1
-; RV32IAXCHERI-NEXT:    csw a4, 0(csp)
-; RV32IAXCHERI-NEXT:    csw a1, 4(csp)
+; RV32IAXCHERI-NEXT:    csw a4, 0(sp)
+; RV32IAXCHERI-NEXT:    csw a1, 4(sp)
 ; RV32IAXCHERI-NEXT:    li a4, 3
-; RV32IAXCHERI-NEXT:    cmove ca0, cs3
-; RV32IAXCHERI-NEXT:    cmove ca1, cs1
+; RV32IAXCHERI-NEXT:    cmove a0, s2
+; RV32IAXCHERI-NEXT:    cmove a1, s3
 ; RV32IAXCHERI-NEXT:    li a5, 0
 ; RV32IAXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV32IAXCHERI-NEXT:    clw a1, 4(csp)
-; RV32IAXCHERI-NEXT:    clw a4, 0(csp)
+; RV32IAXCHERI-NEXT:    clw a1, 4(sp)
+; RV32IAXCHERI-NEXT:    clw a4, 0(sp)
 ; RV32IAXCHERI-NEXT:    bnez a0, .LBB207_7
 ; RV32IAXCHERI-NEXT:  .LBB207_2: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -14178,7 +14178,7 @@ define i64 @atomicrmw_min_i64_release(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IAXCHERI-NEXT:    slt a0, s0, a1
 ; RV32IAXCHERI-NEXT:    j .LBB207_5
 ; RV32IAXCHERI-NEXT:  .LBB207_4: # in Loop: Header=BB207_2 Depth=1
-; RV32IAXCHERI-NEXT:    sltu a0, s2, a4
+; RV32IAXCHERI-NEXT:    sltu a0, s1, a4
 ; RV32IAXCHERI-NEXT:  .LBB207_5: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # in Loop: Header=BB207_2 Depth=1
 ; RV32IAXCHERI-NEXT:    mv a2, a4
@@ -14186,41 +14186,41 @@ define i64 @atomicrmw_min_i64_release(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IAXCHERI-NEXT:    beqz a0, .LBB207_1
 ; RV32IAXCHERI-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # in Loop: Header=BB207_2 Depth=1
-; RV32IAXCHERI-NEXT:    mv a2, s2
+; RV32IAXCHERI-NEXT:    mv a2, s1
 ; RV32IAXCHERI-NEXT:    mv a3, s0
 ; RV32IAXCHERI-NEXT:    j .LBB207_1
 ; RV32IAXCHERI-NEXT:  .LBB207_7: # %atomicrmw.end
 ; RV32IAXCHERI-NEXT:    mv a0, a4
-; RV32IAXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs3, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IAXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s3, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_min_i64_release:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -80
-; RV64IXCHERI-NEXT:    csc cra, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 16(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -80
+; RV64IXCHERI-NEXT:    csc ra, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 16(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    mv s0, a1
-; RV64IXCHERI-NEXT:    cmove cs2, ca0
-; RV64IXCHERI-NEXT:    cld a1, 0(ca0)
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 8
-; RV64IXCHERI-NEXT:    csetbounds cs1, ca0, 8
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    cld a1, 0(a0)
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 8
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 8
 ; RV64IXCHERI-NEXT:    j .LBB207_2
 ; RV64IXCHERI-NEXT:  .LBB207_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB207_2 Depth=1
-; RV64IXCHERI-NEXT:    csd a1, 8(csp)
+; RV64IXCHERI-NEXT:    csd a1, 8(sp)
 ; RV64IXCHERI-NEXT:    li a3, 3
-; RV64IXCHERI-NEXT:    cmove ca0, cs2
-; RV64IXCHERI-NEXT:    cmove ca1, cs1
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    li a4, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV64IXCHERI-NEXT:    cld a1, 8(csp)
+; RV64IXCHERI-NEXT:    cld a1, 8(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB207_4
 ; RV64IXCHERI-NEXT:  .LBB207_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -14232,16 +14232,16 @@ define i64 @atomicrmw_min_i64_release(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV64IXCHERI-NEXT:    j .LBB207_1
 ; RV64IXCHERI-NEXT:  .LBB207_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 80
+; RV64IXCHERI-NEXT:    clc ra, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 80
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_min_i64_release:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camomin.d.rl a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camomin.d.rl a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw min i64 addrspace(200)* %a, i64 %b release
   ret i64 %1
@@ -14250,31 +14250,31 @@ define i64 @atomicrmw_min_i64_release(i64 addrspace(200)* %a, i64 %b) nounwind {
 define i64 @atomicrmw_min_i64_acq_rel(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_min_i64_acq_rel:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs3, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s3, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    mv s0, a2
-; RV32IXCHERI-NEXT:    mv s2, a1
-; RV32IXCHERI-NEXT:    cmove cs3, ca0
-; RV32IXCHERI-NEXT:    clw a1, 4(ca0)
-; RV32IXCHERI-NEXT:    clw a4, 0(ca0)
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 0
-; RV32IXCHERI-NEXT:    csetbounds cs1, ca0, 8
+; RV32IXCHERI-NEXT:    mv s1, a1
+; RV32IXCHERI-NEXT:    cmove s2, a0
+; RV32IXCHERI-NEXT:    clw a1, 4(a0)
+; RV32IXCHERI-NEXT:    clw a4, 0(a0)
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 0
+; RV32IXCHERI-NEXT:    csetbounds s3, a0, 8
 ; RV32IXCHERI-NEXT:    j .LBB208_2
 ; RV32IXCHERI-NEXT:  .LBB208_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB208_2 Depth=1
-; RV32IXCHERI-NEXT:    csw a4, 0(csp)
-; RV32IXCHERI-NEXT:    csw a1, 4(csp)
+; RV32IXCHERI-NEXT:    csw a4, 0(sp)
+; RV32IXCHERI-NEXT:    csw a1, 4(sp)
 ; RV32IXCHERI-NEXT:    li a4, 4
 ; RV32IXCHERI-NEXT:    li a5, 2
-; RV32IXCHERI-NEXT:    cmove ca0, cs3
-; RV32IXCHERI-NEXT:    cmove ca1, cs1
+; RV32IXCHERI-NEXT:    cmove a0, s2
+; RV32IXCHERI-NEXT:    cmove a1, s3
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV32IXCHERI-NEXT:    clw a1, 4(csp)
-; RV32IXCHERI-NEXT:    clw a4, 0(csp)
+; RV32IXCHERI-NEXT:    clw a1, 4(sp)
+; RV32IXCHERI-NEXT:    clw a4, 0(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB208_7
 ; RV32IXCHERI-NEXT:  .LBB208_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -14284,7 +14284,7 @@ define i64 @atomicrmw_min_i64_acq_rel(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-NEXT:    slt a0, s0, a1
 ; RV32IXCHERI-NEXT:    j .LBB208_5
 ; RV32IXCHERI-NEXT:  .LBB208_4: # in Loop: Header=BB208_2 Depth=1
-; RV32IXCHERI-NEXT:    sltu a0, s2, a4
+; RV32IXCHERI-NEXT:    sltu a0, s1, a4
 ; RV32IXCHERI-NEXT:  .LBB208_5: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB208_2 Depth=1
 ; RV32IXCHERI-NEXT:    mv a2, a4
@@ -14292,46 +14292,46 @@ define i64 @atomicrmw_min_i64_acq_rel(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-NEXT:    beqz a0, .LBB208_1
 ; RV32IXCHERI-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB208_2 Depth=1
-; RV32IXCHERI-NEXT:    mv a2, s2
+; RV32IXCHERI-NEXT:    mv a2, s1
 ; RV32IXCHERI-NEXT:    mv a3, s0
 ; RV32IXCHERI-NEXT:    j .LBB208_1
 ; RV32IXCHERI-NEXT:  .LBB208_7: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a4
-; RV32IXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs3, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s3, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_min_i64_acq_rel:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IAXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs3, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IAXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s3, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    mv s0, a2
-; RV32IAXCHERI-NEXT:    mv s2, a1
-; RV32IAXCHERI-NEXT:    cmove cs3, ca0
-; RV32IAXCHERI-NEXT:    clw a1, 4(ca0)
-; RV32IAXCHERI-NEXT:    clw a4, 0(ca0)
-; RV32IAXCHERI-NEXT:    cincoffset ca0, csp, 0
-; RV32IAXCHERI-NEXT:    csetbounds cs1, ca0, 8
+; RV32IAXCHERI-NEXT:    mv s1, a1
+; RV32IAXCHERI-NEXT:    cmove s2, a0
+; RV32IAXCHERI-NEXT:    clw a1, 4(a0)
+; RV32IAXCHERI-NEXT:    clw a4, 0(a0)
+; RV32IAXCHERI-NEXT:    cincoffset a0, sp, 0
+; RV32IAXCHERI-NEXT:    csetbounds s3, a0, 8
 ; RV32IAXCHERI-NEXT:    j .LBB208_2
 ; RV32IAXCHERI-NEXT:  .LBB208_1: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # in Loop: Header=BB208_2 Depth=1
-; RV32IAXCHERI-NEXT:    csw a4, 0(csp)
-; RV32IAXCHERI-NEXT:    csw a1, 4(csp)
+; RV32IAXCHERI-NEXT:    csw a4, 0(sp)
+; RV32IAXCHERI-NEXT:    csw a1, 4(sp)
 ; RV32IAXCHERI-NEXT:    li a4, 4
 ; RV32IAXCHERI-NEXT:    li a5, 2
-; RV32IAXCHERI-NEXT:    cmove ca0, cs3
-; RV32IAXCHERI-NEXT:    cmove ca1, cs1
+; RV32IAXCHERI-NEXT:    cmove a0, s2
+; RV32IAXCHERI-NEXT:    cmove a1, s3
 ; RV32IAXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV32IAXCHERI-NEXT:    clw a1, 4(csp)
-; RV32IAXCHERI-NEXT:    clw a4, 0(csp)
+; RV32IAXCHERI-NEXT:    clw a1, 4(sp)
+; RV32IAXCHERI-NEXT:    clw a4, 0(sp)
 ; RV32IAXCHERI-NEXT:    bnez a0, .LBB208_7
 ; RV32IAXCHERI-NEXT:  .LBB208_2: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -14341,7 +14341,7 @@ define i64 @atomicrmw_min_i64_acq_rel(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IAXCHERI-NEXT:    slt a0, s0, a1
 ; RV32IAXCHERI-NEXT:    j .LBB208_5
 ; RV32IAXCHERI-NEXT:  .LBB208_4: # in Loop: Header=BB208_2 Depth=1
-; RV32IAXCHERI-NEXT:    sltu a0, s2, a4
+; RV32IAXCHERI-NEXT:    sltu a0, s1, a4
 ; RV32IAXCHERI-NEXT:  .LBB208_5: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # in Loop: Header=BB208_2 Depth=1
 ; RV32IAXCHERI-NEXT:    mv a2, a4
@@ -14349,41 +14349,41 @@ define i64 @atomicrmw_min_i64_acq_rel(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IAXCHERI-NEXT:    beqz a0, .LBB208_1
 ; RV32IAXCHERI-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # in Loop: Header=BB208_2 Depth=1
-; RV32IAXCHERI-NEXT:    mv a2, s2
+; RV32IAXCHERI-NEXT:    mv a2, s1
 ; RV32IAXCHERI-NEXT:    mv a3, s0
 ; RV32IAXCHERI-NEXT:    j .LBB208_1
 ; RV32IAXCHERI-NEXT:  .LBB208_7: # %atomicrmw.end
 ; RV32IAXCHERI-NEXT:    mv a0, a4
-; RV32IAXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs3, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IAXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s3, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_min_i64_acq_rel:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -80
-; RV64IXCHERI-NEXT:    csc cra, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 16(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -80
+; RV64IXCHERI-NEXT:    csc ra, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 16(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    mv s0, a1
-; RV64IXCHERI-NEXT:    cmove cs2, ca0
-; RV64IXCHERI-NEXT:    cld a1, 0(ca0)
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 8
-; RV64IXCHERI-NEXT:    csetbounds cs1, ca0, 8
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    cld a1, 0(a0)
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 8
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 8
 ; RV64IXCHERI-NEXT:    j .LBB208_2
 ; RV64IXCHERI-NEXT:  .LBB208_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB208_2 Depth=1
-; RV64IXCHERI-NEXT:    csd a1, 8(csp)
+; RV64IXCHERI-NEXT:    csd a1, 8(sp)
 ; RV64IXCHERI-NEXT:    li a3, 4
 ; RV64IXCHERI-NEXT:    li a4, 2
-; RV64IXCHERI-NEXT:    cmove ca0, cs2
-; RV64IXCHERI-NEXT:    cmove ca1, cs1
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV64IXCHERI-NEXT:    cld a1, 8(csp)
+; RV64IXCHERI-NEXT:    cld a1, 8(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB208_4
 ; RV64IXCHERI-NEXT:  .LBB208_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -14395,16 +14395,16 @@ define i64 @atomicrmw_min_i64_acq_rel(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV64IXCHERI-NEXT:    j .LBB208_1
 ; RV64IXCHERI-NEXT:  .LBB208_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 80
+; RV64IXCHERI-NEXT:    clc ra, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 80
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_min_i64_acq_rel:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camomin.d.aqrl a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camomin.d.aqrl a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw min i64 addrspace(200)* %a, i64 %b acq_rel
   ret i64 %1
@@ -14413,31 +14413,31 @@ define i64 @atomicrmw_min_i64_acq_rel(i64 addrspace(200)* %a, i64 %b) nounwind {
 define i64 @atomicrmw_min_i64_seq_cst(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_min_i64_seq_cst:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs3, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s3, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    mv s0, a2
-; RV32IXCHERI-NEXT:    mv s2, a1
-; RV32IXCHERI-NEXT:    cmove cs3, ca0
-; RV32IXCHERI-NEXT:    clw a1, 4(ca0)
-; RV32IXCHERI-NEXT:    clw a4, 0(ca0)
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 0
-; RV32IXCHERI-NEXT:    csetbounds cs1, ca0, 8
+; RV32IXCHERI-NEXT:    mv s1, a1
+; RV32IXCHERI-NEXT:    cmove s2, a0
+; RV32IXCHERI-NEXT:    clw a1, 4(a0)
+; RV32IXCHERI-NEXT:    clw a4, 0(a0)
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 0
+; RV32IXCHERI-NEXT:    csetbounds s3, a0, 8
 ; RV32IXCHERI-NEXT:    j .LBB209_2
 ; RV32IXCHERI-NEXT:  .LBB209_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB209_2 Depth=1
-; RV32IXCHERI-NEXT:    csw a4, 0(csp)
-; RV32IXCHERI-NEXT:    csw a1, 4(csp)
+; RV32IXCHERI-NEXT:    csw a4, 0(sp)
+; RV32IXCHERI-NEXT:    csw a1, 4(sp)
 ; RV32IXCHERI-NEXT:    li a4, 5
 ; RV32IXCHERI-NEXT:    li a5, 5
-; RV32IXCHERI-NEXT:    cmove ca0, cs3
-; RV32IXCHERI-NEXT:    cmove ca1, cs1
+; RV32IXCHERI-NEXT:    cmove a0, s2
+; RV32IXCHERI-NEXT:    cmove a1, s3
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV32IXCHERI-NEXT:    clw a1, 4(csp)
-; RV32IXCHERI-NEXT:    clw a4, 0(csp)
+; RV32IXCHERI-NEXT:    clw a1, 4(sp)
+; RV32IXCHERI-NEXT:    clw a4, 0(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB209_7
 ; RV32IXCHERI-NEXT:  .LBB209_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -14447,7 +14447,7 @@ define i64 @atomicrmw_min_i64_seq_cst(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-NEXT:    slt a0, s0, a1
 ; RV32IXCHERI-NEXT:    j .LBB209_5
 ; RV32IXCHERI-NEXT:  .LBB209_4: # in Loop: Header=BB209_2 Depth=1
-; RV32IXCHERI-NEXT:    sltu a0, s2, a4
+; RV32IXCHERI-NEXT:    sltu a0, s1, a4
 ; RV32IXCHERI-NEXT:  .LBB209_5: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB209_2 Depth=1
 ; RV32IXCHERI-NEXT:    mv a2, a4
@@ -14455,46 +14455,46 @@ define i64 @atomicrmw_min_i64_seq_cst(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-NEXT:    beqz a0, .LBB209_1
 ; RV32IXCHERI-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB209_2 Depth=1
-; RV32IXCHERI-NEXT:    mv a2, s2
+; RV32IXCHERI-NEXT:    mv a2, s1
 ; RV32IXCHERI-NEXT:    mv a3, s0
 ; RV32IXCHERI-NEXT:    j .LBB209_1
 ; RV32IXCHERI-NEXT:  .LBB209_7: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a4
-; RV32IXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs3, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s3, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_min_i64_seq_cst:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IAXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs3, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IAXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s3, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    mv s0, a2
-; RV32IAXCHERI-NEXT:    mv s2, a1
-; RV32IAXCHERI-NEXT:    cmove cs3, ca0
-; RV32IAXCHERI-NEXT:    clw a1, 4(ca0)
-; RV32IAXCHERI-NEXT:    clw a4, 0(ca0)
-; RV32IAXCHERI-NEXT:    cincoffset ca0, csp, 0
-; RV32IAXCHERI-NEXT:    csetbounds cs1, ca0, 8
+; RV32IAXCHERI-NEXT:    mv s1, a1
+; RV32IAXCHERI-NEXT:    cmove s2, a0
+; RV32IAXCHERI-NEXT:    clw a1, 4(a0)
+; RV32IAXCHERI-NEXT:    clw a4, 0(a0)
+; RV32IAXCHERI-NEXT:    cincoffset a0, sp, 0
+; RV32IAXCHERI-NEXT:    csetbounds s3, a0, 8
 ; RV32IAXCHERI-NEXT:    j .LBB209_2
 ; RV32IAXCHERI-NEXT:  .LBB209_1: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # in Loop: Header=BB209_2 Depth=1
-; RV32IAXCHERI-NEXT:    csw a4, 0(csp)
-; RV32IAXCHERI-NEXT:    csw a1, 4(csp)
+; RV32IAXCHERI-NEXT:    csw a4, 0(sp)
+; RV32IAXCHERI-NEXT:    csw a1, 4(sp)
 ; RV32IAXCHERI-NEXT:    li a4, 5
 ; RV32IAXCHERI-NEXT:    li a5, 5
-; RV32IAXCHERI-NEXT:    cmove ca0, cs3
-; RV32IAXCHERI-NEXT:    cmove ca1, cs1
+; RV32IAXCHERI-NEXT:    cmove a0, s2
+; RV32IAXCHERI-NEXT:    cmove a1, s3
 ; RV32IAXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV32IAXCHERI-NEXT:    clw a1, 4(csp)
-; RV32IAXCHERI-NEXT:    clw a4, 0(csp)
+; RV32IAXCHERI-NEXT:    clw a1, 4(sp)
+; RV32IAXCHERI-NEXT:    clw a4, 0(sp)
 ; RV32IAXCHERI-NEXT:    bnez a0, .LBB209_7
 ; RV32IAXCHERI-NEXT:  .LBB209_2: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -14504,7 +14504,7 @@ define i64 @atomicrmw_min_i64_seq_cst(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IAXCHERI-NEXT:    slt a0, s0, a1
 ; RV32IAXCHERI-NEXT:    j .LBB209_5
 ; RV32IAXCHERI-NEXT:  .LBB209_4: # in Loop: Header=BB209_2 Depth=1
-; RV32IAXCHERI-NEXT:    sltu a0, s2, a4
+; RV32IAXCHERI-NEXT:    sltu a0, s1, a4
 ; RV32IAXCHERI-NEXT:  .LBB209_5: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # in Loop: Header=BB209_2 Depth=1
 ; RV32IAXCHERI-NEXT:    mv a2, a4
@@ -14512,41 +14512,41 @@ define i64 @atomicrmw_min_i64_seq_cst(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IAXCHERI-NEXT:    beqz a0, .LBB209_1
 ; RV32IAXCHERI-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # in Loop: Header=BB209_2 Depth=1
-; RV32IAXCHERI-NEXT:    mv a2, s2
+; RV32IAXCHERI-NEXT:    mv a2, s1
 ; RV32IAXCHERI-NEXT:    mv a3, s0
 ; RV32IAXCHERI-NEXT:    j .LBB209_1
 ; RV32IAXCHERI-NEXT:  .LBB209_7: # %atomicrmw.end
 ; RV32IAXCHERI-NEXT:    mv a0, a4
-; RV32IAXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs3, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IAXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s3, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_min_i64_seq_cst:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -80
-; RV64IXCHERI-NEXT:    csc cra, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 16(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -80
+; RV64IXCHERI-NEXT:    csc ra, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 16(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    mv s0, a1
-; RV64IXCHERI-NEXT:    cmove cs2, ca0
-; RV64IXCHERI-NEXT:    cld a1, 0(ca0)
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 8
-; RV64IXCHERI-NEXT:    csetbounds cs1, ca0, 8
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    cld a1, 0(a0)
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 8
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 8
 ; RV64IXCHERI-NEXT:    j .LBB209_2
 ; RV64IXCHERI-NEXT:  .LBB209_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB209_2 Depth=1
-; RV64IXCHERI-NEXT:    csd a1, 8(csp)
+; RV64IXCHERI-NEXT:    csd a1, 8(sp)
 ; RV64IXCHERI-NEXT:    li a3, 5
 ; RV64IXCHERI-NEXT:    li a4, 5
-; RV64IXCHERI-NEXT:    cmove ca0, cs2
-; RV64IXCHERI-NEXT:    cmove ca1, cs1
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV64IXCHERI-NEXT:    cld a1, 8(csp)
+; RV64IXCHERI-NEXT:    cld a1, 8(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB209_4
 ; RV64IXCHERI-NEXT:  .LBB209_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -14558,16 +14558,16 @@ define i64 @atomicrmw_min_i64_seq_cst(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV64IXCHERI-NEXT:    j .LBB209_1
 ; RV64IXCHERI-NEXT:  .LBB209_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 80
+; RV64IXCHERI-NEXT:    clc ra, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 80
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_min_i64_seq_cst:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camomin.d.aqrl a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camomin.d.aqrl a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw min i64 addrspace(200)* %a, i64 %b seq_cst
   ret i64 %1
@@ -14576,31 +14576,31 @@ define i64 @atomicrmw_min_i64_seq_cst(i64 addrspace(200)* %a, i64 %b) nounwind {
 define i64 @atomicrmw_umax_i64_monotonic(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_umax_i64_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs3, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s3, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    mv s0, a2
-; RV32IXCHERI-NEXT:    mv s2, a1
-; RV32IXCHERI-NEXT:    cmove cs3, ca0
-; RV32IXCHERI-NEXT:    clw a1, 4(ca0)
-; RV32IXCHERI-NEXT:    clw a4, 0(ca0)
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 0
-; RV32IXCHERI-NEXT:    csetbounds cs1, ca0, 8
+; RV32IXCHERI-NEXT:    mv s1, a1
+; RV32IXCHERI-NEXT:    cmove s2, a0
+; RV32IXCHERI-NEXT:    clw a1, 4(a0)
+; RV32IXCHERI-NEXT:    clw a4, 0(a0)
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 0
+; RV32IXCHERI-NEXT:    csetbounds s3, a0, 8
 ; RV32IXCHERI-NEXT:    j .LBB210_2
 ; RV32IXCHERI-NEXT:  .LBB210_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB210_2 Depth=1
-; RV32IXCHERI-NEXT:    csw a4, 0(csp)
-; RV32IXCHERI-NEXT:    csw a1, 4(csp)
-; RV32IXCHERI-NEXT:    cmove ca0, cs3
-; RV32IXCHERI-NEXT:    cmove ca1, cs1
+; RV32IXCHERI-NEXT:    csw a4, 0(sp)
+; RV32IXCHERI-NEXT:    csw a1, 4(sp)
+; RV32IXCHERI-NEXT:    cmove a0, s2
+; RV32IXCHERI-NEXT:    cmove a1, s3
 ; RV32IXCHERI-NEXT:    li a4, 0
 ; RV32IXCHERI-NEXT:    li a5, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV32IXCHERI-NEXT:    clw a1, 4(csp)
-; RV32IXCHERI-NEXT:    clw a4, 0(csp)
+; RV32IXCHERI-NEXT:    clw a1, 4(sp)
+; RV32IXCHERI-NEXT:    clw a4, 0(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB210_7
 ; RV32IXCHERI-NEXT:  .LBB210_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -14610,7 +14610,7 @@ define i64 @atomicrmw_umax_i64_monotonic(i64 addrspace(200)* %a, i64 %b) nounwin
 ; RV32IXCHERI-NEXT:    sltu a0, s0, a1
 ; RV32IXCHERI-NEXT:    j .LBB210_5
 ; RV32IXCHERI-NEXT:  .LBB210_4: # in Loop: Header=BB210_2 Depth=1
-; RV32IXCHERI-NEXT:    sltu a0, s2, a4
+; RV32IXCHERI-NEXT:    sltu a0, s1, a4
 ; RV32IXCHERI-NEXT:  .LBB210_5: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB210_2 Depth=1
 ; RV32IXCHERI-NEXT:    mv a2, a4
@@ -14618,46 +14618,46 @@ define i64 @atomicrmw_umax_i64_monotonic(i64 addrspace(200)* %a, i64 %b) nounwin
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB210_1
 ; RV32IXCHERI-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB210_2 Depth=1
-; RV32IXCHERI-NEXT:    mv a2, s2
+; RV32IXCHERI-NEXT:    mv a2, s1
 ; RV32IXCHERI-NEXT:    mv a3, s0
 ; RV32IXCHERI-NEXT:    j .LBB210_1
 ; RV32IXCHERI-NEXT:  .LBB210_7: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a4
-; RV32IXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs3, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s3, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_umax_i64_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IAXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs3, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IAXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s3, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    mv s0, a2
-; RV32IAXCHERI-NEXT:    mv s2, a1
-; RV32IAXCHERI-NEXT:    cmove cs3, ca0
-; RV32IAXCHERI-NEXT:    clw a1, 4(ca0)
-; RV32IAXCHERI-NEXT:    clw a4, 0(ca0)
-; RV32IAXCHERI-NEXT:    cincoffset ca0, csp, 0
-; RV32IAXCHERI-NEXT:    csetbounds cs1, ca0, 8
+; RV32IAXCHERI-NEXT:    mv s1, a1
+; RV32IAXCHERI-NEXT:    cmove s2, a0
+; RV32IAXCHERI-NEXT:    clw a1, 4(a0)
+; RV32IAXCHERI-NEXT:    clw a4, 0(a0)
+; RV32IAXCHERI-NEXT:    cincoffset a0, sp, 0
+; RV32IAXCHERI-NEXT:    csetbounds s3, a0, 8
 ; RV32IAXCHERI-NEXT:    j .LBB210_2
 ; RV32IAXCHERI-NEXT:  .LBB210_1: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # in Loop: Header=BB210_2 Depth=1
-; RV32IAXCHERI-NEXT:    csw a4, 0(csp)
-; RV32IAXCHERI-NEXT:    csw a1, 4(csp)
-; RV32IAXCHERI-NEXT:    cmove ca0, cs3
-; RV32IAXCHERI-NEXT:    cmove ca1, cs1
+; RV32IAXCHERI-NEXT:    csw a4, 0(sp)
+; RV32IAXCHERI-NEXT:    csw a1, 4(sp)
+; RV32IAXCHERI-NEXT:    cmove a0, s2
+; RV32IAXCHERI-NEXT:    cmove a1, s3
 ; RV32IAXCHERI-NEXT:    li a4, 0
 ; RV32IAXCHERI-NEXT:    li a5, 0
 ; RV32IAXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV32IAXCHERI-NEXT:    clw a1, 4(csp)
-; RV32IAXCHERI-NEXT:    clw a4, 0(csp)
+; RV32IAXCHERI-NEXT:    clw a1, 4(sp)
+; RV32IAXCHERI-NEXT:    clw a4, 0(sp)
 ; RV32IAXCHERI-NEXT:    bnez a0, .LBB210_7
 ; RV32IAXCHERI-NEXT:  .LBB210_2: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -14667,7 +14667,7 @@ define i64 @atomicrmw_umax_i64_monotonic(i64 addrspace(200)* %a, i64 %b) nounwin
 ; RV32IAXCHERI-NEXT:    sltu a0, s0, a1
 ; RV32IAXCHERI-NEXT:    j .LBB210_5
 ; RV32IAXCHERI-NEXT:  .LBB210_4: # in Loop: Header=BB210_2 Depth=1
-; RV32IAXCHERI-NEXT:    sltu a0, s2, a4
+; RV32IAXCHERI-NEXT:    sltu a0, s1, a4
 ; RV32IAXCHERI-NEXT:  .LBB210_5: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # in Loop: Header=BB210_2 Depth=1
 ; RV32IAXCHERI-NEXT:    mv a2, a4
@@ -14675,41 +14675,41 @@ define i64 @atomicrmw_umax_i64_monotonic(i64 addrspace(200)* %a, i64 %b) nounwin
 ; RV32IAXCHERI-NEXT:    bnez a0, .LBB210_1
 ; RV32IAXCHERI-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # in Loop: Header=BB210_2 Depth=1
-; RV32IAXCHERI-NEXT:    mv a2, s2
+; RV32IAXCHERI-NEXT:    mv a2, s1
 ; RV32IAXCHERI-NEXT:    mv a3, s0
 ; RV32IAXCHERI-NEXT:    j .LBB210_1
 ; RV32IAXCHERI-NEXT:  .LBB210_7: # %atomicrmw.end
 ; RV32IAXCHERI-NEXT:    mv a0, a4
-; RV32IAXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs3, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IAXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s3, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_umax_i64_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -80
-; RV64IXCHERI-NEXT:    csc cra, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 16(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -80
+; RV64IXCHERI-NEXT:    csc ra, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 16(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    mv s0, a1
-; RV64IXCHERI-NEXT:    cmove cs2, ca0
-; RV64IXCHERI-NEXT:    cld a1, 0(ca0)
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 8
-; RV64IXCHERI-NEXT:    csetbounds cs1, ca0, 8
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    cld a1, 0(a0)
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 8
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 8
 ; RV64IXCHERI-NEXT:    j .LBB210_2
 ; RV64IXCHERI-NEXT:  .LBB210_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB210_2 Depth=1
-; RV64IXCHERI-NEXT:    csd a1, 8(csp)
-; RV64IXCHERI-NEXT:    cmove ca0, cs2
-; RV64IXCHERI-NEXT:    cmove ca1, cs1
+; RV64IXCHERI-NEXT:    csd a1, 8(sp)
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    li a3, 0
 ; RV64IXCHERI-NEXT:    li a4, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV64IXCHERI-NEXT:    cld a1, 8(csp)
+; RV64IXCHERI-NEXT:    cld a1, 8(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB210_4
 ; RV64IXCHERI-NEXT:  .LBB210_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -14721,16 +14721,16 @@ define i64 @atomicrmw_umax_i64_monotonic(i64 addrspace(200)* %a, i64 %b) nounwin
 ; RV64IXCHERI-NEXT:    j .LBB210_1
 ; RV64IXCHERI-NEXT:  .LBB210_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 80
+; RV64IXCHERI-NEXT:    clc ra, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 80
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_umax_i64_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camomaxu.d a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camomaxu.d a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw umax i64 addrspace(200)* %a, i64 %b monotonic
   ret i64 %1
@@ -14739,31 +14739,31 @@ define i64 @atomicrmw_umax_i64_monotonic(i64 addrspace(200)* %a, i64 %b) nounwin
 define i64 @atomicrmw_umax_i64_acquire(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_umax_i64_acquire:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs3, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s3, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    mv s0, a2
-; RV32IXCHERI-NEXT:    mv s2, a1
-; RV32IXCHERI-NEXT:    cmove cs3, ca0
-; RV32IXCHERI-NEXT:    clw a1, 4(ca0)
-; RV32IXCHERI-NEXT:    clw a4, 0(ca0)
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 0
-; RV32IXCHERI-NEXT:    csetbounds cs1, ca0, 8
+; RV32IXCHERI-NEXT:    mv s1, a1
+; RV32IXCHERI-NEXT:    cmove s2, a0
+; RV32IXCHERI-NEXT:    clw a1, 4(a0)
+; RV32IXCHERI-NEXT:    clw a4, 0(a0)
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 0
+; RV32IXCHERI-NEXT:    csetbounds s3, a0, 8
 ; RV32IXCHERI-NEXT:    j .LBB211_2
 ; RV32IXCHERI-NEXT:  .LBB211_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB211_2 Depth=1
-; RV32IXCHERI-NEXT:    csw a4, 0(csp)
-; RV32IXCHERI-NEXT:    csw a1, 4(csp)
+; RV32IXCHERI-NEXT:    csw a4, 0(sp)
+; RV32IXCHERI-NEXT:    csw a1, 4(sp)
 ; RV32IXCHERI-NEXT:    li a4, 2
 ; RV32IXCHERI-NEXT:    li a5, 2
-; RV32IXCHERI-NEXT:    cmove ca0, cs3
-; RV32IXCHERI-NEXT:    cmove ca1, cs1
+; RV32IXCHERI-NEXT:    cmove a0, s2
+; RV32IXCHERI-NEXT:    cmove a1, s3
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV32IXCHERI-NEXT:    clw a1, 4(csp)
-; RV32IXCHERI-NEXT:    clw a4, 0(csp)
+; RV32IXCHERI-NEXT:    clw a1, 4(sp)
+; RV32IXCHERI-NEXT:    clw a4, 0(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB211_7
 ; RV32IXCHERI-NEXT:  .LBB211_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -14773,7 +14773,7 @@ define i64 @atomicrmw_umax_i64_acquire(i64 addrspace(200)* %a, i64 %b) nounwind
 ; RV32IXCHERI-NEXT:    sltu a0, s0, a1
 ; RV32IXCHERI-NEXT:    j .LBB211_5
 ; RV32IXCHERI-NEXT:  .LBB211_4: # in Loop: Header=BB211_2 Depth=1
-; RV32IXCHERI-NEXT:    sltu a0, s2, a4
+; RV32IXCHERI-NEXT:    sltu a0, s1, a4
 ; RV32IXCHERI-NEXT:  .LBB211_5: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB211_2 Depth=1
 ; RV32IXCHERI-NEXT:    mv a2, a4
@@ -14781,46 +14781,46 @@ define i64 @atomicrmw_umax_i64_acquire(i64 addrspace(200)* %a, i64 %b) nounwind
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB211_1
 ; RV32IXCHERI-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB211_2 Depth=1
-; RV32IXCHERI-NEXT:    mv a2, s2
+; RV32IXCHERI-NEXT:    mv a2, s1
 ; RV32IXCHERI-NEXT:    mv a3, s0
 ; RV32IXCHERI-NEXT:    j .LBB211_1
 ; RV32IXCHERI-NEXT:  .LBB211_7: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a4
-; RV32IXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs3, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s3, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_umax_i64_acquire:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IAXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs3, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IAXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s3, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    mv s0, a2
-; RV32IAXCHERI-NEXT:    mv s2, a1
-; RV32IAXCHERI-NEXT:    cmove cs3, ca0
-; RV32IAXCHERI-NEXT:    clw a1, 4(ca0)
-; RV32IAXCHERI-NEXT:    clw a4, 0(ca0)
-; RV32IAXCHERI-NEXT:    cincoffset ca0, csp, 0
-; RV32IAXCHERI-NEXT:    csetbounds cs1, ca0, 8
+; RV32IAXCHERI-NEXT:    mv s1, a1
+; RV32IAXCHERI-NEXT:    cmove s2, a0
+; RV32IAXCHERI-NEXT:    clw a1, 4(a0)
+; RV32IAXCHERI-NEXT:    clw a4, 0(a0)
+; RV32IAXCHERI-NEXT:    cincoffset a0, sp, 0
+; RV32IAXCHERI-NEXT:    csetbounds s3, a0, 8
 ; RV32IAXCHERI-NEXT:    j .LBB211_2
 ; RV32IAXCHERI-NEXT:  .LBB211_1: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # in Loop: Header=BB211_2 Depth=1
-; RV32IAXCHERI-NEXT:    csw a4, 0(csp)
-; RV32IAXCHERI-NEXT:    csw a1, 4(csp)
+; RV32IAXCHERI-NEXT:    csw a4, 0(sp)
+; RV32IAXCHERI-NEXT:    csw a1, 4(sp)
 ; RV32IAXCHERI-NEXT:    li a4, 2
 ; RV32IAXCHERI-NEXT:    li a5, 2
-; RV32IAXCHERI-NEXT:    cmove ca0, cs3
-; RV32IAXCHERI-NEXT:    cmove ca1, cs1
+; RV32IAXCHERI-NEXT:    cmove a0, s2
+; RV32IAXCHERI-NEXT:    cmove a1, s3
 ; RV32IAXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV32IAXCHERI-NEXT:    clw a1, 4(csp)
-; RV32IAXCHERI-NEXT:    clw a4, 0(csp)
+; RV32IAXCHERI-NEXT:    clw a1, 4(sp)
+; RV32IAXCHERI-NEXT:    clw a4, 0(sp)
 ; RV32IAXCHERI-NEXT:    bnez a0, .LBB211_7
 ; RV32IAXCHERI-NEXT:  .LBB211_2: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -14830,7 +14830,7 @@ define i64 @atomicrmw_umax_i64_acquire(i64 addrspace(200)* %a, i64 %b) nounwind
 ; RV32IAXCHERI-NEXT:    sltu a0, s0, a1
 ; RV32IAXCHERI-NEXT:    j .LBB211_5
 ; RV32IAXCHERI-NEXT:  .LBB211_4: # in Loop: Header=BB211_2 Depth=1
-; RV32IAXCHERI-NEXT:    sltu a0, s2, a4
+; RV32IAXCHERI-NEXT:    sltu a0, s1, a4
 ; RV32IAXCHERI-NEXT:  .LBB211_5: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # in Loop: Header=BB211_2 Depth=1
 ; RV32IAXCHERI-NEXT:    mv a2, a4
@@ -14838,41 +14838,41 @@ define i64 @atomicrmw_umax_i64_acquire(i64 addrspace(200)* %a, i64 %b) nounwind
 ; RV32IAXCHERI-NEXT:    bnez a0, .LBB211_1
 ; RV32IAXCHERI-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # in Loop: Header=BB211_2 Depth=1
-; RV32IAXCHERI-NEXT:    mv a2, s2
+; RV32IAXCHERI-NEXT:    mv a2, s1
 ; RV32IAXCHERI-NEXT:    mv a3, s0
 ; RV32IAXCHERI-NEXT:    j .LBB211_1
 ; RV32IAXCHERI-NEXT:  .LBB211_7: # %atomicrmw.end
 ; RV32IAXCHERI-NEXT:    mv a0, a4
-; RV32IAXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs3, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IAXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s3, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_umax_i64_acquire:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -80
-; RV64IXCHERI-NEXT:    csc cra, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 16(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -80
+; RV64IXCHERI-NEXT:    csc ra, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 16(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    mv s0, a1
-; RV64IXCHERI-NEXT:    cmove cs2, ca0
-; RV64IXCHERI-NEXT:    cld a1, 0(ca0)
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 8
-; RV64IXCHERI-NEXT:    csetbounds cs1, ca0, 8
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    cld a1, 0(a0)
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 8
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 8
 ; RV64IXCHERI-NEXT:    j .LBB211_2
 ; RV64IXCHERI-NEXT:  .LBB211_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB211_2 Depth=1
-; RV64IXCHERI-NEXT:    csd a1, 8(csp)
+; RV64IXCHERI-NEXT:    csd a1, 8(sp)
 ; RV64IXCHERI-NEXT:    li a3, 2
 ; RV64IXCHERI-NEXT:    li a4, 2
-; RV64IXCHERI-NEXT:    cmove ca0, cs2
-; RV64IXCHERI-NEXT:    cmove ca1, cs1
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV64IXCHERI-NEXT:    cld a1, 8(csp)
+; RV64IXCHERI-NEXT:    cld a1, 8(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB211_4
 ; RV64IXCHERI-NEXT:  .LBB211_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -14884,16 +14884,16 @@ define i64 @atomicrmw_umax_i64_acquire(i64 addrspace(200)* %a, i64 %b) nounwind
 ; RV64IXCHERI-NEXT:    j .LBB211_1
 ; RV64IXCHERI-NEXT:  .LBB211_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 80
+; RV64IXCHERI-NEXT:    clc ra, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 80
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_umax_i64_acquire:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camomaxu.d.aq a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camomaxu.d.aq a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw umax i64 addrspace(200)* %a, i64 %b acquire
   ret i64 %1
@@ -14902,31 +14902,31 @@ define i64 @atomicrmw_umax_i64_acquire(i64 addrspace(200)* %a, i64 %b) nounwind
 define i64 @atomicrmw_umax_i64_release(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_umax_i64_release:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs3, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s3, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    mv s0, a2
-; RV32IXCHERI-NEXT:    mv s2, a1
-; RV32IXCHERI-NEXT:    cmove cs3, ca0
-; RV32IXCHERI-NEXT:    clw a1, 4(ca0)
-; RV32IXCHERI-NEXT:    clw a4, 0(ca0)
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 0
-; RV32IXCHERI-NEXT:    csetbounds cs1, ca0, 8
+; RV32IXCHERI-NEXT:    mv s1, a1
+; RV32IXCHERI-NEXT:    cmove s2, a0
+; RV32IXCHERI-NEXT:    clw a1, 4(a0)
+; RV32IXCHERI-NEXT:    clw a4, 0(a0)
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 0
+; RV32IXCHERI-NEXT:    csetbounds s3, a0, 8
 ; RV32IXCHERI-NEXT:    j .LBB212_2
 ; RV32IXCHERI-NEXT:  .LBB212_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB212_2 Depth=1
-; RV32IXCHERI-NEXT:    csw a4, 0(csp)
-; RV32IXCHERI-NEXT:    csw a1, 4(csp)
+; RV32IXCHERI-NEXT:    csw a4, 0(sp)
+; RV32IXCHERI-NEXT:    csw a1, 4(sp)
 ; RV32IXCHERI-NEXT:    li a4, 3
-; RV32IXCHERI-NEXT:    cmove ca0, cs3
-; RV32IXCHERI-NEXT:    cmove ca1, cs1
+; RV32IXCHERI-NEXT:    cmove a0, s2
+; RV32IXCHERI-NEXT:    cmove a1, s3
 ; RV32IXCHERI-NEXT:    li a5, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV32IXCHERI-NEXT:    clw a1, 4(csp)
-; RV32IXCHERI-NEXT:    clw a4, 0(csp)
+; RV32IXCHERI-NEXT:    clw a1, 4(sp)
+; RV32IXCHERI-NEXT:    clw a4, 0(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB212_7
 ; RV32IXCHERI-NEXT:  .LBB212_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -14936,7 +14936,7 @@ define i64 @atomicrmw_umax_i64_release(i64 addrspace(200)* %a, i64 %b) nounwind
 ; RV32IXCHERI-NEXT:    sltu a0, s0, a1
 ; RV32IXCHERI-NEXT:    j .LBB212_5
 ; RV32IXCHERI-NEXT:  .LBB212_4: # in Loop: Header=BB212_2 Depth=1
-; RV32IXCHERI-NEXT:    sltu a0, s2, a4
+; RV32IXCHERI-NEXT:    sltu a0, s1, a4
 ; RV32IXCHERI-NEXT:  .LBB212_5: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB212_2 Depth=1
 ; RV32IXCHERI-NEXT:    mv a2, a4
@@ -14944,46 +14944,46 @@ define i64 @atomicrmw_umax_i64_release(i64 addrspace(200)* %a, i64 %b) nounwind
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB212_1
 ; RV32IXCHERI-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB212_2 Depth=1
-; RV32IXCHERI-NEXT:    mv a2, s2
+; RV32IXCHERI-NEXT:    mv a2, s1
 ; RV32IXCHERI-NEXT:    mv a3, s0
 ; RV32IXCHERI-NEXT:    j .LBB212_1
 ; RV32IXCHERI-NEXT:  .LBB212_7: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a4
-; RV32IXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs3, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s3, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_umax_i64_release:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IAXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs3, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IAXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s3, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    mv s0, a2
-; RV32IAXCHERI-NEXT:    mv s2, a1
-; RV32IAXCHERI-NEXT:    cmove cs3, ca0
-; RV32IAXCHERI-NEXT:    clw a1, 4(ca0)
-; RV32IAXCHERI-NEXT:    clw a4, 0(ca0)
-; RV32IAXCHERI-NEXT:    cincoffset ca0, csp, 0
-; RV32IAXCHERI-NEXT:    csetbounds cs1, ca0, 8
+; RV32IAXCHERI-NEXT:    mv s1, a1
+; RV32IAXCHERI-NEXT:    cmove s2, a0
+; RV32IAXCHERI-NEXT:    clw a1, 4(a0)
+; RV32IAXCHERI-NEXT:    clw a4, 0(a0)
+; RV32IAXCHERI-NEXT:    cincoffset a0, sp, 0
+; RV32IAXCHERI-NEXT:    csetbounds s3, a0, 8
 ; RV32IAXCHERI-NEXT:    j .LBB212_2
 ; RV32IAXCHERI-NEXT:  .LBB212_1: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # in Loop: Header=BB212_2 Depth=1
-; RV32IAXCHERI-NEXT:    csw a4, 0(csp)
-; RV32IAXCHERI-NEXT:    csw a1, 4(csp)
+; RV32IAXCHERI-NEXT:    csw a4, 0(sp)
+; RV32IAXCHERI-NEXT:    csw a1, 4(sp)
 ; RV32IAXCHERI-NEXT:    li a4, 3
-; RV32IAXCHERI-NEXT:    cmove ca0, cs3
-; RV32IAXCHERI-NEXT:    cmove ca1, cs1
+; RV32IAXCHERI-NEXT:    cmove a0, s2
+; RV32IAXCHERI-NEXT:    cmove a1, s3
 ; RV32IAXCHERI-NEXT:    li a5, 0
 ; RV32IAXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV32IAXCHERI-NEXT:    clw a1, 4(csp)
-; RV32IAXCHERI-NEXT:    clw a4, 0(csp)
+; RV32IAXCHERI-NEXT:    clw a1, 4(sp)
+; RV32IAXCHERI-NEXT:    clw a4, 0(sp)
 ; RV32IAXCHERI-NEXT:    bnez a0, .LBB212_7
 ; RV32IAXCHERI-NEXT:  .LBB212_2: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -14993,7 +14993,7 @@ define i64 @atomicrmw_umax_i64_release(i64 addrspace(200)* %a, i64 %b) nounwind
 ; RV32IAXCHERI-NEXT:    sltu a0, s0, a1
 ; RV32IAXCHERI-NEXT:    j .LBB212_5
 ; RV32IAXCHERI-NEXT:  .LBB212_4: # in Loop: Header=BB212_2 Depth=1
-; RV32IAXCHERI-NEXT:    sltu a0, s2, a4
+; RV32IAXCHERI-NEXT:    sltu a0, s1, a4
 ; RV32IAXCHERI-NEXT:  .LBB212_5: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # in Loop: Header=BB212_2 Depth=1
 ; RV32IAXCHERI-NEXT:    mv a2, a4
@@ -15001,41 +15001,41 @@ define i64 @atomicrmw_umax_i64_release(i64 addrspace(200)* %a, i64 %b) nounwind
 ; RV32IAXCHERI-NEXT:    bnez a0, .LBB212_1
 ; RV32IAXCHERI-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # in Loop: Header=BB212_2 Depth=1
-; RV32IAXCHERI-NEXT:    mv a2, s2
+; RV32IAXCHERI-NEXT:    mv a2, s1
 ; RV32IAXCHERI-NEXT:    mv a3, s0
 ; RV32IAXCHERI-NEXT:    j .LBB212_1
 ; RV32IAXCHERI-NEXT:  .LBB212_7: # %atomicrmw.end
 ; RV32IAXCHERI-NEXT:    mv a0, a4
-; RV32IAXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs3, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IAXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s3, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_umax_i64_release:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -80
-; RV64IXCHERI-NEXT:    csc cra, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 16(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -80
+; RV64IXCHERI-NEXT:    csc ra, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 16(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    mv s0, a1
-; RV64IXCHERI-NEXT:    cmove cs2, ca0
-; RV64IXCHERI-NEXT:    cld a1, 0(ca0)
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 8
-; RV64IXCHERI-NEXT:    csetbounds cs1, ca0, 8
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    cld a1, 0(a0)
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 8
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 8
 ; RV64IXCHERI-NEXT:    j .LBB212_2
 ; RV64IXCHERI-NEXT:  .LBB212_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB212_2 Depth=1
-; RV64IXCHERI-NEXT:    csd a1, 8(csp)
+; RV64IXCHERI-NEXT:    csd a1, 8(sp)
 ; RV64IXCHERI-NEXT:    li a3, 3
-; RV64IXCHERI-NEXT:    cmove ca0, cs2
-; RV64IXCHERI-NEXT:    cmove ca1, cs1
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    li a4, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV64IXCHERI-NEXT:    cld a1, 8(csp)
+; RV64IXCHERI-NEXT:    cld a1, 8(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB212_4
 ; RV64IXCHERI-NEXT:  .LBB212_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -15047,16 +15047,16 @@ define i64 @atomicrmw_umax_i64_release(i64 addrspace(200)* %a, i64 %b) nounwind
 ; RV64IXCHERI-NEXT:    j .LBB212_1
 ; RV64IXCHERI-NEXT:  .LBB212_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 80
+; RV64IXCHERI-NEXT:    clc ra, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 80
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_umax_i64_release:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camomaxu.d.rl a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camomaxu.d.rl a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw umax i64 addrspace(200)* %a, i64 %b release
   ret i64 %1
@@ -15065,31 +15065,31 @@ define i64 @atomicrmw_umax_i64_release(i64 addrspace(200)* %a, i64 %b) nounwind
 define i64 @atomicrmw_umax_i64_acq_rel(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_umax_i64_acq_rel:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs3, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s3, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    mv s0, a2
-; RV32IXCHERI-NEXT:    mv s2, a1
-; RV32IXCHERI-NEXT:    cmove cs3, ca0
-; RV32IXCHERI-NEXT:    clw a1, 4(ca0)
-; RV32IXCHERI-NEXT:    clw a4, 0(ca0)
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 0
-; RV32IXCHERI-NEXT:    csetbounds cs1, ca0, 8
+; RV32IXCHERI-NEXT:    mv s1, a1
+; RV32IXCHERI-NEXT:    cmove s2, a0
+; RV32IXCHERI-NEXT:    clw a1, 4(a0)
+; RV32IXCHERI-NEXT:    clw a4, 0(a0)
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 0
+; RV32IXCHERI-NEXT:    csetbounds s3, a0, 8
 ; RV32IXCHERI-NEXT:    j .LBB213_2
 ; RV32IXCHERI-NEXT:  .LBB213_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB213_2 Depth=1
-; RV32IXCHERI-NEXT:    csw a4, 0(csp)
-; RV32IXCHERI-NEXT:    csw a1, 4(csp)
+; RV32IXCHERI-NEXT:    csw a4, 0(sp)
+; RV32IXCHERI-NEXT:    csw a1, 4(sp)
 ; RV32IXCHERI-NEXT:    li a4, 4
 ; RV32IXCHERI-NEXT:    li a5, 2
-; RV32IXCHERI-NEXT:    cmove ca0, cs3
-; RV32IXCHERI-NEXT:    cmove ca1, cs1
+; RV32IXCHERI-NEXT:    cmove a0, s2
+; RV32IXCHERI-NEXT:    cmove a1, s3
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV32IXCHERI-NEXT:    clw a1, 4(csp)
-; RV32IXCHERI-NEXT:    clw a4, 0(csp)
+; RV32IXCHERI-NEXT:    clw a1, 4(sp)
+; RV32IXCHERI-NEXT:    clw a4, 0(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB213_7
 ; RV32IXCHERI-NEXT:  .LBB213_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -15099,7 +15099,7 @@ define i64 @atomicrmw_umax_i64_acq_rel(i64 addrspace(200)* %a, i64 %b) nounwind
 ; RV32IXCHERI-NEXT:    sltu a0, s0, a1
 ; RV32IXCHERI-NEXT:    j .LBB213_5
 ; RV32IXCHERI-NEXT:  .LBB213_4: # in Loop: Header=BB213_2 Depth=1
-; RV32IXCHERI-NEXT:    sltu a0, s2, a4
+; RV32IXCHERI-NEXT:    sltu a0, s1, a4
 ; RV32IXCHERI-NEXT:  .LBB213_5: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB213_2 Depth=1
 ; RV32IXCHERI-NEXT:    mv a2, a4
@@ -15107,46 +15107,46 @@ define i64 @atomicrmw_umax_i64_acq_rel(i64 addrspace(200)* %a, i64 %b) nounwind
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB213_1
 ; RV32IXCHERI-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB213_2 Depth=1
-; RV32IXCHERI-NEXT:    mv a2, s2
+; RV32IXCHERI-NEXT:    mv a2, s1
 ; RV32IXCHERI-NEXT:    mv a3, s0
 ; RV32IXCHERI-NEXT:    j .LBB213_1
 ; RV32IXCHERI-NEXT:  .LBB213_7: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a4
-; RV32IXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs3, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s3, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_umax_i64_acq_rel:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IAXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs3, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IAXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s3, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    mv s0, a2
-; RV32IAXCHERI-NEXT:    mv s2, a1
-; RV32IAXCHERI-NEXT:    cmove cs3, ca0
-; RV32IAXCHERI-NEXT:    clw a1, 4(ca0)
-; RV32IAXCHERI-NEXT:    clw a4, 0(ca0)
-; RV32IAXCHERI-NEXT:    cincoffset ca0, csp, 0
-; RV32IAXCHERI-NEXT:    csetbounds cs1, ca0, 8
+; RV32IAXCHERI-NEXT:    mv s1, a1
+; RV32IAXCHERI-NEXT:    cmove s2, a0
+; RV32IAXCHERI-NEXT:    clw a1, 4(a0)
+; RV32IAXCHERI-NEXT:    clw a4, 0(a0)
+; RV32IAXCHERI-NEXT:    cincoffset a0, sp, 0
+; RV32IAXCHERI-NEXT:    csetbounds s3, a0, 8
 ; RV32IAXCHERI-NEXT:    j .LBB213_2
 ; RV32IAXCHERI-NEXT:  .LBB213_1: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # in Loop: Header=BB213_2 Depth=1
-; RV32IAXCHERI-NEXT:    csw a4, 0(csp)
-; RV32IAXCHERI-NEXT:    csw a1, 4(csp)
+; RV32IAXCHERI-NEXT:    csw a4, 0(sp)
+; RV32IAXCHERI-NEXT:    csw a1, 4(sp)
 ; RV32IAXCHERI-NEXT:    li a4, 4
 ; RV32IAXCHERI-NEXT:    li a5, 2
-; RV32IAXCHERI-NEXT:    cmove ca0, cs3
-; RV32IAXCHERI-NEXT:    cmove ca1, cs1
+; RV32IAXCHERI-NEXT:    cmove a0, s2
+; RV32IAXCHERI-NEXT:    cmove a1, s3
 ; RV32IAXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV32IAXCHERI-NEXT:    clw a1, 4(csp)
-; RV32IAXCHERI-NEXT:    clw a4, 0(csp)
+; RV32IAXCHERI-NEXT:    clw a1, 4(sp)
+; RV32IAXCHERI-NEXT:    clw a4, 0(sp)
 ; RV32IAXCHERI-NEXT:    bnez a0, .LBB213_7
 ; RV32IAXCHERI-NEXT:  .LBB213_2: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -15156,7 +15156,7 @@ define i64 @atomicrmw_umax_i64_acq_rel(i64 addrspace(200)* %a, i64 %b) nounwind
 ; RV32IAXCHERI-NEXT:    sltu a0, s0, a1
 ; RV32IAXCHERI-NEXT:    j .LBB213_5
 ; RV32IAXCHERI-NEXT:  .LBB213_4: # in Loop: Header=BB213_2 Depth=1
-; RV32IAXCHERI-NEXT:    sltu a0, s2, a4
+; RV32IAXCHERI-NEXT:    sltu a0, s1, a4
 ; RV32IAXCHERI-NEXT:  .LBB213_5: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # in Loop: Header=BB213_2 Depth=1
 ; RV32IAXCHERI-NEXT:    mv a2, a4
@@ -15164,41 +15164,41 @@ define i64 @atomicrmw_umax_i64_acq_rel(i64 addrspace(200)* %a, i64 %b) nounwind
 ; RV32IAXCHERI-NEXT:    bnez a0, .LBB213_1
 ; RV32IAXCHERI-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # in Loop: Header=BB213_2 Depth=1
-; RV32IAXCHERI-NEXT:    mv a2, s2
+; RV32IAXCHERI-NEXT:    mv a2, s1
 ; RV32IAXCHERI-NEXT:    mv a3, s0
 ; RV32IAXCHERI-NEXT:    j .LBB213_1
 ; RV32IAXCHERI-NEXT:  .LBB213_7: # %atomicrmw.end
 ; RV32IAXCHERI-NEXT:    mv a0, a4
-; RV32IAXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs3, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IAXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s3, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_umax_i64_acq_rel:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -80
-; RV64IXCHERI-NEXT:    csc cra, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 16(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -80
+; RV64IXCHERI-NEXT:    csc ra, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 16(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    mv s0, a1
-; RV64IXCHERI-NEXT:    cmove cs2, ca0
-; RV64IXCHERI-NEXT:    cld a1, 0(ca0)
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 8
-; RV64IXCHERI-NEXT:    csetbounds cs1, ca0, 8
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    cld a1, 0(a0)
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 8
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 8
 ; RV64IXCHERI-NEXT:    j .LBB213_2
 ; RV64IXCHERI-NEXT:  .LBB213_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB213_2 Depth=1
-; RV64IXCHERI-NEXT:    csd a1, 8(csp)
+; RV64IXCHERI-NEXT:    csd a1, 8(sp)
 ; RV64IXCHERI-NEXT:    li a3, 4
 ; RV64IXCHERI-NEXT:    li a4, 2
-; RV64IXCHERI-NEXT:    cmove ca0, cs2
-; RV64IXCHERI-NEXT:    cmove ca1, cs1
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV64IXCHERI-NEXT:    cld a1, 8(csp)
+; RV64IXCHERI-NEXT:    cld a1, 8(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB213_4
 ; RV64IXCHERI-NEXT:  .LBB213_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -15210,16 +15210,16 @@ define i64 @atomicrmw_umax_i64_acq_rel(i64 addrspace(200)* %a, i64 %b) nounwind
 ; RV64IXCHERI-NEXT:    j .LBB213_1
 ; RV64IXCHERI-NEXT:  .LBB213_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 80
+; RV64IXCHERI-NEXT:    clc ra, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 80
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_umax_i64_acq_rel:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camomaxu.d.aqrl a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camomaxu.d.aqrl a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw umax i64 addrspace(200)* %a, i64 %b acq_rel
   ret i64 %1
@@ -15228,31 +15228,31 @@ define i64 @atomicrmw_umax_i64_acq_rel(i64 addrspace(200)* %a, i64 %b) nounwind
 define i64 @atomicrmw_umax_i64_seq_cst(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_umax_i64_seq_cst:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs3, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s3, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    mv s0, a2
-; RV32IXCHERI-NEXT:    mv s2, a1
-; RV32IXCHERI-NEXT:    cmove cs3, ca0
-; RV32IXCHERI-NEXT:    clw a1, 4(ca0)
-; RV32IXCHERI-NEXT:    clw a4, 0(ca0)
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 0
-; RV32IXCHERI-NEXT:    csetbounds cs1, ca0, 8
+; RV32IXCHERI-NEXT:    mv s1, a1
+; RV32IXCHERI-NEXT:    cmove s2, a0
+; RV32IXCHERI-NEXT:    clw a1, 4(a0)
+; RV32IXCHERI-NEXT:    clw a4, 0(a0)
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 0
+; RV32IXCHERI-NEXT:    csetbounds s3, a0, 8
 ; RV32IXCHERI-NEXT:    j .LBB214_2
 ; RV32IXCHERI-NEXT:  .LBB214_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB214_2 Depth=1
-; RV32IXCHERI-NEXT:    csw a4, 0(csp)
-; RV32IXCHERI-NEXT:    csw a1, 4(csp)
+; RV32IXCHERI-NEXT:    csw a4, 0(sp)
+; RV32IXCHERI-NEXT:    csw a1, 4(sp)
 ; RV32IXCHERI-NEXT:    li a4, 5
 ; RV32IXCHERI-NEXT:    li a5, 5
-; RV32IXCHERI-NEXT:    cmove ca0, cs3
-; RV32IXCHERI-NEXT:    cmove ca1, cs1
+; RV32IXCHERI-NEXT:    cmove a0, s2
+; RV32IXCHERI-NEXT:    cmove a1, s3
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV32IXCHERI-NEXT:    clw a1, 4(csp)
-; RV32IXCHERI-NEXT:    clw a4, 0(csp)
+; RV32IXCHERI-NEXT:    clw a1, 4(sp)
+; RV32IXCHERI-NEXT:    clw a4, 0(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB214_7
 ; RV32IXCHERI-NEXT:  .LBB214_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -15262,7 +15262,7 @@ define i64 @atomicrmw_umax_i64_seq_cst(i64 addrspace(200)* %a, i64 %b) nounwind
 ; RV32IXCHERI-NEXT:    sltu a0, s0, a1
 ; RV32IXCHERI-NEXT:    j .LBB214_5
 ; RV32IXCHERI-NEXT:  .LBB214_4: # in Loop: Header=BB214_2 Depth=1
-; RV32IXCHERI-NEXT:    sltu a0, s2, a4
+; RV32IXCHERI-NEXT:    sltu a0, s1, a4
 ; RV32IXCHERI-NEXT:  .LBB214_5: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB214_2 Depth=1
 ; RV32IXCHERI-NEXT:    mv a2, a4
@@ -15270,46 +15270,46 @@ define i64 @atomicrmw_umax_i64_seq_cst(i64 addrspace(200)* %a, i64 %b) nounwind
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB214_1
 ; RV32IXCHERI-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB214_2 Depth=1
-; RV32IXCHERI-NEXT:    mv a2, s2
+; RV32IXCHERI-NEXT:    mv a2, s1
 ; RV32IXCHERI-NEXT:    mv a3, s0
 ; RV32IXCHERI-NEXT:    j .LBB214_1
 ; RV32IXCHERI-NEXT:  .LBB214_7: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a4
-; RV32IXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs3, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s3, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_umax_i64_seq_cst:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IAXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs3, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IAXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s3, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    mv s0, a2
-; RV32IAXCHERI-NEXT:    mv s2, a1
-; RV32IAXCHERI-NEXT:    cmove cs3, ca0
-; RV32IAXCHERI-NEXT:    clw a1, 4(ca0)
-; RV32IAXCHERI-NEXT:    clw a4, 0(ca0)
-; RV32IAXCHERI-NEXT:    cincoffset ca0, csp, 0
-; RV32IAXCHERI-NEXT:    csetbounds cs1, ca0, 8
+; RV32IAXCHERI-NEXT:    mv s1, a1
+; RV32IAXCHERI-NEXT:    cmove s2, a0
+; RV32IAXCHERI-NEXT:    clw a1, 4(a0)
+; RV32IAXCHERI-NEXT:    clw a4, 0(a0)
+; RV32IAXCHERI-NEXT:    cincoffset a0, sp, 0
+; RV32IAXCHERI-NEXT:    csetbounds s3, a0, 8
 ; RV32IAXCHERI-NEXT:    j .LBB214_2
 ; RV32IAXCHERI-NEXT:  .LBB214_1: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # in Loop: Header=BB214_2 Depth=1
-; RV32IAXCHERI-NEXT:    csw a4, 0(csp)
-; RV32IAXCHERI-NEXT:    csw a1, 4(csp)
+; RV32IAXCHERI-NEXT:    csw a4, 0(sp)
+; RV32IAXCHERI-NEXT:    csw a1, 4(sp)
 ; RV32IAXCHERI-NEXT:    li a4, 5
 ; RV32IAXCHERI-NEXT:    li a5, 5
-; RV32IAXCHERI-NEXT:    cmove ca0, cs3
-; RV32IAXCHERI-NEXT:    cmove ca1, cs1
+; RV32IAXCHERI-NEXT:    cmove a0, s2
+; RV32IAXCHERI-NEXT:    cmove a1, s3
 ; RV32IAXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV32IAXCHERI-NEXT:    clw a1, 4(csp)
-; RV32IAXCHERI-NEXT:    clw a4, 0(csp)
+; RV32IAXCHERI-NEXT:    clw a1, 4(sp)
+; RV32IAXCHERI-NEXT:    clw a4, 0(sp)
 ; RV32IAXCHERI-NEXT:    bnez a0, .LBB214_7
 ; RV32IAXCHERI-NEXT:  .LBB214_2: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -15319,7 +15319,7 @@ define i64 @atomicrmw_umax_i64_seq_cst(i64 addrspace(200)* %a, i64 %b) nounwind
 ; RV32IAXCHERI-NEXT:    sltu a0, s0, a1
 ; RV32IAXCHERI-NEXT:    j .LBB214_5
 ; RV32IAXCHERI-NEXT:  .LBB214_4: # in Loop: Header=BB214_2 Depth=1
-; RV32IAXCHERI-NEXT:    sltu a0, s2, a4
+; RV32IAXCHERI-NEXT:    sltu a0, s1, a4
 ; RV32IAXCHERI-NEXT:  .LBB214_5: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # in Loop: Header=BB214_2 Depth=1
 ; RV32IAXCHERI-NEXT:    mv a2, a4
@@ -15327,41 +15327,41 @@ define i64 @atomicrmw_umax_i64_seq_cst(i64 addrspace(200)* %a, i64 %b) nounwind
 ; RV32IAXCHERI-NEXT:    bnez a0, .LBB214_1
 ; RV32IAXCHERI-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # in Loop: Header=BB214_2 Depth=1
-; RV32IAXCHERI-NEXT:    mv a2, s2
+; RV32IAXCHERI-NEXT:    mv a2, s1
 ; RV32IAXCHERI-NEXT:    mv a3, s0
 ; RV32IAXCHERI-NEXT:    j .LBB214_1
 ; RV32IAXCHERI-NEXT:  .LBB214_7: # %atomicrmw.end
 ; RV32IAXCHERI-NEXT:    mv a0, a4
-; RV32IAXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs3, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IAXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s3, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_umax_i64_seq_cst:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -80
-; RV64IXCHERI-NEXT:    csc cra, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 16(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -80
+; RV64IXCHERI-NEXT:    csc ra, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 16(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    mv s0, a1
-; RV64IXCHERI-NEXT:    cmove cs2, ca0
-; RV64IXCHERI-NEXT:    cld a1, 0(ca0)
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 8
-; RV64IXCHERI-NEXT:    csetbounds cs1, ca0, 8
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    cld a1, 0(a0)
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 8
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 8
 ; RV64IXCHERI-NEXT:    j .LBB214_2
 ; RV64IXCHERI-NEXT:  .LBB214_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB214_2 Depth=1
-; RV64IXCHERI-NEXT:    csd a1, 8(csp)
+; RV64IXCHERI-NEXT:    csd a1, 8(sp)
 ; RV64IXCHERI-NEXT:    li a3, 5
 ; RV64IXCHERI-NEXT:    li a4, 5
-; RV64IXCHERI-NEXT:    cmove ca0, cs2
-; RV64IXCHERI-NEXT:    cmove ca1, cs1
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV64IXCHERI-NEXT:    cld a1, 8(csp)
+; RV64IXCHERI-NEXT:    cld a1, 8(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB214_4
 ; RV64IXCHERI-NEXT:  .LBB214_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -15373,16 +15373,16 @@ define i64 @atomicrmw_umax_i64_seq_cst(i64 addrspace(200)* %a, i64 %b) nounwind
 ; RV64IXCHERI-NEXT:    j .LBB214_1
 ; RV64IXCHERI-NEXT:  .LBB214_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 80
+; RV64IXCHERI-NEXT:    clc ra, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 80
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_umax_i64_seq_cst:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camomaxu.d.aqrl a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camomaxu.d.aqrl a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw umax i64 addrspace(200)* %a, i64 %b seq_cst
   ret i64 %1
@@ -15391,31 +15391,31 @@ define i64 @atomicrmw_umax_i64_seq_cst(i64 addrspace(200)* %a, i64 %b) nounwind
 define i64 @atomicrmw_umin_i64_monotonic(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_umin_i64_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs3, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s3, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    mv s0, a2
-; RV32IXCHERI-NEXT:    mv s2, a1
-; RV32IXCHERI-NEXT:    cmove cs3, ca0
-; RV32IXCHERI-NEXT:    clw a1, 4(ca0)
-; RV32IXCHERI-NEXT:    clw a4, 0(ca0)
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 0
-; RV32IXCHERI-NEXT:    csetbounds cs1, ca0, 8
+; RV32IXCHERI-NEXT:    mv s1, a1
+; RV32IXCHERI-NEXT:    cmove s2, a0
+; RV32IXCHERI-NEXT:    clw a1, 4(a0)
+; RV32IXCHERI-NEXT:    clw a4, 0(a0)
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 0
+; RV32IXCHERI-NEXT:    csetbounds s3, a0, 8
 ; RV32IXCHERI-NEXT:    j .LBB215_2
 ; RV32IXCHERI-NEXT:  .LBB215_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB215_2 Depth=1
-; RV32IXCHERI-NEXT:    csw a4, 0(csp)
-; RV32IXCHERI-NEXT:    csw a1, 4(csp)
-; RV32IXCHERI-NEXT:    cmove ca0, cs3
-; RV32IXCHERI-NEXT:    cmove ca1, cs1
+; RV32IXCHERI-NEXT:    csw a4, 0(sp)
+; RV32IXCHERI-NEXT:    csw a1, 4(sp)
+; RV32IXCHERI-NEXT:    cmove a0, s2
+; RV32IXCHERI-NEXT:    cmove a1, s3
 ; RV32IXCHERI-NEXT:    li a4, 0
 ; RV32IXCHERI-NEXT:    li a5, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV32IXCHERI-NEXT:    clw a1, 4(csp)
-; RV32IXCHERI-NEXT:    clw a4, 0(csp)
+; RV32IXCHERI-NEXT:    clw a1, 4(sp)
+; RV32IXCHERI-NEXT:    clw a4, 0(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB215_7
 ; RV32IXCHERI-NEXT:  .LBB215_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -15425,7 +15425,7 @@ define i64 @atomicrmw_umin_i64_monotonic(i64 addrspace(200)* %a, i64 %b) nounwin
 ; RV32IXCHERI-NEXT:    sltu a0, s0, a1
 ; RV32IXCHERI-NEXT:    j .LBB215_5
 ; RV32IXCHERI-NEXT:  .LBB215_4: # in Loop: Header=BB215_2 Depth=1
-; RV32IXCHERI-NEXT:    sltu a0, s2, a4
+; RV32IXCHERI-NEXT:    sltu a0, s1, a4
 ; RV32IXCHERI-NEXT:  .LBB215_5: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB215_2 Depth=1
 ; RV32IXCHERI-NEXT:    mv a2, a4
@@ -15433,46 +15433,46 @@ define i64 @atomicrmw_umin_i64_monotonic(i64 addrspace(200)* %a, i64 %b) nounwin
 ; RV32IXCHERI-NEXT:    beqz a0, .LBB215_1
 ; RV32IXCHERI-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB215_2 Depth=1
-; RV32IXCHERI-NEXT:    mv a2, s2
+; RV32IXCHERI-NEXT:    mv a2, s1
 ; RV32IXCHERI-NEXT:    mv a3, s0
 ; RV32IXCHERI-NEXT:    j .LBB215_1
 ; RV32IXCHERI-NEXT:  .LBB215_7: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a4
-; RV32IXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs3, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s3, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_umin_i64_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IAXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs3, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IAXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s3, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    mv s0, a2
-; RV32IAXCHERI-NEXT:    mv s2, a1
-; RV32IAXCHERI-NEXT:    cmove cs3, ca0
-; RV32IAXCHERI-NEXT:    clw a1, 4(ca0)
-; RV32IAXCHERI-NEXT:    clw a4, 0(ca0)
-; RV32IAXCHERI-NEXT:    cincoffset ca0, csp, 0
-; RV32IAXCHERI-NEXT:    csetbounds cs1, ca0, 8
+; RV32IAXCHERI-NEXT:    mv s1, a1
+; RV32IAXCHERI-NEXT:    cmove s2, a0
+; RV32IAXCHERI-NEXT:    clw a1, 4(a0)
+; RV32IAXCHERI-NEXT:    clw a4, 0(a0)
+; RV32IAXCHERI-NEXT:    cincoffset a0, sp, 0
+; RV32IAXCHERI-NEXT:    csetbounds s3, a0, 8
 ; RV32IAXCHERI-NEXT:    j .LBB215_2
 ; RV32IAXCHERI-NEXT:  .LBB215_1: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # in Loop: Header=BB215_2 Depth=1
-; RV32IAXCHERI-NEXT:    csw a4, 0(csp)
-; RV32IAXCHERI-NEXT:    csw a1, 4(csp)
-; RV32IAXCHERI-NEXT:    cmove ca0, cs3
-; RV32IAXCHERI-NEXT:    cmove ca1, cs1
+; RV32IAXCHERI-NEXT:    csw a4, 0(sp)
+; RV32IAXCHERI-NEXT:    csw a1, 4(sp)
+; RV32IAXCHERI-NEXT:    cmove a0, s2
+; RV32IAXCHERI-NEXT:    cmove a1, s3
 ; RV32IAXCHERI-NEXT:    li a4, 0
 ; RV32IAXCHERI-NEXT:    li a5, 0
 ; RV32IAXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV32IAXCHERI-NEXT:    clw a1, 4(csp)
-; RV32IAXCHERI-NEXT:    clw a4, 0(csp)
+; RV32IAXCHERI-NEXT:    clw a1, 4(sp)
+; RV32IAXCHERI-NEXT:    clw a4, 0(sp)
 ; RV32IAXCHERI-NEXT:    bnez a0, .LBB215_7
 ; RV32IAXCHERI-NEXT:  .LBB215_2: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -15482,7 +15482,7 @@ define i64 @atomicrmw_umin_i64_monotonic(i64 addrspace(200)* %a, i64 %b) nounwin
 ; RV32IAXCHERI-NEXT:    sltu a0, s0, a1
 ; RV32IAXCHERI-NEXT:    j .LBB215_5
 ; RV32IAXCHERI-NEXT:  .LBB215_4: # in Loop: Header=BB215_2 Depth=1
-; RV32IAXCHERI-NEXT:    sltu a0, s2, a4
+; RV32IAXCHERI-NEXT:    sltu a0, s1, a4
 ; RV32IAXCHERI-NEXT:  .LBB215_5: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # in Loop: Header=BB215_2 Depth=1
 ; RV32IAXCHERI-NEXT:    mv a2, a4
@@ -15490,41 +15490,41 @@ define i64 @atomicrmw_umin_i64_monotonic(i64 addrspace(200)* %a, i64 %b) nounwin
 ; RV32IAXCHERI-NEXT:    beqz a0, .LBB215_1
 ; RV32IAXCHERI-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # in Loop: Header=BB215_2 Depth=1
-; RV32IAXCHERI-NEXT:    mv a2, s2
+; RV32IAXCHERI-NEXT:    mv a2, s1
 ; RV32IAXCHERI-NEXT:    mv a3, s0
 ; RV32IAXCHERI-NEXT:    j .LBB215_1
 ; RV32IAXCHERI-NEXT:  .LBB215_7: # %atomicrmw.end
 ; RV32IAXCHERI-NEXT:    mv a0, a4
-; RV32IAXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs3, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IAXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s3, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_umin_i64_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -80
-; RV64IXCHERI-NEXT:    csc cra, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 16(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -80
+; RV64IXCHERI-NEXT:    csc ra, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 16(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    mv s0, a1
-; RV64IXCHERI-NEXT:    cmove cs2, ca0
-; RV64IXCHERI-NEXT:    cld a1, 0(ca0)
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 8
-; RV64IXCHERI-NEXT:    csetbounds cs1, ca0, 8
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    cld a1, 0(a0)
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 8
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 8
 ; RV64IXCHERI-NEXT:    j .LBB215_2
 ; RV64IXCHERI-NEXT:  .LBB215_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB215_2 Depth=1
-; RV64IXCHERI-NEXT:    csd a1, 8(csp)
-; RV64IXCHERI-NEXT:    cmove ca0, cs2
-; RV64IXCHERI-NEXT:    cmove ca1, cs1
+; RV64IXCHERI-NEXT:    csd a1, 8(sp)
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    li a3, 0
 ; RV64IXCHERI-NEXT:    li a4, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV64IXCHERI-NEXT:    cld a1, 8(csp)
+; RV64IXCHERI-NEXT:    cld a1, 8(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB215_4
 ; RV64IXCHERI-NEXT:  .LBB215_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -15536,16 +15536,16 @@ define i64 @atomicrmw_umin_i64_monotonic(i64 addrspace(200)* %a, i64 %b) nounwin
 ; RV64IXCHERI-NEXT:    j .LBB215_1
 ; RV64IXCHERI-NEXT:  .LBB215_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 80
+; RV64IXCHERI-NEXT:    clc ra, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 80
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_umin_i64_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camominu.d a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camominu.d a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw umin i64 addrspace(200)* %a, i64 %b monotonic
   ret i64 %1
@@ -15554,31 +15554,31 @@ define i64 @atomicrmw_umin_i64_monotonic(i64 addrspace(200)* %a, i64 %b) nounwin
 define i64 @atomicrmw_umin_i64_acquire(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_umin_i64_acquire:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs3, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s3, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    mv s0, a2
-; RV32IXCHERI-NEXT:    mv s2, a1
-; RV32IXCHERI-NEXT:    cmove cs3, ca0
-; RV32IXCHERI-NEXT:    clw a1, 4(ca0)
-; RV32IXCHERI-NEXT:    clw a4, 0(ca0)
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 0
-; RV32IXCHERI-NEXT:    csetbounds cs1, ca0, 8
+; RV32IXCHERI-NEXT:    mv s1, a1
+; RV32IXCHERI-NEXT:    cmove s2, a0
+; RV32IXCHERI-NEXT:    clw a1, 4(a0)
+; RV32IXCHERI-NEXT:    clw a4, 0(a0)
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 0
+; RV32IXCHERI-NEXT:    csetbounds s3, a0, 8
 ; RV32IXCHERI-NEXT:    j .LBB216_2
 ; RV32IXCHERI-NEXT:  .LBB216_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB216_2 Depth=1
-; RV32IXCHERI-NEXT:    csw a4, 0(csp)
-; RV32IXCHERI-NEXT:    csw a1, 4(csp)
+; RV32IXCHERI-NEXT:    csw a4, 0(sp)
+; RV32IXCHERI-NEXT:    csw a1, 4(sp)
 ; RV32IXCHERI-NEXT:    li a4, 2
 ; RV32IXCHERI-NEXT:    li a5, 2
-; RV32IXCHERI-NEXT:    cmove ca0, cs3
-; RV32IXCHERI-NEXT:    cmove ca1, cs1
+; RV32IXCHERI-NEXT:    cmove a0, s2
+; RV32IXCHERI-NEXT:    cmove a1, s3
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV32IXCHERI-NEXT:    clw a1, 4(csp)
-; RV32IXCHERI-NEXT:    clw a4, 0(csp)
+; RV32IXCHERI-NEXT:    clw a1, 4(sp)
+; RV32IXCHERI-NEXT:    clw a4, 0(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB216_7
 ; RV32IXCHERI-NEXT:  .LBB216_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -15588,7 +15588,7 @@ define i64 @atomicrmw_umin_i64_acquire(i64 addrspace(200)* %a, i64 %b) nounwind
 ; RV32IXCHERI-NEXT:    sltu a0, s0, a1
 ; RV32IXCHERI-NEXT:    j .LBB216_5
 ; RV32IXCHERI-NEXT:  .LBB216_4: # in Loop: Header=BB216_2 Depth=1
-; RV32IXCHERI-NEXT:    sltu a0, s2, a4
+; RV32IXCHERI-NEXT:    sltu a0, s1, a4
 ; RV32IXCHERI-NEXT:  .LBB216_5: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB216_2 Depth=1
 ; RV32IXCHERI-NEXT:    mv a2, a4
@@ -15596,46 +15596,46 @@ define i64 @atomicrmw_umin_i64_acquire(i64 addrspace(200)* %a, i64 %b) nounwind
 ; RV32IXCHERI-NEXT:    beqz a0, .LBB216_1
 ; RV32IXCHERI-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB216_2 Depth=1
-; RV32IXCHERI-NEXT:    mv a2, s2
+; RV32IXCHERI-NEXT:    mv a2, s1
 ; RV32IXCHERI-NEXT:    mv a3, s0
 ; RV32IXCHERI-NEXT:    j .LBB216_1
 ; RV32IXCHERI-NEXT:  .LBB216_7: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a4
-; RV32IXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs3, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s3, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_umin_i64_acquire:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IAXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs3, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IAXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s3, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    mv s0, a2
-; RV32IAXCHERI-NEXT:    mv s2, a1
-; RV32IAXCHERI-NEXT:    cmove cs3, ca0
-; RV32IAXCHERI-NEXT:    clw a1, 4(ca0)
-; RV32IAXCHERI-NEXT:    clw a4, 0(ca0)
-; RV32IAXCHERI-NEXT:    cincoffset ca0, csp, 0
-; RV32IAXCHERI-NEXT:    csetbounds cs1, ca0, 8
+; RV32IAXCHERI-NEXT:    mv s1, a1
+; RV32IAXCHERI-NEXT:    cmove s2, a0
+; RV32IAXCHERI-NEXT:    clw a1, 4(a0)
+; RV32IAXCHERI-NEXT:    clw a4, 0(a0)
+; RV32IAXCHERI-NEXT:    cincoffset a0, sp, 0
+; RV32IAXCHERI-NEXT:    csetbounds s3, a0, 8
 ; RV32IAXCHERI-NEXT:    j .LBB216_2
 ; RV32IAXCHERI-NEXT:  .LBB216_1: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # in Loop: Header=BB216_2 Depth=1
-; RV32IAXCHERI-NEXT:    csw a4, 0(csp)
-; RV32IAXCHERI-NEXT:    csw a1, 4(csp)
+; RV32IAXCHERI-NEXT:    csw a4, 0(sp)
+; RV32IAXCHERI-NEXT:    csw a1, 4(sp)
 ; RV32IAXCHERI-NEXT:    li a4, 2
 ; RV32IAXCHERI-NEXT:    li a5, 2
-; RV32IAXCHERI-NEXT:    cmove ca0, cs3
-; RV32IAXCHERI-NEXT:    cmove ca1, cs1
+; RV32IAXCHERI-NEXT:    cmove a0, s2
+; RV32IAXCHERI-NEXT:    cmove a1, s3
 ; RV32IAXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV32IAXCHERI-NEXT:    clw a1, 4(csp)
-; RV32IAXCHERI-NEXT:    clw a4, 0(csp)
+; RV32IAXCHERI-NEXT:    clw a1, 4(sp)
+; RV32IAXCHERI-NEXT:    clw a4, 0(sp)
 ; RV32IAXCHERI-NEXT:    bnez a0, .LBB216_7
 ; RV32IAXCHERI-NEXT:  .LBB216_2: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -15645,7 +15645,7 @@ define i64 @atomicrmw_umin_i64_acquire(i64 addrspace(200)* %a, i64 %b) nounwind
 ; RV32IAXCHERI-NEXT:    sltu a0, s0, a1
 ; RV32IAXCHERI-NEXT:    j .LBB216_5
 ; RV32IAXCHERI-NEXT:  .LBB216_4: # in Loop: Header=BB216_2 Depth=1
-; RV32IAXCHERI-NEXT:    sltu a0, s2, a4
+; RV32IAXCHERI-NEXT:    sltu a0, s1, a4
 ; RV32IAXCHERI-NEXT:  .LBB216_5: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # in Loop: Header=BB216_2 Depth=1
 ; RV32IAXCHERI-NEXT:    mv a2, a4
@@ -15653,41 +15653,41 @@ define i64 @atomicrmw_umin_i64_acquire(i64 addrspace(200)* %a, i64 %b) nounwind
 ; RV32IAXCHERI-NEXT:    beqz a0, .LBB216_1
 ; RV32IAXCHERI-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # in Loop: Header=BB216_2 Depth=1
-; RV32IAXCHERI-NEXT:    mv a2, s2
+; RV32IAXCHERI-NEXT:    mv a2, s1
 ; RV32IAXCHERI-NEXT:    mv a3, s0
 ; RV32IAXCHERI-NEXT:    j .LBB216_1
 ; RV32IAXCHERI-NEXT:  .LBB216_7: # %atomicrmw.end
 ; RV32IAXCHERI-NEXT:    mv a0, a4
-; RV32IAXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs3, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IAXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s3, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_umin_i64_acquire:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -80
-; RV64IXCHERI-NEXT:    csc cra, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 16(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -80
+; RV64IXCHERI-NEXT:    csc ra, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 16(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    mv s0, a1
-; RV64IXCHERI-NEXT:    cmove cs2, ca0
-; RV64IXCHERI-NEXT:    cld a1, 0(ca0)
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 8
-; RV64IXCHERI-NEXT:    csetbounds cs1, ca0, 8
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    cld a1, 0(a0)
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 8
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 8
 ; RV64IXCHERI-NEXT:    j .LBB216_2
 ; RV64IXCHERI-NEXT:  .LBB216_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB216_2 Depth=1
-; RV64IXCHERI-NEXT:    csd a1, 8(csp)
+; RV64IXCHERI-NEXT:    csd a1, 8(sp)
 ; RV64IXCHERI-NEXT:    li a3, 2
 ; RV64IXCHERI-NEXT:    li a4, 2
-; RV64IXCHERI-NEXT:    cmove ca0, cs2
-; RV64IXCHERI-NEXT:    cmove ca1, cs1
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV64IXCHERI-NEXT:    cld a1, 8(csp)
+; RV64IXCHERI-NEXT:    cld a1, 8(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB216_4
 ; RV64IXCHERI-NEXT:  .LBB216_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -15699,16 +15699,16 @@ define i64 @atomicrmw_umin_i64_acquire(i64 addrspace(200)* %a, i64 %b) nounwind
 ; RV64IXCHERI-NEXT:    j .LBB216_1
 ; RV64IXCHERI-NEXT:  .LBB216_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 80
+; RV64IXCHERI-NEXT:    clc ra, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 80
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_umin_i64_acquire:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camominu.d.aq a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camominu.d.aq a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw umin i64 addrspace(200)* %a, i64 %b acquire
   ret i64 %1
@@ -15717,31 +15717,31 @@ define i64 @atomicrmw_umin_i64_acquire(i64 addrspace(200)* %a, i64 %b) nounwind
 define i64 @atomicrmw_umin_i64_release(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_umin_i64_release:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs3, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s3, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    mv s0, a2
-; RV32IXCHERI-NEXT:    mv s2, a1
-; RV32IXCHERI-NEXT:    cmove cs3, ca0
-; RV32IXCHERI-NEXT:    clw a1, 4(ca0)
-; RV32IXCHERI-NEXT:    clw a4, 0(ca0)
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 0
-; RV32IXCHERI-NEXT:    csetbounds cs1, ca0, 8
+; RV32IXCHERI-NEXT:    mv s1, a1
+; RV32IXCHERI-NEXT:    cmove s2, a0
+; RV32IXCHERI-NEXT:    clw a1, 4(a0)
+; RV32IXCHERI-NEXT:    clw a4, 0(a0)
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 0
+; RV32IXCHERI-NEXT:    csetbounds s3, a0, 8
 ; RV32IXCHERI-NEXT:    j .LBB217_2
 ; RV32IXCHERI-NEXT:  .LBB217_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB217_2 Depth=1
-; RV32IXCHERI-NEXT:    csw a4, 0(csp)
-; RV32IXCHERI-NEXT:    csw a1, 4(csp)
+; RV32IXCHERI-NEXT:    csw a4, 0(sp)
+; RV32IXCHERI-NEXT:    csw a1, 4(sp)
 ; RV32IXCHERI-NEXT:    li a4, 3
-; RV32IXCHERI-NEXT:    cmove ca0, cs3
-; RV32IXCHERI-NEXT:    cmove ca1, cs1
+; RV32IXCHERI-NEXT:    cmove a0, s2
+; RV32IXCHERI-NEXT:    cmove a1, s3
 ; RV32IXCHERI-NEXT:    li a5, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV32IXCHERI-NEXT:    clw a1, 4(csp)
-; RV32IXCHERI-NEXT:    clw a4, 0(csp)
+; RV32IXCHERI-NEXT:    clw a1, 4(sp)
+; RV32IXCHERI-NEXT:    clw a4, 0(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB217_7
 ; RV32IXCHERI-NEXT:  .LBB217_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -15751,7 +15751,7 @@ define i64 @atomicrmw_umin_i64_release(i64 addrspace(200)* %a, i64 %b) nounwind
 ; RV32IXCHERI-NEXT:    sltu a0, s0, a1
 ; RV32IXCHERI-NEXT:    j .LBB217_5
 ; RV32IXCHERI-NEXT:  .LBB217_4: # in Loop: Header=BB217_2 Depth=1
-; RV32IXCHERI-NEXT:    sltu a0, s2, a4
+; RV32IXCHERI-NEXT:    sltu a0, s1, a4
 ; RV32IXCHERI-NEXT:  .LBB217_5: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB217_2 Depth=1
 ; RV32IXCHERI-NEXT:    mv a2, a4
@@ -15759,46 +15759,46 @@ define i64 @atomicrmw_umin_i64_release(i64 addrspace(200)* %a, i64 %b) nounwind
 ; RV32IXCHERI-NEXT:    beqz a0, .LBB217_1
 ; RV32IXCHERI-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB217_2 Depth=1
-; RV32IXCHERI-NEXT:    mv a2, s2
+; RV32IXCHERI-NEXT:    mv a2, s1
 ; RV32IXCHERI-NEXT:    mv a3, s0
 ; RV32IXCHERI-NEXT:    j .LBB217_1
 ; RV32IXCHERI-NEXT:  .LBB217_7: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a4
-; RV32IXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs3, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s3, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_umin_i64_release:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IAXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs3, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IAXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s3, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    mv s0, a2
-; RV32IAXCHERI-NEXT:    mv s2, a1
-; RV32IAXCHERI-NEXT:    cmove cs3, ca0
-; RV32IAXCHERI-NEXT:    clw a1, 4(ca0)
-; RV32IAXCHERI-NEXT:    clw a4, 0(ca0)
-; RV32IAXCHERI-NEXT:    cincoffset ca0, csp, 0
-; RV32IAXCHERI-NEXT:    csetbounds cs1, ca0, 8
+; RV32IAXCHERI-NEXT:    mv s1, a1
+; RV32IAXCHERI-NEXT:    cmove s2, a0
+; RV32IAXCHERI-NEXT:    clw a1, 4(a0)
+; RV32IAXCHERI-NEXT:    clw a4, 0(a0)
+; RV32IAXCHERI-NEXT:    cincoffset a0, sp, 0
+; RV32IAXCHERI-NEXT:    csetbounds s3, a0, 8
 ; RV32IAXCHERI-NEXT:    j .LBB217_2
 ; RV32IAXCHERI-NEXT:  .LBB217_1: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # in Loop: Header=BB217_2 Depth=1
-; RV32IAXCHERI-NEXT:    csw a4, 0(csp)
-; RV32IAXCHERI-NEXT:    csw a1, 4(csp)
+; RV32IAXCHERI-NEXT:    csw a4, 0(sp)
+; RV32IAXCHERI-NEXT:    csw a1, 4(sp)
 ; RV32IAXCHERI-NEXT:    li a4, 3
-; RV32IAXCHERI-NEXT:    cmove ca0, cs3
-; RV32IAXCHERI-NEXT:    cmove ca1, cs1
+; RV32IAXCHERI-NEXT:    cmove a0, s2
+; RV32IAXCHERI-NEXT:    cmove a1, s3
 ; RV32IAXCHERI-NEXT:    li a5, 0
 ; RV32IAXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV32IAXCHERI-NEXT:    clw a1, 4(csp)
-; RV32IAXCHERI-NEXT:    clw a4, 0(csp)
+; RV32IAXCHERI-NEXT:    clw a1, 4(sp)
+; RV32IAXCHERI-NEXT:    clw a4, 0(sp)
 ; RV32IAXCHERI-NEXT:    bnez a0, .LBB217_7
 ; RV32IAXCHERI-NEXT:  .LBB217_2: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -15808,7 +15808,7 @@ define i64 @atomicrmw_umin_i64_release(i64 addrspace(200)* %a, i64 %b) nounwind
 ; RV32IAXCHERI-NEXT:    sltu a0, s0, a1
 ; RV32IAXCHERI-NEXT:    j .LBB217_5
 ; RV32IAXCHERI-NEXT:  .LBB217_4: # in Loop: Header=BB217_2 Depth=1
-; RV32IAXCHERI-NEXT:    sltu a0, s2, a4
+; RV32IAXCHERI-NEXT:    sltu a0, s1, a4
 ; RV32IAXCHERI-NEXT:  .LBB217_5: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # in Loop: Header=BB217_2 Depth=1
 ; RV32IAXCHERI-NEXT:    mv a2, a4
@@ -15816,41 +15816,41 @@ define i64 @atomicrmw_umin_i64_release(i64 addrspace(200)* %a, i64 %b) nounwind
 ; RV32IAXCHERI-NEXT:    beqz a0, .LBB217_1
 ; RV32IAXCHERI-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # in Loop: Header=BB217_2 Depth=1
-; RV32IAXCHERI-NEXT:    mv a2, s2
+; RV32IAXCHERI-NEXT:    mv a2, s1
 ; RV32IAXCHERI-NEXT:    mv a3, s0
 ; RV32IAXCHERI-NEXT:    j .LBB217_1
 ; RV32IAXCHERI-NEXT:  .LBB217_7: # %atomicrmw.end
 ; RV32IAXCHERI-NEXT:    mv a0, a4
-; RV32IAXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs3, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IAXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s3, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_umin_i64_release:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -80
-; RV64IXCHERI-NEXT:    csc cra, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 16(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -80
+; RV64IXCHERI-NEXT:    csc ra, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 16(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    mv s0, a1
-; RV64IXCHERI-NEXT:    cmove cs2, ca0
-; RV64IXCHERI-NEXT:    cld a1, 0(ca0)
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 8
-; RV64IXCHERI-NEXT:    csetbounds cs1, ca0, 8
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    cld a1, 0(a0)
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 8
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 8
 ; RV64IXCHERI-NEXT:    j .LBB217_2
 ; RV64IXCHERI-NEXT:  .LBB217_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB217_2 Depth=1
-; RV64IXCHERI-NEXT:    csd a1, 8(csp)
+; RV64IXCHERI-NEXT:    csd a1, 8(sp)
 ; RV64IXCHERI-NEXT:    li a3, 3
-; RV64IXCHERI-NEXT:    cmove ca0, cs2
-; RV64IXCHERI-NEXT:    cmove ca1, cs1
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    li a4, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV64IXCHERI-NEXT:    cld a1, 8(csp)
+; RV64IXCHERI-NEXT:    cld a1, 8(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB217_4
 ; RV64IXCHERI-NEXT:  .LBB217_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -15862,16 +15862,16 @@ define i64 @atomicrmw_umin_i64_release(i64 addrspace(200)* %a, i64 %b) nounwind
 ; RV64IXCHERI-NEXT:    j .LBB217_1
 ; RV64IXCHERI-NEXT:  .LBB217_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 80
+; RV64IXCHERI-NEXT:    clc ra, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 80
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_umin_i64_release:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camominu.d.rl a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camominu.d.rl a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw umin i64 addrspace(200)* %a, i64 %b release
   ret i64 %1
@@ -15880,31 +15880,31 @@ define i64 @atomicrmw_umin_i64_release(i64 addrspace(200)* %a, i64 %b) nounwind
 define i64 @atomicrmw_umin_i64_acq_rel(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_umin_i64_acq_rel:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs3, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s3, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    mv s0, a2
-; RV32IXCHERI-NEXT:    mv s2, a1
-; RV32IXCHERI-NEXT:    cmove cs3, ca0
-; RV32IXCHERI-NEXT:    clw a1, 4(ca0)
-; RV32IXCHERI-NEXT:    clw a4, 0(ca0)
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 0
-; RV32IXCHERI-NEXT:    csetbounds cs1, ca0, 8
+; RV32IXCHERI-NEXT:    mv s1, a1
+; RV32IXCHERI-NEXT:    cmove s2, a0
+; RV32IXCHERI-NEXT:    clw a1, 4(a0)
+; RV32IXCHERI-NEXT:    clw a4, 0(a0)
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 0
+; RV32IXCHERI-NEXT:    csetbounds s3, a0, 8
 ; RV32IXCHERI-NEXT:    j .LBB218_2
 ; RV32IXCHERI-NEXT:  .LBB218_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB218_2 Depth=1
-; RV32IXCHERI-NEXT:    csw a4, 0(csp)
-; RV32IXCHERI-NEXT:    csw a1, 4(csp)
+; RV32IXCHERI-NEXT:    csw a4, 0(sp)
+; RV32IXCHERI-NEXT:    csw a1, 4(sp)
 ; RV32IXCHERI-NEXT:    li a4, 4
 ; RV32IXCHERI-NEXT:    li a5, 2
-; RV32IXCHERI-NEXT:    cmove ca0, cs3
-; RV32IXCHERI-NEXT:    cmove ca1, cs1
+; RV32IXCHERI-NEXT:    cmove a0, s2
+; RV32IXCHERI-NEXT:    cmove a1, s3
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV32IXCHERI-NEXT:    clw a1, 4(csp)
-; RV32IXCHERI-NEXT:    clw a4, 0(csp)
+; RV32IXCHERI-NEXT:    clw a1, 4(sp)
+; RV32IXCHERI-NEXT:    clw a4, 0(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB218_7
 ; RV32IXCHERI-NEXT:  .LBB218_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -15914,7 +15914,7 @@ define i64 @atomicrmw_umin_i64_acq_rel(i64 addrspace(200)* %a, i64 %b) nounwind
 ; RV32IXCHERI-NEXT:    sltu a0, s0, a1
 ; RV32IXCHERI-NEXT:    j .LBB218_5
 ; RV32IXCHERI-NEXT:  .LBB218_4: # in Loop: Header=BB218_2 Depth=1
-; RV32IXCHERI-NEXT:    sltu a0, s2, a4
+; RV32IXCHERI-NEXT:    sltu a0, s1, a4
 ; RV32IXCHERI-NEXT:  .LBB218_5: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB218_2 Depth=1
 ; RV32IXCHERI-NEXT:    mv a2, a4
@@ -15922,46 +15922,46 @@ define i64 @atomicrmw_umin_i64_acq_rel(i64 addrspace(200)* %a, i64 %b) nounwind
 ; RV32IXCHERI-NEXT:    beqz a0, .LBB218_1
 ; RV32IXCHERI-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB218_2 Depth=1
-; RV32IXCHERI-NEXT:    mv a2, s2
+; RV32IXCHERI-NEXT:    mv a2, s1
 ; RV32IXCHERI-NEXT:    mv a3, s0
 ; RV32IXCHERI-NEXT:    j .LBB218_1
 ; RV32IXCHERI-NEXT:  .LBB218_7: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a4
-; RV32IXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs3, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s3, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_umin_i64_acq_rel:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IAXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs3, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IAXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s3, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    mv s0, a2
-; RV32IAXCHERI-NEXT:    mv s2, a1
-; RV32IAXCHERI-NEXT:    cmove cs3, ca0
-; RV32IAXCHERI-NEXT:    clw a1, 4(ca0)
-; RV32IAXCHERI-NEXT:    clw a4, 0(ca0)
-; RV32IAXCHERI-NEXT:    cincoffset ca0, csp, 0
-; RV32IAXCHERI-NEXT:    csetbounds cs1, ca0, 8
+; RV32IAXCHERI-NEXT:    mv s1, a1
+; RV32IAXCHERI-NEXT:    cmove s2, a0
+; RV32IAXCHERI-NEXT:    clw a1, 4(a0)
+; RV32IAXCHERI-NEXT:    clw a4, 0(a0)
+; RV32IAXCHERI-NEXT:    cincoffset a0, sp, 0
+; RV32IAXCHERI-NEXT:    csetbounds s3, a0, 8
 ; RV32IAXCHERI-NEXT:    j .LBB218_2
 ; RV32IAXCHERI-NEXT:  .LBB218_1: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # in Loop: Header=BB218_2 Depth=1
-; RV32IAXCHERI-NEXT:    csw a4, 0(csp)
-; RV32IAXCHERI-NEXT:    csw a1, 4(csp)
+; RV32IAXCHERI-NEXT:    csw a4, 0(sp)
+; RV32IAXCHERI-NEXT:    csw a1, 4(sp)
 ; RV32IAXCHERI-NEXT:    li a4, 4
 ; RV32IAXCHERI-NEXT:    li a5, 2
-; RV32IAXCHERI-NEXT:    cmove ca0, cs3
-; RV32IAXCHERI-NEXT:    cmove ca1, cs1
+; RV32IAXCHERI-NEXT:    cmove a0, s2
+; RV32IAXCHERI-NEXT:    cmove a1, s3
 ; RV32IAXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV32IAXCHERI-NEXT:    clw a1, 4(csp)
-; RV32IAXCHERI-NEXT:    clw a4, 0(csp)
+; RV32IAXCHERI-NEXT:    clw a1, 4(sp)
+; RV32IAXCHERI-NEXT:    clw a4, 0(sp)
 ; RV32IAXCHERI-NEXT:    bnez a0, .LBB218_7
 ; RV32IAXCHERI-NEXT:  .LBB218_2: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -15971,7 +15971,7 @@ define i64 @atomicrmw_umin_i64_acq_rel(i64 addrspace(200)* %a, i64 %b) nounwind
 ; RV32IAXCHERI-NEXT:    sltu a0, s0, a1
 ; RV32IAXCHERI-NEXT:    j .LBB218_5
 ; RV32IAXCHERI-NEXT:  .LBB218_4: # in Loop: Header=BB218_2 Depth=1
-; RV32IAXCHERI-NEXT:    sltu a0, s2, a4
+; RV32IAXCHERI-NEXT:    sltu a0, s1, a4
 ; RV32IAXCHERI-NEXT:  .LBB218_5: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # in Loop: Header=BB218_2 Depth=1
 ; RV32IAXCHERI-NEXT:    mv a2, a4
@@ -15979,41 +15979,41 @@ define i64 @atomicrmw_umin_i64_acq_rel(i64 addrspace(200)* %a, i64 %b) nounwind
 ; RV32IAXCHERI-NEXT:    beqz a0, .LBB218_1
 ; RV32IAXCHERI-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # in Loop: Header=BB218_2 Depth=1
-; RV32IAXCHERI-NEXT:    mv a2, s2
+; RV32IAXCHERI-NEXT:    mv a2, s1
 ; RV32IAXCHERI-NEXT:    mv a3, s0
 ; RV32IAXCHERI-NEXT:    j .LBB218_1
 ; RV32IAXCHERI-NEXT:  .LBB218_7: # %atomicrmw.end
 ; RV32IAXCHERI-NEXT:    mv a0, a4
-; RV32IAXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs3, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IAXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s3, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_umin_i64_acq_rel:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -80
-; RV64IXCHERI-NEXT:    csc cra, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 16(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -80
+; RV64IXCHERI-NEXT:    csc ra, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 16(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    mv s0, a1
-; RV64IXCHERI-NEXT:    cmove cs2, ca0
-; RV64IXCHERI-NEXT:    cld a1, 0(ca0)
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 8
-; RV64IXCHERI-NEXT:    csetbounds cs1, ca0, 8
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    cld a1, 0(a0)
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 8
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 8
 ; RV64IXCHERI-NEXT:    j .LBB218_2
 ; RV64IXCHERI-NEXT:  .LBB218_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB218_2 Depth=1
-; RV64IXCHERI-NEXT:    csd a1, 8(csp)
+; RV64IXCHERI-NEXT:    csd a1, 8(sp)
 ; RV64IXCHERI-NEXT:    li a3, 4
 ; RV64IXCHERI-NEXT:    li a4, 2
-; RV64IXCHERI-NEXT:    cmove ca0, cs2
-; RV64IXCHERI-NEXT:    cmove ca1, cs1
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV64IXCHERI-NEXT:    cld a1, 8(csp)
+; RV64IXCHERI-NEXT:    cld a1, 8(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB218_4
 ; RV64IXCHERI-NEXT:  .LBB218_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -16025,16 +16025,16 @@ define i64 @atomicrmw_umin_i64_acq_rel(i64 addrspace(200)* %a, i64 %b) nounwind
 ; RV64IXCHERI-NEXT:    j .LBB218_1
 ; RV64IXCHERI-NEXT:  .LBB218_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 80
+; RV64IXCHERI-NEXT:    clc ra, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 80
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_umin_i64_acq_rel:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camominu.d.aqrl a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camominu.d.aqrl a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw umin i64 addrspace(200)* %a, i64 %b acq_rel
   ret i64 %1
@@ -16043,31 +16043,31 @@ define i64 @atomicrmw_umin_i64_acq_rel(i64 addrspace(200)* %a, i64 %b) nounwind
 define i64 @atomicrmw_umin_i64_seq_cst(i64 addrspace(200)* %a, i64 %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_umin_i64_seq_cst:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs3, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s3, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    mv s0, a2
-; RV32IXCHERI-NEXT:    mv s2, a1
-; RV32IXCHERI-NEXT:    cmove cs3, ca0
-; RV32IXCHERI-NEXT:    clw a1, 4(ca0)
-; RV32IXCHERI-NEXT:    clw a4, 0(ca0)
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 0
-; RV32IXCHERI-NEXT:    csetbounds cs1, ca0, 8
+; RV32IXCHERI-NEXT:    mv s1, a1
+; RV32IXCHERI-NEXT:    cmove s2, a0
+; RV32IXCHERI-NEXT:    clw a1, 4(a0)
+; RV32IXCHERI-NEXT:    clw a4, 0(a0)
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 0
+; RV32IXCHERI-NEXT:    csetbounds s3, a0, 8
 ; RV32IXCHERI-NEXT:    j .LBB219_2
 ; RV32IXCHERI-NEXT:  .LBB219_1: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB219_2 Depth=1
-; RV32IXCHERI-NEXT:    csw a4, 0(csp)
-; RV32IXCHERI-NEXT:    csw a1, 4(csp)
+; RV32IXCHERI-NEXT:    csw a4, 0(sp)
+; RV32IXCHERI-NEXT:    csw a1, 4(sp)
 ; RV32IXCHERI-NEXT:    li a4, 5
 ; RV32IXCHERI-NEXT:    li a5, 5
-; RV32IXCHERI-NEXT:    cmove ca0, cs3
-; RV32IXCHERI-NEXT:    cmove ca1, cs1
+; RV32IXCHERI-NEXT:    cmove a0, s2
+; RV32IXCHERI-NEXT:    cmove a1, s3
 ; RV32IXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV32IXCHERI-NEXT:    clw a1, 4(csp)
-; RV32IXCHERI-NEXT:    clw a4, 0(csp)
+; RV32IXCHERI-NEXT:    clw a1, 4(sp)
+; RV32IXCHERI-NEXT:    clw a4, 0(sp)
 ; RV32IXCHERI-NEXT:    bnez a0, .LBB219_7
 ; RV32IXCHERI-NEXT:  .LBB219_2: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -16077,7 +16077,7 @@ define i64 @atomicrmw_umin_i64_seq_cst(i64 addrspace(200)* %a, i64 %b) nounwind
 ; RV32IXCHERI-NEXT:    sltu a0, s0, a1
 ; RV32IXCHERI-NEXT:    j .LBB219_5
 ; RV32IXCHERI-NEXT:  .LBB219_4: # in Loop: Header=BB219_2 Depth=1
-; RV32IXCHERI-NEXT:    sltu a0, s2, a4
+; RV32IXCHERI-NEXT:    sltu a0, s1, a4
 ; RV32IXCHERI-NEXT:  .LBB219_5: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB219_2 Depth=1
 ; RV32IXCHERI-NEXT:    mv a2, a4
@@ -16085,46 +16085,46 @@ define i64 @atomicrmw_umin_i64_seq_cst(i64 addrspace(200)* %a, i64 %b) nounwind
 ; RV32IXCHERI-NEXT:    beqz a0, .LBB219_1
 ; RV32IXCHERI-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32IXCHERI-NEXT:    # in Loop: Header=BB219_2 Depth=1
-; RV32IXCHERI-NEXT:    mv a2, s2
+; RV32IXCHERI-NEXT:    mv a2, s1
 ; RV32IXCHERI-NEXT:    mv a3, s0
 ; RV32IXCHERI-NEXT:    j .LBB219_1
 ; RV32IXCHERI-NEXT:  .LBB219_7: # %atomicrmw.end
 ; RV32IXCHERI-NEXT:    mv a0, a4
-; RV32IXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs3, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s3, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_umin_i64_seq_cst:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IAXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
-; RV32IAXCHERI-NEXT:    csc cs3, 8(csp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IAXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
+; RV32IAXCHERI-NEXT:    csc s3, 8(sp) # 8-byte Folded Spill
 ; RV32IAXCHERI-NEXT:    mv s0, a2
-; RV32IAXCHERI-NEXT:    mv s2, a1
-; RV32IAXCHERI-NEXT:    cmove cs3, ca0
-; RV32IAXCHERI-NEXT:    clw a1, 4(ca0)
-; RV32IAXCHERI-NEXT:    clw a4, 0(ca0)
-; RV32IAXCHERI-NEXT:    cincoffset ca0, csp, 0
-; RV32IAXCHERI-NEXT:    csetbounds cs1, ca0, 8
+; RV32IAXCHERI-NEXT:    mv s1, a1
+; RV32IAXCHERI-NEXT:    cmove s2, a0
+; RV32IAXCHERI-NEXT:    clw a1, 4(a0)
+; RV32IAXCHERI-NEXT:    clw a4, 0(a0)
+; RV32IAXCHERI-NEXT:    cincoffset a0, sp, 0
+; RV32IAXCHERI-NEXT:    csetbounds s3, a0, 8
 ; RV32IAXCHERI-NEXT:    j .LBB219_2
 ; RV32IAXCHERI-NEXT:  .LBB219_1: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # in Loop: Header=BB219_2 Depth=1
-; RV32IAXCHERI-NEXT:    csw a4, 0(csp)
-; RV32IAXCHERI-NEXT:    csw a1, 4(csp)
+; RV32IAXCHERI-NEXT:    csw a4, 0(sp)
+; RV32IAXCHERI-NEXT:    csw a1, 4(sp)
 ; RV32IAXCHERI-NEXT:    li a4, 5
 ; RV32IAXCHERI-NEXT:    li a5, 5
-; RV32IAXCHERI-NEXT:    cmove ca0, cs3
-; RV32IAXCHERI-NEXT:    cmove ca1, cs1
+; RV32IAXCHERI-NEXT:    cmove a0, s2
+; RV32IAXCHERI-NEXT:    cmove a1, s3
 ; RV32IAXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV32IAXCHERI-NEXT:    clw a1, 4(csp)
-; RV32IAXCHERI-NEXT:    clw a4, 0(csp)
+; RV32IAXCHERI-NEXT:    clw a1, 4(sp)
+; RV32IAXCHERI-NEXT:    clw a4, 0(sp)
 ; RV32IAXCHERI-NEXT:    bnez a0, .LBB219_7
 ; RV32IAXCHERI-NEXT:  .LBB219_2: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -16134,7 +16134,7 @@ define i64 @atomicrmw_umin_i64_seq_cst(i64 addrspace(200)* %a, i64 %b) nounwind
 ; RV32IAXCHERI-NEXT:    sltu a0, s0, a1
 ; RV32IAXCHERI-NEXT:    j .LBB219_5
 ; RV32IAXCHERI-NEXT:  .LBB219_4: # in Loop: Header=BB219_2 Depth=1
-; RV32IAXCHERI-NEXT:    sltu a0, s2, a4
+; RV32IAXCHERI-NEXT:    sltu a0, s1, a4
 ; RV32IAXCHERI-NEXT:  .LBB219_5: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # in Loop: Header=BB219_2 Depth=1
 ; RV32IAXCHERI-NEXT:    mv a2, a4
@@ -16142,41 +16142,41 @@ define i64 @atomicrmw_umin_i64_seq_cst(i64 addrspace(200)* %a, i64 %b) nounwind
 ; RV32IAXCHERI-NEXT:    beqz a0, .LBB219_1
 ; RV32IAXCHERI-NEXT:  # %bb.6: # %atomicrmw.start
 ; RV32IAXCHERI-NEXT:    # in Loop: Header=BB219_2 Depth=1
-; RV32IAXCHERI-NEXT:    mv a2, s2
+; RV32IAXCHERI-NEXT:    mv a2, s1
 ; RV32IAXCHERI-NEXT:    mv a3, s0
 ; RV32IAXCHERI-NEXT:    j .LBB219_1
 ; RV32IAXCHERI-NEXT:  .LBB219_7: # %atomicrmw.end
 ; RV32IAXCHERI-NEXT:    mv a0, a4
-; RV32IAXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    clc cs3, 8(csp) # 8-byte Folded Reload
-; RV32IAXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IAXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    clc s3, 8(sp) # 8-byte Folded Reload
+; RV32IAXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_umin_i64_seq_cst:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -80
-; RV64IXCHERI-NEXT:    csc cra, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 48(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 32(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 16(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -80
+; RV64IXCHERI-NEXT:    csc ra, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 48(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 32(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 16(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    mv s0, a1
-; RV64IXCHERI-NEXT:    cmove cs2, ca0
-; RV64IXCHERI-NEXT:    cld a1, 0(ca0)
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 8
-; RV64IXCHERI-NEXT:    csetbounds cs1, ca0, 8
+; RV64IXCHERI-NEXT:    cmove s1, a0
+; RV64IXCHERI-NEXT:    cld a1, 0(a0)
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 8
+; RV64IXCHERI-NEXT:    csetbounds s2, a0, 8
 ; RV64IXCHERI-NEXT:    j .LBB219_2
 ; RV64IXCHERI-NEXT:  .LBB219_1: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # in Loop: Header=BB219_2 Depth=1
-; RV64IXCHERI-NEXT:    csd a1, 8(csp)
+; RV64IXCHERI-NEXT:    csd a1, 8(sp)
 ; RV64IXCHERI-NEXT:    li a3, 5
 ; RV64IXCHERI-NEXT:    li a4, 5
-; RV64IXCHERI-NEXT:    cmove ca0, cs2
-; RV64IXCHERI-NEXT:    cmove ca1, cs1
+; RV64IXCHERI-NEXT:    cmove a0, s1
+; RV64IXCHERI-NEXT:    cmove a1, s2
 ; RV64IXCHERI-NEXT:    ccall __atomic_compare_exchange_8
-; RV64IXCHERI-NEXT:    cld a1, 8(csp)
+; RV64IXCHERI-NEXT:    cld a1, 8(sp)
 ; RV64IXCHERI-NEXT:    bnez a0, .LBB219_4
 ; RV64IXCHERI-NEXT:  .LBB219_2: # %atomicrmw.start
 ; RV64IXCHERI-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -16188,16 +16188,16 @@ define i64 @atomicrmw_umin_i64_seq_cst(i64 addrspace(200)* %a, i64 %b) nounwind
 ; RV64IXCHERI-NEXT:    j .LBB219_1
 ; RV64IXCHERI-NEXT:  .LBB219_4: # %atomicrmw.end
 ; RV64IXCHERI-NEXT:    mv a0, a1
-; RV64IXCHERI-NEXT:    clc cra, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 48(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 32(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 80
+; RV64IXCHERI-NEXT:    clc ra, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 48(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 32(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 80
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_umin_i64_seq_cst:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camominu.d.aqrl a0, a1, (ca0)
+; RV64IAXCHERI-NEXT:    camominu.d.aqrl a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw umin i64 addrspace(200)* %a, i64 %b seq_cst
   ret i64 %1
@@ -16206,32 +16206,32 @@ define i64 @atomicrmw_umin_i64_seq_cst(i64 addrspace(200)* %a, i64 %b) nounwind
 define i8 addrspace(200)* @atomicrmw_xchg_cap_monotonic(i8 addrspace(200)* addrspace(200)* %a, i8 addrspace(200)* %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_xchg_cap_monotonic:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 0
 ; RV32IXCHERI-NEXT:    ccall __atomic_exchange_cap
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_xchg_cap_monotonic:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    camoswap.c ca0, ca1, (ca0)
+; RV32IAXCHERI-NEXT:    camoswap.c a0, a1, (a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_xchg_cap_monotonic:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 0
 ; RV64IXCHERI-NEXT:    ccall __atomic_exchange_cap
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_xchg_cap_monotonic:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camoswap.c ca0, ca1, (ca0)
+; RV64IAXCHERI-NEXT:    camoswap.c a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw xchg i8 addrspace(200)* addrspace(200)* %a, i8 addrspace(200)* %b monotonic
   ret i8 addrspace(200)* %1
@@ -16240,32 +16240,32 @@ define i8 addrspace(200)* @atomicrmw_xchg_cap_monotonic(i8 addrspace(200)* addrs
 define i8 addrspace(200)* @atomicrmw_xchg_cap_acquire(i8 addrspace(200)* addrspace(200)* %a, i8 addrspace(200)* %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_xchg_cap_acquire:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 2
 ; RV32IXCHERI-NEXT:    ccall __atomic_exchange_cap
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_xchg_cap_acquire:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    camoswap.c.aq ca0, ca1, (ca0)
+; RV32IAXCHERI-NEXT:    camoswap.c.aq a0, a1, (a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_xchg_cap_acquire:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 2
 ; RV64IXCHERI-NEXT:    ccall __atomic_exchange_cap
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_xchg_cap_acquire:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camoswap.c.aq ca0, ca1, (ca0)
+; RV64IAXCHERI-NEXT:    camoswap.c.aq a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw xchg i8 addrspace(200)* addrspace(200)* %a, i8 addrspace(200)* %b acquire
   ret i8 addrspace(200)* %1
@@ -16274,32 +16274,32 @@ define i8 addrspace(200)* @atomicrmw_xchg_cap_acquire(i8 addrspace(200)* addrspa
 define i8 addrspace(200)* @atomicrmw_xchg_cap_release(i8 addrspace(200)* addrspace(200)* %a, i8 addrspace(200)* %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_xchg_cap_release:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 3
 ; RV32IXCHERI-NEXT:    ccall __atomic_exchange_cap
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_xchg_cap_release:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    camoswap.c.rl ca0, ca1, (ca0)
+; RV32IAXCHERI-NEXT:    camoswap.c.rl a0, a1, (a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_xchg_cap_release:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 3
 ; RV64IXCHERI-NEXT:    ccall __atomic_exchange_cap
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_xchg_cap_release:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camoswap.c.rl ca0, ca1, (ca0)
+; RV64IAXCHERI-NEXT:    camoswap.c.rl a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw xchg i8 addrspace(200)* addrspace(200)* %a, i8 addrspace(200)* %b release
   ret i8 addrspace(200)* %1
@@ -16308,32 +16308,32 @@ define i8 addrspace(200)* @atomicrmw_xchg_cap_release(i8 addrspace(200)* addrspa
 define i8 addrspace(200)* @atomicrmw_xchg_cap_acq_rel(i8 addrspace(200)* addrspace(200)* %a, i8 addrspace(200)* %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_xchg_cap_acq_rel:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 4
 ; RV32IXCHERI-NEXT:    ccall __atomic_exchange_cap
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_xchg_cap_acq_rel:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    camoswap.c.aqrl ca0, ca1, (ca0)
+; RV32IAXCHERI-NEXT:    camoswap.c.aqrl a0, a1, (a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_xchg_cap_acq_rel:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 4
 ; RV64IXCHERI-NEXT:    ccall __atomic_exchange_cap
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_xchg_cap_acq_rel:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camoswap.c.aqrl ca0, ca1, (ca0)
+; RV64IAXCHERI-NEXT:    camoswap.c.aqrl a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw xchg i8 addrspace(200)* addrspace(200)* %a, i8 addrspace(200)* %b acq_rel
   ret i8 addrspace(200)* %1
@@ -16342,32 +16342,32 @@ define i8 addrspace(200)* @atomicrmw_xchg_cap_acq_rel(i8 addrspace(200)* addrspa
 define i8 addrspace(200)* @atomicrmw_xchg_cap_seq_cst(i8 addrspace(200)* addrspace(200)* %a, i8 addrspace(200)* %b) nounwind {
 ; RV32IXCHERI-LABEL: atomicrmw_xchg_cap_seq_cst:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    li a2, 5
 ; RV32IXCHERI-NEXT:    ccall __atomic_exchange_cap
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV32IAXCHERI-LABEL: atomicrmw_xchg_cap_seq_cst:
 ; RV32IAXCHERI:       # %bb.0:
-; RV32IAXCHERI-NEXT:    camoswap.c.aqrl ca0, ca1, (ca0)
+; RV32IAXCHERI-NEXT:    camoswap.c.aqrl a0, a1, (a0)
 ; RV32IAXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: atomicrmw_xchg_cap_seq_cst:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    li a2, 5
 ; RV64IXCHERI-NEXT:    ccall __atomic_exchange_cap
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
 ;
 ; RV64IAXCHERI-LABEL: atomicrmw_xchg_cap_seq_cst:
 ; RV64IAXCHERI:       # %bb.0:
-; RV64IAXCHERI-NEXT:    camoswap.c.aqrl ca0, ca1, (ca0)
+; RV64IAXCHERI-NEXT:    camoswap.c.aqrl a0, a1, (a0)
 ; RV64IAXCHERI-NEXT:    cret
   %1 = atomicrmw xchg i8 addrspace(200)* addrspace(200)* %a, i8 addrspace(200)* %b seq_cst
   ret i8 addrspace(200)* %1
diff --git a/llvm/test/CodeGen/RISCV/cheri/base-pointer.ll b/llvm/test/CodeGen/RISCV/cheri/base-pointer.ll
index 406935590aba1..72443c9b510ce 100644
--- a/llvm/test/CodeGen/RISCV/cheri/base-pointer.ll
+++ b/llvm/test/CodeGen/RISCV/cheri/base-pointer.ll
@@ -11,15 +11,15 @@ declare void @callee(i8 addrspace(200)*, i8 addrspace(200)*)
 define i32 @caller(i32 zeroext %n) nounwind {
 ; RV32IXCHERI-LABEL: caller:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -64
-; RV32IXCHERI-NEXT:    csc cra, 56(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 48(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs1, 40(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs2, 32(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    cincoffset cs0, csp, 64
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -64
+; RV32IXCHERI-NEXT:    csc ra, 56(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 48(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s1, 40(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s2, 32(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset s0, sp, 64
 ; RV32IXCHERI-NEXT:    andi a1, sp, -64
-; RV32IXCHERI-NEXT:    csetaddr csp, csp, a1
-; RV32IXCHERI-NEXT:    cmove cs1, csp
+; RV32IXCHERI-NEXT:    csetaddr sp, sp, a1
+; RV32IXCHERI-NEXT:    cmove s1, sp
 ; RV32IXCHERI-NEXT:    mv s2, a0
 ; RV32IXCHERI-NEXT:    addi a0, a0, 15
 ; RV32IXCHERI-NEXT:    andi a0, a0, -16
@@ -27,33 +27,33 @@ define i32 @caller(i32 zeroext %n) nounwind {
 ; RV32IXCHERI-NEXT:    sub a2, sp, a1
 ; RV32IXCHERI-NEXT:    cram a0, a0
 ; RV32IXCHERI-NEXT:    and a0, a2, a0
-; RV32IXCHERI-NEXT:    csetaddr ca0, csp, a0
-; RV32IXCHERI-NEXT:    csetbounds ca1, ca0, a1
-; RV32IXCHERI-NEXT:    cmove csp, ca0
-; RV32IXCHERI-NEXT:    csetbounds ca1, ca1, s2
-; RV32IXCHERI-NEXT:    cincoffset ca0, cs1, 0
-; RV32IXCHERI-NEXT:    csetbounds ca0, ca0, 1
+; RV32IXCHERI-NEXT:    csetaddr a0, sp, a0
+; RV32IXCHERI-NEXT:    csetbounds a1, a0, a1
+; RV32IXCHERI-NEXT:    cmove sp, a0
+; RV32IXCHERI-NEXT:    csetbounds a1, a1, s2
+; RV32IXCHERI-NEXT:    cincoffset a0, s1, 0
+; RV32IXCHERI-NEXT:    csetbounds a0, a0, 1
 ; RV32IXCHERI-NEXT:    ccall callee
 ; RV32IXCHERI-NEXT:    mv a0, s2
-; RV32IXCHERI-NEXT:    cincoffset csp, cs0, -64
-; RV32IXCHERI-NEXT:    clc cra, 56(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 48(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs1, 40(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs2, 32(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 64
+; RV32IXCHERI-NEXT:    cincoffset sp, s0, -64
+; RV32IXCHERI-NEXT:    clc ra, 56(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 48(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s1, 40(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s2, 32(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 64
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: caller:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -128
-; RV64IXCHERI-NEXT:    csc cra, 112(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 96(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs1, 80(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs2, 64(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    cincoffset cs0, csp, 128
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -128
+; RV64IXCHERI-NEXT:    csc ra, 112(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 96(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s1, 80(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s2, 64(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset s0, sp, 128
 ; RV64IXCHERI-NEXT:    andi a1, sp, -64
-; RV64IXCHERI-NEXT:    csetaddr csp, csp, a1
-; RV64IXCHERI-NEXT:    cmove cs1, csp
+; RV64IXCHERI-NEXT:    csetaddr sp, sp, a1
+; RV64IXCHERI-NEXT:    cmove s1, sp
 ; RV64IXCHERI-NEXT:    mv s2, a0
 ; RV64IXCHERI-NEXT:    addi a0, a0, 15
 ; RV64IXCHERI-NEXT:    andi a0, a0, -16
@@ -61,20 +61,20 @@ define i32 @caller(i32 zeroext %n) nounwind {
 ; RV64IXCHERI-NEXT:    sub a2, sp, a1
 ; RV64IXCHERI-NEXT:    cram a0, a0
 ; RV64IXCHERI-NEXT:    and a0, a2, a0
-; RV64IXCHERI-NEXT:    csetaddr ca0, csp, a0
-; RV64IXCHERI-NEXT:    csetbounds ca1, ca0, a1
-; RV64IXCHERI-NEXT:    cmove csp, ca0
-; RV64IXCHERI-NEXT:    csetbounds ca1, ca1, s2
-; RV64IXCHERI-NEXT:    cincoffset ca0, cs1, 0
-; RV64IXCHERI-NEXT:    csetbounds ca0, ca0, 1
+; RV64IXCHERI-NEXT:    csetaddr a0, sp, a0
+; RV64IXCHERI-NEXT:    csetbounds a1, a0, a1
+; RV64IXCHERI-NEXT:    cmove sp, a0
+; RV64IXCHERI-NEXT:    csetbounds a1, a1, s2
+; RV64IXCHERI-NEXT:    cincoffset a0, s1, 0
+; RV64IXCHERI-NEXT:    csetbounds a0, a0, 1
 ; RV64IXCHERI-NEXT:    ccall callee
 ; RV64IXCHERI-NEXT:    mv a0, s2
-; RV64IXCHERI-NEXT:    cincoffset csp, cs0, -128
-; RV64IXCHERI-NEXT:    clc cra, 112(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 96(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs1, 80(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs2, 64(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 128
+; RV64IXCHERI-NEXT:    cincoffset sp, s0, -128
+; RV64IXCHERI-NEXT:    clc ra, 112(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 96(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s1, 80(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s2, 64(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 128
 ; RV64IXCHERI-NEXT:    cret
   %1 = alloca i8, align 64, addrspace(200)
   %2 = alloca i8, i32 %n, addrspace(200)
diff --git a/llvm/test/CodeGen/RISCV/cheri/branch-relaxation.ll b/llvm/test/CodeGen/RISCV/cheri/branch-relaxation.ll
index d20074c623b94..b44ee069d34c8 100644
--- a/llvm/test/CodeGen/RISCV/cheri/branch-relaxation.ll
+++ b/llvm/test/CodeGen/RISCV/cheri/branch-relaxation.ll
@@ -34,11 +34,11 @@ tail:
 define i32 @relax_cjal(i1 %a) nounwind {
 ; CHECK-LABEL: relax_cjal:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    cincoffset csp, csp, -16
+; CHECK-NEXT:    cincoffset sp, sp, -16
 ; CHECK-NEXT:    andi a0, a0, 1
 ; CHECK-NEXT:    bnez a0, .LBB1_1
 ; CHECK-NEXT:  # %bb.4:
-; CHECK-NEXT:    cjump .LBB1_2, ca0
+; CHECK-NEXT:    cjump .LBB1_2, a0
 ; CHECK-NEXT:  .LBB1_1: # %iftrue
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    #NO_APP
@@ -51,7 +51,7 @@ define i32 @relax_cjal(i1 %a) nounwind {
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:  .LBB1_3: # %tail
 ; CHECK-NEXT:    li a0, 1
-; CHECK-NEXT:    cincoffset csp, csp, 16
+; CHECK-NEXT:    cincoffset sp, sp, 16
 ; CHECK-NEXT:    cret
   br i1 %a, label %iftrue, label %jmp
 
diff --git a/llvm/test/CodeGen/RISCV/cheri/calling-conv-common.ll b/llvm/test/CodeGen/RISCV/cheri/calling-conv-common.ll
index df60e3b2e9670..3b7213454a7e2 100644
--- a/llvm/test/CodeGen/RISCV/cheri/calling-conv-common.ll
+++ b/llvm/test/CodeGen/RISCV/cheri/calling-conv-common.ll
@@ -7,22 +7,22 @@
 define void @callee_cap_int(i8 addrspace(200)* %cap, i8 %int) nounwind {
 ; CHECK-ILP32-LABEL: callee_cap_int:
 ; CHECK-ILP32:       # %bb.0:
-; CHECK-ILP32-NEXT:    sb.cap a1, (ca0)
+; CHECK-ILP32-NEXT:    sb.cap a1, (a0)
 ; CHECK-ILP32-NEXT:    ret
 ;
 ; CHECK-LP64-LABEL: callee_cap_int:
 ; CHECK-LP64:       # %bb.0:
-; CHECK-LP64-NEXT:    sb.cap a1, (ca0)
+; CHECK-LP64-NEXT:    sb.cap a1, (a0)
 ; CHECK-LP64-NEXT:    ret
 ;
 ; CHECK-IL32PC64-LABEL: callee_cap_int:
 ; CHECK-IL32PC64:       # %bb.0:
-; CHECK-IL32PC64-NEXT:    csb a1, 0(ca0)
+; CHECK-IL32PC64-NEXT:    csb a1, 0(a0)
 ; CHECK-IL32PC64-NEXT:    cret
 ;
 ; CHECK-L64PC128-LABEL: callee_cap_int:
 ; CHECK-L64PC128:       # %bb.0:
-; CHECK-L64PC128-NEXT:    csb a1, 0(ca0)
+; CHECK-L64PC128-NEXT:    csb a1, 0(a0)
 ; CHECK-L64PC128-NEXT:    cret
   store i8 %int, i8 addrspace(200)* %cap
   ret void
@@ -31,22 +31,22 @@ define void @callee_cap_int(i8 addrspace(200)* %cap, i8 %int) nounwind {
 define void @callee_int_cap(i8 %int, i8 addrspace(200)* %cap) nounwind {
 ; CHECK-ILP32-LABEL: callee_int_cap:
 ; CHECK-ILP32:       # %bb.0:
-; CHECK-ILP32-NEXT:    sb.cap a0, (ca1)
+; CHECK-ILP32-NEXT:    sb.cap a0, (a1)
 ; CHECK-ILP32-NEXT:    ret
 ;
 ; CHECK-LP64-LABEL: callee_int_cap:
 ; CHECK-LP64:       # %bb.0:
-; CHECK-LP64-NEXT:    sb.cap a0, (ca1)
+; CHECK-LP64-NEXT:    sb.cap a0, (a1)
 ; CHECK-LP64-NEXT:    ret
 ;
 ; CHECK-IL32PC64-LABEL: callee_int_cap:
 ; CHECK-IL32PC64:       # %bb.0:
-; CHECK-IL32PC64-NEXT:    csb a0, 0(ca1)
+; CHECK-IL32PC64-NEXT:    csb a0, 0(a1)
 ; CHECK-IL32PC64-NEXT:    cret
 ;
 ; CHECK-L64PC128-LABEL: callee_int_cap:
 ; CHECK-L64PC128:       # %bb.0:
-; CHECK-L64PC128-NEXT:    csb a0, 0(ca1)
+; CHECK-L64PC128-NEXT:    csb a0, 0(a1)
 ; CHECK-L64PC128-NEXT:    cret
   store i8 %int, i8 addrspace(200)* %cap
   ret void
@@ -55,34 +55,34 @@ define void @callee_int_cap(i8 %int, i8 addrspace(200)* %cap) nounwind {
 define void @callee_cap_cap_int(i8 addrspace(200)* %dst, i8 addrspace(200)* %src, i32 signext %offset) nounwind {
 ; CHECK-ILP32-LABEL: callee_cap_cap_int:
 ; CHECK-ILP32:       # %bb.0:
-; CHECK-ILP32-NEXT:    cincoffset ca1, ca1, a2
-; CHECK-ILP32-NEXT:    lb.cap a1, (ca1)
-; CHECK-ILP32-NEXT:    cincoffset ca0, ca0, a2
-; CHECK-ILP32-NEXT:    sb.cap a1, (ca0)
+; CHECK-ILP32-NEXT:    cincoffset a1, a1, a2
+; CHECK-ILP32-NEXT:    lb.cap a1, (a1)
+; CHECK-ILP32-NEXT:    cincoffset a0, a0, a2
+; CHECK-ILP32-NEXT:    sb.cap a1, (a0)
 ; CHECK-ILP32-NEXT:    ret
 ;
 ; CHECK-LP64-LABEL: callee_cap_cap_int:
 ; CHECK-LP64:       # %bb.0:
-; CHECK-LP64-NEXT:    cincoffset ca1, ca1, a2
-; CHECK-LP64-NEXT:    lb.cap a1, (ca1)
-; CHECK-LP64-NEXT:    cincoffset ca0, ca0, a2
-; CHECK-LP64-NEXT:    sb.cap a1, (ca0)
+; CHECK-LP64-NEXT:    cincoffset a1, a1, a2
+; CHECK-LP64-NEXT:    lb.cap a1, (a1)
+; CHECK-LP64-NEXT:    cincoffset a0, a0, a2
+; CHECK-LP64-NEXT:    sb.cap a1, (a0)
 ; CHECK-LP64-NEXT:    ret
 ;
 ; CHECK-IL32PC64-LABEL: callee_cap_cap_int:
 ; CHECK-IL32PC64:       # %bb.0:
-; CHECK-IL32PC64-NEXT:    cincoffset ca1, ca1, a2
-; CHECK-IL32PC64-NEXT:    clb a1, 0(ca1)
-; CHECK-IL32PC64-NEXT:    cincoffset ca0, ca0, a2
-; CHECK-IL32PC64-NEXT:    csb a1, 0(ca0)
+; CHECK-IL32PC64-NEXT:    cincoffset a1, a1, a2
+; CHECK-IL32PC64-NEXT:    clb a1, 0(a1)
+; CHECK-IL32PC64-NEXT:    cincoffset a0, a0, a2
+; CHECK-IL32PC64-NEXT:    csb a1, 0(a0)
 ; CHECK-IL32PC64-NEXT:    cret
 ;
 ; CHECK-L64PC128-LABEL: callee_cap_cap_int:
 ; CHECK-L64PC128:       # %bb.0:
-; CHECK-L64PC128-NEXT:    cincoffset ca1, ca1, a2
-; CHECK-L64PC128-NEXT:    clb a1, 0(ca1)
-; CHECK-L64PC128-NEXT:    cincoffset ca0, ca0, a2
-; CHECK-L64PC128-NEXT:    csb a1, 0(ca0)
+; CHECK-L64PC128-NEXT:    cincoffset a1, a1, a2
+; CHECK-L64PC128-NEXT:    clb a1, 0(a1)
+; CHECK-L64PC128-NEXT:    cincoffset a0, a0, a2
+; CHECK-L64PC128-NEXT:    csb a1, 0(a0)
 ; CHECK-L64PC128-NEXT:    cret
   %srcoff = getelementptr inbounds i8, i8 addrspace(200)* %src, i32 %offset
   %val = load i8, i8 addrspace(200)* %srcoff
diff --git a/llvm/test/CodeGen/RISCV/cheri/calling-conv-il32pc64.ll b/llvm/test/CodeGen/RISCV/cheri/calling-conv-il32pc64.ll
index c803b2af2464c..e97b30f4c3dad 100644
--- a/llvm/test/CodeGen/RISCV/cheri/calling-conv-il32pc64.ll
+++ b/llvm/test/CodeGen/RISCV/cheri/calling-conv-il32pc64.ll
@@ -4,22 +4,22 @@
 define i32 @get_ith_word(i32 signext %i, ...) addrspace(200) nounwind {
 ; CHECK-LABEL: get_ith_word:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    cincoffset csp, csp, -16
-; CHECK-NEXT:    cincoffset ca1, csp, 8
-; CHECK-NEXT:    csetbounds ca1, ca1, 8
-; CHECK-NEXT:    cincoffset ca2, csp, 16
-; CHECK-NEXT:    csc ca2, 0(ca1)
-; CHECK-NEXT:    clc ca1, 8(csp)
+; CHECK-NEXT:    cincoffset sp, sp, -16
+; CHECK-NEXT:    cincoffset a1, sp, 8
+; CHECK-NEXT:    csetbounds a1, a1, 8
+; CHECK-NEXT:    cincoffset a2, sp, 16
+; CHECK-NEXT:    csc a2, 0(a1)
+; CHECK-NEXT:    clc a1, 8(sp)
 ; CHECK-NEXT:    addi a0, a0, 1
 ; CHECK-NEXT:  .LBB0_1: # %while.cond
 ; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    addi a0, a0, -1
-; CHECK-NEXT:    cincoffset ca1, ca1, 4
+; CHECK-NEXT:    cincoffset a1, a1, 4
 ; CHECK-NEXT:    bgtz a0, .LBB0_1
 ; CHECK-NEXT:  # %bb.2: # %while.end
-; CHECK-NEXT:    csc ca1, 8(csp)
-; CHECK-NEXT:    clw a0, -4(ca1)
-; CHECK-NEXT:    cincoffset csp, csp, 16
+; CHECK-NEXT:    csc a1, 8(sp)
+; CHECK-NEXT:    clw a0, -4(a1)
+; CHECK-NEXT:    cincoffset sp, sp, 16
 ; CHECK-NEXT:    cret
 entry:
   %ap = alloca ptr addrspace(200), align 8, addrspace(200)
@@ -49,25 +49,25 @@ while.end:                                        ; preds = %while.cond
 define ptr addrspace(200) @get_ith_cap(i32 signext %i, ...) addrspace(200) nounwind {
 ; CHECK-LABEL: get_ith_cap:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    cincoffset csp, csp, -16
-; CHECK-NEXT:    cincoffset ca1, csp, 8
-; CHECK-NEXT:    csetbounds ca1, ca1, 8
-; CHECK-NEXT:    cincoffset ca2, csp, 16
-; CHECK-NEXT:    csc ca2, 0(ca1)
-; CHECK-NEXT:    clc ca1, 8(csp)
+; CHECK-NEXT:    cincoffset sp, sp, -16
+; CHECK-NEXT:    cincoffset a1, sp, 8
+; CHECK-NEXT:    csetbounds a1, a1, 8
+; CHECK-NEXT:    cincoffset a2, sp, 16
+; CHECK-NEXT:    csc a2, 0(a1)
+; CHECK-NEXT:    clc a1, 8(sp)
 ; CHECK-NEXT:    addi a0, a0, 1
 ; CHECK-NEXT:  .LBB1_1: # %while.cond
 ; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    addi a2, a1, 7
 ; CHECK-NEXT:    andi a2, a2, -8
-; CHECK-NEXT:    csetaddr ca2, ca1, a2
+; CHECK-NEXT:    csetaddr a2, a1, a2
 ; CHECK-NEXT:    addi a0, a0, -1
-; CHECK-NEXT:    cincoffset ca1, ca2, 8
+; CHECK-NEXT:    cincoffset a1, a2, 8
 ; CHECK-NEXT:    bgtz a0, .LBB1_1
 ; CHECK-NEXT:  # %bb.2: # %while.end
-; CHECK-NEXT:    csc ca1, 8(csp)
-; CHECK-NEXT:    clc ca0, 0(ca2)
-; CHECK-NEXT:    cincoffset csp, csp, 16
+; CHECK-NEXT:    csc a1, 8(sp)
+; CHECK-NEXT:    clc a0, 0(a2)
+; CHECK-NEXT:    cincoffset sp, sp, 16
 ; CHECK-NEXT:    cret
 entry:
   %ap = alloca ptr addrspace(200), align 8, addrspace(200)
@@ -106,13 +106,13 @@ declare void @varargs(i32, ...) addrspace(200) nounwind
 define void @test_varargs_odd_cap_reg() nounwind {
 ; CHECK-LABEL: test_varargs_odd_cap_reg:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    cincoffset csp, csp, -16
-; CHECK-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; CHECK-NEXT:    cincoffset sp, sp, -16
+; CHECK-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; CHECK-NEXT:    li a0, 1
-; CHECK-NEXT:    csc cnull, 0(csp)
+; CHECK-NEXT:    csc zero, 0(sp)
 ; CHECK-NEXT:    ccall varargs
-; CHECK-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; CHECK-NEXT:    cincoffset csp, csp, 16
+; CHECK-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    cincoffset sp, sp, 16
 ; CHECK-NEXT:    cret
 entry:
   tail call addrspace(200) void (i32, ...) @varargs(i32 1, ptr addrspace(200) null)
diff --git a/llvm/test/CodeGen/RISCV/cheri/calling-conv-l64pc128.ll b/llvm/test/CodeGen/RISCV/cheri/calling-conv-l64pc128.ll
index 0be0086340c65..845a75de502f3 100644
--- a/llvm/test/CodeGen/RISCV/cheri/calling-conv-l64pc128.ll
+++ b/llvm/test/CodeGen/RISCV/cheri/calling-conv-l64pc128.ll
@@ -4,22 +4,22 @@
 define i32 @get_ith_word(i32 signext %i, ...) addrspace(200) nounwind {
 ; CHECK-LABEL: get_ith_word:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    cincoffset csp, csp, -16
-; CHECK-NEXT:    cincoffset ca1, csp, 0
-; CHECK-NEXT:    csetbounds ca1, ca1, 16
-; CHECK-NEXT:    cincoffset ca2, csp, 16
-; CHECK-NEXT:    csc ca2, 0(ca1)
-; CHECK-NEXT:    clc ca1, 0(csp)
+; CHECK-NEXT:    cincoffset sp, sp, -16
+; CHECK-NEXT:    cincoffset a1, sp, 0
+; CHECK-NEXT:    csetbounds a1, a1, 16
+; CHECK-NEXT:    cincoffset a2, sp, 16
+; CHECK-NEXT:    csc a2, 0(a1)
+; CHECK-NEXT:    clc a1, 0(sp)
 ; CHECK-NEXT:    addi a0, a0, 1
 ; CHECK-NEXT:  .LBB0_1: # %while.cond
 ; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    addiw a0, a0, -1
-; CHECK-NEXT:    cincoffset ca1, ca1, 4
+; CHECK-NEXT:    cincoffset a1, a1, 4
 ; CHECK-NEXT:    bgtz a0, .LBB0_1
 ; CHECK-NEXT:  # %bb.2: # %while.end
-; CHECK-NEXT:    csc ca1, 0(csp)
-; CHECK-NEXT:    clw a0, -4(ca1)
-; CHECK-NEXT:    cincoffset csp, csp, 16
+; CHECK-NEXT:    csc a1, 0(sp)
+; CHECK-NEXT:    clw a0, -4(a1)
+; CHECK-NEXT:    cincoffset sp, sp, 16
 ; CHECK-NEXT:    cret
 entry:
   %ap = alloca ptr addrspace(200), align 16, addrspace(200)
@@ -47,25 +47,25 @@ while.end:                                        ; preds = %while.cond
 define ptr addrspace(200) @get_ith_cap(i32 signext %i, ...) addrspace(200) nounwind {
 ; CHECK-LABEL: get_ith_cap:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    cincoffset csp, csp, -16
-; CHECK-NEXT:    cincoffset ca1, csp, 0
-; CHECK-NEXT:    csetbounds ca1, ca1, 16
-; CHECK-NEXT:    cincoffset ca2, csp, 16
-; CHECK-NEXT:    csc ca2, 0(ca1)
-; CHECK-NEXT:    clc ca1, 0(csp)
+; CHECK-NEXT:    cincoffset sp, sp, -16
+; CHECK-NEXT:    cincoffset a1, sp, 0
+; CHECK-NEXT:    csetbounds a1, a1, 16
+; CHECK-NEXT:    cincoffset a2, sp, 16
+; CHECK-NEXT:    csc a2, 0(a1)
+; CHECK-NEXT:    clc a1, 0(sp)
 ; CHECK-NEXT:    addi a0, a0, 1
 ; CHECK-NEXT:  .LBB1_1: # %while.cond
 ; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    addi a2, a1, 15
 ; CHECK-NEXT:    andi a2, a2, -16
-; CHECK-NEXT:    csetaddr ca2, ca1, a2
+; CHECK-NEXT:    csetaddr a2, a1, a2
 ; CHECK-NEXT:    addiw a0, a0, -1
-; CHECK-NEXT:    cincoffset ca1, ca2, 16
+; CHECK-NEXT:    cincoffset a1, a2, 16
 ; CHECK-NEXT:    bgtz a0, .LBB1_1
 ; CHECK-NEXT:  # %bb.2: # %while.end
-; CHECK-NEXT:    csc ca1, 0(csp)
-; CHECK-NEXT:    clc ca0, 0(ca2)
-; CHECK-NEXT:    cincoffset csp, csp, 16
+; CHECK-NEXT:    csc a1, 0(sp)
+; CHECK-NEXT:    clc a0, 0(a2)
+; CHECK-NEXT:    cincoffset sp, sp, 16
 ; CHECK-NEXT:    cret
 entry:
   %ap = alloca ptr addrspace(200), align 16, addrspace(200)
@@ -102,17 +102,17 @@ declare void @varargs(i32, ...) addrspace(200) nounwind
 ; go in an even integer register pair and would thus reserve the odd register,
 ; even though we're passing on the stack.
 define void @test_varargs_odd_cap_reg() addrspace(200) nounwind {
-entry:
 ; CHECK-LABEL: test_varargs_odd_cap_reg:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    cincoffset csp, csp, -32
-; CHECK-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
+; CHECK-NEXT:    cincoffset sp, sp, -32
+; CHECK-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
 ; CHECK-NEXT:    li a0, 1
-; CHECK-NEXT:    csc cnull, 0(csp)
+; CHECK-NEXT:    csc zero, 0(sp)
 ; CHECK-NEXT:    ccall varargs
-; CHECK-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; CHECK-NEXT:    cincoffset csp, csp, 32
+; CHECK-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; CHECK-NEXT:    cincoffset sp, sp, 32
 ; CHECK-NEXT:    cret
+entry:
   tail call void (i32, ...) @varargs(i32 1, ptr addrspace(200) null)
   ret void
 }
diff --git a/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-call-ccallee.ll b/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-call-ccallee.ll
index c84ff4d4609f3..218ed331bdb31 100644
--- a/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-call-ccallee.ll
+++ b/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-call-ccallee.ll
@@ -7,8 +7,8 @@ target triple = "riscv32-unknown-unknown"
 ; Function Attrs: nounwind
 define dso_local void @func() local_unnamed_addr addrspace(200) #0 {
 entry:
-  ; Make sure that there's a 4-byte stack argument passed in ct0.
-  ; CHECK:         csetbounds      ct0, csp, 4
+  ; Make sure that there's a 4-byte stack argument passed in t0.
+  ; CHECK:         csetbounds      t0, sp, 4
   call cheriot_compartmentcalleecc void @ccall(i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6) #2
   ret void
 }
diff --git a/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-call-libcall.ll b/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-call-libcall.ll
index beca1b4f0fb81..0a0ce6ab283d7 100644
--- a/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-call-libcall.ll
+++ b/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-call-libcall.ll
@@ -11,13 +11,13 @@ entry:
 ; compartment switcher.
 ; CHECK: li    a0, 1
 ; CHECK: li    a1, 2
-; CHECK: auipcc  ct2, %cheriot_compartment_hi(__library_import_libcalls_add)
-; CHECK: clc     ct2, %cheriot_compartment_lo_i(.LBB0_1)(ct2)
-; CHECK: cjalr   ct2
+; CHECK: auipcc  t2, %cheriot_compartment_hi(__library_import_libcalls_add)
+; CHECK: clc     t2, %cheriot_compartment_lo_i(.LBB0_1)(t2)
+; CHECK: cjalr   t2
   %call = tail call cheriot_librarycallcc i32 @add(i32 1, i32 2) #2
-; CHECK: auipcc  ct2, %cheriot_compartment_hi(__library_import_libcalls_foo)
-; CHECK: clc     ct2, %cheriot_compartment_lo_i(.LBB0_2)(ct2)
-; CHECK: cjalr   ct2
+; CHECK: auipcc  t2, %cheriot_compartment_hi(__library_import_libcalls_foo)
+; CHECK: clc     t2, %cheriot_compartment_lo_i(.LBB0_2)(t2)
+; CHECK: cjalr   t2
   %call1 = tail call cheriot_librarycallcc i32 @foo() #2
   %add = add nsw i32 %call1, %call
   ret i32 %add
diff --git a/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-ccall.ll b/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-ccall.ll
index 9f20b281eb505..fa304c31c39ff 100644
--- a/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-ccall.ll
+++ b/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-ccall.ll
@@ -24,7 +24,7 @@ entry:
 define dso_local cheriot_compartmentcalleecc i32 @test6(i32 addrspace(200)* nocapture readonly %a0, i32 addrspace(200)* nocapture readonly %a1, i32 addrspace(200)* nocapture readonly %a2, i32 addrspace(200)* nocapture readonly %a3, i32 addrspace(200)* nocapture readonly %a4, i32 addrspace(200)* nocapture readonly %a5) local_unnamed_addr addrspace(200) #1 {
 ; Check that we are loading the last register argument
 ; CHECK-LABEL: test6:
-; CHECK: clw     a5, 0(ca5)
+; CHECK: clw     a5, 0(a5)
 entry:
   %0 = load i32, i32 addrspace(200)* %a0, align 4, !tbaa !5
   %1 = load i32, i32 addrspace(200)* %a1, align 4, !tbaa !5
@@ -45,7 +45,7 @@ define dso_local cheriot_compartmentcalleecc i32 @test8(i32 addrspace(200)* noca
 ; Check that the last argument (used in the multiply) is loaded from offset 8
 ; in the stack-argument capability.
 ; CHECK-LABEL: test8:
-; CHECK: clc     [[CREG:[a-z]+[0-9]+]], 8(ct0)
+; CHECK: clc     [[CREG:[a-z]+[0-9]+]], 8(t0)
 ; CHECK: clw     [[IREG:[a-z]+[0-9]+]], 0([[CREG]])
 ; CHECK: mul
 ; CHECK-SAME: [[IREG]]
@@ -82,15 +82,15 @@ define dso_local i32 @testcall8() local_unnamed_addr addrspace(200) #2 {
 entry:
   ; Check that we have the right relocations and stack layout.
   ; CHECK-LABEL: testcall8:
-  ; CHECK:  auicgp  ct0, %cheriot_compartment_hi(testcall8.stack_arg)
-  ; CHECK:  cincoffset      ct0, ct0, %cheriot_compartment_lo_i
-  ; CHECK:  csetbounds      ct0, ct0, %cheriot_compartment_size(testcall8.stack_arg)
-  ; CHECK:  csc     ct0, 8(csp)
-  ; CHECK:  auipcc  ct1, %cheriot_compartment_hi(__import_other_test8callee)
-  ; CHECK:  clc     ct1, %cheriot_compartment_lo_i
-  ; CHECK:  auipcc  ct2, %cheriot_compartment_hi(.compartment_switcher)
-  ; CHECK:  clc     ct2, %cheriot_compartment_lo_i
-  ; CHECK:  cjalr ct2
+  ; CHECK:  auicgp  t0, %cheriot_compartment_hi(testcall8.stack_arg)
+  ; CHECK:  cincoffset      t0, t0, %cheriot_compartment_lo_i
+  ; CHECK:  csetbounds      t0, t0, %cheriot_compartment_size(testcall8.stack_arg)
+  ; CHECK:  csc     t0, 8(sp)
+  ; CHECK:  auipcc  t1, %cheriot_compartment_hi(__import_other_test8callee)
+  ; CHECK:  clc     t1, %cheriot_compartment_lo_i
+  ; CHECK:  auipcc  t2, %cheriot_compartment_hi(.compartment_switcher)
+  ; CHECK:  clc     t2, %cheriot_compartment_lo_i
+  ; CHECK:  cjalr t2
   %args = alloca [8 x i32], align 4, addrspace(200)
   %0 = bitcast [8 x i32] addrspace(200)* %args to i8 addrspace(200)*
   call void @llvm.lifetime.start.p200i8(i64 32, i8 addrspace(200)* nonnull %0) #5
diff --git a/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-ccallback.ll b/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-ccallback.ll
index 14beb623f7199..801d45183b6e9 100644
--- a/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-ccallback.ll
+++ b/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-ccallback.ll
@@ -11,16 +11,16 @@ define dso_local void @call_callback(i32 (i8 addrspace(200)*) addrspace(200)* no
 entry:
 ; Make sure that calling the callback has a sensible call sequence:
 ; CHECK-LABEL: call_callback:
-; Allocate 42 bytes of stack storage and store it in ca0
-; CHECK: cincoffset      ca0, csp,
-; CHECK: csetbounds      ca0, ca0, 42
+; Allocate 42 bytes of stack storage and store it in a0
+; CHECK: cincoffset      a0, sp,
+; CHECK: csetbounds      a0, a0, 42
 ; Move the argument register to the compartment switcher target
 ; TODO: We should be able to avoid the double move here.
-; CHECK: cmove   ct1
-; Load the compartment switcher into $ct2 and jump there
-; CHECK: auipcc  ct2, %cheriot_compartment_hi(.compartment_switcher)
-; CHECK: clc     ct2, %cheriot_compartment_lo_i(.LBB0_1)(ct2)
-; CHECK: cjalr   ct2
+; CHECK: cmove   t1
+; Load the compartment switcher into $t2 and jump there
+; CHECK: auipcc  t2, %cheriot_compartment_hi(.compartment_switcher)
+; CHECK: clc     t2, %cheriot_compartment_lo_i(.LBB0_1)(t2)
+; CHECK: cjalr   t2
   %buf = alloca [42 x i8], align 1, addrspace(200)
   %0 = getelementptr inbounds [42 x i8], [42 x i8] addrspace(200)* %buf, i32 0, i32 0
   %call = notail call cheriot_compartmentcallcc i32 %cb(i8 addrspace(200)* nonnull %0) #4
@@ -39,13 +39,13 @@ entry:
 ; CHECK-LABEL: pass_callback:
 ; Check that this call is loading the import table entry, not the function
 ; address
-; CHECK:         auipcc  ca0, %cheriot_compartment_hi(__import_comp_cb)
-; CHECK:         clc     ca0, %cheriot_compartment_lo_i(.LBB1_1)(ca0)
+; CHECK:         auipcc  a0, %cheriot_compartment_hi(__import_comp_cb)
+; CHECK:         clc     a0, %cheriot_compartment_lo_i(.LBB1_1)(a0)
 ; And make sure that it's really jumping to the right function.
 ; CHECK: ccall   take_callback
   call void @take_callback(i32 (i8 addrspace(200)*) addrspace(200)* nonnull @cb) #4
-; CHECK:         auipcc  ca0, %cheriot_compartment_hi(__import_comp_ecb)
-; CHECK:         clc     ca0, %cheriot_compartment_lo_i
+; CHECK:         auipcc  a0, %cheriot_compartment_hi(__import_comp_ecb)
+; CHECK:         clc     a0, %cheriot_compartment_lo_i
 ; CHECK: ccall   take_callback
   call void @take_callback(i32 (i8 addrspace(200)*) addrspace(200)* nonnull @ecb) #4
   ret void
diff --git a/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-define-libcall.ll b/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-define-libcall.ll
index 5fa663e76b6d4..e038344221be7 100644
--- a/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-define-libcall.ll
+++ b/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-define-libcall.ll
@@ -16,7 +16,7 @@ define dso_local cheriot_librarycallcc i32 @callFromLibcall() local_unnamed_addr
 entry:
 ; CHECK-LABEL: callFromLibcall:
 ; Calls to libcalls from the same compilation unit should be direct calls
-; CHECK: auipcc  ct2, %cheriot_compartment_hi(__library_import_libcalls_foo)
+; CHECK: auipcc  t2, %cheriot_compartment_hi(__library_import_libcalls_foo)
 ; CHECK-NOT: ccall   foo
 ; CHECK: ccall   add
   %call1 = tail call cheriot_librarycallcc i32 @foo() #3
diff --git a/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-exported-interrupts.ll b/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-exported-interrupts.ll
index e1db669d48de1..1289eca082513 100644
--- a/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-exported-interrupts.ll
+++ b/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-exported-interrupts.ll
@@ -15,9 +15,9 @@ entry:
 ; indirectly to use the correct sentries, that we call it with an import that
 ; doesn't conflict with the normal import.
 ; CHECK: _Z15internal_callerv:
-; CHECK:         auipcc ct2, %cheriot_compartment_hi(__library_import_example__Z5emptyv)
-; CHECK:         clc ct2, %cheriot_compartment_lo_i(
-; CHECK:         cjalr ct2
+; CHECK:         auipcc t2, %cheriot_compartment_hi(__library_import_example__Z5emptyv)
+; CHECK:         clc t2, %cheriot_compartment_lo_i(
+; CHECK:         cjalr t2
 ; CHECK: __library_import_example__Z5emptyv:
 ; Although the import is in the library call namespace, the export should not be.
 ; CHECK:         .word   __export_example__Z5emptyv+1
diff --git a/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-fnptr.ll b/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-fnptr.ll
index c0697142c4992..49c4b6a4cad88 100644
--- a/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-fnptr.ll
+++ b/llvm/test/CodeGen/RISCV/cheri/cheri-mcu-fnptr.ll
@@ -7,8 +7,8 @@ target triple = "riscv32-unknown-unknown"
 ; Function Attrs: mustprogress nofree norecurse nosync nounwind readnone willreturn
 define dso_local nonnull void () addrspace(200)* @x() local_unnamed_addr addrspace(200) #0 {
 entry:
-  ; CHECK: auipcc  ca0, %cheriot_compartment_hi(foo)
-  ; CHECK: cincoffset      ca0, ca0, %cheriot_compartment_lo_i(.LBB0_1)
+  ; CHECK: auipcc  a0, %cheriot_compartment_hi(foo)
+  ; CHECK: cincoffset      a0, a0, %cheriot_compartment_lo_i(.LBB0_1)
   ; CHECK-NOT: csetbounds
   ; CHECK: cret
   ret void () addrspace(200)* @foo
diff --git a/llvm/test/CodeGen/RISCV/cheri/cheriot-check-arg-permissions.ll b/llvm/test/CodeGen/RISCV/cheri/cheriot-check-arg-permissions.ll
index 5c28a2fd6f443..4807cbd735c35 100644
--- a/llvm/test/CodeGen/RISCV/cheri/cheriot-check-arg-permissions.ll
+++ b/llvm/test/CodeGen/RISCV/cheri/cheriot-check-arg-permissions.ll
@@ -18,16 +18,16 @@ define dso_local cheriot_compartmentcalleecc void @_Z4ret2v(%struct.ret addrspac
 entry:
   ; CHECK-LABEL: _Z4ret2v:
   ; Make sure that the base points to the current address
-  ; CHECK:      cgetbase        t2, ca0
+  ; CHECK:      cgetbase        t2, a0
   ; CHECK:      bne     a0, t2,
   ; Make sure that the base is above the current stack pointer
   ; CHECK:      blt     a0, sp,
   ; Make sure the length is sufficient for the returned structure
-  ; CHECK:      cgetlen t1, ca0
+  ; CHECK:      cgetlen t1, a0
   ; CHECK:      li    t2, 16
   ; CHECK:      blt     t1, t2,
   ; Make sure that the permissions are as expected
-  ; CHECK:      cgetperm t1, ca0
+  ; CHECK:      cgetperm t1, a0
   ; CHECK:      li    t2, 126
   ; CHECK:      bne     t1, t2,
   %a = getelementptr inbounds %struct.ret, %struct.ret addrspace(200)* %agg.result, i32 0, i32 0
@@ -37,7 +37,7 @@ entry:
   ret void
 }
 
-; A function with on-stack arguments.  These are passed in ct0.  As with sret
+; A function with on-stack arguments.  These are passed in t0.  As with sret
 ; pointers, they are not visible in the C/C++ abstract machine and so the
 ; compiler must insert the check that they are valid.
 
@@ -46,16 +46,16 @@ define dso_local cheriot_compartmentcalleecc i32 @_Z7bigargsiiiiiiii(i32 %a0, i3
 entry:
   ; CHECK-LABEL: _Z7bigargsiiiiiiii:
   ; Make sure that the base points to the current address
-  ; CHECK:      cgetbase        t2, ct0
+  ; CHECK:      cgetbase        t2, t0
   ; CHECK:      bne     t0, t2,
   ; Make sure that the base is above the current stack pointer
   ; CHECK:      blt     t0, sp,
   ; Make sure the length is sufficient for the returned structure
-  ; CHECK:      cgetlen t1, ct0
+  ; CHECK:      cgetlen t1, t0
   ; CHECK:      li    t2, 8
   ; CHECK:      blt     t1, t2,
   ; Make sure that the permissions are as expected
-  ; CHECK:      cgetperm t1, ct0
+  ; CHECK:      cgetperm t1, t0
   ; CHECK:      li    t2, 126
   ; CHECK:      bne     t1, t2,
   %add = add nsw i32 %a7, %a6
diff --git a/llvm/test/CodeGen/RISCV/cheri/cheriot-csetboundsexact.ll b/llvm/test/CodeGen/RISCV/cheri/cheriot-csetboundsexact.ll
index ada8cd923719d..b478a5df952b1 100644
--- a/llvm/test/CodeGen/RISCV/cheri/cheriot-csetboundsexact.ll
+++ b/llvm/test/CodeGen/RISCV/cheri/cheriot-csetboundsexact.ll
@@ -4,7 +4,7 @@
 define i8 addrspace(200)* @test1(i8 addrspace(200)* %cap, i32 %bounds) nounwind {
 ; CHECK-LABEL: test1:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    ct.csetbounds ca0, ca0, 3
+; CHECK-NEXT:    ct.csetbounds a0, a0, 3
 ; CHECK-NEXT:    ct.cret
   %newcap = call i8 addrspace(200)* @llvm.cheri.cap.bounds.set.exact.i32(i8 addrspace(200)* %cap, i32 3)
   ret i8 addrspace(200)* %newcap
@@ -13,7 +13,7 @@ define i8 addrspace(200)* @test1(i8 addrspace(200)* %cap, i32 %bounds) nounwind
 define i8 addrspace(200)* @test2(i8 addrspace(200)* %cap, i32 %bounds) nounwind {
 ; CHECK-LABEL: test2:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    ct.csetbounds ca0, ca0, 511
+; CHECK-NEXT:    ct.csetbounds a0, a0, 511
 ; CHECK-NEXT:    ct.cret
   %newcap = call i8 addrspace(200)* @llvm.cheri.cap.bounds.set.exact.i32(i8 addrspace(200)* %cap, i32 511)
   ret i8 addrspace(200)* %newcap
@@ -23,7 +23,7 @@ define i8 addrspace(200)* @test3(i8 addrspace(200)* %cap, i32 %bounds) nounwind
 ; CHECK-LABEL: test3:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    li a1, 512
-; CHECK-NEXT:    ct.csetboundsexact ca0, ca0, a1
+; CHECK-NEXT:    ct.csetboundsexact a0, a0, a1
 ; CHECK-NEXT:    ct.cret
   %newcap = call i8 addrspace(200)* @llvm.cheri.cap.bounds.set.exact.i32(i8 addrspace(200)* %cap, i32 512)
   ret i8 addrspace(200)* %newcap
diff --git a/llvm/test/CodeGen/RISCV/cheri/cheriot-csetboundsrounddown.ll b/llvm/test/CodeGen/RISCV/cheri/cheriot-csetboundsrounddown.ll
index a050f35debedd..78481f456b97b 100644
--- a/llvm/test/CodeGen/RISCV/cheri/cheriot-csetboundsrounddown.ll
+++ b/llvm/test/CodeGen/RISCV/cheri/cheriot-csetboundsrounddown.ll
@@ -6,7 +6,7 @@ target triple = "riscv32cheriot-unknown-cheriotrtos"
 define ptr addrspace(200) @foo(ptr addrspace(200) %cap, i32 noundef %b) addrspace(200) {
 ; CHECK-LABEL: foo:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    csetboundsrounddown ca0, ca0, a1
+; CHECK-NEXT:    csetboundsrounddown a0, a0, a1
 ; CHECK-NEXT:    cret
 entry:
   %0 = tail call ptr addrspace(200) @llvm.cheri.cap.bounds.set.round.down.i32(ptr addrspace(200) %cap, i32 %b)
diff --git a/llvm/test/CodeGen/RISCV/cheri/cheriot-f64-abi.ll b/llvm/test/CodeGen/RISCV/cheri/cheriot-f64-abi.ll
index a815ef38f84ea..c84ceea262dcd 100644
--- a/llvm/test/CodeGen/RISCV/cheri/cheriot-f64-abi.ll
+++ b/llvm/test/CodeGen/RISCV/cheri/cheriot-f64-abi.ll
@@ -19,7 +19,7 @@ entry:
 define dso_local noundef double @_Z6test02dd(double noundef %a, double noundef returned %b) local_unnamed_addr addrspace(200) #0 {
 ; CHECK-LABEL: _Z6test02dd:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    ct.cmove ca0, ca1
+; CHECK-NEXT:    ct.cmove a0, a1
 ; CHECK-NEXT:    ct.cret
 entry:
   ret double %b
@@ -29,7 +29,7 @@ entry:
 define dso_local noundef double @_Z6test03Pd(ptr addrspace(200) nocapture noundef readonly %a) local_unnamed_addr addrspace(200) #1 {
 ; CHECK-LABEL: _Z6test03Pd:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    ct.clc ca0, 0(ca0)
+; CHECK-NEXT:    ct.clc a0, 0(a0)
 ; CHECK-NEXT:    ct.cret
 entry:
   %0 = load double, ptr addrspace(200) %a, align 8, !tbaa !6
@@ -41,7 +41,7 @@ define dso_local noundef double @_Z6test04v() local_unnamed_addr addrspace(200)
 ; CHECK-LABEL: _Z6test04v:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lui a0, 261888
-; CHECK-NEXT:    ct.csethigh ca0, cnull, a0
+; CHECK-NEXT:    ct.csethigh a0, zero, a0
 ; CHECK-NEXT:    ct.cret
 entry:
   ret double 1.000000e+00
@@ -51,17 +51,17 @@ entry:
 define dso_local noundef double @_Z6test05d(double noundef %a) local_unnamed_addr addrspace(200) #0 {
 ; CHECK-LABEL: _Z6test05d:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    ct.cincoffset csp, csp, -16
-; CHECK-NEXT:    ct.csc cra, 8(csp) # 8-byte Folded Spill
+; CHECK-NEXT:    ct.cincoffset sp, sp, -16
+; CHECK-NEXT:    ct.csc ra, 8(sp) # 8-byte Folded Spill
 ; CHECK-NEXT:    lui a1, 261888
-; CHECK-NEXT:    ct.csethigh ca1, cnull, a1
+; CHECK-NEXT:    ct.csethigh a1, zero, a1
 ; CHECK-NEXT:  .LBB4_1: # %entry
 ; CHECK-NEXT:    # Label of block must be emitted
-; CHECK-NEXT:    ct.auipcc ct2, %cheriot_compartment_hi(__library_import_libcalls___adddf3)
-; CHECK-NEXT:    ct.clc ct2, %cheriot_compartment_lo_i(.LBB4_1)(ct2)
-; CHECK-NEXT:    ct.cjalr ct2
-; CHECK-NEXT:    ct.clc cra, 8(csp) # 8-byte Folded Reload
-; CHECK-NEXT:    ct.cincoffset csp, csp, 16
+; CHECK-NEXT:    ct.auipcc t2, %cheriot_compartment_hi(__library_import_libcalls___adddf3)
+; CHECK-NEXT:    ct.clc t2, %cheriot_compartment_lo_i(.LBB4_1)(t2)
+; CHECK-NEXT:    ct.cjalr t2
+; CHECK-NEXT:    ct.clc ra, 8(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ct.cincoffset sp, sp, 16
 ; CHECK-NEXT:    ct.cret
 entry:
   %add = fadd double %a, 1.000000e+00
@@ -72,16 +72,16 @@ entry:
 define dso_local noundef double @_Z6test06d(double noundef %a) local_unnamed_addr addrspace(200) #0 {
 ; CHECK-LABEL: _Z6test06d:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    ct.cincoffset csp, csp, -16
-; CHECK-NEXT:    ct.csc cra, 8(csp) # 8-byte Folded Spill
-; CHECK-NEXT:    ct.cmove ca1, cnull
+; CHECK-NEXT:    ct.cincoffset sp, sp, -16
+; CHECK-NEXT:    ct.csc ra, 8(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    ct.cmove a1, zero
 ; CHECK-NEXT:  .LBB5_1: # %entry
 ; CHECK-NEXT:    # Label of block must be emitted
-; CHECK-NEXT:    ct.auipcc ct2, %cheriot_compartment_hi(__library_import_libcalls___adddf3)
-; CHECK-NEXT:    ct.clc ct2, %cheriot_compartment_lo_i(.LBB5_1)(ct2)
-; CHECK-NEXT:    ct.cjalr ct2
-; CHECK-NEXT:    ct.clc cra, 8(csp) # 8-byte Folded Reload
-; CHECK-NEXT:    ct.cincoffset csp, csp, 16
+; CHECK-NEXT:    ct.auipcc t2, %cheriot_compartment_hi(__library_import_libcalls___adddf3)
+; CHECK-NEXT:    ct.clc t2, %cheriot_compartment_lo_i(.LBB5_1)(t2)
+; CHECK-NEXT:    ct.cjalr t2
+; CHECK-NEXT:    ct.clc ra, 8(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ct.cincoffset sp, sp, 16
 ; CHECK-NEXT:    ct.cret
 entry:
   %add = fadd double %a, 0.000000e+00
@@ -92,16 +92,16 @@ entry:
 define dso_local noundef double @_Z6test07dd(double noundef %a, double noundef %b) local_unnamed_addr addrspace(200) #0 {
 ; CHECK-LABEL: _Z6test07dd:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    ct.cincoffset csp, csp, -16
-; CHECK-NEXT:    ct.csc cra, 8(csp) # 8-byte Folded Spill
-; CHECK-NEXT:    ct.cmove ca1, cnull
+; CHECK-NEXT:    ct.cincoffset sp, sp, -16
+; CHECK-NEXT:    ct.csc ra, 8(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    ct.cmove a1, zero
 ; CHECK-NEXT:  .LBB6_1: # %entry
 ; CHECK-NEXT:    # Label of block must be emitted
-; CHECK-NEXT:    ct.auipcc ct2, %cheriot_compartment_hi(__library_import_libcalls___adddf3)
-; CHECK-NEXT:    ct.clc ct2, %cheriot_compartment_lo_i(.LBB6_1)(ct2)
-; CHECK-NEXT:    ct.cjalr ct2
-; CHECK-NEXT:    ct.clc cra, 8(csp) # 8-byte Folded Reload
-; CHECK-NEXT:    ct.cincoffset csp, csp, 16
+; CHECK-NEXT:    ct.auipcc t2, %cheriot_compartment_hi(__library_import_libcalls___adddf3)
+; CHECK-NEXT:    ct.clc t2, %cheriot_compartment_lo_i(.LBB6_1)(t2)
+; CHECK-NEXT:    ct.cjalr t2
+; CHECK-NEXT:    ct.clc ra, 8(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ct.cincoffset sp, sp, 16
 ; CHECK-NEXT:    ct.cret
 entry:
   %add = fadd double %a, 0.000000e+00
@@ -112,21 +112,21 @@ entry:
 define dso_local void @_Z6test08dPd(double noundef %a, ptr addrspace(200) nocapture noundef writeonly initializes((0, 8)) %b) local_unnamed_addr addrspace(200) #2 {
 ; CHECK-LABEL: _Z6test08dPd:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    ct.cincoffset csp, csp, -16
-; CHECK-NEXT:    ct.csc cra, 8(csp) # 8-byte Folded Spill
-; CHECK-NEXT:    ct.csc cs0, 0(csp) # 8-byte Folded Spill
-; CHECK-NEXT:    ct.cmove cs0, ca1
+; CHECK-NEXT:    ct.cincoffset sp, sp, -16
+; CHECK-NEXT:    ct.csc ra, 8(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    ct.csc s0, 0(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    ct.cmove s0, a1
 ; CHECK-NEXT:    lui a1, 261888
-; CHECK-NEXT:    ct.csethigh ca1, cnull, a1
+; CHECK-NEXT:    ct.csethigh a1, zero, a1
 ; CHECK-NEXT:  .LBB7_1: # %entry
 ; CHECK-NEXT:    # Label of block must be emitted
-; CHECK-NEXT:    ct.auipcc ct2, %cheriot_compartment_hi(__library_import_libcalls___adddf3)
-; CHECK-NEXT:    ct.clc ct2, %cheriot_compartment_lo_i(.LBB7_1)(ct2)
-; CHECK-NEXT:    ct.cjalr ct2
-; CHECK-NEXT:    ct.csc ca0, 0(cs0)
-; CHECK-NEXT:    ct.clc cra, 8(csp) # 8-byte Folded Reload
-; CHECK-NEXT:    ct.clc cs0, 0(csp) # 8-byte Folded Reload
-; CHECK-NEXT:    ct.cincoffset csp, csp, 16
+; CHECK-NEXT:    ct.auipcc t2, %cheriot_compartment_hi(__library_import_libcalls___adddf3)
+; CHECK-NEXT:    ct.clc t2, %cheriot_compartment_lo_i(.LBB7_1)(t2)
+; CHECK-NEXT:    ct.cjalr t2
+; CHECK-NEXT:    ct.csc a0, 0(s0)
+; CHECK-NEXT:    ct.clc ra, 8(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ct.clc s0, 0(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ct.cincoffset sp, sp, 16
 ; CHECK-NEXT:    ct.cret
 entry:
   %add = fadd double %a, 1.000000e+00
@@ -138,7 +138,7 @@ entry:
 define dso_local void @_Z6test09dPd(double noundef %a, ptr addrspace(200) nocapture noundef writeonly initializes((8, 16)) %b) local_unnamed_addr addrspace(200) #2 {
 ; CHECK-LABEL: _Z6test09dPd:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    ct.csc ca0, 8(ca1)
+; CHECK-NEXT:    ct.csc a0, 8(a1)
 ; CHECK-NEXT:    ct.cret
 entry:
   %arrayidx = getelementptr inbounds nuw i8, ptr addrspace(200) %b, i32 8
@@ -150,15 +150,15 @@ entry:
 define dso_local noundef double @_Z6test10dd(double noundef %a, double noundef %b) local_unnamed_addr addrspace(200) #0 {
 ; CHECK-LABEL: _Z6test10dd:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    ct.cincoffset csp, csp, -16
-; CHECK-NEXT:    ct.csc cra, 8(csp) # 8-byte Folded Spill
+; CHECK-NEXT:    ct.cincoffset sp, sp, -16
+; CHECK-NEXT:    ct.csc ra, 8(sp) # 8-byte Folded Spill
 ; CHECK-NEXT:  .LBB9_1: # %entry
 ; CHECK-NEXT:    # Label of block must be emitted
-; CHECK-NEXT:    ct.auipcc ct2, %cheriot_compartment_hi(__library_import_libcalls___subdf3)
-; CHECK-NEXT:    ct.clc ct2, %cheriot_compartment_lo_i(.LBB9_1)(ct2)
-; CHECK-NEXT:    ct.cjalr ct2
-; CHECK-NEXT:    ct.clc cra, 8(csp) # 8-byte Folded Reload
-; CHECK-NEXT:    ct.cincoffset csp, csp, 16
+; CHECK-NEXT:    ct.auipcc t2, %cheriot_compartment_hi(__library_import_libcalls___subdf3)
+; CHECK-NEXT:    ct.clc t2, %cheriot_compartment_lo_i(.LBB9_1)(t2)
+; CHECK-NEXT:    ct.cjalr t2
+; CHECK-NEXT:    ct.clc ra, 8(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ct.cincoffset sp, sp, 16
 ; CHECK-NEXT:    ct.cret
 entry:
   %sub = fsub double %a, %b
@@ -169,15 +169,15 @@ entry:
 define dso_local noundef double @_Z6test11dd(double noundef %a, double noundef %b) local_unnamed_addr addrspace(200) #0 {
 ; CHECK-LABEL: _Z6test11dd:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    ct.cincoffset csp, csp, -16
-; CHECK-NEXT:    ct.csc cra, 8(csp) # 8-byte Folded Spill
+; CHECK-NEXT:    ct.cincoffset sp, sp, -16
+; CHECK-NEXT:    ct.csc ra, 8(sp) # 8-byte Folded Spill
 ; CHECK-NEXT:  .LBB10_1: # %entry
 ; CHECK-NEXT:    # Label of block must be emitted
-; CHECK-NEXT:    ct.auipcc ct2, %cheriot_compartment_hi(__library_import_libcalls___muldf3)
-; CHECK-NEXT:    ct.clc ct2, %cheriot_compartment_lo_i(.LBB10_1)(ct2)
-; CHECK-NEXT:    ct.cjalr ct2
-; CHECK-NEXT:    ct.clc cra, 8(csp) # 8-byte Folded Reload
-; CHECK-NEXT:    ct.cincoffset csp, csp, 16
+; CHECK-NEXT:    ct.auipcc t2, %cheriot_compartment_hi(__library_import_libcalls___muldf3)
+; CHECK-NEXT:    ct.clc t2, %cheriot_compartment_lo_i(.LBB10_1)(t2)
+; CHECK-NEXT:    ct.cjalr t2
+; CHECK-NEXT:    ct.clc ra, 8(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ct.cincoffset sp, sp, 16
 ; CHECK-NEXT:    ct.cret
 entry:
   %mul = fmul double %a, %b
@@ -188,15 +188,15 @@ entry:
 define dso_local noundef double @_Z6test12dd(double noundef %a, double noundef %b) local_unnamed_addr addrspace(200) #0 {
 ; CHECK-LABEL: _Z6test12dd:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    ct.cincoffset csp, csp, -16
-; CHECK-NEXT:    ct.csc cra, 8(csp) # 8-byte Folded Spill
+; CHECK-NEXT:    ct.cincoffset sp, sp, -16
+; CHECK-NEXT:    ct.csc ra, 8(sp) # 8-byte Folded Spill
 ; CHECK-NEXT:  .LBB11_1: # %entry
 ; CHECK-NEXT:    # Label of block must be emitted
-; CHECK-NEXT:    ct.auipcc ct2, %cheriot_compartment_hi(__library_import_libcalls___divdf3)
-; CHECK-NEXT:    ct.clc ct2, %cheriot_compartment_lo_i(.LBB11_1)(ct2)
-; CHECK-NEXT:    ct.cjalr ct2
-; CHECK-NEXT:    ct.clc cra, 8(csp) # 8-byte Folded Reload
-; CHECK-NEXT:    ct.cincoffset csp, csp, 16
+; CHECK-NEXT:    ct.auipcc t2, %cheriot_compartment_hi(__library_import_libcalls___divdf3)
+; CHECK-NEXT:    ct.clc t2, %cheriot_compartment_lo_i(.LBB11_1)(t2)
+; CHECK-NEXT:    ct.cjalr t2
+; CHECK-NEXT:    ct.clc ra, 8(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ct.cincoffset sp, sp, 16
 ; CHECK-NEXT:    ct.cret
 entry:
   %div = fdiv double %a, %b
@@ -207,26 +207,26 @@ entry:
 define dso_local noundef double @_Z6test1310TwoDoubles(ptr addrspace(200) nocapture noundef readonly %in) local_unnamed_addr addrspace(200) #1 {
 ; CHECK-LABEL: _Z6test1310TwoDoubles:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    ct.cincoffset csp, csp, -16
-; CHECK-NEXT:    ct.csc cra, 8(csp) # 8-byte Folded Spill
-; CHECK-NEXT:    ct.csc cs0, 0(csp) # 8-byte Folded Spill
-; CHECK-NEXT:    ct.clc cs0, 0(ca0)
-; CHECK-NEXT:    ct.clc ca0, 8(ca0)
-; CHECK-NEXT:    ct.cmove ca1, ca0
+; CHECK-NEXT:    ct.cincoffset sp, sp, -16
+; CHECK-NEXT:    ct.csc ra, 8(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    ct.csc s0, 0(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    ct.clc s0, 0(a0)
+; CHECK-NEXT:    ct.clc a0, 8(a0)
+; CHECK-NEXT:    ct.cmove a1, a0
 ; CHECK-NEXT:  .LBB12_1: # %entry
 ; CHECK-NEXT:    # Label of block must be emitted
-; CHECK-NEXT:    ct.auipcc ct2, %cheriot_compartment_hi(__library_import_libcalls___adddf3)
-; CHECK-NEXT:    ct.clc ct2, %cheriot_compartment_lo_i(.LBB12_1)(ct2)
-; CHECK-NEXT:    ct.cjalr ct2
-; CHECK-NEXT:    ct.cmove ca1, cs0
+; CHECK-NEXT:    ct.auipcc t2, %cheriot_compartment_hi(__library_import_libcalls___adddf3)
+; CHECK-NEXT:    ct.clc t2, %cheriot_compartment_lo_i(.LBB12_1)(t2)
+; CHECK-NEXT:    ct.cjalr t2
+; CHECK-NEXT:    ct.cmove a1, s0
 ; CHECK-NEXT:  .LBB12_2: # %entry
 ; CHECK-NEXT:    # Label of block must be emitted
-; CHECK-NEXT:    ct.auipcc ct2, %cheriot_compartment_hi(__library_import_libcalls___adddf3)
-; CHECK-NEXT:    ct.clc ct2, %cheriot_compartment_lo_i(.LBB12_2)(ct2)
-; CHECK-NEXT:    ct.cjalr ct2
-; CHECK-NEXT:    ct.clc cra, 8(csp) # 8-byte Folded Reload
-; CHECK-NEXT:    ct.clc cs0, 0(csp) # 8-byte Folded Reload
-; CHECK-NEXT:    ct.cincoffset csp, csp, 16
+; CHECK-NEXT:    ct.auipcc t2, %cheriot_compartment_hi(__library_import_libcalls___adddf3)
+; CHECK-NEXT:    ct.clc t2, %cheriot_compartment_lo_i(.LBB12_2)(t2)
+; CHECK-NEXT:    ct.cjalr t2
+; CHECK-NEXT:    ct.clc ra, 8(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ct.clc s0, 0(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ct.cincoffset sp, sp, 16
 ; CHECK-NEXT:    ct.cret
 entry:
   %0 = load double, ptr addrspace(200) %in, align 8, !tbaa !10
@@ -243,10 +243,10 @@ declare double @llvm.fmuladd.f64(double, double, double) addrspace(200) #3
 define dso_local void @_Z6test13d(ptr addrspace(200) dead_on_unwind noalias nocapture writable writeonly sret(%struct.TwoDoubles) align 8 initializes((0, 16)) %agg.result, double noundef %a) local_unnamed_addr addrspace(200) #2 {
 ; CHECK-LABEL: _Z6test13d:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    ct.csc ca1, 0(ca0)
+; CHECK-NEXT:    ct.csc a1, 0(a0)
 ; CHECK-NEXT:    lui a1, 262272
-; CHECK-NEXT:    ct.csw a1, 12(ca0)
-; CHECK-NEXT:    ct.csw zero, 8(ca0)
+; CHECK-NEXT:    ct.csw a1, 12(a0)
+; CHECK-NEXT:    ct.csw zero, 8(a0)
 ; CHECK-NEXT:    ct.cret
 entry:
   store double %a, ptr addrspace(200) %agg.result, align 8, !tbaa !10
@@ -260,9 +260,9 @@ define dso_local void @_Z6test14d(ptr addrspace(200) dead_on_unwind noalias noca
 ; CHECK-LABEL: _Z6test14d:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lui a2, 262464
-; CHECK-NEXT:    ct.csw zero, 0(ca0)
-; CHECK-NEXT:    ct.csw a2, 4(ca0)
-; CHECK-NEXT:    ct.csc ca1, 8(ca0)
+; CHECK-NEXT:    ct.csw zero, 0(a0)
+; CHECK-NEXT:    ct.csw a2, 4(a0)
+; CHECK-NEXT:    ct.csc a1, 8(a0)
 ; CHECK-NEXT:    ct.cret
 entry:
   store double 5.000000e+00, ptr addrspace(200) %agg.result, align 8, !tbaa !10
@@ -275,15 +275,15 @@ entry:
 define dso_local noundef double @_Z6test15(i32 noundef %a) local_unnamed_addr addrspace(200) #0 {
 ; CHECK-LABEL: _Z6test15:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    ct.cincoffset csp, csp, -16
-; CHECK-NEXT:    ct.csc cra, 8(csp) # 8-byte Folded Spill
+; CHECK-NEXT:    ct.cincoffset sp, sp, -16
+; CHECK-NEXT:    ct.csc ra, 8(sp) # 8-byte Folded Spill
 ; CHECK-NEXT:  .LBB15_1: # %entry
 ; CHECK-NEXT:    # Label of block must be emitted
-; CHECK-NEXT:    ct.auipcc ct2, %cheriot_compartment_hi(__library_import_libcalls___floatunsidf)
-; CHECK-NEXT:    ct.clc ct2, %cheriot_compartment_lo_i(.LBB15_1)(ct2)
-; CHECK-NEXT:    ct.cjalr ct2
-; CHECK-NEXT:    ct.clc cra, 8(csp) # 8-byte Folded Reload
-; CHECK-NEXT:    ct.cincoffset csp, csp, 16
+; CHECK-NEXT:    ct.auipcc t2, %cheriot_compartment_hi(__library_import_libcalls___floatunsidf)
+; CHECK-NEXT:    ct.clc t2, %cheriot_compartment_lo_i(.LBB15_1)(t2)
+; CHECK-NEXT:    ct.cjalr t2
+; CHECK-NEXT:    ct.clc ra, 8(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ct.cincoffset sp, sp, 16
 ; CHECK-NEXT:    ct.cret
 entry:
   %b = uitofp i32 %a to double
@@ -294,15 +294,15 @@ entry:
 define dso_local noundef double @float2double(float noundef %x) local_unnamed_addr addrspace(200) #0 {
 ; CHECK-LABEL: float2double:
 ; CHECK:       # %bb.0: # %start
-; CHECK-NEXT:    ct.cincoffset csp, csp, -16
-; CHECK-NEXT:    ct.csc cra, 8(csp) # 8-byte Folded Spill
+; CHECK-NEXT:    ct.cincoffset sp, sp, -16
+; CHECK-NEXT:    ct.csc ra, 8(sp) # 8-byte Folded Spill
 ; CHECK-NEXT:  .LBB16_1: # %start
 ; CHECK-NEXT:    # Label of block must be emitted
-; CHECK-NEXT:    ct.auipcc ct2, %cheriot_compartment_hi(__library_import_libcalls___extendsfdf2)
-; CHECK-NEXT:    ct.clc ct2, %cheriot_compartment_lo_i(.LBB16_1)(ct2)
-; CHECK-NEXT:    ct.cjalr ct2
-; CHECK-NEXT:    ct.clc cra, 8(csp) # 8-byte Folded Reload
-; CHECK-NEXT:    ct.cincoffset csp, csp, 16
+; CHECK-NEXT:    ct.auipcc t2, %cheriot_compartment_hi(__library_import_libcalls___extendsfdf2)
+; CHECK-NEXT:    ct.clc t2, %cheriot_compartment_lo_i(.LBB16_1)(t2)
+; CHECK-NEXT:    ct.cjalr t2
+; CHECK-NEXT:    ct.clc ra, 8(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ct.cincoffset sp, sp, 16
 ; CHECK-NEXT:    ct.cret
 start:
   %a = fpext float %x to double
@@ -312,15 +312,15 @@ start:
 define dso_local noundef float @double2float(double noundef %x) local_unnamed_addr addrspace(200) #0 {
 ; CHECK-LABEL: double2float:
 ; CHECK:       # %bb.0: # %start
-; CHECK-NEXT:    ct.cincoffset csp, csp, -16
-; CHECK-NEXT:    ct.csc cra, 8(csp) # 8-byte Folded Spill
+; CHECK-NEXT:    ct.cincoffset sp, sp, -16
+; CHECK-NEXT:    ct.csc ra, 8(sp) # 8-byte Folded Spill
 ; CHECK-NEXT:  .LBB17_1: # %start
 ; CHECK-NEXT:    # Label of block must be emitted
-; CHECK-NEXT:    ct.auipcc ct2, %cheriot_compartment_hi(__library_import_libcalls___truncdfsf2)
-; CHECK-NEXT:    ct.clc ct2, %cheriot_compartment_lo_i(.LBB17_1)(ct2)
-; CHECK-NEXT:    ct.cjalr ct2
-; CHECK-NEXT:    ct.clc cra, 8(csp) # 8-byte Folded Reload
-; CHECK-NEXT:    ct.cincoffset csp, csp, 16
+; CHECK-NEXT:    ct.auipcc t2, %cheriot_compartment_hi(__library_import_libcalls___truncdfsf2)
+; CHECK-NEXT:    ct.clc t2, %cheriot_compartment_lo_i(.LBB17_1)(t2)
+; CHECK-NEXT:    ct.cjalr t2
+; CHECK-NEXT:    ct.clc ra, 8(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ct.cincoffset sp, sp, 16
 ; CHECK-NEXT:    ct.cret
 start:
   %a = fptrunc double %x to float
@@ -330,27 +330,27 @@ start:
 define dso_local noundef double @select_on_int(double noundef %x, double noundef %y, i64 noundef %z) local_unnamed_addr addrspace(200) #0 {
 ; CHECK-LABEL: select_on_int:
 ; CHECK:       # %bb.0: # %start
-; CHECK-NEXT:    ct.cincoffset csp, csp, -16
-; CHECK-NEXT:    ct.csc cra, 8(csp) # 8-byte Folded Spill
-; CHECK-NEXT:    ct.csc cs0, 0(csp) # 8-byte Folded Spill
+; CHECK-NEXT:    ct.cincoffset sp, sp, -16
+; CHECK-NEXT:    ct.csc ra, 8(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    ct.csc s0, 0(sp) # 8-byte Folded Spill
 ; CHECK-NEXT:    slti s0, a3, 0
 ; CHECK-NEXT:  .LBB18_4: # %start
 ; CHECK-NEXT:    # Label of block must be emitted
-; CHECK-NEXT:    ct.auipcc ct2, %cheriot_compartment_hi(__library_import_libcalls___ltdf2)
-; CHECK-NEXT:    ct.clc ct2, %cheriot_compartment_lo_i(.LBB18_4)(ct2)
-; CHECK-NEXT:    ct.cjalr ct2
+; CHECK-NEXT:    ct.auipcc t2, %cheriot_compartment_hi(__library_import_libcalls___ltdf2)
+; CHECK-NEXT:    ct.clc t2, %cheriot_compartment_lo_i(.LBB18_4)(t2)
+; CHECK-NEXT:    ct.cjalr t2
 ; CHECK-NEXT:    slti a0, a0, 0
 ; CHECK-NEXT:    bne s0, a0, .LBB18_2
 ; CHECK-NEXT:  # %bb.1: # %start
-; CHECK-NEXT:    ct.cmove ca0, cnull
+; CHECK-NEXT:    ct.cmove a0, zero
 ; CHECK-NEXT:    j .LBB18_3
 ; CHECK-NEXT:  .LBB18_2:
 ; CHECK-NEXT:    lui a0, 261888
-; CHECK-NEXT:    ct.csethigh ca0, cnull, a0
+; CHECK-NEXT:    ct.csethigh a0, zero, a0
 ; CHECK-NEXT:  .LBB18_3: # %start
-; CHECK-NEXT:    ct.clc cra, 8(csp) # 8-byte Folded Reload
-; CHECK-NEXT:    ct.clc cs0, 0(csp) # 8-byte Folded Reload
-; CHECK-NEXT:    ct.cincoffset csp, csp, 16
+; CHECK-NEXT:    ct.clc ra, 8(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ct.clc s0, 0(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ct.cincoffset sp, sp, 16
 ; CHECK-NEXT:    ct.cret
 start:
   %a = icmp slt i64 %z, 0
@@ -363,20 +363,20 @@ start:
 define dso_local void @trunc_store(ptr addrspace(200) noundef writeonly captures(none) initializes((0, 4)) %a, double noundef %b) local_unnamed_addr addrspace(200) #0 {
 ; CHECK-LABEL: trunc_store:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    ct.cincoffset csp, csp, -16
-; CHECK-NEXT:    ct.csc cra, 8(csp) # 8-byte Folded Spill
-; CHECK-NEXT:    ct.csc cs0, 0(csp) # 8-byte Folded Spill
-; CHECK-NEXT:    ct.cmove cs0, ca0
-; CHECK-NEXT:    ct.cmove ca0, ca1
+; CHECK-NEXT:    ct.cincoffset sp, sp, -16
+; CHECK-NEXT:    ct.csc ra, 8(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    ct.csc s0, 0(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    ct.cmove s0, a0
+; CHECK-NEXT:    ct.cmove a0, a1
 ; CHECK-NEXT:  .LBB19_1: # %entry
 ; CHECK-NEXT:    # Label of block must be emitted
-; CHECK-NEXT:    ct.auipcc ct2, %cheriot_compartment_hi(__library_import_libcalls___truncdfsf2)
-; CHECK-NEXT:    ct.clc ct2, %cheriot_compartment_lo_i(.LBB19_1)(ct2)
-; CHECK-NEXT:    ct.cjalr ct2
-; CHECK-NEXT:    ct.csw a0, 0(cs0)
-; CHECK-NEXT:    ct.clc cra, 8(csp) # 8-byte Folded Reload
-; CHECK-NEXT:    ct.clc cs0, 0(csp) # 8-byte Folded Reload
-; CHECK-NEXT:    ct.cincoffset csp, csp, 16
+; CHECK-NEXT:    ct.auipcc t2, %cheriot_compartment_hi(__library_import_libcalls___truncdfsf2)
+; CHECK-NEXT:    ct.clc t2, %cheriot_compartment_lo_i(.LBB19_1)(t2)
+; CHECK-NEXT:    ct.cjalr t2
+; CHECK-NEXT:    ct.csw a0, 0(s0)
+; CHECK-NEXT:    ct.clc ra, 8(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ct.clc s0, 0(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ct.cincoffset sp, sp, 16
 ; CHECK-NEXT:    ct.cret
 entry:
   %conv = fptrunc double %b to float
@@ -387,20 +387,20 @@ entry:
 define dso_local void @ext_store(ptr addrspace(200) noundef writeonly captures(none) initializes((0, 8)) %a, float noundef %b) local_unnamed_addr addrspace(200) #0 {
 ; CHECK-LABEL: ext_store:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    ct.cincoffset csp, csp, -16
-; CHECK-NEXT:    ct.csc cra, 8(csp) # 8-byte Folded Spill
-; CHECK-NEXT:    ct.csc cs0, 0(csp) # 8-byte Folded Spill
-; CHECK-NEXT:    ct.cmove cs0, ca0
+; CHECK-NEXT:    ct.cincoffset sp, sp, -16
+; CHECK-NEXT:    ct.csc ra, 8(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    ct.csc s0, 0(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    ct.cmove s0, a0
 ; CHECK-NEXT:    mv a0, a1
 ; CHECK-NEXT:  .LBB20_1: # %entry
 ; CHECK-NEXT:    # Label of block must be emitted
-; CHECK-NEXT:    ct.auipcc ct2, %cheriot_compartment_hi(__library_import_libcalls___extendsfdf2)
-; CHECK-NEXT:    ct.clc ct2, %cheriot_compartment_lo_i(.LBB20_1)(ct2)
-; CHECK-NEXT:    ct.cjalr ct2
-; CHECK-NEXT:    ct.csc ca0, 0(cs0)
-; CHECK-NEXT:    ct.clc cra, 8(csp) # 8-byte Folded Reload
-; CHECK-NEXT:    ct.clc cs0, 0(csp) # 8-byte Folded Reload
-; CHECK-NEXT:    ct.cincoffset csp, csp, 16
+; CHECK-NEXT:    ct.auipcc t2, %cheriot_compartment_hi(__library_import_libcalls___extendsfdf2)
+; CHECK-NEXT:    ct.clc t2, %cheriot_compartment_lo_i(.LBB20_1)(t2)
+; CHECK-NEXT:    ct.cjalr t2
+; CHECK-NEXT:    ct.csc a0, 0(s0)
+; CHECK-NEXT:    ct.clc ra, 8(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ct.clc s0, 0(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ct.cincoffset sp, sp, 16
 ; CHECK-NEXT:    ct.cret
 entry:
   %conv = fpext float %b to double
@@ -411,21 +411,21 @@ entry:
 define dso_local void @load_ext_store(ptr addrspace(200) noundef writeonly captures(none) initializes((0, 8)) %a, ptr addrspace(200) noundef readonly captures(none) %b) local_unnamed_addr addrspace(200) #1 {
 ; CHECK-LABEL: load_ext_store:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    ct.cincoffset csp, csp, -16
-; CHECK-NEXT:    ct.csc cra, 8(csp) # 8-byte Folded Spill
-; CHECK-NEXT:    ct.csc cs0, 0(csp) # 8-byte Folded Spill
-; CHECK-NEXT:    ct.clw a1, 0(ca1)
-; CHECK-NEXT:    ct.cmove cs0, ca0
+; CHECK-NEXT:    ct.cincoffset sp, sp, -16
+; CHECK-NEXT:    ct.csc ra, 8(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    ct.csc s0, 0(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    ct.clw a1, 0(a1)
+; CHECK-NEXT:    ct.cmove s0, a0
 ; CHECK-NEXT:    mv a0, a1
 ; CHECK-NEXT:  .LBB21_1: # %entry
 ; CHECK-NEXT:    # Label of block must be emitted
-; CHECK-NEXT:    ct.auipcc ct2, %cheriot_compartment_hi(__library_import_libcalls___extendsfdf2)
-; CHECK-NEXT:    ct.clc ct2, %cheriot_compartment_lo_i(.LBB21_1)(ct2)
-; CHECK-NEXT:    ct.cjalr ct2
-; CHECK-NEXT:    ct.csc ca0, 0(cs0)
-; CHECK-NEXT:    ct.clc cra, 8(csp) # 8-byte Folded Reload
-; CHECK-NEXT:    ct.clc cs0, 0(csp) # 8-byte Folded Reload
-; CHECK-NEXT:    ct.cincoffset csp, csp, 16
+; CHECK-NEXT:    ct.auipcc t2, %cheriot_compartment_hi(__library_import_libcalls___extendsfdf2)
+; CHECK-NEXT:    ct.clc t2, %cheriot_compartment_lo_i(.LBB21_1)(t2)
+; CHECK-NEXT:    ct.cjalr t2
+; CHECK-NEXT:    ct.csc a0, 0(s0)
+; CHECK-NEXT:    ct.clc ra, 8(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ct.clc s0, 0(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ct.cincoffset sp, sp, 16
 ; CHECK-NEXT:    ct.cret
 entry:
   %0 = load float, ptr addrspace(200) %b, align 4, !tbaa !6
@@ -437,20 +437,20 @@ entry:
 define dso_local void @load_trunc_store(ptr addrspace(200) noundef readonly captures(none) %a, ptr addrspace(200) noundef writeonly captures(none) initializes((0, 4)) %b) local_unnamed_addr addrspace(200) #1 {
 ; CHECK-LABEL: load_trunc_store:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    ct.cincoffset csp, csp, -16
-; CHECK-NEXT:    ct.csc cra, 8(csp) # 8-byte Folded Spill
-; CHECK-NEXT:    ct.csc cs0, 0(csp) # 8-byte Folded Spill
-; CHECK-NEXT:    ct.clc ca0, 0(ca0)
-; CHECK-NEXT:    ct.cmove cs0, ca1
+; CHECK-NEXT:    ct.cincoffset sp, sp, -16
+; CHECK-NEXT:    ct.csc ra, 8(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    ct.csc s0, 0(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    ct.clc a0, 0(a0)
+; CHECK-NEXT:    ct.cmove s0, a1
 ; CHECK-NEXT:  .LBB22_1: # %entry
 ; CHECK-NEXT:    # Label of block must be emitted
-; CHECK-NEXT:    ct.auipcc ct2, %cheriot_compartment_hi(__library_import_libcalls___truncdfsf2)
-; CHECK-NEXT:    ct.clc ct2, %cheriot_compartment_lo_i(.LBB22_1)(ct2)
-; CHECK-NEXT:    ct.cjalr ct2
-; CHECK-NEXT:    ct.csw a0, 0(cs0)
-; CHECK-NEXT:    ct.clc cra, 8(csp) # 8-byte Folded Reload
-; CHECK-NEXT:    ct.clc cs0, 0(csp) # 8-byte Folded Reload
-; CHECK-NEXT:    ct.cincoffset csp, csp, 16
+; CHECK-NEXT:    ct.auipcc t2, %cheriot_compartment_hi(__library_import_libcalls___truncdfsf2)
+; CHECK-NEXT:    ct.clc t2, %cheriot_compartment_lo_i(.LBB22_1)(t2)
+; CHECK-NEXT:    ct.cjalr t2
+; CHECK-NEXT:    ct.csw a0, 0(s0)
+; CHECK-NEXT:    ct.clc ra, 8(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ct.clc s0, 0(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ct.cincoffset sp, sp, 16
 ; CHECK-NEXT:    ct.cret
 entry:
   %0 = load double, ptr addrspace(200) %a, align 8, !tbaa !10
diff --git a/llvm/test/CodeGen/RISCV/cheri/cheriot-frame-checks.ll b/llvm/test/CodeGen/RISCV/cheri/cheriot-frame-checks.ll
index 6df20caf22272..009a7b30cf837 100644
--- a/llvm/test/CodeGen/RISCV/cheri/cheriot-frame-checks.ll
+++ b/llvm/test/CodeGen/RISCV/cheri/cheriot-frame-checks.ll
@@ -9,26 +9,26 @@ target triple = "riscv32-unknown-unknown"
 define dso_local cheriot_compartmentcalleecc noundef i32 @_Z22compartment_call_inneriiPKiiS0_ii(i32 noundef %0, i32 noundef %1, ptr addrspace(200) nocapture noundef readnone %2, i32 noundef %3, ptr addrspace(200) nocapture noundef readnone %4, i32 noundef %5, i32 noundef %6) local_unnamed_addr addrspace(200) #0 {
 ; CHECK-LABEL: _Z22compartment_call_inneriiPKiiS0_ii:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    cgetbase t2, ct0
+; CHECK-NEXT:    cgetbase t2, t0
 ; CHECK-NEXT:    bne t0, t2, .LBB0_1
 ; CHECK-NEXT:    blt t0, sp, .LBB0_1
-; CHECK-NEXT:    cgetlen t1, ct0
+; CHECK-NEXT:    cgetlen t1, t0
 ; CHECK-NEXT:    li t2, 4
 ; CHECK-NEXT:    blt t1, t2, .LBB0_1
-; CHECK-NEXT:    cgetperm t1, ct0
+; CHECK-NEXT:    cgetperm t1, t0
 ; CHECK-NEXT:    li t2, 126
 ; CHECK-NEXT:    bne t1, t2, .LBB0_1
-; CHECK-NEXT:    cincoffset csp, csp, -16
-; CHECK-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; CHECK-NEXT:    cincoffset sp, sp, -16
+; CHECK-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; CHECK-NEXT:  .LBB0_2: # Label of block must be emitted
-; CHECK-NEXT:    auipcc ca0, %cheriot_compartment_hi(.L.str)
-; CHECK-NEXT:    cincoffset ca0, ca0, %cheriot_compartment_lo_i(.LBB0_2)
-; CHECK-NEXT:    csetbounds ca0, ca0, %cheriot_compartment_size(.L.str)
+; CHECK-NEXT:    auipcc a0, %cheriot_compartment_hi(.L.str)
+; CHECK-NEXT:    cincoffset a0, a0, %cheriot_compartment_lo_i(.LBB0_2)
+; CHECK-NEXT:    csetbounds a0, a0, %cheriot_compartment_size(.L.str)
 ; CHECK-NEXT:    ccall _Z9debug_logIJEEvPKcDpT_
 ; CHECK-NEXT:    li a0, 0
 ; CHECK-NEXT:    li a1, 0
-; CHECK-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; CHECK-NEXT:    cincoffset csp, csp, 16
+; CHECK-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    cincoffset sp, sp, 16
 ; CHECK-NEXT:    cret
 ; CHECK-NEXT:  .LBB0_1:
 ; CHECK-NEXT:    li a0, -1
diff --git a/llvm/test/CodeGen/RISCV/cheri/cheriot-globals.ll b/llvm/test/CodeGen/RISCV/cheri/cheriot-globals.ll
index 2c99ffc706045..d73f288020c6a 100644
--- a/llvm/test/CodeGen/RISCV/cheri/cheriot-globals.ll
+++ b/llvm/test/CodeGen/RISCV/cheri/cheriot-globals.ll
@@ -17,7 +17,7 @@ entry:
   ; CHECK-SAME: %cheriot_compartment_hi(x)
   ; CHECK: cincoffset
   ; CHECK-SAME: %cheriot_compartment_lo_i
-  ; CHECK: csetbounds ca0, ca0, %cheriot_compartment_size(x)
+  ; CHECK: csetbounds a0, a0, %cheriot_compartment_size(x)
   ret i32 addrspace(200)* @x
 }
 
diff --git a/llvm/test/CodeGen/RISCV/cheri/cheriot-jump-table-address.ll b/llvm/test/CodeGen/RISCV/cheri/cheriot-jump-table-address.ll
index 8d4ff2866081f..7f03dc8d46152 100644
--- a/llvm/test/CodeGen/RISCV/cheri/cheriot-jump-table-address.ll
+++ b/llvm/test/CodeGen/RISCV/cheri/cheriot-jump-table-address.ll
@@ -7,9 +7,9 @@ target triple = "riscv32-unknown-unknown"
 define [2 x i32] @foo(i32 %searched) addrspace(200) {
 ; CHECK-LABEL: foo:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    cincoffset csp, csp, -16
+; CHECK-NEXT:    ct.cincoffset sp, sp, -16
 ; CHECK-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; CHECK-NEXT:    ct.csc ra, 8(sp) # 8-byte Folded Spill
 ; CHECK-NEXT:    .cfi_offset ra, -8
 ; CHECK-NEXT:    addi a0, a0, 1
 ; CHECK-NEXT:    li a1, 4
@@ -18,27 +18,27 @@ define [2 x i32] @foo(i32 %searched) addrspace(200) {
 ; CHECK-NEXT:    slli a0, a0, 2
 ; CHECK-NEXT:  .LBB0_4: # %entry
 ; CHECK-NEXT:    # Label of block must be emitted
-; CHECK-NEXT:    auipcc ca1, %cheriot_compartment_hi(.LJTI0_0)
-; CHECK-NEXT:    cincoffset ca1, ca1, %cheriot_compartment_lo_i(.LBB0_4)
-; CHECK-NEXT:    cincoffset ca0, ca1, a0
-; CHECK-NEXT:    clw a0, 0(ca0)
+; CHECK-NEXT:    ct.auipcc a1, %cheriot_compartment_hi(.LJTI0_0)
+; CHECK-NEXT:    ct.cincoffset a1, a1, %cheriot_compartment_lo_i(.LBB0_4)
+; CHECK-NEXT:    ct.cincoffset a0, a1, a0
+; CHECK-NEXT:    ct.clw a0, 0(a0)
 ; CHECK-NEXT:    li a1, 1
 ; CHECK-NEXT:  .LBB0_5: # %entry
 ; CHECK-NEXT:    # Label of block must be emitted
-; CHECK-NEXT:    auipcc ca2, %cheriot_compartment_hi(.Lfoo$jump_table_base)
-; CHECK-NEXT:    cincoffset ca2, ca2, %cheriot_compartment_lo_i(.LBB0_5)
-; CHECK-NEXT:    cincoffset ca2, ca2, a0
+; CHECK-NEXT:    ct.auipcc a2, %cheriot_compartment_hi(.Lfoo$jump_table_base)
+; CHECK-NEXT:    ct.cincoffset a2, a2, %cheriot_compartment_lo_i(.LBB0_5)
+; CHECK-NEXT:    ct.cincoffset a2, a2, a0
 ; CHECK-NEXT:    li a0, -1
-; CHECK-NEXT:    cjr ca2
+; CHECK-NEXT:    ct.cjr a2
 ; CHECK-NEXT:  .LBB0_2: # %sw.epilog
 ; CHECK-NEXT:    li a0, 0
 ; CHECK-NEXT:    li a1, 0
 ; CHECK-NEXT:  .LBB0_3: # %cleanup
-; CHECK-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
+; CHECK-NEXT:    ct.clc ra, 8(sp) # 8-byte Folded Reload
 ; CHECK-NEXT:    .cfi_restore ra
-; CHECK-NEXT:    cincoffset csp, csp, 16
+; CHECK-NEXT:    ct.cincoffset sp, sp, 16
 ; CHECK-NEXT:    .cfi_def_cfa_offset 0
-; CHECK-NEXT:    cret
+; CHECK-NEXT:    ct.cret
 entry:
   switch i32 %searched, label %sw.epilog [
     i32 -1, label %cleanup
diff --git a/llvm/test/CodeGen/RISCV/cheri/cheriot-jumptable.ll b/llvm/test/CodeGen/RISCV/cheri/cheriot-jumptable.ll
index 1eb2698c9eae3..3d14179a69c01 100644
--- a/llvm/test/CodeGen/RISCV/cheri/cheriot-jumptable.ll
+++ b/llvm/test/CodeGen/RISCV/cheri/cheriot-jumptable.ll
@@ -11,21 +11,21 @@ define dso_local cheriot_compartmentcalleecc i32 @_Z2swi(i32 noundef %v) local_u
 ; CHECK-NEXT:    li a1, 8
 ; CHECK-NEXT:    bltu a1, a0, .LBB0_13
 ; CHECK-NEXT:  # %bb.1: # %entry
-; CHECK-NEXT:    cincoffset csp, csp, -16
-; CHECK-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; CHECK-NEXT:    cincoffset sp, sp, -16
+; CHECK-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; CHECK-NEXT:    slli a0, a0, 2
 ; CHECK-NEXT:  .LBB0_14: # %entry
 ; CHECK-NEXT:    # Label of block must be emitted
-; CHECK-NEXT:    auipcc ca1, %cheriot_compartment_hi(.LJTI0_0)
-; CHECK-NEXT:    cincoffset ca1, ca1, %cheriot_compartment_lo_i(.LBB0_14)
-; CHECK-NEXT:    cincoffset ca0, ca1, a0
-; CHECK-NEXT:    clw a0, 0(ca0)
+; CHECK-NEXT:    auipcc a1, %cheriot_compartment_hi(.LJTI0_0)
+; CHECK-NEXT:    cincoffset a1, a1, %cheriot_compartment_lo_i(.LBB0_14)
+; CHECK-NEXT:    cincoffset a0, a1, a0
+; CHECK-NEXT:    clw a0, 0(a0)
 ; CHECK-NEXT:  .LBB0_15: # %entry
 ; CHECK-NEXT:    # Label of block must be emitted
-; CHECK-NEXT:    auipcc ca1, %cheriot_compartment_hi(.L_Z2swi$jump_table_base)
-; CHECK-NEXT:    cincoffset ca1, ca1, %cheriot_compartment_lo_i(.LBB0_15)
-; CHECK-NEXT:    cincoffset ca0, ca1, a0
-; CHECK-NEXT:    cjr ca0
+; CHECK-NEXT:    auipcc a1, %cheriot_compartment_hi(.L_Z2swi$jump_table_base)
+; CHECK-NEXT:    cincoffset a1, a1, %cheriot_compartment_lo_i(.LBB0_15)
+; CHECK-NEXT:    cincoffset a0, a1, a0
+; CHECK-NEXT:    cjr a0
 ; CHECK-NEXT:  .LBB0_2: # %sw.bb
 ; CHECK-NEXT:    ccall a
 ; CHECK-NEXT:    j .LBB0_11
@@ -54,8 +54,8 @@ define dso_local cheriot_compartmentcalleecc i32 @_Z2swi(i32 noundef %v) local_u
 ; CHECK-NEXT:    ccall i
 ; CHECK-NEXT:  .LBB0_11:
 ; CHECK-NEXT:    addi a0, a0, 12
-; CHECK-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; CHECK-NEXT:    cincoffset csp, csp, 16
+; CHECK-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    cincoffset sp, sp, 16
 ; CHECK-NEXT:  .LBB0_12: # %sw.epilog
 ; CHECK-NEXT:    slli a0, a0, 1
 ; CHECK-NEXT:    li a1, 0
diff --git a/llvm/test/CodeGen/RISCV/cheri/cheriot-load-store-relocs.ll b/llvm/test/CodeGen/RISCV/cheri/cheriot-load-store-relocs.ll
index 19581264e9ed0..af61d26169915 100644
--- a/llvm/test/CodeGen/RISCV/cheri/cheriot-load-store-relocs.ll
+++ b/llvm/test/CodeGen/RISCV/cheri/cheriot-load-store-relocs.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
 ; RUN: llc --filetype=asm --mcpu=cheriot --mtriple=riscv32-unknown-unknown -target-abi cheriot  %s -mattr=+xcheri,+xcheripurecap -o - | FileCheck %s
 ; ModuleID = 'ex.c'
 target datalayout = "e-m:e-pf200:64:64:64:32-p:32:32-i64:64-n32-S128-A200-P200-G200"
@@ -9,16 +10,22 @@ target triple = "riscv32-unknown-unknown"
 
 ; Function Attrs: minsize mustprogress nofree norecurse nosync nounwind optsize willreturn
 define dso_local i32 @example_entry(i32 addrspace(200)* nocapture readnone %input) local_unnamed_addr addrspace(200) #0 {
+; CHECK-LABEL: example_entry:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:  .LBB0_1: # %entry
+; CHECK-NEXT:    # Label of block must be emitted
+; CHECK-NEXT:    auicgp a1, %cheriot_compartment_hi(temp)
+; CHECK-NEXT:    cincoffset a1, a1, %cheriot_compartment_lo_i(.LBB0_1)
+; CHECK-NEXT:    clw a0, 0(a1)
+; CHECK-NEXT:    addi a2, a0, 1
+; CHECK-NEXT:    csw a2, 0(a1)
+; CHECK-NEXT:    cret
 entry:
   ; Check that we generate relocations folded into the loads and stores for
   ; globals.  This is currently broken by the move to post-RA expansion of
   ; cllc.  Keep the test around to check for the new sequence.  If the
   ; optimisation is reintroduced, delete the X from the XCHECK lines.
-  ; CHECK: auicgp
-  ; CHECK-SAME: %cheriot_compartment_hi(temp)
   ; XCHECK: clw
-  ; CHECK: cincoffset
-  ; CHECK-SAME: %cheriot_compartment_lo_i
   %0 = load i32, i32 addrspace(200)* @temp, align 4, !tbaa !5
   %inc = add nsw i32 %0, 1
   store i32 %inc, i32 addrspace(200)* @temp, align 4, !tbaa !5
@@ -27,19 +34,21 @@ entry:
 
 ; Function Attrs: mustprogress nofree norecurse nosync nounwind readnone willreturn
 define dso_local i32 addrspace(200)* @getBigArray() local_unnamed_addr addrspace(200) #0 {
+; CHECK-LABEL: getBigArray:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lui a0, 1
+; CHECK-NEXT:    addi a0, a0, 4
+; CHECK-NEXT:  .LBB1_1: # %entry
+; CHECK-NEXT:    # Label of block must be emitted
+; CHECK-NEXT:    auicgp a1, %cheriot_compartment_hi(bigArray)
+; CHECK-NEXT:    cincoffset a1, a1, %cheriot_compartment_lo_i(.LBB1_1)
+; CHECK-NEXT:    csetbounds a0, a1, a0
+; CHECK-NEXT:    cret
 entry:
-  ; CHECK-LABEL: getBigArray:
   ; Check that we're materialising the constant with two instructions
-  ; CHECK: lui [[BOUNDS_HI:[a-z]+[0-9]+]], 1
-  ; CHECK: addi [[BOUNDS:[a-z]+[0-9]+]], [[BOUNDS_HI]], 4
   ; Check that we're using the correct relocation for the global
-  ; CHECK: auicgp
-  ; CHECK-SAME: %cheriot_compartment_hi(bigArray)
-  ; CHECK: cincoffset
-  ; CHECK-SAME: %cheriot_compartment_lo_i
   ; Slightly hacky pattern to make sure that we're emitting the using the value
   ; that we calculated, rather than an immediate or relocation.
-  ; CHECK: csetbounds	c{{.[0-9]+}}, c{{.[0-9]+}}, [[BOUNDS]]
 
   ret i32 addrspace(200)* getelementptr inbounds ([1025 x i32], [1025 x i32] addrspace(200)* @bigArray, i32 0, i32 0)
 }
diff --git a/llvm/test/CodeGen/RISCV/cheri/cheriot-offset-get.ll b/llvm/test/CodeGen/RISCV/cheri/cheriot-offset-get.ll
index 3a0663fc59b76..f4702ef3decfa 100644
--- a/llvm/test/CodeGen/RISCV/cheri/cheriot-offset-get.ll
+++ b/llvm/test/CodeGen/RISCV/cheri/cheriot-offset-get.ll
@@ -4,7 +4,7 @@
 define i32 @test1(i8 addrspace(200)* %cap) nounwind {
 ; CHECK-LABEL: test1:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    ct.cgetbase a1, ca0
+; CHECK-NEXT:    ct.cgetbase a1, a0
 ; CHECK-NEXT:    sub a0, a0, a1
 ; CHECK-NEXT:    ct.cret
   %newcap = call i32 @llvm.cheri.cap.offset.get.i32(i8 addrspace(200)* %cap)
diff --git a/llvm/test/CodeGen/RISCV/cheri/cheriot-sealed-attr.ll b/llvm/test/CodeGen/RISCV/cheri/cheriot-sealed-attr.ll
index bd27dd86c8bd6..f973b510a47ec 100644
--- a/llvm/test/CodeGen/RISCV/cheri/cheriot-sealed-attr.ll
+++ b/llvm/test/CodeGen/RISCV/cheri/cheriot-sealed-attr.ll
@@ -19,17 +19,17 @@ entry:
 
 ;; CHECK:        .LBB0_1:                                # %entry
 ;; CHECK-NEXT:                                           # Label of block must be emitted
-;; CHECK-NEXT:      auipcc	ca0, %cheriot_compartment_hi(__import.sealed_object.test)
-;; CHECK-NEXT:      clc	ca0, %cheriot_compartment_lo_i(.LBB0_1)(ca0)
+;; CHECK-NEXT:      auipcc	a0, %cheriot_compartment_hi(__import.sealed_object.test)
+;; CHECK-NEXT:      clc	a0, %cheriot_compartment_lo_i(.LBB0_1)(a0)
 ;; CHECK-NEXT:   .LBB0_3:                                # %entry
 ;; CHECK-NEXT:                                           # Label of block must be emitted
-;; CHECK-NEXT:  	  auipcc  ct1, %cheriot_compartment_hi(__import_static_sealing_inner_test_static_sealed_object)
-;; CHECK-NEXT:  	  clc	  ct1, %cheriot_compartment_lo_i(.LBB0_3)(ct1)
+;; CHECK-NEXT:  	  auipcc  t1, %cheriot_compartment_hi(__import_static_sealing_inner_test_static_sealed_object)
+;; CHECK-NEXT:  	  clc	  t1, %cheriot_compartment_lo_i(.LBB0_3)(t1)
 ;; CHECK-NEXT:   .LBB0_2:                                # %entry
 ;; CHECK-NEXT:                                           # Label of block must be emitted
-;; CHECK-NEXT:  	  auipcc  ct2, %cheriot_compartment_hi(.compartment_switcher)
-;; CHECK-NEXT:  	  clc	  ct2, %cheriot_compartment_lo_i(.LBB0_2)(ct2)
-;; CHECK-NEXT:  	  cjalr	  ct2
+;; CHECK-NEXT:  	  auipcc  t2, %cheriot_compartment_hi(.compartment_switcher)
+;; CHECK-NEXT:  	  clc	  t2, %cheriot_compartment_lo_i(.LBB0_2)(t2)
+;; CHECK-NEXT:  	  cjalr	  t2
   %call = notail call cheriot_compartmentcallcc noundef i32 @test_static_sealed_object(ptr addrspace(200) @test) #2
   %call2 = notail call cheriot_compartmentcallcc noundef i32 @test_static_sealed_object(ptr addrspace(200) @__default_malloc_capability) #2
   ret i32 %call2
diff --git a/llvm/test/CodeGen/RISCV/cheri/cheriot-sealing-key-attr.ll b/llvm/test/CodeGen/RISCV/cheri/cheriot-sealing-key-attr.ll
index 3710dc4e4e483..7eb28bd99aa5c 100644
--- a/llvm/test/CodeGen/RISCV/cheri/cheriot-sealing-key-attr.ll
+++ b/llvm/test/CodeGen/RISCV/cheri/cheriot-sealing-key-attr.ll
@@ -24,28 +24,28 @@ entry:
   %SealingKey5 = alloca ptr, align 8, addrspace(200)
 ; CHECK: .LBB0_1:                                # %entry
 ; CHECK:                                         # Label of block must be emitted
-; CHECK:         auipcc  ca0, %cheriot_compartment_hi(__import.sealing_type.static_sealing_test.StructSealingKey)
-; CHECK:         clc     ca0, %cheriot_compartment_lo_i(.LBB0_1)(ca0)
+; CHECK:         auipcc  a0, %cheriot_compartment_hi(__import.sealing_type.static_sealing_test.StructSealingKey)
+; CHECK:         clc     a0, %cheriot_compartment_lo_i(.LBB0_1)(a0)
   store ptr addrspace(200) @__import.sealing_type.static_sealing_test.StructSealingKey, ptr addrspace(200) %SealingKey1, align 8
 ; CHECK: .LBB0_2:                                # %entry
 ; CHECK:                                         # Label of block must be emitted
-; CHECK:         auipcc  ca0, %cheriot_compartment_hi(__import.sealing_type.static_sealing_test.EnumSealingKey)
-; CHECK:         clc     ca0, %cheriot_compartment_lo_i(.LBB0_2)(ca0)
+; CHECK:         auipcc  a0, %cheriot_compartment_hi(__import.sealing_type.static_sealing_test.EnumSealingKey)
+; CHECK:         clc     a0, %cheriot_compartment_lo_i(.LBB0_2)(a0)
   store ptr addrspace(200) @__import.sealing_type.static_sealing_test.EnumSealingKey, ptr addrspace(200) %SealingKey2, align 8
 ; CHECK: .LBB0_3:                                # %entry
 ; CHECK:                                         # Label of block must be emitted
-; CHECK:         auipcc  ca0, %cheriot_compartment_hi(__import.sealing_type.static_sealing_test.TypeDefSealingKey)
-; CHECK:         clc     ca0, %cheriot_compartment_lo_i(.LBB0_3)(ca0)
+; CHECK:         auipcc  a0, %cheriot_compartment_hi(__import.sealing_type.static_sealing_test.TypeDefSealingKey)
+; CHECK:         clc     a0, %cheriot_compartment_lo_i(.LBB0_3)(a0)
   store ptr addrspace(200) @__import.sealing_type.static_sealing_test.TypeDefSealingKey, ptr addrspace(200) %SealingKey3, align 8
 ; CHECK: .LBB0_4:                                # %entry
 ; CHECK:                                         # Label of block must be emitted
-; CHECK:         auipcc  ca0, %cheriot_compartment_hi(__import.sealing_type.static_sealing_test.int)
-; CHECK:         clc     ca0, %cheriot_compartment_lo_i(.LBB0_4)(ca0)
+; CHECK:         auipcc  a0, %cheriot_compartment_hi(__import.sealing_type.static_sealing_test.int)
+; CHECK:         clc     a0, %cheriot_compartment_lo_i(.LBB0_4)(a0)
   store ptr addrspace(200) @__import.sealing_type.static_sealing_test.int, ptr addrspace(200) %SealingKey4, align 8
 ; CHECK: .LBB0_5:                                # %entry
 ; CHECK:                                         # Label of block must be emitted
-; CHECK:         auipcc  ca0, %cheriot_compartment_hi(__import.sealing_type.static_sealing_test.int)
-; CHECK:         clc     ca0, %cheriot_compartment_lo_i(.LBB0_5)(ca0)
+; CHECK:         auipcc  a0, %cheriot_compartment_hi(__import.sealing_type.static_sealing_test.int)
+; CHECK:         clc     a0, %cheriot_compartment_lo_i(.LBB0_5)(a0)
   store ptr addrspace(200) @__import.sealing_type.static_sealing_test.int2, ptr addrspace(200) %SealingKey5, align 8
 ; CHECK: 	cret
 ; CHECK: .Lfunc_end0:
diff --git a/llvm/test/CodeGen/RISCV/cheri/cheriot-stack-size-export.ll b/llvm/test/CodeGen/RISCV/cheri/cheriot-stack-size-export.ll
index f07befe57663a..35a36f78ff9b9 100644
--- a/llvm/test/CodeGen/RISCV/cheri/cheriot-stack-size-export.ll
+++ b/llvm/test/CodeGen/RISCV/cheri/cheriot-stack-size-export.ll
@@ -8,7 +8,7 @@ define dso_local cheriot_compartmentcalleecc void @_Z9usesStackv() addrspace(200
 ; CHECK-LABEL: _Z9usesStackv
 ; Make sure that the stack is what we expect.  If this changes, we need to
 ; update the number in the export table below.
-; CHECK: cincoffset      csp, csp, -48
+; CHECK: cincoffset      sp, sp, -48
 entry:
   %x = alloca [8 x i32], align 4, addrspace(200)
   %arraydecay = getelementptr inbounds [8 x i32], [8 x i32] addrspace(200)* %x, i32 0, i32 0
@@ -22,7 +22,7 @@ declare dso_local void @foo(i8 addrspace(200)*) addrspace(200) #1
 ; Function Attrs: noinline nounwind optnone
 ; CHECK-LABEL: _Z11usesNoStackv
 ; Make sure we don't allocate anything on the stack here.
-; CHECK-NOT: csp
+; CHECK-NOT: sp
 define dso_local cheriot_compartmentcalleecc void @_Z11usesNoStackv() addrspace(200) #0 {
 entry:
   ret void
@@ -35,7 +35,7 @@ define dso_local cheriot_compartmentcalleecc void @_Z13usesHugeStackv() addrspac
 ; if this changes to another large value.
 ; CHECK: lui a0, 1048574
 ; CHECK-NEXT: addi a0, a0, 192
-; CHECK-NEXT: cincoffset csp, csp, a0
+; CHECK-NEXT: cincoffset sp, sp, a0
 entry:
   %x = alloca [2048 x i32], align 4, addrspace(200)
   %arraydecay = getelementptr inbounds [2048 x i32], [2048 x i32] addrspace(200)* %x, i32 0, i32 0
diff --git a/llvm/test/CodeGen/RISCV/cheri/cheriot-struct-ret.ll b/llvm/test/CodeGen/RISCV/cheri/cheriot-struct-ret.ll
index e1a17f40a9bd4..e90dfc71a00c9 100644
--- a/llvm/test/CodeGen/RISCV/cheri/cheriot-struct-ret.ll
+++ b/llvm/test/CodeGen/RISCV/cheri/cheriot-struct-ret.ll
@@ -44,9 +44,9 @@ entry:
   %.fca.1.insert = insertvalue [2 x i32] %.fca.0.insert, i32 %call1, 1
 
   ;; Usual callee epilogue.
-  ;; CHECK-NEXT:  	ct.clc	cra, 8(csp)                     # 8-byte Folded Reload
-  ;; CHECK-NEXT:  	ct.clc	cs0, 0(csp)                     # 8-byte Folded Reload
-  ;; CHECK-NEXT:  	ct.cincoffset	csp, csp, 16
+  ;; CHECK-NEXT:  	ct.clc	ra, 8(sp)                     # 8-byte Folded Reload
+  ;; CHECK-NEXT:  	ct.clc	s0, 0(sp)                     # 8-byte Folded Reload
+  ;; CHECK-NEXT:  	ct.cincoffset	sp, sp, 16
   ;; CHECK-NEXT:  	ct.cret
   ret [2 x i32] %.fca.1.insert
 }
@@ -77,10 +77,10 @@ entry:
   %.fca.1.insert = insertvalue [2 x i32] %.fca.0.insert, i32 %sub2, 1
 
   ;; CHECK:  	mv	a0, s1
-  ;; CHECK:  	ct.clc	cra, 24(csp)                    # 8-byte Folded Reload
-  ;; CHECK:  	ct.clc	cs0, 16(csp)                    # 8-byte Folded Reload
-  ;; CHECK:  	ct.clc	cs1, 8(csp)                     # 8-byte Folded Reload
-  ;; CHECK:  	ct.cincoffset	csp, csp, 32
+  ;; CHECK:  	ct.clc	ra, 24(sp)                    # 8-byte Folded Reload
+  ;; CHECK:  	ct.clc	s0, 16(sp)                    # 8-byte Folded Reload
+  ;; CHECK:  	ct.clc	s1, 8(sp)                     # 8-byte Folded Reload
+  ;; CHECK:  	ct.cincoffset	sp, sp, 32
   ;; CHECK:  	ct.cret
   ret [2 x i32] %.fca.1.insert
 }
@@ -116,26 +116,26 @@ entry:
   ;; CHECK:	ct.ccall	_Z8GetValuev
   %call = tail call cheriot_compartmentcalleecc i32 @_Z8GetValuev()
 
-  ;; CHECK:     auicgp	        cs0, %cheriot_compartment_hi(dummies)
-  ;; CHECK:     cincoffset	cs0, cs0, %cheriot_compartment_lo_i(.LBB4_1)
-  ;; CHECK:     ct.csetbounds   cs0, cs0, %cheriot_compartment_size(dummies)
-  ;; CHECK:     ct.cincoffset   ca0, cs0, a0
+  ;; CHECK:     auicgp	        s0, %cheriot_compartment_hi(dummies)
+  ;; CHECK:     cincoffset	s0, s0, %cheriot_compartment_lo_i(.LBB4_1)
+  ;; CHECK:     ct.csetbounds   s0, s0, %cheriot_compartment_size(dummies)
+  ;; CHECK:     ct.cincoffset   a0, s0, a0
   %rem = urem i32 %call, 5
   %add.ptr = getelementptr inbounds nuw i32, ptr addrspace(200) @dummies, i32 %rem
 
   ;; CHECK:	ct.ccall	_Z8GetValuev
-  ;; CHECK:	ct.cincoffset	ca1, cs0, a0
+  ;; CHECK:	ct.cincoffset	a1, s0, a0
   %call1 = tail call cheriot_compartmentcalleecc i32 @_Z8GetValuev()
   %rem2 = urem i32 %call1, 5
   %add.ptr3 = getelementptr inbounds nuw i32, ptr addrspace(200) @dummies, i32 %rem2
   %.fca.0.insert = insertvalue %struct.TwoPointers poison, ptr addrspace(200) %add.ptr, 0
   %.fca.1.insert = insertvalue %struct.TwoPointers %.fca.0.insert, ptr addrspace(200) %add.ptr3, 1
 
-  ;; CHECK:     ct.clc	ca0, 0(csp)                     # 8-byte Folded Reload
-  ;; CHECK:	ct.clc	cra, 24(csp)                    # 8-byte Folded Reload
-  ;; CHECK:	ct.clc	cs0, 16(csp)                    # 8-byte Folded Reload
-  ;; CHECK:	ct.clc	cs1, 8(csp)                     # 8-byte Folded Reload
-  ;; CHECK:	ct.cincoffset	csp, csp, 32
+  ;; CHECK:     ct.clc	a0, 0(sp)                     # 8-byte Folded Reload
+  ;; CHECK:	ct.clc	ra, 24(sp)                    # 8-byte Folded Reload
+  ;; CHECK:	ct.clc	s0, 16(sp)                    # 8-byte Folded Reload
+  ;; CHECK:	ct.clc	s1, 8(sp)                     # 8-byte Folded Reload
+  ;; CHECK:	ct.cincoffset	sp, sp, 32
   ;; CHECK:	ct.cret
   ret %struct.TwoPointers %.fca.1.insert
 }
@@ -143,13 +143,13 @@ entry:
 ; Function Attrs: mustprogress nofree noinline norecurse nosync nounwind willreturn memory(readwrite, inaccessiblemem: none)
 define dso_local cheriot_compartmentcalleecc %struct.TwoPointers @_Z7ChgPtrs11TwoPointers(ptr addrspace(200) %x.coerce0, ptr addrspace(200) %x.coerce1) local_unnamed_addr addrspace(200) #1 {
 ;; CHECK: _Z7ChgPtrs11TwoPointers:                # @_Z7ChgPtrs11TwoPointers
-;; CHECK: ct.csc	ca1, 16(csp)                    # 8-byte Folded Spill
+;; CHECK: ct.csc	a1, 16(sp)                    # 8-byte Folded Spill
 entry:
 
-  ;; CHECK: auicgp	ca1, %cheriot_compartment_hi(force_use)
-  ;; CHECK: cincoffset	ca1, ca1, %cheriot_compartment_lo_i(.LBB5_1)
-  ;; CHECK: ct.csc	ca1, 8(csp)                     # 8-byte Folded Spill
-  ;; CHECK: ct.csc	ca0, 0(ca1)
+  ;; CHECK: auicgp	a1, %cheriot_compartment_hi(force_use)
+  ;; CHECK: cincoffset	a1, a1, %cheriot_compartment_lo_i(.LBB5_1)
+  ;; CHECK: ct.csc	a1, 8(sp)                     # 8-byte Folded Spill
+  ;; CHECK: ct.csc	a0, 0(a1)
   store ptr addrspace(200) %x.coerce0, ptr addrspace(200) @force_use, align 8, !tbaa !11
 
   ;; CHECK: ct.ccall	_Z8GetValuev
@@ -157,29 +157,29 @@ entry:
   %rem = urem i32 %call, 5
 
   ;; %call above was saved/reloaded in a0
-  ;; CHECK: auicgp	  cs0, %cheriot_compartment_hi(dummies)
-  ;; CHECK: cincoffset	  cs0, cs0, %cheriot_compartment_lo_i(.LBB5_2)
-  ;; CHECK: ct.csetbounds cs0, cs0, %cheriot_compartment_size(dummies)
+  ;; CHECK: auicgp	  s0, %cheriot_compartment_hi(dummies)
+  ;; CHECK: cincoffset	  s0, s0, %cheriot_compartment_lo_i(.LBB5_2)
+  ;; CHECK: ct.csetbounds s0, s0, %cheriot_compartment_size(dummies)
   ;; CHECK: sub	          a0, a0, a1
   ;; CHECK: slli	  a0, a0, 2
-  ;; CHECK: ct.cincoffset ca0, cs0, a0
-  ;; CHECK: ct.csc	ca0, 0(csp)                     # 8-byte Folded Spill
+  ;; CHECK: ct.cincoffset a0, s0, a0
+  ;; CHECK: ct.csc	a0, 0(sp)                     # 8-byte Folded Spill
   %add.ptr = getelementptr inbounds nuw i32, ptr addrspace(200) @dummies, i32 %rem
 
-  ;; CHECK: ct.clc  ca0, 16(csp)                    # 8-byte Folded Reload
-  ;; CHECK: ct.clc  ca1, 8(csp)                     # 8-byte Folded Reload
-  ;; CHECK: ct.csc  ca0, 0(ca1)
+  ;; CHECK: ct.clc  a0, 16(sp)                    # 8-byte Folded Reload
+  ;; CHECK: ct.clc  a1, 8(sp)                     # 8-byte Folded Reload
+  ;; CHECK: ct.csc  a0, 0(a1)
   store ptr addrspace(200) %x.coerce1, ptr addrspace(200) @force_use, align 8, !tbaa !11
 
   ;; CHECK: ct.ccall	_Z8GetValuev
   %call2 = tail call cheriot_compartmentcalleecc i32 @_Z8GetValuev()
   %rem3 = urem i32 %call2, 5
 
-  ;; CHECK: ct.cincoffset	ca1, cs0, a0
+  ;; CHECK: ct.cincoffset	a1, s0, a0
   %add.ptr4 = getelementptr inbounds nuw i32, ptr addrspace(200) @dummies, i32 %rem3
 
-  ;; ca1 already contains the final value; reload ca0
-  ;; CHECK: ct.clc	ca0, 0(csp)                     # 8-byte Folded Reload
+  ;; a1 already contains the final value; reload a0
+  ;; CHECK: ct.clc	a0, 0(sp)                     # 8-byte Folded Reload
   %.fca.0.insert = insertvalue %struct.TwoPointers poison, ptr addrspace(200) %add.ptr, 0
   %.fca.1.insert = insertvalue %struct.TwoPointers %.fca.0.insert, ptr addrspace(200) %add.ptr4, 1
 
@@ -214,20 +214,20 @@ entry:
   %call = tail call cheriot_compartmentcalleecc i32 @_Z8GetValuev()
   %rem = urem i32 %call, 5
 
-  ;; CHECK:  	auicgp	ca1, %cheriot_compartment_hi(dummies)
-  ;; CHECK:  	cincoffset	ca1, ca1, %cheriot_compartment_lo_i(.LBB7_1)
-  ;; CHECK:  	ct.csetbounds	ca1, ca1, %cheriot_compartment_size(dummies)
-  ;; CHECK:  	ct.cincoffset	cs0, ca1, a0
+  ;; CHECK:  	auicgp	a1, %cheriot_compartment_hi(dummies)
+  ;; CHECK:  	cincoffset	a1, a1, %cheriot_compartment_lo_i(.LBB7_1)
+  ;; CHECK:  	ct.csetbounds	a1, a1, %cheriot_compartment_size(dummies)
+  ;; CHECK:  	ct.cincoffset	s0, a1, a0
   %add.ptr = getelementptr inbounds nuw i32, ptr addrspace(200) @dummies, i32 %rem
 
   ;; CHECK:  	ct.ccall	_Z8GetValuev
   %call1 = tail call cheriot_compartmentcalleecc i32 @_Z8GetValuev()
 
   ;; CHECK:  	mv	  a1, a0
-  ;; CHECK:  	ct.cmove  ca0, cs0
-  ;; CHECK:  	ct.clc	  cra, 8(csp)                     # 8-byte Folded Reload
-  ;; CHECK:  	ct.clc	  cs0, 0(csp)                     # 8-byte Folded Reload
-  ;; CHECK:  	ct.cincoffset	csp, csp, 16
+  ;; CHECK:  	ct.cmove  a0, s0
+  ;; CHECK:  	ct.clc	  ra, 8(sp)                     # 8-byte Folded Reload
+  ;; CHECK:  	ct.clc	  s0, 0(sp)                     # 8-byte Folded Reload
+  ;; CHECK:  	ct.cincoffset	sp, sp, 16
   %.fca.0.insert = insertvalue %struct.PointerAndInt poison, ptr addrspace(200) %add.ptr, 0
   %.fca.1.insert = insertvalue %struct.PointerAndInt %.fca.0.insert, i32 %call1, 1
 
@@ -243,19 +243,19 @@ entry:
 
   ;; CHECK:  .LBB8_1:                                # %entry
   ;; CHECK:                                          # Label of block must be emitted
-  ;; CHECK:  	auicgp	ca1, %cheriot_compartment_hi(force_use)
-  ;; CHECK:  	cincoffset	ca1, ca1, %cheriot_compartment_lo_i(.LBB8_1)
-  ;; CHECK:       ct.csc	ca0, 0(ca1)
+  ;; CHECK:  	auicgp	a1, %cheriot_compartment_hi(force_use)
+  ;; CHECK:  	cincoffset	a1, a1, %cheriot_compartment_lo_i(.LBB8_1)
+  ;; CHECK:       ct.csc	a0, 0(a1)
   store ptr addrspace(200) %x.coerce0, ptr addrspace(200) @force_use, align 8, !tbaa !11
 
   ;; CHECK:  	ct.ccall	_Z8GetValuev
   %call = tail call cheriot_compartmentcalleecc i32 @_Z8GetValuev()
   %rem = urem i32 %call, 5
 
-  ;; CHECK:     auicgp	ca1, %cheriot_compartment_hi(dummies)
-  ;; CHECK:     cincoffset	ca1, ca1, %cheriot_compartment_lo_i(.LBB8_2)
-  ;; CHECK:  	ct.csetbounds	ca1, ca1, %cheriot_compartment_size(dummies)
-  ;; CHECK:  	ct.cincoffset	cs1, ca1, a0
+  ;; CHECK:     auicgp	a1, %cheriot_compartment_hi(dummies)
+  ;; CHECK:     cincoffset	a1, a1, %cheriot_compartment_lo_i(.LBB8_2)
+  ;; CHECK:  	ct.csetbounds	a1, a1, %cheriot_compartment_size(dummies)
+  ;; CHECK:  	ct.cincoffset	s1, a1, a0
   %add.ptr = getelementptr inbounds nuw i32, ptr addrspace(200) @dummies, i32 %rem
 
   ;; CHECK:	ct.ccall	_Z8GetValuev
@@ -264,11 +264,11 @@ entry:
   ;; CHECK:       sub	a1, s0, a0
   %sub = sub i32 %x.coerce1, %call2
 
-  ;; CHECK:  	ct.cmove	ca0, cs1
-  ;; CHECK:  	ct.clc	cra, 24(csp)                    # 8-byte Folded Reload
-  ;; CHECK:  	ct.clc	cs0, 16(csp)                    # 8-byte Folded Reload
-  ;; CHECK:  	ct.clc	cs1, 8(csp)                     # 8-byte Folded Reload
-  ;; CHECK:  	ct.cincoffset	csp, csp, 32
+  ;; CHECK:  	ct.cmove	a0, s1
+  ;; CHECK:  	ct.clc	ra, 24(sp)                    # 8-byte Folded Reload
+  ;; CHECK:  	ct.clc	s0, 16(sp)                    # 8-byte Folded Reload
+  ;; CHECK:  	ct.clc	s1, 8(sp)                     # 8-byte Folded Reload
+  ;; CHECK:  	ct.cincoffset	sp, sp, 32
   %.fca.0.insert = insertvalue %struct.PointerAndInt poison, ptr addrspace(200) %add.ptr, 0
   %.fca.1.insert = insertvalue %struct.PointerAndInt %.fca.0.insert, i32 %sub, 1
 
@@ -305,21 +305,21 @@ entry:
   %call = tail call cheriot_compartmentcalleecc i32 @_Z8GetValuev()
   %rem = urem i32 %call, 5
 
-  ;; CHECK: 	auicgp	cs0, %cheriot_compartment_hi(dummies)
-  ;; CHECK:     cincoffset	cs0, cs0, %cheriot_compartment_lo_i(.LBB10_1)
-  ;; CHECK: 	ct.csetbounds	cs0, cs0, %cheriot_compartment_size(dummies)
-  ;; CHECK: 	ct.cincoffset	ca0, cs0, a0
-  ;; CHECK: 	ct.csc	ca0, 0(csp)                     # 8-byte Folded Spill
+  ;; CHECK: 	auicgp	s0, %cheriot_compartment_hi(dummies)
+  ;; CHECK:     cincoffset	s0, s0, %cheriot_compartment_lo_i(.LBB10_1)
+  ;; CHECK: 	ct.csetbounds	s0, s0, %cheriot_compartment_size(dummies)
+  ;; CHECK: 	ct.cincoffset	a0, s0, a0
+  ;; CHECK: 	ct.csc	a0, 0(sp)                     # 8-byte Folded Spill
   %add.ptr = getelementptr inbounds nuw i32, ptr addrspace(200) @dummies, i32 %rem
 
   ;; CHECK: 	ct.ccall	_Z8GetValuev
   %call1 = tail call cheriot_compartmentcalleecc i32 @_Z8GetValuev()
   %rem2 = urem i32 %call1, 5
 
-  ;; CHECK: 	ct.cincoffset	ca1, cs0, a0
+  ;; CHECK: 	ct.cincoffset	a1, s0, a0
   %add.ptr3 = getelementptr inbounds nuw i32, ptr addrspace(200) @dummies, i32 %rem2
 
-  ;; CHECK: 	ct.clc	ca0, 0(csp)                     # 8-byte Folded Reload
+  ;; CHECK: 	ct.clc	a0, 0(sp)                     # 8-byte Folded Reload
   %.fca.0.insert = insertvalue %struct.ParentPtr poison, ptr addrspace(200) %add.ptr, 0
   %.fca.1.0.insert = insertvalue %struct.ParentPtr %.fca.0.insert, ptr addrspace(200) %add.ptr3, 1, 0
 
@@ -331,13 +331,13 @@ entry:
 define dso_local cheriot_compartmentcalleecc %struct.ParentPtr @_Z12ChgParentPtr9ParentPtr(ptr addrspace(200) %x.coerce0, %struct.InnerPtr %x.coerce1) local_unnamed_addr addrspace(200) #1 {
 
 ;; CHECK: _Z12ChgParentPtr9ParentPtr:             # @_Z12ChgParentPtr9ParentPtr
-;; CHECK: 	ct.csc	ca1, 16(csp)                    # 8-byte Folded Spill
+;; CHECK: 	ct.csc	a1, 16(sp)                    # 8-byte Folded Spill
 entry:
 
-  ;; CHECK: 	auicgp	ca1, %cheriot_compartment_hi(force_use)
-  ;; CHECK: 	cincoffset	ca1, ca1, %cheriot_compartment_lo_i(.LBB11_1)
-  ;; CHECK: 	ct.csc	ca1, 8(csp)                     # 8-byte Folded Spill
-  ;; CHECK: 	ct.csc	ca0, 0(ca1)
+  ;; CHECK: 	auicgp	a1, %cheriot_compartment_hi(force_use)
+  ;; CHECK: 	cincoffset	a1, a1, %cheriot_compartment_lo_i(.LBB11_1)
+  ;; CHECK: 	ct.csc	a1, 8(sp)                     # 8-byte Folded Spill
+  ;; CHECK: 	ct.csc	a0, 0(a1)
   %x.coerce1.fca.0.extract = extractvalue %struct.InnerPtr %x.coerce1, 0
   store ptr addrspace(200) %x.coerce0, ptr addrspace(200) @force_use, align 8, !tbaa !11
 
@@ -345,26 +345,26 @@ entry:
   %call = tail call cheriot_compartmentcalleecc i32 @_Z8GetValuev()
   %rem = urem i32 %call, 5
 
-  ;; CHECK: 	auicgp	cs0, %cheriot_compartment_hi(dummies)
-  ;; CHECK: 	cincoffset	cs0, cs0, %cheriot_compartment_lo_i(.LBB11_2)
-  ;; CHECK: 	ct.csetbounds	cs0, cs0, %cheriot_compartment_size(dummies)
-  ;; CHECK: 	ct.cincoffset	ca0, cs0, a0
-  ;; CHECK: 	ct.csc	ca0, 0(csp)                     # 8-byte Folded Spill
+  ;; CHECK: 	auicgp	s0, %cheriot_compartment_hi(dummies)
+  ;; CHECK: 	cincoffset	s0, s0, %cheriot_compartment_lo_i(.LBB11_2)
+  ;; CHECK: 	ct.csetbounds	s0, s0, %cheriot_compartment_size(dummies)
+  ;; CHECK: 	ct.cincoffset	a0, s0, a0
+  ;; CHECK: 	ct.csc	a0, 0(sp)                     # 8-byte Folded Spill
   %add.ptr = getelementptr inbounds nuw i32, ptr addrspace(200) @dummies, i32 %rem
 
-  ;; CHECK: 	ct.clc	ca0, 16(csp)                    # 8-byte Folded Reload
-  ;; CHECK: 	ct.clc	ca1, 8(csp)                     # 8-byte Folded Reload
-  ;; CHECK: 	ct.csc	ca0, 0(ca1)
+  ;; CHECK: 	ct.clc	a0, 16(sp)                    # 8-byte Folded Reload
+  ;; CHECK: 	ct.clc	a1, 8(sp)                     # 8-byte Folded Reload
+  ;; CHECK: 	ct.csc	a0, 0(a1)
   store ptr addrspace(200) %x.coerce1.fca.0.extract, ptr addrspace(200) @force_use, align 8, !tbaa !11
 
   ;; CHECK: 	ct.ccall	_Z8GetValuev
   %call3 = tail call cheriot_compartmentcalleecc i32 @_Z8GetValuev()
   %rem4 = urem i32 %call3, 5
 
-  ;; CHECK: 	ct.cincoffset	ca1, cs0, a0
+  ;; CHECK: 	ct.cincoffset	a1, s0, a0
   %add.ptr5 = getelementptr inbounds nuw i32, ptr addrspace(200) @dummies, i32 %rem4
 
-  ;; CHECK: 	ct.clc	ca0, 0(csp)                     # 8-byte Folded Reload
+  ;; CHECK: 	ct.clc	a0, 0(sp)                     # 8-byte Folded Reload
   %.fca.0.insert = insertvalue %struct.ParentPtr poison, ptr addrspace(200) %add.ptr, 0
   %.fca.1.0.insert = insertvalue %struct.ParentPtr %.fca.0.insert, ptr addrspace(200) %add.ptr5, 1, 0
 
@@ -396,14 +396,14 @@ entry:
 define dso_local cheriot_compartmentcalleecc %struct.TwoPointers @_Z8ChgPtrs2i11TwoPointers(i32 noundef %new_int, ptr addrspace(200) %x.coerce0, ptr addrspace(200) %x.coerce1) local_unnamed_addr addrspace(200) #1 {
 
 ;; CHECK:  _Z8ChgPtrs2i11TwoPointers:              # @_Z8ChgPtrs2i11TwoPointers
-;; CHECK:       ct.csc	ca2, 32(csp)                    # 8-byte Folded Spill
-;; CHECK:  	ct.csw	a0, 28(csp)                     # 4-byte Folded Spill
+;; CHECK:       ct.csc	a2, 32(sp)                    # 8-byte Folded Spill
+;; CHECK:  	ct.csw	a0, 28(sp)                     # 4-byte Folded Spill
 entry:
 
-  ;; CHECK:  	auicgp	ca0, %cheriot_compartment_hi(force_use)
-  ;; CHECK:  	cincoffset	ca0, ca0, %cheriot_compartment_lo_i(.LBB13_1)
-  ;; CHECK:  	ct.csc	ca0, 16(csp)                    # 8-byte Folded Spill
-  ;; CHECK:  	ct.csc	ca1, 0(ca0)
+  ;; CHECK:  	auicgp	a0, %cheriot_compartment_hi(force_use)
+  ;; CHECK:  	cincoffset	a0, a0, %cheriot_compartment_lo_i(.LBB13_1)
+  ;; CHECK:  	ct.csc	a0, 16(sp)                    # 8-byte Folded Spill
+  ;; CHECK:  	ct.csc	a1, 0(a0)
   store ptr addrspace(200) %x.coerce0, ptr addrspace(200) @force_use, align 8, !tbaa !11
 
   ;; CHECK:  	ct.ccall	_Z8GetValuev
@@ -411,28 +411,28 @@ entry:
   %add = add i32 %call, %new_int
   %rem = urem i32 %add, 5
 
-  ;; CHECK:  	auicgp	cs0, %cheriot_compartment_hi(dummies)
-  ;; CHECK:  	cincoffset	cs0, cs0, %cheriot_compartment_lo_i(.LBB13_2)
-  ;; CHECK:  	ct.csetbounds	cs0, cs0, %cheriot_compartment_size(dummies)
-  ;; CHECK:  	ct.cincoffset	ca0, cs0, a0
-  ;; CHECK:  	ct.csc	ca0, 8(csp)                     # 8-byte Folded Spill
+  ;; CHECK:  	auicgp	s0, %cheriot_compartment_hi(dummies)
+  ;; CHECK:  	cincoffset	s0, s0, %cheriot_compartment_lo_i(.LBB13_2)
+  ;; CHECK:  	ct.csetbounds	s0, s0, %cheriot_compartment_size(dummies)
+  ;; CHECK:  	ct.cincoffset	a0, s0, a0
+  ;; CHECK:  	ct.csc	a0, 8(sp)                     # 8-byte Folded Spill
   %add.ptr = getelementptr inbounds nuw i32, ptr addrspace(200) @dummies, i32 %rem
 
-  ;; CHECK:  	ct.clc	ca0, 32(csp)                    # 8-byte Folded Reload
-  ;; CHECK:  	ct.clc	ca1, 16(csp)                    # 8-byte Folded Reload
-  ;; CHECK:  	ct.csc	ca0, 0(ca1)
+  ;; CHECK:  	ct.clc	a0, 32(sp)                    # 8-byte Folded Reload
+  ;; CHECK:  	ct.clc	a1, 16(sp)                    # 8-byte Folded Reload
+  ;; CHECK:  	ct.csc	a0, 0(a1)
   store ptr addrspace(200) %x.coerce1, ptr addrspace(200) @force_use, align 8, !tbaa !11
 
   ;; CHECK:  	ct.ccall	_Z8GetValuev
-  ;; CHECK:  	ct.clw	a1, 28(csp)                     # 4-byte Folded Reload
+  ;; CHECK:  	ct.clw	a1, 28(sp)                     # 4-byte Folded Reload
   %call2 = tail call cheriot_compartmentcalleecc i32 @_Z8GetValuev()
   %add3 = add i32 %call2, %new_int
   %rem4 = urem i32 %add3, 5
 
-  ;; CHECK:  	ct.cincoffset	ca1, cs0, a0
+  ;; CHECK:  	ct.cincoffset	a1, s0, a0
   %add.ptr5 = getelementptr inbounds nuw i32, ptr addrspace(200) @dummies, i32 %rem4
 
-  ;; CHECK:  	ct.clc	ca0, 8(csp)                     # 8-byte Folded Reload
+  ;; CHECK:  	ct.clc	a0, 8(sp)                     # 8-byte Folded Reload
   %.fca.0.insert = insertvalue %struct.TwoPointers poison, ptr addrspace(200) %add.ptr, 0
   %.fca.1.insert = insertvalue %struct.TwoPointers %.fca.0.insert, ptr addrspace(200) %add.ptr5, 1
 
@@ -444,15 +444,15 @@ entry:
 define dso_local cheriot_compartmentcalleecc %struct.ParentPtr @_Z13ChgParentPtr2i9ParentPtr(i32 noundef %new_int, ptr addrspace(200) %x.coerce0, %struct.InnerPtr %x.coerce1) local_unnamed_addr addrspace(200) #1 {
 
 ;; CHECK:  _Z13ChgParentPtr2i9ParentPtr:           # @_Z13ChgParentPtr2i9ParentPtr
-;; CHECK:  	ct.csc	ca2, 32(csp)                    # 8-byte Folded Spill
+;; CHECK:  	ct.csc	a2, 32(sp)                    # 8-byte Folded Spill
 ;; CHECK:  	mv	s0, a0
-;; CHECK:  	ct.csw	a0, 28(csp)                     # 4-byte Folded Spill
+;; CHECK:  	ct.csw	a0, 28(sp)                     # 4-byte Folded Spill
 entry:
 
-  ;; CHECK:  	auicgp	ca0, %cheriot_compartment_hi(force_use)
-  ;; CHECK:  	cincoffset	ca0, ca0, %cheriot_compartment_lo_i(.LBB14_1)
-  ;; CHECK:  	ct.csc	ca0, 16(csp)                    # 8-byte Folded Spill
-  ;; CHECK:  	ct.csc	ca1, 0(ca0)
+  ;; CHECK:  	auicgp	a0, %cheriot_compartment_hi(force_use)
+  ;; CHECK:  	cincoffset	a0, a0, %cheriot_compartment_lo_i(.LBB14_1)
+  ;; CHECK:  	ct.csc	a0, 16(sp)                    # 8-byte Folded Spill
+  ;; CHECK:  	ct.csc	a1, 0(a0)
   %x.coerce1.fca.0.extract = extractvalue %struct.InnerPtr %x.coerce1, 0
   store ptr addrspace(200) %x.coerce0, ptr addrspace(200) @force_use, align 8, !tbaa !11
 
@@ -461,28 +461,28 @@ entry:
   %add = add i32 %call, %new_int
   %rem = urem i32 %add, 5
 
-  ;; CHECK:  	auicgp	cs0, %cheriot_compartment_hi(dummies)
-  ;; CHECK:  	cincoffset	cs0, cs0, %cheriot_compartment_lo_i(.LBB14_2)
-  ;; CHECK:  	ct.csetbounds	cs0, cs0, %cheriot_compartment_size(dummies)
-  ;; CHECK:  	ct.cincoffset	ca0, cs0, a0
-  ;; CHECK:  	ct.csc	ca0, 8(csp)                     # 8-byte Folded Spill
+  ;; CHECK:  	auicgp	s0, %cheriot_compartment_hi(dummies)
+  ;; CHECK:  	cincoffset	s0, s0, %cheriot_compartment_lo_i(.LBB14_2)
+  ;; CHECK:  	ct.csetbounds	s0, s0, %cheriot_compartment_size(dummies)
+  ;; CHECK:  	ct.cincoffset	a0, s0, a0
+  ;; CHECK:  	ct.csc	a0, 8(sp)                     # 8-byte Folded Spill
   %add.ptr = getelementptr inbounds nuw i32, ptr addrspace(200) @dummies, i32 %rem
 
-  ;; CHECK:  	ct.clc	ca0, 32(csp)                    # 8-byte Folded Reload
-  ;; CHECK:  	ct.clc	ca1, 16(csp)                    # 8-byte Folded Reload
-  ;; CHECK:  	ct.csc	ca0, 0(ca1)
+  ;; CHECK:  	ct.clc	a0, 32(sp)                    # 8-byte Folded Reload
+  ;; CHECK:  	ct.clc	a1, 16(sp)                    # 8-byte Folded Reload
+  ;; CHECK:  	ct.csc	a0, 0(a1)
   store ptr addrspace(200) %x.coerce1.fca.0.extract, ptr addrspace(200) @force_use, align 8, !tbaa !11
 
   ;; CHECK:  	ct.ccall	_Z8GetValuev
-  ;; CHECK:  	ct.clw	a1, 28(csp)                     # 4-byte Folded Reload
+  ;; CHECK:  	ct.clw	a1, 28(sp)                     # 4-byte Folded Reload
   %call3 = tail call cheriot_compartmentcalleecc i32 @_Z8GetValuev()
   %add4 = add i32 %call3, %new_int
   %rem5 = urem i32 %add4, 5
 
-  ;; CHECK:  	ct.cincoffset	ca1, cs0, a0
+  ;; CHECK:  	ct.cincoffset	a1, s0, a0
   %add.ptr6 = getelementptr inbounds nuw i32, ptr addrspace(200) @dummies, i32 %rem5
 
-  ;; CHECK:  	ct.clc	ca0, 8(csp)                     # 8-byte Folded Reload
+  ;; CHECK:  	ct.clc	a0, 8(sp)                     # 8-byte Folded Reload
   %.fca.0.insert = insertvalue %struct.ParentPtr poison, ptr addrspace(200) %add.ptr, 0
   %.fca.1.0.insert = insertvalue %struct.ParentPtr %.fca.0.insert, ptr addrspace(200) %add.ptr6, 1, 0
 
@@ -514,16 +514,16 @@ entry:
   br i1 %cmp10, label %for.body, label %for.cond.cleanup
 
 for.cond.for.cond.cleanup_crit_edge:              ; preds = %for.body
-  ;; CHECK:  auicgp	ca2, %cheriot_compartment_hi(dummies)
-  ;; CHECK:  cincoffset	ca2, ca2, %cheriot_compartment_lo_i(.LBB15_5)
-  ;; CHECK:  ct.csetbounds	ca2, ca2, %cheriot_compartment_size(dummies)
+  ;; CHECK:  auicgp	a2, %cheriot_compartment_hi(dummies)
+  ;; CHECK:  cincoffset	a2, a2, %cheriot_compartment_lo_i(.LBB15_5)
+  ;; CHECK:  ct.csetbounds	a2, a2, %cheriot_compartment_size(dummies)
 
-  ;; CHECK:  ct.cincoffset	ca3, ca2, s1
+  ;; CHECK:  ct.cincoffset	a3, a2, s1
   %add.le = add i32 %call1, %0
   %rem.le = urem i32 %add.le, 5
   %add.ptr.le = getelementptr inbounds nuw i32, ptr addrspace(200) @dummies, i32 %rem.le
 
-  ;; CHECK:  ct.cincoffset	ca1, ca2, a0
+  ;; CHECK:  ct.cincoffset	a1, a2, a0
   %add4.le = add i32 %call3, %0
   %rem5.le = urem i32 %add4.le, 5
   %add.ptr6.le = getelementptr inbounds nuw i32, ptr addrspace(200) @dummies, i32 %rem5.le
@@ -549,7 +549,7 @@ for.cond.cleanup:                                 ; preds = %for.cond.for.cond.c
   call void @llvm.lifetime.end.p200(i64 4, ptr addrspace(200) nonnull %_)
   call void @llvm.lifetime.end.p200(i64 8, ptr addrspace(200) nonnull %args) #8
 
-  ;; CHECK:  	ct.cmove	ca0, ca3
+  ;; CHECK:  	ct.cmove	a0, a3
   %.fca.0.insert = insertvalue %struct.TwoPointers poison, ptr addrspace(200) %x.sroa.0.0.lcssa, 0
   %.fca.1.insert = insertvalue %struct.TwoPointers %.fca.0.insert, ptr addrspace(200) %x.sroa.4.0.lcssa, 1
 
@@ -583,11 +583,11 @@ for.cond.for.cond.cleanup_crit_edge:              ; preds = %for.body
   %add5.le = add i32 %call4, %0
   %rem6.le = urem i32 %add5.le, 5
   %add.ptr7.le = getelementptr inbounds nuw i32, ptr addrspace(200) @dummies, i32 %rem6.le
-  ;; CHECK:  	auicgp	ca2, %cheriot_compartment_hi(dummies)
-  ;; CHECK:  	cincoffset	ca2, ca2, %cheriot_compartment_lo_i(.LBB16_6)
-  ;; CHECK:  	ct.csetbounds	ca2, ca2, %cheriot_compartment_size(dummies)
-  ;; CHECK:  	ct.cincoffset	ca0, ca2, s1
-  ;; CHECK:  	ct.cincoffset	ca1, ca2, a1
+  ;; CHECK:  	auicgp	a2, %cheriot_compartment_hi(dummies)
+  ;; CHECK:  	cincoffset	a2, a2, %cheriot_compartment_lo_i(.LBB16_6)
+  ;; CHECK:  	ct.csetbounds	a2, a2, %cheriot_compartment_size(dummies)
+  ;; CHECK:  	ct.cincoffset	a0, a2, s1
+  ;; CHECK:  	ct.cincoffset	a1, a2, a1
   ;; CHECK:  	j	.LBB16_4
   br label %for.cond.cleanup
 
@@ -613,10 +613,10 @@ for.cond.cleanup:                                 ; preds = %for.cond.for.cond.c
   %.fca.1.0.insert = insertvalue %struct.ParentPtr %.fca.0.insert, ptr addrspace(200) %x.sroa.4.0.lcssa, 1, 0
 
   ;; CHECK: .LBB16_4:                               # %for.cond.cleanup
-  ;; CHECK: 	ct.clc	cra, 56(csp)                    # 8-byte Folded Reload
-  ;; CHECK: 	ct.clc	cs0, 48(csp)                    # 8-byte Folded Reload
-  ;; CHECK: 	ct.clc	cs1, 40(csp)                    # 8-byte Folded Reload
-  ;; CHECK: 	ct.cincoffset	csp, csp, 64
+  ;; CHECK: 	ct.clc	ra, 56(sp)                    # 8-byte Folded Reload
+  ;; CHECK: 	ct.clc	s0, 48(sp)                    # 8-byte Folded Reload
+  ;; CHECK: 	ct.clc	s1, 40(sp)                    # 8-byte Folded Reload
+  ;; CHECK: 	ct.cincoffset	sp, sp, 64
   ;; CHECK: 	ct.cret
   ret %struct.ParentPtr %.fca.1.0.insert
 
@@ -627,13 +627,13 @@ define dso_local cheriot_compartmentcalleecc %struct.TwoPointers @_Z8ChgPtrs4iii
 ;; CHECK: _Z8ChgPtrs4iiiii11TwoPointers:          # @_Z8ChgPtrs4iiiii11TwoPointers
 ;; CHECK:     mv	s1, a1
 ;; CHECK:     mv	s0, a0
-;; CHECK:     ct.clc	ca0, 0(ct0)
-;; CHECK:     ct.csc	ca0, 32(csp)                    # 8-byte Folded Spill
+;; CHECK:     ct.clc	a0, 0(t0)
+;; CHECK:     ct.csc	a0, 32(sp)                    # 8-byte Folded Spill
 entry:
-  ;; CHECK:  auicgp	ca0, %cheriot_compartment_hi(force_use)
-  ;; CHECK:  	cincoffset	ca0, ca0, %cheriot_compartment_lo_i(.LBB17_2)
-  ;; CHECK:  	ct.csc	ca0, 24(csp)                    # 8-byte Folded Spill
-  ;; CHECK:  	ct.csc	ca5, 0(ca0)
+  ;; CHECK:  auicgp	a0, %cheriot_compartment_hi(force_use)
+  ;; CHECK:  	cincoffset	a0, a0, %cheriot_compartment_lo_i(.LBB17_2)
+  ;; CHECK:  	ct.csc	a0, 24(sp)                    # 8-byte Folded Spill
+  ;; CHECK:  	ct.csc	a5, 0(a0)
   store ptr addrspace(200) %x.coerce0, ptr addrspace(200) @force_use, align 8, !tbaa !11
 
   ;; CHECK: ct.ccall	_Z8GetValuev
@@ -646,15 +646,15 @@ entry:
   %add4 = add i32 %add3, %call
   %rem = urem i32 %add4, 5
 
-  ;; CHECK: auicgp	ca3, %cheriot_compartment_hi(dummies)
-  ;; CHECK: cincoffset	ca3, ca3, %cheriot_compartment_lo_i(.LBB17_3)
-  ;; CHECK: ct.csc	ca3, 8(csp)                     # 8-byte Folded Spill
-  ;; CHECK: ct.cincoffset	ca0, ca3, a0
-  ;; CHECK: ct.csc	ca0, 16(csp)                    # 8-byte Folded Spill
+  ;; CHECK: auicgp	a3, %cheriot_compartment_hi(dummies)
+  ;; CHECK: cincoffset	a3, a3, %cheriot_compartment_lo_i(.LBB17_3)
+  ;; CHECK: ct.csc	a3, 8(sp)                     # 8-byte Folded Spill
+  ;; CHECK: ct.cincoffset	a0, a3, a0
+  ;; CHECK: ct.csc	a0, 16(sp)                    # 8-byte Folded Spill
   %add.ptr = getelementptr inbounds nuw i32, ptr addrspace(200) @dummies, i32 %rem
 
-  ;; CHECK: ct.clc	ca0, 32(csp)                    # 8-byte Folded Reload
-  ;; CHECK: ct.clc	ca1, 24(csp)                    # 8-byte Folded Reload
+  ;; CHECK: ct.clc	a0, 32(sp)                    # 8-byte Folded Reload
+  ;; CHECK: ct.clc	a1, 24(sp)                    # 8-byte Folded Reload
   store ptr addrspace(200) %x.coerce1, ptr addrspace(200) @force_use, align 8, !tbaa !11
 
   ;; CHECK: ct.ccall	_Z8GetValuev
@@ -666,11 +666,11 @@ entry:
   %add11 = add i32 %add10, %call6
   %rem12 = urem i32 %add11, 5
 
-  ;; CHECK: ct.clc	ca1, 8(csp)                     # 8-byte Folded Reload
-  ;; CHECK: ct.cincoffset	ca1, ca1, a0
+  ;; CHECK: ct.clc	a1, 8(sp)                     # 8-byte Folded Reload
+  ;; CHECK: ct.cincoffset	a1, a1, a0
   %add.ptr13 = getelementptr inbounds nuw i32, ptr addrspace(200) @dummies, i32 %rem12
 
-  ;; CHECK: ct.clc	ca0, 16(csp)                    # 8-byte Folded Reload
+  ;; CHECK: ct.clc	a0, 16(sp)                    # 8-byte Folded Reload
   %.fca.0.insert = insertvalue %struct.TwoPointers poison, ptr addrspace(200) %add.ptr, 0
   %.fca.1.insert = insertvalue %struct.TwoPointers %.fca.0.insert, ptr addrspace(200) %add.ptr13, 1
 
@@ -684,14 +684,14 @@ define dso_local cheriot_compartmentcalleecc %struct.ParentPtr @_Z13ChgParentPtr
 ;; CHECK:  _Z13ChgParentPtr4iiiii9ParentPtr:       # @_Z13ChgParentPtr4iiiii9ParentPtr
 ;; CHECK:  	mv	s1, a1
 ;; CHECK:  	mv	s0, a0
-;; CHECK:  	ct.clc	ca0, 0(ct0)
-;; CHECK:  	ct.csc	ca0, 32(csp)                    # 8-byte Folded Spill
+;; CHECK:  	ct.clc	a0, 0(t0)
+;; CHECK:  	ct.csc	a0, 32(sp)                    # 8-byte Folded Spill
 entry:
 
-  ;; CHECK:  	auicgp	ca0, %cheriot_compartment_hi(force_use)
-  ;; CHECK:  	cincoffset	ca0, ca0, %cheriot_compartment_lo_i(.LBB18_2)
-  ;; CHECK:  	ct.csc	ca0, 24(csp)                    # 8-byte Folded Spill
-  ;; CHECK:  	ct.csc	ca5, 0(ca0)
+  ;; CHECK:  	auicgp	a0, %cheriot_compartment_hi(force_use)
+  ;; CHECK:  	cincoffset	a0, a0, %cheriot_compartment_lo_i(.LBB18_2)
+  ;; CHECK:  	ct.csc	a0, 24(sp)                    # 8-byte Folded Spill
+  ;; CHECK:  	ct.csc	a5, 0(a0)
   %x.coerce1.fca.0.extract = extractvalue %struct.InnerPtr %x.coerce1, 0
   store ptr addrspace(200) %x.coerce0, ptr addrspace(200) @force_use, align 8, !tbaa !11
 
@@ -704,16 +704,16 @@ entry:
   %add5 = add i32 %add4, %call
   %rem = urem i32 %add5, 5
 
-  ;; CHECK:  	auicgp	ca3, %cheriot_compartment_hi(dummies)
-  ;; CHECK:  	cincoffset	ca3, ca3, %cheriot_compartment_lo_i(.LBB18_3)
-  ;; CHECK:  	ct.csetbounds	ca3, ca3, %cheriot_compartment_size(dummies)
-  ;; CHECK:  	ct.csc	ca3, 8(csp)                     # 8-byte Folded Spill
-  ;; CHECK:  	ct.cincoffset	ca0, ca3, a0
-  ;; CHECK:  	ct.csc	ca0, 16(csp)                    # 8-byte Folded Spill
+  ;; CHECK:  	auicgp	a3, %cheriot_compartment_hi(dummies)
+  ;; CHECK:  	cincoffset	a3, a3, %cheriot_compartment_lo_i(.LBB18_3)
+  ;; CHECK:  	ct.csetbounds	a3, a3, %cheriot_compartment_size(dummies)
+  ;; CHECK:  	ct.csc	a3, 8(sp)                     # 8-byte Folded Spill
+  ;; CHECK:  	ct.cincoffset	a0, a3, a0
+  ;; CHECK:  	ct.csc	a0, 16(sp)                    # 8-byte Folded Spill
   %add.ptr = getelementptr inbounds nuw i32, ptr addrspace(200) @dummies, i32 %rem
 
-  ;; CHECK:  	ct.clc	ca0, 32(csp)                    # 8-byte Folded Reload
-  ;; CHECK:  	ct.clc	ca1, 24(csp)                    # 8-byte Folded Reload
+  ;; CHECK:  	ct.clc	a0, 32(sp)                    # 8-byte Folded Reload
+  ;; CHECK:  	ct.clc	a1, 24(sp)                    # 8-byte Folded Reload
   store ptr addrspace(200) %x.coerce1.fca.0.extract, ptr addrspace(200) @force_use, align 8, !tbaa !11
 
   ;; CHECK:  	ct.ccall	_Z8GetValuev
@@ -725,10 +725,10 @@ entry:
   %add12 = add i32 %add11, %call7
   %rem13 = urem i32 %add12, 5
 
-  ;; CHECK:  	ct.cincoffset	ca1, ca1, a0
+  ;; CHECK:  	ct.cincoffset	a1, a1, a0
   %add.ptr14 = getelementptr inbounds nuw i32, ptr addrspace(200) @dummies, i32 %rem13
 
-  ;; CHECK:  	ct.clc	ca0, 16(csp)                    # 8-byte Folded Reload
+  ;; CHECK:  	ct.clc	a0, 16(sp)                    # 8-byte Folded Reload
   %.fca.0.insert = insertvalue %struct.ParentPtr poison, ptr addrspace(200) %add.ptr, 0
   %.fca.1.0.insert = insertvalue %struct.ParentPtr %.fca.0.insert, ptr addrspace(200) %add.ptr14, 1, 0
 
diff --git a/llvm/test/CodeGen/RISCV/cheri/cheriot-variadic-double-align.ll b/llvm/test/CodeGen/RISCV/cheri/cheriot-variadic-double-align.ll
index 05f4e481e44da..16e3d87903c84 100644
--- a/llvm/test/CodeGen/RISCV/cheri/cheriot-variadic-double-align.ll
+++ b/llvm/test/CodeGen/RISCV/cheri/cheriot-variadic-double-align.ll
@@ -9,14 +9,14 @@ declare hidden noundef double @_Z7va_testPKcz(ptr addrspace(200) nocapture readn
 
 define hidden noundef double @_Z6helperv() local_unnamed_addr addrspace(200) {
 ; CHECK-LABEL: _Z6helperv:
-; CHECK-NOT: csw [.*], 4(csp)
+; CHECK-NOT: csw [.*], 4(sp)
 ; CHECK-DAG: lui [[R0:.*]], 261939
 ; CHECK-DAG: lui [[R1:.*]], 209715
 ; CHECK-DAG: addi [[R0]], [[R0]], 819
 ; CHECK-DAG: addi [[R1]], [[R1]], 819
-; CHECK-DAG: csw [[R0]], 12(csp)
-; CHECK-DAG: csw [[R1]], 8(csp)
-; CHECK-NOT: csw [.*], 4(csp)
+; CHECK-DAG: csw [[R0]], 12(sp)
+; CHECK-DAG: csw [[R1]], 8(sp)
+; CHECK-NOT: csw [.*], 4(sp)
 entry:
   %call = tail call noundef double (ptr addrspace(200), ...) @_Z7va_testPKcz(ptr addrspace(200) nonnull poison, i32 noundef 0, double noundef 1.200000e+00)
   ret double %call
diff --git a/llvm/test/CodeGen/RISCV/cheri/cheriot-zero-sret.ll b/llvm/test/CodeGen/RISCV/cheri/cheriot-zero-sret.ll
index a55c408488093..2c674bac4185b 100644
--- a/llvm/test/CodeGen/RISCV/cheri/cheriot-zero-sret.ll
+++ b/llvm/test/CodeGen/RISCV/cheri/cheriot-zero-sret.ll
@@ -15,10 +15,10 @@ entry:
   call void @llvm.lifetime.start.p200i8(i64 12, i8 addrspace(200)* nonnull %0) #3
   ; CHECK-LABEL: _Z1hv:
   ; Make sure that a 3-word struct is zeroed without a memset call.
-  ; CHECK: csw	zero, 8(ca0)
-  ; CHECK: csw	zero, 4(ca0)
-  ; CHECK: csw	zero, 0(ca0)
-  ; CHECK: auipcc	ct1, %cheriot_compartment_hi(__import_sret__Z1fv)
+  ; CHECK: csw	zero, 8(a0)
+  ; CHECK: csw	zero, 4(a0)
+  ; CHECK: csw	zero, 0(a0)
+  ; CHECK: auipcc	t1, %cheriot_compartment_hi(__import_sret__Z1fv)
   notail call cheriot_compartmentcallcc void @_Z1fv(%struct.Smallish addrspace(200)* nonnull sret(%struct.Smallish) align 4 %ref.tmp) #4
   %foo.sroa.0.0..sroa_idx = getelementptr inbounds %struct.Smallish, %struct.Smallish addrspace(200)* %ref.tmp, i32 0, i32 0
   %foo.sroa.0.0.copyload = load i32, i32 addrspace(200)* %foo.sroa.0.0..sroa_idx, align 4, !tbaa.struct !4
@@ -43,7 +43,7 @@ entry:
   call void @llvm.lifetime.start.p200i8(i64 128, i8 addrspace(200)* nonnull %0) #3
   ; CHECK-LABEL: _Z1iv:
   ; Check that we do a proper memset for a big struct.
-  ; CHECK: 	auipcc	ct2, %cheriot_compartment_hi(__library_import_libcalls_memset)
+  ; CHECK: 	auipcc	t2, %cheriot_compartment_hi(__library_import_libcalls_memset)
   notail call cheriot_compartmentcallcc void @_Z1gv(%struct.Big addrspace(200)* nonnull sret(%struct.Big) align 1 %ref.tmp) #4
   %foo.sroa.0.0.copyload = load i8, i8 addrspace(200)* %0, align 1, !tbaa.struct !9
   call void @llvm.lifetime.end.p200i8(i64 128, i8 addrspace(200)* nonnull %0) #3
diff --git a/llvm/test/CodeGen/RISCV/cheri/compress.ll b/llvm/test/CodeGen/RISCV/cheri/compress.ll
index f546d91ec2f5a..4150f8e868893 100644
--- a/llvm/test/CodeGen/RISCV/cheri/compress.ll
+++ b/llvm/test/CodeGen/RISCV/cheri/compress.ll
@@ -26,33 +26,33 @@
 
 define i32 @loadstore(i32 addrspace(200)* %intptrarg, i8 addrspace(200)* addrspace(200)* %ptrptrarg) addrspace(200) #0 {
 ; CHECK-LABEL: <loadstore>:
-; CHECK-NEXT:    c.cincoffset16csp csp, -0x20
-; CHECK-NEXT:    c.clw a2, 0x0(ca0)
+; CHECK-NEXT:    c.cincoffset16csp sp, -0x20
+; CHECK-NEXT:    c.clw a2, 0x0(a0)
 ; CHECK-NEXT:    c.li a3, 0x1
-; CHECK-NEXT:    c.csw a3, 0x0(ca0)
-; CHECK-NEXT:    c.clc ca0, 0x0(ca1)
-; CHECK-NEXT:    c.csc ca0, 0x0(ca1)
-; CHECK-NEXT:    c.csccsp ca0, 0x10(csp)
-; CHECK-NEXT:    c.clccsp ca0, 0x10(csp)
-; CHECK-NEXT:    c.cswcsp a2, 0x0(csp)
-; CHECK-NEXT:    clw zero, 0x0(csp)
+; CHECK-NEXT:    c.csw a3, 0x0(a0)
+; CHECK-NEXT:    c.clc a0, 0x0(a1)
+; CHECK-NEXT:    c.csc a0, 0x0(a1)
+; CHECK-NEXT:    c.csccsp a0, 0x10(sp)
+; CHECK-NEXT:    c.clccsp a0, 0x10(sp)
+; CHECK-NEXT:    c.cswcsp a2, 0x0(sp)
+; CHECK-NEXT:    clw zero, 0x0(sp)
 ; CHECK-NEXT:    c.mv a0, a2
-; CHECK-NEXT:    c.cincoffset16csp csp, 0x20
-; CHECK-NEXT:    c.cjr cra
+; CHECK-NEXT:    c.cincoffset16csp sp, 0x20
+; CHECK-NEXT:    c.cjr ra
 ; CHECK-NORVC-LABEL: <loadstore>:
-; CHECK-NORVC-NEXT:  {{[^a-z.]}}cincoffset csp, csp, -0x20
-; CHECK-NORVC-NEXT:  {{[^a-z.]}}clw a2, 0x0(ca0)
+; CHECK-NORVC-NEXT:  {{[^a-z.]}}cincoffset sp, sp, -0x20
+; CHECK-NORVC-NEXT:  {{[^a-z.]}}clw a2, 0x0(a0)
 ; CHECK-NORVC-NEXT:  {{[^a-z.]}}c.li a3, 0x1
-; CHECK-NORVC-NEXT:  {{[^a-z.]}}csw a3, 0x0(ca0)
-; CHECK-NORVC-NEXT:  {{[^a-z.]}}clc ca0, 0x0(ca1)
-; CHECK-NORVC-NEXT:  {{[^a-z.]}}csc ca0, 0x0(ca1)
-; CHECK-NORVC-NEXT:  {{[^a-z.]}}csc ca0, 0x10(csp)
-; CHECK-NORVC-NEXT:  {{[^a-z.]}}clc ca0, 0x10(csp)
-; CHECK-NORVC-NEXT:  {{[^a-z.]}}csw a2, 0x0(csp)
-; CHECK-NORVC-NEXT:  {{[^a-z.]}}clw zero, 0x0(csp)
+; CHECK-NORVC-NEXT:  {{[^a-z.]}}csw a3, 0x0(a0)
+; CHECK-NORVC-NEXT:  {{[^a-z.]}}clc a0, 0x0(a1)
+; CHECK-NORVC-NEXT:  {{[^a-z.]}}csc a0, 0x0(a1)
+; CHECK-NORVC-NEXT:  {{[^a-z.]}}csc a0, 0x10(sp)
+; CHECK-NORVC-NEXT:  {{[^a-z.]}}clc a0, 0x10(sp)
+; CHECK-NORVC-NEXT:  {{[^a-z.]}}csw a2, 0x0(sp)
+; CHECK-NORVC-NEXT:  {{[^a-z.]}}clw zero, 0x0(sp)
 ; CHECK-NORVC-NEXT:  {{[^a-z.]}}c.mv a0, a2
-; CHECK-NORVC-NEXT:  {{[^a-z.]}}cincoffset csp, csp, 0x20
-; CHECK-NORVC-NEXT:  {{[^a-z.]}}cjalr cnull, 0x0(cra)
+; CHECK-NORVC-NEXT:  {{[^a-z.]}}cincoffset sp, sp, 0x20
+; CHECK-NORVC-NEXT:  {{[^a-z.]}}cjalr zero, 0x0(ra)
   %stackptr = alloca i8 addrspace(200)*, align 16, addrspace(200)
   %stackint = alloca i32, align 16, addrspace(200)
   %val = load volatile i32, i32 addrspace(200)* %intptrarg
@@ -69,33 +69,33 @@ define i32 @loadstore(i32 addrspace(200)* %intptrarg, i8 addrspace(200)* addrspa
 ;; NB: No c.cjalr here, linker relaxations expect the full sequence.
 define i32 @call() addrspace(200) #0 {
 ; CHECK-LABEL: <call>:
-; CHECK-NEXT:    c.cincoffset16csp csp, -{{0x70|0x90}}
-; CHECK-NEXT:    c.csccsp cra, {{0x68|0x80}}(csp)
-; CHECK-NEXT:    c.cincoffset4cspn ca0, csp, 0x40
-; CHECK-NEXT:    cincoffset ca1, csp, 0x0
-; CHECK-NEXT:    csetbounds ca0, ca0, {{0x20|0x40}}
-; CHECK-NEXT:    csetbounds ca2, ca1, 0x40
-; CHECK-NEXT:    cincoffset ca1, ca0, {{0x18|0x30}}
-; CHECK-NEXT:    cincoffset ca0, ca2, 0xc
-; CHECK-NEXT:    auipcc cra, 0x0
-; CHECK-NEXT:    cjalr cra, 0x0(cra)
-; CHECK-NEXT:    c.clccsp cra, {{0x68|0x80}}(csp)
-; CHECK-NEXT:    c.cincoffset16csp csp, {{0x70|0x90}}
-; CHECK-NEXT:    c.cjr cra
+; CHECK-NEXT:    c.cincoffset16csp sp, -{{0x70|0x90}}
+; CHECK-NEXT:    c.csccsp ra, {{0x68|0x80}}(sp)
+; CHECK-NEXT:    c.cincoffset4cspn a0, sp, 0x40
+; CHECK-NEXT:    cincoffset a1, sp, 0x0
+; CHECK-NEXT:    csetbounds a0, a0, {{0x20|0x40}}
+; CHECK-NEXT:    csetbounds a2, a1, 0x40
+; CHECK-NEXT:    cincoffset a1, a0, {{0x18|0x30}}
+; CHECK-NEXT:    cincoffset a0, a2, 0xc
+; CHECK-NEXT:    auipcc ra, 0x0
+; CHECK-NEXT:    cjalr ra, 0x0(ra)
+; CHECK-NEXT:    c.clccsp ra, {{0x68|0x80}}(sp)
+; CHECK-NEXT:    c.cincoffset16csp sp, {{0x70|0x90}}
+; CHECK-NEXT:    c.cjr ra
 ; CHECK-NORVC-LABEL: <call>:
-; CHECK-NORVC-NEXT:  {{[^a-z.]}}cincoffset csp, csp, -0x90
-; CHECK-NORVC-NEXT:  {{[^a-z.]}}csc cra, 0x80(csp)
-; CHECK-NORVC-NEXT:  {{[^a-z.]}}cincoffset ca0, csp, 0x40
-; CHECK-NORVC-NEXT:  {{[^a-z.]}}cincoffset ca1, csp, 0x0
-; CHECK-NORVC-NEXT:  {{[^a-z.]}}csetbounds ca0, ca0, 0x40
-; CHECK-NORVC-NEXT:  {{[^a-z.]}}csetbounds ca2, ca1, 0x40
-; CHECK-NORVC-NEXT:  {{[^a-z.]}}cincoffset ca1, ca0, 0x30
-; CHECK-NORVC-NEXT:  {{[^a-z.]}}cincoffset ca0, ca2, 0xc
-; CHECK-NORVC-NEXT:  {{[^a-z.]}}auipcc cra, 0x0
-; CHECK-NORVC-NEXT:  {{[^a-z.]}}cjalr cra, 0x0(cra)
-; CHECK-NORVC-NEXT:  {{[^a-z.]}}clc cra, 0x80(csp)
-; CHECK-NORVC-NEXT:  {{[^a-z.]}}cincoffset csp, csp, 0x90
-; CHECK-NORVC-NEXT:  {{[^a-z.]}}cjalr cnull, 0x0(cra)
+; CHECK-NORVC-NEXT:  {{[^a-z.]}}cincoffset sp, sp, -0x90
+; CHECK-NORVC-NEXT:  {{[^a-z.]}}csc ra, 0x80(sp)
+; CHECK-NORVC-NEXT:  {{[^a-z.]}}cincoffset a0, sp, 0x40
+; CHECK-NORVC-NEXT:  {{[^a-z.]}}cincoffset a1, sp, 0x0
+; CHECK-NORVC-NEXT:  {{[^a-z.]}}csetbounds a0, a0, 0x40
+; CHECK-NORVC-NEXT:  {{[^a-z.]}}csetbounds a2, a1, 0x40
+; CHECK-NORVC-NEXT:  {{[^a-z.]}}cincoffset a1, a0, 0x30
+; CHECK-NORVC-NEXT:  {{[^a-z.]}}cincoffset a0, a2, 0xc
+; CHECK-NORVC-NEXT:  {{[^a-z.]}}auipcc ra, 0x0
+; CHECK-NORVC-NEXT:  {{[^a-z.]}}cjalr ra, 0x0(ra)
+; CHECK-NORVC-NEXT:  {{[^a-z.]}}clc ra, 0x80(sp)
+; CHECK-NORVC-NEXT:  {{[^a-z.]}}cincoffset sp, sp, 0x90
+; CHECK-NORVC-NEXT:  {{[^a-z.]}}cjalr zero, 0x0(ra)
 
   %ptrarray = alloca [4 x i8 addrspace(200)*], align 16, addrspace(200)
   %intarray = alloca [16 x i32], align 1, addrspace(200)
diff --git a/llvm/test/CodeGen/RISCV/cheri/double-imm.ll b/llvm/test/CodeGen/RISCV/cheri/double-imm.ll
index 966421c8463b2..a191d9581989f 100644
--- a/llvm/test/CodeGen/RISCV/cheri/double-imm.ll
+++ b/llvm/test/CodeGen/RISCV/cheri/double-imm.ll
@@ -17,9 +17,9 @@ define double @double_add_const(double %a) nounwind {
 ; CHECK-LABEL: double_add_const:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:  .LBB0_1: # Label of block must be emitted
-; CHECK-NEXT:    auipcc ca0, %pcrel_hi(.LCPI0_0)
-; CHECK-NEXT:    cincoffset ca0, ca0, %pcrel_lo(.LBB0_1)
-; CHECK-NEXT:    cfld fa5, 0(ca0)
+; CHECK-NEXT:    auipcc a0, %pcrel_hi(.LCPI0_0)
+; CHECK-NEXT:    cincoffset a0, a0, %pcrel_lo(.LBB0_1)
+; CHECK-NEXT:    cfld fa5, 0(a0)
 ; CHECK-NEXT:    fadd.d fa0, fa0, fa5
 ; CHECK-NEXT:    cret
   %1 = fadd double %a, 1.0
diff --git a/llvm/test/CodeGen/RISCV/cheri/double-mem.ll b/llvm/test/CodeGen/RISCV/cheri/double-mem.ll
index 880188873ab09..bbe153b2fd59c 100644
--- a/llvm/test/CodeGen/RISCV/cheri/double-mem.ll
+++ b/llvm/test/CodeGen/RISCV/cheri/double-mem.ll
@@ -1,15 +1,15 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -target-abi ilp32 -mattr=+f,+d,+xcheri,-cap-mode -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -target-abi ilp32 -mattr=+f,+d,+xcheri,-xcheripurecap -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=CHECK-ILP32 %s
-; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=+f,+d,+xcheri,-cap-mode -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=+f,+d,+xcheri,-xcheripurecap -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=CHECK-ILP32D %s
 ; RUN: llc -mtriple=riscv32 -target-abi il32pc64 -mattr=+f,+d,+xcheri,+xcheripurecap -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=CHECK-IL32PC64 %s
 ; RUN: llc -mtriple=riscv32 -target-abi il32pc64d -mattr=+f,+d,+xcheri,+xcheripurecap -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=CHECK-IL32PC64D %s
-; RUN: llc -mtriple=riscv64 -target-abi lp64 -mattr=+f,+d,+xcheri,-cap-mode -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -target-abi lp64 -mattr=+f,+d,+xcheri,-xcheripurecap -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=CHECK-LP64 %s
-; RUN: llc -mtriple=riscv64 -target-abi lp64d -mattr=+f,+d,+xcheri,-cap-mode -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -target-abi lp64d -mattr=+f,+d,+xcheri,-xcheripurecap -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=CHECK-LP64D %s
 ; RUN: llc -mtriple=riscv64 -target-abi l64pc128 -mattr=+f,+d,+xcheri,+xcheripurecap -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=CHECK-L64PC128 %s
@@ -40,45 +40,45 @@ define dso_local double @ddc_fld(double* %a) nounwind {
 ;
 ; CHECK-IL32PC64-LABEL: ddc_fld:
 ; CHECK-IL32PC64:       # %bb.0:
-; CHECK-IL32PC64-NEXT:    cincoffset csp, csp, -16
+; CHECK-IL32PC64-NEXT:    cincoffset sp, sp, -16
 ; CHECK-IL32PC64-NEXT:    lw.ddc a1, (a0)
 ; CHECK-IL32PC64-NEXT:    addi a2, a0, 4
 ; CHECK-IL32PC64-NEXT:    lw.ddc a2, (a2)
 ; CHECK-IL32PC64-NEXT:    addi a0, a0, 24
-; CHECK-IL32PC64-NEXT:    csw a1, 8(csp)
+; CHECK-IL32PC64-NEXT:    csw a1, 8(sp)
 ; CHECK-IL32PC64-NEXT:    addi a1, a0, 4
-; CHECK-IL32PC64-NEXT:    csw a2, 12(csp)
-; CHECK-IL32PC64-NEXT:    cfld fa5, 8(csp)
+; CHECK-IL32PC64-NEXT:    csw a2, 12(sp)
+; CHECK-IL32PC64-NEXT:    cfld fa5, 8(sp)
 ; CHECK-IL32PC64-NEXT:    lw.ddc a0, (a0)
 ; CHECK-IL32PC64-NEXT:    lw.ddc a1, (a1)
-; CHECK-IL32PC64-NEXT:    csw a0, 8(csp)
-; CHECK-IL32PC64-NEXT:    csw a1, 12(csp)
-; CHECK-IL32PC64-NEXT:    cfld fa4, 8(csp)
+; CHECK-IL32PC64-NEXT:    csw a0, 8(sp)
+; CHECK-IL32PC64-NEXT:    csw a1, 12(sp)
+; CHECK-IL32PC64-NEXT:    cfld fa4, 8(sp)
 ; CHECK-IL32PC64-NEXT:    fadd.d fa5, fa5, fa4
-; CHECK-IL32PC64-NEXT:    cfsd fa5, 8(csp)
-; CHECK-IL32PC64-NEXT:    clw a0, 8(csp)
-; CHECK-IL32PC64-NEXT:    clw a1, 12(csp)
-; CHECK-IL32PC64-NEXT:    cincoffset csp, csp, 16
+; CHECK-IL32PC64-NEXT:    cfsd fa5, 8(sp)
+; CHECK-IL32PC64-NEXT:    clw a0, 8(sp)
+; CHECK-IL32PC64-NEXT:    clw a1, 12(sp)
+; CHECK-IL32PC64-NEXT:    cincoffset sp, sp, 16
 ; CHECK-IL32PC64-NEXT:    cret
 ;
 ; CHECK-IL32PC64D-LABEL: ddc_fld:
 ; CHECK-IL32PC64D:       # %bb.0:
-; CHECK-IL32PC64D-NEXT:    cincoffset csp, csp, -16
+; CHECK-IL32PC64D-NEXT:    cincoffset sp, sp, -16
 ; CHECK-IL32PC64D-NEXT:    lw.ddc a1, (a0)
 ; CHECK-IL32PC64D-NEXT:    addi a2, a0, 4
 ; CHECK-IL32PC64D-NEXT:    lw.ddc a2, (a2)
 ; CHECK-IL32PC64D-NEXT:    addi a0, a0, 24
-; CHECK-IL32PC64D-NEXT:    csw a1, 8(csp)
+; CHECK-IL32PC64D-NEXT:    csw a1, 8(sp)
 ; CHECK-IL32PC64D-NEXT:    addi a1, a0, 4
-; CHECK-IL32PC64D-NEXT:    csw a2, 12(csp)
-; CHECK-IL32PC64D-NEXT:    cfld fa5, 8(csp)
+; CHECK-IL32PC64D-NEXT:    csw a2, 12(sp)
+; CHECK-IL32PC64D-NEXT:    cfld fa5, 8(sp)
 ; CHECK-IL32PC64D-NEXT:    lw.ddc a0, (a0)
 ; CHECK-IL32PC64D-NEXT:    lw.ddc a1, (a1)
-; CHECK-IL32PC64D-NEXT:    csw a0, 8(csp)
-; CHECK-IL32PC64D-NEXT:    csw a1, 12(csp)
-; CHECK-IL32PC64D-NEXT:    cfld fa4, 8(csp)
+; CHECK-IL32PC64D-NEXT:    csw a0, 8(sp)
+; CHECK-IL32PC64D-NEXT:    csw a1, 12(sp)
+; CHECK-IL32PC64D-NEXT:    cfld fa4, 8(sp)
 ; CHECK-IL32PC64D-NEXT:    fadd.d fa0, fa5, fa4
-; CHECK-IL32PC64D-NEXT:    cincoffset csp, csp, 16
+; CHECK-IL32PC64D-NEXT:    cincoffset sp, sp, 16
 ; CHECK-IL32PC64D-NEXT:    cret
 ;
 ; CHECK-LP64-LABEL: ddc_fld:
@@ -150,48 +150,48 @@ define dso_local void @ddc_fsd(double* %a, double %b, double %c) nounwind {
 ;
 ; CHECK-IL32PC64-LABEL: ddc_fsd:
 ; CHECK-IL32PC64:       # %bb.0:
-; CHECK-IL32PC64-NEXT:    cincoffset csp, csp, -16
-; CHECK-IL32PC64-NEXT:    csw a3, 8(csp)
-; CHECK-IL32PC64-NEXT:    csw a4, 12(csp)
-; CHECK-IL32PC64-NEXT:    cfld fa5, 8(csp)
-; CHECK-IL32PC64-NEXT:    csw a1, 8(csp)
-; CHECK-IL32PC64-NEXT:    csw a2, 12(csp)
-; CHECK-IL32PC64-NEXT:    cfld fa4, 8(csp)
+; CHECK-IL32PC64-NEXT:    cincoffset sp, sp, -16
+; CHECK-IL32PC64-NEXT:    csw a3, 8(sp)
+; CHECK-IL32PC64-NEXT:    csw a4, 12(sp)
+; CHECK-IL32PC64-NEXT:    cfld fa5, 8(sp)
+; CHECK-IL32PC64-NEXT:    csw a1, 8(sp)
+; CHECK-IL32PC64-NEXT:    csw a2, 12(sp)
+; CHECK-IL32PC64-NEXT:    cfld fa4, 8(sp)
 ; CHECK-IL32PC64-NEXT:    fadd.d fa5, fa4, fa5
-; CHECK-IL32PC64-NEXT:    cfsd fa5, 8(csp)
-; CHECK-IL32PC64-NEXT:    clw a1, 8(csp)
-; CHECK-IL32PC64-NEXT:    clw a2, 12(csp)
+; CHECK-IL32PC64-NEXT:    cfsd fa5, 8(sp)
+; CHECK-IL32PC64-NEXT:    clw a1, 8(sp)
+; CHECK-IL32PC64-NEXT:    clw a2, 12(sp)
 ; CHECK-IL32PC64-NEXT:    addi a3, a0, 4
 ; CHECK-IL32PC64-NEXT:    sw.ddc a1, (a0)
 ; CHECK-IL32PC64-NEXT:    sw.ddc a2, (a3)
-; CHECK-IL32PC64-NEXT:    cfsd fa5, 8(csp)
-; CHECK-IL32PC64-NEXT:    clw a1, 8(csp)
-; CHECK-IL32PC64-NEXT:    clw a2, 12(csp)
+; CHECK-IL32PC64-NEXT:    cfsd fa5, 8(sp)
+; CHECK-IL32PC64-NEXT:    clw a1, 8(sp)
+; CHECK-IL32PC64-NEXT:    clw a2, 12(sp)
 ; CHECK-IL32PC64-NEXT:    addi a0, a0, 64
 ; CHECK-IL32PC64-NEXT:    addi a3, a0, 4
 ; CHECK-IL32PC64-NEXT:    sw.ddc a1, (a0)
 ; CHECK-IL32PC64-NEXT:    sw.ddc a2, (a3)
-; CHECK-IL32PC64-NEXT:    cincoffset csp, csp, 16
+; CHECK-IL32PC64-NEXT:    cincoffset sp, sp, 16
 ; CHECK-IL32PC64-NEXT:    cret
 ;
 ; CHECK-IL32PC64D-LABEL: ddc_fsd:
 ; CHECK-IL32PC64D:       # %bb.0:
-; CHECK-IL32PC64D-NEXT:    cincoffset csp, csp, -16
+; CHECK-IL32PC64D-NEXT:    cincoffset sp, sp, -16
 ; CHECK-IL32PC64D-NEXT:    fadd.d fa5, fa0, fa1
-; CHECK-IL32PC64D-NEXT:    cfsd fa5, 8(csp)
-; CHECK-IL32PC64D-NEXT:    clw a1, 8(csp)
-; CHECK-IL32PC64D-NEXT:    clw a2, 12(csp)
+; CHECK-IL32PC64D-NEXT:    cfsd fa5, 8(sp)
+; CHECK-IL32PC64D-NEXT:    clw a1, 8(sp)
+; CHECK-IL32PC64D-NEXT:    clw a2, 12(sp)
 ; CHECK-IL32PC64D-NEXT:    sw.ddc a1, (a0)
 ; CHECK-IL32PC64D-NEXT:    addi a1, a0, 4
 ; CHECK-IL32PC64D-NEXT:    sw.ddc a2, (a1)
-; CHECK-IL32PC64D-NEXT:    cfsd fa5, 8(csp)
-; CHECK-IL32PC64D-NEXT:    clw a1, 8(csp)
-; CHECK-IL32PC64D-NEXT:    clw a2, 12(csp)
+; CHECK-IL32PC64D-NEXT:    cfsd fa5, 8(sp)
+; CHECK-IL32PC64D-NEXT:    clw a1, 8(sp)
+; CHECK-IL32PC64D-NEXT:    clw a2, 12(sp)
 ; CHECK-IL32PC64D-NEXT:    addi a0, a0, 64
 ; CHECK-IL32PC64D-NEXT:    sw.ddc a1, (a0)
 ; CHECK-IL32PC64D-NEXT:    addi a0, a0, 4
 ; CHECK-IL32PC64D-NEXT:    sw.ddc a2, (a0)
-; CHECK-IL32PC64D-NEXT:    cincoffset csp, csp, 16
+; CHECK-IL32PC64D-NEXT:    cincoffset sp, sp, 16
 ; CHECK-IL32PC64D-NEXT:    cret
 ;
 ; CHECK-LP64-LABEL: ddc_fsd:
@@ -242,16 +242,16 @@ define dso_local double @cap_fld(double addrspace(200)* %a) nounwind {
 ; CHECK-ILP32-LABEL: cap_fld:
 ; CHECK-ILP32:       # %bb.0:
 ; CHECK-ILP32-NEXT:    addi sp, sp, -16
-; CHECK-ILP32-NEXT:    lw.cap a1, (ca0)
-; CHECK-ILP32-NEXT:    cincoffset ca2, ca0, 4
-; CHECK-ILP32-NEXT:    lw.cap a2, (ca2)
-; CHECK-ILP32-NEXT:    cincoffset ca0, ca0, 24
-; CHECK-ILP32-NEXT:    cincoffset ca3, ca0, 4
+; CHECK-ILP32-NEXT:    lw.cap a1, (a0)
+; CHECK-ILP32-NEXT:    cincoffset a2, a0, 4
+; CHECK-ILP32-NEXT:    lw.cap a2, (a2)
+; CHECK-ILP32-NEXT:    cincoffset a0, a0, 24
+; CHECK-ILP32-NEXT:    cincoffset a3, a0, 4
 ; CHECK-ILP32-NEXT:    sw a1, 8(sp)
 ; CHECK-ILP32-NEXT:    sw a2, 12(sp)
 ; CHECK-ILP32-NEXT:    fld fa5, 8(sp)
-; CHECK-ILP32-NEXT:    lw.cap a0, (ca0)
-; CHECK-ILP32-NEXT:    lw.cap a1, (ca3)
+; CHECK-ILP32-NEXT:    lw.cap a0, (a0)
+; CHECK-ILP32-NEXT:    lw.cap a1, (a3)
 ; CHECK-ILP32-NEXT:    sw a0, 8(sp)
 ; CHECK-ILP32-NEXT:    sw a1, 12(sp)
 ; CHECK-ILP32-NEXT:    fld fa4, 8(sp)
@@ -265,16 +265,16 @@ define dso_local double @cap_fld(double addrspace(200)* %a) nounwind {
 ; CHECK-ILP32D-LABEL: cap_fld:
 ; CHECK-ILP32D:       # %bb.0:
 ; CHECK-ILP32D-NEXT:    addi sp, sp, -16
-; CHECK-ILP32D-NEXT:    lw.cap a1, (ca0)
-; CHECK-ILP32D-NEXT:    cincoffset ca2, ca0, 4
-; CHECK-ILP32D-NEXT:    lw.cap a2, (ca2)
-; CHECK-ILP32D-NEXT:    cincoffset ca0, ca0, 24
-; CHECK-ILP32D-NEXT:    cincoffset ca3, ca0, 4
+; CHECK-ILP32D-NEXT:    lw.cap a1, (a0)
+; CHECK-ILP32D-NEXT:    cincoffset a2, a0, 4
+; CHECK-ILP32D-NEXT:    lw.cap a2, (a2)
+; CHECK-ILP32D-NEXT:    cincoffset a0, a0, 24
+; CHECK-ILP32D-NEXT:    cincoffset a3, a0, 4
 ; CHECK-ILP32D-NEXT:    sw a1, 8(sp)
 ; CHECK-ILP32D-NEXT:    sw a2, 12(sp)
 ; CHECK-ILP32D-NEXT:    fld fa5, 8(sp)
-; CHECK-ILP32D-NEXT:    lw.cap a0, (ca0)
-; CHECK-ILP32D-NEXT:    lw.cap a1, (ca3)
+; CHECK-ILP32D-NEXT:    lw.cap a0, (a0)
+; CHECK-ILP32D-NEXT:    lw.cap a1, (a3)
 ; CHECK-ILP32D-NEXT:    sw a0, 8(sp)
 ; CHECK-ILP32D-NEXT:    sw a1, 12(sp)
 ; CHECK-ILP32D-NEXT:    fld fa4, 8(sp)
@@ -284,28 +284,28 @@ define dso_local double @cap_fld(double addrspace(200)* %a) nounwind {
 ;
 ; CHECK-IL32PC64-LABEL: cap_fld:
 ; CHECK-IL32PC64:       # %bb.0:
-; CHECK-IL32PC64-NEXT:    cincoffset csp, csp, -16
-; CHECK-IL32PC64-NEXT:    cfld fa5, 0(ca0)
-; CHECK-IL32PC64-NEXT:    cfld fa4, 24(ca0)
+; CHECK-IL32PC64-NEXT:    cincoffset sp, sp, -16
+; CHECK-IL32PC64-NEXT:    cfld fa5, 0(a0)
+; CHECK-IL32PC64-NEXT:    cfld fa4, 24(a0)
 ; CHECK-IL32PC64-NEXT:    fadd.d fa5, fa5, fa4
-; CHECK-IL32PC64-NEXT:    cfsd fa5, 8(csp)
-; CHECK-IL32PC64-NEXT:    clw a0, 8(csp)
-; CHECK-IL32PC64-NEXT:    clw a1, 12(csp)
-; CHECK-IL32PC64-NEXT:    cincoffset csp, csp, 16
+; CHECK-IL32PC64-NEXT:    cfsd fa5, 8(sp)
+; CHECK-IL32PC64-NEXT:    clw a0, 8(sp)
+; CHECK-IL32PC64-NEXT:    clw a1, 12(sp)
+; CHECK-IL32PC64-NEXT:    cincoffset sp, sp, 16
 ; CHECK-IL32PC64-NEXT:    cret
 ;
 ; CHECK-IL32PC64D-LABEL: cap_fld:
 ; CHECK-IL32PC64D:       # %bb.0:
-; CHECK-IL32PC64D-NEXT:    cfld fa5, 0(ca0)
-; CHECK-IL32PC64D-NEXT:    cfld fa4, 24(ca0)
+; CHECK-IL32PC64D-NEXT:    cfld fa5, 0(a0)
+; CHECK-IL32PC64D-NEXT:    cfld fa4, 24(a0)
 ; CHECK-IL32PC64D-NEXT:    fadd.d fa0, fa5, fa4
 ; CHECK-IL32PC64D-NEXT:    cret
 ;
 ; CHECK-LP64-LABEL: cap_fld:
 ; CHECK-LP64:       # %bb.0:
-; CHECK-LP64-NEXT:    ld.cap a1, (ca0)
-; CHECK-LP64-NEXT:    cincoffset ca0, ca0, 24
-; CHECK-LP64-NEXT:    ld.cap a0, (ca0)
+; CHECK-LP64-NEXT:    ld.cap a1, (a0)
+; CHECK-LP64-NEXT:    cincoffset a0, a0, 24
+; CHECK-LP64-NEXT:    ld.cap a0, (a0)
 ; CHECK-LP64-NEXT:    fmv.d.x fa5, a1
 ; CHECK-LP64-NEXT:    fmv.d.x fa4, a0
 ; CHECK-LP64-NEXT:    fadd.d fa5, fa5, fa4
@@ -314,9 +314,9 @@ define dso_local double @cap_fld(double addrspace(200)* %a) nounwind {
 ;
 ; CHECK-LP64D-LABEL: cap_fld:
 ; CHECK-LP64D:       # %bb.0:
-; CHECK-LP64D-NEXT:    ld.cap a1, (ca0)
-; CHECK-LP64D-NEXT:    cincoffset ca0, ca0, 24
-; CHECK-LP64D-NEXT:    ld.cap a0, (ca0)
+; CHECK-LP64D-NEXT:    ld.cap a1, (a0)
+; CHECK-LP64D-NEXT:    cincoffset a0, a0, 24
+; CHECK-LP64D-NEXT:    ld.cap a0, (a0)
 ; CHECK-LP64D-NEXT:    fmv.d.x fa5, a1
 ; CHECK-LP64D-NEXT:    fmv.d.x fa4, a0
 ; CHECK-LP64D-NEXT:    fadd.d fa0, fa5, fa4
@@ -324,16 +324,16 @@ define dso_local double @cap_fld(double addrspace(200)* %a) nounwind {
 ;
 ; CHECK-L64PC128-LABEL: cap_fld:
 ; CHECK-L64PC128:       # %bb.0:
-; CHECK-L64PC128-NEXT:    cfld fa5, 0(ca0)
-; CHECK-L64PC128-NEXT:    cfld fa4, 24(ca0)
+; CHECK-L64PC128-NEXT:    cfld fa5, 0(a0)
+; CHECK-L64PC128-NEXT:    cfld fa4, 24(a0)
 ; CHECK-L64PC128-NEXT:    fadd.d fa5, fa5, fa4
 ; CHECK-L64PC128-NEXT:    fmv.x.d a0, fa5
 ; CHECK-L64PC128-NEXT:    cret
 ;
 ; CHECK-L64PC128D-LABEL: cap_fld:
 ; CHECK-L64PC128D:       # %bb.0:
-; CHECK-L64PC128D-NEXT:    cfld fa5, 0(ca0)
-; CHECK-L64PC128D-NEXT:    cfld fa4, 24(ca0)
+; CHECK-L64PC128D-NEXT:    cfld fa5, 0(a0)
+; CHECK-L64PC128D-NEXT:    cfld fa4, 24(a0)
 ; CHECK-L64PC128D-NEXT:    fadd.d fa0, fa5, fa4
 ; CHECK-L64PC128D-NEXT:    cret
   %1 = load double, double addrspace(200)* %a
@@ -359,16 +359,16 @@ define dso_local void @cap_fsd(double addrspace(200)* %a, double %b, double %c)
 ; CHECK-ILP32-NEXT:    fsd fa5, 8(sp)
 ; CHECK-ILP32-NEXT:    lw a1, 8(sp)
 ; CHECK-ILP32-NEXT:    lw a2, 12(sp)
-; CHECK-ILP32-NEXT:    cincoffset ca3, ca0, 4
-; CHECK-ILP32-NEXT:    sw.cap a1, (ca0)
-; CHECK-ILP32-NEXT:    sw.cap a2, (ca3)
+; CHECK-ILP32-NEXT:    cincoffset a3, a0, 4
+; CHECK-ILP32-NEXT:    sw.cap a1, (a0)
+; CHECK-ILP32-NEXT:    sw.cap a2, (a3)
 ; CHECK-ILP32-NEXT:    fsd fa5, 8(sp)
 ; CHECK-ILP32-NEXT:    lw a1, 8(sp)
 ; CHECK-ILP32-NEXT:    lw a2, 12(sp)
-; CHECK-ILP32-NEXT:    cincoffset ca0, ca0, 64
-; CHECK-ILP32-NEXT:    cincoffset ca3, ca0, 4
-; CHECK-ILP32-NEXT:    sw.cap a1, (ca0)
-; CHECK-ILP32-NEXT:    sw.cap a2, (ca3)
+; CHECK-ILP32-NEXT:    cincoffset a0, a0, 64
+; CHECK-ILP32-NEXT:    cincoffset a3, a0, 4
+; CHECK-ILP32-NEXT:    sw.cap a1, (a0)
+; CHECK-ILP32-NEXT:    sw.cap a2, (a3)
 ; CHECK-ILP32-NEXT:    addi sp, sp, 16
 ; CHECK-ILP32-NEXT:    ret
 ;
@@ -379,59 +379,59 @@ define dso_local void @cap_fsd(double addrspace(200)* %a, double %b, double %c)
 ; CHECK-ILP32D-NEXT:    fsd fa5, 8(sp)
 ; CHECK-ILP32D-NEXT:    lw a1, 8(sp)
 ; CHECK-ILP32D-NEXT:    lw a2, 12(sp)
-; CHECK-ILP32D-NEXT:    sw.cap a1, (ca0)
-; CHECK-ILP32D-NEXT:    cincoffset ca1, ca0, 4
-; CHECK-ILP32D-NEXT:    sw.cap a2, (ca1)
+; CHECK-ILP32D-NEXT:    sw.cap a1, (a0)
+; CHECK-ILP32D-NEXT:    cincoffset a1, a0, 4
+; CHECK-ILP32D-NEXT:    sw.cap a2, (a1)
 ; CHECK-ILP32D-NEXT:    fsd fa5, 8(sp)
 ; CHECK-ILP32D-NEXT:    lw a1, 8(sp)
 ; CHECK-ILP32D-NEXT:    lw a2, 12(sp)
-; CHECK-ILP32D-NEXT:    cincoffset ca0, ca0, 64
-; CHECK-ILP32D-NEXT:    sw.cap a1, (ca0)
-; CHECK-ILP32D-NEXT:    cincoffset ca0, ca0, 4
-; CHECK-ILP32D-NEXT:    sw.cap a2, (ca0)
+; CHECK-ILP32D-NEXT:    cincoffset a0, a0, 64
+; CHECK-ILP32D-NEXT:    sw.cap a1, (a0)
+; CHECK-ILP32D-NEXT:    cincoffset a0, a0, 4
+; CHECK-ILP32D-NEXT:    sw.cap a2, (a0)
 ; CHECK-ILP32D-NEXT:    addi sp, sp, 16
 ; CHECK-ILP32D-NEXT:    ret
 ;
 ; CHECK-IL32PC64-LABEL: cap_fsd:
 ; CHECK-IL32PC64:       # %bb.0:
-; CHECK-IL32PC64-NEXT:    cincoffset csp, csp, -16
-; CHECK-IL32PC64-NEXT:    csw a3, 8(csp)
-; CHECK-IL32PC64-NEXT:    csw a4, 12(csp)
-; CHECK-IL32PC64-NEXT:    cfld fa5, 8(csp)
-; CHECK-IL32PC64-NEXT:    csw a1, 8(csp)
-; CHECK-IL32PC64-NEXT:    csw a2, 12(csp)
-; CHECK-IL32PC64-NEXT:    cfld fa4, 8(csp)
+; CHECK-IL32PC64-NEXT:    cincoffset sp, sp, -16
+; CHECK-IL32PC64-NEXT:    csw a3, 8(sp)
+; CHECK-IL32PC64-NEXT:    csw a4, 12(sp)
+; CHECK-IL32PC64-NEXT:    cfld fa5, 8(sp)
+; CHECK-IL32PC64-NEXT:    csw a1, 8(sp)
+; CHECK-IL32PC64-NEXT:    csw a2, 12(sp)
+; CHECK-IL32PC64-NEXT:    cfld fa4, 8(sp)
 ; CHECK-IL32PC64-NEXT:    fadd.d fa5, fa4, fa5
-; CHECK-IL32PC64-NEXT:    cfsd fa5, 0(ca0)
-; CHECK-IL32PC64-NEXT:    cfsd fa5, 64(ca0)
-; CHECK-IL32PC64-NEXT:    cincoffset csp, csp, 16
+; CHECK-IL32PC64-NEXT:    cfsd fa5, 0(a0)
+; CHECK-IL32PC64-NEXT:    cfsd fa5, 64(a0)
+; CHECK-IL32PC64-NEXT:    cincoffset sp, sp, 16
 ; CHECK-IL32PC64-NEXT:    cret
 ;
 ; CHECK-IL32PC64D-LABEL: cap_fsd:
 ; CHECK-IL32PC64D:       # %bb.0:
 ; CHECK-IL32PC64D-NEXT:    fadd.d fa5, fa0, fa1
-; CHECK-IL32PC64D-NEXT:    cfsd fa5, 0(ca0)
-; CHECK-IL32PC64D-NEXT:    cfsd fa5, 64(ca0)
+; CHECK-IL32PC64D-NEXT:    cfsd fa5, 0(a0)
+; CHECK-IL32PC64D-NEXT:    cfsd fa5, 64(a0)
 ; CHECK-IL32PC64D-NEXT:    cret
 ;
 ; CHECK-LP64-LABEL: cap_fsd:
 ; CHECK-LP64:       # %bb.0:
 ; CHECK-LP64-NEXT:    fmv.d.x fa5, a2
 ; CHECK-LP64-NEXT:    fmv.d.x fa4, a1
-; CHECK-LP64-NEXT:    cincoffset ca1, ca0, 64
+; CHECK-LP64-NEXT:    cincoffset a1, a0, 64
 ; CHECK-LP64-NEXT:    fadd.d fa5, fa4, fa5
 ; CHECK-LP64-NEXT:    fmv.x.d a2, fa5
-; CHECK-LP64-NEXT:    sd.cap a2, (ca0)
-; CHECK-LP64-NEXT:    sd.cap a2, (ca1)
+; CHECK-LP64-NEXT:    sd.cap a2, (a0)
+; CHECK-LP64-NEXT:    sd.cap a2, (a1)
 ; CHECK-LP64-NEXT:    ret
 ;
 ; CHECK-LP64D-LABEL: cap_fsd:
 ; CHECK-LP64D:       # %bb.0:
 ; CHECK-LP64D-NEXT:    fadd.d fa5, fa0, fa1
 ; CHECK-LP64D-NEXT:    fmv.x.d a1, fa5
-; CHECK-LP64D-NEXT:    sd.cap a1, (ca0)
-; CHECK-LP64D-NEXT:    cincoffset ca0, ca0, 64
-; CHECK-LP64D-NEXT:    sd.cap a1, (ca0)
+; CHECK-LP64D-NEXT:    sd.cap a1, (a0)
+; CHECK-LP64D-NEXT:    cincoffset a0, a0, 64
+; CHECK-LP64D-NEXT:    sd.cap a1, (a0)
 ; CHECK-LP64D-NEXT:    ret
 ;
 ; CHECK-L64PC128-LABEL: cap_fsd:
@@ -439,15 +439,15 @@ define dso_local void @cap_fsd(double addrspace(200)* %a, double %b, double %c)
 ; CHECK-L64PC128-NEXT:    fmv.d.x fa5, a2
 ; CHECK-L64PC128-NEXT:    fmv.d.x fa4, a1
 ; CHECK-L64PC128-NEXT:    fadd.d fa5, fa4, fa5
-; CHECK-L64PC128-NEXT:    cfsd fa5, 0(ca0)
-; CHECK-L64PC128-NEXT:    cfsd fa5, 64(ca0)
+; CHECK-L64PC128-NEXT:    cfsd fa5, 0(a0)
+; CHECK-L64PC128-NEXT:    cfsd fa5, 64(a0)
 ; CHECK-L64PC128-NEXT:    cret
 ;
 ; CHECK-L64PC128D-LABEL: cap_fsd:
 ; CHECK-L64PC128D:       # %bb.0:
 ; CHECK-L64PC128D-NEXT:    fadd.d fa5, fa0, fa1
-; CHECK-L64PC128D-NEXT:    cfsd fa5, 0(ca0)
-; CHECK-L64PC128D-NEXT:    cfsd fa5, 64(ca0)
+; CHECK-L64PC128D-NEXT:    cfsd fa5, 0(a0)
+; CHECK-L64PC128D-NEXT:    cfsd fa5, 64(a0)
 ; CHECK-L64PC128D-NEXT:    cret
   %1 = fadd double %b, %c
   store double %1, double addrspace(200)* %a
diff --git a/llvm/test/CodeGen/RISCV/cheri/float-mem.ll b/llvm/test/CodeGen/RISCV/cheri/float-mem.ll
index eb327403624b8..93fe03a488e1d 100644
--- a/llvm/test/CodeGen/RISCV/cheri/float-mem.ll
+++ b/llvm/test/CodeGen/RISCV/cheri/float-mem.ll
@@ -1,15 +1,15 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -target-abi ilp32 -mattr=+f,+xcheri,-cap-mode -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -target-abi ilp32 -mattr=+f,+xcheri,-xcheripurecap -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=CHECK-ILP32 %s
-; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+f,+xcheri,-cap-mode -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+f,+xcheri,-xcheripurecap -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=CHECK-ILP32F %s
 ; RUN: llc -mtriple=riscv32 -target-abi il32pc64 -mattr=+f,+xcheri,+xcheripurecap -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=CHECK-IL32PC64 %s
 ; RUN: llc -mtriple=riscv32 -target-abi il32pc64f -mattr=+f,+xcheri,+xcheripurecap -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=CHECK-IL32PC64F %s
-; RUN: llc -mtriple=riscv64 -target-abi lp64 -mattr=+f,+xcheri,-cap-mode -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -target-abi lp64 -mattr=+f,+xcheri,-xcheripurecap -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=CHECK-LP64 %s
-; RUN: llc -mtriple=riscv64 -target-abi lp64f -mattr=+f,+xcheri,-cap-mode -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -target-abi lp64f -mattr=+f,+xcheri,-xcheripurecap -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=CHECK-LP64F %s
 ; RUN: llc -mtriple=riscv64 -target-abi l64pc128 -mattr=+f,+xcheri,+xcheripurecap -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=CHECK-L64PC128 %s
@@ -183,9 +183,9 @@ define dso_local void @ddc_fsw(float* %a, float %b, float %c) nounwind {
 define dso_local float @cap_flw(float addrspace(200)* %a) nounwind {
 ; CHECK-ILP32-LABEL: cap_flw:
 ; CHECK-ILP32:       # %bb.0:
-; CHECK-ILP32-NEXT:    lw.cap a1, (ca0)
-; CHECK-ILP32-NEXT:    cincoffset ca0, ca0, 12
-; CHECK-ILP32-NEXT:    lw.cap a0, (ca0)
+; CHECK-ILP32-NEXT:    lw.cap a1, (a0)
+; CHECK-ILP32-NEXT:    cincoffset a0, a0, 12
+; CHECK-ILP32-NEXT:    lw.cap a0, (a0)
 ; CHECK-ILP32-NEXT:    fmv.w.x fa5, a1
 ; CHECK-ILP32-NEXT:    fmv.w.x fa4, a0
 ; CHECK-ILP32-NEXT:    fadd.s fa5, fa5, fa4
@@ -194,9 +194,9 @@ define dso_local float @cap_flw(float addrspace(200)* %a) nounwind {
 ;
 ; CHECK-ILP32F-LABEL: cap_flw:
 ; CHECK-ILP32F:       # %bb.0:
-; CHECK-ILP32F-NEXT:    lw.cap a1, (ca0)
-; CHECK-ILP32F-NEXT:    cincoffset ca0, ca0, 12
-; CHECK-ILP32F-NEXT:    lw.cap a0, (ca0)
+; CHECK-ILP32F-NEXT:    lw.cap a1, (a0)
+; CHECK-ILP32F-NEXT:    cincoffset a0, a0, 12
+; CHECK-ILP32F-NEXT:    lw.cap a0, (a0)
 ; CHECK-ILP32F-NEXT:    fmv.w.x fa5, a1
 ; CHECK-ILP32F-NEXT:    fmv.w.x fa4, a0
 ; CHECK-ILP32F-NEXT:    fadd.s fa0, fa5, fa4
@@ -204,24 +204,24 @@ define dso_local float @cap_flw(float addrspace(200)* %a) nounwind {
 ;
 ; CHECK-IL32PC64-LABEL: cap_flw:
 ; CHECK-IL32PC64:       # %bb.0:
-; CHECK-IL32PC64-NEXT:    cflw fa5, 0(ca0)
-; CHECK-IL32PC64-NEXT:    cflw fa4, 12(ca0)
+; CHECK-IL32PC64-NEXT:    cflw fa5, 0(a0)
+; CHECK-IL32PC64-NEXT:    cflw fa4, 12(a0)
 ; CHECK-IL32PC64-NEXT:    fadd.s fa5, fa5, fa4
 ; CHECK-IL32PC64-NEXT:    fmv.x.w a0, fa5
 ; CHECK-IL32PC64-NEXT:    cret
 ;
 ; CHECK-IL32PC64F-LABEL: cap_flw:
 ; CHECK-IL32PC64F:       # %bb.0:
-; CHECK-IL32PC64F-NEXT:    cflw fa5, 0(ca0)
-; CHECK-IL32PC64F-NEXT:    cflw fa4, 12(ca0)
+; CHECK-IL32PC64F-NEXT:    cflw fa5, 0(a0)
+; CHECK-IL32PC64F-NEXT:    cflw fa4, 12(a0)
 ; CHECK-IL32PC64F-NEXT:    fadd.s fa0, fa5, fa4
 ; CHECK-IL32PC64F-NEXT:    cret
 ;
 ; CHECK-LP64-LABEL: cap_flw:
 ; CHECK-LP64:       # %bb.0:
-; CHECK-LP64-NEXT:    lw.cap a1, (ca0)
-; CHECK-LP64-NEXT:    cincoffset ca0, ca0, 12
-; CHECK-LP64-NEXT:    lw.cap a0, (ca0)
+; CHECK-LP64-NEXT:    lw.cap a1, (a0)
+; CHECK-LP64-NEXT:    cincoffset a0, a0, 12
+; CHECK-LP64-NEXT:    lw.cap a0, (a0)
 ; CHECK-LP64-NEXT:    fmv.w.x fa5, a1
 ; CHECK-LP64-NEXT:    fmv.w.x fa4, a0
 ; CHECK-LP64-NEXT:    fadd.s fa5, fa5, fa4
@@ -230,9 +230,9 @@ define dso_local float @cap_flw(float addrspace(200)* %a) nounwind {
 ;
 ; CHECK-LP64F-LABEL: cap_flw:
 ; CHECK-LP64F:       # %bb.0:
-; CHECK-LP64F-NEXT:    lw.cap a1, (ca0)
-; CHECK-LP64F-NEXT:    cincoffset ca0, ca0, 12
-; CHECK-LP64F-NEXT:    lw.cap a0, (ca0)
+; CHECK-LP64F-NEXT:    lw.cap a1, (a0)
+; CHECK-LP64F-NEXT:    cincoffset a0, a0, 12
+; CHECK-LP64F-NEXT:    lw.cap a0, (a0)
 ; CHECK-LP64F-NEXT:    fmv.w.x fa5, a1
 ; CHECK-LP64F-NEXT:    fmv.w.x fa4, a0
 ; CHECK-LP64F-NEXT:    fadd.s fa0, fa5, fa4
@@ -240,16 +240,16 @@ define dso_local float @cap_flw(float addrspace(200)* %a) nounwind {
 ;
 ; CHECK-L64PC128-LABEL: cap_flw:
 ; CHECK-L64PC128:       # %bb.0:
-; CHECK-L64PC128-NEXT:    cflw fa5, 0(ca0)
-; CHECK-L64PC128-NEXT:    cflw fa4, 12(ca0)
+; CHECK-L64PC128-NEXT:    cflw fa5, 0(a0)
+; CHECK-L64PC128-NEXT:    cflw fa4, 12(a0)
 ; CHECK-L64PC128-NEXT:    fadd.s fa5, fa5, fa4
 ; CHECK-L64PC128-NEXT:    fmv.x.w a0, fa5
 ; CHECK-L64PC128-NEXT:    cret
 ;
 ; CHECK-L64PC128F-LABEL: cap_flw:
 ; CHECK-L64PC128F:       # %bb.0:
-; CHECK-L64PC128F-NEXT:    cflw fa5, 0(ca0)
-; CHECK-L64PC128F-NEXT:    cflw fa4, 12(ca0)
+; CHECK-L64PC128F-NEXT:    cflw fa5, 0(a0)
+; CHECK-L64PC128F-NEXT:    cflw fa4, 12(a0)
 ; CHECK-L64PC128F-NEXT:    fadd.s fa0, fa5, fa4
 ; CHECK-L64PC128F-NEXT:    cret
   %1 = load float, float addrspace(200)* %a
@@ -266,20 +266,20 @@ define dso_local void @cap_fsw(float addrspace(200)* %a, float %b, float %c) nou
 ; CHECK-ILP32:       # %bb.0:
 ; CHECK-ILP32-NEXT:    fmv.w.x fa5, a2
 ; CHECK-ILP32-NEXT:    fmv.w.x fa4, a1
-; CHECK-ILP32-NEXT:    cincoffset ca1, ca0, 32
+; CHECK-ILP32-NEXT:    cincoffset a1, a0, 32
 ; CHECK-ILP32-NEXT:    fadd.s fa5, fa4, fa5
 ; CHECK-ILP32-NEXT:    fmv.x.w a2, fa5
-; CHECK-ILP32-NEXT:    sw.cap a2, (ca0)
-; CHECK-ILP32-NEXT:    sw.cap a2, (ca1)
+; CHECK-ILP32-NEXT:    sw.cap a2, (a0)
+; CHECK-ILP32-NEXT:    sw.cap a2, (a1)
 ; CHECK-ILP32-NEXT:    ret
 ;
 ; CHECK-ILP32F-LABEL: cap_fsw:
 ; CHECK-ILP32F:       # %bb.0:
 ; CHECK-ILP32F-NEXT:    fadd.s fa5, fa0, fa1
 ; CHECK-ILP32F-NEXT:    fmv.x.w a1, fa5
-; CHECK-ILP32F-NEXT:    sw.cap a1, (ca0)
-; CHECK-ILP32F-NEXT:    cincoffset ca0, ca0, 32
-; CHECK-ILP32F-NEXT:    sw.cap a1, (ca0)
+; CHECK-ILP32F-NEXT:    sw.cap a1, (a0)
+; CHECK-ILP32F-NEXT:    cincoffset a0, a0, 32
+; CHECK-ILP32F-NEXT:    sw.cap a1, (a0)
 ; CHECK-ILP32F-NEXT:    ret
 ;
 ; CHECK-IL32PC64-LABEL: cap_fsw:
@@ -287,35 +287,35 @@ define dso_local void @cap_fsw(float addrspace(200)* %a, float %b, float %c) nou
 ; CHECK-IL32PC64-NEXT:    fmv.w.x fa5, a2
 ; CHECK-IL32PC64-NEXT:    fmv.w.x fa4, a1
 ; CHECK-IL32PC64-NEXT:    fadd.s fa5, fa4, fa5
-; CHECK-IL32PC64-NEXT:    cfsw fa5, 0(ca0)
-; CHECK-IL32PC64-NEXT:    cfsw fa5, 32(ca0)
+; CHECK-IL32PC64-NEXT:    cfsw fa5, 0(a0)
+; CHECK-IL32PC64-NEXT:    cfsw fa5, 32(a0)
 ; CHECK-IL32PC64-NEXT:    cret
 ;
 ; CHECK-IL32PC64F-LABEL: cap_fsw:
 ; CHECK-IL32PC64F:       # %bb.0:
 ; CHECK-IL32PC64F-NEXT:    fadd.s fa5, fa0, fa1
-; CHECK-IL32PC64F-NEXT:    cfsw fa5, 0(ca0)
-; CHECK-IL32PC64F-NEXT:    cfsw fa5, 32(ca0)
+; CHECK-IL32PC64F-NEXT:    cfsw fa5, 0(a0)
+; CHECK-IL32PC64F-NEXT:    cfsw fa5, 32(a0)
 ; CHECK-IL32PC64F-NEXT:    cret
 ;
 ; CHECK-LP64-LABEL: cap_fsw:
 ; CHECK-LP64:       # %bb.0:
 ; CHECK-LP64-NEXT:    fmv.w.x fa5, a2
 ; CHECK-LP64-NEXT:    fmv.w.x fa4, a1
-; CHECK-LP64-NEXT:    cincoffset ca1, ca0, 32
+; CHECK-LP64-NEXT:    cincoffset a1, a0, 32
 ; CHECK-LP64-NEXT:    fadd.s fa5, fa4, fa5
 ; CHECK-LP64-NEXT:    fmv.x.w a2, fa5
-; CHECK-LP64-NEXT:    sw.cap a2, (ca0)
-; CHECK-LP64-NEXT:    sw.cap a2, (ca1)
+; CHECK-LP64-NEXT:    sw.cap a2, (a0)
+; CHECK-LP64-NEXT:    sw.cap a2, (a1)
 ; CHECK-LP64-NEXT:    ret
 ;
 ; CHECK-LP64F-LABEL: cap_fsw:
 ; CHECK-LP64F:       # %bb.0:
 ; CHECK-LP64F-NEXT:    fadd.s fa5, fa0, fa1
 ; CHECK-LP64F-NEXT:    fmv.x.w a1, fa5
-; CHECK-LP64F-NEXT:    sw.cap a1, (ca0)
-; CHECK-LP64F-NEXT:    cincoffset ca0, ca0, 32
-; CHECK-LP64F-NEXT:    sw.cap a1, (ca0)
+; CHECK-LP64F-NEXT:    sw.cap a1, (a0)
+; CHECK-LP64F-NEXT:    cincoffset a0, a0, 32
+; CHECK-LP64F-NEXT:    sw.cap a1, (a0)
 ; CHECK-LP64F-NEXT:    ret
 ;
 ; CHECK-L64PC128-LABEL: cap_fsw:
@@ -323,15 +323,15 @@ define dso_local void @cap_fsw(float addrspace(200)* %a, float %b, float %c) nou
 ; CHECK-L64PC128-NEXT:    fmv.w.x fa5, a2
 ; CHECK-L64PC128-NEXT:    fmv.w.x fa4, a1
 ; CHECK-L64PC128-NEXT:    fadd.s fa5, fa4, fa5
-; CHECK-L64PC128-NEXT:    cfsw fa5, 0(ca0)
-; CHECK-L64PC128-NEXT:    cfsw fa5, 32(ca0)
+; CHECK-L64PC128-NEXT:    cfsw fa5, 0(a0)
+; CHECK-L64PC128-NEXT:    cfsw fa5, 32(a0)
 ; CHECK-L64PC128-NEXT:    cret
 ;
 ; CHECK-L64PC128F-LABEL: cap_fsw:
 ; CHECK-L64PC128F:       # %bb.0:
 ; CHECK-L64PC128F-NEXT:    fadd.s fa5, fa0, fa1
-; CHECK-L64PC128F-NEXT:    cfsw fa5, 0(ca0)
-; CHECK-L64PC128F-NEXT:    cfsw fa5, 32(ca0)
+; CHECK-L64PC128F-NEXT:    cfsw fa5, 0(a0)
+; CHECK-L64PC128F-NEXT:    cfsw fa5, 32(a0)
 ; CHECK-L64PC128F-NEXT:    cret
   %1 = fadd float %b, %c
   store float %1, float addrspace(200)* %a
diff --git a/llvm/test/CodeGen/RISCV/cheri/frameaddr-returnaddr.ll b/llvm/test/CodeGen/RISCV/cheri/frameaddr-returnaddr.ll
index 8c89d5f813cee..d0de539f19626 100644
--- a/llvm/test/CodeGen/RISCV/cheri/frameaddr-returnaddr.ll
+++ b/llvm/test/CodeGen/RISCV/cheri/frameaddr-returnaddr.ll
@@ -11,26 +11,26 @@ declare i8 addrspace(200)* @llvm.returnaddress(i32)
 define i8 addrspace(200)* @test_frameaddress_0() nounwind {
 ; RV32IXCHERI-LABEL: test_frameaddress_0:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 0(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    cincoffset cs0, csp, 16
-; RV32IXCHERI-NEXT:    cmove ca0, cs0
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 0(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 0(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset s0, sp, 16
+; RV32IXCHERI-NEXT:    cmove a0, s0
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 0(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: test_frameaddress_0:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -32
-; RV64IXCHERI-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 0(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    cincoffset cs0, csp, 32
-; RV64IXCHERI-NEXT:    cmove ca0, cs0
-; RV64IXCHERI-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 32
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -32
+; RV64IXCHERI-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 0(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset s0, sp, 32
+; RV64IXCHERI-NEXT:    cmove a0, s0
+; RV64IXCHERI-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 32
 ; RV64IXCHERI-NEXT:    cret
   %1 = call i8 addrspace(200)* @llvm.frameaddress(i32 0)
   ret i8 addrspace(200)* %1
@@ -39,32 +39,32 @@ define i8 addrspace(200)* @test_frameaddress_0() nounwind {
 define i8 addrspace(200)* @test_frameaddress_0_alloca() nounwind {
 ; RV32IXCHERI-LABEL: test_frameaddress_0_alloca:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -128
-; RV32IXCHERI-NEXT:    csc cra, 120(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 112(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    cincoffset cs0, csp, 128
-; RV32IXCHERI-NEXT:    cincoffset ca0, cs0, -120
-; RV32IXCHERI-NEXT:    csetbounds ca0, ca0, 104
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -128
+; RV32IXCHERI-NEXT:    csc ra, 120(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 112(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset s0, sp, 128
+; RV32IXCHERI-NEXT:    cincoffset a0, s0, -120
+; RV32IXCHERI-NEXT:    csetbounds a0, a0, 104
 ; RV32IXCHERI-NEXT:    ccall notdead
-; RV32IXCHERI-NEXT:    cmove ca0, cs0
-; RV32IXCHERI-NEXT:    clc cra, 120(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 112(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 128
+; RV32IXCHERI-NEXT:    cmove a0, s0
+; RV32IXCHERI-NEXT:    clc ra, 120(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 112(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 128
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: test_frameaddress_0_alloca:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -144
-; RV64IXCHERI-NEXT:    csc cra, 128(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 112(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    cincoffset cs0, csp, 144
-; RV64IXCHERI-NEXT:    cincoffset ca0, cs0, -132
-; RV64IXCHERI-NEXT:    csetbounds ca0, ca0, 100
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -144
+; RV64IXCHERI-NEXT:    csc ra, 128(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 112(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset s0, sp, 144
+; RV64IXCHERI-NEXT:    cincoffset a0, s0, -132
+; RV64IXCHERI-NEXT:    csetbounds a0, a0, 100
 ; RV64IXCHERI-NEXT:    ccall notdead
-; RV64IXCHERI-NEXT:    cmove ca0, cs0
-; RV64IXCHERI-NEXT:    clc cra, 128(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 112(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 144
+; RV64IXCHERI-NEXT:    cmove a0, s0
+; RV64IXCHERI-NEXT:    clc ra, 128(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 112(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 144
 ; RV64IXCHERI-NEXT:    cret
   %1 = alloca [100 x i8], addrspace(200)
   %2 = bitcast [100 x i8] addrspace(200)* %1 to i8 addrspace(200)*
@@ -76,28 +76,28 @@ define i8 addrspace(200)* @test_frameaddress_0_alloca() nounwind {
 define i8 addrspace(200)* @test_frameaddress_2() nounwind {
 ; RV32IXCHERI-LABEL: test_frameaddress_2:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 0(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    cincoffset cs0, csp, 16
-; RV32IXCHERI-NEXT:    clc ca0, -8(cs0)
-; RV32IXCHERI-NEXT:    clc ca0, -8(ca0)
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 0(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 0(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset s0, sp, 16
+; RV32IXCHERI-NEXT:    clc a0, -8(s0)
+; RV32IXCHERI-NEXT:    clc a0, -8(a0)
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 0(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: test_frameaddress_2:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -32
-; RV64IXCHERI-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 0(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    cincoffset cs0, csp, 32
-; RV64IXCHERI-NEXT:    clc ca0, -16(cs0)
-; RV64IXCHERI-NEXT:    clc ca0, -16(ca0)
-; RV64IXCHERI-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 32
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -32
+; RV64IXCHERI-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 0(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset s0, sp, 32
+; RV64IXCHERI-NEXT:    clc a0, -16(s0)
+; RV64IXCHERI-NEXT:    clc a0, -16(a0)
+; RV64IXCHERI-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 32
 ; RV64IXCHERI-NEXT:    cret
   %1 = call i8 addrspace(200)* @llvm.frameaddress(i32 2)
   ret i8 addrspace(200)* %1
@@ -106,36 +106,36 @@ define i8 addrspace(200)* @test_frameaddress_2() nounwind {
 define i8 addrspace(200)* @test_frameaddress_3_alloca() nounwind {
 ; RV32IXCHERI-LABEL: test_frameaddress_3_alloca:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -128
-; RV32IXCHERI-NEXT:    csc cra, 120(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 112(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    cincoffset cs0, csp, 128
-; RV32IXCHERI-NEXT:    cincoffset ca0, cs0, -120
-; RV32IXCHERI-NEXT:    csetbounds ca0, ca0, 104
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -128
+; RV32IXCHERI-NEXT:    csc ra, 120(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 112(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset s0, sp, 128
+; RV32IXCHERI-NEXT:    cincoffset a0, s0, -120
+; RV32IXCHERI-NEXT:    csetbounds a0, a0, 104
 ; RV32IXCHERI-NEXT:    ccall notdead
-; RV32IXCHERI-NEXT:    clc ca0, -8(cs0)
-; RV32IXCHERI-NEXT:    clc ca0, -8(ca0)
-; RV32IXCHERI-NEXT:    clc ca0, -8(ca0)
-; RV32IXCHERI-NEXT:    clc cra, 120(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 112(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 128
+; RV32IXCHERI-NEXT:    clc a0, -8(s0)
+; RV32IXCHERI-NEXT:    clc a0, -8(a0)
+; RV32IXCHERI-NEXT:    clc a0, -8(a0)
+; RV32IXCHERI-NEXT:    clc ra, 120(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 112(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 128
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: test_frameaddress_3_alloca:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -144
-; RV64IXCHERI-NEXT:    csc cra, 128(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 112(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    cincoffset cs0, csp, 144
-; RV64IXCHERI-NEXT:    cincoffset ca0, cs0, -132
-; RV64IXCHERI-NEXT:    csetbounds ca0, ca0, 100
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -144
+; RV64IXCHERI-NEXT:    csc ra, 128(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 112(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset s0, sp, 144
+; RV64IXCHERI-NEXT:    cincoffset a0, s0, -132
+; RV64IXCHERI-NEXT:    csetbounds a0, a0, 100
 ; RV64IXCHERI-NEXT:    ccall notdead
-; RV64IXCHERI-NEXT:    clc ca0, -16(cs0)
-; RV64IXCHERI-NEXT:    clc ca0, -16(ca0)
-; RV64IXCHERI-NEXT:    clc ca0, -16(ca0)
-; RV64IXCHERI-NEXT:    clc cra, 128(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 112(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 144
+; RV64IXCHERI-NEXT:    clc a0, -16(s0)
+; RV64IXCHERI-NEXT:    clc a0, -16(a0)
+; RV64IXCHERI-NEXT:    clc a0, -16(a0)
+; RV64IXCHERI-NEXT:    clc ra, 128(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 112(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 144
 ; RV64IXCHERI-NEXT:    cret
   %1 = alloca [100 x i8], addrspace(200)
   %2 = bitcast [100 x i8] addrspace(200)* %1 to i8 addrspace(200)*
@@ -147,12 +147,12 @@ define i8 addrspace(200)* @test_frameaddress_3_alloca() nounwind {
 define i8 addrspace(200)* @test_returnaddress_0() nounwind {
 ; RV32IXCHERI-LABEL: test_returnaddress_0:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cmove ca0, cra
+; RV32IXCHERI-NEXT:    cmove a0, ra
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: test_returnaddress_0:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cmove ca0, cra
+; RV64IXCHERI-NEXT:    cmove a0, ra
 ; RV64IXCHERI-NEXT:    cret
   %1 = call i8 addrspace(200)* @llvm.returnaddress(i32 0)
   ret i8 addrspace(200)* %1
@@ -161,32 +161,32 @@ define i8 addrspace(200)* @test_returnaddress_0() nounwind {
 define i8 addrspace(200)* @test_returnaddress_0_alloca() nounwind {
 ; RV32IXCHERI-LABEL: test_returnaddress_0_alloca:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -128
-; RV32IXCHERI-NEXT:    csc cra, 120(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 112(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    cmove cs0, cra
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 8
-; RV32IXCHERI-NEXT:    csetbounds ca0, ca0, 104
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -128
+; RV32IXCHERI-NEXT:    csc ra, 120(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 112(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cmove s0, ra
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 8
+; RV32IXCHERI-NEXT:    csetbounds a0, a0, 104
 ; RV32IXCHERI-NEXT:    ccall notdead
-; RV32IXCHERI-NEXT:    cmove ca0, cs0
-; RV32IXCHERI-NEXT:    clc cra, 120(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 112(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 128
+; RV32IXCHERI-NEXT:    cmove a0, s0
+; RV32IXCHERI-NEXT:    clc ra, 120(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 112(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 128
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: test_returnaddress_0_alloca:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -144
-; RV64IXCHERI-NEXT:    csc cra, 128(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 112(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    cmove cs0, cra
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 12
-; RV64IXCHERI-NEXT:    csetbounds ca0, ca0, 100
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -144
+; RV64IXCHERI-NEXT:    csc ra, 128(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 112(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cmove s0, ra
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 12
+; RV64IXCHERI-NEXT:    csetbounds a0, a0, 100
 ; RV64IXCHERI-NEXT:    ccall notdead
-; RV64IXCHERI-NEXT:    cmove ca0, cs0
-; RV64IXCHERI-NEXT:    clc cra, 128(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 112(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 144
+; RV64IXCHERI-NEXT:    cmove a0, s0
+; RV64IXCHERI-NEXT:    clc ra, 128(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 112(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 144
 ; RV64IXCHERI-NEXT:    cret
   %1 = alloca [100 x i8], addrspace(200)
   %2 = bitcast [100 x i8] addrspace(200)* %1 to i8 addrspace(200)*
@@ -198,30 +198,30 @@ define i8 addrspace(200)* @test_returnaddress_0_alloca() nounwind {
 define i8 addrspace(200)* @test_returnaddress_2() nounwind {
 ; RV32IXCHERI-LABEL: test_returnaddress_2:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 0(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    cincoffset cs0, csp, 16
-; RV32IXCHERI-NEXT:    clc ca0, -8(cs0)
-; RV32IXCHERI-NEXT:    clc ca0, -8(ca0)
-; RV32IXCHERI-NEXT:    clc ca0, -4(ca0)
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 0(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 0(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset s0, sp, 16
+; RV32IXCHERI-NEXT:    clc a0, -8(s0)
+; RV32IXCHERI-NEXT:    clc a0, -8(a0)
+; RV32IXCHERI-NEXT:    clc a0, -4(a0)
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 0(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: test_returnaddress_2:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -32
-; RV64IXCHERI-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 0(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    cincoffset cs0, csp, 32
-; RV64IXCHERI-NEXT:    clc ca0, -16(cs0)
-; RV64IXCHERI-NEXT:    clc ca0, -16(ca0)
-; RV64IXCHERI-NEXT:    clc ca0, -8(ca0)
-; RV64IXCHERI-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 32
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -32
+; RV64IXCHERI-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 0(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset s0, sp, 32
+; RV64IXCHERI-NEXT:    clc a0, -16(s0)
+; RV64IXCHERI-NEXT:    clc a0, -16(a0)
+; RV64IXCHERI-NEXT:    clc a0, -8(a0)
+; RV64IXCHERI-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 32
 ; RV64IXCHERI-NEXT:    cret
   %1 = call i8 addrspace(200)* @llvm.returnaddress(i32 2)
   ret i8 addrspace(200)* %1
@@ -230,38 +230,38 @@ define i8 addrspace(200)* @test_returnaddress_2() nounwind {
 define i8 addrspace(200)* @test_returnaddress_3_alloca() nounwind {
 ; RV32IXCHERI-LABEL: test_returnaddress_3_alloca:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -128
-; RV32IXCHERI-NEXT:    csc cra, 120(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 112(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    cincoffset cs0, csp, 128
-; RV32IXCHERI-NEXT:    cincoffset ca0, cs0, -120
-; RV32IXCHERI-NEXT:    csetbounds ca0, ca0, 104
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -128
+; RV32IXCHERI-NEXT:    csc ra, 120(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 112(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset s0, sp, 128
+; RV32IXCHERI-NEXT:    cincoffset a0, s0, -120
+; RV32IXCHERI-NEXT:    csetbounds a0, a0, 104
 ; RV32IXCHERI-NEXT:    ccall notdead
-; RV32IXCHERI-NEXT:    clc ca0, -8(cs0)
-; RV32IXCHERI-NEXT:    clc ca0, -8(ca0)
-; RV32IXCHERI-NEXT:    clc ca0, -8(ca0)
-; RV32IXCHERI-NEXT:    clc ca0, -4(ca0)
-; RV32IXCHERI-NEXT:    clc cra, 120(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 112(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 128
+; RV32IXCHERI-NEXT:    clc a0, -8(s0)
+; RV32IXCHERI-NEXT:    clc a0, -8(a0)
+; RV32IXCHERI-NEXT:    clc a0, -8(a0)
+; RV32IXCHERI-NEXT:    clc a0, -4(a0)
+; RV32IXCHERI-NEXT:    clc ra, 120(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 112(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 128
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: test_returnaddress_3_alloca:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -144
-; RV64IXCHERI-NEXT:    csc cra, 128(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 112(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    cincoffset cs0, csp, 144
-; RV64IXCHERI-NEXT:    cincoffset ca0, cs0, -132
-; RV64IXCHERI-NEXT:    csetbounds ca0, ca0, 100
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -144
+; RV64IXCHERI-NEXT:    csc ra, 128(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 112(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset s0, sp, 144
+; RV64IXCHERI-NEXT:    cincoffset a0, s0, -132
+; RV64IXCHERI-NEXT:    csetbounds a0, a0, 100
 ; RV64IXCHERI-NEXT:    ccall notdead
-; RV64IXCHERI-NEXT:    clc ca0, -16(cs0)
-; RV64IXCHERI-NEXT:    clc ca0, -16(ca0)
-; RV64IXCHERI-NEXT:    clc ca0, -16(ca0)
-; RV64IXCHERI-NEXT:    clc ca0, -8(ca0)
-; RV64IXCHERI-NEXT:    clc cra, 128(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 112(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 144
+; RV64IXCHERI-NEXT:    clc a0, -16(s0)
+; RV64IXCHERI-NEXT:    clc a0, -16(a0)
+; RV64IXCHERI-NEXT:    clc a0, -16(a0)
+; RV64IXCHERI-NEXT:    clc a0, -8(a0)
+; RV64IXCHERI-NEXT:    clc ra, 128(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 112(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 144
 ; RV64IXCHERI-NEXT:    cret
   %1 = alloca [100 x i8], addrspace(200)
   %2 = bitcast [100 x i8] addrspace(200)* %1 to i8 addrspace(200)*
diff --git a/llvm/test/CodeGen/RISCV/cheri/get-global-addr.ll b/llvm/test/CodeGen/RISCV/cheri/get-global-addr.ll
index 3fdbab30a998d..78434e9769dfb 100644
--- a/llvm/test/CodeGen/RISCV/cheri/get-global-addr.ll
+++ b/llvm/test/CodeGen/RISCV/cheri/get-global-addr.ll
@@ -12,9 +12,9 @@ define double @constant_pool(double %a) nounwind {
 ; L64PC128-LABEL: constant_pool:
 ; L64PC128:       # %bb.0:
 ; L64PC128-NEXT:  .LBB0_1: # Label of block must be emitted
-; L64PC128-NEXT:    auipcc ca0, %pcrel_hi(.LCPI0_0)
-; L64PC128-NEXT:    cincoffset ca0, ca0, %pcrel_lo(.LBB0_1)
-; L64PC128-NEXT:    cfld fa5, 0(ca0)
+; L64PC128-NEXT:    auipcc a0, %pcrel_hi(.LCPI0_0)
+; L64PC128-NEXT:    cincoffset a0, a0, %pcrel_lo(.LBB0_1)
+; L64PC128-NEXT:    cfld fa5, 0(a0)
 ; L64PC128-NEXT:    fadd.d fa0, fa0, fa5
 ; L64PC128-NEXT:    cret
   %1 = fadd double %a, 1.0
@@ -30,8 +30,8 @@ define i8 addrspace(200)* @blockaddress() nounwind {
 ; L64PC128-NEXT:  # %bb.1: # %block
 ; L64PC128-NEXT:  .LBB1_2: # %block
 ; L64PC128-NEXT:    # Label of block must be emitted
-; L64PC128-NEXT:    auipcc ca0, %pcrel_hi(.Ltmp0)
-; L64PC128-NEXT:    cincoffset ca0, ca0, %pcrel_lo(.LBB1_2)
+; L64PC128-NEXT:    auipcc a0, %pcrel_hi(.Ltmp0)
+; L64PC128-NEXT:    cincoffset a0, a0, %pcrel_lo(.LBB1_2)
 ; L64PC128-NEXT:    cret
 entry:
   br label %block
@@ -52,9 +52,9 @@ define i64 @load_external_global_variable(double %a) nounwind {
 ; L64PC128-LABEL: load_external_global_variable:
 ; L64PC128:       # %bb.0:
 ; L64PC128-NEXT:  .LBB2_1: # Label of block must be emitted
-; L64PC128-NEXT:    auipcc ca0, %captab_pcrel_hi(external_variable)
-; L64PC128-NEXT:    clc ca0, %pcrel_lo(.LBB2_1)(ca0)
-; L64PC128-NEXT:    cld a0, 0(ca0)
+; L64PC128-NEXT:    auipcc a0, %captab_pcrel_hi(external_variable)
+; L64PC128-NEXT:    clc a0, %pcrel_lo(.LBB2_1)(a0)
+; L64PC128-NEXT:    cld a0, 0(a0)
 ; L64PC128-NEXT:    cret
   %ret = load i64, i64 addrspace(200)* @external_variable
   ret i64 %ret
@@ -65,9 +65,9 @@ define i64 @load_external_global_constant(double %a) nounwind {
 ; L64PC128-LABEL: load_external_global_constant:
 ; L64PC128:       # %bb.0:
 ; L64PC128-NEXT:  .LBB3_1: # Label of block must be emitted
-; L64PC128-NEXT:    auipcc ca0, %captab_pcrel_hi(external_constant)
-; L64PC128-NEXT:    clc ca0, %pcrel_lo(.LBB3_1)(ca0)
-; L64PC128-NEXT:    cld a0, 0(ca0)
+; L64PC128-NEXT:    auipcc a0, %captab_pcrel_hi(external_constant)
+; L64PC128-NEXT:    clc a0, %pcrel_lo(.LBB3_1)(a0)
+; L64PC128-NEXT:    cld a0, 0(a0)
 ; L64PC128-NEXT:    cret
   %ret = load i64, i64 addrspace(200)* @external_constant
   ret i64 %ret
@@ -78,9 +78,9 @@ define i64 @load_dso_local_external_global_variable(double %a) nounwind {
 ; L64PC128-LABEL: load_dso_local_external_global_variable:
 ; L64PC128:       # %bb.0:
 ; L64PC128-NEXT:  .LBB4_1: # Label of block must be emitted
-; L64PC128-NEXT:    auipcc ca0, %captab_pcrel_hi(dso_local_external_variable)
-; L64PC128-NEXT:    clc ca0, %pcrel_lo(.LBB4_1)(ca0)
-; L64PC128-NEXT:    cld a0, 0(ca0)
+; L64PC128-NEXT:    auipcc a0, %captab_pcrel_hi(dso_local_external_variable)
+; L64PC128-NEXT:    clc a0, %pcrel_lo(.LBB4_1)(a0)
+; L64PC128-NEXT:    cld a0, 0(a0)
 ; L64PC128-NEXT:    cret
   %ret = load i64, i64 addrspace(200)* @dso_local_external_variable
   ret i64 %ret
@@ -92,9 +92,9 @@ define i64 @load_dso_local_external_global_constant(double %a) nounwind {
 ; L64PC128-LABEL: load_dso_local_external_global_constant:
 ; L64PC128:       # %bb.0:
 ; L64PC128-NEXT:  .LBB5_1: # Label of block must be emitted
-; L64PC128-NEXT:    auipcc ca0, %captab_pcrel_hi(dso_local_external_constant)
-; L64PC128-NEXT:    clc ca0, %pcrel_lo(.LBB5_1)(ca0)
-; L64PC128-NEXT:    cld a0, 0(ca0)
+; L64PC128-NEXT:    auipcc a0, %captab_pcrel_hi(dso_local_external_constant)
+; L64PC128-NEXT:    clc a0, %pcrel_lo(.LBB5_1)(a0)
+; L64PC128-NEXT:    cld a0, 0(a0)
 ; L64PC128-NEXT:    cret
   %ret = load i64, i64 addrspace(200)* @dso_local_external_constant
   ret i64 %ret
@@ -105,9 +105,9 @@ define i64 @load_defined_variable(double %a) nounwind {
 ; L64PC128-LABEL: load_defined_variable:
 ; L64PC128:       # %bb.0:
 ; L64PC128-NEXT:  .LBB6_1: # Label of block must be emitted
-; L64PC128-NEXT:    auipcc ca0, %captab_pcrel_hi(defined_variable)
-; L64PC128-NEXT:    clc ca0, %pcrel_lo(.LBB6_1)(ca0)
-; L64PC128-NEXT:    cld a0, 0(ca0)
+; L64PC128-NEXT:    auipcc a0, %captab_pcrel_hi(defined_variable)
+; L64PC128-NEXT:    clc a0, %pcrel_lo(.LBB6_1)(a0)
+; L64PC128-NEXT:    cld a0, 0(a0)
 ; L64PC128-NEXT:    cret
   %ret = load i64, i64 addrspace(200)* @defined_variable
   ret i64 %ret
@@ -118,9 +118,9 @@ define i64 @load_defined_constant(double %a) nounwind {
 ; L64PC128-LABEL: load_defined_constant:
 ; L64PC128:       # %bb.0:
 ; L64PC128-NEXT:  .LBB7_1: # Label of block must be emitted
-; L64PC128-NEXT:    auipcc ca0, %captab_pcrel_hi(defined_constant)
-; L64PC128-NEXT:    clc ca0, %pcrel_lo(.LBB7_1)(ca0)
-; L64PC128-NEXT:    cld a0, 0(ca0)
+; L64PC128-NEXT:    auipcc a0, %captab_pcrel_hi(defined_constant)
+; L64PC128-NEXT:    clc a0, %pcrel_lo(.LBB7_1)(a0)
+; L64PC128-NEXT:    cld a0, 0(a0)
 ; L64PC128-NEXT:    cret
   %ret = load i64, i64 addrspace(200)* @defined_constant
   ret i64 %ret
@@ -131,9 +131,9 @@ define i64 @load_hidden_variable(double %a) nounwind {
 ; L64PC128-LABEL: load_hidden_variable:
 ; L64PC128:       # %bb.0:
 ; L64PC128-NEXT:  .LBB8_1: # Label of block must be emitted
-; L64PC128-NEXT:    auipcc ca0, %captab_pcrel_hi(hidden_variable)
-; L64PC128-NEXT:    clc ca0, %pcrel_lo(.LBB8_1)(ca0)
-; L64PC128-NEXT:    cld a0, 0(ca0)
+; L64PC128-NEXT:    auipcc a0, %captab_pcrel_hi(hidden_variable)
+; L64PC128-NEXT:    clc a0, %pcrel_lo(.LBB8_1)(a0)
+; L64PC128-NEXT:    cld a0, 0(a0)
 ; L64PC128-NEXT:    cret
   %ret = load i64, i64 addrspace(200)* @hidden_variable
   ret i64 %ret
@@ -144,9 +144,9 @@ define i64 @load_hidden_constant(double %a) nounwind {
 ; L64PC128-LABEL: load_hidden_constant:
 ; L64PC128:       # %bb.0:
 ; L64PC128-NEXT:  .LBB9_1: # Label of block must be emitted
-; L64PC128-NEXT:    auipcc ca0, %captab_pcrel_hi(hidden_constant)
-; L64PC128-NEXT:    clc ca0, %pcrel_lo(.LBB9_1)(ca0)
-; L64PC128-NEXT:    cld a0, 0(ca0)
+; L64PC128-NEXT:    auipcc a0, %captab_pcrel_hi(hidden_constant)
+; L64PC128-NEXT:    clc a0, %pcrel_lo(.LBB9_1)(a0)
+; L64PC128-NEXT:    cld a0, 0(a0)
 ; L64PC128-NEXT:    cret
   %ret = load i64, i64 addrspace(200)* @hidden_constant
   ret i64 %ret
@@ -157,9 +157,9 @@ define i64 @load_dso_local_variable(double %a) nounwind {
 ; L64PC128-LABEL: load_dso_local_variable:
 ; L64PC128:       # %bb.0:
 ; L64PC128-NEXT:  .LBB10_1: # Label of block must be emitted
-; L64PC128-NEXT:    auipcc ca0, %captab_pcrel_hi(dso_local_variable)
-; L64PC128-NEXT:    clc ca0, %pcrel_lo(.LBB10_1)(ca0)
-; L64PC128-NEXT:    cld a0, 0(ca0)
+; L64PC128-NEXT:    auipcc a0, %captab_pcrel_hi(dso_local_variable)
+; L64PC128-NEXT:    clc a0, %pcrel_lo(.LBB10_1)(a0)
+; L64PC128-NEXT:    cld a0, 0(a0)
 ; L64PC128-NEXT:    cret
   %ret = load i64, i64 addrspace(200)* @dso_local_variable
   ret i64 %ret
@@ -170,9 +170,9 @@ define i64 @load_dso_local_constant(double %a) nounwind {
 ; L64PC128-LABEL: load_dso_local_constant:
 ; L64PC128:       # %bb.0:
 ; L64PC128-NEXT:  .LBB11_1: # Label of block must be emitted
-; L64PC128-NEXT:    auipcc ca0, %captab_pcrel_hi(dso_local_constant)
-; L64PC128-NEXT:    clc ca0, %pcrel_lo(.LBB11_1)(ca0)
-; L64PC128-NEXT:    cld a0, 0(ca0)
+; L64PC128-NEXT:    auipcc a0, %captab_pcrel_hi(dso_local_constant)
+; L64PC128-NEXT:    clc a0, %pcrel_lo(.LBB11_1)(a0)
+; L64PC128-NEXT:    cld a0, 0(a0)
 ; L64PC128-NEXT:    cret
   %ret = load i64, i64 addrspace(200)* @dso_local_constant
   ret i64 %ret
diff --git a/llvm/test/CodeGen/RISCV/cheri/global-cap-import-attributes.ll b/llvm/test/CodeGen/RISCV/cheri/global-cap-import-attributes.ll
index 41d732e2da10e..861241f30e2a1 100644
--- a/llvm/test/CodeGen/RISCV/cheri/global-cap-import-attributes.ll
+++ b/llvm/test/CodeGen/RISCV/cheri/global-cap-import-attributes.ll
@@ -11,111 +11,111 @@ define dso_local void @_Z7examplev() addrspace(200) #0 {
 entry:
 ; CHECK:        .LBB0_1:                                # %entry
 ; CHECK-NEXT:                                           # Label of block must be emitted
-; CHECK-NEXT:	        auipcc	ca0, %cheriot_compartment_hi("__import_mem_uart_-----")
-; CHECK-NEXT:	        clc	ca0, %cheriot_compartment_lo_i(.LBB0_1)(ca0)
+; CHECK-NEXT:	        auipcc	a0, %cheriot_compartment_hi("__import_mem_uart_-----")
+; CHECK-NEXT:	        clc	a0, %cheriot_compartment_lo_i(.LBB0_1)(a0)
 ; CHECK-NEXT:	        ccall	_Z19doSomethingWithUartP4Uart
   call void @_Z19doSomethingWithUartP4Uart(ptr addrspace(200) noundef @uart_no_perm)
 ; CHECK:        .LBB0_2:                                # %entry
 ; CHECK-NEXT:                                           # Label of block must be emitted
-; CHECK-NEXT:        	auipcc	ca0, %cheriot_compartment_hi("__import_mem_uart_--c--")
-; CHECK-NEXT:        	clc	ca0, %cheriot_compartment_lo_i(.LBB0_2)(ca0)
+; CHECK-NEXT:        	auipcc	a0, %cheriot_compartment_hi("__import_mem_uart_--c--")
+; CHECK-NEXT:        	clc	a0, %cheriot_compartment_lo_i(.LBB0_2)(a0)
 ; CHECK-NEXT:        	ccall	_Z19doSomethingWithUartP4Uart
   call void @_Z19doSomethingWithUartP4Uart(ptr addrspace(200) noundef @uart_c)
 ; CHECK:        .LBB0_3:                                # %entry
 ; CHECK-NEXT:                                           # Label of block must be emitted
-; CHECK-NEXT:        	auipcc	ca0, %cheriot_compartment_hi("__import_mem_uart_---m-")
-; CHECK-NEXT:        	clc	ca0, %cheriot_compartment_lo_i(.LBB0_3)(ca0)
+; CHECK-NEXT:        	auipcc	a0, %cheriot_compartment_hi("__import_mem_uart_---m-")
+; CHECK-NEXT:        	clc	a0, %cheriot_compartment_lo_i(.LBB0_3)(a0)
 ; CHECK-NEXT:        	ccall	_Z19doSomethingWithUartP4Uart
   call void @_Z19doSomethingWithUartP4Uart(ptr addrspace(200) noundef @uart_m)
 
 ; CHECK:        .LBB0_4:                                # %entry
 ; CHECK-NEXT:                                           # Label of block must be emitted
-; CHECK-NEXT:        	auipcc	ca0, %cheriot_compartment_hi("__import_mem_uart_----g")
-; CHECK-NEXT:        	clc	ca0, %cheriot_compartment_lo_i(.LBB0_4)(ca0)
+; CHECK-NEXT:        	auipcc	a0, %cheriot_compartment_hi("__import_mem_uart_----g")
+; CHECK-NEXT:        	clc	a0, %cheriot_compartment_lo_i(.LBB0_4)(a0)
 ; CHECK-NEXT:        	ccall	_Z19doSomethingWithUartP4Uart
   call void @_Z19doSomethingWithUartP4Uart(ptr addrspace(200) noundef @uart_g)
 
 ; CHECK:        .LBB0_5:                                # %entry
 ; CHECK-NEXT:                                           # Label of block must be emitted
-; CHECK-NEXT:        	auipcc	ca0, %cheriot_compartment_hi("__import_mem_uart_--cm-")
-; CHECK-NEXT:        	clc	ca0, %cheriot_compartment_lo_i(.LBB0_5)(ca0)
+; CHECK-NEXT:        	auipcc	a0, %cheriot_compartment_hi("__import_mem_uart_--cm-")
+; CHECK-NEXT:        	clc	a0, %cheriot_compartment_lo_i(.LBB0_5)(a0)
 ; CHECK-NEXT:        	ccall	_Z19doSomethingWithUartP4Uart
   call void @_Z19doSomethingWithUartP4Uart(ptr addrspace(200) noundef @uart_cm)
 
 ; CHECK:        .LBB0_6:                                # %entry
 ; CHECK-NEXT:                                           # Label of block must be emitted
-; CHECK-NEXT:        	auipcc	ca0, %cheriot_compartment_hi("__import_mem_uart_-W---")
-; CHECK-NEXT:        	clc	ca0, %cheriot_compartment_lo_i(.LBB0_6)(ca0)
+; CHECK-NEXT:        	auipcc	a0, %cheriot_compartment_hi("__import_mem_uart_-W---")
+; CHECK-NEXT:        	clc	a0, %cheriot_compartment_lo_i(.LBB0_6)(a0)
 ; CHECK-NEXT:        	ccall	_Z19doSomethingWithUartP4Uart
   call void @_Z19doSomethingWithUartP4Uart(ptr addrspace(200) noundef @uart_W)
 
 ; CHECK:        .LBB0_7:                                # %entry
 ; CHECK-NEXT:                                           # Label of block must be emitted
-; CHECK-NEXT:        	auipcc	ca0, %cheriot_compartment_hi("__import_mem_uart_-Wc--")
-; CHECK-NEXT:        	clc	ca0, %cheriot_compartment_lo_i(.LBB0_7)(ca0)
+; CHECK-NEXT:        	auipcc	a0, %cheriot_compartment_hi("__import_mem_uart_-Wc--")
+; CHECK-NEXT:        	clc	a0, %cheriot_compartment_lo_i(.LBB0_7)(a0)
 ; CHECK-NEXT:        	ccall	_Z19doSomethingWithUartP4Uart
   call void @_Z19doSomethingWithUartP4Uart(ptr addrspace(200) noundef @uart_Wc)
 
 ; CHECK:        .LBB0_8:                                # %entry
 ; CHECK-NEXT:                                           # Label of block must be emitted
-; CHECK-NEXT:        	auipcc	ca0, %cheriot_compartment_hi("__import_mem_uart_-W-m-")
-; CHECK-NEXT:        	clc	ca0, %cheriot_compartment_lo_i(.LBB0_8)(ca0)
+; CHECK-NEXT:        	auipcc	a0, %cheriot_compartment_hi("__import_mem_uart_-W-m-")
+; CHECK-NEXT:        	clc	a0, %cheriot_compartment_lo_i(.LBB0_8)(a0)
 ; CHECK-NEXT:        	ccall	_Z19doSomethingWithUartP4Uart
   call void @_Z19doSomethingWithUartP4Uart(ptr addrspace(200) noundef @uart_Wm)
 
 ; CHECK:        .LBB0_9:                                # %entry
 ; CHECK-NEXT:                                           # Label of block must be emitted
-; CHECK-NEXT:        	auipcc	ca0, %cheriot_compartment_hi("__import_mem_uart_-Wcm-")
-; CHECK-NEXT:        	clc	ca0, %cheriot_compartment_lo_i(.LBB0_9)(ca0)
+; CHECK-NEXT:        	auipcc	a0, %cheriot_compartment_hi("__import_mem_uart_-Wcm-")
+; CHECK-NEXT:        	clc	a0, %cheriot_compartment_lo_i(.LBB0_9)(a0)
 ; CHECK-NEXT:        	ccall	_Z19doSomethingWithUartP4Uart
   call void @_Z19doSomethingWithUartP4Uart(ptr addrspace(200) noundef @uart_Wcm)
 
 ; CHECK:        .LBB0_10:                                # %entry
 ; CHECK-NEXT:                                           # Label of block must be emitted
-; CHECK-NEXT:        	auipcc	ca0, %cheriot_compartment_hi("__import_mem_uart_R----")
-; CHECK-NEXT:        	clc	ca0, %cheriot_compartment_lo_i(.LBB0_10)(ca0)
+; CHECK-NEXT:        	auipcc	a0, %cheriot_compartment_hi("__import_mem_uart_R----")
+; CHECK-NEXT:        	clc	a0, %cheriot_compartment_lo_i(.LBB0_10)(a0)
 ; CHECK-NEXT:        	ccall	_Z19doSomethingWithUartP4Uart
   call void @_Z19doSomethingWithUartP4Uart(ptr addrspace(200) noundef @uart_R)
 
 ; CHECK:        .LBB0_11:                               # %entry
 ; CHECK-NEXT:                                           # Label of block must be emitted
-; CHECK-NEXT:        	auipcc	ca0, %cheriot_compartment_hi("__import_mem_uart_R-c--")
-; CHECK-NEXT:        	clc	ca0, %cheriot_compartment_lo_i(.LBB0_11)(ca0)
+; CHECK-NEXT:        	auipcc	a0, %cheriot_compartment_hi("__import_mem_uart_R-c--")
+; CHECK-NEXT:        	clc	a0, %cheriot_compartment_lo_i(.LBB0_11)(a0)
 ; CHECK-NEXT:        	ccall	_Z19doSomethingWithUartP4Uart
   call void @_Z19doSomethingWithUartP4Uart(ptr addrspace(200) noundef @uart_Rc)
 
 ; CHECK:        .LBB0_12:                               # %entry
 ; CHECK-NEXT:                                           # Label of block must be emitted
-; CHECK-NEXT:        	auipcc	ca0, %cheriot_compartment_hi("__import_mem_uart_R--m-")
-; CHECK-NEXT:        	clc	ca0, %cheriot_compartment_lo_i(.LBB0_12)(ca0)
+; CHECK-NEXT:        	auipcc	a0, %cheriot_compartment_hi("__import_mem_uart_R--m-")
+; CHECK-NEXT:        	clc	a0, %cheriot_compartment_lo_i(.LBB0_12)(a0)
 ; CHECK-NEXT:        	ccall	_Z19doSomethingWithUartP4Uart
   call void @_Z19doSomethingWithUartP4Uart(ptr addrspace(200) noundef @uart_Rm)
 
 ; CHECK:        .LBB0_13:                               # %entry
 ; CHECK-NEXT:                                           # Label of block must be emitted
-; CHECK-NEXT:        	auipcc	ca0, %cheriot_compartment_hi("__import_mem_uart_R-cm-")
-; CHECK-NEXT:        	clc	ca0, %cheriot_compartment_lo_i(.LBB0_13)(ca0)
+; CHECK-NEXT:        	auipcc	a0, %cheriot_compartment_hi("__import_mem_uart_R-cm-")
+; CHECK-NEXT:        	clc	a0, %cheriot_compartment_lo_i(.LBB0_13)(a0)
 ; CHECK-NEXT:        	ccall	_Z19doSomethingWithUartP4Uart
   call void @_Z19doSomethingWithUartP4Uart(ptr addrspace(200) noundef @uart_Rcm)
 
 ; CHECK:        .LBB0_14:                               # %entry
 ; CHECK-NEXT:                                           # Label of block must be emitted
-; CHECK-NEXT:        	auipcc	ca0, %cheriot_compartment_hi("__import_mem_uart_RW---")
-; CHECK-NEXT:        	clc	ca0, %cheriot_compartment_lo_i(.LBB0_14)(ca0)
+; CHECK-NEXT:        	auipcc	a0, %cheriot_compartment_hi("__import_mem_uart_RW---")
+; CHECK-NEXT:        	clc	a0, %cheriot_compartment_lo_i(.LBB0_14)(a0)
 ; CHECK-NEXT:        	ccall	_Z19doSomethingWithUartP4Uart
   call void @_Z19doSomethingWithUartP4Uart(ptr addrspace(200) noundef @uart_RW)
 
 ; CHECK:        .LBB0_15:                               # %entry
 ; CHECK-NEXT:                                           # Label of block must be emitted
-; CHECK-NEXT:        	auipcc	ca0, %cheriot_compartment_hi("__import_mem_uart_RWc--")
-; CHECK-NEXT:        	clc	ca0, %cheriot_compartment_lo_i(.LBB0_15)(ca0)
+; CHECK-NEXT:        	auipcc	a0, %cheriot_compartment_hi("__import_mem_uart_RWc--")
+; CHECK-NEXT:        	clc	a0, %cheriot_compartment_lo_i(.LBB0_15)(a0)
 ; CHECK-NEXT:        	ccall	_Z19doSomethingWithUartP4Uart
   call void @_Z19doSomethingWithUartP4Uart(ptr addrspace(200) noundef @uart_RWc)
 
 ; CHECK:        .LBB0_16:                               # %entry
 ; CHECK-NEXT:                                           # Label of block must be emitted
-; CHECK-NEXT:        	auipcc	ca0, %cheriot_compartment_hi("__import_mem_uart_RW-m-")
-; CHECK-NEXT:        	clc	ca0, %cheriot_compartment_lo_i(.LBB0_16)(ca0)
+; CHECK-NEXT:        	auipcc	a0, %cheriot_compartment_hi("__import_mem_uart_RW-m-")
+; CHECK-NEXT:        	clc	a0, %cheriot_compartment_lo_i(.LBB0_16)(a0)
 ; CHECK-NEXT:        	ccall	_Z19doSomethingWithUartP4Uart
   call void @_Z19doSomethingWithUartP4Uart(ptr addrspace(200) noundef @uart_RWm)
 
@@ -124,25 +124,25 @@ entry:
 
 ; CHECK:        .LBB0_17:                               # %entry
 ; CHECK-NEXT:                                           # Label of block must be emitted
-; CHECK-NEXT:        	auipcc	cs1, %cheriot_compartment_hi("__import_mem_uart_RWcm-")
-; CHECK-NEXT:        	clc	cs1, %cheriot_compartment_lo_i(.LBB0_17)(cs1)
-; CHECK-NEXT:        	cmove	ca0, cs1
+; CHECK-NEXT:        	auipcc	s1, %cheriot_compartment_hi("__import_mem_uart_RWcm-")
+; CHECK-NEXT:        	clc	s1, %cheriot_compartment_lo_i(.LBB0_17)(s1)
+; CHECK-NEXT:        	cmove	a0, s1
 ; CHECK-NEXT:        	ccall	_Z19doSomethingWithUartP4Uart
   call void @_Z19doSomethingWithUartP4Uart(ptr addrspace(200) noundef @uart_RWcm)
 
-; CHECK-NEXT:        	cmove   ca0, cs1
+; CHECK-NEXT:        	cmove   a0, s1
 ; CHECK-NEXT:        	ccall	_Z19doSomethingWithUartP4Uart
   call void @_Z19doSomethingWithUartP4Uart(ptr addrspace(200) noundef @uart_RWcm)
 
-; CHECK-NEXT:        	cmove	ca0, cs1
+; CHECK-NEXT:        	cmove	a0, s1
 ; CHECK-NEXT:        	ccall	_Z19doSomethingWithUartP4Uart
   call void @_Z19doSomethingWithUartP4Uart(ptr addrspace(200) noundef @uart_RWcm)
 
-; CHECK-NEXT:        	cmove	ca0, cs1
+; CHECK-NEXT:        	cmove	a0, s1
 ; CHECK-NEXT:        	ccall	_Z19doSomethingWithUartP4Uart
   call void @_Z19doSomethingWithUartP4Uart(ptr addrspace(200) noundef @uart_RWcm)
 
-; CHECK-NEXT:        	cmove	ca0, cs1
+; CHECK-NEXT:        	cmove	a0, s1
 ; CHECK-NEXT:        	ccall	_Z19doSomethingWithUartP4Uart
   call void @_Z19doSomethingWithUartP4Uart(ptr addrspace(200) noundef @uart_RWcm)
 
@@ -150,34 +150,34 @@ entry:
 
 ; CHECK:        .LBB0_18:                               # %entry
 ; CHECK-NEXT:                                           # Label of block must be emitted
-; CHECK-NEXT:        	auipcc	cs1, %cheriot_compartment_hi("__import_mem_uart_RWcm-")
-; CHECK-NEXT:        	clc	cs1, %cheriot_compartment_lo_i(.LBB0_18)(cs1)
-; CHECK-NEXT:           cmove	ca0, cs1
+; CHECK-NEXT:        	auipcc	s1, %cheriot_compartment_hi("__import_mem_uart_RWcm-")
+; CHECK-NEXT:        	clc	s1, %cheriot_compartment_lo_i(.LBB0_18)(s1)
+; CHECK-NEXT:           cmove	a0, s1
 ; CHECK-NEXT:        	ccall	_Z19doSomethingWithUartP4Uart
   call void @_Z19doSomethingWithUartP4Uart(ptr addrspace(200) noundef @uart_RWcm2)
 
-; CHECK-NEXT:           cmove   ca0, cs1
+; CHECK-NEXT:           cmove   a0, s1
 ; CHECK-NEXT:        	ccall	_Z19doSomethingWithUartP4Uart
   call void @_Z19doSomethingWithUartP4Uart(ptr addrspace(200) noundef @uart_RWcm2)
 
 ; CHECK:        .LBB0_19:                               # %entry
 ; CHECK-NEXT:                                           # Label of block must be emitted
-; CHECK-NEXT:        	auipcc	ca0, %cheriot_compartment_hi("__import_cheriot_shared_object_shared_obj_RWcm-")
-; CHECK-NEXT:        	clc	ca0, %cheriot_compartment_lo_i(.LBB0_19)(ca0)
+; CHECK-NEXT:        	auipcc	a0, %cheriot_compartment_hi("__import_cheriot_shared_object_shared_obj_RWcm-")
+; CHECK-NEXT:        	clc	a0, %cheriot_compartment_lo_i(.LBB0_19)(a0)
 ; CHECK-NEXT:        	ccall	_Z19doSomethingWithSharedObjectP4SharedObject
   call void @_Z19doSomethingWithSharedObjectP4SharedObject(ptr addrspace(200) noundef @shared_obj_RWcm)
 
 ; CHECK:        .LBB0_20:                               # %entry
 ; CHECK-NEXT:                                           # Label of block must be emitted
-; CHECK-NEXT:        	auipcc	ca0, %cheriot_compartment_hi(__import_mem_uart_RWcmg)
-; CHECK-NEXT:        	clc	ca0, %cheriot_compartment_lo_i(.LBB0_20)(ca0)
+; CHECK-NEXT:        	auipcc	a0, %cheriot_compartment_hi(__import_mem_uart_RWcmg)
+; CHECK-NEXT:        	clc	a0, %cheriot_compartment_lo_i(.LBB0_20)(a0)
 ; CHECK-NEXT:        	ccall	_Z19doSomethingWithUartP4Uart
   call void @_Z19doSomethingWithUartP4Uart(ptr addrspace(200) noundef @uart_RWcmg)
 
 ; CHECK:        .LBB0_21:                               # %entry
 ; CHECK-NEXT:                                           # Label of block must be emitted
-; CHECK-NEXT:        	auipcc	ca0, %cheriot_compartment_hi(__import_cheriot_shared_object_shared_obj_RWcmg)
-; CHECK-NEXT:        	clc	ca0, %cheriot_compartment_lo_i(.LBB0_21)(ca0)
+; CHECK-NEXT:        	auipcc	a0, %cheriot_compartment_hi(__import_cheriot_shared_object_shared_obj_RWcmg)
+; CHECK-NEXT:        	clc	a0, %cheriot_compartment_lo_i(.LBB0_21)(a0)
 ; CHECK-NEXT:        	ccall	_Z19doSomethingWithSharedObjectP4SharedObject
   call void @_Z19doSomethingWithSharedObjectP4SharedObject(ptr addrspace(200) noundef @shared_obj_RWcmg)
 
diff --git a/llvm/test/CodeGen/RISCV/cheri/hoist-setbounds.mir b/llvm/test/CodeGen/RISCV/cheri/hoist-setbounds.mir
index b64fdf74ed5de..f7f316a183bb5 100644
--- a/llvm/test/CodeGen/RISCV/cheri/hoist-setbounds.mir
+++ b/llvm/test/CodeGen/RISCV/cheri/hoist-setbounds.mir
@@ -98,36 +98,36 @@ body:             |
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr = COPY $x10
   ; CHECK-NEXT:   [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 492
   ; CHECK-NEXT:   [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 493
-  ; CHECK-NEXT:   [[CIncOffsetImm:%[0-9]+]]:gpcr = CIncOffsetImm %stack.0.buf1, 0
-  ; CHECK-NEXT:   [[CSetBounds:%[0-9]+]]:gpcr = CSetBounds [[CIncOffsetImm]], [[ADDI]]
-  ; CHECK-NEXT:   [[CSetBoundsExact:%[0-9]+]]:gpcr = CSetBoundsExact [[CIncOffsetImm]], [[ADDI]]
-  ; CHECK-NEXT:   [[CSetBoundsImm:%[0-9]+]]:gpcr = CSetBoundsImm [[CIncOffsetImm]], 492
-  ; CHECK-NEXT:   [[CIncOffsetImm1:%[0-9]+]]:gpcr = CIncOffsetImm %stack.0.buf1, 1
-  ; CHECK-NEXT:   [[CSetBounds1:%[0-9]+]]:gpcr = CSetBounds [[CIncOffsetImm1]], [[ADDI]]
-  ; CHECK-NEXT:   [[CSetBoundsExact1:%[0-9]+]]:gpcr = CSetBoundsExact [[CIncOffsetImm1]], [[ADDI]]
-  ; CHECK-NEXT:   [[CSetBoundsImm1:%[0-9]+]]:gpcr = CSetBoundsImm [[CIncOffsetImm1]], 492
+  ; CHECK-NEXT:   [[CIncOffsetImm:%[0-9]+]]:ygpr = CIncOffsetImm %stack.0.buf1, 0
+  ; CHECK-NEXT:   [[CSetBounds:%[0-9]+]]:ygpr = CSetBounds [[CIncOffsetImm]], [[ADDI]]
+  ; CHECK-NEXT:   [[CSetBoundsExact:%[0-9]+]]:ygpr = CSetBoundsExact [[CIncOffsetImm]], [[ADDI]]
+  ; CHECK-NEXT:   [[CSetBoundsImm:%[0-9]+]]:ygpr = CSetBoundsImm [[CIncOffsetImm]], 492
+  ; CHECK-NEXT:   [[CIncOffsetImm1:%[0-9]+]]:ygpr = CIncOffsetImm %stack.0.buf1, 1
+  ; CHECK-NEXT:   [[CSetBounds1:%[0-9]+]]:ygpr = CSetBounds [[CIncOffsetImm1]], [[ADDI]]
+  ; CHECK-NEXT:   [[CSetBoundsExact1:%[0-9]+]]:ygpr = CSetBoundsExact [[CIncOffsetImm1]], [[ADDI]]
+  ; CHECK-NEXT:   [[CSetBoundsImm1:%[0-9]+]]:ygpr = CSetBoundsImm [[CIncOffsetImm1]], 492
   ; CHECK-NEXT:   [[ADDI2:%[0-9]+]]:gpr = ADDI $x0, 491
-  ; CHECK-NEXT:   [[CSetBounds2:%[0-9]+]]:gpcr = CSetBounds [[CIncOffsetImm1]], [[ADDI2]]
-  ; CHECK-NEXT:   [[CSetBoundsExact2:%[0-9]+]]:gpcr = CSetBoundsExact [[CIncOffsetImm1]], [[ADDI2]]
-  ; CHECK-NEXT:   [[CSetBoundsImm2:%[0-9]+]]:gpcr = CSetBoundsImm [[CIncOffsetImm1]], 491
+  ; CHECK-NEXT:   [[CSetBounds2:%[0-9]+]]:ygpr = CSetBounds [[CIncOffsetImm1]], [[ADDI2]]
+  ; CHECK-NEXT:   [[CSetBoundsExact2:%[0-9]+]]:ygpr = CSetBoundsExact [[CIncOffsetImm1]], [[ADDI2]]
+  ; CHECK-NEXT:   [[CSetBoundsImm2:%[0-9]+]]:ygpr = CSetBoundsImm [[CIncOffsetImm1]], 491
   ; CHECK-NEXT:   [[ADDI3:%[0-9]+]]:gpr = ADDI $x0, 88
-  ; CHECK-NEXT:   [[CIncOffsetImm2:%[0-9]+]]:gpcr = CIncOffsetImm %stack.1.buf2, 0
-  ; CHECK-NEXT:   [[CSetBounds3:%[0-9]+]]:gpcr = CSetBounds [[CIncOffsetImm2]], [[ADDI3]]
-  ; CHECK-NEXT:   [[CSetBoundsExact3:%[0-9]+]]:gpcr = CSetBoundsExact [[CIncOffsetImm2]], [[ADDI3]]
-  ; CHECK-NEXT:   [[CIncOffsetImm3:%[0-9]+]]:gpcr = CIncOffsetImm [[CIncOffsetImm1]], -1
-  ; CHECK-NEXT:   [[CSetBounds4:%[0-9]+]]:gpcr = CSetBounds [[CIncOffsetImm3]], [[ADDI3]]
-  ; CHECK-NEXT:   [[CSetBoundsExact4:%[0-9]+]]:gpcr = CSetBoundsExact [[CIncOffsetImm3]], [[ADDI3]]
-  ; CHECK-NEXT:   [[CSetBoundsImm3:%[0-9]+]]:gpcr = CSetBoundsImm [[CIncOffsetImm3]], 492
-  ; CHECK-NEXT:   [[CIncOffsetImm4:%[0-9]+]]:gpcr = CIncOffsetImm $c0, 1
-  ; CHECK-NEXT:   [[CIncOffsetImm5:%[0-9]+]]:gpcr = CIncOffsetImm [[CIncOffsetImm4]], -1
-  ; CHECK-NEXT:   [[CSetBounds5:%[0-9]+]]:gpcr = CSetBounds [[CIncOffsetImm5]], [[ADDI3]]
-  ; CHECK-NEXT:   [[CSetBoundsExact5:%[0-9]+]]:gpcr = CSetBoundsExact [[CIncOffsetImm5]], [[ADDI3]]
-  ; CHECK-NEXT:   [[CSetBoundsImm4:%[0-9]+]]:gpcr = CSetBoundsImm [[CIncOffsetImm5]], 492
-  ; CHECK-NEXT:   [[CSetOffset:%[0-9]+]]:gpcr = CSetOffset [[CIncOffsetImm1]], $x0
-  ; CHECK-NEXT:   [[CSetBoundsImm5:%[0-9]+]]:gpcr = CSetBoundsImm [[CIncOffsetImm1]], 0
-  ; CHECK-NEXT:   [[CIncOffsetImm6:%[0-9]+]]:gpcr = CIncOffsetImm %stack.0.buf1, 492
-  ; CHECK-NEXT:   [[CSetBoundsImm6:%[0-9]+]]:gpcr = CSetBoundsImm [[CIncOffsetImm6]], 0
-  ; CHECK-NEXT:   [[CSetBoundsImm7:%[0-9]+]]:gpcr = CSetBoundsImm [[CIncOffsetImm6]], 1
+  ; CHECK-NEXT:   [[CIncOffsetImm2:%[0-9]+]]:ygpr = CIncOffsetImm %stack.1.buf2, 0
+  ; CHECK-NEXT:   [[CSetBounds3:%[0-9]+]]:ygpr = CSetBounds [[CIncOffsetImm2]], [[ADDI3]]
+  ; CHECK-NEXT:   [[CSetBoundsExact3:%[0-9]+]]:ygpr = CSetBoundsExact [[CIncOffsetImm2]], [[ADDI3]]
+  ; CHECK-NEXT:   [[CIncOffsetImm3:%[0-9]+]]:ygpr = CIncOffsetImm [[CIncOffsetImm1]], -1
+  ; CHECK-NEXT:   [[CSetBounds4:%[0-9]+]]:ygpr = CSetBounds [[CIncOffsetImm3]], [[ADDI3]]
+  ; CHECK-NEXT:   [[CSetBoundsExact4:%[0-9]+]]:ygpr = CSetBoundsExact [[CIncOffsetImm3]], [[ADDI3]]
+  ; CHECK-NEXT:   [[CSetBoundsImm3:%[0-9]+]]:ygpr = CSetBoundsImm [[CIncOffsetImm3]], 492
+  ; CHECK-NEXT:   [[CIncOffsetImm4:%[0-9]+]]:ygpr = CIncOffsetImm $x0_y, 1
+  ; CHECK-NEXT:   [[CIncOffsetImm5:%[0-9]+]]:ygpr = CIncOffsetImm [[CIncOffsetImm4]], -1
+  ; CHECK-NEXT:   [[CSetBounds5:%[0-9]+]]:ygpr = CSetBounds [[CIncOffsetImm5]], [[ADDI3]]
+  ; CHECK-NEXT:   [[CSetBoundsExact5:%[0-9]+]]:ygpr = CSetBoundsExact [[CIncOffsetImm5]], [[ADDI3]]
+  ; CHECK-NEXT:   [[CSetBoundsImm4:%[0-9]+]]:ygpr = CSetBoundsImm [[CIncOffsetImm5]], 492
+  ; CHECK-NEXT:   [[CSetOffset:%[0-9]+]]:ygpr = CSetOffset [[CIncOffsetImm1]], $x0
+  ; CHECK-NEXT:   [[CSetBoundsImm5:%[0-9]+]]:ygpr = CSetBoundsImm [[CIncOffsetImm1]], 0
+  ; CHECK-NEXT:   [[CIncOffsetImm6:%[0-9]+]]:ygpr = CIncOffsetImm %stack.0.buf1, 492
+  ; CHECK-NEXT:   [[CSetBoundsImm6:%[0-9]+]]:ygpr = CSetBoundsImm [[CIncOffsetImm6]], 0
+  ; CHECK-NEXT:   [[CSetBoundsImm7:%[0-9]+]]:ygpr = CSetBoundsImm [[CIncOffsetImm6]], 1
   ; CHECK-NEXT:   PseudoBR %bb.2
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.1.for.cond.cleanup:
@@ -166,48 +166,48 @@ body:             |
     successors: %bb.4(0x80000000)
     %5:gpr = ADDI $x0, 492
     %6:gpr = ADDI $x0, 493
-    %10:gpcr = CIncOffsetImm %stack.0.buf1, 0
-    %11:gpcr = CSetBounds %10, %5
-    %12:gpcr = CSetBoundsExact %10, %5
-    %13:gpcr = CSetBoundsImm %10, 492
-    %14:gpcr = CSetBounds %10, %5
-    %15:gpcr = CSetBoundsExact %10, %5
-    %16:gpcr = CSetBoundsImm %10, 492
-
-    %30:gpcr = CIncOffsetImm %stack.0.buf1, 1
-    %31:gpcr = CSetBounds %30, %5
-    %32:gpcr = CSetBoundsExact %30, %5
-    %33:gpcr = CSetBoundsImm %30, 492
+    %10:ygpr = CIncOffsetImm %stack.0.buf1, 0
+    %11:ygpr = CSetBounds %10, %5
+    %12:ygpr = CSetBoundsExact %10, %5
+    %13:ygpr = CSetBoundsImm %10, 492
+    %14:ygpr = CSetBounds %10, %5
+    %15:ygpr = CSetBoundsExact %10, %5
+    %16:ygpr = CSetBoundsImm %10, 492
+
+    %30:ygpr = CIncOffsetImm %stack.0.buf1, 1
+    %31:ygpr = CSetBounds %30, %5
+    %32:ygpr = CSetBoundsExact %30, %5
+    %33:ygpr = CSetBoundsImm %30, 492
     %34:gpr = ADDI $x0, 491  ; length - 1 -> should be fine
-    %35:gpcr = CSetBounds %30, %34
-    %36:gpcr = CSetBoundsExact %30, %34
-    %37:gpcr = CSetBoundsImm %30, 491
-    %38:gpcr = CSetBoundsImm %30, 492 ; OOB
+    %35:ygpr = CSetBounds %30, %34
+    %36:ygpr = CSetBoundsExact %30, %34
+    %37:ygpr = CSetBoundsImm %30, 491
+    %38:ygpr = CSetBoundsImm %30, 492 ; OOB
 
     %50:gpr = ADDI $x0, 88
-    %51:gpcr = CIncOffsetImm %stack.1.buf2, 0
-    %52:gpcr = CSetBounds %51, %50
-    %53:gpcr = CSetBoundsExact %51, %50
-    %54:gpcr = CSetBounds %51, %50
-
-
-    %100:gpcr = CIncOffsetImm %stack.0.buf1, 1
-    %101:gpcr = CIncOffsetImm %100, -1
-    %102:gpcr = CSetBounds %101, %50
-    %103:gpcr = CSetBoundsExact %101, %50
-    %104:gpcr = CSetBoundsImm %101, 492
-
-    %110:gpcr = CIncOffsetImm $c0, 1
-    %111:gpcr = CIncOffsetImm %110, -1
-    %112:gpcr = CSetBounds %111, %50
-    %113:gpcr = CSetBoundsExact %111, %50
-    %114:gpcr = CSetBoundsImm %111, 492
-
-    %120:gpcr = CSetOffset %100, $x0
-    %121:gpcr = CSetBoundsImm %100, 0
-    %122:gpcr = CIncOffsetImm %stack.0.buf1, 492
-    %123:gpcr = CSetBoundsImm %122, 0
-    %124:gpcr = CSetBoundsImm %122, 1
+    %51:ygpr = CIncOffsetImm %stack.1.buf2, 0
+    %52:ygpr = CSetBounds %51, %50
+    %53:ygpr = CSetBoundsExact %51, %50
+    %54:ygpr = CSetBounds %51, %50
+
+
+    %100:ygpr = CIncOffsetImm %stack.0.buf1, 1
+    %101:ygpr = CIncOffsetImm %100, -1
+    %102:ygpr = CSetBounds %101, %50
+    %103:ygpr = CSetBoundsExact %101, %50
+    %104:ygpr = CSetBoundsImm %101, 492
+
+    %110:ygpr = CIncOffsetImm $x0_y, 1
+    %111:ygpr = CIncOffsetImm %110, -1
+    %112:ygpr = CSetBounds %111, %50
+    %113:ygpr = CSetBoundsExact %111, %50
+    %114:ygpr = CSetBoundsImm %111, 492
+
+    %120:ygpr = CSetOffset %100, $x0
+    %121:ygpr = CSetBoundsImm %100, 0
+    %122:ygpr = CIncOffsetImm %stack.0.buf1, 492
+    %123:ygpr = CSetBoundsImm %122, 0
+    %124:ygpr = CSetBoundsImm %122, 1
 
 
   bb.4.for.inc:
diff --git a/llvm/test/CodeGen/RISCV/cheri/indirectbr.ll b/llvm/test/CodeGen/RISCV/cheri/indirectbr.ll
index 99ea543f48891..de73155424cdc 100644
--- a/llvm/test/CodeGen/RISCV/cheri/indirectbr.ll
+++ b/llvm/test/CodeGen/RISCV/cheri/indirectbr.ll
@@ -7,24 +7,24 @@
 define i32 @indirectbr(i8 addrspace(200)* %target) nounwind {
 ; RV32IXCHERI-LABEL: indirectbr:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    cjr ca0
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cjr a0
 ; RV32IXCHERI-NEXT:  .LBB0_1: # %test_label
 ; RV32IXCHERI-NEXT:    li a0, 0
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: indirectbr:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    cjr ca0
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cjr a0
 ; RV64IXCHERI-NEXT:  .LBB0_1: # %test_label
 ; RV64IXCHERI-NEXT:    li a0, 0
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
   indirectbr i8 addrspace(200)* %target, [label %test_label]
 test_label:
@@ -36,24 +36,24 @@ ret:
 define i32 @indirectbr_with_offset(i8 addrspace(200)* %a) nounwind {
 ; RV32IXCHERI-LABEL: indirectbr_with_offset:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    cjr 1380(ca0)
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cjr 1380(a0)
 ; RV32IXCHERI-NEXT:  .LBB1_1: # %test_label
 ; RV32IXCHERI-NEXT:    li a0, 0
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: indirectbr_with_offset:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    cjr 1380(ca0)
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cjr 1380(a0)
 ; RV64IXCHERI-NEXT:  .LBB1_1: # %test_label
 ; RV64IXCHERI-NEXT:    li a0, 0
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    cret
   %target = getelementptr inbounds i8, i8 addrspace(200)* %a, i32 1380
   indirectbr i8 addrspace(200)* %target, [label %test_label]
diff --git a/llvm/test/CodeGen/RISCV/cheri/isav9-cap-from-ptr.ll b/llvm/test/CodeGen/RISCV/cheri/isav9-cap-from-ptr.ll
index 835c0b55624b2..ba708030120d2 100644
--- a/llvm/test/CodeGen/RISCV/cheri/isav9-cap-from-ptr.ll
+++ b/llvm/test/CodeGen/RISCV/cheri/isav9-cap-from-ptr.ll
@@ -9,13 +9,13 @@ define dso_local i8 addrspace(200)* @cap_from_ptr(i8 addrspace(200)* addrspace(2
 ; ISAV9:       # %bb.0: # %entry
 ; ISAV9-NEXT:    bnez a2, .LBB0_2
 ; ISAV9-NEXT:  # %bb.1: # %entry
-; ISAV9-NEXT:    cmove ca1, cnull
+; ISAV9-NEXT:    cmove a1, zero
 ; ISAV9-NEXT:    j .LBB0_3
 ; ISAV9-NEXT:  .LBB0_2:
-; ISAV9-NEXT:    csetaddr ca1, ca1, a2
+; ISAV9-NEXT:    csetaddr a1, a1, a2
 ; ISAV9-NEXT:  .LBB0_3: # %entry
-; ISAV9-NEXT:    csc ca1, 0(ca0)
-; ISAV9-NEXT:    cmove ca0, ca1
+; ISAV9-NEXT:    csc a1, 0(a0)
+; ISAV9-NEXT:    cmove a0, a1
 ; ISAV9-NEXT:    cret
 entry:
   %new = call i8 addrspace(200)* @llvm.cheri.cap.from.pointer.i64(i8 addrspace(200)* %cap, i64 %offset)
@@ -27,16 +27,16 @@ entry:
 define dso_local i8 addrspace(200)* @cap_from_ptr_ddc(i8 addrspace(200)* addrspace(200)* %ptr, i64 %offset) nounwind {
 ; ISAV9-LABEL: cap_from_ptr_ddc:
 ; ISAV9:       # %bb.0: # %entry
-; ISAV9-NEXT:    cspecialr ca2, ddc
+; ISAV9-NEXT:    cspecialr a2, ddc
 ; ISAV9-NEXT:    bnez a1, .LBB1_2
 ; ISAV9-NEXT:  # %bb.1: # %entry
-; ISAV9-NEXT:    cmove ca1, cnull
+; ISAV9-NEXT:    cmove a1, zero
 ; ISAV9-NEXT:    j .LBB1_3
 ; ISAV9-NEXT:  .LBB1_2:
-; ISAV9-NEXT:    csetaddr ca1, ca2, a1
+; ISAV9-NEXT:    csetaddr a1, a2, a1
 ; ISAV9-NEXT:  .LBB1_3: # %entry
-; ISAV9-NEXT:    csc ca1, 0(ca0)
-; ISAV9-NEXT:    cmove ca0, ca1
+; ISAV9-NEXT:    csc a1, 0(a0)
+; ISAV9-NEXT:    cmove a0, a1
 ; ISAV9-NEXT:    cret
 entry:
   %ddc = call i8 addrspace(200)* @llvm.cheri.ddc.get()
diff --git a/llvm/test/CodeGen/RISCV/cheri/isav9-cap-to-ptr.ll b/llvm/test/CodeGen/RISCV/cheri/isav9-cap-to-ptr.ll
index 0d4433617af18..b6c9b916349d5 100644
--- a/llvm/test/CodeGen/RISCV/cheri/isav9-cap-to-ptr.ll
+++ b/llvm/test/CodeGen/RISCV/cheri/isav9-cap-to-ptr.ll
@@ -7,10 +7,10 @@
 define dso_local i64 @cap_to_ptr(i64 addrspace(200)* %dst, i8 addrspace(200)* %auth, i8 addrspace(200)* %cap) nounwind {
 ; ISAV9-LABEL: cap_to_ptr:
 ; ISAV9:       # %bb.0: # %entry
-; ISAV9-NEXT:    cgettag a1, ca2
+; ISAV9-NEXT:    cgettag a1, a2
 ; ISAV9-NEXT:    neg a1, a1
 ; ISAV9-NEXT:    and a1, a2, a1
-; ISAV9-NEXT:    csd a1, 0(ca0)
+; ISAV9-NEXT:    csd a1, 0(a0)
 ; ISAV9-NEXT:    mv a0, a1
 ; ISAV9-NEXT:    cret
 entry:
@@ -22,10 +22,10 @@ entry:
 define dso_local i64 @cap_from_ptr_ddc(i64 addrspace(200)* %dst, i8 addrspace(200)* %cap) nounwind {
 ; ISAV9-LABEL: cap_from_ptr_ddc:
 ; ISAV9:       # %bb.0: # %entry
-; ISAV9-NEXT:    cgettag a2, ca1
+; ISAV9-NEXT:    cgettag a2, a1
 ; ISAV9-NEXT:    neg a2, a2
 ; ISAV9-NEXT:    and a1, a1, a2
-; ISAV9-NEXT:    csd a1, 0(ca0)
+; ISAV9-NEXT:    csd a1, 0(a0)
 ; ISAV9-NEXT:    mv a0, a1
 ; ISAV9-NEXT:    cret
 entry:
diff --git a/llvm/test/CodeGen/RISCV/cheri/isav9-inttoptr.ll b/llvm/test/CodeGen/RISCV/cheri/isav9-inttoptr.ll
index 99dd40babc6ce..d0a1d3750e753 100644
--- a/llvm/test/CodeGen/RISCV/cheri/isav9-inttoptr.ll
+++ b/llvm/test/CodeGen/RISCV/cheri/isav9-inttoptr.ll
@@ -6,18 +6,18 @@
 define dso_local i8 addrspace(200)* @inttoptr(i64 %ptr) addrspace(200) nounwind {
 ; PURECAP-LABEL: inttoptr:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    cincoffset ca0, cnull, a0
+; PURECAP-NEXT:    cincoffset a0, zero, a0
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: inttoptr:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    cspecialr ca1, ddc
+; HYBRID-NEXT:    cspecialr a1, ddc
 ; HYBRID-NEXT:    bnez a0, .LBB0_2
 ; HYBRID-NEXT:  # %bb.1:
-; HYBRID-NEXT:    cmove ca0, cnull
+; HYBRID-NEXT:    cmove a0, zero
 ; HYBRID-NEXT:    ret
 ; HYBRID-NEXT:  .LBB0_2:
-; HYBRID-NEXT:    csetaddr ca0, ca1, a0
+; HYBRID-NEXT:    csetaddr a0, a1, a0
 ; HYBRID-NEXT:    ret
   %ret = inttoptr i64 %ptr to i8 addrspace(200)*
   ret i8 addrspace(200)* %ret
@@ -26,20 +26,20 @@ define dso_local i8 addrspace(200)* @inttoptr(i64 %ptr) addrspace(200) nounwind
 define dso_local i8 addrspace(200)* @inttoptr_plus_const(i64 %ptr) addrspace(200) nounwind {
 ; PURECAP-LABEL: inttoptr_plus_const:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    cincoffset ca0, cnull, a0
-; PURECAP-NEXT:    cincoffset ca0, ca0, 2
+; PURECAP-NEXT:    cincoffset a0, zero, a0
+; PURECAP-NEXT:    cincoffset a0, a0, 2
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: inttoptr_plus_const:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    cspecialr ca1, ddc
+; HYBRID-NEXT:    cspecialr a1, ddc
 ; HYBRID-NEXT:    bnez a0, .LBB1_2
 ; HYBRID-NEXT:  # %bb.1:
-; HYBRID-NEXT:    cincoffset ca0, cnull, 2
+; HYBRID-NEXT:    cincoffset a0, zero, 2
 ; HYBRID-NEXT:    ret
 ; HYBRID-NEXT:  .LBB1_2:
-; HYBRID-NEXT:    csetaddr ca0, ca1, a0
-; HYBRID-NEXT:    cincoffset ca0, ca0, 2
+; HYBRID-NEXT:    csetaddr a0, a1, a0
+; HYBRID-NEXT:    cincoffset a0, a0, 2
 ; HYBRID-NEXT:    ret
   %cap = inttoptr i64 %ptr to i8 addrspace(200)*
   %ret = getelementptr i8, i8 addrspace(200)* %cap, i64 2
@@ -57,20 +57,20 @@ define dso_local i8 addrspace(200)* @inttoptr_plus_const(i64 %ptr) addrspace(200
 define dso_local i8 addrspace(200)* @inttoptr_plus_var(i64 %ptr, i64 %add) addrspace(200) nounwind {
 ; PURECAP-LABEL: inttoptr_plus_var:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    cincoffset ca0, cnull, a0
-; PURECAP-NEXT:    cincoffset ca0, ca0, a1
+; PURECAP-NEXT:    cincoffset a0, zero, a0
+; PURECAP-NEXT:    cincoffset a0, a0, a1
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: inttoptr_plus_var:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    cspecialr ca2, ddc
+; HYBRID-NEXT:    cspecialr a2, ddc
 ; HYBRID-NEXT:    bnez a0, .LBB2_2
 ; HYBRID-NEXT:  # %bb.1:
-; HYBRID-NEXT:    cincoffset ca0, cnull, a1
+; HYBRID-NEXT:    cincoffset a0, zero, a1
 ; HYBRID-NEXT:    ret
 ; HYBRID-NEXT:  .LBB2_2:
-; HYBRID-NEXT:    csetaddr ca0, ca2, a0
-; HYBRID-NEXT:    cincoffset ca0, ca0, a1
+; HYBRID-NEXT:    csetaddr a0, a2, a0
+; HYBRID-NEXT:    cincoffset a0, a0, a1
 ; HYBRID-NEXT:    ret
   %cap = inttoptr i64 %ptr to i8 addrspace(200)*
   %ret = getelementptr i8, i8 addrspace(200)* %cap, i64 %add
@@ -80,12 +80,12 @@ define dso_local i8 addrspace(200)* @inttoptr_plus_var(i64 %ptr, i64 %add) addrs
 define dso_local i8 addrspace(200)* @inttoptr_null() addrspace(200) nounwind {
 ; PURECAP-LABEL: inttoptr_null:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    cmove ca0, cnull
+; PURECAP-NEXT:    cmove a0, zero
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: inttoptr_null:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    cmove ca0, cnull
+; HYBRID-NEXT:    cmove a0, zero
 ; HYBRID-NEXT:    ret
   %ret = inttoptr i64 0 to i8 addrspace(200)*
   ret i8 addrspace(200)* %ret
@@ -94,12 +94,12 @@ define dso_local i8 addrspace(200)* @inttoptr_null() addrspace(200) nounwind {
 define dso_local i8 addrspace(200)* @inttoptr_null_plus_const() addrspace(200) nounwind {
 ; PURECAP-LABEL: inttoptr_null_plus_const:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    cincoffset ca0, cnull, 2
+; PURECAP-NEXT:    cincoffset a0, zero, 2
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: inttoptr_null_plus_const:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    cincoffset ca0, cnull, 2
+; HYBRID-NEXT:    cincoffset a0, zero, 2
 ; HYBRID-NEXT:    ret
   %null = inttoptr i64 0 to i8 addrspace(200)*
   %ret = getelementptr i8, i8 addrspace(200)* %null, i64 2
@@ -109,12 +109,12 @@ define dso_local i8 addrspace(200)* @inttoptr_null_plus_const() addrspace(200) n
 define dso_local i8 addrspace(200)* @inttoptr_null_plus_var(i64 %add) addrspace(200) nounwind {
 ; PURECAP-LABEL: inttoptr_null_plus_var:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    cincoffset ca0, cnull, a0
+; PURECAP-NEXT:    cincoffset a0, zero, a0
 ; PURECAP-NEXT:    cret
 ;
 ; HYBRID-LABEL: inttoptr_null_plus_var:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    cincoffset ca0, cnull, a0
+; HYBRID-NEXT:    cincoffset a0, zero, a0
 ; HYBRID-NEXT:    ret
   %null = inttoptr i64 0 to i8 addrspace(200)*
   %ret = getelementptr i8, i8 addrspace(200)* %null, i64 %add
diff --git a/llvm/test/CodeGen/RISCV/cheri/isav9-ptrtoint.ll b/llvm/test/CodeGen/RISCV/cheri/isav9-ptrtoint.ll
index 88f0674e2984c..5738172749882 100644
--- a/llvm/test/CodeGen/RISCV/cheri/isav9-ptrtoint.ll
+++ b/llvm/test/CodeGen/RISCV/cheri/isav9-ptrtoint.ll
@@ -13,7 +13,7 @@ define dso_local i64 @ptrtoint(i8 addrspace(200)* %cap) addrspace(200) nounwind
 ;
 ; HYBRID-LABEL: ptrtoint:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    cgettag a1, ca0
+; HYBRID-NEXT:    cgettag a1, a0
 ; HYBRID-NEXT:    neg a1, a1
 ; HYBRID-NEXT:    and a0, a0, a1
 ; HYBRID-NEXT:    ret
@@ -29,7 +29,7 @@ define dso_local i64 @ptrtoint_plus_const(i8 addrspace(200)* %cap) addrspace(200
 ;
 ; HYBRID-LABEL: ptrtoint_plus_const:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    cgettag a1, ca0
+; HYBRID-NEXT:    cgettag a1, a0
 ; HYBRID-NEXT:    neg a1, a1
 ; HYBRID-NEXT:    and a0, a0, a1
 ; HYBRID-NEXT:    addi a0, a0, 2
@@ -47,7 +47,7 @@ define dso_local i64 @ptrtoint_plus_var(i8 addrspace(200)* %cap, i64 %add) addrs
 ;
 ; HYBRID-LABEL: ptrtoint_plus_var:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    cgettag a2, ca0
+; HYBRID-NEXT:    cgettag a2, a0
 ; HYBRID-NEXT:    neg a2, a2
 ; HYBRID-NEXT:    and a0, a0, a2
 ; HYBRID-NEXT:    add a0, a0, a1
@@ -65,7 +65,7 @@ define dso_local i64 @ptrtoint_null() addrspace(200) nounwind {
 ;
 ; HYBRID-LABEL: ptrtoint_null:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    cgettag a0, cnull
+; HYBRID-NEXT:    cgettag a0, zero
 ; HYBRID-NEXT:    neg a0, a0
 ; HYBRID-NEXT:    li a0, 0
 ; HYBRID-NEXT:    ret
@@ -81,7 +81,7 @@ define dso_local i64 @ptrtoint_null_plus_const() addrspace(200) nounwind {
 ;
 ; HYBRID-LABEL: ptrtoint_null_plus_const:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    cgettag a0, cnull
+; HYBRID-NEXT:    cgettag a0, zero
 ; HYBRID-NEXT:    neg a0, a0
 ; HYBRID-NEXT:    li a0, 2
 ; HYBRID-NEXT:    ret
@@ -97,7 +97,7 @@ define dso_local i64 @ptrtoint_null_plus_var(i64 %add) addrspace(200) nounwind {
 ;
 ; HYBRID-LABEL: ptrtoint_null_plus_var:
 ; HYBRID:       # %bb.0:
-; HYBRID-NEXT:    cgettag a1, cnull
+; HYBRID-NEXT:    cgettag a1, zero
 ; HYBRID-NEXT:    neg a1, a1
 ; HYBRID-NEXT:    ret
   %zero = ptrtoint i8 addrspace(200)* null to i64
diff --git a/llvm/test/CodeGen/RISCV/cheri/landing-pad.ll b/llvm/test/CodeGen/RISCV/cheri/landing-pad.ll
index f0bfd6cc015b9..321837816bef5 100644
--- a/llvm/test/CodeGen/RISCV/cheri/landing-pad.ll
+++ b/llvm/test/CodeGen/RISCV/cheri/landing-pad.ll
@@ -17,9 +17,9 @@ declare void @__cxa_end_catch() addrspace(200)
 define void @test() addrspace(200) personality i8 addrspace(200)* bitcast (i32 (...) addrspace(200)* @__gxx_personality_v0 to i8 addrspace(200)*) {
 ; RV32IXCHERI-LABEL: test:
 ; RV32IXCHERI:       # %bb.0: # %entry
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
 ; RV32IXCHERI-NEXT:    .cfi_def_cfa_offset 16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-NEXT:    .cfi_offset ra, -8
 ; RV32IXCHERI-NEXT:  .Ltmp0:
 ; RV32IXCHERI-NEXT:    ccall throw_exception
@@ -31,17 +31,17 @@ define void @test() addrspace(200) personality i8 addrspace(200)* bitcast (i32 (
 ; RV32IXCHERI-NEXT:    ccall __cxa_end_catch
 ; RV32IXCHERI-NEXT:    j .LBB0_2
 ; RV32IXCHERI-NEXT:  .LBB0_2: # %try.cont
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
 ; RV32IXCHERI-NEXT:    .cfi_restore ra
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: test:
 ; RV64IXCHERI:       # %bb.0: # %entry
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -16
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -16
 ; RV64IXCHERI-NEXT:    .cfi_def_cfa_offset 16
-; RV64IXCHERI-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-NEXT:    .cfi_offset ra, -16
 ; RV64IXCHERI-NEXT:  .Ltmp0:
 ; RV64IXCHERI-NEXT:    ccall throw_exception
@@ -53,9 +53,9 @@ define void @test() addrspace(200) personality i8 addrspace(200)* bitcast (i32 (
 ; RV64IXCHERI-NEXT:    ccall __cxa_end_catch
 ; RV64IXCHERI-NEXT:    j .LBB0_2
 ; RV64IXCHERI-NEXT:  .LBB0_2: # %try.cont
-; RV64IXCHERI-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
 ; RV64IXCHERI-NEXT:    .cfi_restore ra
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV64IXCHERI-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IXCHERI-NEXT:    cret
 entry:
diff --git a/llvm/test/CodeGen/RISCV/cheri/large-frame.ll b/llvm/test/CodeGen/RISCV/cheri/large-frame.ll
index b4ffff676207b..6bf7fa585b87a 100644
--- a/llvm/test/CodeGen/RISCV/cheri/large-frame.ll
+++ b/llvm/test/CodeGen/RISCV/cheri/large-frame.ll
@@ -7,38 +7,38 @@
 define dso_local void @bar() addrspace(200) nounwind {
 ; RV32IXCHERI-IL32PC64-LABEL: bar:
 ; RV32IXCHERI-IL32PC64:       # %bb.0: # %entry
-; RV32IXCHERI-IL32PC64-NEXT:    cincoffset csp, csp, -2032
-; RV32IXCHERI-IL32PC64-NEXT:    csc cra, 2024(csp) # 8-byte Folded Spill
-; RV32IXCHERI-IL32PC64-NEXT:    csc cs0, 2016(csp) # 8-byte Folded Spill
-; RV32IXCHERI-IL32PC64-NEXT:    cincoffset cs0, csp, 2032
-; RV32IXCHERI-IL32PC64-NEXT:    cincoffset csp, csp, -2048
-; RV32IXCHERI-IL32PC64-NEXT:    cincoffset csp, csp, -1040
+; RV32IXCHERI-IL32PC64-NEXT:    cincoffset sp, sp, -2032
+; RV32IXCHERI-IL32PC64-NEXT:    csc ra, 2024(sp) # 8-byte Folded Spill
+; RV32IXCHERI-IL32PC64-NEXT:    csc s0, 2016(sp) # 8-byte Folded Spill
+; RV32IXCHERI-IL32PC64-NEXT:    cincoffset s0, sp, 2032
+; RV32IXCHERI-IL32PC64-NEXT:    cincoffset sp, sp, -2048
+; RV32IXCHERI-IL32PC64-NEXT:    cincoffset sp, sp, -1040
 ; RV32IXCHERI-IL32PC64-NEXT:    andi a0, sp, -512
-; RV32IXCHERI-IL32PC64-NEXT:    csetaddr csp, csp, a0
+; RV32IXCHERI-IL32PC64-NEXT:    csetaddr sp, sp, a0
 ; RV32IXCHERI-IL32PC64-NEXT:    lui a0, 1
-; RV32IXCHERI-IL32PC64-NEXT:    cincoffset ca1, csp, 512
-; RV32IXCHERI-IL32PC64-NEXT:    csetbounds ca0, ca1, a0
+; RV32IXCHERI-IL32PC64-NEXT:    cincoffset a1, sp, 512
+; RV32IXCHERI-IL32PC64-NEXT:    csetbounds a0, a1, a0
 ; RV32IXCHERI-IL32PC64-NEXT:    ccall foo
-; RV32IXCHERI-IL32PC64-NEXT:    cincoffset csp, cs0, -2032
-; RV32IXCHERI-IL32PC64-NEXT:    clc cra, 2024(csp) # 8-byte Folded Reload
-; RV32IXCHERI-IL32PC64-NEXT:    clc cs0, 2016(csp) # 8-byte Folded Reload
-; RV32IXCHERI-IL32PC64-NEXT:    cincoffset csp, csp, 2032
+; RV32IXCHERI-IL32PC64-NEXT:    cincoffset sp, s0, -2032
+; RV32IXCHERI-IL32PC64-NEXT:    clc ra, 2024(sp) # 8-byte Folded Reload
+; RV32IXCHERI-IL32PC64-NEXT:    clc s0, 2016(sp) # 8-byte Folded Reload
+; RV32IXCHERI-IL32PC64-NEXT:    cincoffset sp, sp, 2032
 ; RV32IXCHERI-IL32PC64-NEXT:    cret
 ;
 ; RV64IXCHERI-L64PC128-LABEL: bar:
 ; RV64IXCHERI-L64PC128:       # %bb.0: # %entry
-; RV64IXCHERI-L64PC128-NEXT:    cincoffset csp, csp, -2032
-; RV64IXCHERI-L64PC128-NEXT:    csc cra, 2016(csp) # 16-byte Folded Spill
-; RV64IXCHERI-L64PC128-NEXT:    cincoffset csp, csp, -2048
-; RV64IXCHERI-L64PC128-NEXT:    cincoffset csp, csp, -48
+; RV64IXCHERI-L64PC128-NEXT:    cincoffset sp, sp, -2032
+; RV64IXCHERI-L64PC128-NEXT:    csc ra, 2016(sp) # 16-byte Folded Spill
+; RV64IXCHERI-L64PC128-NEXT:    cincoffset sp, sp, -2048
+; RV64IXCHERI-L64PC128-NEXT:    cincoffset sp, sp, -48
 ; RV64IXCHERI-L64PC128-NEXT:    lui a0, 1
-; RV64IXCHERI-L64PC128-NEXT:    cincoffset ca1, csp, 16
-; RV64IXCHERI-L64PC128-NEXT:    csetbounds ca0, ca1, a0
+; RV64IXCHERI-L64PC128-NEXT:    cincoffset a1, sp, 16
+; RV64IXCHERI-L64PC128-NEXT:    csetbounds a0, a1, a0
 ; RV64IXCHERI-L64PC128-NEXT:    ccall foo
-; RV64IXCHERI-L64PC128-NEXT:    cincoffset csp, csp, 2032
-; RV64IXCHERI-L64PC128-NEXT:    cincoffset csp, csp, 64
-; RV64IXCHERI-L64PC128-NEXT:    clc cra, 2016(csp) # 16-byte Folded Reload
-; RV64IXCHERI-L64PC128-NEXT:    cincoffset csp, csp, 2032
+; RV64IXCHERI-L64PC128-NEXT:    cincoffset sp, sp, 2032
+; RV64IXCHERI-L64PC128-NEXT:    cincoffset sp, sp, 64
+; RV64IXCHERI-L64PC128-NEXT:    clc ra, 2016(sp) # 16-byte Folded Reload
+; RV64IXCHERI-L64PC128-NEXT:    cincoffset sp, sp, 2032
 ; RV64IXCHERI-L64PC128-NEXT:    cret
 entry:
   %buf = alloca [4096 x i8], align 1, addrspace(200)
diff --git a/llvm/test/CodeGen/RISCV/cheri/load-imm-from-constant-pool.ll b/llvm/test/CodeGen/RISCV/cheri/load-imm-from-constant-pool.ll
index 9946381b36c03..6d94857cd61dd 100644
--- a/llvm/test/CodeGen/RISCV/cheri/load-imm-from-constant-pool.ll
+++ b/llvm/test/CodeGen/RISCV/cheri/load-imm-from-constant-pool.ll
@@ -49,9 +49,9 @@ define i64 @add_constant(i64 %arg) nounwind {
 ; CHECK-L64PC128-LABEL: add_constant:
 ; CHECK-L64PC128:       # %bb.0:
 ; CHECK-L64PC128-NEXT:  .LBB0_1: # Label of block must be emitted
-; CHECK-L64PC128-NEXT:    auipcc ca1, %pcrel_hi(.LCPI0_0)
-; CHECK-L64PC128-NEXT:    cincoffset ca1, ca1, %pcrel_lo(.LBB0_1)
-; CHECK-L64PC128-NEXT:    cld a1, 0(ca1)
+; CHECK-L64PC128-NEXT:    auipcc a1, %pcrel_hi(.LCPI0_0)
+; CHECK-L64PC128-NEXT:    cincoffset a1, a1, %pcrel_lo(.LBB0_1)
+; CHECK-L64PC128-NEXT:    cld a1, 0(a1)
 ; CHECK-L64PC128-NEXT:    add a0, a0, a1
 ; CHECK-L64PC128-NEXT:    cret
   %add = add i64 %arg, 1311768467139281697
diff --git a/llvm/test/CodeGen/RISCV/cheri/lower-ptrmask.ll b/llvm/test/CodeGen/RISCV/cheri/lower-ptrmask.ll
index 52da8d248c8b2..732deae5d6a41 100644
--- a/llvm/test/CodeGen/RISCV/cheri/lower-ptrmask.ll
+++ b/llvm/test/CodeGen/RISCV/cheri/lower-ptrmask.ll
@@ -3,14 +3,14 @@
 declare ptr addrspace(200) @llvm.ptrmask.p200.i64(ptr addrspace(200), i64);
 
 ; CHECK-LABEL: name: test1
-; CHECK: %0:gpcr = COPY $c10
+; CHECK: %0:ygpr = COPY $x10_y
 ; CHECK-NEXT: %1:gpr = PseudoCGetAddr %0
 ; CHECK-NEXT: %2:gpr = ADDI $x0, -1793
 ; CHECK-NEXT: %3:gpr = SRLI killed %2, 8
 ; CHECK-NEXT: %4:gpr = AND killed %1, killed %3
-; CHECK-NEXT: %5:gpcr = CSetAddr %0, killed %4
-; CHECK-NEXT: $c10 = COPY %5
-; CHECK-NEXT: PseudoCRET implicit $c10
+; CHECK-NEXT: %5:ygpr = CSetAddr %0, killed %4
+; CHECK-NEXT: $x10_y = COPY %5
+; CHECK-NEXT: PseudoCRET implicit $x10_y
 
 define ptr addrspace(200) @test1(ptr addrspace(200) %src) {
   %ptr = call ptr addrspace(200) @llvm.ptrmask.p200.i64(ptr addrspace(200) %src, i64 72057594037927928)
diff --git a/llvm/test/CodeGen/RISCV/cheri/machine-outliner.mir b/llvm/test/CodeGen/RISCV/cheri/machine-outliner.mir
index 91d2d6a5d77f7..bf249467e8a81 100644
--- a/llvm/test/CodeGen/RISCV/cheri/machine-outliner.mir
+++ b/llvm/test/CodeGen/RISCV/cheri/machine-outliner.mir
@@ -31,61 +31,61 @@ name:            pcre2_match_16
 tracksRegLiveness: true
 registers:       []
 liveins:
-  - { reg: '$c10', virtual-reg: '' }
+  - { reg: '$x10_y', virtual-reg: '' }
   - { reg: '$x11', virtual-reg: '' }
 body:             |
   ; CHECK-LABEL: name: pcre2_match_16
   ; CHECK: bb.0:
   ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
-  ; CHECK-NEXT:   liveins: $c10, $x11
+  ; CHECK-NEXT:   liveins: $x10_y, $x11
   ; CHECK-NEXT: {{  $}}
-  ; CHECK-NEXT:   $c13 = CMove $c0
-  ; CHECK-NEXT:   $c14 = CMove $c0
-  ; CHECK-NEXT:   renamable $c12 = CIncOffsetImm renamable $c10, 80
+  ; CHECK-NEXT:   $x13_y = CMove $x0_y
+  ; CHECK-NEXT:   $x14_y = CMove $x0_y
+  ; CHECK-NEXT:   renamable $x12_y = CIncOffsetImm renamable $x10_y, 80
   ; CHECK-NEXT:   renamable $x11 = ANDI killed renamable $x11, 1
   ; CHECK-NEXT:   BEQ renamable $x11, $x0, %bb.2
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.1:
   ; CHECK-NEXT:   successors: %bb.2(0x40000000), %bb.3(0x40000000)
-  ; CHECK-NEXT:   liveins: $c10, $c12, $c13, $x11
+  ; CHECK-NEXT:   liveins: $x10_y, $x12_y, $x13_y, $x11
   ; CHECK-NEXT: {{  $}}
-  ; CHECK-NEXT:   $c5 = PseudoCCALLReg target-flags(riscv-ccall) @OUTLINED_FUNCTION_0, implicit-def $c5, implicit-def $c15, implicit-def $x14, implicit-def $x15, implicit $c10, implicit $c12
+  ; CHECK-NEXT:   $x5_y = PseudoCCALLReg target-flags(riscv-ccall) @OUTLINED_FUNCTION_0, implicit-def $x5_y, implicit-def $x15_y, implicit-def $x14, implicit-def $x15, implicit $x10_y, implicit $x12_y
   ; CHECK-NEXT:   renamable $x14 = ANDI killed renamable $x14, 1
   ; CHECK-NEXT:   BEQ killed renamable $x14, $x0, %bb.3
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.2:
   ; CHECK-NEXT:   successors: %bb.3(0x80000000)
-  ; CHECK-NEXT:   liveins: $c10, $c12, $c13, $x11
+  ; CHECK-NEXT:   liveins: $x10_y, $x12_y, $x13_y, $x11
   ; CHECK-NEXT: {{  $}}
-  ; CHECK-NEXT:   $c5 = PseudoCCALLReg target-flags(riscv-ccall) @OUTLINED_FUNCTION_0, implicit-def $c5, implicit-def $c15, implicit-def $x14, implicit-def $x15, implicit $c10, implicit $c12
+  ; CHECK-NEXT:   $x5_y = PseudoCCALLReg target-flags(riscv-ccall) @OUTLINED_FUNCTION_0, implicit-def $x5_y, implicit-def $x15_y, implicit-def $x14, implicit-def $x15, implicit $x10_y, implicit $x12_y
   ; CHECK-NEXT:   renamable $x15 = ANDI killed renamable $x14, 1
-  ; CHECK-NEXT:   $c14 = CMove $c0
+  ; CHECK-NEXT:   $x14_y = CMove $x0_y
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.3:
   ; CHECK-NEXT:   successors: %bb.1(0x80000000)
-  ; CHECK-NEXT:   liveins: $c10, $c12, $x11
+  ; CHECK-NEXT:   liveins: $x10_y, $x12_y, $x11
   ; CHECK-NEXT: {{  $}}
-  ; CHECK-NEXT:   $c14 = CMove $c0
-  ; CHECK-NEXT:   $c13 = CMove $c10
+  ; CHECK-NEXT:   $x14_y = CMove $x0_y
+  ; CHECK-NEXT:   $x13_y = CMove $x10_y
   ; CHECK-NEXT:   PseudoCBR %bb.1
   bb.0:
     successors: %bb.1(0x40000000), %bb.2(0x40000000)
-    liveins: $c10, $x11
+    liveins: $x10_y, $x11
 
-    $c13 = CMove $c0
-    $c14 = CMove $c0
-    renamable $c12 = CIncOffsetImm renamable $c10, 80
+    $x13_y = CMove $x0_y
+    $x14_y = CMove $x0_y
+    renamable $x12_y = CIncOffsetImm renamable $x10_y, 80
     renamable $x11 = ANDI killed renamable $x11, 1
     BEQ renamable $x11, $x0, %bb.2
 
   bb.1:
     successors: %bb.2(0x40000000), %bb.3(0x40000000)
-    liveins: $c10, $c12, $c13, $x11
+    liveins: $x10_y, $x12_y, $x13_y, $x11
 
-    renamable $x14 = CLHU renamable $c10, 0 :: (load (s16) from %ir.code, addrspace 200)
+    renamable $x14 = CLHU renamable $x10_y, 0 :: (load (s16) from %ir.code, addrspace 200)
     renamable $x15 = SRLI renamable $x14, 3
-    renamable $c15 = CIncOffset renamable $c12, killed renamable $x15
-    renamable $x15 = CLBU killed renamable $c15, 0 :: (load (s8) from %ir.arrayidx648, addrspace 200)
+    renamable $x15_y = CIncOffset renamable $x12_y, killed renamable $x15
+    renamable $x15 = CLBU killed renamable $x15_y, 0 :: (load (s8) from %ir.arrayidx648, addrspace 200)
     renamable $x14 = ANDI killed renamable $x14, 7
     renamable $x14 = SRLW killed renamable $x15, killed renamable $x14
     renamable $x14 = ANDI killed renamable $x14, 1
@@ -93,23 +93,23 @@ body:             |
 
   bb.2:
     successors: %bb.3(0x80000000)
-    liveins: $c10, $c12, $c13, $x11
+    liveins: $x10_y, $x12_y, $x13_y, $x11
 
-    renamable $x14 = CLHU renamable $c10, 0 :: (load (s16) from %ir.code, addrspace 200)
+    renamable $x14 = CLHU renamable $x10_y, 0 :: (load (s16) from %ir.code, addrspace 200)
     renamable $x15 = SRLI renamable $x14, 3
-    renamable $c15 = CIncOffset renamable $c12, killed renamable $x15
-    renamable $x15 = CLBU killed renamable $c15, 0 :: (load (s8) from %ir.arrayidx908, addrspace 200)
+    renamable $x15_y = CIncOffset renamable $x12_y, killed renamable $x15
+    renamable $x15 = CLBU killed renamable $x15_y, 0 :: (load (s8) from %ir.arrayidx908, addrspace 200)
     renamable $x14 = ANDI killed renamable $x14, 7
     renamable $x14 = SRLW killed renamable $x15, killed renamable $x14
     renamable $x15 = ANDI killed renamable $x14, 1
-    $c14 = CMove $c0
+    $x14_y = CMove $x0_y
 
   bb.3:
     successors: %bb.1(0x80000000)
-    liveins: $c10, $c12, $x11
+    liveins: $x10_y, $x12_y, $x11
 
-    $c14 = CMove $c0
-    $c13 = CMove $c10
+    $x14_y = CMove $x0_y
+    $x13_y = CMove $x10_y
     PseudoCBR %bb.1
 
 ...
@@ -122,45 +122,45 @@ body:             |
 # CHECK: liveins:         []
 # CHECK: body:             |
 # CHECK-NEXT:   bb.0:
-# CHECK-NEXT:     liveins: $c10, $c12, $x11, $c13, $c5
+# CHECK-NEXT:     liveins: $x10_y, $x12_y, $x11, $x13_y, $x5_y
 # CHECK-NEXT: {{  $}}
-# CHECK-NEXT:     renamable $x14 = CLHU renamable $c10, 0
+# CHECK-NEXT:     renamable $x14 = CLHU renamable $x10_y, 0
 # CHECK-NEXT:     renamable $x15 = SRLI renamable $x14, 3
-# CHECK-NEXT:     renamable $c15 = CIncOffset renamable $c12, killed renamable $x15
-# CHECK-NEXT:     renamable $x15 = CLBU killed renamable $c15, 0
+# CHECK-NEXT:     renamable $x15_y = CIncOffset renamable $x12_y, killed renamable $x15
+# CHECK-NEXT:     renamable $x15 = CLBU killed renamable $x15_y, 0
 # CHECK-NEXT:     renamable $x14 = ANDI killed renamable $x14, 7
 # CHECK-NEXT:     renamable $x14 = SRLW killed renamable $x15, killed renamable $x14
 # FIXME: This should not be a JALR:
-# CHECK-NEXT:     $c0 = CJALR $c5, 0
+# CHECK-NEXT:     $x0_y = CJALR $x5_y, 0
 # CHECK-EMPTY:
 # CHECK-NEXT: ...
 
 # ASM-LABEL: pcre2_match_16:
 # ASM:       # %bb.0:
-# ASM-NEXT:    cmove ca3, cnull
-# ASM-NEXT:    cmove ca4, cnull
-# ASM-NEXT:    cincoffset ca2, ca0, 80
+# ASM-NEXT:    cmove a3, zero
+# ASM-NEXT:    cmove a4, zero
+# ASM-NEXT:    cincoffset a2, a0, 80
 # ASM-NEXT:    andi a1, a1, 1
 # ASM-NEXT:    beqz a1, .LBB0_2
 # ASM-NEXT:  .LBB0_1:
-# ASM-NEXT:    ccall ct0, OUTLINED_FUNCTION_0
+# ASM-NEXT:    ccall t0, OUTLINED_FUNCTION_0
 # ASM-NEXT:    andi a4, a4, 1
 # ASM-NEXT:    beqz a4, .LBB0_3
 # ASM-NEXT:  .LBB0_2:
-# ASM-NEXT:    ccall ct0, OUTLINED_FUNCTION_0
+# ASM-NEXT:    ccall t0, OUTLINED_FUNCTION_0
 # ASM-NEXT:    andi a5, a4, 1
-# ASM-NEXT:    cmove ca4, cnull
+# ASM-NEXT:    cmove a4, zero
 # ASM-NEXT:  .LBB0_3:
-# ASM-NEXT:    cmove ca4, cnull
-# ASM-NEXT:    cmove ca3, ca0
+# ASM-NEXT:    cmove a4, zero
+# ASM-NEXT:    cmove a3, a0
 # ASM-NEXT:    j .LBB0_1
 #
 # ASM-LABEL: OUTLINED_FUNCTION_0:
 # ASM:       # %bb.0:
-# ASM-NEXT:    clhu a4, 0(ca0)
+# ASM-NEXT:    clhu a4, 0(a0)
 # ASM-NEXT:    srli a5, a4, 3
-# ASM-NEXT:    cincoffset ca5, ca2, a5
-# ASM-NEXT:    clbu a5, 0(ca5)
+# ASM-NEXT:    cincoffset a5, a2, a5
+# ASM-NEXT:    clbu a5, 0(a5)
 # ASM-NEXT:    andi a4, a4, 7
 # ASM-NEXT:    srlw a4, a5, a4
-# ASM-NEXT:    cjr ct0
+# ASM-NEXT:    cjr t0
diff --git a/llvm/test/CodeGen/RISCV/cheri/machinelicm-capability-pseudos.ll b/llvm/test/CodeGen/RISCV/cheri/machinelicm-capability-pseudos.ll
index 03456bb680743..2e84633e5a16d 100644
--- a/llvm/test/CodeGen/RISCV/cheri/machinelicm-capability-pseudos.ll
+++ b/llvm/test/CodeGen/RISCV/cheri/machinelicm-capability-pseudos.ll
@@ -14,12 +14,12 @@ define void @test_clgc(i32 signext %n) {
 ; RV32I:       # %bb.0: # %entry
 ; RV32I-NEXT:  .LBB0_3: # %entry
 ; RV32I-NEXT:    # Label of block must be emitted
-; RV32I-NEXT:    auipcc ca1, %captab_pcrel_hi(g)
-; RV32I-NEXT:    clc ca1, %pcrel_lo(.LBB0_3)(ca1)
+; RV32I-NEXT:    auipcc a1, %captab_pcrel_hi(g)
+; RV32I-NEXT:    clc a1, %pcrel_lo(.LBB0_3)(a1)
 ; RV32I-NEXT:    li a2, 0
 ; RV32I-NEXT:  .LBB0_1: # %loop
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT:    clw zero, 0(ca1)
+; RV32I-NEXT:    clw zero, 0(a1)
 ; RV32I-NEXT:    addi a2, a2, 1
 ; RV32I-NEXT:    blt a2, a0, .LBB0_1
 ; RV32I-NEXT:  # %bb.2: # %ret
@@ -29,12 +29,12 @@ define void @test_clgc(i32 signext %n) {
 ; RV64I:       # %bb.0: # %entry
 ; RV64I-NEXT:  .LBB0_3: # %entry
 ; RV64I-NEXT:    # Label of block must be emitted
-; RV64I-NEXT:    auipcc ca1, %captab_pcrel_hi(g)
-; RV64I-NEXT:    clc ca1, %pcrel_lo(.LBB0_3)(ca1)
+; RV64I-NEXT:    auipcc a1, %captab_pcrel_hi(g)
+; RV64I-NEXT:    clc a1, %pcrel_lo(.LBB0_3)(a1)
 ; RV64I-NEXT:    li a2, 0
 ; RV64I-NEXT:  .LBB0_1: # %loop
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT:    clw zero, 0(ca1)
+; RV64I-NEXT:    clw zero, 0(a1)
 ; RV64I-NEXT:    addiw a2, a2, 1
 ; RV64I-NEXT:    blt a2, a0, .LBB0_1
 ; RV64I-NEXT:  # %bb.2: # %ret
@@ -61,12 +61,12 @@ define void @test_cla_tls_ie(i32 signext %n) {
 ; RV32I-NEXT:    li a1, 0
 ; RV32I-NEXT:  .LBB1_3: # %entry
 ; RV32I-NEXT:    # Label of block must be emitted
-; RV32I-NEXT:    auipcc ca3, %tls_ie_captab_pcrel_hi(ie)
-; RV32I-NEXT:    clw a2, %pcrel_lo(.LBB1_3)(ca3)
-; RV32I-NEXT:    cincoffset ca2, ctp, a2
+; RV32I-NEXT:    auipcc a3, %tls_ie_captab_pcrel_hi(ie)
+; RV32I-NEXT:    clw a2, %pcrel_lo(.LBB1_3)(a3)
+; RV32I-NEXT:    cincoffset a2, tp, a2
 ; RV32I-NEXT:  .LBB1_1: # %loop
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT:    clw zero, 0(ca2)
+; RV32I-NEXT:    clw zero, 0(a2)
 ; RV32I-NEXT:    addi a1, a1, 1
 ; RV32I-NEXT:    blt a1, a0, .LBB1_1
 ; RV32I-NEXT:  # %bb.2: # %ret
@@ -77,12 +77,12 @@ define void @test_cla_tls_ie(i32 signext %n) {
 ; RV64I-NEXT:    li a1, 0
 ; RV64I-NEXT:  .LBB1_3: # %entry
 ; RV64I-NEXT:    # Label of block must be emitted
-; RV64I-NEXT:    auipcc ca3, %tls_ie_captab_pcrel_hi(ie)
-; RV64I-NEXT:    cld a2, %pcrel_lo(.LBB1_3)(ca3)
-; RV64I-NEXT:    cincoffset ca2, ctp, a2
+; RV64I-NEXT:    auipcc a3, %tls_ie_captab_pcrel_hi(ie)
+; RV64I-NEXT:    cld a2, %pcrel_lo(.LBB1_3)(a3)
+; RV64I-NEXT:    cincoffset a2, tp, a2
 ; RV64I-NEXT:  .LBB1_1: # %loop
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT:    clw zero, 0(ca2)
+; RV64I-NEXT:    clw zero, 0(a2)
 ; RV64I-NEXT:    addiw a1, a1, 1
 ; RV64I-NEXT:    blt a1, a0, .LBB1_1
 ; RV64I-NEXT:  # %bb.2: # %ret
@@ -106,58 +106,58 @@ ret:
 define void @test_clc_tls_gd(i32 signext %n) nounwind {
 ; RV32I-LABEL: test_clc_tls_gd:
 ; RV32I:       # %bb.0: # %entry
-; RV32I-NEXT:    cincoffset csp, csp, -32
-; RV32I-NEXT:    csc cra, 24(csp) # 8-byte Folded Spill
-; RV32I-NEXT:    csc cs0, 16(csp) # 8-byte Folded Spill
-; RV32I-NEXT:    csc cs1, 8(csp) # 8-byte Folded Spill
-; RV32I-NEXT:    csc cs2, 0(csp) # 8-byte Folded Spill
+; RV32I-NEXT:    cincoffset sp, sp, -32
+; RV32I-NEXT:    csc ra, 24(sp) # 8-byte Folded Spill
+; RV32I-NEXT:    csc s0, 16(sp) # 8-byte Folded Spill
+; RV32I-NEXT:    csc s1, 8(sp) # 8-byte Folded Spill
+; RV32I-NEXT:    csc s2, 0(sp) # 8-byte Folded Spill
 ; RV32I-NEXT:    mv s0, a0
 ; RV32I-NEXT:    li s2, 0
 ; RV32I-NEXT:  .LBB2_3: # %entry
 ; RV32I-NEXT:    # Label of block must be emitted
-; RV32I-NEXT:    auipcc cs1, %tls_gd_captab_pcrel_hi(gd)
-; RV32I-NEXT:    cincoffset cs1, cs1, %pcrel_lo(.LBB2_3)
+; RV32I-NEXT:    auipcc s1, %tls_gd_captab_pcrel_hi(gd)
+; RV32I-NEXT:    cincoffset s1, s1, %pcrel_lo(.LBB2_3)
 ; RV32I-NEXT:  .LBB2_1: # %loop
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT:    cmove ca0, cs1
+; RV32I-NEXT:    cmove a0, s1
 ; RV32I-NEXT:    ccall __tls_get_addr
-; RV32I-NEXT:    clw zero, 0(ca0)
+; RV32I-NEXT:    clw zero, 0(a0)
 ; RV32I-NEXT:    addi s2, s2, 1
 ; RV32I-NEXT:    blt s2, s0, .LBB2_1
 ; RV32I-NEXT:  # %bb.2: # %ret
-; RV32I-NEXT:    clc cra, 24(csp) # 8-byte Folded Reload
-; RV32I-NEXT:    clc cs0, 16(csp) # 8-byte Folded Reload
-; RV32I-NEXT:    clc cs1, 8(csp) # 8-byte Folded Reload
-; RV32I-NEXT:    clc cs2, 0(csp) # 8-byte Folded Reload
-; RV32I-NEXT:    cincoffset csp, csp, 32
+; RV32I-NEXT:    clc ra, 24(sp) # 8-byte Folded Reload
+; RV32I-NEXT:    clc s0, 16(sp) # 8-byte Folded Reload
+; RV32I-NEXT:    clc s1, 8(sp) # 8-byte Folded Reload
+; RV32I-NEXT:    clc s2, 0(sp) # 8-byte Folded Reload
+; RV32I-NEXT:    cincoffset sp, sp, 32
 ; RV32I-NEXT:    cret
 ;
 ; RV64I-LABEL: test_clc_tls_gd:
 ; RV64I:       # %bb.0: # %entry
-; RV64I-NEXT:    cincoffset csp, csp, -64
-; RV64I-NEXT:    csc cra, 48(csp) # 16-byte Folded Spill
-; RV64I-NEXT:    csc cs0, 32(csp) # 16-byte Folded Spill
-; RV64I-NEXT:    csc cs1, 16(csp) # 16-byte Folded Spill
-; RV64I-NEXT:    csc cs2, 0(csp) # 16-byte Folded Spill
+; RV64I-NEXT:    cincoffset sp, sp, -64
+; RV64I-NEXT:    csc ra, 48(sp) # 16-byte Folded Spill
+; RV64I-NEXT:    csc s0, 32(sp) # 16-byte Folded Spill
+; RV64I-NEXT:    csc s1, 16(sp) # 16-byte Folded Spill
+; RV64I-NEXT:    csc s2, 0(sp) # 16-byte Folded Spill
 ; RV64I-NEXT:    mv s0, a0
 ; RV64I-NEXT:    li s2, 0
 ; RV64I-NEXT:  .LBB2_3: # %entry
 ; RV64I-NEXT:    # Label of block must be emitted
-; RV64I-NEXT:    auipcc cs1, %tls_gd_captab_pcrel_hi(gd)
-; RV64I-NEXT:    cincoffset cs1, cs1, %pcrel_lo(.LBB2_3)
+; RV64I-NEXT:    auipcc s1, %tls_gd_captab_pcrel_hi(gd)
+; RV64I-NEXT:    cincoffset s1, s1, %pcrel_lo(.LBB2_3)
 ; RV64I-NEXT:  .LBB2_1: # %loop
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT:    cmove ca0, cs1
+; RV64I-NEXT:    cmove a0, s1
 ; RV64I-NEXT:    ccall __tls_get_addr
-; RV64I-NEXT:    clw zero, 0(ca0)
+; RV64I-NEXT:    clw zero, 0(a0)
 ; RV64I-NEXT:    addiw s2, s2, 1
 ; RV64I-NEXT:    blt s2, s0, .LBB2_1
 ; RV64I-NEXT:  # %bb.2: # %ret
-; RV64I-NEXT:    clc cra, 48(csp) # 16-byte Folded Reload
-; RV64I-NEXT:    clc cs0, 32(csp) # 16-byte Folded Reload
-; RV64I-NEXT:    clc cs1, 16(csp) # 16-byte Folded Reload
-; RV64I-NEXT:    clc cs2, 0(csp) # 16-byte Folded Reload
-; RV64I-NEXT:    cincoffset csp, csp, 64
+; RV64I-NEXT:    clc ra, 48(sp) # 16-byte Folded Reload
+; RV64I-NEXT:    clc s0, 32(sp) # 16-byte Folded Reload
+; RV64I-NEXT:    clc s1, 16(sp) # 16-byte Folded Reload
+; RV64I-NEXT:    clc s2, 0(sp) # 16-byte Folded Reload
+; RV64I-NEXT:    cincoffset sp, sp, 64
 ; RV64I-NEXT:    cret
 entry:
   br label %loop
diff --git a/llvm/test/CodeGen/RISCV/cheri/machinelicm-hoist.mir b/llvm/test/CodeGen/RISCV/cheri/machinelicm-hoist.mir
index a29c3b352229d..d756c56ffc1dc 100644
--- a/llvm/test/CodeGen/RISCV/cheri/machinelicm-hoist.mir
+++ b/llvm/test/CodeGen/RISCV/cheri/machinelicm-hoist.mir
@@ -44,12 +44,12 @@ tracksRegLiveness: true
 hasWinCFI:       false
 registers:
   - { id: 0, class: gpr, preferred-register: '' }
-  - { id: 1, class: gpcr, preferred-register: '' }
-  - { id: 2, class: gpcr, preferred-register: '' }
+  - { id: 1, class: ygpr, preferred-register: '' }
+  - { id: 2, class: ygpr, preferred-register: '' }
 liveins:
   - { reg: '$x10', virtual-reg: '%0' }
-  - { reg: '$c11', virtual-reg: '%1' }
-  - { reg: '$c11', virtual-reg: '%2' }
+  - { reg: '$x11_y', virtual-reg: '%1' }
+  - { reg: '$x11_y', virtual-reg: '%2' }
 frameInfo:
   isFrameAddressTaken: false
   isReturnAddressTaken: false
@@ -78,16 +78,16 @@ body:             |
   ; CHECK-LABEL: name: hoist_csetbounds
   ; CHECK: bb.0.entry:
   ; CHECK-NEXT:   successors: %bb.2(0x80000000)
-  ; CHECK-NEXT:   liveins: $x10, $c11, $c12
+  ; CHECK-NEXT:   liveins: $x10, $x11_y, $x12_y
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr = COPY $x10
-  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpcr = COPY $c11
-  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:gpcr = COPY $c12
-  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:gpcrc0isddc = COPY $c12
-  ; CHECK-NEXT:   [[CIncOffsetImm:%[0-9]+]]:gpcr = CIncOffsetImm [[COPY1]], 4
-  ; CHECK-NEXT:   [[COPY4:%[0-9]+]]:gpcrc0isddc = COPY [[CIncOffsetImm]]
-  ; CHECK-NEXT:   [[CAndPerm:%[0-9]+]]:gpcr = CAndPerm [[COPY1]], [[COPY]]
-  ; CHECK-NEXT:   [[COPY5:%[0-9]+]]:gpcrc0isddc = COPY [[CAndPerm]]
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:ygpr = COPY $x11_y
+  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:ygpr = COPY $x12_y
+  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:ygprc0isddc = COPY $x12_y
+  ; CHECK-NEXT:   [[CIncOffsetImm:%[0-9]+]]:ygpr = CIncOffsetImm [[COPY1]], 4
+  ; CHECK-NEXT:   [[COPY4:%[0-9]+]]:ygprc0isddc = COPY [[CIncOffsetImm]]
+  ; CHECK-NEXT:   [[CAndPerm:%[0-9]+]]:ygpr = CAndPerm [[COPY1]], [[COPY]]
+  ; CHECK-NEXT:   [[COPY5:%[0-9]+]]:ygprc0isddc = COPY [[CAndPerm]]
   ; CHECK-NEXT:   [[CGetPerm:%[0-9]+]]:gpr = CGetPerm [[COPY2]]
   ; CHECK-NEXT:   [[CGetType:%[0-9]+]]:gpr = CGetType [[COPY2]]
   ; CHECK-NEXT:   [[CGetBase:%[0-9]+]]:gpr = CGetBase [[COPY2]]
@@ -96,34 +96,34 @@ body:             |
   ; CHECK-NEXT:   [[CGetOffset:%[0-9]+]]:gpr = CGetOffset [[COPY2]]
   ; CHECK-NEXT:   [[PseudoCGetAddr:%[0-9]+]]:gpr = PseudoCGetAddr [[COPY2]]
   ; CHECK-NEXT:   [[CGetHigh:%[0-9]+]]:gpr = CGetHigh [[COPY2]]
-  ; CHECK-NEXT:   [[CClearTag:%[0-9]+]]:gpcr = CClearTag [[COPY1]]
-  ; CHECK-NEXT:   [[CMove:%[0-9]+]]:gpcr = CMove [[COPY1]]
+  ; CHECK-NEXT:   [[CClearTag:%[0-9]+]]:ygpr = CClearTag [[COPY1]]
+  ; CHECK-NEXT:   [[CMove:%[0-9]+]]:ygpr = CMove [[COPY1]]
   ; CHECK-NEXT:   [[CTestSubset:%[0-9]+]]:gpr = CTestSubset [[COPY3]], [[COPY2]]
   ; CHECK-NEXT:   [[CRRL:%[0-9]+]]:gpr = CRRL [[COPY]]
   ; CHECK-NEXT:   [[CRAM:%[0-9]+]]:gpr = CRAM [[COPY]]
-  ; CHECK-NEXT:   [[CAndPerm1:%[0-9]+]]:gpcr = CAndPerm [[CIncOffsetImm]], [[COPY]]
-  ; CHECK-NEXT:   [[CSetFlags:%[0-9]+]]:gpcr = CSetFlags [[CIncOffsetImm]], [[COPY]]
-  ; CHECK-NEXT:   [[CSetOffset:%[0-9]+]]:gpcr = CSetOffset [[CIncOffsetImm]], [[COPY]]
-  ; CHECK-NEXT:   [[CSetAddr:%[0-9]+]]:gpcr = CSetAddr [[CIncOffsetImm]], [[COPY]]
-  ; CHECK-NEXT:   [[CIncOffset:%[0-9]+]]:gpcr = CIncOffset [[CIncOffsetImm]], [[COPY]]
-  ; CHECK-NEXT:   [[CIncOffsetImm1:%[0-9]+]]:gpcr = CIncOffsetImm [[CIncOffsetImm]], 10
-  ; CHECK-NEXT:   [[CClearTag1:%[0-9]+]]:gpcr = CClearTag [[CIncOffsetImm]]
-  ; CHECK-NEXT:   [[CSetHigh:%[0-9]+]]:gpcr = CSetHigh [[CIncOffsetImm]], [[COPY]]
-  ; CHECK-NEXT:   [[CAndPerm2:%[0-9]+]]:gpcr = CAndPerm [[CAndPerm]], [[COPY]]
-  ; CHECK-NEXT:   [[CSetFlags1:%[0-9]+]]:gpcr = CSetFlags [[CAndPerm]], [[COPY]]
-  ; CHECK-NEXT:   [[CSetOffset1:%[0-9]+]]:gpcr = CSetOffset [[CAndPerm]], [[COPY]]
-  ; CHECK-NEXT:   [[CSetAddr1:%[0-9]+]]:gpcr = CSetAddr [[CAndPerm]], [[COPY]]
-  ; CHECK-NEXT:   [[CIncOffset1:%[0-9]+]]:gpcr = CIncOffset [[CAndPerm]], [[COPY]]
-  ; CHECK-NEXT:   [[CIncOffsetImm2:%[0-9]+]]:gpcr = CIncOffsetImm [[CAndPerm]], 10
-  ; CHECK-NEXT:   [[CClearTag2:%[0-9]+]]:gpcr = CClearTag [[CAndPerm]]
-  ; CHECK-NEXT:   [[CAndPerm3:%[0-9]+]]:gpcr = CAndPerm $c0, [[COPY]]
-  ; CHECK-NEXT:   [[CSetFlags2:%[0-9]+]]:gpcr = CSetFlags $c0, [[COPY]]
-  ; CHECK-NEXT:   [[CSetOffset2:%[0-9]+]]:gpcr = CSetOffset $c0, [[COPY]]
-  ; CHECK-NEXT:   [[CSetAddr2:%[0-9]+]]:gpcr = CSetAddr $c0, [[COPY]]
-  ; CHECK-NEXT:   [[CIncOffset2:%[0-9]+]]:gpcr = CIncOffset $c0, [[COPY]]
-  ; CHECK-NEXT:   [[CIncOffsetImm3:%[0-9]+]]:gpcr = CIncOffsetImm $c0, 10
-  ; CHECK-NEXT:   [[CClearTag3:%[0-9]+]]:gpcr = CClearTag $c0
-  ; CHECK-NEXT:   [[CSetHigh1:%[0-9]+]]:gpcr = CSetHigh $c0, [[COPY]]
+  ; CHECK-NEXT:   [[CAndPerm1:%[0-9]+]]:ygpr = CAndPerm [[CIncOffsetImm]], [[COPY]]
+  ; CHECK-NEXT:   [[CSetFlags:%[0-9]+]]:ygpr = CSetFlags [[CIncOffsetImm]], [[COPY]]
+  ; CHECK-NEXT:   [[CSetOffset:%[0-9]+]]:ygpr = CSetOffset [[CIncOffsetImm]], [[COPY]]
+  ; CHECK-NEXT:   [[CSetAddr:%[0-9]+]]:ygpr = CSetAddr [[CIncOffsetImm]], [[COPY]]
+  ; CHECK-NEXT:   [[CIncOffset:%[0-9]+]]:ygpr = CIncOffset [[CIncOffsetImm]], [[COPY]]
+  ; CHECK-NEXT:   [[CIncOffsetImm1:%[0-9]+]]:ygpr = CIncOffsetImm [[CIncOffsetImm]], 10
+  ; CHECK-NEXT:   [[CClearTag1:%[0-9]+]]:ygpr = CClearTag [[CIncOffsetImm]]
+  ; CHECK-NEXT:   [[CSetHigh:%[0-9]+]]:ygpr = CSetHigh [[CIncOffsetImm]], [[COPY]]
+  ; CHECK-NEXT:   [[CAndPerm2:%[0-9]+]]:ygpr = CAndPerm [[CAndPerm]], [[COPY]]
+  ; CHECK-NEXT:   [[CSetFlags1:%[0-9]+]]:ygpr = CSetFlags [[CAndPerm]], [[COPY]]
+  ; CHECK-NEXT:   [[CSetOffset1:%[0-9]+]]:ygpr = CSetOffset [[CAndPerm]], [[COPY]]
+  ; CHECK-NEXT:   [[CSetAddr1:%[0-9]+]]:ygpr = CSetAddr [[CAndPerm]], [[COPY]]
+  ; CHECK-NEXT:   [[CIncOffset1:%[0-9]+]]:ygpr = CIncOffset [[CAndPerm]], [[COPY]]
+  ; CHECK-NEXT:   [[CIncOffsetImm2:%[0-9]+]]:ygpr = CIncOffsetImm [[CAndPerm]], 10
+  ; CHECK-NEXT:   [[CClearTag2:%[0-9]+]]:ygpr = CClearTag [[CAndPerm]]
+  ; CHECK-NEXT:   [[CAndPerm3:%[0-9]+]]:ygpr = CAndPerm $x0_y, [[COPY]]
+  ; CHECK-NEXT:   [[CSetFlags2:%[0-9]+]]:ygpr = CSetFlags $x0_y, [[COPY]]
+  ; CHECK-NEXT:   [[CSetOffset2:%[0-9]+]]:ygpr = CSetOffset $x0_y, [[COPY]]
+  ; CHECK-NEXT:   [[CSetAddr2:%[0-9]+]]:ygpr = CSetAddr $x0_y, [[COPY]]
+  ; CHECK-NEXT:   [[CIncOffset2:%[0-9]+]]:ygpr = CIncOffset $x0_y, [[COPY]]
+  ; CHECK-NEXT:   [[CIncOffsetImm3:%[0-9]+]]:ygpr = CIncOffsetImm $x0_y, 10
+  ; CHECK-NEXT:   [[CClearTag3:%[0-9]+]]:ygpr = CClearTag $x0_y
+  ; CHECK-NEXT:   [[CSetHigh1:%[0-9]+]]:ygpr = CSetHigh $x0_y, [[COPY]]
   ; CHECK-NEXT:   PseudoBR %bb.2
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.1.for.cond.cleanup:
@@ -139,53 +139,53 @@ body:             |
   ; CHECK-NEXT:   successors: %bb.4(0x80000000)
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   [[CGetTag:%[0-9]+]]:gpr = CGetTag [[COPY2]]
-  ; CHECK-NEXT:   [[CSeal:%[0-9]+]]:gpcr = CSeal [[COPY1]], [[COPY2]]
-  ; CHECK-NEXT:   [[CUnseal:%[0-9]+]]:gpcr = CUnseal [[COPY1]], [[COPY2]]
-  ; CHECK-NEXT:   [[CAndPerm4:%[0-9]+]]:gpcr = CAndPerm [[COPY1]], [[COPY]]
-  ; CHECK-NEXT:   [[CSetFlags3:%[0-9]+]]:gpcr = CSetFlags [[COPY1]], [[COPY]]
-  ; CHECK-NEXT:   [[CSetOffset3:%[0-9]+]]:gpcr = CSetOffset [[COPY1]], [[COPY]]
-  ; CHECK-NEXT:   [[CSetAddr3:%[0-9]+]]:gpcr = CSetAddr [[COPY1]], [[COPY]]
-  ; CHECK-NEXT:   [[CIncOffset3:%[0-9]+]]:gpcr = CIncOffset [[COPY1]], [[COPY]]
-  ; CHECK-NEXT:   [[CIncOffsetImm4:%[0-9]+]]:gpcr = CIncOffsetImm [[COPY1]], 10
-  ; CHECK-NEXT:   [[CSetBounds:%[0-9]+]]:gpcr = CSetBounds [[COPY1]], [[COPY]]
-  ; CHECK-NEXT:   [[CSetBoundsExact:%[0-9]+]]:gpcr = CSetBoundsExact [[COPY1]], [[COPY]]
-  ; CHECK-NEXT:   [[CSetBoundsImm:%[0-9]+]]:gpcr = CSetBoundsImm [[COPY1]], 10
-  ; CHECK-NEXT:   [[CBuildCap:%[0-9]+]]:gpcr = CBuildCap [[COPY3]], [[COPY2]]
-  ; CHECK-NEXT:   [[CCopyType:%[0-9]+]]:gpcr = CCopyType [[COPY1]], [[COPY2]]
-  ; CHECK-NEXT:   [[CCSeal:%[0-9]+]]:gpcr = CCSeal [[COPY1]], [[COPY2]]
-  ; CHECK-NEXT:   [[CSealEntry:%[0-9]+]]:gpcr = CSealEntry [[COPY1]]
-  ; CHECK-NEXT:   [[CSetHigh2:%[0-9]+]]:gpcr = CSetHigh [[COPY1]], [[COPY]]
+  ; CHECK-NEXT:   [[CSeal:%[0-9]+]]:ygpr = CSeal [[COPY1]], [[COPY2]]
+  ; CHECK-NEXT:   [[CUnseal:%[0-9]+]]:ygpr = CUnseal [[COPY1]], [[COPY2]]
+  ; CHECK-NEXT:   [[CAndPerm4:%[0-9]+]]:ygpr = CAndPerm [[COPY1]], [[COPY]]
+  ; CHECK-NEXT:   [[CSetFlags3:%[0-9]+]]:ygpr = CSetFlags [[COPY1]], [[COPY]]
+  ; CHECK-NEXT:   [[CSetOffset3:%[0-9]+]]:ygpr = CSetOffset [[COPY1]], [[COPY]]
+  ; CHECK-NEXT:   [[CSetAddr3:%[0-9]+]]:ygpr = CSetAddr [[COPY1]], [[COPY]]
+  ; CHECK-NEXT:   [[CIncOffset3:%[0-9]+]]:ygpr = CIncOffset [[COPY1]], [[COPY]]
+  ; CHECK-NEXT:   [[CIncOffsetImm4:%[0-9]+]]:ygpr = CIncOffsetImm [[COPY1]], 10
+  ; CHECK-NEXT:   [[CSetBounds:%[0-9]+]]:ygpr = CSetBounds [[COPY1]], [[COPY]]
+  ; CHECK-NEXT:   [[CSetBoundsExact:%[0-9]+]]:ygpr = CSetBoundsExact [[COPY1]], [[COPY]]
+  ; CHECK-NEXT:   [[CSetBoundsImm:%[0-9]+]]:ygpr = CSetBoundsImm [[COPY1]], 10
+  ; CHECK-NEXT:   [[CBuildCap:%[0-9]+]]:ygpr = CBuildCap [[COPY3]], [[COPY2]]
+  ; CHECK-NEXT:   [[CCopyType:%[0-9]+]]:ygpr = CCopyType [[COPY1]], [[COPY2]]
+  ; CHECK-NEXT:   [[CCSeal:%[0-9]+]]:ygpr = CCSeal [[COPY1]], [[COPY2]]
+  ; CHECK-NEXT:   [[CSealEntry:%[0-9]+]]:ygpr = CSealEntry [[COPY1]]
+  ; CHECK-NEXT:   [[CSetHigh2:%[0-9]+]]:ygpr = CSetHigh [[COPY1]], [[COPY]]
   ; CHECK-NEXT:   [[CToPtr:%[0-9]+]]:gpr = CToPtr [[COPY1]], [[COPY3]]
-  ; CHECK-NEXT:   [[CFromPtr:%[0-9]+]]:gpcr = CFromPtr [[COPY3]], [[COPY]]
-  ; CHECK-NEXT:   [[CSpecialRW:%[0-9]+]]:gpcr = CSpecialRW 0, [[COPY1]]
+  ; CHECK-NEXT:   [[CFromPtr:%[0-9]+]]:ygpr = CFromPtr [[COPY3]], [[COPY]]
+  ; CHECK-NEXT:   [[CSpecialRW:%[0-9]+]]:ygpr = CSpecialRW 0, [[COPY1]]
   ; CHECK-NEXT:   CClear 1, 1
   ; CHECK-NEXT:   FPClear 1, 1
-  ; CHECK-NEXT:   [[CSeal1:%[0-9]+]]:gpcr = CSeal [[CIncOffsetImm]], [[COPY2]]
-  ; CHECK-NEXT:   [[CUnseal1:%[0-9]+]]:gpcr = CUnseal [[CIncOffsetImm]], [[COPY2]]
-  ; CHECK-NEXT:   [[CSetBounds1:%[0-9]+]]:gpcr = CSetBounds [[CIncOffsetImm]], [[COPY]]
-  ; CHECK-NEXT:   [[CSetBoundsExact1:%[0-9]+]]:gpcr = CSetBoundsExact [[CIncOffsetImm]], [[COPY]]
-  ; CHECK-NEXT:   [[CSetBoundsImm1:%[0-9]+]]:gpcr = CSetBoundsImm [[CIncOffsetImm]], 10
-  ; CHECK-NEXT:   [[CBuildCap1:%[0-9]+]]:gpcr = CBuildCap [[COPY4]], [[COPY2]]
-  ; CHECK-NEXT:   [[CCopyType1:%[0-9]+]]:gpcr = CCopyType [[CIncOffsetImm]], [[COPY2]]
-  ; CHECK-NEXT:   [[CCSeal1:%[0-9]+]]:gpcr = CCSeal [[CIncOffsetImm]], [[COPY2]]
-  ; CHECK-NEXT:   [[CSealEntry1:%[0-9]+]]:gpcr = CSealEntry [[CIncOffsetImm]]
-  ; CHECK-NEXT:   [[CSeal2:%[0-9]+]]:gpcr = CSeal [[CAndPerm]], [[COPY2]]
-  ; CHECK-NEXT:   [[CUnseal2:%[0-9]+]]:gpcr = CUnseal [[CAndPerm]], [[COPY2]]
-  ; CHECK-NEXT:   [[CSetBounds2:%[0-9]+]]:gpcr = CSetBounds [[CAndPerm]], [[COPY]]
-  ; CHECK-NEXT:   [[CSetBoundsExact2:%[0-9]+]]:gpcr = CSetBoundsExact [[CAndPerm]], [[COPY]]
-  ; CHECK-NEXT:   [[CSetBoundsImm2:%[0-9]+]]:gpcr = CSetBoundsImm [[CAndPerm]], 10
-  ; CHECK-NEXT:   [[CBuildCap2:%[0-9]+]]:gpcr = CBuildCap [[COPY5]], [[COPY2]]
-  ; CHECK-NEXT:   [[CCopyType2:%[0-9]+]]:gpcr = CCopyType [[CAndPerm]], [[COPY2]]
-  ; CHECK-NEXT:   [[CCSeal2:%[0-9]+]]:gpcr = CCSeal [[CAndPerm]], [[COPY2]]
-  ; CHECK-NEXT:   [[CSealEntry2:%[0-9]+]]:gpcr = CSealEntry [[CIncOffsetImm]]
-  ; CHECK-NEXT:   [[CSeal3:%[0-9]+]]:gpcr = CSeal $c0, [[COPY2]]
-  ; CHECK-NEXT:   [[CUnseal3:%[0-9]+]]:gpcr = CUnseal $c0, [[COPY2]]
-  ; CHECK-NEXT:   [[CSetBounds3:%[0-9]+]]:gpcr = CSetBounds $c0, [[COPY]]
-  ; CHECK-NEXT:   [[CSetBoundsExact3:%[0-9]+]]:gpcr = CSetBoundsExact $c0, [[COPY]]
-  ; CHECK-NEXT:   [[CSetBoundsImm3:%[0-9]+]]:gpcr = CSetBoundsImm $c0, 10
-  ; CHECK-NEXT:   [[CCopyType3:%[0-9]+]]:gpcr = CCopyType $c0, [[COPY2]]
-  ; CHECK-NEXT:   [[CCSeal3:%[0-9]+]]:gpcr = CCSeal $c0, [[COPY2]]
-  ; CHECK-NEXT:   [[CSealEntry3:%[0-9]+]]:gpcr = CSealEntry $c0
+  ; CHECK-NEXT:   [[CSeal1:%[0-9]+]]:ygpr = CSeal [[CIncOffsetImm]], [[COPY2]]
+  ; CHECK-NEXT:   [[CUnseal1:%[0-9]+]]:ygpr = CUnseal [[CIncOffsetImm]], [[COPY2]]
+  ; CHECK-NEXT:   [[CSetBounds1:%[0-9]+]]:ygpr = CSetBounds [[CIncOffsetImm]], [[COPY]]
+  ; CHECK-NEXT:   [[CSetBoundsExact1:%[0-9]+]]:ygpr = CSetBoundsExact [[CIncOffsetImm]], [[COPY]]
+  ; CHECK-NEXT:   [[CSetBoundsImm1:%[0-9]+]]:ygpr = CSetBoundsImm [[CIncOffsetImm]], 10
+  ; CHECK-NEXT:   [[CBuildCap1:%[0-9]+]]:ygpr = CBuildCap [[COPY4]], [[COPY2]]
+  ; CHECK-NEXT:   [[CCopyType1:%[0-9]+]]:ygpr = CCopyType [[CIncOffsetImm]], [[COPY2]]
+  ; CHECK-NEXT:   [[CCSeal1:%[0-9]+]]:ygpr = CCSeal [[CIncOffsetImm]], [[COPY2]]
+  ; CHECK-NEXT:   [[CSealEntry1:%[0-9]+]]:ygpr = CSealEntry [[CIncOffsetImm]]
+  ; CHECK-NEXT:   [[CSeal2:%[0-9]+]]:ygpr = CSeal [[CAndPerm]], [[COPY2]]
+  ; CHECK-NEXT:   [[CUnseal2:%[0-9]+]]:ygpr = CUnseal [[CAndPerm]], [[COPY2]]
+  ; CHECK-NEXT:   [[CSetBounds2:%[0-9]+]]:ygpr = CSetBounds [[CAndPerm]], [[COPY]]
+  ; CHECK-NEXT:   [[CSetBoundsExact2:%[0-9]+]]:ygpr = CSetBoundsExact [[CAndPerm]], [[COPY]]
+  ; CHECK-NEXT:   [[CSetBoundsImm2:%[0-9]+]]:ygpr = CSetBoundsImm [[CAndPerm]], 10
+  ; CHECK-NEXT:   [[CBuildCap2:%[0-9]+]]:ygpr = CBuildCap [[COPY5]], [[COPY2]]
+  ; CHECK-NEXT:   [[CCopyType2:%[0-9]+]]:ygpr = CCopyType [[CAndPerm]], [[COPY2]]
+  ; CHECK-NEXT:   [[CCSeal2:%[0-9]+]]:ygpr = CCSeal [[CAndPerm]], [[COPY2]]
+  ; CHECK-NEXT:   [[CSealEntry2:%[0-9]+]]:ygpr = CSealEntry [[CIncOffsetImm]]
+  ; CHECK-NEXT:   [[CSeal3:%[0-9]+]]:ygpr = CSeal $x0_y, [[COPY2]]
+  ; CHECK-NEXT:   [[CUnseal3:%[0-9]+]]:ygpr = CUnseal $x0_y, [[COPY2]]
+  ; CHECK-NEXT:   [[CSetBounds3:%[0-9]+]]:ygpr = CSetBounds $x0_y, [[COPY]]
+  ; CHECK-NEXT:   [[CSetBoundsExact3:%[0-9]+]]:ygpr = CSetBoundsExact $x0_y, [[COPY]]
+  ; CHECK-NEXT:   [[CSetBoundsImm3:%[0-9]+]]:ygpr = CSetBoundsImm $x0_y, 10
+  ; CHECK-NEXT:   [[CCopyType3:%[0-9]+]]:ygpr = CCopyType $x0_y, [[COPY2]]
+  ; CHECK-NEXT:   [[CCSeal3:%[0-9]+]]:ygpr = CCSeal $x0_y, [[COPY2]]
+  ; CHECK-NEXT:   [[CSealEntry3:%[0-9]+]]:ygpr = CSealEntry $x0_y
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.4.for.inc:
   ; CHECK-NEXT:   successors: %bb.2(0x7c000000), %bb.1(0x04000000)
@@ -196,16 +196,16 @@ body:             |
   ; TAG-CLEAR-LABEL: name: hoist_csetbounds
   ; TAG-CLEAR: bb.0.entry:
   ; TAG-CLEAR-NEXT:   successors: %bb.2(0x80000000)
-  ; TAG-CLEAR-NEXT:   liveins: $x10, $c11, $c12
+  ; TAG-CLEAR-NEXT:   liveins: $x10, $x11_y, $x12_y
   ; TAG-CLEAR-NEXT: {{  $}}
   ; TAG-CLEAR-NEXT:   [[COPY:%[0-9]+]]:gpr = COPY $x10
-  ; TAG-CLEAR-NEXT:   [[COPY1:%[0-9]+]]:gpcr = COPY $c11
-  ; TAG-CLEAR-NEXT:   [[COPY2:%[0-9]+]]:gpcr = COPY $c12
-  ; TAG-CLEAR-NEXT:   [[COPY3:%[0-9]+]]:gpcrc0isddc = COPY $c12
-  ; TAG-CLEAR-NEXT:   [[CIncOffsetImm:%[0-9]+]]:gpcr = CIncOffsetImm [[COPY1]], 4
-  ; TAG-CLEAR-NEXT:   [[COPY4:%[0-9]+]]:gpcrc0isddc = COPY [[CIncOffsetImm]]
-  ; TAG-CLEAR-NEXT:   [[CAndPerm:%[0-9]+]]:gpcr = CAndPerm [[COPY1]], [[COPY]]
-  ; TAG-CLEAR-NEXT:   [[COPY5:%[0-9]+]]:gpcrc0isddc = COPY [[CAndPerm]]
+  ; TAG-CLEAR-NEXT:   [[COPY1:%[0-9]+]]:ygpr = COPY $x11_y
+  ; TAG-CLEAR-NEXT:   [[COPY2:%[0-9]+]]:ygpr = COPY $x12_y
+  ; TAG-CLEAR-NEXT:   [[COPY3:%[0-9]+]]:ygprx0isddc = COPY $x12_y
+  ; TAG-CLEAR-NEXT:   [[CIncOffsetImm:%[0-9]+]]:ygpr = CIncOffsetImm [[COPY1]], 4
+  ; TAG-CLEAR-NEXT:   [[COPY4:%[0-9]+]]:ygprx0isddc = COPY [[CIncOffsetImm]]
+  ; TAG-CLEAR-NEXT:   [[CAndPerm:%[0-9]+]]:ygpr = CAndPerm [[COPY1]], [[COPY]]
+  ; TAG-CLEAR-NEXT:   [[COPY5:%[0-9]+]]:ygprx0isddc = COPY [[CAndPerm]]
   ; TAG-CLEAR-NEXT:   [[CGetPerm:%[0-9]+]]:gpr = CGetPerm [[COPY2]]
   ; TAG-CLEAR-NEXT:   [[CGetType:%[0-9]+]]:gpr = CGetType [[COPY2]]
   ; TAG-CLEAR-NEXT:   [[CGetBase:%[0-9]+]]:gpr = CGetBase [[COPY2]]
@@ -214,74 +214,74 @@ body:             |
   ; TAG-CLEAR-NEXT:   [[CGetOffset:%[0-9]+]]:gpr = CGetOffset [[COPY2]]
   ; TAG-CLEAR-NEXT:   [[PseudoCGetAddr:%[0-9]+]]:gpr = PseudoCGetAddr [[COPY2]]
   ; TAG-CLEAR-NEXT:   [[CGetHigh:%[0-9]+]]:gpr = CGetHigh [[COPY2]]
-  ; TAG-CLEAR-NEXT:   [[CSeal:%[0-9]+]]:gpcr = CSeal [[COPY1]], [[COPY2]]
-  ; TAG-CLEAR-NEXT:   [[CUnseal:%[0-9]+]]:gpcr = CUnseal [[COPY1]], [[COPY2]]
-  ; TAG-CLEAR-NEXT:   [[CSetFlags:%[0-9]+]]:gpcr = CSetFlags [[COPY1]], [[COPY]]
-  ; TAG-CLEAR-NEXT:   [[CSetOffset:%[0-9]+]]:gpcr = CSetOffset [[COPY1]], [[COPY]]
-  ; TAG-CLEAR-NEXT:   [[CSetAddr:%[0-9]+]]:gpcr = CSetAddr [[COPY1]], [[COPY]]
-  ; TAG-CLEAR-NEXT:   [[CIncOffset:%[0-9]+]]:gpcr = CIncOffset [[COPY1]], [[COPY]]
-  ; TAG-CLEAR-NEXT:   [[CIncOffsetImm1:%[0-9]+]]:gpcr = CIncOffsetImm [[COPY1]], 10
-  ; TAG-CLEAR-NEXT:   [[CSetBounds:%[0-9]+]]:gpcr = CSetBounds [[COPY1]], [[COPY]]
-  ; TAG-CLEAR-NEXT:   [[CSetBoundsExact:%[0-9]+]]:gpcr = CSetBoundsExact [[COPY1]], [[COPY]]
-  ; TAG-CLEAR-NEXT:   [[CSetBoundsImm:%[0-9]+]]:gpcr = CSetBoundsImm [[COPY1]], 10
-  ; TAG-CLEAR-NEXT:   [[CClearTag:%[0-9]+]]:gpcr = CClearTag [[COPY1]]
-  ; TAG-CLEAR-NEXT:   [[CBuildCap:%[0-9]+]]:gpcr = CBuildCap [[COPY3]], [[COPY2]]
-  ; TAG-CLEAR-NEXT:   [[CCopyType:%[0-9]+]]:gpcr = CCopyType [[COPY1]], [[COPY2]]
-  ; TAG-CLEAR-NEXT:   [[CCSeal:%[0-9]+]]:gpcr = CCSeal [[COPY1]], [[COPY2]]
-  ; TAG-CLEAR-NEXT:   [[CSealEntry:%[0-9]+]]:gpcr = CSealEntry [[COPY1]]
-  ; TAG-CLEAR-NEXT:   [[CSetHigh:%[0-9]+]]:gpcr = CSetHigh [[COPY1]], [[COPY]]
-  ; TAG-CLEAR-NEXT:   [[CMove:%[0-9]+]]:gpcr = CMove [[COPY1]]
+  ; TAG-CLEAR-NEXT:   [[CSeal:%[0-9]+]]:ygpr = CSeal [[COPY1]], [[COPY2]]
+  ; TAG-CLEAR-NEXT:   [[CUnseal:%[0-9]+]]:ygpr = CUnseal [[COPY1]], [[COPY2]]
+  ; TAG-CLEAR-NEXT:   [[CSetFlags:%[0-9]+]]:ygpr = CSetFlags [[COPY1]], [[COPY]]
+  ; TAG-CLEAR-NEXT:   [[CSetOffset:%[0-9]+]]:ygpr = CSetOffset [[COPY1]], [[COPY]]
+  ; TAG-CLEAR-NEXT:   [[CSetAddr:%[0-9]+]]:ygpr = CSetAddr [[COPY1]], [[COPY]]
+  ; TAG-CLEAR-NEXT:   [[CIncOffset:%[0-9]+]]:ygpr = CIncOffset [[COPY1]], [[COPY]]
+  ; TAG-CLEAR-NEXT:   [[CIncOffsetImm1:%[0-9]+]]:ygpr = CIncOffsetImm [[COPY1]], 10
+  ; TAG-CLEAR-NEXT:   [[CSetBounds:%[0-9]+]]:ygpr = CSetBounds [[COPY1]], [[COPY]]
+  ; TAG-CLEAR-NEXT:   [[CSetBoundsExact:%[0-9]+]]:ygpr = CSetBoundsExact [[COPY1]], [[COPY]]
+  ; TAG-CLEAR-NEXT:   [[CSetBoundsImm:%[0-9]+]]:ygpr = CSetBoundsImm [[COPY1]], 10
+  ; TAG-CLEAR-NEXT:   [[CClearTag:%[0-9]+]]:ygpr = CClearTag [[COPY1]]
+  ; TAG-CLEAR-NEXT:   [[CBuildCap:%[0-9]+]]:ygpr = CBuildCap [[COPY3]], [[COPY2]]
+  ; TAG-CLEAR-NEXT:   [[CCopyType:%[0-9]+]]:ygpr = CCopyType [[COPY1]], [[COPY2]]
+  ; TAG-CLEAR-NEXT:   [[CCSeal:%[0-9]+]]:ygpr = CCSeal [[COPY1]], [[COPY2]]
+  ; TAG-CLEAR-NEXT:   [[CSealEntry:%[0-9]+]]:ygpr = CSealEntry [[COPY1]]
+  ; TAG-CLEAR-NEXT:   [[CSetHigh:%[0-9]+]]:ygpr = CSetHigh [[COPY1]], [[COPY]]
+  ; TAG-CLEAR-NEXT:   [[CMove:%[0-9]+]]:ygpr = CMove [[COPY1]]
   ; TAG-CLEAR-NEXT:   [[CTestSubset:%[0-9]+]]:gpr = CTestSubset [[COPY3]], [[COPY2]]
   ; TAG-CLEAR-NEXT:   [[CRRL:%[0-9]+]]:gpr = CRRL [[COPY]]
   ; TAG-CLEAR-NEXT:   [[CRAM:%[0-9]+]]:gpr = CRAM [[COPY]]
-  ; TAG-CLEAR-NEXT:   [[CSeal1:%[0-9]+]]:gpcr = CSeal [[CIncOffsetImm]], [[COPY2]]
-  ; TAG-CLEAR-NEXT:   [[CUnseal1:%[0-9]+]]:gpcr = CUnseal [[CIncOffsetImm]], [[COPY2]]
-  ; TAG-CLEAR-NEXT:   [[CAndPerm1:%[0-9]+]]:gpcr = CAndPerm [[CIncOffsetImm]], [[COPY]]
-  ; TAG-CLEAR-NEXT:   [[CSetFlags1:%[0-9]+]]:gpcr = CSetFlags [[CIncOffsetImm]], [[COPY]]
-  ; TAG-CLEAR-NEXT:   [[CSetOffset1:%[0-9]+]]:gpcr = CSetOffset [[CIncOffsetImm]], [[COPY]]
-  ; TAG-CLEAR-NEXT:   [[CSetAddr1:%[0-9]+]]:gpcr = CSetAddr [[CIncOffsetImm]], [[COPY]]
-  ; TAG-CLEAR-NEXT:   [[CIncOffset1:%[0-9]+]]:gpcr = CIncOffset [[CIncOffsetImm]], [[COPY]]
-  ; TAG-CLEAR-NEXT:   [[CIncOffsetImm2:%[0-9]+]]:gpcr = CIncOffsetImm [[CIncOffsetImm]], 10
-  ; TAG-CLEAR-NEXT:   [[CSetBounds1:%[0-9]+]]:gpcr = CSetBounds [[CIncOffsetImm]], [[COPY]]
-  ; TAG-CLEAR-NEXT:   [[CSetBoundsExact1:%[0-9]+]]:gpcr = CSetBoundsExact [[CIncOffsetImm]], [[COPY]]
-  ; TAG-CLEAR-NEXT:   [[CSetBoundsImm1:%[0-9]+]]:gpcr = CSetBoundsImm [[CIncOffsetImm]], 10
-  ; TAG-CLEAR-NEXT:   [[CClearTag1:%[0-9]+]]:gpcr = CClearTag [[CIncOffsetImm]]
-  ; TAG-CLEAR-NEXT:   [[CBuildCap1:%[0-9]+]]:gpcr = CBuildCap [[COPY4]], [[COPY2]]
-  ; TAG-CLEAR-NEXT:   [[CCopyType1:%[0-9]+]]:gpcr = CCopyType [[CIncOffsetImm]], [[COPY2]]
-  ; TAG-CLEAR-NEXT:   [[CCSeal1:%[0-9]+]]:gpcr = CCSeal [[CIncOffsetImm]], [[COPY2]]
-  ; TAG-CLEAR-NEXT:   [[CSealEntry1:%[0-9]+]]:gpcr = CSealEntry [[CIncOffsetImm]]
-  ; TAG-CLEAR-NEXT:   [[CSetHigh1:%[0-9]+]]:gpcr = CSetHigh [[CIncOffsetImm]], [[COPY]]
-  ; TAG-CLEAR-NEXT:   [[CSeal2:%[0-9]+]]:gpcr = CSeal [[CAndPerm]], [[COPY2]]
-  ; TAG-CLEAR-NEXT:   [[CUnseal2:%[0-9]+]]:gpcr = CUnseal [[CAndPerm]], [[COPY2]]
-  ; TAG-CLEAR-NEXT:   [[CAndPerm2:%[0-9]+]]:gpcr = CAndPerm [[CAndPerm]], [[COPY]]
-  ; TAG-CLEAR-NEXT:   [[CSetFlags2:%[0-9]+]]:gpcr = CSetFlags [[CAndPerm]], [[COPY]]
-  ; TAG-CLEAR-NEXT:   [[CSetOffset2:%[0-9]+]]:gpcr = CSetOffset [[CAndPerm]], [[COPY]]
-  ; TAG-CLEAR-NEXT:   [[CSetAddr2:%[0-9]+]]:gpcr = CSetAddr [[CAndPerm]], [[COPY]]
-  ; TAG-CLEAR-NEXT:   [[CIncOffset2:%[0-9]+]]:gpcr = CIncOffset [[CAndPerm]], [[COPY]]
-  ; TAG-CLEAR-NEXT:   [[CIncOffsetImm3:%[0-9]+]]:gpcr = CIncOffsetImm [[CAndPerm]], 10
-  ; TAG-CLEAR-NEXT:   [[CSetBounds2:%[0-9]+]]:gpcr = CSetBounds [[CAndPerm]], [[COPY]]
-  ; TAG-CLEAR-NEXT:   [[CSetBoundsExact2:%[0-9]+]]:gpcr = CSetBoundsExact [[CAndPerm]], [[COPY]]
-  ; TAG-CLEAR-NEXT:   [[CSetBoundsImm2:%[0-9]+]]:gpcr = CSetBoundsImm [[CAndPerm]], 10
-  ; TAG-CLEAR-NEXT:   [[CClearTag2:%[0-9]+]]:gpcr = CClearTag [[CAndPerm]]
-  ; TAG-CLEAR-NEXT:   [[CBuildCap2:%[0-9]+]]:gpcr = CBuildCap [[COPY5]], [[COPY2]]
-  ; TAG-CLEAR-NEXT:   [[CCopyType2:%[0-9]+]]:gpcr = CCopyType [[CAndPerm]], [[COPY2]]
-  ; TAG-CLEAR-NEXT:   [[CCSeal2:%[0-9]+]]:gpcr = CCSeal [[CAndPerm]], [[COPY2]]
-  ; TAG-CLEAR-NEXT:   [[CSeal3:%[0-9]+]]:gpcr = CSeal $c0, [[COPY2]]
-  ; TAG-CLEAR-NEXT:   [[CUnseal3:%[0-9]+]]:gpcr = CUnseal $c0, [[COPY2]]
-  ; TAG-CLEAR-NEXT:   [[CAndPerm3:%[0-9]+]]:gpcr = CAndPerm $c0, [[COPY]]
-  ; TAG-CLEAR-NEXT:   [[CSetFlags3:%[0-9]+]]:gpcr = CSetFlags $c0, [[COPY]]
-  ; TAG-CLEAR-NEXT:   [[CSetOffset3:%[0-9]+]]:gpcr = CSetOffset $c0, [[COPY]]
-  ; TAG-CLEAR-NEXT:   [[CSetAddr3:%[0-9]+]]:gpcr = CSetAddr $c0, [[COPY]]
-  ; TAG-CLEAR-NEXT:   [[CIncOffset3:%[0-9]+]]:gpcr = CIncOffset $c0, [[COPY]]
-  ; TAG-CLEAR-NEXT:   [[CIncOffsetImm4:%[0-9]+]]:gpcr = CIncOffsetImm $c0, 10
-  ; TAG-CLEAR-NEXT:   [[CSetBounds3:%[0-9]+]]:gpcr = CSetBounds $c0, [[COPY]]
-  ; TAG-CLEAR-NEXT:   [[CSetBoundsExact3:%[0-9]+]]:gpcr = CSetBoundsExact $c0, [[COPY]]
-  ; TAG-CLEAR-NEXT:   [[CSetBoundsImm3:%[0-9]+]]:gpcr = CSetBoundsImm $c0, 10
-  ; TAG-CLEAR-NEXT:   [[CClearTag3:%[0-9]+]]:gpcr = CClearTag $c0
-  ; TAG-CLEAR-NEXT:   [[CCopyType3:%[0-9]+]]:gpcr = CCopyType $c0, [[COPY2]]
-  ; TAG-CLEAR-NEXT:   [[CCSeal3:%[0-9]+]]:gpcr = CCSeal $c0, [[COPY2]]
-  ; TAG-CLEAR-NEXT:   [[CSealEntry2:%[0-9]+]]:gpcr = CSealEntry $c0
-  ; TAG-CLEAR-NEXT:   [[CSetHigh2:%[0-9]+]]:gpcr = CSetHigh $c0, [[COPY]]
+  ; TAG-CLEAR-NEXT:   [[CSeal1:%[0-9]+]]:ygpr = CSeal [[CIncOffsetImm]], [[COPY2]]
+  ; TAG-CLEAR-NEXT:   [[CUnseal1:%[0-9]+]]:ygpr = CUnseal [[CIncOffsetImm]], [[COPY2]]
+  ; TAG-CLEAR-NEXT:   [[CAndPerm1:%[0-9]+]]:ygpr = CAndPerm [[CIncOffsetImm]], [[COPY]]
+  ; TAG-CLEAR-NEXT:   [[CSetFlags1:%[0-9]+]]:ygpr = CSetFlags [[CIncOffsetImm]], [[COPY]]
+  ; TAG-CLEAR-NEXT:   [[CSetOffset1:%[0-9]+]]:ygpr = CSetOffset [[CIncOffsetImm]], [[COPY]]
+  ; TAG-CLEAR-NEXT:   [[CSetAddr1:%[0-9]+]]:ygpr = CSetAddr [[CIncOffsetImm]], [[COPY]]
+  ; TAG-CLEAR-NEXT:   [[CIncOffset1:%[0-9]+]]:ygpr = CIncOffset [[CIncOffsetImm]], [[COPY]]
+  ; TAG-CLEAR-NEXT:   [[CIncOffsetImm2:%[0-9]+]]:ygpr = CIncOffsetImm [[CIncOffsetImm]], 10
+  ; TAG-CLEAR-NEXT:   [[CSetBounds1:%[0-9]+]]:ygpr = CSetBounds [[CIncOffsetImm]], [[COPY]]
+  ; TAG-CLEAR-NEXT:   [[CSetBoundsExact1:%[0-9]+]]:ygpr = CSetBoundsExact [[CIncOffsetImm]], [[COPY]]
+  ; TAG-CLEAR-NEXT:   [[CSetBoundsImm1:%[0-9]+]]:ygpr = CSetBoundsImm [[CIncOffsetImm]], 10
+  ; TAG-CLEAR-NEXT:   [[CClearTag1:%[0-9]+]]:ygpr = CClearTag [[CIncOffsetImm]]
+  ; TAG-CLEAR-NEXT:   [[CBuildCap1:%[0-9]+]]:ygpr = CBuildCap [[COPY4]], [[COPY2]]
+  ; TAG-CLEAR-NEXT:   [[CCopyType1:%[0-9]+]]:ygpr = CCopyType [[CIncOffsetImm]], [[COPY2]]
+  ; TAG-CLEAR-NEXT:   [[CCSeal1:%[0-9]+]]:ygpr = CCSeal [[CIncOffsetImm]], [[COPY2]]
+  ; TAG-CLEAR-NEXT:   [[CSealEntry1:%[0-9]+]]:ygpr = CSealEntry [[CIncOffsetImm]]
+  ; TAG-CLEAR-NEXT:   [[CSetHigh1:%[0-9]+]]:ygpr = CSetHigh [[CIncOffsetImm]], [[COPY]]
+  ; TAG-CLEAR-NEXT:   [[CSeal2:%[0-9]+]]:ygpr = CSeal [[CAndPerm]], [[COPY2]]
+  ; TAG-CLEAR-NEXT:   [[CUnseal2:%[0-9]+]]:ygpr = CUnseal [[CAndPerm]], [[COPY2]]
+  ; TAG-CLEAR-NEXT:   [[CAndPerm2:%[0-9]+]]:ygpr = CAndPerm [[CAndPerm]], [[COPY]]
+  ; TAG-CLEAR-NEXT:   [[CSetFlags2:%[0-9]+]]:ygpr = CSetFlags [[CAndPerm]], [[COPY]]
+  ; TAG-CLEAR-NEXT:   [[CSetOffset2:%[0-9]+]]:ygpr = CSetOffset [[CAndPerm]], [[COPY]]
+  ; TAG-CLEAR-NEXT:   [[CSetAddr2:%[0-9]+]]:ygpr = CSetAddr [[CAndPerm]], [[COPY]]
+  ; TAG-CLEAR-NEXT:   [[CIncOffset2:%[0-9]+]]:ygpr = CIncOffset [[CAndPerm]], [[COPY]]
+  ; TAG-CLEAR-NEXT:   [[CIncOffsetImm3:%[0-9]+]]:ygpr = CIncOffsetImm [[CAndPerm]], 10
+  ; TAG-CLEAR-NEXT:   [[CSetBounds2:%[0-9]+]]:ygpr = CSetBounds [[CAndPerm]], [[COPY]]
+  ; TAG-CLEAR-NEXT:   [[CSetBoundsExact2:%[0-9]+]]:ygpr = CSetBoundsExact [[CAndPerm]], [[COPY]]
+  ; TAG-CLEAR-NEXT:   [[CSetBoundsImm2:%[0-9]+]]:ygpr = CSetBoundsImm [[CAndPerm]], 10
+  ; TAG-CLEAR-NEXT:   [[CClearTag2:%[0-9]+]]:ygpr = CClearTag [[CAndPerm]]
+  ; TAG-CLEAR-NEXT:   [[CBuildCap2:%[0-9]+]]:ygpr = CBuildCap [[COPY5]], [[COPY2]]
+  ; TAG-CLEAR-NEXT:   [[CCopyType2:%[0-9]+]]:ygpr = CCopyType [[CAndPerm]], [[COPY2]]
+  ; TAG-CLEAR-NEXT:   [[CCSeal2:%[0-9]+]]:ygpr = CCSeal [[CAndPerm]], [[COPY2]]
+  ; TAG-CLEAR-NEXT:   [[CSeal3:%[0-9]+]]:ygpr = CSeal $x0_y, [[COPY2]]
+  ; TAG-CLEAR-NEXT:   [[CUnseal3:%[0-9]+]]:ygpr = CUnseal $x0_y, [[COPY2]]
+  ; TAG-CLEAR-NEXT:   [[CAndPerm3:%[0-9]+]]:ygpr = CAndPerm $x0_y, [[COPY]]
+  ; TAG-CLEAR-NEXT:   [[CSetFlags3:%[0-9]+]]:ygpr = CSetFlags $x0_y, [[COPY]]
+  ; TAG-CLEAR-NEXT:   [[CSetOffset3:%[0-9]+]]:ygpr = CSetOffset $x0_y, [[COPY]]
+  ; TAG-CLEAR-NEXT:   [[CSetAddr3:%[0-9]+]]:ygpr = CSetAddr $x0_y, [[COPY]]
+  ; TAG-CLEAR-NEXT:   [[CIncOffset3:%[0-9]+]]:ygpr = CIncOffset $x0_y, [[COPY]]
+  ; TAG-CLEAR-NEXT:   [[CIncOffsetImm4:%[0-9]+]]:ygpr = CIncOffsetImm $x0_y, 10
+  ; TAG-CLEAR-NEXT:   [[CSetBounds3:%[0-9]+]]:ygpr = CSetBounds $x0_y, [[COPY]]
+  ; TAG-CLEAR-NEXT:   [[CSetBoundsExact3:%[0-9]+]]:ygpr = CSetBoundsExact $x0_y, [[COPY]]
+  ; TAG-CLEAR-NEXT:   [[CSetBoundsImm3:%[0-9]+]]:ygpr = CSetBoundsImm $x0_y, 10
+  ; TAG-CLEAR-NEXT:   [[CClearTag3:%[0-9]+]]:ygpr = CClearTag $x0_y
+  ; TAG-CLEAR-NEXT:   [[CCopyType3:%[0-9]+]]:ygpr = CCopyType $x0_y, [[COPY2]]
+  ; TAG-CLEAR-NEXT:   [[CCSeal3:%[0-9]+]]:ygpr = CCSeal $x0_y, [[COPY2]]
+  ; TAG-CLEAR-NEXT:   [[CSealEntry2:%[0-9]+]]:ygpr = CSealEntry $x0_y
+  ; TAG-CLEAR-NEXT:   [[CSetHigh2:%[0-9]+]]:ygpr = CSetHigh $x0_y, [[COPY]]
   ; TAG-CLEAR-NEXT:   PseudoBR %bb.2
   ; TAG-CLEAR-NEXT: {{  $}}
   ; TAG-CLEAR-NEXT: bb.1.for.cond.cleanup:
@@ -297,7 +297,7 @@ body:             |
   ; TAG-CLEAR-NEXT:   successors: %bb.4(0x80000000)
   ; TAG-CLEAR-NEXT: {{  $}}
   ; TAG-CLEAR-NEXT:   [[CGetTag:%[0-9]+]]:gpr = CGetTag [[COPY2]]
-  ; TAG-CLEAR-NEXT:   [[CSpecialRW:%[0-9]+]]:gpcr = CSpecialRW 0, [[COPY1]]
+  ; TAG-CLEAR-NEXT:   [[CSpecialRW:%[0-9]+]]:ygpr = CSpecialRW 0, [[COPY1]]
   ; TAG-CLEAR-NEXT:   CClear 1, 1
   ; TAG-CLEAR-NEXT:   FPClear 1, 1
   ; TAG-CLEAR-NEXT: {{  $}}
@@ -308,16 +308,16 @@ body:             |
   ; TAG-CLEAR-NEXT:   PseudoBR %bb.1
   bb.0.entry:
     successors: %bb.2(0x80000000)
-    liveins: $x10, $c11, $c12
+    liveins: $x10, $x11_y, $x12_y
 
     %0:gpr = COPY $x10
-    %1:gpcr = COPY $c11
-    %2:gpcr = COPY $c12
-    %3:gpcrc0isddc = COPY $c12
-    %4:gpcr = CIncOffsetImm %1, 4
-    %5:gpcrc0isddc = COPY %4
-    %6:gpcr = CAndPerm %1, %0
-    %7:gpcrc0isddc = COPY %6
+    %1:ygpr = COPY $x11_y
+    %2:ygpr = COPY $x12_y
+    %3:ygprx0isddc = COPY $x12_y
+    %4:ygpr = CIncOffsetImm %1, 4
+    %5:ygprx0isddc = COPY %4
+    %6:ygpr = CAndPerm %1, %0
+    %7:ygprx0isddc = COPY %6
 
 
     PseudoBR %bb.2
@@ -345,33 +345,33 @@ body:             |
     %17:gpr = PseudoCGetAddr %2
     %18:gpr = CGetHigh %2
     ; Mutators can also be hoisted since we default to non-trapping
-    %30:gpcr = CSeal %1, %2
-    %31:gpcr = CUnseal %1, %2
-    %32:gpcr = CAndPerm %1, %0
-    %33:gpcr = CSetFlags %1, %0
-    %34:gpcr = CSetOffset %1, %0
-    %35:gpcr = CSetAddr %1, %0
-    %36:gpcr = CIncOffset %1, %0
-    %37:gpcr = CIncOffsetImm %1, 10
-    %38:gpcr = CSetBounds %1, %0
-    %39:gpcr = CSetBoundsExact %1, %0
-    %40:gpcr = CSetBoundsImm %1, 10
-    %41:gpcr = CClearTag %1 ; Note: CClearTag can be hoisted since it can't trap
-    %42:gpcr = CBuildCap %3, %2
-    %43:gpcr = CCopyType %1, %2
-    %44:gpcr = CCSeal %1, %2
-    %45:gpcr = CSealEntry %1
-    %46:gpcr = CSetHigh %1, %0
+    %30:ygpr = CSeal %1, %2
+    %31:ygpr = CUnseal %1, %2
+    %32:ygpr = CAndPerm %1, %0
+    %33:ygpr = CSetFlags %1, %0
+    %34:ygpr = CSetOffset %1, %0
+    %35:ygpr = CSetAddr %1, %0
+    %36:ygpr = CIncOffset %1, %0
+    %37:ygpr = CIncOffsetImm %1, 10
+    %38:ygpr = CSetBounds %1, %0
+    %39:ygpr = CSetBoundsExact %1, %0
+    %40:ygpr = CSetBoundsImm %1, 10
+    %41:ygpr = CClearTag %1 ; Note: CClearTag can be hoisted since it can't trap
+    %42:ygpr = CBuildCap %3, %2
+    %43:ygpr = CCopyType %1, %2
+    %44:ygpr = CCSeal %1, %2
+    %45:ygpr = CSealEntry %1
+    %46:ygpr = CSetHigh %1, %0
 
     ; Pointer-arithmetic instructions
-    %63:gpcr = CMove %1 ; never traps
+    %63:ygpr = CMove %1 ; never traps
 
     ; Assertion Instructions
     %70:gpr = CTestSubset %3, %2 ; never traps
     ; Note: loads not tested here (yet)
 
     ; Special Capabilty Register Access Instructions
-    %80:gpcr = CSpecialRW 0, %1
+    %80:ygpr = CSpecialRW 0, %1
 
     ; Fast Register-Clearing Instructions
     CClear 1, 1
@@ -383,60 +383,60 @@ body:             |
 
 
     ; Now try using the mutators on a known-unsealed value:
-    %130:gpcr = CSeal %4, %2
-    %131:gpcr = CUnseal %4, %2
-    %132:gpcr = CAndPerm %4, %0
-    %133:gpcr = CSetFlags %4, %0
-    %134:gpcr = CSetOffset %4, %0
-    %135:gpcr = CSetAddr %4, %0
-    %136:gpcr = CIncOffset %4, %0
-    %137:gpcr = CIncOffsetImm %4, 10
-    %138:gpcr = CSetBounds %4, %0
-    %139:gpcr = CSetBoundsExact %4, %0
-    %140:gpcr = CSetBoundsImm %4, 10
-    %141:gpcr = CClearTag %4
-    %142:gpcr = CBuildCap %5, %2
-    %143:gpcr = CCopyType %4, %2
-    %144:gpcr = CCSeal %4, %2
-    %145:gpcr = CSealEntry %4
-    %146:gpcr = CSetHigh %4, %0
+    %130:ygpr = CSeal %4, %2
+    %131:ygpr = CUnseal %4, %2
+    %132:ygpr = CAndPerm %4, %0
+    %133:ygpr = CSetFlags %4, %0
+    %134:ygpr = CSetOffset %4, %0
+    %135:ygpr = CSetAddr %4, %0
+    %136:ygpr = CIncOffset %4, %0
+    %137:ygpr = CIncOffsetImm %4, 10
+    %138:ygpr = CSetBounds %4, %0
+    %139:ygpr = CSetBoundsExact %4, %0
+    %140:ygpr = CSetBoundsImm %4, 10
+    %141:ygpr = CClearTag %4
+    %142:ygpr = CBuildCap %5, %2
+    %143:ygpr = CCopyType %4, %2
+    %144:ygpr = CCSeal %4, %2
+    %145:ygpr = CSealEntry %4
+    %146:ygpr = CSetHigh %4, %0
 
     ; And a known-tagged+unsealed value:
-    %230:gpcr = CSeal %6, %2
-    %231:gpcr = CUnseal %6, %2
-    %232:gpcr = CAndPerm %6, %0
-    %233:gpcr = CSetFlags %6, %0
-    %234:gpcr = CSetOffset %6, %0
-    %235:gpcr = CSetAddr %6, %0
-    %236:gpcr = CIncOffset %6, %0
-    %237:gpcr = CIncOffsetImm %6, 10
-    %238:gpcr = CSetBounds %6, %0
-    %239:gpcr = CSetBoundsExact %6, %0
-    %240:gpcr = CSetBoundsImm %6, 10
-    %241:gpcr = CClearTag %6
-    %242:gpcr = CBuildCap %7, %2
-    %243:gpcr = CCopyType %6, %2
-    %244:gpcr = CCSeal %6, %2
-    %245:gpcr = CSealEntry %4
-    %246:gpcr = CSetHigh %4, %0
+    %230:ygpr = CSeal %6, %2
+    %231:ygpr = CUnseal %6, %2
+    %232:ygpr = CAndPerm %6, %0
+    %233:ygpr = CSetFlags %6, %0
+    %234:ygpr = CSetOffset %6, %0
+    %235:ygpr = CSetAddr %6, %0
+    %236:ygpr = CIncOffset %6, %0
+    %237:ygpr = CIncOffsetImm %6, 10
+    %238:ygpr = CSetBounds %6, %0
+    %239:ygpr = CSetBoundsExact %6, %0
+    %240:ygpr = CSetBoundsImm %6, 10
+    %241:ygpr = CClearTag %6
+    %242:ygpr = CBuildCap %7, %2
+    %243:ygpr = CCopyType %6, %2
+    %244:ygpr = CCSeal %6, %2
+    %245:ygpr = CSealEntry %4
+    %246:ygpr = CSetHigh %4, %0
 
     ; Now try using the mutators on constant NULL:
-    %330:gpcr = CSeal $c0, %2
-    %331:gpcr = CUnseal $c0, %2
-    %332:gpcr = CAndPerm $c0, %0
-    %333:gpcr = CSetFlags $c0, %0
-    %334:gpcr = CSetOffset $c0, %0
-    %335:gpcr = CSetAddr $c0, %0
-    %336:gpcr = CIncOffset $c0, %0
-    %337:gpcr = CIncOffsetImm $c0, 10
-    %338:gpcr = CSetBounds $c0, %0
-    %339:gpcr = CSetBoundsExact $c0, %0
-    %340:gpcr = CSetBoundsImm $c0, 10
-    %341:gpcr = CClearTag $c0
-    %344:gpcr = CCopyType $c0, %2
-    %345:gpcr = CCSeal $c0, %2
-    %346:gpcr = CSealEntry $c0
-    %347:gpcr = CSetHigh $c0, %0
+    %330:ygpr = CSeal $x0_y, %2
+    %331:ygpr = CUnseal $x0_y, %2
+    %332:ygpr = CAndPerm $x0_y, %0
+    %333:ygpr = CSetFlags $x0_y, %0
+    %334:ygpr = CSetOffset $x0_y, %0
+    %335:ygpr = CSetAddr $x0_y, %0
+    %336:ygpr = CIncOffset $x0_y, %0
+    %337:ygpr = CIncOffsetImm $x0_y, 10
+    %338:ygpr = CSetBounds $x0_y, %0
+    %339:ygpr = CSetBoundsExact $x0_y, %0
+    %340:ygpr = CSetBoundsImm $x0_y, 10
+    %341:ygpr = CClearTag $x0_y
+    %344:ygpr = CCopyType $x0_y, %2
+    %345:ygpr = CCSeal $x0_y, %2
+    %346:ygpr = CSealEntry $x0_y
+    %347:ygpr = CSetHigh $x0_y, %0
 
   bb.4.for.inc:
     successors: %bb.2(0x7c000000), %bb.1(0x04000000)
diff --git a/llvm/test/CodeGen/RISCV/cheri/mem32.ll b/llvm/test/CodeGen/RISCV/cheri/mem32.ll
index 6440918d2ca47..a0948cc65d9b0 100644
--- a/llvm/test/CodeGen/RISCV/cheri/mem32.ll
+++ b/llvm/test/CodeGen/RISCV/cheri/mem32.ll
@@ -126,16 +126,16 @@ define i32 @ddc_lhu(i16 *%ptr) nounwind {
 define i32 @ddc_lc(i8 addrspace(200) **%ptr) nounwind {
 ; CHECK-ILP32-LABEL: ddc_lc:
 ; CHECK-ILP32:       # %bb.0:
-; CHECK-ILP32-NEXT:    lc ca1, 0(a0)
-; CHECK-ILP32-NEXT:    lc ca0, 48(a0)
+; CHECK-ILP32-NEXT:    lc a1, 0(a0)
+; CHECK-ILP32-NEXT:    lc a0, 48(a0)
 ; CHECK-ILP32-NEXT:    sub a0, a1, a0
 ; CHECK-ILP32-NEXT:    ret
 ;
 ; CHECK-IL32PC64-LABEL: ddc_lc:
 ; CHECK-IL32PC64:       # %bb.0:
-; CHECK-IL32PC64-NEXT:    lc.ddc ca1, (a0)
+; CHECK-IL32PC64-NEXT:    lc.ddc a1, (a0)
 ; CHECK-IL32PC64-NEXT:    addi a0, a0, 48
-; CHECK-IL32PC64-NEXT:    lc.ddc ca0, (a0)
+; CHECK-IL32PC64-NEXT:    lc.ddc a0, (a0)
 ; CHECK-IL32PC64-NEXT:    sub a0, a1, a0
 ; CHECK-IL32PC64-NEXT:    cret
   %1 = load i8 addrspace(200) *, i8 addrspace(200) **%ptr
@@ -207,15 +207,15 @@ define void @ddc_sw(i32 *%ptr, i32 %val) nounwind {
 define void @ddc_sc(i8 addrspace(200) **%ptr, i8 addrspace(200) *%val) nounwind {
 ; CHECK-ILP32-LABEL: ddc_sc:
 ; CHECK-ILP32:       # %bb.0:
-; CHECK-ILP32-NEXT:    sc ca1, 0(a0)
-; CHECK-ILP32-NEXT:    sc ca1, 80(a0)
+; CHECK-ILP32-NEXT:    sc a1, 0(a0)
+; CHECK-ILP32-NEXT:    sc a1, 80(a0)
 ; CHECK-ILP32-NEXT:    ret
 ;
 ; CHECK-IL32PC64-LABEL: ddc_sc:
 ; CHECK-IL32PC64:       # %bb.0:
-; CHECK-IL32PC64-NEXT:    sc.ddc ca1, (a0)
+; CHECK-IL32PC64-NEXT:    sc.ddc a1, (a0)
 ; CHECK-IL32PC64-NEXT:    addi a0, a0, 80
-; CHECK-IL32PC64-NEXT:    sc.ddc ca1, (a0)
+; CHECK-IL32PC64-NEXT:    sc.ddc a1, (a0)
 ; CHECK-IL32PC64-NEXT:    cret
   store i8 addrspace(200) *%val, i8 addrspace(200) **%ptr
   %1 = getelementptr i8 addrspace(200) *, i8 addrspace(200) **%ptr, i32 10
@@ -228,16 +228,16 @@ define void @ddc_sc(i8 addrspace(200) **%ptr, i8 addrspace(200) *%val) nounwind
 define i32 @cap_lb(i8 addrspace(200) *%cap) nounwind {
 ; CHECK-ILP32-LABEL: cap_lb:
 ; CHECK-ILP32:       # %bb.0:
-; CHECK-ILP32-NEXT:    lb.cap a1, (ca0)
-; CHECK-ILP32-NEXT:    cincoffset ca0, ca0, 11
-; CHECK-ILP32-NEXT:    lb.cap zero, (ca0)
+; CHECK-ILP32-NEXT:    lb.cap a1, (a0)
+; CHECK-ILP32-NEXT:    cincoffset a0, a0, 11
+; CHECK-ILP32-NEXT:    lb.cap zero, (a0)
 ; CHECK-ILP32-NEXT:    mv a0, a1
 ; CHECK-ILP32-NEXT:    ret
 ;
 ; CHECK-IL32PC64-LABEL: cap_lb:
 ; CHECK-IL32PC64:       # %bb.0:
-; CHECK-IL32PC64-NEXT:    clb a1, 0(ca0)
-; CHECK-IL32PC64-NEXT:    clb zero, 11(ca0)
+; CHECK-IL32PC64-NEXT:    clb a1, 0(a0)
+; CHECK-IL32PC64-NEXT:    clb zero, 11(a0)
 ; CHECK-IL32PC64-NEXT:    mv a0, a1
 ; CHECK-IL32PC64-NEXT:    cret
   %1 = load i8, i8 addrspace(200) *%cap
@@ -251,16 +251,16 @@ define i32 @cap_lb(i8 addrspace(200) *%cap) nounwind {
 define i32 @cap_lh(i16 addrspace(200) *%cap) nounwind {
 ; CHECK-ILP32-LABEL: cap_lh:
 ; CHECK-ILP32:       # %bb.0:
-; CHECK-ILP32-NEXT:    lh.cap a1, (ca0)
-; CHECK-ILP32-NEXT:    cincoffset ca0, ca0, 24
-; CHECK-ILP32-NEXT:    lh.cap zero, (ca0)
+; CHECK-ILP32-NEXT:    lh.cap a1, (a0)
+; CHECK-ILP32-NEXT:    cincoffset a0, a0, 24
+; CHECK-ILP32-NEXT:    lh.cap zero, (a0)
 ; CHECK-ILP32-NEXT:    mv a0, a1
 ; CHECK-ILP32-NEXT:    ret
 ;
 ; CHECK-IL32PC64-LABEL: cap_lh:
 ; CHECK-IL32PC64:       # %bb.0:
-; CHECK-IL32PC64-NEXT:    clh a1, 0(ca0)
-; CHECK-IL32PC64-NEXT:    clh zero, 24(ca0)
+; CHECK-IL32PC64-NEXT:    clh a1, 0(a0)
+; CHECK-IL32PC64-NEXT:    clh zero, 24(a0)
 ; CHECK-IL32PC64-NEXT:    mv a0, a1
 ; CHECK-IL32PC64-NEXT:    cret
   %1 = load i16, i16 addrspace(200) *%cap
@@ -274,16 +274,16 @@ define i32 @cap_lh(i16 addrspace(200) *%cap) nounwind {
 define i32 @cap_lw(i32 addrspace(200) *%cap) nounwind {
 ; CHECK-ILP32-LABEL: cap_lw:
 ; CHECK-ILP32:       # %bb.0:
-; CHECK-ILP32-NEXT:    lw.cap a1, (ca0)
-; CHECK-ILP32-NEXT:    cincoffset ca0, ca0, 52
-; CHECK-ILP32-NEXT:    lw.cap zero, (ca0)
+; CHECK-ILP32-NEXT:    lw.cap a1, (a0)
+; CHECK-ILP32-NEXT:    cincoffset a0, a0, 52
+; CHECK-ILP32-NEXT:    lw.cap zero, (a0)
 ; CHECK-ILP32-NEXT:    mv a0, a1
 ; CHECK-ILP32-NEXT:    ret
 ;
 ; CHECK-IL32PC64-LABEL: cap_lw:
 ; CHECK-IL32PC64:       # %bb.0:
-; CHECK-IL32PC64-NEXT:    clw a1, 0(ca0)
-; CHECK-IL32PC64-NEXT:    clw zero, 52(ca0)
+; CHECK-IL32PC64-NEXT:    clw a1, 0(a0)
+; CHECK-IL32PC64-NEXT:    clw zero, 52(a0)
 ; CHECK-IL32PC64-NEXT:    mv a0, a1
 ; CHECK-IL32PC64-NEXT:    cret
   %1 = load i32, i32 addrspace(200) *%cap
@@ -295,16 +295,16 @@ define i32 @cap_lw(i32 addrspace(200) *%cap) nounwind {
 define i32 @cap_lbu(i8 addrspace(200) *%cap) nounwind {
 ; CHECK-ILP32-LABEL: cap_lbu:
 ; CHECK-ILP32:       # %bb.0:
-; CHECK-ILP32-NEXT:    lbu.cap a1, (ca0)
-; CHECK-ILP32-NEXT:    cincoffset ca0, ca0, 14
-; CHECK-ILP32-NEXT:    lbu.cap a0, (ca0)
+; CHECK-ILP32-NEXT:    lbu.cap a1, (a0)
+; CHECK-ILP32-NEXT:    cincoffset a0, a0, 14
+; CHECK-ILP32-NEXT:    lbu.cap a0, (a0)
 ; CHECK-ILP32-NEXT:    add a0, a1, a0
 ; CHECK-ILP32-NEXT:    ret
 ;
 ; CHECK-IL32PC64-LABEL: cap_lbu:
 ; CHECK-IL32PC64:       # %bb.0:
-; CHECK-IL32PC64-NEXT:    clbu a1, 0(ca0)
-; CHECK-IL32PC64-NEXT:    clbu a0, 14(ca0)
+; CHECK-IL32PC64-NEXT:    clbu a1, 0(a0)
+; CHECK-IL32PC64-NEXT:    clbu a0, 14(a0)
 ; CHECK-IL32PC64-NEXT:    add a0, a1, a0
 ; CHECK-IL32PC64-NEXT:    cret
   %1 = load i8, i8 addrspace(200) *%cap
@@ -319,16 +319,16 @@ define i32 @cap_lbu(i8 addrspace(200) *%cap) nounwind {
 define i32 @cap_lhu(i16 addrspace(200) *%cap) nounwind {
 ; CHECK-ILP32-LABEL: cap_lhu:
 ; CHECK-ILP32:       # %bb.0:
-; CHECK-ILP32-NEXT:    lhu.cap a1, (ca0)
-; CHECK-ILP32-NEXT:    cincoffset ca0, ca0, 30
-; CHECK-ILP32-NEXT:    lhu.cap a0, (ca0)
+; CHECK-ILP32-NEXT:    lhu.cap a1, (a0)
+; CHECK-ILP32-NEXT:    cincoffset a0, a0, 30
+; CHECK-ILP32-NEXT:    lhu.cap a0, (a0)
 ; CHECK-ILP32-NEXT:    add a0, a1, a0
 ; CHECK-ILP32-NEXT:    ret
 ;
 ; CHECK-IL32PC64-LABEL: cap_lhu:
 ; CHECK-IL32PC64:       # %bb.0:
-; CHECK-IL32PC64-NEXT:    clhu a1, 0(ca0)
-; CHECK-IL32PC64-NEXT:    clhu a0, 30(ca0)
+; CHECK-IL32PC64-NEXT:    clhu a1, 0(a0)
+; CHECK-IL32PC64-NEXT:    clhu a0, 30(a0)
 ; CHECK-IL32PC64-NEXT:    add a0, a1, a0
 ; CHECK-IL32PC64-NEXT:    cret
   %1 = load i16, i16 addrspace(200) *%cap
@@ -343,16 +343,16 @@ define i32 @cap_lhu(i16 addrspace(200) *%cap) nounwind {
 define i32 @cap_lc(i8 addrspace(200) *addrspace(200) *%cap) nounwind {
 ; CHECK-ILP32-LABEL: cap_lc:
 ; CHECK-ILP32:       # %bb.0:
-; CHECK-ILP32-NEXT:    lc.cap ca1, (ca0)
-; CHECK-ILP32-NEXT:    cincoffset ca0, ca0, 128
-; CHECK-ILP32-NEXT:    lc.cap ca0, (ca0)
+; CHECK-ILP32-NEXT:    lc.cap a1, (a0)
+; CHECK-ILP32-NEXT:    cincoffset a0, a0, 128
+; CHECK-ILP32-NEXT:    lc.cap a0, (a0)
 ; CHECK-ILP32-NEXT:    sub a0, a1, a0
 ; CHECK-ILP32-NEXT:    ret
 ;
 ; CHECK-IL32PC64-LABEL: cap_lc:
 ; CHECK-IL32PC64:       # %bb.0:
-; CHECK-IL32PC64-NEXT:    clc ca1, 0(ca0)
-; CHECK-IL32PC64-NEXT:    clc ca0, 128(ca0)
+; CHECK-IL32PC64-NEXT:    clc a1, 0(a0)
+; CHECK-IL32PC64-NEXT:    clc a0, 128(a0)
 ; CHECK-IL32PC64-NEXT:    sub a0, a1, a0
 ; CHECK-IL32PC64-NEXT:    cret
   %1 = load i8 addrspace(200) *, i8 addrspace(200) *addrspace(200) *%cap
@@ -367,15 +367,15 @@ define i32 @cap_lc(i8 addrspace(200) *addrspace(200) *%cap) nounwind {
 define void @cap_sb(i8 addrspace(200) *%cap, i8 %val) nounwind {
 ; CHECK-ILP32-LABEL: cap_sb:
 ; CHECK-ILP32:       # %bb.0:
-; CHECK-ILP32-NEXT:    sb.cap a1, (ca0)
-; CHECK-ILP32-NEXT:    cincoffset ca0, ca0, 17
-; CHECK-ILP32-NEXT:    sb.cap a1, (ca0)
+; CHECK-ILP32-NEXT:    sb.cap a1, (a0)
+; CHECK-ILP32-NEXT:    cincoffset a0, a0, 17
+; CHECK-ILP32-NEXT:    sb.cap a1, (a0)
 ; CHECK-ILP32-NEXT:    ret
 ;
 ; CHECK-IL32PC64-LABEL: cap_sb:
 ; CHECK-IL32PC64:       # %bb.0:
-; CHECK-IL32PC64-NEXT:    csb a1, 0(ca0)
-; CHECK-IL32PC64-NEXT:    csb a1, 17(ca0)
+; CHECK-IL32PC64-NEXT:    csb a1, 0(a0)
+; CHECK-IL32PC64-NEXT:    csb a1, 17(a0)
 ; CHECK-IL32PC64-NEXT:    cret
   store i8 %val, i8 addrspace(200) *%cap
   %1 = getelementptr i8, i8 addrspace(200) *%cap, i32 17
@@ -386,15 +386,15 @@ define void @cap_sb(i8 addrspace(200) *%cap, i8 %val) nounwind {
 define void @cap_sh(i16 addrspace(200) *%cap, i16 %val) nounwind {
 ; CHECK-ILP32-LABEL: cap_sh:
 ; CHECK-ILP32:       # %bb.0:
-; CHECK-ILP32-NEXT:    sh.cap a1, (ca0)
-; CHECK-ILP32-NEXT:    cincoffset ca0, ca0, 36
-; CHECK-ILP32-NEXT:    sh.cap a1, (ca0)
+; CHECK-ILP32-NEXT:    sh.cap a1, (a0)
+; CHECK-ILP32-NEXT:    cincoffset a0, a0, 36
+; CHECK-ILP32-NEXT:    sh.cap a1, (a0)
 ; CHECK-ILP32-NEXT:    ret
 ;
 ; CHECK-IL32PC64-LABEL: cap_sh:
 ; CHECK-IL32PC64:       # %bb.0:
-; CHECK-IL32PC64-NEXT:    csh a1, 0(ca0)
-; CHECK-IL32PC64-NEXT:    csh a1, 36(ca0)
+; CHECK-IL32PC64-NEXT:    csh a1, 0(a0)
+; CHECK-IL32PC64-NEXT:    csh a1, 36(a0)
 ; CHECK-IL32PC64-NEXT:    cret
   store i16 %val, i16 addrspace(200) *%cap
   %1 = getelementptr i16, i16 addrspace(200) *%cap, i32 18
@@ -405,15 +405,15 @@ define void @cap_sh(i16 addrspace(200) *%cap, i16 %val) nounwind {
 define void @cap_sw(i32 addrspace(200) *%cap, i32 %val) nounwind {
 ; CHECK-ILP32-LABEL: cap_sw:
 ; CHECK-ILP32:       # %bb.0:
-; CHECK-ILP32-NEXT:    sw.cap a1, (ca0)
-; CHECK-ILP32-NEXT:    cincoffset ca0, ca0, 76
-; CHECK-ILP32-NEXT:    sw.cap a1, (ca0)
+; CHECK-ILP32-NEXT:    sw.cap a1, (a0)
+; CHECK-ILP32-NEXT:    cincoffset a0, a0, 76
+; CHECK-ILP32-NEXT:    sw.cap a1, (a0)
 ; CHECK-ILP32-NEXT:    ret
 ;
 ; CHECK-IL32PC64-LABEL: cap_sw:
 ; CHECK-IL32PC64:       # %bb.0:
-; CHECK-IL32PC64-NEXT:    csw a1, 0(ca0)
-; CHECK-IL32PC64-NEXT:    csw a1, 76(ca0)
+; CHECK-IL32PC64-NEXT:    csw a1, 0(a0)
+; CHECK-IL32PC64-NEXT:    csw a1, 76(a0)
 ; CHECK-IL32PC64-NEXT:    cret
   store i32 %val, i32 addrspace(200) *%cap
   %1 = getelementptr i32, i32 addrspace(200) *%cap, i32 19
@@ -424,15 +424,15 @@ define void @cap_sw(i32 addrspace(200) *%cap, i32 %val) nounwind {
 define void @cap_sc(i8 addrspace(200) *addrspace(200) *%cap, i8 addrspace(200) *%val) nounwind {
 ; CHECK-ILP32-LABEL: cap_sc:
 ; CHECK-ILP32:       # %bb.0:
-; CHECK-ILP32-NEXT:    sc.cap ca1, (ca0)
-; CHECK-ILP32-NEXT:    cincoffset ca0, ca0, 160
-; CHECK-ILP32-NEXT:    sc.cap ca1, (ca0)
+; CHECK-ILP32-NEXT:    sc.cap a1, (a0)
+; CHECK-ILP32-NEXT:    cincoffset a0, a0, 160
+; CHECK-ILP32-NEXT:    sc.cap a1, (a0)
 ; CHECK-ILP32-NEXT:    ret
 ;
 ; CHECK-IL32PC64-LABEL: cap_sc:
 ; CHECK-IL32PC64:       # %bb.0:
-; CHECK-IL32PC64-NEXT:    csc ca1, 0(ca0)
-; CHECK-IL32PC64-NEXT:    csc ca1, 160(ca0)
+; CHECK-IL32PC64-NEXT:    csc a1, 0(a0)
+; CHECK-IL32PC64-NEXT:    csc a1, 160(a0)
 ; CHECK-IL32PC64-NEXT:    cret
   store i8 addrspace(200) *%val, i8 addrspace(200) *addrspace(200) *%cap
   %1 = getelementptr i8 addrspace(200) *, i8 addrspace(200) *addrspace(200) *%cap, i32 20
@@ -445,16 +445,16 @@ define i32 addrspace(200)* @lc_far_local(i32 addrspace(200)* addrspace(200)* %a)
 ; CHECK-ILP32:       # %bb.0:
 ; CHECK-ILP32-NEXT:    lui a1, 8
 ; CHECK-ILP32-NEXT:    addi a1, a1, -8
-; CHECK-ILP32-NEXT:    cincoffset ca0, ca0, a1
-; CHECK-ILP32-NEXT:    lc.cap ca0, (ca0)
+; CHECK-ILP32-NEXT:    cincoffset a0, a0, a1
+; CHECK-ILP32-NEXT:    lc.cap a0, (a0)
 ; CHECK-ILP32-NEXT:    ret
 ;
 ; CHECK-IL32PC64-LABEL: lc_far_local:
 ; CHECK-IL32PC64:       # %bb.0:
 ; CHECK-IL32PC64-NEXT:    lui a1, 8
 ; CHECK-IL32PC64-NEXT:    addi a1, a1, -8
-; CHECK-IL32PC64-NEXT:    cincoffset ca0, ca0, a1
-; CHECK-IL32PC64-NEXT:    clc ca0, 0(ca0)
+; CHECK-IL32PC64-NEXT:    cincoffset a0, a0, a1
+; CHECK-IL32PC64-NEXT:    clc a0, 0(a0)
 ; CHECK-IL32PC64-NEXT:    cret
   %1 = getelementptr inbounds i32 addrspace(200)*, i32 addrspace(200)* addrspace(200)* %a, i64 4095
   %2 = load volatile i32 addrspace(200)*, i32 addrspace(200)* addrspace(200)* %1
@@ -466,16 +466,16 @@ define void @sc_far_local(i32 addrspace(200)* addrspace(200)* %a, i32 addrspace(
 ; CHECK-ILP32:       # %bb.0:
 ; CHECK-ILP32-NEXT:    lui a2, 8
 ; CHECK-ILP32-NEXT:    addi a2, a2, -8
-; CHECK-ILP32-NEXT:    cincoffset ca0, ca0, a2
-; CHECK-ILP32-NEXT:    sc.cap ca1, (ca0)
+; CHECK-ILP32-NEXT:    cincoffset a0, a0, a2
+; CHECK-ILP32-NEXT:    sc.cap a1, (a0)
 ; CHECK-ILP32-NEXT:    ret
 ;
 ; CHECK-IL32PC64-LABEL: sc_far_local:
 ; CHECK-IL32PC64:       # %bb.0:
 ; CHECK-IL32PC64-NEXT:    lui a2, 8
 ; CHECK-IL32PC64-NEXT:    addi a2, a2, -8
-; CHECK-IL32PC64-NEXT:    cincoffset ca0, ca0, a2
-; CHECK-IL32PC64-NEXT:    csc ca1, 0(ca0)
+; CHECK-IL32PC64-NEXT:    cincoffset a0, a0, a2
+; CHECK-IL32PC64-NEXT:    csc a1, 0(a0)
 ; CHECK-IL32PC64-NEXT:    cret
   %1 = getelementptr inbounds i32 addrspace(200)*, i32 addrspace(200)* addrspace(200)* %a, i64 4095
   store i32 addrspace(200)* %b, i32 addrspace(200)* addrspace(200)* %1
@@ -487,18 +487,18 @@ define i32 addrspace(200)* @lc_sc_far_local(i32 addrspace(200)* addrspace(200)*
 ; CHECK-ILP32:       # %bb.0:
 ; CHECK-ILP32-NEXT:    lui a2, 8
 ; CHECK-ILP32-NEXT:    addi a2, a2, -8
-; CHECK-ILP32-NEXT:    cincoffset ca2, ca0, a2
-; CHECK-ILP32-NEXT:    lc.cap ca0, (ca2)
-; CHECK-ILP32-NEXT:    sc.cap ca1, (ca2)
+; CHECK-ILP32-NEXT:    cincoffset a2, a0, a2
+; CHECK-ILP32-NEXT:    lc.cap a0, (a2)
+; CHECK-ILP32-NEXT:    sc.cap a1, (a2)
 ; CHECK-ILP32-NEXT:    ret
 ;
 ; CHECK-IL32PC64-LABEL: lc_sc_far_local:
 ; CHECK-IL32PC64:       # %bb.0:
 ; CHECK-IL32PC64-NEXT:    lui a2, 8
 ; CHECK-IL32PC64-NEXT:    addi a2, a2, -8
-; CHECK-IL32PC64-NEXT:    cincoffset ca2, ca0, a2
-; CHECK-IL32PC64-NEXT:    clc ca0, 0(ca2)
-; CHECK-IL32PC64-NEXT:    csc ca1, 0(ca2)
+; CHECK-IL32PC64-NEXT:    cincoffset a2, a0, a2
+; CHECK-IL32PC64-NEXT:    clc a0, 0(a2)
+; CHECK-IL32PC64-NEXT:    csc a1, 0(a2)
 ; CHECK-IL32PC64-NEXT:    cret
   %1 = getelementptr inbounds i32 addrspace(200)*, i32 addrspace(200)* addrspace(200)* %a, i64 4095
   %2 = load volatile i32 addrspace(200)*, i32 addrspace(200)* addrspace(200)* %1
diff --git a/llvm/test/CodeGen/RISCV/cheri/mem64.ll b/llvm/test/CodeGen/RISCV/cheri/mem64.ll
index 2fa3802299945..9c52fe0ae7b78 100644
--- a/llvm/test/CodeGen/RISCV/cheri/mem64.ll
+++ b/llvm/test/CodeGen/RISCV/cheri/mem64.ll
@@ -173,16 +173,16 @@ define dso_local i64 @ddc_lwu(i32 *%ptr) nounwind {
 define dso_local i64 @ddc_lc(i8 addrspace(200) **%ptr) nounwind {
 ; CHECK-LP64-LABEL: ddc_lc:
 ; CHECK-LP64:       # %bb.0:
-; CHECK-LP64-NEXT:    lc ca1, 0(a0)
-; CHECK-LP64-NEXT:    lc ca0, 128(a0)
+; CHECK-LP64-NEXT:    lc a1, 0(a0)
+; CHECK-LP64-NEXT:    lc a0, 128(a0)
 ; CHECK-LP64-NEXT:    sub a0, a1, a0
 ; CHECK-LP64-NEXT:    ret
 ;
 ; CHECK-L64PC128-LABEL: ddc_lc:
 ; CHECK-L64PC128:       # %bb.0:
-; CHECK-L64PC128-NEXT:    lc.ddc ca1, (a0)
+; CHECK-L64PC128-NEXT:    lc.ddc a1, (a0)
 ; CHECK-L64PC128-NEXT:    addi a0, a0, 128
-; CHECK-L64PC128-NEXT:    lc.ddc ca0, (a0)
+; CHECK-L64PC128-NEXT:    lc.ddc a0, (a0)
 ; CHECK-L64PC128-NEXT:    sub a0, a1, a0
 ; CHECK-L64PC128-NEXT:    cret
   %1 = load i8 addrspace(200) *, i8 addrspace(200) **%ptr
@@ -273,15 +273,15 @@ define void @ddc_sd(i64 *%ptr, i64 %val) nounwind {
 define void @ddc_sc(i8 addrspace(200) **%ptr, i8 addrspace(200) *%val) nounwind {
 ; CHECK-LP64-LABEL: ddc_sc:
 ; CHECK-LP64:       # %bb.0:
-; CHECK-LP64-NEXT:    sc ca1, 0(a0)
-; CHECK-LP64-NEXT:    sc ca1, 208(a0)
+; CHECK-LP64-NEXT:    sc a1, 0(a0)
+; CHECK-LP64-NEXT:    sc a1, 208(a0)
 ; CHECK-LP64-NEXT:    ret
 ;
 ; CHECK-L64PC128-LABEL: ddc_sc:
 ; CHECK-L64PC128:       # %bb.0:
-; CHECK-L64PC128-NEXT:    sc.ddc ca1, (a0)
+; CHECK-L64PC128-NEXT:    sc.ddc a1, (a0)
 ; CHECK-L64PC128-NEXT:    addi a0, a0, 208
-; CHECK-L64PC128-NEXT:    sc.ddc ca1, (a0)
+; CHECK-L64PC128-NEXT:    sc.ddc a1, (a0)
 ; CHECK-L64PC128-NEXT:    cret
   store i8 addrspace(200) *%val, i8 addrspace(200) **%ptr
   %1 = getelementptr i8 addrspace(200) *, i8 addrspace(200) **%ptr, i32 13
@@ -294,16 +294,16 @@ define void @ddc_sc(i8 addrspace(200) **%ptr, i8 addrspace(200) *%val) nounwind
 define dso_local i64 @cap_lb(i8 addrspace(200) *%cap) nounwind {
 ; CHECK-LP64-LABEL: cap_lb:
 ; CHECK-LP64:       # %bb.0:
-; CHECK-LP64-NEXT:    lb.cap a1, (ca0)
-; CHECK-LP64-NEXT:    cincoffset ca0, ca0, 14
-; CHECK-LP64-NEXT:    lb.cap zero, (ca0)
+; CHECK-LP64-NEXT:    lb.cap a1, (a0)
+; CHECK-LP64-NEXT:    cincoffset a0, a0, 14
+; CHECK-LP64-NEXT:    lb.cap zero, (a0)
 ; CHECK-LP64-NEXT:    mv a0, a1
 ; CHECK-LP64-NEXT:    ret
 ;
 ; CHECK-L64PC128-LABEL: cap_lb:
 ; CHECK-L64PC128:       # %bb.0:
-; CHECK-L64PC128-NEXT:    clb a1, 0(ca0)
-; CHECK-L64PC128-NEXT:    clb zero, 14(ca0)
+; CHECK-L64PC128-NEXT:    clb a1, 0(a0)
+; CHECK-L64PC128-NEXT:    clb zero, 14(a0)
 ; CHECK-L64PC128-NEXT:    mv a0, a1
 ; CHECK-L64PC128-NEXT:    cret
   %1 = load i8, i8 addrspace(200) *%cap
@@ -317,16 +317,16 @@ define dso_local i64 @cap_lb(i8 addrspace(200) *%cap) nounwind {
 define dso_local i64 @cap_lh(i16 addrspace(200) *%cap) nounwind {
 ; CHECK-LP64-LABEL: cap_lh:
 ; CHECK-LP64:       # %bb.0:
-; CHECK-LP64-NEXT:    lh.cap a1, (ca0)
-; CHECK-LP64-NEXT:    cincoffset ca0, ca0, 30
-; CHECK-LP64-NEXT:    lh.cap zero, (ca0)
+; CHECK-LP64-NEXT:    lh.cap a1, (a0)
+; CHECK-LP64-NEXT:    cincoffset a0, a0, 30
+; CHECK-LP64-NEXT:    lh.cap zero, (a0)
 ; CHECK-LP64-NEXT:    mv a0, a1
 ; CHECK-LP64-NEXT:    ret
 ;
 ; CHECK-L64PC128-LABEL: cap_lh:
 ; CHECK-L64PC128:       # %bb.0:
-; CHECK-L64PC128-NEXT:    clh a1, 0(ca0)
-; CHECK-L64PC128-NEXT:    clh zero, 30(ca0)
+; CHECK-L64PC128-NEXT:    clh a1, 0(a0)
+; CHECK-L64PC128-NEXT:    clh zero, 30(a0)
 ; CHECK-L64PC128-NEXT:    mv a0, a1
 ; CHECK-L64PC128-NEXT:    cret
   %1 = load i16, i16 addrspace(200) *%cap
@@ -340,16 +340,16 @@ define dso_local i64 @cap_lh(i16 addrspace(200) *%cap) nounwind {
 define dso_local i64 @cap_lw(i32 addrspace(200) *%cap) nounwind {
 ; CHECK-LP64-LABEL: cap_lw:
 ; CHECK-LP64:       # %bb.0:
-; CHECK-LP64-NEXT:    lw.cap a1, (ca0)
-; CHECK-LP64-NEXT:    cincoffset ca0, ca0, 64
-; CHECK-LP64-NEXT:    lw.cap zero, (ca0)
+; CHECK-LP64-NEXT:    lw.cap a1, (a0)
+; CHECK-LP64-NEXT:    cincoffset a0, a0, 64
+; CHECK-LP64-NEXT:    lw.cap zero, (a0)
 ; CHECK-LP64-NEXT:    mv a0, a1
 ; CHECK-LP64-NEXT:    ret
 ;
 ; CHECK-L64PC128-LABEL: cap_lw:
 ; CHECK-L64PC128:       # %bb.0:
-; CHECK-L64PC128-NEXT:    clw a1, 0(ca0)
-; CHECK-L64PC128-NEXT:    clw zero, 64(ca0)
+; CHECK-L64PC128-NEXT:    clw a1, 0(a0)
+; CHECK-L64PC128-NEXT:    clw zero, 64(a0)
 ; CHECK-L64PC128-NEXT:    mv a0, a1
 ; CHECK-L64PC128-NEXT:    cret
   %1 = load i32, i32 addrspace(200) *%cap
@@ -363,16 +363,16 @@ define dso_local i64 @cap_lw(i32 addrspace(200) *%cap) nounwind {
 define dso_local i64 @cap_ld(i64 addrspace(200) *%cap) nounwind {
 ; CHECK-LP64-LABEL: cap_ld:
 ; CHECK-LP64:       # %bb.0:
-; CHECK-LP64-NEXT:    ld.cap a1, (ca0)
-; CHECK-LP64-NEXT:    cincoffset ca0, ca0, 136
-; CHECK-LP64-NEXT:    ld.cap zero, (ca0)
+; CHECK-LP64-NEXT:    ld.cap a1, (a0)
+; CHECK-LP64-NEXT:    cincoffset a0, a0, 136
+; CHECK-LP64-NEXT:    ld.cap zero, (a0)
 ; CHECK-LP64-NEXT:    mv a0, a1
 ; CHECK-LP64-NEXT:    ret
 ;
 ; CHECK-L64PC128-LABEL: cap_ld:
 ; CHECK-L64PC128:       # %bb.0:
-; CHECK-L64PC128-NEXT:    cld a1, 0(ca0)
-; CHECK-L64PC128-NEXT:    cld zero, 136(ca0)
+; CHECK-L64PC128-NEXT:    cld a1, 0(a0)
+; CHECK-L64PC128-NEXT:    cld zero, 136(a0)
 ; CHECK-L64PC128-NEXT:    mv a0, a1
 ; CHECK-L64PC128-NEXT:    cret
   %1 = load i64, i64 addrspace(200) *%cap
@@ -384,16 +384,16 @@ define dso_local i64 @cap_ld(i64 addrspace(200) *%cap) nounwind {
 define dso_local i64 @cap_lbu(i8 addrspace(200) *%cap) nounwind {
 ; CHECK-LP64-LABEL: cap_lbu:
 ; CHECK-LP64:       # %bb.0:
-; CHECK-LP64-NEXT:    lbu.cap a1, (ca0)
-; CHECK-LP64-NEXT:    cincoffset ca0, ca0, 18
-; CHECK-LP64-NEXT:    lbu.cap a0, (ca0)
+; CHECK-LP64-NEXT:    lbu.cap a1, (a0)
+; CHECK-LP64-NEXT:    cincoffset a0, a0, 18
+; CHECK-LP64-NEXT:    lbu.cap a0, (a0)
 ; CHECK-LP64-NEXT:    add a0, a1, a0
 ; CHECK-LP64-NEXT:    ret
 ;
 ; CHECK-L64PC128-LABEL: cap_lbu:
 ; CHECK-L64PC128:       # %bb.0:
-; CHECK-L64PC128-NEXT:    clbu a1, 0(ca0)
-; CHECK-L64PC128-NEXT:    clbu a0, 18(ca0)
+; CHECK-L64PC128-NEXT:    clbu a1, 0(a0)
+; CHECK-L64PC128-NEXT:    clbu a0, 18(a0)
 ; CHECK-L64PC128-NEXT:    add a0, a1, a0
 ; CHECK-L64PC128-NEXT:    cret
   %1 = load i8, i8 addrspace(200) *%cap
@@ -408,16 +408,16 @@ define dso_local i64 @cap_lbu(i8 addrspace(200) *%cap) nounwind {
 define dso_local i64 @cap_lhu(i16 addrspace(200) *%cap) nounwind {
 ; CHECK-LP64-LABEL: cap_lhu:
 ; CHECK-LP64:       # %bb.0:
-; CHECK-LP64-NEXT:    lhu.cap a1, (ca0)
-; CHECK-LP64-NEXT:    cincoffset ca0, ca0, 38
-; CHECK-LP64-NEXT:    lhu.cap a0, (ca0)
+; CHECK-LP64-NEXT:    lhu.cap a1, (a0)
+; CHECK-LP64-NEXT:    cincoffset a0, a0, 38
+; CHECK-LP64-NEXT:    lhu.cap a0, (a0)
 ; CHECK-LP64-NEXT:    add a0, a1, a0
 ; CHECK-LP64-NEXT:    ret
 ;
 ; CHECK-L64PC128-LABEL: cap_lhu:
 ; CHECK-L64PC128:       # %bb.0:
-; CHECK-L64PC128-NEXT:    clhu a1, 0(ca0)
-; CHECK-L64PC128-NEXT:    clhu a0, 38(ca0)
+; CHECK-L64PC128-NEXT:    clhu a1, 0(a0)
+; CHECK-L64PC128-NEXT:    clhu a0, 38(a0)
 ; CHECK-L64PC128-NEXT:    add a0, a1, a0
 ; CHECK-L64PC128-NEXT:    cret
   %1 = load i16, i16 addrspace(200) *%cap
@@ -432,16 +432,16 @@ define dso_local i64 @cap_lhu(i16 addrspace(200) *%cap) nounwind {
 define dso_local i64 @cap_lwu(i32 addrspace(200) *%cap) nounwind {
 ; CHECK-LP64-LABEL: cap_lwu:
 ; CHECK-LP64:       # %bb.0:
-; CHECK-LP64-NEXT:    lwu.cap a1, (ca0)
-; CHECK-LP64-NEXT:    cincoffset ca0, ca0, 80
-; CHECK-LP64-NEXT:    lwu.cap a0, (ca0)
+; CHECK-LP64-NEXT:    lwu.cap a1, (a0)
+; CHECK-LP64-NEXT:    cincoffset a0, a0, 80
+; CHECK-LP64-NEXT:    lwu.cap a0, (a0)
 ; CHECK-LP64-NEXT:    add a0, a1, a0
 ; CHECK-LP64-NEXT:    ret
 ;
 ; CHECK-L64PC128-LABEL: cap_lwu:
 ; CHECK-L64PC128:       # %bb.0:
-; CHECK-L64PC128-NEXT:    clwu a1, 0(ca0)
-; CHECK-L64PC128-NEXT:    clwu a0, 80(ca0)
+; CHECK-L64PC128-NEXT:    clwu a1, 0(a0)
+; CHECK-L64PC128-NEXT:    clwu a0, 80(a0)
 ; CHECK-L64PC128-NEXT:    add a0, a1, a0
 ; CHECK-L64PC128-NEXT:    cret
   %1 = load i32, i32 addrspace(200) *%cap
@@ -456,16 +456,16 @@ define dso_local i64 @cap_lwu(i32 addrspace(200) *%cap) nounwind {
 define dso_local i64 @cap_lc(i8 addrspace(200) *addrspace(200) *%cap) nounwind {
 ; CHECK-LP64-LABEL: cap_lc:
 ; CHECK-LP64:       # %bb.0:
-; CHECK-LP64-NEXT:    lc.cap ca1, (ca0)
-; CHECK-LP64-NEXT:    cincoffset ca0, ca0, 336
-; CHECK-LP64-NEXT:    lc.cap ca0, (ca0)
+; CHECK-LP64-NEXT:    lc.cap a1, (a0)
+; CHECK-LP64-NEXT:    cincoffset a0, a0, 336
+; CHECK-LP64-NEXT:    lc.cap a0, (a0)
 ; CHECK-LP64-NEXT:    sub a0, a1, a0
 ; CHECK-LP64-NEXT:    ret
 ;
 ; CHECK-L64PC128-LABEL: cap_lc:
 ; CHECK-L64PC128:       # %bb.0:
-; CHECK-L64PC128-NEXT:    clc ca1, 0(ca0)
-; CHECK-L64PC128-NEXT:    clc ca0, 336(ca0)
+; CHECK-L64PC128-NEXT:    clc a1, 0(a0)
+; CHECK-L64PC128-NEXT:    clc a0, 336(a0)
 ; CHECK-L64PC128-NEXT:    sub a0, a1, a0
 ; CHECK-L64PC128-NEXT:    cret
   %1 = load i8 addrspace(200) *, i8 addrspace(200) *addrspace(200) *%cap
@@ -480,15 +480,15 @@ define dso_local i64 @cap_lc(i8 addrspace(200) *addrspace(200) *%cap) nounwind {
 define void @cap_sb(i8 addrspace(200) *%cap, i8 %val) nounwind {
 ; CHECK-LP64-LABEL: cap_sb:
 ; CHECK-LP64:       # %bb.0:
-; CHECK-LP64-NEXT:    sb.cap a1, (ca0)
-; CHECK-LP64-NEXT:    cincoffset ca0, ca0, 22
-; CHECK-LP64-NEXT:    sb.cap a1, (ca0)
+; CHECK-LP64-NEXT:    sb.cap a1, (a0)
+; CHECK-LP64-NEXT:    cincoffset a0, a0, 22
+; CHECK-LP64-NEXT:    sb.cap a1, (a0)
 ; CHECK-LP64-NEXT:    ret
 ;
 ; CHECK-L64PC128-LABEL: cap_sb:
 ; CHECK-L64PC128:       # %bb.0:
-; CHECK-L64PC128-NEXT:    csb a1, 0(ca0)
-; CHECK-L64PC128-NEXT:    csb a1, 22(ca0)
+; CHECK-L64PC128-NEXT:    csb a1, 0(a0)
+; CHECK-L64PC128-NEXT:    csb a1, 22(a0)
 ; CHECK-L64PC128-NEXT:    cret
   store i8 %val, i8 addrspace(200) *%cap
   %1 = getelementptr i8, i8 addrspace(200) *%cap, i32 22
@@ -499,15 +499,15 @@ define void @cap_sb(i8 addrspace(200) *%cap, i8 %val) nounwind {
 define void @cap_sh(i16 addrspace(200) *%cap, i16 %val) nounwind {
 ; CHECK-LP64-LABEL: cap_sh:
 ; CHECK-LP64:       # %bb.0:
-; CHECK-LP64-NEXT:    sh.cap a1, (ca0)
-; CHECK-LP64-NEXT:    cincoffset ca0, ca0, 46
-; CHECK-LP64-NEXT:    sh.cap a1, (ca0)
+; CHECK-LP64-NEXT:    sh.cap a1, (a0)
+; CHECK-LP64-NEXT:    cincoffset a0, a0, 46
+; CHECK-LP64-NEXT:    sh.cap a1, (a0)
 ; CHECK-LP64-NEXT:    ret
 ;
 ; CHECK-L64PC128-LABEL: cap_sh:
 ; CHECK-L64PC128:       # %bb.0:
-; CHECK-L64PC128-NEXT:    csh a1, 0(ca0)
-; CHECK-L64PC128-NEXT:    csh a1, 46(ca0)
+; CHECK-L64PC128-NEXT:    csh a1, 0(a0)
+; CHECK-L64PC128-NEXT:    csh a1, 46(a0)
 ; CHECK-L64PC128-NEXT:    cret
   store i16 %val, i16 addrspace(200) *%cap
   %1 = getelementptr i16, i16 addrspace(200) *%cap, i32 23
@@ -518,15 +518,15 @@ define void @cap_sh(i16 addrspace(200) *%cap, i16 %val) nounwind {
 define void @cap_sw(i32 addrspace(200) *%cap, i32 %val) nounwind {
 ; CHECK-LP64-LABEL: cap_sw:
 ; CHECK-LP64:       # %bb.0:
-; CHECK-LP64-NEXT:    sw.cap a1, (ca0)
-; CHECK-LP64-NEXT:    cincoffset ca0, ca0, 96
-; CHECK-LP64-NEXT:    sw.cap a1, (ca0)
+; CHECK-LP64-NEXT:    sw.cap a1, (a0)
+; CHECK-LP64-NEXT:    cincoffset a0, a0, 96
+; CHECK-LP64-NEXT:    sw.cap a1, (a0)
 ; CHECK-LP64-NEXT:    ret
 ;
 ; CHECK-L64PC128-LABEL: cap_sw:
 ; CHECK-L64PC128:       # %bb.0:
-; CHECK-L64PC128-NEXT:    csw a1, 0(ca0)
-; CHECK-L64PC128-NEXT:    csw a1, 96(ca0)
+; CHECK-L64PC128-NEXT:    csw a1, 0(a0)
+; CHECK-L64PC128-NEXT:    csw a1, 96(a0)
 ; CHECK-L64PC128-NEXT:    cret
   store i32 %val, i32 addrspace(200) *%cap
   %1 = getelementptr i32, i32 addrspace(200) *%cap, i32 24
@@ -537,15 +537,15 @@ define void @cap_sw(i32 addrspace(200) *%cap, i32 %val) nounwind {
 define void @cap_sd(i64 addrspace(200) *%cap, i64 %val) nounwind {
 ; CHECK-LP64-LABEL: cap_sd:
 ; CHECK-LP64:       # %bb.0:
-; CHECK-LP64-NEXT:    sd.cap a1, (ca0)
-; CHECK-LP64-NEXT:    cincoffset ca0, ca0, 200
-; CHECK-LP64-NEXT:    sd.cap a1, (ca0)
+; CHECK-LP64-NEXT:    sd.cap a1, (a0)
+; CHECK-LP64-NEXT:    cincoffset a0, a0, 200
+; CHECK-LP64-NEXT:    sd.cap a1, (a0)
 ; CHECK-LP64-NEXT:    ret
 ;
 ; CHECK-L64PC128-LABEL: cap_sd:
 ; CHECK-L64PC128:       # %bb.0:
-; CHECK-L64PC128-NEXT:    csd a1, 0(ca0)
-; CHECK-L64PC128-NEXT:    csd a1, 200(ca0)
+; CHECK-L64PC128-NEXT:    csd a1, 0(a0)
+; CHECK-L64PC128-NEXT:    csd a1, 200(a0)
 ; CHECK-L64PC128-NEXT:    cret
   store i64 %val, i64 addrspace(200) *%cap
   %1 = getelementptr i64, i64 addrspace(200) *%cap, i32 25
@@ -556,15 +556,15 @@ define void @cap_sd(i64 addrspace(200) *%cap, i64 %val) nounwind {
 define void @cap_sc(i8 addrspace(200) *addrspace(200) *%cap, i8 addrspace(200) *%val) nounwind {
 ; CHECK-LP64-LABEL: cap_sc:
 ; CHECK-LP64:       # %bb.0:
-; CHECK-LP64-NEXT:    sc.cap ca1, (ca0)
-; CHECK-LP64-NEXT:    cincoffset ca0, ca0, 416
-; CHECK-LP64-NEXT:    sc.cap ca1, (ca0)
+; CHECK-LP64-NEXT:    sc.cap a1, (a0)
+; CHECK-LP64-NEXT:    cincoffset a0, a0, 416
+; CHECK-LP64-NEXT:    sc.cap a1, (a0)
 ; CHECK-LP64-NEXT:    ret
 ;
 ; CHECK-L64PC128-LABEL: cap_sc:
 ; CHECK-L64PC128:       # %bb.0:
-; CHECK-L64PC128-NEXT:    csc ca1, 0(ca0)
-; CHECK-L64PC128-NEXT:    csc ca1, 416(ca0)
+; CHECK-L64PC128-NEXT:    csc a1, 0(a0)
+; CHECK-L64PC128-NEXT:    csc a1, 416(a0)
 ; CHECK-L64PC128-NEXT:    cret
   store i8 addrspace(200) *%val, i8 addrspace(200) *addrspace(200) *%cap
   %1 = getelementptr i8 addrspace(200) *, i8 addrspace(200) *addrspace(200) *%cap, i32 26
@@ -577,14 +577,14 @@ define i64 @lw_near_local(i64 addrspace(200)* %a)  {
 ; CHECK-LP64:       # %bb.0:
 ; CHECK-LP64-NEXT:    lui a1, 1
 ; CHECK-LP64-NEXT:    addi a1, a1, -2040
-; CHECK-LP64-NEXT:    cincoffset ca0, ca0, a1
-; CHECK-LP64-NEXT:    ld.cap a0, (ca0)
+; CHECK-LP64-NEXT:    cincoffset a0, a0, a1
+; CHECK-LP64-NEXT:    ld.cap a0, (a0)
 ; CHECK-LP64-NEXT:    ret
 ;
 ; CHECK-L64PC128-LABEL: lw_near_local:
 ; CHECK-L64PC128:       # %bb.0:
-; CHECK-L64PC128-NEXT:    cincoffset ca0, ca0, 2047
-; CHECK-L64PC128-NEXT:    cld a0, 9(ca0)
+; CHECK-L64PC128-NEXT:    cincoffset a0, a0, 2047
+; CHECK-L64PC128-NEXT:    cld a0, 9(a0)
 ; CHECK-L64PC128-NEXT:    cret
   %1 = getelementptr inbounds i64, i64 addrspace(200)* %a, i64 257
   %2 = load volatile i64, i64 addrspace(200)* %1
@@ -596,14 +596,14 @@ define void @st_near_local(i64 addrspace(200)* %a, i64 %b)  {
 ; CHECK-LP64:       # %bb.0:
 ; CHECK-LP64-NEXT:    lui a2, 1
 ; CHECK-LP64-NEXT:    addi a2, a2, -2040
-; CHECK-LP64-NEXT:    cincoffset ca0, ca0, a2
-; CHECK-LP64-NEXT:    sd.cap a1, (ca0)
+; CHECK-LP64-NEXT:    cincoffset a0, a0, a2
+; CHECK-LP64-NEXT:    sd.cap a1, (a0)
 ; CHECK-LP64-NEXT:    ret
 ;
 ; CHECK-L64PC128-LABEL: st_near_local:
 ; CHECK-L64PC128:       # %bb.0:
-; CHECK-L64PC128-NEXT:    cincoffset ca0, ca0, 2047
-; CHECK-L64PC128-NEXT:    csd a1, 9(ca0)
+; CHECK-L64PC128-NEXT:    cincoffset a0, a0, 2047
+; CHECK-L64PC128-NEXT:    csd a1, 9(a0)
 ; CHECK-L64PC128-NEXT:    cret
   %1 = getelementptr inbounds i64, i64 addrspace(200)* %a, i64 257
   store i64 %b, i64 addrspace(200)* %1
@@ -615,16 +615,16 @@ define i64 @lw_sw_near_local(i64 addrspace(200)* %a, i64 %b)  {
 ; CHECK-LP64:       # %bb.0:
 ; CHECK-LP64-NEXT:    lui a2, 1
 ; CHECK-LP64-NEXT:    addi a2, a2, -2040
-; CHECK-LP64-NEXT:    cincoffset ca2, ca0, a2
-; CHECK-LP64-NEXT:    ld.cap a0, (ca2)
-; CHECK-LP64-NEXT:    sd.cap a1, (ca2)
+; CHECK-LP64-NEXT:    cincoffset a2, a0, a2
+; CHECK-LP64-NEXT:    ld.cap a0, (a2)
+; CHECK-LP64-NEXT:    sd.cap a1, (a2)
 ; CHECK-LP64-NEXT:    ret
 ;
 ; CHECK-L64PC128-LABEL: lw_sw_near_local:
 ; CHECK-L64PC128:       # %bb.0:
-; CHECK-L64PC128-NEXT:    cincoffset ca2, ca0, 2047
-; CHECK-L64PC128-NEXT:    cld a0, 9(ca2)
-; CHECK-L64PC128-NEXT:    csd a1, 9(ca2)
+; CHECK-L64PC128-NEXT:    cincoffset a2, a0, 2047
+; CHECK-L64PC128-NEXT:    cld a0, 9(a2)
+; CHECK-L64PC128-NEXT:    csd a1, 9(a2)
 ; CHECK-L64PC128-NEXT:    cret
   %1 = getelementptr inbounds i64, i64 addrspace(200)* %a, i64 257
   %2 = load volatile i64, i64 addrspace(200)* %1
@@ -637,16 +637,16 @@ define i64 @lw_far_local(i64 addrspace(200)* %a)  {
 ; CHECK-LP64:       # %bb.0:
 ; CHECK-LP64-NEXT:    lui a1, 8
 ; CHECK-LP64-NEXT:    addi a1, a1, -8
-; CHECK-LP64-NEXT:    cincoffset ca0, ca0, a1
-; CHECK-LP64-NEXT:    ld.cap a0, (ca0)
+; CHECK-LP64-NEXT:    cincoffset a0, a0, a1
+; CHECK-LP64-NEXT:    ld.cap a0, (a0)
 ; CHECK-LP64-NEXT:    ret
 ;
 ; CHECK-L64PC128-LABEL: lw_far_local:
 ; CHECK-L64PC128:       # %bb.0:
 ; CHECK-L64PC128-NEXT:    lui a1, 8
 ; CHECK-L64PC128-NEXT:    addi a1, a1, -8
-; CHECK-L64PC128-NEXT:    cincoffset ca0, ca0, a1
-; CHECK-L64PC128-NEXT:    cld a0, 0(ca0)
+; CHECK-L64PC128-NEXT:    cincoffset a0, a0, a1
+; CHECK-L64PC128-NEXT:    cld a0, 0(a0)
 ; CHECK-L64PC128-NEXT:    cret
   %1 = getelementptr inbounds i64, i64 addrspace(200)* %a, i64 4095
   %2 = load volatile i64, i64 addrspace(200)* %1
@@ -658,16 +658,16 @@ define void @st_far_local(i64 addrspace(200)* %a, i64 %b)  {
 ; CHECK-LP64:       # %bb.0:
 ; CHECK-LP64-NEXT:    lui a2, 8
 ; CHECK-LP64-NEXT:    addi a2, a2, -8
-; CHECK-LP64-NEXT:    cincoffset ca0, ca0, a2
-; CHECK-LP64-NEXT:    sd.cap a1, (ca0)
+; CHECK-LP64-NEXT:    cincoffset a0, a0, a2
+; CHECK-LP64-NEXT:    sd.cap a1, (a0)
 ; CHECK-LP64-NEXT:    ret
 ;
 ; CHECK-L64PC128-LABEL: st_far_local:
 ; CHECK-L64PC128:       # %bb.0:
 ; CHECK-L64PC128-NEXT:    lui a2, 8
 ; CHECK-L64PC128-NEXT:    addi a2, a2, -8
-; CHECK-L64PC128-NEXT:    cincoffset ca0, ca0, a2
-; CHECK-L64PC128-NEXT:    csd a1, 0(ca0)
+; CHECK-L64PC128-NEXT:    cincoffset a0, a0, a2
+; CHECK-L64PC128-NEXT:    csd a1, 0(a0)
 ; CHECK-L64PC128-NEXT:    cret
   %1 = getelementptr inbounds i64, i64 addrspace(200)* %a, i64 4095
   store i64 %b, i64 addrspace(200)* %1
@@ -679,18 +679,18 @@ define i64 @lw_sw_far_local(i64 addrspace(200)* %a, i64 %b)  {
 ; CHECK-LP64:       # %bb.0:
 ; CHECK-LP64-NEXT:    lui a2, 8
 ; CHECK-LP64-NEXT:    addi a2, a2, -8
-; CHECK-LP64-NEXT:    cincoffset ca2, ca0, a2
-; CHECK-LP64-NEXT:    ld.cap a0, (ca2)
-; CHECK-LP64-NEXT:    sd.cap a1, (ca2)
+; CHECK-LP64-NEXT:    cincoffset a2, a0, a2
+; CHECK-LP64-NEXT:    ld.cap a0, (a2)
+; CHECK-LP64-NEXT:    sd.cap a1, (a2)
 ; CHECK-LP64-NEXT:    ret
 ;
 ; CHECK-L64PC128-LABEL: lw_sw_far_local:
 ; CHECK-L64PC128:       # %bb.0:
 ; CHECK-L64PC128-NEXT:    lui a2, 8
 ; CHECK-L64PC128-NEXT:    addi a2, a2, -8
-; CHECK-L64PC128-NEXT:    cincoffset ca2, ca0, a2
-; CHECK-L64PC128-NEXT:    cld a0, 0(ca2)
-; CHECK-L64PC128-NEXT:    csd a1, 0(ca2)
+; CHECK-L64PC128-NEXT:    cincoffset a2, a0, a2
+; CHECK-L64PC128-NEXT:    cld a0, 0(a2)
+; CHECK-L64PC128-NEXT:    csd a1, 0(a2)
 ; CHECK-L64PC128-NEXT:    cret
   %1 = getelementptr inbounds i64, i64 addrspace(200)* %a, i64 4095
   %2 = load volatile i64, i64 addrspace(200)* %1
@@ -705,16 +705,16 @@ define i64 @lw_really_far_local(i64 addrspace(200)* %a)  {
 ; CHECK-LP64:       # %bb.0:
 ; CHECK-LP64-NEXT:    lui a1, 524288
 ; CHECK-LP64-NEXT:    addiw a1, a1, -2048
-; CHECK-LP64-NEXT:    cincoffset ca0, ca0, a1
-; CHECK-LP64-NEXT:    ld.cap a0, (ca0)
+; CHECK-LP64-NEXT:    cincoffset a0, a0, a1
+; CHECK-LP64-NEXT:    ld.cap a0, (a0)
 ; CHECK-LP64-NEXT:    ret
 ;
 ; CHECK-L64PC128-LABEL: lw_really_far_local:
 ; CHECK-L64PC128:       # %bb.0:
 ; CHECK-L64PC128-NEXT:    lui a1, 524288
 ; CHECK-L64PC128-NEXT:    addiw a1, a1, -2048
-; CHECK-L64PC128-NEXT:    cincoffset ca0, ca0, a1
-; CHECK-L64PC128-NEXT:    cld a0, 0(ca0)
+; CHECK-L64PC128-NEXT:    cincoffset a0, a0, a1
+; CHECK-L64PC128-NEXT:    cld a0, 0(a0)
 ; CHECK-L64PC128-NEXT:    cret
   %1 = getelementptr inbounds i64, i64 addrspace(200)* %a, i64 268435200
   %2 = load volatile i64, i64 addrspace(200)* %1
@@ -728,16 +728,16 @@ define void @st_really_far_local(i64 addrspace(200)* %a, i64 %b)  {
 ; CHECK-LP64:       # %bb.0:
 ; CHECK-LP64-NEXT:    lui a2, 524288
 ; CHECK-LP64-NEXT:    addiw a2, a2, -2048
-; CHECK-LP64-NEXT:    cincoffset ca0, ca0, a2
-; CHECK-LP64-NEXT:    sd.cap a1, (ca0)
+; CHECK-LP64-NEXT:    cincoffset a0, a0, a2
+; CHECK-LP64-NEXT:    sd.cap a1, (a0)
 ; CHECK-LP64-NEXT:    ret
 ;
 ; CHECK-L64PC128-LABEL: st_really_far_local:
 ; CHECK-L64PC128:       # %bb.0:
 ; CHECK-L64PC128-NEXT:    lui a2, 524288
 ; CHECK-L64PC128-NEXT:    addiw a2, a2, -2048
-; CHECK-L64PC128-NEXT:    cincoffset ca0, ca0, a2
-; CHECK-L64PC128-NEXT:    csd a1, 0(ca0)
+; CHECK-L64PC128-NEXT:    cincoffset a0, a0, a2
+; CHECK-L64PC128-NEXT:    csd a1, 0(a0)
 ; CHECK-L64PC128-NEXT:    cret
   %1 = getelementptr inbounds i64, i64 addrspace(200)* %a, i64 268435200
   store i64 %b, i64 addrspace(200)* %1
@@ -751,18 +751,18 @@ define i64 @lw_sw_really_far_local(i64 addrspace(200)* %a, i64 %b)  {
 ; CHECK-LP64:       # %bb.0:
 ; CHECK-LP64-NEXT:    lui a2, 524288
 ; CHECK-LP64-NEXT:    addiw a2, a2, -2048
-; CHECK-LP64-NEXT:    cincoffset ca2, ca0, a2
-; CHECK-LP64-NEXT:    ld.cap a0, (ca2)
-; CHECK-LP64-NEXT:    sd.cap a1, (ca2)
+; CHECK-LP64-NEXT:    cincoffset a2, a0, a2
+; CHECK-LP64-NEXT:    ld.cap a0, (a2)
+; CHECK-LP64-NEXT:    sd.cap a1, (a2)
 ; CHECK-LP64-NEXT:    ret
 ;
 ; CHECK-L64PC128-LABEL: lw_sw_really_far_local:
 ; CHECK-L64PC128:       # %bb.0:
 ; CHECK-L64PC128-NEXT:    lui a2, 524288
 ; CHECK-L64PC128-NEXT:    addiw a2, a2, -2048
-; CHECK-L64PC128-NEXT:    cincoffset ca2, ca0, a2
-; CHECK-L64PC128-NEXT:    cld a0, 0(ca2)
-; CHECK-L64PC128-NEXT:    csd a1, 0(ca2)
+; CHECK-L64PC128-NEXT:    cincoffset a2, a0, a2
+; CHECK-L64PC128-NEXT:    cld a0, 0(a2)
+; CHECK-L64PC128-NEXT:    csd a1, 0(a2)
 ; CHECK-L64PC128-NEXT:    cret
   %1 = getelementptr inbounds i64, i64 addrspace(200)* %a, i64 268435200
   %2 = load volatile i64, i64 addrspace(200)* %1
diff --git a/llvm/test/CodeGen/RISCV/cheri/ptradd-dagcombine-infinite.ll b/llvm/test/CodeGen/RISCV/cheri/ptradd-dagcombine-infinite.ll
index 0aa64a223de93..9bd98580be98f 100644
--- a/llvm/test/CodeGen/RISCV/cheri/ptradd-dagcombine-infinite.ll
+++ b/llvm/test/CodeGen/RISCV/cheri/ptradd-dagcombine-infinite.ll
@@ -8,7 +8,7 @@
 define %struct.foo addrspace(200)* @fold_geps(i64 %arg1, %struct.foo addrspace(200)* %arg2) nounwind {
 ; CHECK-LABEL: fold_geps:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    cincoffset ca0, ca1, -32
+; CHECK-NEXT:    cincoffset a0, a1, -32
 ; CHECK-NEXT:    cret
 entry:
   %mul = mul nsw i64 0, %arg1
@@ -20,7 +20,7 @@ entry:
 define %struct.foo addrspace(200)* @fold_geps2(i64 %a, i64 %b, %struct.foo addrspace(200)* %ptr) nounwind {
 ; CHECK-LABEL: fold_geps2:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    cincoffset ca0, ca2, -32
+; CHECK-NEXT:    cincoffset a0, a2, -32
 ; CHECK-NEXT:    cret
 entry:
   %zero = sub i64 %a, %a  ; Use a fold that does not return SDValue(N, 0)
@@ -35,8 +35,8 @@ define %struct.foo addrspace(200)* @cannot_fold(i64 %arg1, %struct.foo addrspace
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mul a0, a0, a0
 ; CHECK-NEXT:    slli a0, a0, 5
-; CHECK-NEXT:    cincoffset ca0, ca1, a0
-; CHECK-NEXT:    cincoffset ca0, ca0, -32
+; CHECK-NEXT:    cincoffset a0, a1, a0
+; CHECK-NEXT:    cincoffset a0, a0, -32
 ; CHECK-NEXT:    cret
 entry:
   %mul = mul i64 %arg1, %arg1
@@ -50,8 +50,8 @@ define i8 addrspace(200)* @cannot_fold_2(i64 %arg1, i8 addrspace(200)* %ptr) nou
 ; CHECK-LABEL: cannot_fold_2:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    neg a0, a0
-; CHECK-NEXT:    cincoffset ca0, ca1, a0
-; CHECK-NEXT:    cincoffset ca0, ca0, 304
+; CHECK-NEXT:    cincoffset a0, a1, a0
+; CHECK-NEXT:    cincoffset a0, a0, 304
 ; CHECK-NEXT:    cret
 entry:
   %sub = sub i64 0, %arg1
@@ -72,14 +72,14 @@ define i8 addrspace(200)* @reassociated_node_reuses_other_node(i64 %arg1, %struc
 ; CHECK-LABEL: reassociated_node_reuses_other_node:
 ; CHECK:       # %bb.0: # %bb
 ; CHECK-NEXT:    slli a0, a0, 5
-; CHECK-NEXT:    clc ca2, 0(ca1)
+; CHECK-NEXT:    clc a2, 0(a1)
 ; CHECK-NEXT:    addi a3, a0, 16
-; CHECK-NEXT:    cincoffset ca3, ca1, a3
-; CHECK-NEXT:    csc cnull, 0(ca3)
-; CHECK-NEXT:    cincoffset ca0, ca1, a0
-; CHECK-NEXT:    csc ca2, 0(ca0)
-; CHECK-NEXT:    clc ca1, 16(ca1)
-; CHECK-NEXT:    csc ca1, 16(ca0)
+; CHECK-NEXT:    cincoffset a3, a1, a3
+; CHECK-NEXT:    csc zero, 0(a3)
+; CHECK-NEXT:    cincoffset a0, a1, a0
+; CHECK-NEXT:    csc a2, 0(a0)
+; CHECK-NEXT:    clc a1, 16(a1)
+; CHECK-NEXT:    csc a1, 16(a0)
 ; CHECK-NEXT:    cret
 bb:
   %dst0 = getelementptr inbounds %struct.bar, %struct.bar addrspace(200)* %arg2, i64 %arg1, i32 0
diff --git a/llvm/test/CodeGen/RISCV/cheri/purecap-large-frame.ll b/llvm/test/CodeGen/RISCV/cheri/purecap-large-frame.ll
index 847a1e3075aef..338dd3c37e050 100644
--- a/llvm/test/CodeGen/RISCV/cheri/purecap-large-frame.ll
+++ b/llvm/test/CodeGen/RISCV/cheri/purecap-large-frame.ll
@@ -14,18 +14,18 @@ declare i32 @use_too_large(%struct.too.large addrspace(200)*)
 define void @just_below_threshold() local_unnamed_addr addrspace(200) nounwind {
 ; CHECK-LABEL: just_below_threshold:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    cincoffset csp, csp, -2032
-; CHECK-NEXT:    csc cra, 2016(csp) # 16-byte Folded Spill
-; CHECK-NEXT:    cincoffset csp, csp, -32
-; CHECK-NEXT:    cincoffset ca0, csp, 2032
-; CHECK-NEXT:    csetbounds ca0, ca0, 16
+; CHECK-NEXT:    cincoffset sp, sp, -2032
+; CHECK-NEXT:    csc ra, 2016(sp) # 16-byte Folded Spill
+; CHECK-NEXT:    cincoffset sp, sp, -32
+; CHECK-NEXT:    cincoffset a0, sp, 2032
+; CHECK-NEXT:    csetbounds a0, a0, 16
 ; CHECK-NEXT:    ccall use_i128
-; CHECK-NEXT:    cincoffset ca0, csp, 16
-; CHECK-NEXT:    csetbounds ca0, ca0, 2014
+; CHECK-NEXT:    cincoffset a0, sp, 16
+; CHECK-NEXT:    csetbounds a0, a0, 2014
 ; CHECK-NEXT:    ccall use_large
-; CHECK-NEXT:    cincoffset csp, csp, 32
-; CHECK-NEXT:    clc cra, 2016(csp) # 16-byte Folded Reload
-; CHECK-NEXT:    cincoffset csp, csp, 2032
+; CHECK-NEXT:    cincoffset sp, sp, 32
+; CHECK-NEXT:    clc ra, 2016(sp) # 16-byte Folded Reload
+; CHECK-NEXT:    cincoffset sp, sp, 2032
 ; CHECK-NEXT:    cret
 entry:
   %obj1 = alloca i128, align 16, addrspace(200)
@@ -38,20 +38,20 @@ entry:
 define void @just_above_threshold() local_unnamed_addr addrspace(200) nounwind {
 ; CHECK-LABEL: just_above_threshold:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    cincoffset csp, csp, -2032
-; CHECK-NEXT:    csc cra, 2016(csp) # 16-byte Folded Spill
-; CHECK-NEXT:    cincoffset csp, csp, -48
+; CHECK-NEXT:    cincoffset sp, sp, -2032
+; CHECK-NEXT:    csc ra, 2016(sp) # 16-byte Folded Spill
+; CHECK-NEXT:    cincoffset sp, sp, -48
 ; CHECK-NEXT:    lui a0, 1
-; CHECK-NEXT:    cincoffset ca0, csp, a0
-; CHECK-NEXT:    cincoffset ca0, ca0, -2048
-; CHECK-NEXT:    csetbounds ca0, ca0, 16
+; CHECK-NEXT:    cincoffset a0, sp, a0
+; CHECK-NEXT:    cincoffset a0, a0, -2048
+; CHECK-NEXT:    csetbounds a0, a0, 16
 ; CHECK-NEXT:    ccall use_i128
-; CHECK-NEXT:    cincoffset ca0, csp, 24
-; CHECK-NEXT:    csetbounds ca0, ca0, 2018
+; CHECK-NEXT:    cincoffset a0, sp, 24
+; CHECK-NEXT:    csetbounds a0, a0, 2018
 ; CHECK-NEXT:    ccall use_too_large
-; CHECK-NEXT:    cincoffset csp, csp, 48
-; CHECK-NEXT:    clc cra, 2016(csp) # 16-byte Folded Reload
-; CHECK-NEXT:    cincoffset csp, csp, 2032
+; CHECK-NEXT:    cincoffset sp, sp, 48
+; CHECK-NEXT:    clc ra, 2016(sp) # 16-byte Folded Reload
+; CHECK-NEXT:    cincoffset sp, sp, 2032
 ; CHECK-NEXT:    cret
 entry:
   %obj1 = alloca i128, align 16, addrspace(200)
diff --git a/llvm/test/CodeGen/RISCV/cheri/read_write_register.ll b/llvm/test/CodeGen/RISCV/cheri/read_write_register.ll
index 87a8e86ddf3a3..e016b1489fae1 100644
--- a/llvm/test/CodeGen/RISCV/cheri/read_write_register.ll
+++ b/llvm/test/CodeGen/RISCV/cheri/read_write_register.ll
@@ -30,11 +30,11 @@ define void @set_tp(i64 %value) local_unnamed_addr #2 {
 ; FIXME: this is wrong, but is a bug upstream and not in CHERI clang (https://godbolt.org/z/WTYh5q)
 ; CHECK-L64PC128-LABEL: set_tp:
 ; CHECK-L64PC128:       # %bb.0: # %entry
-; CHECK-L64PC128-NEXT:    cincoffset csp, csp, -16
-; CHECK-L64PC128-NEXT:    csc ctp, 0(csp) # 16-byte Folded Spill
+; CHECK-L64PC128-NEXT:    cincoffset sp, sp, -16
+; CHECK-L64PC128-NEXT:    csc tp, 0(sp) # 16-byte Folded Spill
 ; CHECK-L64PC128-NEXT:    mv tp, a0
-; CHECK-L64PC128-NEXT:    clc ctp, 0(csp) # 16-byte Folded Reload
-; CHECK-L64PC128-NEXT:    cincoffset csp, csp, 16
+; CHECK-L64PC128-NEXT:    clc tp, 0(sp) # 16-byte Folded Reload
+; CHECK-L64PC128-NEXT:    cincoffset sp, sp, 16
 ; CHECK-L64PC128-NEXT:    cret
 ;
 ; CHECK-LP64-LABEL: set_tp:
@@ -53,12 +53,12 @@ declare void @llvm.write_register.i64(metadata, i64) #3
 define i8 addrspace(200)* @get_ctp() local_unnamed_addr #0 {
 ; CHECK-L64PC128-LABEL: get_ctp:
 ; CHECK-L64PC128:       # %bb.0: # %entry
-; CHECK-L64PC128-NEXT:    cmove ca0, ctp
+; CHECK-L64PC128-NEXT:    cmove a0, tp
 ; CHECK-L64PC128-NEXT:    cret
 ;
 ; CHECK-LP64-LABEL: get_ctp:
 ; CHECK-LP64:       # %bb.0: # %entry
-; CHECK-LP64-NEXT:    cmove ca0, ctp
+; CHECK-LP64-NEXT:    cmove a0, tp
 ; CHECK-LP64-NEXT:    ret
 entry:
   %0 = tail call i8 addrspace(200)* @llvm.read_register.p200i8(metadata !1)
@@ -73,16 +73,16 @@ define void @set_ctp(i8 addrspace(200)* %value) local_unnamed_addr #2 {
 ; FIXME: this is wrong, but is a bug upstream and not in CHERI clang (https://godbolt.org/z/WTYh5q)
 ; CHECK-L64PC128-LABEL: set_ctp:
 ; CHECK-L64PC128:       # %bb.0: # %entry
-; CHECK-L64PC128-NEXT:    cincoffset csp, csp, -16
-; CHECK-L64PC128-NEXT:    csc ctp, 0(csp) # 16-byte Folded Spill
-; CHECK-L64PC128-NEXT:    cmove ctp, ca0
-; CHECK-L64PC128-NEXT:    clc ctp, 0(csp) # 16-byte Folded Reload
-; CHECK-L64PC128-NEXT:    cincoffset csp, csp, 16
+; CHECK-L64PC128-NEXT:    cincoffset sp, sp, -16
+; CHECK-L64PC128-NEXT:    csc tp, 0(sp) # 16-byte Folded Spill
+; CHECK-L64PC128-NEXT:    cmove tp, a0
+; CHECK-L64PC128-NEXT:    clc tp, 0(sp) # 16-byte Folded Reload
+; CHECK-L64PC128-NEXT:    cincoffset sp, sp, 16
 ; CHECK-L64PC128-NEXT:    cret
 ;
 ; CHECK-LP64-LABEL: set_ctp:
 ; CHECK-LP64:       # %bb.0: # %entry
-; CHECK-LP64-NEXT:    cmove ctp, ca0
+; CHECK-LP64-NEXT:    cmove tp, a0
 ; CHECK-LP64-NEXT:    ret
 entry:
   tail call void @llvm.write_register.p200i8(metadata !1, i8 addrspace(200)* %value)
@@ -96,12 +96,12 @@ declare void @llvm.write_register.p200i8(metadata, i8 addrspace(200)*) #3
 define %struct.StackPtr addrspace(200)* @get_csp() local_unnamed_addr #0 {
 ; CHECK-L64PC128-LABEL: get_csp:
 ; CHECK-L64PC128:       # %bb.0: # %entry
-; CHECK-L64PC128-NEXT:    cmove ca0, csp
+; CHECK-L64PC128-NEXT:    cmove a0, sp
 ; CHECK-L64PC128-NEXT:    cret
 ;
 ; CHECK-LP64-LABEL: get_csp:
 ; CHECK-LP64:       # %bb.0: # %entry
-; CHECK-LP64-NEXT:    cmove ca0, csp
+; CHECK-LP64-NEXT:    cmove a0, sp
 ; CHECK-LP64-NEXT:    ret
 entry:
   %0 = tail call i8 addrspace(200)* @llvm.read_register.p200i8(metadata !2)
@@ -113,12 +113,12 @@ entry:
 define void @set_csp(%struct.StackPtr addrspace(200)* %value) local_unnamed_addr #2 {
 ; CHECK-L64PC128-LABEL: set_csp:
 ; CHECK-L64PC128:       # %bb.0: # %entry
-; CHECK-L64PC128-NEXT:    cmove csp, ca0
+; CHECK-L64PC128-NEXT:    cmove sp, a0
 ; CHECK-L64PC128-NEXT:    cret
 ;
 ; CHECK-LP64-LABEL: set_csp:
 ; CHECK-LP64:       # %bb.0: # %entry
-; CHECK-LP64-NEXT:    cmove csp, ca0
+; CHECK-LP64-NEXT:    cmove sp, a0
 ; CHECK-LP64-NEXT:    ret
 entry:
   %0 = bitcast %struct.StackPtr addrspace(200)* %value to i8 addrspace(200)*
@@ -151,16 +151,16 @@ define void @set_gp_addr(i64 %value) local_unnamed_addr #2 {
 ; FIXME: this is wrong, but is a bug upstream and not in CHERI clang (https://godbolt.org/z/WTYh5q)
 ; CHECK-L64PC128-LABEL: set_gp_addr:
 ; CHECK-L64PC128:       # %bb.0: # %entry
-; CHECK-L64PC128-NEXT:    cincoffset csp, csp, -16
-; CHECK-L64PC128-NEXT:    csc cgp, 0(csp) # 16-byte Folded Spill
-; CHECK-L64PC128-NEXT:    cincoffset cgp, cnull, a0
-; CHECK-L64PC128-NEXT:    clc cgp, 0(csp) # 16-byte Folded Reload
-; CHECK-L64PC128-NEXT:    cincoffset csp, csp, 16
+; CHECK-L64PC128-NEXT:    cincoffset sp, sp, -16
+; CHECK-L64PC128-NEXT:    csc gp, 0(sp) # 16-byte Folded Spill
+; CHECK-L64PC128-NEXT:    cincoffset gp, zero, a0
+; CHECK-L64PC128-NEXT:    clc gp, 0(sp) # 16-byte Folded Reload
+; CHECK-L64PC128-NEXT:    cincoffset sp, sp, 16
 ; CHECK-L64PC128-NEXT:    cret
 ;
 ; CHECK-LP64-LABEL: set_gp_addr:
 ; CHECK-LP64:       # %bb.0: # %entry
-; CHECK-LP64-NEXT:    cincoffset cgp, cnull, a0
+; CHECK-LP64-NEXT:    cincoffset gp, zero, a0
 ; CHECK-LP64-NEXT:    ret
 entry:
   %0 = getelementptr i8, i8 addrspace(200)* null, i64 %value
diff --git a/llvm/test/CodeGen/RISCV/cheri/realign-stack.ll b/llvm/test/CodeGen/RISCV/cheri/realign-stack.ll
index ec011a3766a1b..627f74287e34c 100644
--- a/llvm/test/CodeGen/RISCV/cheri/realign-stack.ll
+++ b/llvm/test/CodeGen/RISCV/cheri/realign-stack.ll
@@ -9,34 +9,34 @@
 define i8 addrspace(200)* @pluto() addrspace(200) nounwind {
 ; IL32PC64-LABEL: pluto:
 ; IL32PC64:       # %bb.0: # %bb
-; IL32PC64-NEXT:    cincoffset csp, csp, -128
-; IL32PC64-NEXT:    csc cra, 120(csp) # 8-byte Folded Spill
-; IL32PC64-NEXT:    csc cs0, 112(csp) # 8-byte Folded Spill
-; IL32PC64-NEXT:    cincoffset cs0, csp, 128
+; IL32PC64-NEXT:    cincoffset sp, sp, -128
+; IL32PC64-NEXT:    csc ra, 120(sp) # 8-byte Folded Spill
+; IL32PC64-NEXT:    csc s0, 112(sp) # 8-byte Folded Spill
+; IL32PC64-NEXT:    cincoffset s0, sp, 128
 ; IL32PC64-NEXT:    andi a0, sp, -64
-; IL32PC64-NEXT:    csetaddr csp, csp, a0
-; IL32PC64-NEXT:    cincoffset ca0, csp, 0
-; IL32PC64-NEXT:    csetbounds ca0, ca0, 64
-; IL32PC64-NEXT:    cincoffset csp, cs0, -128
-; IL32PC64-NEXT:    clc cra, 120(csp) # 8-byte Folded Reload
-; IL32PC64-NEXT:    clc cs0, 112(csp) # 8-byte Folded Reload
-; IL32PC64-NEXT:    cincoffset csp, csp, 128
+; IL32PC64-NEXT:    csetaddr sp, sp, a0
+; IL32PC64-NEXT:    cincoffset a0, sp, 0
+; IL32PC64-NEXT:    csetbounds a0, a0, 64
+; IL32PC64-NEXT:    cincoffset sp, s0, -128
+; IL32PC64-NEXT:    clc ra, 120(sp) # 8-byte Folded Reload
+; IL32PC64-NEXT:    clc s0, 112(sp) # 8-byte Folded Reload
+; IL32PC64-NEXT:    cincoffset sp, sp, 128
 ; IL32PC64-NEXT:    cret
 ;
 ; L64PC128-LABEL: pluto:
 ; L64PC128:       # %bb.0: # %bb
-; L64PC128-NEXT:    cincoffset csp, csp, -128
-; L64PC128-NEXT:    csc cra, 112(csp) # 16-byte Folded Spill
-; L64PC128-NEXT:    csc cs0, 96(csp) # 16-byte Folded Spill
-; L64PC128-NEXT:    cincoffset cs0, csp, 128
+; L64PC128-NEXT:    cincoffset sp, sp, -128
+; L64PC128-NEXT:    csc ra, 112(sp) # 16-byte Folded Spill
+; L64PC128-NEXT:    csc s0, 96(sp) # 16-byte Folded Spill
+; L64PC128-NEXT:    cincoffset s0, sp, 128
 ; L64PC128-NEXT:    andi a0, sp, -64
-; L64PC128-NEXT:    csetaddr csp, csp, a0
-; L64PC128-NEXT:    cincoffset ca0, csp, 0
-; L64PC128-NEXT:    csetbounds ca0, ca0, 64
-; L64PC128-NEXT:    cincoffset csp, cs0, -128
-; L64PC128-NEXT:    clc cra, 112(csp) # 16-byte Folded Reload
-; L64PC128-NEXT:    clc cs0, 96(csp) # 16-byte Folded Reload
-; L64PC128-NEXT:    cincoffset csp, csp, 128
+; L64PC128-NEXT:    csetaddr sp, sp, a0
+; L64PC128-NEXT:    cincoffset a0, sp, 0
+; L64PC128-NEXT:    csetbounds a0, a0, 64
+; L64PC128-NEXT:    cincoffset sp, s0, -128
+; L64PC128-NEXT:    clc ra, 112(sp) # 16-byte Folded Reload
+; L64PC128-NEXT:    clc s0, 96(sp) # 16-byte Folded Reload
+; L64PC128-NEXT:    cincoffset sp, sp, 128
 ; L64PC128-NEXT:    cret
 bb:
   %tmp = alloca %struct.wobble, align 64, addrspace(200)
diff --git a/llvm/test/CodeGen/RISCV/cheri/rematerialize.mir b/llvm/test/CodeGen/RISCV/cheri/rematerialize.mir
index 0040b587661e5..91a12a2df4d48 100644
--- a/llvm/test/CodeGen/RISCV/cheri/rematerialize.mir
+++ b/llvm/test/CodeGen/RISCV/cheri/rematerialize.mir
@@ -21,9 +21,9 @@ failedISel:      false
 tracksRegLiveness: true
 hasWinCFI:       false
 registers:
-  - { id: 0, class: gpcr, preferred-register: '' }
-  - { id: 1, class: gpcr, preferred-register: '' }
-  - { id: 2, class: gpcr, preferred-register: '' }
+  - { id: 0, class: ygpr, preferred-register: '' }
+  - { id: 1, class: ygpr, preferred-register: '' }
+  - { id: 2, class: ygpr, preferred-register: '' }
 liveins:         []
 frameInfo:
   isFrameAddressTaken: false
@@ -52,53 +52,53 @@ machineFunctionInfo: {}
 body:             |
   bb.0 (%ir-block.0):
     ; CHECK-LABEL: name: test_remat
-    ; CHECK: ADJCALLSTACKDOWNCAP 0, 0, implicit-def dead $c2, implicit $c2
-    ; CHECK-NEXT: dead %5:gpcr = PseudoCLGC @external_fn
-    ; CHECK-NEXT: $c23 = COPY $c2
-    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpcr = COPY $c23
-    ; CHECK-NEXT: [[CIncOffsetImm:%[0-9]+]]:gpcr = CIncOffsetImm [[COPY]], 321
-    ; CHECK-NEXT: $c10 = CIncOffsetImm $c0, 123
-    ; CHECK-NEXT: $c11 = CMove $c0
-    ; CHECK-NEXT: $c12 = COPY [[CIncOffsetImm]]
-    ; CHECK-NEXT: PseudoCCALL target-flags(riscv-ccall) @external_fn, csr_il32pc64_l64pc128, implicit-def dead $c1, implicit killed $c10, implicit killed $c11, implicit killed $c12, implicit-def $c2
-    ; CHECK-NEXT: ADJCALLSTACKUPCAP 0, 0, implicit-def dead $c2, implicit $c2
-    ; CHECK-NEXT: ADJCALLSTACKDOWNCAP 0, 0, implicit-def dead $c2, implicit $c2
-    ; CHECK-NEXT: $c10 = CIncOffsetImm $c0, 123
-    ; CHECK-NEXT: $c11 = CMove $c0
-    ; CHECK-NEXT: $c12 = COPY [[CIncOffsetImm]]
-    ; CHECK-NEXT: PseudoCCALL target-flags(riscv-ccall) @external_fn, csr_il32pc64_l64pc128, implicit-def dead $c1, implicit killed $c10, implicit killed $c11, implicit killed $c12, implicit-def $c2
-    ; CHECK-NEXT: ADJCALLSTACKUPCAP 0, 0, implicit-def dead $c2, implicit $c2
-    ; CHECK-NEXT: ADJCALLSTACKDOWNCAP 0, 0, implicit-def dead $c2, implicit $c2
-    ; CHECK-NEXT: $c10 = CIncOffsetImm $c0, 123
-    ; CHECK-NEXT: $c11 = CMove $c0
-    ; CHECK-NEXT: $c12 = COPY [[CIncOffsetImm]]
-    ; CHECK-NEXT: PseudoCCALL target-flags(riscv-ccall) @external_fn, csr_il32pc64_l64pc128, implicit-def dead $c1, implicit killed $c10, implicit killed $c11, implicit killed $c12, implicit-def $c2
-    ; CHECK-NEXT: ADJCALLSTACKUPCAP 0, 0, implicit-def dead $c2, implicit $c2
+    ; CHECK: ADJCALLSTACKDOWNCAP 0, 0, implicit-def dead $x2_y, implicit $x2_y
+    ; CHECK-NEXT: dead %5:ygpr = PseudoCLGC @external_fn
+    ; CHECK-NEXT: $x23_y = COPY $x2_y
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:ygpr = COPY $x23_y
+    ; CHECK-NEXT: [[CIncOffsetImm:%[0-9]+]]:ygpr = CIncOffsetImm [[COPY]], 321
+    ; CHECK-NEXT: $x10_y = CIncOffsetImm $x0_y, 123
+    ; CHECK-NEXT: $x11_y = CMove $x0_y
+    ; CHECK-NEXT: $x12_y = COPY [[CIncOffsetImm]]
+    ; CHECK-NEXT: PseudoCCALL target-flags(riscv-ccall) @external_fn, csr_il32pc64_l64pc128, implicit-def dead $x1_y, implicit killed $x10_y, implicit killed $x11_y, implicit killed $x12_y, implicit-def $x2_y
+    ; CHECK-NEXT: ADJCALLSTACKUPCAP 0, 0, implicit-def dead $x2_y, implicit $x2_y
+    ; CHECK-NEXT: ADJCALLSTACKDOWNCAP 0, 0, implicit-def dead $x2_y, implicit $x2_y
+    ; CHECK-NEXT: $x10_y = CIncOffsetImm $x0_y, 123
+    ; CHECK-NEXT: $x11_y = CMove $x0_y
+    ; CHECK-NEXT: $x12_y = COPY [[CIncOffsetImm]]
+    ; CHECK-NEXT: PseudoCCALL target-flags(riscv-ccall) @external_fn, csr_il32pc64_l64pc128, implicit-def dead $x1_y, implicit killed $x10_y, implicit killed $x11_y, implicit killed $x12_y, implicit-def $x2_y
+    ; CHECK-NEXT: ADJCALLSTACKUPCAP 0, 0, implicit-def dead $x2_y, implicit $x2_y
+    ; CHECK-NEXT: ADJCALLSTACKDOWNCAP 0, 0, implicit-def dead $x2_y, implicit $x2_y
+    ; CHECK-NEXT: $x10_y = CIncOffsetImm $x0_y, 123
+    ; CHECK-NEXT: $x11_y = CMove $x0_y
+    ; CHECK-NEXT: $x12_y = COPY [[CIncOffsetImm]]
+    ; CHECK-NEXT: PseudoCCALL target-flags(riscv-ccall) @external_fn, csr_il32pc64_l64pc128, implicit-def dead $x1_y, implicit killed $x10_y, implicit killed $x11_y, implicit killed $x12_y, implicit-def $x2_y
+    ; CHECK-NEXT: ADJCALLSTACKUPCAP 0, 0, implicit-def dead $x2_y, implicit $x2_y
     ; CHECK-NEXT: PseudoCRET
-    ADJCALLSTACKDOWNCAP 0, 0, implicit-def dead $c2, implicit $c2
-    %0:gpcr = COPY $c0
-    %1:gpcr = CIncOffsetImm %0, 123
-    %2:gpcr = PseudoCLGC @external_fn
-    %2:gpcr = CMove killed %0
-    $c23 = COPY $c2
-    %3:gpcr = COPY $c23
-    %4:gpcr = CIncOffsetImm %3, 321
-    $c10 = COPY %1
-    $c11 = COPY %2
-    $c12 = COPY %4
-    PseudoCCALL target-flags(riscv-ccall) @external_fn, csr_il32pc64_l64pc128, implicit-def dead $c1, implicit killed $c10, implicit killed $c11, implicit killed $c12, implicit-def $c2
-    ADJCALLSTACKUPCAP 0, 0, implicit-def dead $c2, implicit $c2
-    ADJCALLSTACKDOWNCAP 0, 0, implicit-def dead $c2, implicit $c2
-    $c10 = COPY %1
-    $c11 = COPY %2
-    $c12 = COPY %4
-    PseudoCCALL target-flags(riscv-ccall) @external_fn, csr_il32pc64_l64pc128, implicit-def dead $c1, implicit killed $c10, implicit killed $c11, implicit killed $c12, implicit-def $c2
-    ADJCALLSTACKUPCAP 0, 0, implicit-def dead $c2, implicit $c2
-    ADJCALLSTACKDOWNCAP 0, 0, implicit-def dead $c2, implicit $c2
-    $c10 = COPY killed %1
-    $c11 = COPY %2
-    $c12 = COPY %4
-    PseudoCCALL target-flags(riscv-ccall) @external_fn, csr_il32pc64_l64pc128, implicit-def dead $c1, implicit killed $c10, implicit killed $c11, implicit killed $c12, implicit-def $c2
-    ADJCALLSTACKUPCAP 0, 0, implicit-def dead $c2, implicit $c2
+    ADJCALLSTACKDOWNCAP 0, 0, implicit-def dead $x2_y, implicit $x2_y
+    %0:ygpr = COPY $x0_y
+    %1:ygpr = CIncOffsetImm %0, 123
+    %2:ygpr = PseudoCLGC @external_fn
+    %2:ygpr = CMove killed %0
+    $x23_y = COPY $x2_y
+    %3:ygpr = COPY $x23_y
+    %4:ygpr = CIncOffsetImm %3, 321
+    $x10_y = COPY %1
+    $x11_y = COPY %2
+    $x12_y = COPY %4
+    PseudoCCALL target-flags(riscv-ccall) @external_fn, csr_il32pc64_l64pc128, implicit-def dead $x1_y, implicit killed $x10_y, implicit killed $x11_y, implicit killed $x12_y, implicit-def $x2_y
+    ADJCALLSTACKUPCAP 0, 0, implicit-def dead $x2_y, implicit $x2_y
+    ADJCALLSTACKDOWNCAP 0, 0, implicit-def dead $x2_y, implicit $x2_y
+    $x10_y = COPY %1
+    $x11_y = COPY %2
+    $x12_y = COPY %4
+    PseudoCCALL target-flags(riscv-ccall) @external_fn, csr_il32pc64_l64pc128, implicit-def dead $x1_y, implicit killed $x10_y, implicit killed $x11_y, implicit killed $x12_y, implicit-def $x2_y
+    ADJCALLSTACKUPCAP 0, 0, implicit-def dead $x2_y, implicit $x2_y
+    ADJCALLSTACKDOWNCAP 0, 0, implicit-def dead $x2_y, implicit $x2_y
+    $x10_y = COPY killed %1
+    $x11_y = COPY %2
+    $x12_y = COPY %4
+    PseudoCCALL target-flags(riscv-ccall) @external_fn, csr_il32pc64_l64pc128, implicit-def dead $x1_y, implicit killed $x10_y, implicit killed $x11_y, implicit killed $x12_y, implicit-def $x2_y
+    ADJCALLSTACKUPCAP 0, 0, implicit-def dead $x2_y, implicit $x2_y
     PseudoCRET
 ...
diff --git a/llvm/test/CodeGen/RISCV/cheri/rv32-double-calling-conv.ll b/llvm/test/CodeGen/RISCV/cheri/rv32-double-calling-conv.ll
index 6c6f390380e2f..31fb687d808ba 100644
--- a/llvm/test/CodeGen/RISCV/cheri/rv32-double-calling-conv.ll
+++ b/llvm/test/CodeGen/RISCV/cheri/rv32-double-calling-conv.ll
@@ -15,66 +15,66 @@ declare void @fixed(double)
 define void @calls_fixed(double %d) nounwind {
 ; RV32IXCHERI-IL32PC64-LABEL: calls_fixed:
 ; RV32IXCHERI-IL32PC64:       # %bb.0:
-; RV32IXCHERI-IL32PC64-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-IL32PC64-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-IL32PC64-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-IL32PC64-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-IL32PC64-NEXT:    lui a3, 261888
 ; RV32IXCHERI-IL32PC64-NEXT:    li a2, 0
 ; RV32IXCHERI-IL32PC64-NEXT:    ccall __adddf3
-; RV32IXCHERI-IL32PC64-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-IL32PC64-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-IL32PC64-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-IL32PC64-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-IL32PC64-NEXT:    ctail fixed
 ;
 ; RV32IFDXCHERI-IL32PC64-LABEL: calls_fixed:
 ; RV32IFDXCHERI-IL32PC64:       # %bb.0:
-; RV32IFDXCHERI-IL32PC64-NEXT:    cincoffset csp, csp, -16
-; RV32IFDXCHERI-IL32PC64-NEXT:    csw a0, 8(csp)
-; RV32IFDXCHERI-IL32PC64-NEXT:    csw a1, 12(csp)
+; RV32IFDXCHERI-IL32PC64-NEXT:    cincoffset sp, sp, -16
+; RV32IFDXCHERI-IL32PC64-NEXT:    csw a0, 8(sp)
+; RV32IFDXCHERI-IL32PC64-NEXT:    csw a1, 12(sp)
 ; RV32IFDXCHERI-IL32PC64-NEXT:  .LBB0_1: # Label of block must be emitted
-; RV32IFDXCHERI-IL32PC64-NEXT:    auipcc ca0, %pcrel_hi(.LCPI0_0)
-; RV32IFDXCHERI-IL32PC64-NEXT:    cincoffset ca0, ca0, %pcrel_lo(.LBB0_1)
-; RV32IFDXCHERI-IL32PC64-NEXT:    cfld fa5, 8(csp)
-; RV32IFDXCHERI-IL32PC64-NEXT:    cfld fa4, 0(ca0)
+; RV32IFDXCHERI-IL32PC64-NEXT:    auipcc a0, %pcrel_hi(.LCPI0_0)
+; RV32IFDXCHERI-IL32PC64-NEXT:    cincoffset a0, a0, %pcrel_lo(.LBB0_1)
+; RV32IFDXCHERI-IL32PC64-NEXT:    cfld fa5, 8(sp)
+; RV32IFDXCHERI-IL32PC64-NEXT:    cfld fa4, 0(a0)
 ; RV32IFDXCHERI-IL32PC64-NEXT:    fadd.d fa5, fa5, fa4
-; RV32IFDXCHERI-IL32PC64-NEXT:    cfsd fa5, 8(csp)
-; RV32IFDXCHERI-IL32PC64-NEXT:    clw a0, 8(csp)
-; RV32IFDXCHERI-IL32PC64-NEXT:    clw a1, 12(csp)
-; RV32IFDXCHERI-IL32PC64-NEXT:    cincoffset csp, csp, 16
+; RV32IFDXCHERI-IL32PC64-NEXT:    cfsd fa5, 8(sp)
+; RV32IFDXCHERI-IL32PC64-NEXT:    clw a0, 8(sp)
+; RV32IFDXCHERI-IL32PC64-NEXT:    clw a1, 12(sp)
+; RV32IFDXCHERI-IL32PC64-NEXT:    cincoffset sp, sp, 16
 ; RV32IFDXCHERI-IL32PC64-NEXT:    ctail fixed
 ;
 ; RV32IFXCHERI-IL32PC64F-LABEL: calls_fixed:
 ; RV32IFXCHERI-IL32PC64F:       # %bb.0:
-; RV32IFXCHERI-IL32PC64F-NEXT:    cincoffset csp, csp, -16
-; RV32IFXCHERI-IL32PC64F-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IFXCHERI-IL32PC64F-NEXT:    cincoffset sp, sp, -16
+; RV32IFXCHERI-IL32PC64F-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IFXCHERI-IL32PC64F-NEXT:    lui a3, 261888
 ; RV32IFXCHERI-IL32PC64F-NEXT:    li a2, 0
 ; RV32IFXCHERI-IL32PC64F-NEXT:    ccall __adddf3
-; RV32IFXCHERI-IL32PC64F-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IFXCHERI-IL32PC64F-NEXT:    cincoffset csp, csp, 16
+; RV32IFXCHERI-IL32PC64F-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IFXCHERI-IL32PC64F-NEXT:    cincoffset sp, sp, 16
 ; RV32IFXCHERI-IL32PC64F-NEXT:    ctail fixed
 ;
 ; RV32IFDXCHERI-IL32PC64F-LABEL: calls_fixed:
 ; RV32IFDXCHERI-IL32PC64F:       # %bb.0:
-; RV32IFDXCHERI-IL32PC64F-NEXT:    cincoffset csp, csp, -16
-; RV32IFDXCHERI-IL32PC64F-NEXT:    csw a0, 8(csp)
-; RV32IFDXCHERI-IL32PC64F-NEXT:    csw a1, 12(csp)
+; RV32IFDXCHERI-IL32PC64F-NEXT:    cincoffset sp, sp, -16
+; RV32IFDXCHERI-IL32PC64F-NEXT:    csw a0, 8(sp)
+; RV32IFDXCHERI-IL32PC64F-NEXT:    csw a1, 12(sp)
 ; RV32IFDXCHERI-IL32PC64F-NEXT:  .LBB0_1: # Label of block must be emitted
-; RV32IFDXCHERI-IL32PC64F-NEXT:    auipcc ca0, %pcrel_hi(.LCPI0_0)
-; RV32IFDXCHERI-IL32PC64F-NEXT:    cincoffset ca0, ca0, %pcrel_lo(.LBB0_1)
-; RV32IFDXCHERI-IL32PC64F-NEXT:    cfld fa5, 8(csp)
-; RV32IFDXCHERI-IL32PC64F-NEXT:    cfld fa4, 0(ca0)
+; RV32IFDXCHERI-IL32PC64F-NEXT:    auipcc a0, %pcrel_hi(.LCPI0_0)
+; RV32IFDXCHERI-IL32PC64F-NEXT:    cincoffset a0, a0, %pcrel_lo(.LBB0_1)
+; RV32IFDXCHERI-IL32PC64F-NEXT:    cfld fa5, 8(sp)
+; RV32IFDXCHERI-IL32PC64F-NEXT:    cfld fa4, 0(a0)
 ; RV32IFDXCHERI-IL32PC64F-NEXT:    fadd.d fa5, fa5, fa4
-; RV32IFDXCHERI-IL32PC64F-NEXT:    cfsd fa5, 8(csp)
-; RV32IFDXCHERI-IL32PC64F-NEXT:    clw a0, 8(csp)
-; RV32IFDXCHERI-IL32PC64F-NEXT:    clw a1, 12(csp)
-; RV32IFDXCHERI-IL32PC64F-NEXT:    cincoffset csp, csp, 16
+; RV32IFDXCHERI-IL32PC64F-NEXT:    cfsd fa5, 8(sp)
+; RV32IFDXCHERI-IL32PC64F-NEXT:    clw a0, 8(sp)
+; RV32IFDXCHERI-IL32PC64F-NEXT:    clw a1, 12(sp)
+; RV32IFDXCHERI-IL32PC64F-NEXT:    cincoffset sp, sp, 16
 ; RV32IFDXCHERI-IL32PC64F-NEXT:    ctail fixed
 ;
 ; RV32IFDXCHERI-IL32PC64D-LABEL: calls_fixed:
 ; RV32IFDXCHERI-IL32PC64D:       # %bb.0:
 ; RV32IFDXCHERI-IL32PC64D-NEXT:  .LBB0_1: # Label of block must be emitted
-; RV32IFDXCHERI-IL32PC64D-NEXT:    auipcc ca0, %pcrel_hi(.LCPI0_0)
-; RV32IFDXCHERI-IL32PC64D-NEXT:    cincoffset ca0, ca0, %pcrel_lo(.LBB0_1)
-; RV32IFDXCHERI-IL32PC64D-NEXT:    cfld fa5, 0(ca0)
+; RV32IFDXCHERI-IL32PC64D-NEXT:    auipcc a0, %pcrel_hi(.LCPI0_0)
+; RV32IFDXCHERI-IL32PC64D-NEXT:    cincoffset a0, a0, %pcrel_lo(.LBB0_1)
+; RV32IFDXCHERI-IL32PC64D-NEXT:    cfld fa5, 0(a0)
 ; RV32IFDXCHERI-IL32PC64D-NEXT:    fadd.d fa0, fa0, fa5
 ; RV32IFDXCHERI-IL32PC64D-NEXT:    ctail fixed
   %e = fadd double %d, 1.0
@@ -87,81 +87,81 @@ declare void @vararg(...)
 define void @calls_vararg(double %d) nounwind {
 ; RV32IXCHERI-IL32PC64-LABEL: calls_vararg:
 ; RV32IXCHERI-IL32PC64:       # %bb.0:
-; RV32IXCHERI-IL32PC64-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-IL32PC64-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-IL32PC64-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-IL32PC64-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-IL32PC64-NEXT:    lui a3, 261888
 ; RV32IXCHERI-IL32PC64-NEXT:    li a2, 0
 ; RV32IXCHERI-IL32PC64-NEXT:    ccall __adddf3
-; RV32IXCHERI-IL32PC64-NEXT:    csw a1, 4(csp)
-; RV32IXCHERI-IL32PC64-NEXT:    csw a0, 0(csp)
+; RV32IXCHERI-IL32PC64-NEXT:    csw a1, 4(sp)
+; RV32IXCHERI-IL32PC64-NEXT:    csw a0, 0(sp)
 ; RV32IXCHERI-IL32PC64-NEXT:    ccall vararg
-; RV32IXCHERI-IL32PC64-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-IL32PC64-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-IL32PC64-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-IL32PC64-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-IL32PC64-NEXT:    cret
 ;
 ; RV32IFDXCHERI-IL32PC64-LABEL: calls_vararg:
 ; RV32IFDXCHERI-IL32PC64:       # %bb.0:
-; RV32IFDXCHERI-IL32PC64-NEXT:    cincoffset csp, csp, -32
-; RV32IFDXCHERI-IL32PC64-NEXT:    csc cra, 24(csp) # 8-byte Folded Spill
-; RV32IFDXCHERI-IL32PC64-NEXT:    csw a0, 16(csp)
-; RV32IFDXCHERI-IL32PC64-NEXT:    csw a1, 20(csp)
+; RV32IFDXCHERI-IL32PC64-NEXT:    cincoffset sp, sp, -32
+; RV32IFDXCHERI-IL32PC64-NEXT:    csc ra, 24(sp) # 8-byte Folded Spill
+; RV32IFDXCHERI-IL32PC64-NEXT:    csw a0, 16(sp)
+; RV32IFDXCHERI-IL32PC64-NEXT:    csw a1, 20(sp)
 ; RV32IFDXCHERI-IL32PC64-NEXT:  .LBB1_1: # Label of block must be emitted
-; RV32IFDXCHERI-IL32PC64-NEXT:    auipcc ca0, %pcrel_hi(.LCPI1_0)
-; RV32IFDXCHERI-IL32PC64-NEXT:    cincoffset ca0, ca0, %pcrel_lo(.LBB1_1)
-; RV32IFDXCHERI-IL32PC64-NEXT:    cfld fa5, 16(csp)
-; RV32IFDXCHERI-IL32PC64-NEXT:    cfld fa4, 0(ca0)
+; RV32IFDXCHERI-IL32PC64-NEXT:    auipcc a0, %pcrel_hi(.LCPI1_0)
+; RV32IFDXCHERI-IL32PC64-NEXT:    cincoffset a0, a0, %pcrel_lo(.LBB1_1)
+; RV32IFDXCHERI-IL32PC64-NEXT:    cfld fa5, 16(sp)
+; RV32IFDXCHERI-IL32PC64-NEXT:    cfld fa4, 0(a0)
 ; RV32IFDXCHERI-IL32PC64-NEXT:    fadd.d fa5, fa5, fa4
-; RV32IFDXCHERI-IL32PC64-NEXT:    cfsd fa5, 0(csp)
+; RV32IFDXCHERI-IL32PC64-NEXT:    cfsd fa5, 0(sp)
 ; RV32IFDXCHERI-IL32PC64-NEXT:    ccall vararg
-; RV32IFDXCHERI-IL32PC64-NEXT:    clc cra, 24(csp) # 8-byte Folded Reload
-; RV32IFDXCHERI-IL32PC64-NEXT:    cincoffset csp, csp, 32
+; RV32IFDXCHERI-IL32PC64-NEXT:    clc ra, 24(sp) # 8-byte Folded Reload
+; RV32IFDXCHERI-IL32PC64-NEXT:    cincoffset sp, sp, 32
 ; RV32IFDXCHERI-IL32PC64-NEXT:    cret
 ;
 ; RV32IFXCHERI-IL32PC64F-LABEL: calls_vararg:
 ; RV32IFXCHERI-IL32PC64F:       # %bb.0:
-; RV32IFXCHERI-IL32PC64F-NEXT:    cincoffset csp, csp, -16
-; RV32IFXCHERI-IL32PC64F-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IFXCHERI-IL32PC64F-NEXT:    cincoffset sp, sp, -16
+; RV32IFXCHERI-IL32PC64F-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IFXCHERI-IL32PC64F-NEXT:    lui a3, 261888
 ; RV32IFXCHERI-IL32PC64F-NEXT:    li a2, 0
 ; RV32IFXCHERI-IL32PC64F-NEXT:    ccall __adddf3
-; RV32IFXCHERI-IL32PC64F-NEXT:    csw a1, 4(csp)
-; RV32IFXCHERI-IL32PC64F-NEXT:    csw a0, 0(csp)
+; RV32IFXCHERI-IL32PC64F-NEXT:    csw a1, 4(sp)
+; RV32IFXCHERI-IL32PC64F-NEXT:    csw a0, 0(sp)
 ; RV32IFXCHERI-IL32PC64F-NEXT:    ccall vararg
-; RV32IFXCHERI-IL32PC64F-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IFXCHERI-IL32PC64F-NEXT:    cincoffset csp, csp, 16
+; RV32IFXCHERI-IL32PC64F-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IFXCHERI-IL32PC64F-NEXT:    cincoffset sp, sp, 16
 ; RV32IFXCHERI-IL32PC64F-NEXT:    cret
 ;
 ; RV32IFDXCHERI-IL32PC64F-LABEL: calls_vararg:
 ; RV32IFDXCHERI-IL32PC64F:       # %bb.0:
-; RV32IFDXCHERI-IL32PC64F-NEXT:    cincoffset csp, csp, -32
-; RV32IFDXCHERI-IL32PC64F-NEXT:    csc cra, 24(csp) # 8-byte Folded Spill
-; RV32IFDXCHERI-IL32PC64F-NEXT:    csw a0, 16(csp)
-; RV32IFDXCHERI-IL32PC64F-NEXT:    csw a1, 20(csp)
+; RV32IFDXCHERI-IL32PC64F-NEXT:    cincoffset sp, sp, -32
+; RV32IFDXCHERI-IL32PC64F-NEXT:    csc ra, 24(sp) # 8-byte Folded Spill
+; RV32IFDXCHERI-IL32PC64F-NEXT:    csw a0, 16(sp)
+; RV32IFDXCHERI-IL32PC64F-NEXT:    csw a1, 20(sp)
 ; RV32IFDXCHERI-IL32PC64F-NEXT:  .LBB1_1: # Label of block must be emitted
-; RV32IFDXCHERI-IL32PC64F-NEXT:    auipcc ca0, %pcrel_hi(.LCPI1_0)
-; RV32IFDXCHERI-IL32PC64F-NEXT:    cincoffset ca0, ca0, %pcrel_lo(.LBB1_1)
-; RV32IFDXCHERI-IL32PC64F-NEXT:    cfld fa5, 16(csp)
-; RV32IFDXCHERI-IL32PC64F-NEXT:    cfld fa4, 0(ca0)
+; RV32IFDXCHERI-IL32PC64F-NEXT:    auipcc a0, %pcrel_hi(.LCPI1_0)
+; RV32IFDXCHERI-IL32PC64F-NEXT:    cincoffset a0, a0, %pcrel_lo(.LBB1_1)
+; RV32IFDXCHERI-IL32PC64F-NEXT:    cfld fa5, 16(sp)
+; RV32IFDXCHERI-IL32PC64F-NEXT:    cfld fa4, 0(a0)
 ; RV32IFDXCHERI-IL32PC64F-NEXT:    fadd.d fa5, fa5, fa4
-; RV32IFDXCHERI-IL32PC64F-NEXT:    cfsd fa5, 0(csp)
+; RV32IFDXCHERI-IL32PC64F-NEXT:    cfsd fa5, 0(sp)
 ; RV32IFDXCHERI-IL32PC64F-NEXT:    ccall vararg
-; RV32IFDXCHERI-IL32PC64F-NEXT:    clc cra, 24(csp) # 8-byte Folded Reload
-; RV32IFDXCHERI-IL32PC64F-NEXT:    cincoffset csp, csp, 32
+; RV32IFDXCHERI-IL32PC64F-NEXT:    clc ra, 24(sp) # 8-byte Folded Reload
+; RV32IFDXCHERI-IL32PC64F-NEXT:    cincoffset sp, sp, 32
 ; RV32IFDXCHERI-IL32PC64F-NEXT:    cret
 ;
 ; RV32IFDXCHERI-IL32PC64D-LABEL: calls_vararg:
 ; RV32IFDXCHERI-IL32PC64D:       # %bb.0:
-; RV32IFDXCHERI-IL32PC64D-NEXT:    cincoffset csp, csp, -16
-; RV32IFDXCHERI-IL32PC64D-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IFDXCHERI-IL32PC64D-NEXT:    cincoffset sp, sp, -16
+; RV32IFDXCHERI-IL32PC64D-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IFDXCHERI-IL32PC64D-NEXT:  .LBB1_1: # Label of block must be emitted
-; RV32IFDXCHERI-IL32PC64D-NEXT:    auipcc ca0, %pcrel_hi(.LCPI1_0)
-; RV32IFDXCHERI-IL32PC64D-NEXT:    cincoffset ca0, ca0, %pcrel_lo(.LBB1_1)
-; RV32IFDXCHERI-IL32PC64D-NEXT:    cfld fa5, 0(ca0)
+; RV32IFDXCHERI-IL32PC64D-NEXT:    auipcc a0, %pcrel_hi(.LCPI1_0)
+; RV32IFDXCHERI-IL32PC64D-NEXT:    cincoffset a0, a0, %pcrel_lo(.LBB1_1)
+; RV32IFDXCHERI-IL32PC64D-NEXT:    cfld fa5, 0(a0)
 ; RV32IFDXCHERI-IL32PC64D-NEXT:    fadd.d fa5, fa0, fa5
-; RV32IFDXCHERI-IL32PC64D-NEXT:    cfsd fa5, 0(csp)
+; RV32IFDXCHERI-IL32PC64D-NEXT:    cfsd fa5, 0(sp)
 ; RV32IFDXCHERI-IL32PC64D-NEXT:    ccall vararg
-; RV32IFDXCHERI-IL32PC64D-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IFDXCHERI-IL32PC64D-NEXT:    cincoffset csp, csp, 16
+; RV32IFDXCHERI-IL32PC64D-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IFDXCHERI-IL32PC64D-NEXT:    cincoffset sp, sp, 16
 ; RV32IFDXCHERI-IL32PC64D-NEXT:    cret
   %e = fadd double %d, 1.0
   tail call void (...) @vararg(double %e)
@@ -173,80 +173,80 @@ declare double @return()
 define double @calls_return() nounwind {
 ; RV32IXCHERI-IL32PC64-LABEL: calls_return:
 ; RV32IXCHERI-IL32PC64:       # %bb.0:
-; RV32IXCHERI-IL32PC64-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-IL32PC64-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IXCHERI-IL32PC64-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-IL32PC64-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-IL32PC64-NEXT:    ccall return
 ; RV32IXCHERI-IL32PC64-NEXT:    lui a3, 261888
 ; RV32IXCHERI-IL32PC64-NEXT:    li a2, 0
 ; RV32IXCHERI-IL32PC64-NEXT:    ccall __adddf3
-; RV32IXCHERI-IL32PC64-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-IL32PC64-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-IL32PC64-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-IL32PC64-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-IL32PC64-NEXT:    cret
 ;
 ; RV32IFDXCHERI-IL32PC64-LABEL: calls_return:
 ; RV32IFDXCHERI-IL32PC64:       # %bb.0:
-; RV32IFDXCHERI-IL32PC64-NEXT:    cincoffset csp, csp, -16
-; RV32IFDXCHERI-IL32PC64-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IFDXCHERI-IL32PC64-NEXT:    cincoffset sp, sp, -16
+; RV32IFDXCHERI-IL32PC64-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IFDXCHERI-IL32PC64-NEXT:    ccall return
-; RV32IFDXCHERI-IL32PC64-NEXT:    csw a0, 0(csp)
-; RV32IFDXCHERI-IL32PC64-NEXT:    csw a1, 4(csp)
+; RV32IFDXCHERI-IL32PC64-NEXT:    csw a0, 0(sp)
+; RV32IFDXCHERI-IL32PC64-NEXT:    csw a1, 4(sp)
 ; RV32IFDXCHERI-IL32PC64-NEXT:  .LBB2_1: # Label of block must be emitted
-; RV32IFDXCHERI-IL32PC64-NEXT:    auipcc ca0, %pcrel_hi(.LCPI2_0)
-; RV32IFDXCHERI-IL32PC64-NEXT:    cincoffset ca0, ca0, %pcrel_lo(.LBB2_1)
-; RV32IFDXCHERI-IL32PC64-NEXT:    cfld fa5, 0(csp)
-; RV32IFDXCHERI-IL32PC64-NEXT:    cfld fa4, 0(ca0)
+; RV32IFDXCHERI-IL32PC64-NEXT:    auipcc a0, %pcrel_hi(.LCPI2_0)
+; RV32IFDXCHERI-IL32PC64-NEXT:    cincoffset a0, a0, %pcrel_lo(.LBB2_1)
+; RV32IFDXCHERI-IL32PC64-NEXT:    cfld fa5, 0(sp)
+; RV32IFDXCHERI-IL32PC64-NEXT:    cfld fa4, 0(a0)
 ; RV32IFDXCHERI-IL32PC64-NEXT:    fadd.d fa5, fa5, fa4
-; RV32IFDXCHERI-IL32PC64-NEXT:    cfsd fa5, 0(csp)
-; RV32IFDXCHERI-IL32PC64-NEXT:    clw a0, 0(csp)
-; RV32IFDXCHERI-IL32PC64-NEXT:    clw a1, 4(csp)
-; RV32IFDXCHERI-IL32PC64-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IFDXCHERI-IL32PC64-NEXT:    cincoffset csp, csp, 16
+; RV32IFDXCHERI-IL32PC64-NEXT:    cfsd fa5, 0(sp)
+; RV32IFDXCHERI-IL32PC64-NEXT:    clw a0, 0(sp)
+; RV32IFDXCHERI-IL32PC64-NEXT:    clw a1, 4(sp)
+; RV32IFDXCHERI-IL32PC64-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IFDXCHERI-IL32PC64-NEXT:    cincoffset sp, sp, 16
 ; RV32IFDXCHERI-IL32PC64-NEXT:    cret
 ;
 ; RV32IFXCHERI-IL32PC64F-LABEL: calls_return:
 ; RV32IFXCHERI-IL32PC64F:       # %bb.0:
-; RV32IFXCHERI-IL32PC64F-NEXT:    cincoffset csp, csp, -16
-; RV32IFXCHERI-IL32PC64F-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IFXCHERI-IL32PC64F-NEXT:    cincoffset sp, sp, -16
+; RV32IFXCHERI-IL32PC64F-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IFXCHERI-IL32PC64F-NEXT:    ccall return
 ; RV32IFXCHERI-IL32PC64F-NEXT:    lui a3, 261888
 ; RV32IFXCHERI-IL32PC64F-NEXT:    li a2, 0
 ; RV32IFXCHERI-IL32PC64F-NEXT:    ccall __adddf3
-; RV32IFXCHERI-IL32PC64F-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IFXCHERI-IL32PC64F-NEXT:    cincoffset csp, csp, 16
+; RV32IFXCHERI-IL32PC64F-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IFXCHERI-IL32PC64F-NEXT:    cincoffset sp, sp, 16
 ; RV32IFXCHERI-IL32PC64F-NEXT:    cret
 ;
 ; RV32IFDXCHERI-IL32PC64F-LABEL: calls_return:
 ; RV32IFDXCHERI-IL32PC64F:       # %bb.0:
-; RV32IFDXCHERI-IL32PC64F-NEXT:    cincoffset csp, csp, -16
-; RV32IFDXCHERI-IL32PC64F-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IFDXCHERI-IL32PC64F-NEXT:    cincoffset sp, sp, -16
+; RV32IFDXCHERI-IL32PC64F-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IFDXCHERI-IL32PC64F-NEXT:    ccall return
-; RV32IFDXCHERI-IL32PC64F-NEXT:    csw a0, 0(csp)
-; RV32IFDXCHERI-IL32PC64F-NEXT:    csw a1, 4(csp)
+; RV32IFDXCHERI-IL32PC64F-NEXT:    csw a0, 0(sp)
+; RV32IFDXCHERI-IL32PC64F-NEXT:    csw a1, 4(sp)
 ; RV32IFDXCHERI-IL32PC64F-NEXT:  .LBB2_1: # Label of block must be emitted
-; RV32IFDXCHERI-IL32PC64F-NEXT:    auipcc ca0, %pcrel_hi(.LCPI2_0)
-; RV32IFDXCHERI-IL32PC64F-NEXT:    cincoffset ca0, ca0, %pcrel_lo(.LBB2_1)
-; RV32IFDXCHERI-IL32PC64F-NEXT:    cfld fa5, 0(csp)
-; RV32IFDXCHERI-IL32PC64F-NEXT:    cfld fa4, 0(ca0)
+; RV32IFDXCHERI-IL32PC64F-NEXT:    auipcc a0, %pcrel_hi(.LCPI2_0)
+; RV32IFDXCHERI-IL32PC64F-NEXT:    cincoffset a0, a0, %pcrel_lo(.LBB2_1)
+; RV32IFDXCHERI-IL32PC64F-NEXT:    cfld fa5, 0(sp)
+; RV32IFDXCHERI-IL32PC64F-NEXT:    cfld fa4, 0(a0)
 ; RV32IFDXCHERI-IL32PC64F-NEXT:    fadd.d fa5, fa5, fa4
-; RV32IFDXCHERI-IL32PC64F-NEXT:    cfsd fa5, 0(csp)
-; RV32IFDXCHERI-IL32PC64F-NEXT:    clw a0, 0(csp)
-; RV32IFDXCHERI-IL32PC64F-NEXT:    clw a1, 4(csp)
-; RV32IFDXCHERI-IL32PC64F-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IFDXCHERI-IL32PC64F-NEXT:    cincoffset csp, csp, 16
+; RV32IFDXCHERI-IL32PC64F-NEXT:    cfsd fa5, 0(sp)
+; RV32IFDXCHERI-IL32PC64F-NEXT:    clw a0, 0(sp)
+; RV32IFDXCHERI-IL32PC64F-NEXT:    clw a1, 4(sp)
+; RV32IFDXCHERI-IL32PC64F-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IFDXCHERI-IL32PC64F-NEXT:    cincoffset sp, sp, 16
 ; RV32IFDXCHERI-IL32PC64F-NEXT:    cret
 ;
 ; RV32IFDXCHERI-IL32PC64D-LABEL: calls_return:
 ; RV32IFDXCHERI-IL32PC64D:       # %bb.0:
-; RV32IFDXCHERI-IL32PC64D-NEXT:    cincoffset csp, csp, -16
-; RV32IFDXCHERI-IL32PC64D-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; RV32IFDXCHERI-IL32PC64D-NEXT:    cincoffset sp, sp, -16
+; RV32IFDXCHERI-IL32PC64D-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; RV32IFDXCHERI-IL32PC64D-NEXT:    ccall return
 ; RV32IFDXCHERI-IL32PC64D-NEXT:  .LBB2_1: # Label of block must be emitted
-; RV32IFDXCHERI-IL32PC64D-NEXT:    auipcc ca0, %pcrel_hi(.LCPI2_0)
-; RV32IFDXCHERI-IL32PC64D-NEXT:    cincoffset ca0, ca0, %pcrel_lo(.LBB2_1)
-; RV32IFDXCHERI-IL32PC64D-NEXT:    cfld fa5, 0(ca0)
+; RV32IFDXCHERI-IL32PC64D-NEXT:    auipcc a0, %pcrel_hi(.LCPI2_0)
+; RV32IFDXCHERI-IL32PC64D-NEXT:    cincoffset a0, a0, %pcrel_lo(.LBB2_1)
+; RV32IFDXCHERI-IL32PC64D-NEXT:    cfld fa5, 0(a0)
 ; RV32IFDXCHERI-IL32PC64D-NEXT:    fadd.d fa0, fa0, fa5
-; RV32IFDXCHERI-IL32PC64D-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IFDXCHERI-IL32PC64D-NEXT:    cincoffset csp, csp, 16
+; RV32IFDXCHERI-IL32PC64D-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IFDXCHERI-IL32PC64D-NEXT:    cincoffset sp, sp, 16
 ; RV32IFDXCHERI-IL32PC64D-NEXT:    cret
   %d = tail call double @return()
   %e = fadd double %d, 1.0
@@ -258,15 +258,15 @@ declare void @fixed_soft_split(i32, i32, i32, i32, i32, i32, i32, double)
 define void @calls_fixed_soft_split(i32, i32, i32, i32, i32, i32, i32, double %d) nounwind {
 ; RV32IXCHERI-IL32PC64-LABEL: calls_fixed_soft_split:
 ; RV32IXCHERI-IL32PC64:       # %bb.0:
-; RV32IXCHERI-IL32PC64-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-IL32PC64-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-IL32PC64-NEXT:    clw a1, 16(csp)
+; RV32IXCHERI-IL32PC64-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-IL32PC64-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-IL32PC64-NEXT:    clw a1, 16(sp)
 ; RV32IXCHERI-IL32PC64-NEXT:    mv a0, a7
 ; RV32IXCHERI-IL32PC64-NEXT:    lui a3, 261888
 ; RV32IXCHERI-IL32PC64-NEXT:    li a2, 0
 ; RV32IXCHERI-IL32PC64-NEXT:    ccall __adddf3
 ; RV32IXCHERI-IL32PC64-NEXT:    mv a7, a0
-; RV32IXCHERI-IL32PC64-NEXT:    csw a1, 0(csp)
+; RV32IXCHERI-IL32PC64-NEXT:    csw a1, 0(sp)
 ; RV32IXCHERI-IL32PC64-NEXT:    li a0, 0
 ; RV32IXCHERI-IL32PC64-NEXT:    li a1, 0
 ; RV32IXCHERI-IL32PC64-NEXT:    li a2, 0
@@ -275,27 +275,27 @@ define void @calls_fixed_soft_split(i32, i32, i32, i32, i32, i32, i32, double %d
 ; RV32IXCHERI-IL32PC64-NEXT:    li a5, 0
 ; RV32IXCHERI-IL32PC64-NEXT:    li a6, 0
 ; RV32IXCHERI-IL32PC64-NEXT:    ccall fixed_soft_split
-; RV32IXCHERI-IL32PC64-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-IL32PC64-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-IL32PC64-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-IL32PC64-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-IL32PC64-NEXT:    cret
 ;
 ; RV32IFDXCHERI-IL32PC64-LABEL: calls_fixed_soft_split:
 ; RV32IFDXCHERI-IL32PC64:       # %bb.0:
-; RV32IFDXCHERI-IL32PC64-NEXT:    cincoffset csp, csp, -32
-; RV32IFDXCHERI-IL32PC64-NEXT:    csc cra, 24(csp) # 8-byte Folded Spill
-; RV32IFDXCHERI-IL32PC64-NEXT:    clw a0, 32(csp)
-; RV32IFDXCHERI-IL32PC64-NEXT:    csw a7, 16(csp)
+; RV32IFDXCHERI-IL32PC64-NEXT:    cincoffset sp, sp, -32
+; RV32IFDXCHERI-IL32PC64-NEXT:    csc ra, 24(sp) # 8-byte Folded Spill
+; RV32IFDXCHERI-IL32PC64-NEXT:    clw a0, 32(sp)
+; RV32IFDXCHERI-IL32PC64-NEXT:    csw a7, 16(sp)
 ; RV32IFDXCHERI-IL32PC64-NEXT:  .LBB3_1: # Label of block must be emitted
-; RV32IFDXCHERI-IL32PC64-NEXT:    auipcc ca1, %pcrel_hi(.LCPI3_0)
-; RV32IFDXCHERI-IL32PC64-NEXT:    cincoffset ca1, ca1, %pcrel_lo(.LBB3_1)
-; RV32IFDXCHERI-IL32PC64-NEXT:    cfld fa5, 0(ca1)
-; RV32IFDXCHERI-IL32PC64-NEXT:    csw a0, 20(csp)
-; RV32IFDXCHERI-IL32PC64-NEXT:    cfld fa4, 16(csp)
+; RV32IFDXCHERI-IL32PC64-NEXT:    auipcc a1, %pcrel_hi(.LCPI3_0)
+; RV32IFDXCHERI-IL32PC64-NEXT:    cincoffset a1, a1, %pcrel_lo(.LBB3_1)
+; RV32IFDXCHERI-IL32PC64-NEXT:    cfld fa5, 0(a1)
+; RV32IFDXCHERI-IL32PC64-NEXT:    csw a0, 20(sp)
+; RV32IFDXCHERI-IL32PC64-NEXT:    cfld fa4, 16(sp)
 ; RV32IFDXCHERI-IL32PC64-NEXT:    fadd.d fa5, fa4, fa5
-; RV32IFDXCHERI-IL32PC64-NEXT:    cfsd fa5, 16(csp)
-; RV32IFDXCHERI-IL32PC64-NEXT:    clw a7, 16(csp)
-; RV32IFDXCHERI-IL32PC64-NEXT:    clw a0, 20(csp)
-; RV32IFDXCHERI-IL32PC64-NEXT:    csw a0, 0(csp)
+; RV32IFDXCHERI-IL32PC64-NEXT:    cfsd fa5, 16(sp)
+; RV32IFDXCHERI-IL32PC64-NEXT:    clw a7, 16(sp)
+; RV32IFDXCHERI-IL32PC64-NEXT:    clw a0, 20(sp)
+; RV32IFDXCHERI-IL32PC64-NEXT:    csw a0, 0(sp)
 ; RV32IFDXCHERI-IL32PC64-NEXT:    li a0, 0
 ; RV32IFDXCHERI-IL32PC64-NEXT:    li a1, 0
 ; RV32IFDXCHERI-IL32PC64-NEXT:    li a2, 0
@@ -304,21 +304,21 @@ define void @calls_fixed_soft_split(i32, i32, i32, i32, i32, i32, i32, double %d
 ; RV32IFDXCHERI-IL32PC64-NEXT:    li a5, 0
 ; RV32IFDXCHERI-IL32PC64-NEXT:    li a6, 0
 ; RV32IFDXCHERI-IL32PC64-NEXT:    ccall fixed_soft_split
-; RV32IFDXCHERI-IL32PC64-NEXT:    clc cra, 24(csp) # 8-byte Folded Reload
-; RV32IFDXCHERI-IL32PC64-NEXT:    cincoffset csp, csp, 32
+; RV32IFDXCHERI-IL32PC64-NEXT:    clc ra, 24(sp) # 8-byte Folded Reload
+; RV32IFDXCHERI-IL32PC64-NEXT:    cincoffset sp, sp, 32
 ; RV32IFDXCHERI-IL32PC64-NEXT:    cret
 ;
 ; RV32IFXCHERI-IL32PC64F-LABEL: calls_fixed_soft_split:
 ; RV32IFXCHERI-IL32PC64F:       # %bb.0:
-; RV32IFXCHERI-IL32PC64F-NEXT:    cincoffset csp, csp, -16
-; RV32IFXCHERI-IL32PC64F-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; RV32IFXCHERI-IL32PC64F-NEXT:    clw a1, 16(csp)
+; RV32IFXCHERI-IL32PC64F-NEXT:    cincoffset sp, sp, -16
+; RV32IFXCHERI-IL32PC64F-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; RV32IFXCHERI-IL32PC64F-NEXT:    clw a1, 16(sp)
 ; RV32IFXCHERI-IL32PC64F-NEXT:    mv a0, a7
 ; RV32IFXCHERI-IL32PC64F-NEXT:    lui a3, 261888
 ; RV32IFXCHERI-IL32PC64F-NEXT:    li a2, 0
 ; RV32IFXCHERI-IL32PC64F-NEXT:    ccall __adddf3
 ; RV32IFXCHERI-IL32PC64F-NEXT:    mv a7, a0
-; RV32IFXCHERI-IL32PC64F-NEXT:    csw a1, 0(csp)
+; RV32IFXCHERI-IL32PC64F-NEXT:    csw a1, 0(sp)
 ; RV32IFXCHERI-IL32PC64F-NEXT:    li a0, 0
 ; RV32IFXCHERI-IL32PC64F-NEXT:    li a1, 0
 ; RV32IFXCHERI-IL32PC64F-NEXT:    li a2, 0
@@ -327,27 +327,27 @@ define void @calls_fixed_soft_split(i32, i32, i32, i32, i32, i32, i32, double %d
 ; RV32IFXCHERI-IL32PC64F-NEXT:    li a5, 0
 ; RV32IFXCHERI-IL32PC64F-NEXT:    li a6, 0
 ; RV32IFXCHERI-IL32PC64F-NEXT:    ccall fixed_soft_split
-; RV32IFXCHERI-IL32PC64F-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IFXCHERI-IL32PC64F-NEXT:    cincoffset csp, csp, 16
+; RV32IFXCHERI-IL32PC64F-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IFXCHERI-IL32PC64F-NEXT:    cincoffset sp, sp, 16
 ; RV32IFXCHERI-IL32PC64F-NEXT:    cret
 ;
 ; RV32IFDXCHERI-IL32PC64F-LABEL: calls_fixed_soft_split:
 ; RV32IFDXCHERI-IL32PC64F:       # %bb.0:
-; RV32IFDXCHERI-IL32PC64F-NEXT:    cincoffset csp, csp, -32
-; RV32IFDXCHERI-IL32PC64F-NEXT:    csc cra, 24(csp) # 8-byte Folded Spill
-; RV32IFDXCHERI-IL32PC64F-NEXT:    clw a0, 32(csp)
-; RV32IFDXCHERI-IL32PC64F-NEXT:    csw a7, 16(csp)
+; RV32IFDXCHERI-IL32PC64F-NEXT:    cincoffset sp, sp, -32
+; RV32IFDXCHERI-IL32PC64F-NEXT:    csc ra, 24(sp) # 8-byte Folded Spill
+; RV32IFDXCHERI-IL32PC64F-NEXT:    clw a0, 32(sp)
+; RV32IFDXCHERI-IL32PC64F-NEXT:    csw a7, 16(sp)
 ; RV32IFDXCHERI-IL32PC64F-NEXT:  .LBB3_1: # Label of block must be emitted
-; RV32IFDXCHERI-IL32PC64F-NEXT:    auipcc ca1, %pcrel_hi(.LCPI3_0)
-; RV32IFDXCHERI-IL32PC64F-NEXT:    cincoffset ca1, ca1, %pcrel_lo(.LBB3_1)
-; RV32IFDXCHERI-IL32PC64F-NEXT:    cfld fa5, 0(ca1)
-; RV32IFDXCHERI-IL32PC64F-NEXT:    csw a0, 20(csp)
-; RV32IFDXCHERI-IL32PC64F-NEXT:    cfld fa4, 16(csp)
+; RV32IFDXCHERI-IL32PC64F-NEXT:    auipcc a1, %pcrel_hi(.LCPI3_0)
+; RV32IFDXCHERI-IL32PC64F-NEXT:    cincoffset a1, a1, %pcrel_lo(.LBB3_1)
+; RV32IFDXCHERI-IL32PC64F-NEXT:    cfld fa5, 0(a1)
+; RV32IFDXCHERI-IL32PC64F-NEXT:    csw a0, 20(sp)
+; RV32IFDXCHERI-IL32PC64F-NEXT:    cfld fa4, 16(sp)
 ; RV32IFDXCHERI-IL32PC64F-NEXT:    fadd.d fa5, fa4, fa5
-; RV32IFDXCHERI-IL32PC64F-NEXT:    cfsd fa5, 16(csp)
-; RV32IFDXCHERI-IL32PC64F-NEXT:    clw a7, 16(csp)
-; RV32IFDXCHERI-IL32PC64F-NEXT:    clw a0, 20(csp)
-; RV32IFDXCHERI-IL32PC64F-NEXT:    csw a0, 0(csp)
+; RV32IFDXCHERI-IL32PC64F-NEXT:    cfsd fa5, 16(sp)
+; RV32IFDXCHERI-IL32PC64F-NEXT:    clw a7, 16(sp)
+; RV32IFDXCHERI-IL32PC64F-NEXT:    clw a0, 20(sp)
+; RV32IFDXCHERI-IL32PC64F-NEXT:    csw a0, 0(sp)
 ; RV32IFDXCHERI-IL32PC64F-NEXT:    li a0, 0
 ; RV32IFDXCHERI-IL32PC64F-NEXT:    li a1, 0
 ; RV32IFDXCHERI-IL32PC64F-NEXT:    li a2, 0
@@ -356,16 +356,16 @@ define void @calls_fixed_soft_split(i32, i32, i32, i32, i32, i32, i32, double %d
 ; RV32IFDXCHERI-IL32PC64F-NEXT:    li a5, 0
 ; RV32IFDXCHERI-IL32PC64F-NEXT:    li a6, 0
 ; RV32IFDXCHERI-IL32PC64F-NEXT:    ccall fixed_soft_split
-; RV32IFDXCHERI-IL32PC64F-NEXT:    clc cra, 24(csp) # 8-byte Folded Reload
-; RV32IFDXCHERI-IL32PC64F-NEXT:    cincoffset csp, csp, 32
+; RV32IFDXCHERI-IL32PC64F-NEXT:    clc ra, 24(sp) # 8-byte Folded Reload
+; RV32IFDXCHERI-IL32PC64F-NEXT:    cincoffset sp, sp, 32
 ; RV32IFDXCHERI-IL32PC64F-NEXT:    cret
 ;
 ; RV32IFDXCHERI-IL32PC64D-LABEL: calls_fixed_soft_split:
 ; RV32IFDXCHERI-IL32PC64D:       # %bb.0:
 ; RV32IFDXCHERI-IL32PC64D-NEXT:  .LBB3_1: # Label of block must be emitted
-; RV32IFDXCHERI-IL32PC64D-NEXT:    auipcc ca0, %pcrel_hi(.LCPI3_0)
-; RV32IFDXCHERI-IL32PC64D-NEXT:    cincoffset ca0, ca0, %pcrel_lo(.LBB3_1)
-; RV32IFDXCHERI-IL32PC64D-NEXT:    cfld fa5, 0(ca0)
+; RV32IFDXCHERI-IL32PC64D-NEXT:    auipcc a0, %pcrel_hi(.LCPI3_0)
+; RV32IFDXCHERI-IL32PC64D-NEXT:    cincoffset a0, a0, %pcrel_lo(.LBB3_1)
+; RV32IFDXCHERI-IL32PC64D-NEXT:    cfld fa5, 0(a0)
 ; RV32IFDXCHERI-IL32PC64D-NEXT:    fadd.d fa0, fa0, fa5
 ; RV32IFDXCHERI-IL32PC64D-NEXT:    li a0, 0
 ; RV32IFDXCHERI-IL32PC64D-NEXT:    li a1, 0
@@ -385,15 +385,15 @@ declare void @fixed_soft_stack(i32, i32, i32, i32, i32, i32, i32, i32, double)
 define void @calls_fixed_soft_stack(i32, i32, i32, i32, i32, i32, i32, i32, double %d) nounwind {
 ; RV32IXCHERI-IL32PC64-LABEL: calls_fixed_soft_stack:
 ; RV32IXCHERI-IL32PC64:       # %bb.0:
-; RV32IXCHERI-IL32PC64-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-IL32PC64-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-IL32PC64-NEXT:    clw a0, 16(csp)
-; RV32IXCHERI-IL32PC64-NEXT:    clw a1, 20(csp)
+; RV32IXCHERI-IL32PC64-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-IL32PC64-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-IL32PC64-NEXT:    clw a0, 16(sp)
+; RV32IXCHERI-IL32PC64-NEXT:    clw a1, 20(sp)
 ; RV32IXCHERI-IL32PC64-NEXT:    lui a3, 261888
 ; RV32IXCHERI-IL32PC64-NEXT:    li a2, 0
 ; RV32IXCHERI-IL32PC64-NEXT:    ccall __adddf3
-; RV32IXCHERI-IL32PC64-NEXT:    csw a1, 4(csp)
-; RV32IXCHERI-IL32PC64-NEXT:    csw a0, 0(csp)
+; RV32IXCHERI-IL32PC64-NEXT:    csw a1, 4(sp)
+; RV32IXCHERI-IL32PC64-NEXT:    csw a0, 0(sp)
 ; RV32IXCHERI-IL32PC64-NEXT:    li a0, 0
 ; RV32IXCHERI-IL32PC64-NEXT:    li a1, 0
 ; RV32IXCHERI-IL32PC64-NEXT:    li a2, 0
@@ -403,21 +403,21 @@ define void @calls_fixed_soft_stack(i32, i32, i32, i32, i32, i32, i32, i32, doub
 ; RV32IXCHERI-IL32PC64-NEXT:    li a6, 0
 ; RV32IXCHERI-IL32PC64-NEXT:    li a7, 0
 ; RV32IXCHERI-IL32PC64-NEXT:    ccall fixed_soft_stack
-; RV32IXCHERI-IL32PC64-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-IL32PC64-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-IL32PC64-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-IL32PC64-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-IL32PC64-NEXT:    cret
 ;
 ; RV32IFDXCHERI-IL32PC64-LABEL: calls_fixed_soft_stack:
 ; RV32IFDXCHERI-IL32PC64:       # %bb.0:
-; RV32IFDXCHERI-IL32PC64-NEXT:    cincoffset csp, csp, -16
-; RV32IFDXCHERI-IL32PC64-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; RV32IFDXCHERI-IL32PC64-NEXT:    cfld fa5, 16(csp)
+; RV32IFDXCHERI-IL32PC64-NEXT:    cincoffset sp, sp, -16
+; RV32IFDXCHERI-IL32PC64-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; RV32IFDXCHERI-IL32PC64-NEXT:    cfld fa5, 16(sp)
 ; RV32IFDXCHERI-IL32PC64-NEXT:  .LBB4_1: # Label of block must be emitted
-; RV32IFDXCHERI-IL32PC64-NEXT:    auipcc ca0, %pcrel_hi(.LCPI4_0)
-; RV32IFDXCHERI-IL32PC64-NEXT:    cincoffset ca0, ca0, %pcrel_lo(.LBB4_1)
-; RV32IFDXCHERI-IL32PC64-NEXT:    cfld fa4, 0(ca0)
+; RV32IFDXCHERI-IL32PC64-NEXT:    auipcc a0, %pcrel_hi(.LCPI4_0)
+; RV32IFDXCHERI-IL32PC64-NEXT:    cincoffset a0, a0, %pcrel_lo(.LBB4_1)
+; RV32IFDXCHERI-IL32PC64-NEXT:    cfld fa4, 0(a0)
 ; RV32IFDXCHERI-IL32PC64-NEXT:    fadd.d fa5, fa5, fa4
-; RV32IFDXCHERI-IL32PC64-NEXT:    cfsd fa5, 0(csp)
+; RV32IFDXCHERI-IL32PC64-NEXT:    cfsd fa5, 0(sp)
 ; RV32IFDXCHERI-IL32PC64-NEXT:    li a0, 0
 ; RV32IFDXCHERI-IL32PC64-NEXT:    li a1, 0
 ; RV32IFDXCHERI-IL32PC64-NEXT:    li a2, 0
@@ -427,21 +427,21 @@ define void @calls_fixed_soft_stack(i32, i32, i32, i32, i32, i32, i32, i32, doub
 ; RV32IFDXCHERI-IL32PC64-NEXT:    li a6, 0
 ; RV32IFDXCHERI-IL32PC64-NEXT:    li a7, 0
 ; RV32IFDXCHERI-IL32PC64-NEXT:    ccall fixed_soft_stack
-; RV32IFDXCHERI-IL32PC64-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IFDXCHERI-IL32PC64-NEXT:    cincoffset csp, csp, 16
+; RV32IFDXCHERI-IL32PC64-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IFDXCHERI-IL32PC64-NEXT:    cincoffset sp, sp, 16
 ; RV32IFDXCHERI-IL32PC64-NEXT:    cret
 ;
 ; RV32IFXCHERI-IL32PC64F-LABEL: calls_fixed_soft_stack:
 ; RV32IFXCHERI-IL32PC64F:       # %bb.0:
-; RV32IFXCHERI-IL32PC64F-NEXT:    cincoffset csp, csp, -16
-; RV32IFXCHERI-IL32PC64F-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; RV32IFXCHERI-IL32PC64F-NEXT:    clw a0, 16(csp)
-; RV32IFXCHERI-IL32PC64F-NEXT:    clw a1, 20(csp)
+; RV32IFXCHERI-IL32PC64F-NEXT:    cincoffset sp, sp, -16
+; RV32IFXCHERI-IL32PC64F-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; RV32IFXCHERI-IL32PC64F-NEXT:    clw a0, 16(sp)
+; RV32IFXCHERI-IL32PC64F-NEXT:    clw a1, 20(sp)
 ; RV32IFXCHERI-IL32PC64F-NEXT:    lui a3, 261888
 ; RV32IFXCHERI-IL32PC64F-NEXT:    li a2, 0
 ; RV32IFXCHERI-IL32PC64F-NEXT:    ccall __adddf3
-; RV32IFXCHERI-IL32PC64F-NEXT:    csw a1, 4(csp)
-; RV32IFXCHERI-IL32PC64F-NEXT:    csw a0, 0(csp)
+; RV32IFXCHERI-IL32PC64F-NEXT:    csw a1, 4(sp)
+; RV32IFXCHERI-IL32PC64F-NEXT:    csw a0, 0(sp)
 ; RV32IFXCHERI-IL32PC64F-NEXT:    li a0, 0
 ; RV32IFXCHERI-IL32PC64F-NEXT:    li a1, 0
 ; RV32IFXCHERI-IL32PC64F-NEXT:    li a2, 0
@@ -451,21 +451,21 @@ define void @calls_fixed_soft_stack(i32, i32, i32, i32, i32, i32, i32, i32, doub
 ; RV32IFXCHERI-IL32PC64F-NEXT:    li a6, 0
 ; RV32IFXCHERI-IL32PC64F-NEXT:    li a7, 0
 ; RV32IFXCHERI-IL32PC64F-NEXT:    ccall fixed_soft_stack
-; RV32IFXCHERI-IL32PC64F-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IFXCHERI-IL32PC64F-NEXT:    cincoffset csp, csp, 16
+; RV32IFXCHERI-IL32PC64F-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IFXCHERI-IL32PC64F-NEXT:    cincoffset sp, sp, 16
 ; RV32IFXCHERI-IL32PC64F-NEXT:    cret
 ;
 ; RV32IFDXCHERI-IL32PC64F-LABEL: calls_fixed_soft_stack:
 ; RV32IFDXCHERI-IL32PC64F:       # %bb.0:
-; RV32IFDXCHERI-IL32PC64F-NEXT:    cincoffset csp, csp, -16
-; RV32IFDXCHERI-IL32PC64F-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; RV32IFDXCHERI-IL32PC64F-NEXT:    cfld fa5, 16(csp)
+; RV32IFDXCHERI-IL32PC64F-NEXT:    cincoffset sp, sp, -16
+; RV32IFDXCHERI-IL32PC64F-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; RV32IFDXCHERI-IL32PC64F-NEXT:    cfld fa5, 16(sp)
 ; RV32IFDXCHERI-IL32PC64F-NEXT:  .LBB4_1: # Label of block must be emitted
-; RV32IFDXCHERI-IL32PC64F-NEXT:    auipcc ca0, %pcrel_hi(.LCPI4_0)
-; RV32IFDXCHERI-IL32PC64F-NEXT:    cincoffset ca0, ca0, %pcrel_lo(.LBB4_1)
-; RV32IFDXCHERI-IL32PC64F-NEXT:    cfld fa4, 0(ca0)
+; RV32IFDXCHERI-IL32PC64F-NEXT:    auipcc a0, %pcrel_hi(.LCPI4_0)
+; RV32IFDXCHERI-IL32PC64F-NEXT:    cincoffset a0, a0, %pcrel_lo(.LBB4_1)
+; RV32IFDXCHERI-IL32PC64F-NEXT:    cfld fa4, 0(a0)
 ; RV32IFDXCHERI-IL32PC64F-NEXT:    fadd.d fa5, fa5, fa4
-; RV32IFDXCHERI-IL32PC64F-NEXT:    cfsd fa5, 0(csp)
+; RV32IFDXCHERI-IL32PC64F-NEXT:    cfsd fa5, 0(sp)
 ; RV32IFDXCHERI-IL32PC64F-NEXT:    li a0, 0
 ; RV32IFDXCHERI-IL32PC64F-NEXT:    li a1, 0
 ; RV32IFDXCHERI-IL32PC64F-NEXT:    li a2, 0
@@ -475,16 +475,16 @@ define void @calls_fixed_soft_stack(i32, i32, i32, i32, i32, i32, i32, i32, doub
 ; RV32IFDXCHERI-IL32PC64F-NEXT:    li a6, 0
 ; RV32IFDXCHERI-IL32PC64F-NEXT:    li a7, 0
 ; RV32IFDXCHERI-IL32PC64F-NEXT:    ccall fixed_soft_stack
-; RV32IFDXCHERI-IL32PC64F-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IFDXCHERI-IL32PC64F-NEXT:    cincoffset csp, csp, 16
+; RV32IFDXCHERI-IL32PC64F-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IFDXCHERI-IL32PC64F-NEXT:    cincoffset sp, sp, 16
 ; RV32IFDXCHERI-IL32PC64F-NEXT:    cret
 ;
 ; RV32IFDXCHERI-IL32PC64D-LABEL: calls_fixed_soft_stack:
 ; RV32IFDXCHERI-IL32PC64D:       # %bb.0:
 ; RV32IFDXCHERI-IL32PC64D-NEXT:  .LBB4_1: # Label of block must be emitted
-; RV32IFDXCHERI-IL32PC64D-NEXT:    auipcc ca0, %pcrel_hi(.LCPI4_0)
-; RV32IFDXCHERI-IL32PC64D-NEXT:    cincoffset ca0, ca0, %pcrel_lo(.LBB4_1)
-; RV32IFDXCHERI-IL32PC64D-NEXT:    cfld fa5, 0(ca0)
+; RV32IFDXCHERI-IL32PC64D-NEXT:    auipcc a0, %pcrel_hi(.LCPI4_0)
+; RV32IFDXCHERI-IL32PC64D-NEXT:    cincoffset a0, a0, %pcrel_lo(.LBB4_1)
+; RV32IFDXCHERI-IL32PC64D-NEXT:    cfld fa5, 0(a0)
 ; RV32IFDXCHERI-IL32PC64D-NEXT:    fadd.d fa0, fa0, fa5
 ; RV32IFDXCHERI-IL32PC64D-NEXT:    li a0, 0
 ; RV32IFDXCHERI-IL32PC64D-NEXT:    li a1, 0
diff --git a/llvm/test/CodeGen/RISCV/cheri/select-null.ll b/llvm/test/CodeGen/RISCV/cheri/select-null.ll
index b8fa2d5399833..ce86fa6431be9 100644
--- a/llvm/test/CodeGen/RISCV/cheri/select-null.ll
+++ b/llvm/test/CodeGen/RISCV/cheri/select-null.ll
@@ -32,21 +32,21 @@ define i8 addrspace(200)* @eggs(i1 %cond) local_unnamed_addr addrspace(200) #0 {
 ;
 ; PURECAP-LABEL: eggs:
 ; PURECAP:       # %bb.0: # %bb
-; PURECAP-NEXT:    cincoffset csp, csp, -32
-; PURECAP-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; PURECAP-NEXT:    csc cs0, 0(csp) # 16-byte Folded Spill
+; PURECAP-NEXT:    cincoffset sp, sp, -32
+; PURECAP-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; PURECAP-NEXT:    csc s0, 0(sp) # 16-byte Folded Spill
 ; PURECAP-NEXT:    andi a0, a0, 1
-; PURECAP-NEXT:    cmove cs0, cnull
+; PURECAP-NEXT:    cmove s0, zero
 ; PURECAP-NEXT:    bnez a0, .LBB0_2
 ; PURECAP-NEXT:  # %bb.1: # %bb
-; PURECAP-NEXT:    cincoffset cs0, cnull, 32
+; PURECAP-NEXT:    cincoffset s0, zero, 32
 ; PURECAP-NEXT:  .LBB0_2: # %bb
-; PURECAP-NEXT:    cmove ca0, cnull
+; PURECAP-NEXT:    cmove a0, zero
 ; PURECAP-NEXT:    ccall barney
-; PURECAP-NEXT:    cmove ca0, cs0
-; PURECAP-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; PURECAP-NEXT:    clc cs0, 0(csp) # 16-byte Folded Reload
-; PURECAP-NEXT:    cincoffset csp, csp, 32
+; PURECAP-NEXT:    cmove a0, s0
+; PURECAP-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; PURECAP-NEXT:    clc s0, 0(sp) # 16-byte Folded Reload
+; PURECAP-NEXT:    cincoffset sp, sp, 32
 ; PURECAP-NEXT:    cret
 bb:
   %tmp1.0 = select i1 %cond, i8 addrspace(200)* null, i8 addrspace(200)* inttoptr (i64 32 to i8 addrspace(200)*)
diff --git a/llvm/test/CodeGen/RISCV/cheri/spill.ll b/llvm/test/CodeGen/RISCV/cheri/spill.ll
index 1cb7a68acfdcc..4653fe1d9b498 100644
--- a/llvm/test/CodeGen/RISCV/cheri/spill.ll
+++ b/llvm/test/CodeGen/RISCV/cheri/spill.ll
@@ -22,14 +22,14 @@ define void @test_spill_slot(i8 addrspace(200)** %ptr) nounwind {
 ; RV32IXCHERI-ILP32-NEXT:    sw s10, 32(sp) # 4-byte Folded Spill
 ; RV32IXCHERI-ILP32-NEXT:    sw s11, 28(sp) # 4-byte Folded Spill
 ; RV32IXCHERI-ILP32-NEXT:    sw a0, 12(sp) # 4-byte Folded Spill
-; RV32IXCHERI-ILP32-NEXT:    lc ca1, 0(a0)
-; RV32IXCHERI-ILP32-NEXT:    sc ca1, 16(sp) # 8-byte Folded Spill
+; RV32IXCHERI-ILP32-NEXT:    lc a1, 0(a0)
+; RV32IXCHERI-ILP32-NEXT:    sc a1, 16(sp) # 8-byte Folded Spill
 ; RV32IXCHERI-ILP32-NEXT:    #APP
 ; RV32IXCHERI-ILP32-NEXT:    nop
 ; RV32IXCHERI-ILP32-NEXT:    #NO_APP
-; RV32IXCHERI-ILP32-NEXT:    lc ca0, 16(sp) # 8-byte Folded Reload
+; RV32IXCHERI-ILP32-NEXT:    lc a0, 16(sp) # 8-byte Folded Reload
 ; RV32IXCHERI-ILP32-NEXT:    lw a1, 12(sp) # 4-byte Folded Reload
-; RV32IXCHERI-ILP32-NEXT:    sc ca0, 0(a1)
+; RV32IXCHERI-ILP32-NEXT:    sc a0, 0(a1)
 ; RV32IXCHERI-ILP32-NEXT:    lw ra, 76(sp) # 4-byte Folded Reload
 ; RV32IXCHERI-ILP32-NEXT:    lw s0, 72(sp) # 4-byte Folded Reload
 ; RV32IXCHERI-ILP32-NEXT:    lw s1, 68(sp) # 4-byte Folded Reload
@@ -63,14 +63,14 @@ define void @test_spill_slot(i8 addrspace(200)** %ptr) nounwind {
 ; RV64IXCHERI-LP64-NEXT:    sd s10, 48(sp) # 8-byte Folded Spill
 ; RV64IXCHERI-LP64-NEXT:    sd s11, 40(sp) # 8-byte Folded Spill
 ; RV64IXCHERI-LP64-NEXT:    sd a0, 8(sp) # 8-byte Folded Spill
-; RV64IXCHERI-LP64-NEXT:    lc ca1, 0(a0)
-; RV64IXCHERI-LP64-NEXT:    sc ca1, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-LP64-NEXT:    lc a1, 0(a0)
+; RV64IXCHERI-LP64-NEXT:    sc a1, 16(sp) # 16-byte Folded Spill
 ; RV64IXCHERI-LP64-NEXT:    #APP
 ; RV64IXCHERI-LP64-NEXT:    nop
 ; RV64IXCHERI-LP64-NEXT:    #NO_APP
-; RV64IXCHERI-LP64-NEXT:    lc ca0, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-LP64-NEXT:    lc a0, 16(sp) # 16-byte Folded Reload
 ; RV64IXCHERI-LP64-NEXT:    ld a1, 8(sp) # 8-byte Folded Reload
-; RV64IXCHERI-LP64-NEXT:    sc ca0, 0(a1)
+; RV64IXCHERI-LP64-NEXT:    sc a0, 0(a1)
 ; RV64IXCHERI-LP64-NEXT:    ld ra, 136(sp) # 8-byte Folded Reload
 ; RV64IXCHERI-LP64-NEXT:    ld s0, 128(sp) # 8-byte Folded Reload
 ; RV64IXCHERI-LP64-NEXT:    ld s1, 120(sp) # 8-byte Folded Reload
@@ -89,7 +89,7 @@ define void @test_spill_slot(i8 addrspace(200)** %ptr) nounwind {
   %a = load volatile i8 addrspace(200)*, i8 addrspace(200)** %ptr
   ; Clobber all non-reserved capability registers (ie all but cnull, csp, cgp
   ; and ctp). Note that cfp may be not be reserved so we must clobber it.
-  tail call void asm sideeffect "nop", "~{c1},~{c5},~{c6},~{c7},~{c8},~{c9},~{c10},~{c11},~{c12},~{c13},~{c14},~{c15},~{c16},~{c17},~{c18},~{c19},~{c20},~{c21},~{c22},~{c23},~{c24},~{c25},~{c26},~{c27},~{c28},~{c29},~{c30},~{c31}"()
+  tail call void asm sideeffect "nop", "~{x1},~{x5},~{x6},~{x7},~{x8},~{x9},~{x10},~{x11},~{x12},~{x13},~{x14},~{x15},~{x16},~{x17},~{x18},~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27},~{x28},~{x29},~{x30},~{x31}"()
   store volatile i8 addrspace(200)* %a, i8 addrspace(200)** %ptr
   ret void
 }
diff --git a/llvm/test/CodeGen/RISCV/cheri/stack-protector.ll b/llvm/test/CodeGen/RISCV/cheri/stack-protector.ll
index 361c96cd94933..ff1b54b0bd067 100644
--- a/llvm/test/CodeGen/RISCV/cheri/stack-protector.ll
+++ b/llvm/test/CodeGen/RISCV/cheri/stack-protector.ll
@@ -12,70 +12,70 @@ declare void @callee(i8 addrspace(200)*) addrspace(200)
 define void @caller() addrspace(200) nounwind sspstrong {
 ; IL32PC64-DEFAULT-LABEL: caller:
 ; IL32PC64-DEFAULT:       # %bb.0:
-; IL32PC64-DEFAULT-NEXT:    cincoffset csp, csp, -16
-; IL32PC64-DEFAULT-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; IL32PC64-DEFAULT-NEXT:    cincoffset ca0, csp, 7
-; IL32PC64-DEFAULT-NEXT:    csetbounds ca0, ca0, 1
+; IL32PC64-DEFAULT-NEXT:    cincoffset sp, sp, -16
+; IL32PC64-DEFAULT-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; IL32PC64-DEFAULT-NEXT:    cincoffset a0, sp, 7
+; IL32PC64-DEFAULT-NEXT:    csetbounds a0, a0, 1
 ; IL32PC64-DEFAULT-NEXT:    ccall callee
-; IL32PC64-DEFAULT-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; IL32PC64-DEFAULT-NEXT:    cincoffset csp, csp, 16
+; IL32PC64-DEFAULT-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; IL32PC64-DEFAULT-NEXT:    cincoffset sp, sp, 16
 ; IL32PC64-DEFAULT-NEXT:    cret
 ;
 ; L64PC128-DEFAULT-LABEL: caller:
 ; L64PC128-DEFAULT:       # %bb.0:
-; L64PC128-DEFAULT-NEXT:    cincoffset csp, csp, -32
-; L64PC128-DEFAULT-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; L64PC128-DEFAULT-NEXT:    cincoffset ca0, csp, 15
-; L64PC128-DEFAULT-NEXT:    csetbounds ca0, ca0, 1
+; L64PC128-DEFAULT-NEXT:    cincoffset sp, sp, -32
+; L64PC128-DEFAULT-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; L64PC128-DEFAULT-NEXT:    cincoffset a0, sp, 15
+; L64PC128-DEFAULT-NEXT:    csetbounds a0, a0, 1
 ; L64PC128-DEFAULT-NEXT:    ccall callee
-; L64PC128-DEFAULT-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; L64PC128-DEFAULT-NEXT:    cincoffset csp, csp, 32
+; L64PC128-DEFAULT-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; L64PC128-DEFAULT-NEXT:    cincoffset sp, sp, 32
 ; L64PC128-DEFAULT-NEXT:    cret
 ;
 ; IL32PC64-LABEL: caller:
 ; IL32PC64:       # %bb.0:
-; IL32PC64-NEXT:    cincoffset csp, csp, -32
-; IL32PC64-NEXT:    csc cra, 24(csp) # 8-byte Folded Spill
-; IL32PC64-NEXT:    csc cs0, 16(csp) # 8-byte Folded Spill
+; IL32PC64-NEXT:    cincoffset sp, sp, -32
+; IL32PC64-NEXT:    csc ra, 24(sp) # 8-byte Folded Spill
+; IL32PC64-NEXT:    csc s0, 16(sp) # 8-byte Folded Spill
 ; IL32PC64-NEXT:  .LBB0_3: # Label of block must be emitted
-; IL32PC64-NEXT:    auipcc cs0, %captab_pcrel_hi(__stack_chk_guard)
-; IL32PC64-NEXT:    clc cs0, %pcrel_lo(.LBB0_3)(cs0)
-; IL32PC64-NEXT:    clw a0, 0(cs0)
-; IL32PC64-NEXT:    csw a0, 12(csp)
-; IL32PC64-NEXT:    cincoffset ca0, csp, 11
-; IL32PC64-NEXT:    csetbounds ca0, ca0, 1
+; IL32PC64-NEXT:    auipcc s0, %captab_pcrel_hi(__stack_chk_guard)
+; IL32PC64-NEXT:    clc s0, %pcrel_lo(.LBB0_3)(s0)
+; IL32PC64-NEXT:    clw a0, 0(s0)
+; IL32PC64-NEXT:    csw a0, 12(sp)
+; IL32PC64-NEXT:    cincoffset a0, sp, 11
+; IL32PC64-NEXT:    csetbounds a0, a0, 1
 ; IL32PC64-NEXT:    ccall callee
-; IL32PC64-NEXT:    clc ca0, 12(csp)
-; IL32PC64-NEXT:    clc ca1, 0(cs0)
+; IL32PC64-NEXT:    clc a0, 12(sp)
+; IL32PC64-NEXT:    clc a1, 0(s0)
 ; IL32PC64-NEXT:    bne a1, a0, .LBB0_2
 ; IL32PC64-NEXT:  # %bb.1:
-; IL32PC64-NEXT:    clc cra, 24(csp) # 8-byte Folded Reload
-; IL32PC64-NEXT:    clc cs0, 16(csp) # 8-byte Folded Reload
-; IL32PC64-NEXT:    cincoffset csp, csp, 32
+; IL32PC64-NEXT:    clc ra, 24(sp) # 8-byte Folded Reload
+; IL32PC64-NEXT:    clc s0, 16(sp) # 8-byte Folded Reload
+; IL32PC64-NEXT:    cincoffset sp, sp, 32
 ; IL32PC64-NEXT:    cret
 ; IL32PC64-NEXT:  .LBB0_2:
 ; IL32PC64-NEXT:    ccall __stack_chk_fail
 ;
 ; L64PC128-LABEL: caller:
 ; L64PC128:       # %bb.0:
-; L64PC128-NEXT:    cincoffset csp, csp, -48
-; L64PC128-NEXT:    csc cra, 32(csp) # 16-byte Folded Spill
-; L64PC128-NEXT:    csc cs0, 16(csp) # 16-byte Folded Spill
+; L64PC128-NEXT:    cincoffset sp, sp, -48
+; L64PC128-NEXT:    csc ra, 32(sp) # 16-byte Folded Spill
+; L64PC128-NEXT:    csc s0, 16(sp) # 16-byte Folded Spill
 ; L64PC128-NEXT:  .LBB0_3: # Label of block must be emitted
-; L64PC128-NEXT:    auipcc cs0, %captab_pcrel_hi(__stack_chk_guard)
-; L64PC128-NEXT:    clc cs0, %pcrel_lo(.LBB0_3)(cs0)
-; L64PC128-NEXT:    cld a0, 0(cs0)
-; L64PC128-NEXT:    csd a0, 8(csp)
-; L64PC128-NEXT:    cincoffset ca0, csp, 7
-; L64PC128-NEXT:    csetbounds ca0, ca0, 1
+; L64PC128-NEXT:    auipcc s0, %captab_pcrel_hi(__stack_chk_guard)
+; L64PC128-NEXT:    clc s0, %pcrel_lo(.LBB0_3)(s0)
+; L64PC128-NEXT:    cld a0, 0(s0)
+; L64PC128-NEXT:    csd a0, 8(sp)
+; L64PC128-NEXT:    cincoffset a0, sp, 7
+; L64PC128-NEXT:    csetbounds a0, a0, 1
 ; L64PC128-NEXT:    ccall callee
-; L64PC128-NEXT:    clc ca0, 8(csp)
-; L64PC128-NEXT:    clc ca1, 0(cs0)
+; L64PC128-NEXT:    clc a0, 8(sp)
+; L64PC128-NEXT:    clc a1, 0(s0)
 ; L64PC128-NEXT:    bne a1, a0, .LBB0_2
 ; L64PC128-NEXT:  # %bb.1:
-; L64PC128-NEXT:    clc cra, 32(csp) # 16-byte Folded Reload
-; L64PC128-NEXT:    clc cs0, 16(csp) # 16-byte Folded Reload
-; L64PC128-NEXT:    cincoffset csp, csp, 48
+; L64PC128-NEXT:    clc ra, 32(sp) # 16-byte Folded Reload
+; L64PC128-NEXT:    clc s0, 16(sp) # 16-byte Folded Reload
+; L64PC128-NEXT:    cincoffset sp, sp, 48
 ; L64PC128-NEXT:    cret
 ; L64PC128-NEXT:  .LBB0_2:
 ; L64PC128-NEXT:    ccall __stack_chk_fail
diff --git a/llvm/test/CodeGen/RISCV/cheri/stack.ll b/llvm/test/CodeGen/RISCV/cheri/stack.ll
index 8d22db7e52163..7a61d5de6d9ed 100644
--- a/llvm/test/CodeGen/RISCV/cheri/stack.ll
+++ b/llvm/test/CodeGen/RISCV/cheri/stack.ll
@@ -9,24 +9,24 @@ declare i32 @use_arg(i32 addrspace(200)*) addrspace(200)
 define i32 @static_alloca() nounwind {
 ; RV32IXCHERI-LABEL: static_alloca:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    cincoffset ca0, csp, 4
-; RV32IXCHERI-NEXT:    csetbounds ca0, ca0, 4
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset a0, sp, 4
+; RV32IXCHERI-NEXT:    csetbounds a0, a0, 4
 ; RV32IXCHERI-NEXT:    ccall use_arg
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: static_alloca:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -32
-; RV64IXCHERI-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    cincoffset ca0, csp, 12
-; RV64IXCHERI-NEXT:    csetbounds ca0, ca0, 4
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -32
+; RV64IXCHERI-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset a0, sp, 12
+; RV64IXCHERI-NEXT:    csetbounds a0, a0, 4
 ; RV64IXCHERI-NEXT:    ccall use_arg
-; RV64IXCHERI-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 32
+; RV64IXCHERI-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 32
 ; RV64IXCHERI-NEXT:    cret
   %var = alloca i32, align 4, addrspace(200)
   %call = call i32 @use_arg(i32 addrspace(200)* nonnull %var)
@@ -38,10 +38,10 @@ define i32 @static_alloca() nounwind {
 define i32 @dynamic_alloca(iXLEN %x) nounwind {
 ; RV32IXCHERI-LABEL: dynamic_alloca:
 ; RV32IXCHERI:       # %bb.0:
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, -16
-; RV32IXCHERI-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    csc cs0, 0(csp) # 8-byte Folded Spill
-; RV32IXCHERI-NEXT:    cincoffset cs0, csp, 16
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, -16
+; RV32IXCHERI-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    csc s0, 0(sp) # 8-byte Folded Spill
+; RV32IXCHERI-NEXT:    cincoffset s0, sp, 16
 ; RV32IXCHERI-NEXT:    slli a0, a0, 2
 ; RV32IXCHERI-NEXT:    addi a1, a0, 15
 ; RV32IXCHERI-NEXT:    andi a1, a1, -16
@@ -49,23 +49,23 @@ define i32 @dynamic_alloca(iXLEN %x) nounwind {
 ; RV32IXCHERI-NEXT:    sub a3, sp, a2
 ; RV32IXCHERI-NEXT:    cram a1, a1
 ; RV32IXCHERI-NEXT:    and a1, a3, a1
-; RV32IXCHERI-NEXT:    csetaddr ca1, csp, a1
-; RV32IXCHERI-NEXT:    csetbounds ca2, ca1, a2
-; RV32IXCHERI-NEXT:    cmove csp, ca1
-; RV32IXCHERI-NEXT:    csetbounds ca0, ca2, a0
+; RV32IXCHERI-NEXT:    csetaddr a1, sp, a1
+; RV32IXCHERI-NEXT:    csetbounds a2, a1, a2
+; RV32IXCHERI-NEXT:    cmove sp, a1
+; RV32IXCHERI-NEXT:    csetbounds a0, a2, a0
 ; RV32IXCHERI-NEXT:    ccall use_arg
-; RV32IXCHERI-NEXT:    cincoffset csp, cs0, -16
-; RV32IXCHERI-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    clc cs0, 0(csp) # 8-byte Folded Reload
-; RV32IXCHERI-NEXT:    cincoffset csp, csp, 16
+; RV32IXCHERI-NEXT:    cincoffset sp, s0, -16
+; RV32IXCHERI-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    clc s0, 0(sp) # 8-byte Folded Reload
+; RV32IXCHERI-NEXT:    cincoffset sp, sp, 16
 ; RV32IXCHERI-NEXT:    cret
 ;
 ; RV64IXCHERI-LABEL: dynamic_alloca:
 ; RV64IXCHERI:       # %bb.0:
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, -32
-; RV64IXCHERI-NEXT:    csc cra, 16(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    csc cs0, 0(csp) # 16-byte Folded Spill
-; RV64IXCHERI-NEXT:    cincoffset cs0, csp, 32
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, -32
+; RV64IXCHERI-NEXT:    csc ra, 16(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    csc s0, 0(sp) # 16-byte Folded Spill
+; RV64IXCHERI-NEXT:    cincoffset s0, sp, 32
 ; RV64IXCHERI-NEXT:    slli a0, a0, 2
 ; RV64IXCHERI-NEXT:    addi a1, a0, 15
 ; RV64IXCHERI-NEXT:    andi a1, a1, -16
@@ -73,15 +73,15 @@ define i32 @dynamic_alloca(iXLEN %x) nounwind {
 ; RV64IXCHERI-NEXT:    sub a3, sp, a2
 ; RV64IXCHERI-NEXT:    cram a1, a1
 ; RV64IXCHERI-NEXT:    and a1, a3, a1
-; RV64IXCHERI-NEXT:    csetaddr ca1, csp, a1
-; RV64IXCHERI-NEXT:    csetbounds ca2, ca1, a2
-; RV64IXCHERI-NEXT:    cmove csp, ca1
-; RV64IXCHERI-NEXT:    csetbounds ca0, ca2, a0
+; RV64IXCHERI-NEXT:    csetaddr a1, sp, a1
+; RV64IXCHERI-NEXT:    csetbounds a2, a1, a2
+; RV64IXCHERI-NEXT:    cmove sp, a1
+; RV64IXCHERI-NEXT:    csetbounds a0, a2, a0
 ; RV64IXCHERI-NEXT:    ccall use_arg
-; RV64IXCHERI-NEXT:    cincoffset csp, cs0, -32
-; RV64IXCHERI-NEXT:    clc cra, 16(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    clc cs0, 0(csp) # 16-byte Folded Reload
-; RV64IXCHERI-NEXT:    cincoffset csp, csp, 32
+; RV64IXCHERI-NEXT:    cincoffset sp, s0, -32
+; RV64IXCHERI-NEXT:    clc ra, 16(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    clc s0, 0(sp) # 16-byte Folded Reload
+; RV64IXCHERI-NEXT:    cincoffset sp, sp, 32
 ; RV64IXCHERI-NEXT:    cret
   %var = alloca i32, iXLEN %x, align 4, addrspace(200)
   %call = call i32 @use_arg(i32 addrspace(200)* nonnull %var)
diff --git a/llvm/test/CodeGen/RISCV/cheri/tls-models.ll b/llvm/test/CodeGen/RISCV/cheri/tls-models.ll
index 5bcaf37eb7876..eff117b2a0b58 100644
--- a/llvm/test/CodeGen/RISCV/cheri/tls-models.ll
+++ b/llvm/test/CodeGen/RISCV/cheri/tls-models.ll
@@ -23,46 +23,46 @@
 define i32 addrspace(200)* @f1() nounwind {
 ; IL32PC64-PIC-LABEL: f1:
 ; IL32PC64-PIC:       # %bb.0: # %entry
-; IL32PC64-PIC-NEXT:    cincoffset csp, csp, -16
-; IL32PC64-PIC-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; IL32PC64-PIC-NEXT:    cincoffset sp, sp, -16
+; IL32PC64-PIC-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; IL32PC64-PIC-NEXT:  .LBB0_1: # %entry
 ; IL32PC64-PIC-NEXT:    # Label of block must be emitted
-; IL32PC64-PIC-NEXT:    auipcc ca0, %tls_gd_captab_pcrel_hi(unspecified)
-; IL32PC64-PIC-NEXT:    cincoffset ca0, ca0, %pcrel_lo(.LBB0_1)
+; IL32PC64-PIC-NEXT:    auipcc a0, %tls_gd_captab_pcrel_hi(unspecified)
+; IL32PC64-PIC-NEXT:    cincoffset a0, a0, %pcrel_lo(.LBB0_1)
 ; IL32PC64-PIC-NEXT:    ccall __tls_get_addr
-; IL32PC64-PIC-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; IL32PC64-PIC-NEXT:    cincoffset csp, csp, 16
+; IL32PC64-PIC-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; IL32PC64-PIC-NEXT:    cincoffset sp, sp, 16
 ; IL32PC64-PIC-NEXT:    cret
 ;
 ; L64PC128-PIC-LABEL: f1:
 ; L64PC128-PIC:       # %bb.0: # %entry
-; L64PC128-PIC-NEXT:    cincoffset csp, csp, -16
-; L64PC128-PIC-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; L64PC128-PIC-NEXT:    cincoffset sp, sp, -16
+; L64PC128-PIC-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; L64PC128-PIC-NEXT:  .LBB0_1: # %entry
 ; L64PC128-PIC-NEXT:    # Label of block must be emitted
-; L64PC128-PIC-NEXT:    auipcc ca0, %tls_gd_captab_pcrel_hi(unspecified)
-; L64PC128-PIC-NEXT:    cincoffset ca0, ca0, %pcrel_lo(.LBB0_1)
+; L64PC128-PIC-NEXT:    auipcc a0, %tls_gd_captab_pcrel_hi(unspecified)
+; L64PC128-PIC-NEXT:    cincoffset a0, a0, %pcrel_lo(.LBB0_1)
 ; L64PC128-PIC-NEXT:    ccall __tls_get_addr
-; L64PC128-PIC-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; L64PC128-PIC-NEXT:    cincoffset csp, csp, 16
+; L64PC128-PIC-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; L64PC128-PIC-NEXT:    cincoffset sp, sp, 16
 ; L64PC128-PIC-NEXT:    cret
 ;
 ; IL32PC64-NOPIC-LABEL: f1:
 ; IL32PC64-NOPIC:       # %bb.0: # %entry
 ; IL32PC64-NOPIC-NEXT:  .LBB0_1: # %entry
 ; IL32PC64-NOPIC-NEXT:    # Label of block must be emitted
-; IL32PC64-NOPIC-NEXT:    auipcc ca1, %tls_ie_captab_pcrel_hi(unspecified)
-; IL32PC64-NOPIC-NEXT:    clw a0, %pcrel_lo(.LBB0_1)(ca1)
-; IL32PC64-NOPIC-NEXT:    cincoffset ca0, ctp, a0
+; IL32PC64-NOPIC-NEXT:    auipcc a1, %tls_ie_captab_pcrel_hi(unspecified)
+; IL32PC64-NOPIC-NEXT:    clw a0, %pcrel_lo(.LBB0_1)(a1)
+; IL32PC64-NOPIC-NEXT:    cincoffset a0, tp, a0
 ; IL32PC64-NOPIC-NEXT:    cret
 ;
 ; L64PC128-NOPIC-LABEL: f1:
 ; L64PC128-NOPIC:       # %bb.0: # %entry
 ; L64PC128-NOPIC-NEXT:  .LBB0_1: # %entry
 ; L64PC128-NOPIC-NEXT:    # Label of block must be emitted
-; L64PC128-NOPIC-NEXT:    auipcc ca1, %tls_ie_captab_pcrel_hi(unspecified)
-; L64PC128-NOPIC-NEXT:    cld a0, %pcrel_lo(.LBB0_1)(ca1)
-; L64PC128-NOPIC-NEXT:    cincoffset ca0, ctp, a0
+; L64PC128-NOPIC-NEXT:    auipcc a1, %tls_ie_captab_pcrel_hi(unspecified)
+; L64PC128-NOPIC-NEXT:    cld a0, %pcrel_lo(.LBB0_1)(a1)
+; L64PC128-NOPIC-NEXT:    cincoffset a0, tp, a0
 ; L64PC128-NOPIC-NEXT:    cret
 entry:
   ret i32 addrspace(200)* @unspecified
@@ -74,46 +74,46 @@ entry:
 define i32 addrspace(200)* @f2() nounwind {
 ; IL32PC64-PIC-LABEL: f2:
 ; IL32PC64-PIC:       # %bb.0: # %entry
-; IL32PC64-PIC-NEXT:    cincoffset csp, csp, -16
-; IL32PC64-PIC-NEXT:    csc cra, 8(csp) # 8-byte Folded Spill
+; IL32PC64-PIC-NEXT:    cincoffset sp, sp, -16
+; IL32PC64-PIC-NEXT:    csc ra, 8(sp) # 8-byte Folded Spill
 ; IL32PC64-PIC-NEXT:  .LBB1_1: # %entry
 ; IL32PC64-PIC-NEXT:    # Label of block must be emitted
-; IL32PC64-PIC-NEXT:    auipcc ca0, %tls_gd_captab_pcrel_hi(ld)
-; IL32PC64-PIC-NEXT:    cincoffset ca0, ca0, %pcrel_lo(.LBB1_1)
+; IL32PC64-PIC-NEXT:    auipcc a0, %tls_gd_captab_pcrel_hi(ld)
+; IL32PC64-PIC-NEXT:    cincoffset a0, a0, %pcrel_lo(.LBB1_1)
 ; IL32PC64-PIC-NEXT:    ccall __tls_get_addr
-; IL32PC64-PIC-NEXT:    clc cra, 8(csp) # 8-byte Folded Reload
-; IL32PC64-PIC-NEXT:    cincoffset csp, csp, 16
+; IL32PC64-PIC-NEXT:    clc ra, 8(sp) # 8-byte Folded Reload
+; IL32PC64-PIC-NEXT:    cincoffset sp, sp, 16
 ; IL32PC64-PIC-NEXT:    cret
 ;
 ; L64PC128-PIC-LABEL: f2:
 ; L64PC128-PIC:       # %bb.0: # %entry
-; L64PC128-PIC-NEXT:    cincoffset csp, csp, -16
-; L64PC128-PIC-NEXT:    csc cra, 0(csp) # 16-byte Folded Spill
+; L64PC128-PIC-NEXT:    cincoffset sp, sp, -16
+; L64PC128-PIC-NEXT:    csc ra, 0(sp) # 16-byte Folded Spill
 ; L64PC128-PIC-NEXT:  .LBB1_1: # %entry
 ; L64PC128-PIC-NEXT:    # Label of block must be emitted
-; L64PC128-PIC-NEXT:    auipcc ca0, %tls_gd_captab_pcrel_hi(ld)
-; L64PC128-PIC-NEXT:    cincoffset ca0, ca0, %pcrel_lo(.LBB1_1)
+; L64PC128-PIC-NEXT:    auipcc a0, %tls_gd_captab_pcrel_hi(ld)
+; L64PC128-PIC-NEXT:    cincoffset a0, a0, %pcrel_lo(.LBB1_1)
 ; L64PC128-PIC-NEXT:    ccall __tls_get_addr
-; L64PC128-PIC-NEXT:    clc cra, 0(csp) # 16-byte Folded Reload
-; L64PC128-PIC-NEXT:    cincoffset csp, csp, 16
+; L64PC128-PIC-NEXT:    clc ra, 0(sp) # 16-byte Folded Reload
+; L64PC128-PIC-NEXT:    cincoffset sp, sp, 16
 ; L64PC128-PIC-NEXT:    cret
 ;
 ; IL32PC64-NOPIC-LABEL: f2:
 ; IL32PC64-NOPIC:       # %bb.0: # %entry
 ; IL32PC64-NOPIC-NEXT:  .LBB1_1: # %entry
 ; IL32PC64-NOPIC-NEXT:    # Label of block must be emitted
-; IL32PC64-NOPIC-NEXT:    auipcc ca1, %tls_ie_captab_pcrel_hi(ld)
-; IL32PC64-NOPIC-NEXT:    clw a0, %pcrel_lo(.LBB1_1)(ca1)
-; IL32PC64-NOPIC-NEXT:    cincoffset ca0, ctp, a0
+; IL32PC64-NOPIC-NEXT:    auipcc a1, %tls_ie_captab_pcrel_hi(ld)
+; IL32PC64-NOPIC-NEXT:    clw a0, %pcrel_lo(.LBB1_1)(a1)
+; IL32PC64-NOPIC-NEXT:    cincoffset a0, tp, a0
 ; IL32PC64-NOPIC-NEXT:    cret
 ;
 ; L64PC128-NOPIC-LABEL: f2:
 ; L64PC128-NOPIC:       # %bb.0: # %entry
 ; L64PC128-NOPIC-NEXT:  .LBB1_1: # %entry
 ; L64PC128-NOPIC-NEXT:    # Label of block must be emitted
-; L64PC128-NOPIC-NEXT:    auipcc ca1, %tls_ie_captab_pcrel_hi(ld)
-; L64PC128-NOPIC-NEXT:    cld a0, %pcrel_lo(.LBB1_1)(ca1)
-; L64PC128-NOPIC-NEXT:    cincoffset ca0, ctp, a0
+; L64PC128-NOPIC-NEXT:    auipcc a1, %tls_ie_captab_pcrel_hi(ld)
+; L64PC128-NOPIC-NEXT:    cld a0, %pcrel_lo(.LBB1_1)(a1)
+; L64PC128-NOPIC-NEXT:    cincoffset a0, tp, a0
 ; L64PC128-NOPIC-NEXT:    cret
 entry:
   ret i32 addrspace(200)* @ld
@@ -127,36 +127,36 @@ define i32 addrspace(200)* @f3() nounwind {
 ; IL32PC64-PIC:       # %bb.0: # %entry
 ; IL32PC64-PIC-NEXT:  .LBB2_1: # %entry
 ; IL32PC64-PIC-NEXT:    # Label of block must be emitted
-; IL32PC64-PIC-NEXT:    auipcc ca1, %tls_ie_captab_pcrel_hi(ie)
-; IL32PC64-PIC-NEXT:    clw a0, %pcrel_lo(.LBB2_1)(ca1)
-; IL32PC64-PIC-NEXT:    cincoffset ca0, ctp, a0
+; IL32PC64-PIC-NEXT:    auipcc a1, %tls_ie_captab_pcrel_hi(ie)
+; IL32PC64-PIC-NEXT:    clw a0, %pcrel_lo(.LBB2_1)(a1)
+; IL32PC64-PIC-NEXT:    cincoffset a0, tp, a0
 ; IL32PC64-PIC-NEXT:    cret
 ;
 ; L64PC128-PIC-LABEL: f3:
 ; L64PC128-PIC:       # %bb.0: # %entry
 ; L64PC128-PIC-NEXT:  .LBB2_1: # %entry
 ; L64PC128-PIC-NEXT:    # Label of block must be emitted
-; L64PC128-PIC-NEXT:    auipcc ca1, %tls_ie_captab_pcrel_hi(ie)
-; L64PC128-PIC-NEXT:    cld a0, %pcrel_lo(.LBB2_1)(ca1)
-; L64PC128-PIC-NEXT:    cincoffset ca0, ctp, a0
+; L64PC128-PIC-NEXT:    auipcc a1, %tls_ie_captab_pcrel_hi(ie)
+; L64PC128-PIC-NEXT:    cld a0, %pcrel_lo(.LBB2_1)(a1)
+; L64PC128-PIC-NEXT:    cincoffset a0, tp, a0
 ; L64PC128-PIC-NEXT:    cret
 ;
 ; IL32PC64-NOPIC-LABEL: f3:
 ; IL32PC64-NOPIC:       # %bb.0: # %entry
 ; IL32PC64-NOPIC-NEXT:  .LBB2_1: # %entry
 ; IL32PC64-NOPIC-NEXT:    # Label of block must be emitted
-; IL32PC64-NOPIC-NEXT:    auipcc ca1, %tls_ie_captab_pcrel_hi(ie)
-; IL32PC64-NOPIC-NEXT:    clw a0, %pcrel_lo(.LBB2_1)(ca1)
-; IL32PC64-NOPIC-NEXT:    cincoffset ca0, ctp, a0
+; IL32PC64-NOPIC-NEXT:    auipcc a1, %tls_ie_captab_pcrel_hi(ie)
+; IL32PC64-NOPIC-NEXT:    clw a0, %pcrel_lo(.LBB2_1)(a1)
+; IL32PC64-NOPIC-NEXT:    cincoffset a0, tp, a0
 ; IL32PC64-NOPIC-NEXT:    cret
 ;
 ; L64PC128-NOPIC-LABEL: f3:
 ; L64PC128-NOPIC:       # %bb.0: # %entry
 ; L64PC128-NOPIC-NEXT:  .LBB2_1: # %entry
 ; L64PC128-NOPIC-NEXT:    # Label of block must be emitted
-; L64PC128-NOPIC-NEXT:    auipcc ca1, %tls_ie_captab_pcrel_hi(ie)
-; L64PC128-NOPIC-NEXT:    cld a0, %pcrel_lo(.LBB2_1)(ca1)
-; L64PC128-NOPIC-NEXT:    cincoffset ca0, ctp, a0
+; L64PC128-NOPIC-NEXT:    auipcc a1, %tls_ie_captab_pcrel_hi(ie)
+; L64PC128-NOPIC-NEXT:    cld a0, %pcrel_lo(.LBB2_1)(a1)
+; L64PC128-NOPIC-NEXT:    cincoffset a0, tp, a0
 ; L64PC128-NOPIC-NEXT:    cret
 entry:
   ret i32 addrspace(200)* @ie
@@ -169,29 +169,29 @@ define i32 addrspace(200)* @f4() nounwind {
 ; IL32PC64-PIC-LABEL: f4:
 ; IL32PC64-PIC:       # %bb.0: # %entry
 ; IL32PC64-PIC-NEXT:    lui a0, %tprel_hi(le)
-; IL32PC64-PIC-NEXT:    cincoffset ca0, ctp, a0, %tprel_cincoffset(le)
-; IL32PC64-PIC-NEXT:    cincoffset ca0, ca0, %tprel_lo(le)
+; IL32PC64-PIC-NEXT:    cincoffset a0, tp, a0, %tprel_cincoffset(le)
+; IL32PC64-PIC-NEXT:    cincoffset a0, a0, %tprel_lo(le)
 ; IL32PC64-PIC-NEXT:    cret
 ;
 ; L64PC128-PIC-LABEL: f4:
 ; L64PC128-PIC:       # %bb.0: # %entry
 ; L64PC128-PIC-NEXT:    lui a0, %tprel_hi(le)
-; L64PC128-PIC-NEXT:    cincoffset ca0, ctp, a0, %tprel_cincoffset(le)
-; L64PC128-PIC-NEXT:    cincoffset ca0, ca0, %tprel_lo(le)
+; L64PC128-PIC-NEXT:    cincoffset a0, tp, a0, %tprel_cincoffset(le)
+; L64PC128-PIC-NEXT:    cincoffset a0, a0, %tprel_lo(le)
 ; L64PC128-PIC-NEXT:    cret
 ;
 ; IL32PC64-NOPIC-LABEL: f4:
 ; IL32PC64-NOPIC:       # %bb.0: # %entry
 ; IL32PC64-NOPIC-NEXT:    lui a0, %tprel_hi(le)
-; IL32PC64-NOPIC-NEXT:    cincoffset ca0, ctp, a0, %tprel_cincoffset(le)
-; IL32PC64-NOPIC-NEXT:    cincoffset ca0, ca0, %tprel_lo(le)
+; IL32PC64-NOPIC-NEXT:    cincoffset a0, tp, a0, %tprel_cincoffset(le)
+; IL32PC64-NOPIC-NEXT:    cincoffset a0, a0, %tprel_lo(le)
 ; IL32PC64-NOPIC-NEXT:    cret
 ;
 ; L64PC128-NOPIC-LABEL: f4:
 ; L64PC128-NOPIC:       # %bb.0: # %entry
 ; L64PC128-NOPIC-NEXT:    lui a0, %tprel_hi(le)
-; L64PC128-NOPIC-NEXT:    cincoffset ca0, ctp, a0, %tprel_cincoffset(le)
-; L64PC128-NOPIC-NEXT:    cincoffset ca0, ca0, %tprel_lo(le)
+; L64PC128-NOPIC-NEXT:    cincoffset a0, tp, a0, %tprel_cincoffset(le)
+; L64PC128-NOPIC-NEXT:    cincoffset a0, a0, %tprel_lo(le)
 ; L64PC128-NOPIC-NEXT:    cret
 entry:
   ret i32 addrspace(200)* @le
diff --git a/llvm/test/CodeGen/RISCV/cheri/unaligned-fp-load-store.ll b/llvm/test/CodeGen/RISCV/cheri/unaligned-fp-load-store.ll
index 25421b6248e36..dc89d0972498f 100644
--- a/llvm/test/CodeGen/RISCV/cheri/unaligned-fp-load-store.ll
+++ b/llvm/test/CodeGen/RISCV/cheri/unaligned-fp-load-store.ll
@@ -11,16 +11,16 @@ declare i32 @printf(i8 addrspace(200)*, ...) addrspace(200)
 define i32 @unaligned_float(float addrspace(200)* nocapture readonly %arg, float %newval) unnamed_addr addrspace(200) nounwind {
 ; RV32IFXCHERI-LABEL: unaligned_float:
 ; RV32IFXCHERI:       # %bb.0: # %bb
-; RV32IFXCHERI-NEXT:    cincoffset csp, csp, -32
-; RV32IFXCHERI-NEXT:    csc cra, 24(csp) # 8-byte Folded Spill
-; RV32IFXCHERI-NEXT:    csc cs0, 16(csp) # 8-byte Folded Spill
-; RV32IFXCHERI-NEXT:    cfsw fs0, 12(csp) # 4-byte Folded Spill
+; RV32IFXCHERI-NEXT:    cincoffset sp, sp, -32
+; RV32IFXCHERI-NEXT:    csc ra, 24(sp) # 8-byte Folded Spill
+; RV32IFXCHERI-NEXT:    csc s0, 16(sp) # 8-byte Folded Spill
+; RV32IFXCHERI-NEXT:    cfsw fs0, 12(sp) # 4-byte Folded Spill
 ; RV32IFXCHERI-NEXT:    fmv.s fs0, fa0
-; RV32IFXCHERI-NEXT:    cmove cs0, ca0
-; RV32IFXCHERI-NEXT:    clbu a0, 1(ca0)
-; RV32IFXCHERI-NEXT:    clbu a1, 0(cs0)
-; RV32IFXCHERI-NEXT:    clbu a2, 2(cs0)
-; RV32IFXCHERI-NEXT:    clbu a3, 3(cs0)
+; RV32IFXCHERI-NEXT:    cmove s0, a0
+; RV32IFXCHERI-NEXT:    clbu a0, 1(a0)
+; RV32IFXCHERI-NEXT:    clbu a1, 0(s0)
+; RV32IFXCHERI-NEXT:    clbu a2, 2(s0)
+; RV32IFXCHERI-NEXT:    clbu a3, 3(s0)
 ; RV32IFXCHERI-NEXT:    slli a0, a0, 8
 ; RV32IFXCHERI-NEXT:    or a0, a0, a1
 ; RV32IFXCHERI-NEXT:    slli a2, a2, 16
@@ -29,59 +29,59 @@ define i32 @unaligned_float(float addrspace(200)* nocapture readonly %arg, float
 ; RV32IFXCHERI-NEXT:    or a0, a2, a0
 ; RV32IFXCHERI-NEXT:    fmv.w.x fa0, a0
 ; RV32IFXCHERI-NEXT:    ccall __extendsfdf2
-; RV32IFXCHERI-NEXT:    csw a1, 4(csp)
-; RV32IFXCHERI-NEXT:    csw a0, 0(csp)
+; RV32IFXCHERI-NEXT:    csw a1, 4(sp)
+; RV32IFXCHERI-NEXT:    csw a0, 0(sp)
 ; RV32IFXCHERI-NEXT:    ccall printf
 ; RV32IFXCHERI-NEXT:    fmv.x.w a1, fs0
 ; RV32IFXCHERI-NEXT:    srli a2, a1, 24
-; RV32IFXCHERI-NEXT:    csb a2, 3(cs0)
+; RV32IFXCHERI-NEXT:    csb a2, 3(s0)
 ; RV32IFXCHERI-NEXT:    srli a2, a1, 16
-; RV32IFXCHERI-NEXT:    csb a2, 2(cs0)
+; RV32IFXCHERI-NEXT:    csb a2, 2(s0)
 ; RV32IFXCHERI-NEXT:    srli a2, a1, 8
-; RV32IFXCHERI-NEXT:    csb a2, 1(cs0)
-; RV32IFXCHERI-NEXT:    csb a1, 0(cs0)
-; RV32IFXCHERI-NEXT:    clc cra, 24(csp) # 8-byte Folded Reload
-; RV32IFXCHERI-NEXT:    clc cs0, 16(csp) # 8-byte Folded Reload
-; RV32IFXCHERI-NEXT:    cflw fs0, 12(csp) # 4-byte Folded Reload
-; RV32IFXCHERI-NEXT:    cincoffset csp, csp, 32
+; RV32IFXCHERI-NEXT:    csb a2, 1(s0)
+; RV32IFXCHERI-NEXT:    csb a1, 0(s0)
+; RV32IFXCHERI-NEXT:    clc ra, 24(sp) # 8-byte Folded Reload
+; RV32IFXCHERI-NEXT:    clc s0, 16(sp) # 8-byte Folded Reload
+; RV32IFXCHERI-NEXT:    cflw fs0, 12(sp) # 4-byte Folded Reload
+; RV32IFXCHERI-NEXT:    cincoffset sp, sp, 32
 ; RV32IFXCHERI-NEXT:    cret
 ;
 ; RV64IFXCHERI-LABEL: unaligned_float:
 ; RV64IFXCHERI:       # %bb.0: # %bb
-; RV64IFXCHERI-NEXT:    cincoffset csp, csp, -64
-; RV64IFXCHERI-NEXT:    csc cra, 48(csp) # 16-byte Folded Spill
-; RV64IFXCHERI-NEXT:    csc cs0, 32(csp) # 16-byte Folded Spill
-; RV64IFXCHERI-NEXT:    cfsw fs0, 28(csp) # 4-byte Folded Spill
+; RV64IFXCHERI-NEXT:    cincoffset sp, sp, -64
+; RV64IFXCHERI-NEXT:    csc ra, 48(sp) # 16-byte Folded Spill
+; RV64IFXCHERI-NEXT:    csc s0, 32(sp) # 16-byte Folded Spill
+; RV64IFXCHERI-NEXT:    cfsw fs0, 28(sp) # 4-byte Folded Spill
 ; RV64IFXCHERI-NEXT:    fmv.s fs0, fa0
-; RV64IFXCHERI-NEXT:    cmove cs0, ca0
-; RV64IFXCHERI-NEXT:    clbu a0, 1(ca0)
-; RV64IFXCHERI-NEXT:    clbu a1, 0(cs0)
-; RV64IFXCHERI-NEXT:    clbu a2, 2(cs0)
-; RV64IFXCHERI-NEXT:    clb a3, 3(cs0)
+; RV64IFXCHERI-NEXT:    cmove s0, a0
+; RV64IFXCHERI-NEXT:    clbu a0, 1(a0)
+; RV64IFXCHERI-NEXT:    clbu a1, 0(s0)
+; RV64IFXCHERI-NEXT:    clbu a2, 2(s0)
+; RV64IFXCHERI-NEXT:    clb a3, 3(s0)
 ; RV64IFXCHERI-NEXT:    slli a0, a0, 8
 ; RV64IFXCHERI-NEXT:    or a0, a0, a1
 ; RV64IFXCHERI-NEXT:    slli a2, a2, 16
 ; RV64IFXCHERI-NEXT:    slli a3, a3, 24
 ; RV64IFXCHERI-NEXT:    or a2, a3, a2
 ; RV64IFXCHERI-NEXT:    or a0, a2, a0
-; RV64IFXCHERI-NEXT:    csw a0, 8(csp)
-; RV64IFXCHERI-NEXT:    cflw fa0, 8(csp)
+; RV64IFXCHERI-NEXT:    csw a0, 8(sp)
+; RV64IFXCHERI-NEXT:    cflw fa0, 8(sp)
 ; RV64IFXCHERI-NEXT:    ccall __extendsfdf2
-; RV64IFXCHERI-NEXT:    csd a0, 0(csp)
+; RV64IFXCHERI-NEXT:    csd a0, 0(sp)
 ; RV64IFXCHERI-NEXT:    ccall printf
-; RV64IFXCHERI-NEXT:    cfsw fs0, 16(csp)
-; RV64IFXCHERI-NEXT:    clw a1, 16(csp)
-; RV64IFXCHERI-NEXT:    csb a1, 0(cs0)
+; RV64IFXCHERI-NEXT:    cfsw fs0, 16(sp)
+; RV64IFXCHERI-NEXT:    clw a1, 16(sp)
+; RV64IFXCHERI-NEXT:    csb a1, 0(s0)
 ; RV64IFXCHERI-NEXT:    srli a2, a1, 24
-; RV64IFXCHERI-NEXT:    csb a2, 3(cs0)
+; RV64IFXCHERI-NEXT:    csb a2, 3(s0)
 ; RV64IFXCHERI-NEXT:    srli a2, a1, 16
 ; RV64IFXCHERI-NEXT:    srli a1, a1, 8
-; RV64IFXCHERI-NEXT:    csb a2, 2(cs0)
-; RV64IFXCHERI-NEXT:    csb a1, 1(cs0)
-; RV64IFXCHERI-NEXT:    clc cra, 48(csp) # 16-byte Folded Reload
-; RV64IFXCHERI-NEXT:    clc cs0, 32(csp) # 16-byte Folded Reload
-; RV64IFXCHERI-NEXT:    cflw fs0, 28(csp) # 4-byte Folded Reload
-; RV64IFXCHERI-NEXT:    cincoffset csp, csp, 64
+; RV64IFXCHERI-NEXT:    csb a2, 2(s0)
+; RV64IFXCHERI-NEXT:    csb a1, 1(s0)
+; RV64IFXCHERI-NEXT:    clc ra, 48(sp) # 16-byte Folded Reload
+; RV64IFXCHERI-NEXT:    clc s0, 32(sp) # 16-byte Folded Reload
+; RV64IFXCHERI-NEXT:    cflw fs0, 28(sp) # 4-byte Folded Reload
+; RV64IFXCHERI-NEXT:    cincoffset sp, sp, 64
 ; RV64IFXCHERI-NEXT:    cret
 bb:
   %unaligned_load = load float, float addrspace(200)* %arg, align 1
@@ -94,69 +94,69 @@ bb:
 define i32 @unaligned_double(double addrspace(200)* nocapture readonly %arg, double %newval) unnamed_addr addrspace(200) nounwind {
 ; RV32IFXCHERI-LABEL: unaligned_double:
 ; RV32IFXCHERI:       # %bb.0: # %bb
-; RV32IFXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV32IFXCHERI-NEXT:    csc cra, 40(csp) # 8-byte Folded Spill
-; RV32IFXCHERI-NEXT:    csc cs0, 32(csp) # 8-byte Folded Spill
-; RV32IFXCHERI-NEXT:    csc cs1, 24(csp) # 8-byte Folded Spill
-; RV32IFXCHERI-NEXT:    csc cs2, 16(csp) # 8-byte Folded Spill
+; RV32IFXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV32IFXCHERI-NEXT:    csc ra, 40(sp) # 8-byte Folded Spill
+; RV32IFXCHERI-NEXT:    csc s0, 32(sp) # 8-byte Folded Spill
+; RV32IFXCHERI-NEXT:    csc s1, 24(sp) # 8-byte Folded Spill
+; RV32IFXCHERI-NEXT:    csc s2, 16(sp) # 8-byte Folded Spill
 ; RV32IFXCHERI-NEXT:    mv s0, a2
-; RV32IFXCHERI-NEXT:    mv s2, a1
-; RV32IFXCHERI-NEXT:    cmove cs1, ca0
-; RV32IFXCHERI-NEXT:    clhu a0, 2(ca0)
-; RV32IFXCHERI-NEXT:    clhu a1, 0(cs1)
-; RV32IFXCHERI-NEXT:    clhu a2, 6(cs1)
-; RV32IFXCHERI-NEXT:    clhu a3, 4(cs1)
+; RV32IFXCHERI-NEXT:    mv s1, a1
+; RV32IFXCHERI-NEXT:    cmove s2, a0
+; RV32IFXCHERI-NEXT:    clhu a0, 2(a0)
+; RV32IFXCHERI-NEXT:    clhu a1, 0(s2)
+; RV32IFXCHERI-NEXT:    clhu a2, 6(s2)
+; RV32IFXCHERI-NEXT:    clhu a3, 4(s2)
 ; RV32IFXCHERI-NEXT:    slli a0, a0, 16
 ; RV32IFXCHERI-NEXT:    or a0, a0, a1
 ; RV32IFXCHERI-NEXT:    slli a2, a2, 16
 ; RV32IFXCHERI-NEXT:    or a2, a2, a3
-; RV32IFXCHERI-NEXT:    csw a2, 4(csp)
-; RV32IFXCHERI-NEXT:    csw a0, 0(csp)
+; RV32IFXCHERI-NEXT:    csw a2, 4(sp)
+; RV32IFXCHERI-NEXT:    csw a0, 0(sp)
 ; RV32IFXCHERI-NEXT:    ccall printf
 ; RV32IFXCHERI-NEXT:    srli a1, s0, 16
-; RV32IFXCHERI-NEXT:    csh s0, 4(cs1)
-; RV32IFXCHERI-NEXT:    srli a2, s2, 16
-; RV32IFXCHERI-NEXT:    csh a1, 6(cs1)
-; RV32IFXCHERI-NEXT:    csh a2, 2(cs1)
-; RV32IFXCHERI-NEXT:    csh s2, 0(cs1)
-; RV32IFXCHERI-NEXT:    clc cra, 40(csp) # 8-byte Folded Reload
-; RV32IFXCHERI-NEXT:    clc cs0, 32(csp) # 8-byte Folded Reload
-; RV32IFXCHERI-NEXT:    clc cs1, 24(csp) # 8-byte Folded Reload
-; RV32IFXCHERI-NEXT:    clc cs2, 16(csp) # 8-byte Folded Reload
-; RV32IFXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV32IFXCHERI-NEXT:    csh s0, 4(s2)
+; RV32IFXCHERI-NEXT:    srli a2, s1, 16
+; RV32IFXCHERI-NEXT:    csh a1, 6(s2)
+; RV32IFXCHERI-NEXT:    csh a2, 2(s2)
+; RV32IFXCHERI-NEXT:    csh s1, 0(s2)
+; RV32IFXCHERI-NEXT:    clc ra, 40(sp) # 8-byte Folded Reload
+; RV32IFXCHERI-NEXT:    clc s0, 32(sp) # 8-byte Folded Reload
+; RV32IFXCHERI-NEXT:    clc s1, 24(sp) # 8-byte Folded Reload
+; RV32IFXCHERI-NEXT:    clc s2, 16(sp) # 8-byte Folded Reload
+; RV32IFXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV32IFXCHERI-NEXT:    cret
 ;
 ; RV64IFXCHERI-LABEL: unaligned_double:
 ; RV64IFXCHERI:       # %bb.0: # %bb
-; RV64IFXCHERI-NEXT:    cincoffset csp, csp, -64
-; RV64IFXCHERI-NEXT:    csc cra, 48(csp) # 16-byte Folded Spill
-; RV64IFXCHERI-NEXT:    csc cs0, 32(csp) # 16-byte Folded Spill
-; RV64IFXCHERI-NEXT:    csc cs1, 16(csp) # 16-byte Folded Spill
+; RV64IFXCHERI-NEXT:    cincoffset sp, sp, -64
+; RV64IFXCHERI-NEXT:    csc ra, 48(sp) # 16-byte Folded Spill
+; RV64IFXCHERI-NEXT:    csc s0, 32(sp) # 16-byte Folded Spill
+; RV64IFXCHERI-NEXT:    csc s1, 16(sp) # 16-byte Folded Spill
 ; RV64IFXCHERI-NEXT:    mv s0, a1
-; RV64IFXCHERI-NEXT:    cmove cs1, ca0
-; RV64IFXCHERI-NEXT:    clhu a0, 2(ca0)
-; RV64IFXCHERI-NEXT:    clhu a1, 0(cs1)
-; RV64IFXCHERI-NEXT:    clhu a2, 4(cs1)
-; RV64IFXCHERI-NEXT:    clhu a3, 6(cs1)
+; RV64IFXCHERI-NEXT:    cmove s1, a0
+; RV64IFXCHERI-NEXT:    clhu a0, 2(a0)
+; RV64IFXCHERI-NEXT:    clhu a1, 0(s1)
+; RV64IFXCHERI-NEXT:    clhu a2, 4(s1)
+; RV64IFXCHERI-NEXT:    clhu a3, 6(s1)
 ; RV64IFXCHERI-NEXT:    slli a0, a0, 16
 ; RV64IFXCHERI-NEXT:    or a0, a0, a1
 ; RV64IFXCHERI-NEXT:    slli a2, a2, 32
 ; RV64IFXCHERI-NEXT:    slli a3, a3, 48
 ; RV64IFXCHERI-NEXT:    or a2, a3, a2
 ; RV64IFXCHERI-NEXT:    or a0, a2, a0
-; RV64IFXCHERI-NEXT:    csd a0, 0(csp)
+; RV64IFXCHERI-NEXT:    csd a0, 0(sp)
 ; RV64IFXCHERI-NEXT:    ccall printf
 ; RV64IFXCHERI-NEXT:    srli a1, s0, 48
-; RV64IFXCHERI-NEXT:    csh a1, 6(cs1)
+; RV64IFXCHERI-NEXT:    csh a1, 6(s1)
 ; RV64IFXCHERI-NEXT:    srli a1, s0, 32
-; RV64IFXCHERI-NEXT:    csh a1, 4(cs1)
+; RV64IFXCHERI-NEXT:    csh a1, 4(s1)
 ; RV64IFXCHERI-NEXT:    srli a1, s0, 16
-; RV64IFXCHERI-NEXT:    csh a1, 2(cs1)
-; RV64IFXCHERI-NEXT:    csh s0, 0(cs1)
-; RV64IFXCHERI-NEXT:    clc cra, 48(csp) # 16-byte Folded Reload
-; RV64IFXCHERI-NEXT:    clc cs0, 32(csp) # 16-byte Folded Reload
-; RV64IFXCHERI-NEXT:    clc cs1, 16(csp) # 16-byte Folded Reload
-; RV64IFXCHERI-NEXT:    cincoffset csp, csp, 64
+; RV64IFXCHERI-NEXT:    csh a1, 2(s1)
+; RV64IFXCHERI-NEXT:    csh s0, 0(s1)
+; RV64IFXCHERI-NEXT:    clc ra, 48(sp) # 16-byte Folded Reload
+; RV64IFXCHERI-NEXT:    clc s0, 32(sp) # 16-byte Folded Reload
+; RV64IFXCHERI-NEXT:    clc s1, 16(sp) # 16-byte Folded Reload
+; RV64IFXCHERI-NEXT:    cincoffset sp, sp, 64
 ; RV64IFXCHERI-NEXT:    cret
 bb:
   %unaligned_load = load double, double addrspace(200)* %arg, align 2
@@ -168,76 +168,76 @@ bb:
 define i32 @unaligned_fp128(fp128 addrspace(200)* nocapture readonly %arg, fp128 %newval) unnamed_addr addrspace(200) nounwind {
 ; RV32IFXCHERI-LABEL: unaligned_fp128:
 ; RV32IFXCHERI:       # %bb.0: # %bb
-; RV32IFXCHERI-NEXT:    cincoffset csp, csp, -80
-; RV32IFXCHERI-NEXT:    csc cra, 72(csp) # 8-byte Folded Spill
-; RV32IFXCHERI-NEXT:    csc cs0, 64(csp) # 8-byte Folded Spill
-; RV32IFXCHERI-NEXT:    csc cs1, 56(csp) # 8-byte Folded Spill
-; RV32IFXCHERI-NEXT:    csc cs2, 48(csp) # 8-byte Folded Spill
-; RV32IFXCHERI-NEXT:    csc cs3, 40(csp) # 8-byte Folded Spill
-; RV32IFXCHERI-NEXT:    csc cs4, 32(csp) # 8-byte Folded Spill
-; RV32IFXCHERI-NEXT:    cmove cs0, ca0
-; RV32IFXCHERI-NEXT:    clw s1, 0(ca1)
-; RV32IFXCHERI-NEXT:    clw s2, 4(ca1)
-; RV32IFXCHERI-NEXT:    clw s3, 8(ca1)
-; RV32IFXCHERI-NEXT:    clw s4, 12(ca1)
-; RV32IFXCHERI-NEXT:    clw a1, 0(ca0)
-; RV32IFXCHERI-NEXT:    clw a0, 4(ca0)
-; RV32IFXCHERI-NEXT:    clw a2, 8(cs0)
-; RV32IFXCHERI-NEXT:    clw a3, 12(cs0)
-; RV32IFXCHERI-NEXT:    csw a3, 28(csp)
-; RV32IFXCHERI-NEXT:    csw a2, 24(csp)
-; RV32IFXCHERI-NEXT:    csw a0, 20(csp)
-; RV32IFXCHERI-NEXT:    cincoffset ca0, csp, 16
-; RV32IFXCHERI-NEXT:    csw a1, 16(csp)
+; RV32IFXCHERI-NEXT:    cincoffset sp, sp, -80
+; RV32IFXCHERI-NEXT:    csc ra, 72(sp) # 8-byte Folded Spill
+; RV32IFXCHERI-NEXT:    csc s0, 64(sp) # 8-byte Folded Spill
+; RV32IFXCHERI-NEXT:    csc s1, 56(sp) # 8-byte Folded Spill
+; RV32IFXCHERI-NEXT:    csc s2, 48(sp) # 8-byte Folded Spill
+; RV32IFXCHERI-NEXT:    csc s3, 40(sp) # 8-byte Folded Spill
+; RV32IFXCHERI-NEXT:    csc s4, 32(sp) # 8-byte Folded Spill
+; RV32IFXCHERI-NEXT:    cmove s0, a0
+; RV32IFXCHERI-NEXT:    clw s1, 0(a1)
+; RV32IFXCHERI-NEXT:    clw s2, 4(a1)
+; RV32IFXCHERI-NEXT:    clw s3, 8(a1)
+; RV32IFXCHERI-NEXT:    clw s4, 12(a1)
+; RV32IFXCHERI-NEXT:    clw a1, 0(a0)
+; RV32IFXCHERI-NEXT:    clw a0, 4(a0)
+; RV32IFXCHERI-NEXT:    clw a2, 8(s0)
+; RV32IFXCHERI-NEXT:    clw a3, 12(s0)
+; RV32IFXCHERI-NEXT:    csw a3, 28(sp)
+; RV32IFXCHERI-NEXT:    csw a2, 24(sp)
+; RV32IFXCHERI-NEXT:    csw a0, 20(sp)
+; RV32IFXCHERI-NEXT:    cincoffset a0, sp, 16
+; RV32IFXCHERI-NEXT:    csw a1, 16(sp)
 ; RV32IFXCHERI-NEXT:    ccall __trunctfdf2
-; RV32IFXCHERI-NEXT:    csw a1, 4(csp)
-; RV32IFXCHERI-NEXT:    csw a0, 0(csp)
+; RV32IFXCHERI-NEXT:    csw a1, 4(sp)
+; RV32IFXCHERI-NEXT:    csw a0, 0(sp)
 ; RV32IFXCHERI-NEXT:    ccall printf
-; RV32IFXCHERI-NEXT:    csw s4, 12(cs0)
-; RV32IFXCHERI-NEXT:    csw s3, 8(cs0)
-; RV32IFXCHERI-NEXT:    csw s2, 4(cs0)
-; RV32IFXCHERI-NEXT:    csw s1, 0(cs0)
-; RV32IFXCHERI-NEXT:    clc cra, 72(csp) # 8-byte Folded Reload
-; RV32IFXCHERI-NEXT:    clc cs0, 64(csp) # 8-byte Folded Reload
-; RV32IFXCHERI-NEXT:    clc cs1, 56(csp) # 8-byte Folded Reload
-; RV32IFXCHERI-NEXT:    clc cs2, 48(csp) # 8-byte Folded Reload
-; RV32IFXCHERI-NEXT:    clc cs3, 40(csp) # 8-byte Folded Reload
-; RV32IFXCHERI-NEXT:    clc cs4, 32(csp) # 8-byte Folded Reload
-; RV32IFXCHERI-NEXT:    cincoffset csp, csp, 80
+; RV32IFXCHERI-NEXT:    csw s4, 12(s0)
+; RV32IFXCHERI-NEXT:    csw s3, 8(s0)
+; RV32IFXCHERI-NEXT:    csw s2, 4(s0)
+; RV32IFXCHERI-NEXT:    csw s1, 0(s0)
+; RV32IFXCHERI-NEXT:    clc ra, 72(sp) # 8-byte Folded Reload
+; RV32IFXCHERI-NEXT:    clc s0, 64(sp) # 8-byte Folded Reload
+; RV32IFXCHERI-NEXT:    clc s1, 56(sp) # 8-byte Folded Reload
+; RV32IFXCHERI-NEXT:    clc s2, 48(sp) # 8-byte Folded Reload
+; RV32IFXCHERI-NEXT:    clc s3, 40(sp) # 8-byte Folded Reload
+; RV32IFXCHERI-NEXT:    clc s4, 32(sp) # 8-byte Folded Reload
+; RV32IFXCHERI-NEXT:    cincoffset sp, sp, 80
 ; RV32IFXCHERI-NEXT:    cret
 ;
 ; RV64IFXCHERI-LABEL: unaligned_fp128:
 ; RV64IFXCHERI:       # %bb.0: # %bb
-; RV64IFXCHERI-NEXT:    cincoffset csp, csp, -80
-; RV64IFXCHERI-NEXT:    csc cra, 64(csp) # 16-byte Folded Spill
-; RV64IFXCHERI-NEXT:    csc cs0, 48(csp) # 16-byte Folded Spill
-; RV64IFXCHERI-NEXT:    csc cs1, 32(csp) # 16-byte Folded Spill
-; RV64IFXCHERI-NEXT:    csc cs2, 16(csp) # 16-byte Folded Spill
+; RV64IFXCHERI-NEXT:    cincoffset sp, sp, -80
+; RV64IFXCHERI-NEXT:    csc ra, 64(sp) # 16-byte Folded Spill
+; RV64IFXCHERI-NEXT:    csc s0, 48(sp) # 16-byte Folded Spill
+; RV64IFXCHERI-NEXT:    csc s1, 32(sp) # 16-byte Folded Spill
+; RV64IFXCHERI-NEXT:    csc s2, 16(sp) # 16-byte Folded Spill
 ; RV64IFXCHERI-NEXT:    mv s0, a2
-; RV64IFXCHERI-NEXT:    mv s2, a1
-; RV64IFXCHERI-NEXT:    cmove cs1, ca0
-; RV64IFXCHERI-NEXT:    clwu a0, 4(ca0)
-; RV64IFXCHERI-NEXT:    clwu a1, 0(cs1)
-; RV64IFXCHERI-NEXT:    clwu a2, 12(cs1)
-; RV64IFXCHERI-NEXT:    clwu a3, 8(cs1)
+; RV64IFXCHERI-NEXT:    mv s1, a1
+; RV64IFXCHERI-NEXT:    cmove s2, a0
+; RV64IFXCHERI-NEXT:    clwu a0, 4(a0)
+; RV64IFXCHERI-NEXT:    clwu a1, 0(s2)
+; RV64IFXCHERI-NEXT:    clwu a2, 12(s2)
+; RV64IFXCHERI-NEXT:    clwu a3, 8(s2)
 ; RV64IFXCHERI-NEXT:    slli a0, a0, 32
 ; RV64IFXCHERI-NEXT:    or a0, a0, a1
 ; RV64IFXCHERI-NEXT:    slli a1, a2, 32
 ; RV64IFXCHERI-NEXT:    or a1, a1, a3
 ; RV64IFXCHERI-NEXT:    ccall __trunctfdf2
-; RV64IFXCHERI-NEXT:    csd a0, 0(csp)
+; RV64IFXCHERI-NEXT:    csd a0, 0(sp)
 ; RV64IFXCHERI-NEXT:    ccall printf
 ; RV64IFXCHERI-NEXT:    srli a1, s0, 32
-; RV64IFXCHERI-NEXT:    csw s0, 8(cs1)
-; RV64IFXCHERI-NEXT:    srli a2, s2, 32
-; RV64IFXCHERI-NEXT:    csw a1, 12(cs1)
-; RV64IFXCHERI-NEXT:    csw a2, 4(cs1)
-; RV64IFXCHERI-NEXT:    csw s2, 0(cs1)
-; RV64IFXCHERI-NEXT:    clc cra, 64(csp) # 16-byte Folded Reload
-; RV64IFXCHERI-NEXT:    clc cs0, 48(csp) # 16-byte Folded Reload
-; RV64IFXCHERI-NEXT:    clc cs1, 32(csp) # 16-byte Folded Reload
-; RV64IFXCHERI-NEXT:    clc cs2, 16(csp) # 16-byte Folded Reload
-; RV64IFXCHERI-NEXT:    cincoffset csp, csp, 80
+; RV64IFXCHERI-NEXT:    csw s0, 8(s2)
+; RV64IFXCHERI-NEXT:    srli a2, s1, 32
+; RV64IFXCHERI-NEXT:    csw a1, 12(s2)
+; RV64IFXCHERI-NEXT:    csw a2, 4(s2)
+; RV64IFXCHERI-NEXT:    csw s1, 0(s2)
+; RV64IFXCHERI-NEXT:    clc ra, 64(sp) # 16-byte Folded Reload
+; RV64IFXCHERI-NEXT:    clc s0, 48(sp) # 16-byte Folded Reload
+; RV64IFXCHERI-NEXT:    clc s1, 32(sp) # 16-byte Folded Reload
+; RV64IFXCHERI-NEXT:    clc s2, 16(sp) # 16-byte Folded Reload
+; RV64IFXCHERI-NEXT:    cincoffset sp, sp, 80
 ; RV64IFXCHERI-NEXT:    cret
 bb:
   %unaligned_load = load fp128, fp128 addrspace(200)* %arg, align 4
@@ -250,58 +250,58 @@ bb:
 define i32 @unaligned_int(i32 addrspace(200)* nocapture readonly %arg) unnamed_addr addrspace(200) nounwind {
 ; RV32IFXCHERI-LABEL: unaligned_int:
 ; RV32IFXCHERI:       # %bb.0: # %bb
-; RV32IFXCHERI-NEXT:    cincoffset csp, csp, -32
-; RV32IFXCHERI-NEXT:    csc cra, 24(csp) # 8-byte Folded Spill
-; RV32IFXCHERI-NEXT:    csc cs0, 16(csp) # 8-byte Folded Spill
-; RV32IFXCHERI-NEXT:    cmove cs0, ca0
-; RV32IFXCHERI-NEXT:    clbu a0, 1(ca0)
-; RV32IFXCHERI-NEXT:    clbu a1, 0(cs0)
-; RV32IFXCHERI-NEXT:    clbu a2, 2(cs0)
-; RV32IFXCHERI-NEXT:    clbu a3, 3(cs0)
+; RV32IFXCHERI-NEXT:    cincoffset sp, sp, -32
+; RV32IFXCHERI-NEXT:    csc ra, 24(sp) # 8-byte Folded Spill
+; RV32IFXCHERI-NEXT:    csc s0, 16(sp) # 8-byte Folded Spill
+; RV32IFXCHERI-NEXT:    cmove s0, a0
+; RV32IFXCHERI-NEXT:    clbu a0, 1(a0)
+; RV32IFXCHERI-NEXT:    clbu a1, 0(s0)
+; RV32IFXCHERI-NEXT:    clbu a2, 2(s0)
+; RV32IFXCHERI-NEXT:    clbu a3, 3(s0)
 ; RV32IFXCHERI-NEXT:    slli a0, a0, 8
 ; RV32IFXCHERI-NEXT:    or a0, a0, a1
 ; RV32IFXCHERI-NEXT:    slli a2, a2, 16
 ; RV32IFXCHERI-NEXT:    slli a3, a3, 24
 ; RV32IFXCHERI-NEXT:    or a2, a3, a2
 ; RV32IFXCHERI-NEXT:    or a0, a2, a0
-; RV32IFXCHERI-NEXT:    csw a0, 0(csp)
+; RV32IFXCHERI-NEXT:    csw a0, 0(sp)
 ; RV32IFXCHERI-NEXT:    ccall printf
-; RV32IFXCHERI-NEXT:    csb zero, 3(cs0)
-; RV32IFXCHERI-NEXT:    csb zero, 2(cs0)
-; RV32IFXCHERI-NEXT:    csb zero, 1(cs0)
+; RV32IFXCHERI-NEXT:    csb zero, 3(s0)
+; RV32IFXCHERI-NEXT:    csb zero, 2(s0)
+; RV32IFXCHERI-NEXT:    csb zero, 1(s0)
 ; RV32IFXCHERI-NEXT:    li a1, 1
-; RV32IFXCHERI-NEXT:    csb a1, 0(cs0)
-; RV32IFXCHERI-NEXT:    clc cra, 24(csp) # 8-byte Folded Reload
-; RV32IFXCHERI-NEXT:    clc cs0, 16(csp) # 8-byte Folded Reload
-; RV32IFXCHERI-NEXT:    cincoffset csp, csp, 32
+; RV32IFXCHERI-NEXT:    csb a1, 0(s0)
+; RV32IFXCHERI-NEXT:    clc ra, 24(sp) # 8-byte Folded Reload
+; RV32IFXCHERI-NEXT:    clc s0, 16(sp) # 8-byte Folded Reload
+; RV32IFXCHERI-NEXT:    cincoffset sp, sp, 32
 ; RV32IFXCHERI-NEXT:    cret
 ;
 ; RV64IFXCHERI-LABEL: unaligned_int:
 ; RV64IFXCHERI:       # %bb.0: # %bb
-; RV64IFXCHERI-NEXT:    cincoffset csp, csp, -48
-; RV64IFXCHERI-NEXT:    csc cra, 32(csp) # 16-byte Folded Spill
-; RV64IFXCHERI-NEXT:    csc cs0, 16(csp) # 16-byte Folded Spill
-; RV64IFXCHERI-NEXT:    cmove cs0, ca0
-; RV64IFXCHERI-NEXT:    clbu a0, 1(ca0)
-; RV64IFXCHERI-NEXT:    clbu a1, 0(cs0)
-; RV64IFXCHERI-NEXT:    clbu a2, 2(cs0)
-; RV64IFXCHERI-NEXT:    clb a3, 3(cs0)
+; RV64IFXCHERI-NEXT:    cincoffset sp, sp, -48
+; RV64IFXCHERI-NEXT:    csc ra, 32(sp) # 16-byte Folded Spill
+; RV64IFXCHERI-NEXT:    csc s0, 16(sp) # 16-byte Folded Spill
+; RV64IFXCHERI-NEXT:    cmove s0, a0
+; RV64IFXCHERI-NEXT:    clbu a0, 1(a0)
+; RV64IFXCHERI-NEXT:    clbu a1, 0(s0)
+; RV64IFXCHERI-NEXT:    clbu a2, 2(s0)
+; RV64IFXCHERI-NEXT:    clb a3, 3(s0)
 ; RV64IFXCHERI-NEXT:    slli a0, a0, 8
 ; RV64IFXCHERI-NEXT:    or a0, a0, a1
 ; RV64IFXCHERI-NEXT:    slli a2, a2, 16
 ; RV64IFXCHERI-NEXT:    slli a3, a3, 24
 ; RV64IFXCHERI-NEXT:    or a2, a3, a2
 ; RV64IFXCHERI-NEXT:    or a0, a2, a0
-; RV64IFXCHERI-NEXT:    csd a0, 0(csp)
+; RV64IFXCHERI-NEXT:    csd a0, 0(sp)
 ; RV64IFXCHERI-NEXT:    ccall printf
-; RV64IFXCHERI-NEXT:    csb zero, 3(cs0)
-; RV64IFXCHERI-NEXT:    csb zero, 2(cs0)
-; RV64IFXCHERI-NEXT:    csb zero, 1(cs0)
+; RV64IFXCHERI-NEXT:    csb zero, 3(s0)
+; RV64IFXCHERI-NEXT:    csb zero, 2(s0)
+; RV64IFXCHERI-NEXT:    csb zero, 1(s0)
 ; RV64IFXCHERI-NEXT:    li a1, 1
-; RV64IFXCHERI-NEXT:    csb a1, 0(cs0)
-; RV64IFXCHERI-NEXT:    clc cra, 32(csp) # 16-byte Folded Reload
-; RV64IFXCHERI-NEXT:    clc cs0, 16(csp) # 16-byte Folded Reload
-; RV64IFXCHERI-NEXT:    cincoffset csp, csp, 48
+; RV64IFXCHERI-NEXT:    csb a1, 0(s0)
+; RV64IFXCHERI-NEXT:    clc ra, 32(sp) # 16-byte Folded Reload
+; RV64IFXCHERI-NEXT:    clc s0, 16(sp) # 16-byte Folded Reload
+; RV64IFXCHERI-NEXT:    cincoffset sp, sp, 48
 ; RV64IFXCHERI-NEXT:    cret
 bb:
   %unaligned_load = load i32, i32 addrspace(200)* %arg, align 1
diff --git a/llvm/test/CodeGen/RISCV/cheri/vector-store.ll b/llvm/test/CodeGen/RISCV/cheri/vector-store.ll
index 6ad94e7f79921..420961d5a08a1 100644
--- a/llvm/test/CodeGen/RISCV/cheri/vector-store.ll
+++ b/llvm/test/CodeGen/RISCV/cheri/vector-store.ll
@@ -14,10 +14,10 @@ define <4 x i32> @vec_load(ptr addrspace(200) %src) addrspace(200) nounwind {
 ;
 ; PURECAP-LABEL: vec_load:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    cld a2, 8(ca1)
-; PURECAP-NEXT:    cld a1, 0(ca1)
-; PURECAP-NEXT:    csd a2, 8(ca0)
-; PURECAP-NEXT:    csd a1, 0(ca0)
+; PURECAP-NEXT:    cld a2, 8(a1)
+; PURECAP-NEXT:    cld a1, 0(a1)
+; PURECAP-NEXT:    csd a2, 8(a0)
+; PURECAP-NEXT:    csd a1, 0(a0)
 ; PURECAP-NEXT:    cret
   %ret = load <4 x i32>, ptr addrspace(200) %src, align 16
   ret <4 x i32> %ret
@@ -34,9 +34,9 @@ define void @vec_store(i32 %0, ptr addrspace(200) %dst) addrspace(200) nounwind
 ;
 ; PURECAP-LABEL: vec_store:
 ; PURECAP:       # %bb.0:
-; PURECAP-NEXT:    csw a0, 4(ca1)
-; PURECAP-NEXT:    csw zero, 0(ca1)
-; PURECAP-NEXT:    csd zero, 8(ca1)
+; PURECAP-NEXT:    csw a0, 4(a1)
+; PURECAP-NEXT:    csw zero, 0(a1)
+; PURECAP-NEXT:    csd zero, 8(a1)
 ; PURECAP-NEXT:    cret
   %vecins = insertelement <4 x i32> zeroinitializer, i32 %0, i32 1
   store <4 x i32> %vecins, ptr addrspace(200) %dst, align 16
diff --git a/llvm/test/CodeGen/RISCV/stack-folding.ll b/llvm/test/CodeGen/RISCV/stack-folding.ll
index b0859449d8589..92578016b7f9a 100644
--- a/llvm/test/CodeGen/RISCV/stack-folding.ll
+++ b/llvm/test/CodeGen/RISCV/stack-folding.ll
@@ -54,51 +54,51 @@ define i1 @test_sext_w(i64 %x, i32 %y) nounwind {
 ;
 ; RV64ZB-PURECAP-LABEL: test_sext_w:
 ; RV64ZB-PURECAP:       # %bb.0:
-; RV64ZB-PURECAP-NEXT:    cincoffset csp, csp, -256
-; RV64ZB-PURECAP-NEXT:    csc cra, 240(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cgp, 224(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc ctp, 208(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cs0, 192(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cs1, 176(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cs2, 160(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cs3, 144(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cs4, 128(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cs5, 112(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cs6, 96(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cs7, 80(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cs8, 64(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cs9, 48(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cs10, 32(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cs11, 16(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csd a1, 0(csp) # 8-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csd a0, 8(csp) # 8-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    cincoffset sp, sp, -256
+; RV64ZB-PURECAP-NEXT:    csc ra, 240(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc gp, 224(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc tp, 208(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc s0, 192(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc s1, 176(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc s2, 160(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc s3, 144(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc s4, 128(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc s5, 112(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc s6, 96(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc s7, 80(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc s8, 64(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc s9, 48(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc s10, 32(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc s11, 16(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csd a1, 0(sp) # 8-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csd a0, 8(sp) # 8-byte Folded Spill
 ; RV64ZB-PURECAP-NEXT:    #APP
 ; RV64ZB-PURECAP-NEXT:    #NO_APP
-; RV64ZB-PURECAP-NEXT:    cld a0, 8(csp) # 8-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    cld a0, 8(sp) # 8-byte Folded Reload
 ; RV64ZB-PURECAP-NEXT:    beqz a0, .LBB0_2
 ; RV64ZB-PURECAP-NEXT:  # %bb.1: # %falsebb
 ; RV64ZB-PURECAP-NEXT:    li a0, 0
 ; RV64ZB-PURECAP-NEXT:    j .LBB0_3
 ; RV64ZB-PURECAP-NEXT:  .LBB0_2: # %truebb
-; RV64ZB-PURECAP-NEXT:    clw a0, 0(csp) # 8-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clw a0, 0(sp) # 8-byte Folded Reload
 ; RV64ZB-PURECAP-NEXT:    slti a0, a0, 0
 ; RV64ZB-PURECAP-NEXT:  .LBB0_3: # %falsebb
-; RV64ZB-PURECAP-NEXT:    clc cra, 240(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cgp, 224(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc ctp, 208(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cs0, 192(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cs1, 176(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cs2, 160(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cs3, 144(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cs4, 128(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cs5, 112(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cs6, 96(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cs7, 80(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cs8, 64(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cs9, 48(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cs10, 32(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cs11, 16(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    cincoffset csp, csp, 256
+; RV64ZB-PURECAP-NEXT:    clc ra, 240(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc gp, 224(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc tp, 208(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc s0, 192(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc s1, 176(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc s2, 160(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc s3, 144(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc s4, 128(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc s5, 112(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc s6, 96(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc s7, 80(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc s8, 64(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc s9, 48(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc s10, 32(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc s11, 16(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    cincoffset sp, sp, 256
 ; RV64ZB-PURECAP-NEXT:    cret
   tail call void asm sideeffect "", "~{x1},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x9},~{x10},~{x11},~{x12},~{x13},~{x14},~{x15},~{x16},~{x17},~{x18},~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27},~{x28},~{x29},~{x30},~{x31}"()
   %a = icmp eq i64 %x, 0
@@ -204,50 +204,50 @@ define i64 @test_sext_b(i64 %x, i8 %y) nounwind {
 ;
 ; RV64ZB-PURECAP-LABEL: test_sext_b:
 ; RV64ZB-PURECAP:       # %bb.0:
-; RV64ZB-PURECAP-NEXT:    cincoffset csp, csp, -256
-; RV64ZB-PURECAP-NEXT:    csc cra, 240(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cgp, 224(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc ctp, 208(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cs0, 192(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cs1, 176(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cs2, 160(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cs3, 144(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cs4, 128(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cs5, 112(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cs6, 96(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cs7, 80(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cs8, 64(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cs9, 48(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cs10, 32(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cs11, 16(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csd a1, 0(csp) # 8-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csd a0, 8(csp) # 8-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    cincoffset sp, sp, -256
+; RV64ZB-PURECAP-NEXT:    csc ra, 240(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc gp, 224(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc tp, 208(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc s0, 192(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc s1, 176(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc s2, 160(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc s3, 144(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc s4, 128(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc s5, 112(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc s6, 96(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc s7, 80(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc s8, 64(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc s9, 48(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc s10, 32(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc s11, 16(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csd a1, 0(sp) # 8-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csd a0, 8(sp) # 8-byte Folded Spill
 ; RV64ZB-PURECAP-NEXT:    #APP
 ; RV64ZB-PURECAP-NEXT:    #NO_APP
-; RV64ZB-PURECAP-NEXT:    cld a0, 8(csp) # 8-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    cld a0, 8(sp) # 8-byte Folded Reload
 ; RV64ZB-PURECAP-NEXT:    beqz a0, .LBB1_2
 ; RV64ZB-PURECAP-NEXT:  # %bb.1: # %falsebb
 ; RV64ZB-PURECAP-NEXT:    li a0, 0
 ; RV64ZB-PURECAP-NEXT:    j .LBB1_3
 ; RV64ZB-PURECAP-NEXT:  .LBB1_2: # %truebb
-; RV64ZB-PURECAP-NEXT:    clb a0, 0(csp) # 8-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clb a0, 0(sp) # 8-byte Folded Reload
 ; RV64ZB-PURECAP-NEXT:  .LBB1_3: # %falsebb
-; RV64ZB-PURECAP-NEXT:    clc cra, 240(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cgp, 224(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc ctp, 208(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cs0, 192(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cs1, 176(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cs2, 160(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cs3, 144(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cs4, 128(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cs5, 112(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cs6, 96(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cs7, 80(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cs8, 64(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cs9, 48(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cs10, 32(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cs11, 16(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    cincoffset csp, csp, 256
+; RV64ZB-PURECAP-NEXT:    clc ra, 240(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc gp, 224(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc tp, 208(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc s0, 192(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc s1, 176(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc s2, 160(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc s3, 144(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc s4, 128(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc s5, 112(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc s6, 96(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc s7, 80(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc s8, 64(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc s9, 48(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc s10, 32(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc s11, 16(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    cincoffset sp, sp, 256
 ; RV64ZB-PURECAP-NEXT:    cret
   tail call void asm sideeffect "", "~{x1},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x9},~{x10},~{x11},~{x12},~{x13},~{x14},~{x15},~{x16},~{x17},~{x18},~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27},~{x28},~{x29},~{x30},~{x31}"()
   %a = icmp eq i64 %x, 0
@@ -353,50 +353,50 @@ define i64 @test_sext_h(i64 %x, i16 %y) nounwind {
 ;
 ; RV64ZB-PURECAP-LABEL: test_sext_h:
 ; RV64ZB-PURECAP:       # %bb.0:
-; RV64ZB-PURECAP-NEXT:    cincoffset csp, csp, -256
-; RV64ZB-PURECAP-NEXT:    csc cra, 240(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cgp, 224(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc ctp, 208(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cs0, 192(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cs1, 176(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cs2, 160(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cs3, 144(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cs4, 128(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cs5, 112(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cs6, 96(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cs7, 80(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cs8, 64(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cs9, 48(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cs10, 32(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cs11, 16(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csd a1, 0(csp) # 8-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csd a0, 8(csp) # 8-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    cincoffset sp, sp, -256
+; RV64ZB-PURECAP-NEXT:    csc ra, 240(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc gp, 224(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc tp, 208(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc s0, 192(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc s1, 176(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc s2, 160(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc s3, 144(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc s4, 128(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc s5, 112(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc s6, 96(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc s7, 80(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc s8, 64(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc s9, 48(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc s10, 32(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc s11, 16(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csd a1, 0(sp) # 8-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csd a0, 8(sp) # 8-byte Folded Spill
 ; RV64ZB-PURECAP-NEXT:    #APP
 ; RV64ZB-PURECAP-NEXT:    #NO_APP
-; RV64ZB-PURECAP-NEXT:    cld a0, 8(csp) # 8-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    cld a0, 8(sp) # 8-byte Folded Reload
 ; RV64ZB-PURECAP-NEXT:    beqz a0, .LBB2_2
 ; RV64ZB-PURECAP-NEXT:  # %bb.1: # %falsebb
 ; RV64ZB-PURECAP-NEXT:    li a0, 0
 ; RV64ZB-PURECAP-NEXT:    j .LBB2_3
 ; RV64ZB-PURECAP-NEXT:  .LBB2_2: # %truebb
-; RV64ZB-PURECAP-NEXT:    clh a0, 0(csp) # 8-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clh a0, 0(sp) # 8-byte Folded Reload
 ; RV64ZB-PURECAP-NEXT:  .LBB2_3: # %falsebb
-; RV64ZB-PURECAP-NEXT:    clc cra, 240(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cgp, 224(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc ctp, 208(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cs0, 192(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cs1, 176(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cs2, 160(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cs3, 144(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cs4, 128(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cs5, 112(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cs6, 96(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cs7, 80(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cs8, 64(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cs9, 48(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cs10, 32(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cs11, 16(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    cincoffset csp, csp, 256
+; RV64ZB-PURECAP-NEXT:    clc ra, 240(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc gp, 224(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc tp, 208(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc s0, 192(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc s1, 176(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc s2, 160(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc s3, 144(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc s4, 128(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc s5, 112(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc s6, 96(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc s7, 80(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc s8, 64(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc s9, 48(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc s10, 32(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc s11, 16(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    cincoffset sp, sp, 256
 ; RV64ZB-PURECAP-NEXT:    cret
   tail call void asm sideeffect "", "~{x1},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x9},~{x10},~{x11},~{x12},~{x13},~{x14},~{x15},~{x16},~{x17},~{x18},~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27},~{x28},~{x29},~{x30},~{x31}"()
   %a = icmp eq i64 %x, 0
@@ -456,50 +456,50 @@ define i64 @test_zext_b(i64 %x, i8 %y) nounwind {
 ;
 ; RV64ZB-PURECAP-LABEL: test_zext_b:
 ; RV64ZB-PURECAP:       # %bb.0:
-; RV64ZB-PURECAP-NEXT:    cincoffset csp, csp, -256
-; RV64ZB-PURECAP-NEXT:    csc cra, 240(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cgp, 224(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc ctp, 208(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cs0, 192(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cs1, 176(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cs2, 160(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cs3, 144(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cs4, 128(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cs5, 112(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cs6, 96(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cs7, 80(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cs8, 64(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cs9, 48(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cs10, 32(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cs11, 16(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csd a1, 0(csp) # 8-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csd a0, 8(csp) # 8-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    cincoffset sp, sp, -256
+; RV64ZB-PURECAP-NEXT:    csc ra, 240(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc gp, 224(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc tp, 208(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc s0, 192(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc s1, 176(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc s2, 160(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc s3, 144(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc s4, 128(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc s5, 112(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc s6, 96(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc s7, 80(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc s8, 64(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc s9, 48(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc s10, 32(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc s11, 16(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csd a1, 0(sp) # 8-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csd a0, 8(sp) # 8-byte Folded Spill
 ; RV64ZB-PURECAP-NEXT:    #APP
 ; RV64ZB-PURECAP-NEXT:    #NO_APP
-; RV64ZB-PURECAP-NEXT:    cld a0, 8(csp) # 8-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    cld a0, 8(sp) # 8-byte Folded Reload
 ; RV64ZB-PURECAP-NEXT:    beqz a0, .LBB3_2
 ; RV64ZB-PURECAP-NEXT:  # %bb.1: # %falsebb
 ; RV64ZB-PURECAP-NEXT:    li a0, 0
 ; RV64ZB-PURECAP-NEXT:    j .LBB3_3
 ; RV64ZB-PURECAP-NEXT:  .LBB3_2: # %truebb
-; RV64ZB-PURECAP-NEXT:    clbu a0, 0(csp) # 8-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clbu a0, 0(sp) # 8-byte Folded Reload
 ; RV64ZB-PURECAP-NEXT:  .LBB3_3: # %falsebb
-; RV64ZB-PURECAP-NEXT:    clc cra, 240(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cgp, 224(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc ctp, 208(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cs0, 192(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cs1, 176(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cs2, 160(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cs3, 144(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cs4, 128(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cs5, 112(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cs6, 96(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cs7, 80(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cs8, 64(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cs9, 48(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cs10, 32(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cs11, 16(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    cincoffset csp, csp, 256
+; RV64ZB-PURECAP-NEXT:    clc ra, 240(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc gp, 224(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc tp, 208(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc s0, 192(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc s1, 176(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc s2, 160(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc s3, 144(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc s4, 128(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc s5, 112(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc s6, 96(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc s7, 80(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc s8, 64(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc s9, 48(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc s10, 32(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc s11, 16(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    cincoffset sp, sp, 256
 ; RV64ZB-PURECAP-NEXT:    cret
   tail call void asm sideeffect "", "~{x1},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x9},~{x10},~{x11},~{x12},~{x13},~{x14},~{x15},~{x16},~{x17},~{x18},~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27},~{x28},~{x29},~{x30},~{x31}"()
   %a = icmp eq i64 %x, 0
@@ -605,50 +605,50 @@ define i64 @test_zext_h(i64 %x, i16 %y) nounwind {
 ;
 ; RV64ZB-PURECAP-LABEL: test_zext_h:
 ; RV64ZB-PURECAP:       # %bb.0:
-; RV64ZB-PURECAP-NEXT:    cincoffset csp, csp, -256
-; RV64ZB-PURECAP-NEXT:    csc cra, 240(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cgp, 224(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc ctp, 208(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cs0, 192(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cs1, 176(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cs2, 160(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cs3, 144(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cs4, 128(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cs5, 112(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cs6, 96(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cs7, 80(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cs8, 64(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cs9, 48(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cs10, 32(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cs11, 16(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csd a1, 0(csp) # 8-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csd a0, 8(csp) # 8-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    cincoffset sp, sp, -256
+; RV64ZB-PURECAP-NEXT:    csc ra, 240(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc gp, 224(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc tp, 208(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc s0, 192(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc s1, 176(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc s2, 160(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc s3, 144(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc s4, 128(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc s5, 112(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc s6, 96(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc s7, 80(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc s8, 64(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc s9, 48(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc s10, 32(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc s11, 16(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csd a1, 0(sp) # 8-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csd a0, 8(sp) # 8-byte Folded Spill
 ; RV64ZB-PURECAP-NEXT:    #APP
 ; RV64ZB-PURECAP-NEXT:    #NO_APP
-; RV64ZB-PURECAP-NEXT:    cld a0, 8(csp) # 8-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    cld a0, 8(sp) # 8-byte Folded Reload
 ; RV64ZB-PURECAP-NEXT:    beqz a0, .LBB4_2
 ; RV64ZB-PURECAP-NEXT:  # %bb.1: # %falsebb
 ; RV64ZB-PURECAP-NEXT:    li a0, 0
 ; RV64ZB-PURECAP-NEXT:    j .LBB4_3
 ; RV64ZB-PURECAP-NEXT:  .LBB4_2: # %truebb
-; RV64ZB-PURECAP-NEXT:    clhu a0, 0(csp) # 8-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clhu a0, 0(sp) # 8-byte Folded Reload
 ; RV64ZB-PURECAP-NEXT:  .LBB4_3: # %falsebb
-; RV64ZB-PURECAP-NEXT:    clc cra, 240(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cgp, 224(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc ctp, 208(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cs0, 192(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cs1, 176(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cs2, 160(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cs3, 144(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cs4, 128(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cs5, 112(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cs6, 96(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cs7, 80(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cs8, 64(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cs9, 48(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cs10, 32(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cs11, 16(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    cincoffset csp, csp, 256
+; RV64ZB-PURECAP-NEXT:    clc ra, 240(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc gp, 224(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc tp, 208(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc s0, 192(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc s1, 176(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc s2, 160(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc s3, 144(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc s4, 128(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc s5, 112(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc s6, 96(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc s7, 80(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc s8, 64(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc s9, 48(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc s10, 32(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc s11, 16(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    cincoffset sp, sp, 256
 ; RV64ZB-PURECAP-NEXT:    cret
   tail call void asm sideeffect "", "~{x1},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x9},~{x10},~{x11},~{x12},~{x13},~{x14},~{x15},~{x16},~{x17},~{x18},~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27},~{x28},~{x29},~{x30},~{x31}"()
   %a = icmp eq i64 %x, 0
@@ -754,50 +754,50 @@ define i64 @test_zext_w(i64 %x, i32 %y) nounwind {
 ;
 ; RV64ZB-PURECAP-LABEL: test_zext_w:
 ; RV64ZB-PURECAP:       # %bb.0:
-; RV64ZB-PURECAP-NEXT:    cincoffset csp, csp, -256
-; RV64ZB-PURECAP-NEXT:    csc cra, 240(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cgp, 224(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc ctp, 208(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cs0, 192(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cs1, 176(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cs2, 160(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cs3, 144(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cs4, 128(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cs5, 112(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cs6, 96(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cs7, 80(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cs8, 64(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cs9, 48(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cs10, 32(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csc cs11, 16(csp) # 16-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csd a1, 0(csp) # 8-byte Folded Spill
-; RV64ZB-PURECAP-NEXT:    csd a0, 8(csp) # 8-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    cincoffset sp, sp, -256
+; RV64ZB-PURECAP-NEXT:    csc ra, 240(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc gp, 224(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc tp, 208(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc s0, 192(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc s1, 176(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc s2, 160(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc s3, 144(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc s4, 128(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc s5, 112(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc s6, 96(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc s7, 80(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc s8, 64(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc s9, 48(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc s10, 32(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csc s11, 16(sp) # 16-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csd a1, 0(sp) # 8-byte Folded Spill
+; RV64ZB-PURECAP-NEXT:    csd a0, 8(sp) # 8-byte Folded Spill
 ; RV64ZB-PURECAP-NEXT:    #APP
 ; RV64ZB-PURECAP-NEXT:    #NO_APP
-; RV64ZB-PURECAP-NEXT:    cld a0, 8(csp) # 8-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    cld a0, 8(sp) # 8-byte Folded Reload
 ; RV64ZB-PURECAP-NEXT:    beqz a0, .LBB5_2
 ; RV64ZB-PURECAP-NEXT:  # %bb.1: # %falsebb
 ; RV64ZB-PURECAP-NEXT:    li a0, 0
 ; RV64ZB-PURECAP-NEXT:    j .LBB5_3
 ; RV64ZB-PURECAP-NEXT:  .LBB5_2: # %truebb
-; RV64ZB-PURECAP-NEXT:    clwu a0, 0(csp) # 8-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clwu a0, 0(sp) # 8-byte Folded Reload
 ; RV64ZB-PURECAP-NEXT:  .LBB5_3: # %falsebb
-; RV64ZB-PURECAP-NEXT:    clc cra, 240(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cgp, 224(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc ctp, 208(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cs0, 192(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cs1, 176(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cs2, 160(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cs3, 144(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cs4, 128(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cs5, 112(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cs6, 96(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cs7, 80(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cs8, 64(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cs9, 48(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cs10, 32(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    clc cs11, 16(csp) # 16-byte Folded Reload
-; RV64ZB-PURECAP-NEXT:    cincoffset csp, csp, 256
+; RV64ZB-PURECAP-NEXT:    clc ra, 240(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc gp, 224(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc tp, 208(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc s0, 192(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc s1, 176(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc s2, 160(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc s3, 144(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc s4, 128(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc s5, 112(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc s6, 96(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc s7, 80(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc s8, 64(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc s9, 48(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc s10, 32(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    clc s11, 16(sp) # 16-byte Folded Reload
+; RV64ZB-PURECAP-NEXT:    cincoffset sp, sp, 256
 ; RV64ZB-PURECAP-NEXT:    cret
   tail call void asm sideeffect "", "~{x1},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x9},~{x10},~{x11},~{x12},~{x13},~{x14},~{x15},~{x16},~{x17},~{x18},~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27},~{x28},~{x29},~{x30},~{x31}"()
   %a = icmp eq i64 %x, 0
diff --git a/llvm/test/MC/RISCV/cheri/attribute-with-insts.s b/llvm/test/MC/RISCV/cheri/attribute-with-insts.s
index 1cc4ab7a4c94e..4c41daf57699d 100644
--- a/llvm/test/MC/RISCV/cheri/attribute-with-insts.s
+++ b/llvm/test/MC/RISCV/cheri/attribute-with-insts.s
@@ -12,5 +12,5 @@
 
 .attribute arch, "rv64i2p1_xcheri0p0"
 
-# CHECK-INST: cincoffset ct0, ct1, 0
+# CHECK-INST: cincoffset t0, t1, 0
 cincoffset ct0, ct1, 0
diff --git a/llvm/test/MC/RISCV/cheri/cheriot-auipcccgp.s b/llvm/test/MC/RISCV/cheri/cheriot-auipcccgp.s
index 029743d3d4b5f..7a966a8f19276 100644
--- a/llvm/test/MC/RISCV/cheri/cheriot-auipcccgp.s
+++ b/llvm/test/MC/RISCV/cheri/cheriot-auipcccgp.s
@@ -2,14 +2,14 @@
 # RUN:     | FileCheck %s
 hello:
 	auipcc ca0, 12345
-	# CHECK: auipcc  ca0, 12345
+	# CHECK: auipcc  a0, 12345
 	# CHECK: encoding: [0x17,0x95,0x03,0x03]
 	auicgp cra, 12345
-	# CHECK:        auicgp  cra, 12345
+	# CHECK:        auicgp  ra, 12345
 	# CHECK: encoding: [0xfb,0x90,0x03,0x03]
 	auipcc csp, 12345
-	# CHECK:        auipcc  csp, 12345
+	# CHECK:        auipcc  sp, 12345
 	# CHECK: encoding: [0x17,0x91,0x03,0x03]
 	auicgp csp, 12345
-	# CHECK:        auicgp  csp, 12345
+	# CHECK:        auicgp  sp, 12345
 	# CHECK: encoding: [0x7b,0x91,0x03,0x03]
diff --git a/llvm/test/MC/RISCV/cheri/cheriot-only.s b/llvm/test/MC/RISCV/cheri/cheriot-only.s
index f3e2a3ce719ea..452ec0ffa749d 100644
--- a/llvm/test/MC/RISCV/cheri/cheriot-only.s
+++ b/llvm/test/MC/RISCV/cheri/cheriot-only.s
@@ -4,6 +4,6 @@
 foo:
 // CHERIOT: foo:
     auipcc ct3, %cheriot_compartment_hi(foo)
-// CHERIOT: ct.auipcc	ct3, %cheriot_compartment_hi(foo)
+// CHERIOT: ct.auipcc	t3, %cheriot_compartment_hi(foo)
     clc  ct2, %cheriot_compartment_lo_i(foo)(ct2)
-// CHERIOT: ct.clc	ct2, %cheriot_compartment_lo_i(foo)(ct2)
+// CHERIOT: ct.clc	t2, %cheriot_compartment_lo_i(foo)(t2)
diff --git a/llvm/test/MC/RISCV/cheri/cheriot.s b/llvm/test/MC/RISCV/cheri/cheriot.s
index 1b0f53998cfee..cd573bd03feea 100644
--- a/llvm/test/MC/RISCV/cheri/cheriot.s
+++ b/llvm/test/MC/RISCV/cheri/cheriot.s
@@ -3,72 +3,72 @@
 // RUN: llvm-mc %s -triple=riscv32 -mattr=+xcheri,+xcheripurecap -show-encoding | FileCheck %s -check-prefixes=CHERI
 
 csetboundsrounddown cra, cra, zero
-// CHERIOT: ct.csetboundsrounddown	cra, cra, zero  # encoding: [0xdb,0x80,0x00,0x14]
-// CHERI: csetboundsrounddown	cra, cra, zero  # encoding: [0xdb,0x80,0x00,0x14]
+// CHERIOT: ct.csetboundsrounddown	ra, ra, zero  # encoding: [0xdb,0x80,0x00,0x14]
+// CHERI: csetboundsrounddown	ra, ra, zero  # encoding: [0xdb,0x80,0x00,0x14]
 csetboundsrounddown cra, ca5, zero
-// CHERIOT: ct.csetboundsrounddown	cra, ca5, zero  # encoding: [0xdb,0x80,0x07,0x14]
-// CHERI: csetboundsrounddown	cra, ca5, zero  # encoding: [0xdb,0x80,0x07,0x14]
+// CHERIOT: ct.csetboundsrounddown	ra, a5, zero  # encoding: [0xdb,0x80,0x07,0x14]
+// CHERI: csetboundsrounddown	ra, a5, zero  # encoding: [0xdb,0x80,0x07,0x14]
 csetboundsrounddown cra, cra, a5
-// CHERIOT: ct.csetboundsrounddown	cra, cra, a5    # encoding: [0xdb,0x80,0xf0,0x14]
-// CHERI: csetboundsrounddown	cra, cra, a5    # encoding: [0xdb,0x80,0xf0,0x14]
+// CHERIOT: ct.csetboundsrounddown	ra, ra, a5    # encoding: [0xdb,0x80,0xf0,0x14]
+// CHERI: csetboundsrounddown	ra, ra, a5    # encoding: [0xdb,0x80,0xf0,0x14]
 csetboundsrounddown cra, ca5, a5
-// CHERIOT: ct.csetboundsrounddown	cra, ca5, a5    # encoding: [0xdb,0x80,0xf7,0x14]
-// CHERI: csetboundsrounddown	cra, ca5, a5    # encoding: [0xdb,0x80,0xf7,0x14]
+// CHERIOT: ct.csetboundsrounddown	ra, a5, a5    # encoding: [0xdb,0x80,0xf7,0x14]
+// CHERI: csetboundsrounddown	ra, a5, a5    # encoding: [0xdb,0x80,0xf7,0x14]
 csetboundsrounddown ca5, cra, zero
-// CHERIOT: ct.csetboundsrounddown	ca5, cra, zero  # encoding: [0xdb,0x87,0x00,0x14]
-// CHERI: csetboundsrounddown	ca5, cra, zero  # encoding: [0xdb,0x87,0x00,0x14]
+// CHERIOT: ct.csetboundsrounddown	a5, ra, zero  # encoding: [0xdb,0x87,0x00,0x14]
+// CHERI: csetboundsrounddown	a5, ra, zero  # encoding: [0xdb,0x87,0x00,0x14]
 csetboundsrounddown ca5, ca5, zero
-// CHERIOT: ct.csetboundsrounddown	ca5, ca5, zero  # encoding: [0xdb,0x87,0x07,0x14]
-// CHERI: csetboundsrounddown	ca5, ca5, zero  # encoding: [0xdb,0x87,0x07,0x14]
+// CHERIOT: ct.csetboundsrounddown	a5, a5, zero  # encoding: [0xdb,0x87,0x07,0x14]
+// CHERI: csetboundsrounddown	a5, a5, zero  # encoding: [0xdb,0x87,0x07,0x14]
 csetboundsrounddown ca5, cra, a5
-// CHERIOT: ct.csetboundsrounddown	ca5, cra, a5    # encoding: [0xdb,0x87,0xf0,0x14]
-// CHERI: csetboundsrounddown	ca5, cra, a5    # encoding: [0xdb,0x87,0xf0,0x14]
+// CHERIOT: ct.csetboundsrounddown	a5, ra, a5    # encoding: [0xdb,0x87,0xf0,0x14]
+// CHERI: csetboundsrounddown	a5, ra, a5    # encoding: [0xdb,0x87,0xf0,0x14]
 csetboundsrounddown ca5, ca5, a5
-// CHERIOT: ct.csetboundsrounddown	ca5, ca5, a5    # encoding: [0xdb,0x87,0xf7,0x14]
-// CHERI: csetboundsrounddown	ca5, ca5, a5    # encoding: [0xdb,0x87,0xf7,0x14]
+// CHERIOT: ct.csetboundsrounddown	a5, a5, a5    # encoding: [0xdb,0x87,0xf7,0x14]
+// CHERI: csetboundsrounddown	a5, a5, a5    # encoding: [0xdb,0x87,0xf7,0x14]
 
 candperm ca1, ca5, x2
-// CHERIOT: ct.candperm	ca1, ca5, sp            # encoding: [0xdb,0x85,0x27,0x1a]
-// CHERI: candperm	ca1, ca5, sp                    # encoding: [0xdb,0x85,0x27,0x1a]
+// CHERIOT: ct.candperm	a1, a5, sp            # encoding: [0xdb,0x85,0x27,0x1a]
+// CHERI: candperm	a1, a5, sp                    # encoding: [0xdb,0x85,0x27,0x1a]
 ccleartag ca1, ca5
-// CHERIOT: ct.ccleartag	ca1, ca5                # encoding: [0xdb,0x85,0xb7,0xfe]
-// CHERI: ccleartag	ca1, ca5                # encoding: [0xdb,0x85,0xb7,0xfe]
+// CHERIOT: ct.ccleartag	a1, a5                # encoding: [0xdb,0x85,0xb7,0xfe]
+// CHERI: ccleartag	a1, a5                # encoding: [0xdb,0x85,0xb7,0xfe]
 cgetbase x2, ca5
-// CHERIOT: ct.cgetbase	sp, ca5                 # encoding: [0x5b,0x81,0x27,0xfe]
-// CHERI: cgetbase	sp, ca5                         # encoding: [0x5b,0x81,0x27,0xfe]
+// CHERIOT: ct.cgetbase	sp, a5                 # encoding: [0x5b,0x81,0x27,0xfe]
+// CHERI: cgetbase	sp, a5                         # encoding: [0x5b,0x81,0x27,0xfe]
 cgethigh x2, ca5
-// CHERIOT: ct.cgethigh	sp, ca5                 # encoding: [0x5b,0x81,0x77,0xff]
-// CHERI: cgethigh	sp, ca5                         # encoding: [0x5b,0x81,0x77,0xff]
+// CHERIOT: ct.cgethigh	sp, a5                 # encoding: [0x5b,0x81,0x77,0xff]
+// CHERI: cgethigh	sp, a5                         # encoding: [0x5b,0x81,0x77,0xff]
 cgetlen x2, ca5
-// CHERIOT: ct.cgetlen	sp, ca5                 # encoding: [0x5b,0x81,0x37,0xfe]
-// CHERI: cgetlen	sp, ca5                         # encoding: [0x5b,0x81,0x37,0xfe]
+// CHERIOT: ct.cgetlen	sp, a5                 # encoding: [0x5b,0x81,0x37,0xfe]
+// CHERI: cgetlen	sp, a5                         # encoding: [0x5b,0x81,0x37,0xfe]
 cgetperm x2, ca5
-// CHERIOT: ct.cgetperm	sp, ca5                 # encoding: [0x5b,0x81,0x07,0xfe]
-// CHERI: cgetperm	sp, ca5                         # encoding: [0x5b,0x81,0x07,0xfe]
+// CHERIOT: ct.cgetperm	sp, a5                 # encoding: [0x5b,0x81,0x07,0xfe]
+// CHERI: cgetperm	sp, a5                         # encoding: [0x5b,0x81,0x07,0xfe]
 cgettag x2, ca5
-// CHERIOT: ct.cgettag	sp, ca5                 # encoding: [0x5b,0x81,0x47,0xfe]
-// CHERI: cgettag	sp, ca5                         # encoding: [0x5b,0x81,0x47,0xfe]
+// CHERIOT: ct.cgettag	sp, a5                 # encoding: [0x5b,0x81,0x47,0xfe]
+// CHERI: cgettag	sp, a5                         # encoding: [0x5b,0x81,0x47,0xfe]
 cgettype x2, ca5
-// CHERIOT: ct.cgettype	sp, ca5                 # encoding: [0x5b,0x81,0x17,0xfe]
-// CHERI: cgettype	sp, ca5                         # encoding: [0x5b,0x81,0x17,0xfe]
+// CHERIOT: ct.cgettype	sp, a5                 # encoding: [0x5b,0x81,0x17,0xfe]
+// CHERI: cgettype	sp, a5                         # encoding: [0x5b,0x81,0x17,0xfe]
 cincoffset ca1, ca2, x2
-// CHERIOT: ct.cincoffset	ca1, ca2, sp            # encoding: [0xdb,0x05,0x26,0x22]
-// CHERI: cincoffset	ca1, ca2, sp            # encoding: [0xdb,0x05,0x26,0x22]
+// CHERIOT: ct.cincoffset	a1, a2, sp            # encoding: [0xdb,0x05,0x26,0x22]
+// CHERI: cincoffset	a1, a2, sp            # encoding: [0xdb,0x05,0x26,0x22]
 cincoffset ca1, ca2, 3
-// CHERIOT: ct.cincoffset	ca1, ca2, 3             # encoding: [0xdb,0x15,0x36,0x00]
-// CHERI: cincoffset	ca1, ca2, 3             # encoding: [0xdb,0x15,0x36,0x00]
+// CHERIOT: ct.cincoffset	a1, a2, 3             # encoding: [0xdb,0x15,0x36,0x00]
+// CHERI: cincoffset	a1, a2, 3             # encoding: [0xdb,0x15,0x36,0x00]
 cincoffsetimm ca1, ca2, 3
-// CHERIOT: ct.cincoffset	ca1, ca2, 3             # encoding: [0xdb,0x15,0x36,0x00]
-// CHERI: cincoffset	ca1, ca2, 3             # encoding: [0xdb,0x15,0x36,0x00]
+// CHERIOT: ct.cincoffset	a1, a2, 3             # encoding: [0xdb,0x15,0x36,0x00]
+// CHERI: cincoffset	a1, a2, 3             # encoding: [0xdb,0x15,0x36,0x00]
 clc c1, (ca2)
-// CHERIOT: ct.clc	cra, 0(ca2)                     # encoding: [0x83,0x30,0x06,0x00]
-// CHERI: clc	cra, 0(ca2)                     # encoding: [0x83,0x30,0x06,0x00]
+// CHERIOT: ct.clc	ra, 0(a2)                     # encoding: [0x83,0x30,0x06,0x00]
+// CHERI: clc	ra, 0(a2)                     # encoding: [0x83,0x30,0x06,0x00]
 clc c1, 7(ca2)
-// CHERIOT: ct.clc	cra, 7(ca2)                     # encoding: [0x83,0x30,0x76,0x00]
-// CHERI: clc	cra, 7(ca2)                     # encoding: [0x83,0x30,0x76,0x00]
+// CHERIOT: ct.clc	ra, 7(a2)                     # encoding: [0x83,0x30,0x76,0x00]
+// CHERI: clc	ra, 7(a2)                     # encoding: [0x83,0x30,0x76,0x00]
 cmove ca1, ca2
-// CHERIOT: ct.cmove	ca1, ca2                        # encoding: [0xdb,0x05,0xa6,0xfe]
-// CHERI: cmove	ca1, ca2                        # encoding: [0xdb,0x05,0xa6,0xfe]
+// CHERIOT: ct.cmove	a1, a2                        # encoding: [0xdb,0x05,0xa6,0xfe]
+// CHERI: cmove	a1, a2                        # encoding: [0xdb,0x05,0xa6,0xfe]
 cram x2, x5
 // CHERIOT: cram	sp, t0                          # encoding: [0x5b,0x81,0x92,0xfe]
 // CHERI: cram	sp, t0                          # encoding: [0x5b,0x81,0x92,0xfe]
@@ -82,41 +82,41 @@ croundrepresentablelength x2, x5
 // CHERIOT: crrl	sp, t0                          # encoding: [0x5b,0x81,0x82,0xfe]
 // CHERI: crrl	sp, t0                          # encoding: [0x5b,0x81,0x82,0xfe]
 csc c1, (ca2)
-// CHERIOT: ct.csc	cra, 0(ca2)                     # encoding: [0x23,0x30,0x16,0x00]
-// CHERI: csc	cra, 0(ca2)                     # encoding: [0x23,0x30,0x16,0x00]
+// CHERIOT: ct.csc	ra, 0(a2)                     # encoding: [0x23,0x30,0x16,0x00]
+// CHERI: csc	ra, 0(a2)                     # encoding: [0x23,0x30,0x16,0x00]
 csc c1, 7(ca2)
-// CHERIOT: ct.csc	cra, 7(ca2)                     # encoding: [0xa3,0x33,0x16,0x00]
-// CHERI: csc	cra, 7(ca2)                     # encoding: [0xa3,0x33,0x16,0x00]
+// CHERIOT: ct.csc	ra, 7(a2)                     # encoding: [0xa3,0x33,0x16,0x00]
+// CHERI: csc	ra, 7(a2)                     # encoding: [0xa3,0x33,0x16,0x00]
 cseal ca1, ca2, ca3
-// CHERIOT: ct.cseal	ca1, ca2, ca3                   # encoding: [0xdb,0x05,0xd6,0x16]
-// CHERI: cseal	ca1, ca2, ca3                   # encoding: [0xdb,0x05,0xd6,0x16]
+// CHERIOT: ct.cseal	a1, a2, a3                   # encoding: [0xdb,0x05,0xd6,0x16]
+// CHERI: cseal	a1, a2, a3                   # encoding: [0xdb,0x05,0xd6,0x16]
 csetaddr ca5, ca3, x2
-// CHERIOT: ct.csetaddr	ca5, ca3, sp            # encoding: [0xdb,0x87,0x26,0x20]
-// CHERI: csetaddr	ca5, ca3, sp                    # encoding: [0xdb,0x87,0x26,0x20]
+// CHERIOT: ct.csetaddr	a5, a3, sp            # encoding: [0xdb,0x87,0x26,0x20]
+// CHERI: csetaddr	a5, a3, sp                    # encoding: [0xdb,0x87,0x26,0x20]
 csetbounds ca5, ca3, x2
-// CHERIOT: ct.csetbounds	ca5, ca3, sp            # encoding: [0xdb,0x87,0x26,0x10]
-// CHERI: csetbounds	ca5, ca3, sp            # encoding: [0xdb,0x87,0x26,0x10]
+// CHERIOT: ct.csetbounds	a5, a3, sp            # encoding: [0xdb,0x87,0x26,0x10]
+// CHERI: csetbounds	a5, a3, sp            # encoding: [0xdb,0x87,0x26,0x10]
 csetbounds ca5, ca3, 3
-// CHERIOT: ct.csetbounds	ca5, ca3, 3             # encoding: [0xdb,0xa7,0x36,0x00]
-// CHERI: csetbounds	ca5, ca3, 3             # encoding: [0xdb,0xa7,0x36,0x00]
+// CHERIOT: ct.csetbounds	a5, a3, 3             # encoding: [0xdb,0xa7,0x36,0x00]
+// CHERI: csetbounds	a5, a3, 3             # encoding: [0xdb,0xa7,0x36,0x00]
 csetboundsimm ca5, ca3, 3
-// CHERIOT: ct.csetbounds	ca5, ca3, 3             # encoding: [0xdb,0xa7,0x36,0x00]
-// CHERI: csetbounds	ca5, ca3, 3             # encoding: [0xdb,0xa7,0x36,0x00]
+// CHERIOT: ct.csetbounds	a5, a3, 3             # encoding: [0xdb,0xa7,0x36,0x00]
+// CHERI: csetbounds	a5, a3, 3             # encoding: [0xdb,0xa7,0x36,0x00]
 csetboundsexact ca5, ca3, x2
-// CHERIOT: ct.csetboundsexact	ca5, ca3, sp    # encoding: [0xdb,0x87,0x26,0x12]
-// CHERI: csetboundsexact	ca5, ca3, sp            # encoding: [0xdb,0x87,0x26,0x12]
+// CHERIOT: ct.csetboundsexact	a5, a3, sp    # encoding: [0xdb,0x87,0x26,0x12]
+// CHERI: csetboundsexact	a5, a3, sp            # encoding: [0xdb,0x87,0x26,0x12]
 csetequalexact x2, ca5, ca3
-// CHERIOT: ct.cseqx	sp, ca5, ca3                    # encoding: [0x5b,0x81,0xd7,0x42]
-// CHERI: cseqx	sp, ca5, ca3                    # encoding: [0x5b,0x81,0xd7,0x42]
+// CHERIOT: ct.cseqx	sp, a5, a3                    # encoding: [0x5b,0x81,0xd7,0x42]
+// CHERI: cseqx	sp, a5, a3                    # encoding: [0x5b,0x81,0xd7,0x42]
 cseqx x2, ca5, ca3
-// CHERIOT: ct.cseqx	sp, ca5, ca3                    # encoding: [0x5b,0x81,0xd7,0x42]
-// CHERI: cseqx	sp, ca5, ca3                    # encoding: [0x5b,0x81,0xd7,0x42]
+// CHERIOT: ct.cseqx	sp, a5, a3                    # encoding: [0x5b,0x81,0xd7,0x42]
+// CHERI: cseqx	sp, a5, a3                    # encoding: [0x5b,0x81,0xd7,0x42]
 csethigh ca5, ca3, x7
-// CHERIOT: ct.csethigh	ca5, ca3, t2            # encoding: [0xdb,0x87,0x76,0x2c]
-// CHERI: csethigh	ca5, ca3, t2                    # encoding: [0xdb,0x87,0x76,0x2c]
+// CHERIOT: ct.csethigh	a5, a3, t2            # encoding: [0xdb,0x87,0x76,0x2c]
+// CHERI: csethigh	a5, a3, t2                    # encoding: [0xdb,0x87,0x76,0x2c]
 ctestsubset x7, ca5, ca3
-// CHERIOT: ct.ctestsubset	t2, ca5, ca3            # encoding: [0xdb,0x83,0xd7,0x40]
-// CHERI: ctestsubset	t2, ca5, ca3            # encoding: [0xdb,0x83,0xd7,0x40]
+// CHERIOT: ct.ctestsubset	t2, a5, a3            # encoding: [0xdb,0x83,0xd7,0x40]
+// CHERI: ctestsubset	t2, a5, a3            # encoding: [0xdb,0x83,0xd7,0x40]
 cunseal ca5, ca3, ca1
-// CHERIOT: ct.cunseal	ca5, ca3, ca1           # encoding: [0xdb,0x87,0xb6,0x18]
-// CHERI: cunseal	ca5, ca3, ca1                   # encoding: [0xdb,0x87,0xb6,0x18]
\ No newline at end of file
+// CHERIOT: ct.cunseal	a5, a3, a1           # encoding: [0xdb,0x87,0xb6,0x18]
+// CHERI: cunseal	a5, a3, a1                   # encoding: [0xdb,0x87,0xb6,0x18]
\ No newline at end of file
diff --git a/llvm/test/MC/RISCV/cheri/rv32axcheri-cap-mode-only-valid.s b/llvm/test/MC/RISCV/cheri/rv32axcheri-cap-mode-only-valid.s
index 8865eac659d33..d777e52e92cb1 100644
--- a/llvm/test/MC/RISCV/cheri/rv32axcheri-cap-mode-only-valid.s
+++ b/llvm/test/MC/RISCV/cheri/rv32axcheri-cap-mode-only-valid.s
@@ -12,41 +12,41 @@
 # RUN:     | llvm-objdump --mattr=+a,+xcheri,+xcheripurecap -M no-aliases -d -r - \
 # RUN:     | FileCheck -check-prefixes=CHECK-ASM-AND-OBJ %s
 
-# CHECK-ASM-AND-OBJ: clr.c ct0, (ct1)
+# CHECK-ASM-AND-OBJ: clr.c t0, (t1)
 # CHECK-ASM: encoding: [0xaf,0x32,0x03,0x10]
 clr.c ct0, (ct1)
-# CHECK-ASM-AND-OBJ: clr.c.aq ct1, (ct2)
+# CHECK-ASM-AND-OBJ: clr.c.aq t1, (t2)
 # CHECK-ASM: encoding: [0x2f,0xb3,0x03,0x14]
 clr.c.aq ct1, (ct2)
-# CHECK-ASM-AND-OBJ: clr.c.rl ct2, (ct3)
+# CHECK-ASM-AND-OBJ: clr.c.rl t2, (t3)
 # CHECK-ASM: encoding: [0xaf,0x33,0x0e,0x12]
 clr.c.rl ct2, (ct3)
-# CHECK-ASM-AND-OBJ: clr.c.aqrl ct3, (ct4)
+# CHECK-ASM-AND-OBJ: clr.c.aqrl t3, (t4)
 # CHECK-ASM: encoding: [0x2f,0xbe,0x0e,0x16]
 clr.c.aqrl ct3, (ct4)
 
-# CHECK-ASM-AND-OBJ: csc.c t6, ct5, (ct4)
+# CHECK-ASM-AND-OBJ: csc.c t6, t5, (t4)
 # CHECK-ASM: encoding: [0xaf,0xbf,0xee,0x19]
 csc.c t6, ct5, (ct4)
-# CHECK-ASM-AND-OBJ: csc.c.aq t5, ct4, (ct3)
+# CHECK-ASM-AND-OBJ: csc.c.aq t5, t4, (t3)
 # CHECK-ASM: encoding: [0x2f,0x3f,0xde,0x1d]
 csc.c.aq t5, ct4, (ct3)
-# CHECK-ASM-AND-OBJ: csc.c.rl t4, ct3, (ct2)
+# CHECK-ASM-AND-OBJ: csc.c.rl t4, t3, (t2)
 # CHECK-ASM: encoding: [0xaf,0xbe,0xc3,0x1b]
 csc.c.rl t4, ct3, (ct2)
-# CHECK-ASM-AND-OBJ: csc.c.aqrl t3, ct2, (ct1)
+# CHECK-ASM-AND-OBJ: csc.c.aqrl t3, t2, (t1)
 # CHECK-ASM: encoding: [0x2f,0x3e,0x73,0x1e]
 csc.c.aqrl t3, ct2, (ct1)
 
-# CHECK-ASM-AND-OBJ: camoswap.c ca4, cra, (cs0)
+# CHECK-ASM-AND-OBJ: camoswap.c a4, ra, (s0)
 # CHECK-ASM: encoding: [0x2f,0x37,0x14,0x08]
 camoswap.c ca4, cra, (cs0)
-# CHECK-ASM-AND-OBJ: camoswap.c.aq ca4, cra, (cs0)
+# CHECK-ASM-AND-OBJ: camoswap.c.aq a4, ra, (s0)
 # CHECK-ASM: encoding: [0x2f,0x37,0x14,0x0c]
 camoswap.c.aq ca4, cra, (cs0)
-# CHECK-ASM-AND-OBJ: camoswap.c.rl ca4, cra, (cs0)
+# CHECK-ASM-AND-OBJ: camoswap.c.rl a4, ra, (s0)
 # CHECK-ASM: encoding: [0x2f,0x37,0x14,0x0a]
 camoswap.c.rl ca4, cra, (cs0)
-# CHECK-ASM-AND-OBJ: camoswap.c.aqrl ca4, cra, (cs0)
+# CHECK-ASM-AND-OBJ: camoswap.c.aqrl a4, ra, (s0)
 # CHECK-ASM: encoding: [0x2f,0x37,0x14,0x0e]
 camoswap.c.aqrl ca4, cra, (cs0)
diff --git a/llvm/test/MC/RISCV/cheri/rv32axcheri-cap-mode-valid.s b/llvm/test/MC/RISCV/cheri/rv32axcheri-cap-mode-valid.s
index e485d6309513f..7809c6e70fb53 100644
--- a/llvm/test/MC/RISCV/cheri/rv32axcheri-cap-mode-valid.s
+++ b/llvm/test/MC/RISCV/cheri/rv32axcheri-cap-mode-valid.s
@@ -22,192 +22,192 @@
 # RUN:     | llvm-objdump --mattr=+a,+xcheri,+xcheripurecap -M no-aliases -d -r - \
 # RUN:     | FileCheck -check-prefixes=CHECK-ASM-AND-OBJ %s
 
-# CHECK-ASM-AND-OBJ: clr.b t0, (ct1)
+# CHECK-ASM-AND-OBJ: clr.b t0, (t1)
 # CHECK-ASM: encoding: [0xaf,0x02,0x03,0x10]
 clr.b t0, (ct1)
-# CHECK-ASM-AND-OBJ: clr.b.aq t1, (ct2)
+# CHECK-ASM-AND-OBJ: clr.b.aq t1, (t2)
 # CHECK-ASM: encoding: [0x2f,0x83,0x03,0x14]
 clr.b.aq t1, (ct2)
-# CHECK-ASM-AND-OBJ: clr.b.rl t2, (ct3)
+# CHECK-ASM-AND-OBJ: clr.b.rl t2, (t3)
 # CHECK-ASM: encoding: [0xaf,0x03,0x0e,0x12]
 clr.b.rl t2, (ct3)
-# CHECK-ASM-AND-OBJ: clr.b.aqrl t3, (ct4)
+# CHECK-ASM-AND-OBJ: clr.b.aqrl t3, (t4)
 # CHECK-ASM: encoding: [0x2f,0x8e,0x0e,0x16]
 clr.b.aqrl t3, (ct4)
 
-# CHECK-ASM-AND-OBJ: clr.h t0, (ct1)
+# CHECK-ASM-AND-OBJ: clr.h t0, (t1)
 # CHECK-ASM: encoding: [0xaf,0x12,0x03,0x10]
 clr.h t0, (ct1)
-# CHECK-ASM-AND-OBJ: clr.h.aq t1, (ct2)
+# CHECK-ASM-AND-OBJ: clr.h.aq t1, (t2)
 # CHECK-ASM: encoding: [0x2f,0x93,0x03,0x14]
 clr.h.aq t1, (ct2)
-# CHECK-ASM-AND-OBJ: clr.h.rl t2, (ct3)
+# CHECK-ASM-AND-OBJ: clr.h.rl t2, (t3)
 # CHECK-ASM: encoding: [0xaf,0x13,0x0e,0x12]
 clr.h.rl t2, (ct3)
-# CHECK-ASM-AND-OBJ: clr.h.aqrl t3, (ct4)
+# CHECK-ASM-AND-OBJ: clr.h.aqrl t3, (t4)
 # CHECK-ASM: encoding: [0x2f,0x9e,0x0e,0x16]
 clr.h.aqrl t3, (ct4)
 
-# CHECK-ASM-AND-OBJ: clr.w t0, (ct1)
+# CHECK-ASM-AND-OBJ: clr.w t0, (t1)
 # CHECK-ASM: encoding: [0xaf,0x22,0x03,0x10]
 clr.w t0, (ct1)
-# CHECK-ASM-AND-OBJ: clr.w.aq t1, (ct2)
+# CHECK-ASM-AND-OBJ: clr.w.aq t1, (t2)
 # CHECK-ASM: encoding: [0x2f,0xa3,0x03,0x14]
 clr.w.aq t1, (ct2)
-# CHECK-ASM-AND-OBJ: clr.w.rl t2, (ct3)
+# CHECK-ASM-AND-OBJ: clr.w.rl t2, (t3)
 # CHECK-ASM: encoding: [0xaf,0x23,0x0e,0x12]
 clr.w.rl t2, (ct3)
-# CHECK-ASM-AND-OBJ: clr.w.aqrl t3, (ct4)
+# CHECK-ASM-AND-OBJ: clr.w.aqrl t3, (t4)
 # CHECK-ASM: encoding: [0x2f,0xae,0x0e,0x16]
 clr.w.aqrl t3, (ct4)
 
-# CHECK-ASM-AND-OBJ: csc.b t6, t5, (ct4)
+# CHECK-ASM-AND-OBJ: csc.b t6, t5, (t4)
 # CHECK-ASM: encoding: [0xaf,0x8f,0xee,0x19]
 csc.b t6, t5, (ct4)
-# CHECK-ASM-AND-OBJ: csc.b.aq t5, t4, (ct3)
+# CHECK-ASM-AND-OBJ: csc.b.aq t5, t4, (t3)
 # CHECK-ASM: encoding: [0x2f,0x0f,0xde,0x1d]
 csc.b.aq t5, t4, (ct3)
-# CHECK-ASM-AND-OBJ: csc.b.rl t4, t3, (ct2)
+# CHECK-ASM-AND-OBJ: csc.b.rl t4, t3, (t2)
 # CHECK-ASM: encoding: [0xaf,0x8e,0xc3,0x1b]
 csc.b.rl t4, t3, (ct2)
-# CHECK-ASM-AND-OBJ: csc.b.aqrl t3, t2, (ct1)
+# CHECK-ASM-AND-OBJ: csc.b.aqrl t3, t2, (t1)
 # CHECK-ASM: encoding: [0x2f,0x0e,0x73,0x1e]
 csc.b.aqrl t3, t2, (ct1)
 
-# CHECK-ASM-AND-OBJ: csc.h t6, t5, (ct4)
+# CHECK-ASM-AND-OBJ: csc.h t6, t5, (t4)
 # CHECK-ASM: encoding: [0xaf,0x9f,0xee,0x19]
 csc.h t6, t5, (ct4)
-# CHECK-ASM-AND-OBJ: csc.h.aq t5, t4, (ct3)
+# CHECK-ASM-AND-OBJ: csc.h.aq t5, t4, (t3)
 # CHECK-ASM: encoding: [0x2f,0x1f,0xde,0x1d]
 csc.h.aq t5, t4, (ct3)
-# CHECK-ASM-AND-OBJ: csc.h.rl t4, t3, (ct2)
+# CHECK-ASM-AND-OBJ: csc.h.rl t4, t3, (t2)
 # CHECK-ASM: encoding: [0xaf,0x9e,0xc3,0x1b]
 csc.h.rl t4, t3, (ct2)
-# CHECK-ASM-AND-OBJ: csc.h.aqrl t3, t2, (ct1)
+# CHECK-ASM-AND-OBJ: csc.h.aqrl t3, t2, (t1)
 # CHECK-ASM: encoding: [0x2f,0x1e,0x73,0x1e]
 csc.h.aqrl t3, t2, (ct1)
 
-# CHECK-ASM-AND-OBJ: csc.w t6, t5, (ct4)
+# CHECK-ASM-AND-OBJ: csc.w t6, t5, (t4)
 # CHECK-ASM: encoding: [0xaf,0xaf,0xee,0x19]
 csc.w t6, t5, (ct4)
-# CHECK-ASM-AND-OBJ: csc.w.aq t5, t4, (ct3)
+# CHECK-ASM-AND-OBJ: csc.w.aq t5, t4, (t3)
 # CHECK-ASM: encoding: [0x2f,0x2f,0xde,0x1d]
 csc.w.aq t5, t4, (ct3)
-# CHECK-ASM-AND-OBJ: csc.w.rl t4, t3, (ct2)
+# CHECK-ASM-AND-OBJ: csc.w.rl t4, t3, (t2)
 # CHECK-ASM: encoding: [0xaf,0xae,0xc3,0x1b]
 csc.w.rl t4, t3, (ct2)
-# CHECK-ASM-AND-OBJ: csc.w.aqrl t3, t2, (ct1)
+# CHECK-ASM-AND-OBJ: csc.w.aqrl t3, t2, (t1)
 # CHECK-ASM: encoding: [0x2f,0x2e,0x73,0x1e]
 csc.w.aqrl t3, t2, (ct1)
 
-# CHECK-ASM-AND-OBJ: camoswap.w a4, ra, (cs0)
+# CHECK-ASM-AND-OBJ: camoswap.w a4, ra, (s0)
 # CHECK-ASM: encoding: [0x2f,0x27,0x14,0x08]
 camoswap.w a4, ra, (cs0)
-# CHECK-ASM-AND-OBJ: camoadd.w a1, a2, (ca3)
+# CHECK-ASM-AND-OBJ: camoadd.w a1, a2, (a3)
 # CHECK-ASM: encoding: [0xaf,0xa5,0xc6,0x00]
 camoadd.w a1, a2, (ca3)
-# CHECK-ASM-AND-OBJ: camoxor.w a2, a3, (ca4)
+# CHECK-ASM-AND-OBJ: camoxor.w a2, a3, (a4)
 # CHECK-ASM: encoding: [0x2f,0x26,0xd7,0x20]
 camoxor.w a2, a3, (ca4)
-# CHECK-ASM-AND-OBJ: camoand.w a3, a4, (ca5)
+# CHECK-ASM-AND-OBJ: camoand.w a3, a4, (a5)
 # CHECK-ASM: encoding: [0xaf,0xa6,0xe7,0x60]
 camoand.w a3, a4, (ca5)
-# CHECK-ASM-AND-OBJ: camoor.w a4, a5, (ca6)
+# CHECK-ASM-AND-OBJ: camoor.w a4, a5, (a6)
 # CHECK-ASM: encoding: [0x2f,0x27,0xf8,0x40]
 camoor.w a4, a5, (ca6)
-# CHECK-ASM-AND-OBJ: camomin.w a5, a6, (ca7)
+# CHECK-ASM-AND-OBJ: camomin.w a5, a6, (a7)
 # CHECK-ASM: encoding: [0xaf,0xa7,0x08,0x81]
 camomin.w a5, a6, (ca7)
-# CHECK-ASM-AND-OBJ: camomax.w s7, s6, (cs5)
+# CHECK-ASM-AND-OBJ: camomax.w s7, s6, (s5)
 # CHECK-ASM: encoding: [0xaf,0xab,0x6a,0xa1]
 camomax.w s7, s6, (cs5)
-# CHECK-ASM-AND-OBJ: camominu.w s6, s5, (cs4)
+# CHECK-ASM-AND-OBJ: camominu.w s6, s5, (s4)
 # CHECK-ASM: encoding: [0x2f,0x2b,0x5a,0xc1]
 camominu.w s6, s5, (cs4)
-# CHECK-ASM-AND-OBJ: camomaxu.w s5, s4, (cs3)
+# CHECK-ASM-AND-OBJ: camomaxu.w s5, s4, (s3)
 # CHECK-ASM: encoding: [0xaf,0xaa,0x49,0xe1]
 camomaxu.w s5, s4, (cs3)
 
-# CHECK-ASM-AND-OBJ: camoswap.w.aq a4, ra, (cs0)
+# CHECK-ASM-AND-OBJ: camoswap.w.aq a4, ra, (s0)
 # CHECK-ASM: encoding: [0x2f,0x27,0x14,0x0c]
 camoswap.w.aq a4, ra, (cs0)
-# CHECK-ASM-AND-OBJ: camoadd.w.aq a1, a2, (ca3)
+# CHECK-ASM-AND-OBJ: camoadd.w.aq a1, a2, (a3)
 # CHECK-ASM: encoding: [0xaf,0xa5,0xc6,0x04]
 camoadd.w.aq a1, a2, (ca3)
-# CHECK-ASM-AND-OBJ: camoxor.w.aq a2, a3, (ca4)
+# CHECK-ASM-AND-OBJ: camoxor.w.aq a2, a3, (a4)
 # CHECK-ASM: encoding: [0x2f,0x26,0xd7,0x24]
 camoxor.w.aq a2, a3, (ca4)
-# CHECK-ASM-AND-OBJ: camoand.w.aq a3, a4, (ca5)
+# CHECK-ASM-AND-OBJ: camoand.w.aq a3, a4, (a5)
 # CHECK-ASM: encoding: [0xaf,0xa6,0xe7,0x64]
 camoand.w.aq a3, a4, (ca5)
-# CHECK-ASM-AND-OBJ: camoor.w.aq a4, a5, (ca6)
+# CHECK-ASM-AND-OBJ: camoor.w.aq a4, a5, (a6)
 # CHECK-ASM: encoding: [0x2f,0x27,0xf8,0x44]
 camoor.w.aq a4, a5, (ca6)
-# CHECK-ASM-AND-OBJ: camomin.w.aq a5, a6, (ca7)
+# CHECK-ASM-AND-OBJ: camomin.w.aq a5, a6, (a7)
 # CHECK-ASM: encoding: [0xaf,0xa7,0x08,0x85]
 camomin.w.aq a5, a6, (ca7)
-# CHECK-ASM-AND-OBJ: camomax.w.aq s7, s6, (cs5)
+# CHECK-ASM-AND-OBJ: camomax.w.aq s7, s6, (s5)
 # CHECK-ASM: encoding: [0xaf,0xab,0x6a,0xa5]
 camomax.w.aq s7, s6, (cs5)
-# CHECK-ASM-AND-OBJ: camominu.w.aq s6, s5, (cs4)
+# CHECK-ASM-AND-OBJ: camominu.w.aq s6, s5, (s4)
 # CHECK-ASM: encoding: [0x2f,0x2b,0x5a,0xc5]
 camominu.w.aq s6, s5, (cs4)
-# CHECK-ASM-AND-OBJ: camomaxu.w.aq s5, s4, (cs3)
+# CHECK-ASM-AND-OBJ: camomaxu.w.aq s5, s4, (s3)
 # CHECK-ASM: encoding: [0xaf,0xaa,0x49,0xe5]
 camomaxu.w.aq s5, s4, (cs3)
 
-# CHECK-ASM-AND-OBJ: camoswap.w.rl a4, ra, (cs0)
+# CHECK-ASM-AND-OBJ: camoswap.w.rl a4, ra, (s0)
 # CHECK-ASM: encoding: [0x2f,0x27,0x14,0x0a]
 camoswap.w.rl a4, ra, (cs0)
-# CHECK-ASM-AND-OBJ: camoadd.w.rl a1, a2, (ca3)
+# CHECK-ASM-AND-OBJ: camoadd.w.rl a1, a2, (a3)
 # CHECK-ASM: encoding: [0xaf,0xa5,0xc6,0x02]
 camoadd.w.rl a1, a2, (ca3)
-# CHECK-ASM-AND-OBJ: camoxor.w.rl a2, a3, (ca4)
+# CHECK-ASM-AND-OBJ: camoxor.w.rl a2, a3, (a4)
 # CHECK-ASM: encoding: [0x2f,0x26,0xd7,0x22]
 camoxor.w.rl a2, a3, (ca4)
-# CHECK-ASM-AND-OBJ: camoand.w.rl a3, a4, (ca5)
+# CHECK-ASM-AND-OBJ: camoand.w.rl a3, a4, (a5)
 # CHECK-ASM: encoding: [0xaf,0xa6,0xe7,0x62]
 camoand.w.rl a3, a4, (ca5)
-# CHECK-ASM-AND-OBJ: camoor.w.rl a4, a5, (ca6)
+# CHECK-ASM-AND-OBJ: camoor.w.rl a4, a5, (a6)
 # CHECK-ASM: encoding: [0x2f,0x27,0xf8,0x42]
 camoor.w.rl a4, a5, (ca6)
-# CHECK-ASM-AND-OBJ: camomin.w.rl a5, a6, (ca7)
+# CHECK-ASM-AND-OBJ: camomin.w.rl a5, a6, (a7)
 # CHECK-ASM: encoding: [0xaf,0xa7,0x08,0x83]
 camomin.w.rl a5, a6, (ca7)
-# CHECK-ASM-AND-OBJ: camomax.w.rl s7, s6, (cs5)
+# CHECK-ASM-AND-OBJ: camomax.w.rl s7, s6, (s5)
 # CHECK-ASM: encoding: [0xaf,0xab,0x6a,0xa3]
 camomax.w.rl s7, s6, (cs5)
-# CHECK-ASM-AND-OBJ: camominu.w.rl s6, s5, (cs4)
+# CHECK-ASM-AND-OBJ: camominu.w.rl s6, s5, (s4)
 # CHECK-ASM: encoding: [0x2f,0x2b,0x5a,0xc3]
 camominu.w.rl s6, s5, (cs4)
-# CHECK-ASM-AND-OBJ: camomaxu.w.rl s5, s4, (cs3)
+# CHECK-ASM-AND-OBJ: camomaxu.w.rl s5, s4, (s3)
 # CHECK-ASM: encoding: [0xaf,0xaa,0x49,0xe3]
 camomaxu.w.rl s5, s4, (cs3)
 
-# CHECK-ASM-AND-OBJ: camoswap.w.aqrl a4, ra, (cs0)
+# CHECK-ASM-AND-OBJ: camoswap.w.aqrl a4, ra, (s0)
 # CHECK-ASM: encoding: [0x2f,0x27,0x14,0x0e]
 camoswap.w.aqrl a4, ra, (cs0)
-# CHECK-ASM-AND-OBJ: camoadd.w.aqrl a1, a2, (ca3)
+# CHECK-ASM-AND-OBJ: camoadd.w.aqrl a1, a2, (a3)
 # CHECK-ASM: encoding: [0xaf,0xa5,0xc6,0x06]
 camoadd.w.aqrl a1, a2, (ca3)
-# CHECK-ASM-AND-OBJ: camoxor.w.aqrl a2, a3, (ca4)
+# CHECK-ASM-AND-OBJ: camoxor.w.aqrl a2, a3, (a4)
 # CHECK-ASM: encoding: [0x2f,0x26,0xd7,0x26]
 camoxor.w.aqrl a2, a3, (ca4)
-# CHECK-ASM-AND-OBJ: camoand.w.aqrl a3, a4, (ca5)
+# CHECK-ASM-AND-OBJ: camoand.w.aqrl a3, a4, (a5)
 # CHECK-ASM: encoding: [0xaf,0xa6,0xe7,0x66]
 camoand.w.aqrl a3, a4, (ca5)
-# CHECK-ASM-AND-OBJ: camoor.w.aqrl a4, a5, (ca6)
+# CHECK-ASM-AND-OBJ: camoor.w.aqrl a4, a5, (a6)
 # CHECK-ASM: encoding: [0x2f,0x27,0xf8,0x46]
 camoor.w.aqrl a4, a5, (ca6)
-# CHECK-ASM-AND-OBJ: camomin.w.aqrl a5, a6, (ca7)
+# CHECK-ASM-AND-OBJ: camomin.w.aqrl a5, a6, (a7)
 # CHECK-ASM: encoding: [0xaf,0xa7,0x08,0x87]
 camomin.w.aqrl a5, a6, (ca7)
-# CHECK-ASM-AND-OBJ: camomax.w.aqrl s7, s6, (cs5)
+# CHECK-ASM-AND-OBJ: camomax.w.aqrl s7, s6, (s5)
 # CHECK-ASM: encoding: [0xaf,0xab,0x6a,0xa7]
 camomax.w.aqrl s7, s6, (cs5)
-# CHECK-ASM-AND-OBJ: camominu.w.aqrl s6, s5, (cs4)
+# CHECK-ASM-AND-OBJ: camominu.w.aqrl s6, s5, (s4)
 # CHECK-ASM: encoding: [0x2f,0x2b,0x5a,0xc7]
 camominu.w.aqrl s6, s5, (cs4)
-# CHECK-ASM-AND-OBJ: camomaxu.w.aqrl s5, s4, (cs3)
+# CHECK-ASM-AND-OBJ: camomaxu.w.aqrl s5, s4, (s3)
 # CHECK-ASM: encoding: [0xaf,0xaa,0x49,0xe7]
 camomaxu.w.aqrl s5, s4, (cs3)
diff --git a/llvm/test/MC/RISCV/cheri/rv32axcheri-only-valid.s b/llvm/test/MC/RISCV/cheri/rv32axcheri-only-valid.s
index e7d75d3a0e6e1..f2f7d294c19d9 100644
--- a/llvm/test/MC/RISCV/cheri/rv32axcheri-only-valid.s
+++ b/llvm/test/MC/RISCV/cheri/rv32axcheri-only-valid.s
@@ -4,57 +4,57 @@
 # RUN:     | llvm-objdump -M no-aliases --mattr=+a,+xcheri -d - \
 # RUN:     | FileCheck -check-prefixes=CHECK-ASM-AND-OBJ %s
 
-# CHECK-ASM-AND-OBJ: lr.c ct0, (t1)
+# CHECK-ASM-AND-OBJ: lr.c t0, (t1)
 # CHECK-ASM: encoding: [0xaf,0x32,0x03,0x10]
 lr.c ct0, (t1)
-# CHECK-ASM-AND-OBJ: lr.c.aq ct1, (t2)
+# CHECK-ASM-AND-OBJ: lr.c.aq t1, (t2)
 # CHECK-ASM: encoding: [0x2f,0xb3,0x03,0x14]
 lr.c.aq ct1, (t2)
-# CHECK-ASM-AND-OBJ: lr.c.rl ct2, (t3)
+# CHECK-ASM-AND-OBJ: lr.c.rl t2, (t3)
 # CHECK-ASM: encoding: [0xaf,0x33,0x0e,0x12]
 lr.c.rl ct2, (t3)
-# CHECK-ASM-AND-OBJ: lr.c.aqrl ct3, (t4)
+# CHECK-ASM-AND-OBJ: lr.c.aqrl t3, (t4)
 # CHECK-ASM: encoding: [0x2f,0xbe,0x0e,0x16]
 lr.c.aqrl ct3, (t4)
 
-# CHECK-ASM-AND-OBJ: sc.c t6, ct5, (t4)
+# CHECK-ASM-AND-OBJ: sc.c t6, t5, (t4)
 # CHECK-ASM: encoding: [0xaf,0xbf,0xee,0x19]
 sc.c t6, ct5, (t4)
-# CHECK-ASM-AND-OBJ: sc.c.aq t5, ct4, (t3)
+# CHECK-ASM-AND-OBJ: sc.c.aq t5, t4, (t3)
 # CHECK-ASM: encoding: [0x2f,0x3f,0xde,0x1d]
 sc.c.aq t5, ct4, (t3)
-# CHECK-ASM-AND-OBJ: sc.c.rl t4, ct3, (t2)
+# CHECK-ASM-AND-OBJ: sc.c.rl t4, t3, (t2)
 # CHECK-ASM: encoding: [0xaf,0xbe,0xc3,0x1b]
 sc.c.rl t4, ct3, (t2)
-# CHECK-ASM-AND-OBJ: sc.c.aqrl t3, ct2, (t1)
+# CHECK-ASM-AND-OBJ: sc.c.aqrl t3, t2, (t1)
 # CHECK-ASM: encoding: [0x2f,0x3e,0x73,0x1e]
 sc.c.aqrl t3, ct2, (t1)
 
-# CHECK-ASM-AND-OBJ: amoswap.c ca4, cra, (s0)
+# CHECK-ASM-AND-OBJ: amoswap.c a4, ra, (s0)
 # CHECK-ASM: encoding: [0x2f,0x37,0x14,0x08]
 amoswap.c ca4, cra, (s0)
-# CHECK-ASM-AND-OBJ: amoswap.c.aq ca4, cra, (s0)
+# CHECK-ASM-AND-OBJ: amoswap.c.aq a4, ra, (s0)
 # CHECK-ASM: encoding: [0x2f,0x37,0x14,0x0c]
 amoswap.c.aq ca4, cra, (s0)
-# CHECK-ASM-AND-OBJ: amoswap.c.rl ca4, cra, (s0)
+# CHECK-ASM-AND-OBJ: amoswap.c.rl a4, ra, (s0)
 # CHECK-ASM: encoding: [0x2f,0x37,0x14,0x0a]
 amoswap.c.rl ca4, cra, (s0)
-# CHECK-ASM-AND-OBJ: amoswap.c.aqrl ca4, cra, (s0)
+# CHECK-ASM-AND-OBJ: amoswap.c.aqrl a4, ra, (s0)
 # CHECK-ASM: encoding: [0x2f,0x37,0x14,0x0e]
 amoswap.c.aqrl ca4, cra, (s0)
 
-# CHECK-ASM-AND-OBJ: lr.c.ddc cra, (sp)
+# CHECK-ASM-AND-OBJ: lr.c.ddc ra, (sp)
 # CHECK-ASM: encoding: [0xdb,0x00,0x31,0xfb]
 lr.c.ddc c1, (x2)
 
-# CHECK-ASM-AND-OBJ: sc.c.ddc cra, (sp)
+# CHECK-ASM-AND-OBJ: sc.c.ddc ra, (sp)
 # CHECK-ASM: encoding: [0xdb,0x09,0x11,0xf8]
 sc.c.ddc c1, (x2)
 
-# CHECK-ASM-AND-OBJ: lr.c.cap cra, (csp)
+# CHECK-ASM-AND-OBJ: lr.c.cap ra, (sp)
 # CHECK-ASM: encoding: [0xdb,0x00,0xb1,0xfb]
 lr.c.cap c1, (c2)
 
-# CHECK-ASM-AND-OBJ: sc.c.cap cra, (csp)
+# CHECK-ASM-AND-OBJ: sc.c.cap ra, (sp)
 # CHECK-ASM: encoding: [0xdb,0x0d,0x11,0xf8]
 sc.c.cap c1, (c2)
diff --git a/llvm/test/MC/RISCV/cheri/rv32axcheri-valid.s b/llvm/test/MC/RISCV/cheri/rv32axcheri-valid.s
index ed594ba57bb97..e9de1ce58e0b6 100644
--- a/llvm/test/MC/RISCV/cheri/rv32axcheri-valid.s
+++ b/llvm/test/MC/RISCV/cheri/rv32axcheri-valid.s
@@ -29,22 +29,22 @@ sc.h.ddc x1, (x2)
 # CHECK-ASM: encoding: [0x5b,0x09,0x11,0xf8]
 sc.w.ddc x1, (x2)
 
-# CHECK-ASM-AND-OBJ: lr.b.cap ra, (csp)
+# CHECK-ASM-AND-OBJ: lr.b.cap ra, (sp)
 # CHECK-ASM: encoding: [0xdb,0x00,0x81,0xfb]
 lr.b.cap x1, (c2)
-# CHECK-ASM-AND-OBJ: lr.h.cap ra, (csp)
+# CHECK-ASM-AND-OBJ: lr.h.cap ra, (sp)
 # CHECK-ASM: encoding: [0xdb,0x00,0x91,0xfb]
 lr.h.cap x1, (c2)
-# CHECK-ASM-AND-OBJ: lr.w.cap ra, (csp)
+# CHECK-ASM-AND-OBJ: lr.w.cap ra, (sp)
 # CHECK-ASM: encoding: [0xdb,0x00,0xa1,0xfb]
 lr.w.cap x1, (c2)
 
-# CHECK-ASM-AND-OBJ: sc.b.cap ra, (csp)
+# CHECK-ASM-AND-OBJ: sc.b.cap ra, (sp)
 # CHECK-ASM: encoding: [0x5b,0x0c,0x11,0xf8]
 sc.b.cap x1, (c2)
-# CHECK-ASM-AND-OBJ: sc.h.cap ra, (csp)
+# CHECK-ASM-AND-OBJ: sc.h.cap ra, (sp)
 # CHECK-ASM: encoding: [0xdb,0x0c,0x11,0xf8]
 sc.h.cap x1, (c2)
-# CHECK-ASM-AND-OBJ: sc.w.cap ra, (csp)
+# CHECK-ASM-AND-OBJ: sc.w.cap ra, (sp)
 # CHECK-ASM: encoding: [0x5b,0x0d,0x11,0xf8]
 sc.w.cap x1, (c2)
diff --git a/llvm/test/MC/RISCV/cheri/rv32cxcheri-cap-mode-invalid.s b/llvm/test/MC/RISCV/cheri/rv32cxcheri-cap-mode-invalid.s
index b66b845ad5113..1be13426c1983 100644
--- a/llvm/test/MC/RISCV/cheri/rv32cxcheri-cap-mode-invalid.s
+++ b/llvm/test/MC/RISCV/cheri/rv32cxcheri-cap-mode-invalid.s
@@ -1,11 +1,11 @@
 # RUN: not llvm-mc -triple riscv32 -mattr=+c,+xcheri,+xcheripurecap -filetype=null -riscv-no-aliases -show-encoding < %s 2>&1 \
-# RUN:     | FileCheck %s --check-prefixes=CHECK,CHECK-RV32,CHECK-RV32-C --implicit-check-not="error:"
+# RUN:     | FileCheck %s --check-prefixes=CHECK-RV32,CHECK-RV32-C --implicit-check-not="error:"
 # RUN: not llvm-mc -triple riscv32 -mattr=+xcheri,+xcheripurecap -filetype=null -riscv-no-aliases -show-encoding < %s 2>&1 \
-# RUN:     | FileCheck %s --check-prefixes=CHECK,CHECK-RV32,CHECK-RV32-NO-C --implicit-check-not="error:"
+# RUN:     | FileCheck %s --check-prefixes=CHECK-RV32,CHECK-RV32-NO-C --implicit-check-not="error:"
 # RUN: not llvm-mc -triple riscv64 -mattr=+c,+xcheri,+xcheripurecap -filetype=null -riscv-no-aliases -show-encoding < %s 2>&1\
-# RUN:     | FileCheck %s --check-prefixes=CHECK,CHECK-RV64-C --implicit-check-not="error:"
+# RUN:     | FileCheck %s --check-prefixes=CHECK-RV64-C --implicit-check-not="error:"
 # RUN: not llvm-mc -triple riscv64 -mattr=+xcheri,+xcheripurecap -filetype=null -riscv-no-aliases -show-encoding < %s 2>&1 \
-# RUN:     | FileCheck %s --check-prefixes=CHECK,CHECK-RV64-NO-C --implicit-check-not="error:"
+# RUN:     | FileCheck %s --check-prefixes=CHECK-RV64-NO-C --implicit-check-not="error:"
 
 ## C.JAL is only defined for RV32C:
 c.cjal 2046
@@ -28,21 +28,3 @@ c.csw a5, 1(ca3)
 # CHECK-RV64-C: <stdin>:[[#@LINE-4]]:11: error: immediate must be a multiple of 4 bytes in the range [0, 124]
 # TODO-RV64-NO-C: <stdin>:[[#@LINE-5]]:11: error: instruction requires the following: 'C' (Compressed Instructions){{$}}
 # CHECK-RV64-NO-C: <stdin>:[[#@LINE-6]]:11: error: invalid operand for instruction
-
-c.csw a5, 4(a3)
-# CHECK: <stdin>:[[#@LINE-1]]:13: error: invalid operand for instruction
-c.sw a5, 4(a3)
-# CHECK-RV32-NO-C: <stdin>:[[#@LINE-1]]:1: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores), Not Capability Mode
-# CHECK-RV32-C: <stdin>:[[#@LINE-2]]:12: error: invalid operand for instruction
-# CHECK-RV64-NO-C: <stdin>:[[#@LINE-3]]:1: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores), Not Capability Mode
-# CHECK-RV64-C: <stdin>:[[#@LINE-4]]:12: error: invalid operand for instruction
-
-# Bad operands:
-c.cjalr a1
-# CHECK: <stdin>:[[#@LINE-1]]:9: error: invalid operand for instruction
-c.cjr a1
-# CHECK: <stdin>:[[#@LINE-1]]:7: error: invalid operand for instruction
-c.csc a5, 16(ca3)
-# CHECK: <stdin>:[[#@LINE-1]]:7: error: invalid operand for instruction
-c.csc ca5, 16(a3)
-# CHECK: <stdin>:[[#@LINE-1]]:15: error: invalid operand for instruction
diff --git a/llvm/test/MC/RISCV/cheri/rv32cxcheri-cap-mode-only-valid.s b/llvm/test/MC/RISCV/cheri/rv32cxcheri-cap-mode-only-valid.s
index 2bb91810d672e..f0d78f7d96545 100644
--- a/llvm/test/MC/RISCV/cheri/rv32cxcheri-cap-mode-only-valid.s
+++ b/llvm/test/MC/RISCV/cheri/rv32cxcheri-cap-mode-only-valid.s
@@ -6,28 +6,28 @@
 
 ## Different encoding between RV64 and RV32 (see rv64cxcheri-cap-mode-only-valid.s)
 
-# CHECK-ASM-AND-OBJ: c.clccsp cra, 40(csp)
+# CHECK-ASM-AND-OBJ: c.clccsp ra, 40(sp)
 # CHECK-ASM-SAME: encoding: [0xa2,0x70]
 c.clccsp cra, 40(csp)
-# CHECK-ASM-AND-OBJ: c.clccsp cra, 40(csp)
+# CHECK-ASM-AND-OBJ: c.clccsp ra, 40(sp)
 # CHECK-ASM-SAME: encoding: [0xa2,0x70]
 c.lcsp cra, 40(csp)
-# CHECK-ASM-AND-OBJ: c.csccsp cra, 256(csp)
+# CHECK-ASM-AND-OBJ: c.csccsp ra, 256(sp)
 # CHECK-ASM-SAME: encoding: [0x06,0xe2]
 c.csccsp cra, 256(csp)
-# CHECK-ASM-AND-OBJ: c.csccsp cra, 256(csp)
+# CHECK-ASM-AND-OBJ: c.csccsp ra, 256(sp)
 # CHECK-ASM-SAME: encoding: [0x06,0xe2]
 c.scsp cra, 256(csp)
-# CHECK-ASM-AND-OBJ: c.clc ca2, 16(ca0)
+# CHECK-ASM-AND-OBJ: c.clc a2, 16(a0)
 # CHECK-ASM-SAME: encoding: [0x10,0x69]
 c.clc ca2, 16(ca0)
-# CHECK-ASM-AND-OBJ: c.clc ca2, 16(ca0)
+# CHECK-ASM-AND-OBJ: c.clc a2, 16(a0)
 # CHECK-ASM-SAME: encoding: [0x10,0x69]
 c.lc ca2, 16(ca0)
-# CHECK-ASM-AND-OBJ: c.csc ca5, 128(ca3)
+# CHECK-ASM-AND-OBJ: c.csc a5, 128(a3)
 # CHECK-ASM-SAME: encoding: [0xdc,0xe2]
 c.csc ca5, 128(ca3)
-# CHECK-ASM-AND-OBJ: c.csc ca5, 128(ca3)
+# CHECK-ASM-AND-OBJ: c.csc a5, 128(a3)
 # CHECK-ASM-SAME: encoding: [0xdc,0xe2]
 c.sc ca5, 128(ca3)
 
diff --git a/llvm/test/MC/RISCV/cheri/rv32cxcheri-cap-mode-valid.s b/llvm/test/MC/RISCV/cheri/rv32cxcheri-cap-mode-valid.s
index 01187030df72c..65037d1b73ccd 100644
--- a/llvm/test/MC/RISCV/cheri/rv32cxcheri-cap-mode-valid.s
+++ b/llvm/test/MC/RISCV/cheri/rv32cxcheri-cap-mode-valid.s
@@ -9,47 +9,47 @@
 # RUN:     | llvm-objdump --no-print-imm-hex -M no-aliases --mattr=+c,+xcheri,+xcheripurecap -d - \
 # RUN:     | FileCheck --check-prefixes=CHECK-ASM-AND-OBJ %s
 
-# CHECK-ASM-AND-OBJ: c.clwcsp ra, 0(csp)
+# CHECK-ASM-AND-OBJ: c.clwcsp ra, 0(sp)
 # CHECK-ASM-SAME: encoding: [0x82,0x40]
 c.clwcsp ra, 0(csp)
-# CHECK-ASM-AND-OBJ: c.clwcsp ra, 0(csp)
+# CHECK-ASM-AND-OBJ: c.clwcsp ra, 0(sp)
 # CHECK-ASM-SAME: encoding: [0x82,0x40]
 c.lwsp ra, 0(csp)
-# CHECK-ASM-AND-OBJ: c.cswcsp ra, 252(csp)
+# CHECK-ASM-AND-OBJ: c.cswcsp ra, 252(sp)
 # CHECK-ASM-SAME: encoding: [0x86,0xdf]
 c.cswcsp ra, 252(csp)
-# CHECK-ASM-AND-OBJ: c.cswcsp ra, 252(csp)
+# CHECK-ASM-AND-OBJ: c.cswcsp ra, 252(sp)
 # CHECK-ASM-SAME: encoding: [0x86,0xdf]
 c.swsp ra, 252(csp)
-# CHECK-ASM-AND-OBJ: c.clw a2, 0(ca0)
+# CHECK-ASM-AND-OBJ: c.clw a2, 0(a0)
 # CHECK-ASM-SAME: encoding: [0x10,0x41]
 c.clw a2, 0(ca0)
-# CHECK-ASM-AND-OBJ: c.clw a2, 0(ca0)
+# CHECK-ASM-AND-OBJ: c.clw a2, 0(a0)
 # CHECK-ASM-SAME: encoding: [0x10,0x41]
 c.lw a2, 0(ca0)
-# CHECK-ASM-AND-OBJ: c.csw a5, 124(ca3)
+# CHECK-ASM-AND-OBJ: c.csw a5, 124(a3)
 # CHECK-ASM-SAME: encoding: [0xfc,0xde]
 c.csw a5, 124(ca3)
-# CHECK-ASM-AND-OBJ: c.csw a5, 124(ca3)
+# CHECK-ASM-AND-OBJ: c.csw a5, 124(a3)
 # CHECK-ASM-SAME: encoding: [0xfc,0xde]
 c.sw a5, 124(ca3)
 
-# CHECK-ASM-AND-OBJ: c.cjr ca7
+# CHECK-ASM-AND-OBJ: c.cjr a7
 # CHECK-ASM-SAME: encoding: [0x82,0x88]
 c.cjr ca7
-# CHECK-ASM-AND-OBJ: c.cjalr ca1
+# CHECK-ASM-AND-OBJ: c.cjalr a1
 # CHECK-ASM-SAME: encoding: [0x82,0x95]
 c.cjalr ca1
 
-# CHECK-ASM-AND-OBJ: c.cincoffset16csp csp, -512
+# CHECK-ASM-AND-OBJ: c.cincoffset16csp sp, -512
 # CHECK-ASM-SAME: encoding: [0x01,0x71]
 c.cincoffset16csp csp, -512
-# CHECK-ASM-AND-OBJ: c.cincoffset16csp csp, 496
+# CHECK-ASM-AND-OBJ: c.cincoffset16csp sp, 496
 # CHECK-ASM-SAME: encoding: [0x7d,0x61]
 c.cincoffset16csp csp, 496
-# CHECK-ASM-AND-OBJ: c.cincoffset4cspn ca3, csp, 1020
+# CHECK-ASM-AND-OBJ: c.cincoffset4cspn a3, sp, 1020
 # CHECK-ASM-SAME: encoding: [0xf4,0x1f]
 c.cincoffset4cspn ca3, csp, 1020
-# CHECK-ASM-AND-OBJ: c.cincoffset4cspn ca3, csp, 4
+# CHECK-ASM-AND-OBJ: c.cincoffset4cspn a3, sp, 4
 # CHECK-ASM-SAME: encoding: [0x54,0x00]
 c.cincoffset4cspn ca3, csp, 4
diff --git a/llvm/test/MC/RISCV/cheri/rv32fdcxcheri-cap-mode-only-valid.s b/llvm/test/MC/RISCV/cheri/rv32fdcxcheri-cap-mode-only-valid.s
index 572de2f566b6f..389d9ea7f85b7 100644
--- a/llvm/test/MC/RISCV/cheri/rv32fdcxcheri-cap-mode-only-valid.s
+++ b/llvm/test/MC/RISCV/cheri/rv32fdcxcheri-cap-mode-only-valid.s
@@ -6,28 +6,28 @@
 
 ## Floating-point store is only supported in capmode for RV32
 
-# CHECK-ASM-AND-OBJ: c.cfsd fa0, 40(ca0)
+# CHECK-ASM-AND-OBJ: c.cfsd fa0, 40(a0)
 # CHECK-ASM-SAME: encoding: [0x08,0xb5]
 c.cfsd fa0, 40(ca0)
-# CHECK-ASM-AND-OBJ: c.cfsd fa0, 40(ca0)
+# CHECK-ASM-AND-OBJ: c.cfsd fa0, 40(a0)
 # CHECK-ASM-SAME: encoding: [0x08,0xb5]
 c.fsd fa0, 40(ca0)
-# CHECK-ASM-AND-OBJ: c.cfld fa0, 40(ca0)
+# CHECK-ASM-AND-OBJ: c.cfld fa0, 40(a0)
 # CHECK-ASM-SAME: encoding: [0x08,0x35]
 c.cfld fa0, 40(ca0)
-# CHECK-ASM-AND-OBJ: c.cfld fa0, 40(ca0)
+# CHECK-ASM-AND-OBJ: c.cfld fa0, 40(a0)
 # CHECK-ASM-SAME: encoding: [0x08,0x35]
 c.fld fa0, 40(ca0)
 
-# CHECK-ASM-AND-OBJ: c.cfsdcsp ft1, 40(csp)
+# CHECK-ASM-AND-OBJ: c.cfsdcsp ft1, 40(sp)
 # CHECK-ASM-SAME: encoding: [0x06,0xb4]
 c.cfsdcsp ft1, 40(csp)
-# CHECK-ASM-AND-OBJ: c.cfsdcsp ft1, 40(csp)
+# CHECK-ASM-AND-OBJ: c.cfsdcsp ft1, 40(sp)
 # CHECK-ASM-SAME: encoding: [0x06,0xb4]
 c.fsdsp ft1, 40(csp)
-# CHECK-ASM-AND-OBJ: c.cfldcsp ft1, 40(csp)
+# CHECK-ASM-AND-OBJ: c.cfldcsp ft1, 40(sp)
 # CHECK-ASM-SAME: encoding: [0xa2,0x30]
 c.cfldcsp ft1, 40(csp)
-# CHECK-ASM-AND-OBJ: c.cfldcsp ft1, 40(csp)
+# CHECK-ASM-AND-OBJ: c.cfldcsp ft1, 40(sp)
 # CHECK-ASM-SAME: encoding: [0xa2,0x30]
 c.fldsp ft1, 40(csp)
diff --git a/llvm/test/MC/RISCV/cheri/rv32fdxcheri-cap-mode-valid.s b/llvm/test/MC/RISCV/cheri/rv32fdxcheri-cap-mode-valid.s
index 72b02b1096fce..a6873887b1355 100644
--- a/llvm/test/MC/RISCV/cheri/rv32fdxcheri-cap-mode-valid.s
+++ b/llvm/test/MC/RISCV/cheri/rv32fdxcheri-cap-mode-valid.s
@@ -10,54 +10,54 @@
 # RUN:     | FileCheck -check-prefixes=CHECK-ASM-AND-OBJ %s
 
 
-# CHECK-ASM-AND-OBJ: cfsd fa0, 40(ca0)
+# CHECK-ASM-AND-OBJ: cfsd fa0, 40(a0)
 # CHECK-ASM-SAME: encoding: [0x27,0x34,0xa5,0x02]
 cfsd fa0, 40(ca0)
-# CHECK-ASM-AND-OBJ: cfsd fa0, 40(ca0)
+# CHECK-ASM-AND-OBJ: cfsd fa0, 40(a0)
 # CHECK-ASM-SAME: encoding: [0x27,0x34,0xa5,0x02]
 fsd fa0, 40(ca0)
-# CHECK-ASM-AND-OBJ: cfld fa0, 40(ca0)
+# CHECK-ASM-AND-OBJ: cfld fa0, 40(a0)
 # CHECK-ASM-SAME: encoding: [0x07,0x35,0x85,0x02]
 cfld fa0, 40(ca0)
-# CHECK-ASM-AND-OBJ: cfld fa0, 40(ca0)
+# CHECK-ASM-AND-OBJ: cfld fa0, 40(a0)
 # CHECK-ASM-SAME: encoding: [0x07,0x35,0x85,0x02]
 cfld fa0, 40(ca0)
 
-# CHECK-ASM-AND-OBJ: cfsw ft1, 40(ca0)
+# CHECK-ASM-AND-OBJ: cfsw ft1, 40(a0)
 # CHECK-ASM-SAME: encoding: [0x27,0x24,0x15,0x02]
 cfsw ft1, 40(ca0)
-# CHECK-ASM-AND-OBJ: cfsw ft1, 40(ca0)
+# CHECK-ASM-AND-OBJ: cfsw ft1, 40(a0)
 # CHECK-ASM-SAME: encoding: [0x27,0x24,0x15,0x02]
 fsw ft1, 40(ca0)
-# CHECK-ASM-AND-OBJ: cflw ft1, 40(ca0)
+# CHECK-ASM-AND-OBJ: cflw ft1, 40(a0)
 # CHECK-ASM-SAME: encoding: [0x87,0x20,0x85,0x02]
 cflw ft1, 40(ca0)
-# CHECK-ASM-AND-OBJ: cflw ft1, 40(ca0)
+# CHECK-ASM-AND-OBJ: cflw ft1, 40(a0)
 # CHECK-ASM-SAME: encoding: [0x87,0x20,0x85,0x02]
 flw ft1, 40(ca0)
 
-# CHECK-ASM-AND-OBJ: cfsd fa0, 0(ca0)
+# CHECK-ASM-AND-OBJ: cfsd fa0, 0(a0)
 # CHECK-ASM-SAME: encoding: [0x27,0x30,0xa5,0x00]
 cfsd fa0, (ca0)
-# CHECK-ASM-AND-OBJ: cfsd fa0, 0(ca0)
+# CHECK-ASM-AND-OBJ: cfsd fa0, 0(a0)
 # CHECK-ASM-SAME: encoding: [0x27,0x30,0xa5,0x00]
 fsd fa0, (ca0)
-# CHECK-ASM-AND-OBJ: cfld fa0, 0(ca0)
+# CHECK-ASM-AND-OBJ: cfld fa0, 0(a0)
 # CHECK-ASM-SAME: encoding: [0x07,0x35,0x05,0x00]
 cfld fa0, (ca0)
-# CHECK-ASM-AND-OBJ: cfld fa0, 0(ca0)
+# CHECK-ASM-AND-OBJ: cfld fa0, 0(a0)
 # CHECK-ASM-SAME: encoding: [0x07,0x35,0x05,0x00]
 fld fa0, (ca0)
 
-# CHECK-ASM-AND-OBJ: cfsw ft1, 0(ca0)
+# CHECK-ASM-AND-OBJ: cfsw ft1, 0(a0)
 # CHECK-ASM-SAME: encoding: [0x27,0x20,0x15,0x00]
 cfsw ft1, (ca0)
-# CHECK-ASM-AND-OBJ: cfsw ft1, 0(ca0)
+# CHECK-ASM-AND-OBJ: cfsw ft1, 0(a0)
 # CHECK-ASM-SAME: encoding: [0x27,0x20,0x15,0x00]
 fsw ft1, (ca0)
-# CHECK-ASM-AND-OBJ: cflw ft1, 0(ca0)
+# CHECK-ASM-AND-OBJ: cflw ft1, 0(a0)
 # CHECK-ASM-SAME: encoding: [0x87,0x20,0x05,0x00]
 cflw ft1, (ca0)
-# CHECK-ASM-AND-OBJ: cflw ft1, 0(ca0)
+# CHECK-ASM-AND-OBJ: cflw ft1, 0(a0)
 # CHECK-ASM-SAME: encoding: [0x87,0x20,0x05,0x00]
 flw ft1, (ca0)
diff --git a/llvm/test/MC/RISCV/cheri/rv32xcheri-cap-mode-only-valid.s b/llvm/test/MC/RISCV/cheri/rv32xcheri-cap-mode-only-valid.s
index e2912723d73d0..451513c6a537e 100644
--- a/llvm/test/MC/RISCV/cheri/rv32xcheri-cap-mode-only-valid.s
+++ b/llvm/test/MC/RISCV/cheri/rv32xcheri-cap-mode-only-valid.s
@@ -14,17 +14,17 @@
 
 # Capability load/store uses different encodings for RV32 vs RV64
 
-# CHECK-ASM-AND-OBJ: clc ca2, 17(ca0)
+# CHECK-ASM-AND-OBJ: clc a2, 17(a0)
 # CHECK-ASM-SAME: encoding: [0x03,0x36,0x15,0x01]
 clc ca2, 17(ca0)
-# CHECK-ASM-AND-OBJ: csc ca5, 25(ca3)
+# CHECK-ASM-AND-OBJ: csc a5, 25(a3)
 # CHECK-ASM-SAME: encoding: [0xa3,0xbc,0xf6,0x00]
 csc ca5, 25(ca3)
 
 
-# CHECK-ASM-AND-OBJ: clc ca2, 0(ca0)
+# CHECK-ASM-AND-OBJ: clc a2, 0(a0)
 # CHECK-ASM-SAME: encoding: [0x03,0x36,0x05,0x00]
 clc ca2, (ca0)
-# CHECK-ASM-AND-OBJ: csc ca5, 0(ca3)
+# CHECK-ASM-AND-OBJ: csc a5, 0(a3)
 # CHECK-ASM-SAME: encoding: [0x23,0xb0,0xf6,0x00]
 csc ca5, (ca3)
diff --git a/llvm/test/MC/RISCV/cheri/rv32xcheri-cap-mode-valid.s b/llvm/test/MC/RISCV/cheri/rv32xcheri-cap-mode-valid.s
index 745f724bdd5b9..f29f92105e513 100644
--- a/llvm/test/MC/RISCV/cheri/rv32xcheri-cap-mode-valid.s
+++ b/llvm/test/MC/RISCV/cheri/rv32xcheri-cap-mode-valid.s
@@ -22,60 +22,60 @@
 # RUN:     | llvm-objdump --no-print-imm-hex -M no-aliases --mattr=+xcheri,+xcheripurecap -d - \
 # RUN:     | FileCheck --check-prefixes=CHECK-ASM-AND-OBJ %s
 
-# CHECK-ASM-AND-OBJ:  clb a2, 17(ca0)
+# CHECK-ASM-AND-OBJ:  clb a2, 17(a0)
 # CHECK-ASM-SAME: encoding: [0x03,0x06,0x15,0x01]
 clb a2, 17(ca0)
-# CHECK-ASM-AND-OBJ: csb a5, 25(ca3)
+# CHECK-ASM-AND-OBJ: csb a5, 25(a3)
 # CHECK-ASM-SAME: encoding: [0xa3,0x8c,0xf6,0x00]
 csb a5, 25(ca3)
 
-# CHECK-ASM-AND-OBJ: clh a2, 17(ca0)
+# CHECK-ASM-AND-OBJ: clh a2, 17(a0)
 # CHECK-ASM-SAME: encoding: [0x03,0x16,0x15,0x01]
 clh a2, 17(ca0)
-# CHECK-ASM-AND-OBJ: csh a5, 25(ca3)
+# CHECK-ASM-AND-OBJ: csh a5, 25(a3)
 # CHECK-ASM-SAME: encoding: [0xa3,0x9c,0xf6,0x00]
 csh a5, 25(ca3)
 
-# CHECK-ASM-AND-OBJ: clw ra, 17(csp)
+# CHECK-ASM-AND-OBJ: clw ra, 17(sp)
 # CHECK-ASM-SAME: encoding: [0x83,0x20,0x11,0x01]
 clw ra, 17(csp)
-# CHECK-ASM-AND-OBJ: csw ra, 25(csp)
+# CHECK-ASM-AND-OBJ: csw ra, 25(sp)
 # CHECK-ASM-SAME: encoding: [0xa3,0x2c,0x11,0x00]
 csw ra, 25(csp)
 
-# CHECK-ASM-AND-OBJ: clbu ra, 17(csp)
+# CHECK-ASM-AND-OBJ: clbu ra, 17(sp)
 # CHECK-ASM-SAME: encoding: [0x83,0x40,0x11,0x01]
 clbu ra, 17(csp)
 
-# CHECK-ASM-AND-OBJ: clhu ra, 17(csp)
+# CHECK-ASM-AND-OBJ: clhu ra, 17(sp)
 # CHECK-ASM-SAME: encoding: [0x83,0x50,0x11,0x01]
 clhu ra, 17(csp)
 
-# CHECK-ASM-AND-OBJ:  clb a2, 0(ca0)
+# CHECK-ASM-AND-OBJ:  clb a2, 0(a0)
 # CHECK-ASM-SAME: encoding: [0x03,0x06,0x05,0x00]
 clb a2, (ca0)
-# CHECK-ASM-AND-OBJ: csb a5, 0(ca3)
+# CHECK-ASM-AND-OBJ: csb a5, 0(a3)
 # CHECK-ASM-SAME: encoding: [0x23,0x80,0xf6,0x00]
 csb a5, (ca3)
 
-# CHECK-ASM-AND-OBJ: clh a2, 0(ca0)
+# CHECK-ASM-AND-OBJ: clh a2, 0(a0)
 # CHECK-ASM-SAME: encoding: [0x03,0x16,0x05,0x00]
 clh a2, (ca0)
-# CHECK-ASM-AND-OBJ: csh a5, 0(ca3)
+# CHECK-ASM-AND-OBJ: csh a5, 0(a3)
 # CHECK-ASM-SAME: encoding: [0x23,0x90,0xf6,0x00]
 csh a5, (ca3)
 
-# CHECK-ASM-AND-OBJ: clw ra, 0(csp)
+# CHECK-ASM-AND-OBJ: clw ra, 0(sp)
 # CHECK-ASM-SAME: encoding: [0x83,0x20,0x01,0x00]
 clw ra, (csp)
-# CHECK-ASM-AND-OBJ: csw ra, 0(csp)
+# CHECK-ASM-AND-OBJ: csw ra, 0(sp)
 # CHECK-ASM-SAME: encoding: [0x23,0x20,0x11,0x00]
 csw ra, (csp)
 
-# CHECK-ASM-AND-OBJ: clbu ra, 0(csp)
+# CHECK-ASM-AND-OBJ: clbu ra, 0(sp)
 # CHECK-ASM-SAME: encoding: [0x83,0x40,0x01,0x00]
 clbu ra, (csp)
 
-# CHECK-ASM-AND-OBJ: clhu ra, 0(csp)
+# CHECK-ASM-AND-OBJ: clhu ra, 0(sp)
 # CHECK-ASM-SAME: encoding: [0x83,0x50,0x01,0x00]
 clhu ra, (csp)
diff --git a/llvm/test/MC/RISCV/cheri/rv32xcheri-only-valid.s b/llvm/test/MC/RISCV/cheri/rv32xcheri-only-valid.s
index ce884be00e0ff..c4ea5d5617456 100644
--- a/llvm/test/MC/RISCV/cheri/rv32xcheri-only-valid.s
+++ b/llvm/test/MC/RISCV/cheri/rv32xcheri-only-valid.s
@@ -4,26 +4,26 @@
 # RUN:     | llvm-objdump --no-print-imm-hex -M no-aliases --mattr=+xcheri -d - \
 # RUN:     | FileCheck -check-prefix=CHECK-INST %s
 
-# CHECK-INST: lc cra, 3(sp)
+# CHECK-INST: lc ra, 3(sp)
 # CHECK: encoding: [0x83,0x30,0x31,0x00]
 lc c1, 3(x2)
 
-# CHECK-INST: sc cra, 3(sp)
+# CHECK-INST: sc ra, 3(sp)
 # CHECK: encoding: [0xa3,0x31,0x11,0x00]
 sc c1, 3(x2)
 
-# CHECK-INST: lc.ddc cra, (sp)
+# CHECK-INST: lc.ddc ra, (sp)
 # CHECK: encoding: [0xdb,0x00,0x31,0xfa]
 lc.ddc c1, (x2)
 
-# CHECK-INST: sc.ddc cra, (sp)
+# CHECK-INST: sc.ddc ra, (sp)
 # CHECK: encoding: [0xdb,0x01,0x11,0xf8]
 sc.ddc c1, (x2)
 
-# CHECK-INST: lc.cap cra, (csp)
+# CHECK-INST: lc.cap ra, (sp)
 # CHECK: encoding: [0xdb,0x00,0xb1,0xfa]
 lc.cap c1, (c2)
 
-# CHECK-INST: sc.cap cra, (csp)
+# CHECK-INST: sc.cap ra, (sp)
 # CHECK: encoding: [0xdb,0x05,0x11,0xf8]
 sc.cap c1, (c2)
diff --git a/llvm/test/MC/RISCV/cheri/rv32xcheri-valid.s b/llvm/test/MC/RISCV/cheri/rv32xcheri-valid.s
index 49e53f03fb36e..57fcffd37f969 100644
--- a/llvm/test/MC/RISCV/cheri/rv32xcheri-valid.s
+++ b/llvm/test/MC/RISCV/cheri/rv32xcheri-valid.s
@@ -9,115 +9,115 @@
 # RUN:     | llvm-objdump --no-print-imm-hex -M no-aliases --mattr=+xcheri -d - \
 # RUN:     | FileCheck -check-prefix=CHECK-INST %s
 
-# CHECK-INST: cgetperm ra, csp
+# CHECK-INST: cgetperm ra, sp
 # CHECK: encoding: [0xdb,0x00,0x01,0xfe]
 cgetperm x1, c2
-# CHECK-INST: cgettype ra, csp
+# CHECK-INST: cgettype ra, sp
 # CHECK: encoding: [0xdb,0x00,0x11,0xfe]
 cgettype x1, c2
-# CHECK-INST: cgetbase ra, csp
+# CHECK-INST: cgetbase ra, sp
 # CHECK: encoding: [0xdb,0x00,0x21,0xfe]
 cgetbase x1, c2
-# CHECK-INST: cgetlen ra, csp
+# CHECK-INST: cgetlen ra, sp
 # CHECK: encoding: [0xdb,0x00,0x31,0xfe]
 cgetlen x1, c2
-# CHECK-INST: cgettag ra, csp
+# CHECK-INST: cgettag ra, sp
 # CHECK: encoding: [0xdb,0x00,0x41,0xfe]
 cgettag x1, c2
-# CHECK-INST: cgetsealed ra, csp
+# CHECK-INST: cgetsealed ra, sp
 # CHECK: encoding: [0xdb,0x00,0x51,0xfe]
 cgetsealed x1, c2
-# CHECK-INST: cgetoffset ra, csp
+# CHECK-INST: cgetoffset ra, sp
 # CHECK: encoding: [0xdb,0x00,0x61,0xfe]
 cgetoffset x1, c2
-# CHECK-INST: cgetflags ra, csp
+# CHECK-INST: cgetflags ra, sp
 # CHECK: encoding: [0xdb,0x00,0x71,0xfe]
 cgetflags x1, c2
 # CHECK-INST: addi ra, sp, 0
 # CHECK: encoding: [0x93,0x00,0x01,0x00]
 cgetaddr x1, c2
-# CHECK-INST: cgethigh ra, csp
+# CHECK-INST: cgethigh ra, sp
 # CHECK: encoding: [0xdb,0x00,0x71,0xff]
 cgethigh x1, c2
 
-# CHECK-INST: cseal cra, csp, cgp
+# CHECK-INST: cseal ra, sp, gp
 # CHECK: encoding: [0xdb,0x00,0x31,0x16]
 cseal c1, c2, c3
-# CHECK-INST: cunseal cra, csp, cgp
+# CHECK-INST: cunseal ra, sp, gp
 # CHECK: encoding: [0xdb,0x00,0x31,0x18]
 cunseal c1, c2, c3
-# CHECK-INST: candperm cra, csp, gp
+# CHECK-INST: candperm ra, sp, gp
 # CHECK: encoding: [0xdb,0x00,0x31,0x1a]
 candperm c1, c2, x3
-# CHECK-INST: csetflags cra, csp, gp
+# CHECK-INST: csetflags ra, sp, gp
 # CHECK: encoding: [0xdb,0x00,0x31,0x1c]
 csetflags c1, c2, x3
-# CHECK-INST: csetoffset cra, csp, gp
+# CHECK-INST: csetoffset ra, sp, gp
 # CHECK: encoding: [0xdb,0x00,0x31,0x1e]
 csetoffset c1, c2, x3
-# CHECK-INST: csetaddr cra, csp, gp
+# CHECK-INST: csetaddr ra, sp, gp
 # CHECK: encoding: [0xdb,0x00,0x31,0x20]
 csetaddr c1, c2, x3
-# CHECK-INST: csethigh cra, csp, gp
+# CHECK-INST: csethigh ra, sp, gp
 # CHECK: encoding: [0xdb,0x00,0x31,0x2c]
 csethigh c1, c2, x3
-# CHECK-INST: cincoffset cra, csp, gp
+# CHECK-INST: cincoffset ra, sp, gp
 # CHECK: encoding: [0xdb,0x00,0x31,0x22]
 cincoffset c1, c2, x3
-# CHECK-INST: cincoffset cra, csp, -173
+# CHECK-INST: cincoffset ra, sp, -173
 # CHECK: encoding: [0xdb,0x10,0x31,0xf5]
 cincoffset c1, c2, -173
-# CHECK-INST: cincoffset cra, csp, -173
+# CHECK-INST: cincoffset ra, sp, -173
 # CHECK: encoding: [0xdb,0x10,0x31,0xf5]
 cincoffsetimm c1, c2, -173
-# CHECK-INST: csetbounds cra, csp, gp
+# CHECK-INST: csetbounds ra, sp, gp
 # CHECK: encoding: [0xdb,0x00,0x31,0x10]
 csetbounds c1, c2, x3
-# CHECK-INST: csetboundsexact cra, csp, gp
+# CHECK-INST: csetboundsexact ra, sp, gp
 # CHECK: encoding: [0xdb,0x00,0x31,0x12]
 csetboundsexact c1, c2, x3
-# CHECK-INST: csetbounds cra, csp, 3029
+# CHECK-INST: csetbounds ra, sp, 3029
 # CHECK: encoding: [0xdb,0x20,0x51,0xbd]
 csetbounds c1, c2, 0xbd5
-# CHECK-INST: csetbounds cra, csp, 3029
+# CHECK-INST: csetbounds ra, sp, 3029
 # CHECK: encoding: [0xdb,0x20,0x51,0xbd]
 csetboundsimm c1, c2, 0xbd5
-# CHECK-INST: ccleartag cra, csp
+# CHECK-INST: ccleartag ra, sp
 # CHECK: encoding: [0xdb,0x00,0xb1,0xfe]
 ccleartag c1, c2
-# CHECK-INST: cbuildcap cra, csp, cgp
+# CHECK-INST: cbuildcap ra, sp, gp
 # CHECK: encoding: [0xdb,0x00,0x31,0x3a]
 cbuildcap c1, c2, c3
-# CHECK-INST: cbuildcap cra, ddc, cgp
+# CHECK-INST: cbuildcap ra, ddc, gp
 # CHECK: encoding: [0xdb,0x00,0x30,0x3a]
 cbuildcap c1, ddc, c3
-# CHECK-INST: ccopytype cra, csp, cgp
+# CHECK-INST: ccopytype ra, sp, gp
 # CHECK: encoding: [0xdb,0x00,0x31,0x3c]
 ccopytype c1, c2, c3
-# CHECK-INST: ccseal cra, csp, cgp
+# CHECK-INST: ccseal ra, sp, gp
 # CHECK: encoding: [0xdb,0x00,0x31,0x3e]
 ccseal c1, c2, c3
-# CHECK-INST: csealentry cra, csp
+# CHECK-INST: csealentry ra, sp
 # CHECK: encoding: [0xdb,0x00,0x11,0xff]
 csealentry c1, c2
 
 # CHECK-INST: sub ra, sp, gp
 # CHECK: encoding: [0xb3,0x00,0x31,0x40]
 csub x1, c2, c3
-# CHECK-INST: cmove cra, csp
+# CHECK-INST: cmove ra, sp
 # CHECK: encoding: [0xdb,0x00,0xa1,0xfe]
 cmove c1, c2
 
-# CHECK-INST: jalr.cap cra, csp
+# CHECK-INST: jalr.cap ra, sp
 # CHECK: encoding: [0xdb,0x00,0xc1,0xfe]
 jalr.cap c1, c2
-# CHECK-INST: jalr.cap cra, csp
+# CHECK-INST: jalr.cap ra, sp
 # CHECK: encoding: [0xdb,0x00,0xc1,0xfe]
 jalr.cap c2
-# CHECK-INST: jalr.cap cnull, cra
+# CHECK-INST: jalr.cap zero, ra
 # CHECK: encoding: [0x5b,0x80,0xc0,0xfe]
 jr.cap c1
-# CHECK-INST: jalr.cap cnull, cra
+# CHECK-INST: jalr.cap zero, ra
 # CHECK: encoding: [0x5b,0x80,0xc0,0xfe]
 ret.cap
 # CHECK-INST: jalr.pcc ra, sp
@@ -132,34 +132,34 @@ jr.pcc x1
 # CHECK-INST: jalr.pcc zero, ra
 # CHECK: encoding: [0x5b,0x80,0x40,0xff]
 ret.pcc
-# CHECK-INST: cinvoke cra, csp
+# CHECK-INST: cinvoke ra, sp
 # CHECK: encoding: [0xdb,0x80,0x20,0xfc]
 cinvoke c1, c2
 
-# CHECK-INST: ctestsubset ra, csp, cgp
+# CHECK-INST: ctestsubset ra, sp, gp
 # CHECK: encoding: [0xdb,0x00,0x31,0x40]
 ctestsubset x1, c2, c3
-# CHECK-INST: ctestsubset ra, ddc, cgp
+# CHECK-INST: ctestsubset ra, ddc, gp
 # CHECK: encoding: [0xdb,0x00,0x30,0x40]
 ctestsubset x1, ddc, c3
 
-# CHECK-INST: csetequalexact ra, csp, cgp
+# CHECK-INST: csetequalexact ra, sp, gp
 # CHECK: encoding: [0xdb,0x00,0x31,0x42]
 csetequalexact x1, c2, c3
-# CHECK-INST: csetequalexact ra, csp, cgp
+# CHECK-INST: csetequalexact ra, sp, gp
 # CHECK: encoding: [0xdb,0x00,0x31,0x42]
 cseqx x1, c2, c3
 
-# CHECK-INST: cspecialrw cra, uscratchc, csp
+# CHECK-INST: cspecialrw ra, uscratchc, sp
 # CHECK: encoding: [0xdb,0x00,0x61,0x02]
 cspecialrw c1, uscratchc, c2
-# CHECK-INST: cspecialrw cra, uscratchc, csp
+# CHECK-INST: cspecialrw ra, uscratchc, sp
 # CHECK: encoding: [0xdb,0x00,0x61,0x02]
 cspecialrw c1, 0x6, c2
-# CHECK-INST: cspecialrw cra, uscratchc, cnull
+# CHECK-INST: cspecialrw ra, uscratchc, zero
 # CHECK: encoding: [0xdb,0x00,0x60,0x02]
 cspecialr c1, uscratchc
-# CHECK-INST: cspecialrw cnull, uscratchc, csp
+# CHECK-INST: cspecialrw zero, uscratchc, sp
 # CHECK: encoding: [0x5b,0x00,0x61,0x02]
 cspecialw uscratchc, c2
 
@@ -183,7 +183,7 @@ crepresentablealignmentmask x1, x2
 # CHECK: encoding: [0xdb,0x00,0x91,0xfe]
 cram x1, x2
 
-# CHECK-INST: cloadtags ra, (csp)
+# CHECK-INST: cloadtags ra, (sp)
 # CHECK: encoding: [0xdb,0x00,0x21,0xff]
 cloadtags x1, (c2)
 
@@ -213,28 +213,28 @@ sh.ddc x1, (x2)
 # CHECK: encoding: [0x5b,0x01,0x11,0xf8]
 sw.ddc x1, (x2)
 
-# CHECK-INST: lb.cap ra, (csp)
+# CHECK-INST: lb.cap ra, (sp)
 # CHECK: encoding: [0xdb,0x00,0x81,0xfa]
 lb.cap x1, (c2)
-# CHECK-INST: lh.cap ra, (csp)
+# CHECK-INST: lh.cap ra, (sp)
 # CHECK: encoding: [0xdb,0x00,0x91,0xfa]
 lh.cap x1, (c2)
-# CHECK-INST: lw.cap ra, (csp)
+# CHECK-INST: lw.cap ra, (sp)
 # CHECK: encoding: [0xdb,0x00,0xa1,0xfa]
 lw.cap x1, (c2)
-# CHECK-INST: lbu.cap ra, (csp)
+# CHECK-INST: lbu.cap ra, (sp)
 # CHECK: encoding: [0xdb,0x00,0xc1,0xfa]
 lbu.cap x1, (c2)
-# CHECK-INST: lhu.cap ra, (csp)
+# CHECK-INST: lhu.cap ra, (sp)
 # CHECK: encoding: [0xdb,0x00,0xd1,0xfa]
 lhu.cap x1, (c2)
 
-# CHECK-INST: sb.cap ra, (csp)
+# CHECK-INST: sb.cap ra, (sp)
 # CHECK: encoding: [0x5b,0x04,0x11,0xf8]
 sb.cap x1, (c2)
-# CHECK-INST: sh.cap ra, (csp)
+# CHECK-INST: sh.cap ra, (sp)
 # CHECK: encoding: [0xdb,0x04,0x11,0xf8]
 sh.cap x1, (c2)
-# CHECK-INST: sw.cap ra, (csp)
+# CHECK-INST: sw.cap ra, (sp)
 # CHECK: encoding: [0x5b,0x05,0x11,0xf8]
 sw.cap x1, (c2)
diff --git a/llvm/test/MC/RISCV/cheri/rv64axcheri-cap-mode-aliases-valid.s b/llvm/test/MC/RISCV/cheri/rv64axcheri-cap-mode-aliases-valid.s
index 509ce74fb3218..add35a2623452 100644
--- a/llvm/test/MC/RISCV/cheri/rv64axcheri-cap-mode-aliases-valid.s
+++ b/llvm/test/MC/RISCV/cheri/rv64axcheri-cap-mode-aliases-valid.s
@@ -12,178 +12,178 @@
 # The below tests for clr.d, csc.d and camo*.d, using `0(reg)` are actually
 # implemented using a custom parser, but we test them as if they're aliases.
 
-# CHECK-INST: clr.d a1, (ca0)
-# CHECK-ALIAS: clr.d a1, (ca0)
+# CHECK-INST: clr.d a1, (a0)
+# CHECK-ALIAS: clr.d a1, (a0)
 clr.d a1, 0(ca0)
 
-# CHECK-INST: clr.d.aq a1, (ca0)
-# CHECK-ALIAS: clr.d.aq a1, (ca0)
+# CHECK-INST: clr.d.aq a1, (a0)
+# CHECK-ALIAS: clr.d.aq a1, (a0)
 clr.d.aq a1, 0(ca0)
 
-# CHECK-INST: clr.d.rl a1, (ca0)
-# CHECK-ALIAS: clr.d.rl a1, (ca0)
+# CHECK-INST: clr.d.rl a1, (a0)
+# CHECK-ALIAS: clr.d.rl a1, (a0)
 clr.d.rl a1, 0(ca0)
 
-# CHECK-INST: clr.d.aqrl a1, (ca0)
-# CHECK-ALIAS: clr.d.aqrl a1, (ca0)
+# CHECK-INST: clr.d.aqrl a1, (a0)
+# CHECK-ALIAS: clr.d.aqrl a1, (a0)
 clr.d.aqrl a1, 0(ca0)
 
-# CHECK-INST: csc.d a2, a1, (ca0)
-# CHECK-ALIAS: csc.d a2, a1, (ca0)
+# CHECK-INST: csc.d a2, a1, (a0)
+# CHECK-ALIAS: csc.d a2, a1, (a0)
 csc.d a2, a1, 0(ca0)
 
-# CHECK-INST: csc.d.aq a2, a1, (ca0)
-# CHECK-ALIAS: csc.d.aq a2, a1, (ca0)
+# CHECK-INST: csc.d.aq a2, a1, (a0)
+# CHECK-ALIAS: csc.d.aq a2, a1, (a0)
 csc.d.aq a2, a1, 0(ca0)
 
-# CHECK-INST: csc.d.rl a2, a1, (ca0)
-# CHECK-ALIAS: csc.d.rl a2, a1, (ca0)
+# CHECK-INST: csc.d.rl a2, a1, (a0)
+# CHECK-ALIAS: csc.d.rl a2, a1, (a0)
 csc.d.rl a2, a1, 0(ca0)
 
-# CHECK-INST: csc.d.aqrl a2, a1, (ca0)
-# CHECK-ALIAS: csc.d.aqrl a2, a1, (ca0)
+# CHECK-INST: csc.d.aqrl a2, a1, (a0)
+# CHECK-ALIAS: csc.d.aqrl a2, a1, (a0)
 csc.d.aqrl a2, a1, 0(ca0)
 
-# CHECK-INST: camoswap.d a2, a1, (ca0)
-# CHECK-ALIAS: camoswap.d a2, a1, (ca0)
+# CHECK-INST: camoswap.d a2, a1, (a0)
+# CHECK-ALIAS: camoswap.d a2, a1, (a0)
 camoswap.d a2, a1, 0(ca0)
 
-# CHECK-INST: camoswap.d.aq a2, a1, (ca0)
-# CHECK-ALIAS: camoswap.d.aq a2, a1, (ca0)
+# CHECK-INST: camoswap.d.aq a2, a1, (a0)
+# CHECK-ALIAS: camoswap.d.aq a2, a1, (a0)
 camoswap.d.aq a2, a1, 0(ca0)
 
-# CHECK-INST: camoswap.d.rl a2, a1, (ca0)
-# CHECK-ALIAS: camoswap.d.rl a2, a1, (ca0)
+# CHECK-INST: camoswap.d.rl a2, a1, (a0)
+# CHECK-ALIAS: camoswap.d.rl a2, a1, (a0)
 camoswap.d.rl a2, a1, 0(ca0)
 
-# CHECK-INST: camoswap.d.aqrl a2, a1, (ca0)
-# CHECK-ALIAS: camoswap.d.aqrl a2, a1, (ca0)
+# CHECK-INST: camoswap.d.aqrl a2, a1, (a0)
+# CHECK-ALIAS: camoswap.d.aqrl a2, a1, (a0)
 camoswap.d.aqrl a2, a1, 0(ca0)
 
-# CHECK-INST: camoadd.d a2, a1, (ca0)
-# CHECK-ALIAS: camoadd.d a2, a1, (ca0)
+# CHECK-INST: camoadd.d a2, a1, (a0)
+# CHECK-ALIAS: camoadd.d a2, a1, (a0)
 camoadd.d a2, a1, 0(ca0)
 
-# CHECK-INST: camoadd.d.aq a2, a1, (ca0)
-# CHECK-ALIAS: camoadd.d.aq a2, a1, (ca0)
+# CHECK-INST: camoadd.d.aq a2, a1, (a0)
+# CHECK-ALIAS: camoadd.d.aq a2, a1, (a0)
 camoadd.d.aq a2, a1, 0(ca0)
 
-# CHECK-INST: camoadd.d.rl a2, a1, (ca0)
-# CHECK-ALIAS: camoadd.d.rl a2, a1, (ca0)
+# CHECK-INST: camoadd.d.rl a2, a1, (a0)
+# CHECK-ALIAS: camoadd.d.rl a2, a1, (a0)
 camoadd.d.rl a2, a1, 0(ca0)
 
-# CHECK-INST: camoadd.d.aqrl a2, a1, (ca0)
-# CHECK-ALIAS: camoadd.d.aqrl a2, a1, (ca0)
+# CHECK-INST: camoadd.d.aqrl a2, a1, (a0)
+# CHECK-ALIAS: camoadd.d.aqrl a2, a1, (a0)
 camoadd.d.aqrl a2, a1, 0(ca0)
 
-# CHECK-INST: camoxor.d a2, a1, (ca0)
-# CHECK-ALIAS: camoxor.d a2, a1, (ca0)
+# CHECK-INST: camoxor.d a2, a1, (a0)
+# CHECK-ALIAS: camoxor.d a2, a1, (a0)
 camoxor.d a2, a1, 0(ca0)
 
-# CHECK-INST: camoxor.d.aq a2, a1, (ca0)
-# CHECK-ALIAS: camoxor.d.aq a2, a1, (ca0)
+# CHECK-INST: camoxor.d.aq a2, a1, (a0)
+# CHECK-ALIAS: camoxor.d.aq a2, a1, (a0)
 camoxor.d.aq a2, a1, 0(ca0)
 
-# CHECK-INST: camoxor.d.rl a2, a1, (ca0)
-# CHECK-ALIAS: camoxor.d.rl a2, a1, (ca0)
+# CHECK-INST: camoxor.d.rl a2, a1, (a0)
+# CHECK-ALIAS: camoxor.d.rl a2, a1, (a0)
 camoxor.d.rl a2, a1, 0(ca0)
 
-# CHECK-INST: camoxor.d.aqrl a2, a1, (ca0)
-# CHECK-ALIAS: camoxor.d.aqrl a2, a1, (ca0)
+# CHECK-INST: camoxor.d.aqrl a2, a1, (a0)
+# CHECK-ALIAS: camoxor.d.aqrl a2, a1, (a0)
 camoxor.d.aqrl a2, a1, 0(ca0)
 
-# CHECK-INST: camoand.d a2, a1, (ca0)
-# CHECK-ALIAS: camoand.d a2, a1, (ca0)
+# CHECK-INST: camoand.d a2, a1, (a0)
+# CHECK-ALIAS: camoand.d a2, a1, (a0)
 camoand.d a2, a1, 0(ca0)
 
-# CHECK-INST: camoand.d.aq a2, a1, (ca0)
-# CHECK-ALIAS: camoand.d.aq a2, a1, (ca0)
+# CHECK-INST: camoand.d.aq a2, a1, (a0)
+# CHECK-ALIAS: camoand.d.aq a2, a1, (a0)
 camoand.d.aq a2, a1, 0(ca0)
 
-# CHECK-INST: camoand.d.rl a2, a1, (ca0)
-# CHECK-ALIAS: camoand.d.rl a2, a1, (ca0)
+# CHECK-INST: camoand.d.rl a2, a1, (a0)
+# CHECK-ALIAS: camoand.d.rl a2, a1, (a0)
 camoand.d.rl a2, a1, 0(ca0)
 
-# CHECK-INST: camoand.d.aqrl a2, a1, (ca0)
-# CHECK-ALIAS: camoand.d.aqrl a2, a1, (ca0)
+# CHECK-INST: camoand.d.aqrl a2, a1, (a0)
+# CHECK-ALIAS: camoand.d.aqrl a2, a1, (a0)
 camoand.d.aqrl a2, a1, 0(ca0)
 
-# CHECK-INST: camoor.d a2, a1, (ca0)
-# CHECK-ALIAS: camoor.d a2, a1, (ca0)
+# CHECK-INST: camoor.d a2, a1, (a0)
+# CHECK-ALIAS: camoor.d a2, a1, (a0)
 camoor.d a2, a1, 0(ca0)
 
-# CHECK-INST: camoor.d.aq a2, a1, (ca0)
-# CHECK-ALIAS: camoor.d.aq a2, a1, (ca0)
+# CHECK-INST: camoor.d.aq a2, a1, (a0)
+# CHECK-ALIAS: camoor.d.aq a2, a1, (a0)
 camoor.d.aq a2, a1, 0(ca0)
 
-# CHECK-INST: camoor.d.rl a2, a1, (ca0)
-# CHECK-ALIAS: camoor.d.rl a2, a1, (ca0)
+# CHECK-INST: camoor.d.rl a2, a1, (a0)
+# CHECK-ALIAS: camoor.d.rl a2, a1, (a0)
 camoor.d.rl a2, a1, 0(ca0)
 
-# CHECK-INST: camoor.d.aqrl a2, a1, (ca0)
-# CHECK-ALIAS: camoor.d.aqrl a2, a1, (ca0)
+# CHECK-INST: camoor.d.aqrl a2, a1, (a0)
+# CHECK-ALIAS: camoor.d.aqrl a2, a1, (a0)
 camoor.d.aqrl a2, a1, 0(ca0)
 
-# CHECK-INST: camomin.d a2, a1, (ca0)
-# CHECK-ALIAS: camomin.d a2, a1, (ca0)
+# CHECK-INST: camomin.d a2, a1, (a0)
+# CHECK-ALIAS: camomin.d a2, a1, (a0)
 camomin.d a2, a1, 0(ca0)
 
-# CHECK-INST: camomin.d.aq a2, a1, (ca0)
-# CHECK-ALIAS: camomin.d.aq a2, a1, (ca0)
+# CHECK-INST: camomin.d.aq a2, a1, (a0)
+# CHECK-ALIAS: camomin.d.aq a2, a1, (a0)
 camomin.d.aq a2, a1, 0(ca0)
 
-# CHECK-INST: camomin.d.rl a2, a1, (ca0)
-# CHECK-ALIAS: camomin.d.rl a2, a1, (ca0)
+# CHECK-INST: camomin.d.rl a2, a1, (a0)
+# CHECK-ALIAS: camomin.d.rl a2, a1, (a0)
 camomin.d.rl a2, a1, 0(ca0)
 
-# CHECK-INST: camomin.d.aqrl a2, a1, (ca0)
-# CHECK-ALIAS: camomin.d.aqrl a2, a1, (ca0)
+# CHECK-INST: camomin.d.aqrl a2, a1, (a0)
+# CHECK-ALIAS: camomin.d.aqrl a2, a1, (a0)
 camomin.d.aqrl a2, a1, 0(ca0)
 
-# CHECK-INST: camomax.d a2, a1, (ca0)
-# CHECK-ALIAS: camomax.d a2, a1, (ca0)
+# CHECK-INST: camomax.d a2, a1, (a0)
+# CHECK-ALIAS: camomax.d a2, a1, (a0)
 camomax.d a2, a1, 0(ca0)
 
-# CHECK-INST: camomax.d.aq a2, a1, (ca0)
-# CHECK-ALIAS: camomax.d.aq a2, a1, (ca0)
+# CHECK-INST: camomax.d.aq a2, a1, (a0)
+# CHECK-ALIAS: camomax.d.aq a2, a1, (a0)
 camomax.d.aq a2, a1, 0(ca0)
 
-# CHECK-INST: camomax.d.rl a2, a1, (ca0)
-# CHECK-ALIAS: camomax.d.rl a2, a1, (ca0)
+# CHECK-INST: camomax.d.rl a2, a1, (a0)
+# CHECK-ALIAS: camomax.d.rl a2, a1, (a0)
 camomax.d.rl a2, a1, 0(ca0)
 
-# CHECK-INST: camomax.d.aqrl a2, a1, (ca0)
-# CHECK-ALIAS: camomax.d.aqrl a2, a1, (ca0)
+# CHECK-INST: camomax.d.aqrl a2, a1, (a0)
+# CHECK-ALIAS: camomax.d.aqrl a2, a1, (a0)
 camomax.d.aqrl a2, a1, 0(ca0)
 
-# CHECK-INST: camominu.d a2, a1, (ca0)
-# CHECK-ALIAS: camominu.d a2, a1, (ca0)
+# CHECK-INST: camominu.d a2, a1, (a0)
+# CHECK-ALIAS: camominu.d a2, a1, (a0)
 camominu.d a2, a1, 0(ca0)
 
-# CHECK-INST: camominu.d.aq a2, a1, (ca0)
-# CHECK-ALIAS: camominu.d.aq a2, a1, (ca0)
+# CHECK-INST: camominu.d.aq a2, a1, (a0)
+# CHECK-ALIAS: camominu.d.aq a2, a1, (a0)
 camominu.d.aq a2, a1, 0(ca0)
 
-# CHECK-INST: camominu.d.rl a2, a1, (ca0)
-# CHECK-ALIAS: camominu.d.rl a2, a1, (ca0)
+# CHECK-INST: camominu.d.rl a2, a1, (a0)
+# CHECK-ALIAS: camominu.d.rl a2, a1, (a0)
 camominu.d.rl a2, a1, 0(ca0)
 
-# CHECK-INST: camominu.d.aqrl a2, a1, (ca0)
-# CHECK-ALIAS: camominu.d.aqrl a2, a1, (ca0)
+# CHECK-INST: camominu.d.aqrl a2, a1, (a0)
+# CHECK-ALIAS: camominu.d.aqrl a2, a1, (a0)
 camominu.d.aqrl a2, a1, 0(ca0)
 
-# CHECK-INST: camomaxu.d a2, a1, (ca0)
-# CHECK-ALIAS: camomaxu.d a2, a1, (ca0)
+# CHECK-INST: camomaxu.d a2, a1, (a0)
+# CHECK-ALIAS: camomaxu.d a2, a1, (a0)
 camomaxu.d a2, a1, 0(ca0)
 
-# CHECK-INST: camomaxu.d.aq a2, a1, (ca0)
-# CHECK-ALIAS: camomaxu.d.aq a2, a1, (ca0)
+# CHECK-INST: camomaxu.d.aq a2, a1, (a0)
+# CHECK-ALIAS: camomaxu.d.aq a2, a1, (a0)
 camomaxu.d.aq a2, a1, 0(ca0)
 
-# CHECK-INST: camomaxu.d.rl a2, a1, (ca0)
-# CHECK-ALIAS: camomaxu.d.rl a2, a1, (ca0)
+# CHECK-INST: camomaxu.d.rl a2, a1, (a0)
+# CHECK-ALIAS: camomaxu.d.rl a2, a1, (a0)
 camomaxu.d.rl a2, a1, 0(ca0)
 
-# CHECK-INST: camomaxu.d.aqrl a2, a1, (ca0)
-# CHECK-ALIAS: camomaxu.d.aqrl a2, a1, (ca0)
+# CHECK-INST: camomaxu.d.aqrl a2, a1, (a0)
+# CHECK-ALIAS: camomaxu.d.aqrl a2, a1, (a0)
 camomaxu.d.aqrl a2, a1, 0(ca0)
diff --git a/llvm/test/MC/RISCV/cheri/rv64axcheri-cap-mode-valid.s b/llvm/test/MC/RISCV/cheri/rv64axcheri-cap-mode-valid.s
index ebd7badb35b52..d64699c8e100d 100644
--- a/llvm/test/MC/RISCV/cheri/rv64axcheri-cap-mode-valid.s
+++ b/llvm/test/MC/RISCV/cheri/rv64axcheri-cap-mode-valid.s
@@ -13,182 +13,182 @@
 # RUN:     | FileCheck -check-prefixes=CHECK-ASM-AND-OBJ %s
 
 
-# CHECK-ASM-AND-OBJ: clr.d t0, (ct1)
+# CHECK-ASM-AND-OBJ: clr.d t0, (t1)
 # CHECK-ASM: encoding: [0xaf,0x32,0x03,0x10]
 clr.d t0, (ct1)
-# CHECK-ASM-AND-OBJ: clr.d.aq t1, (ct2)
+# CHECK-ASM-AND-OBJ: clr.d.aq t1, (t2)
 # CHECK-ASM: encoding: [0x2f,0xb3,0x03,0x14]
 clr.d.aq t1, (ct2)
-# CHECK-ASM-AND-OBJ: clr.d.rl t2, (ct3)
+# CHECK-ASM-AND-OBJ: clr.d.rl t2, (t3)
 # CHECK-ASM: encoding: [0xaf,0x33,0x0e,0x12]
 clr.d.rl t2, (ct3)
-# CHECK-ASM-AND-OBJ: clr.d.aqrl t3, (ct4)
+# CHECK-ASM-AND-OBJ: clr.d.aqrl t3, (t4)
 # CHECK-ASM: encoding: [0x2f,0xbe,0x0e,0x16]
 clr.d.aqrl t3, (ct4)
 
-# CHECK-ASM-AND-OBJ: clr.c ct0, (ct1)
+# CHECK-ASM-AND-OBJ: clr.c t0, (t1)
 # CHECK-ASM: encoding: [0xaf,0x42,0x03,0x10]
 clr.c ct0, (ct1)
-# CHECK-ASM-AND-OBJ: clr.c.aq ct1, (ct2)
+# CHECK-ASM-AND-OBJ: clr.c.aq t1, (t2)
 # CHECK-ASM: encoding: [0x2f,0xc3,0x03,0x14]
 clr.c.aq ct1, (ct2)
-# CHECK-ASM-AND-OBJ: clr.c.rl ct2, (ct3)
+# CHECK-ASM-AND-OBJ: clr.c.rl t2, (t3)
 # CHECK-ASM: encoding: [0xaf,0x43,0x0e,0x12]
 clr.c.rl ct2, (ct3)
-# CHECK-ASM-AND-OBJ: clr.c.aqrl ct3, (ct4)
+# CHECK-ASM-AND-OBJ: clr.c.aqrl t3, (t4)
 # CHECK-ASM: encoding: [0x2f,0xce,0x0e,0x16]
 clr.c.aqrl ct3, (ct4)
 
-# CHECK-ASM-AND-OBJ: csc.d t6, t5, (ct4)
+# CHECK-ASM-AND-OBJ: csc.d t6, t5, (t4)
 # CHECK-ASM: encoding: [0xaf,0xbf,0xee,0x19]
 csc.d t6, t5, (ct4)
-# CHECK-ASM-AND-OBJ: csc.d.aq t5, t4, (ct3)
+# CHECK-ASM-AND-OBJ: csc.d.aq t5, t4, (t3)
 # CHECK-ASM: encoding: [0x2f,0x3f,0xde,0x1d]
 csc.d.aq t5, t4, (ct3)
-# CHECK-ASM-AND-OBJ: csc.d.rl t4, t3, (ct2)
+# CHECK-ASM-AND-OBJ: csc.d.rl t4, t3, (t2)
 # CHECK-ASM: encoding: [0xaf,0xbe,0xc3,0x1b]
 csc.d.rl t4, t3, (ct2)
-# CHECK-ASM-AND-OBJ: csc.d.aqrl t3, t2, (ct1)
+# CHECK-ASM-AND-OBJ: csc.d.aqrl t3, t2, (t1)
 # CHECK-ASM: encoding: [0x2f,0x3e,0x73,0x1e]
 csc.d.aqrl t3, t2, (ct1)
 
-# CHECK-ASM-AND-OBJ: csc.c t6, ct5, (ct4)
+# CHECK-ASM-AND-OBJ: csc.c t6, t5, (t4)
 # CHECK-ASM: encoding: [0xaf,0xcf,0xee,0x19]
 csc.c t6, ct5, (ct4)
-# CHECK-ASM-AND-OBJ: csc.c.aq t5, ct4, (ct3)
+# CHECK-ASM-AND-OBJ: csc.c.aq t5, t4, (t3)
 # CHECK-ASM: encoding: [0x2f,0x4f,0xde,0x1d]
 csc.c.aq t5, ct4, (ct3)
-# CHECK-ASM-AND-OBJ: csc.c.rl t4, ct3, (ct2)
+# CHECK-ASM-AND-OBJ: csc.c.rl t4, t3, (t2)
 # CHECK-ASM: encoding: [0xaf,0xce,0xc3,0x1b]
 csc.c.rl t4, ct3, (ct2)
-# CHECK-ASM-AND-OBJ: csc.c.aqrl t3, ct2, (ct1)
+# CHECK-ASM-AND-OBJ: csc.c.aqrl t3, t2, (t1)
 # CHECK-ASM: encoding: [0x2f,0x4e,0x73,0x1e]
 csc.c.aqrl t3, ct2, (ct1)
 
-# CHECK-ASM-AND-OBJ: camoswap.d a4, ra, (cs0)
+# CHECK-ASM-AND-OBJ: camoswap.d a4, ra, (s0)
 # CHECK-ASM: encoding: [0x2f,0x37,0x14,0x08]
 camoswap.d a4, ra, (cs0)
-# CHECK-ASM-AND-OBJ: camoadd.d a1, a2, (ca3)
+# CHECK-ASM-AND-OBJ: camoadd.d a1, a2, (a3)
 # CHECK-ASM: encoding: [0xaf,0xb5,0xc6,0x00]
 camoadd.d a1, a2, (ca3)
-# CHECK-ASM-AND-OBJ: camoxor.d a2, a3, (ca4)
+# CHECK-ASM-AND-OBJ: camoxor.d a2, a3, (a4)
 # CHECK-ASM: encoding: [0x2f,0x36,0xd7,0x20]
 camoxor.d a2, a3, (ca4)
-# CHECK-ASM-AND-OBJ: camoand.d a3, a4, (ca5)
+# CHECK-ASM-AND-OBJ: camoand.d a3, a4, (a5)
 # CHECK-ASM: encoding: [0xaf,0xb6,0xe7,0x60]
 camoand.d a3, a4, (ca5)
-# CHECK-ASM-AND-OBJ: camoor.d a4, a5, (ca6)
+# CHECK-ASM-AND-OBJ: camoor.d a4, a5, (a6)
 # CHECK-ASM: encoding: [0x2f,0x37,0xf8,0x40]
 camoor.d a4, a5, (ca6)
-# CHECK-ASM-AND-OBJ: camomin.d a5, a6, (ca7)
+# CHECK-ASM-AND-OBJ: camomin.d a5, a6, (a7)
 # CHECK-ASM: encoding: [0xaf,0xb7,0x08,0x81]
 camomin.d a5, a6, (ca7)
-# CHECK-ASM-AND-OBJ: camomax.d s7, s6, (cs5)
+# CHECK-ASM-AND-OBJ: camomax.d s7, s6, (s5)
 # CHECK-ASM: encoding: [0xaf,0xbb,0x6a,0xa1]
 camomax.d s7, s6, (cs5)
-# CHECK-ASM-AND-OBJ: camominu.d s6, s5, (cs4)
+# CHECK-ASM-AND-OBJ: camominu.d s6, s5, (s4)
 # CHECK-ASM: encoding: [0x2f,0x3b,0x5a,0xc1]
 camominu.d s6, s5, (cs4)
-# CHECK-ASM-AND-OBJ: camomaxu.d s5, s4, (cs3)
+# CHECK-ASM-AND-OBJ: camomaxu.d s5, s4, (s3)
 # CHECK-ASM: encoding: [0xaf,0xba,0x49,0xe1]
 camomaxu.d s5, s4, (cs3)
 
-# CHECK-ASM-AND-OBJ: camoswap.c ca4, cra, (cs0)
+# CHECK-ASM-AND-OBJ: camoswap.c a4, ra, (s0)
 # CHECK-ASM: encoding: [0x2f,0x47,0x14,0x08]
 camoswap.c ca4, cra, (cs0)
 
-# CHECK-ASM-AND-OBJ: camoswap.d.aq a4, ra, (cs0)
+# CHECK-ASM-AND-OBJ: camoswap.d.aq a4, ra, (s0)
 # CHECK-ASM: encoding: [0x2f,0x37,0x14,0x0c]
 camoswap.d.aq a4, ra, (cs0)
-# CHECK-ASM-AND-OBJ: camoadd.d.aq a1, a2, (ca3)
+# CHECK-ASM-AND-OBJ: camoadd.d.aq a1, a2, (a3)
 # CHECK-ASM: encoding: [0xaf,0xb5,0xc6,0x04]
 camoadd.d.aq a1, a2, (ca3)
-# CHECK-ASM-AND-OBJ: camoxor.d.aq a2, a3, (ca4)
+# CHECK-ASM-AND-OBJ: camoxor.d.aq a2, a3, (a4)
 # CHECK-ASM: encoding: [0x2f,0x36,0xd7,0x24]
 camoxor.d.aq a2, a3, (ca4)
-# CHECK-ASM-AND-OBJ: camoand.d.aq a3, a4, (ca5)
+# CHECK-ASM-AND-OBJ: camoand.d.aq a3, a4, (a5)
 # CHECK-ASM: encoding: [0xaf,0xb6,0xe7,0x64]
 camoand.d.aq a3, a4, (ca5)
-# CHECK-ASM-AND-OBJ: camoor.d.aq a4, a5, (ca6)
+# CHECK-ASM-AND-OBJ: camoor.d.aq a4, a5, (a6)
 # CHECK-ASM: encoding: [0x2f,0x37,0xf8,0x44]
 camoor.d.aq a4, a5, (ca6)
-# CHECK-ASM-AND-OBJ: camomin.d.aq a5, a6, (ca7)
+# CHECK-ASM-AND-OBJ: camomin.d.aq a5, a6, (a7)
 # CHECK-ASM: encoding: [0xaf,0xb7,0x08,0x85]
 camomin.d.aq a5, a6, (ca7)
-# CHECK-ASM-AND-OBJ: camomax.d.aq s7, s6, (cs5)
+# CHECK-ASM-AND-OBJ: camomax.d.aq s7, s6, (s5)
 # CHECK-ASM: encoding: [0xaf,0xbb,0x6a,0xa5]
 camomax.d.aq s7, s6, (cs5)
-# CHECK-ASM-AND-OBJ: camominu.d.aq s6, s5, (cs4)
+# CHECK-ASM-AND-OBJ: camominu.d.aq s6, s5, (s4)
 # CHECK-ASM: encoding: [0x2f,0x3b,0x5a,0xc5]
 camominu.d.aq s6, s5, (cs4)
-# CHECK-ASM-AND-OBJ: camomaxu.d.aq s5, s4, (cs3)
+# CHECK-ASM-AND-OBJ: camomaxu.d.aq s5, s4, (s3)
 # CHECK-ASM: encoding: [0xaf,0xba,0x49,0xe5]
 camomaxu.d.aq s5, s4, (cs3)
 
-# CHECK-ASM-AND-OBJ: camoswap.c.aq ca4, cra, (cs0)
+# CHECK-ASM-AND-OBJ: camoswap.c.aq a4, ra, (s0)
 # CHECK-ASM: encoding: [0x2f,0x47,0x14,0x0c]
 camoswap.c.aq ca4, cra, (cs0)
 
-# CHECK-ASM-AND-OBJ: camoswap.d.rl a4, ra, (cs0)
+# CHECK-ASM-AND-OBJ: camoswap.d.rl a4, ra, (s0)
 # CHECK-ASM: encoding: [0x2f,0x37,0x14,0x0a]
 camoswap.d.rl a4, ra, (cs0)
-# CHECK-ASM-AND-OBJ: camoadd.d.rl a1, a2, (ca3)
+# CHECK-ASM-AND-OBJ: camoadd.d.rl a1, a2, (a3)
 # CHECK-ASM: encoding: [0xaf,0xb5,0xc6,0x02]
 camoadd.d.rl a1, a2, (ca3)
-# CHECK-ASM-AND-OBJ: camoxor.d.rl a2, a3, (ca4)
+# CHECK-ASM-AND-OBJ: camoxor.d.rl a2, a3, (a4)
 # CHECK-ASM: encoding: [0x2f,0x36,0xd7,0x22]
 camoxor.d.rl a2, a3, (ca4)
-# CHECK-ASM-AND-OBJ: camoand.d.rl a3, a4, (ca5)
+# CHECK-ASM-AND-OBJ: camoand.d.rl a3, a4, (a5)
 # CHECK-ASM: encoding: [0xaf,0xb6,0xe7,0x62]
 camoand.d.rl a3, a4, (ca5)
-# CHECK-ASM-AND-OBJ: camoor.d.rl a4, a5, (ca6)
+# CHECK-ASM-AND-OBJ: camoor.d.rl a4, a5, (a6)
 # CHECK-ASM: encoding: [0x2f,0x37,0xf8,0x42]
 camoor.d.rl a4, a5, (ca6)
-# CHECK-ASM-AND-OBJ: camomin.d.rl a5, a6, (ca7)
+# CHECK-ASM-AND-OBJ: camomin.d.rl a5, a6, (a7)
 # CHECK-ASM: encoding: [0xaf,0xb7,0x08,0x83]
 camomin.d.rl a5, a6, (ca7)
-# CHECK-ASM-AND-OBJ: camomax.d.rl s7, s6, (cs5)
+# CHECK-ASM-AND-OBJ: camomax.d.rl s7, s6, (s5)
 # CHECK-ASM: encoding: [0xaf,0xbb,0x6a,0xa3]
 camomax.d.rl s7, s6, (cs5)
-# CHECK-ASM-AND-OBJ: camominu.d.rl s6, s5, (cs4)
+# CHECK-ASM-AND-OBJ: camominu.d.rl s6, s5, (s4)
 # CHECK-ASM: encoding: [0x2f,0x3b,0x5a,0xc3]
 camominu.d.rl s6, s5, (cs4)
-# CHECK-ASM-AND-OBJ: camomaxu.d.rl s5, s4, (cs3)
+# CHECK-ASM-AND-OBJ: camomaxu.d.rl s5, s4, (s3)
 # CHECK-ASM: encoding: [0xaf,0xba,0x49,0xe3]
 camomaxu.d.rl s5, s4, (cs3)
 
-# CHECK-ASM-AND-OBJ: camoswap.c.rl ca4, cra, (cs0)
+# CHECK-ASM-AND-OBJ: camoswap.c.rl a4, ra, (s0)
 # CHECK-ASM: encoding: [0x2f,0x47,0x14,0x0a]
 camoswap.c.rl ca4, cra, (cs0)
 
-# CHECK-ASM-AND-OBJ: camoswap.d.aqrl a4, ra, (cs0)
+# CHECK-ASM-AND-OBJ: camoswap.d.aqrl a4, ra, (s0)
 # CHECK-ASM: encoding: [0x2f,0x37,0x14,0x0e]
 camoswap.d.aqrl a4, ra, (cs0)
-# CHECK-ASM-AND-OBJ: camoadd.d.aqrl a1, a2, (ca3)
+# CHECK-ASM-AND-OBJ: camoadd.d.aqrl a1, a2, (a3)
 # CHECK-ASM: encoding: [0xaf,0xb5,0xc6,0x06]
 camoadd.d.aqrl a1, a2, (ca3)
-# CHECK-ASM-AND-OBJ: camoxor.d.aqrl a2, a3, (ca4)
+# CHECK-ASM-AND-OBJ: camoxor.d.aqrl a2, a3, (a4)
 # CHECK-ASM: encoding: [0x2f,0x36,0xd7,0x26]
 camoxor.d.aqrl a2, a3, (ca4)
-# CHECK-ASM-AND-OBJ: camoand.d.aqrl a3, a4, (ca5)
+# CHECK-ASM-AND-OBJ: camoand.d.aqrl a3, a4, (a5)
 # CHECK-ASM: encoding: [0xaf,0xb6,0xe7,0x66]
 camoand.d.aqrl a3, a4, (ca5)
-# CHECK-ASM-AND-OBJ: camoor.d.aqrl a4, a5, (ca6)
+# CHECK-ASM-AND-OBJ: camoor.d.aqrl a4, a5, (a6)
 # CHECK-ASM: encoding: [0x2f,0x37,0xf8,0x46]
 camoor.d.aqrl a4, a5, (ca6)
-# CHECK-ASM-AND-OBJ: camomin.d.aqrl a5, a6, (ca7)
+# CHECK-ASM-AND-OBJ: camomin.d.aqrl a5, a6, (a7)
 # CHECK-ASM: encoding: [0xaf,0xb7,0x08,0x87]
 camomin.d.aqrl a5, a6, (ca7)
-# CHECK-ASM-AND-OBJ: camomax.d.aqrl s7, s6, (cs5)
+# CHECK-ASM-AND-OBJ: camomax.d.aqrl s7, s6, (s5)
 # CHECK-ASM: encoding: [0xaf,0xbb,0x6a,0xa7]
 camomax.d.aqrl s7, s6, (cs5)
-# CHECK-ASM-AND-OBJ: camominu.d.aqrl s6, s5, (cs4)
+# CHECK-ASM-AND-OBJ: camominu.d.aqrl s6, s5, (s4)
 # CHECK-ASM: encoding: [0x2f,0x3b,0x5a,0xc7]
 camominu.d.aqrl s6, s5, (cs4)
-# CHECK-ASM-AND-OBJ: camomaxu.d.aqrl s5, s4, (cs3)
+# CHECK-ASM-AND-OBJ: camomaxu.d.aqrl s5, s4, (s3)
 # CHECK-ASM: encoding: [0xaf,0xba,0x49,0xe7]
 camomaxu.d.aqrl s5, s4, (cs3)
 
-# CHECK-ASM-AND-OBJ: camoswap.c.aqrl ca4, cra, (cs0)
+# CHECK-ASM-AND-OBJ: camoswap.c.aqrl a4, ra, (s0)
 # CHECK-ASM: encoding: [0x2f,0x47,0x14,0x0e]
 camoswap.c.aqrl ca4, cra, (cs0)
diff --git a/llvm/test/MC/RISCV/cheri/rv64axcheri-valid.s b/llvm/test/MC/RISCV/cheri/rv64axcheri-valid.s
index 39e61d3c7696d..13d94b91e90b5 100644
--- a/llvm/test/MC/RISCV/cheri/rv64axcheri-valid.s
+++ b/llvm/test/MC/RISCV/cheri/rv64axcheri-valid.s
@@ -4,69 +4,69 @@
 # RUN:     | llvm-objdump -M no-aliases --mattr=+a,+xcheri -d - \
 # RUN:     | FileCheck -check-prefixes=CHECK-ASM-AND-OBJ %s
 
-# CHECK-ASM-AND-OBJ: lr.c ct0, (t1)
+# CHECK-ASM-AND-OBJ: lr.c t0, (t1)
 # CHECK-ASM: encoding: [0xaf,0x42,0x03,0x10]
 lr.c ct0, (t1)
-# CHECK-ASM-AND-OBJ: lr.c.aq ct1, (t2)
+# CHECK-ASM-AND-OBJ: lr.c.aq t1, (t2)
 # CHECK-ASM: encoding: [0x2f,0xc3,0x03,0x14]
 lr.c.aq ct1, (t2)
-# CHECK-ASM-AND-OBJ: lr.c.rl ct2, (t3)
+# CHECK-ASM-AND-OBJ: lr.c.rl t2, (t3)
 # CHECK-ASM: encoding: [0xaf,0x43,0x0e,0x12]
 lr.c.rl ct2, (t3)
-# CHECK-ASM-AND-OBJ: lr.c.aqrl ct3, (t4)
+# CHECK-ASM-AND-OBJ: lr.c.aqrl t3, (t4)
 # CHECK-ASM: encoding: [0x2f,0xce,0x0e,0x16]
 lr.c.aqrl ct3, (t4)
 
-# CHECK-ASM-AND-OBJ: sc.c t6, ct5, (t4)
+# CHECK-ASM-AND-OBJ: sc.c t6, t5, (t4)
 # CHECK-ASM: encoding: [0xaf,0xcf,0xee,0x19]
 sc.c t6, ct5, (t4)
-# CHECK-ASM-AND-OBJ: sc.c.aq t5, ct4, (t3)
+# CHECK-ASM-AND-OBJ: sc.c.aq t5, t4, (t3)
 # CHECK-ASM: encoding: [0x2f,0x4f,0xde,0x1d]
 sc.c.aq t5, ct4, (t3)
-# CHECK-ASM-AND-OBJ: sc.c.rl t4, ct3, (t2)
+# CHECK-ASM-AND-OBJ: sc.c.rl t4, t3, (t2)
 # CHECK-ASM: encoding: [0xaf,0xce,0xc3,0x1b]
 sc.c.rl t4, ct3, (t2)
-# CHECK-ASM-AND-OBJ: sc.c.aqrl t3, ct2, (t1)
+# CHECK-ASM-AND-OBJ: sc.c.aqrl t3, t2, (t1)
 # CHECK-ASM: encoding: [0x2f,0x4e,0x73,0x1e]
 sc.c.aqrl t3, ct2, (t1)
 
-# CHECK-ASM-AND-OBJ: amoswap.c ca4, cra, (s0)
+# CHECK-ASM-AND-OBJ: amoswap.c a4, ra, (s0)
 # CHECK-ASM: encoding: [0x2f,0x47,0x14,0x08]
 amoswap.c ca4, cra, (s0)
-# CHECK-ASM-AND-OBJ: amoswap.c.aq ca4, cra, (s0)
+# CHECK-ASM-AND-OBJ: amoswap.c.aq a4, ra, (s0)
 # CHECK-ASM: encoding: [0x2f,0x47,0x14,0x0c]
 amoswap.c.aq ca4, cra, (s0)
-# CHECK-ASM-AND-OBJ: amoswap.c.rl ca4, cra, (s0)
+# CHECK-ASM-AND-OBJ: amoswap.c.rl a4, ra, (s0)
 # CHECK-ASM: encoding: [0x2f,0x47,0x14,0x0a]
 amoswap.c.rl ca4, cra, (s0)
-# CHECK-ASM-AND-OBJ: amoswap.c.aqrl ca4, cra, (s0)
+# CHECK-ASM-AND-OBJ: amoswap.c.aqrl a4, ra, (s0)
 # CHECK-ASM: encoding: [0x2f,0x47,0x14,0x0e]
 amoswap.c.aqrl ca4, cra, (s0)
 
 # CHECK-ASM-AND-OBJ: lr.d.ddc ra, (sp)
 # CHECK-ASM: encoding: [0xdb,0x00,0x31,0xfb]
 lr.d.ddc x1, (x2)
-# CHECK-ASM-AND-OBJ: lr.c.ddc cra, (sp)
+# CHECK-ASM-AND-OBJ: lr.c.ddc ra, (sp)
 # CHECK-ASM: encoding: [0xdb,0x00,0x41,0xfb]
 lr.c.ddc c1, (x2)
 
 # CHECK-ASM-AND-OBJ: sc.d.ddc ra, (sp)
 # CHECK-ASM: encoding: [0xdb,0x09,0x11,0xf8]
 sc.d.ddc x1, (x2)
-# CHECK-ASM-AND-OBJ: sc.c.ddc cra, (sp)
+# CHECK-ASM-AND-OBJ: sc.c.ddc ra, (sp)
 # CHECK-ASM: encoding: [0x5b,0x0a,0x11,0xf8]
 sc.c.ddc c1, (x2)
 
-# CHECK-ASM-AND-OBJ: lr.d.cap ra, (csp)
+# CHECK-ASM-AND-OBJ: lr.d.cap ra, (sp)
 # CHECK-ASM: encoding: [0xdb,0x00,0xb1,0xfb]
 lr.d.cap x1, (c2)
-# CHECK-ASM-AND-OBJ: lr.c.cap cra, (csp)
+# CHECK-ASM-AND-OBJ: lr.c.cap ra, (sp)
 # CHECK-ASM: encoding: [0xdb,0x00,0xc1,0xfb]
 lr.c.cap c1, (c2)
 
-# CHECK-ASM-AND-OBJ: sc.d.cap ra, (csp)
+# CHECK-ASM-AND-OBJ: sc.d.cap ra, (sp)
 # CHECK-ASM: encoding: [0xdb,0x0d,0x11,0xf8]
 sc.d.cap x1, (c2)
-# CHECK-ASM-AND-OBJ: sc.c.cap cra, (csp)
+# CHECK-ASM-AND-OBJ: sc.c.cap ra, (sp)
 # CHECK-ASM: encoding: [0x5b,0x0e,0x11,0xf8]
 sc.c.cap c1, (c2)
diff --git a/llvm/test/MC/RISCV/cheri/rv64cxcheri-cap-mode-only-valid.s b/llvm/test/MC/RISCV/cheri/rv64cxcheri-cap-mode-only-valid.s
index c10f669dc8d78..5eef5561be285 100644
--- a/llvm/test/MC/RISCV/cheri/rv64cxcheri-cap-mode-only-valid.s
+++ b/llvm/test/MC/RISCV/cheri/rv64cxcheri-cap-mode-only-valid.s
@@ -5,52 +5,52 @@
 # RUN:     | FileCheck -check-prefixes=CHECK-ASM-AND-OBJ %s
 
 ## Different encoding between RV64 and RV32 (see rv32cxcheri-cap-mode-only-valid.s)
-# CHECK-ASM-AND-OBJ: c.clccsp cra, 32(csp)
+# CHECK-ASM-AND-OBJ: c.clccsp ra, 32(sp)
 # CHECK-ASM-SAME: encoding: [0x82,0x30]
 c.clccsp cra, 32(csp)
-# CHECK-ASM-AND-OBJ: c.clccsp cra, 32(csp)
+# CHECK-ASM-AND-OBJ: c.clccsp ra, 32(sp)
 # CHECK-ASM-SAME: encoding: [0x82,0x30]
 c.lcsp cra, 32(csp)
-# CHECK-ASM-AND-OBJ-NEXT: c.csccsp cra, 256(csp)
+# CHECK-ASM-AND-OBJ-NEXT: c.csccsp ra, 256(sp)
 # CHECK-ASM-SAME: encoding: [0x06,0xa2]
 c.csccsp cra, 256(csp)
-# CHECK-ASM-AND-OBJ-NEXT: c.csccsp cra, 256(csp)
+# CHECK-ASM-AND-OBJ-NEXT: c.csccsp ra, 256(sp)
 # CHECK-ASM-SAME: encoding: [0x06,0xa2]
 c.scsp cra, 256(csp)
-# CHECK-ASM-AND-OBJ-NEXT: c.clc ca2, 16(ca0)
+# CHECK-ASM-AND-OBJ-NEXT: c.clc a2, 16(a0)
 # CHECK-ASM-SAME: encoding: [0x10,0x29]
 c.clc ca2, 16(ca0)
-# CHECK-ASM-AND-OBJ-NEXT: c.clc ca2, 16(ca0)
+# CHECK-ASM-AND-OBJ-NEXT: c.clc a2, 16(a0)
 # CHECK-ASM-SAME: encoding: [0x10,0x29]
 c.lc ca2, 16(ca0)
-# CHECK-ASM-AND-OBJ-NEXT: c.csc ca5, 128(ca3)
+# CHECK-ASM-AND-OBJ-NEXT: c.csc a5, 128(a3)
 # CHECK-ASM-SAME: encoding: [0xdc,0xa2]
 c.csc ca5, 128(ca3)
-# CHECK-ASM-AND-OBJ-NEXT: c.csc ca5, 128(ca3)
+# CHECK-ASM-AND-OBJ-NEXT: c.csc a5, 128(a3)
 # CHECK-ASM-SAME: encoding: [0xdc,0xa2]
 c.sc ca5, 128(ca3)
 ## *D operations need RV64C:
-# CHECK-ASM-AND-OBJ-NEXT: c.cldcsp ra, 40(csp)
+# CHECK-ASM-AND-OBJ-NEXT: c.cldcsp ra, 40(sp)
 # CHECK-ASM-SAME: encoding: [0xa2,0x70]
 c.cldcsp ra, 40(csp)
-# CHECK-ASM-AND-OBJ-NEXT: c.cldcsp ra, 40(csp)
+# CHECK-ASM-AND-OBJ-NEXT: c.cldcsp ra, 40(sp)
 # CHECK-ASM-SAME: encoding: [0xa2,0x70]
 c.ldsp ra, 40(csp)
-# CHECK-ASM-AND-OBJ-NEXT: c.csdcsp ra, 256(csp)
+# CHECK-ASM-AND-OBJ-NEXT: c.csdcsp ra, 256(sp)
 # CHECK-ASM-SAME: encoding: [0x06,0xe2]
 c.sdsp ra, 256(csp)
-# CHECK-ASM-AND-OBJ-NEXT: c.csdcsp ra, 256(csp)
+# CHECK-ASM-AND-OBJ-NEXT: c.csdcsp ra, 256(sp)
 # CHECK-ASM-SAME: encoding: [0x06,0xe2]
 c.sdsp ra, 256(csp)
-# CHECK-ASM-AND-OBJ-NEXT: c.cld a2, 16(ca0)
+# CHECK-ASM-AND-OBJ-NEXT: c.cld a2, 16(a0)
 # CHECK-ASM-SAME: encoding: [0x10,0x69]
 c.cld a2, 16(ca0)
-# CHECK-ASM-AND-OBJ-NEXT: c.cld a2, 16(ca0)
+# CHECK-ASM-AND-OBJ-NEXT: c.cld a2, 16(a0)
 # CHECK-ASM-SAME: encoding: [0x10,0x69]
 c.ld a2, 16(ca0)
-# CHECK-ASM-AND-OBJ-NEXT: c.csd a5, 128(ca3)
+# CHECK-ASM-AND-OBJ-NEXT: c.csd a5, 128(a3)
 # CHECK-ASM-SAME: encoding: [0xdc,0xe2]
 c.csd a5, 128(ca3)
-# CHECK-ASM-AND-OBJ-NEXT: c.csd a5, 128(ca3)
+# CHECK-ASM-AND-OBJ-NEXT: c.csd a5, 128(a3)
 # CHECK-ASM-SAME: encoding: [0xdc,0xe2]
 c.sd a5, 128(ca3)
diff --git a/llvm/test/MC/RISCV/cheri/rv64xcheri-cap-mode-only-valid.s b/llvm/test/MC/RISCV/cheri/rv64xcheri-cap-mode-only-valid.s
index 2e51167f7454b..443d61ab851fd 100644
--- a/llvm/test/MC/RISCV/cheri/rv64xcheri-cap-mode-only-valid.s
+++ b/llvm/test/MC/RISCV/cheri/rv64xcheri-cap-mode-only-valid.s
@@ -14,38 +14,38 @@
 
 # Capability load/store uses different encodings for RV32 vs RV64
 
-# CHECK-ASM-AND-OBJ: clc ca2, 17(ca0)
+# CHECK-ASM-AND-OBJ: clc a2, 17(a0)
 # CHECK-ASM-SAME: encoding: [0x0f,0x26,0x15,0x01]
 clc ca2, 17(ca0)
-# CHECK-ASM-AND-OBJ: csc ca5, 25(ca3)
+# CHECK-ASM-AND-OBJ: csc a5, 25(a3)
 # CHECK-ASM-SAME: encoding: [0xa3,0xcc,0xf6,0x00]
 csc ca5, 25(ca3)
 
-# CHECK-ASM-AND-OBJ: cld a2, 17(ca0)
+# CHECK-ASM-AND-OBJ: cld a2, 17(a0)
 # CHECK-ASM-SAME: encoding: [0x03,0x36,0x15,0x01]
 cld a2, 17(ca0)
-# CHECK-ASM-AND-OBJ: csd a5, 25(ca3)
+# CHECK-ASM-AND-OBJ: csd a5, 25(a3)
 # CHECK-ASM-SAME: encoding: [0xa3,0xbc,0xf6,0x00]
 csd a5, 25(ca3)
 
-# CHECK-ASM-AND-OBJ: clwu a2, 17(ca0)
+# CHECK-ASM-AND-OBJ: clwu a2, 17(a0)
 # CHECK-ASM-SAME: encoding: [0x03,0x66,0x15,0x01]
 clwu a2, 17(ca0)
 
-# CHECK-ASM-AND-OBJ: clc ca2, 0(ca0)
+# CHECK-ASM-AND-OBJ: clc a2, 0(a0)
 # CHECK-ASM-SAME: encoding: [0x0f,0x26,0x05,0x00]
 clc ca2, (ca0)
-# CHECK-ASM-AND-OBJ: csc ca5, 0(ca3)
+# CHECK-ASM-AND-OBJ: csc a5, 0(a3)
 # CHECK-ASM-SAME: encoding: [0x23,0xc0,0xf6,0x00]
 csc ca5, (ca3)
 
-# CHECK-ASM-AND-OBJ: cld a2, 0(ca0)
+# CHECK-ASM-AND-OBJ: cld a2, 0(a0)
 # CHECK-ASM-SAME: encoding: [0x03,0x36,0x05,0x00]
 cld a2, (ca0)
-# CHECK-ASM-AND-OBJ: csd a5, 0(ca3)
+# CHECK-ASM-AND-OBJ: csd a5, 0(a3)
 # CHECK-ASM-SAME: encoding: [0x23,0xb0,0xf6,0x00]
 csd a5, (ca3)
 
-# CHECK-ASM-AND-OBJ: clwu a2, 0(ca0)
+# CHECK-ASM-AND-OBJ: clwu a2, 0(a0)
 # CHECK-ASM-SAME: encoding: [0x03,0x66,0x05,0x00]
 clwu a2, (ca0)
diff --git a/llvm/test/MC/RISCV/cheri/rv64xcheri-valid.s b/llvm/test/MC/RISCV/cheri/rv64xcheri-valid.s
index c092d5ca06f27..1f1100369d790 100644
--- a/llvm/test/MC/RISCV/cheri/rv64xcheri-valid.s
+++ b/llvm/test/MC/RISCV/cheri/rv64xcheri-valid.s
@@ -4,11 +4,11 @@
 # RUN:     | llvm-objdump --no-print-imm-hex -M no-aliases --mattr=+xcheri -d - \
 # RUN:     | FileCheck -check-prefix=CHECK-INST %s
 
-# CHECK-INST: lc cra, 3(sp)
+# CHECK-INST: lc ra, 3(sp)
 # CHECK: encoding: [0x8f,0x20,0x31,0x00]
 lc c1, 3(x2)
 
-# CHECK-INST: sc cra, 3(sp)
+# CHECK-INST: sc ra, 3(sp)
 # CHECK: encoding: [0xa3,0x41,0x11,0x00]
 sc c1, 3(x2)
 
@@ -18,30 +18,30 @@ ld.ddc x1, (x2)
 # CHECK-INST: lwu.ddc ra, (sp)
 # CHECK: encoding: [0xdb,0x00,0x61,0xfa]
 lwu.ddc x1, (x2)
-# CHECK-INST: lc.ddc cra, (sp)
+# CHECK-INST: lc.ddc ra, (sp)
 # CHECK: encoding: [0xdb,0x00,0x71,0xfb]
 lc.ddc c1, (x2)
 
 # CHECK-INST: sd.ddc ra, (sp)
 # CHECK: encoding: [0xdb,0x01,0x11,0xf8]
 sd.ddc x1, (x2)
-# CHECK-INST: sc.ddc cra, (sp)
+# CHECK-INST: sc.ddc ra, (sp)
 # CHECK: encoding: [0x5b,0x02,0x11,0xf8]
 sc.ddc c1, (x2)
 
-# CHECK-INST: ld.cap ra, (csp)
+# CHECK-INST: ld.cap ra, (sp)
 # CHECK: encoding: [0xdb,0x00,0xb1,0xfa]
 ld.cap x1, (c2)
-# CHECK-INST: lwu.cap ra, (csp)
+# CHECK-INST: lwu.cap ra, (sp)
 # CHECK: encoding: [0xdb,0x00,0xe1,0xfa]
 lwu.cap x1, (c2)
-# CHECK-INST: lc.cap cra, (csp)
+# CHECK-INST: lc.cap ra, (sp)
 # CHECK: encoding: [0xdb,0x00,0xf1,0xfb]
 lc.cap c1, (c2)
 
-# CHECK-INST: sd.cap ra, (csp)
+# CHECK-INST: sd.cap ra, (sp)
 # CHECK: encoding: [0xdb,0x05,0x11,0xf8]
 sd.cap x1, (c2)
-# CHECK-INST: sc.cap cra, (csp)
+# CHECK-INST: sc.cap ra, (sp)
 # CHECK: encoding: [0x5b,0x06,0x11,0xf8]
 sc.cap c1, (c2)
diff --git a/llvm/test/MC/RISCV/rvi-pseudos-invalid.s b/llvm/test/MC/RISCV/rvi-pseudos-invalid.s
index 4ddc970bd1f84..2dcab572fb7b6 100644
--- a/llvm/test/MC/RISCV/rvi-pseudos-invalid.s
+++ b/llvm/test/MC/RISCV/rvi-pseudos-invalid.s
@@ -12,7 +12,7 @@ lga x1, %hi(foo) # CHECK: :[[@LINE]]:9: error: operand must be a bare symbol nam
 lga x1, %lo(foo) # CHECK: :[[@LINE]]:9: error: operand must be a bare symbol name
 
 sw a2, %hi(a_symbol), a3 # CHECK: :[[@LINE]]:8: error: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo specifier or an integer in the range [-2048, 2047]
-sw a2, %lo(a_symbol), a3 # CHECK: :[[@LINE]]:23: error: operand must be a bare symbol name
+sw a2, %lo(a_symbol), a3 # CHECK: :[[@LINE]]:23: error: invalid operand for instruction
 sw a2, %lo(a_symbol)(a4), a3 # CHECK: :[[@LINE]]:27: error: invalid operand for instruction
 
 # Too few operands must be rejected
diff --git a/llvm/test/Transforms/RelLookupTableConverter/cheri.ll b/llvm/test/Transforms/RelLookupTableConverter/cheri.ll
index 0ac75bc4dbe5a..8c3f99c829542 100644
--- a/llvm/test/Transforms/RelLookupTableConverter/cheri.ll
+++ b/llvm/test/Transforms/RelLookupTableConverter/cheri.ll
@@ -66,11 +66,11 @@ define ptr addrspace(200) @load_from_string_table(i64 %idx) addrspace(200) {
 ; PURECAP-ASM:       # %bb.0: # %bb
 ; PURECAP-ASM-NEXT:  .LBB0_1: # %bb
 ; PURECAP-ASM-NEXT:    # Label of block must be emitted
-; PURECAP-ASM-NEXT:    auipcc ca1, %captab_pcrel_hi(global)
-; PURECAP-ASM-NEXT:    clc ca1, %pcrel_lo(.LBB0_1)(ca1)
+; PURECAP-ASM-NEXT:    auipcc a1, %captab_pcrel_hi(global)
+; PURECAP-ASM-NEXT:    clc a1, %pcrel_lo(.LBB0_1)(a1)
 ; PURECAP-ASM-NEXT:    slli a0, a0, 4
-; PURECAP-ASM-NEXT:    cincoffset ca0, ca1, a0
-; PURECAP-ASM-NEXT:    clc ca0, 0(ca0)
+; PURECAP-ASM-NEXT:    cincoffset a0, a1, a0
+; PURECAP-ASM-NEXT:    clc a0, 0(a0)
 ; PURECAP-ASM-NEXT:    cret
 bb:
   %ptr = getelementptr inbounds [6 x ptr addrspace(200)], ptr addrspace(200) @global, i64 0, i64 %idx