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[CHERI] Integrate the RISCV Y version of the CHERI register file. #258

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Oct 9, 2025
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[CHERI] Integrate the RISCV Y version of the CHERI register file. #258

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20 changes: 10 additions & 10 deletions clang/test/CodeGen/cheri/cheri-hybrid-ptr-to-cap.c
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Original file line number Diff line number Diff line change
Expand Up @@ -26,10 +26,10 @@ void *__capability global_fn_to_cap(void) {
// ASM-MIPS: cgetpcc $c1
// ASM-MIPS-NEXT: ld $1, %got_disp(external_fn)($1)
// ASM-MIPS-NEXT: cfromptr $c3, $c1, $1
// ASM-RISCV: cspecialr ca1, pcc
// ASM-RISCV: cspecialr a1, pcc
// ASM-RISCV: auipc a0, %got_pcrel_hi(external_fn)
// ASM-RISCV-NEXT: ld a0, %pcrel_lo(.Lpcrel_hi0)(a0)
// ASM-RISCV-NEXT: csetaddr ca1, ca1, a0
// ASM-RISCV-NEXT: csetaddr a1, a1, a0
return (__cheri_tocap void *__capability)&external_fn;
}

Expand All @@ -46,8 +46,8 @@ void *__capability global_data_to_cap(void) {
// ASM-MIPS-NEXT: csetbounds $c3, $c1, 4
// ASM-RISCV: auipc a0, %got_pcrel_hi(external_global)
// ASM-RISCV-NEXT: ld a0, %pcrel_lo(.Lpcrel_hi1)(a0)
// ASM-RISCV-NEXT: cspecialr ca1, ddc
// ASM-RISCV-NEXT: csetaddr ca1, ca1, a0
// ASM-RISCV-NEXT: cspecialr a1, ddc
// ASM-RISCV-NEXT: csetaddr a1, a1, a0
// We do not set bounds on RISCV
// ASM-RISCV-NOT: csetbounds
return (__cheri_tocap void *__capability)&external_global;
Expand All @@ -68,8 +68,8 @@ void *__capability fn_ptr_to_cap(void (*fn_ptr)(void)) {
// ASM-LABEL: fn_ptr_to_cap:
// ASM-MIPS: cgetpcc $c1
// ASM-MIPS-NEXT: cfromptr $c3, $c1, $1
// ASM-RISCV: cspecialr ca1, pcc
// ASM-RISCV-NEXT: csetaddr ca1, ca1, a0
// ASM-RISCV: cspecialr a1, pcc
// ASM-RISCV-NEXT: csetaddr a1, a1, a0
return (__cheri_tocap void *__capability)fn_ptr;
}

Expand All @@ -88,8 +88,8 @@ void *__capability fn_ptr_to_cap(void (*fn_ptr)(void)) {
void *__capability fn_ptr_to_cap_not_smart_enough(void (*fn_ptr)(void)) {
// ASM-LABEL: fn_ptr_to_cap_not_smart_enough:
// ASM-MIPS: cfromddc $c3, $1
// ASM-RISCV: cspecialr ca1, ddc
// ASM-RISCV-NEXT: csetaddr ca1, ca1, a0
// ASM-RISCV: cspecialr a1, ddc
// ASM-RISCV-NEXT: csetaddr a1, a1, a0
// Note: In this case clang doesn't see that the result is actual a function
// so it uses DDC:
void *tmp = (void *)fn_ptr;
Expand All @@ -109,7 +109,7 @@ void *__capability data_ptr_to_cap(int *data_ptr) {
// Note: For data pointers we derive from DDC:
// ASM-LABEL: data_ptr_to_cap:
// ASM-MIPS: cfromddc $c3, $1
// ASM-RISCV: cspecialr ca1, ddc
// ASM-RISCV-NEXT: csetaddr ca1, ca1, a0
// ASM-RISCV: cspecialr a1, ddc
// ASM-RISCV-NEXT: csetaddr a1, a1, a0
return (__cheri_tocap void *__capability)data_ptr;
}
6 changes: 3 additions & 3 deletions clang/test/CodeGen/cheri/cheri-mcu-atomic-libcall.c
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Expand Up @@ -4,8 +4,8 @@ _Atomic(int) x;

int callFromNotLibcall(void) {
// Check that atomic libcalls get the right calling convention at the call site.
// CHECK: auipcc ct2, %cheriot_compartment_hi(__library_import_libcalls___atomic_fetch_add_4)
// CHECK: clc ct2, %cheriot_compartment_lo_i(.LBB0_2)(ct2)
// CHECK: cjalr ct2
// CHECK: auipcc t2, %cheriot_compartment_hi(__library_import_libcalls___atomic_fetch_add_4)
// CHECK: clc t2, %cheriot_compartment_lo_i(.LBB0_2)(t2)
// CHECK: cjalr t2
return __c11_atomic_fetch_add(&x, 1, 5);
}
8 changes: 4 additions & 4 deletions lld/test/ELF/cheri/riscv/cheriot_compartment_hi.s
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Expand Up @@ -10,12 +10,12 @@
.p2align 1
.type _start,@function
_start: # @_Z5entryv
ct.auipcc ct1, %cheriot_compartment_hi(near)
ct.auipcc ct1, %cheriot_compartment_hi(mid)
ct.auipcc t1, %cheriot_compartment_hi(near)
ct.auipcc t1, %cheriot_compartment_hi(mid)

# CHECK: 00012000 <_start>:
# CHECK-NEXT: 12000: 00000317 ct.auipcc ct1, 0x0
# CHECK-NEXT: 12004: 00001317 ct.auipcc ct1, 0x1
# CHECK-NEXT: 12000: 00000317 ct.auipcc t1, 0x0
# CHECK-NEXT: 12004: 00001317 ct.auipcc t1, 0x1

.type near,@object
.p2align 3, 0x0
Expand Down
32 changes: 16 additions & 16 deletions lld/test/ELF/cheri/riscv/cheriot_compartment_lo_i.s
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Expand Up @@ -10,33 +10,33 @@
.p2align 1
.type _start,@function
_start: # @_Z5entryv
ct.auipcc ct1, %cheriot_compartment_hi(near)
ct.clc ct1, %cheriot_compartment_lo_i(_start)(ct1)
ct.auipcc t1, %cheriot_compartment_hi(near)
ct.clc t1, %cheriot_compartment_lo_i(_start)(t1)
.MID_BLOCK:
ct.auipcc ct1, %cheriot_compartment_hi(mid)
ct.clc ct1, %cheriot_compartment_lo_i(.MID_BLOCK)(ct1)
ct.auipcc t1, %cheriot_compartment_hi(mid)
ct.clc t1, %cheriot_compartment_lo_i(.MID_BLOCK)(t1)
.CGP_BLOCK:
ct.auipcc ct1, %cheriot_compartment_hi(cgp)
ct.clw ra, %cheriot_compartment_lo_i(.CGP_BLOCK)(ct1)
ct.auipcc t1, %cheriot_compartment_hi(cgp)
ct.clw ra, %cheriot_compartment_lo_i(.CGP_BLOCK)(t1)
.CGP_FAR_BLOCK:
ct.auipcc ct1, %cheriot_compartment_hi(cgp_far)
ct.clw ra, %cheriot_compartment_lo_i(.CGP_FAR_BLOCK)(ct1)
ct.auipcc t1, %cheriot_compartment_hi(cgp_far)
ct.clw ra, %cheriot_compartment_lo_i(.CGP_FAR_BLOCK)(t1)

# CHECK: 00012000 <_start>:
# CHECK-NEXT: 12000: 00000317 ct.auipcc ct1, 0x0
# CHECK-NEXT: 12004: 02033303 ct.clc ct1, 0x20(ct1)
# CHECK-NEXT: 12000: 00000317 ct.auipcc t1, 0x0
# CHECK-NEXT: 12004: 02033303 ct.clc t1, 0x20(t1)

# CHECK: 00012008 <.MID_BLOCK>:
# CHECK-NEXT: 12008: 00001317 ct.auipcc ct1, 0x1
# CHECK-NEXT: 1200c: 7f833303 ct.clc ct1, 0x7f8(ct1)
# CHECK-NEXT: 12008: 00001317 ct.auipcc t1, 0x1
# CHECK-NEXT: 1200c: 7f833303 ct.clc t1, 0x7f8(t1)

# CHECK: 00012010 <.CGP_BLOCK>:
# CHECK-NEXT: 12010: ffffe37b ct.auicgp ct1, 0xffffe
# CHECK-NEXT: 12014: ffc32083 ct.clw ra, -0x4(ct1)
# CHECK-NEXT: 12010: ffffe37b ct.auicgp t1, 0xffffe
# CHECK-NEXT: 12014: ffc32083 ct.clw ra, -0x4(t1)

# CHECK: 00012018 <.CGP_FAR_BLOCK>:
# CHECK-NEXT: 12018: 0000237b ct.auicgp ct1, 0x2
# CHECK-NEXT: 1201c: 00032083 ct.clw ra, 0x0(ct1)
# CHECK-NEXT: 12018: 0000237b ct.auicgp t1, 0x2
# CHECK-NEXT: 1201c: 00032083 ct.clw ra, 0x0(t1)

.type near,@object
.p2align 3, 0x0
Expand Down
32 changes: 16 additions & 16 deletions lld/test/ELF/cheri/riscv/plt.s
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Expand Up @@ -44,17 +44,17 @@
# DIS: <_start>:
## Direct call
## foo - . = 0x11020-0x11000 = 32
# DIS-NEXT: 11000: auipcc cra, 0
# DIS-NEXT: cjalr 32(cra)
# DIS-NEXT: 11000: auipcc ra, 0
# DIS-NEXT: cjalr 32(ra)
## bar@plt - . = 0x11050-0x11008 = 72
# DIS-NEXT: 11008: auipcc cra, 0
# DIS-NEXT: cjalr 72(cra)
# DIS-NEXT: 11008: auipcc ra, 0
# DIS-NEXT: cjalr 72(ra)
## bar@plt - . = 0x11050-0x11010 = 64
# DIS-NEXT: 11010: auipcc cra, 0
# DIS-NEXT: cjalr 64(cra)
# DIS-NEXT: 11010: auipcc ra, 0
# DIS-NEXT: cjalr 64(ra)
## weak@plt - . = 0x11060-0x11018 = 72
# DIS-NEXT: 11018: auipcc cra, 0
# DIS-NEXT: cjalr 72(cra)
# DIS-NEXT: 11018: auipcc ra, 0
# DIS-NEXT: cjalr 72(ra)
# DIS: <foo>:
# DIS-NEXT: 11020:

Expand All @@ -63,17 +63,17 @@
# DIS-NEXT: ...

## 32-bit: &.captable[bar]-. = 0x12000-0x11050 = 4096*1-80
# DIS: 11050: auipcc ct3, 1
# DIS32-NEXT: clc ct3, -80(ct3)
# DIS64-NEXT: clc ct3, -80(ct3)
# DIS-NEXT: cjalr ct1, ct3
# DIS: 11050: auipcc t3, 1
# DIS32-NEXT: clc t3, -80(t3)
# DIS64-NEXT: clc t3, -80(t3)
# DIS-NEXT: cjalr t1, t3
# DIS-NEXT: nop

## 32-bit: &.captable[weak]-. = 0x12008-0x11060 = 4096*1-88
# DIS: 11060: auipcc ct3, 1
# DIS32-NEXT: clc ct3, -88(ct3)
# DIS64-NEXT: clc ct3, -80(ct3)
# DIS-NEXT: cjalr ct1, ct3
# DIS: 11060: auipcc t3, 1
# DIS32-NEXT: clc t3, -88(t3)
# DIS64-NEXT: clc t3, -80(t3)
# DIS-NEXT: cjalr t1, t3
# DIS-NEXT: nop

.global _start, foo, bar
Expand Down
84 changes: 42 additions & 42 deletions lld/test/ELF/cheri/riscv/tls.s
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Expand Up @@ -54,40 +54,40 @@
# RV32-SO-CAP-NEXT: 0x00003298 00000000 00000000

# 0x121e0 - 0x111b4 = 0x0102c (GD evar)
# RV32-DIS: 111b4: auipcc ca0, 1
# RV32-DIS-NEXT: cincoffset ca0, ca0, 44
# RV32-DIS: 111b4: auipcc a0, 1
# RV32-DIS-NEXT: cincoffset a0, a0, 44

# 0x121f0 - 0x111bc = 0x01034 (IE evar)
# RV32-DIS: 111bc: auipcc ca0, 1
# RV32-DIS-NEXT: clw a0, 52(ca0)
# RV32-DIS: 111bc: auipcc a0, 1
# RV32-DIS-NEXT: clw a0, 52(a0)

# 0x121e8 - 0x111c4 = 0x01024 (GD lvar)
# RV32-DIS: 111c4: auipcc ca0, 1
# RV32-DIS-NEXT: cincoffset ca0, ca0, 36
# RV32-DIS: 111c4: auipcc a0, 1
# RV32-DIS-NEXT: cincoffset a0, a0, 36

# 0x121f4 - 0x111cc = 0x01028 (IE lvar)
# RV32-DIS: 111cc: auipcc ca0, 1
# RV32-DIS-NEXT: clw a0, 40(ca0)
# RV32-DIS: 111cc: auipcc a0, 1
# RV32-DIS-NEXT: clw a0, 40(a0)

# RV32-DIS: 111d4: lui a0, 0
# RV32-DIS-NEXT: cincoffset ca0, ctp, a0
# RV32-DIS-NEXT: cincoffset ca0, ca0, 4
# RV32-DIS-NEXT: cincoffset a0, tp, a0
# RV32-DIS-NEXT: cincoffset a0, a0, 4

# 0x3288 - 0x1210 = 0x2078 (GD evar)
# RV32-SO-DIS: 1210: auipcc ca0, 2
# RV32-SO-DIS-NEXT: cincoffset ca0, ca0, 120
# RV32-SO-DIS: 1210: auipcc a0, 2
# RV32-SO-DIS-NEXT: cincoffset a0, a0, 120

# 0x3298 - 0x1218 = 0x2080 (IE evar)
# RV32-SO-DIS: 1218: auipcc ca0, 2
# RV32-SO-DIS-NEXT: clw a0, 128(ca0)
# RV32-SO-DIS: 1218: auipcc a0, 2
# RV32-SO-DIS-NEXT: clw a0, 128(a0)

# 0x3290 - 0x1220 = 0x2070 (GD lvar)
# RV32-SO-DIS: 1220: auipcc ca0, 2
# RV32-SO-DIS-NEXT: cincoffset ca0, ca0, 112
# RV32-SO-DIS: 1220: auipcc a0, 2
# RV32-SO-DIS-NEXT: cincoffset a0, a0, 112

# 0x329c - 0x1228 = 0x2074 (IE lvar)
# RV32-SO-DIS: 1228: auipcc ca0, 2
# RV32-SO-DIS-NEXT: clw a0, 116(ca0)
# RV32-SO-DIS: 1228: auipcc a0, 2
# RV32-SO-DIS-NEXT: clw a0, 116(a0)

# RV64-REL: .rela.dyn {
# RV64-REL-NEXT: 0x122F0 R_RISCV_TLS_DTPMOD64 evar 0x0
Expand All @@ -114,55 +114,55 @@
# RV64-SO-CAP-NEXT: 0x00003440 00000000 00000000 00000000 00000000

# 0x122f0 - 0x112b8 = 0x01038 (GD evar)
# RV64-DIS: 112b8: auipcc ca0, 1
# RV64-DIS-NEXT: cincoffset ca0, ca0, 56
# RV64-DIS: 112b8: auipcc a0, 1
# RV64-DIS-NEXT: cincoffset a0, a0, 56

# 0x12310 - 0x112c0 = 0x01050 (IE evar)
# RV64-DIS: 112c0: auipcc ca0, 1
# RV64-DIS-NEXT: cld a0, 80(ca0)
# RV64-DIS: 112c0: auipcc a0, 1
# RV64-DIS-NEXT: cld a0, 80(a0)

# 0x12300 - 0x112c8 = 0x01038 (GD lvar)
# RV64-DIS: 112c8: auipcc ca0, 1
# RV64-DIS-NEXT: cincoffset ca0, ca0, 56
# RV64-DIS: 112c8: auipcc a0, 1
# RV64-DIS-NEXT: cincoffset a0, a0, 56

# 0x12318 - 0x112d0 = 0x01048 (IE lvar)
# RV64-DIS: 112d0: auipcc ca0, 1
# RV64-DIS-NEXT: cld a0, 72(ca0)
# RV64-DIS: 112d0: auipcc a0, 1
# RV64-DIS-NEXT: cld a0, 72(a0)

# RV64-DIS: 112d8: lui a0, 0
# RV64-DIS-NEXT: cincoffset ca0, ctp, a0
# RV64-DIS-NEXT: cincoffset ca0, ca0, 4
# RV64-DIS-NEXT: cincoffset a0, tp, a0
# RV64-DIS-NEXT: cincoffset a0, a0, 4

# 0x3420 - 0x1350 = 0x20d0 (GD evar)
# RV64-SO-DIS: 1350: auipcc ca0, 2
# RV64-SO-DIS-NEXT: cincoffset ca0, ca0, 208
# RV64-SO-DIS: 1350: auipcc a0, 2
# RV64-SO-DIS-NEXT: cincoffset a0, a0, 208

# 0x3440 - 0x1358 = 0x20e8 (IE evar)
# RV64-SO-DIS: 1358: auipcc ca0, 2
# RV64-SO-DIS-NEXT: cld a0, 232(ca0)
# RV64-SO-DIS: 1358: auipcc a0, 2
# RV64-SO-DIS-NEXT: cld a0, 232(a0)

# 0x3430 - 0x1360 = 0x20d0 (GD lvar)
# RV64-SO-DIS: 1360: auipcc ca0, 2
# RV64-SO-DIS-NEXT: cincoffset ca0, ca0, 208
# RV64-SO-DIS: 1360: auipcc a0, 2
# RV64-SO-DIS-NEXT: cincoffset a0, a0, 208

# 0x3448 - 0x1368 = 0x20e0 (IE lvar)
# RV64-SO-DIS: 1368: auipcc ca0, 2
# RV64-SO-DIS-NEXT: cld a0, 224(ca0)
# RV64-SO-DIS: 1368: auipcc a0, 2
# RV64-SO-DIS-NEXT: cld a0, 224(a0)

.global _start
_start:
clc.tls.gd ca0, evar
clc.tls.gd a0, evar

cla.tls.ie a0, evar, ca0
cla.tls.ie a0, evar, a0

clc.tls.gd ca0, lvar
clc.tls.gd a0, lvar

cla.tls.ie a0, lvar, ca0
cla.tls.ie a0, lvar, a0

.if PIC == 0
lui a0, %tprel_hi(lvar)
cincoffset ca0, ctp, a0, %tprel_cincoffset(lvar)
cincoffset ca0, ca0, %tprel_lo(lvar)
cincoffset a0, tp, a0, %tprel_cincoffset(lvar)
cincoffset a0, a0, %tprel_lo(lvar)
.endif

.tbss
Expand Down
22 changes: 19 additions & 3 deletions llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
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Expand Up @@ -549,9 +549,9 @@ struct RISCVOperand final : public MCParsedAsmOperand {
RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg.RegNum);
}

bool isGPCR() const {
bool isYGPR() const {
return Kind == KindTy::Register &&
RISCVMCRegisterClasses[RISCV::GPCRRegClassID].contains(Reg.RegNum);
RISCVMCRegisterClasses[RISCV::YGPRRegClassID].contains(Reg.RegNum);
}

bool isGPRPair() const {
Expand Down Expand Up @@ -1464,6 +1464,11 @@ static MCRegister convertFPR64ToFPR128(MCRegister Reg) {
return Reg - RISCV::F0_D + RISCV::F0_Q;
}

static MCRegister convertGPRToYGPR(MCRegister Reg) {
assert(Reg >= RISCV::X0 && Reg <= RISCV::X31 && "Invalid register");
return Reg - RISCV::X0 + RISCV::X0_Y;
}

static MCRegister convertVRToVRMx(const MCRegisterInfo &RI, MCRegister Reg,
unsigned Kind) {
unsigned RegClassID;
Expand Down Expand Up @@ -1492,6 +1497,17 @@ unsigned RISCVAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
RISCVMCRegisterClasses[RISCV::FPR64CRegClassID].contains(Reg);
bool IsRegVR = RISCVMCRegisterClasses[RISCV::VRRegClassID].contains(Reg);

bool WantsYReg = Kind == MCK_YGPR || Kind == MCK_YGPRC ||
Kind == MCK_YGPRTC || Kind == MCK_YGPRE ||
Kind == MCK_YGPRNoX0X1 || Kind == MCK_YGPRNoX0 ||
Kind == MCK_YGPRX0IsDDC;

if (Op.isGPR() && WantsYReg) {
// GPR and capability GPR use the same register names, convert if required.
Op.Reg.RegNum = convertGPRToYGPR(Reg);
return Match_Success;
}

if (IsRegFPR64 && Kind == MCK_FPR128) {
Op.Reg.RegNum = convertFPR64ToFPR128(Reg);
return Match_Success;
Expand Down Expand Up @@ -4245,7 +4261,7 @@ bool RISCVAsmParser::checkPseudoCIncOffsetTPRel(MCInst &Inst,
assert(Inst.getOpcode() == RISCV::PseudoCIncOffsetTPRel &&
"Invalid instruction");
assert(Inst.getOperand(1).isReg() && "Unexpected first operand kind");
if (Inst.getOperand(1).getReg() != RISCV::C4) {
if (Inst.getOperand(1).getReg() != RISCV::X4_Y) {
SMLoc ErrorLoc = ((RISCVOperand &)*Operands[2]).getStartLoc();
return Error(ErrorLoc, "the first input operand must be ctp/c4 when using "
"%tprel_cincoffset modifier");
Expand Down
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