diff --git a/lld/ELF/Arch/Cheri.cpp b/lld/ELF/Arch/Cheri.cpp index 3bd18741918dd..75f6e42e64483 100644 --- a/lld/ELF/Arch/Cheri.cpp +++ b/lld/ELF/Arch/Cheri.cpp @@ -333,7 +333,8 @@ void CheriCapRelocsSection::addCapReloc(CheriCapRelocLocation loc, auto sourceMsg = [&]() -> std::string { return sourceSymbol ? verboseToString(ctx, sourceSymbol) : loc.toString(ctx); }; - if (target.sym()->isUndefined() && !target.sym()->isUndefWeak()) { + if (isa(target.symOrSec) && target.sym()->isUndefined() && + !target.sym()->isUndefWeak()) { auto diag = (ctx.arg.unresolvedSymbols == UnresolvedPolicy::ReportError) ? Err(ctx) : (errorHandler().fatalWarnings) ? Msg(ctx) @@ -362,6 +363,7 @@ void CheriCapRelocsSection::addCapReloc(CheriCapRelocLocation loc, return; // Maybe happens with vtables? } if (targetNeedsDynReloc) { + assert(isa(target.symOrSec)); bool relativeToLoadAddress = false; // The addend is not used as the offset into the capability here, as we // have the offset field in the __cap_relocs for that. The Addend @@ -398,6 +400,9 @@ void CheriCapRelocsSection::addCapReloc(CheriCapRelocLocation loc, template static uint64_t getTargetSize(Ctx &ctx, const CheriCapRelocLocation &location, const SymbolAndOffset &target) { + if (InputSectionBase *isec = dyn_cast(target.symOrSec)) + return isec->getSize(); + uint64_t targetSize = target.sym()->getSize(ctx); if (targetSize > INT_MAX) { error("Insanely large symbol size for " + target.verboseToString(ctx) + @@ -523,9 +528,24 @@ void CheriCapRelocsSection::writeToImpl(uint8_t *buf) { location.section->getOutputSection()->addr + outSecOffset; // The target VA is the base address of the capability, so symbol + 0 - uint64_t targetVA = realTarget.sym()->getVA(ctx, 0); - bool preemptibleDynReloc = - reloc.needsDynReloc && realTarget.sym()->isPreemptible; + uint64_t targetVA; + bool isPreemptible, isFunc, isTls; + OutputSection *os; + if (Symbol *s = dyn_cast(realTarget.symOrSec)) { + targetVA = realTarget.sym()->getVA(ctx, 0); + isPreemptible = reloc.needsDynReloc && realTarget.sym()->isPreemptible; + isFunc = s->isFunc(); + isTls = s->isTls(); + os = s->getOutputSection(); + } else { + InputSectionBase *isec = cast(realTarget.symOrSec); + targetVA = isec->getVA(0); + isPreemptible = false; + isFunc = (isec->flags & SHF_EXECINSTR) != 0; + isTls = isec->type == STT_TLS; + os = isec->getOutputSection(); + } + bool preemptibleDynReloc = reloc.needsDynReloc && isPreemptible; uint64_t targetSize = 0; if (preemptibleDynReloc) { // If we have a relocation against a preemptible symbol (even in the @@ -543,10 +563,10 @@ void CheriCapRelocsSection::writeToImpl(uint8_t *buf) { uint64_t targetOffset = reloc.capabilityOffset + realTarget.offset; uint64_t permissions = 0; // Fow now Function implies ReadOnly so don't add the flag - if (realTarget.sym()->isFunc()) { + if (isFunc) { permissions |= CaptablePermissions::function; - } else if (auto os = realTarget.sym()->getOutputSection()) { - assert(!realTarget.sym()->isTls()); + } else if (os) { + assert(!isTls); // if ((OS->getPhdrFlags() & PF_W) == 0) { if (((os->flags & SHF_WRITE) == 0) || isRelroSection(ctx, os)) { permissions |= CaptablePermissions::readOnly; @@ -1080,15 +1100,16 @@ static bool isSymIncludedInDynsym(Ctx &ctx, const Symbol &sym) { (ctx.arg.exportDynamic && (sym.isUsedInRegularObj || !sym.ltoCanOmit)); } - template -void addCapabilityRelocation(Ctx &ctx, Symbol *sym, RelType type, - InputSectionBase *sec, uint64_t offset, - RelExpr expr, int64_t addend, bool isCallExpr, - llvm::function_ref referencedBy, - RelocationBaseSection *dynRelSec) { +void addCapabilityRelocation( + Ctx &ctx, llvm::PointerUnion symOrSec, + RelType type, InputSectionBase *sec, uint64_t offset, RelExpr expr, + int64_t addend, bool isCallExpr, + llvm::function_ref referencedBy, + RelocationBaseSection *dynRelSec) { + Symbol *sym = dyn_cast(symOrSec); assert(expr == R_CHERI_CAPABILITY); - if (sec->name == ".gcc_except_table" && sym->isPreemptible) { + if (sec->name == ".gcc_except_table" && sym && sym->isPreemptible) { // We previously had an ugly workaround here to create a hidden alias for // relocations in the exception table, but this has since been fixed in // the compiler. Add an explicit error here in case someone tries to @@ -1102,14 +1123,15 @@ void addCapabilityRelocation(Ctx &ctx, Symbol *sym, RelType type, // Emit either the legacy __cap_relocs section or a R_CHERI_CAPABILITY reloc // For local symbols we can also emit the untagged capability bits and // instruct csu/rtld to run CBuildCap - CapRelocsMode capRelocMode = sym->isPreemptible + CapRelocsMode capRelocMode = sym && sym->isPreemptible ? ctx.arg.preemptibleCapRelocsMode : ctx.arg.localCapRelocsMode; bool needTrampoline = false; // In the PLT ABI (and fndesc?) we have to use an elf relocation for function // pointers to ensure that the runtime linker adds the required trampolines // that sets $cgp: - if (!isCallExpr && ctx.arg.emachine == llvm::ELF::EM_MIPS && sym->isFunc()) { + if (!isCallExpr && ctx.arg.emachine == llvm::ELF::EM_MIPS && sym && + sym->isFunc()) { if (!lld::elf::hasDynamicLinker(ctx)) { // In static binaries we do not need PLT stubs for function pointers since // all functions share the same $cgp @@ -1118,7 +1140,6 @@ void addCapabilityRelocation(Ctx &ctx, Symbol *sym, RelType type, if (ctx.arg.verboseCapRelocs) Msg(ctx) << "Do not need function pointer trampoline for " << toStr(ctx, *sym) << " in static binary"; - needTrampoline = false; } else if (ctx.in.mipsAbiFlags) { auto abi = static_cast &>(*ctx.in.mipsAbiFlags) .getCheriAbiVariant(); @@ -1126,18 +1147,19 @@ void addCapabilityRelocation(Ctx &ctx, Symbol *sym, RelType type, *abi == llvm::ELF::DF_MIPS_CHERI_ABI_FNDESC)) needTrampoline = true; } - } - if (needTrampoline) { - capRelocMode = CapRelocsMode::ElfReloc; - assert(capRelocMode == ctx.arg.preemptibleCapRelocsMode); - if (ctx.arg.verboseCapRelocs) - message("Using trampoline for function pointer against " + - verboseToString(ctx, sym)); + if (needTrampoline) { + capRelocMode = CapRelocsMode::ElfReloc; + assert(capRelocMode == ctx.arg.preemptibleCapRelocsMode); + if (ctx.arg.verboseCapRelocs) + message("Using trampoline for function pointer against " + + verboseToString(ctx, sym)); + } } // local cap relocs don't need a Elf relocation with a full symbol lookup: if (capRelocMode == CapRelocsMode::ElfReloc) { + assert(sym && "ELF relocs should not be used against sections"); assert((sym->isPreemptible || needTrampoline) && "ELF relocs should not be used for non-preemptible symbols"); assert((!sym->isLocal() || needTrampoline) && @@ -1195,10 +1217,10 @@ void addCapabilityRelocation(Ctx &ctx, Symbol *sym, RelType type, } else if (capRelocMode == CapRelocsMode::Legacy) { if (ctx.arg.relativeCapRelocsOnly) { - assert(!sym->isPreemptible); + assert(!sym || !sym->isPreemptible); } - ctx.in.capRelocs->addCapReloc({sec, offset}, {sym, 0u}, - sym->isPreemptible, addend); + ctx.in.capRelocs->addCapReloc({sec, offset}, {symOrSec, 0u}, + sym && sym->isPreemptible, addend); } else { assert(ctx.arg.localCapRelocsMode == CapRelocsMode::CBuildCap); error("CBuildCap method not implemented yet!"); @@ -1209,14 +1231,18 @@ void addCapabilityRelocation(Ctx &ctx, Symbol *sym, RelType type, } // namespace lld template void lld::elf::addCapabilityRelocation( - Ctx &ctx, Symbol *, RelType, InputSectionBase *, uint64_t, RelExpr, int64_t, - bool, llvm::function_ref, RelocationBaseSection *); + Ctx &ctx, llvm::PointerUnion, RelType, + InputSectionBase *, uint64_t, RelExpr, int64_t, bool, + llvm::function_ref, RelocationBaseSection *); template void lld::elf::addCapabilityRelocation( - Ctx &ctx, Symbol *, RelType, InputSectionBase *, uint64_t, RelExpr, int64_t, - bool, llvm::function_ref, RelocationBaseSection *); + Ctx &ctx, llvm::PointerUnion, RelType, + InputSectionBase *, uint64_t, RelExpr, int64_t, bool, + llvm::function_ref, RelocationBaseSection *); template void lld::elf::addCapabilityRelocation( - Ctx &ctx, Symbol *, RelType, InputSectionBase *, uint64_t, RelExpr, int64_t, - bool, llvm::function_ref, RelocationBaseSection *); + Ctx &ctx, llvm::PointerUnion, RelType, + InputSectionBase *, uint64_t, RelExpr, int64_t, bool, + llvm::function_ref, RelocationBaseSection *); template void lld::elf::addCapabilityRelocation( - Ctx &ctx, Symbol *, RelType, InputSectionBase *, uint64_t, RelExpr, int64_t, - bool, llvm::function_ref, RelocationBaseSection *); + Ctx &ctx, llvm::PointerUnion, RelType, + InputSectionBase *, uint64_t, RelExpr, int64_t, bool, + llvm::function_ref, RelocationBaseSection *); diff --git a/lld/ELF/Arch/Cheri.h b/lld/ELF/Arch/Cheri.h index a846273cd2e61..02dbd4a07d943 100644 --- a/lld/ELF/Arch/Cheri.h +++ b/lld/ELF/Arch/Cheri.h @@ -16,12 +16,10 @@ namespace elf { struct SymbolAndOffset { public: - SymbolAndOffset(Symbol *s, int64_t o) : symOrSec(s), offset(o) { + SymbolAndOffset(llvm::PointerUnion s, int64_t o) + : symOrSec(s), offset(o) { assert(s && "Should not be null"); } - SymbolAndOffset(InputSectionBase *isec, int64_t o) : symOrSec(isec), offset(o) { - assert(isec && "Should not be null"); - } SymbolAndOffset(const SymbolAndOffset &) = default; SymbolAndOffset &operator=(const SymbolAndOffset &) = default; @@ -364,11 +362,12 @@ inline uint64_t getBiasedCGPOffsetLo12(Ctx &ctx, const Symbol &sym) } template -void addCapabilityRelocation(Ctx &ctx, Symbol *sym, RelType type, - InputSectionBase *sec, uint64_t offset, - RelExpr expr, int64_t addend, bool isCallExpr, - llvm::function_ref referencedBy, - RelocationBaseSection *dynRelSec = nullptr); +void addCapabilityRelocation( + Ctx &ctx, llvm::PointerUnion target, + RelType type, InputSectionBase *sec, uint64_t offset, RelExpr expr, + int64_t addend, bool isCallExpr, + llvm::function_ref referencedBy, + RelocationBaseSection *dynRelSec = nullptr); } // namespace elf } // namespace lld diff --git a/lld/ELF/Arch/RISCV.cpp b/lld/ELF/Arch/RISCV.cpp index f4e04222a2e62..9a5c4cae9a219 100644 --- a/lld/ELF/Arch/RISCV.cpp +++ b/lld/ELF/Arch/RISCV.cpp @@ -78,7 +78,6 @@ enum Op { CIncOffsetImm = 0x105b, CLC_64 = 0x3003, CLC_128 = 0x200f, - CSub = 0x2800005b, AUIPCC = 0x17, AUICGP = 0x7b, @@ -128,10 +127,7 @@ RISCV::RISCV(Ctx &ctx) : TargetInfo(ctx) { pltRel = R_RISCV_JUMP_SLOT; relativeRel = R_RISCV_RELATIVE; iRelativeRel = R_RISCV_IRELATIVE; - sizeRel = R_RISCV_CHERI_SIZE; cheriCapRel = R_RISCV_CHERI_CAPABILITY; - // TODO: R_RISCV_CHERI_JUMP_SLOT in a separate .got.plt / .captable.plt - cheriCapCallRel = R_RISCV_CHERI_CAPABILITY; if (ctx.arg.is64) { symbolicRel = R_RISCV_64; tlsModuleIndexRel = R_RISCV_TLS_DTPMOD64; @@ -275,12 +271,12 @@ void RISCV::writePltHeader(uint8_t *buf) const { // (c)sub t1, (c)t1, (c)t3 // l[wdc] (c)t3, %pcrel_lo(1b)((c)t2); (c)t3 = _dl_runtime_resolve // addi t1, t1, -pltHeaderSize-12; t1 = &.plt[i] - &.plt[0] - // addi t0, t2, %pcrel_lo(1b) - // srli t1, t1, (rv64?1:2); t1 = &.got.plt[i] - &.got.plt[0] - // l[wd] t0, Wordsize(t0); t0 = link_map - // jr t3 + // addi/cincoffset (c)t0, (c)t2, %pcrel_lo(1b) + // (if shift != 0): srli t1, t1, shift; t1 = &.got.plt[i] - &.got.plt[0] + // l[wdc] (c)t0, Ptrsize((c)t0); (c)t0 = link_map + // (c)jr (c)t3 + // (if shift == 0): nop uint32_t offset = ctx.in.gotPlt->getVA() - ctx.in.plt->getVA(); - uint32_t ptrsub = ctx.arg.isCheriAbi ? CSub : SUB; uint32_t ptrload = ctx.arg.isCheriAbi ? ctx.arg.is64 ? CLC_128 : CLC_64 : ctx.arg.is64 ? LD : LW; @@ -290,7 +286,7 @@ void RISCV::writePltHeader(uint8_t *buf) const { uint32_t ptrsize = ctx.arg.isCheriAbi ? ctx.arg.capabilitySize : ctx.arg.wordsize; write32le(buf + 0, utype(AUIPC, X_T2, hi20(offset))); - write32le(buf + 4, rtype(ptrsub, X_T1, X_T1, X_T3)); + write32le(buf + 4, rtype(SUB, X_T1, X_T1, X_T3)); write32le(buf + 8, itype(ptrload, X_T3, X_T2, lo12(offset))); write32le(buf + 12, itype(ADDI, X_T1, X_T1, -ctx.target->pltHeaderSize - 12)); write32le(buf + 16, itype(ptraddi, X_T0, X_T2, lo12(offset))); @@ -497,30 +493,19 @@ void RISCV::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const { // auipc[c] + [c]jalr pair case R_RISCV_CALL: case R_RISCV_CALL_PLT: - case R_RISCV_CHERI_CCALL: { - int64_t hi = SignExtend64(val + 0x800, bits) >> 12; - checkInt(ctx, loc, hi, 20, rel); - if (isInt<20>(hi)) { - relocateNoSym(loc, R_RISCV_PCREL_HI20, val); - relocateNoSym(loc + 4, R_RISCV_PCREL_LO12_I, val); - } - return; - } - + case R_RISCV_CHERI_CCALL: case R_RISCV_CHERIOT_CCALL: { - // Cheriot uses an 11-bit shift on AUIPCC, requiring different relocation - // compared to R_RISCV_CHERI_CCALL. int64_t hi = SignExtend64(val + 0x800, bits) >> 12; checkInt(ctx, loc, hi, 20, rel); if (isInt<20>(hi)) { - relocate(loc, - Relocation{rel.expr, R_RISCV_CHERIOT_COMPARTMENT_HI, rel.offset, - rel.addend, rel.sym}, - val); - relocate(loc + 4, - Relocation{rel.expr, R_RISCV_CHERIOT_COMPARTMENT_LO_I, - rel.offset, rel.addend, rel.sym}, - val); + relocateNoSym(loc, + ctx.arg.isCheriot ? R_RISCV_CHERIOT_COMPARTMENT_HI + : R_RISCV_PCREL_HI20, + val); + relocateNoSym(loc + 4, + ctx.arg.isCheriot ? R_RISCV_CHERIOT_COMPARTMENT_LO_I + : R_RISCV_PCREL_LO12_I, + val); } return; } @@ -909,10 +894,6 @@ void elf::initSymbolAnchors(Ctx &ctx) { // Relax R_RISCV_CALL/R_RISCV_CALL_PLT auipc+jalr to c.j, c.jal, or jal. static void relaxCall(Ctx &ctx, const InputSection &sec, size_t i, uint64_t loc, Relocation &r, uint32_t &remove) { - bool isCCall = - (r.type == R_RISCV_CHERI_CCALL) || (r.type == R_RISCV_CHERIOT_CCALL); - auto jalRVCType = (isCCall) ? R_RISCV_CHERI_RVC_CJUMP : R_RISCV_RVC_JUMP; - auto jalType = (isCCall) ? R_RISCV_CHERI_CJAL : R_RISCV_JAL; const bool rvc = getEFlags(ctx, sec.file) & EF_RISCV_RVC; const Symbol &sym = *r.sym; const uint64_t insnPair = read64le(sec.content().data() + r.offset); @@ -924,7 +905,7 @@ static void relaxCall(Ctx &ctx, const InputSection &sec, size_t i, uint64_t loc, // When the caller specifies the old value of `remove`, disallow its // increment. if (remove >= 6 && rvc && isInt<12>(displace) && rd == 0) { - sec.relaxAux->relocTypes[i] = jalRVCType; + sec.relaxAux->relocTypes[i] = R_RISCV_RVC_JUMP; sec.relaxAux->writes.push_back(0xa001); // c.[c]j remove = 6; } else if (remove >= 6 && rvc && isInt<12>(displace) && rd == X_RA && @@ -933,7 +914,7 @@ static void relaxCall(Ctx &ctx, const InputSection &sec, size_t i, uint64_t loc, sec.relaxAux->writes.push_back(0x2001); // c.jal remove = 6; } else if (remove >= 4 && isInt<21>(displace)) { - sec.relaxAux->relocTypes[i] = jalType; + sec.relaxAux->relocTypes[i] = R_RISCV_JAL; sec.relaxAux->writes.push_back(0x6f | rd << 7); // [c]jal remove = 4; } else { diff --git a/lld/test/ELF/cheri/riscv/tls.s b/lld/test/ELF/cheri/riscv/tls.s index f10bb3b149657..b6197d35bf147 100644 --- a/lld/test/ELF/cheri/riscv/tls.s +++ b/lld/test/ELF/cheri/riscv/tls.s @@ -167,7 +167,7 @@ _start: .if PIC == 0 lui a0, %tprel_hi(lvar) - cincoffset a0, tp, a0, %tprel_cincoffset(lvar) + cincoffset a0, tp, a0, %tprel_add(lvar) cincoffset a0, a0, %tprel_lo(lvar) .endif diff --git a/llvm/include/llvm/BinaryFormat/ELFRelocs/RISCV.def b/llvm/include/llvm/BinaryFormat/ELFRelocs/RISCV.def index d4314767de0cd..b052ae69af644 100644 --- a/llvm/include/llvm/BinaryFormat/ELFRelocs/RISCV.def +++ b/llvm/include/llvm/BinaryFormat/ELFRelocs/RISCV.def @@ -64,7 +64,7 @@ ELF_RELOC(R_RISCV_VENDOR, 191) // ELF_RELOC(R_RISCV_CUSTOM192, 192) // ELF_RELOC(R_RISCV_CUSTOM193, 193) ELF_RELOC(R_RISCV_CUSTOM194, 194) -// ELF_RELOC(R_RISCV_CUSTOM195, 195) +ELF_RELOC(R_RISCV_CUSTOM195, 195) // ELF_RELOC(R_RISCV_CUSTOM196, 196) // ELF_RELOC(R_RISCV_CUSTOM197, 197) // ELF_RELOC(R_RISCV_CUSTOM198, 198) @@ -129,14 +129,14 @@ ELF_RELOC(R_RISCV_CUSTOM255, 255) // CHERI relocations ELF_RELOC(R_RISCV_CHERI_CAPTAB_PCREL_HI20, 192) ELF_RELOC(R_RISCV_CHERI_CAPABILITY, 193) -// 194 reserved for R_RISCV_CHERI_CAPABILITY_CALL -ELF_RELOC(R_RISCV_CHERI_SIZE, 195) -ELF_RELOC(R_RISCV_CHERI_TPREL_CINCOFFSET, 196) -ELF_RELOC(R_RISCV_CHERI_TLS_IE_CAPTAB_PCREL_HI20, 197) -ELF_RELOC(R_RISCV_CHERI_TLS_GD_CAPTAB_PCREL_HI20, 198) -ELF_RELOC(R_RISCV_CHERI_CJAL, 199) -ELF_RELOC(R_RISCV_CHERI_CCALL, 200) -ELF_RELOC(R_RISCV_CHERI_RVC_CJUMP, 201) +// 194 reserved +// 195 reserved +ELF_RELOC(R_RISCV_CHERI_TPREL_CINCOFFSET, 196) // Deprecated +ELF_RELOC(R_RISCV_CHERI_TLS_IE_CAPTAB_PCREL_HI20, 197) // Deprecated +ELF_RELOC(R_RISCV_CHERI_TLS_GD_CAPTAB_PCREL_HI20, 198) // Deprecated +ELF_RELOC(R_RISCV_CHERI_CJAL, 199) // Deprecated +ELF_RELOC(R_RISCV_CHERI_CCALL, 200) // Deprecated +ELF_RELOC(R_RISCV_CHERI_RVC_CJUMP, 201) // Deprecated // CHERIoT relocations ELF_RELOC(R_RISCV_CHERIOT_COMPARTMENT_HI, 220) diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp index cd019691d4ff1..abf85532fabf2 100644 --- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp @@ -201,8 +201,8 @@ class RISCVAsmParser : public MCTargetAsmParser { // Helper to emit pseudo instruction "cllc" used in PCC-relative addressing. void emitCapLoadLocalCap(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out); - // Helper to emit pseudo instruction "clgc" used in captable addressing with - // the PC-relative ABI. + // Helper to emit pseudo instruction "clgc" used in GOT-indirect addressing + // with the PC-relative ABI. void emitCapLoadGlobalCap(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out); // Helper to emit pseudo instruction "cla.tls.ie" used in initial-exec TLS @@ -237,9 +237,7 @@ class RISCVAsmParser : public MCTargetAsmParser { ParseStatus parseZeroOffsetMemOp(OperandVector &Operands); ParseStatus parseOperandWithSpecifier(OperandVector &Operands); ParseStatus parseBareSymbol(OperandVector &Operands); - template ParseStatus parseCallSymbol(OperandVector &Operands); - template ParseStatus parsePseudoJumpSymbol(OperandVector &Operands); ParseStatus parseJALOffset(OperandVector &Operands); ParseStatus parseVTypeI(OperandVector &Operands); @@ -650,16 +648,6 @@ struct RISCVOperand final : public MCParsedAsmOperand { VK == ELF::R_RISCV_CALL_PLT; } - bool isCCallSymbol() const { - int64_t Imm; - // Must be of 'immediate' type but not a constant. - if (!isImm() || evaluateConstantImm(getImm(), Imm)) - return false; - RISCV::Specifier VK = RISCV::S_None; - return RISCVAsmParser::classifySymbolRef(getImm(), VK) && - VK == RISCV::S_CCALL; - } - bool isPseudoJumpSymbol() const { int64_t Imm; // Must be of 'immediate' type but not a constant. @@ -671,17 +659,6 @@ struct RISCVOperand final : public MCParsedAsmOperand { VK == ELF::R_RISCV_CALL_PLT; } - bool isPseudoCJumpSymbol() const { - int64_t Imm; - // Must be of 'immediate' type but not a constant. - if (!isImm() || evaluateConstantImm(getImm(), Imm)) - return false; - - RISCV::Specifier VK = RISCV::S_None; - return RISCVAsmParser::classifySymbolRef(getImm(), VK) && - VK == RISCV::S_CCALL; - } - bool isTPRelAddSymbol() const { int64_t Imm; // Must be of 'immediate' type but not a constant. @@ -704,16 +681,6 @@ struct RISCVOperand final : public MCParsedAsmOperand { VK == ELF::R_RISCV_TLSDESC_CALL; } - bool isTPRelCIncOffsetSymbol() const { - int64_t Imm; - RISCV::Specifier VK = RISCV::S_None; - // Must be of 'immediate' type but not a constant. - if (!isImm() || evaluateConstantImm(getImm(), Imm)) - return false; - return RISCVAsmParser::classifySymbolRef(getImm(), VK) && - VK == RISCV::S_TPREL_CINCOFFSET; - } - bool isCSRSystemRegister() const { return isSystemRegister(); } // If the last operand of the vsetvli/vsetvli instruction is a constant @@ -1078,10 +1045,18 @@ struct RISCVOperand final : public MCParsedAsmOperand { bool IsConstantImm = evaluateConstantImm(getImm(), Imm); if (!IsConstantImm) { IsValid = RISCVAsmParser::classifySymbolRef(getImm(), VK); - return IsValid && VK == RISCV::S_CHERIOT_COMPARTMENT_HI; + return IsValid && + (VK == ELF::R_RISCV_PCREL_HI20 || VK == ELF::R_RISCV_GOT_HI20 || + VK == ELF::R_RISCV_TLS_GOT_HI20 || + VK == ELF::R_RISCV_TLS_GD_HI20 || + VK == ELF::R_RISCV_TLSDESC_HI20 || + VK == RISCV::S_CHERIOT_COMPARTMENT_HI); } else { return isUInt<20>(Imm) && - (VK == RISCV::S_None || + (VK == RISCV::S_None || VK == ELF::R_RISCV_PCREL_HI20 || + VK == ELF::R_RISCV_GOT_HI20 || VK == ELF::R_RISCV_TLS_GOT_HI20 || + VK == ELF::R_RISCV_TLS_GD_HI20 || + VK == ELF::R_RISCV_TLSDESC_HI20 || VK == RISCV::S_CHERIOT_COMPARTMENT_HI); } } @@ -1851,17 +1826,18 @@ bool RISCVAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, "capability register name or an integer " "in the range"); } - case Match_InvalidPseudoCJumpSymbol: { + case Match_InvalidPseudoJumpSymbol: { SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc(); return Error(ErrorLoc, "operand must be a valid jump target"); } - case Match_InvalidCCallSymbol: { + case Match_InvalidCallSymbol: { SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc(); return Error(ErrorLoc, "operand must be a bare symbol name"); } - case Match_InvalidTPRelCIncOffsetSymbol: { + case Match_InvalidTPRelAddSymbol: { SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc(); - return Error(ErrorLoc, "operand must be a symbol with %tprel_cincoffset modifier"); + return Error(ErrorLoc, + "operand must be a symbol with %tprel_add specifier"); } case Match_InvalidVTypeI: { SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc(); @@ -2470,14 +2446,13 @@ ParseStatus RISCVAsmParser::parseBareSymbol(OperandVector &Operands) { return ParseStatus::Success; } -template ParseStatus RISCVAsmParser::parseCallSymbol(OperandVector &Operands) { SMLoc S = getLoc(); const MCExpr *Res; if (getLexer().getKind() != AsmToken::Identifier) return ParseStatus::NoMatch; - std::string Identifier(getTok().getIdentifier()); + StringRef Identifier(getTok().getIdentifier()); if (getLexer().peekTok().is(AsmToken::At)) { Lex(); @@ -2494,12 +2469,7 @@ ParseStatus RISCVAsmParser::parseCallSymbol(OperandVector &Operands) { } SMLoc E = SMLoc::getFromPointer(S.getPointer() + Identifier.size()); - RISCV::Specifier Kind; - if (IsCap) { - Kind = RISCV::S_CCALL; - } else { - Kind = ELF::R_RISCV_CALL_PLT; - } + RISCV::Specifier Kind = ELF::R_RISCV_CALL_PLT; MCSymbol *Sym = getContext().getOrCreateSymbol(Identifier); Res = MCSymbolRefExpr::create(Sym, getContext()); @@ -2508,7 +2478,6 @@ ParseStatus RISCVAsmParser::parseCallSymbol(OperandVector &Operands) { return ParseStatus::Success; } -template ParseStatus RISCVAsmParser::parsePseudoJumpSymbol(OperandVector &Operands) { SMLoc S = getLoc(); SMLoc E; @@ -2520,9 +2489,7 @@ ParseStatus RISCVAsmParser::parsePseudoJumpSymbol(OperandVector &Operands) { if (Res->getKind() != MCExpr::ExprKind::SymbolRef) return Error(S, "operand must be a valid jump target"); - RISCV::Specifier Kind = - IsCap ? RISCV::S_CCALL : ELF::R_RISCV_CALL_PLT; - Res = MCSpecifierExpr::create(Res, Kind, getContext()); + Res = MCSpecifierExpr::create(Res, ELF::R_RISCV_CALL_PLT, getContext()); Operands.push_back(RISCVOperand::createImm(Res, S, E, isRV64())); return ParseStatus::Success; } @@ -4210,17 +4177,16 @@ void RISCVAsmParser::emitCapLoadLocalCap(MCInst &Inst, SMLoc IDLoc, void RISCVAsmParser::emitCapLoadGlobalCap(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out) { // The capability load global capability pseudo-instruction "clgc" is used in - // captable-indirect addressing of global symbols in the PC-relative ABI: + // GOT-indirect addressing of global symbols in the PC-relative ABI: // clgc rdest, symbol // expands to - // TmpLabel: AUIPCC cdest, %captab_pcrel_hi(symbol) + // TmpLabel: AUIPCC cdest, %got_pcrel_hi(symbol) // CLC cdest, %pcrel_lo(TmpLabel)(cdest) MCOperand DestReg = Inst.getOperand(0); const MCExpr *Symbol = Inst.getOperand(1).getExpr(); unsigned SecondOpcode = isRV64() ? RISCV::CLC_128 : RISCV::CLC_64; - emitAuipccInstPair(DestReg, DestReg, Symbol, - RISCV::S_CAPTAB_PCREL_HI, SecondOpcode, - IDLoc, Out); + emitAuipccInstPair(DestReg, DestReg, Symbol, ELF::R_RISCV_GOT_HI20, + SecondOpcode, IDLoc, Out); } void RISCVAsmParser::emitCapLoadTLSIEAddress(MCInst &Inst, SMLoc IDLoc, @@ -4229,15 +4195,14 @@ void RISCVAsmParser::emitCapLoadTLSIEAddress(MCInst &Inst, SMLoc IDLoc, // in initial-exec TLS model addressing of global symbols: // cla.tls.ie rdest, symbol, tmp // expands to - // TmpLabel: AUIPCC tmp, %tls_ie_captab_pcrel_hi(symbol) + // TmpLabel: AUIPCC tmp, %tls_ie_pcrel_hi(symbol) // CLx rdest, %pcrel_lo(TmpLabel)(tmp) MCOperand DestReg = Inst.getOperand(0); MCOperand TmpReg = Inst.getOperand(1); const MCExpr *Symbol = Inst.getOperand(2).getExpr(); unsigned SecondOpcode = isRV64() ? RISCV::CLD : RISCV::CLW; - emitAuipccInstPair(DestReg, TmpReg, Symbol, - RISCV::S_TLS_IE_CAPTAB_PCREL_HI, SecondOpcode, - IDLoc, Out); + emitAuipccInstPair(DestReg, TmpReg, Symbol, ELF::R_RISCV_TLS_GOT_HI20, + SecondOpcode, IDLoc, Out); } void RISCVAsmParser::emitCapLoadTLSGDCap(MCInst &Inst, SMLoc IDLoc, @@ -4250,8 +4215,7 @@ void RISCVAsmParser::emitCapLoadTLSGDCap(MCInst &Inst, SMLoc IDLoc, // CINCOFFSET rdest, rdest, %pcrel_lo(TmpLabel) MCOperand DestReg = Inst.getOperand(0); const MCExpr *Symbol = Inst.getOperand(1).getExpr(); - emitAuipccInstPair(DestReg, DestReg, Symbol, - RISCV::S_TLS_GD_CAPTAB_PCREL_HI, + emitAuipccInstPair(DestReg, DestReg, Symbol, ELF::R_RISCV_TLS_GD_HI20, RISCV::CIncOffsetImm, IDLoc, Out); } @@ -4263,7 +4227,7 @@ bool RISCVAsmParser::checkPseudoCIncOffsetTPRel(MCInst &Inst, if (Inst.getOperand(1).getReg() != RISCV::X4_Y) { SMLoc ErrorLoc = ((RISCVOperand &)*Operands[2]).getStartLoc(); return Error(ErrorLoc, "the first input operand must be ctp/c4 when using " - "%tprel_cincoffset modifier"); + "%tprel_add specifier"); } return false; diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp index 112d761fb1753..04599d073bc58 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp @@ -88,14 +88,7 @@ MCFixupKindInfo RISCVAsmBackend::getFixupKindInfo(MCFixupKind Kind) const { // Andes fixups {"fixup_riscv_nds_branch_10", 0, 32, 0}, - {"fixup_riscv_captab_pcrel_hi20", 12, 20, 0}, {"fixup_riscv_capability", 0, 0, 0}, - {"fixup_riscv_tprel_cincoffset", 0, 0, 0}, - {"fixup_riscv_tls_ie_captab_pcrel_hi20", 12, 20, 0}, - {"fixup_riscv_tls_gd_captab_pcrel_hi20", 12, 20, 0}, - {"fixup_riscv_cjal", 12, 20, 0}, - {"fixup_riscv_ccall", 0, 64, 0}, - {"fixup_riscv_rvc_cjump", 2, 11, 0}, {"fixup_riscv_cheriot_compartment_hi", 0, 32, 0}, {"fixup_riscv_cheriot_compartment_lo_i", 0, 32, 0}, @@ -137,7 +130,6 @@ bool RISCVAsmBackend::fixupNeedsRelaxationAdvanced(const MCFixup &Fixup, // in the range [-256, 254]. return Offset > 254 || Offset < -256; case RISCV::fixup_riscv_rvc_jump: - case RISCV::fixup_riscv_rvc_cjump: // For compressed jump instructions the immediate must be // in the range [-2048, 2046]. return Offset > 2046 || Offset < -2048; @@ -495,10 +487,7 @@ static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value, switch (Fixup.getKind()) { default: llvm_unreachable("Unknown fixup kind!"); - case RISCV::fixup_riscv_captab_pcrel_hi20: case RISCV::fixup_riscv_capability: - case RISCV::fixup_riscv_tls_ie_captab_pcrel_hi20: - case RISCV::fixup_riscv_tls_gd_captab_pcrel_hi20: llvm_unreachable("Relocation should be unconditionally forced\n"); case FK_Data_1: case FK_Data_2: @@ -522,8 +511,7 @@ static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value, case RISCV::fixup_riscv_pcrel_hi20: // Add 1 if bit 11 is 1, to compensate for low 12 bits being negative. return ((Value + 0x800) >> 12) & 0xfffff; - case RISCV::fixup_riscv_jal: - case RISCV::fixup_riscv_cjal: { + case RISCV::fixup_riscv_jal: { if (!isInt<21>(Value)) Ctx.reportError(Fixup.getLoc(), "fixup value out of range"); if (Value & 0x1) @@ -560,8 +548,7 @@ static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value, return Value; } case RISCV::fixup_riscv_call: - case RISCV::fixup_riscv_call_plt: - case RISCV::fixup_riscv_ccall: { + case RISCV::fixup_riscv_call_plt: { // Jalr will add UpperImm with the sign-extended 12-bit LowerImm, // we need to add 0x800ULL before extract upper bits to reflect the // effect of the sign extension. @@ -569,8 +556,7 @@ static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value, uint64_t LowerImm = Value & 0xfffULL; return UpperImm | ((LowerImm << 20) << 32); } - case RISCV::fixup_riscv_rvc_jump: - case RISCV::fixup_riscv_rvc_cjump: { + case RISCV::fixup_riscv_rvc_jump: { if (!isInt<12>(Value)) Ctx.reportError(Fixup.getLoc(), "fixup value out of range"); // Need to produce offset[11|4|9:8|10|6|7|3:1|5] from the 11-bit Value. @@ -706,10 +692,7 @@ static const MCFixup *getPCRelHiFixup(const MCSpecifierExpr &Expr, continue; auto Kind = F.getKind(); if (!mc::isRelocation(F.getKind())) { - if (Kind == RISCV::fixup_riscv_pcrel_hi20 || - Kind == RISCV::fixup_riscv_captab_pcrel_hi20 || - Kind == RISCV::fixup_riscv_tls_ie_captab_pcrel_hi20 || - Kind == RISCV::fixup_riscv_tls_gd_captab_pcrel_hi20) { + if (Kind == RISCV::fixup_riscv_pcrel_hi20) { *DFOut = DF; return &F; } diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h index 8d241d779a063..786df6aac5bc7 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h @@ -283,15 +283,10 @@ enum { MO_TLSDESC_LOAD_LO = 14, MO_TLSDESC_ADD_LO = 15, MO_TLSDESC_CALL = 16, - MO_CAPTAB_PCREL_HI = 17, - MO_TPREL_CINCOFFSET = 18, - MO_TLS_IE_CAPTAB_PCREL_HI = 19, - MO_TLS_GD_CAPTAB_PCREL_HI = 20, - MO_CCALL = 21, - MO_CHERIOT_COMPARTMENT_HI = 22, - MO_CHERIOT_COMPARTMENT_LO_I = 23, - MO_CHERIOT_COMPARTMENT_LO_S = 24, - MO_CHERIOT_COMPARTMENT_SIZE = 25, + MO_CHERIOT_COMPARTMENT_HI = 17, + MO_CHERIOT_COMPARTMENT_LO_I = 18, + MO_CHERIOT_COMPARTMENT_LO_S = 19, + MO_CHERIOT_COMPARTMENT_SIZE = 20, // Used to differentiate between target-specific "direct" flags and "bitmask" // flags. A machine operand can only have one "direct" flag, but can have diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp index b507f34328adc..b801cda15827e 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp @@ -108,22 +108,6 @@ unsigned RISCVELFObjectWriter::getRelocType(const MCFixup &Fixup, return ELF::R_RISCV_QC_E_CALL_PLT; case RISCV::fixup_riscv_nds_branch_10: return ELF::R_RISCV_NDS_BRANCH_10; - case RISCV::fixup_riscv_captab_pcrel_hi20: - return ELF::R_RISCV_CHERI_CAPTAB_PCREL_HI20; - case RISCV::fixup_riscv_tls_ie_captab_pcrel_hi20: - return ELF::R_RISCV_CHERI_TLS_IE_CAPTAB_PCREL_HI20; - case RISCV::fixup_riscv_tls_gd_captab_pcrel_hi20: - return ELF::R_RISCV_CHERI_TLS_GD_CAPTAB_PCREL_HI20; - case RISCV::fixup_riscv_cjal: - return ELF::R_RISCV_CHERI_CJAL; - case RISCV::fixup_riscv_ccall: { - const auto *STI = getContext().getSubtargetInfo(); - if (STI->hasFeature(RISCV::FeatureVendorXCheriot)) - return ELF::R_RISCV_CHERIOT_CCALL; - return ELF::R_RISCV_CHERI_CCALL; - } - case RISCV::fixup_riscv_rvc_cjump: - return ELF::R_RISCV_CHERI_RVC_CJUMP; case RISCV::fixup_riscv_cheriot_compartment_hi: return ELF::R_RISCV_CHERIOT_COMPARTMENT_HI; case RISCV::fixup_riscv_cheriot_compartment_lo_i: @@ -167,8 +151,6 @@ unsigned RISCVELFObjectWriter::getRelocType(const MCFixup &Fixup, return ELF::R_RISCV_QC_ABS20_U; case RISCV::fixup_riscv_capability: return ELF::R_RISCV_CHERI_CAPABILITY; - case RISCV::fixup_riscv_tprel_cincoffset: - return ELF::R_RISCV_CHERI_TPREL_CINCOFFSET; case RISCV::fixup_riscv_cheriot_compartment_hi: return ELF::R_RISCV_CHERIOT_COMPARTMENT_HI; case RISCV::fixup_riscv_cheriot_compartment_lo_i: diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVFixupKinds.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVFixupKinds.h index c48d2a5fcc8f6..83a98aa37817e 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVFixupKinds.h +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVFixupKinds.h @@ -64,30 +64,8 @@ enum Fixups { // 10-bit fixup for symbol references in the xandesperf branch instruction fixup_riscv_nds_branch_10, - // fixup_riscv_captab_pcrel_hi20 - 20-bit fixup corresponding to - // captab_pcrel_hi(foo) for instructions like auipcc - fixup_riscv_captab_pcrel_hi20, // fixup_riscv_capability - CLen-bit fixup corresponding to .chericap fixup_riscv_capability, - // fixup_riscv_tprel_cincoffset - A fixup corresponding to - // %tprel_cincoffset(foo) for the cincoffset_tls instruction. Used to provide - // a hint to the linker. - fixup_riscv_tprel_cincoffset, - // fixup_riscv_tls_ie_captab_pcrel_hi20 - 20-bit fixup corresponding to - // tls_ie_captab_pcrel_hi(foo) for instructions like auipcc - fixup_riscv_tls_ie_captab_pcrel_hi20, - // fixup_riscv_tls_gd_captab_pcrel_hi20 - 20-bit fixup corresponding to - // tls_gd_captab_pcrel_hi(foo) for instructions like auipcc - fixup_riscv_tls_gd_captab_pcrel_hi20, - // fixup_riscv_cjal - 20-bit fixup for symbol references in the cjal - // instruction - fixup_riscv_cjal, - // fixup_riscv_call - A fixup representing a ccall attached to the auipcc - // instruction in a pair composed of adjacent auipcc+cjalr instructions. - fixup_riscv_ccall, - // fixup_riscv_rvc_cjump - 11-bit fixup for symbol references in the - // compressed capability jump instruction - fixup_riscv_rvc_cjump, // $cgp- or $pcc-relative global, used with auicgp / auipcc instructions fixup_riscv_cheriot_compartment_hi, diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp index 2684e62ef9b79..d6fe7f2adf3b3 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp @@ -141,12 +141,6 @@ static void addFixup(SmallVectorImpl &Fixups, uint32_t Offset, case RISCV::fixup_riscv_qc_e_branch: case RISCV::fixup_riscv_qc_e_call_plt: case RISCV::fixup_riscv_nds_branch_10: - case RISCV::fixup_riscv_captab_pcrel_hi20: - case RISCV::fixup_riscv_tls_ie_captab_pcrel_hi20: - case RISCV::fixup_riscv_tls_gd_captab_pcrel_hi20: - case RISCV::fixup_riscv_cjal: - case RISCV::fixup_riscv_ccall: - case RISCV::fixup_riscv_rvc_cjump: PCRel = true; } Fixups.push_back(MCFixup::create(Offset, Value, Kind, PCRel)); @@ -300,14 +294,13 @@ void RISCVMCCodeEmitter::expandCIncOffsetTPRel( "Expected expression as third input to CTP-relative cincoffset"); const MCSpecifierExpr *Expr = dyn_cast(SrcSymbol.getExpr()); - assert(Expr && Expr->getSpecifier() == RISCV::S_TPREL_CINCOFFSET && - "Expected tprel_cincoffset relocation on CTP-relative symbol"); + assert(Expr && Expr->getSpecifier() == ELF::R_RISCV_TPREL_ADD && + "Expected tprel_add relocation on CTP-relative symbol"); - // Emit the correct tprel_cincoffset relocation for the symbol. - Fixups.push_back(MCFixup::create( - 0, Expr, MCFixupKind(RISCV::fixup_riscv_tprel_cincoffset))); + // Emit the correct tprel_add relocation for the symbol. + addFixup(Fixups, 0, Expr, ELF::R_RISCV_TPREL_ADD); - // Emit fixup_riscv_relax for tprel_cincoffset where the relax feature is enabled. + // Emit fixup_riscv_relax for tprel_add where the relax feature is enabled. if (STI.getFeatureBits()[RISCV::FeatureRelax]) { const MCConstantExpr *Dummy = MCConstantExpr::create(0, Ctx); Fixups.push_back(MCFixup::create(0, Dummy, ELF::R_RISCV_RELAX)); @@ -740,23 +733,6 @@ uint64_t RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo, FixupKind = RISCV::fixup_riscv_qc_abs20_u; RelaxCandidate = true; break; - case RISCV::S_CAPTAB_PCREL_HI: - FixupKind = RISCV::fixup_riscv_captab_pcrel_hi20; - break; - case RISCV::S_TPREL_CINCOFFSET: - // See VK_TPREL_ADD. - llvm_unreachable( - "VK_TPREL_CINCOFFSET should not represent an instruction operand"); - case RISCV::S_TLS_IE_CAPTAB_PCREL_HI: - FixupKind = RISCV::fixup_riscv_tls_ie_captab_pcrel_hi20; - break; - case RISCV::S_TLS_GD_CAPTAB_PCREL_HI: - FixupKind = RISCV::fixup_riscv_tls_gd_captab_pcrel_hi20; - break; - case RISCV::S_CCALL: - FixupKind = RISCV::fixup_riscv_ccall; - RelaxCandidate = true; - break; case RISCV::S_CHERIOT_COMPARTMENT_HI: FixupKind = RISCV::fixup_riscv_cheriot_compartment_hi; RelaxCandidate = true; @@ -778,19 +754,13 @@ uint64_t RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo, if (MIFrm == RISCVII::InstFormatJ) { FixupKind = RISCV::fixup_riscv_jal; AsmRelaxToLinkerRelaxableWithFeature(RISCV::FeatureVendorXqcilb); - } else if (Desc.getOpcode() == RISCV::CJAL) { - FixupKind = RISCV::fixup_riscv_cjal; } else if (MIFrm == RISCVII::InstFormatB) { FixupKind = RISCV::fixup_riscv_branch; // This might be assembler relaxed to `b; jal` but we cannot relax // the `jal` again in the assembler. } else if (MIFrm == RISCVII::InstFormatCJ) { - if (Desc.getOpcode() == RISCV::C_CJAL) - FixupKind = RISCV::fixup_riscv_rvc_cjump; - else { - FixupKind = RISCV::fixup_riscv_rvc_jump; - AsmRelaxToLinkerRelaxableWithFeature(RISCV::FeatureVendorXqcilb); - } + FixupKind = RISCV::fixup_riscv_rvc_jump; + AsmRelaxToLinkerRelaxableWithFeature(RISCV::FeatureVendorXqcilb); } else if (MIFrm == RISCVII::InstFormatCB) { FixupKind = RISCV::fixup_riscv_rvc_branch; // This might be assembler relaxed to `b; jal` but we cannot relax diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp index 7f77688ee99b0..9ab1976a99e43 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp @@ -46,10 +46,6 @@ RISCV::Specifier RISCV::parseSpecifierName(StringRef name) { // Used in data directives .Case("pltpcrel", ELF::R_RISCV_PLT32) .Case("gotpcrel", ELF::R_RISCV_GOT32_PCREL) - .Case("captab_pcrel_hi", RISCV::S_CAPTAB_PCREL_HI) - .Case("tprel_cincoffset", RISCV::S_TPREL_CINCOFFSET) - .Case("tls_ie_captab_pcrel_hi", RISCV::S_TLS_IE_CAPTAB_PCREL_HI) - .Case("tls_gd_captab_pcrel_hi", RISCV::S_TLS_GD_CAPTAB_PCREL_HI) .Case("cheriot_compartment_hi", RISCV::S_CHERIOT_COMPARTMENT_HI) .Case("cheriot_compartment_lo_i", RISCV::S_CHERIOT_COMPARTMENT_LO_I) .Case("cheriot_compartment_lo_s", RISCV::S_CHERIOT_COMPARTMENT_LO_S) @@ -89,18 +85,10 @@ StringRef RISCV::getSpecifierName(Specifier S) { return "tlsdesc_call"; case ELF::R_RISCV_TLS_GD_HI20: return "tls_gd_pcrel_hi"; - case RISCV::S_CAPTAB_PCREL_HI: - return "captab_pcrel_hi"; - case RISCV::S_TPREL_CINCOFFSET: - return "tprel_cincoffset"; - case RISCV::S_TLS_IE_CAPTAB_PCREL_HI: - return "tls_ie_captab_pcrel_hi"; - case RISCV::S_TLS_GD_CAPTAB_PCREL_HI: - return "tls_gd_captab_pcrel_hi"; + case ELF::R_RISCV_CALL: + return "call"; case ELF::R_RISCV_CALL_PLT: return "call_plt"; - case RISCV::S_CCALL: - return "ccall"; case RISCV::S_CHERIOT_COMPARTMENT_HI: return "cheriot_compartment_hi"; case RISCV::S_CHERIOT_COMPARTMENT_LO_I: diff --git a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp index 4068d974cf8ab..5201107fb9b20 100644 --- a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp +++ b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp @@ -1315,21 +1315,6 @@ static MCOperand lowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym, case RISCVII::MO_TLSDESC_CALL: Kind = ELF::R_RISCV_TLSDESC_CALL; break; - case RISCVII::MO_CAPTAB_PCREL_HI: - Kind = RISCV::S_CAPTAB_PCREL_HI; - break; - case RISCVII::MO_TPREL_CINCOFFSET: - Kind = RISCV::S_TPREL_CINCOFFSET; - break; - case RISCVII::MO_TLS_IE_CAPTAB_PCREL_HI: - Kind = RISCV::S_TLS_IE_CAPTAB_PCREL_HI; - break; - case RISCVII::MO_TLS_GD_CAPTAB_PCREL_HI: - Kind = RISCV::S_TLS_GD_CAPTAB_PCREL_HI; - break; - case RISCVII::MO_CCALL: - Kind = RISCV::S_CCALL; - break; case RISCVII::MO_CHERIOT_COMPARTMENT_HI: Kind = RISCV::S_CHERIOT_COMPARTMENT_HI; break; diff --git a/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp b/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp index 3ee61aeb2e500..69f67893f7fb7 100644 --- a/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp +++ b/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp @@ -800,7 +800,7 @@ bool RISCVExpandPseudo::expandCapLoadGlobalCap( const auto &STI = MF->getSubtarget(); unsigned SecondOpcode = STI.is64Bit() ? RISCV::CLC_128 : RISCV::CLC_64; - return expandAuipccInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_CAPTAB_PCREL_HI, + return expandAuipccInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_GOT_HI, SecondOpcode); } @@ -811,16 +811,14 @@ bool RISCVExpandPseudo::expandCapLoadTLSIEAddress( const auto &STI = MF->getSubtarget(); unsigned SecondOpcode = STI.is64Bit() ? RISCV::CLD : RISCV::CLW; - return expandAuipccInstPair(MBB, MBBI, NextMBBI, - RISCVII::MO_TLS_IE_CAPTAB_PCREL_HI, + return expandAuipccInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_TLS_GOT_HI, SecondOpcode); } bool RISCVExpandPseudo::expandCapLoadTLSGDCap( MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, MachineBasicBlock::iterator &NextMBBI) { - return expandAuipccInstPair(MBB, MBBI, NextMBBI, - RISCVII::MO_TLS_GD_CAPTAB_PCREL_HI, + return expandAuipccInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_TLS_GD_HI, RISCV::CIncOffsetImm); } diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 312b95890c7fa..69a38eddefe54 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -8999,9 +8999,9 @@ SDValue RISCVTargetLowering::getAddr(NodeTy *N, EVT Ty, SelectionDAG &DAG, // for read-only constants (e.g. floating-point constant-pools). return DAG.getNode(RISCVISD::CLLC, DL, Ty, Addr); } - // Generate a sequence to load a capability from the captable. This - // generates the pattern (PseudoCLGC sym), which expands to - // (clc (auipcc %captab_pcrel_hi(sym)) %pcrel_lo(auipc)). + // Generate a sequence to load a capability from the GOT. This generates + // the pattern (PseudoCLGC sym), which expands to + // (clc (auipcc %got_pcrel_hi(sym)) %pcrel_lo(auipc)). MachineFunction &MF = DAG.getMachineFunction(); MachineMemOperand *MemOp = MF.getMachineMemOperand( MachinePointerInfo::getGOT(MF), @@ -9093,14 +9093,14 @@ SDValue RISCVTargetLowering::lowerGlobalAddress(SDValue Op, GlobalAddressSDNode *N = cast(Op); assert(N->getOffset() == 0 && "unexpected offset in global node"); - // External variables always have to be loaded from the captable to get bounds - // and to allow for them to be provided by another DSO without requiring copy + // External variables always have to be loaded from the GOT to get bounds and + // to allow for them to be provided by another DSO without requiring copy // relocations. // Read-only accesses in the same DSO *could* theoretically use pc-relative // addressing, but that would mean we get a capability bounded to the $pcc // bounds and therefore would not be checked when we pass the reference to - // another function. Therefore, we always load from the captable for all - // global variables. + // another function. Therefore, we always load from the GOT for all global + // variables. const GlobalValue *GV = N->getGlobal(); if (auto *GVar = llvm::dyn_cast(GV)) { @@ -9162,10 +9162,10 @@ SDValue RISCVTargetLowering::getStaticTLSAddr(GlobalAddressSDNode *N, if (RISCVABI::isCheriPureCapABI(Subtarget.getTargetABI())) { if (UseGOT) { - // Use PC-relative addressing to access the captable for this TLS symbol, - // then load the address from the captable and add the thread pointer. - // This generates the pattern (PseudoCLA_TLS_IE sym), which expands to - // (cld (auipcc %tls_ie_captab_pcrel_hi(sym)) %pcrel_lo(auipc)). + // Use PC-relative addressing to access the GOT for this TLS symbol, then + // load the address from the GOT and add the thread pointer. This + // generates the pattern (PseudoCLA_TLS_IE sym), which expands to + // (cld (auipcc %tls_ie_pcrel_hi(sym)) %pcrel_lo(auipc)). SDValue Addr = DAG.getTargetGlobalAddress(GV, DL, Ty, 0, 0); MachineFunction &MF = DAG.getMachineFunction(); MachineMemOperand *MemOp = MF.getMachineMemOperand( @@ -9186,12 +9186,12 @@ SDValue RISCVTargetLowering::getStaticTLSAddr(GlobalAddressSDNode *N, // pointer, with the appropriate adjustment for the thread pointer offset. // This generates the pattern // (cincoffset (cincoffset_tprel (lui %tprel_hi(sym)) - // ctp %tprel_cincoffset(sym)) + // ctp %tprel_add(sym)) // %tprel_lo(sym)) SDValue AddrHi = DAG.getTargetGlobalAddress(GV, DL, XLenVT, 0, RISCVII::MO_TPREL_HI); SDValue AddrCIncOffset = - DAG.getTargetGlobalAddress(GV, DL, Ty, 0, RISCVII::MO_TPREL_CINCOFFSET); + DAG.getTargetGlobalAddress(GV, DL, Ty, 0, RISCVII::MO_TPREL_ADD); SDValue AddrLo = DAG.getTargetGlobalAddress(GV, DL, XLenVT, 0, RISCVII::MO_TPREL_LO); @@ -9260,7 +9260,7 @@ SDValue RISCVTargetLowering::getDynamicTLSAddr(GlobalAddressSDNode *N, // // For pure capability TLS, this generates the pattern (PseudoCLC_TLS_GD sym), // which expands to - // (cincoffset (auipcc %tls_gd_captab_pcrel_hi(sym)) %pcrel_lo(auipc)). + // (cincoffset (auipcc %tls_gd_pcrel_hi(sym)) %pcrel_lo(auipc)). unsigned Opcode = RISCVABI::isCheriPureCapABI(Subtarget.getTargetABI()) ? RISCV::PseudoCLC_TLS_GD : RISCV::PseudoLA_TLS_GD; @@ -23506,26 +23506,21 @@ SDValue RISCVTargetLowering::LowerCall(CallLoweringInfo &CLI, } } else if (GlobalAddressSDNode *S = dyn_cast(Callee)) { const GlobalValue *GV = S->getGlobal(); - if (RISCVABI::isCheriPureCapABI(Subtarget.getTargetABI())) { - if (UseLegacyIndirectPurecapCalls) { - Callee = getAddr(S, Callee.getValueType(), DAG, /*IsLocal=*/false, + if (RISCVABI::isCheriPureCapABI(Subtarget.getTargetABI()) && + UseLegacyIndirectPurecapCalls) { + Callee = getAddr(S, Callee.getValueType(), DAG, /*IsLocal=*/false, /*CanDeriveFromPcc=*/true); - } else { - Callee = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, RISCVII::MO_CCALL); - } } else { Callee = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, RISCVII::MO_CALL); } } else if (ExternalSymbolSDNode *S = dyn_cast(Callee)) { - if (RISCVABI::isCheriPureCapABI(Subtarget.getTargetABI())) { - if (UseLegacyIndirectPurecapCalls) { - Callee = getAddr(S, Callee.getValueType(), DAG, /*IsLocal=*/false, + if (RISCVABI::isCheriPureCapABI(Subtarget.getTargetABI()) && + UseLegacyIndirectPurecapCalls) { + Callee = getAddr(S, Callee.getValueType(), DAG, /*IsLocal=*/false, /*CanDeriveFromPcc=*/true); - } else { - Callee = DAG.getTargetExternalFunctionSymbol(S->getSymbol(), RISCVII::MO_CCALL); - } } else { - Callee = DAG.getTargetExternalFunctionSymbol(S->getSymbol(), RISCVII::MO_CALL); + Callee = + DAG.getTargetExternalFunctionSymbol(S->getSymbol(), RISCVII::MO_CALL); } } diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp index 45fa71746e66c..412d8713e552c 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp @@ -3538,16 +3538,11 @@ RISCVInstrInfo::getSerializableDirectMachineOperandTargetFlags() const { {MO_TLSDESC_LOAD_LO, "riscv-tlsdesc-load-lo"}, {MO_TLSDESC_ADD_LO, "riscv-tlsdesc-add-lo"}, {MO_TLSDESC_CALL, "riscv-tlsdesc-call"}, - {MO_CAPTAB_PCREL_HI, "riscv-captab-pcrel-hi"}, - {MO_TPREL_CINCOFFSET, "riscv-tprel-cincoffset"}, - {MO_TLS_IE_CAPTAB_PCREL_HI, "riscv-tls-ie-captab-pcrel-hi"}, - {MO_TLS_GD_CAPTAB_PCREL_HI, "riscv-tls-gd-captab-pcrel-hi"}, - {MO_CCALL, "riscv-ccall"}, {MO_CHERIOT_COMPARTMENT_HI, "riscv-cheriot-compartment-hi"}, {MO_CHERIOT_COMPARTMENT_LO_I, "riscv-cheriot-compartment-lo-i"}, {MO_CHERIOT_COMPARTMENT_LO_S, "riscv-cheriot-compartment-lo-s"}, {MO_CHERIOT_COMPARTMENT_SIZE, "riscv-cheriot-compartment-size"}, - }; + }; return ArrayRef(TargetFlags); } @@ -3780,21 +3775,18 @@ MachineBasicBlock::iterator RISCVInstrInfo::insertOutlinedCall( It = MBB.insert( It, BuildMI(MF, DebugLoc(), get(IsPurecap ? RISCV::PseudoCTAIL : RISCV::PseudoTAIL)) - .addGlobalAddress( - M.getNamedValue(MF.getName()), - /*Offset=*/0, - IsPurecap ? RISCVII::MO_CCALL : RISCVII::MO_CALL)); + .addGlobalAddress(M.getNamedValue(MF.getName()), + /*Offset=*/0, RISCVII::MO_CALL)); return It; } // Add in a call instruction to the outlined function at the given location. It = MBB.insert( - It, - BuildMI(MF, DebugLoc(), - get(IsPurecap ? RISCV::PseudoCCALLReg : RISCV::PseudoCALLReg), - IsPurecap ? RISCV::X5_Y : RISCV::X5) - .addGlobalAddress(M.getNamedValue(MF.getName()), 0, - IsPurecap ? RISCVII::MO_CCALL : RISCVII::MO_CALL)); + It, BuildMI(MF, DebugLoc(), + get(IsPurecap ? RISCV::PseudoCCALLReg : RISCV::PseudoCALLReg), + IsPurecap ? RISCV::X5_Y : RISCV::X5) + .addGlobalAddress(M.getNamedValue(MF.getName()), 0, + RISCVII::MO_CALL)); return It; } diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXCheri.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXCheri.td index 53c8e98bc1a26..89dfee7c391dd 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoXCheri.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXCheri.td @@ -61,36 +61,10 @@ def riscv_cap_bounds_set // Operand and SDNode transformation definitions. //===----------------------------------------------------------------------===// -def CCallSymbol : AsmOperandClass { - let Name = "CCallSymbol"; - let RenderMethod = "addImmOperands"; - let DiagnosticType = "InvalidCCallSymbol"; - let ParserMethod = "parseCallSymbol"; -} - -def cap_call_symbol : Operand { let ParserMatchClass = CCallSymbol; } - -def PseudoCJumpSymbol : AsmOperandClass { - let Name = "PseudoCJumpSymbol"; - let RenderMethod = "addImmOperands"; - let DiagnosticType = "InvalidPseudoCJumpSymbol"; - let ParserMethod = "parsePseudoJumpSymbol"; -} +def cap_call_symbol : Operand { let ParserMatchClass = CallSymbol; } def pseudo_cap_jump_symbol : Operand { - let ParserMatchClass = PseudoCJumpSymbol; -} - -def TPRelCIncOffsetSymbol : AsmOperandClass { - let Name = "TPRelCIncOffsetSymbol"; - let RenderMethod = "addImmOperands"; - let DiagnosticType = "InvalidTPRelCIncOffsetSymbol"; - let ParserMethod = "parseOperandWithSpecifier"; -} - -// A bare symbol with the %tprel_add variant. -def tprel_cincoffset_symbol : Operand { - let ParserMatchClass = TPRelCIncOffsetSymbol; + let ParserMatchClass = PseudoJumpSymbol; } def CheriZeroOffsetMemOpOperand : AsmOperandClass { @@ -1372,8 +1346,8 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCodeGenOnly = 0, let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCodeGenOnly = 0 in def PseudoCIncOffsetTPRel : Pseudo<(outs YGPR:$rd), - (ins YGPR:$rs1, GPR:$rs2, tprel_cincoffset_symbol:$src), [], - "cincoffset", "$rd, $rs1, $rs2, $src">; + (ins YGPR:$rs1, GPR:$rs2, tprel_add_symbol:$src), [], "cincoffset", + "$rd, $rs1, $rs2, $src">; } let Predicates = [HasCheri, HasStdExtD, IsRV32] in { diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/bounded-allocas-lifetimes.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/bounded-allocas-lifetimes.ll index 17527cc770795..3ee8295a51703 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/bounded-allocas-lifetimes.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/bounded-allocas-lifetimes.ll @@ -17,7 +17,7 @@ define void @static_alloca() { ; CHECK-NEXT: LIFETIME_START %stack.0 ; CHECK-NEXT: ADJCALLSTACKDOWNCAP 0, 0, implicit-def dead $x2_y, implicit $x2_y ; CHECK-NEXT: $x10_y = COPY [[CSetBoundsImm]] - ; CHECK-NEXT: PseudoCCALL target-flags(riscv-ccall) @use, csr_il32pc64f_l64pc128f, implicit-def dead $x1_y, implicit $x10_y, implicit-def $x2_y + ; CHECK-NEXT: PseudoCCALL target-flags(riscv-call) @use, csr_il32pc64f_l64pc128f, implicit-def dead $x1_y, implicit $x10_y, implicit-def $x2_y ; CHECK-NEXT: ADJCALLSTACKUPCAP 0, 0, implicit-def dead $x2_y, implicit $x2_y ; CHECK-NEXT: LIFETIME_END %stack.0 ; CHECK-NEXT: PseudoCRET @@ -54,7 +54,7 @@ define void @dynamic_alloca(i64 zeroext %n) { ; CHECK-NEXT: [[CSetBounds1:%[0-9]+]]:ygpr = CSetBounds killed [[CSetBounds]], [[SLLI]] ; CHECK-NEXT: ADJCALLSTACKDOWNCAP 0, 0, implicit-def dead $x2_y, implicit $x2_y ; CHECK-NEXT: $x10_y = COPY [[CSetBounds1]] - ; CHECK-NEXT: PseudoCCALL target-flags(riscv-ccall) @use, csr_il32pc64f_l64pc128f, implicit-def dead $x1_y, implicit $x10_y, implicit-def $x2_y + ; CHECK-NEXT: PseudoCCALL target-flags(riscv-call) @use, csr_il32pc64f_l64pc128f, implicit-def dead $x1_y, implicit $x10_y, implicit-def $x2_y ; CHECK-NEXT: ADJCALLSTACKUPCAP 0, 0, implicit-def dead $x2_y, implicit $x2_y ; CHECK-NEXT: PseudoCRET %1 = alloca i32, i64 %n, align 4, addrspace(200) diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/cheri-intrinsics-folding-broken-module-regression.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/cheri-intrinsics-folding-broken-module-regression.ll index 5af50f984d024..aa8bb5d7e3839 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/cheri-intrinsics-folding-broken-module-regression.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/cheri-intrinsics-folding-broken-module-regression.ll @@ -19,10 +19,10 @@ define void @g(i32 %x, i32 %y) addrspace(200) nounwind { ; ASM-LABEL: g: ; ASM: # %bb.0: ; ASM-NEXT: .LBB0_1: # Label of block must be emitted -; ASM-NEXT: auipcc a2, %captab_pcrel_hi(d) +; ASM-NEXT: auipcc a2, %got_pcrel_hi(d) ; ASM-NEXT: clc a2, %pcrel_lo(.LBB0_1)(a2) ; ASM-NEXT: .LBB0_2: # Label of block must be emitted -; ASM-NEXT: auipcc a3, %captab_pcrel_hi(e) +; ASM-NEXT: auipcc a3, %got_pcrel_hi(e) ; ASM-NEXT: clc a3, %pcrel_lo(.LBB0_2)(a3) ; ASM-NEXT: cincoffset a0, a2, a0 ; ASM-NEXT: cincoffset a0, a0, a1 diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/memcpy-from-constant.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/memcpy-from-constant.ll index 0e5268d6da6ec..d09e5bbcb70a9 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/memcpy-from-constant.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/memcpy-from-constant.ll @@ -46,7 +46,7 @@ define linkonce_odr void @copy_from_ptr_constant(ptr addrspace(200) %dst) addrsp ; CHECK: # %bb.0: # %do.body ; CHECK-NEXT: .LBB3_1: # %do.body ; CHECK-NEXT: # Label of block must be emitted -; CHECK-NEXT: auipcc a1, %captab_pcrel_hi(constant_ptrs) +; CHECK-NEXT: auipcc a1, %got_pcrel_hi(constant_ptrs) ; CHECK-NEXT: clc a1, %pcrel_lo(.LBB3_1)(a1) ; CHECK-NEXT: clc a1, 0(a1) ; CHECK-NEXT: csc a1, 0(a0) @@ -61,7 +61,7 @@ define linkonce_odr void @copy_from_ptr_constant_with_offset(ptr addrspace(200) ; CHECK: # %bb.0: # %do.body ; CHECK-NEXT: .LBB4_1: # %do.body ; CHECK-NEXT: # Label of block must be emitted -; CHECK-NEXT: auipcc a1, %captab_pcrel_hi(constant_ptrs) +; CHECK-NEXT: auipcc a1, %got_pcrel_hi(constant_ptrs) ; CHECK-NEXT: clc a1, %pcrel_lo(.LBB4_1)(a1) ; CHECK-NEXT: clc a1, 8(a1) ; CHECK-NEXT: csc a1, 0(a0) @@ -110,7 +110,7 @@ define linkonce_odr void @copy_from_ptr_constant_preserve(ptr addrspace(200) %ds ; CHECK: # %bb.0: # %do.body ; CHECK-NEXT: .LBB8_1: # %do.body ; CHECK-NEXT: # Label of block must be emitted -; CHECK-NEXT: auipcc a1, %captab_pcrel_hi(constant_ptrs) +; CHECK-NEXT: auipcc a1, %got_pcrel_hi(constant_ptrs) ; CHECK-NEXT: clc a1, %pcrel_lo(.LBB8_1)(a1) ; CHECK-NEXT: clc a1, 0(a1) ; CHECK-NEXT: csc a1, 0(a0) @@ -125,7 +125,7 @@ define linkonce_odr void @copy_from_ptr_constant_with_offset_preserve(ptr addrsp ; CHECK: # %bb.0: # %do.body ; CHECK-NEXT: .LBB9_1: # %do.body ; CHECK-NEXT: # Label of block must be emitted -; CHECK-NEXT: auipcc a1, %captab_pcrel_hi(constant_ptrs) +; CHECK-NEXT: auipcc a1, %got_pcrel_hi(constant_ptrs) ; CHECK-NEXT: clc a1, %pcrel_lo(.LBB9_1)(a1) ; CHECK-NEXT: clc a1, 8(a1) ; CHECK-NEXT: csc a1, 0(a0) diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/memcpy-zeroinit.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/memcpy-zeroinit.ll index 3e39289f2e679..8b90a36cd6ebd 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/memcpy-zeroinit.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/memcpy-zeroinit.ll @@ -27,7 +27,7 @@ define void @_thr_umutex_init_volatile(%struct.umutex addrspace(200)* %mtx) loca ; CHECK-LABEL: _thr_umutex_init_volatile: ; CHECK: # %bb.0: ; CHECK-NEXT: .LBB1_1: # Label of block must be emitted -; CHECK-NEXT: auipcc a1, %captab_pcrel_hi(_thr_umutex_init.default_mtx) +; CHECK-NEXT: auipcc a1, %got_pcrel_hi(_thr_umutex_init.default_mtx) ; CHECK-NEXT: clc a1, %pcrel_lo(.LBB1_1)(a1) ; CHECK-NEXT: clc a2, 40(a1) ; CHECK-NEXT: csc a2, 40(a0) diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/strcpy-to-memcpy-no-tags.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/strcpy-to-memcpy-no-tags.ll index aa4ccd78c957b..e57ec2b63f998 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/strcpy-to-memcpy-no-tags.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/strcpy-to-memcpy-no-tags.ll @@ -84,7 +84,7 @@ define void @test_strcat_to_memcpy(ptr addrspace(200) align 4 %dst) addrspace(20 ; CHECK-ASM-NEXT: cincoffset a0, s0, a0 ; CHECK-ASM-NEXT: .LBB2_1: # %entry ; CHECK-ASM-NEXT: # Label of block must be emitted -; CHECK-ASM-NEXT: auipcc a1, %captab_pcrel_hi(.Lstr) +; CHECK-ASM-NEXT: auipcc a1, %got_pcrel_hi(.Lstr) ; CHECK-ASM-NEXT: clc a1, %pcrel_lo(.LBB2_1)(a1) ; CHECK-ASM-NEXT: li a2, 17 ; CHECK-ASM-NEXT: ccall memcpy @@ -113,7 +113,7 @@ define void @test_strncpy_to_memcpy(ptr addrspace(200) align 4 %dst) addrspace(2 ; CHECK-ASM-NEXT: csc ra, 8(sp) # 8-byte Folded Spill ; CHECK-ASM-NEXT: .LBB3_1: # %entry ; CHECK-ASM-NEXT: # Label of block must be emitted -; CHECK-ASM-NEXT: auipcc a1, %captab_pcrel_hi(.Lstr) +; CHECK-ASM-NEXT: auipcc a1, %got_pcrel_hi(.Lstr) ; CHECK-ASM-NEXT: clc a1, %pcrel_lo(.LBB3_1)(a1) ; CHECK-ASM-NEXT: li a2, 17 ; CHECK-ASM-NEXT: li a3, 0 @@ -140,7 +140,7 @@ define void @test_stpncpy_to_memcpy(ptr addrspace(200) align 4 %dst) addrspace(2 ; CHECK-ASM-NEXT: csc ra, 8(sp) # 8-byte Folded Spill ; CHECK-ASM-NEXT: .LBB4_1: # %entry ; CHECK-ASM-NEXT: # Label of block must be emitted -; CHECK-ASM-NEXT: auipcc a1, %captab_pcrel_hi(.Lstr) +; CHECK-ASM-NEXT: auipcc a1, %got_pcrel_hi(.Lstr) ; CHECK-ASM-NEXT: clc a1, %pcrel_lo(.LBB4_1)(a1) ; CHECK-ASM-NEXT: li a2, 17 ; CHECK-ASM-NEXT: li a3, 0 diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/unaligned-loads-stores-purecap.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/unaligned-loads-stores-purecap.ll index 37c1870da0a42..808807f712bfe 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/unaligned-loads-stores-purecap.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/unaligned-loads-stores-purecap.ll @@ -11,7 +11,7 @@ define i64 @load_global_i64_align_1(i64 %y) addrspace(200) nounwind { ; CHECK-LABEL: load_global_i64_align_1: ; CHECK: # %bb.0: ; CHECK-NEXT: .LBB0_1: # Label of block must be emitted -; CHECK-NEXT: auipcc a0, %captab_pcrel_hi(a1) +; CHECK-NEXT: auipcc a0, %got_pcrel_hi(a1) ; CHECK-NEXT: clc a0, %pcrel_lo(.LBB0_1)(a0) ; CHECK-NEXT: clbu a1, 0(a0) ; CHECK-NEXT: clbu a2, 1(a0) @@ -42,7 +42,7 @@ define i64 @load_global_i64_align_2(i64 %y) addrspace(200) nounwind { ; CHECK-LABEL: load_global_i64_align_2: ; CHECK: # %bb.0: ; CHECK-NEXT: .LBB1_1: # Label of block must be emitted -; CHECK-NEXT: auipcc a0, %captab_pcrel_hi(a2) +; CHECK-NEXT: auipcc a0, %got_pcrel_hi(a2) ; CHECK-NEXT: clc a0, %pcrel_lo(.LBB1_1)(a0) ; CHECK-NEXT: clhu a1, 2(a0) ; CHECK-NEXT: clhu a2, 0(a0) @@ -61,7 +61,7 @@ define i64 @load_global_i64_align_4(i64 %y) addrspace(200) nounwind { ; CHECK-LABEL: load_global_i64_align_4: ; CHECK: # %bb.0: ; CHECK-NEXT: .LBB2_1: # Label of block must be emitted -; CHECK-NEXT: auipcc a1, %captab_pcrel_hi(a4) +; CHECK-NEXT: auipcc a1, %got_pcrel_hi(a4) ; CHECK-NEXT: clc a1, %pcrel_lo(.LBB2_1)(a1) ; CHECK-NEXT: clw a0, 0(a1) ; CHECK-NEXT: clw a1, 4(a1) @@ -74,7 +74,7 @@ define i64 @load_global_i64_align_8(i64 %y) addrspace(200) nounwind { ; CHECK-LABEL: load_global_i64_align_8: ; CHECK: # %bb.0: ; CHECK-NEXT: .LBB3_1: # Label of block must be emitted -; CHECK-NEXT: auipcc a1, %captab_pcrel_hi(a8) +; CHECK-NEXT: auipcc a1, %got_pcrel_hi(a8) ; CHECK-NEXT: clc a1, %pcrel_lo(.LBB3_1)(a1) ; CHECK-NEXT: clw a0, 0(a1) ; CHECK-NEXT: clw a1, 4(a1) @@ -87,7 +87,7 @@ define void @store_global_i64_align_1(i64 %y) addrspace(200) nounwind { ; CHECK-LABEL: store_global_i64_align_1: ; CHECK: # %bb.0: ; CHECK-NEXT: .LBB4_1: # Label of block must be emitted -; CHECK-NEXT: auipcc a2, %captab_pcrel_hi(a1) +; CHECK-NEXT: auipcc a2, %got_pcrel_hi(a1) ; CHECK-NEXT: clc a2, %pcrel_lo(.LBB4_1)(a2) ; CHECK-NEXT: srli a3, a1, 24 ; CHECK-NEXT: csb a3, 7(a2) @@ -112,7 +112,7 @@ define void @store_global_i64_align_2(i64 %y) addrspace(200) nounwind { ; CHECK-LABEL: store_global_i64_align_2: ; CHECK: # %bb.0: ; CHECK-NEXT: .LBB5_1: # Label of block must be emitted -; CHECK-NEXT: auipcc a2, %captab_pcrel_hi(a2) +; CHECK-NEXT: auipcc a2, %got_pcrel_hi(a2) ; CHECK-NEXT: clc a2, %pcrel_lo(.LBB5_1)(a2) ; CHECK-NEXT: csh a1, 4(a2) ; CHECK-NEXT: srli a1, a1, 16 @@ -129,7 +129,7 @@ define void @store_global_i64_align_4(i64 %y) addrspace(200) nounwind { ; CHECK-LABEL: store_global_i64_align_4: ; CHECK: # %bb.0: ; CHECK-NEXT: .LBB6_1: # Label of block must be emitted -; CHECK-NEXT: auipcc a2, %captab_pcrel_hi(a4) +; CHECK-NEXT: auipcc a2, %got_pcrel_hi(a4) ; CHECK-NEXT: clc a2, %pcrel_lo(.LBB6_1)(a2) ; CHECK-NEXT: csw a1, 4(a2) ; CHECK-NEXT: csw a0, 0(a2) @@ -142,7 +142,7 @@ define void @store_global_i64_align_8(i64 %y) addrspace(200) nounwind { ; CHECK-LABEL: store_global_i64_align_8: ; CHECK: # %bb.0: ; CHECK-NEXT: .LBB7_1: # Label of block must be emitted -; CHECK-NEXT: auipcc a2, %captab_pcrel_hi(a8) +; CHECK-NEXT: auipcc a2, %got_pcrel_hi(a8) ; CHECK-NEXT: clc a2, %pcrel_lo(.LBB7_1)(a2) ; CHECK-NEXT: csw a1, 4(a2) ; CHECK-NEXT: csw a0, 0(a2) diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/bounded-allocas-lifetimes.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/bounded-allocas-lifetimes.ll index a9757df5df533..7acc52a024046 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/bounded-allocas-lifetimes.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/bounded-allocas-lifetimes.ll @@ -17,7 +17,7 @@ define void @static_alloca() { ; CHECK-NEXT: LIFETIME_START %stack.0 ; CHECK-NEXT: ADJCALLSTACKDOWNCAP 0, 0, implicit-def dead $x2_y, implicit $x2_y ; CHECK-NEXT: $x10_y = COPY [[CSetBoundsImm]] - ; CHECK-NEXT: PseudoCCALL target-flags(riscv-ccall) @use, csr_il32pc64d_l64pc128d, implicit-def dead $x1_y, implicit $x10_y, implicit-def $x2_y + ; CHECK-NEXT: PseudoCCALL target-flags(riscv-call) @use, csr_il32pc64d_l64pc128d, implicit-def dead $x1_y, implicit $x10_y, implicit-def $x2_y ; CHECK-NEXT: ADJCALLSTACKUPCAP 0, 0, implicit-def dead $x2_y, implicit $x2_y ; CHECK-NEXT: LIFETIME_END %stack.0 ; CHECK-NEXT: PseudoCRET @@ -54,7 +54,7 @@ define void @dynamic_alloca(i64 zeroext %n) { ; CHECK-NEXT: [[CSetBounds1:%[0-9]+]]:ygpr = CSetBounds killed [[CSetBounds]], [[SLLI]] ; CHECK-NEXT: ADJCALLSTACKDOWNCAP 0, 0, implicit-def dead $x2_y, implicit $x2_y ; CHECK-NEXT: $x10_y = COPY [[CSetBounds1]] - ; CHECK-NEXT: PseudoCCALL target-flags(riscv-ccall) @use, csr_il32pc64d_l64pc128d, implicit-def dead $x1_y, implicit $x10_y, implicit-def $x2_y + ; CHECK-NEXT: PseudoCCALL target-flags(riscv-call) @use, csr_il32pc64d_l64pc128d, implicit-def dead $x1_y, implicit $x10_y, implicit-def $x2_y ; CHECK-NEXT: ADJCALLSTACKUPCAP 0, 0, implicit-def dead $x2_y, implicit $x2_y ; CHECK-NEXT: PseudoCRET %1 = alloca i32, i64 %n, align 4, addrspace(200) diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/cheri-intrinsics-folding-broken-module-regression.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/cheri-intrinsics-folding-broken-module-regression.ll index e714263a9d82d..f4018b80652d8 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/cheri-intrinsics-folding-broken-module-regression.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/cheri-intrinsics-folding-broken-module-regression.ll @@ -19,10 +19,10 @@ define void @g(i64 %x, i64 %y) addrspace(200) nounwind { ; ASM-LABEL: g: ; ASM: # %bb.0: ; ASM-NEXT: .LBB0_1: # Label of block must be emitted -; ASM-NEXT: auipcc a2, %captab_pcrel_hi(d) +; ASM-NEXT: auipcc a2, %got_pcrel_hi(d) ; ASM-NEXT: clc a2, %pcrel_lo(.LBB0_1)(a2) ; ASM-NEXT: .LBB0_2: # Label of block must be emitted -; ASM-NEXT: auipcc a3, %captab_pcrel_hi(e) +; ASM-NEXT: auipcc a3, %got_pcrel_hi(e) ; ASM-NEXT: clc a3, %pcrel_lo(.LBB0_2)(a3) ; ASM-NEXT: cincoffset a0, a2, a0 ; ASM-NEXT: cincoffset a0, a0, a1 diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/memcpy-from-constant.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/memcpy-from-constant.ll index a41d6347e2361..a0f0bffe27adb 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/memcpy-from-constant.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/memcpy-from-constant.ll @@ -46,7 +46,7 @@ define linkonce_odr void @copy_from_ptr_constant(ptr addrspace(200) %dst) addrsp ; CHECK: # %bb.0: # %do.body ; CHECK-NEXT: .LBB3_1: # %do.body ; CHECK-NEXT: # Label of block must be emitted -; CHECK-NEXT: auipcc a1, %captab_pcrel_hi(constant_ptrs) +; CHECK-NEXT: auipcc a1, %got_pcrel_hi(constant_ptrs) ; CHECK-NEXT: clc a1, %pcrel_lo(.LBB3_1)(a1) ; CHECK-NEXT: clc a1, 0(a1) ; CHECK-NEXT: csc a1, 0(a0) @@ -61,7 +61,7 @@ define linkonce_odr void @copy_from_ptr_constant_with_offset(ptr addrspace(200) ; CHECK: # %bb.0: # %do.body ; CHECK-NEXT: .LBB4_1: # %do.body ; CHECK-NEXT: # Label of block must be emitted -; CHECK-NEXT: auipcc a1, %captab_pcrel_hi(constant_ptrs) +; CHECK-NEXT: auipcc a1, %got_pcrel_hi(constant_ptrs) ; CHECK-NEXT: clc a1, %pcrel_lo(.LBB4_1)(a1) ; CHECK-NEXT: clc a1, 16(a1) ; CHECK-NEXT: csc a1, 0(a0) @@ -110,7 +110,7 @@ define linkonce_odr void @copy_from_ptr_constant_preserve(ptr addrspace(200) %ds ; CHECK: # %bb.0: # %do.body ; CHECK-NEXT: .LBB8_1: # %do.body ; CHECK-NEXT: # Label of block must be emitted -; CHECK-NEXT: auipcc a1, %captab_pcrel_hi(constant_ptrs) +; CHECK-NEXT: auipcc a1, %got_pcrel_hi(constant_ptrs) ; CHECK-NEXT: clc a1, %pcrel_lo(.LBB8_1)(a1) ; CHECK-NEXT: clc a1, 0(a1) ; CHECK-NEXT: csc a1, 0(a0) @@ -125,7 +125,7 @@ define linkonce_odr void @copy_from_ptr_constant_with_offset_preserve(ptr addrsp ; CHECK: # %bb.0: # %do.body ; CHECK-NEXT: .LBB9_1: # %do.body ; CHECK-NEXT: # Label of block must be emitted -; CHECK-NEXT: auipcc a1, %captab_pcrel_hi(constant_ptrs) +; CHECK-NEXT: auipcc a1, %got_pcrel_hi(constant_ptrs) ; CHECK-NEXT: clc a1, %pcrel_lo(.LBB9_1)(a1) ; CHECK-NEXT: clc a1, 16(a1) ; CHECK-NEXT: csc a1, 0(a0) diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/memcpy-zeroinit.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/memcpy-zeroinit.ll index fad24ba659133..6c881accf522a 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/memcpy-zeroinit.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/memcpy-zeroinit.ll @@ -24,7 +24,7 @@ define void @_thr_umutex_init_volatile(%struct.umutex addrspace(200)* %mtx) loca ; CHECK-LABEL: _thr_umutex_init_volatile: ; CHECK: # %bb.0: ; CHECK-NEXT: .LBB1_1: # Label of block must be emitted -; CHECK-NEXT: auipcc a1, %captab_pcrel_hi(_thr_umutex_init.default_mtx) +; CHECK-NEXT: auipcc a1, %got_pcrel_hi(_thr_umutex_init.default_mtx) ; CHECK-NEXT: clc a1, %pcrel_lo(.LBB1_1)(a1) ; CHECK-NEXT: clc a2, 32(a1) ; CHECK-NEXT: csc a2, 32(a0) diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/strcpy-to-memcpy-no-tags.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/strcpy-to-memcpy-no-tags.ll index e2f965e3449b8..a64e1f33223a2 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/strcpy-to-memcpy-no-tags.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/strcpy-to-memcpy-no-tags.ll @@ -82,7 +82,7 @@ define void @test_strcat_to_memcpy(ptr addrspace(200) align 8 %dst) addrspace(20 ; CHECK-ASM-NEXT: cincoffset a0, s0, a0 ; CHECK-ASM-NEXT: .LBB2_1: # %entry ; CHECK-ASM-NEXT: # Label of block must be emitted -; CHECK-ASM-NEXT: auipcc a1, %captab_pcrel_hi(.Lstr) +; CHECK-ASM-NEXT: auipcc a1, %got_pcrel_hi(.Lstr) ; CHECK-ASM-NEXT: clc a1, %pcrel_lo(.LBB2_1)(a1) ; CHECK-ASM-NEXT: li a2, 17 ; CHECK-ASM-NEXT: ccall memcpy diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/unaligned-loads-stores-purecap.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/unaligned-loads-stores-purecap.ll index fd06c66749db4..0747994b6277a 100644 --- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/unaligned-loads-stores-purecap.ll +++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/unaligned-loads-stores-purecap.ll @@ -11,7 +11,7 @@ define i64 @load_global_i64_align_1(i64 %y) addrspace(200) nounwind { ; CHECK-LABEL: load_global_i64_align_1: ; CHECK: # %bb.0: ; CHECK-NEXT: .LBB0_1: # Label of block must be emitted -; CHECK-NEXT: auipcc a0, %captab_pcrel_hi(a1) +; CHECK-NEXT: auipcc a0, %got_pcrel_hi(a1) ; CHECK-NEXT: clc a0, %pcrel_lo(.LBB0_1)(a0) ; CHECK-NEXT: clbu a1, 0(a0) ; CHECK-NEXT: clbu a2, 1(a0) @@ -44,7 +44,7 @@ define i64 @load_global_i64_align_2(i64 %y) addrspace(200) nounwind { ; CHECK-LABEL: load_global_i64_align_2: ; CHECK: # %bb.0: ; CHECK-NEXT: .LBB1_1: # Label of block must be emitted -; CHECK-NEXT: auipcc a0, %captab_pcrel_hi(a2) +; CHECK-NEXT: auipcc a0, %got_pcrel_hi(a2) ; CHECK-NEXT: clc a0, %pcrel_lo(.LBB1_1)(a0) ; CHECK-NEXT: clhu a1, 2(a0) ; CHECK-NEXT: clhu a2, 0(a0) @@ -65,7 +65,7 @@ define i64 @load_global_i64_align_4(i64 %y) addrspace(200) nounwind { ; CHECK-LABEL: load_global_i64_align_4: ; CHECK: # %bb.0: ; CHECK-NEXT: .LBB2_1: # Label of block must be emitted -; CHECK-NEXT: auipcc a0, %captab_pcrel_hi(a4) +; CHECK-NEXT: auipcc a0, %got_pcrel_hi(a4) ; CHECK-NEXT: clc a0, %pcrel_lo(.LBB2_1)(a0) ; CHECK-NEXT: clwu a1, 4(a0) ; CHECK-NEXT: clwu a0, 0(a0) @@ -80,7 +80,7 @@ define i64 @load_global_i64_align_8(i64 %y) addrspace(200) nounwind { ; CHECK-LABEL: load_global_i64_align_8: ; CHECK: # %bb.0: ; CHECK-NEXT: .LBB3_1: # Label of block must be emitted -; CHECK-NEXT: auipcc a0, %captab_pcrel_hi(a8) +; CHECK-NEXT: auipcc a0, %got_pcrel_hi(a8) ; CHECK-NEXT: clc a0, %pcrel_lo(.LBB3_1)(a0) ; CHECK-NEXT: cld a0, 0(a0) ; CHECK-NEXT: cret @@ -92,7 +92,7 @@ define void @store_global_i64_align_1(i64 %y) addrspace(200) nounwind { ; CHECK-LABEL: store_global_i64_align_1: ; CHECK: # %bb.0: ; CHECK-NEXT: .LBB4_1: # Label of block must be emitted -; CHECK-NEXT: auipcc a1, %captab_pcrel_hi(a1) +; CHECK-NEXT: auipcc a1, %got_pcrel_hi(a1) ; CHECK-NEXT: clc a1, %pcrel_lo(.LBB4_1)(a1) ; CHECK-NEXT: srli a2, a0, 56 ; CHECK-NEXT: csb a2, 7(a1) @@ -118,7 +118,7 @@ define void @store_global_i64_align_2(i64 %y) addrspace(200) nounwind { ; CHECK-LABEL: store_global_i64_align_2: ; CHECK: # %bb.0: ; CHECK-NEXT: .LBB5_1: # Label of block must be emitted -; CHECK-NEXT: auipcc a1, %captab_pcrel_hi(a2) +; CHECK-NEXT: auipcc a1, %got_pcrel_hi(a2) ; CHECK-NEXT: clc a1, %pcrel_lo(.LBB5_1)(a1) ; CHECK-NEXT: srli a2, a0, 48 ; CHECK-NEXT: csh a2, 6(a1) @@ -136,7 +136,7 @@ define void @store_global_i64_align_4(i64 %y) addrspace(200) nounwind { ; CHECK-LABEL: store_global_i64_align_4: ; CHECK: # %bb.0: ; CHECK-NEXT: .LBB6_1: # Label of block must be emitted -; CHECK-NEXT: auipcc a1, %captab_pcrel_hi(a4) +; CHECK-NEXT: auipcc a1, %got_pcrel_hi(a4) ; CHECK-NEXT: clc a1, %pcrel_lo(.LBB6_1)(a1) ; CHECK-NEXT: csw a0, 0(a1) ; CHECK-NEXT: srli a0, a0, 32 @@ -150,7 +150,7 @@ define void @store_global_i64_align_8(i64 %y) addrspace(200) nounwind { ; CHECK-LABEL: store_global_i64_align_8: ; CHECK: # %bb.0: ; CHECK-NEXT: .LBB7_1: # Label of block must be emitted -; CHECK-NEXT: auipcc a1, %captab_pcrel_hi(a8) +; CHECK-NEXT: auipcc a1, %got_pcrel_hi(a8) ; CHECK-NEXT: clc a1, %pcrel_lo(.LBB7_1)(a1) ; CHECK-NEXT: csd a0, 0(a1) ; CHECK-NEXT: cret diff --git a/llvm/test/CodeGen/CHERI-Generic/byval-buffer.ll b/llvm/test/CodeGen/CHERI-Generic/byval-buffer.ll index 97b0cc387e1e1..2624f82d9bc32 100644 --- a/llvm/test/CodeGen/CHERI-Generic/byval-buffer.ll +++ b/llvm/test/CodeGen/CHERI-Generic/byval-buffer.ll @@ -170,7 +170,7 @@ define dso_local void @clang_purecap_byval_args() local_unnamed_addr addrspace(2 ; PURECAP-RV64-NEXT: csc s0, 1040(sp) # 16-byte Folded Spill ; PURECAP-RV64-NEXT: .LBB0_1: # %entry ; PURECAP-RV64-NEXT: # Label of block must be emitted -; PURECAP-RV64-NEXT: auipcc s0, %captab_pcrel_hi(global_foo) +; PURECAP-RV64-NEXT: auipcc s0, %got_pcrel_hi(global_foo) ; PURECAP-RV64-NEXT: clc s0, %pcrel_lo(.LBB0_1)(s0) ; PURECAP-RV64-NEXT: li a2, 1024 ; PURECAP-RV64-NEXT: cmove a0, s0 diff --git a/llvm/test/CodeGen/RISCV/cheri/get-global-addr.ll b/llvm/test/CodeGen/RISCV/cheri/get-global-addr.ll index 78434e9769dfb..020931cff15cc 100644 --- a/llvm/test/CodeGen/RISCV/cheri/get-global-addr.ll +++ b/llvm/test/CodeGen/RISCV/cheri/get-global-addr.ll @@ -52,7 +52,7 @@ define i64 @load_external_global_variable(double %a) nounwind { ; L64PC128-LABEL: load_external_global_variable: ; L64PC128: # %bb.0: ; L64PC128-NEXT: .LBB2_1: # Label of block must be emitted -; L64PC128-NEXT: auipcc a0, %captab_pcrel_hi(external_variable) +; L64PC128-NEXT: auipcc a0, %got_pcrel_hi(external_variable) ; L64PC128-NEXT: clc a0, %pcrel_lo(.LBB2_1)(a0) ; L64PC128-NEXT: cld a0, 0(a0) ; L64PC128-NEXT: cret @@ -65,7 +65,7 @@ define i64 @load_external_global_constant(double %a) nounwind { ; L64PC128-LABEL: load_external_global_constant: ; L64PC128: # %bb.0: ; L64PC128-NEXT: .LBB3_1: # Label of block must be emitted -; L64PC128-NEXT: auipcc a0, %captab_pcrel_hi(external_constant) +; L64PC128-NEXT: auipcc a0, %got_pcrel_hi(external_constant) ; L64PC128-NEXT: clc a0, %pcrel_lo(.LBB3_1)(a0) ; L64PC128-NEXT: cld a0, 0(a0) ; L64PC128-NEXT: cret @@ -78,7 +78,7 @@ define i64 @load_dso_local_external_global_variable(double %a) nounwind { ; L64PC128-LABEL: load_dso_local_external_global_variable: ; L64PC128: # %bb.0: ; L64PC128-NEXT: .LBB4_1: # Label of block must be emitted -; L64PC128-NEXT: auipcc a0, %captab_pcrel_hi(dso_local_external_variable) +; L64PC128-NEXT: auipcc a0, %got_pcrel_hi(dso_local_external_variable) ; L64PC128-NEXT: clc a0, %pcrel_lo(.LBB4_1)(a0) ; L64PC128-NEXT: cld a0, 0(a0) ; L64PC128-NEXT: cret @@ -92,7 +92,7 @@ define i64 @load_dso_local_external_global_constant(double %a) nounwind { ; L64PC128-LABEL: load_dso_local_external_global_constant: ; L64PC128: # %bb.0: ; L64PC128-NEXT: .LBB5_1: # Label of block must be emitted -; L64PC128-NEXT: auipcc a0, %captab_pcrel_hi(dso_local_external_constant) +; L64PC128-NEXT: auipcc a0, %got_pcrel_hi(dso_local_external_constant) ; L64PC128-NEXT: clc a0, %pcrel_lo(.LBB5_1)(a0) ; L64PC128-NEXT: cld a0, 0(a0) ; L64PC128-NEXT: cret @@ -105,7 +105,7 @@ define i64 @load_defined_variable(double %a) nounwind { ; L64PC128-LABEL: load_defined_variable: ; L64PC128: # %bb.0: ; L64PC128-NEXT: .LBB6_1: # Label of block must be emitted -; L64PC128-NEXT: auipcc a0, %captab_pcrel_hi(defined_variable) +; L64PC128-NEXT: auipcc a0, %got_pcrel_hi(defined_variable) ; L64PC128-NEXT: clc a0, %pcrel_lo(.LBB6_1)(a0) ; L64PC128-NEXT: cld a0, 0(a0) ; L64PC128-NEXT: cret @@ -118,7 +118,7 @@ define i64 @load_defined_constant(double %a) nounwind { ; L64PC128-LABEL: load_defined_constant: ; L64PC128: # %bb.0: ; L64PC128-NEXT: .LBB7_1: # Label of block must be emitted -; L64PC128-NEXT: auipcc a0, %captab_pcrel_hi(defined_constant) +; L64PC128-NEXT: auipcc a0, %got_pcrel_hi(defined_constant) ; L64PC128-NEXT: clc a0, %pcrel_lo(.LBB7_1)(a0) ; L64PC128-NEXT: cld a0, 0(a0) ; L64PC128-NEXT: cret @@ -131,7 +131,7 @@ define i64 @load_hidden_variable(double %a) nounwind { ; L64PC128-LABEL: load_hidden_variable: ; L64PC128: # %bb.0: ; L64PC128-NEXT: .LBB8_1: # Label of block must be emitted -; L64PC128-NEXT: auipcc a0, %captab_pcrel_hi(hidden_variable) +; L64PC128-NEXT: auipcc a0, %got_pcrel_hi(hidden_variable) ; L64PC128-NEXT: clc a0, %pcrel_lo(.LBB8_1)(a0) ; L64PC128-NEXT: cld a0, 0(a0) ; L64PC128-NEXT: cret @@ -144,7 +144,7 @@ define i64 @load_hidden_constant(double %a) nounwind { ; L64PC128-LABEL: load_hidden_constant: ; L64PC128: # %bb.0: ; L64PC128-NEXT: .LBB9_1: # Label of block must be emitted -; L64PC128-NEXT: auipcc a0, %captab_pcrel_hi(hidden_constant) +; L64PC128-NEXT: auipcc a0, %got_pcrel_hi(hidden_constant) ; L64PC128-NEXT: clc a0, %pcrel_lo(.LBB9_1)(a0) ; L64PC128-NEXT: cld a0, 0(a0) ; L64PC128-NEXT: cret @@ -157,7 +157,7 @@ define i64 @load_dso_local_variable(double %a) nounwind { ; L64PC128-LABEL: load_dso_local_variable: ; L64PC128: # %bb.0: ; L64PC128-NEXT: .LBB10_1: # Label of block must be emitted -; L64PC128-NEXT: auipcc a0, %captab_pcrel_hi(dso_local_variable) +; L64PC128-NEXT: auipcc a0, %got_pcrel_hi(dso_local_variable) ; L64PC128-NEXT: clc a0, %pcrel_lo(.LBB10_1)(a0) ; L64PC128-NEXT: cld a0, 0(a0) ; L64PC128-NEXT: cret @@ -170,7 +170,7 @@ define i64 @load_dso_local_constant(double %a) nounwind { ; L64PC128-LABEL: load_dso_local_constant: ; L64PC128: # %bb.0: ; L64PC128-NEXT: .LBB11_1: # Label of block must be emitted -; L64PC128-NEXT: auipcc a0, %captab_pcrel_hi(dso_local_constant) +; L64PC128-NEXT: auipcc a0, %got_pcrel_hi(dso_local_constant) ; L64PC128-NEXT: clc a0, %pcrel_lo(.LBB11_1)(a0) ; L64PC128-NEXT: cld a0, 0(a0) ; L64PC128-NEXT: cret diff --git a/llvm/test/CodeGen/RISCV/cheri/machine-outliner.mir b/llvm/test/CodeGen/RISCV/cheri/machine-outliner.mir index fae1b58f1b22b..bdd816dc9f6cc 100644 --- a/llvm/test/CodeGen/RISCV/cheri/machine-outliner.mir +++ b/llvm/test/CodeGen/RISCV/cheri/machine-outliner.mir @@ -49,7 +49,7 @@ body: | ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000) ; CHECK-NEXT: liveins: $x10_y, $x12_y, $x13_y, $x11 ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: PseudoCCALLReg target-flags(riscv-ccall) @OUTLINED_FUNCTION_0, implicit-def $x14, implicit-def $x15, implicit-def $x5_y, implicit-def $x15_y, implicit $x10_y, implicit $x12_y + ; CHECK-NEXT: PseudoCCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x14, implicit-def $x15, implicit-def $x5_y, implicit-def $x15_y, implicit $x10_y, implicit $x12_y ; CHECK-NEXT: renamable $x14 = ANDI killed renamable $x14, 1 ; CHECK-NEXT: BEQ killed renamable $x14, $x0, %bb.3 ; CHECK-NEXT: {{ $}} @@ -57,7 +57,7 @@ body: | ; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: liveins: $x10_y, $x12_y, $x13_y, $x11 ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: PseudoCCALLReg target-flags(riscv-ccall) @OUTLINED_FUNCTION_0, implicit-def $x14, implicit-def $x15, implicit-def $x5_y, implicit-def $x15_y, implicit $x10_y, implicit $x12_y + ; CHECK-NEXT: PseudoCCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x14, implicit-def $x15, implicit-def $x5_y, implicit-def $x15_y, implicit $x10_y, implicit $x12_y ; CHECK-NEXT: renamable $x15 = ANDI killed renamable $x14, 1 ; CHECK-NEXT: $x14_y = CMove $x0_y ; CHECK-NEXT: {{ $}} diff --git a/llvm/test/CodeGen/RISCV/cheri/machinelicm-capability-pseudos.ll b/llvm/test/CodeGen/RISCV/cheri/machinelicm-capability-pseudos.ll index 2e84633e5a16d..952008ab9e7c9 100644 --- a/llvm/test/CodeGen/RISCV/cheri/machinelicm-capability-pseudos.ll +++ b/llvm/test/CodeGen/RISCV/cheri/machinelicm-capability-pseudos.ll @@ -14,7 +14,7 @@ define void @test_clgc(i32 signext %n) { ; RV32I: # %bb.0: # %entry ; RV32I-NEXT: .LBB0_3: # %entry ; RV32I-NEXT: # Label of block must be emitted -; RV32I-NEXT: auipcc a1, %captab_pcrel_hi(g) +; RV32I-NEXT: auipcc a1, %got_pcrel_hi(g) ; RV32I-NEXT: clc a1, %pcrel_lo(.LBB0_3)(a1) ; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: .LBB0_1: # %loop @@ -29,7 +29,7 @@ define void @test_clgc(i32 signext %n) { ; RV64I: # %bb.0: # %entry ; RV64I-NEXT: .LBB0_3: # %entry ; RV64I-NEXT: # Label of block must be emitted -; RV64I-NEXT: auipcc a1, %captab_pcrel_hi(g) +; RV64I-NEXT: auipcc a1, %got_pcrel_hi(g) ; RV64I-NEXT: clc a1, %pcrel_lo(.LBB0_3)(a1) ; RV64I-NEXT: li a2, 0 ; RV64I-NEXT: .LBB0_1: # %loop @@ -61,7 +61,7 @@ define void @test_cla_tls_ie(i32 signext %n) { ; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: .LBB1_3: # %entry ; RV32I-NEXT: # Label of block must be emitted -; RV32I-NEXT: auipcc a3, %tls_ie_captab_pcrel_hi(ie) +; RV32I-NEXT: auipcc a3, %tls_ie_pcrel_hi(ie) ; RV32I-NEXT: clw a2, %pcrel_lo(.LBB1_3)(a3) ; RV32I-NEXT: cincoffset a2, tp, a2 ; RV32I-NEXT: .LBB1_1: # %loop @@ -77,7 +77,7 @@ define void @test_cla_tls_ie(i32 signext %n) { ; RV64I-NEXT: li a1, 0 ; RV64I-NEXT: .LBB1_3: # %entry ; RV64I-NEXT: # Label of block must be emitted -; RV64I-NEXT: auipcc a3, %tls_ie_captab_pcrel_hi(ie) +; RV64I-NEXT: auipcc a3, %tls_ie_pcrel_hi(ie) ; RV64I-NEXT: cld a2, %pcrel_lo(.LBB1_3)(a3) ; RV64I-NEXT: cincoffset a2, tp, a2 ; RV64I-NEXT: .LBB1_1: # %loop @@ -115,7 +115,7 @@ define void @test_clc_tls_gd(i32 signext %n) nounwind { ; RV32I-NEXT: li s2, 0 ; RV32I-NEXT: .LBB2_3: # %entry ; RV32I-NEXT: # Label of block must be emitted -; RV32I-NEXT: auipcc s1, %tls_gd_captab_pcrel_hi(gd) +; RV32I-NEXT: auipcc s1, %tls_gd_pcrel_hi(gd) ; RV32I-NEXT: cincoffset s1, s1, %pcrel_lo(.LBB2_3) ; RV32I-NEXT: .LBB2_1: # %loop ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 @@ -143,7 +143,7 @@ define void @test_clc_tls_gd(i32 signext %n) nounwind { ; RV64I-NEXT: li s2, 0 ; RV64I-NEXT: .LBB2_3: # %entry ; RV64I-NEXT: # Label of block must be emitted -; RV64I-NEXT: auipcc s1, %tls_gd_captab_pcrel_hi(gd) +; RV64I-NEXT: auipcc s1, %tls_gd_pcrel_hi(gd) ; RV64I-NEXT: cincoffset s1, s1, %pcrel_lo(.LBB2_3) ; RV64I-NEXT: .LBB2_1: # %loop ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 diff --git a/llvm/test/CodeGen/RISCV/cheri/rematerialize.mir b/llvm/test/CodeGen/RISCV/cheri/rematerialize.mir index 91a12a2df4d48..6853d0c502a5d 100644 --- a/llvm/test/CodeGen/RISCV/cheri/rematerialize.mir +++ b/llvm/test/CodeGen/RISCV/cheri/rematerialize.mir @@ -60,19 +60,19 @@ body: | ; CHECK-NEXT: $x10_y = CIncOffsetImm $x0_y, 123 ; CHECK-NEXT: $x11_y = CMove $x0_y ; CHECK-NEXT: $x12_y = COPY [[CIncOffsetImm]] - ; CHECK-NEXT: PseudoCCALL target-flags(riscv-ccall) @external_fn, csr_il32pc64_l64pc128, implicit-def dead $x1_y, implicit killed $x10_y, implicit killed $x11_y, implicit killed $x12_y, implicit-def $x2_y + ; CHECK-NEXT: PseudoCCALL target-flags(riscv-call) @external_fn, csr_il32pc64_l64pc128, implicit-def dead $x1_y, implicit killed $x10_y, implicit killed $x11_y, implicit killed $x12_y, implicit-def $x2_y ; CHECK-NEXT: ADJCALLSTACKUPCAP 0, 0, implicit-def dead $x2_y, implicit $x2_y ; CHECK-NEXT: ADJCALLSTACKDOWNCAP 0, 0, implicit-def dead $x2_y, implicit $x2_y ; CHECK-NEXT: $x10_y = CIncOffsetImm $x0_y, 123 ; CHECK-NEXT: $x11_y = CMove $x0_y ; CHECK-NEXT: $x12_y = COPY [[CIncOffsetImm]] - ; CHECK-NEXT: PseudoCCALL target-flags(riscv-ccall) @external_fn, csr_il32pc64_l64pc128, implicit-def dead $x1_y, implicit killed $x10_y, implicit killed $x11_y, implicit killed $x12_y, implicit-def $x2_y + ; CHECK-NEXT: PseudoCCALL target-flags(riscv-call) @external_fn, csr_il32pc64_l64pc128, implicit-def dead $x1_y, implicit killed $x10_y, implicit killed $x11_y, implicit killed $x12_y, implicit-def $x2_y ; CHECK-NEXT: ADJCALLSTACKUPCAP 0, 0, implicit-def dead $x2_y, implicit $x2_y ; CHECK-NEXT: ADJCALLSTACKDOWNCAP 0, 0, implicit-def dead $x2_y, implicit $x2_y ; CHECK-NEXT: $x10_y = CIncOffsetImm $x0_y, 123 ; CHECK-NEXT: $x11_y = CMove $x0_y ; CHECK-NEXT: $x12_y = COPY [[CIncOffsetImm]] - ; CHECK-NEXT: PseudoCCALL target-flags(riscv-ccall) @external_fn, csr_il32pc64_l64pc128, implicit-def dead $x1_y, implicit killed $x10_y, implicit killed $x11_y, implicit killed $x12_y, implicit-def $x2_y + ; CHECK-NEXT: PseudoCCALL target-flags(riscv-call) @external_fn, csr_il32pc64_l64pc128, implicit-def dead $x1_y, implicit killed $x10_y, implicit killed $x11_y, implicit killed $x12_y, implicit-def $x2_y ; CHECK-NEXT: ADJCALLSTACKUPCAP 0, 0, implicit-def dead $x2_y, implicit $x2_y ; CHECK-NEXT: PseudoCRET ADJCALLSTACKDOWNCAP 0, 0, implicit-def dead $x2_y, implicit $x2_y @@ -86,19 +86,19 @@ body: | $x10_y = COPY %1 $x11_y = COPY %2 $x12_y = COPY %4 - PseudoCCALL target-flags(riscv-ccall) @external_fn, csr_il32pc64_l64pc128, implicit-def dead $x1_y, implicit killed $x10_y, implicit killed $x11_y, implicit killed $x12_y, implicit-def $x2_y + PseudoCCALL target-flags(riscv-call) @external_fn, csr_il32pc64_l64pc128, implicit-def dead $x1_y, implicit killed $x10_y, implicit killed $x11_y, implicit killed $x12_y, implicit-def $x2_y ADJCALLSTACKUPCAP 0, 0, implicit-def dead $x2_y, implicit $x2_y ADJCALLSTACKDOWNCAP 0, 0, implicit-def dead $x2_y, implicit $x2_y $x10_y = COPY %1 $x11_y = COPY %2 $x12_y = COPY %4 - PseudoCCALL target-flags(riscv-ccall) @external_fn, csr_il32pc64_l64pc128, implicit-def dead $x1_y, implicit killed $x10_y, implicit killed $x11_y, implicit killed $x12_y, implicit-def $x2_y + PseudoCCALL target-flags(riscv-call) @external_fn, csr_il32pc64_l64pc128, implicit-def dead $x1_y, implicit killed $x10_y, implicit killed $x11_y, implicit killed $x12_y, implicit-def $x2_y ADJCALLSTACKUPCAP 0, 0, implicit-def dead $x2_y, implicit $x2_y ADJCALLSTACKDOWNCAP 0, 0, implicit-def dead $x2_y, implicit $x2_y $x10_y = COPY killed %1 $x11_y = COPY %2 $x12_y = COPY %4 - PseudoCCALL target-flags(riscv-ccall) @external_fn, csr_il32pc64_l64pc128, implicit-def dead $x1_y, implicit killed $x10_y, implicit killed $x11_y, implicit killed $x12_y, implicit-def $x2_y + PseudoCCALL target-flags(riscv-call) @external_fn, csr_il32pc64_l64pc128, implicit-def dead $x1_y, implicit killed $x10_y, implicit killed $x11_y, implicit killed $x12_y, implicit-def $x2_y ADJCALLSTACKUPCAP 0, 0, implicit-def dead $x2_y, implicit $x2_y PseudoCRET ... diff --git a/llvm/test/CodeGen/RISCV/cheri/stack-protector.ll b/llvm/test/CodeGen/RISCV/cheri/stack-protector.ll index ff1b54b0bd067..a04104e725042 100644 --- a/llvm/test/CodeGen/RISCV/cheri/stack-protector.ll +++ b/llvm/test/CodeGen/RISCV/cheri/stack-protector.ll @@ -38,7 +38,7 @@ define void @caller() addrspace(200) nounwind sspstrong { ; IL32PC64-NEXT: csc ra, 24(sp) # 8-byte Folded Spill ; IL32PC64-NEXT: csc s0, 16(sp) # 8-byte Folded Spill ; IL32PC64-NEXT: .LBB0_3: # Label of block must be emitted -; IL32PC64-NEXT: auipcc s0, %captab_pcrel_hi(__stack_chk_guard) +; IL32PC64-NEXT: auipcc s0, %got_pcrel_hi(__stack_chk_guard) ; IL32PC64-NEXT: clc s0, %pcrel_lo(.LBB0_3)(s0) ; IL32PC64-NEXT: clw a0, 0(s0) ; IL32PC64-NEXT: csw a0, 12(sp) @@ -62,7 +62,7 @@ define void @caller() addrspace(200) nounwind sspstrong { ; L64PC128-NEXT: csc ra, 32(sp) # 16-byte Folded Spill ; L64PC128-NEXT: csc s0, 16(sp) # 16-byte Folded Spill ; L64PC128-NEXT: .LBB0_3: # Label of block must be emitted -; L64PC128-NEXT: auipcc s0, %captab_pcrel_hi(__stack_chk_guard) +; L64PC128-NEXT: auipcc s0, %got_pcrel_hi(__stack_chk_guard) ; L64PC128-NEXT: clc s0, %pcrel_lo(.LBB0_3)(s0) ; L64PC128-NEXT: cld a0, 0(s0) ; L64PC128-NEXT: csd a0, 8(sp) diff --git a/llvm/test/CodeGen/RISCV/cheri/tls-models.ll b/llvm/test/CodeGen/RISCV/cheri/tls-models.ll index eff117b2a0b58..e8eec1a575ce8 100644 --- a/llvm/test/CodeGen/RISCV/cheri/tls-models.ll +++ b/llvm/test/CodeGen/RISCV/cheri/tls-models.ll @@ -27,7 +27,7 @@ define i32 addrspace(200)* @f1() nounwind { ; IL32PC64-PIC-NEXT: csc ra, 8(sp) # 8-byte Folded Spill ; IL32PC64-PIC-NEXT: .LBB0_1: # %entry ; IL32PC64-PIC-NEXT: # Label of block must be emitted -; IL32PC64-PIC-NEXT: auipcc a0, %tls_gd_captab_pcrel_hi(unspecified) +; IL32PC64-PIC-NEXT: auipcc a0, %tls_gd_pcrel_hi(unspecified) ; IL32PC64-PIC-NEXT: cincoffset a0, a0, %pcrel_lo(.LBB0_1) ; IL32PC64-PIC-NEXT: ccall __tls_get_addr ; IL32PC64-PIC-NEXT: clc ra, 8(sp) # 8-byte Folded Reload @@ -40,7 +40,7 @@ define i32 addrspace(200)* @f1() nounwind { ; L64PC128-PIC-NEXT: csc ra, 0(sp) # 16-byte Folded Spill ; L64PC128-PIC-NEXT: .LBB0_1: # %entry ; L64PC128-PIC-NEXT: # Label of block must be emitted -; L64PC128-PIC-NEXT: auipcc a0, %tls_gd_captab_pcrel_hi(unspecified) +; L64PC128-PIC-NEXT: auipcc a0, %tls_gd_pcrel_hi(unspecified) ; L64PC128-PIC-NEXT: cincoffset a0, a0, %pcrel_lo(.LBB0_1) ; L64PC128-PIC-NEXT: ccall __tls_get_addr ; L64PC128-PIC-NEXT: clc ra, 0(sp) # 16-byte Folded Reload @@ -51,7 +51,7 @@ define i32 addrspace(200)* @f1() nounwind { ; IL32PC64-NOPIC: # %bb.0: # %entry ; IL32PC64-NOPIC-NEXT: .LBB0_1: # %entry ; IL32PC64-NOPIC-NEXT: # Label of block must be emitted -; IL32PC64-NOPIC-NEXT: auipcc a1, %tls_ie_captab_pcrel_hi(unspecified) +; IL32PC64-NOPIC-NEXT: auipcc a1, %tls_ie_pcrel_hi(unspecified) ; IL32PC64-NOPIC-NEXT: clw a0, %pcrel_lo(.LBB0_1)(a1) ; IL32PC64-NOPIC-NEXT: cincoffset a0, tp, a0 ; IL32PC64-NOPIC-NEXT: cret @@ -60,7 +60,7 @@ define i32 addrspace(200)* @f1() nounwind { ; L64PC128-NOPIC: # %bb.0: # %entry ; L64PC128-NOPIC-NEXT: .LBB0_1: # %entry ; L64PC128-NOPIC-NEXT: # Label of block must be emitted -; L64PC128-NOPIC-NEXT: auipcc a1, %tls_ie_captab_pcrel_hi(unspecified) +; L64PC128-NOPIC-NEXT: auipcc a1, %tls_ie_pcrel_hi(unspecified) ; L64PC128-NOPIC-NEXT: cld a0, %pcrel_lo(.LBB0_1)(a1) ; L64PC128-NOPIC-NEXT: cincoffset a0, tp, a0 ; L64PC128-NOPIC-NEXT: cret @@ -78,7 +78,7 @@ define i32 addrspace(200)* @f2() nounwind { ; IL32PC64-PIC-NEXT: csc ra, 8(sp) # 8-byte Folded Spill ; IL32PC64-PIC-NEXT: .LBB1_1: # %entry ; IL32PC64-PIC-NEXT: # Label of block must be emitted -; IL32PC64-PIC-NEXT: auipcc a0, %tls_gd_captab_pcrel_hi(ld) +; IL32PC64-PIC-NEXT: auipcc a0, %tls_gd_pcrel_hi(ld) ; IL32PC64-PIC-NEXT: cincoffset a0, a0, %pcrel_lo(.LBB1_1) ; IL32PC64-PIC-NEXT: ccall __tls_get_addr ; IL32PC64-PIC-NEXT: clc ra, 8(sp) # 8-byte Folded Reload @@ -91,7 +91,7 @@ define i32 addrspace(200)* @f2() nounwind { ; L64PC128-PIC-NEXT: csc ra, 0(sp) # 16-byte Folded Spill ; L64PC128-PIC-NEXT: .LBB1_1: # %entry ; L64PC128-PIC-NEXT: # Label of block must be emitted -; L64PC128-PIC-NEXT: auipcc a0, %tls_gd_captab_pcrel_hi(ld) +; L64PC128-PIC-NEXT: auipcc a0, %tls_gd_pcrel_hi(ld) ; L64PC128-PIC-NEXT: cincoffset a0, a0, %pcrel_lo(.LBB1_1) ; L64PC128-PIC-NEXT: ccall __tls_get_addr ; L64PC128-PIC-NEXT: clc ra, 0(sp) # 16-byte Folded Reload @@ -102,7 +102,7 @@ define i32 addrspace(200)* @f2() nounwind { ; IL32PC64-NOPIC: # %bb.0: # %entry ; IL32PC64-NOPIC-NEXT: .LBB1_1: # %entry ; IL32PC64-NOPIC-NEXT: # Label of block must be emitted -; IL32PC64-NOPIC-NEXT: auipcc a1, %tls_ie_captab_pcrel_hi(ld) +; IL32PC64-NOPIC-NEXT: auipcc a1, %tls_ie_pcrel_hi(ld) ; IL32PC64-NOPIC-NEXT: clw a0, %pcrel_lo(.LBB1_1)(a1) ; IL32PC64-NOPIC-NEXT: cincoffset a0, tp, a0 ; IL32PC64-NOPIC-NEXT: cret @@ -111,7 +111,7 @@ define i32 addrspace(200)* @f2() nounwind { ; L64PC128-NOPIC: # %bb.0: # %entry ; L64PC128-NOPIC-NEXT: .LBB1_1: # %entry ; L64PC128-NOPIC-NEXT: # Label of block must be emitted -; L64PC128-NOPIC-NEXT: auipcc a1, %tls_ie_captab_pcrel_hi(ld) +; L64PC128-NOPIC-NEXT: auipcc a1, %tls_ie_pcrel_hi(ld) ; L64PC128-NOPIC-NEXT: cld a0, %pcrel_lo(.LBB1_1)(a1) ; L64PC128-NOPIC-NEXT: cincoffset a0, tp, a0 ; L64PC128-NOPIC-NEXT: cret @@ -127,7 +127,7 @@ define i32 addrspace(200)* @f3() nounwind { ; IL32PC64-PIC: # %bb.0: # %entry ; IL32PC64-PIC-NEXT: .LBB2_1: # %entry ; IL32PC64-PIC-NEXT: # Label of block must be emitted -; IL32PC64-PIC-NEXT: auipcc a1, %tls_ie_captab_pcrel_hi(ie) +; IL32PC64-PIC-NEXT: auipcc a1, %tls_ie_pcrel_hi(ie) ; IL32PC64-PIC-NEXT: clw a0, %pcrel_lo(.LBB2_1)(a1) ; IL32PC64-PIC-NEXT: cincoffset a0, tp, a0 ; IL32PC64-PIC-NEXT: cret @@ -136,7 +136,7 @@ define i32 addrspace(200)* @f3() nounwind { ; L64PC128-PIC: # %bb.0: # %entry ; L64PC128-PIC-NEXT: .LBB2_1: # %entry ; L64PC128-PIC-NEXT: # Label of block must be emitted -; L64PC128-PIC-NEXT: auipcc a1, %tls_ie_captab_pcrel_hi(ie) +; L64PC128-PIC-NEXT: auipcc a1, %tls_ie_pcrel_hi(ie) ; L64PC128-PIC-NEXT: cld a0, %pcrel_lo(.LBB2_1)(a1) ; L64PC128-PIC-NEXT: cincoffset a0, tp, a0 ; L64PC128-PIC-NEXT: cret @@ -145,7 +145,7 @@ define i32 addrspace(200)* @f3() nounwind { ; IL32PC64-NOPIC: # %bb.0: # %entry ; IL32PC64-NOPIC-NEXT: .LBB2_1: # %entry ; IL32PC64-NOPIC-NEXT: # Label of block must be emitted -; IL32PC64-NOPIC-NEXT: auipcc a1, %tls_ie_captab_pcrel_hi(ie) +; IL32PC64-NOPIC-NEXT: auipcc a1, %tls_ie_pcrel_hi(ie) ; IL32PC64-NOPIC-NEXT: clw a0, %pcrel_lo(.LBB2_1)(a1) ; IL32PC64-NOPIC-NEXT: cincoffset a0, tp, a0 ; IL32PC64-NOPIC-NEXT: cret @@ -154,7 +154,7 @@ define i32 addrspace(200)* @f3() nounwind { ; L64PC128-NOPIC: # %bb.0: # %entry ; L64PC128-NOPIC-NEXT: .LBB2_1: # %entry ; L64PC128-NOPIC-NEXT: # Label of block must be emitted -; L64PC128-NOPIC-NEXT: auipcc a1, %tls_ie_captab_pcrel_hi(ie) +; L64PC128-NOPIC-NEXT: auipcc a1, %tls_ie_pcrel_hi(ie) ; L64PC128-NOPIC-NEXT: cld a0, %pcrel_lo(.LBB2_1)(a1) ; L64PC128-NOPIC-NEXT: cincoffset a0, tp, a0 ; L64PC128-NOPIC-NEXT: cret @@ -169,28 +169,28 @@ define i32 addrspace(200)* @f4() nounwind { ; IL32PC64-PIC-LABEL: f4: ; IL32PC64-PIC: # %bb.0: # %entry ; IL32PC64-PIC-NEXT: lui a0, %tprel_hi(le) -; IL32PC64-PIC-NEXT: cincoffset a0, tp, a0, %tprel_cincoffset(le) +; IL32PC64-PIC-NEXT: cincoffset a0, tp, a0, %tprel_add(le) ; IL32PC64-PIC-NEXT: cincoffset a0, a0, %tprel_lo(le) ; IL32PC64-PIC-NEXT: cret ; ; L64PC128-PIC-LABEL: f4: ; L64PC128-PIC: # %bb.0: # %entry ; L64PC128-PIC-NEXT: lui a0, %tprel_hi(le) -; L64PC128-PIC-NEXT: cincoffset a0, tp, a0, %tprel_cincoffset(le) +; L64PC128-PIC-NEXT: cincoffset a0, tp, a0, %tprel_add(le) ; L64PC128-PIC-NEXT: cincoffset a0, a0, %tprel_lo(le) ; L64PC128-PIC-NEXT: cret ; ; IL32PC64-NOPIC-LABEL: f4: ; IL32PC64-NOPIC: # %bb.0: # %entry ; IL32PC64-NOPIC-NEXT: lui a0, %tprel_hi(le) -; IL32PC64-NOPIC-NEXT: cincoffset a0, tp, a0, %tprel_cincoffset(le) +; IL32PC64-NOPIC-NEXT: cincoffset a0, tp, a0, %tprel_add(le) ; IL32PC64-NOPIC-NEXT: cincoffset a0, a0, %tprel_lo(le) ; IL32PC64-NOPIC-NEXT: cret ; ; L64PC128-NOPIC-LABEL: f4: ; L64PC128-NOPIC: # %bb.0: # %entry ; L64PC128-NOPIC-NEXT: lui a0, %tprel_hi(le) -; L64PC128-NOPIC-NEXT: cincoffset a0, tp, a0, %tprel_cincoffset(le) +; L64PC128-NOPIC-NEXT: cincoffset a0, tp, a0, %tprel_add(le) ; L64PC128-NOPIC-NEXT: cincoffset a0, a0, %tprel_lo(le) ; L64PC128-NOPIC-NEXT: cret entry: diff --git a/llvm/test/MC/RISCV/rv32-relaxation-xqci.s b/llvm/test/MC/RISCV/rv32-relaxation-xqci.s index 2bfebce1a1703..b38aa373c90f0 100644 --- a/llvm/test/MC/RISCV/rv32-relaxation-xqci.s +++ b/llvm/test/MC/RISCV/rv32-relaxation-xqci.s @@ -40,7 +40,7 @@ start: # CHECK: qc.e.j {{0x[0-9a-f]+}} c.j undef # CHECK: qc.e.j {{0x[0-9a-f]+}} -# CHECK: R_RISCV_CHERI_SIZE undef +# CHECK: R_RISCV_CUSTOM195 undef c.jal NEAR # CHECK: c.jal {{0x[0-9a-f]+}} @@ -56,7 +56,7 @@ start: # CHECK: qc.e.jal {{0x[0-9a-f]+}} c.jal undef # CHECK: qc.e.jal {{0x[0-9a-f]+}} -# CHECK: R_RISCV_CHERI_SIZE undef +# CHECK: R_RISCV_CUSTOM195 undef jal zero, NEAR # CHECK: c.j {{0x[0-9a-f]+}} @@ -72,7 +72,7 @@ start: # CHECK: qc.e.j {{0x[0-9a-f]+}} jal zero, undef # CHECK: qc.e.j {{0x[0-9a-f]+}} -# CHECK: R_RISCV_CHERI_SIZE undef +# CHECK: R_RISCV_CUSTOM195 undef jal ra, NEAR # CHECK: c.jal {{0x[0-9a-f]+}} @@ -88,7 +88,7 @@ start: # CHECK: qc.e.jal {{0x[0-9a-f]+}} jal ra, undef # CHECK: qc.e.jal {{0x[0-9a-f]+}} -# CHECK: R_RISCV_CHERI_SIZE undef +# CHECK: R_RISCV_CUSTOM195 undef qc.e.j NEAR # CHECK: c.j {{0x[0-9a-f]+}} @@ -104,7 +104,7 @@ start: # CHECK: qc.e.j {{0x[0-9a-f]+}} qc.e.j undef # CHECK: qc.e.j {{0x[0-9a-f]+}} -# CHECK: R_RISCV_CHERI_SIZE undef +# CHECK: R_RISCV_CUSTOM195 undef qc.e.jal NEAR # CHECK: c.jal {{0x[0-9a-f]+}} @@ -120,7 +120,7 @@ start: # CHECK: qc.e.jal {{0x[0-9a-f]+}} qc.e.jal undef # CHECK: qc.e.jal {{0x[0-9a-f]+}} -# CHECK: R_RISCV_CHERI_SIZE undef +# CHECK: R_RISCV_CUSTOM195 undef diff --git a/llvm/test/MC/RISCV/xqcibi-linker-relaxation.s b/llvm/test/MC/RISCV/xqcibi-linker-relaxation.s index 9f4e269372520..098e31c93bc4d 100644 --- a/llvm/test/MC/RISCV/xqcibi-linker-relaxation.s +++ b/llvm/test/MC/RISCV/xqcibi-linker-relaxation.s @@ -15,7 +15,7 @@ branch_over_relaxable: jal x1, foo # CHECK: qc.e.jal 0x0 # CHECK-NEXT: R_RISCV_VENDOR QUALCOMM -# CHECK-NEXT: R_RISCV_CHERI_SIZE foo +# CHECK-NEXT: R_RISCV_CUSTOM195 foo # CHECK-NEXT: R_RISCV_RELAX *ABS* bne a0, a1, branch_over_relaxable # CHECK-NEXT: bne a0, a1, 0x6 diff --git a/llvm/test/MC/RISCV/xqcilb-relocations.s b/llvm/test/MC/RISCV/xqcilb-relocations.s index 88350534db7ee..48c8c6931c8af 100644 --- a/llvm/test/MC/RISCV/xqcilb-relocations.s +++ b/llvm/test/MC/RISCV/xqcilb-relocations.s @@ -21,13 +21,13 @@ this_section: # ASM: qc.e.j undef # OBJ: qc.e.j 0x0 # OBJ-NEXT: R_RISCV_VENDOR QUALCOMM{{$}} -# OBJ-NEXT: R_RISCV_CHERI_SIZE undef{{$}} +# OBJ-NEXT: R_RISCV_CUSTOM195 undef{{$}} qc.e.j undef # ASM: qc.e.jal undef # OBJ-NEXT: qc.e.jal 0x6 # OBJ-NEXT: R_RISCV_VENDOR QUALCOMM{{$}} -# OBJ-NEXT: R_RISCV_CHERI_SIZE undef{{$}} +# OBJ-NEXT: R_RISCV_CUSTOM195 undef{{$}} qc.e.jal undef @@ -42,26 +42,26 @@ qc.e.jal same_section # ASM: qc.e.j same_section_extern # OBJ-NEXT: qc.e.j 0x18 # OBJ-NEXT: R_RISCV_VENDOR QUALCOMM{{$}} -# OBJ-NEXT: R_RISCV_CHERI_SIZE same_section_extern{{$}} +# OBJ-NEXT: R_RISCV_CUSTOM195 same_section_extern{{$}} qc.e.j same_section_extern # ASM: qc.e.jal same_section_extern # OBJ-NEXT: qc.e.jal 0x1e # OBJ-NEXT: R_RISCV_VENDOR QUALCOMM{{$}} -# OBJ-NEXT: R_RISCV_CHERI_SIZE same_section_extern{{$}} +# OBJ-NEXT: R_RISCV_CUSTOM195 same_section_extern{{$}} qc.e.jal same_section_extern # ASM: qc.e.j other_section # OBJ-NEXT: qc.e.j 0x24 # OBJ-NEXT: R_RISCV_VENDOR QUALCOMM{{$}} -# OBJ-NEXT: R_RISCV_CHERI_SIZE other_section{{$}} +# OBJ-NEXT: R_RISCV_CUSTOM195 other_section{{$}} qc.e.j other_section # ASM: qc.e.jal other_section # OBJ-NEXT: qc.e.jal 0x2a # OBJ-NEXT: R_RISCV_VENDOR QUALCOMM{{$}} -# OBJ-NEXT: R_RISCV_CHERI_SIZE other_section{{$}} +# OBJ-NEXT: R_RISCV_CUSTOM195 other_section{{$}} qc.e.jal other_section @@ -81,14 +81,14 @@ same_section_extern: # ASM: qc.e.j same_section # OBJ: qc.e.j 0x38 # OBJ-NEXT: R_RISCV_VENDOR QUALCOMM{{$}} -# OBJ-NEXT: R_RISCV_CHERI_SIZE same_section{{$}} +# OBJ-NEXT: R_RISCV_CUSTOM195 same_section{{$}} # OBJ-NEXT: R_RISCV_RELAX qc.e.j same_section # ASM: qc.e.jal same_section # OBJ-NEXT: qc.e.jal 0x3e # OBJ-NEXT: R_RISCV_VENDOR QUALCOMM{{$}} -# OBJ-NEXT: R_RISCV_CHERI_SIZE same_section{{$}} +# OBJ-NEXT: R_RISCV_CUSTOM195 same_section{{$}} # OBJ-NEXT: R_RISCV_RELAX qc.e.jal same_section @@ -99,14 +99,14 @@ qc.e.j undef # ASM: j undef # OBJ: qc.e.j 0x44 # OBJ-NEXT: R_RISCV_VENDOR QUALCOMM{{$}} -# OBJ-NEXT: R_RISCV_CHERI_SIZE undef{{$}} +# OBJ-NEXT: R_RISCV_CUSTOM195 undef{{$}} # OBJ-NEXT: R_RISCV_RELAX qc.e.jal undef # ASM: jal undef # OBJ: qc.e.jal 0x4a # OBJ-NEXT: R_RISCV_VENDOR QUALCOMM{{$}} -# OBJ-NEXT: R_RISCV_CHERI_SIZE undef{{$}} +# OBJ-NEXT: R_RISCV_CUSTOM195 undef{{$}} # OBJ-NEXT: R_RISCV_RELAX .section .text.other, "ax", @progbits diff --git a/llvm/test/Transforms/RelLookupTableConverter/cheri.ll b/llvm/test/Transforms/RelLookupTableConverter/cheri.ll index 8c3f99c829542..236c31d230680 100644 --- a/llvm/test/Transforms/RelLookupTableConverter/cheri.ll +++ b/llvm/test/Transforms/RelLookupTableConverter/cheri.ll @@ -66,7 +66,7 @@ define ptr addrspace(200) @load_from_string_table(i64 %idx) addrspace(200) { ; PURECAP-ASM: # %bb.0: # %bb ; PURECAP-ASM-NEXT: .LBB0_1: # %bb ; PURECAP-ASM-NEXT: # Label of block must be emitted -; PURECAP-ASM-NEXT: auipcc a1, %captab_pcrel_hi(global) +; PURECAP-ASM-NEXT: auipcc a1, %got_pcrel_hi(global) ; PURECAP-ASM-NEXT: clc a1, %pcrel_lo(.LBB0_1)(a1) ; PURECAP-ASM-NEXT: slli a0, a0, 4 ; PURECAP-ASM-NEXT: cincoffset a0, a1, a0