[CHERI CSA] Subobject representability warning in mqtt.cc

[resistor]

This could be a false positive!

---
MainSourceFile:  '/Users/resistor/Documents/network-stack/lib/mqtt/mqtt.cc'
Diagnostics:
  - DiagnosticName:  clang-analyzer-cheri.SubObjectRepresentability
    DiagnosticMessage:
      Message:         'Field ''coreMQTTContext'' of type ''MQTTContext_t'' (size 128) requires 16 byte alignment for precise bounds; field offset is 8 (aligned to 8); Current bounds: 0-144'
      FilePath:        '/Users/resistor/Documents/network-stack/lib/mqtt/mqtt.cc'
      FileOffset:      1308
      Replacements:    []
      Ranges:
        - FilePath:        '/Users/resistor/Documents/network-stack/lib/mqtt/mqtt.cc'
          FileOffset:      1308
          Length:          36
    Notes:
      - Message:         '8/8 bytes exposed (may expose capability!)'
        FilePath:        '/Users/resistor/Documents/network-stack/lib/mqtt/mqtt.cc'
        FileOffset:      1194
        Replacements:    []
      - Message:         '8/32 bytes exposed (may expose capability!)'
        FilePath:        '/Users/resistor/Documents/network-stack/lib/mqtt/mqtt.cc'
        FileOffset:      1347
        Replacements:    []
      - Message:         Address of a field taken
        FilePath:        '/Users/resistor/Documents/network-stack/lib/mqtt/mqtt.cc'
        FileOffset:      20385
        Replacements:    []
      - Message:         'Field ''coreMQTTContext'' of type ''MQTTContext_t'' (size 128) requires 16 byte alignment for precise bounds; field offset is 8 (aligned to 8); Current bounds: 0-144'
        FilePath:        '/Users/resistor/Documents/network-stack/lib/mqtt/mqtt.cc'
        FileOffset:      1308
        Replacements:    []
        Ranges:
          - FilePath:        '/Users/resistor/Documents/network-stack/lib/mqtt/mqtt.cc'
            FileOffset:      1308
            Length:          36
    Level:           Warning
    BuildDirectory:  '/Users/resistor/Documents/network-stack'
...

[resistor]

This seems to be a false positive in that we are not correctly picking up the cheriot cap format in clang-tidy.

[resistor]

CHERIoT-Platform/llvm-project#208