Add a new 'exception' trace option that prints only on interrupts and exceptions.

Author: rmn30

c_emulator/riscv_config.h

@@ -5,3 +5,4 @@ extern bool config_print_instr;
 extern bool config_print_reg;
 extern bool config_print_mem_access;
 extern bool config_print_platform;
+extern bool config_print_exception;

c_emulator/riscv_prelude.c

@@ -55,3 +55,8 @@ bool get_config_print_platform(unit u)
 {
   return (config_print_platform) ? true : false;
 }
+
+bool get_config_print_exception(unit u)
+{
+  return (config_print_exception) ? true : false;
+}

c_emulator/riscv_prelude.h

@@ -9,8 +9,10 @@ unit print_instr(sail_string s);
 unit print_reg(sail_string s);
 unit print_mem_access(sail_string s);
 unit print_platform(sail_string s);
+unit print_exception(sail_string s);
 
 bool get_config_print_instr(unit u);
 bool get_config_print_reg(unit u);
 bool get_config_print_mem(unit u);
 bool get_config_print_platform(unit u);
+bool get_config_print_exception(unit u);

c_emulator/riscv_sim.c

@@ -85,6 +85,7 @@ bool config_print_reg = true;
 bool config_print_mem_access = true;
 bool config_print_platform = true;
 bool config_print_rvfi = false;
+bool config_print_exception = true;
 int config_use_boot_rom = 
 #ifdef NO_BOOT_ROM
 false
@@ -101,6 +102,7 @@ void set_config_print(char *var, bool val)
     config_print_reg = val;
     config_print_platform = val;
     config_print_rvfi = val;
+    config_print_exception = val;
   } else if (strcmp("instr", var) == 0) {
     config_print_instr = val;
   } else if (strcmp("reg", var) == 0) {
@@ -111,9 +113,11 @@ void set_config_print(char *var, bool val)
     config_print_rvfi = val;
   } else if (strcmp("platform", var) == 0) {
     config_print_platform = val;
+  } else if (strcmp("exception", var) == 0) {
+    config_print_exception = val;
   } else {
     fprintf(stderr, "Unknown trace category: '%s' (should be %s)\n",
-            "instr|reg|mem|platform|all", var);
+            "instr|reg|mem|exception|platform|all", var);
     exit(1);
   }
 }

model/prelude.sail

@@ -79,13 +79,15 @@ val print_platform = {ocaml: "Platform.print_platform", interpreter: "print_endl
 val get_config_print_instr = {ocaml: "Platform.get_config_print_instr", c:"get_config_print_instr"} : unit -> bool
 val get_config_print_reg = {ocaml: "Platform.get_config_print_reg", c:"get_config_print_reg"} : unit -> bool
 val get_config_print_mem = {ocaml: "Platform.get_config_print_mem", c:"get_config_print_mem"} : unit -> bool
+val get_config_print_exception = {ocaml: "Platform.get_config_print_exception", c:"get_config_print_exception"} : unit -> bool
 
 val get_config_print_platform = {ocaml: "Platform.get_config_print_platform", c:"get_config_print_platform"} : unit -> bool
 // defaults for other backends
 function get_config_print_instr () = false
 function get_config_print_reg () = false
 function get_config_print_mem () = false
 function get_config_print_platform () = false
+function get_config_print_exception () = false
 
 val sign_extend : forall 'n 'm, 'm >= 'n. (implicit('m), bits('n)) -> bits('m)
 val zero_extend : forall 'n 'm, 'm >= 'n. (implicit('m), bits('n)) -> bits('m)

model/riscv_step.sail

@@ -35,8 +35,8 @@ function step(step_no : int) -> bool = {
   let (retired, stepped) : (Retired, bool) =
     match dispatchInterrupt(cur_privilege) {
       Some(intr, priv) => {
-        if   get_config_print_instr()
-        then print_bits("Handling interrupt: ", interruptType_to_bits(intr));
+        if get_config_print_instr() | get_config_print_exception()
+        then print("Handling interrupt PC=" ^ BitStr(PC) ^ " IRQ=" ^ BitStr(interruptType_to_bits(intr)));
         handle_interrupt(intr, priv);
         (RETIRE_FAIL, false)
       },