vhdl20008 with vivado #37
Description
this generate elsif sequence isrestricted to VHDL20008 :
When using Xilinx IP flow, it is unclear how to instruct this file to be compiled with VHDL2008 attribute.
Changing the generate structure will change generate labels which will lead to difficulties managing the same cocotb testbenches for NGultra and Xilinx.
For now the patch will be to comment this line like this :
gen_inst_phy_plus_lane: if G_TARGET = "VERSAL" generate
inst_phy_plus_lane : phy_plus_lane
port map(
RST_N => RST_N,
CLK => CLK,
RST_TXCLK_N => rst_sync_gty_n,
LANE_RESET_PPL_OUT => lane_reset_ppl_out,
CLK_TX_OUT => clk_tx_i,
RST_TX_DONE => rst_tx_done,
-- Clock and reset
------------------
CLK_GTY => CLK_REF_P, -- Clock signal
-- FROM Data-link layer
DATA_TX => data_tx_mux,
CAPABILITY_TX => capability_tx_mux,
NEW_DATA_TX => new_data_tx_mux,
VALID_K_CHARAC_TX => valid_k_charac_tx_mux,
FIFO_TX_FULL => fifo_tx_full_ppl,
-- TO Data-link layer
FIFO_RX_RD_EN => fifo_rx_rd_en_demux,
DATA_RX => data_rx_ppl,
FIFO_RX_EMPTY => fifo_rx_empty_ppl,
FIFO_RX_DATA_VALID => fifo_rx_data_valid_ppl,
VALID_K_CHARAC_RX => valid_k_charac_rx_ppl,
FAR_END_CAPA_DL => far_end_capa_dl_ppl,
LANE_ACTIVE_DL => lane_active_ppl,
LANE_RESET_DL => lane_reset_mux,
-- FROM/TO Outside
TX_POS => TX_POS,
TX_NEG => TX_NEG,
RX_POS => RX_POS,
RX_NEG => RX_NEG,
-- PARAMETERS and STATUS
LANE_START => lane_start_ppl,
AUTOSTART => autostart_ppl,
LANE_RESET => lane_reset_ppl,
PARALLEL_LOOPBACK_EN => parallel_loopback_en_ppl,
STANDBY_REASON => standby_reason_ppl,
NEAR_END_SERIAL_LB_EN => near_end_serial_lb_en_ppl,
FAR_END_SERIAL_LB_EN => far_end_serial_lb_en_ppl,
LANE_STATE => lane_state_ppl,
RX_ERROR_CNT => rx_error_cnt_ppl,
RX_ERROR_OVF => rx_error_ovf_ppl,
LOSS_SIGNAL => loss_signal_ppl,
FAR_END_CAPA => far_end_capa_ppl,
RX_POLARITY => rx_polarity_ppl
);
-- elsif G_TARGET = "NG_ULTRA" generate
-- inst_phy_plus_lane : phy_plus_lane_64b
-- port map(
-- RST_N => RST_N,
-- CLK => CLK,
-- RST_TXCLK_N => rst_sync_gty_n,
-- LANE_RESET_PPL_OUT => lane_reset_ppl_out,
-- CLK_TX_OUT => clk_tx_i,
-- RST_TX_DONE => rst_tx_done,
-- -- Clock and reset
-- ------------------
-- CLK_REF_N => CLK_REF_N, -- Clock signal
-- CLK_REF_P => CLK_REF_P,
-- -- FROM Data-link layer
-- DATA_TX => data_tx_mux,
-- CAPABILITY_TX => capability_tx_mux,
-- NEW_DATA_TX => new_data_tx_mux,
-- VALID_K_CHARAC_TX => valid_k_charac_tx_mux,
-- FIFO_TX_FULL => fifo_tx_full_ppl,
-- -- TO Data-link layer
-- FIFO_RX_RD_EN => fifo_rx_rd_en_demux,
-- DATA_RX => data_rx_ppl,
-- FIFO_RX_EMPTY => fifo_rx_empty_ppl,
-- FIFO_RX_DATA_VALID => fifo_rx_data_valid_ppl,
-- VALID_K_CHARAC_RX => valid_k_charac_rx_ppl,
-- FAR_END_CAPA_DL => far_end_capa_dl_ppl,
-- LANE_ACTIVE_DL => lane_active_ppl,
-- LANE_RESET_DL => lane_reset_mux,
-- -- FROM/TO Outside
-- TX_POS => TX_POS,
-- TX_NEG => TX_NEG,
-- RX_POS => RX_POS,
-- RX_NEG => RX_NEG,
-- -- PARAMETERS and STATUS
-- LANE_START => lane_start_ppl,
-- AUTOSTART => autostart_ppl,
-- LANE_RESET => lane_reset_ppl,
-- PARALLEL_LOOPBACK_EN => parallel_loopback_en_ppl,
-- STANDBY_REASON => standby_reason_ppl,
-- NEAR_END_SERIAL_LB_EN => near_end_serial_lb_en_ppl,
-- FAR_END_SERIAL_LB_EN => far_end_serial_lb_en_ppl,
-- LANE_STATE => lane_state_ppl,
-- RX_ERROR_CNT => rx_error_cnt_ppl,
-- RX_ERROR_OVF => rx_error_ovf_ppl,
-- LOSS_SIGNAL => loss_signal_ppl,
-- FAR_END_CAPA => far_end_capa_ppl,
-- RX_POLARITY => rx_polarity_ppl
-- );
end generate;
please check correctness of the XDC constraint file has the patch might change:
spacefibrelight/implementation/app/validation_pf/VEK280_master.xdc
Lines 21 to 22 in f8b7330