Small Refactor of MachineModel to facilitate tests

By allowing MachineModel to be constructed by a SpecsBuffer rather than
a file, we can easily get a MachineModel in any tests that have one as a
dependency.

Author: Quincunx271

include/opt-sched/Scheduler/buffers.h

@@ -96,6 +96,7 @@ class InputBuffer {
 class SpecsBuffer : public InputBuffer {
 public:
   SpecsBuffer();
+  explicit SpecsBuffer(char *buf, long size);
   void ReadSpec(const char *const title, char *value);
   void readLine(char *value, int maxPieceCnt);
   void readLstElmnt(char *value);

include/opt-sched/Scheduler/machine_model.h

@@ -10,19 +10,14 @@ Last Update:  Mar. 2011
 #ifndef OPTSCHED_BASIC_MACHINE_MODEL_H
 #define OPTSCHED_BASIC_MACHINE_MODEL_H
 
-// For class ostream.
-#include <iostream>
-// For class string.
-#include <string>
-// For class vector.
 #include "opt-sched/Scheduler/defines.h"
+#include <string>
 #include <vector>
 
 namespace llvm {
 namespace opt_sched {
 
-using std::string;
-using std::vector;
+class SpecsBuffer;
 
 // The possible types of dependence between two machine instructions.
 enum DependenceType {
@@ -55,7 +50,7 @@ const int MAX_ISSUTYPE_CNT = 20;
 // A description of an instruction type.
 struct InstTypeInfo {
   // The name of the instruction type.
-  string name;
+  std::string name;
   // Whether instructions of this type can be scheduled only in a particular
   // context.
   bool isCntxtDep;
@@ -77,7 +72,7 @@ struct InstTypeInfo {
 // A description of a issue type/FU.
 struct IssueTypeInfo {
   // The name of the issue type.
-  string name;
+  std::string name;
   // How many slots of this issue type the machine has per cycle.
   int slotsCount;
 };
@@ -86,12 +81,13 @@ struct IssueTypeInfo {
 class MachineModel {
 public:
   // Loads a machine model description from a file.
-  MachineModel(const string &modelFile);
+  MachineModel(const std::string &modelFile);
+  MachineModel(SpecsBuffer &buf);
   // A no-op virtual destructor to allow proper subclassing.
   virtual ~MachineModel() {}
 
   // Returns the name of the machine model.
-  const string &GetModelName() const;
+  const std::string &GetModelName() const;
   // Returns the number of instruction types.
   int GetInstTypeCnt() const;
   // Returns the number of issue types (pipelines).
@@ -104,7 +100,7 @@ class MachineModel {
   // Returns the number of registers of a given type.
   int GetPhysRegCnt(int16_t regType) const;
   // Returns the name of a given register type.
-  const string &GetRegTypeName(int16_t regType) const;
+  const std::string &GetRegTypeName(int16_t regType) const;
   // Returns the register type given its name.
   int16_t GetRegTypeByName(const char *const regTypeName) const;
   // Returns the number of issue slots for a given issue type.
@@ -126,8 +122,8 @@ class MachineModel {
   // Returns the instruction type given the name of the instruction as well
   // as the name of the previous instruction (used for context-dependent
   // instructions).
-  InstType GetInstTypeByName(const string &typeName,
-                             const string &prevName = "") const;
+  InstType GetInstTypeByName(const std::string &typeName,
+                             const std::string &prevName = "") const;
   // Return the default instruction type
   InstType getDefaultInstType() const;
   // Return the default issue type
@@ -161,9 +157,9 @@ class MachineModel {
            issueTypes_[0].slotsCount == 1 && !includesUnpipelined_;
   }
   // Add a new instruction type.
-  void AddInstType(InstTypeInfo &instTypeInfo);
+  void AddInstType(InstTypeInfo instTypeInfo);
   // Add a new issue type.
-  void addIssueType(IssueTypeInfo &IssueTypeInfo);
+  void addIssueType(IssueTypeInfo IssueTypeInfo);
 
 protected:
   // Creates an uninitialized machine model. For use by subclasses.
@@ -172,13 +168,13 @@ class MachineModel {
   // A description of a register type.
   struct RegTypeInfo {
     // The name of the register.
-    string name;
+    std::string name;
     // How many register of this type the machine has.
     int count;
   };
 
   // The name of the machine model.
-  string mdlName_;
+  std::string mdlName_;
   // The machine's issue rate. I.e. the total number of issue slots for all
   // issue types.
   int issueRate_;
@@ -188,11 +184,11 @@ class MachineModel {
   bool includesUnpipelined_ = false;
 
   // A vector of instruction type descriptions.
-  vector<InstTypeInfo> instTypes_;
+  std::vector<InstTypeInfo> instTypes_;
   // A vector of register types with their names and counts.
-  vector<RegTypeInfo> registerTypes_;
+  std::vector<RegTypeInfo> registerTypes_;
   // A vector of issue types with their names and slot counts.
-  vector<IssueTypeInfo> issueTypes_;
+  std::vector<IssueTypeInfo> issueTypes_;
 };
 
 } // namespace opt_sched

lib/Scheduler/buffers.cpp

@@ -580,3 +580,6 @@ FUNC_RESULT SpecsBuffer::checkTitle(const char *const title) {
 }
 
 SpecsBuffer::SpecsBuffer() { nxtLineType = NXT_DATA; }
+SpecsBuffer::SpecsBuffer(char *buf, long size) : SpecsBuffer() {
+  SetBuf(buf, size);
+}

lib/Scheduler/machine_model.cpp

@@ -11,11 +11,16 @@
 
 using namespace llvm::opt_sched;
 
-MachineModel::MachineModel(const string &modelFile) {
-  SpecsBuffer buf;
-  char buffer[MAX_NAMESIZE];
+using std::string;
+using std::vector;
 
+MachineModel::MachineModel(const std::string &modelFile) {
+  SpecsBuffer buf;
   buf.Load(modelFile.c_str());
+}
+
+MachineModel::MachineModel(SpecsBuffer &buf) {
+  char buffer[MAX_NAMESIZE];
 
   buf.ReadSpec("MODEL_NAME:", buffer);
   mdlName_ = buffer;
@@ -197,15 +202,15 @@ bool MachineModel::IsFloat(InstType instTypeCode) const {
   return instTypes_[instTypeCode].name[0] == 'f';
 }
 
-void MachineModel::AddInstType(InstTypeInfo &instTypeInfo) {
+void MachineModel::AddInstType(InstTypeInfo instTypeInfo) {
   // If this new instruction type is unpipelined notify the model
   if (!instTypeInfo.pipelined)
     includesUnpipelined_ = true;
 
   instTypes_.push_back(std::move(instTypeInfo));
 }
 
-void MachineModel::addIssueType(IssueTypeInfo &IssueTypeInfo) {
+void MachineModel::addIssueType(IssueTypeInfo IssueTypeInfo) {
   issueTypes_.push_back(std::move(IssueTypeInfo));
 }
 

lib/Scheduler/ready_list.cpp

@@ -3,6 +3,8 @@
 #include "opt-sched/Scheduler/logger.h"
 #include "opt-sched/Scheduler/utilities.h"
 
+#include <iostream>
+
 using namespace llvm::opt_sched;
 
 ReadyList::ReadyList(DataDepGraph *dataDepGraph, SchedPriorities prirts) {

unittests/Basic/CMakeLists.txt

@@ -4,4 +4,5 @@ add_optsched_unittest(OptSchedBasicTests
   LinkedListTest.cpp
   LoggerTest.cpp
   UtilitiesTest.cpp
+  simple_machine_model_test.cpp
   )

unittests/Basic/simple_machine_model.h

@@ -0,0 +1,54 @@
+#ifndef OPTSCHED_SIMPLE_MACHINE_MODEL_H
+#define OPTSCHED_SIMPLE_MACHINE_MODEL_H
+
+#include <string.h> // strdup is in the C header, but not the C++ header
+
+#include "opt-sched/Scheduler/buffers.h"
+#include "opt-sched/Scheduler/machine_model.h"
+
+inline llvm::opt_sched::MachineModel simpleMachineModel() {
+  static constexpr const char SimpleModel[] = R"(
+MODEL_NAME: Simple
+
+# The limit on the total number of instructions that can be issued in one cycle
+ISSUE_RATE: 1
+
+# Each instruction must have an issue type, i.e. a function unit that the instruction uses.
+ISSUE_TYPE_COUNT: 1
+
+# Default issue type for LLVM instructions.
+Default 1
+
+DEP_LATENCY_ANTI: 0
+DEP_LATENCY_OUTPUT: 1
+DEP_LATENCY_OTHER: 1
+
+# This will not be used. Reg type info will be taken from the compiler.
+REG_TYPE_COUNT: 2
+I 1
+F 1
+
+# Set this to the total number of instructions
+INST_TYPE_COUNT: 2
+
+INST_TYPE: artificial
+ISSUE_TYPE: Default
+LATENCY: 0
+PIPELINED: YES
+BLOCKS_CYCLE: NO
+SUPPORTED: NO
+
+INST_TYPE: Inst
+ISSUE_TYPE: Default
+LATENCY: 1
+PIPELINED: YES
+BLOCKS_CYCLE: NO
+SUPPORTED: YES
+  )";
+
+  llvm::opt_sched::SpecsBuffer Buf(strdup(SimpleModel), sizeof(SimpleModel));
+  llvm::opt_sched::MachineModel Model(Buf);
+  return Model;
+}
+
+#endif

unittests/Basic/simple_machine_model_test.cpp

@@ -0,0 +1,12 @@
+#include "simple_machine_model.h"
+
+#include "gtest/gtest.h"
+
+using llvm::opt_sched::MachineModel;
+
+namespace {
+TEST(SimpleMachineModel, CanBeLoaded) {
+  MachineModel Model = simpleMachineModel();
+  EXPECT_EQ(1, Model.GetIssueRate());
+}
+} // namespace