|
| 1 | +#include "ddg.h" |
| 2 | + |
| 3 | +#include "gtest/gtest.h" |
| 4 | + |
| 5 | +using namespace llvm::opt_sched; |
| 6 | + |
| 7 | +namespace { |
| 8 | +TEST(SimpleDDG, CanBeMade) { |
| 9 | + std::shared_ptr<DataDepGraph> DDG = makeDDG(R"( |
| 10 | +dag 7 "Simple" |
| 11 | +{ |
| 12 | +dag_id fake:3 |
| 13 | +dag_weight 1.000000 |
| 14 | +compiler LLVM |
| 15 | +dag_lb -1 |
| 16 | +dag_ub -1 |
| 17 | +nodes |
| 18 | +node 0 "Inst" |
| 19 | + sched_order 0 |
| 20 | + issue_cycle 0 |
| 21 | +node 1 "Inst" |
| 22 | + sched_order 1 |
| 23 | + issue_cycle 1 |
| 24 | +node 2 "Inst" |
| 25 | + sched_order 2 |
| 26 | + issue_cycle 2 |
| 27 | +node 3 "Inst" |
| 28 | + sched_order 3 |
| 29 | + issue_cycle 3 |
| 30 | +node 4 "Inst" |
| 31 | + sched_order 4 |
| 32 | + issue_cycle 4 |
| 33 | +node 5 "artificial" "__optsched_entry" |
| 34 | +node 6 "artificial" |
| 35 | +dependencies |
| 36 | +dep 0 1 "other" 0 |
| 37 | +dep 1 2 "other" 0 |
| 38 | +dep 2 6 "other" 0 |
| 39 | +dep 3 4 "data" 1 |
| 40 | +dep 4 6 "other" 0 |
| 41 | +dep 5 3 "other" 0 |
| 42 | +dep 5 0 "other" 0 |
| 43 | +} |
| 44 | + )"); |
| 45 | + |
| 46 | + EXPECT_EQ(7, DDG->GetNodeCnt()); |
| 47 | +} |
| 48 | + |
| 49 | +TEST(SimpleDDG, CanBeMadeWithRealData) { |
| 50 | + MachineModel Model = simpleMachineModel(); |
| 51 | + { |
| 52 | + InstTypeInfo Info; |
| 53 | + Info.issuType = Model.getDefaultIssueType(); |
| 54 | + Info.name = "ATOMIC_FENCE"; |
| 55 | + Info.isCntxtDep = false; |
| 56 | + Info.ltncy = 0; |
| 57 | + Info.pipelined = true; |
| 58 | + Info.sprtd = true; |
| 59 | + Info.blksCycle = true; |
| 60 | + Model.AddInstType(Info); |
| 61 | + |
| 62 | + Info.name = "S_BARRIER"; |
| 63 | + Model.AddInstType(Info); |
| 64 | + |
| 65 | + Info.name = "S_ADD_I32"; |
| 66 | + Info.ltncy = 1; |
| 67 | + Model.AddInstType(Info); |
| 68 | + |
| 69 | + Info.name = "S_CMP_LT_U32"; |
| 70 | + Info.ltncy = 1; |
| 71 | + Model.AddInstType(Info); |
| 72 | + } |
| 73 | + |
| 74 | + std::shared_ptr<DataDepGraph> DDG = makeDDG(R"( |
| 75 | +dag 7 "Simple" |
| 76 | +{ |
| 77 | +dag_id kernel_c18_sdk_94:3 |
| 78 | +dag_weight 1.000000 |
| 79 | +compiler LLVM |
| 80 | +dag_lb -1 |
| 81 | +dag_ub -1 |
| 82 | +nodes |
| 83 | +node 0 "ATOMIC_FENCE" |
| 84 | + sched_order 0 |
| 85 | + issue_cycle 0 |
| 86 | +node 1 "S_BARRIER" "S_BARRIER" |
| 87 | + sched_order 1 |
| 88 | + issue_cycle 1 |
| 89 | +node 2 "ATOMIC_FENCE" "ATOMIC_FENCE" |
| 90 | + sched_order 2 |
| 91 | + issue_cycle 2 |
| 92 | +node 3 "S_ADD_I32" "S_ADD_I32" |
| 93 | + sched_order 3 |
| 94 | + issue_cycle 3 |
| 95 | +node 4 "S_CMP_LT_U32" "S_CMP_LT_U32" |
| 96 | + sched_order 4 |
| 97 | + issue_cycle 4 |
| 98 | +node 5 "artificial" "__optsched_entry" |
| 99 | +node 6 "artificial" |
| 100 | +dependencies |
| 101 | +dep 0 1 "other" 0 |
| 102 | +dep 1 2 "other" 0 |
| 103 | +dep 2 6 "other" 0 |
| 104 | +dep 3 4 "data" 1 |
| 105 | +dep 4 6 "other" 0 |
| 106 | +dep 5 3 "other" 0 |
| 107 | +dep 5 0 "other" 0 |
| 108 | +} |
| 109 | + )", |
| 110 | + &Model); |
| 111 | + |
| 112 | + EXPECT_EQ(7, DDG->GetNodeCnt()); |
| 113 | +} |
| 114 | +} // namespace |
0 commit comments