[clang][IR] Overload @llvm.thread.pointer to support non-AS0 targets

Author: jrtc27

clang/lib/CodeGen/CGBuiltin.cpp

@@ -5726,8 +5726,9 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl GD, unsigned BuiltinID,
   case Builtin::BI__builtin_thread_pointer: {
     if (!getContext().getTargetInfo().isTLSSupported())
       CGM.ErrorUnsupported(E, "__builtin_thread_pointer");
-    // Fall through - it's already mapped to the intrinsic by ClangBuiltin.
-    break;
+
+    return RValue::get(Builder.CreateIntrinsic(llvm::Intrinsic::thread_pointer,
+                                               {GlobalsInt8PtrTy}, {}));
   }
   case Builtin::BI__builtin_os_log_format:
     return emitBuiltinOSLogFormat(*E);

clang/test/CodeGen/builtins-arm64.c

@@ -10,7 +10,7 @@ void f0(void *a, void *b) {
 
 void *tp (void) {
   return __builtin_thread_pointer ();
-// CHECK-LINUX: call {{.*}} @llvm.thread.pointer()
+// CHECK-LINUX: call {{.*}} @llvm.thread.pointer.p0()
 }
 
 // CHECK: call {{.*}} @llvm.bitreverse.i32(i32 %a)

llvm/include/llvm/IR/Intrinsics.td

@@ -860,7 +860,7 @@ def int_stackrestore  : DefaultAttrsIntrinsic<[], [llvm_anyptr_ty]>,
 
 def int_get_dynamic_area_offset : DefaultAttrsIntrinsic<[llvm_anyint_ty]>;
 
-def int_thread_pointer : DefaultAttrsIntrinsic<[llvm_ptr_ty], [], [IntrNoMem]>,
+def int_thread_pointer : DefaultAttrsIntrinsic<[llvm_anyptr_ty], [], [IntrNoMem]>,
                          ClangBuiltin<"__builtin_thread_pointer">;
 
 // IntrInaccessibleMemOrArgMemOnly is a little more pessimistic than strictly

llvm/lib/IR/AutoUpgrade.cpp

@@ -785,7 +785,8 @@ static bool UpgradeIntrinsicFunction1(Function *F, Function *&NewFn) {
       return true;
     }
     if (Name == "aarch64.thread.pointer" || Name == "arm.thread.pointer") {
-      NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::thread_pointer);
+      NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::thread_pointer,
+                                        F->getReturnType());
       return true;
     }
     if (Name.startswith("arm.neon.vqadds.")) {
@@ -1333,6 +1334,14 @@ static bool UpgradeIntrinsicFunction1(Function *F, Function *&NewFn) {
     }
     break;
 
+  case 't':
+    if (Name == "thread.pointer") {
+      NewFn = Intrinsic::getDeclaration(
+          F->getParent(), Intrinsic::thread_pointer, F->getReturnType());
+      return true;
+    }
+    break;
+
   case 'v': {
     auto *ArgTy = F->arg_empty() ? nullptr : F->arg_begin()->getType();
     if (Name == "va_start") {

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

@@ -24401,7 +24401,8 @@ bool AArch64TargetLowering::shouldNormalizeToSelectSequence(LLVMContext &,
 static Value *UseTlsOffset(IRBuilderBase &IRB, unsigned Offset) {
   Module *M = IRB.GetInsertBlock()->getParent()->getParent();
   Function *ThreadPointerFunc =
-      Intrinsic::getDeclaration(M, Intrinsic::thread_pointer);
+      Intrinsic::getDeclaration(M, Intrinsic::thread_pointer,
+                                IRB.getInt8PtrTy());
   return IRB.CreatePointerCast(
       IRB.CreateConstGEP1_32(IRB.getInt8Ty(), IRB.CreateCall(ThreadPointerFunc),
                              Offset),

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

@@ -17854,12 +17854,14 @@ bool RISCVTargetLowering::preferScalarizeSplat(SDNode *N) const {
 
 static Value *useTpOffset(IRBuilderBase &IRB, unsigned Offset) {
   Module *M = IRB.GetInsertBlock()->getParent()->getParent();
+  unsigned AS = M->getDataLayout().getGlobalsAddressSpace();
   Function *ThreadPointerFunc =
-      Intrinsic::getDeclaration(M, Intrinsic::thread_pointer);
+      Intrinsic::getDeclaration(M, Intrinsic::thread_pointer,
+                                IRB.getInt8PtrTy(AS));
   return IRB.CreatePointerCast(
       IRB.CreateConstGEP1_32(IRB.getInt8Ty(),
                              IRB.CreateCall(ThreadPointerFunc), Offset),
-      IRB.getInt8PtrTy()->getPointerTo(0));
+      IRB.getInt8PtrTy()->getPointerTo(AS));
 }
 
 Value *RISCVTargetLowering::getIRStackGuard(IRBuilderBase &IRB) const {

llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp

@@ -1182,7 +1182,8 @@ Value *HWAddressSanitizer::getHwasanThreadSlotPtr(IRBuilder<> &IRB, Type *Ty) {
     // Android provides a fixed TLS slot for sanitizers. See TLS_SLOT_SANITIZER
     // in Bionic's libc/private/bionic_tls.h.
     Function *ThreadPointerFunc =
-        Intrinsic::getDeclaration(M, Intrinsic::thread_pointer);
+        Intrinsic::getDeclaration(M, Intrinsic::thread_pointer,
+                                  IRB.getInt8PtrTy());
     Value *SlotPtr = IRB.CreatePointerCast(
         IRB.CreateConstGEP1_32(Int8Ty, IRB.CreateCall(ThreadPointerFunc), 0x30),
         Ty->getPointerTo(0));

llvm/test/Assembler/autoupgrade-thread-pointer.ll

@@ -6,14 +6,14 @@ declare ptr @llvm.arm.thread.pointer()
 
 define ptr @test1() {
 ; CHECK: test1()
-; CHECK: call ptr @llvm.thread.pointer()
+; CHECK: call ptr @llvm.thread.pointer.p0()
   %1 = call ptr @llvm.aarch64.thread.pointer()
   ret ptr %1
 }
 
 define ptr @test2() {
 ; CHECK: test2()
-; CHECK: call ptr @llvm.thread.pointer()
+; CHECK: call ptr @llvm.thread.pointer.p0()
   %1 = call ptr @llvm.arm.thread.pointer()
   ret ptr %1
 }

llvm/test/CodeGen/RISCV/cheri/thread-pointer.ll

@@ -0,0 +1,14 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: %riscv32_cheri_purecap_llc < %s | FileCheck %s
+; RUN: %riscv64_cheri_purecap_llc < %s | FileCheck %s
+
+declare ptr addrspace(200) @llvm.thread.pointer.p200()
+
+define ptr addrspace(200) @thread_pointer() nounwind {
+; CHECK-LABEL: thread_pointer:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    cmove ca0, ctp
+; CHECK-NEXT:    ret
+  %1 = tail call ptr addrspace(200) @llvm.thread.pointer.p200()
+  ret ptr addrspace(200) %1
+}

llvm/test/Instrumentation/HWAddressSanitizer/alloca-array.ll

@@ -9,7 +9,7 @@ declare void @use(ptr, ptr)
 define void @test_alloca() sanitize_hwaddress {
 ; CHECK-LABEL: define void @test_alloca
 ; CHECK-SAME: () #[[ATTR0:[0-9]+]] {
-; CHECK-NEXT:    [[TMP1:%.*]] = call ptr @llvm.thread.pointer()
+; CHECK-NEXT:    [[TMP1:%.*]] = call ptr @llvm.thread.pointer.p0()
 ; CHECK-NEXT:    [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48
 ; CHECK-NEXT:    [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 8
 ; CHECK-NEXT:    [[TMP4:%.*]] = ashr i64 [[TMP3]], 3