[RISCV] Drop CHERI-RISC-V-specific assembly modifiers and relocations

LLD is now using a normal GOT so all the captable-related names are a
misnomer, instead they should be the same as the normal GOT ones. We can
also drop various other gratuitously-different relocations and modifiers
whilst here. The idea was to make it possible to support mixing integer
and capability mode instructions when it comes to instructions that need
relocations, but that comes down to the same problem that R_RISCV_RELAX
faces when it comes to .option arch, so we shouldn't be doing something
special here that leads to a bunch of unnecessary divergence.

As far as I know we don't have any assembly in our software stack that
uses these modifiers, it all uses the pseudos that hide this detail.

Author: jrtc27

lld/test/ELF/cheri/riscv/tls.s

@@ -167,7 +167,7 @@ _start:
 
 .if PIC == 0
 	lui a0, %tprel_hi(lvar)
-	cincoffset ca0, ctp, a0, %tprel_cincoffset(lvar)
+	cincoffset ca0, ctp, a0, %tprel_add(lvar)
 	cincoffset ca0, ca0, %tprel_lo(lvar)
 .endif
 

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

@@ -229,9 +229,7 @@ class RISCVAsmParser : public MCTargetAsmParser {
   ParseStatus parseZeroOffsetMemOp(OperandVector &Operands);
   ParseStatus parseOperandWithModifier(OperandVector &Operands);
   ParseStatus parseBareSymbol(OperandVector &Operands);
-  template <bool IsCap = false>
   ParseStatus parseCallSymbol(OperandVector &Operands);
-  template <bool IsCap = false>
   ParseStatus parsePseudoJumpSymbol(OperandVector &Operands);
   ParseStatus parseJALOffset(OperandVector &Operands);
   ParseStatus parseVTypeI(OperandVector &Operands);
@@ -569,16 +567,6 @@ struct RISCVOperand final : public MCParsedAsmOperand {
             VK == RISCVMCExpr::VK_RISCV_CALL_PLT);
   }
 
-  bool isCCallSymbol() const {
-    int64_t Imm;
-    RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
-    // Must be of 'immediate' type but not a constant.
-    if (!isImm() || evaluateConstantImm(getImm(), Imm, VK))
-      return false;
-    return RISCVAsmParser::classifySymbolRef(getImm(), VK) &&
-           VK == RISCVMCExpr::VK_RISCV_CCALL;
-  }
-
   bool isPseudoJumpSymbol() const {
     int64_t Imm;
     RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
@@ -589,16 +577,6 @@ struct RISCVOperand final : public MCParsedAsmOperand {
            VK == RISCVMCExpr::VK_RISCV_CALL;
   }
 
-  bool isPseudoCJumpSymbol() const {
-    int64_t Imm;
-    RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
-    // Must be of 'immediate' type but not a constant.
-    if (!isImm() || evaluateConstantImm(getImm(), Imm, VK))
-      return false;
-    return RISCVAsmParser::classifySymbolRef(getImm(), VK) &&
-           VK == RISCVMCExpr::VK_RISCV_CCALL;
-  }
-
   bool isTPRelAddSymbol() const {
     int64_t Imm;
     RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
@@ -609,16 +587,6 @@ struct RISCVOperand final : public MCParsedAsmOperand {
            VK == RISCVMCExpr::VK_RISCV_TPREL_ADD;
   }
 
-  bool isTPRelCIncOffsetSymbol() const {
-    int64_t Imm;
-    RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
-    // Must be of 'immediate' type but not a constant.
-    if (!isImm() || evaluateConstantImm(getImm(), Imm, VK))
-      return false;
-    return RISCVAsmParser::classifySymbolRef(getImm(), VK) &&
-           VK == RISCVMCExpr::VK_RISCV_TPREL_CINCOFFSET;
-  }
-
   bool isCSRSystemRegister() const { return isSystemRegister(); }
 
   bool isVTypeImm(unsigned N) const {
@@ -1008,19 +976,13 @@ struct RISCVOperand final : public MCParsedAsmOperand {
       return IsValid && (VK == RISCVMCExpr::VK_RISCV_PCREL_HI ||
                          VK == RISCVMCExpr::VK_RISCV_GOT_HI ||
                          VK == RISCVMCExpr::VK_RISCV_TLS_GOT_HI ||
-                         VK == RISCVMCExpr::VK_RISCV_TLS_GD_HI ||
-                         VK == RISCVMCExpr::VK_RISCV_CAPTAB_PCREL_HI ||
-                         VK == RISCVMCExpr::VK_RISCV_TLS_IE_CAPTAB_PCREL_HI ||
-                         VK == RISCVMCExpr::VK_RISCV_TLS_GD_CAPTAB_PCREL_HI);
+                         VK == RISCVMCExpr::VK_RISCV_TLS_GD_HI);
     } else {
       return isUInt<20>(Imm) && (VK == RISCVMCExpr::VK_RISCV_None ||
                                  VK == RISCVMCExpr::VK_RISCV_PCREL_HI ||
                                  VK == RISCVMCExpr::VK_RISCV_GOT_HI ||
                                  VK == RISCVMCExpr::VK_RISCV_TLS_GOT_HI ||
-                                 VK == RISCVMCExpr::VK_RISCV_TLS_GD_HI ||
-                                 VK == RISCVMCExpr::VK_RISCV_CAPTAB_PCREL_HI ||
-                                 VK == RISCVMCExpr::VK_RISCV_TLS_IE_CAPTAB_PCREL_HI ||
-                                 VK == RISCVMCExpr::VK_RISCV_TLS_GD_CAPTAB_PCREL_HI);
+                                 VK == RISCVMCExpr::VK_RISCV_TLS_GD_HI);
     }
   }
 
@@ -1665,24 +1627,18 @@ bool RISCVAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
     SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc();
     return Error(ErrorLoc, "operand must be a bare symbol name");
   }
-  case Match_InvalidPseudoJumpSymbol:
-  case Match_InvalidPseudoCJumpSymbol: {
+  case Match_InvalidPseudoJumpSymbol: {
     SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc();
     return Error(ErrorLoc, "operand must be a valid jump target");
   }
-  case Match_InvalidCallSymbol:
-  case Match_InvalidCCallSymbol: {
+  case Match_InvalidCallSymbol: {
     SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc();
     return Error(ErrorLoc, "operand must be a bare symbol name");
   }
   case Match_InvalidTPRelAddSymbol: {
     SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc();
     return Error(ErrorLoc, "operand must be a symbol with %tprel_add modifier");
   }
-  case Match_InvalidTPRelCIncOffsetSymbol: {
-    SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc();
-    return Error(ErrorLoc, "operand must be a symbol with %tprel_cincoffset modifier");
-  }
   case Match_InvalidRTZArg: {
     SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc();
     return Error(ErrorLoc, "operand must be 'rtz' floating-point rounding mode");
@@ -2250,7 +2206,6 @@ ParseStatus RISCVAsmParser::parseBareSymbol(OperandVector &Operands) {
   return ParseStatus::Success;
 }
 
-template <bool IsCap>
 ParseStatus RISCVAsmParser::parseCallSymbol(OperandVector &Operands) {
   SMLoc S = getLoc();
   const MCExpr *Res;
@@ -2268,17 +2223,12 @@ ParseStatus RISCVAsmParser::parseCallSymbol(OperandVector &Operands) {
 
   SMLoc E = SMLoc::getFromPointer(S.getPointer() + Identifier.size());
 
-  RISCVMCExpr::VariantKind Kind;
-  if (IsCap) {
-    Kind = RISCVMCExpr::VK_RISCV_CCALL;
-    // Both relocations are the same for RISC-V, so CHERI-RISC-V only provides
-    // a single relocation, but be friendly and permit the redundant suffix.
-    Identifier.consume_back("@plt");
-  } else {
-    Kind = RISCVMCExpr::VK_RISCV_CALL;
-    if (Identifier.consume_back("@plt"))
-      Kind = RISCVMCExpr::VK_RISCV_CALL_PLT;
-  }
+  RISCVMCExpr::VariantKind Kind = RISCVMCExpr::VK_RISCV_CALL;
+  // CHERI-RISC-V always uses the fixed relocation but never prints the suffix.
+  // However, we allow the redundant suffix to be provided anyway.
+  if (Identifier.consume_back("@plt") &&
+      !getSTI().hasFeature(RISCV::FeatureCapMode))
+    Kind = RISCVMCExpr::VK_RISCV_CALL_PLT;
 
   MCSymbol *Sym = getContext().getOrCreateSymbol(Identifier);
   Res = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, getContext());
@@ -2287,7 +2237,6 @@ ParseStatus RISCVAsmParser::parseCallSymbol(OperandVector &Operands) {
   return ParseStatus::Success;
 }
 
-template <bool IsCap>
 ParseStatus RISCVAsmParser::parsePseudoJumpSymbol(OperandVector &Operands) {
   SMLoc S = getLoc();
   SMLoc E;
@@ -2301,9 +2250,7 @@ ParseStatus RISCVAsmParser::parsePseudoJumpSymbol(OperandVector &Operands) {
           MCSymbolRefExpr::VariantKind::VK_PLT)
     return Error(S, "operand must be a valid jump target");
 
-  RISCVMCExpr::VariantKind Kind =
-      IsCap ? RISCVMCExpr::VK_RISCV_CCALL : RISCVMCExpr::VK_RISCV_CALL;
-  Res = RISCVMCExpr::create(Res, Kind, getContext());
+  Res = RISCVMCExpr::create(Res, RISCVMCExpr::VK_RISCV_CALL, getContext());
   Operands.push_back(RISCVOperand::createImm(Res, S, E, isRV64()));
   return ParseStatus::Success;
 }
@@ -3704,14 +3651,13 @@ void RISCVAsmParser::emitCapLoadGlobalCap(MCInst &Inst, SMLoc IDLoc,
   // captable-indirect addressing of global symbols in the PC-relative ABI:
   //   clgc rdest, symbol
   // expands to
-  //   TmpLabel: AUIPCC cdest, %captab_pcrel_hi(symbol)
+  //   TmpLabel: AUIPCC cdest, %got_pcrel_hi(symbol)
   //             CLC cdest, %pcrel_lo(TmpLabel)(cdest)
   MCOperand DestReg = Inst.getOperand(0);
   const MCExpr *Symbol = Inst.getOperand(1).getExpr();
   unsigned SecondOpcode = isRV64() ? RISCV::CLC_128 : RISCV::CLC_64;
-  emitAuipccInstPair(DestReg, DestReg, Symbol,
-                     RISCVMCExpr::VK_RISCV_CAPTAB_PCREL_HI, SecondOpcode,
-                     IDLoc, Out);
+  emitAuipccInstPair(DestReg, DestReg, Symbol, RISCVMCExpr::VK_RISCV_GOT_HI,
+                     SecondOpcode, IDLoc, Out);
 }
 
 void RISCVAsmParser::emitCapLoadTLSIEAddress(MCInst &Inst, SMLoc IDLoc,
@@ -3720,15 +3666,14 @@ void RISCVAsmParser::emitCapLoadTLSIEAddress(MCInst &Inst, SMLoc IDLoc,
   // in initial-exec TLS model addressing of global symbols:
   //   cla.tls.ie rdest, symbol
   // expands to
-  //   TmpLabel: AUIPCC cdest, %tls_ie_captab_pcrel_hi(symbol)
+  //   TmpLabel: AUIPCC cdest, %tls_ie_pcrel_hi(symbol)
   //             CLx rdest, %pcrel_lo(TmpLabel)(cdest)
   MCOperand DestReg = Inst.getOperand(0);
   MCOperand TmpReg = MCOperand::createReg(convertGPRToGPCR(DestReg.getReg()));
   const MCExpr *Symbol = Inst.getOperand(1).getExpr();
   unsigned SecondOpcode = isRV64() ? RISCV::CLD : RISCV::CLW;
-  emitAuipccInstPair(DestReg, TmpReg, Symbol,
-                     RISCVMCExpr::VK_RISCV_TLS_IE_CAPTAB_PCREL_HI, SecondOpcode,
-                     IDLoc, Out);
+  emitAuipccInstPair(DestReg, TmpReg, Symbol, RISCVMCExpr::VK_RISCV_TLS_GOT_HI,
+                     SecondOpcode, IDLoc, Out);
 }
 
 void RISCVAsmParser::emitCapLoadTLSGDCap(MCInst &Inst, SMLoc IDLoc,
@@ -3741,8 +3686,7 @@ void RISCVAsmParser::emitCapLoadTLSGDCap(MCInst &Inst, SMLoc IDLoc,
   //             CINCOFFSET cdest, cdest, %pcrel_lo(TmpLabel)
   MCOperand DestReg = Inst.getOperand(0);
   const MCExpr *Symbol = Inst.getOperand(1).getExpr();
-  emitAuipccInstPair(DestReg, DestReg, Symbol,
-                     RISCVMCExpr::VK_RISCV_TLS_GD_CAPTAB_PCREL_HI,
+  emitAuipccInstPair(DestReg, DestReg, Symbol, RISCVMCExpr::VK_RISCV_TLS_GD_HI,
                      RISCV::CIncOffsetImm, IDLoc, Out);
 }
 
@@ -3754,7 +3698,7 @@ bool RISCVAsmParser::checkPseudoCIncOffsetTPRel(MCInst &Inst,
   if (Inst.getOperand(1).getReg() != RISCV::C4) {
     SMLoc ErrorLoc = ((RISCVOperand &)*Operands[2]).getStartLoc();
     return Error(ErrorLoc, "the first input operand must be ctp/c4 when using "
-                           "%tprel_cincoffset modifier");
+                           "%tprel_add modifier");
   }
 
   return false;

llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp

@@ -94,16 +94,6 @@ RISCVAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
 
       {"fixup_riscv_set_6b", 2, 6, 0},
       {"fixup_riscv_sub_6b", 2, 6, 0},
-
-      {"fixup_riscv_captab_pcrel_hi20", 12, 20, MCFixupKindInfo::FKF_IsPCRel},
-      {"fixup_riscv_tprel_cincoffset", 0, 0, 0},
-      {"fixup_riscv_tls_ie_captab_pcrel_hi20", 12, 20,
-       MCFixupKindInfo::FKF_IsPCRel},
-      {"fixup_riscv_tls_gd_captab_pcrel_hi20", 12, 20,
-       MCFixupKindInfo::FKF_IsPCRel},
-      {"fixup_riscv_cjal", 12, 20, MCFixupKindInfo::FKF_IsPCRel},
-      {"fixup_riscv_ccall", 0, 64, MCFixupKindInfo::FKF_IsPCRel},
-      {"fixup_riscv_rvc_cjump", 2, 11, MCFixupKindInfo::FKF_IsPCRel},
   };
   static_assert((std::size(Infos)) == RISCV::NumTargetFixupKinds,
                 "Not all fixup kinds added to Infos array");
@@ -142,9 +132,6 @@ bool RISCVAsmBackend::shouldForceRelocation(const MCAssembler &Asm,
   case RISCV::fixup_riscv_got_hi20:
   case RISCV::fixup_riscv_tls_got_hi20:
   case RISCV::fixup_riscv_tls_gd_hi20:
-  case RISCV::fixup_riscv_captab_pcrel_hi20:
-  case RISCV::fixup_riscv_tls_ie_captab_pcrel_hi20:
-  case RISCV::fixup_riscv_tls_gd_captab_pcrel_hi20:
     return true;
   }
 
@@ -181,7 +168,6 @@ bool RISCVAsmBackend::fixupNeedsRelaxationAdvanced(const MCFixup &Fixup,
     // in the range [-256, 254].
     return Offset > 254 || Offset < -256;
   case RISCV::fixup_riscv_rvc_jump:
-  case RISCV::fixup_riscv_rvc_cjump:
     // For compressed jump instructions the immediate must be
     // in the range [-2048, 2046].
     return Offset > 2046 || Offset < -2048;
@@ -419,11 +405,8 @@ static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
   case RISCV::fixup_riscv_got_hi20:
   case RISCV::fixup_riscv_tls_got_hi20:
   case RISCV::fixup_riscv_tls_gd_hi20:
-  case RISCV::fixup_riscv_captab_pcrel_hi20:
   case FK_Cap_8:
   case FK_Cap_16:
-  case RISCV::fixup_riscv_tls_ie_captab_pcrel_hi20:
-  case RISCV::fixup_riscv_tls_gd_captab_pcrel_hi20:
     llvm_unreachable("Relocation should be unconditionally forced\n");
   case RISCV::fixup_riscv_set_8:
   case RISCV::fixup_riscv_add_8:
@@ -463,8 +446,7 @@ static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
   case RISCV::fixup_riscv_tprel_hi20:
     // Add 1 if bit 11 is 1, to compensate for low 12 bits being negative.
     return ((Value + 0x800) >> 12) & 0xfffff;
-  case RISCV::fixup_riscv_jal:
-  case RISCV::fixup_riscv_cjal: {
+  case RISCV::fixup_riscv_jal: {
     if (!isInt<21>(Value))
       Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
     if (Value & 0x1)
@@ -500,17 +482,15 @@ static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
     return Value;
   }
   case RISCV::fixup_riscv_call:
-  case RISCV::fixup_riscv_call_plt:
-  case RISCV::fixup_riscv_ccall: {
+  case RISCV::fixup_riscv_call_plt: {
     // Jalr will add UpperImm with the sign-extended 12-bit LowerImm,
     // we need to add 0x800ULL before extract upper bits to reflect the
     // effect of the sign extension.
     uint64_t UpperImm = (Value + 0x800ULL) & 0xfffff000ULL;
     uint64_t LowerImm = Value & 0xfffULL;
     return UpperImm | ((LowerImm << 20) << 32);
   }
-  case RISCV::fixup_riscv_rvc_jump:
-  case RISCV::fixup_riscv_rvc_cjump: {
+  case RISCV::fixup_riscv_rvc_jump: {
     // Need to produce offset[11|4|9:8|10|6|7|3:1|5] from the 11-bit Value.
     unsigned Bit11  = (Value >> 11) & 0x1;
     unsigned Bit4   = (Value >> 4) & 0x1;

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

@@ -227,11 +227,6 @@ enum {
   MO_TPREL_ADD = 10,
   MO_TLS_GOT_HI = 11,
   MO_TLS_GD_HI = 12,
-  MO_CAPTAB_PCREL_HI = 13,
-  MO_TPREL_CINCOFFSET = 14,
-  MO_TLS_IE_CAPTAB_PCREL_HI = 15,
-  MO_TLS_GD_CAPTAB_PCREL_HI = 16,
-  MO_CCALL = 17,
 
   // Used to differentiate between target-specific "direct" flags and "bitmask"
   // flags. A machine operand can only have one "direct" flag, but can have

llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp

@@ -89,18 +89,6 @@ unsigned RISCVELFObjectWriter::getRelocType(MCContext &Ctx,
       return ELF::R_RISCV_CALL_PLT;
     case RISCV::fixup_riscv_call_plt:
       return ELF::R_RISCV_CALL_PLT;
-    case RISCV::fixup_riscv_captab_pcrel_hi20:
-      return ELF::R_RISCV_CHERI_CAPTAB_PCREL_HI20;
-    case RISCV::fixup_riscv_tls_ie_captab_pcrel_hi20:
-      return ELF::R_RISCV_CHERI_TLS_IE_CAPTAB_PCREL_HI20;
-    case RISCV::fixup_riscv_tls_gd_captab_pcrel_hi20:
-      return ELF::R_RISCV_CHERI_TLS_GD_CAPTAB_PCREL_HI20;
-    case RISCV::fixup_riscv_cjal:
-      return ELF::R_RISCV_CHERI_CJAL;
-    case RISCV::fixup_riscv_ccall:
-      return ELF::R_RISCV_CHERI_CCALL;
-    case RISCV::fixup_riscv_rvc_cjump:
-      return ELF::R_RISCV_CHERI_RVC_CJUMP;
     case RISCV::fixup_riscv_add_8:
       return ELF::R_RISCV_ADD8;
     case RISCV::fixup_riscv_sub_8:
@@ -169,8 +157,6 @@ unsigned RISCVELFObjectWriter::getRelocType(MCContext &Ctx,
       return ELF::R_RISCV_NONE;
     }
     return ELF::R_RISCV_CHERI_CAPABILITY;
-  case RISCV::fixup_riscv_tprel_cincoffset:
-    return ELF::R_RISCV_CHERI_TPREL_CINCOFFSET;
   case RISCV::fixup_riscv_set_6b:
     return ELF::R_RISCV_SET6;
   case RISCV::fixup_riscv_sub_6b:

llvm/lib/Target/RISCV/MCTargetDesc/RISCVFixupKinds.h

@@ -107,29 +107,6 @@ enum Fixups {
   // DWARF CFA.
   fixup_riscv_sub_6b,
 
-  // fixup_riscv_captab_pcrel_hi20 - 20-bit fixup corresponding to
-  // captab_pcrel_hi(foo) for instructions like auipcc
-  fixup_riscv_captab_pcrel_hi20,
-  // fixup_riscv_tprel_cincoffset - A fixup corresponding to
-  // %tprel_cincoffset(foo) for the cincoffset_tls instruction. Used to provide
-  // a hint to the linker.
-  fixup_riscv_tprel_cincoffset,
-  // fixup_riscv_tls_ie_captab_pcrel_hi20 - 20-bit fixup corresponding to
-  // tls_ie_captab_pcrel_hi(foo) for instructions like auipcc
-  fixup_riscv_tls_ie_captab_pcrel_hi20,
-  // fixup_riscv_tls_gd_captab_pcrel_hi20 - 20-bit fixup corresponding to
-  // tls_gd_captab_pcrel_hi(foo) for instructions like auipcc
-  fixup_riscv_tls_gd_captab_pcrel_hi20,
-  // fixup_riscv_cjal - 20-bit fixup for symbol references in the cjal
-  // instruction
-  fixup_riscv_cjal,
-  // fixup_riscv_call - A fixup representing a ccall attached to the auipcc
-  // instruction in a pair composed of adjacent auipcc+cjalr instructions.
-  fixup_riscv_ccall,
-  // fixup_riscv_rvc_cjump - 11-bit fixup for symbol references in the
-  // compressed capability jump instruction
-  fixup_riscv_rvc_cjump,
-
   // Used as a sentinel, must be the last
   fixup_riscv_invalid,
   NumTargetFixupKinds = fixup_riscv_invalid - FirstTargetFixupKind