Skip to content

Commit a3b146b

Browse files
arichardsonarichardson
committed
[CHERI StdCompat] Expand explicit mode stores using mode-switching
Same as the previous commit.
1 parent b35db52 commit a3b146b

File tree

3 files changed

+377
-53
lines changed

3 files changed

+377
-53
lines changed

‎llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -151,6 +151,12 @@ bool RISCVExpandPseudo::expandMI(MachineBasicBlock &MBB,
151151
EXPAND_MODE(LD)
152152
EXPAND_MODE(LC_64)
153153
EXPAND_MODE(LC_128)
154+
EXPAND_MODE(SB)
155+
EXPAND_MODE(SH)
156+
EXPAND_MODE(SW)
157+
EXPAND_MODE(SD)
158+
EXPAND_MODE(SC_64)
159+
EXPAND_MODE(SC_128)
154160

155161
case RISCV::PseudoCLA_TLS_IE:
156162
return expandCapLoadTLSIEAddress(MBB, MBBI, NextMBBI);

‎llvm/lib/Target/RISCV/RISCVInstrInfoXCheri.td

Lines changed: 50 additions & 53 deletions
Original file line numberDiff line numberDiff line change
@@ -188,6 +188,20 @@ class CheriStore_r<bits<5> op, string opcodestr, RegisterClass rs2Class,
188188
(ins rs2Class:$rs2, rs1Operand:$rs1),
189189
opcodestr, "$rs2, $rs1">;
190190

191+
multiclass ExplicitCheriStore_r<bits<5> op, string opcodestr, RegisterClass rs2Class,
192+
RegisterOperand rs1Operand,
193+
list<Predicate> ExtraPreds = []> {
194+
let Predicates = !listconcat([HasXCheriAll], ExtraPreds) in
195+
def NAME: CheriStore_r<op, opcodestr, rs2Class, rs1Operand>;
196+
// Adding a mode switch either side of the load expands to 3 instructions.
197+
// The predicate here is HasCheriCommon, since in the xcheri case we can
198+
// just expand this to an explicit mode load.
199+
let hasSideEffects = 0, mayLoad = 0, mayStore = 1, Size = 12,
200+
Predicates = !listconcat([HasCheriCommon], ExtraPreds) in
201+
def Pseudo_#NAME : Pseudo<(outs), (ins rs2Class:$rs2, rs1Operand:$rs1), [],
202+
"pseudo_"#opcodestr, "$rs2, $rs1">;
203+
}
204+
191205
let hasSideEffects = 0, mayLoad = 0, mayStore = 1, Constraints = "$rd = $rs2" in
192206
class CheriStoreCond_r<bits<5> op, string opcodestr, RegisterClass rs2Class,
193207
RegisterOperand rs1Operand>
@@ -574,22 +588,13 @@ defm LC_64_DDC : ExplicitCheriLoad_r<0b00011, "lc.ddc", GPCR, GPRMemZeroOffset,
574588

575589
defm LC_128_DDC : ExplicitCheriLoad_r<0b10111, "lc.ddc", GPCR, GPRMemZeroOffset, [IsRV64]>;
576590

577-
let Predicates = [HasXCheriAll] in {
578-
def SB_DDC : CheriStore_r<0b00000, "sb.ddc", GPR, GPRMemZeroOffset>;
579-
def SH_DDC : CheriStore_r<0b00001, "sh.ddc", GPR, GPRMemZeroOffset>;
580-
def SW_DDC : CheriStore_r<0b00010, "sw.ddc", GPR, GPRMemZeroOffset>;
581-
}
582-
583-
let Predicates = [HasXCheriAll, IsRV64] in {
584-
def SD_DDC : CheriStore_r<0b00011, "sd.ddc", GPR, GPRMemZeroOffset>;
585-
}
586-
587-
let DecoderNamespace = "RISCV32Only_",
588-
Predicates = [HasXCheriAll, IsRV32] in
589-
def SC_DDC_64 : CheriStore_r<0b00011, "sc.ddc", GPCR, GPRMemZeroOffset>;
590-
591-
let Predicates = [HasXCheriAll, IsRV64] in
592-
def SC_DDC_128 : CheriStore_r<0b00100, "sc.ddc", GPCR, GPRMemZeroOffset>;
591+
defm SB_DDC : ExplicitCheriStore_r<0b00000, "sb.ddc", GPR, GPRMemZeroOffset>;
592+
defm SH_DDC : ExplicitCheriStore_r<0b00001, "sh.ddc", GPR, GPRMemZeroOffset>;
593+
defm SW_DDC : ExplicitCheriStore_r<0b00010, "sw.ddc", GPR, GPRMemZeroOffset>;
594+
defm SD_DDC : ExplicitCheriStore_r<0b00011, "sd.ddc", GPR, GPRMemZeroOffset, [IsRV64]>;
595+
let DecoderNamespace = "RISCV32Only_" in
596+
defm SC_64_DDC : ExplicitCheriStore_r<0b00011, "sc.ddc", GPCR, GPRMemZeroOffset, [IsRV32]>;
597+
defm SC_128_DDC : ExplicitCheriStore_r<0b00100, "sc.ddc", GPCR, GPRMemZeroOffset, [IsRV64]>;
593598

594599
defm LB_CAP : ExplicitCheriLoad_r<0b01000, "lb.cap", GPR, GPCRMemZeroOffset>;
595600
defm LH_CAP : ExplicitCheriLoad_r<0b01001, "lh.cap", GPR, GPCRMemZeroOffset>;
@@ -605,22 +610,13 @@ defm LC_64_CAP : ExplicitCheriLoad_r<0b01011, "lc.cap", GPCR, GPCRMemZeroOffset
605610

606611
defm LC_128_CAP : ExplicitCheriLoad_r<0b11111, "lc.cap", GPCR, GPCRMemZeroOffset, [IsRV64]>;
607612

608-
let Predicates = [HasXCheriAll] in {
609-
def SB_CAP : CheriStore_r<0b01000, "sb.cap", GPR, GPCRMemZeroOffset>;
610-
def SH_CAP : CheriStore_r<0b01001, "sh.cap", GPR, GPCRMemZeroOffset>;
611-
def SW_CAP : CheriStore_r<0b01010, "sw.cap", GPR, GPCRMemZeroOffset>;
612-
}
613-
614-
let Predicates = [HasXCheriAll, IsRV64] in {
615-
def SD_CAP : CheriStore_r<0b01011, "sd.cap", GPR, GPCRMemZeroOffset>;
616-
}
617-
618-
let DecoderNamespace = "RISCV32Only_",
619-
Predicates = [HasXCheriAll, IsRV32] in
620-
def SC_CAP_64 : CheriStore_r<0b01011, "sc.cap", GPCR, GPCRMemZeroOffset>;
621-
622-
let Predicates = [HasXCheriAll, IsRV64] in
623-
def SC_CAP_128 : CheriStore_r<0b01100, "sc.cap", GPCR, GPCRMemZeroOffset>;
613+
defm SB_CAP : ExplicitCheriStore_r<0b01000, "sb.cap", GPR, GPCRMemZeroOffset>;
614+
defm SH_CAP : ExplicitCheriStore_r<0b01001, "sh.cap", GPR, GPCRMemZeroOffset>;
615+
defm SW_CAP : ExplicitCheriStore_r<0b01010, "sw.cap", GPR, GPCRMemZeroOffset>;
616+
defm SD_CAP : ExplicitCheriStore_r<0b01011, "sd.cap", GPR, GPCRMemZeroOffset, [IsRV64]>;
617+
let DecoderNamespace = "RISCV32Only_" in
618+
defm SC_64_CAP : ExplicitCheriStore_r<0b01011, "sc.cap", GPCR, GPCRMemZeroOffset, [IsRV32]>;
619+
defm SC_128_CAP : ExplicitCheriStore_r<0b01100, "sc.cap", GPCR, GPCRMemZeroOffset, [IsRV64]>;
624620

625621
let Predicates = [HasXCheriAll, HasStdExtA] in {
626622
def LR_B_DDC : CheriLoad_r<0b10000, "lr.b.ddc", GPR, GPRMemZeroOffset>;
@@ -1525,7 +1521,8 @@ multiclass CheriExplicitStPat<PatFrag StoreOp, RVInst Inst,
15251521
RegisterClass StTy, RegisterClass AddrTy,
15261522
ValueType StoreVt = XLenVT,
15271523
ValueType AddrVt = XLenVT> {
1528-
def : Pat<(StoreOp (StoreVt StTy:$rs2), (AddrVt AddrTy:$rs1)), (Inst StTy:$rs2, AddrTy:$rs1)>;
1524+
def : Pat<(StoreOp (StoreVt StTy:$rs2), (AddrVt AddrTy:$rs1)),
1525+
(!cast<Pseudo>("Pseudo_"#Inst) StTy:$rs2, AddrTy:$rs1)>;
15291526
}
15301527

15311528
/// DDC-relative loads
@@ -1565,33 +1562,33 @@ def : Pat<(load (XLenVT GPR:$rs1)), (FMV_D_X (Pseudo_LD_DDC (XLenVT GPR:$rs1)))>
15651562

15661563
/// DDC-relative stores
15671564

1568-
let Predicates = [HasXCheriAll, IsCapMode] in {
1565+
let Predicates = [HasCheriCommon, IsCapMode] in {
15691566
defm : CheriExplicitStPat<truncstorei8, SB_DDC, GPR, GPR>;
15701567
defm : CheriExplicitStPat<truncstorei16, SH_DDC, GPR, GPR>;
15711568
}
15721569

1573-
let Predicates = [HasXCheriAll, IsCapMode, IsRV32] in {
1570+
let Predicates = [HasCheriCommon, IsCapMode, IsRV32] in {
15741571
defm : CheriExplicitStPat<store, SW_DDC, GPR, GPR>;
1575-
defm : CheriExplicitStPat<store, SC_DDC_64, GPCR, GPR, CLenVT, XLenVT>;
1572+
defm : CheriExplicitStPat<store, SC_64_DDC, GPCR, GPR, CLenVT, XLenVT>;
15761573
}
15771574

1578-
let Predicates = [HasXCheriAll, IsCapMode, IsRV64] in {
1575+
let Predicates = [HasCheriCommon, IsCapMode, IsRV64] in {
15791576
defm : CheriExplicitStPat<truncstorei32, SW_DDC, GPR, GPR>;
15801577
defm : CheriExplicitStPat<store, SD_DDC, GPR, GPR>;
1581-
defm : CheriExplicitStPat<store, SC_DDC_128, GPCR, GPR, CLenVT, XLenVT>;
1578+
defm : CheriExplicitStPat<store, SC_128_DDC, GPCR, GPR, CLenVT, XLenVT>;
15821579
}
15831580

1584-
let Predicates = [HasXCheriAll, IsCapMode, HasStdExtF] in
1581+
let Predicates = [HasCheriCommon, IsCapMode, HasStdExtF] in
15851582
def : Pat<(store FPR32:$rs2, (XLenVT GPR:$rs1)),
1586-
(SW_DDC (FMV_X_W FPR32:$rs2), (XLenVT GPR:$rs1))>;
1583+
(Pseudo_SW_DDC (FMV_X_W FPR32:$rs2), (XLenVT GPR:$rs1))>;
15871584

1588-
let Predicates = [HasXCheriAll, IsCapMode, HasStdExtD, IsRV32] in
1585+
let Predicates = [HasCheriCommon, IsCapMode, HasStdExtD, IsRV32] in
15891586
def : Pat<(store FPR64:$rs2, (XLenVT GPR:$rs1)),
15901587
(KILL (SplitStoreF64Pseudo FPR64:$rs2, (XLenVT GPR:$rs1)))>;
15911588

1592-
let Predicates = [HasXCheriAll, IsCapMode, HasStdExtD, IsRV64] in
1589+
let Predicates = [HasCheriCommon, IsCapMode, HasStdExtD, IsRV64] in
15931590
def : Pat<(store FPR64:$rs2, (XLenVT GPR:$rs1)),
1594-
(SD_DDC (FMV_X_D FPR64:$rs2), (XLenVT GPR:$rs1))>;
1591+
(Pseudo_SD_DDC (FMV_X_D FPR64:$rs2), (XLenVT GPR:$rs1))>;
15951592

15961593
/// Capability loads
15971594

@@ -1630,33 +1627,33 @@ def : Pat<(load GPCR:$rs1), (FMV_D_X (Pseudo_LD_CAP GPCR:$rs1))>;
16301627

16311628
/// Capability stores
16321629

1633-
let Predicates = [HasXCheriAll, NotCapMode] in {
1630+
let Predicates = [HasCheriCommon, NotCapMode] in {
16341631
defm : CheriExplicitStPat<truncstorei8, SB_CAP, GPR, GPCR, XLenVT, CLenVT>;
16351632
defm : CheriExplicitStPat<truncstorei16, SH_CAP, GPR, GPCR, XLenVT, CLenVT>;
16361633
}
16371634

1638-
let Predicates = [HasXCheriAll, NotCapMode, IsRV32] in {
1635+
let Predicates = [HasCheriCommon, NotCapMode, IsRV32] in {
16391636
defm : CheriExplicitStPat<store, SW_CAP, GPR, GPCR, XLenVT, CLenVT>;
1640-
defm : CheriExplicitStPat<store, SC_CAP_64, GPCR, GPCR, CLenVT, CLenVT>;
1637+
defm : CheriExplicitStPat<store, SC_64_CAP, GPCR, GPCR, CLenVT, CLenVT>;
16411638
}
16421639

1643-
let Predicates = [HasXCheriAll, NotCapMode, IsRV64] in {
1640+
let Predicates = [HasCheriCommon, NotCapMode, IsRV64] in {
16441641
defm : CheriExplicitStPat<truncstorei32, SW_CAP, GPR, GPCR, XLenVT, CLenVT>;
16451642
defm : CheriExplicitStPat<store, SD_CAP, GPR, GPCR, XLenVT, CLenVT>;
1646-
defm : CheriExplicitStPat<store, SC_CAP_128, GPCR, GPCR, CLenVT, CLenVT>;
1643+
defm : CheriExplicitStPat<store, SC_128_CAP, GPCR, GPCR, CLenVT, CLenVT>;
16471644
}
16481645

1649-
let Predicates = [HasXCheriAll, NotCapMode, HasStdExtF] in
1646+
let Predicates = [HasCheriCommon, NotCapMode, HasStdExtF] in
16501647
def : Pat<(store FPR32:$rs2, GPCR:$rs1),
1651-
(SW_CAP (FMV_X_W FPR32:$rs2), GPCR:$rs1)>;
1648+
(Pseudo_SW_CAP (FMV_X_W FPR32:$rs2), GPCR:$rs1)>;
16521649

1653-
let Predicates = [HasXCheriAll, NotCapMode, HasStdExtD, IsRV32] in
1650+
let Predicates = [HasCheriCommon, NotCapMode, HasStdExtD, IsRV32] in
16541651
def : Pat<(store FPR64:$rs2, GPCR:$rs1),
16551652
(KILL (CheriSplitStoreF64Pseudo FPR64:$rs2, GPCR:$rs1))>;
16561653

1657-
let Predicates = [HasXCheriAll, NotCapMode, HasStdExtD, IsRV64] in
1654+
let Predicates = [HasCheriCommon, NotCapMode, HasStdExtD, IsRV64] in
16581655
def : Pat<(store FPR64:$rs2, GPCR:$rs1),
1659-
(SD_CAP (FMV_X_D FPR64:$rs2), GPCR:$rs1)>;
1656+
(Pseudo_SD_CAP (FMV_X_D FPR64:$rs2), GPCR:$rs1)>;
16601657

16611658
/// Non-Capability Mode Instructions
16621659

0 commit comments

Comments
 (0)