diff --git a/lld/ELF/Arch/Cheri.cpp b/lld/ELF/Arch/Cheri.cpp
index d392d16e0b28b..45a9342fc1905 100644
--- a/lld/ELF/Arch/Cheri.cpp
+++ b/lld/ELF/Arch/Cheri.cpp
@@ -47,7 +47,7 @@ template <class ELFT> struct InMemoryCapRelocEntry {
 
 CheriCapRelocsSection::CheriCapRelocsSection(StringRef name)
     : SyntheticSection((config->isPic && !config->relativeCapRelocsOnly)
-                           ? SHF_ALLOC | SHF_WRITE /* XXX: actually RELRO */
+                           ? SHF_ALLOC | SHF_WRITE
                            : SHF_ALLOC,
                        SHT_PROGBITS, config->wordsize, name) {
   this->entsize = config->wordsize * 5;
@@ -322,7 +322,8 @@ void CheriCapRelocsSection::addCapReloc(CheriCapRelocLocation loc,
   auto sourceMsg = [&]() -> std::string {
     return sourceSymbol ? verboseToString(sourceSymbol) : loc.toString();
   };
-  if (target.sym()->isUndefined() && !target.sym()->isUndefWeak()) {
+  if (isa<Symbol *>(target.symOrSec) && target.sym()->isUndefined() &&
+      !target.sym()->isUndefWeak()) {
     std::string msg =
         "cap_reloc against undefined symbol: " + toString(*target.sym()) +
         "\n>>> referenced by " + sourceMsg();
@@ -348,6 +349,7 @@ void CheriCapRelocsSection::addCapReloc(CheriCapRelocLocation loc,
     return; // Maybe happens with vtables?
   }
   if (targetNeedsDynReloc) {
+    assert(isa<Symbol *>(target.symOrSec));
     bool relativeToLoadAddress = false;
     // The addend is not used as the offset into the capability here, as we
     // have the offset field in the __cap_relocs for that. The Addend
@@ -384,6 +386,9 @@ void CheriCapRelocsSection::addCapReloc(CheriCapRelocLocation loc,
 template <typename ELFT>
 static uint64_t getTargetSize(const CheriCapRelocLocation &location,
                               const SymbolAndOffset &target) {
+  if (InputSectionBase *isec = dyn_cast<InputSectionBase *>(target.symOrSec))
+    return isec->getSize();
+
   uint64_t targetSize = target.sym()->getSize();
   if (targetSize > INT_MAX) {
     error("Insanely large symbol size for " + target.verboseToString() +
@@ -510,9 +515,24 @@ void CheriCapRelocsSection::writeToImpl(uint8_t *buf) {
         location.section->getOutputSection()->addr + outSecOffset;
 
     // The target VA is the base address of the capability, so symbol + 0
-    uint64_t targetVA = realTarget.sym()->getVA(0);
-    bool preemptibleDynReloc =
-        reloc.needsDynReloc && realTarget.sym()->isPreemptible;
+    uint64_t targetVA;
+    bool isPreemptible, isFunc, isTls;
+    OutputSection *os;
+    if (Symbol *s = dyn_cast<Symbol *>(realTarget.symOrSec)) {
+      targetVA = realTarget.sym()->getVA(0);
+      isPreemptible = reloc.needsDynReloc && realTarget.sym()->isPreemptible;
+      isFunc = s->isFunc();
+      isTls = s->isTls();
+      os = s->getOutputSection();
+    } else {
+      InputSectionBase *isec = cast<InputSectionBase *>(realTarget.symOrSec);
+      targetVA = isec->getVA(0);
+      isPreemptible = false;
+      isFunc = (isec->flags & SHF_EXECINSTR) != 0;
+      isTls = isec->type == STT_TLS;
+      os = isec->getOutputSection();
+    }
+    bool preemptibleDynReloc = reloc.needsDynReloc && isPreemptible;
     uint64_t targetSize = 0;
     if (preemptibleDynReloc) {
       // If we have a relocation against a preemptible symbol (even in the
@@ -529,10 +549,10 @@ void CheriCapRelocsSection::writeToImpl(uint8_t *buf) {
     uint64_t targetOffset = reloc.capabilityOffset + realTarget.offset;
     uint64_t permissions = 0;
     // Fow now Function implies ReadOnly so don't add the flag
-    if (realTarget.sym()->isFunc()) {
+    if (isFunc) {
       permissions |= CaptablePermissions<ELFT>::function;
-    } else if (auto os = realTarget.sym()->getOutputSection()) {
-      assert(!realTarget.sym()->isTls());
+    } else if (os) {
+      assert(!isTls);
       // if ((OS->getPhdrFlags() & PF_W) == 0) {
       if (((os->flags & SHF_WRITE) == 0) || isRelroSection(os)) {
         permissions |= CaptablePermissions<ELFT>::readOnly;
@@ -583,15 +603,14 @@ void CheriCapRelocsSection::writeTo(uint8_t *buf) {
   invokeELFT(writeToImpl, buf);
 }
 
-
-CheriCapTableSection::CheriCapTableSection()
-  : SyntheticSection(SHF_ALLOC | SHF_WRITE, /* XXX: actually RELRO for BIND_NOW*/
-                     SHT_PROGBITS, config->capabilitySize, ".captable") {
+MipsCheriCapTableSection::MipsCheriCapTableSection()
+    : SyntheticSection(SHF_ALLOC | SHF_WRITE, SHT_PROGBITS,
+                       config->capabilitySize, ".captable") {
   assert(config->capabilitySize > 0);
   this->entsize = config->capabilitySize;
 }
 
-void CheriCapTableSection::writeTo(uint8_t* buf) {
+void MipsCheriCapTableSection::writeTo(uint8_t *buf) {
   // Capability part should be filled with all zeros and crt_init_globals fills
   // it in. For the TLS part, assignValuesAndAddCapTableSymbols adds any static
   // relocations needed, and should be procesed by relocateAlloc.
@@ -604,8 +623,8 @@ static Defined *findMatchingFunction(const InputSectionBase *isec,
   return isec->getEnclosingFunction(symOffset);
 }
 
-CheriCapTableSection::CaptableMap &
-CheriCapTableSection::getCaptableMapForFileAndOffset(
+MipsCheriCapTableSection::CaptableMap &
+MipsCheriCapTableSection::getCaptableMapForFileAndOffset(
     const InputSectionBase *isec, uint64_t offset) {
   if (LLVM_LIKELY(config->capTableScope == CapTableScopePolicy::All))
     return globalEntries;
@@ -627,8 +646,9 @@ CheriCapTableSection::getCaptableMapForFileAndOffset(
   return globalEntries;
 }
 
-void CheriCapTableSection::addEntry(Symbol &sym, RelExpr expr,
-                                    InputSectionBase *isec, uint64_t offset) {
+void MipsCheriCapTableSection::addEntry(Symbol &sym, RelExpr expr,
+                                        InputSectionBase *isec,
+                                        uint64_t offset) {
   // FIXME: can this be called from multiple threads?
   CapTableIndex idx;
   idx.needsSmallImm = false;
@@ -636,8 +656,8 @@ void CheriCapTableSection::addEntry(Symbol &sym, RelExpr expr,
   idx.firstUse = SymbolAndOffset(isec, offset);
   assert(!idx.firstUse->symOrSec.isNull());
   switch (expr) {
-  case R_CHERI_CAPABILITY_TABLE_INDEX_SMALL_IMMEDIATE:
-  case R_CHERI_CAPABILITY_TABLE_INDEX_CALL_SMALL_IMMEDIATE:
+  case R_MIPS_CHERI_CAPTAB_INDEX_SMALL_IMMEDIATE:
+  case R_MIPS_CHERI_CAPTAB_INDEX_CALL_SMALL_IMMEDIATE:
     idx.needsSmallImm = true;
     break;
   default:
@@ -649,8 +669,8 @@ void CheriCapTableSection::addEntry(Symbol &sym, RelExpr expr,
   // not used as a function pointer and therefore does not need a unique
   // address (plt stub) across all DSOs.
   switch (expr) {
-  case R_CHERI_CAPABILITY_TABLE_INDEX_CALL:
-  case R_CHERI_CAPABILITY_TABLE_INDEX_CALL_SMALL_IMMEDIATE:
+  case R_MIPS_CHERI_CAPTAB_INDEX_CALL:
+  case R_MIPS_CHERI_CAPTAB_INDEX_CALL_SMALL_IMMEDIATE:
     if (!sym.isFunc() && !sym.isUndefWeak()) {
       CheriCapRelocLocation loc{isec, offset};
       std::string msg = "call relocation against non-function symbol " + verboseToString(&sym, 0) +
@@ -690,25 +710,25 @@ void CheriCapTableSection::addEntry(Symbol &sym, RelExpr expr,
   }
 }
 
-void CheriCapTableSection::addDynTlsEntry(Symbol &sym) {
+void MipsCheriCapTableSection::addDynTlsEntry(Symbol &sym) {
   dynTlsEntries.map.insert(std::make_pair(&sym, CapTableIndex()));
 }
 
-void CheriCapTableSection::addTlsIndex() {
+void MipsCheriCapTableSection::addTlsIndex() {
   dynTlsEntries.map.insert(std::make_pair(nullptr, CapTableIndex()));
 }
 
-void CheriCapTableSection::addTlsEntry(Symbol &sym) {
+void MipsCheriCapTableSection::addTlsEntry(Symbol &sym) {
   tlsEntries.map.insert(std::make_pair(&sym, CapTableIndex()));
 }
 
-uint32_t CheriCapTableSection::getIndex(const Symbol &sym,
-                                        const InputSectionBase *isec,
-                                        uint64_t offset) const {
+uint32_t MipsCheriCapTableSection::getIndex(const Symbol &sym,
+                                            const InputSectionBase *isec,
+                                            uint64_t offset) const {
   assert(valuesAssigned && "getIndex called before index assignment");
   const CaptableMap &entries =
-      const_cast<CheriCapTableSection *>(this)->getCaptableMapForFileAndOffset(
-          isec, offset);
+      const_cast<MipsCheriCapTableSection *>(this)
+          ->getCaptableMapForFileAndOffset(isec, offset);
   auto it = entries.map.find(const_cast<Symbol *>(&sym));
   assert(entries.firstIndex != std::numeric_limits<uint64_t>::max() &&
          "First index not set yet?");
@@ -720,21 +740,21 @@ uint32_t CheriCapTableSection::getIndex(const Symbol &sym,
   return *it->second.index - entries.firstIndex;
 }
 
-uint32_t CheriCapTableSection::getDynTlsOffset(const Symbol &sym) const {
+uint32_t MipsCheriCapTableSection::getDynTlsOffset(const Symbol &sym) const {
   assert(valuesAssigned && "getDynTlsOffset called before index assignment");
   auto it = dynTlsEntries.map.find(const_cast<Symbol *>(&sym));
   assert(it != dynTlsEntries.map.end());
   return *it->second.index * config->wordsize;
 }
 
-uint32_t CheriCapTableSection::getTlsIndexOffset() const {
+uint32_t MipsCheriCapTableSection::getTlsIndexOffset() const {
   assert(valuesAssigned && "getTlsIndexOffset called before index assignment");
   auto it = dynTlsEntries.map.find(nullptr);
   assert(it != dynTlsEntries.map.end());
   return *it->second.index * config->wordsize;
 }
 
-uint32_t CheriCapTableSection::getTlsOffset(const Symbol &sym) const {
+uint32_t MipsCheriCapTableSection::getTlsOffset(const Symbol &sym) const {
   assert(valuesAssigned && "getTlsOffset called before index assignment");
   auto it = tlsEntries.map.find(const_cast<Symbol *>(&sym));
   assert(it != tlsEntries.map.end());
@@ -742,9 +762,9 @@ uint32_t CheriCapTableSection::getTlsOffset(const Symbol &sym) const {
 }
 
 template <class ELFT>
-uint64_t CheriCapTableSection::assignIndices(uint64_t startIndex,
-                                             CaptableMap &entries,
-                                             const Twine &symContext) {
+uint64_t MipsCheriCapTableSection::assignIndices(uint64_t startIndex,
+                                                 CaptableMap &entries,
+                                                 const Twine &symContext) {
   // Usually StartIndex will be zero (one global captable) but if we are
   // compiling with per-file/per-function
   uint64_t smallEntryCount = 0;
@@ -847,7 +867,7 @@ uint64_t CheriCapTableSection::assignIndices(uint64_t startIndex,
     RelocationBaseSection *dynRelSec =
         it.second.usedInCallExpr ? in.relaPlt.get() : mainPart->relaDyn.get();
     addCapabilityRelocation<ELFT>(
-        targetSym, elfCapabilityReloc, in.cheriCapTable.get(), off,
+        targetSym, elfCapabilityReloc, in.mipsCheriCapTable.get(), off,
         R_CHERI_CAPABILITY, 0, it.second.usedInCallExpr,
         [&]() {
           return ("\n>>> referenced by " + refName + "\n>>> first used in " +
@@ -861,7 +881,7 @@ uint64_t CheriCapTableSection::assignIndices(uint64_t startIndex,
 }
 
 template <class ELFT>
-void CheriCapTableSection::assignValuesAndAddCapTableSymbols() {
+void MipsCheriCapTableSection::assignValuesAndAddCapTableSymbols() {
   // First assign the global indices (which will usually be the only ones)
   uint64_t assignedEntries = assignIndices<ELFT>(0, globalEntries, "");
   if (LLVM_UNLIKELY(config->capTableScope != CapTableScopePolicy::All)) {
@@ -949,22 +969,22 @@ void CheriCapTableSection::assignValuesAndAddCapTableSymbols() {
 }
 
 template void
-CheriCapTableSection::assignValuesAndAddCapTableSymbols<ELF32LE>();
+MipsCheriCapTableSection::assignValuesAndAddCapTableSymbols<ELF32LE>();
 template void
-CheriCapTableSection::assignValuesAndAddCapTableSymbols<ELF32BE>();
+MipsCheriCapTableSection::assignValuesAndAddCapTableSymbols<ELF32BE>();
 template void
-CheriCapTableSection::assignValuesAndAddCapTableSymbols<ELF64LE>();
+MipsCheriCapTableSection::assignValuesAndAddCapTableSymbols<ELF64LE>();
 template void
-CheriCapTableSection::assignValuesAndAddCapTableSymbols<ELF64BE>();
+MipsCheriCapTableSection::assignValuesAndAddCapTableSymbols<ELF64BE>();
 
-CheriCapTableMappingSection::CheriCapTableMappingSection()
+MipsCheriCapTableMappingSection::MipsCheriCapTableMappingSection()
     : SyntheticSection(SHF_ALLOC, SHT_PROGBITS, 8, ".captable_mapping") {
   assert(config->capabilitySize > 0);
   this->entsize = sizeof(CaptableMappingEntry);
   static_assert(sizeof(CaptableMappingEntry) == 24, "");
 }
 
-size_t CheriCapTableMappingSection::getSize() const {
+size_t MipsCheriCapTableMappingSection::getSize() const {
   assert(config->capTableScope != CapTableScopePolicy::All);
   if (!isNeeded())
     return 0;
@@ -981,9 +1001,9 @@ size_t CheriCapTableMappingSection::getSize() const {
   return count * sizeof(CaptableMappingEntry);
 }
 
-void CheriCapTableMappingSection::writeTo(uint8_t *buf) {
+void MipsCheriCapTableMappingSection::writeTo(uint8_t *buf) {
   assert(config->capTableScope != CapTableScopePolicy::All);
-  if (!in.cheriCapTable)
+  if (!in.mipsCheriCapTable)
     return;
   if (!in.symTab) {
     error("Cannot write " + this->name + " without .symtab section!");
@@ -998,14 +1018,14 @@ void CheriCapTableMappingSection::writeTo(uint8_t *buf) {
     Symbol* sym = ste.sym;
     if (!sym->isDefined() || !sym->isFunc())
       continue;
-    const CheriCapTableSection::CaptableMap *capTableMap = nullptr;
+    const MipsCheriCapTableSection::CaptableMap *capTableMap = nullptr;
     if (config->capTableScope == CapTableScopePolicy::Function) {
-      auto it = in.cheriCapTable->perFunctionEntries.find(sym);
-      if (it != in.cheriCapTable->perFunctionEntries.end())
+      auto it = in.mipsCheriCapTable->perFunctionEntries.find(sym);
+      if (it != in.mipsCheriCapTable->perFunctionEntries.end())
         capTableMap = &it->second;
     } else if (config->capTableScope == CapTableScopePolicy::File) {
-      auto it = in.cheriCapTable->perFileEntries.find(sym->file);
-      if (it != in.cheriCapTable->perFileEntries.end())
+      auto it = in.mipsCheriCapTable->perFileEntries.find(sym->file);
+      if (it != in.mipsCheriCapTable->perFileEntries.end())
         capTableMap = &it->second;
     } else {
       llvm_unreachable("Invalid mode!");
@@ -1047,13 +1067,14 @@ void CheriCapTableMappingSection::writeTo(uint8_t *buf) {
 }
 
 template <typename ELFT>
-void addCapabilityRelocation(Symbol *sym, RelType type, InputSectionBase *sec,
-                             uint64_t offset, RelExpr expr, int64_t addend,
-                             bool isCallExpr,
-                             llvm::function_ref<std::string()> referencedBy,
-                             RelocationBaseSection *dynRelSec) {
+void addCapabilityRelocation(
+    llvm::PointerUnion<Symbol *, InputSectionBase *> symOrSec, RelType type,
+    InputSectionBase *sec, uint64_t offset, RelExpr expr, int64_t addend,
+    bool isCallExpr, llvm::function_ref<std::string()> referencedBy,
+    RelocationBaseSection *dynRelSec) {
+  Symbol *sym = dyn_cast<Symbol *>(symOrSec);
   assert(expr == R_CHERI_CAPABILITY);
-  if (sec->name == ".gcc_except_table" && sym->isPreemptible) {
+  if (sec->name == ".gcc_except_table" && sym && sym->isPreemptible) {
     // We previously had an ugly workaround here to create a hidden alias for
     // relocations in the exception table, but this has since been fixed in
     // the compiler. Add an explicit error here in case someone tries to
@@ -1067,14 +1088,15 @@ void addCapabilityRelocation(Symbol *sym, RelType type, InputSectionBase *sec,
   // Emit either the legacy __cap_relocs section or a R_CHERI_CAPABILITY reloc
   // For local symbols we can also emit the untagged capability bits and
   // instruct csu/rtld to run CBuildCap
-  CapRelocsMode capRelocMode = sym->isPreemptible
+  CapRelocsMode capRelocMode = sym && sym->isPreemptible
                                    ? config->preemptibleCapRelocsMode
                                    : config->localCapRelocsMode;
   bool needTrampoline = false;
   // In the PLT ABI (and fndesc?) we have to use an elf relocation for function
   // pointers to ensure that the runtime linker adds the required trampolines
   // that sets $cgp:
-  if (!isCallExpr && config->emachine == llvm::ELF::EM_MIPS && sym->isFunc()) {
+  if (!isCallExpr && config->emachine == llvm::ELF::EM_MIPS && sym &&
+      sym->isFunc()) {
     if (!lld::elf::hasDynamicLinker()) {
       // In static binaries we do not need PLT stubs for function pointers since
       // all functions share the same $cgp
@@ -1083,7 +1105,6 @@ void addCapabilityRelocation(Symbol *sym, RelType type, InputSectionBase *sec,
       if (config->verboseCapRelocs)
         message("Do not need function pointer trampoline for " +
                 toString(*sym) + " in static binary");
-      needTrampoline = false;
     } else if (in.mipsAbiFlags) {
       auto abi = static_cast<MipsAbiFlagsSection<ELFT> &>(*in.mipsAbiFlags)
                      .getCheriAbiVariant();
@@ -1091,18 +1112,19 @@ void addCapabilityRelocation(Symbol *sym, RelType type, InputSectionBase *sec,
                   *abi == llvm::ELF::DF_MIPS_CHERI_ABI_FNDESC))
         needTrampoline = true;
     }
-  }
 
-  if (needTrampoline) {
-    capRelocMode = CapRelocsMode::ElfReloc;
-    assert(capRelocMode == config->preemptibleCapRelocsMode);
-    if (config->verboseCapRelocs)
-      message("Using trampoline for function pointer against " +
-              verboseToString(sym));
+    if (needTrampoline) {
+      capRelocMode = CapRelocsMode::ElfReloc;
+      assert(capRelocMode == config->preemptibleCapRelocsMode);
+      if (config->verboseCapRelocs)
+        message("Using trampoline for function pointer against " +
+                verboseToString(sym));
+    }
   }
 
   // local cap relocs don't need a Elf relocation with a full symbol lookup:
   if (capRelocMode == CapRelocsMode::ElfReloc) {
+    assert(sym && "ELF relocs should not be used against sections");
     assert((sym->isPreemptible || needTrampoline) &&
            "ELF relocs should not be used for non-preemptible symbols");
     assert((!sym->isLocal() || needTrampoline) &&
@@ -1157,10 +1179,10 @@ void addCapabilityRelocation(Symbol *sym, RelType type, InputSectionBase *sec,
 
   } else if (capRelocMode == CapRelocsMode::Legacy) {
     if (config->relativeCapRelocsOnly) {
-      assert(!sym->isPreemptible);
+      assert(!sym || !sym->isPreemptible);
     }
-    in.capRelocs->addCapReloc<ELFT>({sec, offset}, {sym, 0u},
-                                    sym->isPreemptible, addend);
+    in.capRelocs->addCapReloc<ELFT>({sec, offset}, {symOrSec, 0u},
+                                    sym && sym->isPreemptible, addend);
   } else {
     assert(config->localCapRelocsMode == CapRelocsMode::CBuildCap);
     error("CBuildCap method not implemented yet!");
@@ -1171,14 +1193,18 @@ void addCapabilityRelocation(Symbol *sym, RelType type, InputSectionBase *sec,
 } // namespace lld
 
 template void lld::elf::addCapabilityRelocation<ELF32LE>(
-    Symbol *, RelType, InputSectionBase *, uint64_t, RelExpr, int64_t, bool,
+    llvm::PointerUnion<Symbol *, InputSectionBase *>, RelType,
+    InputSectionBase *, uint64_t, RelExpr, int64_t, bool,
     llvm::function_ref<std::string()>, RelocationBaseSection *);
 template void lld::elf::addCapabilityRelocation<ELF32BE>(
-    Symbol *, RelType, InputSectionBase *, uint64_t, RelExpr, int64_t, bool,
+    llvm::PointerUnion<Symbol *, InputSectionBase *>, RelType,
+    InputSectionBase *, uint64_t, RelExpr, int64_t, bool,
     llvm::function_ref<std::string()>, RelocationBaseSection *);
 template void lld::elf::addCapabilityRelocation<ELF64LE>(
-    Symbol *, RelType, InputSectionBase *, uint64_t, RelExpr, int64_t, bool,
+    llvm::PointerUnion<Symbol *, InputSectionBase *>, RelType,
+    InputSectionBase *, uint64_t, RelExpr, int64_t, bool,
     llvm::function_ref<std::string()>, RelocationBaseSection *);
 template void lld::elf::addCapabilityRelocation<ELF64BE>(
-    Symbol *, RelType, InputSectionBase *, uint64_t, RelExpr, int64_t, bool,
+    llvm::PointerUnion<Symbol *, InputSectionBase *>, RelType,
+    InputSectionBase *, uint64_t, RelExpr, int64_t, bool,
     llvm::function_ref<std::string()>, RelocationBaseSection *);
diff --git a/lld/ELF/Arch/Cheri.h b/lld/ELF/Arch/Cheri.h
index fbd432071af28..b4322b83d99f6 100644
--- a/lld/ELF/Arch/Cheri.h
+++ b/lld/ELF/Arch/Cheri.h
@@ -15,12 +15,10 @@ namespace elf {
 
 struct SymbolAndOffset {
 public:
-  SymbolAndOffset(Symbol *s, int64_t o) : symOrSec(s), offset(o) {
+  SymbolAndOffset(llvm::PointerUnion<Symbol *, InputSectionBase *> s, int64_t o)
+      : symOrSec(s), offset(o) {
     assert(s && "Should not be null");
   }
-  SymbolAndOffset(InputSectionBase *isec, int64_t o) : symOrSec(isec), offset(o) {
-    assert(isec && "Should not be null");
-  }
   SymbolAndOffset(const SymbolAndOffset &) = default;
   SymbolAndOffset &operator=(const SymbolAndOffset &) = default;
 
@@ -186,9 +184,9 @@ class CheriCapRelocsSection : public SyntheticSection {
 // +---------------------------------------+
 // TODO: TLS caps also need to be per file/function
 
-class CheriCapTableSection : public SyntheticSection {
+class MipsCheriCapTableSection : public SyntheticSection {
 public:
-  CheriCapTableSection();
+  MipsCheriCapTableSection();
   // InputFile and Offset is needed in order to implement per-file/per-function
   // tables
   void addEntry(Symbol &sym, RelExpr expr, InputSectionBase *isec,
@@ -266,7 +264,7 @@ class CheriCapTableSection : public SyntheticSection {
   CaptableMap dynTlsEntries;
   CaptableMap tlsEntries;
   bool valuesAssigned = false;
-  friend class CheriCapTableMappingSection;
+  friend class MipsCheriCapTableMappingSection;
 };
 
 // TODO: could shrink these to reduce size overhead but this is experimental
@@ -280,13 +278,13 @@ struct CaptableMappingEntry {
 
 // Map from symbol vaddr -> captable subset so that RTLD can setup the correct
 // trampolines to initialize $cgp to the correct subset
-class CheriCapTableMappingSection : public SyntheticSection {
+class MipsCheriCapTableMappingSection : public SyntheticSection {
 public:
-  CheriCapTableMappingSection();
+  MipsCheriCapTableMappingSection();
   bool isNeeded() const override {
     if (config->capTableScope == CapTableScopePolicy::All)
       return false;
-    return in.cheriCapTable && in.cheriCapTable->isNeeded();
+    return in.mipsCheriCapTable && in.mipsCheriCapTable->isNeeded();
   }
   void writeTo(uint8_t *buf) override;
   size_t getSize() const override;
@@ -320,11 +318,11 @@ inline void readOnlyCapRelocsError(Symbol &sym, const Twine &sourceMsg) {
 }
 
 template <typename ELFT>
-void addCapabilityRelocation(Symbol *sym, RelType type, InputSectionBase *sec,
-                             uint64_t offset, RelExpr expr, int64_t addend,
-                             bool isCallExpr,
-                             llvm::function_ref<std::string()> referencedBy,
-                             RelocationBaseSection *dynRelSec = nullptr);
+void addCapabilityRelocation(
+    llvm::PointerUnion<Symbol *, InputSectionBase *> target, RelType type,
+    InputSectionBase *sec, uint64_t offset, RelExpr expr, int64_t addend,
+    bool isCallExpr, llvm::function_ref<std::string()> referencedBy,
+    RelocationBaseSection *dynRelSec = nullptr);
 } // namespace elf
 } // namespace lld
 
diff --git a/lld/ELF/Arch/Mips.cpp b/lld/ELF/Arch/Mips.cpp
index d131b84f1cecd..0334059ef2eda 100644
--- a/lld/ELF/Arch/Mips.cpp
+++ b/lld/ELF/Arch/Mips.cpp
@@ -123,7 +123,7 @@ RelExpr MIPS<ELFT>::getRelExpr(RelType type, const Symbol &s,
   case R_MICROMIPS_GPREL7_S2:
     return R_MIPS_GOTREL;
   case R_MIPS_CHERI_CAPTABLEREL16:
-    return R_CHERI_CAPABILITY_TABLE_REL;
+    return R_MIPS_CHERI_CAPTAB_REL;
   case R_MIPS_26:
   case R_MICROMIPS_26_S1:
     return R_PLT;
@@ -212,16 +212,16 @@ RelExpr MIPS<ELFT>::getRelExpr(RelType type, const Symbol &s,
     return R_CHERI_CAPABILITY;
   case R_MIPS_CHERI_CAPTAB_LO16:
   case R_MIPS_CHERI_CAPTAB_HI16:
-    return R_CHERI_CAPABILITY_TABLE_INDEX;
+    return R_MIPS_CHERI_CAPTAB_INDEX;
   case R_MIPS_CHERI_CAPCALL_LO16:
   case R_MIPS_CHERI_CAPCALL_HI16:
-    return R_CHERI_CAPABILITY_TABLE_INDEX_CALL;
+    return R_MIPS_CHERI_CAPTAB_INDEX_CALL;
   case R_MIPS_CHERI_CAPTAB_CLC11:
   case R_MIPS_CHERI_CAPTAB20:
-    return R_CHERI_CAPABILITY_TABLE_INDEX_SMALL_IMMEDIATE;
+    return R_MIPS_CHERI_CAPTAB_INDEX_SMALL_IMMEDIATE;
   case R_MIPS_CHERI_CAPCALL_CLC11:
   case R_MIPS_CHERI_CAPCALL20:
-    return R_CHERI_CAPABILITY_TABLE_INDEX_CALL_SMALL_IMMEDIATE;
+    return R_MIPS_CHERI_CAPTAB_INDEX_CALL_SMALL_IMMEDIATE;
   case R_MIPS_CHERI_CAPTAB_TLS_GD_LO16:
   case R_MIPS_CHERI_CAPTAB_TLS_GD_HI16:
     return R_MIPS_CHERI_CAPTAB_TLSGD;
diff --git a/lld/ELF/Arch/RISCV.cpp b/lld/ELF/Arch/RISCV.cpp
index 3776b6be07a7a..9ad3ee983b39e 100644
--- a/lld/ELF/Arch/RISCV.cpp
+++ b/lld/ELF/Arch/RISCV.cpp
@@ -68,7 +68,6 @@ enum Op {
   CIncOffsetImm = 0x105b,
   CLC_64 = 0x3003,
   CLC_128 = 0x200f,
-  CSub = 0x2800005b,
 };
 
 enum Reg {
@@ -112,10 +111,7 @@ RISCV::RISCV() {
   pltRel = R_RISCV_JUMP_SLOT;
   relativeRel = R_RISCV_RELATIVE;
   iRelativeRel = R_RISCV_IRELATIVE;
-  sizeRel = R_RISCV_CHERI_SIZE;
   cheriCapRel = R_RISCV_CHERI_CAPABILITY;
-  // TODO: R_RISCV_CHERI_JUMP_SLOT in a separate .got.plt / .captable.plt
-  cheriCapCallRel = R_RISCV_CHERI_CAPABILITY;
   if (config->is64) {
     symbolicRel = R_RISCV_64;
     tlsModuleIndexRel = R_RISCV_TLS_DTPMOD64;
@@ -127,7 +123,10 @@ RISCV::RISCV() {
     tlsOffsetRel = R_RISCV_TLS_DTPREL32;
     tlsGotRel = R_RISCV_TLS_TPREL32;
   }
-  gotRel = symbolicRel;
+  if (config->isCheriAbi)
+    gotRel = *cheriCapRel;
+  else
+    gotRel = symbolicRel;
   absPointerRel = symbolicRel;
 
   // .got[0] = _DYNAMIC
@@ -222,6 +221,10 @@ void RISCV::writeGotHeader(uint8_t *buf) const {
 }
 
 void RISCV::writeGotPlt(uint8_t *buf, const Symbol &s) const {
+  // Initialised by __cap_relocs for CHERI
+  if (config->isCheriAbi)
+    return;
+
   if (config->is64)
     write64le(buf, in.plt->getVA());
   else
@@ -238,14 +241,7 @@ void RISCV::writeIgotPlt(uint8_t *buf, const Symbol &s) const {
 }
 
 void RISCV::writePltHeader(uint8_t *buf) const {
-  // TODO: Remove once we have a CHERI .got.plt and R_RISCV_CHERI_JUMP_SLOT.
-  // Without those there can be no lazy binding support (though the former
-  // requirement can be relaxed provided .captable[0] is _dl_runtime_resolve,
-  // at least when the PLT is non-empty), so for now we emit a header full of
-  // trapping instructions to ensure we don't accidentally end up trying to use
-  // it. Ideally we would have a header size of 0, but isCheriAbi isn't known
-  // in the constructor.
-  if (config->isCheriAbi) {
+  if (config->isCheriAbi && !config->zCheriRiscvJumpSlot) {
     memset(buf, 0, pltHeaderSize);
     return;
   }
@@ -259,7 +255,6 @@ void RISCV::writePltHeader(uint8_t *buf) const {
   // (c)jr (c)t3
   // (if shift == 0): nop
   uint32_t offset = in.gotPlt->getVA() - in.plt->getVA();
-  uint32_t ptrsub = config->isCheriAbi ? CSub : SUB;
   uint32_t ptrload = config->isCheriAbi ? config->is64 ? CLC_128 : CLC_64
                                         : config->is64 ? LD : LW;
   uint32_t ptraddi = config->isCheriAbi ? CIncOffsetImm : ADDI;
@@ -268,7 +263,7 @@ void RISCV::writePltHeader(uint8_t *buf) const {
   uint32_t ptrsize = config->isCheriAbi ? config->capabilitySize
                                         : config->wordsize;
   write32le(buf + 0, utype(AUIPC, X_T2, hi20(offset)));
-  write32le(buf + 4, rtype(ptrsub, X_T1, X_T1, X_T3));
+  write32le(buf + 4, rtype(SUB, X_T1, X_T1, X_T3));
   write32le(buf + 8, itype(ptrload, X_T3, X_T2, lo12(offset)));
   write32le(buf + 12, itype(ADDI, X_T1, X_T1, -target->pltHeaderSize - 12));
   write32le(buf + 16, itype(ptraddi, X_T0, X_T2, lo12(offset)));
@@ -288,8 +283,9 @@ void RISCV::writePlt(uint8_t *buf, const Symbol &sym,
   // nop
   uint32_t ptrload = config->isCheriAbi ? config->is64 ? CLC_128 : CLC_64
                                         : config->is64 ? LD : LW;
-  uint32_t entryva = config->isCheriAbi ? sym.getCapTableVA(in.plt.get(), 0)
-                                        : sym.getGotPltVA();
+  uint32_t entryva = config->isCheriAbi && !config->zCheriRiscvJumpSlot
+                         ? sym.getGotVA()
+                         : sym.getGotPltVA();
   uint32_t offset = entryva - pltEntryAddr;
   write32le(buf + 0, utype(AUIPC, X_T3, hi20(offset)));
   write32le(buf + 4, itype(ptrload, X_T3, X_T3, lo12(offset)));
@@ -363,12 +359,13 @@ RelExpr RISCV::getRelExpr(const RelType type, const Symbol &s,
     return config->relax ? R_RELAX_HINT : R_NONE;
   case R_RISCV_CHERI_CAPABILITY:
     return R_CHERI_CAPABILITY;
+  // TODO: Deprecate and eventually remove these
   case R_RISCV_CHERI_CAPTAB_PCREL_HI20:
-    return R_CHERI_CAPABILITY_TABLE_ENTRY_PC;
+    return R_GOT_PC;
   case R_RISCV_CHERI_TLS_IE_CAPTAB_PCREL_HI20:
-    return R_CHERI_CAPABILITY_TABLE_TLSIE_ENTRY_PC;
+    return R_GOT_PC;
   case R_RISCV_CHERI_TLS_GD_CAPTAB_PCREL_HI20:
-    return R_CHERI_CAPABILITY_TABLE_TLSGD_ENTRY_PC;
+    return R_TLSGD_PC;
   default:
     error(getErrorLocation(loc) + "unknown relocation (" + Twine(type) +
           ") against symbol " + toString(s));
diff --git a/lld/ELF/Config.h b/lld/ELF/Config.h
index 4a7651fd29cd0..132594203d3ed 100644
--- a/lld/ELF/Config.h
+++ b/lld/ELF/Config.h
@@ -308,6 +308,7 @@ struct Config {
   // -z captabledebug: add additional symbols $captable_load_<symbols> before
   // each captable clc instruction that indicates which symbol should be loaded
   bool zCapTableDebug;
+  bool zCheriRiscvJumpSlot;
   bool zCombreloc;
   bool zCopyreloc;
   bool zForceBti;
diff --git a/lld/ELF/Driver.cpp b/lld/ELF/Driver.cpp
index 13f2f395edabf..4347749c50e21 100644
--- a/lld/ELF/Driver.cpp
+++ b/lld/ELF/Driver.cpp
@@ -535,6 +535,7 @@ static uint8_t getZStartStopVisibility(opt::InputArgList &args) {
 
 constexpr const char *knownZFlags[] = {
     "captabledebug",
+    "cheri-riscv-jump-slot",
     "combreloc",
     "copyreloc",
     "defs",
@@ -1433,6 +1434,7 @@ static void readConfigs(opt::InputArgList &args) {
       args.hasFlag(OPT_warn_symbol_ordering, OPT_no_warn_symbol_ordering, true);
   config->whyExtract = args.getLastArgValue(OPT_why_extract);
   config->zCapTableDebug = getZFlag(args, "captabledebug", "nocaptabledebug", false);
+  config->zCheriRiscvJumpSlot = hasZOption(args, "cheri-riscv-jump-slot");
   config->zCombreloc = getZFlag(args, "combreloc", "nocombreloc", true);
   config->zCopyreloc = getZFlag(args, "copyreloc", "nocopyreloc", true);
   config->zForceBti = hasZOption(args, "force-bti");
diff --git a/lld/ELF/InputSection.cpp b/lld/ELF/InputSection.cpp
index 0d045286212ea..d649e1c900d7f 100644
--- a/lld/ELF/InputSection.cpp
+++ b/lld/ELF/InputSection.cpp
@@ -863,44 +863,28 @@ uint64_t InputSectionBase::getRelocTargetVA(const InputFile *file, RelType type,
     return in.got->getTlsIndexVA() + a - p;
   case R_CHERI_CAPABILITY:
     llvm_unreachable("R_CHERI_CAPABILITY should not be handled here!");
-  case R_CHERI_CAPABILITY_TABLE_INDEX:
-  case R_CHERI_CAPABILITY_TABLE_INDEX_SMALL_IMMEDIATE:
-  case R_CHERI_CAPABILITY_TABLE_INDEX_CALL:
-  case R_CHERI_CAPABILITY_TABLE_INDEX_CALL_SMALL_IMMEDIATE:
+  case R_MIPS_CHERI_CAPTAB_INDEX:
+  case R_MIPS_CHERI_CAPTAB_INDEX_SMALL_IMMEDIATE:
+  case R_MIPS_CHERI_CAPTAB_INDEX_CALL:
+  case R_MIPS_CHERI_CAPTAB_INDEX_CALL_SMALL_IMMEDIATE:
     assert(a == 0 && "capability table index relocs should not have addends");
-    return sym.getCapTableOffset(isec, offset);
-  case R_CHERI_CAPABILITY_TABLE_ENTRY_PC: {
-    assert(a == 0 && "capability table entry relocs should not have addends");
-    return sym.getCapTableVA(isec, offset) - p;
-  }
-  case R_CHERI_CAPABILITY_TABLE_TLSGD_ENTRY_PC: {
-    assert(a == 0 && "capability table index relocs should not have addends");
-    uint64_t capTableOffset =
-        in.cheriCapTable->getDynTlsOffset(sym);
-    return ElfSym::cheriCapabilityTable->getVA() + capTableOffset - p;
-  }
-  case R_CHERI_CAPABILITY_TABLE_TLSIE_ENTRY_PC: {
-    assert(a == 0 && "capability table index relocs should not have addends");
-    uint64_t capTableOffset =
-        in.cheriCapTable->getTlsOffset(sym);
-    return ElfSym::cheriCapabilityTable->getVA() + capTableOffset - p;
-  }
-  case R_CHERI_CAPABILITY_TABLE_REL:
-    if (!ElfSym::cheriCapabilityTable) {
+    return sym.getMipsCheriCapTableOffset(isec, offset);
+  case R_MIPS_CHERI_CAPTAB_REL:
+    if (!ElfSym::mipsCheriCapabilityTable) {
       error("cannot compute difference between non-existent "
             "CheriCapabilityTable and symbol " + toString(sym));
       return sym.getVA(a);
     }
-    return sym.getVA(a) - ElfSym::cheriCapabilityTable->getVA();
+    return sym.getVA(a) - ElfSym::mipsCheriCapabilityTable->getVA();
   case R_MIPS_CHERI_CAPTAB_TLSGD:
     assert(a == 0 && "capability table index relocs should not have addends");
-    return in.cheriCapTable->getDynTlsOffset(sym);
+    return in.mipsCheriCapTable->getDynTlsOffset(sym);
   case R_MIPS_CHERI_CAPTAB_TLSLD:
     assert(a == 0 && "capability table index relocs should not have addends");
-    return in.cheriCapTable->getTlsIndexOffset();
+    return in.mipsCheriCapTable->getTlsIndexOffset();
   case R_MIPS_CHERI_CAPTAB_TPREL:
     assert(a == 0 && "capability table index relocs should not have addends");
-    return in.cheriCapTable->getTlsOffset(sym);
+    return in.mipsCheriCapTable->getTlsOffset(sym);
   default:
     llvm_unreachable("invalid expression");
   }
diff --git a/lld/ELF/Relocations.cpp b/lld/ELF/Relocations.cpp
index 3f1293176a1d4..8f913bb72a97f 100644
--- a/lld/ELF/Relocations.cpp
+++ b/lld/ELF/Relocations.cpp
@@ -222,7 +222,7 @@ static bool isRelExpr(RelExpr expr) {
   return oneof<R_PC, R_GOTREL, R_GOTPLTREL, R_MIPS_GOTREL, R_PPC64_CALL,
                R_PPC64_RELAX_TOC, R_AARCH64_PAGE_PC, R_RELAX_GOT_PC,
                R_RISCV_PC_INDIRECT, R_PPC64_RELAX_GOT_PC, R_LOONGARCH_PAGE_PC,
-               R_CHERI_CAPABILITY_TABLE_REL>(expr);
+               R_MIPS_CHERI_CAPTAB_REL>(expr);
 }
 
 static RelExpr toPlt(RelExpr expr) {
@@ -890,20 +890,30 @@ template <class PltSection, class GotPltSection>
 static void addPltEntry(PltSection &plt, GotPltSection &gotPlt,
                         RelocationBaseSection &rel, RelType type, Symbol &sym) {
   plt.addEntry(sym);
-  if (config->isCheriAbi) {
-    // TODO: More normal .got.plt rather than piggy-backing on .captable. We
-    // pass R_CHERI_CAPABILITY_TABLE_INDEX rather than the more obvious
-    // R_CHERI_CAPABILITY_TABLE_INDEX_CALL to force dynamic relocations into
-    // .rela.dyn rather than .rela.plt so no rtld changes are needed, as the
-    // latter doesn't really achieve anything without lazy binding.
-    in.cheriCapTable->addEntry(sym, R_CHERI_CAPABILITY_TABLE_INDEX, &plt, 0);
-  } else {
-    gotPlt.addEntry(sym);
-    rel.addReloc({type, &gotPlt, sym.getGotPltOffset(),
-                  sym.isPreemptible ? DynamicReloc::AgainstSymbol
-                                    : DynamicReloc::AddendOnlyWithTargetVA,
-                  sym, 0, R_ABS});
-  }
+
+  // For CHERI-RISC-V if JUMP_SLOT relocations are disabled (to be compatible
+  // with old CheriBSD) we mark the symbol NEEDS_GOT so it will end up in .got
+  // as a function pointer, and uses .rela.dyn rather than .rela.plt, so no
+  // rtld changes are needed.
+  //
+  // TODO: Remove this option.
+  if (config->emachine == EM_RISCV && config->isCheriAbi &&
+      !config->zCheriRiscvJumpSlot)
+    return;
+
+  if (config->isCheriAbi && !sym.isPreemptible)
+    error("cannot create non-preemptible PLT entry on CHERI against symbol: " +
+          toString(sym));
+
+  gotPlt.addEntry(sym);
+  rel.addReloc({type, &gotPlt, sym.getGotPltOffset(),
+                sym.isPreemptible ? DynamicReloc::AgainstSymbol
+                                  : DynamicReloc::AddendOnlyWithTargetVA,
+                sym, 0, R_ABS});
+  if (config->isCheriAbi)
+    invokeELFT(addCapabilityRelocation, &plt, *target->cheriCapRel, &gotPlt,
+               sym.getGotPltOffset(), R_CHERI_CAPABILITY, 0, false,
+               [] { return ""; });
 }
 
 static void addGotEntry(Symbol &sym) {
@@ -918,8 +928,12 @@ static void addGotEntry(Symbol &sym) {
   }
 
   // Otherwise, the value is either a link-time constant or the load base
-  // plus a constant.
-  if (!config->isPic || isAbsolute(sym))
+  // plus a constant. For CHERI it always requires run-time initialisation.
+  if (config->isCheriAbi) {
+    invokeELFT(addCapabilityRelocation, &sym, *target->cheriCapRel,
+               in.got.get(), off, R_CHERI_CAPABILITY, 0, false,
+               [] { return ""; });
+  } else if (!config->isPic || isAbsolute(sym))
     in.got->addConstant({R_ABS, target->symbolicRel, off, 0, &sym});
   else
     addRelativeReloc(*in.got, off, sym, 0, R_ABS, target->symbolicRel);
@@ -971,12 +985,11 @@ bool RelocationScanner::isStaticLinkTimeConstant(RelExpr e, RelType type,
   // These expressions always compute a constant
   if (oneof<R_GOTPLT, R_GOT_OFF, R_RELAX_HINT, R_MIPS_GOT_LOCAL_PAGE,
             R_MIPS_GOTREL, R_MIPS_GOT_OFF, R_MIPS_GOT_OFF32, R_MIPS_GOT_GP_PC,
-            R_CHERI_CAPABILITY_TABLE_INDEX,
-            R_CHERI_CAPABILITY_TABLE_INDEX_SMALL_IMMEDIATE,
-            R_CHERI_CAPABILITY_TABLE_INDEX_CALL,
-            R_CHERI_CAPABILITY_TABLE_INDEX_CALL_SMALL_IMMEDIATE,
-            R_CHERI_CAPABILITY_TABLE_ENTRY_PC,
-            R_CHERI_CAPABILITY_TABLE_REL,
+            R_MIPS_CHERI_CAPTAB_INDEX,
+            R_MIPS_CHERI_CAPTAB_INDEX_SMALL_IMMEDIATE,
+            R_MIPS_CHERI_CAPTAB_INDEX_CALL,
+            R_MIPS_CHERI_CAPTAB_INDEX_CALL_SMALL_IMMEDIATE,
+            R_MIPS_CHERI_CAPTAB_REL,
             R_AARCH64_GOT_PAGE_PC, R_GOT_PC, R_GOTONLY_PC, R_GOTPLTONLY_PC,
             R_PLT_PC, R_PLT_GOTPLT, R_PPC32_PLTREL, R_PPC64_CALL_PLT,
             R_PPC64_RELAX_TOC, R_RISCV_ADD, R_AARCH64_GOT_PAGE,
@@ -1083,13 +1096,12 @@ void RelocationScanner::processAux(RelExpr expr, RelType type, uint64_t offset,
     return;
   }
 
-  if (oneof<R_CHERI_CAPABILITY_TABLE_INDEX,
-            R_CHERI_CAPABILITY_TABLE_INDEX_SMALL_IMMEDIATE,
-            R_CHERI_CAPABILITY_TABLE_INDEX_CALL,
-            R_CHERI_CAPABILITY_TABLE_INDEX_CALL_SMALL_IMMEDIATE,
-            R_CHERI_CAPABILITY_TABLE_ENTRY_PC>(expr)) {
+  if (oneof<R_MIPS_CHERI_CAPTAB_INDEX,
+            R_MIPS_CHERI_CAPTAB_INDEX_SMALL_IMMEDIATE,
+            R_MIPS_CHERI_CAPTAB_INDEX_CALL,
+            R_MIPS_CHERI_CAPTAB_INDEX_CALL_SMALL_IMMEDIATE>(expr)) {
     std::lock_guard<std::mutex> lock(relocMutex);
-    in.cheriCapTable->addEntry(sym, expr, sec, offset);
+    in.mipsCheriCapTable->addEntry(sym, expr, sec, offset);
     // Write out the index into the instruction
     sec->relocations.push_back({expr, type, offset, addend, &sym});
     return;
@@ -1112,6 +1124,10 @@ void RelocationScanner::processAux(RelExpr expr, RelType type, uint64_t offset,
     }
   } else if (needsPlt(expr)) {
     sym.setFlags(NEEDS_PLT);
+    // See addPltEntry
+    if (config->emachine == EM_RISCV && config->isCheriAbi &&
+        !config->zCheriRiscvJumpSlot)
+      sym.setFlags(NEEDS_GOT);
   } else if (LLVM_UNLIKELY(isIfunc)) {
     sym.setFlags(HAS_DIRECT_RELOC);
   }
@@ -1255,6 +1271,10 @@ void RelocationScanner::processAux(RelExpr expr, RelType type, uint64_t offset,
                     "' cannot be preempted; recompile with -fPIE" +
                     getLocation(*sec, sym, offset));
       sym.setFlags(NEEDS_COPY | NEEDS_PLT);
+      // See addPltEntry
+      if (config->emachine == EM_RISCV && config->isCheriAbi &&
+          !config->zCheriRiscvJumpSlot)
+        sym.setFlags(NEEDS_GOT);
       sec->addReloc({expr, type, offset, addend, &sym});
       return;
     }
@@ -1286,17 +1306,17 @@ static unsigned handleMipsTlsRelocation(RelType type, Symbol &sym,
     return 1;
   }
   if (expr == R_MIPS_CHERI_CAPTAB_TLSLD) {
-    in.cheriCapTable->addTlsIndex();
+    in.mipsCheriCapTable->addTlsIndex();
     c.relocations.push_back({expr, type, offset, addend, &sym});
     return 1;
   }
   if (expr == R_MIPS_CHERI_CAPTAB_TLSGD) {
-    in.cheriCapTable->addDynTlsEntry(sym);
+    in.mipsCheriCapTable->addDynTlsEntry(sym);
     c.relocations.push_back({expr, type, offset, addend, &sym});
     return 1;
   }
   if (expr == R_MIPS_CHERI_CAPTAB_TPREL) {
-    in.cheriCapTable->addTlsEntry(sym);
+    in.mipsCheriCapTable->addTlsEntry(sym);
     c.relocations.push_back({expr, type, offset, addend, &sym});
     return 1;
   }
@@ -1345,21 +1365,6 @@ static unsigned handleTlsRelocation(RelType type, Symbol &sym,
                      config->emachine != EM_RISCV &&
                      !c.file->ppc64DisableTLSRelax;
 
-  // No targets currently support TLS relaxation, so we can avoid duplicating
-  // much of the logic below for the captable.
-  if (expr == R_CHERI_CAPABILITY_TABLE_TLSGD_ENTRY_PC) {
-    std::lock_guard<std::mutex> lock(relocMutex);
-    in.cheriCapTable->addDynTlsEntry(sym);
-    c.relocations.push_back({expr, type, offset, addend, &sym});
-    return 1;
-  }
-  if (expr == R_CHERI_CAPABILITY_TABLE_TLSIE_ENTRY_PC) {
-    std::lock_guard<std::mutex> lock(relocMutex);
-    in.cheriCapTable->addTlsEntry(sym);
-    c.relocations.push_back({expr, type, offset, addend, &sym});
-    return 1;
-  }
-
   // If we are producing an executable and the symbol is non-preemptable, it
   // must be defined and the code sequence can be relaxed to use Local-Exec.
   //
diff --git a/lld/ELF/Relocations.h b/lld/ELF/Relocations.h
index b0ca7a496b060..1433fb8e0c558 100644
--- a/lld/ELF/Relocations.h
+++ b/lld/ELF/Relocations.h
@@ -102,14 +102,11 @@ enum RelExpr {
   R_PPC64_RELAX_GOT_PC,
   R_RISCV_ADD,
   R_RISCV_PC_INDIRECT,
-  R_CHERI_CAPABILITY_TABLE_INDEX,
-  R_CHERI_CAPABILITY_TABLE_INDEX_SMALL_IMMEDIATE,
-  R_CHERI_CAPABILITY_TABLE_INDEX_CALL,
-  R_CHERI_CAPABILITY_TABLE_INDEX_CALL_SMALL_IMMEDIATE,
-  R_CHERI_CAPABILITY_TABLE_ENTRY_PC,
-  R_CHERI_CAPABILITY_TABLE_TLSGD_ENTRY_PC,
-  R_CHERI_CAPABILITY_TABLE_TLSIE_ENTRY_PC,
-  R_CHERI_CAPABILITY_TABLE_REL, // relative offset to _CHERI_CAPABILITY_TABLE_
+  R_MIPS_CHERI_CAPTAB_INDEX,
+  R_MIPS_CHERI_CAPTAB_INDEX_SMALL_IMMEDIATE,
+  R_MIPS_CHERI_CAPTAB_INDEX_CALL,
+  R_MIPS_CHERI_CAPTAB_INDEX_CALL_SMALL_IMMEDIATE,
+  R_MIPS_CHERI_CAPTAB_REL, // relative offset to _CHERI_CAPABILITY_TABLE_
   R_MIPS_CHERI_CAPTAB_TLSGD,
   R_MIPS_CHERI_CAPTAB_TLSLD,
   R_MIPS_CHERI_CAPTAB_TPREL,
diff --git a/lld/ELF/Symbols.cpp b/lld/ELF/Symbols.cpp
index f7be8a79040f0..a7539598e51c5 100644
--- a/lld/ELF/Symbols.cpp
+++ b/lld/ELF/Symbols.cpp
@@ -138,7 +138,7 @@ Defined *ElfSym::globalOffsetTable;
 Defined *ElfSym::mipsGp;
 Defined *ElfSym::mipsGpDisp;
 Defined *ElfSym::mipsLocalGp;
-Defined *ElfSym::cheriCapabilityTable;
+Defined *ElfSym::mipsCheriCapabilityTable;
 Defined *ElfSym::riscvGlobalPointer;
 Defined *ElfSym::relaIpltStart;
 Defined *ElfSym::relaIpltEnd;
@@ -266,16 +266,16 @@ uint64_t Symbol::getPltVA() const {
   return outVA;
 }
 
-uint64_t Symbol::getCapTableVA(const InputSectionBase *isec,
-                               uint64_t offset) const {
-  return ElfSym::cheriCapabilityTable->getVA() +
-    getCapTableOffset(isec, offset);
+uint64_t Symbol::getMipsCheriCapTableVA(const InputSectionBase *isec,
+                                        uint64_t offset) const {
+  return ElfSym::mipsCheriCapabilityTable->getVA() +
+         getMipsCheriCapTableOffset(isec, offset);
 }
 
-uint64_t Symbol::getCapTableOffset(const InputSectionBase *isec,
-                                   uint64_t offset) const {
+uint64_t Symbol::getMipsCheriCapTableOffset(const InputSectionBase *isec,
+                                            uint64_t offset) const {
   return config->capabilitySize *
-    in.cheriCapTable->getIndex(*this, isec, offset);
+         in.mipsCheriCapTable->getIndex(*this, isec, offset);
 }
 
 uint64_t Defined::getSize() const {
diff --git a/lld/ELF/Symbols.h b/lld/ELF/Symbols.h
index fb7b28c1f9362..46c26aa693682 100644
--- a/lld/ELF/Symbols.h
+++ b/lld/ELF/Symbols.h
@@ -226,9 +226,10 @@ class Symbol {
   uint64_t getGotPltOffset() const;
   uint64_t getGotPltVA() const;
   uint64_t getPltVA() const;
-  uint64_t getCapTableVA(const InputSectionBase *isec, uint64_t offset) const;
-  uint64_t getCapTableOffset(const InputSectionBase *isec,
-                             uint64_t offset) const;
+  uint64_t getMipsCheriCapTableVA(const InputSectionBase *isec,
+                                  uint64_t offset) const;
+  uint64_t getMipsCheriCapTableOffset(const InputSectionBase *isec,
+                                      uint64_t offset) const;
   uint64_t getSize() const;
   OutputSection *getOutputSection() const;
 
@@ -540,8 +541,8 @@ struct ElfSym {
   static Defined *mipsLocalGp;
 
   // The _CHERI_CAPABILITY_TABLE_ symbol points to the beginning of the
-  // .captable section
-  static Defined *cheriCapabilityTable;
+  // .captable section. Only for MIPS.
+  static Defined *mipsCheriCapabilityTable;
 
   // __global_pointer$ for RISC-V.
   static Defined *riscvGlobalPointer;
diff --git a/lld/ELF/SyntheticSections.cpp b/lld/ELF/SyntheticSections.cpp
index 9359742a9fbc3..2b1720ede264d 100644
--- a/lld/ELF/SyntheticSections.cpp
+++ b/lld/ELF/SyntheticSections.cpp
@@ -660,6 +660,9 @@ GotSection::GotSection()
 
 void GotSection::addConstant(const Relocation &r) { relocations.push_back(r); }
 void GotSection::addEntry(Symbol &sym) {
+  // TODO: Separate out TLS IE entries for CHERI so we can pack them more
+  // efficiently rather than consuming a whole capability-sized slot for an
+  // integer.
   assert(sym.auxIdx == symAux.size() - 1);
   symAux.back().gotIdx = numEntries++;
 }
@@ -674,8 +677,12 @@ bool GotSection::addTlsDescEntry(Symbol &sym) {
 bool GotSection::addDynTlsEntry(Symbol &sym) {
   assert(sym.auxIdx == symAux.size() - 1);
   symAux.back().tlsGdIdx = numEntries;
-  // Global Dynamic TLS entries take two GOT slots.
-  numEntries += 2;
+  // Global Dynamic TLS entries take two GOT slots, except on CHERI where they
+  // can be packed into one GOT slot.
+  if (config->isCheriAbi)
+    ++numEntries;
+  else
+    numEntries += 2;
   return true;
 }
 
@@ -684,13 +691,13 @@ bool GotSection::addDynTlsEntry(Symbol &sym) {
 bool GotSection::addTlsIndex() {
   if (tlsIndexOff != uint32_t(-1))
     return false;
-  tlsIndexOff = numEntries * config->wordsize;
+  tlsIndexOff = numEntries * target->gotEntrySize;
   numEntries += 2;
   return true;
 }
 
 uint32_t GotSection::getTlsDescOffset(const Symbol &sym) const {
-  return sym.getTlsDescIdx() * config->wordsize;
+  return sym.getTlsDescIdx() * target->gotEntrySize;
 }
 
 uint64_t GotSection::getTlsDescAddr(const Symbol &sym) const {
@@ -698,11 +705,11 @@ uint64_t GotSection::getTlsDescAddr(const Symbol &sym) const {
 }
 
 uint64_t GotSection::getGlobalDynAddr(const Symbol &b) const {
-  return this->getVA() + b.getTlsGdIdx() * config->wordsize;
+  return this->getVA() + b.getTlsGdIdx() * target->gotEntrySize;
 }
 
 uint64_t GotSection::getGlobalDynOffset(const Symbol &b) const {
-  return b.getTlsGdIdx() * config->wordsize;
+  return b.getTlsGdIdx() * target->gotEntrySize;
 }
 
 void GotSection::finalizeContents() {
@@ -710,7 +717,7 @@ void GotSection::finalizeContents() {
       numEntries <= target->gotHeaderEntriesNum && !ElfSym::globalOffsetTable)
     size = 0;
   else
-    size = numEntries * config->wordsize;
+    size = numEntries * target->gotEntrySize;
 }
 
 bool GotSection::isNeeded() const {
@@ -1167,8 +1174,8 @@ void MipsGotSection::writeTo(uint8_t *buf) {
 // section. I don't know why we have a BSS style type for the section but it is
 // consistent across both 64-bit PowerPC ABIs as well as the 32-bit PowerPC ABI.
 GotPltSection::GotPltSection()
-    : SyntheticSection(SHF_ALLOC | SHF_WRITE, SHT_PROGBITS, config->wordsize,
-                       ".got.plt") {
+    : SyntheticSection(SHF_ALLOC | SHF_WRITE, SHT_PROGBITS,
+                       target->gotEntrySize, ".got.plt") {
   if (config->emachine == EM_PPC) {
     name = ".plt";
   } else if (config->emachine == EM_PPC64) {
@@ -1579,14 +1586,15 @@ DynamicSection<ELFT>::computeContents() {
       if (f->isNeeded)
         checkMipsShlibCompatible(f, f->cheriFlags, targetCheriFlags);
     }
-    if (in.cheriCapTable && in.cheriCapTable->isNeeded()) {
-      addInSec(DT_MIPS_CHERI_CAPTABLE, *in.cheriCapTable);
-      addInt(DT_MIPS_CHERI_CAPTABLESZ, in.cheriCapTable->getParent()->size);
+    if (in.mipsCheriCapTable && in.mipsCheriCapTable->isNeeded()) {
+      addInSec(DT_MIPS_CHERI_CAPTABLE, *in.mipsCheriCapTable);
+      addInt(DT_MIPS_CHERI_CAPTABLESZ, in.mipsCheriCapTable->getParent()->size);
     }
-    if (in.cheriCapTableMapping && in.cheriCapTableMapping->isNeeded()) {
-      addInSec(DT_MIPS_CHERI_CAPTABLE_MAPPING, *in.cheriCapTableMapping);
+    if (in.mipsCheriCapTableMapping &&
+        in.mipsCheriCapTableMapping->isNeeded()) {
+      addInSec(DT_MIPS_CHERI_CAPTABLE_MAPPING, *in.mipsCheriCapTableMapping);
       addInt(DT_MIPS_CHERI_CAPTABLE_MAPPINGSZ,
-             in.cheriCapTableMapping->getParent()->size);
+             in.mipsCheriCapTableMapping->getParent()->size);
     }
     if (in.capRelocs && in.capRelocs->isNeeded()) {
       addInSec(DT_MIPS_CHERI___CAPRELOCS, *in.capRelocs);
@@ -1732,9 +1740,10 @@ void RelocationBaseSection::finalizeContents() {
   if (in.relaPlt.get() == this && in.gotPlt->getParent()) {
     getParent()->flags |= ELF::SHF_INFO_LINK;
     // For CheriABI we use the captable as the sh_info value
-    if (config->isCheriAbi && in.cheriCapTable && in.cheriCapTable->isNeeded()) {
-      assert(in.cheriCapTable->getParent()->sectionIndex != UINT32_MAX);
-      getParent()->info = in.cheriCapTable->getParent()->sectionIndex;
+    if (config->isCheriAbi && in.mipsCheriCapTable &&
+        in.mipsCheriCapTable->isNeeded()) {
+      assert(in.mipsCheriCapTable->getParent()->sectionIndex != UINT32_MAX);
+      getParent()->info = in.mipsCheriCapTable->getParent()->sectionIndex;
     } else {
       getParent()->info = in.gotPlt->getParent()->sectionIndex;
     }
@@ -1742,9 +1751,10 @@ void RelocationBaseSection::finalizeContents() {
   if (in.relaIplt.get() == this && in.igotPlt->getParent()) {
     getParent()->flags |= ELF::SHF_INFO_LINK;
     // For CheriABI we use the captable as the sh_info value
-    if (config->isCheriAbi && in.cheriCapTable && in.cheriCapTable->isNeeded()) {
-      assert(in.cheriCapTable->getParent()->sectionIndex != UINT32_MAX);
-      getParent()->info = in.cheriCapTable->getParent()->sectionIndex;
+    if (config->isCheriAbi && in.mipsCheriCapTable &&
+        in.mipsCheriCapTable->isNeeded()) {
+      assert(in.mipsCheriCapTable->getParent()->sectionIndex != UINT32_MAX);
+      getParent()->info = in.mipsCheriCapTable->getParent()->sectionIndex;
     } else {
       getParent()->info = in.igotPlt->getParent()->sectionIndex;
     }
@@ -3950,8 +3960,8 @@ void InStruct::reset() {
   bss.reset();
   bssRelRo.reset();
   capRelocs.reset();
-  cheriCapTableMapping.reset();
-  cheriCapTableMapping.reset();
+  mipsCheriCapTableMapping.reset();
+  mipsCheriCapTableMapping.reset();
   got.reset();
   gotPlt.reset();
   igotPlt.reset();
diff --git a/lld/ELF/SyntheticSections.h b/lld/ELF/SyntheticSections.h
index 69cb8830ab7a2..7632a2c274058 100644
--- a/lld/ELF/SyntheticSections.h
+++ b/lld/ELF/SyntheticSections.h
@@ -1217,8 +1217,8 @@ class PPC64LongBranchTargetSection final : public SyntheticSection {
 
 // Can only be forward declared here since it depends on SyntheticSection
 class CheriCapRelocsSection;
-class CheriCapTableSection;
-class CheriCapTableMappingSection;
+class MipsCheriCapTableSection;
+class MipsCheriCapTableMappingSection;
 
 template <typename ELFT>
 class PartitionElfHeaderSection final : public SyntheticSection {
@@ -1324,10 +1324,10 @@ struct InStruct {
   std::unique_ptr<GotSection> got;
   std::unique_ptr<GotPltSection> gotPlt;
   std::unique_ptr<IgotPltSection> igotPlt;
-  std::unique_ptr<CheriCapTableSection> cheriCapTable;
+  std::unique_ptr<MipsCheriCapTableSection> mipsCheriCapTable;
   std::unique_ptr<CheriCapRelocsSection> capRelocs;
   // For per-file/per-function tables:
-  std::unique_ptr<CheriCapTableMappingSection> cheriCapTableMapping;
+  std::unique_ptr<MipsCheriCapTableMappingSection> mipsCheriCapTableMapping;
   std::unique_ptr<SyntheticSection> armCmseSGSection;
   std::unique_ptr<PPC64LongBranchTargetSection> ppc64LongBranchTarget;
   std::unique_ptr<SyntheticSection> mipsAbiFlags;
diff --git a/lld/ELF/Writer.cpp b/lld/ELF/Writer.cpp
index d4eaedee57ab4..96ca015ecb457 100644
--- a/lld/ELF/Writer.cpp
+++ b/lld/ELF/Writer.cpp
@@ -321,11 +321,15 @@ template <class ELFT> void elf::createSyntheticSections() {
 
   if (config->capabilitySize > 0) {
     in.capRelocs = std::make_unique<CheriCapRelocsSection>("__cap_relocs");
-    in.cheriCapTable = std::make_unique<CheriCapTableSection>();
-    add(*in.cheriCapTable);
-    if (config->capTableScope != CapTableScopePolicy::All) {
-      in.cheriCapTableMapping = std::make_unique<CheriCapTableMappingSection>();
-      add(*in.cheriCapTableMapping);
+
+    if (config->emachine == EM_MIPS) {
+      in.mipsCheriCapTable = std::make_unique<MipsCheriCapTableSection>();
+      add(*in.mipsCheriCapTable);
+      if (config->capTableScope != CapTableScopePolicy::All) {
+        in.mipsCheriCapTableMapping =
+            std::make_unique<MipsCheriCapTableMappingSection>();
+        add(*in.mipsCheriCapTableMapping);
+      }
     }
   }
 
@@ -847,7 +851,7 @@ bool elf::isRelroSection(const OutputSection *sec) {
 
   // Similarly the CHERI capability table is also relro since the capabilities
   // in the table need to be initialized at runtime to set the tag bits
-  if (in.cheriCapTable && sec == in.cheriCapTable->getParent()) {
+  if (in.mipsCheriCapTable && sec == in.mipsCheriCapTable->getParent()) {
     // Without -z now, the PLT stubs can update the captable entries so we
     // can't mark it as relro. It can also be relro for static binaries:
     return config->zNow || !config->isPic;
@@ -1944,13 +1948,13 @@ template <class ELFT> void Writer<ELFT>::finalizeSections() {
       }
     }
 
-    if (in.cheriCapTable) {
+    if (config->emachine == EM_MIPS && in.mipsCheriCapTable) {
       // When creating relocatable output we should not define the
       // _CHERI_CAPABILITY_TABLE_ symbol because otherwise we get duplicate
       // symbol errors when linking that into a final executable
       if (!config->relocatable)
-        ElfSym::cheriCapabilityTable =
-            addOptionalRegular(captableSym, in.cheriCapTable.get(), 0);
+        ElfSym::mipsCheriCapabilityTable =
+            addOptionalRegular(captableSym, in.mipsCheriCapTable.get(), 0);
     }
 
     // This responsible for splitting up .eh_frame section into
@@ -1987,18 +1991,19 @@ template <class ELFT> void Writer<ELFT>::finalizeSections() {
     // Do the cap table index assignment
     // Must come before CapRelocs->finalizeContents() because it can add
     // __cap_relocs
-    if (in.cheriCapTable) {
+    if (in.mipsCheriCapTable) {
       // Ensure that we always have a _CHERI_CAPABILITY_TABLE_ symbol if the
       // cap table exists. This makes llvm-objdump more useful since it can now
       // print the target of a cap table load
-      if (!ElfSym::cheriCapabilityTable && in.cheriCapTable->isNeeded()) {
-        ElfSym::cheriCapabilityTable = cast<Defined>(
-            symtab.addSymbol(Defined{nullptr, captableSym, STB_LOCAL,
-              STV_HIDDEN, STT_NOTYPE, 0, 0, in.cheriCapTable.get()}));
-        ElfSym::cheriCapabilityTable->isSectionStartSymbol = true;
-        assert(!ElfSym::cheriCapabilityTable->isPreemptible);
+      if (!ElfSym::mipsCheriCapabilityTable &&
+          in.mipsCheriCapTable->isNeeded()) {
+        ElfSym::mipsCheriCapabilityTable = cast<Defined>(symtab.addSymbol(
+            Defined{nullptr, captableSym, STB_LOCAL, STV_HIDDEN, STT_NOTYPE, 0,
+                    0, in.mipsCheriCapTable.get()}));
+        ElfSym::mipsCheriCapabilityTable->isSectionStartSymbol = true;
+        assert(!ElfSym::mipsCheriCapabilityTable->isPreemptible);
       }
-      in.cheriCapTable->assignValuesAndAddCapTableSymbols<ELFT>();
+      in.mipsCheriCapTable->assignValuesAndAddCapTableSymbols<ELFT>();
     }
 
     // Now handle __cap_relocs (must be before RelaDyn because it might
@@ -2342,9 +2347,9 @@ template <class ELFT> void Writer<ELFT>::addStartEndSymbols() {
   define("__fini_array_start", "__fini_array_end", Out::finiArray);
   define("__ctors_start", "__ctors_end", findSection(".ctors"));
   define("__dtors_start", "__dtors_end", findSection(".dtors"));
-  if (in.cheriCapTable)
+  if (in.mipsCheriCapTable)
     define("__cap_table_start", "__cap_table_end",
-           in.cheriCapTable->getOutputSection());
+           in.mipsCheriCapTable->getOutputSection());
 
   if (OutputSection *sec = findSection(".ARM.exidx"))
     define("__exidx_start", "__exidx_end", sec);
diff --git a/lld/test/ELF/cheri/riscv/plt.s b/lld/test/ELF/cheri/riscv/plt.s
index 432a8d44d6287..471f9eadd67e5 100644
--- a/lld/test/ELF/cheri/riscv/plt.s
+++ b/lld/test/ELF/cheri/riscv/plt.s
@@ -4,20 +4,30 @@
 # RUN: %riscv32_cheri_purecap_llvm-mc -filetype=obj %t1.s -o %t1.32.o
 # RUN: ld.lld -shared %t1.32.o -soname=t1.32.so -o %t1.32.so
 # RUN: %riscv32_cheri_purecap_llvm-mc -filetype=obj %s -o %t.32.o
-# RUN: ld.lld %t.32.o %t1.32.so -z separate-code -o %t.32
-# RUN: llvm-readelf -S -s %t.32 | FileCheck --check-prefixes=SEC,NM %s
-# RUN: llvm-readobj -r %t.32 | FileCheck --check-prefix=RELOC32 %s
-# RUN: llvm-readelf -x .captable %t.32 | FileCheck --check-prefix=CAPTAB32 %s
-# RUN: llvm-objdump -d --no-show-raw-insn %t.32 | FileCheck --check-prefixes=DIS,DIS32 %s
+# RUN: ld.lld %t.32.o %t1.32.so -z separate-code -o %t.32.got
+# RUN: llvm-readelf -S -s %t.32.got | FileCheck --check-prefixes=SEC,NM %s
+# RUN: llvm-readobj -r --cap-relocs %t.32.got | FileCheck --check-prefix=RELOCGOT32 %s
+# RUN: llvm-readelf -x .got %t.32.got | FileCheck --check-prefix=GOT32 %s
+# RUN: llvm-objdump -d --no-show-raw-insn %t.32.got | FileCheck --check-prefixes=DIS,DISGOT,DISGOT32 %s
+# RUN: ld.lld %t.32.o %t1.32.so -z separate-code -z cheri-riscv-jump-slot -o %t.32.got.plt
+# RUN: llvm-readelf -S -s %t.32.got.plt | FileCheck --check-prefixes=SEC,NM %s
+# RUN: llvm-readobj -r --cap-relocs %t.32.got.plt | FileCheck --check-prefix=RELOCGOTPLT32 %s
+# RUN: llvm-readelf -x .got.plt %t.32.got.plt | FileCheck --check-prefix=GOTPLT32 %s
+# RUN: llvm-objdump -d --no-show-raw-insn %t.32.got.plt | FileCheck --check-prefixes=DIS,DISGOTPLT,DISGOTPLT32 %s
 
 # RUN: %riscv64_cheri_purecap_llvm-mc -filetype=obj %t1.s -o %t1.64.o
 # RUN: ld.lld -shared %t1.64.o -soname=t1.64.so -o %t1.64.so
 # RUN: %riscv64_cheri_purecap_llvm-mc -filetype=obj %s -o %t.64.o
-# RUN: ld.lld %t.64.o %t1.64.so -z separate-code -o %t.64
-# RUN: llvm-readelf -S -s %t.64 | FileCheck --check-prefixes=SEC,NM %s
-# RUN: llvm-readobj -r %t.64 | FileCheck --check-prefix=RELOC64 %s
-# RUN: llvm-readelf -x .captable %t.64 | FileCheck --check-prefix=CAPTAB64 %s
-# RUN: llvm-objdump -d --no-show-raw-insn %t.64 | FileCheck --check-prefixes=DIS,DIS64 %s
+# RUN: ld.lld %t.64.o %t1.64.so -z separate-code -o %t.64.got
+# RUN: llvm-readelf -S -s %t.64.got | FileCheck --check-prefixes=SEC,NM %s
+# RUN: llvm-readobj -r --cap-relocs %t.64.got | FileCheck --check-prefix=RELOCGOT64 %s
+# RUN: llvm-readelf -x .got %t.64.got | FileCheck --check-prefix=GOT64 %s
+# RUN: llvm-objdump -d --no-show-raw-insn %t.64.got | FileCheck --check-prefixes=DIS,DISGOT,DISGOT64 %s
+# RUN: ld.lld %t.64.o %t1.64.so -z separate-code -z cheri-riscv-jump-slot -o %t.64.got.plt
+# RUN: llvm-readelf -S -s %t.64.got.plt | FileCheck --check-prefixes=SEC,NM %s
+# RUN: llvm-readobj -r --cap-relocs %t.64.got.plt | FileCheck --check-prefix=RELOCGOTPLT64 %s
+# RUN: llvm-readelf -x .got.plt %t.64.got.plt | FileCheck --check-prefix=GOTPLT64 %s
+# RUN: llvm-objdump -d --no-show-raw-insn %t.64.got.plt | FileCheck --check-prefixes=DIS,DISGOTPLT,DISGOTPLT64 %s
 
 # SEC: .plt PROGBITS {{0*}}00011030
 
@@ -26,20 +36,50 @@
 # NM: {{0*}}00000000 0 FUNC GLOBAL DEFAULT UND bar
 # NM: {{0*}}00000000 0 FUNC WEAK   DEFAULT UND weak
 
-# RELOC32:      .rela.dyn {
-# RELOC32-NEXT:   0x12000 R_RISCV_CHERI_CAPABILITY bar 0x0
-# RELOC32-NEXT:   0x12008 R_RISCV_CHERI_CAPABILITY weak 0x0
-# RELOC32-NEXT: }
-# CAPTAB32:      section '.captable'
-# CAPTAB32-NEXT: 0x00012000 00000000 00000000 00000000 00000000
+# RELOCGOT32:      .rela.dyn {
+# RELOCGOT32-NEXT:   0x12068 R_RISCV_CHERI_CAPABILITY bar 0x0
+# RELOCGOT32-NEXT:   0x12070 R_RISCV_CHERI_CAPABILITY weak 0x0
+# RELOCGOT32-NEXT: }
+# RELOCGOT32:      There is no __cap_relocs section in the file.
+# GOT32:      section '.got'
+# GOT32-NEXT: 0x00012060 00200100 00000000 00000000 00000000
+# GOT32-NEXT: 0x00012070 00000000 00000000
 
-# RELOC64:      .rela.dyn {
-# RELOC64-NEXT:   0x12000 R_RISCV_CHERI_CAPABILITY bar 0x0
-# RELOC64-NEXT:   0x12010 R_RISCV_CHERI_CAPABILITY weak 0x0
-# RELOC64-NEXT: }
-# CAPTAB64:      section '.captable'
-# CAPTAB64-NEXT: 0x00012000 00000000 00000000 00000000 00000000
-# CAPTAB64-NEXT: 0x00012010 00000000 00000000 00000000 00000000
+# RELOCGOTPLT32:      .rela.plt {
+# RELOCGOTPLT32-NEXT:   0x13088 R_RISCV_JUMP_SLOT bar 0x0
+# RELOCGOTPLT32-NEXT:   0x13090 R_RISCV_JUMP_SLOT weak 0x0
+# RELOCGOTPLT32-NEXT: }
+# RELOCGOTPLT32:      CHERI __cap_relocs [
+# RELOCGOTPLT32-NEXT:   0x013088 Base: 0x11030 (<unknown symbol>+0) Length: 64 Perms: Function
+# RELOCGOTPLT32-NEXT:   0x013090 Base: 0x11030 (<unknown symbol>+0) Length: 64 Perms: Function
+# RELOCGOTPLT32-NEXT: ]
+# GOTPLT32:      section '.got.plt'
+# GOTPLT32-NEXT: 0x00013078 00000000 00000000 00000000 00000000
+# GOTPLT32-NEXT: 0x00013088 00000000 00000000 00000000 00000000
+
+# RELOCGOT64:      .rela.dyn {
+# RELOCGOT64-NEXT:   0x120D0 R_RISCV_CHERI_CAPABILITY bar 0x0
+# RELOCGOT64-NEXT:   0x120E0 R_RISCV_CHERI_CAPABILITY weak 0x0
+# RELOCGOT64-NEXT: }
+# RELOCGOT64:      There is no __cap_relocs section in the file.
+# GOT64:      section '.got'
+# GOT64-NEXT: 0x000120c0 00200100 00000000 00000000 00000000
+# GOT64-NEXT: 0x000120d0 00000000 00000000 00000000 00000000
+# GOT64-NEXT: 0x000120e0 00000000 00000000 00000000 00000000
+
+# RELOCGOTPLT64:      .rela.plt {
+# RELOCGOTPLT64-NEXT:   0x13110 R_RISCV_JUMP_SLOT bar 0x0
+# RELOCGOTPLT64-NEXT:   0x13120 R_RISCV_JUMP_SLOT weak 0x0
+# RELOCGOTPLT64-NEXT: }
+# RELOCGOTPLT64:      CHERI __cap_relocs [
+# RELOCGOTPLT64-NEXT:   0x013110 Base: 0x11030 (<unknown symbol>+0) Length: 64 Perms: Function
+# RELOCGOTPLT64-NEXT:   0x013120 Base: 0x11030 (<unknown symbol>+0) Length: 64 Perms: Function
+# RELOCGOTPLT64-NEXT: ]
+# GOTPLT64:      section '.got.plt'
+# GOTPLT64-NEXT: 0x000130f0 00000000 00000000 00000000 00000000
+# GOTPLT64-NEXT: 0x00013100 00000000 00000000 00000000 00000000
+# GOTPLT64-NEXT: 0x00013110 00000000 00000000 00000000 00000000
+# GOTPLT64-NEXT: 0x00013120 00000000 00000000 00000000 00000000
 
 # DIS:      <_start>:
 ## Direct call
@@ -58,23 +98,49 @@
 # DIS:      <foo>:
 # DIS-NEXT:   11020:
 
-# DIS:      Disassembly of section .plt:
-# DIS:      <.plt>:
-# DIS-NEXT:     ...
+# DIS:              Disassembly of section .plt:
+# DIS:              <.plt>:
+# DISGOT-NEXT:          ...
+# DISGOTPLT-NEXT:       auipcc ct2, 2
+# DISGOTPLT-NEXT:       sub t1, t1, t3
+## 32-bit: .got.plt - .plt = 0x13078 - 0x11030 = 4096*2+72
+## 64-bit: .got.plt - .plt = 0x130f0 - 0x11030 = 4096*2+192
+# DISGOTPLT32-NEXT:     lc ct3, 72(ct2)
+# DISGOTPLT64-NEXT:     lc ct3, 192(ct2)
+# DISGOTPLT-NEXT:       addi t1, t1, -44
+# DISGOTPLT32-NEXT:     cincoffset ct0, ct2, 72
+# DISGOTPLT64-NEXT:     cincoffset ct0, ct2, 192
+# DISGOTPLT32-NEXT:     srli t1, t1, 1
+# DISGOTPLT32-NEXT:     lc ct0, 8(ct0)
+# DISGOTPLT64-NEXT:     lc ct0, 16(ct0)
+# DISGOTPLT-NEXT:       jr ct3
+# DISGOTPLT64-NEXT:     nop
 
-## 32-bit: &.captable[bar]-. = 0x12000-0x11050 = 4096*1-80
-# DIS:        11050: auipcc ct3, 1
-# DIS32-NEXT:   lc ct3, -80(ct3)
-# DIS64-NEXT:   lc ct3, -80(ct3)
-# DIS-NEXT:     jalr ct1, ct3
-# DIS-NEXT:     nop
+## 32-bit (.got): &.got[bar]-. = 0x12068-0x11050 = 4096*1+24
+## 64-bit (.got): &.got[bar]-. = 0x120d0-0x11050 = 4096*1+128
+## 32-bit (.got.plt): &.got.plt[bar]-. = 0x13088-0x11050 = 4096*2+56
+## 64-bit (.got.plt): &.got.plt[bar]-. = 0x13110-0x11050 = 4096*2+192
+# DISGOT:           11050: auipcc ct3, 1
+# DISGOTPLT:        11050: auipcc ct3, 2
+# DISGOT32-NEXT:      lc ct3, 24(ct3)
+# DISGOT64-NEXT:      lc ct3, 128(ct3)
+# DISGOTPLT32-NEXT:   lc ct3, 56(ct3)
+# DISGOTPLT64-NEXT:   lc ct3, 192(ct3)
+# DIS-NEXT:           jalr ct1, ct3
+# DIS-NEXT:           nop
 
-## 32-bit: &.captable[weak]-. = 0x12008-0x11060 = 4096*1-88
-# DIS:        11060: auipcc ct3, 1
-# DIS32-NEXT:   lc ct3, -88(ct3)
-# DIS64-NEXT:   lc ct3, -80(ct3)
-# DIS-NEXT:     jalr ct1, ct3
-# DIS-NEXT:     nop
+## 32-bit (.got): &.got[weak]-. = 0x12070-0x11060 = 4096*1+16
+## 64-bit (.got): &.got[weak]-. = 0x120e0-0x11060 = 4096*1+128
+## 32-bit (.got.plt): &.got.plt[weak]-. = 0x13090-0x11060 = 4096*2+48
+## 64-bit (.got.plt): &.got.plt[weak]-. = 0x13120-0x11060 = 4096*2+192
+# DISGOT:           11060: auipcc ct3, 1
+# DISGOTPLT:        11060: auipcc ct3, 2
+# DISGOT32-NEXT:      lc ct3, 16(ct3)
+# DISGOT64-NEXT:      lc ct3, 128(ct3)
+# DISGOTPLT32-NEXT:   lc ct3, 48(ct3)
+# DISGOTPLT64-NEXT:   lc ct3, 192(ct3)
+# DIS-NEXT:           jalr ct1, ct3
+# DIS-NEXT:           nop
 
 .global _start, foo, bar
 .weak weak
diff --git a/lld/test/ELF/cheri/riscv/reloc-got.s b/lld/test/ELF/cheri/riscv/reloc-got.s
new file mode 100644
index 0000000000000..b9c99fbb01e0f
--- /dev/null
+++ b/lld/test/ELF/cheri/riscv/reloc-got.s
@@ -0,0 +1,77 @@
+# REQUIRES: riscv
+# RUN: echo '.globl b; b:' | %riscv32_cheri_purecap_llvm-mc -filetype=obj - -o %t1.o
+# RUN: ld.lld -shared %t1.o -soname=t1.so -o %t1.so
+
+# RUN: %riscv32_cheri_purecap_llvm-mc -filetype=obj -position-independent %s -o %t.o
+# RUN: ld.lld %t.o %t1.so -o %t
+# RUN: llvm-readelf -S %t | FileCheck --check-prefix=SEC32 %s
+# RUN: llvm-readobj -r --cap-relocs %t | FileCheck --check-prefix=RELOC32 %s
+# RUN: llvm-nm %t | FileCheck --check-prefix=NM32 %s
+# RUN: llvm-readobj -x .got %t | FileCheck --check-prefix=HEX32 %s
+# RUN: llvm-objdump -d --no-show-raw-insn %t | FileCheck --check-prefix=DIS32 %s
+
+# RUN: echo '.globl b; b:' | %riscv64_cheri_purecap_llvm-mc -filetype=obj - -o %t1.o
+# RUN: ld.lld -shared %t1.o -soname=t1.so -o %t1.so
+
+# RUN: %riscv64_cheri_purecap_llvm-mc -filetype=obj -position-independent %s -o %t.o
+# RUN: ld.lld %t.o %t1.so -o %t
+# RUN: llvm-readelf -S %t | FileCheck --check-prefix=SEC64 %s
+# RUN: llvm-readobj -r --cap-relocs %t | FileCheck --check-prefix=RELOC64 %s
+# RUN: llvm-nm %t | FileCheck --check-prefix=NM64 %s
+# RUN: llvm-readobj -x .got %t | FileCheck --check-prefix=HEX64 %s
+# RUN: llvm-objdump -d --no-show-raw-insn %t | FileCheck --check-prefix=DIS64 %s
+
+# SEC32: .got PROGBITS         00012230 000230 000018
+# SEC64: .got PROGBITS 00000000000123a0 0003a0 000030
+
+# RELOC32:      .rela.dyn {
+# RELOC32-NEXT:   0x12238 R_RISCV_CHERI_CAPABILITY b 0x0
+# RELOC32-NEXT: }
+# RELOC32:      CHERI __cap_relocs [
+# RELOC32-NEXT:   0x012240 Base: 0x13248 (a+0) Length: 4 Perms: Object
+# RELOC32-NEXT: ]
+
+# RELOC64:      .rela.dyn {
+# RELOC64-NEXT:   0x123B0 R_RISCV_CHERI_CAPABILITY b 0x0
+# RELOC64-NEXT: }
+# RELOC64:      CHERI __cap_relocs [
+# RELOC64-NEXT:   0x0123c0 Base: 0x133d0 (a+0) Length: 4 Perms: Object
+# RELOC64-NEXT: ]
+
+# NM32: 00013248 d a
+# NM64: 00000000000133d0 d a
+
+## .got[0] = _DYNAMIC
+## .got[1] = 0 (relocated by R_RISCV_CHERI_CAPABILITY at run time)
+## .got[2] = 0 (relocated by __cap_relocs at run time)
+# HEX32: section '.got':
+# HEX32: 0x00012230 c0210100 00000000 00000000 00000000
+# HEX32: 0x00012240 00000000 00000000
+
+# HEX64: section '.got':
+# HEX64: 0x000123a0 c0220100 00000000 00000000 00000000
+# HEX64: 0x000123b0 00000000 00000000 00000000 00000000
+# HEX64: 0x000123c0 00000000 00000000 00000000 00000000
+
+## &.got[2]-. = 0x12240-0x111b0 = 4096*1+144
+# DIS32:      111b0: auipcc ca0, 1
+# DIS32-NEXT:        lc ca0, 144(ca0)
+## &.got[1]-. = 0x12238-0x111b8 = 4096*1+128
+# DIS32:      111b8: auipcc ca0, 1
+# DIS32-NEXT:        lc ca0, 128(ca0)
+
+## &.got[2]-. = 0x123c0-0x112b0 = 4096*1+272
+# DIS64:      112b0: auipcc ca0, 1
+# DIS64-NEXT:        lc ca0, 272(ca0)
+## &.got[1]-. = 0x123b0-0x112b8 = 4096*1+248
+# DIS64:      112b8: auipcc ca0, 1
+# DIS64-NEXT:        lc ca0, 248(ca0)
+
+clgc ca0, a
+clgc ca0, b
+
+.data
+a:
+## An undefined reference of _GLOBAL_OFFSET_TABLE_ causes .got[0] to be
+## allocated to store _DYNAMIC.
+.long _GLOBAL_OFFSET_TABLE_ - .
diff --git a/lld/test/ELF/cheri/riscv/tls.s b/lld/test/ELF/cheri/riscv/tls.s
index b3826b5ac9962..19fb3825d6b56 100644
--- a/lld/test/ELF/cheri/riscv/tls.s
+++ b/lld/test/ELF/cheri/riscv/tls.s
@@ -7,13 +7,13 @@
 # RUN: %riscv32_cheri_purecap_llvm-mc --defsym PIC=0 -filetype=obj %s -o %t.32.o
 # RUN: ld.lld %t.32.o %t1.32.so -o %t.32
 # RUN: llvm-readobj -r %t.32 | FileCheck --check-prefix=RV32-REL %s
-# RUN: llvm-readelf -x .captable %t.32 | FileCheck --check-prefix=RV32-CAP %s
+# RUN: llvm-readelf -x .got %t.32 | FileCheck --check-prefix=RV32-GOT %s
 # RUN: llvm-objdump -d --no-show-raw-insn %t.32 | FileCheck --check-prefix=RV32-DIS %s
 
 # RUN: %riscv32_cheri_purecap_llvm-mc --defsym PIC=1 -filetype=obj %s -o %t.32.pico
 # RUN: ld.lld -shared %t.32.pico %t1.32.so -o %t.32.so
 # RUN: llvm-readobj -r %t.32.so | FileCheck --check-prefix=RV32-SO-REL %s
-# RUN: llvm-readelf -x .captable %t.32.so | FileCheck --check-prefix=RV32-SO-CAP %s
+# RUN: llvm-readelf -x .got %t.32.so | FileCheck --check-prefix=RV32-SO-GOT %s
 # RUN: llvm-objdump -d --no-show-raw-insn %t.32.so | FileCheck --check-prefix=RV32-SO-DIS %s
 
 # RUN: %riscv64_cheri_purecap_llvm-mc -filetype=obj %t.s -o %t1.64.o
@@ -22,132 +22,138 @@
 # RUN: %riscv64_cheri_purecap_llvm-mc --defsym PIC=0 -filetype=obj %s -o %t.64.o
 # RUN: ld.lld %t.64.o %t1.64.so -o %t.64
 # RUN: llvm-readobj -r %t.64 | FileCheck --check-prefix=RV64-REL %s
-# RUN: llvm-readelf -x .captable %t.64 | FileCheck --check-prefix=RV64-CAP %s
+# RUN: llvm-readelf -x .got %t.64 | FileCheck --check-prefix=RV64-GOT %s
 # RUN: llvm-objdump -d --no-show-raw-insn %t.64 | FileCheck --check-prefix=RV64-DIS %s
 
 # RUN: %riscv64_cheri_purecap_llvm-mc --defsym PIC=1 -filetype=obj %s -o %t.64.pico
 # RUN: ld.lld -shared %t.64.pico %t1.64.so -o %t.64.so
 # RUN: llvm-readobj -r %t.64.so | FileCheck --check-prefix=RV64-SO-REL %s
-# RUN: llvm-readelf -x .captable %t.64.so | FileCheck --check-prefix=RV64-SO-CAP %s
+# RUN: llvm-readelf -x .got %t.64.so | FileCheck --check-prefix=RV64-SO-GOT %s
 # RUN: llvm-objdump -d --no-show-raw-insn %t.64.so | FileCheck --check-prefix=RV64-SO-DIS %s
 
 # RV32-REL:      .rela.dyn {
-# RV32-REL-NEXT:   0x121E0 R_RISCV_TLS_DTPMOD32 evar 0x0
-# RV32-REL-NEXT:   0x121E4 R_RISCV_TLS_DTPREL32 evar 0x0
-# RV32-REL-NEXT:   0x121F0 R_RISCV_TLS_TPREL32 evar 0x0
+# RV32-REL-NEXT:   0x12248 R_RISCV_TLS_DTPMOD32 evar 0x0
+# RV32-REL-NEXT:   0x1224C R_RISCV_TLS_DTPREL32 evar 0x0
+# RV32-REL-NEXT:   0x12250 R_RISCV_TLS_TPREL32 evar 0x0
 # RV32-REL-NEXT: }
 
 # RV32-SO-REL:      .rela.dyn {
-# RV32-SO-REL-NEXT:   0x3290 R_RISCV_TLS_DTPMOD32 - 0x0
-# RV32-SO-REL-NEXT:   0x329C R_RISCV_TLS_TPREL32 - 0x4
-# RV32-SO-REL-NEXT:   0x3288 R_RISCV_TLS_DTPMOD32 evar 0x0
-# RV32-SO-REL-NEXT:   0x328C R_RISCV_TLS_DTPREL32 evar 0x0
-# RV32-SO-REL-NEXT:   0x3298 R_RISCV_TLS_TPREL32 evar 0x0
+# RV32-SO-REL-NEXT:   0x2288 R_RISCV_TLS_DTPMOD32 - 0x0
+# RV32-SO-REL-NEXT:   0x2290 R_RISCV_TLS_TPREL32 - 0x4
+# RV32-SO-REL-NEXT:   0x2278 R_RISCV_TLS_DTPMOD32 evar 0x0
+# RV32-SO-REL-NEXT:   0x227C R_RISCV_TLS_DTPREL32 evar 0x0
+# RV32-SO-REL-NEXT:   0x2280 R_RISCV_TLS_TPREL32 evar 0x0
 # RV32-SO-REL-NEXT: }
 
-# RV32-CAP: section '.captable':
-# RV32-CAP-NEXT: 0x000121e0 00000000 00000000 01000000 04000000
-# RV32-CAP-NEXT: 0x000121f0 00000000 04000000
+# RV32-GOT: section '.got':
+# RV32-GOT-NEXT: 0x00012240 e0210100 00000000 00000000 00000000
+# RV32-GOT-NEXT: 0x00012250 00000000 00000000 01000000 04000000
+# RV32-GOT-NEXT: 0x00012260 04000000 00000000
 
-# RV32-SO-CAP: section '.captable':
-# RV32-SO-CAP-NEXT: 0x00003288 00000000 00000000 00000000 04000000
-# RV32-SO-CAP-NEXT: 0x00003298 00000000 00000000
+# RV32-SO-GOT: section '.got':
+# RV32-SO-GOT-NEXT: 0x00002270 10220000 00000000 00000000 00000000
+# RV32-SO-GOT-NEXT: 0x00002280 00000000 00000000 00000000 04000000
+# RV32-SO-GOT-NEXT: 0x00002290 00000000 00000000
 
-# 0x121e0 - 0x111b4 = 0x0102c (GD evar)
+# 0x12248 - 0x111b4 = 0x1094 (GD evar)
 # RV32-DIS:      111b4: auipcc ca0, 1
-# RV32-DIS-NEXT:        cincoffset ca0, ca0, 44
+# RV32-DIS-NEXT:        cincoffset ca0, ca0, 148
 
-# 0x121f0 - 0x111bc = 0x01034 (IE evar)
+# 0x12250 - 0x111bc = 0x1094 (IE evar)
 # RV32-DIS:      111bc: auipcc ca0, 1
-# RV32-DIS-NEXT:        lw a0, 52(ca0)
+# RV32-DIS-NEXT:        lw a0, 148(ca0)
 
-# 0x121e8 - 0x111c4 = 0x01024 (GD lvar)
+# 0x12258 - 0x111c4 = 0x1094 (GD lvar)
 # RV32-DIS:      111c4: auipcc ca0, 1
-# RV32-DIS-NEXT:        cincoffset ca0, ca0, 36
+# RV32-DIS-NEXT:        cincoffset ca0, ca0, 148
 
-# 0x121f4 - 0x111cc = 0x01028 (IE lvar)
+# 0x12260 - 0x111cc = 0x1094 (IE lvar)
 # RV32-DIS:      111cc: auipcc ca0, 1
-# RV32-DIS-NEXT:        lw a0, 40(ca0)
+# RV32-DIS-NEXT:        lw a0, 148(ca0)
 
 # RV32-DIS:      111d4: lui a0, 0
 # RV32-DIS-NEXT:        cincoffset ca0, ctp, a0
 # RV32-DIS-NEXT:        cincoffset ca0, ca0, 4
 
-# 0x3288 - 0x1210 = 0x2078 (GD evar)
-# RV32-SO-DIS:      1210: auipcc ca0, 2
-# RV32-SO-DIS-NEXT:       cincoffset ca0, ca0, 120
+# 0x2278 - 0x11f0 = 0x1088 (GD evar)
+# RV32-SO-DIS:      11f0: auipcc ca0, 1
+# RV32-SO-DIS-NEXT:       cincoffset ca0, ca0, 136
 
-# 0x3298 - 0x1218 = 0x2080 (IE evar)
-# RV32-SO-DIS:      1218: auipcc ca0, 2
-# RV32-SO-DIS-NEXT:       lw a0, 128(ca0)
+# 0x2280 - 0x11f8 = 0x1088 (IE evar)
+# RV32-SO-DIS:      11f8: auipcc ca0, 1
+# RV32-SO-DIS-NEXT:       lw a0, 136(ca0)
 
-# 0x3290 - 0x1220 = 0x2070 (GD lvar)
-# RV32-SO-DIS:      1220: auipcc ca0, 2
-# RV32-SO-DIS-NEXT:       cincoffset ca0, ca0, 112
+# 0x2288 - 0x1200 = 0x1088 (GD lvar)
+# RV32-SO-DIS:      1200: auipcc ca0, 1
+# RV32-SO-DIS-NEXT:       cincoffset ca0, ca0, 136
 
-# 0x329c - 0x1228 = 0x2074 (IE lvar)
-# RV32-SO-DIS:      1228: auipcc ca0, 2
-# RV32-SO-DIS-NEXT:       lw a0, 116(ca0)
+# 0x2290 - 0x1208 = 0x1088 (IE lvar)
+# RV32-SO-DIS:      1208: auipcc ca0, 1
+# RV32-SO-DIS-NEXT:       lw a0, 136(ca0)
 
 # RV64-REL:      .rela.dyn {
-# RV64-REL-NEXT:   0x122F0 R_RISCV_TLS_DTPMOD64 evar 0x0
-# RV64-REL-NEXT:   0x122F8 R_RISCV_TLS_DTPREL64 evar 0x0
-# RV64-REL-NEXT:   0x12310 R_RISCV_TLS_TPREL64 evar 0x0
+# RV64-REL-NEXT:   0x123C0 R_RISCV_TLS_DTPMOD64 evar 0x0
+# RV64-REL-NEXT:   0x123C8 R_RISCV_TLS_DTPREL64 evar 0x0
+# RV64-REL-NEXT:   0x123D0 R_RISCV_TLS_TPREL64 evar 0x0
 # RV64-REL-NEXT: }
 
 # RV64-SO-REL:      .rela.dyn {
-# RV64-SO-REL-NEXT:   0x3430 R_RISCV_TLS_DTPMOD64 - 0x0
-# RV64-SO-REL-NEXT:   0x3448 R_RISCV_TLS_TPREL64 - 0x4
-# RV64-SO-REL-NEXT:   0x3420 R_RISCV_TLS_DTPMOD64 evar 0x0
-# RV64-SO-REL-NEXT:   0x3428 R_RISCV_TLS_DTPREL64 evar 0x0
-# RV64-SO-REL-NEXT:   0x3440 R_RISCV_TLS_TPREL64 evar 0x0
+# RV64-SO-REL-NEXT:   0x2430 R_RISCV_TLS_DTPMOD64 - 0x0
+# RV64-SO-REL-NEXT:   0x2440 R_RISCV_TLS_TPREL64 - 0x4
+# RV64-SO-REL-NEXT:   0x2410 R_RISCV_TLS_DTPMOD64 evar 0x0
+# RV64-SO-REL-NEXT:   0x2418 R_RISCV_TLS_DTPREL64 evar 0x0
+# RV64-SO-REL-NEXT:   0x2420 R_RISCV_TLS_TPREL64 evar 0x0
 # RV64-SO-REL-NEXT: }
 
-# RV64-CAP: section '.captable':
-# RV64-CAP-NEXT: 0x000122f0 00000000 00000000 00000000 00000000
-# RV64-CAP-NEXT: 0x00012300 01000000 00000000 04000000 00000000
-# RV64-CAP-NEXT: 0x00012310 00000000 00000000 04000000 00000000
-
-# RV64-SO-CAP: section '.captable':
-# RV64-SO-CAP-NEXT: 0x00003420 00000000 00000000 00000000 00000000
-# RV64-SO-CAP-NEXT: 0x00003430 00000000 00000000 04000000 00000000
-# RV64-SO-CAP-NEXT: 0x00003440 00000000 00000000 00000000 00000000
-
-# 0x122f0 - 0x112b8 = 0x01038 (GD evar)
+# RV64-GOT: section '.got':
+# RV64-GOT-NEXT: 0x000123b0 e8220100 00000000 00000000 00000000
+# RV64-GOT-NEXT: 0x000123c0 00000000 00000000 00000000 00000000
+# RV64-GOT-NEXT: 0x000123d0 00000000 00000000 00000000 00000000
+# RV64-GOT-NEXT: 0x000123e0 01000000 00000000 04000000 00000000
+# RV64-GOT-NEXT: 0x000123f0 04000000 00000000 00000000 00000000
+
+# RV64-SO-GOT: section '.got':
+# RV64-SO-GOT-NEXT: 0x00002400 38230000 00000000 00000000 00000000
+# RV64-SO-GOT-NEXT: 0x00002410 00000000 00000000 00000000 00000000
+# RV64-SO-GOT-NEXT: 0x00002420 00000000 00000000 00000000 00000000
+# RV64-SO-GOT-NEXT: 0x00002430 00000000 00000000 04000000 00000000
+# RV64-SO-GOT-NEXT: 0x00002440 00000000 00000000 00000000 00000000
+
+# 0x123c0 - 0x112b8 = 0x1108 (GD evar)
 # RV64-DIS:      112b8: auipcc ca0, 1
-# RV64-DIS-NEXT:        cincoffset ca0, ca0, 56
+# RV64-DIS-NEXT:        cincoffset ca0, ca0, 264
 
-# 0x12310 - 0x112c0 = 0x01050 (IE evar)
+# 0x123d0 - 0x112c0 = 0x1110 (IE evar)
 # RV64-DIS:      112c0: auipcc ca0, 1
-# RV64-DIS-NEXT:        ld a0, 80(ca0)
+# RV64-DIS-NEXT:        ld a0, 272(ca0)
 
-# 0x12300 - 0x112c8 = 0x01038 (GD lvar)
+# 0x123e0 - 0x112c8 = 0x1118 (GD lvar)
 # RV64-DIS:      112c8: auipcc ca0, 1
-# RV64-DIS-NEXT:        cincoffset ca0, ca0, 56
+# RV64-DIS-NEXT:        cincoffset ca0, ca0, 280
 
-# 0x12318 - 0x112d0 = 0x01048 (IE lvar)
+# 0x123f0 - 0x112d0 = 0x1120 (IE lvar)
 # RV64-DIS:      112d0: auipcc ca0, 1
-# RV64-DIS-NEXT:        ld a0, 72(ca0)
+# RV64-DIS-NEXT:        ld a0, 288(ca0)
 
 # RV64-DIS:      112d8: lui a0, 0
 # RV64-DIS-NEXT:        cincoffset ca0, ctp, a0
 # RV64-DIS-NEXT:        cincoffset ca0, ca0, 4
 
-# 0x3420 - 0x1350 = 0x20d0 (GD evar)
-# RV64-SO-DIS:      1350: auipcc ca0, 2
-# RV64-SO-DIS-NEXT:       cincoffset ca0, ca0, 208
+# 0x2410 - 0x1318 = 0x10f8 (GD evar)
+# RV64-SO-DIS:      1318: auipcc ca0, 1
+# RV64-SO-DIS-NEXT:       cincoffset ca0, ca0, 248
 
-# 0x3440 - 0x1358 = 0x20e8 (IE evar)
-# RV64-SO-DIS:      1358: auipcc ca0, 2
-# RV64-SO-DIS-NEXT:       ld a0, 232(ca0)
+# 0x2420 - 0x1320 = 0x1100 (IE evar)
+# RV64-SO-DIS:      1320: auipcc ca0, 1
+# RV64-SO-DIS-NEXT:       ld a0, 256(ca0)
 
-# 0x3430 - 0x1360 = 0x20d0 (GD lvar)
-# RV64-SO-DIS:      1360: auipcc ca0, 2
-# RV64-SO-DIS-NEXT:       cincoffset ca0, ca0, 208
+# 0x2430 - 0x1328 = 0x1108 (GD lvar)
+# RV64-SO-DIS:      1328: auipcc ca0, 1
+# RV64-SO-DIS-NEXT:       cincoffset ca0, ca0, 264
 
-# 0x3448 - 0x1368 = 0x20e0 (IE lvar)
-# RV64-SO-DIS:      1368: auipcc ca0, 2
-# RV64-SO-DIS-NEXT:       ld a0, 224(ca0)
+# 0x2440 - 0x1330 = 0x1110 (IE lvar)
+# RV64-SO-DIS:      1330: auipcc ca0, 1
+# RV64-SO-DIS-NEXT:       ld a0, 272(ca0)
 
 .global _start
 _start:
@@ -161,7 +167,7 @@ _start:
 
 .if PIC == 0
 	lui a0, %tprel_hi(lvar)
-	cincoffset ca0, ctp, a0, %tprel_cincoffset(lvar)
+	cincoffset ca0, ctp, a0, %tprel_add(lvar)
 	cincoffset ca0, ca0, %tprel_lo(lvar)
 .endif
 
diff --git a/llvm/include/llvm/BinaryFormat/ELFRelocs/RISCV.def b/llvm/include/llvm/BinaryFormat/ELFRelocs/RISCV.def
index b4e07a447eef7..938582adbb6e1 100644
--- a/llvm/include/llvm/BinaryFormat/ELFRelocs/RISCV.def
+++ b/llvm/include/llvm/BinaryFormat/ELFRelocs/RISCV.def
@@ -58,11 +58,11 @@ ELF_RELOC(R_RISCV_PLT32,             59)
 
 ELF_RELOC(R_RISCV_CHERI_CAPTAB_PCREL_HI20,        192)
 ELF_RELOC(R_RISCV_CHERI_CAPABILITY,               193)
-// 194 reserved for R_RISCV_CHERI_CAPABILITY_CALL
-ELF_RELOC(R_RISCV_CHERI_SIZE,                     195)
-ELF_RELOC(R_RISCV_CHERI_TPREL_CINCOFFSET,         196)
-ELF_RELOC(R_RISCV_CHERI_TLS_IE_CAPTAB_PCREL_HI20, 197)
-ELF_RELOC(R_RISCV_CHERI_TLS_GD_CAPTAB_PCREL_HI20, 198)
-ELF_RELOC(R_RISCV_CHERI_CJAL,                     199)
-ELF_RELOC(R_RISCV_CHERI_CCALL,                    200)
-ELF_RELOC(R_RISCV_CHERI_RVC_CJUMP,                201)
+// 194 reserved
+// 195 reserved
+ELF_RELOC(R_RISCV_CHERI_TPREL_CINCOFFSET,         196) // Deprecated
+ELF_RELOC(R_RISCV_CHERI_TLS_IE_CAPTAB_PCREL_HI20, 197) // Deprecated
+ELF_RELOC(R_RISCV_CHERI_TLS_GD_CAPTAB_PCREL_HI20, 198) // Deprecated
+ELF_RELOC(R_RISCV_CHERI_CJAL,                     199) // Deprecated
+ELF_RELOC(R_RISCV_CHERI_CCALL,                    200) // Deprecated
+ELF_RELOC(R_RISCV_CHERI_RVC_CJUMP,                201) // Deprecated
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 0b24abe99a675..b3e12bbde2731 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -193,8 +193,8 @@ class RISCVAsmParser : public MCTargetAsmParser {
   // Helper to emit pseudo instruction "cllc" used in PCC-relative addressing.
   void emitCapLoadLocalCap(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out);
 
-  // Helper to emit pseudo instruction "clgc" used in captable addressing with
-  // the PC-relative ABI.
+  // Helper to emit pseudo instruction "clgc" used in GOT-indirect addressing
+  // with the PC-relative ABI.
   void emitCapLoadGlobalCap(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out);
 
   // Helper to emit pseudo instruction "cla.tls.ie" used in initial-exec TLS
@@ -229,9 +229,7 @@ class RISCVAsmParser : public MCTargetAsmParser {
   ParseStatus parseZeroOffsetMemOp(OperandVector &Operands);
   ParseStatus parseOperandWithModifier(OperandVector &Operands);
   ParseStatus parseBareSymbol(OperandVector &Operands);
-  template <bool IsCap = false>
   ParseStatus parseCallSymbol(OperandVector &Operands);
-  template <bool IsCap = false>
   ParseStatus parsePseudoJumpSymbol(OperandVector &Operands);
   ParseStatus parseJALOffset(OperandVector &Operands);
   ParseStatus parseVTypeI(OperandVector &Operands);
@@ -569,16 +567,6 @@ struct RISCVOperand final : public MCParsedAsmOperand {
             VK == RISCVMCExpr::VK_RISCV_CALL_PLT);
   }
 
-  bool isCCallSymbol() const {
-    int64_t Imm;
-    RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
-    // Must be of 'immediate' type but not a constant.
-    if (!isImm() || evaluateConstantImm(getImm(), Imm, VK))
-      return false;
-    return RISCVAsmParser::classifySymbolRef(getImm(), VK) &&
-           VK == RISCVMCExpr::VK_RISCV_CCALL;
-  }
-
   bool isPseudoJumpSymbol() const {
     int64_t Imm;
     RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
@@ -589,16 +577,6 @@ struct RISCVOperand final : public MCParsedAsmOperand {
            VK == RISCVMCExpr::VK_RISCV_CALL;
   }
 
-  bool isPseudoCJumpSymbol() const {
-    int64_t Imm;
-    RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
-    // Must be of 'immediate' type but not a constant.
-    if (!isImm() || evaluateConstantImm(getImm(), Imm, VK))
-      return false;
-    return RISCVAsmParser::classifySymbolRef(getImm(), VK) &&
-           VK == RISCVMCExpr::VK_RISCV_CCALL;
-  }
-
   bool isTPRelAddSymbol() const {
     int64_t Imm;
     RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
@@ -609,16 +587,6 @@ struct RISCVOperand final : public MCParsedAsmOperand {
            VK == RISCVMCExpr::VK_RISCV_TPREL_ADD;
   }
 
-  bool isTPRelCIncOffsetSymbol() const {
-    int64_t Imm;
-    RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
-    // Must be of 'immediate' type but not a constant.
-    if (!isImm() || evaluateConstantImm(getImm(), Imm, VK))
-      return false;
-    return RISCVAsmParser::classifySymbolRef(getImm(), VK) &&
-           VK == RISCVMCExpr::VK_RISCV_TPREL_CINCOFFSET;
-  }
-
   bool isCSRSystemRegister() const { return isSystemRegister(); }
 
   bool isVTypeImm(unsigned N) const {
@@ -1008,19 +976,13 @@ struct RISCVOperand final : public MCParsedAsmOperand {
       return IsValid && (VK == RISCVMCExpr::VK_RISCV_PCREL_HI ||
                          VK == RISCVMCExpr::VK_RISCV_GOT_HI ||
                          VK == RISCVMCExpr::VK_RISCV_TLS_GOT_HI ||
-                         VK == RISCVMCExpr::VK_RISCV_TLS_GD_HI ||
-                         VK == RISCVMCExpr::VK_RISCV_CAPTAB_PCREL_HI ||
-                         VK == RISCVMCExpr::VK_RISCV_TLS_IE_CAPTAB_PCREL_HI ||
-                         VK == RISCVMCExpr::VK_RISCV_TLS_GD_CAPTAB_PCREL_HI);
+                         VK == RISCVMCExpr::VK_RISCV_TLS_GD_HI);
     } else {
       return isUInt<20>(Imm) && (VK == RISCVMCExpr::VK_RISCV_None ||
                                  VK == RISCVMCExpr::VK_RISCV_PCREL_HI ||
                                  VK == RISCVMCExpr::VK_RISCV_GOT_HI ||
                                  VK == RISCVMCExpr::VK_RISCV_TLS_GOT_HI ||
-                                 VK == RISCVMCExpr::VK_RISCV_TLS_GD_HI ||
-                                 VK == RISCVMCExpr::VK_RISCV_CAPTAB_PCREL_HI ||
-                                 VK == RISCVMCExpr::VK_RISCV_TLS_IE_CAPTAB_PCREL_HI ||
-                                 VK == RISCVMCExpr::VK_RISCV_TLS_GD_CAPTAB_PCREL_HI);
+                                 VK == RISCVMCExpr::VK_RISCV_TLS_GD_HI);
     }
   }
 
@@ -1665,13 +1627,11 @@ bool RISCVAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
     SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc();
     return Error(ErrorLoc, "operand must be a bare symbol name");
   }
-  case Match_InvalidPseudoJumpSymbol:
-  case Match_InvalidPseudoCJumpSymbol: {
+  case Match_InvalidPseudoJumpSymbol: {
     SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc();
     return Error(ErrorLoc, "operand must be a valid jump target");
   }
-  case Match_InvalidCallSymbol:
-  case Match_InvalidCCallSymbol: {
+  case Match_InvalidCallSymbol: {
     SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc();
     return Error(ErrorLoc, "operand must be a bare symbol name");
   }
@@ -1679,10 +1639,6 @@ bool RISCVAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
     SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc();
     return Error(ErrorLoc, "operand must be a symbol with %tprel_add modifier");
   }
-  case Match_InvalidTPRelCIncOffsetSymbol: {
-    SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc();
-    return Error(ErrorLoc, "operand must be a symbol with %tprel_cincoffset modifier");
-  }
   case Match_InvalidRTZArg: {
     SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc();
     return Error(ErrorLoc, "operand must be 'rtz' floating-point rounding mode");
@@ -2250,7 +2206,6 @@ ParseStatus RISCVAsmParser::parseBareSymbol(OperandVector &Operands) {
   return ParseStatus::Success;
 }
 
-template <bool IsCap>
 ParseStatus RISCVAsmParser::parseCallSymbol(OperandVector &Operands) {
   SMLoc S = getLoc();
   const MCExpr *Res;
@@ -2268,17 +2223,12 @@ ParseStatus RISCVAsmParser::parseCallSymbol(OperandVector &Operands) {
 
   SMLoc E = SMLoc::getFromPointer(S.getPointer() + Identifier.size());
 
-  RISCVMCExpr::VariantKind Kind;
-  if (IsCap) {
-    Kind = RISCVMCExpr::VK_RISCV_CCALL;
-    // Both relocations are the same for RISC-V, so CHERI-RISC-V only provides
-    // a single relocation, but be friendly and permit the redundant suffix.
-    Identifier.consume_back("@plt");
-  } else {
-    Kind = RISCVMCExpr::VK_RISCV_CALL;
-    if (Identifier.consume_back("@plt"))
-      Kind = RISCVMCExpr::VK_RISCV_CALL_PLT;
-  }
+  RISCVMCExpr::VariantKind Kind = RISCVMCExpr::VK_RISCV_CALL;
+  // CHERI-RISC-V always uses the fixed relocation but never prints the suffix.
+  // However, we allow the redundant suffix to be provided anyway.
+  if (Identifier.consume_back("@plt") &&
+      !getSTI().hasFeature(RISCV::FeatureCapMode))
+    Kind = RISCVMCExpr::VK_RISCV_CALL_PLT;
 
   MCSymbol *Sym = getContext().getOrCreateSymbol(Identifier);
   Res = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, getContext());
@@ -2287,7 +2237,6 @@ ParseStatus RISCVAsmParser::parseCallSymbol(OperandVector &Operands) {
   return ParseStatus::Success;
 }
 
-template <bool IsCap>
 ParseStatus RISCVAsmParser::parsePseudoJumpSymbol(OperandVector &Operands) {
   SMLoc S = getLoc();
   SMLoc E;
@@ -2301,9 +2250,7 @@ ParseStatus RISCVAsmParser::parsePseudoJumpSymbol(OperandVector &Operands) {
           MCSymbolRefExpr::VariantKind::VK_PLT)
     return Error(S, "operand must be a valid jump target");
 
-  RISCVMCExpr::VariantKind Kind =
-      IsCap ? RISCVMCExpr::VK_RISCV_CCALL : RISCVMCExpr::VK_RISCV_CALL;
-  Res = RISCVMCExpr::create(Res, Kind, getContext());
+  Res = RISCVMCExpr::create(Res, RISCVMCExpr::VK_RISCV_CALL, getContext());
   Operands.push_back(RISCVOperand::createImm(Res, S, E, isRV64()));
   return ParseStatus::Success;
 }
@@ -3701,17 +3648,16 @@ void RISCVAsmParser::emitCapLoadLocalCap(MCInst &Inst, SMLoc IDLoc,
 void RISCVAsmParser::emitCapLoadGlobalCap(MCInst &Inst, SMLoc IDLoc,
                                           MCStreamer &Out) {
   // The capability load global capability pseudo-instruction "clgc" is used in
-  // captable-indirect addressing of global symbols in the PC-relative ABI:
+  // GOT-indirect addressing of global symbols in the PC-relative ABI:
   //   clgc rdest, symbol
   // expands to
-  //   TmpLabel: AUIPCC cdest, %captab_pcrel_hi(symbol)
+  //   TmpLabel: AUIPCC cdest, %got_pcrel_hi(symbol)
   //             CLC cdest, %pcrel_lo(TmpLabel)(cdest)
   MCOperand DestReg = Inst.getOperand(0);
   const MCExpr *Symbol = Inst.getOperand(1).getExpr();
   unsigned SecondOpcode = isRV64() ? RISCV::CLC_128 : RISCV::CLC_64;
-  emitAuipccInstPair(DestReg, DestReg, Symbol,
-                     RISCVMCExpr::VK_RISCV_CAPTAB_PCREL_HI, SecondOpcode,
-                     IDLoc, Out);
+  emitAuipccInstPair(DestReg, DestReg, Symbol, RISCVMCExpr::VK_RISCV_GOT_HI,
+                     SecondOpcode, IDLoc, Out);
 }
 
 void RISCVAsmParser::emitCapLoadTLSIEAddress(MCInst &Inst, SMLoc IDLoc,
@@ -3720,15 +3666,14 @@ void RISCVAsmParser::emitCapLoadTLSIEAddress(MCInst &Inst, SMLoc IDLoc,
   // in initial-exec TLS model addressing of global symbols:
   //   cla.tls.ie rdest, symbol
   // expands to
-  //   TmpLabel: AUIPCC cdest, %tls_ie_captab_pcrel_hi(symbol)
+  //   TmpLabel: AUIPCC cdest, %tls_ie_pcrel_hi(symbol)
   //             CLx rdest, %pcrel_lo(TmpLabel)(cdest)
   MCOperand DestReg = Inst.getOperand(0);
   MCOperand TmpReg = MCOperand::createReg(convertGPRToGPCR(DestReg.getReg()));
   const MCExpr *Symbol = Inst.getOperand(1).getExpr();
   unsigned SecondOpcode = isRV64() ? RISCV::CLD : RISCV::CLW;
-  emitAuipccInstPair(DestReg, TmpReg, Symbol,
-                     RISCVMCExpr::VK_RISCV_TLS_IE_CAPTAB_PCREL_HI, SecondOpcode,
-                     IDLoc, Out);
+  emitAuipccInstPair(DestReg, TmpReg, Symbol, RISCVMCExpr::VK_RISCV_TLS_GOT_HI,
+                     SecondOpcode, IDLoc, Out);
 }
 
 void RISCVAsmParser::emitCapLoadTLSGDCap(MCInst &Inst, SMLoc IDLoc,
@@ -3741,8 +3686,7 @@ void RISCVAsmParser::emitCapLoadTLSGDCap(MCInst &Inst, SMLoc IDLoc,
   //             CINCOFFSET cdest, cdest, %pcrel_lo(TmpLabel)
   MCOperand DestReg = Inst.getOperand(0);
   const MCExpr *Symbol = Inst.getOperand(1).getExpr();
-  emitAuipccInstPair(DestReg, DestReg, Symbol,
-                     RISCVMCExpr::VK_RISCV_TLS_GD_CAPTAB_PCREL_HI,
+  emitAuipccInstPair(DestReg, DestReg, Symbol, RISCVMCExpr::VK_RISCV_TLS_GD_HI,
                      RISCV::CIncOffsetImm, IDLoc, Out);
 }
 
@@ -3754,7 +3698,7 @@ bool RISCVAsmParser::checkPseudoCIncOffsetTPRel(MCInst &Inst,
   if (Inst.getOperand(1).getReg() != RISCV::C4) {
     SMLoc ErrorLoc = ((RISCVOperand &)*Operands[2]).getStartLoc();
     return Error(ErrorLoc, "the first input operand must be ctp/c4 when using "
-                           "%tprel_cincoffset modifier");
+                           "%tprel_add modifier");
   }
 
   return false;
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
index d7ad91fb54050..4f05937c25393 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
@@ -94,16 +94,6 @@ RISCVAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
 
       {"fixup_riscv_set_6b", 2, 6, 0},
       {"fixup_riscv_sub_6b", 2, 6, 0},
-
-      {"fixup_riscv_captab_pcrel_hi20", 12, 20, MCFixupKindInfo::FKF_IsPCRel},
-      {"fixup_riscv_tprel_cincoffset", 0, 0, 0},
-      {"fixup_riscv_tls_ie_captab_pcrel_hi20", 12, 20,
-       MCFixupKindInfo::FKF_IsPCRel},
-      {"fixup_riscv_tls_gd_captab_pcrel_hi20", 12, 20,
-       MCFixupKindInfo::FKF_IsPCRel},
-      {"fixup_riscv_cjal", 12, 20, MCFixupKindInfo::FKF_IsPCRel},
-      {"fixup_riscv_ccall", 0, 64, MCFixupKindInfo::FKF_IsPCRel},
-      {"fixup_riscv_rvc_cjump", 2, 11, MCFixupKindInfo::FKF_IsPCRel},
   };
   static_assert((std::size(Infos)) == RISCV::NumTargetFixupKinds,
                 "Not all fixup kinds added to Infos array");
@@ -142,9 +132,6 @@ bool RISCVAsmBackend::shouldForceRelocation(const MCAssembler &Asm,
   case RISCV::fixup_riscv_got_hi20:
   case RISCV::fixup_riscv_tls_got_hi20:
   case RISCV::fixup_riscv_tls_gd_hi20:
-  case RISCV::fixup_riscv_captab_pcrel_hi20:
-  case RISCV::fixup_riscv_tls_ie_captab_pcrel_hi20:
-  case RISCV::fixup_riscv_tls_gd_captab_pcrel_hi20:
     return true;
   }
 
@@ -181,7 +168,6 @@ bool RISCVAsmBackend::fixupNeedsRelaxationAdvanced(const MCFixup &Fixup,
     // in the range [-256, 254].
     return Offset > 254 || Offset < -256;
   case RISCV::fixup_riscv_rvc_jump:
-  case RISCV::fixup_riscv_rvc_cjump:
     // For compressed jump instructions the immediate must be
     // in the range [-2048, 2046].
     return Offset > 2046 || Offset < -2048;
@@ -419,11 +405,8 @@ static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
   case RISCV::fixup_riscv_got_hi20:
   case RISCV::fixup_riscv_tls_got_hi20:
   case RISCV::fixup_riscv_tls_gd_hi20:
-  case RISCV::fixup_riscv_captab_pcrel_hi20:
   case FK_Cap_8:
   case FK_Cap_16:
-  case RISCV::fixup_riscv_tls_ie_captab_pcrel_hi20:
-  case RISCV::fixup_riscv_tls_gd_captab_pcrel_hi20:
     llvm_unreachable("Relocation should be unconditionally forced\n");
   case RISCV::fixup_riscv_set_8:
   case RISCV::fixup_riscv_add_8:
@@ -463,8 +446,7 @@ static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
   case RISCV::fixup_riscv_tprel_hi20:
     // Add 1 if bit 11 is 1, to compensate for low 12 bits being negative.
     return ((Value + 0x800) >> 12) & 0xfffff;
-  case RISCV::fixup_riscv_jal:
-  case RISCV::fixup_riscv_cjal: {
+  case RISCV::fixup_riscv_jal: {
     if (!isInt<21>(Value))
       Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
     if (Value & 0x1)
@@ -500,8 +482,7 @@ static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
     return Value;
   }
   case RISCV::fixup_riscv_call:
-  case RISCV::fixup_riscv_call_plt:
-  case RISCV::fixup_riscv_ccall: {
+  case RISCV::fixup_riscv_call_plt: {
     // Jalr will add UpperImm with the sign-extended 12-bit LowerImm,
     // we need to add 0x800ULL before extract upper bits to reflect the
     // effect of the sign extension.
@@ -509,8 +490,7 @@ static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
     uint64_t LowerImm = Value & 0xfffULL;
     return UpperImm | ((LowerImm << 20) << 32);
   }
-  case RISCV::fixup_riscv_rvc_jump:
-  case RISCV::fixup_riscv_rvc_cjump: {
+  case RISCV::fixup_riscv_rvc_jump: {
     // Need to produce offset[11|4|9:8|10|6|7|3:1|5] from the 11-bit Value.
     unsigned Bit11  = (Value >> 11) & 0x1;
     unsigned Bit4   = (Value >> 4) & 0x1;
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
index 53da43e7ee4c1..9d2a8ff5a5f3b 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
@@ -227,11 +227,6 @@ enum {
   MO_TPREL_ADD = 10,
   MO_TLS_GOT_HI = 11,
   MO_TLS_GD_HI = 12,
-  MO_CAPTAB_PCREL_HI = 13,
-  MO_TPREL_CINCOFFSET = 14,
-  MO_TLS_IE_CAPTAB_PCREL_HI = 15,
-  MO_TLS_GD_CAPTAB_PCREL_HI = 16,
-  MO_CCALL = 17,
 
   // Used to differentiate between target-specific "direct" flags and "bitmask"
   // flags. A machine operand can only have one "direct" flag, but can have
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp
index 78c8114d01eef..94332f7ff660b 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp
@@ -89,18 +89,6 @@ unsigned RISCVELFObjectWriter::getRelocType(MCContext &Ctx,
       return ELF::R_RISCV_CALL_PLT;
     case RISCV::fixup_riscv_call_plt:
       return ELF::R_RISCV_CALL_PLT;
-    case RISCV::fixup_riscv_captab_pcrel_hi20:
-      return ELF::R_RISCV_CHERI_CAPTAB_PCREL_HI20;
-    case RISCV::fixup_riscv_tls_ie_captab_pcrel_hi20:
-      return ELF::R_RISCV_CHERI_TLS_IE_CAPTAB_PCREL_HI20;
-    case RISCV::fixup_riscv_tls_gd_captab_pcrel_hi20:
-      return ELF::R_RISCV_CHERI_TLS_GD_CAPTAB_PCREL_HI20;
-    case RISCV::fixup_riscv_cjal:
-      return ELF::R_RISCV_CHERI_CJAL;
-    case RISCV::fixup_riscv_ccall:
-      return ELF::R_RISCV_CHERI_CCALL;
-    case RISCV::fixup_riscv_rvc_cjump:
-      return ELF::R_RISCV_CHERI_RVC_CJUMP;
     case RISCV::fixup_riscv_add_8:
       return ELF::R_RISCV_ADD8;
     case RISCV::fixup_riscv_sub_8:
@@ -169,8 +157,6 @@ unsigned RISCVELFObjectWriter::getRelocType(MCContext &Ctx,
       return ELF::R_RISCV_NONE;
     }
     return ELF::R_RISCV_CHERI_CAPABILITY;
-  case RISCV::fixup_riscv_tprel_cincoffset:
-    return ELF::R_RISCV_CHERI_TPREL_CINCOFFSET;
   case RISCV::fixup_riscv_set_6b:
     return ELF::R_RISCV_SET6;
   case RISCV::fixup_riscv_sub_6b:
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVFixupKinds.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVFixupKinds.h
index 89b26461090da..5727aab3cd4ca 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVFixupKinds.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVFixupKinds.h
@@ -107,29 +107,6 @@ enum Fixups {
   // DWARF CFA.
   fixup_riscv_sub_6b,
 
-  // fixup_riscv_captab_pcrel_hi20 - 20-bit fixup corresponding to
-  // captab_pcrel_hi(foo) for instructions like auipcc
-  fixup_riscv_captab_pcrel_hi20,
-  // fixup_riscv_tprel_cincoffset - A fixup corresponding to
-  // %tprel_cincoffset(foo) for the cincoffset_tls instruction. Used to provide
-  // a hint to the linker.
-  fixup_riscv_tprel_cincoffset,
-  // fixup_riscv_tls_ie_captab_pcrel_hi20 - 20-bit fixup corresponding to
-  // tls_ie_captab_pcrel_hi(foo) for instructions like auipcc
-  fixup_riscv_tls_ie_captab_pcrel_hi20,
-  // fixup_riscv_tls_gd_captab_pcrel_hi20 - 20-bit fixup corresponding to
-  // tls_gd_captab_pcrel_hi(foo) for instructions like auipcc
-  fixup_riscv_tls_gd_captab_pcrel_hi20,
-  // fixup_riscv_cjal - 20-bit fixup for symbol references in the cjal
-  // instruction
-  fixup_riscv_cjal,
-  // fixup_riscv_call - A fixup representing a ccall attached to the auipcc
-  // instruction in a pair composed of adjacent auipcc+cjalr instructions.
-  fixup_riscv_ccall,
-  // fixup_riscv_rvc_cjump - 11-bit fixup for symbol references in the
-  // compressed capability jump instruction
-  fixup_riscv_rvc_cjump,
-
   // Used as a sentinel, must be the last
   fixup_riscv_invalid,
   NumTargetFixupKinds = fixup_riscv_invalid - FirstTargetFixupKind
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
index b1b495c79c37e..6e735ea5c25c2 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
@@ -240,14 +240,14 @@ void RISCVMCCodeEmitter::expandCIncOffsetTPRel(
          "Expected expression as third input to CTP-relative cincoffset");
 
   const RISCVMCExpr *Expr = dyn_cast<RISCVMCExpr>(SrcSymbol.getExpr());
-  assert(Expr && Expr->getKind() == RISCVMCExpr::VK_RISCV_TPREL_CINCOFFSET &&
-         "Expected tprel_cincoffset relocation on CTP-relative symbol");
+  assert(Expr && Expr->getKind() == RISCVMCExpr::VK_RISCV_TPREL_ADD &&
+         "Expected tprel_add relocation on CTP-relative symbol");
 
-  // Emit the correct tprel_cincoffset relocation for the symbol.
+  // Emit the correct tprel_add relocation for the symbol.
   Fixups.push_back(MCFixup::create(
-      0, Expr, MCFixupKind(RISCV::fixup_riscv_tprel_cincoffset), MI.getLoc()));
+      0, Expr, MCFixupKind(RISCV::fixup_riscv_tprel_add), MI.getLoc()));
 
-  // Emit fixup_riscv_relax for tprel_cincoffset where the relax feature is enabled.
+  // Emit fixup_riscv_relax for tprel_add where the relax feature is enabled.
   if (STI.getFeatureBits()[RISCV::FeatureRelax]) {
     const MCConstantExpr *Dummy = MCConstantExpr::create(0, Ctx);
     Fixups.push_back(MCFixup::create(
@@ -517,44 +517,27 @@ unsigned RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo,
       FixupKind = RISCV::fixup_riscv_tls_gd_hi20;
       break;
     case RISCVMCExpr::VK_RISCV_CALL:
-      FixupKind = RISCV::fixup_riscv_call;
+      // CHERI-RISC-V always uses R_RISCV_CALL_PLT but always uses
+      // VK_RISCV_CALL so as to not print the redundant suffix.
+      if (STI.hasFeature(RISCV::FeatureCapMode))
+        FixupKind = RISCV::fixup_riscv_call_plt;
+      else
+        FixupKind = RISCV::fixup_riscv_call;
       RelaxCandidate = true;
       break;
     case RISCVMCExpr::VK_RISCV_CALL_PLT:
       FixupKind = RISCV::fixup_riscv_call_plt;
       RelaxCandidate = true;
       break;
-    case RISCVMCExpr::VK_RISCV_CAPTAB_PCREL_HI:
-      FixupKind = RISCV::fixup_riscv_captab_pcrel_hi20;
-      break;
-    case RISCVMCExpr::VK_RISCV_TPREL_CINCOFFSET:
-      // See VK_RISCV_TPREL_ADD.
-      llvm_unreachable(
-          "VK_RISCV_TPREL_CINCOFFSET should not represent an instruction operand");
-    case RISCVMCExpr::VK_RISCV_TLS_IE_CAPTAB_PCREL_HI:
-      FixupKind = RISCV::fixup_riscv_tls_ie_captab_pcrel_hi20;
-      break;
-    case RISCVMCExpr::VK_RISCV_TLS_GD_CAPTAB_PCREL_HI:
-      FixupKind = RISCV::fixup_riscv_tls_gd_captab_pcrel_hi20;
-      break;
-    case RISCVMCExpr::VK_RISCV_CCALL:
-      FixupKind = RISCV::fixup_riscv_ccall;
-      RelaxCandidate = true;
-      break;
     }
   } else if (Kind == MCExpr::SymbolRef &&
              cast<MCSymbolRefExpr>(Expr)->getKind() == MCSymbolRefExpr::VK_None) {
     if (MIFrm == RISCVII::InstFormatJ) {
       FixupKind = RISCV::fixup_riscv_jal;
-    } else if (Desc.getOpcode() == RISCV::CJAL) {
-      FixupKind = RISCV::fixup_riscv_cjal;
     } else if (MIFrm == RISCVII::InstFormatB) {
       FixupKind = RISCV::fixup_riscv_branch;
     } else if (MIFrm == RISCVII::InstFormatCJ) {
-      if (Desc.getOpcode() == RISCV::C_CJAL)
-        FixupKind = RISCV::fixup_riscv_rvc_cjump;
-      else
-        FixupKind = RISCV::fixup_riscv_rvc_jump;
+      FixupKind = RISCV::fixup_riscv_rvc_jump;
     } else if (MIFrm == RISCVII::InstFormatCB) {
       FixupKind = RISCV::fixup_riscv_rvc_branch;
     } else if (MIFrm == RISCVII::InstFormatI) {
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp
index 8ff9122ba02ce..d67351102bc1c 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp
@@ -36,7 +36,7 @@ const RISCVMCExpr *RISCVMCExpr::create(const MCExpr *Expr, VariantKind Kind,
 void RISCVMCExpr::printImpl(raw_ostream &OS, const MCAsmInfo *MAI) const {
   VariantKind Kind = getKind();
   bool HasVariant = ((Kind != VK_RISCV_None) && (Kind != VK_RISCV_CALL) &&
-                     (Kind != VK_RISCV_CALL_PLT) && (Kind != VK_RISCV_CCALL));
+                     (Kind != VK_RISCV_CALL_PLT));
 
   if (HasVariant)
     OS << '%' << getVariantKindName(getKind()) << '(';
@@ -81,9 +81,6 @@ const MCFixup *RISCVMCExpr::getPCRelHiFixup(const MCFragment **DFOut) const {
     case RISCV::fixup_riscv_tls_got_hi20:
     case RISCV::fixup_riscv_tls_gd_hi20:
     case RISCV::fixup_riscv_pcrel_hi20:
-    case RISCV::fixup_riscv_captab_pcrel_hi20:
-    case RISCV::fixup_riscv_tls_ie_captab_pcrel_hi20:
-    case RISCV::fixup_riscv_tls_gd_captab_pcrel_hi20:
       if (DFOut)
         *DFOut = DF;
       return &F;
@@ -124,10 +121,6 @@ RISCVMCExpr::VariantKind RISCVMCExpr::getVariantKindForName(StringRef name) {
       .Case("tprel_add", VK_RISCV_TPREL_ADD)
       .Case("tls_ie_pcrel_hi", VK_RISCV_TLS_GOT_HI)
       .Case("tls_gd_pcrel_hi", VK_RISCV_TLS_GD_HI)
-      .Case("captab_pcrel_hi", VK_RISCV_CAPTAB_PCREL_HI)
-      .Case("tprel_cincoffset", VK_RISCV_TPREL_CINCOFFSET)
-      .Case("tls_ie_captab_pcrel_hi", VK_RISCV_TLS_IE_CAPTAB_PCREL_HI)
-      .Case("tls_gd_captab_pcrel_hi", VK_RISCV_TLS_GD_CAPTAB_PCREL_HI)
       .Default(VK_RISCV_Invalid);
 }
 
@@ -156,20 +149,10 @@ StringRef RISCVMCExpr::getVariantKindName(VariantKind Kind) {
     return "tls_ie_pcrel_hi";
   case VK_RISCV_TLS_GD_HI:
     return "tls_gd_pcrel_hi";
-  case VK_RISCV_CAPTAB_PCREL_HI:
-    return "captab_pcrel_hi";
-  case VK_RISCV_TPREL_CINCOFFSET:
-    return "tprel_cincoffset";
-  case VK_RISCV_TLS_IE_CAPTAB_PCREL_HI:
-    return "tls_ie_captab_pcrel_hi";
-  case VK_RISCV_TLS_GD_CAPTAB_PCREL_HI:
-    return "tls_gd_captab_pcrel_hi";
   case VK_RISCV_CALL:
     return "call";
   case VK_RISCV_CALL_PLT:
     return "call_plt";
-  case VK_RISCV_CCALL:
-    return "ccall";
   case VK_RISCV_32_PCREL:
     return "32_pcrel";
   }
@@ -212,8 +195,6 @@ void RISCVMCExpr::fixELFSymbolsInTLSFixups(MCAssembler &Asm) const {
   case VK_RISCV_TPREL_HI:
   case VK_RISCV_TLS_GOT_HI:
   case VK_RISCV_TLS_GD_HI:
-  case VK_RISCV_TLS_IE_CAPTAB_PCREL_HI:
-  case VK_RISCV_TLS_GD_CAPTAB_PCREL_HI:
     break;
   }
 
@@ -227,12 +208,7 @@ bool RISCVMCExpr::evaluateAsConstant(int64_t &Res) const {
       Kind == VK_RISCV_GOT_HI || Kind == VK_RISCV_TPREL_HI ||
       Kind == VK_RISCV_TPREL_LO || Kind == VK_RISCV_TPREL_ADD ||
       Kind == VK_RISCV_TLS_GOT_HI || Kind == VK_RISCV_TLS_GD_HI ||
-      Kind == VK_RISCV_CALL || Kind == VK_RISCV_CALL_PLT ||
-      Kind == VK_RISCV_CAPTAB_PCREL_HI ||
-      Kind == VK_RISCV_TPREL_CINCOFFSET ||
-      Kind == VK_RISCV_TLS_IE_CAPTAB_PCREL_HI ||
-      Kind == VK_RISCV_TLS_GD_CAPTAB_PCREL_HI ||
-      Kind == VK_RISCV_CCALL)
+      Kind == VK_RISCV_CALL || Kind == VK_RISCV_CALL_PLT)
     return false;
 
   if (!getSubExpr()->evaluateAsRelocatable(Value, nullptr, nullptr))
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.h
index 45ad339c2cb0c..ee83bf0208ef4 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.h
@@ -37,11 +37,6 @@ class RISCVMCExpr : public MCTargetExpr {
     VK_RISCV_CALL,
     VK_RISCV_CALL_PLT,
     VK_RISCV_32_PCREL,
-    VK_RISCV_CAPTAB_PCREL_HI,
-    VK_RISCV_TPREL_CINCOFFSET,
-    VK_RISCV_TLS_IE_CAPTAB_PCREL_HI,
-    VK_RISCV_TLS_GD_CAPTAB_PCREL_HI,
-    VK_RISCV_CCALL,
     VK_RISCV_Invalid // Must be the last item
   };
 
diff --git a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
index 2311de45bb24e..b787ddf7ca0b1 100644
--- a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
+++ b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
@@ -659,21 +659,6 @@ static MCOperand lowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym,
   case RISCVII::MO_TLS_GD_HI:
     Kind = RISCVMCExpr::VK_RISCV_TLS_GD_HI;
     break;
-  case RISCVII::MO_CAPTAB_PCREL_HI:
-    Kind = RISCVMCExpr::VK_RISCV_CAPTAB_PCREL_HI;
-    break;
-  case RISCVII::MO_TPREL_CINCOFFSET:
-    Kind = RISCVMCExpr::VK_RISCV_TPREL_CINCOFFSET;
-    break;
-  case RISCVII::MO_TLS_IE_CAPTAB_PCREL_HI:
-    Kind = RISCVMCExpr::VK_RISCV_TLS_IE_CAPTAB_PCREL_HI;
-    break;
-  case RISCVII::MO_TLS_GD_CAPTAB_PCREL_HI:
-    Kind = RISCVMCExpr::VK_RISCV_TLS_GD_CAPTAB_PCREL_HI;
-    break;
-  case RISCVII::MO_CCALL:
-    Kind = RISCVMCExpr::VK_RISCV_CCALL;
-    break;
   }
 
   const MCExpr *ME =
diff --git a/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp b/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
index 49c86aa211cf6..56716e6e6d5d0 100644
--- a/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
@@ -239,7 +239,7 @@ bool RISCVExpandPseudo::expandCapLoadGlobalCap(
 
   const auto &STI = MF->getSubtarget<RISCVSubtarget>();
   unsigned SecondOpcode = STI.is64Bit() ? RISCV::CLC_128 : RISCV::CLC_64;
-  return expandAuipccInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_CAPTAB_PCREL_HI,
+  return expandAuipccInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_GOT_HI,
                               SecondOpcode);
 }
 
@@ -250,16 +250,14 @@ bool RISCVExpandPseudo::expandCapLoadTLSIEAddress(
 
   const auto &STI = MF->getSubtarget<RISCVSubtarget>();
   unsigned SecondOpcode = STI.is64Bit() ? RISCV::CLD : RISCV::CLW;
-  return expandAuipccInstPair(MBB, MBBI, NextMBBI,
-                              RISCVII::MO_TLS_IE_CAPTAB_PCREL_HI,
+  return expandAuipccInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_TLS_GOT_HI,
                               SecondOpcode, true);
 }
 
 bool RISCVExpandPseudo::expandCapLoadTLSGDCap(
     MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
     MachineBasicBlock::iterator &NextMBBI) {
-  return expandAuipccInstPair(MBB, MBBI, NextMBBI,
-                              RISCVII::MO_TLS_GD_CAPTAB_PCREL_HI,
+  return expandAuipccInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_TLS_GD_HI,
                               RISCV::CIncOffsetImm);
 }
 
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 25e7330083f82..536034ee7ccbb 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -5775,9 +5775,9 @@ SDValue RISCVTargetLowering::getAddr(NodeTy *N, EVT Ty, SelectionDAG &DAG,
       // for read-only constants (e.g. floating-point constant-pools).
       return DAG.getNode(RISCVISD::CLLC, DL, Ty, Addr);
     }
-    // Generate a sequence to load a capability from the captable. This
-    // generates the pattern (PseudoCLGC sym), which expands to
-    // (clc (auipcc %captab_pcrel_hi(sym)) %pcrel_lo(auipc)).
+    // Generate a sequence to load a capability from the GOT. This generates
+    // the pattern (PseudoCLGC sym), which expands to
+    // (clc (auipcc %got_pcrel_hi(sym)) %pcrel_lo(auipc)).
     MachineFunction &MF = DAG.getMachineFunction();
     MachineMemOperand *MemOp = MF.getMachineMemOperand(
         MachinePointerInfo::getGOT(MF),
@@ -5862,14 +5862,14 @@ SDValue RISCVTargetLowering::lowerGlobalAddress(SDValue Op,
   GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op);
   assert(N->getOffset() == 0 && "unexpected offset in global node");
 
-  // External variables always have to be loaded from the captable to get bounds
-  // and to allow for them to be provided by another DSO without requiring copy
+  // External variables always have to be loaded from the GOT to get bounds and
+  // to allow for them to be provided by another DSO without requiring copy
   // relocations.
   // Read-only accesses in the same DSO *could* theoretically use pc-relative
   // addressing, but that would mean we get a capability bounded to the $pcc
   // bounds and therefore would not be checked when we pass the reference to
-  // another function. Therefore, we always load from the captable for all
-  // global variables.
+  // another function. Therefore, we always load from the GOT for all global
+  // variables.
   const GlobalValue *GV = N->getGlobal();
   return getAddr(N, Ty, DAG, GV->isDSOLocal(), /*CanDeriveFromPcc=*/false,
                  GV->hasExternalWeakLinkage());
@@ -5908,10 +5908,10 @@ SDValue RISCVTargetLowering::getStaticTLSAddr(GlobalAddressSDNode *N,
 
   if (RISCVABI::isCheriPureCapABI(Subtarget.getTargetABI())) {
     if (NotLocal) {
-      // Use PC-relative addressing to access the captable for this TLS symbol,
-      // then load the address from the captable and add the thread pointer.
-      // This generates the pattern (PseudoCLA_TLS_IE sym), which expands to
-      // (cld (auipcc %tls_ie_captab_pcrel_hi(sym)) %pcrel_lo(auipc)).
+      // Use PC-relative addressing to access the GOT for this TLS symbol, then
+      // load the address from the GOT and add the thread pointer. This
+      // generates the pattern (PseudoCLA_TLS_IE sym), which expands to
+      // (cld (auipcc %tls_ie_pcrel_hi(sym)) %pcrel_lo(auipc)).
       SDValue Addr = DAG.getTargetGlobalAddress(GV, DL, Ty, 0, 0);
       MachineFunction &MF = DAG.getMachineFunction();
       MachineMemOperand *MemOp = MF.getMachineMemOperand(
@@ -5932,12 +5932,12 @@ SDValue RISCVTargetLowering::getStaticTLSAddr(GlobalAddressSDNode *N,
     // pointer, with the appropriate adjustment for the thread pointer offset.
     // This generates the pattern
     // (cincoffset (cincoffset_tprel (lui %tprel_hi(sym))
-    //                               ctp %tprel_cincoffset(sym))
+    //                               ctp %tprel_add(sym))
     //             %tprel_lo(sym))
     SDValue AddrHi =
         DAG.getTargetGlobalAddress(GV, DL, XLenVT, 0, RISCVII::MO_TPREL_HI);
     SDValue AddrCIncOffset =
-        DAG.getTargetGlobalAddress(GV, DL, Ty, 0, RISCVII::MO_TPREL_CINCOFFSET);
+        DAG.getTargetGlobalAddress(GV, DL, Ty, 0, RISCVII::MO_TPREL_ADD);
     SDValue AddrLo =
         DAG.getTargetGlobalAddress(GV, DL, XLenVT, 0, RISCVII::MO_TPREL_LO);
 
@@ -6006,7 +6006,7 @@ SDValue RISCVTargetLowering::getDynamicTLSAddr(GlobalAddressSDNode *N,
   //
   // For pure capability TLS, this generates the pattern (PseudoCLC_TLS_GD sym),
   // which expands to
-  // (cincoffset (auipcc %tls_gd_captab_pcrel_hi(sym)) %pcrel_lo(auipc)).
+  // (cincoffset (auipcc %tls_gd_pcrel_hi(sym)) %pcrel_lo(auipc)).
   unsigned Opcode = RISCVABI::isCheriPureCapABI(Subtarget.getTargetABI())
                         ? RISCVISD::CLC_TLS_GD
                         : RISCVISD::LA_TLS_GD;
@@ -16297,14 +16297,11 @@ SDValue RISCVTargetLowering::LowerCall(CallLoweringInfo &CLI,
   if (GlobalAddressSDNode *S = dyn_cast<GlobalAddressSDNode>(Callee)) {
     const GlobalValue *GV = S->getGlobal();
 
-    unsigned OpFlags;
-    if (RISCVABI::isCheriPureCapABI(Subtarget.getTargetABI())) {
-      OpFlags = RISCVII::MO_CCALL;
-    } else {
-      OpFlags = RISCVII::MO_CALL;
-      if (!getTargetMachine().shouldAssumeDSOLocal(*GV->getParent(), GV))
-        OpFlags = RISCVII::MO_PLT;
-    }
+    unsigned OpFlags = RISCVII::MO_CALL;
+    // See RISCVMCCodeEmitter::getImmOpValue
+    if (!RISCVABI::isCheriPureCapABI(Subtarget.getTargetABI()) &&
+        !getTargetMachine().shouldAssumeDSOLocal(*GV->getParent(), GV))
+      OpFlags = RISCVII::MO_PLT;
 
     if (RISCVABI::isCheriPureCapABI(Subtarget.getTargetABI()) &&
         UseLegacyIndirectPurecapCalls)
@@ -16313,16 +16310,13 @@ SDValue RISCVTargetLowering::LowerCall(CallLoweringInfo &CLI,
     else
       Callee = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, OpFlags);
   } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
-    unsigned OpFlags;
+    unsigned OpFlags = RISCVII::MO_CALL;
 
-    if (RISCVABI::isCheriPureCapABI(Subtarget.getTargetABI())) {
-      OpFlags = RISCVII::MO_CCALL;
-    } else {
-      OpFlags = RISCVII::MO_CALL;
-      if (!getTargetMachine().shouldAssumeDSOLocal(*MF.getFunction().getParent(),
-                                                   nullptr))
-        OpFlags = RISCVII::MO_PLT;
-    }
+    // See RISCVMCCodeEmitter::getImmOpValue
+    if (!RISCVABI::isCheriPureCapABI(Subtarget.getTargetABI()) &&
+        !getTargetMachine().shouldAssumeDSOLocal(*MF.getFunction().getParent(),
+                                                 nullptr))
+      OpFlags = RISCVII::MO_PLT;
 
     // Legacy behaviour always used indirect calls even for static functions.
     // This could be optimised, but shouldAssumeDSOLocal is too weak, since
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index aad461ca640e1..fa1eb765b919f 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -2172,12 +2172,7 @@ RISCVInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
       {MO_TPREL_HI, "riscv-tprel-hi"},
       {MO_TPREL_ADD, "riscv-tprel-add"},
       {MO_TLS_GOT_HI, "riscv-tls-got-hi"},
-      {MO_TLS_GD_HI, "riscv-tls-gd-hi"},
-      {MO_CAPTAB_PCREL_HI, "riscv-captab-pcrel-hi"},
-      {MO_TPREL_CINCOFFSET, "riscv-tprel-cincoffset"},
-      {MO_TLS_IE_CAPTAB_PCREL_HI, "riscv-tls-ie-captab-pcrel-hi"},
-      {MO_TLS_GD_CAPTAB_PCREL_HI, "riscv-tls-gd-captab-pcrel-hi"},
-      {MO_CCALL, "riscv-ccall"}};
+      {MO_TLS_GD_HI, "riscv-tls-gd-hi"}};
   return ArrayRef(TargetFlags);
 }
 
@@ -2345,12 +2340,11 @@ MachineBasicBlock::iterator RISCVInstrInfo::insertOutlinedCall(
   bool IsPurecap = RISCVABI::isCheriPureCapABI(
       MF.getSubtarget<RISCVSubtarget>().getTargetABI());
   It = MBB.insert(
-      It,
-      BuildMI(MF, DebugLoc(),
-              get(IsPurecap ? RISCV::PseudoCCALLReg : RISCV::PseudoCALLReg),
-              IsPurecap ? RISCV::C5 : RISCV::X5)
-          .addGlobalAddress(M.getNamedValue(MF.getName()), 0,
-                            IsPurecap ? RISCVII::MO_CCALL : RISCVII::MO_CALL));
+      It, BuildMI(MF, DebugLoc(),
+                  get(IsPurecap ? RISCV::PseudoCCALLReg : RISCV::PseudoCALLReg),
+                  IsPurecap ? RISCV::C5 : RISCV::X5)
+              .addGlobalAddress(M.getNamedValue(MF.getName()), 0,
+                                RISCVII::MO_CALL));
   return It;
 }
 
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXCheri.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXCheri.td
index c0bfd805f2ee4..8b0bfd05d2778 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXCheri.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXCheri.td
@@ -47,38 +47,12 @@ def riscv_clc_tls_gd      : SDNode<"RISCVISD::CLC_TLS_GD", SDT_RISCVSymLoad>;
 // Operand and SDNode transformation definitions.
 //===----------------------------------------------------------------------===//
 
-def CCallSymbol : AsmOperandClass {
-  let Name = "CCallSymbol";
-  let RenderMethod = "addImmOperands";
-  let DiagnosticType = "InvalidCCallSymbol";
-  let ParserMethod = "parseCallSymbol<true>";
-}
-
 def cap_call_symbol : Operand<CLenVT> {
-  let ParserMatchClass = CCallSymbol;
-}
-
-def PseudoCJumpSymbol : AsmOperandClass {
-  let Name = "PseudoCJumpSymbol";
-  let RenderMethod = "addImmOperands";
-  let DiagnosticType = "InvalidPseudoCJumpSymbol";
-  let ParserMethod = "parsePseudoJumpSymbol<true>";
+  let ParserMatchClass = CallSymbol;
 }
 
 def pseudo_cap_jump_symbol : Operand<CLenVT> {
-  let ParserMatchClass = PseudoCJumpSymbol;
-}
-
-def TPRelCIncOffsetSymbol : AsmOperandClass {
-  let Name = "TPRelCIncOffsetSymbol";
-  let RenderMethod = "addImmOperands";
-  let DiagnosticType = "InvalidTPRelCIncOffsetSymbol";
-  let ParserMethod = "parseOperandWithModifier";
-}
-
-// A bare symbol with the %tprel_add variant.
-def tprel_cincoffset_symbol : Operand<XLenVT> {
-  let ParserMatchClass = TPRelCIncOffsetSymbol;
+  let ParserMatchClass = PseudoJumpSymbol;
 }
 
 def CheriZeroOffsetMemOpOperand : AsmOperandClass {
@@ -1240,7 +1214,7 @@ def : Pat<(riscv_clc_tls_gd tglobaltlsaddr:$in),
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCodeGenOnly = 0 in
 def PseudoCIncOffsetTPRel : Pseudo<(outs GPCR:$rd),
                                    (ins GPCR:$rs1, GPR:$rs2,
-                                        tprel_cincoffset_symbol:$src), [],
+                                        tprel_add_symbol:$src), [],
                                    "cincoffset", "$rd, $rs1, $rs2, $src">;
 }
 
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/bounded-allocas-lifetimes.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/bounded-allocas-lifetimes.ll
index 9edc4d128277d..4e1c300a7b8ee 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/bounded-allocas-lifetimes.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/bounded-allocas-lifetimes.ll
@@ -17,7 +17,7 @@ define void @static_alloca() {
   ; CHECK-NEXT:   LIFETIME_START %stack.0
   ; CHECK-NEXT:   ADJCALLSTACKDOWNCAP 0, 0, implicit-def dead $c2, implicit $c2
   ; CHECK-NEXT:   $c10 = COPY [[CSetBoundsImm]]
-  ; CHECK-NEXT:   PseudoCCALL target-flags(riscv-ccall) @use, csr_il32pc64f_l64pc128f, implicit-def dead $c1, implicit $c10, implicit-def $c2
+  ; CHECK-NEXT:   PseudoCCALL target-flags(riscv-call) @use, csr_il32pc64f_l64pc128f, implicit-def dead $c1, implicit $c10, implicit-def $c2
   ; CHECK-NEXT:   ADJCALLSTACKUPCAP 0, 0, implicit-def dead $c2, implicit $c2
   ; CHECK-NEXT:   LIFETIME_END %stack.0
   ; CHECK-NEXT:   PseudoCRET
@@ -54,7 +54,7 @@ define void @dynamic_alloca(i64 zeroext %n) {
   ; CHECK-NEXT:   [[CSetBounds1:%[0-9]+]]:gpcr = CSetBounds killed [[CSetBounds]], [[SLLI]]
   ; CHECK-NEXT:   ADJCALLSTACKDOWNCAP 0, 0, implicit-def dead $c2, implicit $c2
   ; CHECK-NEXT:   $c10 = COPY [[CSetBounds1]]
-  ; CHECK-NEXT:   PseudoCCALL target-flags(riscv-ccall) @use, csr_il32pc64f_l64pc128f, implicit-def dead $c1, implicit $c10, implicit-def $c2
+  ; CHECK-NEXT:   PseudoCCALL target-flags(riscv-call) @use, csr_il32pc64f_l64pc128f, implicit-def dead $c1, implicit $c10, implicit-def $c2
   ; CHECK-NEXT:   ADJCALLSTACKUPCAP 0, 0, implicit-def dead $c2, implicit $c2
   ; CHECK-NEXT:   PseudoCRET
   %1 = alloca i32, i64 %n, align 4, addrspace(200)
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/cheri-intrinsics-folding-broken-module-regression.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/cheri-intrinsics-folding-broken-module-regression.ll
index 0d1a98f2a7e95..82169913cc7d4 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/cheri-intrinsics-folding-broken-module-regression.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/cheri-intrinsics-folding-broken-module-regression.ll
@@ -19,10 +19,10 @@ define void @g(i32 %x, i32 %y) addrspace(200) nounwind {
 ; ASM-LABEL: g:
 ; ASM:       # %bb.0:
 ; ASM-NEXT:  .LBB0_1: # Label of block must be emitted
-; ASM-NEXT:    auipcc ca2, %captab_pcrel_hi(d)
+; ASM-NEXT:    auipcc ca2, %got_pcrel_hi(d)
 ; ASM-NEXT:    lc ca2, %pcrel_lo(.LBB0_1)(ca2)
 ; ASM-NEXT:  .LBB0_2: # Label of block must be emitted
-; ASM-NEXT:    auipcc ca3, %captab_pcrel_hi(e)
+; ASM-NEXT:    auipcc ca3, %got_pcrel_hi(e)
 ; ASM-NEXT:    lc ca3, %pcrel_lo(.LBB0_2)(ca3)
 ; ASM-NEXT:    cincoffset ca0, ca2, a0
 ; ASM-NEXT:    cincoffset ca0, ca0, a1
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/memcpy-from-constant.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/memcpy-from-constant.ll
index dccebbbcd54c9..4875ddbbe5a03 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/memcpy-from-constant.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/memcpy-from-constant.ll
@@ -46,7 +46,7 @@ define linkonce_odr void @copy_from_ptr_constant(ptr addrspace(200) %dst) addrsp
 ; CHECK:       # %bb.0: # %do.body
 ; CHECK-NEXT:  .LBB3_1: # %do.body
 ; CHECK-NEXT:    # Label of block must be emitted
-; CHECK-NEXT:    auipcc ca1, %captab_pcrel_hi(constant_ptrs)
+; CHECK-NEXT:    auipcc ca1, %got_pcrel_hi(constant_ptrs)
 ; CHECK-NEXT:    lc ca1, %pcrel_lo(.LBB3_1)(ca1)
 ; CHECK-NEXT:    lc ca1, 0(ca1)
 ; CHECK-NEXT:    sc ca1, 0(ca0)
@@ -61,7 +61,7 @@ define linkonce_odr void @copy_from_ptr_constant_with_offset(ptr addrspace(200)
 ; CHECK:       # %bb.0: # %do.body
 ; CHECK-NEXT:  .LBB4_1: # %do.body
 ; CHECK-NEXT:    # Label of block must be emitted
-; CHECK-NEXT:    auipcc ca1, %captab_pcrel_hi(constant_ptrs)
+; CHECK-NEXT:    auipcc ca1, %got_pcrel_hi(constant_ptrs)
 ; CHECK-NEXT:    lc ca1, %pcrel_lo(.LBB4_1)(ca1)
 ; CHECK-NEXT:    lc ca1, 8(ca1)
 ; CHECK-NEXT:    sc ca1, 0(ca0)
@@ -110,7 +110,7 @@ define linkonce_odr void @copy_from_ptr_constant_preserve(ptr addrspace(200) %ds
 ; CHECK:       # %bb.0: # %do.body
 ; CHECK-NEXT:  .LBB8_1: # %do.body
 ; CHECK-NEXT:    # Label of block must be emitted
-; CHECK-NEXT:    auipcc ca1, %captab_pcrel_hi(constant_ptrs)
+; CHECK-NEXT:    auipcc ca1, %got_pcrel_hi(constant_ptrs)
 ; CHECK-NEXT:    lc ca1, %pcrel_lo(.LBB8_1)(ca1)
 ; CHECK-NEXT:    lc ca1, 0(ca1)
 ; CHECK-NEXT:    sc ca1, 0(ca0)
@@ -125,7 +125,7 @@ define linkonce_odr void @copy_from_ptr_constant_with_offset_preserve(ptr addrsp
 ; CHECK:       # %bb.0: # %do.body
 ; CHECK-NEXT:  .LBB9_1: # %do.body
 ; CHECK-NEXT:    # Label of block must be emitted
-; CHECK-NEXT:    auipcc ca1, %captab_pcrel_hi(constant_ptrs)
+; CHECK-NEXT:    auipcc ca1, %got_pcrel_hi(constant_ptrs)
 ; CHECK-NEXT:    lc ca1, %pcrel_lo(.LBB9_1)(ca1)
 ; CHECK-NEXT:    lc ca1, 8(ca1)
 ; CHECK-NEXT:    sc ca1, 0(ca0)
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/memcpy-zeroinit.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/memcpy-zeroinit.ll
index 07f5e7967ca7b..78335bd32e559 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/memcpy-zeroinit.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/memcpy-zeroinit.ll
@@ -27,7 +27,7 @@ define void @_thr_umutex_init_volatile(%struct.umutex addrspace(200)* %mtx) loca
 ; CHECK-LABEL: _thr_umutex_init_volatile:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:  .LBB1_1: # Label of block must be emitted
-; CHECK-NEXT:    auipcc ca1, %captab_pcrel_hi(_thr_umutex_init.default_mtx)
+; CHECK-NEXT:    auipcc ca1, %got_pcrel_hi(_thr_umutex_init.default_mtx)
 ; CHECK-NEXT:    lc ca1, %pcrel_lo(.LBB1_1)(ca1)
 ; CHECK-NEXT:    lc ca2, 40(ca1)
 ; CHECK-NEXT:    sc ca2, 40(ca0)
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/strcpy-to-memcpy-no-tags.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/strcpy-to-memcpy-no-tags.ll
index 1ea2b2bf2c4c2..c2ffad26d3128 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/strcpy-to-memcpy-no-tags.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/strcpy-to-memcpy-no-tags.ll
@@ -84,7 +84,7 @@ define void @test_strcat_to_memcpy(ptr addrspace(200) align 4 %dst) addrspace(20
 ; CHECK-ASM-NEXT:    cincoffset ca0, cs0, a0
 ; CHECK-ASM-NEXT:  .LBB2_1: # %entry
 ; CHECK-ASM-NEXT:    # Label of block must be emitted
-; CHECK-ASM-NEXT:    auipcc ca1, %captab_pcrel_hi(.Lstr)
+; CHECK-ASM-NEXT:    auipcc ca1, %got_pcrel_hi(.Lstr)
 ; CHECK-ASM-NEXT:    lc ca1, %pcrel_lo(.LBB2_1)(ca1)
 ; CHECK-ASM-NEXT:    li a2, 17
 ; CHECK-ASM-NEXT:    ccall memcpy
@@ -113,7 +113,7 @@ define void @test_strncpy_to_memcpy(ptr addrspace(200) align 4 %dst) addrspace(2
 ; CHECK-ASM-NEXT:    sc cra, 8(csp) # 8-byte Folded Spill
 ; CHECK-ASM-NEXT:  .LBB3_1: # %entry
 ; CHECK-ASM-NEXT:    # Label of block must be emitted
-; CHECK-ASM-NEXT:    auipcc ca1, %captab_pcrel_hi(.Lstr)
+; CHECK-ASM-NEXT:    auipcc ca1, %got_pcrel_hi(.Lstr)
 ; CHECK-ASM-NEXT:    lc ca1, %pcrel_lo(.LBB3_1)(ca1)
 ; CHECK-ASM-NEXT:    li a2, 17
 ; CHECK-ASM-NEXT:    li a3, 0
@@ -140,7 +140,7 @@ define void @test_stpncpy_to_memcpy(ptr addrspace(200) align 4 %dst) addrspace(2
 ; CHECK-ASM-NEXT:    sc cra, 8(csp) # 8-byte Folded Spill
 ; CHECK-ASM-NEXT:  .LBB4_1: # %entry
 ; CHECK-ASM-NEXT:    # Label of block must be emitted
-; CHECK-ASM-NEXT:    auipcc ca1, %captab_pcrel_hi(.Lstr)
+; CHECK-ASM-NEXT:    auipcc ca1, %got_pcrel_hi(.Lstr)
 ; CHECK-ASM-NEXT:    lc ca1, %pcrel_lo(.LBB4_1)(ca1)
 ; CHECK-ASM-NEXT:    li a2, 17
 ; CHECK-ASM-NEXT:    li a3, 0
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV32/unaligned-loads-stores-purecap.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV32/unaligned-loads-stores-purecap.ll
index a1b0488b85794..623478a9c8d45 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV32/unaligned-loads-stores-purecap.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV32/unaligned-loads-stores-purecap.ll
@@ -11,7 +11,7 @@ define i64 @load_global_i64_align_1(i64 %y) addrspace(200) nounwind {
 ; CHECK-LABEL: load_global_i64_align_1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:  .LBB0_1: # Label of block must be emitted
-; CHECK-NEXT:    auipcc ca1, %captab_pcrel_hi(a1)
+; CHECK-NEXT:    auipcc ca1, %got_pcrel_hi(a1)
 ; CHECK-NEXT:    lc ca1, %pcrel_lo(.LBB0_1)(ca1)
 ; CHECK-NEXT:    lbu a0, 1(ca1)
 ; CHECK-NEXT:    lbu a2, 0(ca1)
@@ -42,7 +42,7 @@ define i64 @load_global_i64_align_2(i64 %y) addrspace(200) nounwind {
 ; CHECK-LABEL: load_global_i64_align_2:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:  .LBB1_1: # Label of block must be emitted
-; CHECK-NEXT:    auipcc ca0, %captab_pcrel_hi(a2)
+; CHECK-NEXT:    auipcc ca0, %got_pcrel_hi(a2)
 ; CHECK-NEXT:    lc ca0, %pcrel_lo(.LBB1_1)(ca0)
 ; CHECK-NEXT:    lhu a1, 2(ca0)
 ; CHECK-NEXT:    lhu a2, 0(ca0)
@@ -61,7 +61,7 @@ define i64 @load_global_i64_align_4(i64 %y) addrspace(200) nounwind {
 ; CHECK-LABEL: load_global_i64_align_4:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:  .LBB2_1: # Label of block must be emitted
-; CHECK-NEXT:    auipcc ca1, %captab_pcrel_hi(a4)
+; CHECK-NEXT:    auipcc ca1, %got_pcrel_hi(a4)
 ; CHECK-NEXT:    lc ca1, %pcrel_lo(.LBB2_1)(ca1)
 ; CHECK-NEXT:    lw a0, 0(ca1)
 ; CHECK-NEXT:    lw a1, 4(ca1)
@@ -74,7 +74,7 @@ define i64 @load_global_i64_align_8(i64 %y) addrspace(200) nounwind {
 ; CHECK-LABEL: load_global_i64_align_8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:  .LBB3_1: # Label of block must be emitted
-; CHECK-NEXT:    auipcc ca1, %captab_pcrel_hi(a8)
+; CHECK-NEXT:    auipcc ca1, %got_pcrel_hi(a8)
 ; CHECK-NEXT:    lc ca1, %pcrel_lo(.LBB3_1)(ca1)
 ; CHECK-NEXT:    lw a0, 0(ca1)
 ; CHECK-NEXT:    lw a1, 4(ca1)
@@ -87,7 +87,7 @@ define void @store_global_i64_align_1(i64 %y) addrspace(200) nounwind {
 ; CHECK-LABEL: store_global_i64_align_1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:  .LBB4_1: # Label of block must be emitted
-; CHECK-NEXT:    auipcc ca2, %captab_pcrel_hi(a1)
+; CHECK-NEXT:    auipcc ca2, %got_pcrel_hi(a1)
 ; CHECK-NEXT:    lc ca2, %pcrel_lo(.LBB4_1)(ca2)
 ; CHECK-NEXT:    sb a1, 4(ca2)
 ; CHECK-NEXT:    sb a0, 0(ca2)
@@ -112,7 +112,7 @@ define void @store_global_i64_align_2(i64 %y) addrspace(200) nounwind {
 ; CHECK-LABEL: store_global_i64_align_2:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:  .LBB5_1: # Label of block must be emitted
-; CHECK-NEXT:    auipcc ca2, %captab_pcrel_hi(a2)
+; CHECK-NEXT:    auipcc ca2, %got_pcrel_hi(a2)
 ; CHECK-NEXT:    lc ca2, %pcrel_lo(.LBB5_1)(ca2)
 ; CHECK-NEXT:    sh a1, 4(ca2)
 ; CHECK-NEXT:    sh a0, 0(ca2)
@@ -129,7 +129,7 @@ define void @store_global_i64_align_4(i64 %y) addrspace(200) nounwind {
 ; CHECK-LABEL: store_global_i64_align_4:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:  .LBB6_1: # Label of block must be emitted
-; CHECK-NEXT:    auipcc ca2, %captab_pcrel_hi(a4)
+; CHECK-NEXT:    auipcc ca2, %got_pcrel_hi(a4)
 ; CHECK-NEXT:    lc ca2, %pcrel_lo(.LBB6_1)(ca2)
 ; CHECK-NEXT:    sw a1, 4(ca2)
 ; CHECK-NEXT:    sw a0, 0(ca2)
@@ -142,7 +142,7 @@ define void @store_global_i64_align_8(i64 %y) addrspace(200) nounwind {
 ; CHECK-LABEL: store_global_i64_align_8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:  .LBB7_1: # Label of block must be emitted
-; CHECK-NEXT:    auipcc ca2, %captab_pcrel_hi(a8)
+; CHECK-NEXT:    auipcc ca2, %got_pcrel_hi(a8)
 ; CHECK-NEXT:    lc ca2, %pcrel_lo(.LBB7_1)(ca2)
 ; CHECK-NEXT:    sw a1, 4(ca2)
 ; CHECK-NEXT:    sw a0, 0(ca2)
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/bounded-allocas-lifetimes.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/bounded-allocas-lifetimes.ll
index 9ff00fe1c1c24..ff52ec086bcea 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/bounded-allocas-lifetimes.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/bounded-allocas-lifetimes.ll
@@ -17,7 +17,7 @@ define void @static_alloca() {
   ; CHECK-NEXT:   LIFETIME_START %stack.0
   ; CHECK-NEXT:   ADJCALLSTACKDOWNCAP 0, 0, implicit-def dead $c2, implicit $c2
   ; CHECK-NEXT:   $c10 = COPY [[CSetBoundsImm]]
-  ; CHECK-NEXT:   PseudoCCALL target-flags(riscv-ccall) @use, csr_il32pc64d_l64pc128d, implicit-def dead $c1, implicit $c10, implicit-def $c2
+  ; CHECK-NEXT:   PseudoCCALL target-flags(riscv-call) @use, csr_il32pc64d_l64pc128d, implicit-def dead $c1, implicit $c10, implicit-def $c2
   ; CHECK-NEXT:   ADJCALLSTACKUPCAP 0, 0, implicit-def dead $c2, implicit $c2
   ; CHECK-NEXT:   LIFETIME_END %stack.0
   ; CHECK-NEXT:   PseudoCRET
@@ -54,7 +54,7 @@ define void @dynamic_alloca(i64 zeroext %n) {
   ; CHECK-NEXT:   [[CSetBounds1:%[0-9]+]]:gpcr = CSetBounds killed [[CSetBounds]], [[SLLI]]
   ; CHECK-NEXT:   ADJCALLSTACKDOWNCAP 0, 0, implicit-def dead $c2, implicit $c2
   ; CHECK-NEXT:   $c10 = COPY [[CSetBounds1]]
-  ; CHECK-NEXT:   PseudoCCALL target-flags(riscv-ccall) @use, csr_il32pc64d_l64pc128d, implicit-def dead $c1, implicit $c10, implicit-def $c2
+  ; CHECK-NEXT:   PseudoCCALL target-flags(riscv-call) @use, csr_il32pc64d_l64pc128d, implicit-def dead $c1, implicit $c10, implicit-def $c2
   ; CHECK-NEXT:   ADJCALLSTACKUPCAP 0, 0, implicit-def dead $c2, implicit $c2
   ; CHECK-NEXT:   PseudoCRET
   %1 = alloca i32, i64 %n, align 4, addrspace(200)
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/cheri-intrinsics-folding-broken-module-regression.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/cheri-intrinsics-folding-broken-module-regression.ll
index b09ad3df06175..d34e04fe34b35 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/cheri-intrinsics-folding-broken-module-regression.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/cheri-intrinsics-folding-broken-module-regression.ll
@@ -19,10 +19,10 @@ define void @g(i64 %x, i64 %y) addrspace(200) nounwind {
 ; ASM-LABEL: g:
 ; ASM:       # %bb.0:
 ; ASM-NEXT:  .LBB0_1: # Label of block must be emitted
-; ASM-NEXT:    auipcc ca2, %captab_pcrel_hi(d)
+; ASM-NEXT:    auipcc ca2, %got_pcrel_hi(d)
 ; ASM-NEXT:    lc ca2, %pcrel_lo(.LBB0_1)(ca2)
 ; ASM-NEXT:  .LBB0_2: # Label of block must be emitted
-; ASM-NEXT:    auipcc ca3, %captab_pcrel_hi(e)
+; ASM-NEXT:    auipcc ca3, %got_pcrel_hi(e)
 ; ASM-NEXT:    lc ca3, %pcrel_lo(.LBB0_2)(ca3)
 ; ASM-NEXT:    cincoffset ca0, ca2, a0
 ; ASM-NEXT:    cincoffset ca0, ca0, a1
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/memcpy-from-constant.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/memcpy-from-constant.ll
index 53e372ffc95fe..3e49666aef64b 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/memcpy-from-constant.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/memcpy-from-constant.ll
@@ -46,7 +46,7 @@ define linkonce_odr void @copy_from_ptr_constant(ptr addrspace(200) %dst) addrsp
 ; CHECK:       # %bb.0: # %do.body
 ; CHECK-NEXT:  .LBB3_1: # %do.body
 ; CHECK-NEXT:    # Label of block must be emitted
-; CHECK-NEXT:    auipcc ca1, %captab_pcrel_hi(constant_ptrs)
+; CHECK-NEXT:    auipcc ca1, %got_pcrel_hi(constant_ptrs)
 ; CHECK-NEXT:    lc ca1, %pcrel_lo(.LBB3_1)(ca1)
 ; CHECK-NEXT:    lc ca1, 0(ca1)
 ; CHECK-NEXT:    sc ca1, 0(ca0)
@@ -61,7 +61,7 @@ define linkonce_odr void @copy_from_ptr_constant_with_offset(ptr addrspace(200)
 ; CHECK:       # %bb.0: # %do.body
 ; CHECK-NEXT:  .LBB4_1: # %do.body
 ; CHECK-NEXT:    # Label of block must be emitted
-; CHECK-NEXT:    auipcc ca1, %captab_pcrel_hi(constant_ptrs)
+; CHECK-NEXT:    auipcc ca1, %got_pcrel_hi(constant_ptrs)
 ; CHECK-NEXT:    lc ca1, %pcrel_lo(.LBB4_1)(ca1)
 ; CHECK-NEXT:    lc ca1, 16(ca1)
 ; CHECK-NEXT:    sc ca1, 0(ca0)
@@ -110,7 +110,7 @@ define linkonce_odr void @copy_from_ptr_constant_preserve(ptr addrspace(200) %ds
 ; CHECK:       # %bb.0: # %do.body
 ; CHECK-NEXT:  .LBB8_1: # %do.body
 ; CHECK-NEXT:    # Label of block must be emitted
-; CHECK-NEXT:    auipcc ca1, %captab_pcrel_hi(constant_ptrs)
+; CHECK-NEXT:    auipcc ca1, %got_pcrel_hi(constant_ptrs)
 ; CHECK-NEXT:    lc ca1, %pcrel_lo(.LBB8_1)(ca1)
 ; CHECK-NEXT:    lc ca1, 0(ca1)
 ; CHECK-NEXT:    sc ca1, 0(ca0)
@@ -125,7 +125,7 @@ define linkonce_odr void @copy_from_ptr_constant_with_offset_preserve(ptr addrsp
 ; CHECK:       # %bb.0: # %do.body
 ; CHECK-NEXT:  .LBB9_1: # %do.body
 ; CHECK-NEXT:    # Label of block must be emitted
-; CHECK-NEXT:    auipcc ca1, %captab_pcrel_hi(constant_ptrs)
+; CHECK-NEXT:    auipcc ca1, %got_pcrel_hi(constant_ptrs)
 ; CHECK-NEXT:    lc ca1, %pcrel_lo(.LBB9_1)(ca1)
 ; CHECK-NEXT:    lc ca1, 16(ca1)
 ; CHECK-NEXT:    sc ca1, 0(ca0)
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/memcpy-zeroinit.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/memcpy-zeroinit.ll
index 275a8979fd9d2..55e63f9fd384e 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/memcpy-zeroinit.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/memcpy-zeroinit.ll
@@ -24,7 +24,7 @@ define void @_thr_umutex_init_volatile(%struct.umutex addrspace(200)* %mtx) loca
 ; CHECK-LABEL: _thr_umutex_init_volatile:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:  .LBB1_1: # Label of block must be emitted
-; CHECK-NEXT:    auipcc ca1, %captab_pcrel_hi(_thr_umutex_init.default_mtx)
+; CHECK-NEXT:    auipcc ca1, %got_pcrel_hi(_thr_umutex_init.default_mtx)
 ; CHECK-NEXT:    lc ca1, %pcrel_lo(.LBB1_1)(ca1)
 ; CHECK-NEXT:    lc ca2, 32(ca1)
 ; CHECK-NEXT:    sc ca2, 32(ca0)
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/strcpy-to-memcpy-no-tags.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/strcpy-to-memcpy-no-tags.ll
index b1b5551c50491..9663b5dd3575a 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/strcpy-to-memcpy-no-tags.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/strcpy-to-memcpy-no-tags.ll
@@ -84,7 +84,7 @@ define void @test_strcat_to_memcpy(ptr addrspace(200) align 8 %dst) addrspace(20
 ; CHECK-ASM-NEXT:    cincoffset ca0, cs0, a0
 ; CHECK-ASM-NEXT:  .LBB2_1: # %entry
 ; CHECK-ASM-NEXT:    # Label of block must be emitted
-; CHECK-ASM-NEXT:    auipcc ca1, %captab_pcrel_hi(.Lstr)
+; CHECK-ASM-NEXT:    auipcc ca1, %got_pcrel_hi(.Lstr)
 ; CHECK-ASM-NEXT:    lc ca1, %pcrel_lo(.LBB2_1)(ca1)
 ; CHECK-ASM-NEXT:    li a2, 17
 ; CHECK-ASM-NEXT:    ccall memcpy
diff --git a/llvm/test/CodeGen/CHERI-Generic/RISCV64/unaligned-loads-stores-purecap.ll b/llvm/test/CodeGen/CHERI-Generic/RISCV64/unaligned-loads-stores-purecap.ll
index dd5eb1d3c0c78..4f8fcc43e3420 100644
--- a/llvm/test/CodeGen/CHERI-Generic/RISCV64/unaligned-loads-stores-purecap.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/RISCV64/unaligned-loads-stores-purecap.ll
@@ -11,7 +11,7 @@ define i64 @load_global_i64_align_1(i64 %y) addrspace(200) nounwind {
 ; CHECK-LABEL: load_global_i64_align_1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:  .LBB0_1: # Label of block must be emitted
-; CHECK-NEXT:    auipcc ca0, %captab_pcrel_hi(a1)
+; CHECK-NEXT:    auipcc ca0, %got_pcrel_hi(a1)
 ; CHECK-NEXT:    lc ca0, %pcrel_lo(.LBB0_1)(ca0)
 ; CHECK-NEXT:    lbu a1, 1(ca0)
 ; CHECK-NEXT:    lbu a2, 0(ca0)
@@ -44,7 +44,7 @@ define i64 @load_global_i64_align_2(i64 %y) addrspace(200) nounwind {
 ; CHECK-LABEL: load_global_i64_align_2:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:  .LBB1_1: # Label of block must be emitted
-; CHECK-NEXT:    auipcc ca0, %captab_pcrel_hi(a2)
+; CHECK-NEXT:    auipcc ca0, %got_pcrel_hi(a2)
 ; CHECK-NEXT:    lc ca0, %pcrel_lo(.LBB1_1)(ca0)
 ; CHECK-NEXT:    lhu a1, 2(ca0)
 ; CHECK-NEXT:    lhu a2, 0(ca0)
@@ -65,7 +65,7 @@ define i64 @load_global_i64_align_4(i64 %y) addrspace(200) nounwind {
 ; CHECK-LABEL: load_global_i64_align_4:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:  .LBB2_1: # Label of block must be emitted
-; CHECK-NEXT:    auipcc ca0, %captab_pcrel_hi(a4)
+; CHECK-NEXT:    auipcc ca0, %got_pcrel_hi(a4)
 ; CHECK-NEXT:    lc ca0, %pcrel_lo(.LBB2_1)(ca0)
 ; CHECK-NEXT:    lwu a1, 4(ca0)
 ; CHECK-NEXT:    lwu a0, 0(ca0)
@@ -80,7 +80,7 @@ define i64 @load_global_i64_align_8(i64 %y) addrspace(200) nounwind {
 ; CHECK-LABEL: load_global_i64_align_8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:  .LBB3_1: # Label of block must be emitted
-; CHECK-NEXT:    auipcc ca0, %captab_pcrel_hi(a8)
+; CHECK-NEXT:    auipcc ca0, %got_pcrel_hi(a8)
 ; CHECK-NEXT:    lc ca0, %pcrel_lo(.LBB3_1)(ca0)
 ; CHECK-NEXT:    ld a0, 0(ca0)
 ; CHECK-NEXT:    ret
@@ -92,7 +92,7 @@ define void @store_global_i64_align_1(i64 %y) addrspace(200) nounwind {
 ; CHECK-LABEL: store_global_i64_align_1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:  .LBB4_1: # Label of block must be emitted
-; CHECK-NEXT:    auipcc ca1, %captab_pcrel_hi(a1)
+; CHECK-NEXT:    auipcc ca1, %got_pcrel_hi(a1)
 ; CHECK-NEXT:    lc ca1, %pcrel_lo(.LBB4_1)(ca1)
 ; CHECK-NEXT:    sb a0, 0(ca1)
 ; CHECK-NEXT:    srli a2, a0, 56
@@ -118,7 +118,7 @@ define void @store_global_i64_align_2(i64 %y) addrspace(200) nounwind {
 ; CHECK-LABEL: store_global_i64_align_2:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:  .LBB5_1: # Label of block must be emitted
-; CHECK-NEXT:    auipcc ca1, %captab_pcrel_hi(a2)
+; CHECK-NEXT:    auipcc ca1, %got_pcrel_hi(a2)
 ; CHECK-NEXT:    lc ca1, %pcrel_lo(.LBB5_1)(ca1)
 ; CHECK-NEXT:    sh a0, 0(ca1)
 ; CHECK-NEXT:    srli a2, a0, 48
@@ -136,7 +136,7 @@ define void @store_global_i64_align_4(i64 %y) addrspace(200) nounwind {
 ; CHECK-LABEL: store_global_i64_align_4:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:  .LBB6_1: # Label of block must be emitted
-; CHECK-NEXT:    auipcc ca1, %captab_pcrel_hi(a4)
+; CHECK-NEXT:    auipcc ca1, %got_pcrel_hi(a4)
 ; CHECK-NEXT:    lc ca1, %pcrel_lo(.LBB6_1)(ca1)
 ; CHECK-NEXT:    sw a0, 0(ca1)
 ; CHECK-NEXT:    srli a0, a0, 32
@@ -150,7 +150,7 @@ define void @store_global_i64_align_8(i64 %y) addrspace(200) nounwind {
 ; CHECK-LABEL: store_global_i64_align_8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:  .LBB7_1: # Label of block must be emitted
-; CHECK-NEXT:    auipcc ca1, %captab_pcrel_hi(a8)
+; CHECK-NEXT:    auipcc ca1, %got_pcrel_hi(a8)
 ; CHECK-NEXT:    lc ca1, %pcrel_lo(.LBB7_1)(ca1)
 ; CHECK-NEXT:    sd a0, 0(ca1)
 ; CHECK-NEXT:    ret
diff --git a/llvm/test/CodeGen/CHERI-Generic/byval-buffer.ll b/llvm/test/CodeGen/CHERI-Generic/byval-buffer.ll
index c0e779d43180e..e79435ca836e7 100644
--- a/llvm/test/CodeGen/CHERI-Generic/byval-buffer.ll
+++ b/llvm/test/CodeGen/CHERI-Generic/byval-buffer.ll
@@ -170,7 +170,7 @@ define dso_local void @clang_purecap_byval_args() local_unnamed_addr addrspace(2
 ; PURECAP-RV64-NEXT:    sc cs0, 1040(csp) # 16-byte Folded Spill
 ; PURECAP-RV64-NEXT:  .LBB0_1: # %entry
 ; PURECAP-RV64-NEXT:    # Label of block must be emitted
-; PURECAP-RV64-NEXT:    auipcc cs0, %captab_pcrel_hi(global_foo)
+; PURECAP-RV64-NEXT:    auipcc cs0, %got_pcrel_hi(global_foo)
 ; PURECAP-RV64-NEXT:    lc cs0, %pcrel_lo(.LBB0_1)(cs0)
 ; PURECAP-RV64-NEXT:    li a2, 1024
 ; PURECAP-RV64-NEXT:    cmove ca0, cs0
diff --git a/llvm/test/CodeGen/RISCV/cheri/get-global-addr.ll b/llvm/test/CodeGen/RISCV/cheri/get-global-addr.ll
index 37f6a7c1e2086..d572eb2f99adc 100644
--- a/llvm/test/CodeGen/RISCV/cheri/get-global-addr.ll
+++ b/llvm/test/CodeGen/RISCV/cheri/get-global-addr.ll
@@ -52,7 +52,7 @@ define i64 @load_external_global_variable(double %a) nounwind {
 ; L64PC128-LABEL: load_external_global_variable:
 ; L64PC128:       # %bb.0:
 ; L64PC128-NEXT:  .LBB2_1: # Label of block must be emitted
-; L64PC128-NEXT:    auipcc ca0, %captab_pcrel_hi(external_variable)
+; L64PC128-NEXT:    auipcc ca0, %got_pcrel_hi(external_variable)
 ; L64PC128-NEXT:    lc ca0, %pcrel_lo(.LBB2_1)(ca0)
 ; L64PC128-NEXT:    ld a0, 0(ca0)
 ; L64PC128-NEXT:    ret
@@ -65,7 +65,7 @@ define i64 @load_external_global_constant(double %a) nounwind {
 ; L64PC128-LABEL: load_external_global_constant:
 ; L64PC128:       # %bb.0:
 ; L64PC128-NEXT:  .LBB3_1: # Label of block must be emitted
-; L64PC128-NEXT:    auipcc ca0, %captab_pcrel_hi(external_constant)
+; L64PC128-NEXT:    auipcc ca0, %got_pcrel_hi(external_constant)
 ; L64PC128-NEXT:    lc ca0, %pcrel_lo(.LBB3_1)(ca0)
 ; L64PC128-NEXT:    ld a0, 0(ca0)
 ; L64PC128-NEXT:    ret
@@ -78,7 +78,7 @@ define i64 @load_dso_local_external_global_variable(double %a) nounwind {
 ; L64PC128-LABEL: load_dso_local_external_global_variable:
 ; L64PC128:       # %bb.0:
 ; L64PC128-NEXT:  .LBB4_1: # Label of block must be emitted
-; L64PC128-NEXT:    auipcc ca0, %captab_pcrel_hi(dso_local_external_variable)
+; L64PC128-NEXT:    auipcc ca0, %got_pcrel_hi(dso_local_external_variable)
 ; L64PC128-NEXT:    lc ca0, %pcrel_lo(.LBB4_1)(ca0)
 ; L64PC128-NEXT:    ld a0, 0(ca0)
 ; L64PC128-NEXT:    ret
@@ -92,7 +92,7 @@ define i64 @load_dso_local_external_global_constant(double %a) nounwind {
 ; L64PC128-LABEL: load_dso_local_external_global_constant:
 ; L64PC128:       # %bb.0:
 ; L64PC128-NEXT:  .LBB5_1: # Label of block must be emitted
-; L64PC128-NEXT:    auipcc ca0, %captab_pcrel_hi(dso_local_external_constant)
+; L64PC128-NEXT:    auipcc ca0, %got_pcrel_hi(dso_local_external_constant)
 ; L64PC128-NEXT:    lc ca0, %pcrel_lo(.LBB5_1)(ca0)
 ; L64PC128-NEXT:    ld a0, 0(ca0)
 ; L64PC128-NEXT:    ret
@@ -105,7 +105,7 @@ define i64 @load_defined_variable(double %a) nounwind {
 ; L64PC128-LABEL: load_defined_variable:
 ; L64PC128:       # %bb.0:
 ; L64PC128-NEXT:  .LBB6_1: # Label of block must be emitted
-; L64PC128-NEXT:    auipcc ca0, %captab_pcrel_hi(defined_variable)
+; L64PC128-NEXT:    auipcc ca0, %got_pcrel_hi(defined_variable)
 ; L64PC128-NEXT:    lc ca0, %pcrel_lo(.LBB6_1)(ca0)
 ; L64PC128-NEXT:    ld a0, 0(ca0)
 ; L64PC128-NEXT:    ret
@@ -118,7 +118,7 @@ define i64 @load_defined_constant(double %a) nounwind {
 ; L64PC128-LABEL: load_defined_constant:
 ; L64PC128:       # %bb.0:
 ; L64PC128-NEXT:  .LBB7_1: # Label of block must be emitted
-; L64PC128-NEXT:    auipcc ca0, %captab_pcrel_hi(defined_constant)
+; L64PC128-NEXT:    auipcc ca0, %got_pcrel_hi(defined_constant)
 ; L64PC128-NEXT:    lc ca0, %pcrel_lo(.LBB7_1)(ca0)
 ; L64PC128-NEXT:    ld a0, 0(ca0)
 ; L64PC128-NEXT:    ret
@@ -131,7 +131,7 @@ define i64 @load_hidden_variable(double %a) nounwind {
 ; L64PC128-LABEL: load_hidden_variable:
 ; L64PC128:       # %bb.0:
 ; L64PC128-NEXT:  .LBB8_1: # Label of block must be emitted
-; L64PC128-NEXT:    auipcc ca0, %captab_pcrel_hi(hidden_variable)
+; L64PC128-NEXT:    auipcc ca0, %got_pcrel_hi(hidden_variable)
 ; L64PC128-NEXT:    lc ca0, %pcrel_lo(.LBB8_1)(ca0)
 ; L64PC128-NEXT:    ld a0, 0(ca0)
 ; L64PC128-NEXT:    ret
@@ -144,7 +144,7 @@ define i64 @load_hidden_constant(double %a) nounwind {
 ; L64PC128-LABEL: load_hidden_constant:
 ; L64PC128:       # %bb.0:
 ; L64PC128-NEXT:  .LBB9_1: # Label of block must be emitted
-; L64PC128-NEXT:    auipcc ca0, %captab_pcrel_hi(hidden_constant)
+; L64PC128-NEXT:    auipcc ca0, %got_pcrel_hi(hidden_constant)
 ; L64PC128-NEXT:    lc ca0, %pcrel_lo(.LBB9_1)(ca0)
 ; L64PC128-NEXT:    ld a0, 0(ca0)
 ; L64PC128-NEXT:    ret
@@ -157,7 +157,7 @@ define i64 @load_dso_local_variable(double %a) nounwind {
 ; L64PC128-LABEL: load_dso_local_variable:
 ; L64PC128:       # %bb.0:
 ; L64PC128-NEXT:  .LBB10_1: # Label of block must be emitted
-; L64PC128-NEXT:    auipcc ca0, %captab_pcrel_hi(dso_local_variable)
+; L64PC128-NEXT:    auipcc ca0, %got_pcrel_hi(dso_local_variable)
 ; L64PC128-NEXT:    lc ca0, %pcrel_lo(.LBB10_1)(ca0)
 ; L64PC128-NEXT:    ld a0, 0(ca0)
 ; L64PC128-NEXT:    ret
@@ -170,7 +170,7 @@ define i64 @load_dso_local_constant(double %a) nounwind {
 ; L64PC128-LABEL: load_dso_local_constant:
 ; L64PC128:       # %bb.0:
 ; L64PC128-NEXT:  .LBB11_1: # Label of block must be emitted
-; L64PC128-NEXT:    auipcc ca0, %captab_pcrel_hi(dso_local_constant)
+; L64PC128-NEXT:    auipcc ca0, %got_pcrel_hi(dso_local_constant)
 ; L64PC128-NEXT:    lc ca0, %pcrel_lo(.LBB11_1)(ca0)
 ; L64PC128-NEXT:    ld a0, 0(ca0)
 ; L64PC128-NEXT:    ret
diff --git a/llvm/test/CodeGen/RISCV/cheri/machine-outliner.mir b/llvm/test/CodeGen/RISCV/cheri/machine-outliner.mir
index 8045cfb83bfc9..c000a743ab101 100644
--- a/llvm/test/CodeGen/RISCV/cheri/machine-outliner.mir
+++ b/llvm/test/CodeGen/RISCV/cheri/machine-outliner.mir
@@ -48,7 +48,7 @@ body:             |
   ; CHECK-NEXT:   successors: %bb.2(0x40000000), %bb.3(0x40000000)
   ; CHECK-NEXT:   liveins: $c10, $c12, $c13, $x11
   ; CHECK-NEXT: {{  $}}
-  ; CHECK-NEXT:   $c5 = PseudoCCALLReg target-flags(riscv-ccall) @OUTLINED_FUNCTION_0, implicit-def $c5, implicit-def $c15, implicit-def $x14, implicit-def $x15, implicit $c10, implicit $c12
+  ; CHECK-NEXT:   $c5 = PseudoCCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $c5, implicit-def $c15, implicit-def $x14, implicit-def $x15, implicit $c10, implicit $c12
   ; CHECK-NEXT:   renamable $x14 = ANDI killed renamable $x14, 1
   ; CHECK-NEXT:   BEQ killed renamable $x14, $x0, %bb.3
   ; CHECK-NEXT: {{  $}}
@@ -56,7 +56,7 @@ body:             |
   ; CHECK-NEXT:   successors: %bb.3(0x80000000)
   ; CHECK-NEXT:   liveins: $c10, $c12, $c13, $x11
   ; CHECK-NEXT: {{  $}}
-  ; CHECK-NEXT:   $c5 = PseudoCCALLReg target-flags(riscv-ccall) @OUTLINED_FUNCTION_0, implicit-def $c5, implicit-def $c15, implicit-def $x14, implicit-def $x15, implicit $c10, implicit $c12
+  ; CHECK-NEXT:   $c5 = PseudoCCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $c5, implicit-def $c15, implicit-def $x14, implicit-def $x15, implicit $c10, implicit $c12
   ; CHECK-NEXT:   renamable $x15 = ANDI killed renamable $x14, 1
   ; CHECK-NEXT:   $c14 = CMove $c0
   ; CHECK-NEXT: {{  $}}
diff --git a/llvm/test/CodeGen/RISCV/cheri/machinelicm-capability-pseudos.ll b/llvm/test/CodeGen/RISCV/cheri/machinelicm-capability-pseudos.ll
index e250b7fabc549..93c156561f18c 100644
--- a/llvm/test/CodeGen/RISCV/cheri/machinelicm-capability-pseudos.ll
+++ b/llvm/test/CodeGen/RISCV/cheri/machinelicm-capability-pseudos.ll
@@ -14,7 +14,7 @@ define void @test_clgc(i32 signext %n) {
 ; RV32I:       # %bb.0: # %entry
 ; RV32I-NEXT:  .LBB0_3: # %entry
 ; RV32I-NEXT:    # Label of block must be emitted
-; RV32I-NEXT:    auipcc ca1, %captab_pcrel_hi(g)
+; RV32I-NEXT:    auipcc ca1, %got_pcrel_hi(g)
 ; RV32I-NEXT:    lc ca1, %pcrel_lo(.LBB0_3)(ca1)
 ; RV32I-NEXT:    li a2, 0
 ; RV32I-NEXT:  .LBB0_1: # %loop
@@ -29,7 +29,7 @@ define void @test_clgc(i32 signext %n) {
 ; RV64I:       # %bb.0: # %entry
 ; RV64I-NEXT:  .LBB0_3: # %entry
 ; RV64I-NEXT:    # Label of block must be emitted
-; RV64I-NEXT:    auipcc ca1, %captab_pcrel_hi(g)
+; RV64I-NEXT:    auipcc ca1, %got_pcrel_hi(g)
 ; RV64I-NEXT:    lc ca1, %pcrel_lo(.LBB0_3)(ca1)
 ; RV64I-NEXT:    li a2, 0
 ; RV64I-NEXT:  .LBB0_1: # %loop
@@ -60,7 +60,7 @@ define void @test_cla_tls_ie(i32 signext %n) {
 ; RV32I:       # %bb.0: # %entry
 ; RV32I-NEXT:  .LBB1_3: # %entry
 ; RV32I-NEXT:    # Label of block must be emitted
-; RV32I-NEXT:    auipcc ca2, %tls_ie_captab_pcrel_hi(ie)
+; RV32I-NEXT:    auipcc ca2, %tls_ie_pcrel_hi(ie)
 ; RV32I-NEXT:    lw a2, %pcrel_lo(.LBB1_3)(ca2)
 ; RV32I-NEXT:    li a1, 0
 ; RV32I-NEXT:    cincoffset ca2, ctp, a2
@@ -76,7 +76,7 @@ define void @test_cla_tls_ie(i32 signext %n) {
 ; RV64I:       # %bb.0: # %entry
 ; RV64I-NEXT:  .LBB1_3: # %entry
 ; RV64I-NEXT:    # Label of block must be emitted
-; RV64I-NEXT:    auipcc ca2, %tls_ie_captab_pcrel_hi(ie)
+; RV64I-NEXT:    auipcc ca2, %tls_ie_pcrel_hi(ie)
 ; RV64I-NEXT:    ld a2, %pcrel_lo(.LBB1_3)(ca2)
 ; RV64I-NEXT:    li a1, 0
 ; RV64I-NEXT:    cincoffset ca2, ctp, a2
@@ -115,7 +115,7 @@ define void @test_clc_tls_gd(i32 signext %n) nounwind {
 ; RV32I-NEXT:    li s2, 0
 ; RV32I-NEXT:  .LBB2_3: # %entry
 ; RV32I-NEXT:    # Label of block must be emitted
-; RV32I-NEXT:    auipcc cs1, %tls_gd_captab_pcrel_hi(gd)
+; RV32I-NEXT:    auipcc cs1, %tls_gd_pcrel_hi(gd)
 ; RV32I-NEXT:    cincoffset cs1, cs1, %pcrel_lo(.LBB2_3)
 ; RV32I-NEXT:  .LBB2_1: # %loop
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
@@ -143,7 +143,7 @@ define void @test_clc_tls_gd(i32 signext %n) nounwind {
 ; RV64I-NEXT:    li s2, 0
 ; RV64I-NEXT:  .LBB2_3: # %entry
 ; RV64I-NEXT:    # Label of block must be emitted
-; RV64I-NEXT:    auipcc cs1, %tls_gd_captab_pcrel_hi(gd)
+; RV64I-NEXT:    auipcc cs1, %tls_gd_pcrel_hi(gd)
 ; RV64I-NEXT:    cincoffset cs1, cs1, %pcrel_lo(.LBB2_3)
 ; RV64I-NEXT:  .LBB2_1: # %loop
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
diff --git a/llvm/test/CodeGen/RISCV/cheri/rematerialize.mir b/llvm/test/CodeGen/RISCV/cheri/rematerialize.mir
index 16b6cb86ceb57..baf7e87c23c9d 100644
--- a/llvm/test/CodeGen/RISCV/cheri/rematerialize.mir
+++ b/llvm/test/CodeGen/RISCV/cheri/rematerialize.mir
@@ -60,19 +60,19 @@ body:             |
     ; CHECK-NEXT: $c10 = CIncOffsetImm $c0, 123
     ; CHECK-NEXT: $c11 = CMove $c0
     ; CHECK-NEXT: $c12 = COPY [[CIncOffsetImm]]
-    ; CHECK-NEXT: PseudoCCALL target-flags(riscv-ccall) @external_fn, csr_il32pc64_l64pc128, implicit-def dead $c1, implicit killed $c10, implicit killed $c11, implicit killed $c12, implicit-def $c2
+    ; CHECK-NEXT: PseudoCCALL target-flags(riscv-call) @external_fn, csr_il32pc64_l64pc128, implicit-def dead $c1, implicit killed $c10, implicit killed $c11, implicit killed $c12, implicit-def $c2
     ; CHECK-NEXT: ADJCALLSTACKUPCAP 0, 0, implicit-def dead $c2, implicit $c2
     ; CHECK-NEXT: ADJCALLSTACKDOWNCAP 0, 0, implicit-def dead $c2, implicit $c2
     ; CHECK-NEXT: $c10 = CIncOffsetImm $c0, 123
     ; CHECK-NEXT: $c11 = CMove $c0
     ; CHECK-NEXT: $c12 = COPY [[CIncOffsetImm]]
-    ; CHECK-NEXT: PseudoCCALL target-flags(riscv-ccall) @external_fn, csr_il32pc64_l64pc128, implicit-def dead $c1, implicit killed $c10, implicit killed $c11, implicit killed $c12, implicit-def $c2
+    ; CHECK-NEXT: PseudoCCALL target-flags(riscv-call) @external_fn, csr_il32pc64_l64pc128, implicit-def dead $c1, implicit killed $c10, implicit killed $c11, implicit killed $c12, implicit-def $c2
     ; CHECK-NEXT: ADJCALLSTACKUPCAP 0, 0, implicit-def dead $c2, implicit $c2
     ; CHECK-NEXT: ADJCALLSTACKDOWNCAP 0, 0, implicit-def dead $c2, implicit $c2
     ; CHECK-NEXT: $c10 = CIncOffsetImm $c0, 123
     ; CHECK-NEXT: $c11 = CMove $c0
     ; CHECK-NEXT: $c12 = COPY [[CIncOffsetImm]]
-    ; CHECK-NEXT: PseudoCCALL target-flags(riscv-ccall) @external_fn, csr_il32pc64_l64pc128, implicit-def dead $c1, implicit killed $c10, implicit killed $c11, implicit killed $c12, implicit-def $c2
+    ; CHECK-NEXT: PseudoCCALL target-flags(riscv-call) @external_fn, csr_il32pc64_l64pc128, implicit-def dead $c1, implicit killed $c10, implicit killed $c11, implicit killed $c12, implicit-def $c2
     ; CHECK-NEXT: ADJCALLSTACKUPCAP 0, 0, implicit-def dead $c2, implicit $c2
     ; CHECK-NEXT: PseudoCRET
     ADJCALLSTACKDOWNCAP 0, 0, implicit-def dead $c2, implicit $c2
@@ -86,19 +86,19 @@ body:             |
     $c10 = COPY %1
     $c11 = COPY %2
     $c12 = COPY %4
-    PseudoCCALL target-flags(riscv-ccall) @external_fn, csr_il32pc64_l64pc128, implicit-def dead $c1, implicit killed $c10, implicit killed $c11, implicit killed $c12, implicit-def $c2
+    PseudoCCALL target-flags(riscv-call) @external_fn, csr_il32pc64_l64pc128, implicit-def dead $c1, implicit killed $c10, implicit killed $c11, implicit killed $c12, implicit-def $c2
     ADJCALLSTACKUPCAP 0, 0, implicit-def dead $c2, implicit $c2
     ADJCALLSTACKDOWNCAP 0, 0, implicit-def dead $c2, implicit $c2
     $c10 = COPY %1
     $c11 = COPY %2
     $c12 = COPY %4
-    PseudoCCALL target-flags(riscv-ccall) @external_fn, csr_il32pc64_l64pc128, implicit-def dead $c1, implicit killed $c10, implicit killed $c11, implicit killed $c12, implicit-def $c2
+    PseudoCCALL target-flags(riscv-call) @external_fn, csr_il32pc64_l64pc128, implicit-def dead $c1, implicit killed $c10, implicit killed $c11, implicit killed $c12, implicit-def $c2
     ADJCALLSTACKUPCAP 0, 0, implicit-def dead $c2, implicit $c2
     ADJCALLSTACKDOWNCAP 0, 0, implicit-def dead $c2, implicit $c2
     $c10 = COPY killed %1
     $c11 = COPY %2
     $c12 = COPY %4
-    PseudoCCALL target-flags(riscv-ccall) @external_fn, csr_il32pc64_l64pc128, implicit-def dead $c1, implicit killed $c10, implicit killed $c11, implicit killed $c12, implicit-def $c2
+    PseudoCCALL target-flags(riscv-call) @external_fn, csr_il32pc64_l64pc128, implicit-def dead $c1, implicit killed $c10, implicit killed $c11, implicit killed $c12, implicit-def $c2
     ADJCALLSTACKUPCAP 0, 0, implicit-def dead $c2, implicit $c2
     PseudoCRET
 ...
diff --git a/llvm/test/CodeGen/RISCV/cheri/stack-protector.ll b/llvm/test/CodeGen/RISCV/cheri/stack-protector.ll
index d2c3338364323..66bb6334e41fe 100644
--- a/llvm/test/CodeGen/RISCV/cheri/stack-protector.ll
+++ b/llvm/test/CodeGen/RISCV/cheri/stack-protector.ll
@@ -38,7 +38,7 @@ define void @caller() addrspace(200) nounwind sspstrong {
 ; IL32PC64-NEXT:    sc cra, 24(csp) # 8-byte Folded Spill
 ; IL32PC64-NEXT:    sc cs0, 16(csp) # 8-byte Folded Spill
 ; IL32PC64-NEXT:  .LBB0_3: # Label of block must be emitted
-; IL32PC64-NEXT:    auipcc cs0, %captab_pcrel_hi(__stack_chk_guard)
+; IL32PC64-NEXT:    auipcc cs0, %got_pcrel_hi(__stack_chk_guard)
 ; IL32PC64-NEXT:    lc cs0, %pcrel_lo(.LBB0_3)(cs0)
 ; IL32PC64-NEXT:    lw a0, 0(cs0)
 ; IL32PC64-NEXT:    sw a0, 12(csp)
@@ -62,7 +62,7 @@ define void @caller() addrspace(200) nounwind sspstrong {
 ; L64PC128-NEXT:    sc cra, 32(csp) # 16-byte Folded Spill
 ; L64PC128-NEXT:    sc cs0, 16(csp) # 16-byte Folded Spill
 ; L64PC128-NEXT:  .LBB0_3: # Label of block must be emitted
-; L64PC128-NEXT:    auipcc cs0, %captab_pcrel_hi(__stack_chk_guard)
+; L64PC128-NEXT:    auipcc cs0, %got_pcrel_hi(__stack_chk_guard)
 ; L64PC128-NEXT:    lc cs0, %pcrel_lo(.LBB0_3)(cs0)
 ; L64PC128-NEXT:    ld a0, 0(cs0)
 ; L64PC128-NEXT:    sd a0, 8(csp)
diff --git a/llvm/test/CodeGen/RISCV/cheri/tls-models.ll b/llvm/test/CodeGen/RISCV/cheri/tls-models.ll
index 3274c24a2c353..29b32c01894bd 100644
--- a/llvm/test/CodeGen/RISCV/cheri/tls-models.ll
+++ b/llvm/test/CodeGen/RISCV/cheri/tls-models.ll
@@ -27,7 +27,7 @@ define i32 addrspace(200)* @f1() nounwind {
 ; IL32PC64-PIC-NEXT:    sc cra, 8(csp) # 8-byte Folded Spill
 ; IL32PC64-PIC-NEXT:  .LBB0_1: # %entry
 ; IL32PC64-PIC-NEXT:    # Label of block must be emitted
-; IL32PC64-PIC-NEXT:    auipcc ca0, %tls_gd_captab_pcrel_hi(unspecified)
+; IL32PC64-PIC-NEXT:    auipcc ca0, %tls_gd_pcrel_hi(unspecified)
 ; IL32PC64-PIC-NEXT:    cincoffset ca0, ca0, %pcrel_lo(.LBB0_1)
 ; IL32PC64-PIC-NEXT:    ccall __tls_get_addr
 ; IL32PC64-PIC-NEXT:    lc cra, 8(csp) # 8-byte Folded Reload
@@ -40,7 +40,7 @@ define i32 addrspace(200)* @f1() nounwind {
 ; L64PC128-PIC-NEXT:    sc cra, 0(csp) # 16-byte Folded Spill
 ; L64PC128-PIC-NEXT:  .LBB0_1: # %entry
 ; L64PC128-PIC-NEXT:    # Label of block must be emitted
-; L64PC128-PIC-NEXT:    auipcc ca0, %tls_gd_captab_pcrel_hi(unspecified)
+; L64PC128-PIC-NEXT:    auipcc ca0, %tls_gd_pcrel_hi(unspecified)
 ; L64PC128-PIC-NEXT:    cincoffset ca0, ca0, %pcrel_lo(.LBB0_1)
 ; L64PC128-PIC-NEXT:    ccall __tls_get_addr
 ; L64PC128-PIC-NEXT:    lc cra, 0(csp) # 16-byte Folded Reload
@@ -51,7 +51,7 @@ define i32 addrspace(200)* @f1() nounwind {
 ; IL32PC64-NOPIC:       # %bb.0: # %entry
 ; IL32PC64-NOPIC-NEXT:  .LBB0_1: # %entry
 ; IL32PC64-NOPIC-NEXT:    # Label of block must be emitted
-; IL32PC64-NOPIC-NEXT:    auipcc ca0, %tls_ie_captab_pcrel_hi(unspecified)
+; IL32PC64-NOPIC-NEXT:    auipcc ca0, %tls_ie_pcrel_hi(unspecified)
 ; IL32PC64-NOPIC-NEXT:    lw a0, %pcrel_lo(.LBB0_1)(ca0)
 ; IL32PC64-NOPIC-NEXT:    cincoffset ca0, ctp, a0
 ; IL32PC64-NOPIC-NEXT:    ret
@@ -60,7 +60,7 @@ define i32 addrspace(200)* @f1() nounwind {
 ; L64PC128-NOPIC:       # %bb.0: # %entry
 ; L64PC128-NOPIC-NEXT:  .LBB0_1: # %entry
 ; L64PC128-NOPIC-NEXT:    # Label of block must be emitted
-; L64PC128-NOPIC-NEXT:    auipcc ca0, %tls_ie_captab_pcrel_hi(unspecified)
+; L64PC128-NOPIC-NEXT:    auipcc ca0, %tls_ie_pcrel_hi(unspecified)
 ; L64PC128-NOPIC-NEXT:    ld a0, %pcrel_lo(.LBB0_1)(ca0)
 ; L64PC128-NOPIC-NEXT:    cincoffset ca0, ctp, a0
 ; L64PC128-NOPIC-NEXT:    ret
@@ -78,7 +78,7 @@ define i32 addrspace(200)* @f2() nounwind {
 ; IL32PC64-PIC-NEXT:    sc cra, 8(csp) # 8-byte Folded Spill
 ; IL32PC64-PIC-NEXT:  .LBB1_1: # %entry
 ; IL32PC64-PIC-NEXT:    # Label of block must be emitted
-; IL32PC64-PIC-NEXT:    auipcc ca0, %tls_gd_captab_pcrel_hi(ld)
+; IL32PC64-PIC-NEXT:    auipcc ca0, %tls_gd_pcrel_hi(ld)
 ; IL32PC64-PIC-NEXT:    cincoffset ca0, ca0, %pcrel_lo(.LBB1_1)
 ; IL32PC64-PIC-NEXT:    ccall __tls_get_addr
 ; IL32PC64-PIC-NEXT:    lc cra, 8(csp) # 8-byte Folded Reload
@@ -91,7 +91,7 @@ define i32 addrspace(200)* @f2() nounwind {
 ; L64PC128-PIC-NEXT:    sc cra, 0(csp) # 16-byte Folded Spill
 ; L64PC128-PIC-NEXT:  .LBB1_1: # %entry
 ; L64PC128-PIC-NEXT:    # Label of block must be emitted
-; L64PC128-PIC-NEXT:    auipcc ca0, %tls_gd_captab_pcrel_hi(ld)
+; L64PC128-PIC-NEXT:    auipcc ca0, %tls_gd_pcrel_hi(ld)
 ; L64PC128-PIC-NEXT:    cincoffset ca0, ca0, %pcrel_lo(.LBB1_1)
 ; L64PC128-PIC-NEXT:    ccall __tls_get_addr
 ; L64PC128-PIC-NEXT:    lc cra, 0(csp) # 16-byte Folded Reload
@@ -102,7 +102,7 @@ define i32 addrspace(200)* @f2() nounwind {
 ; IL32PC64-NOPIC:       # %bb.0: # %entry
 ; IL32PC64-NOPIC-NEXT:  .LBB1_1: # %entry
 ; IL32PC64-NOPIC-NEXT:    # Label of block must be emitted
-; IL32PC64-NOPIC-NEXT:    auipcc ca0, %tls_ie_captab_pcrel_hi(ld)
+; IL32PC64-NOPIC-NEXT:    auipcc ca0, %tls_ie_pcrel_hi(ld)
 ; IL32PC64-NOPIC-NEXT:    lw a0, %pcrel_lo(.LBB1_1)(ca0)
 ; IL32PC64-NOPIC-NEXT:    cincoffset ca0, ctp, a0
 ; IL32PC64-NOPIC-NEXT:    ret
@@ -111,7 +111,7 @@ define i32 addrspace(200)* @f2() nounwind {
 ; L64PC128-NOPIC:       # %bb.0: # %entry
 ; L64PC128-NOPIC-NEXT:  .LBB1_1: # %entry
 ; L64PC128-NOPIC-NEXT:    # Label of block must be emitted
-; L64PC128-NOPIC-NEXT:    auipcc ca0, %tls_ie_captab_pcrel_hi(ld)
+; L64PC128-NOPIC-NEXT:    auipcc ca0, %tls_ie_pcrel_hi(ld)
 ; L64PC128-NOPIC-NEXT:    ld a0, %pcrel_lo(.LBB1_1)(ca0)
 ; L64PC128-NOPIC-NEXT:    cincoffset ca0, ctp, a0
 ; L64PC128-NOPIC-NEXT:    ret
@@ -127,7 +127,7 @@ define i32 addrspace(200)* @f3() nounwind {
 ; IL32PC64-PIC:       # %bb.0: # %entry
 ; IL32PC64-PIC-NEXT:  .LBB2_1: # %entry
 ; IL32PC64-PIC-NEXT:    # Label of block must be emitted
-; IL32PC64-PIC-NEXT:    auipcc ca0, %tls_ie_captab_pcrel_hi(ie)
+; IL32PC64-PIC-NEXT:    auipcc ca0, %tls_ie_pcrel_hi(ie)
 ; IL32PC64-PIC-NEXT:    lw a0, %pcrel_lo(.LBB2_1)(ca0)
 ; IL32PC64-PIC-NEXT:    cincoffset ca0, ctp, a0
 ; IL32PC64-PIC-NEXT:    ret
@@ -136,7 +136,7 @@ define i32 addrspace(200)* @f3() nounwind {
 ; L64PC128-PIC:       # %bb.0: # %entry
 ; L64PC128-PIC-NEXT:  .LBB2_1: # %entry
 ; L64PC128-PIC-NEXT:    # Label of block must be emitted
-; L64PC128-PIC-NEXT:    auipcc ca0, %tls_ie_captab_pcrel_hi(ie)
+; L64PC128-PIC-NEXT:    auipcc ca0, %tls_ie_pcrel_hi(ie)
 ; L64PC128-PIC-NEXT:    ld a0, %pcrel_lo(.LBB2_1)(ca0)
 ; L64PC128-PIC-NEXT:    cincoffset ca0, ctp, a0
 ; L64PC128-PIC-NEXT:    ret
@@ -145,7 +145,7 @@ define i32 addrspace(200)* @f3() nounwind {
 ; IL32PC64-NOPIC:       # %bb.0: # %entry
 ; IL32PC64-NOPIC-NEXT:  .LBB2_1: # %entry
 ; IL32PC64-NOPIC-NEXT:    # Label of block must be emitted
-; IL32PC64-NOPIC-NEXT:    auipcc ca0, %tls_ie_captab_pcrel_hi(ie)
+; IL32PC64-NOPIC-NEXT:    auipcc ca0, %tls_ie_pcrel_hi(ie)
 ; IL32PC64-NOPIC-NEXT:    lw a0, %pcrel_lo(.LBB2_1)(ca0)
 ; IL32PC64-NOPIC-NEXT:    cincoffset ca0, ctp, a0
 ; IL32PC64-NOPIC-NEXT:    ret
@@ -154,7 +154,7 @@ define i32 addrspace(200)* @f3() nounwind {
 ; L64PC128-NOPIC:       # %bb.0: # %entry
 ; L64PC128-NOPIC-NEXT:  .LBB2_1: # %entry
 ; L64PC128-NOPIC-NEXT:    # Label of block must be emitted
-; L64PC128-NOPIC-NEXT:    auipcc ca0, %tls_ie_captab_pcrel_hi(ie)
+; L64PC128-NOPIC-NEXT:    auipcc ca0, %tls_ie_pcrel_hi(ie)
 ; L64PC128-NOPIC-NEXT:    ld a0, %pcrel_lo(.LBB2_1)(ca0)
 ; L64PC128-NOPIC-NEXT:    cincoffset ca0, ctp, a0
 ; L64PC128-NOPIC-NEXT:    ret
@@ -169,28 +169,28 @@ define i32 addrspace(200)* @f4() nounwind {
 ; IL32PC64-PIC-LABEL: f4:
 ; IL32PC64-PIC:       # %bb.0: # %entry
 ; IL32PC64-PIC-NEXT:    lui a0, %tprel_hi(le)
-; IL32PC64-PIC-NEXT:    cincoffset ca0, ctp, a0, %tprel_cincoffset(le)
+; IL32PC64-PIC-NEXT:    cincoffset ca0, ctp, a0, %tprel_add(le)
 ; IL32PC64-PIC-NEXT:    cincoffset ca0, ca0, %tprel_lo(le)
 ; IL32PC64-PIC-NEXT:    ret
 ;
 ; L64PC128-PIC-LABEL: f4:
 ; L64PC128-PIC:       # %bb.0: # %entry
 ; L64PC128-PIC-NEXT:    lui a0, %tprel_hi(le)
-; L64PC128-PIC-NEXT:    cincoffset ca0, ctp, a0, %tprel_cincoffset(le)
+; L64PC128-PIC-NEXT:    cincoffset ca0, ctp, a0, %tprel_add(le)
 ; L64PC128-PIC-NEXT:    cincoffset ca0, ca0, %tprel_lo(le)
 ; L64PC128-PIC-NEXT:    ret
 ;
 ; IL32PC64-NOPIC-LABEL: f4:
 ; IL32PC64-NOPIC:       # %bb.0: # %entry
 ; IL32PC64-NOPIC-NEXT:    lui a0, %tprel_hi(le)
-; IL32PC64-NOPIC-NEXT:    cincoffset ca0, ctp, a0, %tprel_cincoffset(le)
+; IL32PC64-NOPIC-NEXT:    cincoffset ca0, ctp, a0, %tprel_add(le)
 ; IL32PC64-NOPIC-NEXT:    cincoffset ca0, ca0, %tprel_lo(le)
 ; IL32PC64-NOPIC-NEXT:    ret
 ;
 ; L64PC128-NOPIC-LABEL: f4:
 ; L64PC128-NOPIC:       # %bb.0: # %entry
 ; L64PC128-NOPIC-NEXT:    lui a0, %tprel_hi(le)
-; L64PC128-NOPIC-NEXT:    cincoffset ca0, ctp, a0, %tprel_cincoffset(le)
+; L64PC128-NOPIC-NEXT:    cincoffset ca0, ctp, a0, %tprel_add(le)
 ; L64PC128-NOPIC-NEXT:    cincoffset ca0, ca0, %tprel_lo(le)
 ; L64PC128-NOPIC-NEXT:    ret
 entry:
diff --git a/llvm/test/Transforms/RelLookupTableConverter/cheri.ll b/llvm/test/Transforms/RelLookupTableConverter/cheri.ll
index 24265bf26c0fa..e540cb46f7775 100644
--- a/llvm/test/Transforms/RelLookupTableConverter/cheri.ll
+++ b/llvm/test/Transforms/RelLookupTableConverter/cheri.ll
@@ -63,7 +63,7 @@ define ptr addrspace(200) @load_from_string_table(i64 %idx) addrspace(200) {
 ; PURECAP-ASM:       # %bb.0: # %bb
 ; PURECAP-ASM-NEXT:  .LBB0_1: # %bb
 ; PURECAP-ASM-NEXT:    # Label of block must be emitted
-; PURECAP-ASM-NEXT:    auipcc ca1, %captab_pcrel_hi(global)
+; PURECAP-ASM-NEXT:    auipcc ca1, %got_pcrel_hi(global)
 ; PURECAP-ASM-NEXT:    lc ca1, %pcrel_lo(.LBB0_1)(ca1)
 ; PURECAP-ASM-NEXT:    slli a0, a0, 4
 ; PURECAP-ASM-NEXT:    cincoffset ca0, ca1, a0