Expected cutout. Gathered from "Final Result".

Andreu Bernad Serra · Andreu Bernad Serra · commit ff490d9e28f8 · 2021-04-16T10:38:39.000+02:00
diff --git a/doc/assy.rst b/doc/assy.rst
@@ -135,7 +135,7 @@ Next we want to instantiate all the components and add them to the assembly.
         .add(make_connector(), name="con_bl", color=cq.Color("black"))
         .add(make_connector(), name="con_br", color=cq.Color("black"))
         .add(
-            make_panel(W + SLOT_D, H + SLOT_D, PANEL_T),
+            make_panel(W + SLOT_D, H + SLOT_D, PANEL_T, SLOT_D),
             name="panel",
             color=cq.Color(0, 0, 1, 0.2),
         )

Original file line number	Diff line number	Diff line change
`@@ -135,7 +135,7 @@ Next we want to instantiate all the components and add them to the assembly.`
`135`	`135`	`.add(make_connector(), name="con_bl", color=cq.Color("black"))`
`136`	`136`	`.add(make_connector(), name="con_br", color=cq.Color("black"))`
`137`	`137`	`.add(`
`138`		`- make_panel(W + SLOT_D, H + SLOT_D, PANEL_T),`
	`138`	`+ make_panel(W + SLOT_D, H + SLOT_D, PANEL_T, SLOT_D),`
`139`	`139`	`name="panel",`
`140`	`140`	`color=cq.Color(0, 0, 1, 0.2),`
`141`	`141`	`)`