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[SystemZ] Fix address operand parsing incompatibilities with GAS
The LLVM AsmParser showed different behavior compared to GAS when parsing address operands in the following two ways: - If the address operand only has a single register (no comma), it is always interpreted as base register by GAS, even in the vector-index case (vgef etc.) This means the following is actually incorrect usage, as the base cannot be a vector register: vgef %v0, 0(%v1), 0. - GAS allows specifying a missing base register by using a comma after the first register, e.g. vgef %v0, 0(%v1,), 0.
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5 files changed

+58
-11
lines changed

5 files changed

+58
-11
lines changed

‎llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp‎

Lines changed: 14 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1071,9 +1071,16 @@ bool SystemZAsmParser::parseAddress(bool &HaveReg1, Register &Reg1,
10711071
if (getLexer().is(AsmToken::Integer)) {
10721072
if (parseIntegerRegister(Reg2, RegGR))
10731073
return true;
1074-
} else {
1075-
if (isParsingGNU() && parseRegister(Reg2, /*RequirePercent=*/true))
1076-
return true;
1074+
} else if (isParsingGNU()) {
1075+
if (Parser.getTok().is(AsmToken::Percent)) {
1076+
if (parseRegister(Reg2, /*RequirePercent=*/true))
1077+
return true;
1078+
} else {
1079+
// GAS allows ",)" to indicate a missing base register.
1080+
Reg2.Num = 0;
1081+
Reg2.Group = RegGR;
1082+
Reg2.StartLoc = Reg2.EndLoc = Parser.getTok().getLoc();
1083+
}
10771084
}
10781085
}
10791086

@@ -1186,6 +1193,10 @@ ParseStatus SystemZAsmParser::parseAddress(OperandVector &Operands,
11861193
if (!HaveReg1 || Reg1.Group != RegV)
11871194
return Error(StartLoc, "vector index required in address");
11881195
Index = SystemZMC::VR128Regs[Reg1.Num];
1196+
// In GAS mode, we must have Reg2, since a single register would be
1197+
// interpreted as base register, which cannot be a vector register.
1198+
if (isParsingGNU() && !HaveReg2)
1199+
return Error(Reg1.StartLoc, "invalid use of vector addressing");
11891200
// If we have Reg2, it must be an address register.
11901201
if (HaveReg2) {
11911202
if (parseAddressRegister(Reg2))

‎llvm/test/MC/SystemZ/insn-bad-z13.s‎

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1470,6 +1470,10 @@
14701470
#CHECK: vgef %v0, 0(%r1), 0
14711471
#CHECK: error: vector index required
14721472
#CHECK: vgef %v0, 0(%r2,%r1), 0
1473+
#CHECK: error: invalid use of vector addressing
1474+
#CHECK: vgef %v0, 0(%v1), 0
1475+
#CHECK: error: vector index required
1476+
#CHECK: vgef %v0, 0(,%v1), 0
14731477
#CHECK: error: invalid operand
14741478
#CHECK: vgef %v0, 0(%v0,%r1), -1
14751479
#CHECK: error: invalid operand
@@ -1481,6 +1485,8 @@
14811485

14821486
vgef %v0, 0(%r1), 0
14831487
vgef %v0, 0(%r2,%r1), 0
1488+
vgef %v0, 0(%v1), 0
1489+
vgef %v0, 0(,%v1), 0
14841490
vgef %v0, 0(%v0,%r1), -1
14851491
vgef %v0, 0(%v0,%r1), 4
14861492
vgef %v0, -1(%v0,%r1), 0
@@ -1490,6 +1496,10 @@
14901496
#CHECK: vgeg %v0, 0(%r1), 0
14911497
#CHECK: error: vector index required
14921498
#CHECK: vgeg %v0, 0(%r2,%r1), 0
1499+
#CHECK: error: invalid use of vector addressing
1500+
#CHECK: vgeg %v0, 0(%v1), 0
1501+
#CHECK: error: vector index required
1502+
#CHECK: vgeg %v0, 0(,%v1), 0
14931503
#CHECK: error: invalid operand
14941504
#CHECK: vgeg %v0, 0(%v0,%r1), -1
14951505
#CHECK: error: invalid operand
@@ -1501,6 +1511,8 @@
15011511

15021512
vgeg %v0, 0(%r1), 0
15031513
vgeg %v0, 0(%r2,%r1), 0
1514+
vgeg %v0, 0(%v1), 0
1515+
vgeg %v0, 0(,%v1), 0
15041516
vgeg %v0, 0(%v0,%r1), -1
15051517
vgeg %v0, 0(%v0,%r1), 2
15061518
vgeg %v0, -1(%v0,%r1), 0
@@ -2282,6 +2294,10 @@
22822294
#CHECK: vscef %v0, 0(%r1), 0
22832295
#CHECK: error: vector index required
22842296
#CHECK: vscef %v0, 0(%r2,%r1), 0
2297+
#CHECK: error: invalid use of vector addressing
2298+
#CHECK: vscef %v0, 0(%v1), 0
2299+
#CHECK: error: vector index required
2300+
#CHECK: vscef %v0, 0(,%v1), 0
22852301
#CHECK: error: invalid operand
22862302
#CHECK: vscef %v0, 0(%v0,%r1), -1
22872303
#CHECK: error: invalid operand
@@ -2293,6 +2309,8 @@
22932309

22942310
vscef %v0, 0(%r1), 0
22952311
vscef %v0, 0(%r2,%r1), 0
2312+
vscef %v0, 0(%v1), 0
2313+
vscef %v0, 0(,%v1), 0
22962314
vscef %v0, 0(%v0,%r1), -1
22972315
vscef %v0, 0(%v0,%r1), 4
22982316
vscef %v0, -1(%v0,%r1), 0
@@ -2302,6 +2320,10 @@
23022320
#CHECK: vsceg %v0, 0(%r1), 0
23032321
#CHECK: error: vector index required
23042322
#CHECK: vsceg %v0, 0(%r2,%r1), 0
2323+
#CHECK: error: invalid use of vector addressing
2324+
#CHECK: vsceg %v0, 0(%v1), 0
2325+
#CHECK: error: vector index required
2326+
#CHECK: vsceg %v0, 0(,%v1), 0
23052327
#CHECK: error: invalid operand
23062328
#CHECK: vsceg %v0, 0(%v0,%r1), -1
23072329
#CHECK: error: invalid operand
@@ -2313,6 +2335,8 @@
23132335

23142336
vsceg %v0, 0(%r1), 0
23152337
vsceg %v0, 0(%r2,%r1), 0
2338+
vsceg %v0, 0(%v1), 0
2339+
vsceg %v0, 0(,%v1), 0
23162340
vsceg %v0, 0(%v0,%r1), -1
23172341
vsceg %v0, 0(%v0,%r1), 2
23182342
vsceg %v0, -1(%v0,%r1), 0

‎llvm/test/MC/SystemZ/insn-good-z13.s‎

Lines changed: 14 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -2918,6 +2918,7 @@
29182918
vgbm %v31, 0
29192919
vgbm %v17, 0x1234
29202920

2921+
#CHECK: vgef %v0, 0(%v0,0), 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x13]
29212922
#CHECK: vgef %v0, 0(%v0,0), 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x13]
29222923
#CHECK: vgef %v0, 0(%v0,%r1), 0 # encoding: [0xe7,0x00,0x10,0x00,0x00,0x13]
29232924
#CHECK: vgef %v0, 0(%v0,%r1), 3 # encoding: [0xe7,0x00,0x10,0x00,0x30,0x13]
@@ -2943,7 +2944,8 @@
29432944
#CHECK: vgef %v31, 0(%v0,%r1), 0 # encoding: [0xe7,0xf0,0x10,0x00,0x08,0x13]
29442945
#CHECK: vgef %v10, 1000(%v19,%r7), 1 # encoding: [0xe7,0xa3,0x73,0xe8,0x14,0x13]
29452946

2946-
vgef %v0, 0(%v0), 0
2947+
vgef %v0, 0(%v0,), 0
2948+
vgef %v0, 0(%v0,0), 0
29472949
vgef %v0, 0(%v0,%r1), 0
29482950
vgef %v0, 0(%v0,%r1), 3
29492951
vgef %v0, 0(%v0,%r15), 0
@@ -2957,7 +2959,7 @@
29572959
vgef %v0, 0(%v0,1), 3
29582960
vgef %v0, 0(0,%r15), 0
29592961
vgef %v0, 0(%v15,1), 0
2960-
vgef 0, 0(0), 0
2962+
vgef 0, 0(0,), 0
29612963
vgef 0, 0(0,1), 0
29622964
vgef 0, 0(0,1), 3
29632965
vgef 0, 0(0,15), 0
@@ -2968,6 +2970,7 @@
29682970
vgef 31, 0(0,1), 0
29692971
vgef 10, 1000(19,7), 1
29702972

2973+
#CHECK: vgeg %v0, 0(%v0,0), 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x12]
29712974
#CHECK: vgeg %v0, 0(%v0,0), 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x12]
29722975
#CHECK: vgeg %v0, 0(%v0,%r1), 0 # encoding: [0xe7,0x00,0x10,0x00,0x00,0x12]
29732976
#CHECK: vgeg %v0, 0(%v0,%r1), 1 # encoding: [0xe7,0x00,0x10,0x00,0x10,0x12]
@@ -2993,7 +2996,8 @@
29932996
#CHECK: vgeg %v31, 0(%v0,%r1), 0 # encoding: [0xe7,0xf0,0x10,0x00,0x08,0x12]
29942997
#CHECK: vgeg %v10, 1000(%v19,%r7), 1 # encoding: [0xe7,0xa3,0x73,0xe8,0x14,0x12]
29952998

2996-
vgeg %v0, 0(%v0), 0
2999+
vgeg %v0, 0(%v0,), 0
3000+
vgeg %v0, 0(%v0,0), 0
29973001
vgeg %v0, 0(%v0,%r1), 0
29983002
vgeg %v0, 0(%v0,%r1), 1
29993003
vgeg %v0, 0(%v0,%r15), 0
@@ -3007,7 +3011,7 @@
30073011
vgeg %v0, 0(%v0,1), 1
30083012
vgeg %v0, 0(0,%r15), 0
30093013
vgeg %v0, 0(%v15,1), 0
3010-
vgeg 0, 0(0), 0
3014+
vgeg 0, 0(0,), 0
30113015
vgeg 0, 0(0,1), 0
30123016
vgeg 0, 0(0,1), 1
30133017
vgeg 0, 0(0,15), 0
@@ -5950,6 +5954,7 @@
59505954
vscbiq %v31, %v0, %v0
59515955
vscbiq %v18, %v3, %v20
59525956

5957+
#CHECK: vscef %v0, 0(%v0,0), 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x1b]
59535958
#CHECK: vscef %v0, 0(%v0,0), 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x1b]
59545959
#CHECK: vscef %v0, 0(%v0,%r1), 0 # encoding: [0xe7,0x00,0x10,0x00,0x00,0x1b]
59555960
#CHECK: vscef %v0, 0(%v0,%r1), 3 # encoding: [0xe7,0x00,0x10,0x00,0x30,0x1b]
@@ -5961,7 +5966,8 @@
59615966
#CHECK: vscef %v31, 0(%v0,%r1), 0 # encoding: [0xe7,0xf0,0x10,0x00,0x08,0x1b]
59625967
#CHECK: vscef %v10, 1000(%v19,%r7), 1 # encoding: [0xe7,0xa3,0x73,0xe8,0x14,0x1b]
59635968

5964-
vscef %v0, 0(%v0), 0
5969+
vscef %v0, 0(%v0,), 0
5970+
vscef %v0, 0(%v0,0), 0
59655971
vscef %v0, 0(%v0,%r1), 0
59665972
vscef %v0, 0(%v0,%r1), 3
59675973
vscef %v0, 0(%v0,%r15), 0
@@ -5972,6 +5978,7 @@
59725978
vscef %v31, 0(%v0,%r1), 0
59735979
vscef %v10, 1000(%v19,%r7), 1
59745980

5981+
#CHECK: vsceg %v0, 0(%v0,0), 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x1a]
59755982
#CHECK: vsceg %v0, 0(%v0,0), 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x1a]
59765983
#CHECK: vsceg %v0, 0(%v0,%r1), 0 # encoding: [0xe7,0x00,0x10,0x00,0x00,0x1a]
59775984
#CHECK: vsceg %v0, 0(%v0,%r1), 1 # encoding: [0xe7,0x00,0x10,0x00,0x10,0x1a]
@@ -5983,7 +5990,8 @@
59835990
#CHECK: vsceg %v31, 0(%v0,%r1), 0 # encoding: [0xe7,0xf0,0x10,0x00,0x08,0x1a]
59845991
#CHECK: vsceg %v10, 1000(%v19,%r7), 1 # encoding: [0xe7,0xa3,0x73,0xe8,0x14,0x1a]
59855992

5986-
vsceg %v0, 0(%v0), 0
5993+
vsceg %v0, 0(%v0,), 0
5994+
vsceg %v0, 0(%v0,0), 0
59875995
vsceg %v0, 0(%v0,%r1), 0
59885996
vsceg %v0, 0(%v0,%r1), 1
59895997
vsceg %v0, 0(%v0,%r15), 0

‎llvm/test/MC/SystemZ/insn-good.s‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -8918,6 +8918,8 @@
89188918
#CHECK: l %r0, 0(%r15,0) # encoding: [0x58,0x0f,0x00,0x00]
89198919
#CHECK: l %r0, 0(%r1,0) # encoding: [0x58,0x01,0x00,0x00]
89208920
#CHECK: l %r0, 0(%r15,0) # encoding: [0x58,0x0f,0x00,0x00]
8921+
#CHECK: l %r0, 0(%r1,0) # encoding: [0x58,0x01,0x00,0x00]
8922+
#CHECK: l %r0, 0(%r15,0) # encoding: [0x58,0x0f,0x00,0x00]
89218923
#CHECK: l %r0, 4095(%r15) # encoding: [0x58,0x00,0xff,0xff]
89228924
#CHECK: l %r0, 4095(%r1,%r15) # encoding: [0x58,0x01,0xff,0xff]
89238925
#CHECK: l %r0, 4095(%r15,0) # encoding: [0x58,0x0f,0x0f,0xff]
@@ -8937,6 +8939,8 @@
89378939
l %r0, 0(%r0,%r15)
89388940
l %r0, 0(0,%r1)
89398941
l %r0, 0(0,%r15)
8942+
l %r0, 0(%r1,)
8943+
l %r0, 0(%r15,)
89408944
l %r0, 0(%r1,0)
89418945
l %r0, 0(%r15,0)
89428946
l %r0, 0(%r1,%r0)

‎llvm/test/MC/SystemZ/tokens.s‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@
77
#CHECK: foo 100(, 200
88
#CHECK: error: invalid instruction
99
#CHECK: foo 100(200), 300
10-
#CHECK: error: register expected
10+
#CHECK: error: invalid instruction
1111
#CHECK: foo 100(200,), 300
1212
#CHECK: error: invalid instruction
1313
#CHECK: foo 100(200,%r1), 300
@@ -59,7 +59,7 @@
5959
#CHECK: foo {, 200
6060
#CHECK: error: invalid instruction
6161
#CHECK: foo 100(15), 300
62-
#CHECK: error: register expected
62+
#CHECK: error: invalid instruction
6363
#CHECK: foo 100(15,), 300
6464
#CHECK: error: invalid instruction
6565
#CHECK: foo 100(15,%r1), 300

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