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[Clang][LLVM][AArch64]Add support for svrint{32|64}{z|x} intrinsics
This patch add supports in Clang for these assembly intrinsics: FRINT32X FRINT32Z FRINT64X FRINT64Z By adding support for these intrinsics: // Variant is available for _f64 svfloat32_t svrint32x[_f32]_z(svbool_t pg, svfloat32_t zn); // Variant is available for _f64 svfloat32_t svrint32x[_f32]_x(svbool_t pg, svfloat32_t zn); // Variant is available for _f64 svfloat32_t svrint32x[_f32]_m(svfloat32_t inactive, svbool_t pg, svfloat32_t zn); // Variant is available for _f64 svfloat32_t svrint32z[_f32]_z(svbool_t pg, svfloat32_t zn); // Variant is available for _f64 svfloat32_t svrint32z[_f32]_x(svbool_t pg, svfloat32_t zn); // Variant is available for _f64 svfloat32_t svrint32z[_f32]_m(svfloat32_t inactive, svbool_t pg, svfloat32_t zn); // Variant is available for _f64 svfloat32_t svrint64x[_f32]_z(svbool_t pg, svfloat32_t zn); // Variant is available for _f64 svfloat32_t svrint64x[_f32]_x(svbool_t pg, svfloat32_t zn); // Variant is available for _f64 svfloat32_t svrint64x[_f32]_m(svfloat32_t inactive, svbool_t pg, svfloat32_t zn); // Variant is available for _f64 svfloat32_t svrint64z[_f32]_z(svbool_t pg, svfloat32_t zn); // Variant is available for _f64 svfloat32_t svrint64z[_f32]_x(svbool_t pg, svfloat32_t zn); // Variant is available for _f64 svfloat32_t svrint64z[_f32]_m(svfloat32_t inactive, svbool_t pg, svfloat32_t zn); ``` according to the ACLE[1] [1]ARM-software/acle#412
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‎clang/include/clang/Basic/arm_sve.td‎

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -778,6 +778,13 @@ defm SVRINTX : SInstZPZ<"svrintx", "hfd", "aarch64_sve_frintx">;
778778
defm SVRINTZ : SInstZPZ<"svrintz", "hfd", "aarch64_sve_frintz">;
779779
defm SVSQRT : SInstZPZ<"svsqrt", "hfd", "aarch64_sve_fsqrt">;
780780

781+
let SVETargetGuard = "sve2p2|sme2p2", SMETargetGuard = "sve2p2|sme2p2" in {
782+
defm SVRINT32X : SInstZPZ<"svrint32x", "fd", "aarch64_sve_frint32x">;
783+
defm SVRINT32Z : SInstZPZ<"svrint32z", "fd", "aarch64_sve_frint32z">;
784+
defm SVRINT64X : SInstZPZ<"svrint64x", "fd", "aarch64_sve_frint64x">;
785+
defm SVRINT64Z : SInstZPZ<"svrint64z", "fd", "aarch64_sve_frint64z">;
786+
}
787+
781788
let SMETargetGuard = "sme2,ssve-fexpa" in {
782789
def SVEXPA : SInst<"svexpa[_{d}]", "du", "hfd", MergeNone, "aarch64_sve_fexpa_x", [VerifyRuntimeMode]>;
783790
}

‎clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c‎

Lines changed: 445 additions & 0 deletions
Large diffs are not rendered by default.

‎llvm/include/llvm/IR/IntrinsicsAArch64.td‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2155,6 +2155,10 @@ def int_aarch64_sve_frintn : AdvSIMD_Merged1VectorArg_Intrinsic;
21552155
def int_aarch64_sve_frintp : AdvSIMD_Merged1VectorArg_Intrinsic;
21562156
def int_aarch64_sve_frintx : AdvSIMD_Merged1VectorArg_Intrinsic;
21572157
def int_aarch64_sve_frintz : AdvSIMD_Merged1VectorArg_Intrinsic;
2158+
def int_aarch64_sve_frint32x : AdvSIMD_Merged1VectorArg_Intrinsic;
2159+
def int_aarch64_sve_frint32z : AdvSIMD_Merged1VectorArg_Intrinsic;
2160+
def int_aarch64_sve_frint64x : AdvSIMD_Merged1VectorArg_Intrinsic;
2161+
def int_aarch64_sve_frint64z : AdvSIMD_Merged1VectorArg_Intrinsic;
21582162
def int_aarch64_sve_frsqrte_x : AdvSIMD_1VectorArg_Intrinsic;
21592163
def int_aarch64_sve_frsqrts_x : AdvSIMD_2VectorArg_Intrinsic;
21602164
def int_aarch64_sve_fscale : AdvSIMD_SVE_SCALE_Intrinsic;

‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp‎

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -271,9 +271,13 @@ static bool isMergePassthruOpcode(unsigned Opc) {
271271
case AArch64ISD::FFLOOR_MERGE_PASSTHRU:
272272
case AArch64ISD::FNEARBYINT_MERGE_PASSTHRU:
273273
case AArch64ISD::FRINT_MERGE_PASSTHRU:
274+
case AArch64ISD::FRINT32_MERGE_PASSTHRU:
275+
case AArch64ISD::FRINT64_MERGE_PASSTHRU:
274276
case AArch64ISD::FROUND_MERGE_PASSTHRU:
275277
case AArch64ISD::FROUNDEVEN_MERGE_PASSTHRU:
276278
case AArch64ISD::FTRUNC_MERGE_PASSTHRU:
279+
case AArch64ISD::FTRUNC32_MERGE_PASSTHRU:
280+
case AArch64ISD::FTRUNC64_MERGE_PASSTHRU:
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case AArch64ISD::FP_ROUND_MERGE_PASSTHRU:
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case AArch64ISD::FP_EXTEND_MERGE_PASSTHRU:
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case AArch64ISD::SINT_TO_FP_MERGE_PASSTHRU:
@@ -6610,6 +6614,14 @@ SDValue AArch64TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
66106614
case Intrinsic::aarch64_sve_frintx:
66116615
return DAG.getNode(AArch64ISD::FRINT_MERGE_PASSTHRU, DL, Op.getValueType(),
66126616
Op.getOperand(2), Op.getOperand(3), Op.getOperand(1));
6617+
case Intrinsic::aarch64_sve_frint32x:
6618+
return DAG.getNode(AArch64ISD::FRINT32_MERGE_PASSTHRU, DL,
6619+
Op.getValueType(), Op.getOperand(2), Op.getOperand(3),
6620+
Op.getOperand(1));
6621+
case Intrinsic::aarch64_sve_frint64x:
6622+
return DAG.getNode(AArch64ISD::FRINT64_MERGE_PASSTHRU, DL,
6623+
Op.getValueType(), Op.getOperand(2), Op.getOperand(3),
6624+
Op.getOperand(1));
66136625
case Intrinsic::aarch64_sve_frinta:
66146626
return DAG.getNode(AArch64ISD::FROUND_MERGE_PASSTHRU, DL, Op.getValueType(),
66156627
Op.getOperand(2), Op.getOperand(3), Op.getOperand(1));
@@ -6620,6 +6632,14 @@ SDValue AArch64TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
66206632
case Intrinsic::aarch64_sve_frintz:
66216633
return DAG.getNode(AArch64ISD::FTRUNC_MERGE_PASSTHRU, DL, Op.getValueType(),
66226634
Op.getOperand(2), Op.getOperand(3), Op.getOperand(1));
6635+
case Intrinsic::aarch64_sve_frint32z:
6636+
return DAG.getNode(AArch64ISD::FTRUNC32_MERGE_PASSTHRU, DL,
6637+
Op.getValueType(), Op.getOperand(2), Op.getOperand(3),
6638+
Op.getOperand(1));
6639+
case Intrinsic::aarch64_sve_frint64z:
6640+
return DAG.getNode(AArch64ISD::FTRUNC64_MERGE_PASSTHRU, DL,
6641+
Op.getValueType(), Op.getOperand(2), Op.getOperand(3),
6642+
Op.getOperand(1));
66236643
case Intrinsic::aarch64_sve_ucvtf:
66246644
return DAG.getNode(AArch64ISD::UINT_TO_FP_MERGE_PASSTHRU, DL,
66256645
Op.getValueType(), Op.getOperand(2), Op.getOperand(3),

‎llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td‎

Lines changed: 12 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -290,9 +290,13 @@ def AArch64frintp_mt : SDNode<"AArch64ISD::FCEIL_MERGE_PASSTHRU", SDT_AArch64Ari
290290
def AArch64frintm_mt : SDNode<"AArch64ISD::FFLOOR_MERGE_PASSTHRU", SDT_AArch64Arith>;
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def AArch64frinti_mt : SDNode<"AArch64ISD::FNEARBYINT_MERGE_PASSTHRU", SDT_AArch64Arith>;
292292
def AArch64frintx_mt : SDNode<"AArch64ISD::FRINT_MERGE_PASSTHRU", SDT_AArch64Arith>;
293+
def AArch64frint32x_mt : SDNode<"AArch64ISD::FRINT32_MERGE_PASSTHRU", SDT_AArch64Arith>;
294+
def AArch64frint64x_mt : SDNode<"AArch64ISD::FRINT64_MERGE_PASSTHRU", SDT_AArch64Arith>;
293295
def AArch64frinta_mt : SDNode<"AArch64ISD::FROUND_MERGE_PASSTHRU", SDT_AArch64Arith>;
294296
def AArch64frintn_mt : SDNode<"AArch64ISD::FROUNDEVEN_MERGE_PASSTHRU", SDT_AArch64Arith>;
295297
def AArch64frintz_mt : SDNode<"AArch64ISD::FTRUNC_MERGE_PASSTHRU", SDT_AArch64Arith>;
298+
def AArch64frint32z_mt : SDNode<"AArch64ISD::FTRUNC32_MERGE_PASSTHRU", SDT_AArch64Arith>;
299+
def AArch64frint64z_mt : SDNode<"AArch64ISD::FTRUNC64_MERGE_PASSTHRU", SDT_AArch64Arith>;
296300
def AArch64fsqrt_mt : SDNode<"AArch64ISD::FSQRT_MERGE_PASSTHRU", SDT_AArch64Arith>;
297301
def AArch64frecpx_mt : SDNode<"AArch64ISD::FRECPX_MERGE_PASSTHRU", SDT_AArch64Arith>;
298302
def AArch64rbit_mt : SDNode<"AArch64ISD::BITREVERSE_MERGE_PASSTHRU", SDT_AArch64Arith>;
@@ -4611,15 +4615,15 @@ let Predicates = [HasSVE2p2_or_SME2p2] in {
46114615

46124616
// Floating point round to integral fp value in integer size range
46134617
// Merging
4614-
defm FRINT32Z_ZPmZ : sve_fp_2op_p_zd_frint<0b00, "frint32z">;
4615-
defm FRINT32X_ZPmZ : sve_fp_2op_p_zd_frint<0b01, "frint32x">;
4616-
defm FRINT64X_ZPmZ : sve_fp_2op_p_zd_frint<0b10, "frint64z">;
4617-
defm FRINT64Z_ZPmZ : sve_fp_2op_p_zd_frint<0b11, "frint64x">;
4618+
defm FRINT32Z_ZPmZ : sve_fp_2op_p_zd_frint<0b00, "frint32z", AArch64frint32z_mt>;
4619+
defm FRINT32X_ZPmZ : sve_fp_2op_p_zd_frint<0b01, "frint32x", AArch64frint32x_mt>;
4620+
defm FRINT64Z_ZPmZ : sve_fp_2op_p_zd_frint<0b10, "frint64z", AArch64frint64z_mt>;
4621+
defm FRINT64X_ZPmZ : sve_fp_2op_p_zd_frint<0b11, "frint64x", AArch64frint64x_mt>;
46184622
// Zeroing
4619-
defm FRINT32Z_ZPzZ : sve_fp_z2op_p_zd_frint<0b00, "frint32z">;
4620-
defm FRINT32X_ZPzZ : sve_fp_z2op_p_zd_frint<0b01, "frint32x">;
4621-
defm FRINT64Z_ZPzZ : sve_fp_z2op_p_zd_frint<0b10, "frint64z">;
4622-
defm FRINT64X_ZPzZ : sve_fp_z2op_p_zd_frint<0b11, "frint64x">;
4623+
defm FRINT32Z_ZPzZ : sve_fp_z2op_p_zd_frint<0b00, "frint32z", AArch64frint32z_mt>;
4624+
defm FRINT32X_ZPzZ : sve_fp_z2op_p_zd_frint<0b01, "frint32x", AArch64frint32x_mt>;
4625+
defm FRINT64Z_ZPzZ : sve_fp_z2op_p_zd_frint<0b10, "frint64z", AArch64frint64z_mt>;
4626+
defm FRINT64X_ZPzZ : sve_fp_z2op_p_zd_frint<0b11, "frint64x", AArch64frint64x_mt>;
46234627

46244628
// Floating-point round to integral fp value, zeroing predicate
46254629
defm FRINTN_ZPzZ : sve_fp_z2op_p_zd_hsd<0b00000, "frintn", AArch64frintn_mt>;

‎llvm/lib/Target/AArch64/SVEInstrFormats.td‎

Lines changed: 17 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3249,9 +3249,20 @@ multiclass sve2_fp_convert_down_odd_rounding<string asm, string op, SDPatternOpe
32493249
def : SVE_1_Op_Passthru_Pat<nxv2f32, ir_op, nxv2i1, nxv2f64, !cast<Instruction>(NAME # _DtoS)>;
32503250
}
32513251

3252-
multiclass sve_fp_2op_p_zd_frint<bits<2> opc, string asm> {
3252+
multiclass sve_fp_2op_p_zd_frint<bits<2> opc, string asm, SDPatternOperator op = null_frag> {
32533253
def _S : sve_fp_2op_p_zd<{ 0b0010, opc{1}, 0, opc{0} }, asm, ZPR32, ZPR32, ElementSizeS>;
32543254
def _D : sve_fp_2op_p_zd<{ 0b0010, opc{1}, 1, opc{0} }, asm, ZPR64, ZPR64, ElementSizeD>;
3255+
3256+
def : SVE_1_Op_Passthru_Pat<nxv4f32, op, nxv4i1, nxv4f32, !cast<Instruction>(NAME # _S)>;
3257+
def : SVE_1_Op_Passthru_Pat<nxv2f32, op, nxv2i1, nxv2f32, !cast<Instruction>(NAME # _S)>;
3258+
def : SVE_1_Op_Passthru_Pat<nxv2f64, op, nxv2i1, nxv2f64, !cast<Instruction>(NAME # _D)>;
3259+
3260+
def _S_UNDEF : PredOneOpPassthruPseudo<NAME # _S, ZPR32>;
3261+
def _D_UNDEF : PredOneOpPassthruPseudo<NAME # _D, ZPR64>;
3262+
3263+
defm : SVE_1_Op_PassthruUndef_Pat<nxv4f32, op, nxv4i1, nxv4f32, !cast<Instruction>(NAME # _S_UNDEF)>;
3264+
defm : SVE_1_Op_PassthruUndef_Pat<nxv2f32, op, nxv2i1, nxv2f32, !cast<Instruction>(NAME # _S_UNDEF)>;
3265+
defm : SVE_1_Op_PassthruUndef_Pat<nxv2f64, op, nxv2i1, nxv2f64, !cast<Instruction>(NAME # _D_UNDEF)>;
32553266
}
32563267

32573268
//===----------------------------------------------------------------------===//
@@ -3334,9 +3345,13 @@ multiclass sve_fp_z2op_p_zd_hsd<bits<5> opc, string asm, SDPatternOperator op> {
33343345
defm : SVE_1_Op_PassthruUndefZero_Pat<nxv2f64, op, nxv2i1, nxv2f64, !cast<Instruction>(NAME # _D)>;
33353346
}
33363347

3337-
multiclass sve_fp_z2op_p_zd_frint<bits<2> opc, string asm> {
3348+
multiclass sve_fp_z2op_p_zd_frint<bits<2> opc, string asm, SDPatternOperator op = null_frag> {
33383349
def _S : sve_fp_z2op_p_zd<{ 0b0010, opc{1}, 0, opc{0} }, asm, ZPR32, ZPR32>;
33393350
def _D : sve_fp_z2op_p_zd<{ 0b0010, opc{1}, 1, opc{0} }, asm, ZPR64, ZPR64>;
3351+
3352+
defm : SVE_1_Op_PassthruUndefZero_Pat<nxv4f32, op, nxv4i1, nxv4f32, !cast<Instruction>(NAME # _S)>;
3353+
defm : SVE_1_Op_PassthruUndefZero_Pat<nxv2f32, op, nxv2i1, nxv2f32, !cast<Instruction>(NAME # _S)>;
3354+
defm : SVE_1_Op_PassthruUndefZero_Pat<nxv2f64, op, nxv2i1, nxv2f64, !cast<Instruction>(NAME # _D)>;
33403355
}
33413356

33423357
multiclass sve_fp_z2op_p_zd_bfcvt<string asm, SDPatternOperator op> {

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