11diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
2- index 5038f8a1f..fe9d45a82 100644
2+ index e921ced83..d79182061 100644
33--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
44+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
5- @@ -146,6 +146,12 @@ static cl::opt<bool> EnableVectorFCopySignExtendRound(
5+ @@ -153,6 +153,13 @@ static cl::opt<bool> EnableVectorFCopySignExtendRound(
6+ "combiner-vector-fcopysign-extend-round", cl::Hidden, cl::init(false),
67 cl::desc(
78 "Enable merging extends and rounds into FCOPYSIGN on vector types"));
8-
9+ +
910+ static cl::opt<bool> EnableLoadCombine(
1011+ "combiner-load-merging", cl::Hidden, cl::init(true),
1112+ cl::desc("DAG combine enable merging multiple loads "
@@ -15,7 +16,7 @@ index 5038f8a1f..fe9d45a82 100644
1516 namespace {
1617
1718 class DAGCombiner {
18- @@ -8874 ,6 +8880 ,9 @@ static SDValue stripTruncAndExt(SDValue Value) {
19+ @@ -9053 ,6 +9060 ,9 @@ static SDValue stripTruncAndExt(SDValue Value) {
1920 /// =>
2021 /// *((i32)p) = BSWAP(val);
2122 SDValue DAGCombiner::mergeTruncStores(StoreSDNode *N) {
@@ -25,7 +26,7 @@ index 5038f8a1f..fe9d45a82 100644
2526 // The matching looks for "store (trunc x)" patterns that appear early but are
2627 // likely to be replaced by truncating store nodes during combining.
2728 // TODO: If there is evidence that running this later would help, this
28- @@ -9092 ,6 +9101 ,9 @@ SDValue DAGCombiner::MatchLoadCombine(SDNode *N) {
29+ @@ -9277 ,6 +9287 ,9 @@ SDValue DAGCombiner::MatchLoadCombine(SDNode *N) {
2930 assert(N->getOpcode() == ISD::OR &&
3031 "Can only match load combining against OR nodes");
3132
@@ -36,10 +37,10 @@ index 5038f8a1f..fe9d45a82 100644
3637 EVT VT = N->getValueType(0);
3738 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
3839diff --git a/llvm/lib/Transforms/Scalar/SROA.cpp b/llvm/lib/Transforms/Scalar/SROA.cpp
39- index 17a94f938..623a22913 100644
40+ index e88c130cc..983a7e2b1 100644
4041--- a/llvm/lib/Transforms/Scalar/SROA.cpp
4142+++ b/llvm/lib/Transforms/Scalar/SROA.cpp
42- @@ -123 ,6 +123 ,10 @@ static cl::opt<bool> SROAStrictInbounds("sroa-strict-inbounds", cl::init(false),
43+ @@ -120 ,6 +120 ,10 @@ STATISTIC(NumVectorized, "Number of vectorized aggregates");
4344 /// Disable running mem2reg during SROA in order to test or debug SROA.
4445 static cl::opt<bool> SROASkipMem2Reg("sroa-skip-mem2reg", cl::init(false),
4546 cl::Hidden);
@@ -50,7 +51,7 @@ index 17a94f938..623a22913 100644
5051 namespace {
5152
5253 class AllocaSliceRewriter;
53- @@ -1232 ,6 +1236 ,11 @@ private:
54+ @@ -1190 ,6 +1194 ,11 @@ private:
5455 if (!IsOffsetKnown)
5556 return PI.setAborted(&II);
5657
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