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fpoussinfpoussin
authored
Merge pull request #420 from dynfer/pr
Support for H7 LTDC and SDRAM
2 parents 057ecd3 + 920bb8c commit 5668ae1

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6 files changed

+65
-9
lines changed

6 files changed

+65
-9
lines changed

‎os/hal/include/hal_fsmc.h‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -43,7 +43,7 @@
4343
defined(STM32F745xx) || defined(STM32F746xx) || \
4444
defined(STM32F756xx) || defined(STM32F767xx) || \
4545
defined(STM32F769xx) || defined(STM32F777xx) || \
46-
defined(STM32F779xx))
46+
defined(STM32F779xx) || defined(STM32H743xx))
4747
#if !defined(FSMC_Bank1_R_BASE)
4848
#define FSMC_Bank1_R_BASE (FMC_R_BASE + 0x0000)
4949
#endif
@@ -89,7 +89,7 @@
8989
#define FSMC_Bank4_MAP_BASE ((uint32_t) 0x90000000)
9090
#if (defined(STM32F427xx) || defined(STM32F437xx) || \
9191
defined(STM32F429xx) || defined(STM32F439xx) || \
92-
defined(STM32F7))
92+
defined(STM32F7) || defined(STM32H743xx))
9393
#define FSMC_Bank5_MAP_BASE ((uint32_t) 0xC0000000)
9494
#define FSMC_Bank6_MAP_BASE ((uint32_t) 0xD0000000)
9595
#endif
@@ -167,7 +167,7 @@ typedef struct {
167167

168168
#if (defined(STM32F427xx) || defined(STM32F437xx) || \
169169
defined(STM32F429xx) || defined(STM32F439xx) || \
170-
defined(STM32F7))
170+
defined(STM32F7) || defined(STM32H743xx))
171171

172172
typedef struct {
173173
__IO uint32_t SDCR1; /**< SDRAM control register (bank 1) */
@@ -221,7 +221,7 @@ typedef struct {
221221
#define FSMC_BCR_MWID_16 ((uint32_t)1 << 4)
222222
#if (defined(STM32F427xx) || defined(STM32F437xx) || \
223223
defined(STM32F429xx) || defined(STM32F439xx) || \
224-
defined(STM32F7))
224+
defined(STM32F7) || defined(STM32H743xx))
225225
#define FSMC_BCR_MWID_32 ((uint32_t)2 << 4)
226226
#else
227227
#define FSMC_BCR_MWID_RESERVED1 ((uint32_t)2 << 4)
@@ -239,7 +239,7 @@ typedef struct {
239239
#define FSMC_BCR_CBURSTRW ((uint32_t)1 << 19)
240240
#if (defined(STM32F427xx) || defined(STM32F437xx) || \
241241
defined(STM32F429xx) || defined(STM32F439xx) || \
242-
defined(STM32F7))
242+
defined(STM32F7) || defined(STM32H743xx))
243243
#define FSMC_BCR_CCLKEN ((uint32_t)1 << 20)
244244
#endif
245245
#if (defined(STM32F7))
@@ -330,7 +330,7 @@ struct FSMCDriver {
330330

331331
#if (defined(STM32F427xx) || defined(STM32F437xx) || \
332332
defined(STM32F429xx) || defined(STM32F439xx) || \
333-
defined(STM32F7))
333+
defined(STM32F7) || defined(STM32H743xx))
334334
#if HAL_USE_SDRAM
335335
FSMC_SDRAM_TypeDef *sdram;
336336
#endif

‎os/hal/ports/STM32/LLD/DMA2Dv1/hal_stm32_dma2d.c‎

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -98,46 +98,70 @@ OSAL_IRQ_HANDLER(STM32_DMA2D_HANDLER) {
9898
if (dma2dp->config->cfgerr_isr != NULL)
9999
dma2dp->config->cfgerr_isr(dma2dp);
100100
job_done = true;
101+
#if defined(STM32H743xx)
102+
DMA2D->IFCR |= DMA2D_IFCR_CCEIF;
103+
#else
101104
DMA2D->IFCR |= DMA2D_IFSR_CCEIF;
105+
#endif
102106
}
103107

104108
/* Handle CLUT (Palette) Transfer Complete ISR.*/
105109
if ((DMA2D->ISR & DMA2D_ISR_CTCIF) && (DMA2D->CR & DMA2D_CR_CTCIE)) {
106110
if (dma2dp->config->paltrfdone_isr != NULL)
107111
dma2dp->config->paltrfdone_isr(dma2dp);
108112
job_done = true;
113+
#if defined(STM32H743xx)
114+
DMA2D->IFCR |= DMA2D_IFCR_CCTCIF;
115+
#else
109116
DMA2D->IFCR |= DMA2D_IFSR_CCTCIF;
117+
#endif
110118
}
111119

112120
/* Handle CLUT (Palette) Access Error ISR.*/
113121
if ((DMA2D->ISR & DMA2D_ISR_CAEIF) && (DMA2D->CR & DMA2D_CR_CAEIE)) {
114122
if (dma2dp->config->palacserr_isr != NULL)
115123
dma2dp->config->palacserr_isr(dma2dp);
116124
job_done = true;
125+
#if defined(STM32H743xx)
126+
DMA2D->IFCR |= DMA2D_ISR_CAEIF;
127+
#else
117128
DMA2D->IFCR |= DMA2D_IFSR_CCAEIF;
129+
#endif
118130
}
119131

120132
/* Handle Transfer Watermark ISR.*/
121133
if ((DMA2D->ISR & DMA2D_ISR_TWIF) && (DMA2D->CR & DMA2D_CR_TWIE)) {
122134
if (dma2dp->config->trfwmark_isr != NULL)
123135
dma2dp->config->trfwmark_isr(dma2dp);
136+
#if defined(STM32H743xx)
137+
DMA2D->IFCR |= DMA2D_IFCR_CTWIF;
138+
#else
124139
DMA2D->IFCR |= DMA2D_IFSR_CTWIF;
140+
#endif
125141
}
126142

127143
/* Handle Transfer Complete ISR.*/
128144
if ((DMA2D->ISR & DMA2D_ISR_TCIF) && (DMA2D->CR & DMA2D_CR_TCIE)) {
129145
if (dma2dp->config->trfdone_isr != NULL)
130146
dma2dp->config->trfdone_isr(dma2dp);
131147
job_done = true;
148+
#if defined(STM32H743xx)
149+
DMA2D->IFCR |= DMA2D_IFCR_CTCIF;
150+
#else
132151
DMA2D->IFCR |= DMA2D_IFSR_CTCIF;
152+
#endif
133153
}
134154

135155
/* Handle Transfer Error ISR.*/
136156
if ((DMA2D->ISR & DMA2D_ISR_TEIF) && (DMA2D->CR & DMA2D_CR_TEIE)) {
137157
if (dma2dp->config->trferr_isr != NULL)
138158
dma2dp->config->trferr_isr(dma2dp);
139159
job_done = true;
160+
#if defined(STM32H743xx)
161+
DMA2D->IFCR |= DMA2D_IFCR_CTEIF;
162+
#else
140163
DMA2D->IFCR |= DMA2D_IFSR_CTEIF;
164+
#endif
141165
}
142166

143167
if (job_done) {

‎os/hal/ports/STM32/LLD/FSMCv1/hal_sdram_lld.c‎

Lines changed: 21 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -32,7 +32,7 @@
3232
defined(STM32F745xx) || defined(STM32F746xx) || \
3333
defined(STM32F756xx) || defined(STM32F767xx) || \
3434
defined(STM32F769xx) || defined(STM32F777xx) || \
35-
defined(STM32F779xx))
35+
defined(STM32F779xx) || defined(STM32H743xx))
3636

3737
#if (HAL_USE_SDRAM == TRUE) || defined(__DOXYGEN__)
3838

@@ -78,10 +78,12 @@ SDRAMDriver SDRAMD1;
7878
*
7979
* @notapi
8080
*/
81+
#if !defined(STM32H743xx) // H7xx has no busy flag
8182
static void sdram_lld_wait_ready(void) {
8283
/* Wait until the SDRAM controller is ready */
8384
while (SDRAMD1.sdram->SDSR & FMC_SDSR_BUSY);
8485
}
86+
#endif
8587

8688
/**
8789
* @brief Executes the SDRAM memory initialization sequence.
@@ -102,36 +104,50 @@ static void sdram_lld_init_sequence(const SDRAMConfig *cfgp) {
102104
#endif
103105

104106
/* Step 3: Configure a clock configuration enable command.*/
107+
#if !defined(STM32H743xx)
105108
sdram_lld_wait_ready();
109+
#endif
106110
SDRAMD1.sdram->SDCMR = FMCCM_CLK_ENABLED | command_target;
107111

108112
/* Step 4: Insert delay (tipically 100uS).*/
109113
osalSysPolledDelayX(OSAL_US2RTC(STM32_HCLK, 100));
110114

111115
/* Step 5: Configure a PALL (precharge all) command.*/
116+
#if !defined(STM32H743xx)
112117
sdram_lld_wait_ready();
118+
#endif
113119
SDRAMD1.sdram->SDCMR = FMCCM_PALL | command_target;
114120

115121
/* Step 6.1: Configure a Auto-Refresh command: send the first command.*/
122+
#if !defined(STM32H743xx)
116123
sdram_lld_wait_ready();
124+
#endif
117125
SDRAMD1.sdram->SDCMR = FMCCM_AUTO_REFRESH | command_target |
118126
(cfgp->sdcmr & FMC_SDCMR_NRFS);
119127

120128
/* Step 6.2: Send the second command.*/
129+
#if !defined(STM32H743xx)
121130
sdram_lld_wait_ready();
131+
#endif;
122132
SDRAMD1.sdram->SDCMR = FMCCM_AUTO_REFRESH | command_target |
123133
(cfgp->sdcmr & FMC_SDCMR_NRFS);
124134

125135
/* Step 7: Program the external memory mode register.*/
136+
#if !defined(STM32H743xx)
126137
sdram_lld_wait_ready();
138+
#endif
127139
SDRAMD1.sdram->SDCMR = FMCCM_LOAD_MODE | command_target |
128140
(cfgp->sdcmr & FMC_SDCMR_MRD);
129141

130142
/* Step 8: Set clock.*/
143+
#if !defined(STM32H743xx)
131144
sdram_lld_wait_ready();
145+
#endif
132146
SDRAMD1.sdram->SDRTR = cfgp->sdrtr & FMC_SDRTR_COUNT;
133147

148+
#if !defined(STM32H743xx)
134149
sdram_lld_wait_ready();
150+
#endif
135151
}
136152

137153
/*===========================================================================*/
@@ -149,6 +165,10 @@ void sdram_lld_start(SDRAMDriver *sdramp, const SDRAMConfig *cfgp)
149165
sdramp->sdram->SDCR2 = cfgp->sdcr;
150166
sdramp->sdram->SDTR2 = cfgp->sdtr;
151167

168+
#if defined(STM32H743xx)
169+
FMC_Bank1_R->BTCR[0] |= FMC_BCR1_FMCEN;
170+
#endif
171+
152172
sdram_lld_init_sequence(cfgp);
153173
}
154174

‎os/hal/ports/STM32/LLD/FSMCv1/hal_sdram_lld.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -83,7 +83,7 @@
8383
defined(STM32F745xx) || defined(STM32F746xx) || \
8484
defined(STM32F756xx) || defined(STM32F767xx) || \
8585
defined(STM32F769xx) || defined(STM32F777xx) || \
86-
defined(STM32F779xx))
86+
defined(STM32F779xx) || defined(STM32H743xx))
8787
#else
8888
#error "Device is not compatible with SDRAM"
8989
#endif

‎os/hal/ports/STM32/LLD/LTDCv1/hal_stm32_ltdc.c‎

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -233,7 +233,11 @@ void ltdcInit(void) {
233233
rccResetLTDC();
234234

235235
/* Enable the LTDC clock.*/
236+
#if defined(STM32H743xx)
237+
RCC->D1CFGR = (RCC->D1CFGR & ~(0x3U << 16U)) | (2 << 16);
238+
#else
236239
RCC->DCKCFGR = (RCC->DCKCFGR & ~RCC_DCKCFGR_PLLSAIDIVR) | (2 << 16); /* /8 */
240+
#endif
237241
rccEnableLTDC(false);
238242

239243
/* Driver struct initialization.*/
@@ -765,7 +769,11 @@ bool ltdcIsDitheringEnabledI(LTDCDriver *ltdcp) {
765769
osalDbgCheck(ltdcp == &LTDCD1);
766770
(void)ltdcp;
767771

772+
#if defined(STM32H743xx)
773+
return (LTDC->GCR & LTDC_GCR_DEN) != 0;
774+
#else
768775
return (LTDC->GCR & LTDC_GCR_DTEN) != 0;
776+
#endif
769777
}
770778

771779
/**
@@ -836,7 +844,11 @@ void ltdcDisableDitheringI(LTDCDriver *ltdcp) {
836844
osalDbgCheck(ltdcp == &LTDCD1);
837845
(void)ltdcp;
838846

847+
#if defined(STM32H743xx)
848+
LTDC->GCR &= ~LTDC_GCR_DEN;
849+
#else
839850
LTDC->GCR &= ~LTDC_GCR_DTEN;
851+
#endif
840852
}
841853

842854
/**

‎os/hal/src/hal_fsmc.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -105,7 +105,7 @@ void fsmcInit(void) {
105105
defined(STM32F745xx) || defined(STM32F746xx) || \
106106
defined(STM32F756xx) || defined(STM32F767xx) || \
107107
defined(STM32F769xx) || defined(STM32F777xx) || \
108-
defined(STM32F779xx))
108+
defined(STM32F779xx) || defined(STM32H743xx))
109109
#if STM32_SDRAM_USE_SDRAM1 || STM32_SDRAM_USE_SDRAM2
110110
FSMCD1.sdram = (FSMC_SDRAM_TypeDef *)FSMC_Bank5_6_R_BASE;
111111
#endif

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