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1 | 1 | /* |
2 | 2 | Copyright (C) 2023 1Conan |
3 | | - Copyright (C) 2023 Dimitris Mantzouranis |
| 3 | + Copyright (C) 2025 Dimitris Mantzouranis |
4 | 4 |
|
5 | 5 | Licensed under the Apache License, Version 2.0 (the "License"); |
6 | 6 | you may not use this file except in compliance with the License. |
|
16 | 16 | */ |
17 | 17 |
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18 | 18 | #ifndef SN32_I2C_H |
19 | | -#define SN32_I2C_H |
| 19 | +# define SN32_I2C_H |
20 | 20 |
|
21 | 21 | typedef struct { |
22 | 22 | union { |
23 | | - uint32_t CTRL; |
| 23 | + volatile uint32_t CTRL; /*!< (@ 0x00000000) Offset:0x00 I2Cn Control Register */ |
24 | 24 |
|
25 | 25 | struct { |
26 | 26 | uint32_t : 1; |
27 | | - uint32_t NACK : 1; |
28 | | - uint32_t ACK : 1; |
| 27 | + volatile uint32_t NACK : 1; /*!< [1..1] NACK assert flag */ |
| 28 | + volatile uint32_t ACK : 1; /*!< [2..2] ACK assert flag */ |
29 | 29 | uint32_t : 1; |
30 | | - uint32_t STO : 1; |
31 | | - uint32_t STA : 1; |
| 30 | + volatile uint32_t STO : 1; /*!< [4..4] STOP assert flag */ |
| 31 | + volatile uint32_t STA : 1; /*!< [5..5] START assert flag */ |
32 | 32 | uint32_t : 1; |
33 | | - uint32_t MODE : 1; |
34 | | - uint32_t I2CEN : 1; |
| 33 | + volatile uint32_t I2CMODE : 1; /*!< [7..7] I2C mode */ |
| 34 | + volatile uint32_t I2CEN : 1; /*!< [8..8] I2Cn interface enable */ |
35 | 35 | uint32_t : 23; |
36 | 36 | } CTRL_b; |
37 | 37 | }; |
38 | 38 |
|
39 | 39 | union { |
40 | | - uint32_t STAT; |
| 40 | + volatile uint32_t STAT; /*!< (@ 0x00000004) Offset:0x04 I2Cn Status Register */ |
41 | 41 |
|
42 | 42 | struct { |
43 | | - uint32_t RX_DN : 1; |
44 | | - uint32_t ACK_STAT : 1; |
45 | | - uint32_t NACK_STAT : 1; |
46 | | - uint32_t STOP_DN : 1; |
47 | | - uint32_t START_DN : 1; |
48 | | - uint32_t MST : 1; |
49 | | - uint32_t SLV_RX_HIT : 1; |
50 | | - uint32_t SLV_TX_HIT : 1; |
51 | | - uint32_t LOST_ARB : 1; |
52 | | - uint32_t TIMEOUT : 1; |
| 43 | + volatile const uint32_t RX_DN : 1; /*!< [0..0] RX done status */ |
| 44 | + volatile const uint32_t ACK_STAT : 1; /*!< [1..1] ACK done status */ |
| 45 | + volatile const uint32_t NACK_STAT : 1; /*!< [2..2] NACK done status */ |
| 46 | + volatile const uint32_t STOP_DN : 1; /*!< [3..3] STOP done status */ |
| 47 | + volatile const uint32_t START_DN : 1; /*!< [4..4] START done status */ |
| 48 | + volatile const uint32_t MST : 1; /*!< [5..5] I2C master/slave status */ |
| 49 | + volatile const uint32_t SLV_RX_HIT : 1; /*!< [6..6] Slave RX address hit flag */ |
| 50 | + volatile const uint32_t SLV_TX_HIT : 1; /*!< [7..7] Slave TX address hit flag */ |
| 51 | + volatile const uint32_t LOST_ARB : 1; /*!< [8..8] Lost arbitration status */ |
| 52 | + volatile const uint32_t TIMEOUT : 1; /*!< [9..9] Time-out status */ |
53 | 53 | uint32_t : 5; |
54 | | - uint32_t I2CIF : 1; |
| 54 | + volatile uint32_t I2CIF : 1; /*!< [15..15] I2C interrupt flag */ |
55 | 55 | uint32_t : 16; |
56 | 56 | } STAT_b; |
57 | 57 | }; |
58 | 58 |
|
59 | | - uint32_t TXDATA; |
60 | | - uint32_t RXDATA; |
| 59 | + volatile uint32_t TXDATA; /*!< (@ 0x00000008) Offset:0x08 I2Cn TX Data Register */ |
| 60 | + volatile const uint32_t RXDATA; /*!< (@ 0x0000000C) Offset:0x0C I2Cn RX Data Register */ |
61 | 61 |
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62 | 62 | union { |
63 | | - uint32_t SLVADRR0; |
| 63 | + volatile uint32_t SLVADDR0; /*!< (@ 0x00000010) Offset:0x10 I2Cn Slave Address 0 Register */ |
64 | 64 |
|
65 | 65 | struct { |
66 | | - uint32_t ADDR : 10; |
| 66 | + volatile uint32_t ADDR : 10; /*!< [9..0] I2Cn slave address 0 */ |
67 | 67 | uint32_t : 20; |
68 | | - uint32_t GCEN : 1; |
69 | | - uint32_t ADD_MODE : 1; |
70 | | - |
| 68 | + volatile uint32_t GCEN : 1; /*!< [30..30] General call address enable */ |
| 69 | + volatile uint32_t ADD_MODE : 1; /*!< [31..31] Slave address mode */ |
71 | 70 | } SLVADDR0_b; |
72 | 71 | }; |
73 | 72 |
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74 | | - uint32_t SLVADDR1; |
75 | | - uint32_t SLVADDR2; |
76 | | - uint32_t SLVADDR3; |
77 | | - uint32_t SCLHT; |
78 | | - uint32_t SCLLT; |
79 | | - uint32_t SCLCT; |
80 | | - uint32_t TOCTRL; |
| 73 | + volatile uint32_t SLVADDR1; /*!< (@ 0x00000014) Offset:0x14 I2Cn Slave Address 1 Register */ |
| 74 | + volatile uint32_t SLVADDR2; /*!< (@ 0x00000018) Offset:0x18 I2Cn Slave Address 2 Register */ |
| 75 | + volatile uint32_t SLVADDR3; /*!< (@ 0x0000001C) Offset:0x1C I2Cn Slave Address 3 Register */ |
| 76 | + volatile uint32_t SCLHT; /*!< (@ 0x00000020) Offset:0x20 I2Cn SCL High Time Register */ |
| 77 | + volatile uint32_t SCLLT; /*!< (@ 0x00000024) Offset:0x24 I2Cn SCL Low Time Register */ |
| 78 | + volatile uint32_t SCLCT; /*!< (@ 0x00000028) Offset:0x28 I2C SCL Check Time register */ |
| 79 | + volatile uint32_t TOCTRL; /*!< (@ 0x0000002C) Offset:0x2C I2Cn Timeout Control Register */ |
81 | 80 | } sn32_i2c_t; |
82 | 81 |
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83 | 82 |
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