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sn32: i2c: fixup generic header
1 parent 8c4e1e2 commit d668d48

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2 files changed

+36
-37
lines changed

2 files changed

+36
-37
lines changed

os/hal/ports/SN32/LLD/SN32F2xx/I2C/hal_i2c_lld.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -450,10 +450,10 @@ msg_t i2c_lld_match_address(I2CDriver *i2cp, i2caddr_t addr) {
450450

451451
I2C_TypeDef *dp = i2cp->i2c;
452452
uint16_t i2cadr = addr << 1;
453-
uint16_t ownAdr = dp->SLVADRR0 & (0x7f<<1);
453+
uint16_t ownAdr = dp->SLVADDR0 & (0x7f<<1);
454454

455455
if (ownAdr == 0 || ownAdr == i2cadr)
456-
dp->SLVADRR0 = i2cadr;
456+
dp->SLVADDR0 = i2cadr;
457457
else
458458
/* cannot add this address to set of those matched */
459459
return MSG_RESET;

os/hal/ports/SN32/LLD/SN32F2xx/I2C/sn32_i2c.h

Lines changed: 34 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
/*
22
Copyright (C) 2023 1Conan
3-
Copyright (C) 2023 Dimitris Mantzouranis
3+
Copyright (C) 2025 Dimitris Mantzouranis
44
55
Licensed under the Apache License, Version 2.0 (the "License");
66
you may not use this file except in compliance with the License.
@@ -16,68 +16,67 @@
1616
*/
1717

1818
#ifndef SN32_I2C_H
19-
#define SN32_I2C_H
19+
# define SN32_I2C_H
2020

2121
typedef struct {
2222
union {
23-
uint32_t CTRL;
23+
volatile uint32_t CTRL; /*!< (@ 0x00000000) Offset:0x00 I2Cn Control Register */
2424

2525
struct {
2626
uint32_t : 1;
27-
uint32_t NACK : 1;
28-
uint32_t ACK : 1;
27+
volatile uint32_t NACK : 1; /*!< [1..1] NACK assert flag */
28+
volatile uint32_t ACK : 1; /*!< [2..2] ACK assert flag */
2929
uint32_t : 1;
30-
uint32_t STO : 1;
31-
uint32_t STA : 1;
30+
volatile uint32_t STO : 1; /*!< [4..4] STOP assert flag */
31+
volatile uint32_t STA : 1; /*!< [5..5] START assert flag */
3232
uint32_t : 1;
33-
uint32_t MODE : 1;
34-
uint32_t I2CEN : 1;
33+
volatile uint32_t I2CMODE : 1; /*!< [7..7] I2C mode */
34+
volatile uint32_t I2CEN : 1; /*!< [8..8] I2Cn interface enable */
3535
uint32_t : 23;
3636
} CTRL_b;
3737
};
3838

3939
union {
40-
uint32_t STAT;
40+
volatile uint32_t STAT; /*!< (@ 0x00000004) Offset:0x04 I2Cn Status Register */
4141

4242
struct {
43-
uint32_t RX_DN : 1;
44-
uint32_t ACK_STAT : 1;
45-
uint32_t NACK_STAT : 1;
46-
uint32_t STOP_DN : 1;
47-
uint32_t START_DN : 1;
48-
uint32_t MST : 1;
49-
uint32_t SLV_RX_HIT : 1;
50-
uint32_t SLV_TX_HIT : 1;
51-
uint32_t LOST_ARB : 1;
52-
uint32_t TIMEOUT : 1;
43+
volatile const uint32_t RX_DN : 1; /*!< [0..0] RX done status */
44+
volatile const uint32_t ACK_STAT : 1; /*!< [1..1] ACK done status */
45+
volatile const uint32_t NACK_STAT : 1; /*!< [2..2] NACK done status */
46+
volatile const uint32_t STOP_DN : 1; /*!< [3..3] STOP done status */
47+
volatile const uint32_t START_DN : 1; /*!< [4..4] START done status */
48+
volatile const uint32_t MST : 1; /*!< [5..5] I2C master/slave status */
49+
volatile const uint32_t SLV_RX_HIT : 1; /*!< [6..6] Slave RX address hit flag */
50+
volatile const uint32_t SLV_TX_HIT : 1; /*!< [7..7] Slave TX address hit flag */
51+
volatile const uint32_t LOST_ARB : 1; /*!< [8..8] Lost arbitration status */
52+
volatile const uint32_t TIMEOUT : 1; /*!< [9..9] Time-out status */
5353
uint32_t : 5;
54-
uint32_t I2CIF : 1;
54+
volatile uint32_t I2CIF : 1; /*!< [15..15] I2C interrupt flag */
5555
uint32_t : 16;
5656
} STAT_b;
5757
};
5858

59-
uint32_t TXDATA;
60-
uint32_t RXDATA;
59+
volatile uint32_t TXDATA; /*!< (@ 0x00000008) Offset:0x08 I2Cn TX Data Register */
60+
volatile const uint32_t RXDATA; /*!< (@ 0x0000000C) Offset:0x0C I2Cn RX Data Register */
6161

6262
union {
63-
uint32_t SLVADRR0;
63+
volatile uint32_t SLVADDR0; /*!< (@ 0x00000010) Offset:0x10 I2Cn Slave Address 0 Register */
6464

6565
struct {
66-
uint32_t ADDR : 10;
66+
volatile uint32_t ADDR : 10; /*!< [9..0] I2Cn slave address 0 */
6767
uint32_t : 20;
68-
uint32_t GCEN : 1;
69-
uint32_t ADD_MODE : 1;
70-
68+
volatile uint32_t GCEN : 1; /*!< [30..30] General call address enable */
69+
volatile uint32_t ADD_MODE : 1; /*!< [31..31] Slave address mode */
7170
} SLVADDR0_b;
7271
};
7372

74-
uint32_t SLVADDR1;
75-
uint32_t SLVADDR2;
76-
uint32_t SLVADDR3;
77-
uint32_t SCLHT;
78-
uint32_t SCLLT;
79-
uint32_t SCLCT;
80-
uint32_t TOCTRL;
73+
volatile uint32_t SLVADDR1; /*!< (@ 0x00000014) Offset:0x14 I2Cn Slave Address 1 Register */
74+
volatile uint32_t SLVADDR2; /*!< (@ 0x00000018) Offset:0x18 I2Cn Slave Address 2 Register */
75+
volatile uint32_t SLVADDR3; /*!< (@ 0x0000001C) Offset:0x1C I2Cn Slave Address 3 Register */
76+
volatile uint32_t SCLHT; /*!< (@ 0x00000020) Offset:0x20 I2Cn SCL High Time Register */
77+
volatile uint32_t SCLLT; /*!< (@ 0x00000024) Offset:0x24 I2Cn SCL Low Time Register */
78+
volatile uint32_t SCLCT; /*!< (@ 0x00000028) Offset:0x28 I2C SCL Check Time register */
79+
volatile uint32_t TOCTRL; /*!< (@ 0x0000002C) Offset:0x2C I2Cn Timeout Control Register */
8180
} sn32_i2c_t;
8281

8382

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