diff --git a/demos/AT32/RT-AT-START-F402/.cproject b/demos/AT32/RT-AT-START-F402/.cproject new file mode 100644 index 0000000000..6c27b211fd --- /dev/null +++ b/demos/AT32/RT-AT-START-F402/.cproject @@ -0,0 +1,56 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/demos/AT32/RT-AT-START-F402/.project b/demos/AT32/RT-AT-START-F402/.project new file mode 100644 index 0000000000..42c9f78f7b --- /dev/null +++ b/demos/AT32/RT-AT-START-F402/.project @@ -0,0 +1,78 @@ + + + RT-AT-START-F402 + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + mingw32-make + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + false + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/demos/AT32/RT-AT-START-F402/Makefile b/demos/AT32/RT-AT-START-F402/Makefile new file mode 100644 index 0000000000..468a12016c --- /dev/null +++ b/demos/AT32/RT-AT-START-F402/Makefile @@ -0,0 +1,197 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO). +ifeq ($(USE_LTO),) + USE_LTO = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# Enable this if you want to use bitbang I2C. +ifeq ($(USE_HAL_I2C_FALLBACK),) + USE_HAL_I2C_FALLBACK = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x400 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU (no, softfp, hard). +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# FPU-related options. +ifeq ($(USE_FPU_OPT),) + USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16 +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, target, sources and paths +# + +# Define project name here +PROJECT = ch + +# Target settings. +MCU = cortex-m4 + +# Imported source files and paths. +CHIBIOS := ../../../../ChibiOS +CHIBIOS_CONTRIB := ../../.. +CONFDIR := ./cfg +BUILDDIR := ./build +DEPDIR := ./.dep + +# Licensing files. +include $(CHIBIOS)/os/license/license.mk +# Startup files. +include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_at32f402.mk +# HAL-OSAL files (optional). +include $(CHIBIOS_CONTRIB)/os/hal/hal.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/AT32F402_405/platform.mk +include $(CHIBIOS_CONTRIB)/os/hal/boards/AT_START_F402/board.mk +include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMv7-M/compilers/GCC/mk/port.mk +# Auto-build files in ./source recursively. +include $(CHIBIOS)/tools/mk/autobuild.mk +# Other files (optional). +include $(CHIBIOS)/os/test/test.mk +include $(CHIBIOS)/test/rt/rt_test.mk +include $(CHIBIOS)/test/oslib/oslib_test.mk +include $(CHIBIOS)/os/hal/lib/streams/streams.mk +include $(CHIBIOS)/os/various/shell/shell.mk + +# Define linker script file here. +LDSCRIPT= $(STARTUPLD_CONTRIB)/AT32F402xC.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(ALLCSRC) \ + $(TESTSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = $(ALLCPPSRC) + +# List ASM source files here. +ASMSRC = $(ALLASMSRC) + +# List ASM with preprocessor source files here. +ASMXSRC = $(ALLXASMSRC) + +# Inclusion directories. +INCDIR = $(CONFDIR) $(ALLINC) $(TESTINC) + +# Define C warning options here. +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes + +# Define C++ warning options here. +CPPWARN = -Wall -Wextra -Wundef + +# +# Project, target, sources and paths +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user section +############################################################################## + +############################################################################## +# Common rules +# + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk +include $(RULESPATH)/arm-none-eabi.mk +include $(RULESPATH)/rules.mk + +# +# Common rules +############################################################################## + +############################################################################## +# Custom rules +# + +# +# Custom rules +############################################################################## diff --git a/demos/AT32/RT-AT-START-F402/cfg/chconf.h b/demos/AT32/RT-AT-START-F402/cfg/chconf.h new file mode 100644 index 0000000000..56fe06776a --- /dev/null +++ b/demos/AT32/RT-AT-START-F402/cfg/chconf.h @@ -0,0 +1,842 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_7_0_ + +/*===========================================================================*/ +/** + * @name System settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Handling of instances. + * @note If enabled then threads assigned to various instances can + * interact each other using the same synchronization objects. + * If disabled then each OS instance is a separate world, no + * direct interactions are handled by the OS. + */ +#if !defined(CH_CFG_SMP_MODE) +#define CH_CFG_SMP_MODE FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_ST_RESOLUTION) +#define CH_CFG_ST_RESOLUTION 32 +#endif + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_CFG_ST_FREQUENCY) +#define CH_CFG_ST_FREQUENCY 10000 +#endif + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_INTERVALS_SIZE) +#define CH_CFG_INTERVALS_SIZE 32 +#endif + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_TIME_TYPES_SIZE) +#define CH_CFG_TIME_TYPES_SIZE 32 +#endif + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#if !defined(CH_CFG_ST_TIMEDELTA) +#define CH_CFG_ST_TIMEDELTA 2 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#if !defined(CH_CFG_TIME_QUANTUM) +#define CH_CFG_TIME_QUANTUM 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#if !defined(CH_CFG_NO_IDLE_THREAD) +#define CH_CFG_NO_IDLE_THREAD FALSE +#endif + +/** + * @brief Kernel hardening level. + * @details This option is the level of functional-safety checks enabled + * in the kerkel. The meaning is: + * - 0: No checks, maximum performance. + * - 1: Reasonable checks. + * - 2: All checks. + * . + */ +#if !defined(CH_CFG_HARDENING_LEVEL) +#define CH_CFG_HARDENING_LEVEL 0 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_OPTIMIZE_SPEED) +#define CH_CFG_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TM) +#define CH_CFG_USE_TM TRUE +#endif + +/** + * @brief Time Stamps APIs. + * @details If enabled then the time stamps APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TIMESTAMP) +#define CH_CFG_USE_TIMESTAMP TRUE +#endif + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_REGISTRY) +#define CH_CFG_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_WAITEXIT) +#define CH_CFG_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_SEMAPHORES) +#define CH_CFG_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MUTEXES) +#define CH_CFG_USE_MUTEXES TRUE +#endif + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_CONDVARS) +#define CH_CFG_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_EVENTS) +#define CH_CFG_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MESSAGES) +#define CH_CFG_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#if !defined(CH_CFG_USE_DYNAMIC) +#define CH_CFG_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name OSLIB options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_MAILBOXES) +#define CH_CFG_USE_MAILBOXES TRUE +#endif + +/** + * @brief Memory checks APIs. + * @details If enabled then the memory checks APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCHECKS) +#define CH_CFG_USE_MEMCHECKS TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCORE) +#define CH_CFG_USE_MEMCORE TRUE +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#if !defined(CH_CFG_MEMCORE_SIZE) +#define CH_CFG_MEMCORE_SIZE 0 +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_CFG_USE_HEAP) +#define CH_CFG_USE_HEAP TRUE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMPOOLS) +#define CH_CFG_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_FIFOS) +#define CH_CFG_USE_OBJ_FIFOS TRUE +#endif + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Objects Caches APIs. + * @details If enabled then the objects caches APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_CACHES) +#define CH_CFG_USE_OBJ_CACHES TRUE +#endif + +/** + * @brief Delegate threads APIs. + * @details If enabled then the delegate threads APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_DELEGATES) +#define CH_CFG_USE_DELEGATES TRUE +#endif + +/** + * @brief Jobs Queues APIs. + * @details If enabled then the jobs queues APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_JOBS) +#define CH_CFG_USE_JOBS TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_CFG_USE_FACTORY) +#define CH_CFG_USE_FACTORY TRUE +#endif + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 +#endif + +/** + * @brief Enables the registry of generic objects. + */ +#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE +#endif + +/** + * @brief Enables factory for generic buffers. + */ +#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE +#endif + +/** + * @brief Enables factory for semaphores. + */ +#if !defined(CH_CFG_FACTORY_SEMAPHORES) +#define CH_CFG_FACTORY_SEMAPHORES TRUE +#endif + +/** + * @brief Enables factory for mailboxes. + */ +#if !defined(CH_CFG_FACTORY_MAILBOXES) +#define CH_CFG_FACTORY_MAILBOXES TRUE +#endif + +/** + * @brief Enables factory for objects FIFOs. + */ +#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE +#endif + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_STATISTICS) +#define CH_DBG_STATISTICS FALSE +#endif + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_MASK) +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_ALL +#endif + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_BUFFER_SIZE) +#define CH_DBG_TRACE_BUFFER_SIZE 128 +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#if !defined(CH_DBG_THREADS_PROFILING) +#define CH_DBG_THREADS_PROFILING FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add system custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add system initialization code here.*/ \ +} + +/** + * @brief OS instance structure extension. + * @details User fields added to the end of the @p os_instance_t structure. + */ +#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS \ + /* Add OS instance custom fields here.*/ + +/** + * @brief OS instance initialization hook. + * + * @param[in] oip pointer to the @p os_instance_t structure + */ +#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) { \ + /* Add OS instance initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + * + * @param[in] ntp thread being switched in + * @param[in] otp thread being switched out + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** + * @brief Runtime Faults Collection Unit hook. + * @details This hook is invoked each time new faults are collected and stored. + */ +#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) { \ + /* Faults handling code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/demos/AT32/RT-AT-START-F402/cfg/config.h b/demos/AT32/RT-AT-START-F402/cfg/config.h new file mode 100644 index 0000000000..1e7c044f47 --- /dev/null +++ b/demos/AT32/RT-AT-START-F402/cfg/config.h @@ -0,0 +1,39 @@ +/* + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * CRC driver system settings. + */ +#define AT32_CRC_USE_CRC1 FALSE + +#define CRC_USE_DMA FALSE +#define AT32_CRC_CRC1_DMA_PRIORITY 2 +#define AT32_CRC_CRC1_IRQ_PRIORITY 5 +#define AT32_CRC_CRC1_DMA_STREAM AT32_DMA_STREAM_ID_ANY + +/* + * I2C fallback driver system settings. + */ +#define SW_I2C_USE_I2C1 FALSE +#define SW_I2C_USE_I2C2 FALSE +#define SW_I2C_USE_I2C3 FALSE +#define SW_I2C_USE_I2C4 FALSE + +/* + * Other settings. + */ +#define BOARD_OTG_VBUSIG diff --git a/demos/AT32/RT-AT-START-F402/cfg/halconf.h b/demos/AT32/RT-AT-START-F402/cfg/halconf.h new file mode 100644 index 0000000000..09dfd22866 --- /dev/null +++ b/demos/AT32/RT-AT-START-F402/cfg/halconf.h @@ -0,0 +1,557 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_8_4_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the EFlash subsystem. + */ +#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__) +#define HAL_USE_EFL FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/** + * @brief Enables the WSPI subsystem. + */ +#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) +#define HAL_USE_WSPI FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS FALSE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS FALSE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Timeout before assuming a failure while waiting for card idle. + * @note Time is in milliseconds. + */ +#if !defined(MMC_IDLE_TIMEOUT_MS) || defined(__DOXYGEN__) +#define MMC_IDLE_TIMEOUT_MS 1000 +#endif + +/** + * @brief Mutual exclusion on the SPI bus. + */ +#if !defined(MMC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define MMC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SIO driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SIO_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SIO_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Support for thread synchronization API. + */ +#if !defined(SIO_USE_SYNCHRONIZATION) || defined(__DOXYGEN__) +#define SIO_USE_SYNCHRONIZATION TRUE +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 256 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 2 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Inserts an assertion on function errors before returning. + */ +#if !defined(SPI_USE_ASSERT_ON_ERROR) || defined(__DOXYGEN__) +#define SPI_USE_ASSERT_ON_ERROR TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#include "halconf_community.h" + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/demos/AT32/RT-AT-START-F402/cfg/halconf_community.h b/demos/AT32/RT-AT-START-F402/cfg/halconf_community.h new file mode 100644 index 0000000000..5a77290c71 --- /dev/null +++ b/demos/AT32/RT-AT-START-F402/cfg/halconf_community.h @@ -0,0 +1,182 @@ +/* + ChibiOS - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef HALCONF_COMMUNITY_H +#define HALCONF_COMMUNITY_H + +/** + * @brief Enables the community overlay. + */ +#if !defined(HAL_USE_COMMUNITY) || defined(__DOXYGEN__) +#define HAL_USE_COMMUNITY TRUE +#endif + +/** + * @brief Enables the FSMC subsystem. + */ +#if !defined(HAL_USE_FSMC) || defined(__DOXYGEN__) +#define HAL_USE_FSMC FALSE +#endif + +/** + * @brief Enables the NAND subsystem. + */ +#if !defined(HAL_USE_NAND) || defined(__DOXYGEN__) +#define HAL_USE_NAND FALSE +#endif + +/** + * @brief Enables the 1-wire subsystem. + */ +#if !defined(HAL_USE_ONEWIRE) || defined(__DOXYGEN__) +#define HAL_USE_ONEWIRE FALSE +#endif + +/** + * @brief Enables the EICU subsystem. + */ +#if !defined(HAL_USE_EICU) || defined(__DOXYGEN__) +#define HAL_USE_EICU FALSE +#endif + +/** + * @brief Enables the CRC subsystem. + */ +#if !defined(HAL_USE_CRC) || defined(__DOXYGEN__) +#define HAL_USE_CRC FALSE +#endif + +/** + * @brief Enables the RNG subsystem. + */ +#if !defined(HAL_USE_RNG) || defined(__DOXYGEN__) +#define HAL_USE_RNG FALSE +#endif + +/** + * @brief Enables the EEPROM subsystem. + */ +#if !defined(HAL_USE_EEPROM) || defined(__DOXYGEN__) +#define HAL_USE_EEPROM FALSE +#endif + +/** + * @brief Enables the TIMCAP subsystem. + */ +#if !defined(HAL_USE_TIMCAP) || defined(__DOXYGEN__) +#define HAL_USE_TIMCAP FALSE +#endif + +/** + * @brief Enables the COMP subsystem. + */ +#if !defined(HAL_USE_COMP) || defined(__DOXYGEN__) +#define HAL_USE_COMP FALSE +#endif + +/** + * @brief Enables the OPAMP subsystem. + */ +#if !defined(HAL_USE_OPAMP) || defined(__DOXYGEN__) +#define HAL_USE_OPAMP FALSE +#endif + +/** + * @brief Enables the QEI subsystem. + */ +#if !defined(HAL_USE_QEI) || defined(__DOXYGEN__) +#define HAL_USE_QEI FALSE +#endif + +/** + * @brief Enables the USBH subsystem. + */ +#if !defined(HAL_USE_USBH) || defined(__DOXYGEN__) +#define HAL_USE_USBH FALSE +#endif + +/** + * @brief Enables the USB_MSD subsystem. + */ +#if !defined(HAL_USE_USB_MSD) || defined(__DOXYGEN__) +#define HAL_USE_USB_MSD FALSE +#endif + +/*===========================================================================*/ +/* FSMCNAND driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the @p nandAcquireBus() and @p nanReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(NAND_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define NAND_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* 1-wire driver related settings. */ +/*===========================================================================*/ +/** + * @brief Enables strong pull up feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_STRONG_PULLUP FALSE + +/** + * @brief Enables search ROM feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_SEARCH_ROM TRUE + +/*===========================================================================*/ +/* QEI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables discard of overlow + */ +#if !defined(QEI_USE_OVERFLOW_DISCARD) || defined(__DOXYGEN__) +#define QEI_USE_OVERFLOW_DISCARD FALSE +#endif + +/** + * @brief Enables min max of overlow + */ +#if !defined(QEI_USE_OVERFLOW_MINMAX) || defined(__DOXYGEN__) +#define QEI_USE_OVERFLOW_MINMAX FALSE +#endif + +/*===========================================================================*/ +/* EEProm driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables 24xx series I2C eeprom device driver. + * @note Disabling this option saves both code and data space. + */ +#define EEPROM_USE_EE24XX FALSE + /** + * @brief Enables 25xx series SPI eeprom device driver. + * @note Disabling this option saves both code and data space. + */ +#define EEPROM_USE_EE25XX FALSE + +#endif /* HALCONF_COMMUNITY_H */ + +/** @} */ diff --git a/demos/AT32/RT-AT-START-F402/cfg/mcuconf.h b/demos/AT32/RT-AT-START-F402/cfg/mcuconf.h new file mode 100644 index 0000000000..ca518f729d --- /dev/null +++ b/demos/AT32/RT-AT-START-F402/cfg/mcuconf.h @@ -0,0 +1,268 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef MCUCONF_H +#define MCUCONF_H + +/* + * AT32F402 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define AT32F402_MCUCONF + +/* + * General settings. + */ +#define AT32_NO_INIT FALSE + +/* + * HAL driver system settings. + */ +#define AT32_HICK_ENABLED TRUE +#define AT32_LICK_ENABLED FALSE +#define AT32_HEXT_ENABLED TRUE +#define AT32_LEXT_ENABLED FALSE +#define AT32_PLLU_ENABLED TRUE +#define AT32_SCLKSEL AT32_SCLKSEL_PLL +#define AT32_PLLRCS AT32_PLLRCS_HEXT +#define AT32_PLL_MS_VALUE 1 +#define AT32_PLL_NS_VALUE 72 +#define AT32_PLL_FP_VALUE 4 +#define AT32_PLL_FU_VALUE 18 +#define AT32_AHBDIV AT32_AHBDIV_DIV1 +#define AT32_APB1DIV AT32_APB1DIV_DIV2 +#define AT32_APB2DIV AT32_APB2DIV_DIV1 +#define AT32_HICK_TO_SCLK AT32_HICK_TO_SCLK_48M +#define AT32_HICKDIV AT32_HICKDIV_DIV1 +#define AT32_HICK_TO_SCLK_DIV AT32_HICK_TO_SCLK_DIV_DIV1 +#define AT32_HEXT_TO_SCLK_DIV AT32_HEXT_TO_SCLK_DIV_DIV1 +#define AT32_USB_CLOCK48_REQUIRED TRUE +#define AT32_PLLU_USB48_SEL AT32_PLLU_USB48_SEL_PLLU +#define AT32_CLKOUT_SEL AT32_CLKOUT_SEL_HICK +#define AT32_CLKOUTDIV1 AT32_CLKOUTDIV1_DIV1 +#define AT32_CLKOUTDIV2 AT32_CLKOUTDIV2_DIV1 +#define AT32_ERTCSEL AT32_ERTCSEL_NOCLOCK +#define AT32_ERTCDIV_VALUE 12 +#define AT32_I2SF5CLKSEL AT32_I2SF5CLKSEL_SCLK +#define AT32_PVM_ENABLE FALSE +#define AT32_PVMSEL AT32_PVMSEL_LEV1 +#define AT32_LDOOVSEL AT32_LDOOVSEL_LEV3 + +/* + * IRQ system settings. + */ +#define AT32_IRQ_EXINT0_PRIORITY 6 +#define AT32_IRQ_EXINT1_PRIORITY 6 +#define AT32_IRQ_EXINT2_PRIORITY 6 +#define AT32_IRQ_EXINT3_PRIORITY 6 +#define AT32_IRQ_EXINT4_PRIORITY 6 +#define AT32_IRQ_EXINT5_9_PRIORITY 6 +#define AT32_IRQ_EXINT10_15_PRIORITY 6 +#define AT32_IRQ_EXINT16_PRIORITY 6 +#define AT32_IRQ_EXINT17_PRIORITY 15 +#define AT32_IRQ_EXINT18_PRIORITY 6 +#define AT32_IRQ_EXINT20_PRIORITY 6 +#define AT32_IRQ_EXINT21_PRIORITY 15 +#define AT32_IRQ_EXINT22_PRIORITY 15 + +#define AT32_IRQ_TMR1_BRK_TMR9_PRIORITY 7 +#define AT32_IRQ_TMR1_OVF_TMR10_PRIORITY 7 +#define AT32_IRQ_TMR1_HALL_TMR11_PRIORITY 7 +#define AT32_IRQ_TMR1_CH_PRIORITY 7 +#define AT32_IRQ_TMR2_PRIORITY 7 +#define AT32_IRQ_TMR3_PRIORITY 7 +#define AT32_IRQ_TMR4_PRIORITY 7 +#define AT32_IRQ_TMR6_PRIORITY 7 +#define AT32_IRQ_TMR7_PRIORITY 7 +#define AT32_IRQ_TMR13_PRIORITY 7 +#define AT32_IRQ_TMR14_PRIORITY 7 + +#define AT32_IRQ_USART1_PRIORITY 12 +#define AT32_IRQ_USART2_PRIORITY 12 +#define AT32_IRQ_USART3_PRIORITY 12 +#define AT32_IRQ_UART4_PRIORITY 12 +#define AT32_IRQ_UART5_PRIORITY 12 +#define AT32_IRQ_USART6_PRIORITY 12 +#define AT32_IRQ_UART7_PRIORITY 12 +#define AT32_IRQ_UART8_PRIORITY 12 + +/* + * ADC driver system settings. + */ +#define AT32_ADC_USE_ADC1 FALSE +#define AT32_ADC_ADC1_DMA_PRIORITY 2 +#define AT32_ADC_IRQ_PRIORITY 6 +#define AT32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define AT32_ADC_ADCDIV 8 + +/* + * CAN driver system settings. + */ +#define AT32_CAN_USE_CAN1 FALSE +#define AT32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * GPT driver system settings. + */ +#define AT32_GPT_USE_TMR1 FALSE +#define AT32_GPT_USE_TMR2 FALSE +#define AT32_GPT_USE_TMR3 FALSE +#define AT32_GPT_USE_TMR4 FALSE +#define AT32_GPT_USE_TMR6 FALSE +#define AT32_GPT_USE_TMR7 FALSE +#define AT32_GPT_USE_TMR9 FALSE +#define AT32_GPT_USE_TMR10 FALSE +#define AT32_GPT_USE_TMR11 FALSE +#define AT32_GPT_USE_TMR13 FALSE +#define AT32_GPT_USE_TMR14 FALSE + +/* + * I2C driver system settings. + */ +#define AT32_I2C_USE_I2C1 FALSE +#define AT32_I2C_USE_I2C2 FALSE +#define AT32_I2C_USE_I2C3 FALSE +#define AT32_I2C_BUSY_TIMEOUT 50 +#define AT32_I2C_I2C1_DMA_PRIORITY 3 +#define AT32_I2C_I2C2_DMA_PRIORITY 3 +#define AT32_I2C_I2C3_DMA_PRIORITY 3 +#define AT32_I2C_I2C1_IRQ_PRIORITY 5 +#define AT32_I2C_I2C2_IRQ_PRIORITY 5 +#define AT32_I2C_I2C3_IRQ_PRIORITY 5 +#define AT32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define AT32_ICU_USE_TMR1 FALSE +#define AT32_ICU_USE_TMR2 FALSE +#define AT32_ICU_USE_TMR3 FALSE +#define AT32_ICU_USE_TMR4 FALSE +#define AT32_ICU_USE_TMR9 FALSE + +/* + * PWM driver system settings. + */ +#define AT32_PWM_USE_TMR1 FALSE +#define AT32_PWM_USE_TMR2 FALSE +#define AT32_PWM_USE_TMR3 FALSE +#define AT32_PWM_USE_TMR4 FALSE +#define AT32_PWM_USE_TMR9 FALSE +#define AT32_PWM_USE_TMR10 FALSE +#define AT32_PWM_USE_TMR11 FALSE +#define AT32_PWM_USE_TMR13 FALSE +#define AT32_PWM_USE_TMR14 FALSE + +/* + * RTC driver system settings. + */ +#define AT32_ERTC_DIVA_VALUE 32 +#define AT32_ERTC_DIVB_VALUE 1024 +#define AT32_ERTC_CTRL_INIT 0 +#define AT32_ERTC_TAMP_INIT 0 + +/* + * SERIAL driver system settings. + */ +#define AT32_SERIAL_USE_USART1 TRUE +#define AT32_SERIAL_USE_USART2 FALSE +#define AT32_SERIAL_USE_USART3 FALSE +#define AT32_SERIAL_USE_UART4 FALSE +#define AT32_SERIAL_USE_UART5 FALSE +#define AT32_SERIAL_USE_USART6 FALSE +#define AT32_SERIAL_USE_UART7 FALSE +#define AT32_SERIAL_USE_UART8 FALSE + +/* + * SIO driver system settings. + */ +#define AT32_SIO_USE_USART1 FALSE +#define AT32_SIO_USE_USART2 FALSE +#define AT32_SIO_USE_USART3 FALSE +#define AT32_SIO_USE_UART4 FALSE +#define AT32_SIO_USE_UART5 FALSE +#define AT32_SIO_USE_USART6 FALSE +#define AT32_SIO_USE_UART7 FALSE +#define AT32_SIO_USE_UART8 FALSE + +/* + * SPI driver system settings. + */ +#define AT32_SPI_USE_SPI1 FALSE +#define AT32_SPI_USE_SPI2 FALSE +#define AT32_SPI_USE_SPI3 FALSE +#define AT32_SPI_SPI1_DMA_PRIORITY 1 +#define AT32_SPI_SPI2_DMA_PRIORITY 1 +#define AT32_SPI_SPI3_DMA_PRIORITY 1 +#define AT32_SPI_SPI1_IRQ_PRIORITY 10 +#define AT32_SPI_SPI2_IRQ_PRIORITY 10 +#define AT32_SPI_SPI3_IRQ_PRIORITY 10 +#define AT32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define AT32_ST_IRQ_PRIORITY 8 +#define AT32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define AT32_UART_USE_USART1 FALSE +#define AT32_UART_USE_USART2 FALSE +#define AT32_UART_USE_USART3 FALSE +#define AT32_UART_USE_UART4 FALSE +#define AT32_UART_USE_UART5 FALSE +#define AT32_UART_USE_USART6 FALSE +#define AT32_UART_USE_UART7 FALSE +#define AT32_UART_USE_UART8 FALSE +#define AT32_UART_USART1_DMA_PRIORITY 0 +#define AT32_UART_USART2_DMA_PRIORITY 0 +#define AT32_UART_USART3_DMA_PRIORITY 0 +#define AT32_UART_UART4_DMA_PRIORITY 0 +#define AT32_UART_UART5_DMA_PRIORITY 0 +#define AT32_UART_USART6_DMA_PRIORITY 0 +#define AT32_UART_UART7_DMA_PRIORITY 0 +#define AT32_UART_UART8_DMA_PRIORITY 0 +#define AT32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define AT32_USB_USE_OTG1 FALSE +#define AT32_USB_OTG1_IRQ_PRIORITY 14 +#define AT32_USB_OTG1_RX_FIFO_SIZE 512 + +/* + * WDG driver system settings. + */ +#define AT32_WDG_USE_WDT FALSE + +#include "config.h" + +#endif /* MCUCONF_H */ diff --git a/demos/AT32/RT-AT-START-F402/main.c b/demos/AT32/RT-AT-START-F402/main.c new file mode 100644 index 0000000000..1d8790d591 --- /dev/null +++ b/demos/AT32/RT-AT-START-F402/main.c @@ -0,0 +1,79 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" +#include "rt_test_root.h" +#include "oslib_test_root.h" + +/* + * This is a periodic thread that does absolutely nothing except flashing + * a LED. + */ +static THD_WORKING_AREA(waThread1, 128); +static THD_FUNCTION(Thread1, arg) { + + (void)arg; + chRegSetThreadName("blinker"); + while (true) { + palToggleLine(LINE_LED_RED); + chThdSleepMilliseconds(250); + palToggleLine(LINE_LED_YELLOW); + chThdSleepMilliseconds(250); + palToggleLine(LINE_LED_GREEN); + chThdSleepMilliseconds(250); + } +} + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Activates the serial driver 1 using the driver default configuration. + */ + sdStart(&SD1, NULL); + + /* + * Creates the example thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing except + * sleeping in a loop and check the button state. + */ + while (true) { + if (palReadLine(LINE_BUTTON)) { + test_execute((BaseSequentialStream *)&SD1, &rt_test_suite); + test_execute((BaseSequentialStream *)&SD1, &oslib_test_suite); + } + chThdSleepMilliseconds(500); + } +} diff --git a/demos/AT32/RT-AT-START-F405/Makefile b/demos/AT32/RT-AT-START-F405/Makefile index 4bec71adea..634bbe42ce 100644 --- a/demos/AT32/RT-AT-START-F405/Makefile +++ b/demos/AT32/RT-AT-START-F405/Makefile @@ -103,10 +103,10 @@ DEPDIR := ./.dep # Licensing files. include $(CHIBIOS)/os/license/license.mk # Startup files. -include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_at32f405xx.mk +include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_at32f405.mk # HAL-OSAL files (optional). -include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/AT32F405xx/platform.mk +include $(CHIBIOS_CONTRIB)/os/hal/hal.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/AT32F402_405/platform.mk include $(CHIBIOS_CONTRIB)/os/hal/boards/AT_START_F405/board.mk include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk # RTOS files (optional). diff --git a/demos/AT32/RT-AT-START-F405/cfg/chconf.h b/demos/AT32/RT-AT-START-F405/cfg/chconf.h index 46b3f78b68..17c627b0e5 100644 --- a/demos/AT32/RT-AT-START-F405/cfg/chconf.h +++ b/demos/AT32/RT-AT-START-F405/cfg/chconf.h @@ -1,7 +1,8 @@ /* ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + ChibiOS - Copyright (C) 2024..2025 Maxjta Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/demos/AT32/RT-AT-START-F405/cfg/config.h b/demos/AT32/RT-AT-START-F405/cfg/config.h index 4fbd7cc3df..d1e4494978 100644 --- a/demos/AT32/RT-AT-START-F405/cfg/config.h +++ b/demos/AT32/RT-AT-START-F405/cfg/config.h @@ -1,7 +1,7 @@ /* - ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + ChibiOS - Copyright (C) 2024..2025 Maxjta Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -16,6 +16,16 @@ limitations under the License. */ +/* + * CRC driver system settings. + */ +#define AT32_CRC_USE_CRC1 FALSE + +#define CRC_USE_DMA FALSE +#define AT32_CRC_CRC1_DMA_PRIORITY 2 +#define AT32_CRC_CRC1_IRQ_PRIORITY 5 +#define AT32_CRC_CRC1_DMA_STREAM AT32_DMA_STREAM_ID_ANY + /* * I2C fallback driver system settings. */ diff --git a/demos/AT32/RT-AT-START-F405/cfg/halconf.h b/demos/AT32/RT-AT-START-F405/cfg/halconf.h index 59fb7c11f3..ae96c63baf 100644 --- a/demos/AT32/RT-AT-START-F405/cfg/halconf.h +++ b/demos/AT32/RT-AT-START-F405/cfg/halconf.h @@ -1,8 +1,8 @@ /* ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian - ChibiOS - Copyright (C) 2023..2024 Maxjta + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + ChibiOS - Copyright (C) 2024..2025 Maxjta Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -47,7 +47,7 @@ * @brief Enables the ADC subsystem. */ #if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) -#define HAL_USE_ADC TRUE +#define HAL_USE_ADC FALSE #endif /** @@ -89,7 +89,7 @@ * @brief Enables the I2C subsystem. */ #if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) -#define HAL_USE_I2C TRUE +#define HAL_USE_I2C FALSE #endif /** @@ -166,7 +166,7 @@ * @brief Enables the SPI subsystem. */ #if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) -#define HAL_USE_SPI TRUE +#define HAL_USE_SPI FALSE #endif /** @@ -187,7 +187,7 @@ * @brief Enables the USB subsystem. */ #if !defined(HAL_USE_USB) || defined(__DOXYGEN__) -#define HAL_USE_USB TRUE +#define HAL_USE_USB FALSE #endif /** @@ -551,6 +551,8 @@ #define WSPI_USE_MUTUAL_EXCLUSION TRUE #endif +#include "halconf_community.h" + #endif /* HALCONF_H */ /** @} */ diff --git a/demos/AT32/RT-AT-START-F405/cfg/halconf_community.h b/demos/AT32/RT-AT-START-F405/cfg/halconf_community.h new file mode 100644 index 0000000000..5a77290c71 --- /dev/null +++ b/demos/AT32/RT-AT-START-F405/cfg/halconf_community.h @@ -0,0 +1,182 @@ +/* + ChibiOS - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef HALCONF_COMMUNITY_H +#define HALCONF_COMMUNITY_H + +/** + * @brief Enables the community overlay. + */ +#if !defined(HAL_USE_COMMUNITY) || defined(__DOXYGEN__) +#define HAL_USE_COMMUNITY TRUE +#endif + +/** + * @brief Enables the FSMC subsystem. + */ +#if !defined(HAL_USE_FSMC) || defined(__DOXYGEN__) +#define HAL_USE_FSMC FALSE +#endif + +/** + * @brief Enables the NAND subsystem. + */ +#if !defined(HAL_USE_NAND) || defined(__DOXYGEN__) +#define HAL_USE_NAND FALSE +#endif + +/** + * @brief Enables the 1-wire subsystem. + */ +#if !defined(HAL_USE_ONEWIRE) || defined(__DOXYGEN__) +#define HAL_USE_ONEWIRE FALSE +#endif + +/** + * @brief Enables the EICU subsystem. + */ +#if !defined(HAL_USE_EICU) || defined(__DOXYGEN__) +#define HAL_USE_EICU FALSE +#endif + +/** + * @brief Enables the CRC subsystem. + */ +#if !defined(HAL_USE_CRC) || defined(__DOXYGEN__) +#define HAL_USE_CRC FALSE +#endif + +/** + * @brief Enables the RNG subsystem. + */ +#if !defined(HAL_USE_RNG) || defined(__DOXYGEN__) +#define HAL_USE_RNG FALSE +#endif + +/** + * @brief Enables the EEPROM subsystem. + */ +#if !defined(HAL_USE_EEPROM) || defined(__DOXYGEN__) +#define HAL_USE_EEPROM FALSE +#endif + +/** + * @brief Enables the TIMCAP subsystem. + */ +#if !defined(HAL_USE_TIMCAP) || defined(__DOXYGEN__) +#define HAL_USE_TIMCAP FALSE +#endif + +/** + * @brief Enables the COMP subsystem. + */ +#if !defined(HAL_USE_COMP) || defined(__DOXYGEN__) +#define HAL_USE_COMP FALSE +#endif + +/** + * @brief Enables the OPAMP subsystem. + */ +#if !defined(HAL_USE_OPAMP) || defined(__DOXYGEN__) +#define HAL_USE_OPAMP FALSE +#endif + +/** + * @brief Enables the QEI subsystem. + */ +#if !defined(HAL_USE_QEI) || defined(__DOXYGEN__) +#define HAL_USE_QEI FALSE +#endif + +/** + * @brief Enables the USBH subsystem. + */ +#if !defined(HAL_USE_USBH) || defined(__DOXYGEN__) +#define HAL_USE_USBH FALSE +#endif + +/** + * @brief Enables the USB_MSD subsystem. + */ +#if !defined(HAL_USE_USB_MSD) || defined(__DOXYGEN__) +#define HAL_USE_USB_MSD FALSE +#endif + +/*===========================================================================*/ +/* FSMCNAND driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the @p nandAcquireBus() and @p nanReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(NAND_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define NAND_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* 1-wire driver related settings. */ +/*===========================================================================*/ +/** + * @brief Enables strong pull up feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_STRONG_PULLUP FALSE + +/** + * @brief Enables search ROM feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_SEARCH_ROM TRUE + +/*===========================================================================*/ +/* QEI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables discard of overlow + */ +#if !defined(QEI_USE_OVERFLOW_DISCARD) || defined(__DOXYGEN__) +#define QEI_USE_OVERFLOW_DISCARD FALSE +#endif + +/** + * @brief Enables min max of overlow + */ +#if !defined(QEI_USE_OVERFLOW_MINMAX) || defined(__DOXYGEN__) +#define QEI_USE_OVERFLOW_MINMAX FALSE +#endif + +/*===========================================================================*/ +/* EEProm driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables 24xx series I2C eeprom device driver. + * @note Disabling this option saves both code and data space. + */ +#define EEPROM_USE_EE24XX FALSE + /** + * @brief Enables 25xx series SPI eeprom device driver. + * @note Disabling this option saves both code and data space. + */ +#define EEPROM_USE_EE25XX FALSE + +#endif /* HALCONF_COMMUNITY_H */ + +/** @} */ diff --git a/demos/AT32/RT-AT-START-F405/cfg/mcuconf.h b/demos/AT32/RT-AT-START-F405/cfg/mcuconf.h index a7eb2a1ad1..11d5d29972 100644 --- a/demos/AT32/RT-AT-START-F405/cfg/mcuconf.h +++ b/demos/AT32/RT-AT-START-F405/cfg/mcuconf.h @@ -1,8 +1,8 @@ /* ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian - ChibiOS - Copyright (C) 2023..2024 Maxjta + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + ChibiOS - Copyright (C) 2024..2025 Maxjta Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -34,7 +34,7 @@ * 0...3 Lowest...Highest. */ -#define AT32F405xx_MCUCONF +#define AT32F405_MCUCONF /* * General settings. @@ -45,27 +45,34 @@ * HAL driver system settings. */ #define AT32_HICK_ENABLED TRUE -#define AT32_LICK_ENABLED TRUE +#define AT32_LICK_ENABLED FALSE #define AT32_HEXT_ENABLED TRUE #define AT32_LEXT_ENABLED FALSE +#define AT32_PLLU_ENABLED TRUE #define AT32_SCLKSEL AT32_SCLKSEL_PLL #define AT32_PLLRCS AT32_PLLRCS_HEXT -#define AT32_PLLHEXTDIV AT32_PLLHEXTDIV_DIV1 -#define AT32_PLLCFGEN AT32_PLLCFGEN_SOLID -#define AT32_PLL_FP_VALUE 4 -#define AT32_PLL_FU_VALUE 18 #define AT32_PLL_MS_VALUE 1 #define AT32_PLL_NS_VALUE 72 +#define AT32_PLL_FP_VALUE 4 +#define AT32_PLL_FU_VALUE 18 #define AT32_AHBDIV AT32_AHBDIV_DIV1 #define AT32_APB1DIV AT32_APB1DIV_DIV2 -#define AT32_APB2DIV AT32_APB2DIV_DIV2 -#define AT32_ADCDIV AT32_ADCDIV_DIV4 -#define AT32_USB_CLOCK_REQUIRED TRUE +#define AT32_APB2DIV AT32_APB2DIV_DIV1 +#define AT32_HICK_TO_SCLK AT32_HICK_TO_SCLK_48M +#define AT32_HICKDIV AT32_HICKDIV_DIV1 +#define AT32_HICK_TO_SCLK_DIV AT32_HICK_TO_SCLK_DIV_DIV1 +#define AT32_HEXT_TO_SCLK_DIV AT32_HEXT_TO_SCLK_DIV_DIV1 +#define AT32_USB_CLOCK48_REQUIRED TRUE +#define AT32_PLLU_USB48_SEL AT32_PLLU_USB48_SEL_PLLU #define AT32_CLKOUT_SEL AT32_CLKOUT_SEL_HICK -#define AT32_CLKOUTDIV AT32_CLKOUTDIV_DIV1 -#define AT32_ERTCSEL AT32_ERTCSEL_LICK +#define AT32_CLKOUTDIV1 AT32_CLKOUTDIV1_DIV1 +#define AT32_CLKOUTDIV2 AT32_CLKOUTDIV2_DIV1 +#define AT32_ERTCSEL AT32_ERTCSEL_NOCLOCK +#define AT32_ERTCDIV_VALUE 12 +#define AT32_I2SF5CLKSEL AT32_I2SF5CLKSEL_SCLK #define AT32_PVM_ENABLE FALSE #define AT32_PVMSEL AT32_PVMSEL_LEV1 +#define AT32_LDOOVSEL AT32_LDOOVSEL_LEV3 /* * IRQ system settings. @@ -80,7 +87,6 @@ #define AT32_IRQ_EXINT16_PRIORITY 6 #define AT32_IRQ_EXINT17_PRIORITY 15 #define AT32_IRQ_EXINT18_PRIORITY 6 -#define AT32_IRQ_EXINT19_PRIORITY 6 #define AT32_IRQ_EXINT20_PRIORITY 6 #define AT32_IRQ_EXINT21_PRIORITY 15 #define AT32_IRQ_EXINT22_PRIORITY 15 @@ -92,7 +98,6 @@ #define AT32_IRQ_TMR2_PRIORITY 7 #define AT32_IRQ_TMR3_PRIORITY 7 #define AT32_IRQ_TMR4_PRIORITY 7 -#define AT32_IRQ_TMR5_PRIORITY 7 #define AT32_IRQ_TMR6_PRIORITY 7 #define AT32_IRQ_TMR7_PRIORITY 7 #define AT32_IRQ_TMR13_PRIORITY 7 @@ -110,9 +115,11 @@ /* * ADC driver system settings. */ -#define AT32_ADC_USE_ADC1 TRUE +#define AT32_ADC_USE_ADC1 FALSE #define AT32_ADC_ADC1_DMA_PRIORITY 2 -#define AT32_ADC_ADC1_IRQ_PRIORITY 6 +#define AT32_ADC_IRQ_PRIORITY 6 +#define AT32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define AT32_ADC_ADCDIV 8 /* * CAN driver system settings. @@ -120,11 +127,6 @@ #define AT32_CAN_USE_CAN1 FALSE #define AT32_CAN_CAN1_IRQ_PRIORITY 11 -/* - * DMA driver system settings. - */ -#define AT32_DMA_USE_DMAMUX TRUE - /* * GPT driver system settings. */ @@ -132,7 +134,8 @@ #define AT32_GPT_USE_TMR2 FALSE #define AT32_GPT_USE_TMR3 FALSE #define AT32_GPT_USE_TMR4 FALSE -#define AT32_GPT_USE_TMR5 FALSE +#define AT32_GPT_USE_TMR6 FALSE +#define AT32_GPT_USE_TMR7 FALSE #define AT32_GPT_USE_TMR9 FALSE #define AT32_GPT_USE_TMR10 FALSE #define AT32_GPT_USE_TMR11 FALSE @@ -142,18 +145,16 @@ /* * I2C driver system settings. */ -#define AT32_I2C_USE_I2C1 TRUE +#define AT32_I2C_USE_I2C1 FALSE #define AT32_I2C_USE_I2C2 FALSE -#define AT32_I2C_USE_DMA FALSE +#define AT32_I2C_USE_I2C3 FALSE #define AT32_I2C_BUSY_TIMEOUT 50 -#define AT32_I2C_I2C1_IRQ_PRIORITY 5 -#define AT32_I2C_I2C2_IRQ_PRIORITY 5 #define AT32_I2C_I2C1_DMA_PRIORITY 3 #define AT32_I2C_I2C2_DMA_PRIORITY 3 -#define AT32_I2C_I2C1_RX_DMA_STREAM AT32_DMA_STREAM_ID_ANY -#define AT32_I2C_I2C1_TX_DMA_STREAM AT32_DMA_STREAM_ID_ANY -#define AT32_I2C_I2C2_RX_DMA_STREAM AT32_DMA_STREAM_ID_ANY -#define AT32_I2C_I2C2_TX_DMA_STREAM AT32_DMA_STREAM_ID_ANY +#define AT32_I2C_I2C3_DMA_PRIORITY 3 +#define AT32_I2C_I2C1_IRQ_PRIORITY 5 +#define AT32_I2C_I2C2_IRQ_PRIORITY 5 +#define AT32_I2C_I2C3_IRQ_PRIORITY 5 #define AT32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") /* @@ -163,12 +164,7 @@ #define AT32_ICU_USE_TMR2 FALSE #define AT32_ICU_USE_TMR3 FALSE #define AT32_ICU_USE_TMR4 FALSE -#define AT32_ICU_USE_TMR5 FALSE #define AT32_ICU_USE_TMR9 FALSE -#define AT32_ICU_USE_TMR10 FALSE -#define AT32_ICU_USE_TMR11 FALSE -#define AT32_ICU_USE_TMR13 FALSE -#define AT32_ICU_USE_TMR14 FALSE /* * PWM driver system settings. @@ -177,7 +173,6 @@ #define AT32_PWM_USE_TMR2 FALSE #define AT32_PWM_USE_TMR3 FALSE #define AT32_PWM_USE_TMR4 FALSE -#define AT32_PWM_USE_TMR5 FALSE #define AT32_PWM_USE_TMR9 FALSE #define AT32_PWM_USE_TMR10 FALSE #define AT32_PWM_USE_TMR11 FALSE @@ -192,16 +187,6 @@ #define AT32_ERTC_CTRL_INIT 0 #define AT32_ERTC_TAMP_INIT 0 -/* - * SDC driver system settings. - */ -#define AT32_SDC_SDIO_DMA_PRIORITY 3 -#define AT32_SDC_SDIO_IRQ_PRIORITY 9 -#define AT32_SDC_WRITE_TIMEOUT_MS 1000 -#define AT32_SDC_READ_TIMEOUT_MS 1000 -#define AT32_SDC_CLOCK_ACTIVATION_DELAY 10 -#define AT32_SDC_SDIO_UNALIGNED_SUPPORT TRUE - /* * SERIAL driver system settings. */ @@ -210,21 +195,34 @@ #define AT32_SERIAL_USE_USART3 FALSE #define AT32_SERIAL_USE_UART4 FALSE #define AT32_SERIAL_USE_UART5 FALSE +#define AT32_SERIAL_USE_USART6 FALSE +#define AT32_SERIAL_USE_UART7 FALSE +#define AT32_SERIAL_USE_UART8 FALSE + +/* + * SIO driver system settings. + */ +#define AT32_SIO_USE_USART1 FALSE +#define AT32_SIO_USE_USART2 FALSE +#define AT32_SIO_USE_USART3 FALSE +#define AT32_SIO_USE_UART4 FALSE +#define AT32_SIO_USE_UART5 FALSE +#define AT32_SIO_USE_USART6 FALSE +#define AT32_SIO_USE_UART7 FALSE +#define AT32_SIO_USE_UART8 FALSE /* * SPI driver system settings. */ -#define AT32_SPI_USE_SPI1 TRUE +#define AT32_SPI_USE_SPI1 FALSE #define AT32_SPI_USE_SPI2 FALSE -#define AT32_SPI_SPI1_RX_DMA_STREAM AT32_DMA_STREAM_ID_ANY -#define AT32_SPI_SPI1_TX_DMA_STREAM AT32_DMA_STREAM_ID_ANY -#define AT32_SPI_SPI2_RX_DMA_STREAM AT32_DMA_STREAM_ID_ANY -#define AT32_SPI_SPI2_TX_DMA_STREAM AT32_DMA_STREAM_ID_ANY - +#define AT32_SPI_USE_SPI3 FALSE #define AT32_SPI_SPI1_DMA_PRIORITY 1 #define AT32_SPI_SPI2_DMA_PRIORITY 1 +#define AT32_SPI_SPI3_DMA_PRIORITY 1 #define AT32_SPI_SPI1_IRQ_PRIORITY 10 #define AT32_SPI_SPI2_IRQ_PRIORITY 10 +#define AT32_SPI_SPI3_IRQ_PRIORITY 10 #define AT32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") /* @@ -241,23 +239,14 @@ #define AT32_UART_USE_USART3 FALSE #define AT32_UART_USE_UART4 FALSE #define AT32_UART_USE_UART5 FALSE - -#define AT32_UART_USART1_RX_DMA_STREAM AT32_DMA_STREAM_ID_ANY -#define AT32_UART_USART1_TX_DMA_STREAM AT32_DMA_STREAM_ID_ANY -#define AT32_UART_USART2_RX_DMA_STREAM AT32_DMA_STREAM_ID_ANY -#define AT32_UART_USART2_TX_DMA_STREAM AT32_DMA_STREAM_ID_ANY -#define AT32_UART_USART3_RX_DMA_STREAM AT32_DMA_STREAM_ID_ANY -#define AT32_UART_USART3_TX_DMA_STREAM AT32_DMA_STREAM_ID_ANY -#define AT32_UART_UART4_RX_DMA_STREAM AT32_DMA_STREAM_ID_ANY -#define AT32_UART_UART4_TX_DMA_STREAM AT32_DMA_STREAM_ID_ANY -#define AT32_UART_UART5_RX_DMA_STREAM AT32_DMA_STREAM_ID_ANY -#define AT32_UART_UART5_TX_DMA_STREAM AT32_DMA_STREAM_ID_ANY - +#define AT32_UART_USE_USART6 FALSE +#define AT32_UART_USE_UART7 FALSE +#define AT32_UART_USE_UART8 FALSE #define AT32_UART_USART1_DMA_PRIORITY 0 #define AT32_UART_USART2_DMA_PRIORITY 0 #define AT32_UART_USART3_DMA_PRIORITY 0 -#define AT32_UART_USART4_DMA_PRIORITY 0 -#define AT32_UART_USART5_DMA_PRIORITY 0 +#define AT32_UART_UART4_DMA_PRIORITY 0 +#define AT32_UART_UART5_DMA_PRIORITY 0 #define AT32_UART_USART6_DMA_PRIORITY 0 #define AT32_UART_UART7_DMA_PRIORITY 0 #define AT32_UART_UART8_DMA_PRIORITY 0 @@ -266,27 +255,19 @@ /* * USB driver system settings. */ -#define AT32_USB_USE_OTG1 TRUE +#define AT32_USB_USE_OTG1 FALSE +#define AT32_USB_USE_OTG2 FALSE #define AT32_USB_OTG1_IRQ_PRIORITY 14 -#define AT32_USB_OTG1_RX_FIFO_SIZE 512 - -#define AT32_USB_USE_OTG2 TRUE #define AT32_USB_OTG2_IRQ_PRIORITY 14 +#define AT32_USB_OTG1_RX_FIFO_SIZE 512 #define AT32_USB_OTG2_RX_FIFO_SIZE 1024 -#define AT32_USE_USB_OTG2_HS TRUE -#define AT32_OTG2_SUPPORTS_HS TRUE - +#define AT32_USE_USB_OTG2_HS_DMA FALSE /* * WDG driver system settings. */ #define AT32_WDG_USE_WDT FALSE -/* - * DMA driver Version. - */ -#define AT32_USE_DMA_V1 FALSE - #include "config.h" #endif /* MCUCONF_H */ diff --git a/demos/AT32/RT-AT-START-F405/main.c b/demos/AT32/RT-AT-START-F405/main.c index 65e1853b01..02d637cbd1 100644 --- a/demos/AT32/RT-AT-START-F405/main.c +++ b/demos/AT32/RT-AT-START-F405/main.c @@ -1,8 +1,8 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian - ChibiOS - Copyright (C) 2023..2024 Maxjta + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + ChibiOS - Copyright (C) 2024..2025 Maxjta Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -32,17 +32,11 @@ static THD_FUNCTION(Thread1, arg) { (void)arg; chRegSetThreadName("blinker"); while (true) { - palSetLine(LINE_LED_RED); + palToggleLine(LINE_LED_RED); chThdSleepMilliseconds(250); - palSetLine(LINE_LED_YELLOW); + palToggleLine(LINE_LED_YELLOW); chThdSleepMilliseconds(250); - palSetLine(LINE_LED_GREEN); - chThdSleepMilliseconds(250); - palClearLine(LINE_LED_RED); - chThdSleepMilliseconds(250); - palClearLine(LINE_LED_YELLOW); - chThdSleepMilliseconds(250); - palClearLine(LINE_LED_GREEN); + palToggleLine(LINE_LED_GREEN); chThdSleepMilliseconds(250); } } diff --git a/demos/AT32/RT-AT-START-F415/cfg/chconf.h b/demos/AT32/RT-AT-START-F415/cfg/chconf.h index 46b3f78b68..56fe06776a 100644 --- a/demos/AT32/RT-AT-START-F415/cfg/chconf.h +++ b/demos/AT32/RT-AT-START-F415/cfg/chconf.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/demos/AT32/RT-AT-START-F415/cfg/config.h b/demos/AT32/RT-AT-START-F415/cfg/config.h index 361e185d9c..056a8f39ff 100644 --- a/demos/AT32/RT-AT-START-F415/cfg/config.h +++ b/demos/AT32/RT-AT-START-F415/cfg/config.h @@ -1,6 +1,6 @@ /* - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/demos/AT32/RT-AT-START-F415/cfg/halconf.h b/demos/AT32/RT-AT-START-F415/cfg/halconf.h index 2e7a8067b9..09dfd22866 100644 --- a/demos/AT32/RT-AT-START-F415/cfg/halconf.h +++ b/demos/AT32/RT-AT-START-F415/cfg/halconf.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/demos/AT32/RT-AT-START-F415/cfg/halconf_community.h b/demos/AT32/RT-AT-START-F415/cfg/halconf_community.h index c43d668764..5a77290c71 100644 --- a/demos/AT32/RT-AT-START-F415/cfg/halconf_community.h +++ b/demos/AT32/RT-AT-START-F415/cfg/halconf_community.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/demos/AT32/RT-AT-START-F415/cfg/mcuconf.h b/demos/AT32/RT-AT-START-F415/cfg/mcuconf.h index 9a93b2eca7..86ad2e5cf1 100644 --- a/demos/AT32/RT-AT-START-F415/cfg/mcuconf.h +++ b/demos/AT32/RT-AT-START-F415/cfg/mcuconf.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -106,6 +106,7 @@ #define AT32_ADC_USE_ADC1 FALSE #define AT32_ADC_ADC1_DMA_PRIORITY 2 #define AT32_ADC_ADC1_IRQ_PRIORITY 6 +#define AT32_ADC_ADC1_DMA_IRQ_PRIORITY 6 /* * CAN driver system settings. diff --git a/demos/AT32/RT-AT-START-F415/main.c b/demos/AT32/RT-AT-START-F415/main.c index bca19993a3..1d8790d591 100644 --- a/demos/AT32/RT-AT-START-F415/main.c +++ b/demos/AT32/RT-AT-START-F415/main.c @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/common/ext/CMSIS/ArteryTek/AT32F402_405/at32f402_405.h b/os/common/ext/CMSIS/ArteryTek/AT32F402_405/at32f402_405.h new file mode 100644 index 0000000000..53d4314c28 --- /dev/null +++ b/os/common/ext/CMSIS/ArteryTek/AT32F402_405/at32f402_405.h @@ -0,0 +1,214 @@ +/** + ************************************************************************** + * @file at32f402_405.h + * @author Artery Technology & HorrorTroll & Zhaqian & Maxjta + * @brief AT32F402_405 header file + * + ************************************************************************** + * Copyright notice & Disclaimer + * + * The software Board Support Package (BSP) that is made available to + * download from Artery official website is the copyrighted work of Artery. + * Artery authorizes customers to use, copy, and distribute the BSP + * software and its related documentation for the purpose of design and + * development in conjunction with Artery microcontrollers. Use of the + * software is governed by this copyright notice and the following disclaimer. + * + * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES, + * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS, + * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR + * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS, + * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. + * + ************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup at32f402_405 + * @{ + */ + +#ifndef __AT32F402_405_H +#define __AT32F402_405_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +#if defined (__CC_ARM) + #pragma anon_unions +#endif + +/** @addtogroup Library_configuration_section + * @{ + */ + +/** + * @brief AT32 Family + */ +#if !defined (AT32F402_405) +#define AT32F402_405 +#endif /* AT32F402_405 */ + +/* Uncomment the line below according to the target AT32 device used in your + application + */ + +#if !defined(AT32F402KB) && !defined(AT32F402KC) && !defined(AT32F402CB) && \ + !defined(AT32F402CC) && !defined(AT32F402RB) && !defined(AT32F402RC) + /* #define AT32F402KB */ /*!< AT32F402KB */ + /* #define AT32F402KC */ /*!< AT32F402KC */ + /* #define AT32F402CB */ /*!< AT32F402CB */ + /* #define AT32F402CC */ /*!< AT32F402CC */ + /* #define AT32F402RB */ /*!< AT32F402RB */ + /* #define AT32F402RC */ /*!< AT32F402RC */ +#endif + +#if !defined(AT32F405KB) && !defined(AT32F405KC) && !defined(AT32F405CB) && \ + !defined(AT32F405CC) && !defined(AT32F405RB) && !defined(AT32F405RC) + /* #define AT32F405KB */ /*!< AT32F405KB */ + /* #define AT32F405KC */ /*!< AT32F405KC */ + /* #define AT32F405CB */ /*!< AT32F405CB */ + /* #define AT32F405CC */ /*!< AT32F405CC */ + /* #define AT32F405RB */ /*!< AT32F405RB */ + /* #define AT32F405RC */ /*!< AT32F405RC */ +#endif + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + */ + +#ifndef USE_STDPERIPH_DRIVER +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ + #ifdef _RTE_ + #include "RTE_Components.h" + #ifdef RTE_DEVICE_STDPERIPH_FRAMEWORK + #define USE_STDPERIPH_DRIVER + #endif + #endif +#endif /* USE_STDPERIPH_DRIVER */ + +/** @addtogroup Device_Included + * @{ + */ + +#if defined(AT32F402KB) || defined(AT32F402KC) || \ + defined(AT32F405KB) || defined(AT32F405KC) + #include "at32f402_405kx.h" +#elif defined(AT32F402CB) || defined(AT32F402CC) || \ + defined(AT32F405CB) || defined(AT32F405CC) + #include "at32f402_405cx.h" +#elif defined(AT32F402RB) || defined(AT32F402RC) || \ + defined(AT32F405RB) || defined(AT32F405RC) + #include "at32f402_405rx.h" +#else + #error "Please select first the target AT32F402_405 device used in your application (in at32f402_405.h file)" +#endif + +/** + * @} + */ + +/** @addtogroup Exported_types + * @{ + */ + +typedef int32_t INT32; +typedef int16_t INT16; +typedef int8_t INT8; +typedef uint32_t UINT32; +typedef uint16_t UINT16; +typedef uint8_t UINT8; + +typedef int32_t s32; +typedef int16_t s16; +typedef int8_t s8; + +typedef const int32_t sc32; /*!< read only */ +typedef const int16_t sc16; /*!< read only */ +typedef const int8_t sc8; /*!< read only */ + +typedef __IO int32_t vs32; +typedef __IO int16_t vs16; +typedef __IO int8_t vs8; + +typedef __I int32_t vsc32; /*!< read only */ +typedef __I int16_t vsc16; /*!< read only */ +typedef __I int8_t vsc8; /*!< read only */ + +typedef uint32_t u32; +typedef uint16_t u16; +typedef uint8_t u8; + +typedef const uint32_t uc32; /*!< read only */ +typedef const uint16_t uc16; /*!< read only */ +typedef const uint8_t uc8; /*!< read only */ + +typedef __IO uint32_t vu32; +typedef __IO uint16_t vu16; +typedef __IO uint8_t vu8; + +typedef __I uint32_t vuc32; /*!< read only */ +typedef __I uint16_t vuc16; /*!< read only */ +typedef __I uint8_t vuc8; /*!< read only */ + +/** + * @brief flag status + */ +typedef enum {RESET = 0, SET = !RESET} flag_status; + +/** + * @brief confirm state + */ +typedef enum {DISABLE = 0, ENABLE = !DISABLE} confirm_state; + +/** + * @brief error status + */ +typedef enum {ERROR = 0, SUCCESS = !ERROR} error_status; + +/** + * @} + */ + + +/** @addtogroup Exported_macros + * @{ + */ + +#define REG8(addr) *(volatile uint8_t *)(addr) +#define REG16(addr) *(volatile uint16_t *)(addr) +#define REG32(addr) *(volatile uint32_t *)(addr) + +#define MAKE_VALUE(reg_offset, bit_num) (uint32_t)(((reg_offset) << 16) | (bit_num & 0x1F)) + +#define PERIPH_REG(periph_base, value) REG32((periph_base + (value >> 16))) +#define PERIPH_REG_BIT(value) (0x1U << (value & 0x1F)) + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __AT32F402_405_H */ + +/** + * @} + */ + +/** + * @} + */ + +/*********************** (C) COPYRIGHT Artery Technology *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ArteryTek/AT32F402_405/at32f402_405cx.h b/os/common/ext/CMSIS/ArteryTek/AT32F402_405/at32f402_405cx.h new file mode 100644 index 0000000000..5d029d01ef --- /dev/null +++ b/os/common/ext/CMSIS/ArteryTek/AT32F402_405/at32f402_405cx.h @@ -0,0 +1,11148 @@ +/** + ************************************************************************** + * @file at32f402_405cx.h + * @author Artery Technology & HorrorTroll & Zhaqian & Maxjta + * @version v2.1.2 + * @date 20-Jan-2025 + * @brief AT32F402_405Cx header file. + * + ************************************************************************** + * Copyright notice & Disclaimer + * + * The software Board Support Package (BSP) that is made available to + * download from Artery official website is the copyrighted work of Artery. + * Artery authorizes customers to use, copy, and distribute the BSP + * software and its related documentation for the purpose of design and + * development in conjunction with Artery microcontrollers. Use of the + * software is governed by this copyright notice and the following disclaimer. + * + * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES, + * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS, + * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR + * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS, + * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. + * + ************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup at32f402_405cx + * @{ + */ + +#ifndef __AT32F402_405Cx_H +#define __AT32F402_405Cx_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** + * @brief CMSIS Device version number V2.1.2 + */ +#define __AT32F402_405_LIBRARY_VERSION_MAJOR (0x02) /*!< [31:24] major version */ +#define __AT32F402_405_LIBRARY_VERSION_MIDDLE (0x01) /*!< [23:16] middle version */ +#define __AT32F402_405_LIBRARY_VERSION_MINOR (0x02) /*!< [15:8] minor version */ +#define __AT32F402_405_LIBRARY_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __AT32F402_405_LIBRARY_VERSION ((__AT32F402_405_LIBRARY_VERSION_MAJOR << 24)\ + |(__AT32F402_405_LIBRARY_VERSION_MIDDLE << 16)\ + |(__AT32F402_405_LIBRARY_VERSION_MINOR << 8 )\ + |(__AT32F402_405_LIBRARY_VERSION_RC)) + +/** + * @} + */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ +#define __CM4_REV 0x0001U /*!< Core Revision r0p1 */ +#define __MPU_PRESENT 1U /*!< AT32 devices provide an MPU */ +#define __NVIC_PRIO_BITS 4U /*!< AT32 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /*!< AT32 devices provide an FPU */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief AT32F402_405Cx Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ + + /*!< Interrupt Number Definition */ +typedef enum +{ +/****** Cortex-M4 Processor Exceptions Numbers ***************************************************/ + Reset_IRQn = -15, /*!< 1 Reset Vector Interrupt */ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + +/****** AT32 specific Interrupt Numbers **********************************************************/ + WWDT_IRQn = 0, /*!< Window WatchDog Timer Interrupt */ + PVM_IRQn = 1, /*!< PVM Interrupt linked to EXINT16 */ + TAMPER_IRQn = 2, /*!< Tamper Interrupt linked to EXINT21 */ + ERTC_WKUP_IRQn = 3, /*!< ERTC Wake Up Interrupt linked to EXINT22 */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + CRM_IRQn = 5, /*!< CRM global Interrupt */ + EXINT0_IRQn = 6, /*!< EXINT Line 0 Interrupt */ + EXINT1_IRQn = 7, /*!< EXINT Line 1 Interrupt */ + EXINT2_IRQn = 8, /*!< EXINT Line 2 Interrupt */ + EXINT3_IRQn = 9, /*!< EXINT Line 3 Interrupt */ + EXINT4_IRQn = 10, /*!< EXINT Line 4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ + ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ + CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ + CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SE_IRQn = 22, /*!< CAN1 SE Interrupt */ + EXINT9_5_IRQn = 23, /*!< EXINT Line[9:5] Interrupts */ + TMR1_BRK_TMR9_IRQn = 24, /*!< TMR1 Break Interrupt and TMR9 global Interrupt */ + TMR1_OVF_TMR10_IRQn = 25, /*!< TMR1 Overflow Interrupt and TMR10 global Interrupt */ + TMR1_TRG_HALL_TMR11_IRQn = 26, /*!< TMR1 Trigger and Hall Interrupt and TMR11 global IRQ */ + TMR1_CH_IRQn = 27, /*!< TMR1 Channel Interrupt */ + TMR2_GLOBAL_IRQn = 28, /*!< TMR2 global Interrupt */ + TMR3_GLOBAL_IRQn = 29, /*!< TMR3 global Interrupt */ + TMR4_GLOBAL_IRQn = 30, /*!< TMR4 global Interrupt */ + I2C1_EVT_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ERR_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EVT_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ERR_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXINT15_10_IRQn = 40, /*!< EXINT Line[15:10] Interrupts */ + ERTCAlarm_IRQn = 41, /*!< ERTC Alarm Interrupt linked to EXINT17 */ + OTGFS_WKUP_IRQn = 42, /*!< OTGFS Wake Up Interrupt linked to EXINT18 */ + TMR13_GLOBAL_IRQn = 44, /*!< TMR13 global Interrupt */ + TMR14_GLOBAL_IRQn = 45, /*!< TMR14 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + USART4_IRQn = 52, /*!< USART4 global Interrupt */ + USART5_IRQn = 53, /*!< USART5 global Interrupt */ + TMR6_GLOBAL_IRQn = 54, /*!< TMR6 global Interrupt */ + TMR7_GLOBAL_IRQn = 55, /*!< TMR7 global Interrupt */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ + DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ + OTGFS_IRQn = 67, /*!< OTGFS global Interrupt */ + DMA2_Channel6_IRQn = 68, /*!< DMA2 Channel 6 global Interrupt */ + DMA2_Channel7_IRQn = 69, /*!< DMA2 Channel 7 global Interrupt */ + USART6_IRQn = 71, /*!< USART6 global Interrupt */ + I2C3_EVT_IRQn = 72, /*!< I2C3 Event Interrupt */ + I2C3_ERR_IRQn = 73, /*!< I2C3 Error Interrupt */ + OTGHS_EP1_OUT_IRQn = 74, /*!< OTGHS Endpoint 1 OUT Interrupt (F405 only) */ + OTGHS_EP1_IN_IRQn = 75, /*!< OTGHS Endpoint 1 IN Interrupt (F405 only) */ + OTGHS_WKUP_IRQn = 76, /*!< OTGHS Wake Up IRQ linked to EXINT20 (F405 only) */ + OTGHS_IRQn = 77, /*!< OTGHS global Interrupt (F405 only) */ + FPU_IRQn = 81, /*!< FPU exception Interrupt */ + UART7_IRQn = 82, /*!< UART7 global Interrupt */ + I2SF5_IRQn = 85, /*!< I2SF5 global Interrupt */ + QSPI1_IRQn = 92, /*!< QSPI1 global Interrupt */ + DMAMUX_IRQn = 94, /*!< DMAMUX overflow Interrupt */ + ACC_IRQn = 103, /*!< ACC global Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm4.h" +#include "system_at32f402_405.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief HICK Auto Clock Calibration + */ + +typedef struct +{ + __IO uint32_t STS; /*!< ACC Status register, Address offset: 0x00 */ + __IO uint32_t CTRL1; /*!< ACC Control register 1, Address offset: 0x04 */ + __IO uint32_t CTRL2; /*!< ACC Control register 2, Address offset: 0x08 */ + __IO uint32_t CP1; /*!< ACC Compare value 1, Address offset: 0x0C */ + __IO uint32_t CP2; /*!< ACC Compare value 2, Address offset: 0x10 */ + __IO uint32_t CP3; /*!< ACC Compare value 3, Address offset: 0x14 */ +} ACC_TypeDef; + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t STS; /*!< ADC status register, Address offset: 0x000 */ + __IO uint32_t CTRL1; /*!< ADC control register 1, Address offset: 0x004 */ + __IO uint32_t CTRL2; /*!< ADC control register 2, Address offset: 0x008 */ + __IO uint32_t SPT1; /*!< ADC sampling time register 1, Address offset: 0x00C */ + __IO uint32_t SPT2; /*!< ADC sampling time register 2, Address offset: 0x010 */ + __IO uint32_t PCDTO1; /*!< ADC preempted channel data offset reg 1, Address offset: 0x014 */ + __IO uint32_t PCDTO2; /*!< ADC preempted channel data offset reg 2, Address offset: 0x018 */ + __IO uint32_t PCDTO3; /*!< ADC preempted channel data offset reg 3, Address offset: 0x01C */ + __IO uint32_t PCDTO4; /*!< ADC preempted channel data offset reg 4, Address offset: 0x020 */ + __IO uint32_t VMHB; /*!< ADC voltage monitor high threshold register, Address offset: 0x024 */ + __IO uint32_t VMLB; /*!< ADC voltage monitor low threshold register, Address offset: 0x028 */ + __IO uint32_t OSQ1; /*!< ADC ordinary sequence register 1, Address offset: 0x02C */ + __IO uint32_t OSQ2; /*!< ADC ordinary sequence register 2, Address offset: 0x030 */ + __IO uint32_t OSQ3; /*!< ADC ordinary sequence register 3, Address offset: 0x034 */ + __IO uint32_t PSQ; /*!< ADC preempted sequence register, Address offset: 0x038 */ + __IO uint32_t PDT1; /*!< ADC preempted data register 1, Address offset: 0x03C */ + __IO uint32_t PDT2; /*!< ADC preempted data register 2, Address offset: 0x040 */ + __IO uint32_t PDT3; /*!< ADC preempted data register 3, Address offset: 0x044 */ + __IO uint32_t PDT4; /*!< ADC preempted data register 4, Address offset: 0x048 */ + __IO uint32_t ODT; /*!< ADC ordinary data register, Address offset: 0x04C */ + uint32_t RESERVED[12]; /*!< Reserved, Address offset: 0x050 ~ 0x07C */ + __IO uint32_t OVSP; /*!< ADC oversampling register, Address offset: 0x080 */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CCTRL; /*!< ADC common control register, Address offset: 0x304 */ +} ADC_Common_TypeDef; + +/** + * @brief Controller Area Network TX Mailbox Registers + */ + +typedef struct +{ + __IO uint32_t TMI; + __IO uint32_t TMC; + __IO uint32_t TMDTL; + __IO uint32_t TMDTH; +} CAN_TxMailBox_TypeDef; + +/** + * @brief Controller Area Network FIFO Mailbox Registers + */ + +typedef struct +{ + __IO uint32_t RFI; + __IO uint32_t RFC; + __IO uint32_t RFDTL; + __IO uint32_t RFDTH; +} CAN_FIFOMailBox_TypeDef; + +/** + * @brief Controller Area Network Filter Registers + */ + +typedef struct +{ + __IO uint32_t FFB1; + __IO uint32_t FFB2; +} CAN_FilterRegister_TypeDef; + +/** + * @brief Controller Area Network + */ + +typedef struct +{ + __IO uint32_t MCTRL; /*!< CAN master control register, Address offset: 0x000 */ + __IO uint32_t MSTS; /*!< CAN master status register, Address offset: 0x004 */ + __IO uint32_t TSTS; /*!< CAN transmit status register, Address offset: 0x008 */ + __IO uint32_t RF0; /*!< CAN receive FIFO 0 register, Address offset: 0x00C */ + __IO uint32_t RF1; /*!< CAN receive FIFO 1 register, Address offset: 0x010 */ + __IO uint32_t INTEN; /*!< CAN interrupt enable register, Address offset: 0x014 */ + __IO uint32_t ESTS; /*!< CAN error status register, Address offset: 0x018 */ + __IO uint32_t BTMG; /*!< CAN bit timing register, Address offset: 0x01C */ + uint32_t RESERVED0[88]; /*!< Reserved, Address offset: 0x020 ~ 0x17C */ + CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN TX Mailbox registers, Address offset: 0x180 ~ 0x1AC */ + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO Mailbox registers, Address offset: 0x1B0 ~ 0x1CC */ + uint32_t RESERVED1[12]; /*!< Reserved, Address offset: 0x1D0 ~ 0x1FC */ + __IO uint32_t FCTRL; /*!< CAN filter control register, Address offset: 0x200 */ + __IO uint32_t FMCFG; /*!< CAN filter mode configuration register, Address offset: 0x204 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x208 */ + __IO uint32_t FBWCFG; /*!< CAN filter bit width configuration register, Address offset: 0x20C */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x210 */ + __IO uint32_t FRF; /*!< CAN filter FIFO association register, Address offset: 0x214 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x218 */ + __IO uint32_t FACFG; /*!< CAN filter activation control register, Address offset: 0x21C */ + uint32_t RESERVED5[8]; /*!< Reserved, Address offset: 0x220 ~ 0x23C */ + CAN_FilterRegister_TypeDef sFilterRegister[14]; /*!< CAN filter registers, Address offset: 0x240 ~ 0x2AC */ +} CAN_TypeDef; + +/** + * @brief CRC Calculation Unit + */ + +typedef struct +{ + __IO uint32_t DT; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t CDT; /*!< CRC Common data register, Address offset: 0x04 */ + __IO uint32_t CTRL; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x0C */ + __IO uint32_t IDT; /*!< CRC Initialization register, Address offset: 0x10 */ + __IO uint32_t POLY; /*!< CRC Polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Clock and Reset Manage + */ + +typedef struct +{ + __IO uint32_t CTRL; /*!< CRM Clock control register, Address offset: 0x00 */ + __IO uint32_t PLLCFG; /*!< CRM PLL clock configuration register, Address offset: 0x04 */ + __IO uint32_t CFG; /*!< CRM Clock configuration register, Address offset: 0x08 */ + __IO uint32_t CLKINT; /*!< CRM Clock interrupt register, Address offset: 0x0C */ + __IO uint32_t AHBRST1; /*!< CRM AHB peripheral reset register 1, Address offset: 0x10 */ + __IO uint32_t AHBRST2; /*!< CRM AHB peripheral reset register 2, Address offset: 0x14 */ + __IO uint32_t AHBRST3; /*!< CRM AHB peripheral reset register 3, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t APB1RST; /*!< CRM APB1 peripheral reset register, Address offset: 0x20 */ + __IO uint32_t APB2RST; /*!< CRM APB2 peripheral reset register, Address offset: 0x24 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x28 ~ 0x2C */ + __IO uint32_t AHBEN1; /*!< CRM AHB peripheral clock enable register 1, Address offset: 0x30 */ + __IO uint32_t AHBEN2; /*!< CRM AHB peripheral clock enable register 2, Address offset: 0x34 */ + __IO uint32_t AHBEN3; /*!< CRM AHB peripheral clock enable register 3, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x3C */ + __IO uint32_t APB1EN; /*!< CRM APB1 peripheral clock enable register, Address offset: 0x40 */ + __IO uint32_t APB2EN; /*!< CRM APB2 peripheral clock enable register, Address offset: 0x44 */ + uint32_t RESERVED3[2]; /*!< Reserved, Address offset: 0x48 ~ 0x4C */ + __IO uint32_t AHBLPEN1; /*!< CRM AHB periph clk enable in LP mode reg 1, Address offset: 0x50 */ + __IO uint32_t AHBLPEN2; /*!< CRM AHB periph clk enable in LP mode reg 2, Address offset: 0x54 */ + __IO uint32_t AHBLPEN3; /*!< CRM AHB periph clk enable in LP mode reg 3, Address offset: 0x58 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x5C */ + __IO uint32_t APB1LPEN; /*!< CRM APB1 periph clk enable in LP mode reg, Address offset: 0x60 */ + __IO uint32_t APB2LPEN; /*!< CRM APB2 periph clk enable in LP mode reg, Address offset: 0x64 */ + uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x68 ~ 0x6C */ + __IO uint32_t BPDC; /*!< CRM Battery powered domain control register, Address offset: 0x70 */ + __IO uint32_t CTRLSTS; /*!< CRM Control/status register, Address offset: 0x74 */ + __IO uint32_t OTGHS; /*!< CRM OTGHS control register (F405 only), Address offset: 0x78 */ + uint32_t RESERVED6[9]; /*!< Reserved, Address offset: 0x7C ~ 0x9C */ + __IO uint32_t MISC1; /*!< CRM Additional register 1, Address offset: 0xA0 */ + __IO uint32_t MISC2; /*!< CRM Additional register 2, Address offset: 0xA4 */ +} CRM_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< DEBUG device ID, Address offset: 0xE004_2000 */ + __IO uint32_t CTRL; /*!< DEBUG control register, Address offset: 0xE004_2004 */ + __IO uint32_t APB1_PAUSE; /*!< DEBUG APB1 pause register, Address offset: 0xE004_2008 */ + __IO uint32_t APB2_PAUSE; /*!< DEBUG APB2 pause register, Address offset: 0xE004_200C */ + uint32_t RESERVED[4]; /*!< Reserved, Address offset: 0xE004_2010 ~ 0xE004_201C */ + __IO uint32_t SER_ID; /*!< DEBUG serial ID, Address offset: 0xE004_2020 */ +} DEBUG_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCTRL; /*!< DMA channel x configuration register, Address offset: 0x008 + 20 * (x - 1) (x = 1 ... 7) */ + __IO uint32_t CDTCNT; /*!< DMA channel x number of data register, Address offset: 0x00C + 20 * (x - 1) (x = 1 ... 7) */ + __IO uint32_t CPADDR; /*!< DMA channel x peripheral address register, Address offset: 0x010 + 20 * (x - 1) (x = 1 ... 7) */ + __IO uint32_t CMADDR; /*!< DMA channel x memory address register, Address offset: 0x014 + 20 * (x - 1) (x = 1 ... 7) */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t MUXCCTRL; /*!< DMA multiplexed channel x control register, Address offset: 0x104 + 4 * (x - 1) (x = 1 ... 7) */ +} DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t MUXSYNCSTS; /*!< DMA multiplexed channel sync status reg, Address offset: 0x130 */ + __IO uint32_t MUXSYNCCLR; /*!< DMA multiplexed channel irq flag clear reg, Address offset: 0x134 */ +} DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t MUXGCTRL; /*!< DMA multiplexed generator x control reg, Address offset: 0x120 + 4 * (x - 1) (x = 1 ... 4) */ +} DMAMUX_Generator_TypeDef; + +typedef struct +{ + __IO uint32_t MUXGSTS; /*!< DMA multiplexed generator irq status reg, Address offset: 0x138 */ + __IO uint32_t MUXGCLR; /*!< DMA mux generator irq flag clear register, Address offset: 0x13c */ +} DMAMUX_GeneratorStatus_TypeDef; + +typedef struct +{ + __IO uint32_t STS; /*!< DMA interrupt status register, Address offset: 0x000 */ + __IO uint32_t CLR; /*!< DMA interrupt flag clear register, Address offset: 0x004 */ + uint32_t RESERVED[62]; /*!< Reserved, Address offset: 0x008 ~ 0x0FC */ + __IO uint32_t MUXSEL; /*!< DMA multiplexed select register, Address offset: 0x100 */ +} DMA_TypeDef; + +/** + * @brief Enhanced Real-Time Clock + */ + +typedef struct +{ + __IO uint32_t TIME; /*!< ERTC time register, Address offset: 0x00 */ + __IO uint32_t DATE; /*!< ERTC date register, Address offset: 0x04 */ + __IO uint32_t CTRL; /*!< ERTC control register, Address offset: 0x08 */ + __IO uint32_t STS; /*!< ERTC initialization and status register, Address offset: 0x0C */ + __IO uint32_t DIV; /*!< ERTC divider register, Address offset: 0x10 */ + __IO uint32_t WAT; /*!< ERTC wakeup timer register, Address offset: 0x14 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x18 */ + __IO uint32_t ALA; /*!< ERTC alarm clock A register, Address offset: 0x1C */ + __IO uint32_t ALB; /*!< ERTC alarm clock B register, Address offset: 0x20 */ + __IO uint32_t WP; /*!< ERTC write protection register, Address offset: 0x24 */ + __IO uint32_t SBS; /*!< ERTC subsecond register, Address offset: 0x28 */ + __IO uint32_t TADJ; /*!< ERTC time adjustment register, Address offset: 0x2C */ + __IO uint32_t TSTM; /*!< ERTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDT; /*!< ERTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSBS; /*!< ERTC time stamp subsecond register, Address offset: 0x38 */ + __IO uint32_t SCAL; /*!< ERTC smooth calibration register, Address offset: 0x3C */ + __IO uint32_t TAMP; /*!< ERTC tamper configuration register, Address offset: 0x40 */ + __IO uint32_t ALASBS; /*!< ERTC alarm clock A subsecond register, Address offset: 0x44 */ + __IO uint32_t ALBSBS; /*!< ERTC alarm clock B subsecond register, Address offset: 0x48 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x4C */ + __IO uint32_t BPR1; /*!< ERTC battery powered domain data register 1, Address offset: 0x50 */ + __IO uint32_t BPR2; /*!< ERTC battery powered domain data register 2, Address offset: 0x54 */ + __IO uint32_t BPR3; /*!< ERTC battery powered domain data register 3, Address offset: 0x58 */ + __IO uint32_t BPR4; /*!< ERTC battery powered domain data register 4, Address offset: 0x5C */ + __IO uint32_t BPR5; /*!< ERTC battery powered domain data register 5, Address offset: 0x60 */ + __IO uint32_t BPR6; /*!< ERTC battery powered domain data register 6, Address offset: 0x64 */ + __IO uint32_t BPR7; /*!< ERTC battery powered domain data register 7, Address offset: 0x68 */ + __IO uint32_t BPR8; /*!< ERTC battery powered domain data register 8, Address offset: 0x6C */ + __IO uint32_t BPR9; /*!< ERTC battery powered domain data register 9, Address offset: 0x70 */ + __IO uint32_t BPR10; /*!< ERTC BAT powered domain data register 10, Address offset: 0x74 */ + __IO uint32_t BPR11; /*!< ERTC BAT powered domain data register 11, Address offset: 0x78 */ + __IO uint32_t BPR12; /*!< ERTC BAT powered domain data register 12, Address offset: 0x7C */ + __IO uint32_t BPR13; /*!< ERTC BAT powered domain data register 13, Address offset: 0x80 */ + __IO uint32_t BPR14; /*!< ERTC BAT powered domain data register 14, Address offset: 0x84 */ + __IO uint32_t BPR15; /*!< ERTC BAT powered domain data register 15, Address offset: 0x88 */ + __IO uint32_t BPR16; /*!< ERTC BAT powered domain data register 16, Address offset: 0x8C */ + __IO uint32_t BPR17; /*!< ERTC BAT powered domain data register 17, Address offset: 0x90 */ + __IO uint32_t BPR18; /*!< ERTC BAT powered domain data register 18, Address offset: 0x94 */ + __IO uint32_t BPR19; /*!< ERTC BAT powered domain data register 19, Address offset: 0x98 */ + __IO uint32_t BPR20; /*!< ERTC BAT powered domain data register 20, Address offset: 0x9C */ +} ERTC_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t INTEN; /*!< EXINT Interrupt enable register, Address offset: 0x00 */ + __IO uint32_t EVTEN; /*!< EXINT Event enable register, Address offset: 0x04 */ + __IO uint32_t POLCFG1; /*!< EXINT Polarity configuration register 1, Address offset: 0x08 */ + __IO uint32_t POLCFG2; /*!< EXINT Polarity configuration register 2, Address offset: 0x0C */ + __IO uint32_t SWTRG; /*!< EXINT Software trigger register, Address offset: 0x10 */ + __IO uint32_t INTSTS; /*!< EXINT Interrupt status register, Address offset: 0x14 */ +} EXINT_TypeDef; + +/** + * @brief Flash Memory Registers + */ + +typedef struct +{ + __IO uint32_t PSR; /*!< FLASH performance select register, Address offset: 0x00 */ + __IO uint32_t UNLOCK; /*!< FLASH unlock register, Address offset: 0x04 */ + __IO uint32_t USD_UNLOCK; /*!< FLASH user system data unlock register, Address offset: 0x08 */ + __IO uint32_t STS; /*!< FLASH status register, Address offset: 0x0C */ + __IO uint32_t CTRL; /*!< FLASH control register, Address offset: 0x10 */ + __IO uint32_t ADDR; /*!< FLASH address register, Address offset: 0x14 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x18 */ + __IO uint32_t USD; /*!< FLASH user system data register, Address offset: 0x1C */ + __IO uint32_t EPPS; /*!< FLASH erase/program protection status reg, Address offset: 0x20 */ + uint32_t RESERVED1[20]; /*!< Reserved, Address offset: 0x24 ~ 0x70 */ + __IO uint32_t SLIB_STS0; /*!< FLASH security library status register 0, Address offset: 0x74 */ + __IO uint32_t SLIB_STS1; /*!< FLASH security library status register 1, Address offset: 0x78 */ + __IO uint32_t SLIB_PWD_CLR; /*!< FLASH security library password clear reg, Address offset: 0x7C */ + __IO uint32_t SLIB_MISC_STS; /*!< FLASH security library additional stat reg, Address offset: 0x80 */ + __IO uint32_t CRC_ADDR; /*!< FLASH CRC address register, Address offset: 0x84 */ + __IO uint32_t CRC_CTRL; /*!< FLASH CRC control register, Address offset: 0x88 */ + __IO uint32_t CRC_CHKR; /*!< FLASH CRC check result register, Address offset: 0x8C */ + uint32_t RESERVED2[52]; /*!< Reserved, Address offset: 0x90 ~ 0x15C */ + __IO uint32_t SLIB_SET_PWD; /*!< FLASH security library password setting reg, Address offset: 0x160 */ + __IO uint32_t SLIB_SET_RANGE; /*!< FLASH security library address setting reg, Address offset: 0x164 */ + __IO uint32_t EM_SLIB_SET; /*!< FLASH extension mem security lib set reg, Address offset: 0x168 */ + __IO uint32_t BTM_MODE_SET; /*!< FLASH boot memory mode setting register, Address offset: 0x16C */ + __IO uint32_t SLIB_UNLOCK; /*!< FLASH security library unlock register, Address offset: 0x170 */ +} FLASH_TypeDef; + +/** + * @brief User System Data Registers + */ + +typedef struct +{ + __IO uint16_t FAP; /*!< USD memory access protection, Address offset: 0x1FFF_F800 */ + __IO uint16_t SSB; /*!< USD System configuration byte, Address offset: 0x1FFF_F802 */ + __IO uint16_t DATA0; /*!< USD User data 0, Address offset: 0x1FFF_F804 */ + __IO uint16_t DATA1; /*!< USD User data 1, Address offset: 0x1FFF_F806 */ + __IO uint16_t EPP0; /*!< USD erase/write protection byte 0, Address offset: 0x1FFF_F808 */ + __IO uint16_t EPP1; /*!< USD erase/write protection byte 1, Address offset: 0x1FFF_F80A */ + __IO uint16_t EPP2; /*!< USD erase/write protection byte 2, Address offset: 0x1FFF_F80C */ + __IO uint16_t EPP3; /*!< USD erase/write protection byte 3, Address offset: 0x1FFF_F80E */ + uint32_t RESERVED0[9]; /*!< Reserved, Address offset: 0x1FFF_F810 ~ 0x1FFF_F830 */ + __IO uint16_t QSPIKEY0; /*!< USD QSPI ciphertext access area + encryption key byte 0, Address offset: 0x1FFF_F834 */ + __IO uint16_t QSPIKEY1; /*!< USD QSPI ciphertext access area + encryption key byte 1, Address offset: 0x1FFF_F836 */ + __IO uint16_t QSPIKEY2; /*!< USD QSPI ciphertext access area + encryption key byte 2, Address offset: 0x1FFF_F838 */ + __IO uint16_t QSPIKEY3; /*!< USD QSPI ciphertext access area + encryption key byte 3, Address offset: 0x1FFF_F83A */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x1FFF_F83C ~ 0x1FFF_F848 */ + __IO uint16_t DATA[218]; /*!< USD User data 2 ~ 219, Address offset: 0x1FFF_F84C ~ 0x1FFF_F9FC */ +} USD_TypeDef; + +/** + * @brief General Purpose I/O or Multiplexed Function I/O + */ + +typedef struct +{ + __IO uint32_t CFGR; /*!< GPIO configuration register, Address offset: 0x00 */ + __IO uint32_t OMODE; /*!< GPIO output mode register, Address offset: 0x04 */ + __IO uint32_t ODRVR; /*!< GPIO drive capability register, Address offset: 0x08 */ + __IO uint32_t PULL; /*!< GPIO pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDT; /*!< GPIO input data register, Address offset: 0x10 */ + __IO uint32_t ODT; /*!< GPIO output data register, Address offset: 0x14 */ + __IO uint32_t SCR; /*!< GPIO set/clear register, Address offset: 0x18 */ + __IO uint32_t WPR; /*!< GPIO write protection register, Address offset: 0x1C */ + __IO uint32_t MUXL; /*!< GPIO multiplexed function low register, Address offset: 0x20 */ + __IO uint32_t MUXH; /*!< GPIO multiplexed function high register, Address offset: 0x24 */ + __IO uint32_t CLR; /*!< GPIO port bit clear register, Address offset: 0x28 */ + __IO uint32_t TOGR; /*!< GPIO port bit toggle register, Address offset: 0x2C */ + uint32_t RESERVED[3]; /*!< Reserved, Address offset: 0x30 ~ 0x38 */ + __IO uint32_t HDRV; /*!< GPIO huge current control register, Address offset: 0x3C */ + __IO uint32_t SRCTR; /*!< GPIO SRCTR register, Address offset: 0x40 */ +} GPIO_TypeDef; + +/** + * @brief Inter Integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CTRL1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CTRL2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OADDR1; /*!< I2C Own address register 1, Address offset: 0x08 */ + __IO uint32_t OADDR2; /*!< I2C Own address register 2, Address offset: 0x0C */ + __IO uint32_t CLKCTRL; /*!< I2C Clock control register, Address offset: 0x10 */ + __IO uint32_t TIMEOUT; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t STS; /*!< I2C Status register, Address offset: 0x18 */ + __IO uint32_t CLR; /*!< I2C Status clear flag register, Address offset: 0x1C */ + __IO uint32_t PEC; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDT; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDT; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CTRL; /*!< PWC Power control register, Address offset: 0x00 */ + __IO uint32_t CTRLSTS; /*!< PWC Power control/status register, Address offset: 0x04 */ + uint32_t RESERVED[2]; /*!< Reserved, Address offset: 0x08 ~ 0x0C */ + __IO uint32_t LDOOV; /*!< PWC LDO output voltage select register, Address offset: 0x10 */ +} PWC_TypeDef; + +/** + * @brief Quad-SPI Interface + */ + +typedef struct +{ + __IO uint32_t CMD_W0; /*!< QSPI Command word 0 register, Address offset: 0x00 */ + __IO uint32_t CMD_W1; /*!< QSPI Command word 1 register, Address offset: 0x04 */ + __IO uint32_t CMD_W2; /*!< QSPI Command word 2 register, Address offset: 0x08 */ + __IO uint32_t CMD_W3; /*!< QSPI Command word 3 register, Address offset: 0x0C */ + __IO uint32_t CTRL; /*!< QSPI Control register, Address offset: 0x10 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t FIFOSTS; /*!< QSPI FIFO status register, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t CTRL2; /*!< QSPI Control register 2, Address offset: 0x20 */ + __IO uint32_t CMDSTS; /*!< QSPI Command status register, Address offset: 0x24 */ + __IO uint32_t RSTS; /*!< QSPI Read status register, Address offset: 0x28 */ + __IO uint32_t FSIZE; /*!< QSPI Flash size register, Address offset: 0x2C */ + __IO uint32_t XIP_CMD_W0; /*!< QSPI XIP command word 0 register, Address offset: 0x30 */ + __IO uint32_t XIP_CMD_W1; /*!< QSPI XIP command word 1 register, Address offset: 0x34 */ + __IO uint32_t XIP_CMD_W2; /*!< QSPI XIP command word 2 register, Address offset: 0x38 */ + __IO uint32_t XIP_CMD_W3; /*!< QSPI XIP command word 3 register, Address offset: 0x3C */ + __IO uint32_t CTRL3; /*!< QSPI Control register 3, Address offset: 0x40 */ + uint32_t RESERVED2[3]; /*!< Reserved, Address offset: 0x44 ~ 0x4C */ + __IO uint32_t REV; /*!< QSPI Revision register, Address offset: 0x50 */ + uint32_t RESERVED3[43]; /*!< Reserved, Address offset: 0x54 ~ 0xFC */ + __IO uint8_t DT_U8; /*!< QSPI Data port (8-bit) register, Address offset: 0x100 */ + __IO uint16_t DT_U16; /*!< QSPI Data port (16-bit) register, Address offset: 0x100 */ + __IO uint32_t DT; /*!< QSPI Data port register, Address offset: 0x100 */ +} QSPI_TypeDef; + +/** + * @brief System Configuration Controller + */ + +typedef struct +{ + __IO uint32_t CFG1; /*!< SCFG configuration register 1, Address offset: 0x00 */ + __IO uint32_t CFG2; /*!< SCFG configuration register 2, Address offset: 0x04 */ + __IO uint32_t EXINTC[4]; /*!< SCFG external interrupt config register x, Address offset: 0x08 ~ 0x14 */ + uint32_t RESERVED[5]; /*!< Reserved, Address offset: 0x18 ~ 0x28 */ + __IO uint32_t UHDRV; /*!< SCFG ultra high source/sinking strength reg, Address offset: 0x2C */ +} SCFG_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CTRL1; /*!< SPI control register 1, Address offset: 0x00 */ + __IO uint32_t CTRL2; /*!< SPI control register 2, Address offset: 0x04 */ + __IO uint32_t STS; /*!< SPI status register, Address offset: 0x08 */ + __IO uint32_t DT; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CPOLY; /*!< SPI CRC register, Address offset: 0x10 */ + __IO uint32_t RCRC; /*!< SPI receive CRC register, Address offset: 0x14 */ + __IO uint32_t TCRC; /*!< SPI transmit CRC register, Address offset: 0x18 */ + __IO uint32_t I2SCTRL; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + __IO uint32_t I2SCLKP; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ + uint32_t RESERVED[3]; /*!< Reserved, Address offset: 0x24 ~ 0x2C */ + __IO uint32_t MISC1; /*!< SPI_I2SF5 additional register, Address offset: 0x30 */ +} SPI_TypeDef; + +/** + * @brief TMR Timers + */ + +typedef struct +{ + __IO uint32_t CTRL1; /*!< TMR control register 1, Address offset: 0x00 */ + __IO uint32_t CTRL2; /*!< TMR control register 2, Address offset: 0x04 */ + __IO uint32_t STCTRL; /*!< TMR slave timer control register, Address offset: 0x08 */ + __IO uint32_t IDEN; /*!< TMR DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t ISTS; /*!< TMR interrupt status register, Address offset: 0x10 */ + __IO uint32_t SWEVT; /*!< TMR software event register, Address offset: 0x14 */ + __IO uint32_t CM1; /*!< TMR channel mode register 1, Address offset: 0x18 */ + __IO uint32_t CM2; /*!< TMR channel mode register 2, Address offset: 0x1C */ + __IO uint32_t CCTRL; /*!< TMR channel control register, Address offset: 0x20 */ + __IO uint32_t CVAL; /*!< TMR counter value register, Address offset: 0x24 */ + __IO uint32_t DIV; /*!< TMR division value register, Address offset: 0x28 */ + __IO uint32_t PR; /*!< TMR period register, Address offset: 0x2C */ + __IO uint32_t RPR; /*!< TMR repetition period register, Address offset: 0x30 */ + __IO uint32_t C1DT; /*!< TMR channel 1 data register, Address offset: 0x34 */ + __IO uint32_t C2DT; /*!< TMR channel 2 data register, Address offset: 0x38 */ + __IO uint32_t C3DT; /*!< TMR channel 3 data register, Address offset: 0x3C */ + __IO uint32_t C4DT; /*!< TMR channel 4 data register, Address offset: 0x40 */ + __IO uint32_t BRK; /*!< TMR break register, Address offset: 0x44 */ + __IO uint32_t DMACTRL; /*!< TMR DMA control register, Address offset: 0x48 */ + __IO uint32_t DMADT; /*!< TMR DMA data register, Address offset: 0x4C */ + __IO uint32_t RMP; /*!< TMR channel input remap register, Address offset: 0x50 */ +} TMR_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint32_t STS; /*!< USART status register, Address offset: 0x00 */ + __IO uint32_t DT; /*!< USART data register, Address offset: 0x04 */ + __IO uint32_t BAUDR; /*!< USART baud rate register, Address offset: 0x08 */ + __IO uint32_t CTRL1; /*!< USART control register 1, Address offset: 0x0C */ + __IO uint32_t CTRL2; /*!< USART control register 2, Address offset: 0x10 */ + __IO uint32_t CTRL3; /*!< USART control register 3, Address offset: 0x14 */ + __IO uint32_t GDIV; /*!< USART guard time and divider register, Address offset: 0x18 */ + __IO uint32_t RTOV; /*!< USART receiver timeout detection register, Address offset: 0x1C */ + __IO uint32_t IFC; /*!< USART interrupt flag clear register, Address offset: 0x20 */ +} USART_TypeDef; + +/** + * @brief WATCHDOG Timer + */ + +typedef struct +{ + __IO uint32_t CMD; /*!< WDT Command register, Address offset: 0x00 */ + __IO uint32_t DIV; /*!< WDT Divider register, Address offset: 0x04 */ + __IO uint32_t RLD; /*!< WDT Reload register, Address offset: 0x08 */ + __IO uint32_t STS; /*!< WDT Status register, Address offset: 0x0C */ + __IO uint32_t WIN; /*!< WDT Window register, Address offset: 0x10 */ +} WDT_TypeDef; + +/** + * @brief Window WATCHDOG Timer + */ + +typedef struct +{ + __IO uint32_t CTRL; /*!< WWDT Control register, Address offset: 0x00 */ + __IO uint32_t CFG; /*!< WWDT Configuration register, Address offset: 0x04 */ + __IO uint32_t STS; /*!< WWDT Status register, Address offset: 0x08 */ +} WWDT_TypeDef; + +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ + +#define FLASH_BASE 0x08000000U /*!< FLASH base address in the alias region */ +#define FLASH_BANK1_END 0x0803FFFFU /*!< FLASH end address of bank 1 */ +#define QSPI1_BASE 0x90000000U /*!< QSPI1 base address */ +#define SRAM_BASE 0x20000000U /*!< SRAM base address in the alias region */ +#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */ + +#define SRAM_BB_BASE 0x22000000U /*!< SRAM base address in the bit-band region */ +#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE /*!< APB1 base address */ +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U) /*!< APB2 base address */ +#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000U) /*!< AHB base address */ + +#define TMR2_BASE (APB1PERIPH_BASE + 0x00000000U) /*!< TMR2 base address */ +#define TMR3_BASE (APB1PERIPH_BASE + 0x00000400U) /*!< TMR3 base address */ +#define TMR4_BASE (APB1PERIPH_BASE + 0x00000800U) /*!< TMR4 base address */ +#define TMR6_BASE (APB1PERIPH_BASE + 0x00001000U) /*!< TMR6 base address */ +#define TMR7_BASE (APB1PERIPH_BASE + 0x00001400U) /*!< TMR7 base address */ +#define TMR13_BASE (APB1PERIPH_BASE + 0x00001C00U) /*!< TMR13 base address */ +#define TMR14_BASE (APB1PERIPH_BASE + 0x00002000U) /*!< TMR14 base address */ +#define ERTC_BASE (APB1PERIPH_BASE + 0x00002800U) /*!< ERTC base address */ +#define WWDT_BASE (APB1PERIPH_BASE + 0x00002C00U) /*!< WWDT base address */ +#define WDT_BASE (APB1PERIPH_BASE + 0x00003000U) /*!< WDT base address */ +#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800U) /*!< SPI2 base address */ +#define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00U) /*!< SPI3 base address */ +#define USART2_BASE (APB1PERIPH_BASE + 0x00004400U) /*!< USART2 base address */ +#define USART3_BASE (APB1PERIPH_BASE + 0x00004800U) /*!< USART3 base address */ +#define USART4_BASE (APB1PERIPH_BASE + 0x00004C00U) /*!< USART4 base address */ +#define USART5_BASE (APB1PERIPH_BASE + 0x00005000U) /*!< USART5 base address */ +#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400U) /*!< I2C1 base address */ +#define I2C2_BASE (APB1PERIPH_BASE + 0x00005800U) /*!< I2C2 base address */ +#define I2C3_BASE (APB1PERIPH_BASE + 0x00005C00U) /*!< I2C3 base address */ +#define CAN1_BASE (APB1PERIPH_BASE + 0x00006400U) /*!< CAN1 base address */ +#define PWC_BASE (APB1PERIPH_BASE + 0x00007000U) /*!< PWC base address */ +#define UART7_BASE (APB1PERIPH_BASE + 0x00007800U) /*!< UART7 base address */ + +#define TMR1_BASE (APB2PERIPH_BASE + 0x00000000U) /*!< TMR1 base address */ +#define USART1_BASE (APB2PERIPH_BASE + 0x00001000U) /*!< USART1 base address */ +#define USART6_BASE (APB2PERIPH_BASE + 0x00001400U) /*!< USART6 base address */ + +#define ADC1_BASE (APB2PERIPH_BASE + 0x00002000U) /*!< ADC1 base address */ +#define ADC_Common_BASE (APB2PERIPH_BASE + 0x00002300U) /*!< ADC Common base address */ + +#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000U) /*!< SPI1 base address */ +#define SCFG_BASE (APB2PERIPH_BASE + 0x00003800U) /*!< SCFG base address */ +#define EXINT_BASE (APB2PERIPH_BASE + 0x00003C00U) /*!< EXINT base address */ +#define TMR9_BASE (APB2PERIPH_BASE + 0x00004000U) /*!< TMR9 base address */ +#define TMR10_BASE (APB2PERIPH_BASE + 0x00004400U) /*!< TMR10 base address */ +#define TMR11_BASE (APB2PERIPH_BASE + 0x00004800U) /*!< TMR11 base address */ +#define I2SF5_BASE (APB2PERIPH_BASE + 0x00005000U) /*!< I2SF5 base address */ +#define ACC_BASE (APB2PERIPH_BASE + 0x00007400U) /*!< ACC base address */ + +#define GPIOA_BASE (AHBPERIPH_BASE + 0x00000000U) /*!< GPIOA base address */ +#define GPIOB_BASE (AHBPERIPH_BASE + 0x00000400U) /*!< GPIOB base address */ +#define GPIOC_BASE (AHBPERIPH_BASE + 0x00000800U) /*!< GPIOC base address */ +#define GPIOD_BASE (AHBPERIPH_BASE + 0x00000C00U) /*!< GPIOD base address */ +#define GPIOF_BASE (AHBPERIPH_BASE + 0x00001400U) /*!< GPIOF base address */ +#define CRC_BASE (AHBPERIPH_BASE + 0x00003000U) /*!< CRC base address */ +#define CRM_BASE (AHBPERIPH_BASE + 0x00003800U) /*!< CRM base address */ + +#define DMA1_BASE (AHBPERIPH_BASE + 0x00006000U) /*!< DMA1 base address */ +#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x00006008U) /*!< DMA1 Channel 1 base address */ +#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x0000601CU) /*!< DMA1 Channel 2 base address */ +#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x00006030U) /*!< DMA1 Channel 3 base address */ +#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x00006044U) /*!< DMA1 Channel 4 base address */ +#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x00006058U) /*!< DMA1 Channel 5 base address */ +#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x0000606CU) /*!< DMA1 Channel 6 base address */ +#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x00006080U) /*!< DMA1 Channel 7 base address */ + +#define DMA1MUX_BASE (AHBPERIPH_BASE + 0x00006104U) /*!< DMA1 Multiplexed base address */ +#define DMA1MUX_Channel1_BASE (DMA1MUX_BASE) /*!< DMA1 Multiplexed Channel 1 base address */ +#define DMA1MUX_Channel2_BASE (AHBPERIPH_BASE + 0x00006108U) /*!< DMA1 Multiplexed Channel 2 base address */ +#define DMA1MUX_Channel3_BASE (AHBPERIPH_BASE + 0x0000610CU) /*!< DMA1 Multiplexed Channel 3 base address */ +#define DMA1MUX_Channel4_BASE (AHBPERIPH_BASE + 0x00006110U) /*!< DMA1 Multiplexed Channel 4 base address */ +#define DMA1MUX_Channel5_BASE (AHBPERIPH_BASE + 0x00006114U) /*!< DMA1 Multiplexed Channel 5 base address */ +#define DMA1MUX_Channel6_BASE (AHBPERIPH_BASE + 0x00006118U) /*!< DMA1 Multiplexed Channel 6 base address */ +#define DMA1MUX_Channel7_BASE (AHBPERIPH_BASE + 0x0000611CU) /*!< DMA1 Multiplexed Channel 7 base address */ +#define DMA1MUX_Generator1_BASE (AHBPERIPH_BASE + 0x00006120U) /*!< DMA1 Multiplexed Generator 1 base address */ +#define DMA1MUX_Generator2_BASE (AHBPERIPH_BASE + 0x00006124U) /*!< DMA1 Multiplexed Generator 2 base address */ +#define DMA1MUX_Generator3_BASE (AHBPERIPH_BASE + 0x00006128U) /*!< DMA1 Multiplexed Generator 3 base address */ +#define DMA1MUX_Generator4_BASE (AHBPERIPH_BASE + 0x0000612CU) /*!< DMA1 Multiplexed Generator 4 base address */ +#define DMA1MUX_ChannelStatus_BASE (AHBPERIPH_BASE + 0x00006130U) /*!< DMA1 Multiplexed Channel status base address */ +#define DMA1MUX_GeneratorStatus_BASE (AHBPERIPH_BASE + 0x00006138U) /*!< DMA1 Multiplexed Generator status base address */ + +#define DMA2_BASE (AHBPERIPH_BASE + 0x00006400U) /*!< DMA2 base address */ +#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x00006408U) /*!< DMA2 Channel 1 base address */ +#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x0000641CU) /*!< DMA2 Channel 2 base address */ +#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x00006430U) /*!< DMA2 Channel 3 base address */ +#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x00006444U) /*!< DMA2 Channel 4 base address */ +#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x00006458U) /*!< DMA2 Channel 5 base address */ +#define DMA2_Channel6_BASE (AHBPERIPH_BASE + 0x0000646CU) /*!< DMA2 Channel 6 base address */ +#define DMA2_Channel7_BASE (AHBPERIPH_BASE + 0x00006480U) /*!< DMA2 Channel 7 base address */ + +#define DMA2MUX_BASE (AHBPERIPH_BASE + 0x00006504U) /*!< DMA2 Multiplexed base address */ +#define DMA2MUX_Channel1_BASE (DMA2MUX_BASE) /*!< DMA2 Multiplexed Channel 1 base address */ +#define DMA2MUX_Channel2_BASE (AHBPERIPH_BASE + 0x00006508U) /*!< DMA2 Multiplexed Channel 2 base address */ +#define DMA2MUX_Channel3_BASE (AHBPERIPH_BASE + 0x0000650CU) /*!< DMA2 Multiplexed Channel 3 base address */ +#define DMA2MUX_Channel4_BASE (AHBPERIPH_BASE + 0x00006510U) /*!< DMA2 Multiplexed Channel 4 base address */ +#define DMA2MUX_Channel5_BASE (AHBPERIPH_BASE + 0x00006514U) /*!< DMA2 Multiplexed Channel 5 base address */ +#define DMA2MUX_Channel6_BASE (AHBPERIPH_BASE + 0x00006518U) /*!< DMA2 Multiplexed Channel 6 base address */ +#define DMA2MUX_Channel7_BASE (AHBPERIPH_BASE + 0x0000651CU) /*!< DMA2 Multiplexed Channel 7 base address */ +#define DMA2MUX_Generator1_BASE (AHBPERIPH_BASE + 0x00006520U) /*!< DMA2 Multiplexed Generator 1 base address */ +#define DMA2MUX_Generator2_BASE (AHBPERIPH_BASE + 0x00006524U) /*!< DMA2 Multiplexed Generator 2 base address */ +#define DMA2MUX_Generator3_BASE (AHBPERIPH_BASE + 0x00006528U) /*!< DMA2 Multiplexed Generator 3 base address */ +#define DMA2MUX_Generator4_BASE (AHBPERIPH_BASE + 0x0000652CU) /*!< DMA2 Multiplexed Generator 4 base address */ +#define DMA2MUX_ChannelStatus_BASE (AHBPERIPH_BASE + 0x00006530U) /*!< DMA2 Multiplexed Channel status base address */ +#define DMA2MUX_GeneratorStatus_BASE (AHBPERIPH_BASE + 0x00006538U) /*!< DMA2 Multiplexed Generator status base address */ + +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00003C00U) /*!< FLASH registers base address */ +#define QSPI1_R_BASE 0xA0001000U /*!< QSPI1 registers base address */ +#define FLASHSIZE_BASE 0x1FFFF7E0U /*!< FLASH Size register base address */ +#define UID_BASE 0x1FFFF7E8U /*!< Unique device ID register base address */ +#define USD_BASE 0x1FFFF800U /*!< FLASH User System Data base address */ + +#define DEBUG_BASE 0xE0042000U /*!< Debug MCU registers base address */ + +/* USB OTG FS */ +#define USB_OTG_FS_PERIPH_BASE 0x50000000U /*!< USB OTG FS Peripheral Registers base address */ + +/* USB OTG HS (F405 only) */ +#define USB_OTG_HS_PERIPH_BASE 0x40040000U /*!< USB OTG HS Peripheral Registers base address */ + +#define USB_OTG_GLOBAL_BASE 0x00000000U /*!< USB OTG Global Registers base address */ +#define USB_OTG_DEVICE_BASE 0x00000800U /*!< USB OTG Device ModeRegisters base address */ +#define USB_OTG_IN_ENDPOINT_BASE 0x00000900U /*!< USB OTG IN Endpoint Registers base address */ +#define USB_OTG_OUT_ENDPOINT_BASE 0x00000B00U /*!< USB OTG OUT Endpoint Registers base address */ +#define USB_OTG_EP_REG_SIZE 0x00000020U /*!< USB OTG All Endpoint Registers size address */ +#define USB_OTG_HOST_BASE 0x00000400U /*!< USB OTG Host Mode Registers base address */ +#define USB_OTG_HOST_PORT_BASE 0x00000440U /*!< USB OTG Host Port Registers base address */ +#define USB_OTG_HOST_CHANNEL_BASE 0x00000500U /*!< USB OTG Host Channel Registers base address */ +#define USB_OTG_HOST_CHANNEL_SIZE 0x00000020U /*!< USB OTG Host Channel Registers size address */ +#define USB_OTG_PCGCCTL_BASE 0x00000E00U /*!< USB OTG Power and Ctrl Registers base address */ +#define USB_OTG_FIFO_BASE 0x00001000U /*!< USB OTG FIFO Registers base address */ +#define USB_OTG_FIFO_SIZE 0x00001000U /*!< USB OTG FIFO Registers size address */ + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ + +#define ACC ((ACC_TypeDef *)ACC_BASE) +#define ADC1 ((ADC_TypeDef *)ADC1_BASE) +#define ADC_COMMON ((ADC_Common_TypeDef *)ADC_Common_BASE) +#define CAN1 ((CAN_TypeDef *)CAN1_BASE) +#define CRC ((CRC_TypeDef *)CRC_BASE) +#define CRM ((CRM_TypeDef *)CRM_BASE) +#define DEBUG ((DEBUG_TypeDef *)DEBUG_BASE) +#define DMA1 ((DMA_TypeDef *)DMA1_BASE) +#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE) +#define DMA1MUX_Channel1 ((DMAMUX_Channel_TypeDef *) DMA1MUX_Channel1_BASE) +#define DMA1MUX_Channel2 ((DMAMUX_Channel_TypeDef *) DMA1MUX_Channel2_BASE) +#define DMA1MUX_Channel3 ((DMAMUX_Channel_TypeDef *) DMA1MUX_Channel3_BASE) +#define DMA1MUX_Channel4 ((DMAMUX_Channel_TypeDef *) DMA1MUX_Channel4_BASE) +#define DMA1MUX_Channel5 ((DMAMUX_Channel_TypeDef *) DMA1MUX_Channel5_BASE) +#define DMA1MUX_Channel6 ((DMAMUX_Channel_TypeDef *) DMA1MUX_Channel6_BASE) +#define DMA1MUX_Channel7 ((DMAMUX_Channel_TypeDef *) DMA1MUX_Channel7_BASE) +#define DMA1MUX_Generator1 ((DMAMUX_Generator_TypeDef *) DMA1MUX_Generator1_BASE) +#define DMA1MUX_Generator2 ((DMAMUX_Generator_TypeDef *) DMA1MUX_Generator2_BASE) +#define DMA1MUX_Generator3 ((DMAMUX_Generator_TypeDef *) DMA1MUX_Generator3_BASE) +#define DMA1MUX_Generator4 ((DMAMUX_Generator_TypeDef *) DMA1MUX_Generator4_BASE) +#define DMA1MUX_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMA1MUX_ChannelStatus_BASE) +#define DMA1MUX_GeneratorStatus ((DMAMUX_GeneratorStatus_TypeDef *) DMA1MUX_GeneratorStatus_BASE) +#define DMA2 ((DMA_TypeDef *)DMA2_BASE) +#define DMA2_Channel1 ((DMA_Channel_TypeDef *)DMA2_Channel1_BASE) +#define DMA2_Channel2 ((DMA_Channel_TypeDef *)DMA2_Channel2_BASE) +#define DMA2_Channel3 ((DMA_Channel_TypeDef *)DMA2_Channel3_BASE) +#define DMA2_Channel4 ((DMA_Channel_TypeDef *)DMA2_Channel4_BASE) +#define DMA2_Channel5 ((DMA_Channel_TypeDef *)DMA2_Channel5_BASE) +#define DMA2_Channel6 ((DMA_Channel_TypeDef *)DMA2_Channel6_BASE) +#define DMA2_Channel7 ((DMA_Channel_TypeDef *)DMA2_Channel7_BASE) +#define DMA2MUX_Channel1 ((DMAMUX_Channel_TypeDef *) DMA2MUX_Channel1_BASE) +#define DMA2MUX_Channel2 ((DMAMUX_Channel_TypeDef *) DMA2MUX_Channel2_BASE) +#define DMA2MUX_Channel3 ((DMAMUX_Channel_TypeDef *) DMA2MUX_Channel3_BASE) +#define DMA2MUX_Channel4 ((DMAMUX_Channel_TypeDef *) DMA2MUX_Channel4_BASE) +#define DMA2MUX_Channel5 ((DMAMUX_Channel_TypeDef *) DMA2MUX_Channel5_BASE) +#define DMA2MUX_Channel6 ((DMAMUX_Channel_TypeDef *) DMA2MUX_Channel6_BASE) +#define DMA2MUX_Channel7 ((DMAMUX_Channel_TypeDef *) DMA2MUX_Channel7_BASE) +#define DMA2MUX_Generator1 ((DMAMUX_Generator_TypeDef *) DMA2MUX_Generator1_BASE) +#define DMA2MUX_Generator2 ((DMAMUX_Generator_TypeDef *) DMA2MUX_Generator2_BASE) +#define DMA2MUX_Generator3 ((DMAMUX_Generator_TypeDef *) DMA2MUX_Generator3_BASE) +#define DMA2MUX_Generator4 ((DMAMUX_Generator_TypeDef *) DMA2MUX_Generator4_BASE) +#define DMA2MUX_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMA2MUX_ChannelStatus_BASE) +#define DMA2MUX_GeneratorStatus ((DMAMUX_GeneratorStatus_TypeDef *) DMA2MUX_GeneratorStatus_BASE) +#define ERTC ((ERTC_TypeDef *)ERTC_BASE) +#define EXINT ((EXINT_TypeDef *)EXINT_BASE) +#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE) +#define USD ((USD_TypeDef *)USD_BASE) +#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE) +#define GPIOF ((GPIO_TypeDef *)GPIOF_BASE) +#define I2C1 ((I2C_TypeDef *)I2C1_BASE) +#define I2C2 ((I2C_TypeDef *)I2C2_BASE) +#define I2C3 ((I2C_TypeDef *)I2C3_BASE) +#define PWC ((PWC_TypeDef *)PWC_BASE) +#define QSPI1 ((QSPI_TypeDef *)QSPI1_R_BASE) +#define SCFG ((SCFG_TypeDef *)SCFG_BASE) +#define SPI1 ((SPI_TypeDef *)SPI1_BASE) +#define SPI2 ((SPI_TypeDef *)SPI2_BASE) +#define SPI3 ((SPI_TypeDef *)SPI3_BASE) +#define I2SF5 ((SPI_TypeDef *)I2SF5_BASE) +#define TMR1 ((TMR_TypeDef *)TMR1_BASE) +#define TMR2 ((TMR_TypeDef *)TMR2_BASE) +#define TMR3 ((TMR_TypeDef *)TMR3_BASE) +#define TMR4 ((TMR_TypeDef *)TMR4_BASE) +#define TMR6 ((TMR_TypeDef *)TMR6_BASE) +#define TMR7 ((TMR_TypeDef *)TMR7_BASE) +#define TMR9 ((TMR_TypeDef *)TMR9_BASE) +#define TMR10 ((TMR_TypeDef *)TMR10_BASE) +#define TMR11 ((TMR_TypeDef *)TMR11_BASE) +#define TMR13 ((TMR_TypeDef *)TMR13_BASE) +#define TMR14 ((TMR_TypeDef *)TMR14_BASE) +#define USART1 ((USART_TypeDef *)USART1_BASE) +#define USART2 ((USART_TypeDef *)USART2_BASE) +#define USART3 ((USART_TypeDef *)USART3_BASE) +#define USART4 ((USART_TypeDef *)USART4_BASE) +#define USART5 ((USART_TypeDef *)USART5_BASE) +#define USART6 ((USART_TypeDef *)USART6_BASE) +#define UART7 ((USART_TypeDef *)UART7_BASE) +#define WDT ((WDT_TypeDef *)WDT_BASE) +#define WWDT ((WWDT_TypeDef *)WWDT_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral registers bits definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Power Control (PWC) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for PWC_CTRL register *******************/ +#define PWC_CTRL_VRSEL_Pos (0U) +#define PWC_CTRL_VRSEL_Msk (0x1U << PWC_CTRL_VRSEL_Pos) /*!< 0x00000001 */ +#define PWC_CTRL_VRSEL PWC_CTRL_VRSEL_Msk /*!< LDO state select in deep sleep mode */ +#define PWC_CTRL_LPSEL_Pos (1U) +#define PWC_CTRL_LPSEL_Msk (0x1U << PWC_CTRL_LPSEL_Pos) /*!< 0x00000002 */ +#define PWC_CTRL_LPSEL PWC_CTRL_LPSEL_Msk /*!< Low power mode select in deep sleep mode */ +#define PWC_CTRL_CLSWEF_Pos (2U) +#define PWC_CTRL_CLSWEF_Msk (0x1U << PWC_CTRL_CLSWEF_Pos) /*!< 0x00000004 */ +#define PWC_CTRL_CLSWEF PWC_CTRL_CLSWEF_Msk /*!< Clear SWEF flag */ +#define PWC_CTRL_CLSEF_Pos (3U) +#define PWC_CTRL_CLSEF_Msk (0x1U << PWC_CTRL_CLSEF_Pos) /*!< 0x00000008 */ +#define PWC_CTRL_CLSEF PWC_CTRL_CLSEF_Msk /*!< Clear SEF flag */ +#define PWC_CTRL_PVMEN_Pos (4U) +#define PWC_CTRL_PVMEN_Msk (0x1U << PWC_CTRL_PVMEN_Pos) /*!< 0x00000010 */ +#define PWC_CTRL_PVMEN PWC_CTRL_PVMEN_Msk /*!< Power voltage monitoring enable */ + +/*!< PVM level configuration */ +#define PWC_CTRL_PVMSEL_Pos (5U) +#define PWC_CTRL_PVMSEL_Msk (0x7U << PWC_CTRL_PVMSEL_Pos) /*!< 0x000000E0 */ +#define PWC_CTRL_PVMSEL PWC_CTRL_PVMSEL_Msk /*!< PVMSEL[2:0] bits (Power voltage monitoring boundary select) */ +#define PWC_CTRL_PVMSEL_0 (0x1U << PWC_CTRL_PVMSEL_Pos) /*!< 0x00000020 */ +#define PWC_CTRL_PVMSEL_1 (0x2U << PWC_CTRL_PVMSEL_Pos) /*!< 0x00000040 */ +#define PWC_CTRL_PVMSEL_2 (0x4U << PWC_CTRL_PVMSEL_Pos) /*!< 0x00000080 */ + +#define PWC_CTRL_PVMSEL_LEV1 0x00000020U /*!< PVM level 2.3V */ +#define PWC_CTRL_PVMSEL_LEV2 0x00000040U /*!< PVM level 2.4V */ +#define PWC_CTRL_PVMSEL_LEV3 0x00000060U /*!< PVM level 2.5V */ +#define PWC_CTRL_PVMSEL_LEV4 0x00000080U /*!< PVM level 2.6V */ +#define PWC_CTRL_PVMSEL_LEV5 0x000000A0U /*!< PVM level 2.7V */ +#define PWC_CTRL_PVMSEL_LEV6 0x000000C0U /*!< PVM level 2.8V */ +#define PWC_CTRL_PVMSEL_LEV7 0x000000E0U /*!< PVM level 2.9V */ + +/* Legacy defines */ +#define PWC_CTRL_PVMSEL_2V3 PWC_CTRL_PVMSEL_LEV1 +#define PWC_CTRL_PVMSEL_2V4 PWC_CTRL_PVMSEL_LEV2 +#define PWC_CTRL_PVMSEL_2V5 PWC_CTRL_PVMSEL_LEV3 +#define PWC_CTRL_PVMSEL_2V6 PWC_CTRL_PVMSEL_LEV4 +#define PWC_CTRL_PVMSEL_2V7 PWC_CTRL_PVMSEL_LEV5 +#define PWC_CTRL_PVMSEL_2V8 PWC_CTRL_PVMSEL_LEV6 +#define PWC_CTRL_PVMSEL_2V9 PWC_CTRL_PVMSEL_LEV7 + +#define PWC_CTRL_BPWEN_Pos (8U) +#define PWC_CTRL_BPWEN_Msk (0x1U << PWC_CTRL_BPWEN_Pos) /*!< 0x00000100 */ +#define PWC_CTRL_BPWEN PWC_CTRL_BPWEN_Msk /*!< Battery powered domain write enable */ + +/***************** Bit definition for PWC_CTRLSTS register ******************/ +#define PWC_CTRLSTS_SWEF_Pos (0U) +#define PWC_CTRLSTS_SWEF_Msk (0x1U << PWC_CTRLSTS_SWEF_Pos) /*!< 0x00000001 */ +#define PWC_CTRLSTS_SWEF PWC_CTRLSTS_SWEF_Msk /*!< Standby wake-up event flag */ +#define PWC_CTRLSTS_SEF_Pos (1U) +#define PWC_CTRLSTS_SEF_Msk (0x1U << PWC_CTRLSTS_SEF_Pos) /*!< 0x00000002 */ +#define PWC_CTRLSTS_SEF PWC_CTRLSTS_SEF_Msk /*!< Standby mode entry flag */ +#define PWC_CTRLSTS_PVMOF_Pos (2U) +#define PWC_CTRLSTS_PVMOF_Msk (0x1U << PWC_CTRLSTS_PVMOF_Pos) /*!< 0x00000004 */ +#define PWC_CTRLSTS_PVMOF PWC_CTRLSTS_PVMOF_Msk /*!< Power voltage monitoring output flag */ +#define PWC_CTRLSTS_SWPEN1_Pos (8U) +#define PWC_CTRLSTS_SWPEN1_Msk (0x1U << PWC_CTRLSTS_SWPEN1_Pos) /*!< 0x00000100 */ +#define PWC_CTRLSTS_SWPEN1 PWC_CTRLSTS_SWPEN1_Msk /*!< Standby wake-up pin 1 enable */ +#define PWC_CTRLSTS_SWPEN2_Pos (9U) +#define PWC_CTRLSTS_SWPEN2_Msk (0x1U << PWC_CTRLSTS_SWPEN2_Pos) /*!< 0x00000200 */ +#define PWC_CTRLSTS_SWPEN2 PWC_CTRLSTS_SWPEN2_Msk /*!< Standby wake-up pin 2 enable */ +#define PWC_CTRLSTS_SWPEN6_Pos (13U) +#define PWC_CTRLSTS_SWPEN6_Msk (0x1U << PWC_CTRLSTS_SWPEN6_Pos) /*!< 0x00002000 */ +#define PWC_CTRLSTS_SWPEN6 PWC_CTRLSTS_SWPEN6_Msk /*!< Standby wake-up pin 6 enable */ + +/****************** Bit definition for PWC_LDOOV register *******************/ +/*!< LDOOVSEL congiguration */ +#define PWC_LDOOV_LDOOVSEL_Pos (0U) +#define PWC_LDOOV_LDOOVSEL_Msk (0x3U << PWC_LDOOV_LDOOVSEL_Pos) /*!< 0x00000003 */ +#define PWC_LDOOV_LDOOVSEL PWC_LDOOV_LDOOVSEL_Msk /*!< LDOOVSEL[1:0] bits (Voltage regulator output voltage select) */ +#define PWC_LDOOV_LDOOVSEL_0 (0x1U << PWC_LDOOV_LDOOVSEL_Pos) /*!< 0x00000001 */ +#define PWC_LDOOV_LDOOVSEL_1 (0x2U << PWC_LDOOV_LDOOVSEL_Pos) /*!< 0x00000002 */ + +#define PWC_LDOOV_LDOOVSEL_LEV0 0x00000000U /*!< Voltage output level 1.0V */ +#define PWC_LDOOV_LDOOVSEL_LEV2 0x00000002U /*!< Voltage output level 1.2V */ +#define PWC_LDOOV_LDOOVSEL_LEV3 0x00000003U /*!< Voltage output level 1.3V */ + +/* Legacy defines */ +#define PWC_LDOOV_LDOOVSEL_1V0 PWC_LDOOV_LDOOVSEL_LEV0 +#define PWC_LDOOV_LDOOVSEL_1V2 PWC_LDOOV_LDOOVSEL_LEV2 +#define PWC_LDOOV_LDOOVSEL_1V3 PWC_LDOOV_LDOOVSEL_LEV3 + +#define PWC_LDOOV_VREXLPEN_Pos (4U) +#define PWC_LDOOV_VREXLPEN_Msk (0x1U << PWC_LDOOV_VREXLPEN_Pos) /*!< 0x00000010 */ +#define PWC_LDOOV_VREXLPEN PWC_LDOOV_VREXLPEN_Msk /*!< Voltage regulator extra low power mode enable */ + +/******************************************************************************/ +/* */ +/* Clock and reset manage (CRM) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for CRM_CTRL register *******************/ +#define CRM_CTRL_HICKEN_Pos (0U) +#define CRM_CTRL_HICKEN_Msk (0x1U << CRM_CTRL_HICKEN_Pos) /*!< 0x00000001 */ +#define CRM_CTRL_HICKEN CRM_CTRL_HICKEN_Msk /*!< High speed internal clock enable */ +#define CRM_CTRL_HICKSTBL_Pos (1U) +#define CRM_CTRL_HICKSTBL_Msk (0x1U << CRM_CTRL_HICKSTBL_Pos) /*!< 0x00000002 */ +#define CRM_CTRL_HICKSTBL CRM_CTRL_HICKSTBL_Msk /*!< High speed internal clock stable */ +#define CRM_CTRL_HICKTRIM_Pos (2U) +#define CRM_CTRL_HICKTRIM_Msk (0x3FU << CRM_CTRL_HICKTRIM_Pos) /*!< 0x000000FC */ +#define CRM_CTRL_HICKTRIM CRM_CTRL_HICKTRIM_Msk /*!< High speed internal clock trimming */ +#define CRM_CTRL_HICKCAL_Pos (8U) +#define CRM_CTRL_HICKCAL_Msk (0xFFU << CRM_CTRL_HICKCAL_Pos) /*!< 0x0000FF00 */ +#define CRM_CTRL_HICKCAL CRM_CTRL_HICKCAL_Msk /*!< High speed internal clock calibration */ +#define CRM_CTRL_HEXTEN_Pos (16U) +#define CRM_CTRL_HEXTEN_Msk (0x1U << CRM_CTRL_HEXTEN_Pos) /*!< 0x00010000 */ +#define CRM_CTRL_HEXTEN CRM_CTRL_HEXTEN_Msk /*!< High speed external crystal enable */ +#define CRM_CTRL_HEXTSTBL_Pos (17U) +#define CRM_CTRL_HEXTSTBL_Msk (0x1U << CRM_CTRL_HEXTSTBL_Pos) /*!< 0x00020000 */ +#define CRM_CTRL_HEXTSTBL CRM_CTRL_HEXTSTBL_Msk /*!< High speed external crystal stable */ +#define CRM_CTRL_HEXTBYPS_Pos (18U) +#define CRM_CTRL_HEXTBYPS_Msk (0x1U << CRM_CTRL_HEXTBYPS_Pos) /*!< 0x00040000 */ +#define CRM_CTRL_HEXTBYPS CRM_CTRL_HEXTBYPS_Msk /*!< High speed external crystal bypass */ +#define CRM_CTRL_CFDEN_Pos (19U) +#define CRM_CTRL_CFDEN_Msk (0x1U << CRM_CTRL_CFDEN_Pos) /*!< 0x00080000 */ +#define CRM_CTRL_CFDEN CRM_CTRL_CFDEN_Msk /*!< Clock failure detector enable */ +#define CRM_CTRL_PLLEN_Pos (24U) +#define CRM_CTRL_PLLEN_Msk (0x1U << CRM_CTRL_PLLEN_Pos) /*!< 0x01000000 */ +#define CRM_CTRL_PLLEN CRM_CTRL_PLLEN_Msk /*!< PLL enable */ +#define CRM_CTRL_PLLSTBL_Pos (25U) +#define CRM_CTRL_PLLSTBL_Msk (0x1U << CRM_CTRL_PLLSTBL_Pos) /*!< 0x02000000 */ +#define CRM_CTRL_PLLSTBL CRM_CTRL_PLLSTBL_Msk /*!< PLL clock stable */ +#define CRM_CTRL_PLLUSTBL_Pos (26U) +#define CRM_CTRL_PLLUSTBL_Msk (0x1U << CRM_CTRL_PLLUSTBL_Pos) /*!< 0x04000000 */ +#define CRM_CTRL_PLLUSTBL CRM_CTRL_PLLUSTBL_Msk /*!< PLLU clock stable */ + +/****************** Bit definition for CRM_PLLCFG register ******************/ +/*!< PLL_MS congiguration */ +#define CRM_PLLCFG_PLL_MS_Pos (0U) +#define CRM_PLLCFG_PLL_MS_Msk (0xFU << CRM_PLLCFG_PLL_MS_Pos) /*!< 0x0000000F */ +#define CRM_PLLCFG_PLL_MS CRM_PLLCFG_PLL_MS_Msk /*!< PLL_MS[3:0] bits (PLL pre-division) */ +#define CRM_PLLCFG_PLL_MS_0 (0x1U << CRM_PLLCFG_PLL_MS_Pos) /*!< 0x00000001 */ +#define CRM_PLLCFG_PLL_MS_1 (0x2U << CRM_PLLCFG_PLL_MS_Pos) /*!< 0x00000002 */ +#define CRM_PLLCFG_PLL_MS_2 (0x4U << CRM_PLLCFG_PLL_MS_Pos) /*!< 0x00000004 */ +#define CRM_PLLCFG_PLL_MS_3 (0x8U << CRM_PLLCFG_PLL_MS_Pos) /*!< 0x00000008 */ + +/*!< PLL_NS congiguration */ +#define CRM_PLLCFG_PLL_NS_Pos (6U) +#define CRM_PLLCFG_PLL_NS_Msk (0x1FFU << CRM_PLLCFG_PLL_NS_Pos) /*!< 0x00007FC0 */ +#define CRM_PLLCFG_PLL_NS CRM_PLLCFG_PLL_NS_Msk /*!< PLL_NS[8:0] bits (PLL multiplication factor) */ +#define CRM_PLLCFG_PLL_NS_0 (0x001U << CRM_PLLCFG_PLL_NS_Pos) /*!< 0x00000040 */ +#define CRM_PLLCFG_PLL_NS_1 (0x002U << CRM_PLLCFG_PLL_NS_Pos) /*!< 0x00000080 */ +#define CRM_PLLCFG_PLL_NS_2 (0x004U << CRM_PLLCFG_PLL_NS_Pos) /*!< 0x00000100 */ +#define CRM_PLLCFG_PLL_NS_3 (0x008U << CRM_PLLCFG_PLL_NS_Pos) /*!< 0x00000200 */ +#define CRM_PLLCFG_PLL_NS_4 (0x010U << CRM_PLLCFG_PLL_NS_Pos) /*!< 0x00000400 */ +#define CRM_PLLCFG_PLL_NS_5 (0x020U << CRM_PLLCFG_PLL_NS_Pos) /*!< 0x00000800 */ +#define CRM_PLLCFG_PLL_NS_6 (0x040U << CRM_PLLCFG_PLL_NS_Pos) /*!< 0x00001000 */ +#define CRM_PLLCFG_PLL_NS_7 (0x080U << CRM_PLLCFG_PLL_NS_Pos) /*!< 0x00002000 */ +#define CRM_PLLCFG_PLL_NS_8 (0x100U << CRM_PLLCFG_PLL_NS_Pos) /*!< 0x00004000 */ + +/*!< PLL_FP congiguration */ +#define CRM_PLLCFG_PLL_FP_Pos (16U) +#define CRM_PLLCFG_PLL_FP_Msk (0xFU << CRM_PLLCFG_PLL_FP_Pos) /*!< 0x000F0000 */ +#define CRM_PLLCFG_PLL_FP CRM_PLLCFG_PLL_FP_Msk /*!< PLL_FP[3:0] bits (PLLP post-division) */ +#define CRM_PLLCFG_PLL_FP_0 (0x1U << CRM_PLLCFG_PLL_FP_Pos) /*!< 0x00010000 */ +#define CRM_PLLCFG_PLL_FP_1 (0x2U << CRM_PLLCFG_PLL_FP_Pos) /*!< 0x00020000 */ +#define CRM_PLLCFG_PLL_FP_2 (0x4U << CRM_PLLCFG_PLL_FP_Pos) /*!< 0x00040000 */ +#define CRM_PLLCFG_PLL_FP_3 (0x8U << CRM_PLLCFG_PLL_FP_Pos) /*!< 0x00080000 */ + +/*!< PLL_FU congiguration */ +#define CRM_PLLCFG_PLL_FU_Pos (20U) +#define CRM_PLLCFG_PLL_FU_Msk (0x7U << CRM_PLLCFG_PLL_FU_Pos) /*!< 0x00700000 */ +#define CRM_PLLCFG_PLL_FU CRM_PLLCFG_PLL_FU_Msk /*!< PLL_FU[2:0] bits (PLLU post-division) */ +#define CRM_PLLCFG_PLL_FU_0 (0x1U << CRM_PLLCFG_PLL_FU_Pos) /*!< 0x00100000 */ +#define CRM_PLLCFG_PLL_FU_1 (0x2U << CRM_PLLCFG_PLL_FU_Pos) /*!< 0x00200000 */ +#define CRM_PLLCFG_PLL_FU_2 (0x4U << CRM_PLLCFG_PLL_FU_Pos) /*!< 0x00400000 */ + +#define CRM_PLLCFG_PLLU_EN_Pos (29U) +#define CRM_PLLCFG_PLLU_EN_Msk (0x1U << CRM_PLLCFG_PLLU_EN_Pos) /*!< 0x20000000 */ +#define CRM_PLLCFG_PLLU_EN CRM_PLLCFG_PLLU_EN_Msk /*!< PLLU enable */ +#define CRM_PLLCFG_PLLRCS_Pos (30U) +#define CRM_PLLCFG_PLLRCS_Msk (0x1U << CRM_PLLCFG_PLLRCS_Pos) /*!< 0x40000000 */ +#define CRM_PLLCFG_PLLRCS CRM_PLLCFG_PLLRCS_Msk /*!< PLL reference clock select */ +#define CRM_PLLCFG_PLLRST_Pos (31U) +#define CRM_PLLCFG_PLLRST_Msk (0x1U << CRM_PLLCFG_PLLRST_Pos) /*!< 0x80000000 */ +#define CRM_PLLCFG_PLLRST CRM_PLLCFG_PLLRST_Msk /*!< PLLRST */ + +/******************* Bit definition for CRM_CFG register ********************/ +/*!< SCLKSEL configuration */ +#define CRM_CFG_SCLKSEL_Pos (0U) +#define CRM_CFG_SCLKSEL_Msk (0x3U << CRM_CFG_SCLKSEL_Pos) /*!< 0x00000003 */ +#define CRM_CFG_SCLKSEL CRM_CFG_SCLKSEL_Msk /*!< SCLKSEL[1:0] bits (System clock select) */ +#define CRM_CFG_SCLKSEL_0 (0x1U << CRM_CFG_SCLKSEL_Pos) /*!< 0x00000001 */ +#define CRM_CFG_SCLKSEL_1 (0x2U << CRM_CFG_SCLKSEL_Pos) /*!< 0x00000002 */ + +#define CRM_CFG_SCLKSEL_HICK 0x00000000U /*!< HICK */ +#define CRM_CFG_SCLKSEL_HEXT 0x00000001U /*!< HEXT */ +#define CRM_CFG_SCLKSEL_PLL 0x00000002U /*!< PLL */ + +/*!< SCLKSTS configuration */ +#define CRM_CFG_SCLKSTS_Pos (2U) +#define CRM_CFG_SCLKSTS_Msk (0x3U << CRM_CFG_SCLKSTS_Pos) /*!< 0x0000000C */ +#define CRM_CFG_SCLKSTS CRM_CFG_SCLKSTS_Msk /*!< SCLKSTS[1:0] bits (System clock select status) */ +#define CRM_CFG_SCLKSTS_0 (0x1U << CRM_CFG_SCLKSTS_Pos) /*!< 0x00000004 */ +#define CRM_CFG_SCLKSTS_1 (0x2U << CRM_CFG_SCLKSTS_Pos) /*!< 0x00000008 */ + +#define CRM_CFG_SCLKSTS_HICK 0x00000000U /*!< HICK */ +#define CRM_CFG_SCLKSTS_HEXT 0x00000004U /*!< HEXT */ +#define CRM_CFG_SCLKSTS_PLL 0x00000008U /*!< PLL */ + +/*!< AHBDIV configuration */ +#define CRM_CFG_AHBDIV_Pos (4U) +#define CRM_CFG_AHBDIV_Msk (0xFU << CRM_CFG_AHBDIV_Pos) /*!< 0x000000F0 */ +#define CRM_CFG_AHBDIV CRM_CFG_AHBDIV_Msk /*!< AHBDIV[3:0] bits (AHB division) */ +#define CRM_CFG_AHBDIV_0 (0x1U << CRM_CFG_AHBDIV_Pos) /*!< 0x00000010 */ +#define CRM_CFG_AHBDIV_1 (0x2U << CRM_CFG_AHBDIV_Pos) /*!< 0x00000020 */ +#define CRM_CFG_AHBDIV_2 (0x4U << CRM_CFG_AHBDIV_Pos) /*!< 0x00000040 */ +#define CRM_CFG_AHBDIV_3 (0x8U << CRM_CFG_AHBDIV_Pos) /*!< 0x00000080 */ + +#define CRM_CFG_AHBDIV_DIV1 0x00000000U /*!< SCLK is not divided */ +#define CRM_CFG_AHBDIV_DIV2 0x00000080U /*!< SCLK is divided by 2 */ +#define CRM_CFG_AHBDIV_DIV4 0x00000090U /*!< SCLK is divided by 4 */ +#define CRM_CFG_AHBDIV_DIV8 0x000000A0U /*!< SCLK is divided by 8 */ +#define CRM_CFG_AHBDIV_DIV16 0x000000B0U /*!< SCLK is divided by 16 */ +#define CRM_CFG_AHBDIV_DIV64 0x000000C0U /*!< SCLK is divided by 64 */ +#define CRM_CFG_AHBDIV_DIV128 0x000000D0U /*!< SCLK is divided by 128 */ +#define CRM_CFG_AHBDIV_DIV256 0x000000E0U /*!< SCLK is divided by 256 */ +#define CRM_CFG_AHBDIV_DIV512 0x000000F0U /*!< SCLK is divided by 512 */ + +/*!< APB1DIV configuration */ +#define CRM_CFG_APB1DIV_Pos (10U) +#define CRM_CFG_APB1DIV_Msk (0x7U << CRM_CFG_APB1DIV_Pos) /*!< 0x00001C00 */ +#define CRM_CFG_APB1DIV CRM_CFG_APB1DIV_Msk /*!< APB1DIV[2:0] bits (APB1 division) */ +#define CRM_CFG_APB1DIV_0 (0x1U << CRM_CFG_APB1DIV_Pos) /*!< 0x00000400 */ +#define CRM_CFG_APB1DIV_1 (0x2U << CRM_CFG_APB1DIV_Pos) /*!< 0x00000800 */ +#define CRM_CFG_APB1DIV_2 (0x4U << CRM_CFG_APB1DIV_Pos) /*!< 0x00001000 */ + +#define CRM_CFG_APB1DIV_DIV1 0x00000000U /*!< HCLK is not divided */ +#define CRM_CFG_APB1DIV_DIV2 0x00001000U /*!< HCLK is divided by 2 */ +#define CRM_CFG_APB1DIV_DIV4 0x00001400U /*!< HCLK is divided by 4 */ +#define CRM_CFG_APB1DIV_DIV8 0x00001800U /*!< HCLK is divided by 8 */ +#define CRM_CFG_APB1DIV_DIV16 0x00001C00U /*!< HCLK is divided by 16 */ + +/*!< APB2DIV configuration */ +#define CRM_CFG_APB2DIV_Pos (13U) +#define CRM_CFG_APB2DIV_Msk (0x7U << CRM_CFG_APB2DIV_Pos) /*!< 0x0000E000 */ +#define CRM_CFG_APB2DIV CRM_CFG_APB2DIV_Msk /*!< APB2DIV[2:0] bits (APB2 division) */ +#define CRM_CFG_APB2DIV_0 (0x1U << CRM_CFG_APB2DIV_Pos) /*!< 0x00002000 */ +#define CRM_CFG_APB2DIV_1 (0x2U << CRM_CFG_APB2DIV_Pos) /*!< 0x00004000 */ +#define CRM_CFG_APB2DIV_2 (0x4U << CRM_CFG_APB2DIV_Pos) /*!< 0x00008000 */ + +#define CRM_CFG_APB2DIV_DIV1 0x00000000U /*!< HCLK is not divided */ +#define CRM_CFG_APB2DIV_DIV2 0x00008000U /*!< HCLK is divided by 2 */ +#define CRM_CFG_APB2DIV_DIV4 0x0000A000U /*!< HCLK is divided by 4 */ +#define CRM_CFG_APB2DIV_DIV8 0x0000C000U /*!< HCLK is divided by 8 */ +#define CRM_CFG_APB2DIV_DIV16 0x0000E000U /*!< HCLK is divided by 16 */ + +/*!< ERTCDIV configuration */ +#define CRM_CFG_ERTCDIV_Pos (16U) +#define CRM_CFG_ERTCDIV_Msk (0x1FU << CRM_CFG_ERTCDIV_Pos) /*!< 0x001F0000 */ +#define CRM_CFG_ERTCDIV CRM_CFG_ERTCDIV_Msk /*!< ERTCDIV[4:0] bits (HEXT division for ERTC clock) */ +#define CRM_CFG_ERTCDIV_0 (0x01U << CRM_CFG_ERTCDIV_Pos) /*!< 0x00010000 */ +#define CRM_CFG_ERTCDIV_1 (0x02U << CRM_CFG_ERTCDIV_Pos) /*!< 0x00020000 */ +#define CRM_CFG_ERTCDIV_2 (0x04U << CRM_CFG_ERTCDIV_Pos) /*!< 0x00040000 */ +#define CRM_CFG_ERTCDIV_3 (0x08U << CRM_CFG_ERTCDIV_Pos) /*!< 0x00080000 */ +#define CRM_CFG_ERTCDIV_4 (0x10U << CRM_CFG_ERTCDIV_Pos) /*!< 0x00100000 */ + +#define CRM_CFG_ERTCDIV_DIV2 0x00020000U /*!< HEXT/2 */ +#define CRM_CFG_ERTCDIV_DIV3 0x00030000U /*!< HEXT/3 */ +#define CRM_CFG_ERTCDIV_DIV4 0x00040000U /*!< HEXT/4 */ +#define CRM_CFG_ERTCDIV_DIV5 0x00050000U /*!< HEXT/5 */ +#define CRM_CFG_ERTCDIV_DIV6 0x00060000U /*!< HEXT/6 */ +#define CRM_CFG_ERTCDIV_DIV7 0x00070000U /*!< HEXT/7 */ +#define CRM_CFG_ERTCDIV_DIV8 0x00080000U /*!< HEXT/8 */ +#define CRM_CFG_ERTCDIV_DIV9 0x00090000U /*!< HEXT/9 */ +#define CRM_CFG_ERTCDIV_DIV10 0x000A0000U /*!< HEXT/10 */ +#define CRM_CFG_ERTCDIV_DIV11 0x000B0000U /*!< HEXT/11 */ +#define CRM_CFG_ERTCDIV_DIV12 0x000C0000U /*!< HEXT/12 */ +#define CRM_CFG_ERTCDIV_DIV13 0x000D0000U /*!< HEXT/13 */ +#define CRM_CFG_ERTCDIV_DIV14 0x000E0000U /*!< HEXT/14 */ +#define CRM_CFG_ERTCDIV_DIV15 0x000F0000U /*!< HEXT/15 */ +#define CRM_CFG_ERTCDIV_DIV16 0x00100000U /*!< HEXT/16 */ +#define CRM_CFG_ERTCDIV_DIV17 0x00110000U /*!< HEXT/17 */ +#define CRM_CFG_ERTCDIV_DIV18 0x00120000U /*!< HEXT/18 */ +#define CRM_CFG_ERTCDIV_DIV19 0x00130000U /*!< HEXT/19 */ +#define CRM_CFG_ERTCDIV_DIV20 0x00140000U /*!< HEXT/20 */ +#define CRM_CFG_ERTCDIV_DIV21 0x00150000U /*!< HEXT/21 */ +#define CRM_CFG_ERTCDIV_DIV22 0x00160000U /*!< HEXT/22 */ +#define CRM_CFG_ERTCDIV_DIV23 0x00170000U /*!< HEXT/23 */ +#define CRM_CFG_ERTCDIV_DIV24 0x00180000U /*!< HEXT/24 */ +#define CRM_CFG_ERTCDIV_DIV25 0x00190000U /*!< HEXT/25 */ +#define CRM_CFG_ERTCDIV_DIV26 0x001A0000U /*!< HEXT/26 */ +#define CRM_CFG_ERTCDIV_DIV27 0x001B0000U /*!< HEXT/27 */ +#define CRM_CFG_ERTCDIV_DIV28 0x001C0000U /*!< HEXT/28 */ +#define CRM_CFG_ERTCDIV_DIV29 0x001D0000U /*!< HEXT/29 */ +#define CRM_CFG_ERTCDIV_DIV30 0x001E0000U /*!< HEXT/30 */ +#define CRM_CFG_ERTCDIV_DIV31 0x001F0000U /*!< HEXT/31 */ + +/*!< I2SF5CLKSEL configuration */ +#define CRM_CFG_I2SF5CLKSEL_Pos (22U) +#define CRM_CFG_I2SF5CLKSEL_Msk (0x3U << CRM_CFG_I2SF5CLKSEL_Pos) /*!< 0x00C00000 */ +#define CRM_CFG_I2SF5CLKSEL CRM_CFG_I2SF5CLKSEL_Msk /*!< I2SF5CLKSEL[1:0] bits (I2SF5 clock source selection) */ +#define CRM_CFG_I2SF5CLKSEL_0 (0x1U << CRM_CFG_I2SF5CLKSEL_Pos) /*!< 0x00400000 */ +#define CRM_CFG_I2SF5CLKSEL_1 (0x2U << CRM_CFG_I2SF5CLKSEL_Pos) /*!< 0x00800000 */ + +#define CRM_CFG_I2SF5CLKSEL_SCLK 0x00000000U /*!< System clock */ +#define CRM_CFG_I2SF5CLKSEL_PLL 0x00400000U /*!< PLL */ +#define CRM_CFG_I2SF5CLKSEL_HICK 0x00800000U /*!< HICK */ +#define CRM_CFG_I2SF5CLKSEL_EXTERNAL 0x00C00000U /*!< External input clock */ + +/*!< CLKOUTDIV1 configuration */ +#define CRM_CFG_CLKOUTDIV1_Pos (27U) +#define CRM_CFG_CLKOUTDIV1_Msk (0x7U << CRM_CFG_CLKOUTDIV1_Pos) /*!< 0x38000000 */ +#define CRM_CFG_CLKOUTDIV1 CRM_CFG_CLKOUTDIV1_Msk /*!< CLKOUTDIV1[2:0] bits (Clock output division 1) */ +#define CRM_CFG_CLKOUTDIV1_0 (0x1U << CRM_CFG_CLKOUTDIV1_Pos) /*!< 0x08000000 */ +#define CRM_CFG_CLKOUTDIV1_1 (0x2U << CRM_CFG_CLKOUTDIV1_Pos) /*!< 0x10000000 */ +#define CRM_CFG_CLKOUTDIV1_2 (0x4U << CRM_CFG_CLKOUTDIV1_Pos) /*!< 0x20000000 */ + +#define CRM_CFG_CLKOUTDIV1_DIV1 0x00000000U /*!< No clock output */ +#define CRM_CFG_CLKOUTDIV1_DIV2 0x20000000U /*!< Clock output divided by 2 */ +#define CRM_CFG_CLKOUTDIV1_DIV3 0x28000000U /*!< Clock output divided by 3 */ +#define CRM_CFG_CLKOUTDIV1_DIV4 0x30000000U /*!< Clock output divided by 4 */ +#define CRM_CFG_CLKOUTDIV1_DIV5 0x38000000U /*!< Clock output divided by 5 */ + +/*!< CLKOUT_SEL1 configuration */ +#define CRM_CFG_CLKOUT_SEL1_Pos (30U) +#define CRM_CFG_CLKOUT_SEL1_Msk (0x3U << CRM_CFG_CLKOUT_SEL1_Pos) /*!< 0xC0000000 */ +#define CRM_CFG_CLKOUT_SEL1 CRM_CFG_CLKOUT_SEL1_Msk /*!< CLKOUT_SEL1[1:0] bits (Clock output selection 1) */ +#define CRM_CFG_CLKOUT_SEL1_0 (0x1U << CRM_CFG_CLKOUT_SEL1_Pos) /*!< 0x40000000 */ +#define CRM_CFG_CLKOUT_SEL1_1 (0x2U << CRM_CFG_CLKOUT_SEL1_Pos) /*!< 0x80000000 */ + +#define CRM_CFG_CLKOUT_SEL1_SCLK 0x00000000U /*!< System clock */ +#define CRM_CFG_CLKOUT_SEL1_CLKOUT_SEL2 0x40000000U /*!< CLKOUT_SEL2 bit in the CRM_MISC1 register */ +#define CRM_CFG_CLKOUT_SEL1_HEXT 0x80000000U /*!< HEXT */ +#define CRM_CFG_CLKOUT_SEL1_PLL 0xC0000000U /*!< PLL */ + +/* Reference defines */ +#define CRM_CFG_CLKSEL1 CRM_CFG_CLKOUT_SEL1 +#define CRM_CFG_CLKSEL1_0 CRM_CFG_CLKOUT_SEL1_0 +#define CRM_CFG_CLKSEL1_1 CRM_CFG_CLKOUT_SEL1_1 +#define CRM_CFG_CLKSEL1_SCLK CRM_CFG_CLKOUT_SEL1_SCLK +#define CRM_CFG_CLKSEL1_CLKOUT_SEL2 CRM_CFG_CLKOUT_SEL1_CLKOUT_SEL2 +#define CRM_CFG_CLKSEL1_HEXT CRM_CFG_CLKOUT_SEL1_HEXT +#define CRM_CFG_CLKSEL1_PLL CRM_CFG_CLKOUT_SEL1_PLL + +/*!<*************** Bit definition for CRM_CLKINT register ******************/ +#define CRM_CLKINT_LICKSTBLF_Pos (0U) +#define CRM_CLKINT_LICKSTBLF_Msk (0x1U << CRM_CLKINT_LICKSTBLF_Pos) /*!< 0x00000001 */ +#define CRM_CLKINT_LICKSTBLF CRM_CLKINT_LICKSTBLF_Msk /*!< LICK stable interrupt flag */ +#define CRM_CLKINT_LEXTSTBLF_Pos (1U) +#define CRM_CLKINT_LEXTSTBLF_Msk (0x1U << CRM_CLKINT_LEXTSTBLF_Pos) /*!< 0x00000002 */ +#define CRM_CLKINT_LEXTSTBLF CRM_CLKINT_LEXTSTBLF_Msk /*!< LEXT stable flag */ +#define CRM_CLKINT_HICKSTBLF_Pos (2U) +#define CRM_CLKINT_HICKSTBLF_Msk (0x1U << CRM_CLKINT_HICKSTBLF_Pos) /*!< 0x00000004 */ +#define CRM_CLKINT_HICKSTBLF CRM_CLKINT_HICKSTBLF_Msk /*!< HICK stable flag */ +#define CRM_CLKINT_HEXTSTBLF_Pos (3U) +#define CRM_CLKINT_HEXTSTBLF_Msk (0x1U << CRM_CLKINT_HEXTSTBLF_Pos) /*!< 0x00000008 */ +#define CRM_CLKINT_HEXTSTBLF CRM_CLKINT_HEXTSTBLF_Msk /*!< HEXT stable flag */ +#define CRM_CLKINT_PLLSTBLF_Pos (4U) +#define CRM_CLKINT_PLLSTBLF_Msk (0x1U << CRM_CLKINT_PLLSTBLF_Pos) /*!< 0x00000010 */ +#define CRM_CLKINT_PLLSTBLF CRM_CLKINT_PLLSTBLF_Msk /*!< PLL stable flag */ +#define CRM_CLKINT_CFDF_Pos (7U) +#define CRM_CLKINT_CFDF_Msk (0x1U << CRM_CLKINT_CFDF_Pos) /*!< 0x00000080 */ +#define CRM_CLKINT_CFDF CRM_CLKINT_CFDF_Msk /*!< Clock failure detection flag */ +#define CRM_CLKINT_LICKSTBLIEN_Pos (8U) +#define CRM_CLKINT_LICKSTBLIEN_Msk (0x1U << CRM_CLKINT_LICKSTBLIEN_Pos) /*!< 0x00000100 */ +#define CRM_CLKINT_LICKSTBLIEN CRM_CLKINT_LICKSTBLIEN_Msk /*!< LICK stable interrupt enable */ +#define CRM_CLKINT_LEXTSTBLIEN_Pos (9U) +#define CRM_CLKINT_LEXTSTBLIEN_Msk (0x1U << CRM_CLKINT_LEXTSTBLIEN_Pos) /*!< 0x00000200 */ +#define CRM_CLKINT_LEXTSTBLIEN CRM_CLKINT_LEXTSTBLIEN_Msk /*!< LEXT stable interrupt enable */ +#define CRM_CLKINT_HICKSTBLIEN_Pos (10U) +#define CRM_CLKINT_HICKSTBLIEN_Msk (0x1U << CRM_CLKINT_HICKSTBLIEN_Pos) /*!< 0x00000400 */ +#define CRM_CLKINT_HICKSTBLIEN CRM_CLKINT_HICKSTBLIEN_Msk /*!< HICK stable interrupt enable */ +#define CRM_CLKINT_HEXTSTBLIEN_Pos (11U) +#define CRM_CLKINT_HEXTSTBLIEN_Msk (0x1U << CRM_CLKINT_HEXTSTBLIEN_Pos) /*!< 0x00000800 */ +#define CRM_CLKINT_HEXTSTBLIEN CRM_CLKINT_HEXTSTBLIEN_Msk /*!< HEXT stable interrupt enable */ +#define CRM_CLKINT_PLLSTBLIEN_Pos (12U) +#define CRM_CLKINT_PLLSTBLIEN_Msk (0x1U << CRM_CLKINT_PLLSTBLIEN_Pos) /*!< 0x00001000 */ +#define CRM_CLKINT_PLLSTBLIEN CRM_CLKINT_PLLSTBLIEN_Msk /*!< PLL stable interrupt enable */ +#define CRM_CLKINT_LICKSTBLFC_Pos (16U) +#define CRM_CLKINT_LICKSTBLFC_Msk (0x1U << CRM_CLKINT_LICKSTBLFC_Pos) /*!< 0x00010000 */ +#define CRM_CLKINT_LICKSTBLFC CRM_CLKINT_LICKSTBLFC_Msk /*!< LICK stable flag clear */ +#define CRM_CLKINT_LEXTSTBLFC_Pos (17U) +#define CRM_CLKINT_LEXTSTBLFC_Msk (0x1U << CRM_CLKINT_LEXTSTBLFC_Pos) /*!< 0x00020000 */ +#define CRM_CLKINT_LEXTSTBLFC CRM_CLKINT_LEXTSTBLFC_Msk /*!< LEXT stable flag clear */ +#define CRM_CLKINT_HICKSTBLFC_Pos (18U) +#define CRM_CLKINT_HICKSTBLFC_Msk (0x1U << CRM_CLKINT_HICKSTBLFC_Pos) /*!< 0x00040000 */ +#define CRM_CLKINT_HICKSTBLFC CRM_CLKINT_HICKSTBLFC_Msk /*!< HICK stable flag clear */ +#define CRM_CLKINT_HEXTSTBLFC_Pos (19U) +#define CRM_CLKINT_HEXTSTBLFC_Msk (0x1U << CRM_CLKINT_HEXTSTBLFC_Pos) /*!< 0x00080000 */ +#define CRM_CLKINT_HEXTSTBLFC CRM_CLKINT_HEXTSTBLFC_Msk /*!< HEXT stable flag clear */ +#define CRM_CLKINT_PLLSTBLFC_Pos (20U) +#define CRM_CLKINT_PLLSTBLFC_Msk (0x1U << CRM_CLKINT_PLLSTBLFC_Pos) /*!< 0x00100000 */ +#define CRM_CLKINT_PLLSTBLFC CRM_CLKINT_PLLSTBLFC_Msk /*!< PLL stable flag clear */ +#define CRM_CLKINT_CFDFC_Pos (23U) +#define CRM_CLKINT_CFDFC_Msk (0x1U << CRM_CLKINT_CFDFC_Pos) /*!< 0x00800000 */ +#define CRM_CLKINT_CFDFC CRM_CLKINT_CFDFC_Msk /*!< Clock failure detection flag clear */ + +/***************** Bit definition for CRM_AHBRST1 register ******************/ +#define CRM_AHBRST1_GPIOARST_Pos (0U) +#define CRM_AHBRST1_GPIOARST_Msk (0x1U << CRM_AHBRST1_GPIOARST_Pos) /*!< 0x00000001 */ +#define CRM_AHBRST1_GPIOARST CRM_AHBRST1_GPIOARST_Msk /*!< IO port A reset */ +#define CRM_AHBRST1_GPIOBRST_Pos (1U) +#define CRM_AHBRST1_GPIOBRST_Msk (0x1U << CRM_AHBRST1_GPIOBRST_Pos) /*!< 0x00000002 */ +#define CRM_AHBRST1_GPIOBRST CRM_AHBRST1_GPIOBRST_Msk /*!< IO port B reset */ +#define CRM_AHBRST1_GPIOCRST_Pos (2U) +#define CRM_AHBRST1_GPIOCRST_Msk (0x1U << CRM_AHBRST1_GPIOCRST_Pos) /*!< 0x00000004 */ +#define CRM_AHBRST1_GPIOCRST CRM_AHBRST1_GPIOCRST_Msk /*!< IO port C reset */ +#define CRM_AHBRST1_GPIODRST_Pos (3U) +#define CRM_AHBRST1_GPIODRST_Msk (0x1U << CRM_AHBRST1_GPIODRST_Pos) /*!< 0x00000008 */ +#define CRM_AHBRST1_GPIODRST CRM_AHBRST1_GPIODRST_Msk /*!< IO port D reset */ +#define CRM_AHBRST1_GPIOFRST_Pos (5U) +#define CRM_AHBRST1_GPIOFRST_Msk (0x1U << CRM_AHBRST1_GPIOFRST_Pos) /*!< 0x00000020 */ +#define CRM_AHBRST1_GPIOFRST CRM_AHBRST1_GPIOFRST_Msk /*!< IO port F reset */ +#define CRM_AHBRST1_CRCRST_Pos (12U) +#define CRM_AHBRST1_CRCRST_Msk (0x1U << CRM_AHBRST1_CRCRST_Pos) /*!< 0x00001000 */ +#define CRM_AHBRST1_CRCRST CRM_AHBRST1_CRCRST_Msk /*!< CRC reset */ +#define CRM_AHBRST1_DMA1RST_Pos (22U) +#define CRM_AHBRST1_DMA1RST_Msk (0x1U << CRM_AHBRST1_DMA1RST_Pos) /*!< 0x00400000 */ +#define CRM_AHBRST1_DMA1RST CRM_AHBRST1_DMA1RST_Msk /*!< DMA1 reset */ +#define CRM_AHBRST1_DMA2RST_Pos (24U) +#define CRM_AHBRST1_DMA2RST_Msk (0x1U << CRM_AHBRST1_DMA2RST_Pos) /*!< 0x01000000 */ +#define CRM_AHBRST1_DMA2RST CRM_AHBRST1_DMA2RST_Msk /*!< DMA2 reset */ +#define CRM_AHBRST1_OTGHSRST_Pos (29U) +#define CRM_AHBRST1_OTGHSRST_Msk (0x1U << CRM_AHBRST1_OTGHSRST_Pos) /*!< 0x20000000 */ +#define CRM_AHBRST1_OTGHSRST CRM_AHBRST1_OTGHSRST_Msk /*!< OTGHS reset (F405 only) */ + +/***************** Bit definition for CRM_AHBRST2 register ******************/ +#define CRM_AHBRST2_OTGFSRST_Pos (7U) +#define CRM_AHBRST2_OTGFSRST_Msk (0x1U << CRM_AHBRST2_OTGFSRST_Pos) /*!< 0x00000080 */ +#define CRM_AHBRST2_OTGFSRST CRM_AHBRST2_OTGFSRST_Msk /*!< OTGFS reset */ + +/***************** Bit definition for CRM_AHBRST3 register ******************/ +#define CRM_AHBRST3_QSPI1RST_Pos (1U) +#define CRM_AHBRST3_QSPI1RST_Msk (0x1U << CRM_AHBRST3_QSPI1RST_Pos) /*!< 0x00000002 */ +#define CRM_AHBRST3_QSPI1RST CRM_AHBRST3_QSPI1RST_Msk /*!< QSPI1 reset */ + +/***************** Bit definition for CRM_APB1RST register ******************/ +#define CRM_APB1RST_TMR2RST_Pos (0U) +#define CRM_APB1RST_TMR2RST_Msk (0x1U << CRM_APB1RST_TMR2RST_Pos) /*!< 0x00000001 */ +#define CRM_APB1RST_TMR2RST CRM_APB1RST_TMR2RST_Msk /*!< TMR2 reset */ +#define CRM_APB1RST_TMR3RST_Pos (1U) +#define CRM_APB1RST_TMR3RST_Msk (0x1U << CRM_APB1RST_TMR3RST_Pos) /*!< 0x00000002 */ +#define CRM_APB1RST_TMR3RST CRM_APB1RST_TMR3RST_Msk /*!< TMR3 reset */ +#define CRM_APB1RST_TMR4RST_Pos (2U) +#define CRM_APB1RST_TMR4RST_Msk (0x1U << CRM_APB1RST_TMR4RST_Pos) /*!< 0x00000004 */ +#define CRM_APB1RST_TMR4RST CRM_APB1RST_TMR4RST_Msk /*!< TMR4 reset */ +#define CRM_APB1RST_TMR6RST_Pos (4U) +#define CRM_APB1RST_TMR6RST_Msk (0x1U << CRM_APB1RST_TMR6RST_Pos) /*!< 0x00000010 */ +#define CRM_APB1RST_TMR6RST CRM_APB1RST_TMR6RST_Msk /*!< TMR6 reset */ +#define CRM_APB1RST_TMR7RST_Pos (5U) +#define CRM_APB1RST_TMR7RST_Msk (0x1U << CRM_APB1RST_TMR7RST_Pos) /*!< 0x00000020 */ +#define CRM_APB1RST_TMR7RST CRM_APB1RST_TMR7RST_Msk /*!< TMR7 reset */ +#define CRM_APB1RST_TMR13RST_Pos (7U) +#define CRM_APB1RST_TMR13RST_Msk (0x1U << CRM_APB1RST_TMR13RST_Pos) /*!< 0x00000080 */ +#define CRM_APB1RST_TMR13RST CRM_APB1RST_TMR13RST_Msk /*!< TMR13 reset */ +#define CRM_APB1RST_TMR14RST_Pos (8U) +#define CRM_APB1RST_TMR14RST_Msk (0x1U << CRM_APB1RST_TMR14RST_Pos) /*!< 0x00000100 */ +#define CRM_APB1RST_TMR14RST CRM_APB1RST_TMR14RST_Msk /*!< TMR14 reset */ +#define CRM_APB1RST_WWDTRST_Pos (11U) +#define CRM_APB1RST_WWDTRST_Msk (0x1U << CRM_APB1RST_WWDTRST_Pos) /*!< 0x00000800 */ +#define CRM_APB1RST_WWDTRST CRM_APB1RST_WWDTRST_Msk /*!< WWDT reset */ +#define CRM_APB1RST_SPI2RST_Pos (14U) +#define CRM_APB1RST_SPI2RST_Msk (0x1U << CRM_APB1RST_SPI2RST_Pos) /*!< 0x00004000 */ +#define CRM_APB1RST_SPI2RST CRM_APB1RST_SPI2RST_Msk /*!< SPI2 reset */ +#define CRM_APB1RST_SPI3RST_Pos (15U) +#define CRM_APB1RST_SPI3RST_Msk (0x1U << CRM_APB1RST_SPI3RST_Pos) /*!< 0x00008000 */ +#define CRM_APB1RST_SPI3RST CRM_APB1RST_SPI3RST_Msk /*!< SPI3 reset */ +#define CRM_APB1RST_USART2RST_Pos (17U) +#define CRM_APB1RST_USART2RST_Msk (0x1U << CRM_APB1RST_USART2RST_Pos) /*!< 0x00020000 */ +#define CRM_APB1RST_USART2RST CRM_APB1RST_USART2RST_Msk /*!< USART2 reset */ +#define CRM_APB1RST_USART3RST_Pos (18U) +#define CRM_APB1RST_USART3RST_Msk (0x1U << CRM_APB1RST_USART3RST_Pos) /*!< 0x00040000 */ +#define CRM_APB1RST_USART3RST CRM_APB1RST_USART3RST_Msk /*!< USART3 reset */ +#define CRM_APB1RST_USART4RST_Pos (19U) +#define CRM_APB1RST_USART4RST_Msk (0x1U << CRM_APB1RST_USART4RST_Pos) /*!< 0x00080000 */ +#define CRM_APB1RST_USART4RST CRM_APB1RST_USART4RST_Msk /*!< USART4 reset */ +#define CRM_APB1RST_USART5RST_Pos (20U) +#define CRM_APB1RST_USART5RST_Msk (0x1U << CRM_APB1RST_USART5RST_Pos) /*!< 0x00100000 */ +#define CRM_APB1RST_USART5RST CRM_APB1RST_USART5RST_Msk /*!< USART5 reset */ +#define CRM_APB1RST_I2C1RST_Pos (21U) +#define CRM_APB1RST_I2C1RST_Msk (0x1U << CRM_APB1RST_I2C1RST_Pos) /*!< 0x00200000 */ +#define CRM_APB1RST_I2C1RST CRM_APB1RST_I2C1RST_Msk /*!< I2C1 reset */ +#define CRM_APB1RST_I2C2RST_Pos (22U) +#define CRM_APB1RST_I2C2RST_Msk (0x1U << CRM_APB1RST_I2C2RST_Pos) /*!< 0x00400000 */ +#define CRM_APB1RST_I2C2RST CRM_APB1RST_I2C2RST_Msk /*!< I2C2 reset */ +#define CRM_APB1RST_I2C3RST_Pos (23U) +#define CRM_APB1RST_I2C3RST_Msk (0x1U << CRM_APB1RST_I2C3RST_Pos) /*!< 0x00800000 */ +#define CRM_APB1RST_I2C3RST CRM_APB1RST_I2C3RST_Msk /*!< I2C3 reset */ +#define CRM_APB1RST_CAN1RST_Pos (25U) +#define CRM_APB1RST_CAN1RST_Msk (0x1U << CRM_APB1RST_CAN1RST_Pos) /*!< 0x02000000 */ +#define CRM_APB1RST_CAN1RST CRM_APB1RST_CAN1RST_Msk /*!< CAN1 reset */ +#define CRM_APB1RST_PWCRST_Pos (28U) +#define CRM_APB1RST_PWCRST_Msk (0x1U << CRM_APB1RST_PWCRST_Pos) /*!< 0x10000000 */ +#define CRM_APB1RST_PWCRST CRM_APB1RST_PWCRST_Msk /*!< PWC reset */ +#define CRM_APB1RST_UART7RST_Pos (30U) +#define CRM_APB1RST_UART7RST_Msk (0x1U << CRM_APB1RST_UART7RST_Pos) /*!< 0x40000000 */ +#define CRM_APB1RST_UART7RST CRM_APB1RST_UART7RST_Msk /*!< UART7 reset */ + +/***************** Bit definition for CRM_APB2RST register ******************/ +#define CRM_APB2RST_TMR1RST_Pos (0U) +#define CRM_APB2RST_TMR1RST_Msk (0x1U << CRM_APB2RST_TMR1RST_Pos) /*!< 0x00000001 */ +#define CRM_APB2RST_TMR1RST CRM_APB2RST_TMR1RST_Msk /*!< TMR1 reset */ +#define CRM_APB2RST_USART1RST_Pos (4U) +#define CRM_APB2RST_USART1RST_Msk (0x1U << CRM_APB2RST_USART1RST_Pos) /*!< 0x00000010 */ +#define CRM_APB2RST_USART1RST CRM_APB2RST_USART1RST_Msk /*!< USART1 reset */ +#define CRM_APB2RST_USART6RST_Pos (5U) +#define CRM_APB2RST_USART6RST_Msk (0x1U << CRM_APB2RST_USART6RST_Pos) /*!< 0x00000020 */ +#define CRM_APB2RST_USART6RST CRM_APB2RST_USART6RST_Msk /*!< USART6 reset */ +#define CRM_APB2RST_ADCRST_Pos (8U) +#define CRM_APB2RST_ADCRST_Msk (0x1U << CRM_APB2RST_ADCRST_Pos) /*!< 0x00000100 */ +#define CRM_APB2RST_ADCRST CRM_APB2RST_ADCRST_Msk /*!< ADC reset */ +#define CRM_APB2RST_SPI1RST_Pos (12U) +#define CRM_APB2RST_SPI1RST_Msk (0x1U << CRM_APB2RST_SPI1RST_Pos) /*!< 0x00001000 */ +#define CRM_APB2RST_SPI1RST CRM_APB2RST_SPI1RST_Msk /*!< SPI1 reset */ +#define CRM_APB2RST_SCFGRST_Pos (14U) +#define CRM_APB2RST_SCFGRST_Msk (0x1U << CRM_APB2RST_SCFGRST_Pos) /*!< 0x00004000 */ +#define CRM_APB2RST_SCFGRST CRM_APB2RST_SCFGRST_Msk /*!< SCFG reset */ +#define CRM_APB2RST_EXINTRST_Pos (15U) +#define CRM_APB2RST_EXINTRST_Msk (0x1U << CRM_APB2RST_EXINTRST_Pos) /*!< 0x00008000 */ +#define CRM_APB2RST_EXINTRST CRM_APB2RST_EXINTRST_Msk /*!< EXINT reset */ +#define CRM_APB2RST_TMR9RST_Pos (16U) +#define CRM_APB2RST_TMR9RST_Msk (0x1U << CRM_APB2RST_TMR9RST_Pos) /*!< 0x00010000 */ +#define CRM_APB2RST_TMR9RST CRM_APB2RST_TMR9RST_Msk /*!< TMR9 reset */ +#define CRM_APB2RST_TMR10RST_Pos (17U) +#define CRM_APB2RST_TMR10RST_Msk (0x1U << CRM_APB2RST_TMR10RST_Pos) /*!< 0x00020000 */ +#define CRM_APB2RST_TMR10RST CRM_APB2RST_TMR10RST_Msk /*!< TMR10 reset */ +#define CRM_APB2RST_TMR11RST_Pos (18U) +#define CRM_APB2RST_TMR11RST_Msk (0x1U << CRM_APB2RST_TMR11RST_Pos) /*!< 0x00040000 */ +#define CRM_APB2RST_TMR11RST CRM_APB2RST_TMR11RST_Msk /*!< TMR11 reset */ +#define CRM_APB2RST_I2SF5RST_Pos (20U) +#define CRM_APB2RST_I2SF5RST_Msk (0x1U << CRM_APB2RST_I2SF5RST_Pos) /*!< 0x00100000 */ +#define CRM_APB2RST_I2SF5RST CRM_APB2RST_I2SF5RST_Msk /*!< I2SF5 reset */ +#define CRM_APB2RST_ACCRST_Pos (29U) +#define CRM_APB2RST_ACCRST_Msk (0x1U << CRM_APB2RST_ACCRST_Pos) /*!< 0x20000000 */ +#define CRM_APB2RST_ACCRST CRM_APB2RST_ACCRST_Msk /*!< ACC reset */ + +/****************** Bit definition for CRM_AHBEN1 register ******************/ +#define CRM_AHBEN1_GPIOAEN_Pos (0U) +#define CRM_AHBEN1_GPIOAEN_Msk (0x1U << CRM_AHBEN1_GPIOAEN_Pos) /*!< 0x00000001 */ +#define CRM_AHBEN1_GPIOAEN CRM_AHBEN1_GPIOAEN_Msk /*!< IO port A clock enable */ +#define CRM_AHBEN1_GPIOBEN_Pos (1U) +#define CRM_AHBEN1_GPIOBEN_Msk (0x1U << CRM_AHBEN1_GPIOBEN_Pos) /*!< 0x00000002 */ +#define CRM_AHBEN1_GPIOBEN CRM_AHBEN1_GPIOBEN_Msk /*!< IO port B clock enable */ +#define CRM_AHBEN1_GPIOCEN_Pos (2U) +#define CRM_AHBEN1_GPIOCEN_Msk (0x1U << CRM_AHBEN1_GPIOCEN_Pos) /*!< 0x00000004 */ +#define CRM_AHBEN1_GPIOCEN CRM_AHBEN1_GPIOCEN_Msk /*!< IO port C clock enable */ +#define CRM_AHBEN1_GPIODEN_Pos (3U) +#define CRM_AHBEN1_GPIODEN_Msk (0x1U << CRM_AHBEN1_GPIODEN_Pos) /*!< 0x00000008 */ +#define CRM_AHBEN1_GPIODEN CRM_AHBEN1_GPIODEN_Msk /*!< IO port D clock enable */ +#define CRM_AHBEN1_GPIOFEN_Pos (5U) +#define CRM_AHBEN1_GPIOFEN_Msk (0x1U << CRM_AHBEN1_GPIOFEN_Pos) /*!< 0x00000020 */ +#define CRM_AHBEN1_GPIOFEN CRM_AHBEN1_GPIOFEN_Msk /*!< IO port F clock enable */ +#define CRM_AHBEN1_CRCEN_Pos (12U) +#define CRM_AHBEN1_CRCEN_Msk (0x1U << CRM_AHBEN1_CRCEN_Pos) /*!< 0x00001000 */ +#define CRM_AHBEN1_CRCEN CRM_AHBEN1_CRCEN_Msk /*!< CRC clock enable */ +#define CRM_AHBEN1_DMA1EN_Pos (22U) +#define CRM_AHBEN1_DMA1EN_Msk (0x1U << CRM_AHBEN1_DMA1EN_Pos) /*!< 0x00400000 */ +#define CRM_AHBEN1_DMA1EN CRM_AHBEN1_DMA1EN_Msk /*!< DMA1 clock enable */ +#define CRM_AHBEN1_DMA2EN_Pos (24U) +#define CRM_AHBEN1_DMA2EN_Msk (0x1U << CRM_AHBEN1_DMA2EN_Pos) /*!< 0x01000000 */ +#define CRM_AHBEN1_DMA2EN CRM_AHBEN1_DMA2EN_Msk /*!< DMA2 clock enable */ +#define CRM_AHBEN1_OTGHSEN_Pos (29U) +#define CRM_AHBEN1_OTGHSEN_Msk (0x1U << CRM_AHBEN1_OTGHSEN_Pos) /*!< 0x20000000 */ +#define CRM_AHBEN1_OTGHSEN CRM_AHBEN1_OTGHSEN_Msk /*!< OTGHS clock enable (F405 only) */ + +/****************** Bit definition for CRM_AHBEN2 register ******************/ +#define CRM_AHBEN2_OTGFSEN_Pos (7U) +#define CRM_AHBEN2_OTGFSEN_Msk (0x1U << CRM_AHBEN2_OTGFSEN_Pos) /*!< 0x00000080 */ +#define CRM_AHBEN2_OTGFSEN CRM_AHBEN2_OTGFSEN_Msk /*!< OTGFS clock enable */ + +/****************** Bit definition for CRM_AHBEN3 register ******************/ +#define CRM_AHBEN3_QSPI1EN_Pos (1U) +#define CRM_AHBEN3_QSPI1EN_Msk (0x1U << CRM_AHBEN3_QSPI1EN_Pos) /*!< 0x00000002 */ +#define CRM_AHBEN3_QSPI1EN CRM_AHBEN3_QSPI1EN_Msk /*!< QSPI1 clock enable */ + +/****************** Bit definition for CRM_APB1EN register ******************/ +#define CRM_APB1EN_TMR2EN_Pos (0U) +#define CRM_APB1EN_TMR2EN_Msk (0x1U << CRM_APB1EN_TMR2EN_Pos) /*!< 0x00000001 */ +#define CRM_APB1EN_TMR2EN CRM_APB1EN_TMR2EN_Msk /*!< TMR2 clock enable */ +#define CRM_APB1EN_TMR3EN_Pos (1U) +#define CRM_APB1EN_TMR3EN_Msk (0x1U << CRM_APB1EN_TMR3EN_Pos) /*!< 0x00000002 */ +#define CRM_APB1EN_TMR3EN CRM_APB1EN_TMR3EN_Msk /*!< TMR3 clock enable */ +#define CRM_APB1EN_TMR4EN_Pos (2U) +#define CRM_APB1EN_TMR4EN_Msk (0x1U << CRM_APB1EN_TMR4EN_Pos) /*!< 0x00000004 */ +#define CRM_APB1EN_TMR4EN CRM_APB1EN_TMR4EN_Msk /*!< TMR4 clock enable */ +#define CRM_APB1EN_TMR6EN_Pos (4U) +#define CRM_APB1EN_TMR6EN_Msk (0x1U << CRM_APB1EN_TMR6EN_Pos) /*!< 0x00000010 */ +#define CRM_APB1EN_TMR6EN CRM_APB1EN_TMR6EN_Msk /*!< TMR6 clock enable */ +#define CRM_APB1EN_TMR7EN_Pos (5U) +#define CRM_APB1EN_TMR7EN_Msk (0x1U << CRM_APB1EN_TMR7EN_Pos) /*!< 0x00000020 */ +#define CRM_APB1EN_TMR7EN CRM_APB1EN_TMR7EN_Msk /*!< TMR7 clock enable */ +#define CRM_APB1EN_TMR13EN_Pos (7U) +#define CRM_APB1EN_TMR13EN_Msk (0x1U << CRM_APB1EN_TMR13EN_Pos) /*!< 0x00000080 */ +#define CRM_APB1EN_TMR13EN CRM_APB1EN_TMR13EN_Msk /*!< TMR13 clock enable */ +#define CRM_APB1EN_TMR14EN_Pos (8U) +#define CRM_APB1EN_TMR14EN_Msk (0x1U << CRM_APB1EN_TMR14EN_Pos) /*!< 0x00000100 */ +#define CRM_APB1EN_TMR14EN CRM_APB1EN_TMR14EN_Msk /*!< TMR14 clock enable */ +#define CRM_APB1EN_WWDTEN_Pos (11U) +#define CRM_APB1EN_WWDTEN_Msk (0x1U << CRM_APB1EN_WWDTEN_Pos) /*!< 0x00000800 */ +#define CRM_APB1EN_WWDTEN CRM_APB1EN_WWDTEN_Msk /*!< WWDT clock enable */ +#define CRM_APB1EN_SPI2EN_Pos (14U) +#define CRM_APB1EN_SPI2EN_Msk (0x1U << CRM_APB1EN_SPI2EN_Pos) /*!< 0x00004000 */ +#define CRM_APB1EN_SPI2EN CRM_APB1EN_SPI2EN_Msk /*!< SPI2 clock enable */ +#define CRM_APB1EN_SPI3EN_Pos (15U) +#define CRM_APB1EN_SPI3EN_Msk (0x1U << CRM_APB1EN_SPI3EN_Pos) /*!< 0x00008000 */ +#define CRM_APB1EN_SPI3EN CRM_APB1EN_SPI3EN_Msk /*!< SPI3 clock enable */ +#define CRM_APB1EN_USART2EN_Pos (17U) +#define CRM_APB1EN_USART2EN_Msk (0x1U << CRM_APB1EN_USART2EN_Pos) /*!< 0x00020000 */ +#define CRM_APB1EN_USART2EN CRM_APB1EN_USART2EN_Msk /*!< USART2 clock enable */ +#define CRM_APB1EN_USART3EN_Pos (18U) +#define CRM_APB1EN_USART3EN_Msk (0x1U << CRM_APB1EN_USART3EN_Pos) /*!< 0x00040000 */ +#define CRM_APB1EN_USART3EN CRM_APB1EN_USART3EN_Msk /*!< USART3 clock enable */ +#define CRM_APB1EN_USART4EN_Pos (19U) +#define CRM_APB1EN_USART4EN_Msk (0x1U << CRM_APB1EN_USART4EN_Pos) /*!< 0x00080000 */ +#define CRM_APB1EN_USART4EN CRM_APB1EN_USART4EN_Msk /*!< USART4 clock enable */ +#define CRM_APB1EN_USART5EN_Pos (20U) +#define CRM_APB1EN_USART5EN_Msk (0x1U << CRM_APB1EN_USART5EN_Pos) /*!< 0x00100000 */ +#define CRM_APB1EN_USART5EN CRM_APB1EN_USART5EN_Msk /*!< USART5 clock enable */ +#define CRM_APB1EN_I2C1EN_Pos (21U) +#define CRM_APB1EN_I2C1EN_Msk (0x1U << CRM_APB1EN_I2C1EN_Pos) /*!< 0x00200000 */ +#define CRM_APB1EN_I2C1EN CRM_APB1EN_I2C1EN_Msk /*!< I2C1 clock enable */ +#define CRM_APB1EN_I2C2EN_Pos (22U) +#define CRM_APB1EN_I2C2EN_Msk (0x1U << CRM_APB1EN_I2C2EN_Pos) /*!< 0x00400000 */ +#define CRM_APB1EN_I2C2EN CRM_APB1EN_I2C2EN_Msk /*!< I2C2 clock enable */ +#define CRM_APB1EN_I2C3EN_Pos (23U) +#define CRM_APB1EN_I2C3EN_Msk (0x1U << CRM_APB1EN_I2C3EN_Pos) /*!< 0x00800000 */ +#define CRM_APB1EN_I2C3EN CRM_APB1EN_I2C3EN_Msk /*!< I2C3 clock enable */ +#define CRM_APB1EN_CAN1EN_Pos (25U) +#define CRM_APB1EN_CAN1EN_Msk (0x1U << CRM_APB1EN_CAN1EN_Pos) /*!< 0x02000000 */ +#define CRM_APB1EN_CAN1EN CRM_APB1EN_CAN1EN_Msk /*!< CAN1 clock enable */ +#define CRM_APB1EN_PWCEN_Pos (28U) +#define CRM_APB1EN_PWCEN_Msk (0x1U << CRM_APB1EN_PWCEN_Pos) /*!< 0x10000000 */ +#define CRM_APB1EN_PWCEN CRM_APB1EN_PWCEN_Msk /*!< Power control clock enable */ +#define CRM_APB1EN_UART7EN_Pos (30U) +#define CRM_APB1EN_UART7EN_Msk (0x1U << CRM_APB1EN_UART7EN_Pos) /*!< 0x40000000 */ +#define CRM_APB1EN_UART7EN CRM_APB1EN_UART7EN_Msk /*!< UART7 clock enable */ + +/****************** Bit definition for CRM_APB2EN register ******************/ +#define CRM_APB2EN_TMR1EN_Pos (0U) +#define CRM_APB2EN_TMR1EN_Msk (0x1U << CRM_APB2EN_TMR1EN_Pos) /*!< 0x00000001 */ +#define CRM_APB2EN_TMR1EN CRM_APB2EN_TMR1EN_Msk /*!< TMR1 clock enable */ +#define CRM_APB2EN_USART1EN_Pos (4U) +#define CRM_APB2EN_USART1EN_Msk (0x1U << CRM_APB2EN_USART1EN_Pos) /*!< 0x00000010 */ +#define CRM_APB2EN_USART1EN CRM_APB2EN_USART1EN_Msk /*!< USART1 clock enable */ +#define CRM_APB2EN_USART6EN_Pos (5U) +#define CRM_APB2EN_USART6EN_Msk (0x1U << CRM_APB2EN_USART6EN_Pos) /*!< 0x00000020 */ +#define CRM_APB2EN_USART6EN CRM_APB2EN_USART6EN_Msk /*!< USART6 clock enable */ +#define CRM_APB2EN_ADC1EN_Pos (8U) +#define CRM_APB2EN_ADC1EN_Msk (0x1U << CRM_APB2EN_ADC1EN_Pos) /*!< 0x00000100 */ +#define CRM_APB2EN_ADC1EN CRM_APB2EN_ADC1EN_Msk /*!< ADC1 clock enable */ +#define CRM_APB2EN_SPI1EN_Pos (12U) +#define CRM_APB2EN_SPI1EN_Msk (0x1U << CRM_APB2EN_SPI1EN_Pos) /*!< 0x00001000 */ +#define CRM_APB2EN_SPI1EN CRM_APB2EN_SPI1EN_Msk /*!< SPI1 clock enable */ +#define CRM_APB2EN_SCFGEN_Pos (14U) +#define CRM_APB2EN_SCFGEN_Msk (0x1U << CRM_APB2EN_SCFGEN_Pos) /*!< 0x00004000 */ +#define CRM_APB2EN_SCFGEN CRM_APB2EN_SCFGEN_Msk /*!< SCFG clock enable */ +#define CRM_APB2EN_TMR9EN_Pos (16U) +#define CRM_APB2EN_TMR9EN_Msk (0x1U << CRM_APB2EN_TMR9EN_Pos) /*!< 0x00010000 */ +#define CRM_APB2EN_TMR9EN CRM_APB2EN_TMR9EN_Msk /*!< TMR9 clock enable */ +#define CRM_APB2EN_TMR10EN_Pos (17U) +#define CRM_APB2EN_TMR10EN_Msk (0x1U << CRM_APB2EN_TMR10EN_Pos) /*!< 0x00020000 */ +#define CRM_APB2EN_TMR10EN CRM_APB2EN_TMR10EN_Msk /*!< TMR10 clock enable */ +#define CRM_APB2EN_TMR11EN_Pos (18U) +#define CRM_APB2EN_TMR11EN_Msk (0x1U << CRM_APB2EN_TMR11EN_Pos) /*!< 0x00040000 */ +#define CRM_APB2EN_TMR11EN CRM_APB2EN_TMR11EN_Msk /*!< TMR11 clock enable */ +#define CRM_APB2EN_I2SF5EN_Pos (20U) +#define CRM_APB2EN_I2SF5EN_Msk (0x1U << CRM_APB2EN_I2SF5EN_Pos) /*!< 0x00100000 */ +#define CRM_APB2EN_I2SF5EN CRM_APB2EN_I2SF5EN_Msk /*!< I2SF5 clock enable */ +#define CRM_APB2EN_ACCEN_Pos (29U) +#define CRM_APB2EN_ACCEN_Msk (0x1U << CRM_APB2EN_ACCEN_Pos) /*!< 0x20000000 */ +#define CRM_APB2EN_ACCEN CRM_APB2EN_ACCEN_Msk /*!< ACC clock enable */ + +/***************** Bit definition for CRM_AHBLPEN1 register *****************/ +#define CRM_AHBLPEN1_GPIOALPEN_Pos (0U) +#define CRM_AHBLPEN1_GPIOALPEN_Msk (0x1U << CRM_AHBLPEN1_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define CRM_AHBLPEN1_GPIOALPEN CRM_AHBLPEN1_GPIOALPEN_Msk /*!< IO port A clock enable in sleep mode */ +#define CRM_AHBLPEN1_GPIOBLPEN_Pos (1U) +#define CRM_AHBLPEN1_GPIOBLPEN_Msk (0x1U << CRM_AHBLPEN1_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define CRM_AHBLPEN1_GPIOBLPEN CRM_AHBLPEN1_GPIOBLPEN_Msk /*!< IO port B clock enable in sleep mode */ +#define CRM_AHBLPEN1_GPIOCLPEN_Pos (2U) +#define CRM_AHBLPEN1_GPIOCLPEN_Msk (0x1U << CRM_AHBLPEN1_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define CRM_AHBLPEN1_GPIOCLPEN CRM_AHBLPEN1_GPIOCLPEN_Msk /*!< IO port C clock enable in sleep mode */ +#define CRM_AHBLPEN1_GPIODLPEN_Pos (3U) +#define CRM_AHBLPEN1_GPIODLPEN_Msk (0x1U << CRM_AHBLPEN1_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define CRM_AHBLPEN1_GPIODLPEN CRM_AHBLPEN1_GPIODLPEN_Msk /*!< IO port D clock enable in sleep mode */ +#define CRM_AHBLPEN1_GPIOFLPEN_Pos (5U) +#define CRM_AHBLPEN1_GPIOFLPEN_Msk (0x1U << CRM_AHBLPEN1_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define CRM_AHBLPEN1_GPIOFLPEN CRM_AHBLPEN1_GPIOFLPEN_Msk /*!< IO port F clock enable in sleep mode */ +#define CRM_AHBLPEN1_CRCLPEN_Pos (12U) +#define CRM_AHBLPEN1_CRCLPEN_Msk (0x1U << CRM_AHBLPEN1_CRCLPEN_Pos) /*!< 0x00001000 */ +#define CRM_AHBLPEN1_CRCLPEN CRM_AHBLPEN1_CRCLPEN_Msk /*!< CRC clock enable in sleep mode */ +#define CRM_AHBLPEN1_FLASHLPEN_Pos (15U) +#define CRM_AHBLPEN1_FLASHLPEN_Msk (0x1U << CRM_AHBLPEN1_FLASHLPEN_Pos) /*!< 0x00008000 */ +#define CRM_AHBLPEN1_FLASHLPEN CRM_AHBLPEN1_FLASHLPEN_Msk /*!< FLASH clock enable in sleep mode */ +#define CRM_AHBLPEN1_SRAMLPEN_Pos (16U) +#define CRM_AHBLPEN1_SRAMLPEN_Msk (0x1U << CRM_AHBLPEN1_SRAMLPEN_Pos) /*!< 0x00010000 */ +#define CRM_AHBLPEN1_SRAMLPEN CRM_AHBLPEN1_SRAMLPEN_Msk /*!< SRAM clock enable in sleep mode */ +#define CRM_AHBLPEN1_DMA1LPEN_Pos (22U) +#define CRM_AHBLPEN1_DMA1LPEN_Msk (0x1U << CRM_AHBLPEN1_DMA1LPEN_Pos) /*!< 0x00400000 */ +#define CRM_AHBLPEN1_DMA1LPEN CRM_AHBLPEN1_DMA1LPEN_Msk /*!< DMA1 clock enable in sleep mode */ +#define CRM_AHBLPEN1_DMA2LPEN_Pos (24U) +#define CRM_AHBLPEN1_DMA2LPEN_Msk (0x1U << CRM_AHBLPEN1_DMA2LPEN_Pos) /*!< 0x01000000 */ +#define CRM_AHBLPEN1_DMA2LPEN CRM_AHBLPEN1_DMA2LPEN_Msk /*!< DMA2 clock enable in sleep mode */ +#define CRM_AHBLPEN1_OTGHSLPEN_Pos (29U) +#define CRM_AHBLPEN1_OTGHSLPEN_Msk (0x1U << CRM_AHBLPEN1_OTGHSLPEN_Pos) /*!< 0x20000000 */ +#define CRM_AHBLPEN1_OTGHSLPEN CRM_AHBLPEN1_OTGHSLPEN_Msk /*!< OTGHS clock enable in sleep mode (F405 only) */ + +/***************** Bit definition for CRM_AHBLPEN2 register *****************/ +#define CRM_AHBLPEN2_OTGFSLPEN_Pos (7U) +#define CRM_AHBLPEN2_OTGFSLPEN_Msk (0x1U << CRM_AHBLPEN2_OTGFSLPEN_Pos) /*!< 0x00000080 */ +#define CRM_AHBLPEN2_OTGFSLPEN CRM_AHBLPEN2_OTGFSLPEN_Msk /*!< OTGFS clock enable in sleep mode */ + +/***************** Bit definition for CRM_AHBLPEN3 register *****************/ +#define CRM_AHBLPEN3_QSPI1LPEN_Pos (1U) +#define CRM_AHBLPEN3_QSPI1LPEN_Msk (0x1U << CRM_AHBLPEN3_QSPI1LPEN_Pos) /*!< 0x00000002 */ +#define CRM_AHBLPEN3_QSPI1LPEN CRM_AHBLPEN3_QSPI1LPEN_Msk /*!< QSPI1 clock enable in sleep mode */ + +/***************** Bit definition for CRM_APB1LPEN register *****************/ +#define CRM_APB1LPEN_TMR2LPEN_Pos (0U) +#define CRM_APB1LPEN_TMR2LPEN_Msk (0x1U << CRM_APB1LPEN_TMR2LPEN_Pos) /*!< 0x00000001 */ +#define CRM_APB1LPEN_TMR2LPEN CRM_APB1LPEN_TMR2LPEN_Msk /*!< TMR2 clock enable in sleep mode */ +#define CRM_APB1LPEN_TMR3LPEN_Pos (1U) +#define CRM_APB1LPEN_TMR3LPEN_Msk (0x1U << CRM_APB1LPEN_TMR3LPEN_Pos) /*!< 0x00000002 */ +#define CRM_APB1LPEN_TMR3LPEN CRM_APB1LPEN_TMR3LPEN_Msk /*!< TMR3 clock enable in sleep mode */ +#define CRM_APB1LPEN_TMR4LPEN_Pos (2U) +#define CRM_APB1LPEN_TMR4LPEN_Msk (0x1U << CRM_APB1LPEN_TMR4LPEN_Pos) /*!< 0x00000004 */ +#define CRM_APB1LPEN_TMR4LPEN CRM_APB1LPEN_TMR4LPEN_Msk /*!< TMR4 clock enable in sleep mode */ +#define CRM_APB1LPEN_TMR6LPEN_Pos (4U) +#define CRM_APB1LPEN_TMR6LPEN_Msk (0x1U << CRM_APB1LPEN_TMR6LPEN_Pos) /*!< 0x00000010 */ +#define CRM_APB1LPEN_TMR6LPEN CRM_APB1LPEN_TMR6LPEN_Msk /*!< TMR6 clock enable in sleep mode */ +#define CRM_APB1LPEN_TMR7LPEN_Pos (5U) +#define CRM_APB1LPEN_TMR7LPEN_Msk (0x1U << CRM_APB1LPEN_TMR7LPEN_Pos) /*!< 0x00000020 */ +#define CRM_APB1LPEN_TMR7LPEN CRM_APB1LPEN_TMR7LPEN_Msk /*!< TMR7 clock enable in sleep mode */ +#define CRM_APB1LPEN_TMR13LPEN_Pos (7U) +#define CRM_APB1LPEN_TMR13LPEN_Msk (0x1U << CRM_APB1LPEN_TMR13LPEN_Pos) /*!< 0x00000080 */ +#define CRM_APB1LPEN_TMR13LPEN CRM_APB1LPEN_TMR13LPEN_Msk /*!< TMR13 clock enable in sleep mode */ +#define CRM_APB1LPEN_TMR14LPEN_Pos (8U) +#define CRM_APB1LPEN_TMR14LPEN_Msk (0x1U << CRM_APB1LPEN_TMR14LPEN_Pos) /*!< 0x00000100 */ +#define CRM_APB1LPEN_TMR14LPEN CRM_APB1LPEN_TMR14LPEN_Msk /*!< TMR14 clock enable in sleep mode */ +#define CRM_APB1LPEN_WWDTLPEN_Pos (11U) +#define CRM_APB1LPEN_WWDTLPEN_Msk (0x1U << CRM_APB1LPEN_WWDTLPEN_Pos) /*!< 0x00000800 */ +#define CRM_APB1LPEN_WWDTLPEN CRM_APB1LPEN_WWDTLPEN_Msk /*!< WWDT clock enable in sleep mode */ +#define CRM_APB1LPEN_SPI2LPEN_Pos (14U) +#define CRM_APB1LPEN_SPI2LPEN_Msk (0x1U << CRM_APB1LPEN_SPI2LPEN_Pos) /*!< 0x00004000 */ +#define CRM_APB1LPEN_SPI2LPEN CRM_APB1LPEN_SPI2LPEN_Msk /*!< SPI2 clock enable in sleep mode */ +#define CRM_APB1LPEN_SPI3LPEN_Pos (15U) +#define CRM_APB1LPEN_SPI3LPEN_Msk (0x1U << CRM_APB1LPEN_SPI3LPEN_Pos) /*!< 0x00008000 */ +#define CRM_APB1LPEN_SPI3LPEN CRM_APB1LPEN_SPI3LPEN_Msk /*!< SPI3 clock enable in sleep mode */ +#define CRM_APB1LPEN_USART2LPEN_Pos (17U) +#define CRM_APB1LPEN_USART2LPEN_Msk (0x1U << CRM_APB1LPEN_USART2LPEN_Pos) /*!< 0x00020000 */ +#define CRM_APB1LPEN_USART2LPEN CRM_APB1LPEN_USART2LPEN_Msk /*!< USART2 clock enable in sleep mode */ +#define CRM_APB1LPEN_USART3LPEN_Pos (18U) +#define CRM_APB1LPEN_USART3LPEN_Msk (0x1U << CRM_APB1LPEN_USART3LPEN_Pos) /*!< 0x00040000 */ +#define CRM_APB1LPEN_USART3LPEN CRM_APB1LPEN_USART3LPEN_Msk /*!< USART3 clock enable in sleep mode */ +#define CRM_APB1LPEN_USART4LPEN_Pos (19U) +#define CRM_APB1LPEN_USART4LPEN_Msk (0x1U << CRM_APB1LPEN_USART4LPEN_Pos) /*!< 0x00080000 */ +#define CRM_APB1LPEN_USART4LPEN CRM_APB1LPEN_USART4LPEN_Msk /*!< USART4 clock enable in sleep mode */ +#define CRM_APB1LPEN_USART5LPEN_Pos (20U) +#define CRM_APB1LPEN_USART5LPEN_Msk (0x1U << CRM_APB1LPEN_USART5LPEN_Pos) /*!< 0x00100000 */ +#define CRM_APB1LPEN_USART5LPEN CRM_APB1LPEN_USART5LPEN_Msk /*!< USART5 clock enable in sleep mode */ +#define CRM_APB1LPEN_I2C1LPEN_Pos (21U) +#define CRM_APB1LPEN_I2C1LPEN_Msk (0x1U << CRM_APB1LPEN_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define CRM_APB1LPEN_I2C1LPEN CRM_APB1LPEN_I2C1LPEN_Msk /*!< I2C1 clock enable in sleep mode */ +#define CRM_APB1LPEN_I2C2LPEN_Pos (22U) +#define CRM_APB1LPEN_I2C2LPEN_Msk (0x1U << CRM_APB1LPEN_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define CRM_APB1LPEN_I2C2LPEN CRM_APB1LPEN_I2C2LPEN_Msk /*!< I2C2 clock enable in sleep mode */ +#define CRM_APB1LPEN_I2C3LPEN_Pos (23U) +#define CRM_APB1LPEN_I2C3LPEN_Msk (0x1U << CRM_APB1LPEN_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define CRM_APB1LPEN_I2C3LPEN CRM_APB1LPEN_I2C3LPEN_Msk /*!< I2C3 clock enable in sleep mode */ +#define CRM_APB1LPEN_CAN1LPEN_Pos (25U) +#define CRM_APB1LPEN_CAN1LPEN_Msk (0x1U << CRM_APB1LPEN_CAN1LPEN_Pos) /*!< 0x02000000 */ +#define CRM_APB1LPEN_CAN1LPEN CRM_APB1LPEN_CAN1LPEN_Msk /*!< CAN1 clock enable in sleep mode */ +#define CRM_APB1LPEN_PWCLPEN_Pos (28U) +#define CRM_APB1LPEN_PWCLPEN_Msk (0x1U << CRM_APB1LPEN_PWCLPEN_Pos) /*!< 0x10000000 */ +#define CRM_APB1LPEN_PWCLPEN CRM_APB1LPEN_PWCLPEN_Msk /*!< Power control clock enable in sleep mode */ +#define CRM_APB1LPEN_UART7LPEN_Pos (30U) +#define CRM_APB1LPEN_UART7LPEN_Msk (0x1U << CRM_APB1LPEN_UART7LPEN_Pos) /*!< 0x40000000 */ +#define CRM_APB1LPEN_UART7LPEN CRM_APB1LPEN_UART7LPEN_Msk /*!< UART7 clock enable in sleep mode */ + +/***************** Bit definition for CRM_APB2LPEN register *****************/ +#define CRM_APB2LPEN_TMR1LPEN_Pos (0U) +#define CRM_APB2LPEN_TMR1LPEN_Msk (0x1U << CRM_APB2LPEN_TMR1LPEN_Pos) /*!< 0x00000001 */ +#define CRM_APB2LPEN_TMR1LPEN CRM_APB2LPEN_TMR1LPEN_Msk /*!< TMR1 clock enable in sleep mode */ +#define CRM_APB2LPEN_USART1LPEN_Pos (4U) +#define CRM_APB2LPEN_USART1LPEN_Msk (0x1U << CRM_APB2LPEN_USART1LPEN_Pos) /*!< 0x00000010 */ +#define CRM_APB2LPEN_USART1LPEN CRM_APB2LPEN_USART1LPEN_Msk /*!< USART1 clock enable in sleep mode */ +#define CRM_APB2LPEN_USART6LPEN_Pos (5U) +#define CRM_APB2LPEN_USART6LPEN_Msk (0x1U << CRM_APB2LPEN_USART6LPEN_Pos) /*!< 0x00000020 */ +#define CRM_APB2LPEN_USART6LPEN CRM_APB2LPEN_USART6LPEN_Msk /*!< USART6 clock enable in sleep mode */ +#define CRM_APB2LPEN_ADC1LPEN_Pos (8U) +#define CRM_APB2LPEN_ADC1LPEN_Msk (0x1U << CRM_APB2LPEN_ADC1LPEN_Pos) /*!< 0x00000100 */ +#define CRM_APB2LPEN_ADC1LPEN CRM_APB2LPEN_ADC1LPEN_Msk /*!< ADC1 clock enable in sleep mode */ +#define CRM_APB2LPEN_SPI1LPEN_Pos (12U) +#define CRM_APB2LPEN_SPI1LPEN_Msk (0x1U << CRM_APB2LPEN_SPI1LPEN_Pos) /*!< 0x00001000 */ +#define CRM_APB2LPEN_SPI1LPEN CRM_APB2LPEN_SPI1LPEN_Msk /*!< SPI1 clock enable in sleep mode */ +#define CRM_APB2LPEN_SCFGLPEN_Pos (14U) +#define CRM_APB2LPEN_SCFGLPEN_Msk (0x1U << CRM_APB2LPEN_SCFGLPEN_Pos) /*!< 0x00004000 */ +#define CRM_APB2LPEN_SCFGLPEN CRM_APB2LPEN_SCFGLPEN_Msk /*!< SCFG clock enable in sleep mode */ +#define CRM_APB2LPEN_TMR9LPEN_Pos (16U) +#define CRM_APB2LPEN_TMR9LPEN_Msk (0x1U << CRM_APB2LPEN_TMR9LPEN_Pos) /*!< 0x00010000 */ +#define CRM_APB2LPEN_TMR9LPEN CRM_APB2LPEN_TMR9LPEN_Msk /*!< TMR9 clock enable in sleep mode */ +#define CRM_APB2LPEN_TMR10LPEN_Pos (17U) +#define CRM_APB2LPEN_TMR10LPEN_Msk (0x1U << CRM_APB2LPEN_TMR10LPEN_Pos) /*!< 0x00020000 */ +#define CRM_APB2LPEN_TMR10LPEN CRM_APB2LPEN_TMR10LPEN_Msk /*!< TMR10 clock enable in sleep mode */ +#define CRM_APB2LPEN_TMR11LPEN_Pos (18U) +#define CRM_APB2LPEN_TMR11LPEN_Msk (0x1U << CRM_APB2LPEN_TMR11LPEN_Pos) /*!< 0x00040000 */ +#define CRM_APB2LPEN_TMR11LPEN CRM_APB2LPEN_TMR11LPEN_Msk /*!< TMR11 clock enable in sleep mode */ +#define CRM_APB2LPEN_I2SF5LPEN_Pos (20U) +#define CRM_APB2LPEN_I2SF5LPEN_Msk (0x1U << CRM_APB2LPEN_I2SF5LPEN_Pos) /*!< 0x00100000 */ +#define CRM_APB2LPEN_I2SF5LPEN CRM_APB2LPEN_I2SF5LPEN_Msk /*!< I2SF5 clock enable in sleep mode */ +#define CRM_APB2LPEN_ACCLPEN_Pos (29U) +#define CRM_APB2LPEN_ACCLPEN_Msk (0x1U << CRM_APB2LPEN_ACCLPEN_Pos) /*!< 0x20000000 */ +#define CRM_APB2LPEN_ACCLPEN CRM_APB2LPEN_ACCLPEN_Msk /*!< ACC clock enable in sleep mode */ + +/******************* Bit definition for CRM_BPDC register *******************/ +#define CRM_BPDC_LEXTEN_Pos (0U) +#define CRM_BPDC_LEXTEN_Msk (0x1U << CRM_BPDC_LEXTEN_Pos) /*!< 0x00000001 */ +#define CRM_BPDC_LEXTEN CRM_BPDC_LEXTEN_Msk /*!< External low-speed oscillator enable */ +#define CRM_BPDC_LEXTSTBL_Pos (1U) +#define CRM_BPDC_LEXTSTBL_Msk (0x1U << CRM_BPDC_LEXTSTBL_Pos) /*!< 0x00000002 */ +#define CRM_BPDC_LEXTSTBL CRM_BPDC_LEXTSTBL_Msk /*!< External low-speed oscillator stable */ +#define CRM_BPDC_LEXTBYPS_Pos (2U) +#define CRM_BPDC_LEXTBYPS_Msk (0x1U << CRM_BPDC_LEXTBYPS_Pos) /*!< 0x00000004 */ +#define CRM_BPDC_LEXTBYPS CRM_BPDC_LEXTBYPS_Msk /*!< External low-speed crystal bypass */ + +/*!< ERTCSEL congiguration */ +#define CRM_BPDC_ERTCSEL_Pos (8U) +#define CRM_BPDC_ERTCSEL_Msk (0x3U << CRM_BPDC_ERTCSEL_Pos) /*!< 0x00000300 */ +#define CRM_BPDC_ERTCSEL CRM_BPDC_ERTCSEL_Msk /*!< ERTCSEL[1:0] bits (ERTC clock selection) */ +#define CRM_BPDC_ERTCSEL_0 (0x1U << CRM_BPDC_ERTCSEL_Pos) /*!< 0x00000100 */ +#define CRM_BPDC_ERTCSEL_1 (0x2U << CRM_BPDC_ERTCSEL_Pos) /*!< 0x00000200 */ + +#define CRM_BPDC_ERTCSEL_NOCLOCK 0x00000000U /*!< No clock */ +#define CRM_BPDC_ERTCSEL_LEXT 0x00000100U /*!< LEXT */ +#define CRM_BPDC_ERTCSEL_LICK 0x00000200U /*!< LICK */ +#define CRM_BPDC_ERTCSEL_HEXT 0x00000300U /*!< Devided HEXT with ERTCDIV bit in CRM_CFG */ + +#define CRM_BPDC_ERTCEN_Pos (15U) +#define CRM_BPDC_ERTCEN_Msk (0x1U << CRM_BPDC_ERTCEN_Pos) /*!< 0x00008000 */ +#define CRM_BPDC_ERTCEN CRM_BPDC_ERTCEN_Msk /*!< ERTC clock enable */ +#define CRM_BPDC_BPDRST_Pos (16U) +#define CRM_BPDC_BPDRST_Msk (0x1U << CRM_BPDC_BPDRST_Pos) /*!< 0x00010000 */ +#define CRM_BPDC_BPDRST CRM_BPDC_BPDRST_Msk /*!< Battery powered domain software reset */ + +/***************** Bit definition for CRM_CTRLSTS register ******************/ +#define CRM_CTRLSTS_LICKEN_Pos (0U) +#define CRM_CTRLSTS_LICKEN_Msk (0x1U << CRM_CTRLSTS_LICKEN_Pos) /*!< 0x00000001 */ +#define CRM_CTRLSTS_LICKEN CRM_CTRLSTS_LICKEN_Msk /*!< LICK enable */ +#define CRM_CTRLSTS_LICKSTBL_Pos (1U) +#define CRM_CTRLSTS_LICKSTBL_Msk (0x1U << CRM_CTRLSTS_LICKSTBL_Pos) /*!< 0x00000002 */ +#define CRM_CTRLSTS_LICKSTBL CRM_CTRLSTS_LICKSTBL_Msk /*!< LICK stable */ +#define CRM_CTRLSTS_RSTFC_Pos (24U) +#define CRM_CTRLSTS_RSTFC_Msk (0x1U << CRM_CTRLSTS_RSTFC_Pos) /*!< 0x01000000 */ +#define CRM_CTRLSTS_RSTFC CRM_CTRLSTS_RSTFC_Msk /*!< Reset flag clear */ +#define CRM_CTRLSTS_NRSTF_Pos (26U) +#define CRM_CTRLSTS_NRSTF_Msk (0x1U << CRM_CTRLSTS_NRSTF_Pos) /*!< 0x04000000 */ +#define CRM_CTRLSTS_NRSTF CRM_CTRLSTS_NRSTF_Msk /*!< NRST pin reset flag */ +#define CRM_CTRLSTS_PORRSTF_Pos (27U) +#define CRM_CTRLSTS_PORRSTF_Msk (0x1U << CRM_CTRLSTS_PORRSTF_Pos) /*!< 0x08000000 */ +#define CRM_CTRLSTS_PORRSTF CRM_CTRLSTS_PORRSTF_Msk /*!< POR/LVR reset flag */ +#define CRM_CTRLSTS_SWRSTF_Pos (28U) +#define CRM_CTRLSTS_SWRSTF_Msk (0x1U << CRM_CTRLSTS_SWRSTF_Pos) /*!< 0x10000000 */ +#define CRM_CTRLSTS_SWRSTF CRM_CTRLSTS_SWRSTF_Msk /*!< Software reset flag */ +#define CRM_CTRLSTS_WDTRSTF_Pos (29U) +#define CRM_CTRLSTS_WDTRSTF_Msk (0x1U << CRM_CTRLSTS_WDTRSTF_Pos) /*!< 0x20000000 */ +#define CRM_CTRLSTS_WDTRSTF CRM_CTRLSTS_WDTRSTF_Msk /*!< Watchdog timer reset flag */ +#define CRM_CTRLSTS_WWDTRSTF_Pos (30U) +#define CRM_CTRLSTS_WWDTRSTF_Msk (0x1U << CRM_CTRLSTS_WWDTRSTF_Pos) /*!< 0x40000000 */ +#define CRM_CTRLSTS_WWDTRSTF CRM_CTRLSTS_WWDTRSTF_Msk /*!< Window watchdog timer reset flag */ +#define CRM_CTRLSTS_LPRSTF_Pos (31U) +#define CRM_CTRLSTS_LPRSTF_Msk (0x1U << CRM_CTRLSTS_LPRSTF_Pos) /*!< 0x80000000 */ +#define CRM_CTRLSTS_LPRSTF CRM_CTRLSTS_LPRSTF_Msk /*!< Low-power reset flag */ + +/****************** Bit definition for CRM_OTGHS register *******************/ +#define CRM_OTGHS_USBHS_PHY12_SEL_Pos (4U) +#define CRM_OTGHS_USBHS_PHY12_SEL_Msk (0x1U << CRM_OTGHS_USBHS_PHY12_SEL_Pos) /*!< 0x00000010 */ +#define CRM_OTGHS_USBHS_PHY12_SEL CRM_OTGHS_USBHS_PHY12_SEL_Msk /*!< USBHS PHY 12M clock source select (F405 only) */ + +/****************** Bit definition for CRM_MISC1 register *******************/ +#define CRM_MISC1_HICKCAL_KEY_Pos (0U) +#define CRM_MISC1_HICKCAL_KEY_Msk (0xFFU << CRM_MISC1_HICKCAL_KEY_Pos) /*!< 0x000000FF */ +#define CRM_MISC1_HICKCAL_KEY CRM_MISC1_HICKCAL_KEY_Msk /*!< HICK calibration key */ +#define CRM_MISC1_HICKDIV_Pos (12U) +#define CRM_MISC1_HICKDIV_Msk (0x1U << CRM_MISC1_HICKDIV_Pos) /*!< 0x00001000 */ +#define CRM_MISC1_HICKDIV CRM_MISC1_HICKDIV_Msk /*!< HICK 6 divider selection */ +#define CRM_MISC1_HICK_TO_SCLK_Pos (14U) +#define CRM_MISC1_HICK_TO_SCLK_Msk (0x1U << CRM_MISC1_HICK_TO_SCLK_Pos) /*!< 0x00004000 */ +#define CRM_MISC1_HICK_TO_SCLK CRM_MISC1_HICK_TO_SCLK_Msk /*!< HICK as system clock frequency select */ +#define CRM_MISC1_HICKRST_Pos (15U) +#define CRM_MISC1_HICKRST_Msk (0x1U << CRM_MISC1_HICKRST_Pos) /*!< 0x00008000 */ +#define CRM_MISC1_HICKRST CRM_MISC1_HICKRST_Msk /*!< HICKRST */ + +/*!< CLKOUT_SEL2 congiguration */ +#define CRM_MISC1_CLKOUT_SEL2_Pos (16U) +#define CRM_MISC1_CLKOUT_SEL2_Msk (0xFU << CRM_MISC1_CLKOUT_SEL2_Pos) /*!< 0x000F0000 */ +#define CRM_MISC1_CLKOUT_SEL2 CRM_MISC1_CLKOUT_SEL2_Msk /*!< CLKOUT_SEL2[3:0] bits (Clock output selection 2) */ +#define CRM_MISC1_CLKOUT_SEL2_0 (0x1U << CRM_MISC1_CLKOUT_SEL2_Pos) /*!< 0x00010000 */ +#define CRM_MISC1_CLKOUT_SEL2_1 (0x2U << CRM_MISC1_CLKOUT_SEL2_Pos) /*!< 0x00020000 */ +#define CRM_MISC1_CLKOUT_SEL2_2 (0x4U << CRM_MISC1_CLKOUT_SEL2_Pos) /*!< 0x00040000 */ +#define CRM_MISC1_CLKOUT_SEL2_3 (0x8U << CRM_MISC1_CLKOUT_SEL2_Pos) /*!< 0x00080000 */ + +#define CRM_MISC1_CLKOUT_SEL2_USBFS 0x00000000U /*!< USBFS 48M */ +#define CRM_MISC1_CLKOUT_SEL2_ADC 0x00010000U /*!< ADC */ +#define CRM_MISC1_CLKOUT_SEL2_HICK 0x00020000U /*!< HICK */ +#define CRM_MISC1_CLKOUT_SEL2_LICK 0x00030000U /*!< LICK */ +#define CRM_MISC1_CLKOUT_SEL2_LEXT 0x00040000U /*!< LEXT */ + +/* Reference defines */ +#define CRM_MISC1_CLKSEL2 CRM_MISC1_CLKOUT_SEL2 +#define CRM_MISC1_CLKSEL2_0 CRM_MISC1_CLKOUT_SEL2_0 +#define CRM_MISC1_CLKSEL2_1 CRM_MISC1_CLKOUT_SEL2_1 +#define CRM_MISC1_CLKSEL2_2 CRM_MISC1_CLKOUT_SEL2_2 +#define CRM_MISC1_CLKSEL2_3 CRM_MISC1_CLKOUT_SEL2_3 +#define CRM_MISC1_CLKSEL2_USBFS CRM_MISC1_CLKOUT_SEL2_USBFS +#define CRM_MISC1_CLKSEL2_ADC CRM_MISC1_CLKOUT_SEL2_ADC +#define CRM_MISC1_CLKSEL2_HICK CRM_MISC1_CLKOUT_SEL2_HICK +#define CRM_MISC1_CLKSEL2_LICK CRM_MISC1_CLKOUT_SEL2_LICK +#define CRM_MISC1_CLKSEL2_LEXT CRM_MISC1_CLKOUT_SEL2_LEXT + +/*!< CLKOUTDIV2 congiguration */ +#define CRM_MISC1_CLKOUTDIV2_Pos (28U) +#define CRM_MISC1_CLKOUTDIV2_Msk (0xFU << CRM_MISC1_CLKOUTDIV2_Pos) /*!< 0xF0000000 */ +#define CRM_MISC1_CLKOUTDIV2 CRM_MISC1_CLKOUTDIV2_Msk /*!< CLKOUTDIV2[3:0] bits (Clock output division 2) */ +#define CRM_MISC1_CLKOUTDIV2_0 (0x1U << CRM_MISC1_CLKOUTDIV2_Pos) /*!< 0x10000000 */ +#define CRM_MISC1_CLKOUTDIV2_1 (0x2U << CRM_MISC1_CLKOUTDIV2_Pos) /*!< 0x20000000 */ +#define CRM_MISC1_CLKOUTDIV2_2 (0x4U << CRM_MISC1_CLKOUTDIV2_Pos) /*!< 0x40000000 */ +#define CRM_MISC1_CLKOUTDIV2_3 (0x8U << CRM_MISC1_CLKOUTDIV2_Pos) /*!< 0x80000000 */ + +#define CRM_MISC1_CLKOUTDIV2_DIV1 0x00000000U /*!< No clock output */ +#define CRM_MISC1_CLKOUTDIV2_DIV2 0x80000000U /*!< Clock output divided by 2 */ +#define CRM_MISC1_CLKOUTDIV2_DIV4 0x90000000U /*!< Clock output divided by 4 */ +#define CRM_MISC1_CLKOUTDIV2_DIV8 0xA0000000U /*!< Clock output divided by 8 */ +#define CRM_MISC1_CLKOUTDIV2_DIV16 0xB0000000U /*!< Clock output divided by 16 */ +#define CRM_MISC1_CLKOUTDIV2_DIV64 0xC0000000U /*!< Clock output divided by 64 */ +#define CRM_MISC1_CLKOUTDIV2_DIV128 0xD0000000U /*!< Clock output divided by 128 */ +#define CRM_MISC1_CLKOUTDIV2_DIV256 0xE0000000U /*!< Clock output divided by 256 */ +#define CRM_MISC1_CLKOUTDIV2_DIV512 0xF0000000U /*!< Clock output divided by 512 */ + +/****************** Bit definition for CRM_MISC2 register *******************/ +/*!< AUTO_STEP_EN congiguration */ +#define CRM_MISC2_AUTO_STEP_EN_Pos (4U) +#define CRM_MISC2_AUTO_STEP_EN_Msk (0x3U << CRM_MISC2_AUTO_STEP_EN_Pos) /*!< 0x00000030 */ +#define CRM_MISC2_AUTO_STEP_EN CRM_MISC2_AUTO_STEP_EN_Msk /*!< AUTO_STEP_EN[1:0] bits (Auto step-by-step SCLK switch enable) */ +#define CRM_MISC2_AUTO_STEP_EN_0 (0x1U << CRM_MISC2_AUTO_STEP_EN_Pos) /*!< 0x00000010 */ +#define CRM_MISC2_AUTO_STEP_EN_1 (0x2U << CRM_MISC2_AUTO_STEP_EN_Pos) /*!< 0x00000020 */ + +#define CRM_MISC2_PLLU_USB48_SEL_Pos (10U) +#define CRM_MISC2_PLLU_USB48_SEL_Msk (0x1U << CRM_MISC2_PLLU_USB48_SEL_Pos) /*!< 0x00000400 */ +#define CRM_MISC2_PLLU_USB48_SEL CRM_MISC2_PLLU_USB48_SEL_Msk /*!< USBFS 48M clock source selection */ + +/*!< HICK_TO_SCLK_DIV congiguration */ +#define CRM_MISC2_HICK_TO_SCLK_DIV_Pos (16U) +#define CRM_MISC2_HICK_TO_SCLK_DIV_Msk (0x7U << CRM_MISC2_HICK_TO_SCLK_DIV_Pos) /*!< 0x00070000 */ +#define CRM_MISC2_HICK_TO_SCLK_DIV CRM_MISC2_HICK_TO_SCLK_DIV_Msk /*!< HICK_TO_SCLK_DIV[2:0] bits (HICK as SCLK frequency division) */ +#define CRM_MISC2_HICK_TO_SCLK_DIV_0 (0x1U << CRM_MISC2_HICK_TO_SCLK_DIV_Pos) /*!< 0x00010000 */ +#define CRM_MISC2_HICK_TO_SCLK_DIV_1 (0x2U << CRM_MISC2_HICK_TO_SCLK_DIV_Pos) /*!< 0x00020000 */ +#define CRM_MISC2_HICK_TO_SCLK_DIV_2 (0x4U << CRM_MISC2_HICK_TO_SCLK_DIV_Pos) /*!< 0x00040000 */ + +#define CRM_MISC2_HICK_TO_SCLK_DIV_DIV1 0x00000000U /*!< HICK */ +#define CRM_MISC2_HICK_TO_SCLK_DIV_DIV2 0x00010000U /*!< HICK/2 */ +#define CRM_MISC2_HICK_TO_SCLK_DIV_DIV4 0x00020000U /*!< HICK/4 */ +#define CRM_MISC2_HICK_TO_SCLK_DIV_DIV8 0x00030000U /*!< HICK/8 */ +#define CRM_MISC2_HICK_TO_SCLK_DIV_DIV16 0x00040000U /*!< HICK/16 */ + +/*!< HEXT_TO_SCLK_DIV congiguration */ +#define CRM_MISC2_HEXT_TO_SCLK_DIV_Pos (19U) +#define CRM_MISC2_HEXT_TO_SCLK_DIV_Msk (0x7U << CRM_MISC2_HEXT_TO_SCLK_DIV_Pos) /*!< 0x00380000 */ +#define CRM_MISC2_HEXT_TO_SCLK_DIV CRM_MISC2_HEXT_TO_SCLK_DIV_Msk /*!< HEXT_TO_SCLK_DIV[2:0] bits (HEXT as SCLK frequency division) */ +#define CRM_MISC2_HEXT_TO_SCLK_DIV_0 (0x1U << CRM_MISC2_HEXT_TO_SCLK_DIV_Pos) /*!< 0x00080000 */ +#define CRM_MISC2_HEXT_TO_SCLK_DIV_1 (0x2U << CRM_MISC2_HEXT_TO_SCLK_DIV_Pos) /*!< 0x00100000 */ +#define CRM_MISC2_HEXT_TO_SCLK_DIV_2 (0x4U << CRM_MISC2_HEXT_TO_SCLK_DIV_Pos) /*!< 0x00200000 */ + +#define CRM_MISC2_HEXT_TO_SCLK_DIV_DIV1 0x00000000U /*!< HEXT */ +#define CRM_MISC2_HEXT_TO_SCLK_DIV_DIV2 0x00080000U /*!< HEXT/2 */ +#define CRM_MISC2_HEXT_TO_SCLK_DIV_DIV4 0x00100000U /*!< HEXT/4 */ +#define CRM_MISC2_HEXT_TO_SCLK_DIV_DIV8 0x00180000U /*!< HEXT/8 */ +#define CRM_MISC2_HEXT_TO_SCLK_DIV_DIV16 0x00200000U /*!< HEXT/16 */ +#define CRM_MISC2_HEXT_TO_SCLK_DIV_DIV32 0x00280000U /*!< HEXT/32 */ + +/******************************************************************************/ +/* */ +/* Flash and User System Data Registers (FLASH) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for FLASH_PSR register ******************/ +/*!< WTCYC congiguration */ +#define FLASH_PSR_WTCYC_Pos (0U) +#define FLASH_PSR_WTCYC_Msk (0x7U << FLASH_PSR_WTCYC_Pos) /*!< 0x00000007 */ +#define FLASH_PSR_WTCYC FLASH_PSR_WTCYC_Msk /*!< WTCYC[2:0] bits (Wait cycle) */ +#define FLASH_PSR_WTCYC_0 (0x1U << FLASH_PSR_WTCYC_Pos) /*!< 0x00000001 */ +#define FLASH_PSR_WTCYC_1 (0x2U << FLASH_PSR_WTCYC_Pos) /*!< 0x00000002 */ +#define FLASH_PSR_WTCYC_2 (0x4U << FLASH_PSR_WTCYC_Pos) /*!< 0x00000004 */ + +#define FLASH_PSR_PFT_EN_Pos (4U) +#define FLASH_PSR_PFT_EN_Msk (0x1U << FLASH_PSR_PFT_EN_Pos) /*!< 0x00000010 */ +#define FLASH_PSR_PFT_EN FLASH_PSR_PFT_EN_Msk /*!< Prefetch enable */ +#define FLASH_PSR_PFT_ENF_Pos (5U) +#define FLASH_PSR_PFT_ENF_Msk (0x1U << FLASH_PSR_PFT_ENF_Pos) /*!< 0x00000020 */ +#define FLASH_PSR_PFT_ENF FLASH_PSR_PFT_ENF_Msk /*!< Prefetch enable flag */ +#define FLASH_PSR_PFT_EN2_Pos (6U) +#define FLASH_PSR_PFT_EN2_Msk (0x1U << FLASH_PSR_PFT_EN2_Pos) /*!< 0x00000040 */ +#define FLASH_PSR_PFT_EN2 FLASH_PSR_PFT_EN2_Msk /*!< Prefetch enable 2 */ +#define FLASH_PSR_PFT_ENF2_Pos (7U) +#define FLASH_PSR_PFT_ENF2_Msk (0x1U << FLASH_PSR_PFT_ENF2_Pos) /*!< 0x00000080 */ +#define FLASH_PSR_PFT_ENF2 FLASH_PSR_PFT_ENF2_Msk /*!< Prefetch enable flag 2 */ +#define FLASH_PSR_PFT_LAT_DIS_Pos (8U) +#define FLASH_PSR_PFT_LAT_DIS_Msk (0x1U << FLASH_PSR_PFT_LAT_DIS_Pos) /*!< 0x00000100 */ +#define FLASH_PSR_PFT_LAT_DIS FLASH_PSR_PFT_LAT_DIS_Msk /*!< Prefetch latency disable */ + +/***************** Bit definition for FLASH_UNLOCK register *****************/ +#define FLASH_UNLOCK_UKVAL_Pos (0U) +#define FLASH_UNLOCK_UKVAL_Msk (0xFFFFFFFFU << FLASH_UNLOCK_UKVAL_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_UNLOCK_UKVAL FLASH_UNLOCK_UKVAL_Msk /*!< Unlock key value */ + +#define FAP_KEY_Pos (0U) +#define FAP_KEY_Msk (0xA5U << FAP_KEY_Pos) /*!< 0x000000A5 */ +#define FAP_KEY FAP_KEY_Msk /*!< Flash access protection key */ +#define FLASH_KEY1_Pos (0U) +#define FLASH_KEY1_Msk (0x45670123U << FLASH_KEY1_Pos) /*!< 0x45670123 */ +#define FLASH_KEY1 FLASH_KEY1_Msk /*!< Flash key 1 */ +#define FLASH_KEY2_Pos (0U) +#define FLASH_KEY2_Msk (0xCDEF89ABU << FLASH_KEY2_Pos) /*!< 0xCDEF89AB */ +#define FLASH_KEY2 FLASH_KEY2_Msk /*!< Flash key 2 */ + +/*************** Bit definition for FLASH_USD_UNLOCK register ***************/ +#define FLASH_USD_UNLOCK_USD_UKVAL_Pos (0U) /*!< 0xFFFFFFFF */ +#define FLASH_USD_UNLOCK_USD_UKVAL_Msk (0xFFFFFFFFU << FLASH_USD_UNLOCK_USD_UKVAL_Pos) +#define FLASH_USD_UNLOCK_USD_UKVAL FLASH_USD_UNLOCK_USD_UKVAL_Msk /*!< User system data unlock key value */ + +#define FLASH_USDKEY1 FLASH_KEY1 /*!< User system data key 1 */ +#define FLASH_USDKEY2 FLASH_KEY2 /*!< User system data key 2 */ + +/****************** Bit definition for FLASH_STS register *******************/ +#define FLASH_STS_OBF_Pos (0U) +#define FLASH_STS_OBF_Msk (0x1U << FLASH_STS_OBF_Pos) /*!< 0x00000001 */ +#define FLASH_STS_OBF FLASH_STS_OBF_Msk /*!< Operation busy flag */ +#define FLASH_STS_PRGMERR_Pos (2U) +#define FLASH_STS_PRGMERR_Msk (0x1U << FLASH_STS_PRGMERR_Pos) /*!< 0x00000004 */ +#define FLASH_STS_PRGMERR FLASH_STS_PRGMERR_Msk /*!< Programming error */ +#define FLASH_STS_EPPERR_Pos (4U) +#define FLASH_STS_EPPERR_Msk (0x1U << FLASH_STS_EPPERR_Pos) /*!< 0x00000010 */ +#define FLASH_STS_EPPERR FLASH_STS_EPPERR_Msk /*!< Erase/program protection error */ +#define FLASH_STS_ODF_Pos (5U) +#define FLASH_STS_ODF_Msk (0x1U << FLASH_STS_ODF_Pos) /*!< 0x00000020 */ +#define FLASH_STS_ODF FLASH_STS_ODF_Msk /*!< Operation done flag */ + +/****************** Bit definition for FLASH_CTRL register ******************/ +#define FLASH_CTRL_FPRGM_Pos (0U) +#define FLASH_CTRL_FPRGM_Msk (0x1U << FLASH_CTRL_FPRGM_Pos) /*!< 0x00000001 */ +#define FLASH_CTRL_FPRGM FLASH_CTRL_FPRGM_Msk /*!< Flash program */ +#define FLASH_CTRL_SECERS_Pos (1U) +#define FLASH_CTRL_SECERS_Msk (0x1U << FLASH_CTRL_SECERS_Pos) /*!< 0x00000002 */ +#define FLASH_CTRL_SECERS FLASH_CTRL_SECERS_Msk /*!< Page erase */ +#define FLASH_CTRL_BANKERS_Pos (2U) +#define FLASH_CTRL_BANKERS_Msk (0x1U << FLASH_CTRL_BANKERS_Pos) /*!< 0x00000004 */ +#define FLASH_CTRL_BANKERS FLASH_CTRL_BANKERS_Msk /*!< Bank erase */ +#define FLASH_CTRL_USDPRGM_Pos (4U) +#define FLASH_CTRL_USDPRGM_Msk (0x1U << FLASH_CTRL_USDPRGM_Pos) /*!< 0x00000010 */ +#define FLASH_CTRL_USDPRGM FLASH_CTRL_USDPRGM_Msk /*!< User system data program */ +#define FLASH_CTRL_USDERS_Pos (5U) +#define FLASH_CTRL_USDERS_Msk (0x1U << FLASH_CTRL_USDERS_Pos) /*!< 0x00000020 */ +#define FLASH_CTRL_USDERS FLASH_CTRL_USDERS_Msk /*!< User system data erase */ +#define FLASH_CTRL_ERSTR_Pos (6U) +#define FLASH_CTRL_ERSTR_Msk (0x1U << FLASH_CTRL_ERSTR_Pos) /*!< 0x00000040 */ +#define FLASH_CTRL_ERSTR FLASH_CTRL_ERSTR_Msk /*!< Erase start */ +#define FLASH_CTRL_OPLK_Pos (7U) +#define FLASH_CTRL_OPLK_Msk (0x1U << FLASH_CTRL_OPLK_Pos) /*!< 0x00000080 */ +#define FLASH_CTRL_OPLK FLASH_CTRL_OPLK_Msk /*!< Operation lock */ +#define FLASH_CTRL_USDULKS_Pos (9U) +#define FLASH_CTRL_USDULKS_Msk (0x1U << FLASH_CTRL_USDULKS_Pos) /*!< 0x00000200 */ +#define FLASH_CTRL_USDULKS FLASH_CTRL_USDULKS_Msk /*!< User system data unlock success */ +#define FLASH_CTRL_ERRIE_Pos (10U) +#define FLASH_CTRL_ERRIE_Msk (0x1U << FLASH_CTRL_ERRIE_Pos) /*!< 0x00000400 */ +#define FLASH_CTRL_ERRIE FLASH_CTRL_ERRIE_Msk /*!< Error interrupt enable */ +#define FLASH_CTRL_ODFIE_Pos (12U) +#define FLASH_CTRL_ODFIE_Msk (0x1U << FLASH_CTRL_ODFIE_Pos) /*!< 0x00001000 */ +#define FLASH_CTRL_ODFIE FLASH_CTRL_ODFIE_Msk /*!< Operation done flag interrupt enable */ + +/****************** Bit definition for FLASH_ADDR register ******************/ +#define FLASH_ADDR_FA_Pos (0U) +#define FLASH_ADDR_FA_Msk (0xFFFFFFFFU << FLASH_ADDR_FA_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_ADDR_FA FLASH_ADDR_FA_Msk /*!< Flash address */ + +/****************** Bit definition for FLASH_USD register *******************/ +#define FLASH_USD_USDERR_Pos (0U) +#define FLASH_USD_USDERR_Msk (0x1U << FLASH_USD_USDERR_Pos) /*!< 0x00000001 */ +#define FLASH_USD_USDERR FLASH_USD_USDERR_Msk /*!< User system data error */ +#define FLASH_USD_FAP_Pos (1U) +#define FLASH_USD_FAP_Msk (0x1U << FLASH_USD_FAP_Pos) /*!< 0x00000002 */ +#define FLASH_USD_FAP FLASH_USD_FAP_Msk /*!< Flash access protection */ + +/*!< SSB congiguration */ +#define FLASH_USD_WDT_ATO_EN_Pos (2U) +#define FLASH_USD_WDT_ATO_EN_Msk (0x1U << FLASH_USD_WDT_ATO_EN_Pos) /*!< 0x00000004 */ +#define FLASH_USD_WDT_ATO_EN FLASH_USD_WDT_ATO_EN_Msk /*!< nWDT_ATO_EN */ +#define FLASH_USD_DEPSLP_RST_Pos (3U) +#define FLASH_USD_DEPSLP_RST_Msk (0x1U << FLASH_USD_DEPSLP_RST_Pos) /*!< 0x00000008 */ +#define FLASH_USD_DEPSLP_RST FLASH_USD_DEPSLP_RST_Msk /*!< nDEPSLP_RST */ +#define FLASH_USD_STDBY_RST_Pos (4U) +#define FLASH_USD_STDBY_RST_Msk (0x1U << FLASH_USD_STDBY_RST_Pos) /*!< 0x00000010 */ +#define FLASH_USD_STDBY_RST FLASH_USD_STDBY_RST_Msk /*!< nSTDBY_RST */ +#define FLASH_USD_BOOT1_Pos (6U) +#define FLASH_USD_BOOT1_Msk (0x1U << FLASH_USD_BOOT1_Pos) /*!< 0x00000040 */ +#define FLASH_USD_BOOT1 FLASH_USD_BOOT1_Msk /*!< nBOOT1 */ +#define FLASH_USD_DEPSLP_WDT_Pos (7U) +#define FLASH_USD_DEPSLP_WDT_Msk (0x1U << FLASH_USD_DEPSLP_WDT_Pos) /*!< 0x00000080 */ +#define FLASH_USD_DEPSLP_WDT FLASH_USD_DEPSLP_WDT_Msk /*!< nDEPSLP_WDT */ +#define FLASH_USD_STDBY_WDT_Pos (8U) +#define FLASH_USD_STDBY_WDT_Msk (0x1U << FLASH_USD_STDBY_WDT_Pos) /*!< 0x00000100 */ +#define FLASH_USD_STDBY_WDT FLASH_USD_STDBY_WDT_Msk /*!< nSTDBY_WDT */ +#define FLASH_USD_RAM_PRT_CHK_Pos (9U) +#define FLASH_USD_RAM_PRT_CHK_Msk (0x1U << FLASH_USD_RAM_PRT_CHK_Pos) /*!< 0x00000200 */ +#define FLASH_USD_RAM_PRT_CHK FLASH_USD_RAM_PRT_CHK_Msk /*!< nRAM_PRT_CHK */ +#define FLASH_USD_SSB_Pos (2U) +#define FLASH_USD_SSB_Msk (0xFFU << FLASH_USD_SSB_Pos) /*!< 0x000003FC */ +#define FLASH_USD_SSB FLASH_USD_SSB_Msk /*!< System setting byte */ + +#define FLASH_USD_USER_D0_Pos (10U) +#define FLASH_USD_USER_D0_Msk (0xFFU << FLASH_USD_USER_D0_Pos) /*!< 0x0003FC00 */ +#define FLASH_USD_USER_D0 FLASH_USD_USER_D0_Msk /*!< User data 0 */ +#define FLASH_USD_USER_D1_Pos (18U) +#define FLASH_USD_USER_D1_Msk (0xFFU << FLASH_USD_USER_D1_Pos) /*!< 0x03FC0000 */ +#define FLASH_USD_USER_D1 FLASH_USD_USER_D1_Msk /*!< User data 1 */ +#define FLASH_USD_FAP_HL_Pos (26U) +#define FLASH_USD_FAP_HL_Msk (0x1U << FLASH_USD_FAP_HL_Pos) /*!< 0x04000000 */ +#define FLASH_USD_FAP_HL FLASH_USD_FAP_HL_Msk /*!< Flash access protection high level */ + +/****************** Bit definition for FLASH_EPPS register ******************/ +#define FLASH_EPPS_EPPS_Pos (0U) +#define FLASH_EPPS_EPPS_Msk (0xFFFFFFFFU << FLASH_EPPS_EPPS_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_EPPS_EPPS FLASH_EPPS_EPPS_Msk /*!< Erase/Program protection status */ + +/******************* Bit definition for SLIB_STS0 register *******************/ +#define SLIB_STS0_BTM_AP_ENF_Pos (0U) +#define SLIB_STS0_BTM_AP_ENF_Msk (0x1U << SLIB_STS0_BTM_AP_ENF_Pos) /*!< 0x00000001 */ +#define SLIB_STS0_BTM_AP_ENF SLIB_STS0_BTM_AP_ENF_Msk /*!< Boot memory store application code enabled flag */ +#define SLIB_STS0_EM_SLIB_ENF_Pos (2U) +#define SLIB_STS0_EM_SLIB_ENF_Msk (0x1U << SLIB_STS0_EM_SLIB_ENF_Pos) /*!< 0x00000004 */ +#define SLIB_STS0_EM_SLIB_ENF SLIB_STS0_EM_SLIB_ENF_Msk /*!< Extension memory sLib enable flag */ +#define SLIB_STS0_SLIB_ENF_Pos (3U) +#define SLIB_STS0_SLIB_ENF_Msk (0x1U << SLIB_STS0_SLIB_ENF_Pos) /*!< 0x00000008 */ +#define SLIB_STS0_SLIB_ENF SLIB_STS0_SLIB_ENF_Msk /*!< Security library enable flag */ +#define SLIB_STS0_EM_SLIB_INST_SS_Pos (16U) /*!< 0x00FF0000 */ +#define SLIB_STS0_EM_SLIB_INST_SS_Msk (0xFFU << SLIB_STS0_EM_SLIB_INST_SS_Pos) +#define SLIB_STS0_EM_SLIB_INST_SS SLIB_STS0_EM_SLIB_INST_SS_Msk /*!< Extension memory sLib instruction start page */ + +/******************* Bit definition for SLIB_STS1 register *******************/ +#define SLIB_STS1_SLIB_SS_Pos (0U) +#define SLIB_STS1_SLIB_SS_Msk (0x7FFU << SLIB_STS1_SLIB_SS_Pos) /*!< 0x000007FF */ +#define SLIB_STS1_SLIB_SS SLIB_STS1_SLIB_SS_Msk /*!< Security library start page */ +#define SLIB_STS1_SLIB_INST_SS_Pos (11U) +#define SLIB_STS1_SLIB_INST_SS_Msk (0x7FFU << SLIB_STS1_SLIB_INST_SS_Pos) /*!< 0x003FF800 */ +#define SLIB_STS1_SLIB_INST_SS SLIB_STS1_SLIB_INST_SS_Msk /*!< Security library instruction start page */ +#define SLIB_STS1_SLIB_ES_Pos (22U) +#define SLIB_STS1_SLIB_ES_Msk (0x3FFU << SLIB_STS1_SLIB_ES_Pos) /*!< 0xFFC00000 */ +#define SLIB_STS1_SLIB_ES SLIB_STS1_SLIB_ES_Msk /*!< Security library end page */ + +/***************** Bit definition for SLIB_PWD_CLR register ******************/ +#define SLIB_PWD_CLR_SLIB_PCLR_VAL_Pos (0U) /*!< 0xFFFFFFFF */ +#define SLIB_PWD_CLR_SLIB_PCLR_VAL_Msk (0xFFFFFFFFU << SLIB_PWD_CLR_SLIB_PCLR_VAL_Pos) +#define SLIB_PWD_CLR_SLIB_PCLR_VAL SLIB_PWD_CLR_SLIB_PCLR_VAL_Msk /*!< Security library password clear value */ + +/***************** Bit definition for SLIB_MISC_STS register *****************/ +#define SLIB_MISC_STS_SLIB_PWD_ERR_Pos (0U) /*!< 0x00000001 */ +#define SLIB_MISC_STS_SLIB_PWD_ERR_Msk (0x1U << SLIB_MISC_STS_SLIB_PWD_ERR_Pos) +#define SLIB_MISC_STS_SLIB_PWD_ERR SLIB_MISC_STS_SLIB_PWD_ERR_Msk /*!< Security library password error */ +#define SLIB_MISC_STS_SLIB_PWD_OK_Pos (1U) +#define SLIB_MISC_STS_SLIB_PWD_OK_Msk (0x1U << SLIB_MISC_STS_SLIB_PWD_OK_Pos) /*!< 0x00000002 */ +#define SLIB_MISC_STS_SLIB_PWD_OK SLIB_MISC_STS_SLIB_PWD_OK_Msk /*!< Security library password ok */ +#define SLIB_MISC_STS_SLIB_ULKF_Pos (2U) +#define SLIB_MISC_STS_SLIB_ULKF_Msk (0x1U << SLIB_MISC_STS_SLIB_ULKF_Pos) /*!< 0x00000004 */ +#define SLIB_MISC_STS_SLIB_ULKF SLIB_MISC_STS_SLIB_ULKF_Msk /*!< Security library unlock flag */ + +/**************** Bit definition for FLASH_CRC_ADDR register *****************/ +#define FLASH_CRC_ADDR_CRC_ADDR_Pos (0U) /*!< 0xFFFFFFFF */ +#define FLASH_CRC_ADDR_CRC_ADDR_Msk (0xFFFFFFFFU << FLASH_CRC_ADDR_CRC_ADDR_Pos) +#define FLASH_CRC_ADDR_CRC_ADDR FLASH_CRC_ADDR_CRC_ADDR_Msk /*!< CRC address */ + +/**************** Bit definition for FLASH_CRC_CTRL register *****************/ +#define FLASH_CRC_CTRL_CRC_SN_Pos (0U) +#define FLASH_CRC_CTRL_CRC_SN_Msk (0xFFFFU << FLASH_CRC_CTRL_CRC_SN_Pos) /*!< 0x0000FFFF */ +#define FLASH_CRC_CTRL_CRC_SN FLASH_CRC_CTRL_CRC_SN_Msk /*!< CRC page number */ +#define FLASH_CRC_CTRL_CRC_STRT_Pos (16U) +#define FLASH_CRC_CTRL_CRC_STRT_Msk (0x1U << FLASH_CRC_CTRL_CRC_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_CRC_CTRL_CRC_STRT FLASH_CRC_CTRL_CRC_STRT_Msk /*!< CRC start */ + +/**************** Bit definition for FLASH_CRC_CHKR register *****************/ +#define FLASH_CRC_CHKR_CRC_CHKR_Pos (0U) /*!< 0xFFFFFFFF */ +#define FLASH_CRC_CHKR_CRC_CHKR_Msk (0xFFFFFFFFU << FLASH_CRC_CHKR_CRC_CHKR_Pos) +#define FLASH_CRC_CHKR_CRC_CHKR FLASH_CRC_CHKR_CRC_CHKR_Msk /*!< CRC check result */ + +/***************** Bit definition for SLIB_SET_PWD register ******************/ +#define SLIB_SET_PWD_SLIB_PSET_VAL_Pos (0U) /*!< 0xFFFFFFFF */ +#define SLIB_SET_PWD_SLIB_PSET_VAL_Msk (0xFFFFFFFFU << SLIB_SET_PWD_SLIB_PSET_VAL_Pos) +#define SLIB_SET_PWD_SLIB_PSET_VAL SLIB_SET_PWD_SLIB_PSET_VAL_Msk /*!< Security library password setting value */ + +/**************** Bit definition for SLIB_SET_RANGE register *****************/ +#define SLIB_SET_RANGE_SLIB_SS_SET_Pos (0U) /*!< 0x000007FF */ +#define SLIB_SET_RANGE_SLIB_SS_SET_Msk (0x7FFU << SLIB_SET_RANGE_SLIB_SS_SET_Pos) +#define SLIB_SET_RANGE_SLIB_SS_SET SLIB_SET_RANGE_SLIB_SS_SET_Msk /*!< Security library start page setting */ +#define SLIB_SET_RANGE_SLIB_ISS_SET_Pos (11U) /*!< 0x003FF800 */ +#define SLIB_SET_RANGE_SLIB_ISS_SET_Msk (0x7FFU << SLIB_SET_RANGE_SLIB_ISS_SET_Pos) +#define SLIB_SET_RANGE_SLIB_ISS_SET SLIB_SET_RANGE_SLIB_ISS_SET_Msk /*!< Security library instruction start page setting */ +#define SLIB_SET_RANGE_SLIB_ES_SET_Pos (22U) /*!< 0xFFC00000 */ +#define SLIB_SET_RANGE_SLIB_ES_SET_Msk (0x3FFU << SLIB_SET_RANGE_SLIB_ES_SET_Pos) +#define SLIB_SET_RANGE_SLIB_ES_SET SLIB_SET_RANGE_SLIB_ES_SET_Msk /*!< Security library end page setting */ + +/****************** Bit definition for EM_SLIB_SET register ******************/ +#define EM_SLIB_SET_EM_SLIB_SET_Pos (0U) /*!< 0x0000FFFF */ +#define EM_SLIB_SET_EM_SLIB_SET_Msk (0xFFFFU << EM_SLIB_SET_EM_SLIB_SET_Pos) +#define EM_SLIB_SET_EM_SLIB_SET EM_SLIB_SET_EM_SLIB_SET_Msk /*!< Extension memory sLib setting */ +#define EM_SLIB_SET_EM_SLIB_ISS_SET_Pos (16U) /*!< 0x00FF0000 */ +#define EM_SLIB_SET_EM_SLIB_ISS_SET_Msk (0xFFU << EM_SLIB_SET_EM_SLIB_ISS_SET_Pos) +#define EM_SLIB_SET_EM_SLIB_ISS_SET EM_SLIB_SET_EM_SLIB_ISS_SET_Msk /*!< Extension memory sLib instruction start page setting */ + +/***************** Bit definition for BTM_MODE_SET register ******************/ +#define BTM_MODE_SET_BTM_MODE_SET_Pos (0U) /*!< 0x000000FF */ +#define BTM_MODE_SET_BTM_MODE_SET_Msk (0xFFU << BTM_MODE_SET_BTM_MODE_SET_Pos) +#define BTM_MODE_SET_BTM_MODE_SET BTM_MODE_SET_BTM_MODE_SET_Msk /*!< Boot memory mode setting */ + +/***************** Bit definition for SLIB_UNLOCK register ******************/ +#define SLIB_UNLOCK_SLIB_UKVAL_Pos (0U) /*!< 0xFFFFFFFF */ +#define SLIB_UNLOCK_SLIB_UKVAL_Msk (0xFFFFFFFFU << SLIB_UNLOCK_SLIB_UKVAL_Pos) +#define SLIB_UNLOCK_SLIB_UKVAL SLIB_UNLOCK_SLIB_UKVAL_Msk /*!< Security library unlock key value */ + +#define SLIB_KEY_Pos (0U) +#define SLIB_KEY_Msk (0xA35F6D24U << SLIB_KEY_Pos) /*!< 0xA35F6D24 */ +#define SLIB_KEY SLIB_KEY_Msk /*!< Security library key */ + +/*----------------------------------------------------------------------------*/ + +/****************** Bit definition for FLASH_FAP register *******************/ +#define FLASH_FAP_FAP_Pos (0U) +#define FLASH_FAP_FAP_Msk (0xFFU << FLASH_FAP_FAP_Pos) /*!< 0x000000FF */ +#define FLASH_FAP_FAP FLASH_FAP_FAP_Msk /*!< Flash memory access protection */ +#define FLASH_FAP_nFAP_Pos (8U) +#define FLASH_FAP_nFAP_Msk (0xFFU << FLASH_FAP_nFAP_Pos) /*!< 0x0000FF00 */ +#define FLASH_FAP_nFAP FLASH_FAP_nFAP_Msk /*!< Inverse code of flash memory access protection */ + +/****************** Bit definition for FLASH_SSB register *******************/ +#define FLASH_SSB_SSB_Pos (16U) +#define FLASH_SSB_SSB_Msk (0xFFU << FLASH_SSB_SSB_Pos) /*!< 0x00FF0000 */ +#define FLASH_SSB_SSB FLASH_SSB_SSB_Msk /*!< System configuration byte */ +#define FLASH_SSB_nSSB_Pos (24U) +#define FLASH_SSB_nSSB_Msk (0xFFU << FLASH_SSB_nSSB_Pos) /*!< 0xFF000000 */ +#define FLASH_SSB_nSSB FLASH_SSB_nSSB_Msk /*!< Inverse code of system configuration byte */ + +/***************** Bit definition for FLASH_DATA0 register ******************/ +#define FLASH_DATA0_DATA0_Pos (0U) +#define FLASH_DATA0_DATA0_Msk (0xFFU << FLASH_DATA0_DATA0_Pos) /*!< 0x000000FF */ +#define FLASH_DATA0_DATA0 FLASH_DATA0_DATA0_Msk /*!< User data 0 */ +#define FLASH_DATA0_nDATA0_Pos (8U) +#define FLASH_DATA0_nDATA0_Msk (0xFFU << FLASH_DATA0_nDATA0_Pos) /*!< 0x0000FF00 */ +#define FLASH_DATA0_nDATA0 FLASH_DATA0_nDATA0_Msk /*!< Inverse code of user data 0 */ + +/***************** Bit definition for FLASH_DATA1 register ******************/ +#define FLASH_DATA1_DATA1_Pos (16U) +#define FLASH_DATA1_DATA1_Msk (0xFFU << FLASH_DATA1_DATA1_Pos) /*!< 0x00FF0000 */ +#define FLASH_DATA1_DATA1 FLASH_DATA1_DATA1_Msk /*!< User data 1 */ +#define FLASH_DATA1_nDATA1_Pos (24U) +#define FLASH_DATA1_nDATA1_Msk (0xFFU << FLASH_DATA1_nDATA1_Pos) /*!< 0xFF000000 */ +#define FLASH_DATA1_nDATA1 FLASH_DATA1_nDATA1_Msk /*!< Inverse code of user data 1 */ + +/****************** Bit definition for FLASH_EPP0 register ******************/ +#define FLASH_EPP0_EPP0_Pos (0U) +#define FLASH_EPP0_EPP0_Msk (0xFFU << FLASH_EPP0_EPP0_Pos) /*!< 0x000000FF */ +#define FLASH_EPP0_EPP0 FLASH_EPP0_EPP0_Msk /*!< Flash erase/write protection byte 0 */ +#define FLASH_EPP0_nEPP0_Pos (8U) +#define FLASH_EPP0_nEPP0_Msk (0xFFU << FLASH_EPP0_nEPP0_Pos) /*!< 0x0000FF00 */ +#define FLASH_EPP0_nEPP0 FLASH_EPP0_nEPP0_Msk /*!< Inverse code of flash erase/write protection byte 0 */ + +/****************** Bit definition for FLASH_EPP1 register ******************/ +#define FLASH_EPP1_EPP1_Pos (16U) +#define FLASH_EPP1_EPP1_Msk (0xFFU << FLASH_EPP1_EPP1_Pos) /*!< 0x00FF0000 */ +#define FLASH_EPP1_EPP1 FLASH_EPP1_EPP1_Msk /*!< Flash erase/write protection byte 1 */ +#define FLASH_EPP1_nEPP1_Pos (24U) +#define FLASH_EPP1_nEPP1_Msk (0xFFU << FLASH_EPP1_nEPP1_Pos) /*!< 0xFF000000 */ +#define FLASH_EPP1_nEPP1 FLASH_EPP1_nEPP1_Msk /*!< Inverse code of flash erase/write protection byte 1 */ + +/****************** Bit definition for FLASH_EPP2 register ******************/ +#define FLASH_EPP2_EPP2_Pos (0U) +#define FLASH_EPP2_EPP2_Msk (0xFFU << FLASH_EPP2_EPP2_Pos) /*!< 0x000000FF */ +#define FLASH_EPP2_EPP2 FLASH_EPP2_EPP2_Msk /*!< Flash erase/write protection byte 2 */ +#define FLASH_EPP2_nEPP2_Pos (8U) +#define FLASH_EPP2_nEPP2_Msk (0xFFU << FLASH_EPP2_nEPP2_Pos) /*!< 0x0000FF00 */ +#define FLASH_EPP2_nEPP2 FLASH_EPP2_nEPP2_Msk /*!< Inverse code of flash erase/write protection byte 2 */ + +/****************** Bit definition for FLASH_EPP3 register ******************/ +#define FLASH_EPP3_EPP3_Pos (16U) +#define FLASH_EPP3_EPP3_Msk (0xFFU << FLASH_EPP3_EPP3_Pos) /*!< 0x00FF0000 */ +#define FLASH_EPP3_EPP3 FLASH_EPP3_EPP3_Msk /*!< Flash erase/write protection byte 3 */ +#define FLASH_EPP3_nEPP3_Pos (24U) +#define FLASH_EPP3_nEPP3_Msk (0xFFU << FLASH_EPP3_nEPP3_Pos) /*!< 0xFF000000 */ +#define FLASH_EPP3_nEPP3 FLASH_EPP3_nEPP3_Msk /*!< Inverse code of flash erase/write protection byte 3 */ + +/**************** Bit definition for FLASH_QSPIKEY0 register ****************/ +#define FLASH_QSPIKEY0_QSPIKEY0_Pos (0U) +#define FLASH_QSPIKEY0_QSPIKEY0_Msk (0xFFU << FLASH_QSPIKEY0_QSPIKEY0_Pos) /*!< 0x000000FF */ +#define FLASH_QSPIKEY0_QSPIKEY0 FLASH_QSPIKEY0_QSPIKEY0_Msk /*!< QSPI ciphertext access area encryption key byte 0 */ +#define FLASH_QSPIKEY0_nQSPIKEY0_Pos (8U) +#define FLASH_QSPIKEY0_nQSPIKEY0_Msk (0xFFU << FLASH_QSPIKEY0_nQSPIKEY0_Pos) /*!< 0x0000FF00 */ +#define FLASH_QSPIKEY0_nQSPIKEY0 FLASH_QSPIKEY0_nQSPIKEY0_Msk /*!< Inverse code of QSPI ciphertext access area encryption key byte 0 */ + +/**************** Bit definition for FLASH_QSPIKEY1 register ****************/ +#define FLASH_QSPIKEY1_QSPIKEY1_Pos (16U) +#define FLASH_QSPIKEY1_QSPIKEY1_Msk (0xFFU << FLASH_QSPIKEY1_QSPIKEY1_Pos) /*!< 0x00FF0000 */ +#define FLASH_QSPIKEY1_QSPIKEY1 FLASH_QSPIKEY1_QSPIKEY1_Msk /*!< QSPI ciphertext access area encryption key byte 1 */ +#define FLASH_QSPIKEY1_nQSPIKEY1_Pos (23U) +#define FLASH_QSPIKEY1_nQSPIKEY1_Msk (0xFFU << FLASH_QSPIKEY1_nQSPIKEY1_Pos) /*!< 0xFF000000 */ +#define FLASH_QSPIKEY1_nQSPIKEY1 FLASH_QSPIKEY1_nQSPIKEY1_Msk /*!< Inverse code of QSPI ciphertext access area encryption key byte 1 */ + +/**************** Bit definition for FLASH_QSPIKEY2 register ****************/ +#define FLASH_QSPIKEY2_QSPIKEY2_Pos (0U) +#define FLASH_QSPIKEY2_QSPIKEY2_Msk (0xFFU << FLASH_QSPIKEY2_QSPIKEY2_Pos) /*!< 0x000000FF */ +#define FLASH_QSPIKEY2_QSPIKEY2 FLASH_QSPIKEY2_QSPIKEY2_Msk /*!< QSPI ciphertext access area encryption key byte 2 */ +#define FLASH_QSPIKEY2_nQSPIKEY2_Pos (8U) +#define FLASH_QSPIKEY2_nQSPIKEY2_Msk (0xFFU << FLASH_QSPIKEY2_nQSPIKEY2_Pos) /*!< 0x0000FF00 */ +#define FLASH_QSPIKEY2_nQSPIKEY2 FLASH_QSPIKEY2_nQSPIKEY2_Msk /*!< Inverse code of QSPI ciphertext access area encryption key byte 2 */ + +/**************** Bit definition for FLASH_QSPIKEY3 register ****************/ +#define FLASH_QSPIKEY3_QSPIKEY3_Pos (16U) +#define FLASH_QSPIKEY3_QSPIKEY3_Msk (0xFFU << FLASH_QSPIKEY3_QSPIKEY3_Pos) /*!< 0x00FF0000 */ +#define FLASH_QSPIKEY3_QSPIKEY3 FLASH_QSPIKEY3_QSPIKEY3_Msk /*!< QSPI ciphertext access area encryption key byte 3 */ +#define FLASH_QSPIKEY3_nQSPIKEY3_Pos (23U) +#define FLASH_QSPIKEY3_nQSPIKEY3_Msk (0xFFU << FLASH_QSPIKEY3_nQSPIKEY3_Pos) /*!< 0xFF000000 */ +#define FLASH_QSPIKEY3_nQSPIKEY3 FLASH_QSPIKEY3_nQSPIKEY3_Msk /*!< Inverse code of QSPI ciphertext access area encryption key byte 3 */ + +/***************** Bit definition for FLASH_DATA2 register ******************/ +#define FLASH_DATA2_DATA2_Pos (0U) +#define FLASH_DATA2_DATA2_Msk (0xFFU << FLASH_DATA2_DATA2_Pos) /*!< 0x000000FF */ +#define FLASH_DATA2_DATA2 FLASH_DATA2_DATA2_Msk /*!< User data 2 */ +#define FLASH_DATA2_nDATA2_Pos (8U) +#define FLASH_DATA2_nDATA2_Msk (0xFFU << FLASH_DATA2_nDATA2_Pos) /*!< 0x0000FF00 */ +#define FLASH_DATA2_nDATA2 FLASH_DATA2_nDATA2_Msk /*!< Inverse code of user data 2 */ + +/***************** Bit definition for FLASH_DATA3 register ******************/ +#define FLASH_DATA3_DATA3_Pos (16U) +#define FLASH_DATA3_DATA3_Msk (0xFFU << FLASH_DATA3_DATA3_Pos) /*!< 0x00FF0000 */ +#define FLASH_DATA3_DATA3 FLASH_DATA3_DATA3_Msk /*!< User data 3 */ +#define FLASH_DATA3_nDATA3_Pos (24U) +#define FLASH_DATA3_nDATA3_Msk (0xFFU << FLASH_DATA3_nDATA3_Pos) /*!< 0xFF000000 */ +#define FLASH_DATA3_nDATA3 FLASH_DATA3_nDATA3_Msk /*!< Inverse code of user data 3 */ + +/***************** Bit definition for FLASH_DATA4 register ******************/ +#define FLASH_DATA4_DATA4_Pos (0U) +#define FLASH_DATA4_DATA4_Msk (0xFFU << FLASH_DATA4_DATA4_Pos) /*!< 0x000000FF */ +#define FLASH_DATA4_DATA4 FLASH_DATA4_DATA4_Msk /*!< User data 4 */ +#define FLASH_DATA4_nDATA4_Pos (8U) +#define FLASH_DATA4_nDATA4_Msk (0xFFU << FLASH_DATA4_nDATA4_Pos) /*!< 0x0000FF00 */ +#define FLASH_DATA4_nDATA4 FLASH_DATA4_nDATA4_Msk /*!< Inverse code of user data 4 */ + +/***************** Bit definition for FLASH_DATA5 register ******************/ +#define FLASH_DATA5_DATA5_Pos (16U) +#define FLASH_DATA5_DATA5_Msk (0xFFU << FLASH_DATA5_DATA5_Pos) /*!< 0x00FF0000 */ +#define FLASH_DATA5_DATA5 FLASH_DATA5_DATA5_Msk /*!< User data 5 */ +#define FLASH_DATA5_nDATA5_Pos (24U) +#define FLASH_DATA5_nDATA5_Msk (0xFFU << FLASH_DATA5_nDATA5_Pos) /*!< 0xFF000000 */ +#define FLASH_DATA5_nDATA5 FLASH_DATA5_nDATA5_Msk /*!< Inverse code of user data 5 */ + +/***************** Bit definition for FLASH_DATA6 register ******************/ +#define FLASH_DATA6_DATA6_Pos (0U) +#define FLASH_DATA6_DATA6_Msk (0xFFU << FLASH_DATA6_DATA6_Pos) /*!< 0x000000FF */ +#define FLASH_DATA6_DATA6 FLASH_DATA6_DATA6_Msk /*!< User data 6 */ +#define FLASH_DATA6_nDATA6_Pos (8U) +#define FLASH_DATA6_nDATA6_Msk (0xFFU << FLASH_DATA6_nDATA6_Pos) /*!< 0x0000FF00 */ +#define FLASH_DATA6_nDATA6 FLASH_DATA6_nDATA6_Msk /*!< Inverse code of user data 6 */ + +/***************** Bit definition for FLASH_DATA7 register ******************/ +#define FLASH_DATA7_DATA7_Pos (16U) +#define FLASH_DATA7_DATA7_Msk (0xFFU << FLASH_DATA7_DATA7_Pos) /*!< 0x00FF0000 */ +#define FLASH_DATA7_DATA7 FLASH_DATA7_DATA7_Msk /*!< User data 7 */ +#define FLASH_DATA7_nDATA7_Pos (24U) +#define FLASH_DATA7_nDATA7_Msk (0xFFU << FLASH_DATA7_nDATA7_Pos) /*!< 0xFF000000 */ +#define FLASH_DATA7_nDATA7 FLASH_DATA7_nDATA7_Msk /*!< Inverse code of user data 7 */ + +/*!< Noted: The FLASH_DATA go up to 219, it too long for added in here */ + +/******************************************************************************/ +/* */ +/* General-purpose I/Os (GPIO) & Multiplex function I/Os (IOMUX) */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for GPIO_CFGR register *******************/ +#define GPIO_CFGR_IOMC_Pos (0U) +#define GPIO_CFGR_IOMC_Msk (0xFFFFFFFFU << GPIO_CFGR_IOMC_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_CFGR_IOMC GPIO_CFGR_IOMC_Msk /*!< GPIO x mode configuration */ + +/*!< IOMC0 configuration */ +#define GPIO_CFGR_IOMC0_Pos (0U) +#define GPIO_CFGR_IOMC0_Msk (0x3U << GPIO_CFGR_IOMC0_Pos) /*!< 0x00000003 */ +#define GPIO_CFGR_IOMC0 GPIO_CFGR_IOMC0_Msk /*!< IOMC0[1:0] bits (GPIO x mode configuration, pin 0) */ +#define GPIO_CFGR_IOMC0_0 (0x1U << GPIO_CFGR_IOMC0_Pos) /*!< 0x00000001 */ +#define GPIO_CFGR_IOMC0_1 (0x2U << GPIO_CFGR_IOMC0_Pos) /*!< 0x00000002 */ + +/*!< IOMC1 configuration */ +#define GPIO_CFGR_IOMC1_Pos (2U) +#define GPIO_CFGR_IOMC1_Msk (0x3U << GPIO_CFGR_IOMC1_Pos) /*!< 0x0000000C */ +#define GPIO_CFGR_IOMC1 GPIO_CFGR_IOMC1_Msk /*!< IOMC1[1:0] bits (GPIO x mode configuration, pin 1) */ +#define GPIO_CFGR_IOMC1_0 (0x1U << GPIO_CFGR_IOMC1_Pos) /*!< 0x00000004 */ +#define GPIO_CFGR_IOMC1_1 (0x2U << GPIO_CFGR_IOMC1_Pos) /*!< 0x00000008 */ + +/*!< IOMC2 configuration */ +#define GPIO_CFGR_IOMC2_Pos (4U) +#define GPIO_CFGR_IOMC2_Msk (0x3U << GPIO_CFGR_IOMC2_Pos) /*!< 0x00000030 */ +#define GPIO_CFGR_IOMC2 GPIO_CFGR_IOMC2_Msk /*!< IOMC2[1:0] bits (GPIO x mode configuration, pin 2) */ +#define GPIO_CFGR_IOMC2_0 (0x1U << GPIO_CFGR_IOMC2_Pos) /*!< 0x00000010 */ +#define GPIO_CFGR_IOMC2_1 (0x2U << GPIO_CFGR_IOMC2_Pos) /*!< 0x00000020 */ + +/*!< IOMC3 configuration */ +#define GPIO_CFGR_IOMC3_Pos (6U) +#define GPIO_CFGR_IOMC3_Msk (0x3U << GPIO_CFGR_IOMC3_Pos) /*!< 0x000000C0 */ +#define GPIO_CFGR_IOMC3 GPIO_CFGR_IOMC3_Msk /*!< IOMC3[1:0] bits (GPIO x mode configuration, pin 3) */ +#define GPIO_CFGR_IOMC3_0 (0x1U << GPIO_CFGR_IOMC3_Pos) /*!< 0x00000040 */ +#define GPIO_CFGR_IOMC3_1 (0x2U << GPIO_CFGR_IOMC3_Pos) /*!< 0x00000080 */ + +/*!< IOMC4 configuration */ +#define GPIO_CFGR_IOMC4_Pos (8U) +#define GPIO_CFGR_IOMC4_Msk (0x3U << GPIO_CFGR_IOMC4_Pos) /*!< 0x00000300 */ +#define GPIO_CFGR_IOMC4 GPIO_CFGR_IOMC4_Msk /*!< IOMC4[1:0] bits (GPIO x mode configuration, pin 4) */ +#define GPIO_CFGR_IOMC4_0 (0x1U << GPIO_CFGR_IOMC4_Pos) /*!< 0x00000100 */ +#define GPIO_CFGR_IOMC4_1 (0x2U << GPIO_CFGR_IOMC4_Pos) /*!< 0x00000200 */ + +/*!< IOMC5 configuration */ +#define GPIO_CFGR_IOMC5_Pos (10U) +#define GPIO_CFGR_IOMC5_Msk (0x3U << GPIO_CFGR_IOMC5_Pos) /*!< 0x00000C00 */ +#define GPIO_CFGR_IOMC5 GPIO_CFGR_IOMC5_Msk /*!< IOMC5[1:0] bits (GPIO x mode configuration, pin 5) */ +#define GPIO_CFGR_IOMC5_0 (0x1U << GPIO_CFGR_IOMC5_Pos) /*!< 0x00000400 */ +#define GPIO_CFGR_IOMC5_1 (0x2U << GPIO_CFGR_IOMC5_Pos) /*!< 0x00000800 */ + +/*!< IOMC6 configuration */ +#define GPIO_CFGR_IOMC6_Pos (12U) +#define GPIO_CFGR_IOMC6_Msk (0x3U << GPIO_CFGR_IOMC6_Pos) /*!< 0x00003000 */ +#define GPIO_CFGR_IOMC6 GPIO_CFGR_IOMC6_Msk /*!< IOMC6[1:0] bits (GPIO x mode configuration, pin 6) */ +#define GPIO_CFGR_IOMC6_0 (0x1U << GPIO_CFGR_IOMC6_Pos) /*!< 0x00001000 */ +#define GPIO_CFGR_IOMC6_1 (0x2U << GPIO_CFGR_IOMC6_Pos) /*!< 0x00002000 */ + +/*!< IOMC7 configuration */ +#define GPIO_CFGR_IOMC7_Pos (14U) +#define GPIO_CFGR_IOMC7_Msk (0x3U << GPIO_CFGR_IOMC7_Pos) /*!< 0x0000C000 */ +#define GPIO_CFGR_IOMC7 GPIO_CFGR_IOMC7_Msk /*!< IOMC7[1:0] bits (GPIO x mode configuration, pin 7) */ +#define GPIO_CFGR_IOMC7_0 (0x1U << GPIO_CFGR_IOMC7_Pos) /*!< 0x00004000 */ +#define GPIO_CFGR_IOMC7_1 (0x2U << GPIO_CFGR_IOMC7_Pos) /*!< 0x00008000 */ + +/*!< IOMC8 configuration */ +#define GPIO_CFGR_IOMC8_Pos (16U) +#define GPIO_CFGR_IOMC8_Msk (0x3U << GPIO_CFGR_IOMC8_Pos) /*!< 0x00030000 */ +#define GPIO_CFGR_IOMC8 GPIO_CFGR_IOMC8_Msk /*!< IOMC8[1:0] bits (GPIO x mode configuration, pin 8) */ +#define GPIO_CFGR_IOMC8_0 (0x1U << GPIO_CFGR_IOMC8_Pos) /*!< 0x00010000 */ +#define GPIO_CFGR_IOMC8_1 (0x2U << GPIO_CFGR_IOMC8_Pos) /*!< 0x00020000 */ + +/*!< IOMC9 configuration */ +#define GPIO_CFGR_IOMC9_Pos (18U) +#define GPIO_CFGR_IOMC9_Msk (0x3U << GPIO_CFGR_IOMC9_Pos) /*!< 0x000C0000 */ +#define GPIO_CFGR_IOMC9 GPIO_CFGR_IOMC9_Msk /*!< IOMC9[1:0] bits (GPIO x mode configuration, pin 9) */ +#define GPIO_CFGR_IOMC9_0 (0x1U << GPIO_CFGR_IOMC9_Pos) /*!< 0x00040000 */ +#define GPIO_CFGR_IOMC9_1 (0x2U << GPIO_CFGR_IOMC9_Pos) /*!< 0x00080000 */ + +/*!< IOMC10 configuration */ +#define GPIO_CFGR_IOMC10_Pos (20U) +#define GPIO_CFGR_IOMC10_Msk (0x3U << GPIO_CFGR_IOMC10_Pos) /*!< 0x00300000 */ +#define GPIO_CFGR_IOMC10 GPIO_CFGR_IOMC10_Msk /*!< IOMC10[1:0] bits (GPIO x mode configuration, pin 10) */ +#define GPIO_CFGR_IOMC10_0 (0x1U << GPIO_CFGR_IOMC10_Pos) /*!< 0x00100000 */ +#define GPIO_CFGR_IOMC10_1 (0x2U << GPIO_CFGR_IOMC10_Pos) /*!< 0x00200000 */ + +/*!< IOMC11 configuration */ +#define GPIO_CFGR_IOMC11_Pos (22U) +#define GPIO_CFGR_IOMC11_Msk (0x3U << GPIO_CFGR_IOMC11_Pos) /*!< 0x00C00000 */ +#define GPIO_CFGR_IOMC11 GPIO_CFGR_IOMC11_Msk /*!< IOMC11[1:0] bits (GPIO x mode configuration, pin 11) */ +#define GPIO_CFGR_IOMC11_0 (0x1U << GPIO_CFGR_IOMC11_Pos) /*!< 0x00400000 */ +#define GPIO_CFGR_IOMC11_1 (0x2U << GPIO_CFGR_IOMC11_Pos) /*!< 0x00800000 */ + +/*!< IOMC12 configuration */ +#define GPIO_CFGR_IOMC12_Pos (24U) +#define GPIO_CFGR_IOMC12_Msk (0x3U << GPIO_CFGR_IOMC12_Pos) /*!< 0x03000000 */ +#define GPIO_CFGR_IOMC12 GPIO_CFGR_IOMC12_Msk /*!< IOMC12[1:0] bits (GPIO x mode configuration, pin 12) */ +#define GPIO_CFGR_IOMC12_0 (0x1U << GPIO_CFGR_IOMC12_Pos) /*!< 0x01000000 */ +#define GPIO_CFGR_IOMC12_1 (0x2U << GPIO_CFGR_IOMC12_Pos) /*!< 0x02000000 */ + +/*!< IOMC13 configuration */ +#define GPIO_CFGR_IOMC13_Pos (26U) +#define GPIO_CFGR_IOMC13_Msk (0x3U << GPIO_CFGR_IOMC13_Pos) /*!< 0x0C000000 */ +#define GPIO_CFGR_IOMC13 GPIO_CFGR_IOMC13_Msk /*!< IOMC13[1:0] bits (GPIO x mode configuration, pin 13) */ +#define GPIO_CFGR_IOMC13_0 (0x1U << GPIO_CFGR_IOMC13_Pos) /*!< 0x04000000 */ +#define GPIO_CFGR_IOMC13_1 (0x2U << GPIO_CFGR_IOMC13_Pos) /*!< 0x08000000 */ + +/*!< IOMC14 configuration */ +#define GPIO_CFGR_IOMC14_Pos (28U) +#define GPIO_CFGR_IOMC14_Msk (0x3U << GPIO_CFGR_IOMC14_Pos) /*!< 0x30000000 */ +#define GPIO_CFGR_IOMC14 GPIO_CFGR_IOMC14_Msk /*!< IOMC14[1:0] bits (GPIO x mode configuration, pin 14) */ +#define GPIO_CFGR_IOMC14_0 (0x1U << GPIO_CFGR_IOMC14_Pos) /*!< 0x10000000 */ +#define GPIO_CFGR_IOMC14_1 (0x2U << GPIO_CFGR_IOMC14_Pos) /*!< 0x20000000 */ + +/*!< IOMC15 configuration */ +#define GPIO_CFGR_IOMC15_Pos (30U) +#define GPIO_CFGR_IOMC15_Msk (0x3U << GPIO_CFGR_IOMC15_Pos) /*!< 0xC0000000 */ +#define GPIO_CFGR_IOMC15 GPIO_CFGR_IOMC15_Msk /*!< IOMC15[1:0] bits (GPIO x mode configuration, pin 15) */ +#define GPIO_CFGR_IOMC15_0 (0x1U << GPIO_CFGR_IOMC15_Pos) /*!< 0x40000000 */ +#define GPIO_CFGR_IOMC15_1 (0x2U << GPIO_CFGR_IOMC15_Pos) /*!< 0x80000000 */ + +/****************** Bit definition for GPIO_OMODE register ******************/ +#define GPIO_OMODE_OM0_Pos (0U) +#define GPIO_OMODE_OM0_Msk (0x1U << GPIO_OMODE_OM0_Pos) /*!< 0x00000001 */ +#define GPIO_OMODE_OM0 GPIO_OMODE_OM0_Msk /*!< GPIO x output mode configuration, pin 0 */ +#define GPIO_OMODE_OM1_Pos (1U) +#define GPIO_OMODE_OM1_Msk (0x3U << GPIO_OMODE_OM1_Pos) /*!< 0x00000002 */ +#define GPIO_OMODE_OM1 GPIO_OMODE_OM1_Msk /*!< GPIO x output mode configuration, pin 1 */ +#define GPIO_OMODE_OM2_Pos (2U) +#define GPIO_OMODE_OM2_Msk (0x3U << GPIO_OMODE_OM2_Pos) /*!< 0x00000004 */ +#define GPIO_OMODE_OM2 GPIO_OMODE_OM2_Msk /*!< GPIO x output mode configuration, pin 2 */ +#define GPIO_OMODE_OM3_Pos (3U) +#define GPIO_OMODE_OM3_Msk (0x3U << GPIO_OMODE_OM3_Pos) /*!< 0x00000008 */ +#define GPIO_OMODE_OM3 GPIO_OMODE_OM3_Msk /*!< GPIO x output mode configuration, pin 3 */ +#define GPIO_OMODE_OM4_Pos (4U) +#define GPIO_OMODE_OM4_Msk (0x3U << GPIO_OMODE_OM4_Pos) /*!< 0x00000010 */ +#define GPIO_OMODE_OM4 GPIO_OMODE_OM4_Msk /*!< GPIO x output mode configuration, pin 4 */ +#define GPIO_OMODE_OM5_Pos (5U) +#define GPIO_OMODE_OM5_Msk (0x3U << GPIO_OMODE_OM5_Pos) /*!< 0x00000020 */ +#define GPIO_OMODE_OM5 GPIO_OMODE_OM5_Msk /*!< GPIO x output mode configuration, pin 5 */ +#define GPIO_OMODE_OM6_Pos (6U) +#define GPIO_OMODE_OM6_Msk (0x3U << GPIO_OMODE_OM6_Pos) /*!< 0x00000040 */ +#define GPIO_OMODE_OM6 GPIO_OMODE_OM6_Msk /*!< GPIO x output mode configuration, pin 6 */ +#define GPIO_OMODE_OM7_Pos (7U) +#define GPIO_OMODE_OM7_Msk (0x3U << GPIO_OMODE_OM7_Pos) /*!< 0x00000080 */ +#define GPIO_OMODE_OM7 GPIO_OMODE_OM7_Msk /*!< GPIO x output mode configuration, pin 7 */ +#define GPIO_OMODE_OM8_Pos (8U) +#define GPIO_OMODE_OM8_Msk (0x1U << GPIO_OMODE_OM8_Pos) /*!< 0x00000100 */ +#define GPIO_OMODE_OM8 GPIO_OMODE_OM8_Msk /*!< GPIO x output mode configuration, pin 8 */ +#define GPIO_OMODE_OM9_Pos (9U) +#define GPIO_OMODE_OM9_Msk (0x1U << GPIO_OMODE_OM9_Pos) /*!< 0x00000200 */ +#define GPIO_OMODE_OM9 GPIO_OMODE_OM9_Msk /*!< GPIO x output mode configuration, pin 9 */ +#define GPIO_OMODE_OM10_Pos (10U) +#define GPIO_OMODE_OM10_Msk (0x1U << GPIO_OMODE_OM10_Pos) /*!< 0x00000400 */ +#define GPIO_OMODE_OM10 GPIO_OMODE_OM10_Msk /*!< GPIO x output mode configuration, pin 10 */ +#define GPIO_OMODE_OM11_Pos (11U) +#define GPIO_OMODE_OM11_Msk (0x1U << GPIO_OMODE_OM11_Pos) /*!< 0x00000800 */ +#define GPIO_OMODE_OM11 GPIO_OMODE_OM11_Msk /*!< GPIO x output mode configuration, pin 11 */ +#define GPIO_OMODE_OM12_Pos (12U) +#define GPIO_OMODE_OM12_Msk (0x1U << GPIO_OMODE_OM12_Pos) /*!< 0x00001000 */ +#define GPIO_OMODE_OM12 GPIO_OMODE_OM12_Msk /*!< GPIO x output mode configuration, pin 12 */ +#define GPIO_OMODE_OM13_Pos (13U) +#define GPIO_OMODE_OM13_Msk (0x1U << GPIO_OMODE_OM13_Pos) /*!< 0x00002000 */ +#define GPIO_OMODE_OM13 GPIO_OMODE_OM13_Msk /*!< GPIO x output mode configuration, pin 13 */ +#define GPIO_OMODE_OM14_Pos (14U) +#define GPIO_OMODE_OM14_Msk (0x1U << GPIO_OMODE_OM14_Pos) /*!< 0x00004000 */ +#define GPIO_OMODE_OM14 GPIO_OMODE_OM14_Msk /*!< GPIO x output mode configuration, pin 14 */ +#define GPIO_OMODE_OM15_Pos (15U) +#define GPIO_OMODE_OM15_Msk (0x1U << GPIO_OMODE_OM15_Pos) /*!< 0x00008000 */ +#define GPIO_OMODE_OM15 GPIO_OMODE_OM15_Msk /*!< GPIO x output mode configuration, pin 15 */ + +/*!<*************** Bit definition for GPIO_ODRVR register ******************/ +#define GPIO_ODRVR_ODRV_Pos (0U) +#define GPIO_ODRVR_ODRV_Msk (0xFFFFFFFFU << GPIO_ODRVR_ODRV_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_ODRVR_ODRV GPIO_ODRVR_ODRV_Msk /*!< GPIO x drive capability */ + +/*!< ODRV0 configuration */ +#define GPIO_ODRVR_ODRV0_Pos (0U) +#define GPIO_ODRVR_ODRV0_Msk (0x3U << GPIO_ODRVR_ODRV0_Pos) /*!< 0x00000003 */ +#define GPIO_ODRVR_ODRV0 GPIO_ODRVR_ODRV0_Msk /*!< ODRV0[1:0] bits (GPIO x drive capability, pin 0) */ +#define GPIO_ODRVR_ODRV0_0 (0x1U << GPIO_ODRVR_ODRV0_Pos) /*!< 0x00000001 */ +#define GPIO_ODRVR_ODRV0_1 (0x2U << GPIO_ODRVR_ODRV0_Pos) /*!< 0x00000002 */ + +/*!< ODRV1 configuration */ +#define GPIO_ODRVR_ODRV1_Pos (2U) +#define GPIO_ODRVR_ODRV1_Msk (0x3U << GPIO_ODRVR_ODRV1_Pos) /*!< 0x0000000C */ +#define GPIO_ODRVR_ODRV1 GPIO_ODRVR_ODRV1_Msk /*!< ODRV1[1:0] bits (GPIO x drive capability, pin 1) */ +#define GPIO_ODRVR_ODRV1_0 (0x1U << GPIO_ODRVR_ODRV1_Pos) /*!< 0x00000004 */ +#define GPIO_ODRVR_ODRV1_1 (0x2U << GPIO_ODRVR_ODRV1_Pos) /*!< 0x00000008 */ + +/*!< ODRV2 configuration */ +#define GPIO_ODRVR_ODRV2_Pos (4U) +#define GPIO_ODRVR_ODRV2_Msk (0x3U << GPIO_ODRVR_ODRV2_Pos) /*!< 0x00000030 */ +#define GPIO_ODRVR_ODRV2 GPIO_ODRVR_ODRV2_Msk /*!< ODRV2[1:0] bits (GPIO x drive capability, pin 2) */ +#define GPIO_ODRVR_ODRV2_0 (0x1U << GPIO_ODRVR_ODRV2_Pos) /*!< 0x00000010 */ +#define GPIO_ODRVR_ODRV2_1 (0x2U << GPIO_ODRVR_ODRV2_Pos) /*!< 0x00000020 */ + +/*!< ODRV3 configuration */ +#define GPIO_ODRVR_ODRV3_Pos (6U) +#define GPIO_ODRVR_ODRV3_Msk (0x3U << GPIO_ODRVR_ODRV3_Pos) /*!< 0x000000C0 */ +#define GPIO_ODRVR_ODRV3 GPIO_ODRVR_ODRV3_Msk /*!< ODRV3[1:0] bits (GPIO x drive capability, pin 3) */ +#define GPIO_ODRVR_ODRV3_0 (0x1U << GPIO_ODRVR_ODRV3_Pos) /*!< 0x00000040 */ +#define GPIO_ODRVR_ODRV3_1 (0x2U << GPIO_ODRVR_ODRV3_Pos) /*!< 0x00000080 */ + +/*!< ODRV4 configuration */ +#define GPIO_ODRVR_ODRV4_Pos (8U) +#define GPIO_ODRVR_ODRV4_Msk (0x3U << GPIO_ODRVR_ODRV4_Pos) /*!< 0x00000300 */ +#define GPIO_ODRVR_ODRV4 GPIO_ODRVR_ODRV4_Msk /*!< ODRV4[1:0] bits (GPIO x drive capability, pin 4) */ +#define GPIO_ODRVR_ODRV4_0 (0x1U << GPIO_ODRVR_ODRV4_Pos) /*!< 0x00000100 */ +#define GPIO_ODRVR_ODRV4_1 (0x2U << GPIO_ODRVR_ODRV4_Pos) /*!< 0x00000200 */ + +/*!< ODRV5 configuration */ +#define GPIO_ODRVR_ODRV5_Pos (10U) +#define GPIO_ODRVR_ODRV5_Msk (0x3U << GPIO_ODRVR_ODRV5_Pos) /*!< 0x00000C00 */ +#define GPIO_ODRVR_ODRV5 GPIO_ODRVR_ODRV5_Msk /*!< ODRV5[1:0] bits (GPIO x drive capability, pin 5) */ +#define GPIO_ODRVR_ODRV5_0 (0x1U << GPIO_ODRVR_ODRV5_Pos) /*!< 0x00000400 */ +#define GPIO_ODRVR_ODRV5_1 (0x2U << GPIO_ODRVR_ODRV5_Pos) /*!< 0x00000800 */ + +/*!< ODRV6 configuration */ +#define GPIO_ODRVR_ODRV6_Pos (12U) +#define GPIO_ODRVR_ODRV6_Msk (0x3U << GPIO_ODRVR_ODRV6_Pos) /*!< 0x00003000 */ +#define GPIO_ODRVR_ODRV6 GPIO_ODRVR_ODRV6_Msk /*!< ODRV6[1:0] bits (GPIO x drive capability, pin 6) */ +#define GPIO_ODRVR_ODRV6_0 (0x1U << GPIO_ODRVR_ODRV6_Pos) /*!< 0x00001000 */ +#define GPIO_ODRVR_ODRV6_1 (0x2U << GPIO_ODRVR_ODRV6_Pos) /*!< 0x00002000 */ + +/*!< ODRV7 configuration */ +#define GPIO_ODRVR_ODRV7_Pos (14U) +#define GPIO_ODRVR_ODRV7_Msk (0x3U << GPIO_ODRVR_ODRV7_Pos) /*!< 0x0000C000 */ +#define GPIO_ODRVR_ODRV7 GPIO_ODRVR_ODRV7_Msk /*!< ODRV7[1:0] bits (GPIO x drive capability, pin 7) */ +#define GPIO_ODRVR_ODRV7_0 (0x1U << GPIO_ODRVR_ODRV7_Pos) /*!< 0x00004000 */ +#define GPIO_ODRVR_ODRV7_1 (0x2U << GPIO_ODRVR_ODRV7_Pos) /*!< 0x00008000 */ + +/*!< ODRV8 configuration */ +#define GPIO_ODRVR_ODRV8_Pos (16U) +#define GPIO_ODRVR_ODRV8_Msk (0x3U << GPIO_ODRVR_ODRV8_Pos) /*!< 0x00030000 */ +#define GPIO_ODRVR_ODRV8 GPIO_ODRVR_ODRV8_Msk /*!< ODRV8[1:0] bits (GPIO x drive capability, pin 8) */ +#define GPIO_ODRVR_ODRV8_0 (0x1U << GPIO_ODRVR_ODRV8_Pos) /*!< 0x00010000 */ +#define GPIO_ODRVR_ODRV8_1 (0x2U << GPIO_ODRVR_ODRV8_Pos) /*!< 0x00020000 */ + +/*!< ODRV9 configuration */ +#define GPIO_ODRVR_ODRV9_Pos (18U) +#define GPIO_ODRVR_ODRV9_Msk (0x3U << GPIO_ODRVR_ODRV9_Pos) /*!< 0x000C0000 */ +#define GPIO_ODRVR_ODRV9 GPIO_ODRVR_ODRV9_Msk /*!< ODRV9[1:0] bits (GPIO x drive capability, pin 9) */ +#define GPIO_ODRVR_ODRV9_0 (0x1U << GPIO_ODRVR_ODRV9_Pos) /*!< 0x00040000 */ +#define GPIO_ODRVR_ODRV9_1 (0x2U << GPIO_ODRVR_ODRV9_Pos) /*!< 0x00080000 */ + +/*!< ODRV10 configuration */ +#define GPIO_ODRVR_ODRV10_Pos (20U) +#define GPIO_ODRVR_ODRV10_Msk (0x3U << GPIO_ODRVR_ODRV10_Pos) /*!< 0x00300000 */ +#define GPIO_ODRVR_ODRV10 GPIO_ODRVR_ODRV10_Msk /*!< ODRV10[1:0] bits (GPIO x drive capability, pin 10) */ +#define GPIO_ODRVR_ODRV10_0 (0x1U << GPIO_ODRVR_ODRV10_Pos) /*!< 0x00100000 */ +#define GPIO_ODRVR_ODRV10_1 (0x2U << GPIO_ODRVR_ODRV10_Pos) /*!< 0x00200000 */ + +/*!< ODRV11 configuration */ +#define GPIO_ODRVR_ODRV11_Pos (22U) +#define GPIO_ODRVR_ODRV11_Msk (0x3U << GPIO_ODRVR_ODRV11_Pos) /*!< 0x00C00000 */ +#define GPIO_ODRVR_ODRV11 GPIO_ODRVR_ODRV11_Msk /*!< ODRV11[1:0] bits (GPIO x drive capability, pin 11) */ +#define GPIO_ODRVR_ODRV11_0 (0x1U << GPIO_ODRVR_ODRV11_Pos) /*!< 0x00400000 */ +#define GPIO_ODRVR_ODRV11_1 (0x2U << GPIO_ODRVR_ODRV11_Pos) /*!< 0x00800000 */ + +/*!< ODRV12 configuration */ +#define GPIO_ODRVR_ODRV12_Pos (24U) +#define GPIO_ODRVR_ODRV12_Msk (0x3U << GPIO_ODRVR_ODRV12_Pos) /*!< 0x03000000 */ +#define GPIO_ODRVR_ODRV12 GPIO_ODRVR_ODRV12_Msk /*!< ODRV12[1:0] bits (GPIO x drive capability, pin 12) */ +#define GPIO_ODRVR_ODRV12_0 (0x1U << GPIO_ODRVR_ODRV12_Pos) /*!< 0x01000000 */ +#define GPIO_ODRVR_ODRV12_1 (0x2U << GPIO_ODRVR_ODRV12_Pos) /*!< 0x02000000 */ + +/*!< ODRV13 configuration */ +#define GPIO_ODRVR_ODRV13_Pos (26U) +#define GPIO_ODRVR_ODRV13_Msk (0x3U << GPIO_ODRVR_ODRV13_Pos) /*!< 0x0C000000 */ +#define GPIO_ODRVR_ODRV13 GPIO_ODRVR_ODRV13_Msk /*!< ODRV13[1:0] bits (GPIO x drive capability, pin 13) */ +#define GPIO_ODRVR_ODRV13_0 (0x1U << GPIO_ODRVR_ODRV13_Pos) /*!< 0x04000000 */ +#define GPIO_ODRVR_ODRV13_1 (0x2U << GPIO_ODRVR_ODRV13_Pos) /*!< 0x08000000 */ + +/*!< ODRV14 configuration */ +#define GPIO_ODRVR_ODRV14_Pos (28U) +#define GPIO_ODRVR_ODRV14_Msk (0x3U << GPIO_ODRVR_ODRV14_Pos) /*!< 0x30000000 */ +#define GPIO_ODRVR_ODRV14 GPIO_ODRVR_ODRV14_Msk /*!< ODRV14[1:0] bits (GPIO x drive capability, pin 14) */ +#define GPIO_ODRVR_ODRV14_0 (0x1U << GPIO_ODRVR_ODRV14_Pos) /*!< 0x10000000 */ +#define GPIO_ODRVR_ODRV14_1 (0x2U << GPIO_ODRVR_ODRV14_Pos) /*!< 0x20000000 */ + +/*!< ODRV15 configuration */ +#define GPIO_ODRVR_ODRV15_Pos (30U) +#define GPIO_ODRVR_ODRV15_Msk (0x3U << GPIO_ODRVR_ODRV15_Pos) /*!< 0xC0000000 */ +#define GPIO_ODRVR_ODRV15 GPIO_ODRVR_ODRV15_Msk /*!< ODRV15[1:0] bits (GPIO x drive capability, pin 15) */ +#define GPIO_ODRVR_ODRV15_0 (0x1U << GPIO_ODRVR_ODRV15_Pos) /*!< 0x40000000 */ +#define GPIO_ODRVR_ODRV15_1 (0x2U << GPIO_ODRVR_ODRV15_Pos) /*!< 0x80000000 */ + +/*!<*************** Bit definition for GPIO_PULL register *******************/ +#define GPIO_PULL_PULL_Pos (0U) +#define GPIO_PULL_PULL_Msk (0xFFFFFFFFU << GPIO_PULL_PULL_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_PULL_PULL GPIO_PULL_PULL_Msk /*!< GPIO x pull-up/pull-down configuration */ + +/*!< PULL0 configuration */ +#define GPIO_PULL_PULL0_Pos (0U) +#define GPIO_PULL_PULL0_Msk (0x3U << GPIO_PULL_PULL0_Pos) /*!< 0x00000003 */ +#define GPIO_PULL_PULL0 GPIO_PULL_PULL0_Msk /*!< PULL0[1:0] bits (GPIO x pull-up/pull-down configuration, pin 0) */ +#define GPIO_PULL_PULL0_0 (0x1U << GPIO_PULL_PULL0_Pos) /*!< 0x00000001 */ +#define GPIO_PULL_PULL0_1 (0x2U << GPIO_PULL_PULL0_Pos) /*!< 0x00000002 */ + +/*!< PULL1 configuration */ +#define GPIO_PULL_PULL1_Pos (2U) +#define GPIO_PULL_PULL1_Msk (0x3U << GPIO_PULL_PULL1_Pos) /*!< 0x0000000C */ +#define GPIO_PULL_PULL1 GPIO_PULL_PULL1_Msk /*!< PULL1[1:0] bits (GPIO x pull-up/pull-down configuration, pin 1) */ +#define GPIO_PULL_PULL1_0 (0x1U << GPIO_PULL_PULL1_Pos) /*!< 0x00000004 */ +#define GPIO_PULL_PULL1_1 (0x2U << GPIO_PULL_PULL1_Pos) /*!< 0x00000008 */ + +/*!< PULL2 configuration */ +#define GPIO_PULL_PULL2_Pos (4U) +#define GPIO_PULL_PULL2_Msk (0x3U << GPIO_PULL_PULL2_Pos) /*!< 0x00000030 */ +#define GPIO_PULL_PULL2 GPIO_PULL_PULL2_Msk /*!< PULL2[1:0] bits (GPIO x pull-up/pull-down configuration, pin 2) */ +#define GPIO_PULL_PULL2_0 (0x1U << GPIO_PULL_PULL2_Pos) /*!< 0x00000010 */ +#define GPIO_PULL_PULL2_1 (0x2U << GPIO_PULL_PULL2_Pos) /*!< 0x00000020 */ + +/*!< PULL3 configuration */ +#define GPIO_PULL_PULL3_Pos (6U) +#define GPIO_PULL_PULL3_Msk (0x3U << GPIO_PULL_PULL3_Pos) /*!< 0x000000C0 */ +#define GPIO_PULL_PULL3 GPIO_PULL_PULL3_Msk /*!< PULL3[1:0] bits (GPIO x pull-up/pull-down configuration, pin 3) */ +#define GPIO_PULL_PULL3_0 (0x1U << GPIO_PULL_PULL3_Pos) /*!< 0x00000040 */ +#define GPIO_PULL_PULL3_1 (0x2U << GPIO_PULL_PULL3_Pos) /*!< 0x00000080 */ + +/*!< PULL4 configuration */ +#define GPIO_PULL_PULL4_Pos (8U) +#define GPIO_PULL_PULL4_Msk (0x3U << GPIO_PULL_PULL4_Pos) /*!< 0x00000300 */ +#define GPIO_PULL_PULL4 GPIO_PULL_PULL4_Msk /*!< PULL4[1:0] bits (GPIO x pull-up/pull-down configuration, pin 4) */ +#define GPIO_PULL_PULL4_0 (0x1U << GPIO_PULL_PULL4_Pos) /*!< 0x00000100 */ +#define GPIO_PULL_PULL4_1 (0x2U << GPIO_PULL_PULL4_Pos) /*!< 0x00000200 */ + +/*!< PULL5 configuration */ +#define GPIO_PULL_PULL5_Pos (10U) +#define GPIO_PULL_PULL5_Msk (0x3U << GPIO_PULL_PULL5_Pos) /*!< 0x00000C00 */ +#define GPIO_PULL_PULL5 GPIO_PULL_PULL5_Msk /*!< PULL5[1:0] bits (GPIO x pull-up/pull-down configuration, pin 5) */ +#define GPIO_PULL_PULL5_0 (0x1U << GPIO_PULL_PULL5_Pos) /*!< 0x00000400 */ +#define GPIO_PULL_PULL5_1 (0x2U << GPIO_PULL_PULL5_Pos) /*!< 0x00000800 */ + +/*!< PULL6 configuration */ +#define GPIO_PULL_PULL6_Pos (12U) +#define GPIO_PULL_PULL6_Msk (0x3U << GPIO_PULL_PULL6_Pos) /*!< 0x00003000 */ +#define GPIO_PULL_PULL6 GPIO_PULL_PULL6_Msk /*!< PULL6[1:0] bits (GPIO x pull-up/pull-down configuration, pin 6) */ +#define GPIO_PULL_PULL6_0 (0x1U << GPIO_PULL_PULL6_Pos) /*!< 0x00001000 */ +#define GPIO_PULL_PULL6_1 (0x2U << GPIO_PULL_PULL6_Pos) /*!< 0x00002000 */ + +/*!< PULL7 configuration */ +#define GPIO_PULL_PULL7_Pos (14U) +#define GPIO_PULL_PULL7_Msk (0x3U << GPIO_PULL_PULL7_Pos) /*!< 0x0000C000 */ +#define GPIO_PULL_PULL7 GPIO_PULL_PULL7_Msk /*!< PULL7[1:0] bits (GPIO x pull-up/pull-down configuration, pin 7) */ +#define GPIO_PULL_PULL7_0 (0x1U << GPIO_PULL_PULL7_Pos) /*!< 0x00004000 */ +#define GPIO_PULL_PULL7_1 (0x2U << GPIO_PULL_PULL7_Pos) /*!< 0x00008000 */ + +/*!< PULL8 configuration */ +#define GPIO_PULL_PULL8_Pos (16U) +#define GPIO_PULL_PULL8_Msk (0x3U << GPIO_PULL_PULL8_Pos) /*!< 0x00030000 */ +#define GPIO_PULL_PULL8 GPIO_PULL_PULL8_Msk /*!< PULL8[1:0] bits (GPIO x pull-up/pull-down configuration, pin 8) */ +#define GPIO_PULL_PULL8_0 (0x1U << GPIO_PULL_PULL8_Pos) /*!< 0x00010000 */ +#define GPIO_PULL_PULL8_1 (0x2U << GPIO_PULL_PULL8_Pos) /*!< 0x00020000 */ + +/*!< PULL9 configuration */ +#define GPIO_PULL_PULL9_Pos (18U) +#define GPIO_PULL_PULL9_Msk (0x3U << GPIO_PULL_PULL9_Pos) /*!< 0x000C0000 */ +#define GPIO_PULL_PULL9 GPIO_PULL_PULL9_Msk /*!< PULL9[1:0] bits (GPIO x pull-up/pull-down configuration, pin 9) */ +#define GPIO_PULL_PULL9_0 (0x1U << GPIO_PULL_PULL9_Pos) /*!< 0x00040000 */ +#define GPIO_PULL_PULL9_1 (0x2U << GPIO_PULL_PULL9_Pos) /*!< 0x00080000 */ + +/*!< PULL10 configuration */ +#define GPIO_PULL_PULL10_Pos (20U) +#define GPIO_PULL_PULL10_Msk (0x3U << GPIO_PULL_PULL10_Pos) /*!< 0x00300000 */ +#define GPIO_PULL_PULL10 GPIO_PULL_PULL10_Msk /*!< PULL10[1:0] bits (GPIO x pull-up/pull-down configuration, pin 10) */ +#define GPIO_PULL_PULL10_0 (0x1U << GPIO_PULL_PULL10_Pos) /*!< 0x00100000 */ +#define GPIO_PULL_PULL10_1 (0x2U << GPIO_PULL_PULL10_Pos) /*!< 0x00200000 */ + +/*!< PULL11 configuration */ +#define GPIO_PULL_PULL11_Pos (22U) +#define GPIO_PULL_PULL11_Msk (0x3U << GPIO_PULL_PULL11_Pos) /*!< 0x00C00000 */ +#define GPIO_PULL_PULL11 GPIO_PULL_PULL11_Msk /*!< PULL11[1:0] bits (GPIO x pull-up/pull-down configuration, pin 11) */ +#define GPIO_PULL_PULL11_0 (0x1U << GPIO_PULL_PULL11_Pos) /*!< 0x00400000 */ +#define GPIO_PULL_PULL11_1 (0x2U << GPIO_PULL_PULL11_Pos) /*!< 0x00800000 */ + +/*!< PULL12 configuration */ +#define GPIO_PULL_PULL12_Pos (24U) +#define GPIO_PULL_PULL12_Msk (0x3U << GPIO_PULL_PULL12_Pos) /*!< 0x03000000 */ +#define GPIO_PULL_PULL12 GPIO_PULL_PULL12_Msk /*!< PULL12[1:0] bits (GPIO x pull-up/pull-down configuration, pin 12) */ +#define GPIO_PULL_PULL12_0 (0x1U << GPIO_PULL_PULL12_Pos) /*!< 0x01000000 */ +#define GPIO_PULL_PULL12_1 (0x2U << GPIO_PULL_PULL12_Pos) /*!< 0x02000000 */ + +/*!< PULL13 configuration */ +#define GPIO_PULL_PULL13_Pos (26U) +#define GPIO_PULL_PULL13_Msk (0x3U << GPIO_PULL_PULL13_Pos) /*!< 0x0C000000 */ +#define GPIO_PULL_PULL13 GPIO_PULL_PULL13_Msk /*!< PULL13[1:0] bits (GPIO x pull-up/pull-down configuration, pin 13) */ +#define GPIO_PULL_PULL13_0 (0x1U << GPIO_PULL_PULL13_Pos) /*!< 0x04000000 */ +#define GPIO_PULL_PULL13_1 (0x2U << GPIO_PULL_PULL13_Pos) /*!< 0x08000000 */ + +/*!< PULL14 configuration */ +#define GPIO_PULL_PULL14_Pos (28U) +#define GPIO_PULL_PULL14_Msk (0x3U << GPIO_PULL_PULL14_Pos) /*!< 0x30000000 */ +#define GPIO_PULL_PULL14 GPIO_PULL_PULL14_Msk /*!< PULL14[1:0] bits (GPIO x pull-up/pull-down configuration, pin 14) */ +#define GPIO_PULL_PULL14_0 (0x1U << GPIO_PULL_PULL14_Pos) /*!< 0x10000000 */ +#define GPIO_PULL_PULL14_1 (0x2U << GPIO_PULL_PULL14_Pos) /*!< 0x20000000 */ + +/*!< PULL15 configuration */ +#define GPIO_PULL_PULL15_Pos (30U) +#define GPIO_PULL_PULL15_Msk (0x3U << GPIO_PULL_PULL15_Pos) /*!< 0xC0000000 */ +#define GPIO_PULL_PULL15 GPIO_PULL_PULL15_Msk /*!< PULL15[1:0] bits (GPIO x pull-up/pull-down configuration, pin 15) */ +#define GPIO_PULL_PULL15_0 (0x1U << GPIO_PULL_PULL15_Pos) /*!< 0x40000000 */ +#define GPIO_PULL_PULL15_1 (0x2U << GPIO_PULL_PULL15_Pos) /*!< 0x80000000 */ + +/*!<**************** Bit definition for GPIO_IDT register *******************/ +#define GPIO_IDT_IDT0_Pos (0U) +#define GPIO_IDT_IDT0_Msk (0x1U << GPIO_IDT_IDT0_Pos) /*!< 0x00000001 */ +#define GPIO_IDT_IDT0 GPIO_IDT_IDT0_Msk /*!< GPIO x input data, pin 0 */ +#define GPIO_IDT_IDT1_Pos (1U) +#define GPIO_IDT_IDT1_Msk (0x1U << GPIO_IDT_IDT1_Pos) /*!< 0x00000002 */ +#define GPIO_IDT_IDT1 GPIO_IDT_IDT1_Msk /*!< GPIO x input data, pin 1 */ +#define GPIO_IDT_IDT2_Pos (2U) +#define GPIO_IDT_IDT2_Msk (0x1U << GPIO_IDT_IDT2_Pos) /*!< 0x00000004 */ +#define GPIO_IDT_IDT2 GPIO_IDT_IDT2_Msk /*!< GPIO x input data, pin 2 */ +#define GPIO_IDT_IDT3_Pos (3U) +#define GPIO_IDT_IDT3_Msk (0x1U << GPIO_IDT_IDT3_Pos) /*!< 0x00000008 */ +#define GPIO_IDT_IDT3 GPIO_IDT_IDT3_Msk /*!< GPIO x input data, pin 3 */ +#define GPIO_IDT_IDT4_Pos (4U) +#define GPIO_IDT_IDT4_Msk (0x1U << GPIO_IDT_IDT4_Pos) /*!< 0x00000010 */ +#define GPIO_IDT_IDT4 GPIO_IDT_IDT4_Msk /*!< GPIO x input data, pin 4 */ +#define GPIO_IDT_IDT5_Pos (5U) +#define GPIO_IDT_IDT5_Msk (0x1U << GPIO_IDT_IDT5_Pos) /*!< 0x00000020 */ +#define GPIO_IDT_IDT5 GPIO_IDT_IDT5_Msk /*!< GPIO x input data, pin 5 */ +#define GPIO_IDT_IDT6_Pos (6U) +#define GPIO_IDT_IDT6_Msk (0x1U << GPIO_IDT_IDT6_Pos) /*!< 0x00000040 */ +#define GPIO_IDT_IDT6 GPIO_IDT_IDT6_Msk /*!< GPIO x input data, pin 6 */ +#define GPIO_IDT_IDT7_Pos (7U) +#define GPIO_IDT_IDT7_Msk (0x1U << GPIO_IDT_IDT7_Pos) /*!< 0x00000080 */ +#define GPIO_IDT_IDT7 GPIO_IDT_IDT7_Msk /*!< GPIO x input data, pin 7 */ +#define GPIO_IDT_IDT8_Pos (8U) +#define GPIO_IDT_IDT8_Msk (0x1U << GPIO_IDT_IDT8_Pos) /*!< 0x00000100 */ +#define GPIO_IDT_IDT8 GPIO_IDT_IDT8_Msk /*!< GPIO x input data, pin 8 */ +#define GPIO_IDT_IDT9_Pos (9U) +#define GPIO_IDT_IDT9_Msk (0x1U << GPIO_IDT_IDT9_Pos) /*!< 0x00000200 */ +#define GPIO_IDT_IDT9 GPIO_IDT_IDT9_Msk /*!< GPIO x input data, pin 9 */ +#define GPIO_IDT_IDT10_Pos (10U) +#define GPIO_IDT_IDT10_Msk (0x1U << GPIO_IDT_IDT10_Pos) /*!< 0x00000400 */ +#define GPIO_IDT_IDT10 GPIO_IDT_IDT10_Msk /*!< GPIO x input data, pin 10 */ +#define GPIO_IDT_IDT11_Pos (11U) +#define GPIO_IDT_IDT11_Msk (0x1U << GPIO_IDT_IDT11_Pos) /*!< 0x00000800 */ +#define GPIO_IDT_IDT11 GPIO_IDT_IDT11_Msk /*!< GPIO x input data, pin 11 */ +#define GPIO_IDT_IDT12_Pos (12U) +#define GPIO_IDT_IDT12_Msk (0x1U << GPIO_IDT_IDT12_Pos) /*!< 0x00001000 */ +#define GPIO_IDT_IDT12 GPIO_IDT_IDT12_Msk /*!< GPIO x input data, pin 12 */ +#define GPIO_IDT_IDT13_Pos (13U) +#define GPIO_IDT_IDT13_Msk (0x1U << GPIO_IDT_IDT13_Pos) /*!< 0x00002000 */ +#define GPIO_IDT_IDT13 GPIO_IDT_IDT13_Msk /*!< GPIO x input data, pin 13 */ +#define GPIO_IDT_IDT14_Pos (14U) +#define GPIO_IDT_IDT14_Msk (0x1U << GPIO_IDT_IDT14_Pos) /*!< 0x00004000 */ +#define GPIO_IDT_IDT14 GPIO_IDT_IDT14_Msk /*!< GPIO x input data, pin 14 */ +#define GPIO_IDT_IDT15_Pos (15U) +#define GPIO_IDT_IDT15_Msk (0x1U << GPIO_IDT_IDT15_Pos) /*!< 0x00008000 */ +#define GPIO_IDT_IDT15 GPIO_IDT_IDT15_Msk /*!< GPIO x input data, pin 15 */ + +/******************* Bit definition for GPIO_ODT register *******************/ +#define GPIO_ODT_ODT0_Pos (0U) +#define GPIO_ODT_ODT0_Msk (0x1U << GPIO_ODT_ODT0_Pos) /*!< 0x00000001 */ +#define GPIO_ODT_ODT0 GPIO_ODT_ODT0_Msk /*!< GPIO x output data, pin 0 */ +#define GPIO_ODT_ODT1_Pos (1U) +#define GPIO_ODT_ODT1_Msk (0x1U << GPIO_ODT_ODT1_Pos) /*!< 0x00000002 */ +#define GPIO_ODT_ODT1 GPIO_ODT_ODT1_Msk /*!< GPIO x output data, pin 1 */ +#define GPIO_ODT_ODT2_Pos (2U) +#define GPIO_ODT_ODT2_Msk (0x1U << GPIO_ODT_ODT2_Pos) /*!< 0x00000004 */ +#define GPIO_ODT_ODT2 GPIO_ODT_ODT2_Msk /*!< GPIO x output data, pin 2 */ +#define GPIO_ODT_ODT3_Pos (3U) +#define GPIO_ODT_ODT3_Msk (0x1U << GPIO_ODT_ODT3_Pos) /*!< 0x00000008 */ +#define GPIO_ODT_ODT3 GPIO_ODT_ODT3_Msk /*!< GPIO x output data, pin 3 */ +#define GPIO_ODT_ODT4_Pos (4U) +#define GPIO_ODT_ODT4_Msk (0x1U << GPIO_ODT_ODT4_Pos) /*!< 0x00000010 */ +#define GPIO_ODT_ODT4 GPIO_ODT_ODT4_Msk /*!< GPIO x output data, pin 4 */ +#define GPIO_ODT_ODT5_Pos (5U) +#define GPIO_ODT_ODT5_Msk (0x1U << GPIO_ODT_ODT5_Pos) /*!< 0x00000020 */ +#define GPIO_ODT_ODT5 GPIO_ODT_ODT5_Msk /*!< GPIO x output data, pin 5 */ +#define GPIO_ODT_ODT6_Pos (6U) +#define GPIO_ODT_ODT6_Msk (0x1U << GPIO_ODT_ODT6_Pos) /*!< 0x00000040 */ +#define GPIO_ODT_ODT6 GPIO_ODT_ODT6_Msk /*!< GPIO x output data, pin 6 */ +#define GPIO_ODT_ODT7_Pos (7U) +#define GPIO_ODT_ODT7_Msk (0x1U << GPIO_ODT_ODT7_Pos) /*!< 0x00000080 */ +#define GPIO_ODT_ODT7 GPIO_ODT_ODT7_Msk /*!< GPIO x output data, pin 7 */ +#define GPIO_ODT_ODT8_Pos (8U) +#define GPIO_ODT_ODT8_Msk (0x1U << GPIO_ODT_ODT8_Pos) /*!< 0x00000100 */ +#define GPIO_ODT_ODT8 GPIO_ODT_ODT8_Msk /*!< GPIO x output data, pin 8 */ +#define GPIO_ODT_ODT9_Pos (9U) +#define GPIO_ODT_ODT9_Msk (0x1U << GPIO_ODT_ODT9_Pos) /*!< 0x00000200 */ +#define GPIO_ODT_ODT9 GPIO_ODT_ODT9_Msk /*!< GPIO x output data, pin 9 */ +#define GPIO_ODT_ODT10_Pos (10U) +#define GPIO_ODT_ODT10_Msk (0x1U << GPIO_ODT_ODT10_Pos) /*!< 0x00000400 */ +#define GPIO_ODT_ODT10 GPIO_ODT_ODT10_Msk /*!< GPIO x output data, pin 10 */ +#define GPIO_ODT_ODT11_Pos (11U) +#define GPIO_ODT_ODT11_Msk (0x1U << GPIO_ODT_ODT11_Pos) /*!< 0x00000800 */ +#define GPIO_ODT_ODT11 GPIO_ODT_ODT11_Msk /*!< GPIO x output data, pin 11 */ +#define GPIO_ODT_ODT12_Pos (12U) +#define GPIO_ODT_ODT12_Msk (0x1U << GPIO_ODT_ODT12_Pos) /*!< 0x00001000 */ +#define GPIO_ODT_ODT12 GPIO_ODT_ODT12_Msk /*!< GPIO x output data, pin 12 */ +#define GPIO_ODT_ODT13_Pos (13U) +#define GPIO_ODT_ODT13_Msk (0x1U << GPIO_ODT_ODT13_Pos) /*!< 0x00002000 */ +#define GPIO_ODT_ODT13 GPIO_ODT_ODT13_Msk /*!< GPIO x output data, pin 13 */ +#define GPIO_ODT_ODT14_Pos (14U) +#define GPIO_ODT_ODT14_Msk (0x1U << GPIO_ODT_ODT14_Pos) /*!< 0x00004000 */ +#define GPIO_ODT_ODT14 GPIO_ODT_ODT14_Msk /*!< GPIO x output data, pin 14 */ +#define GPIO_ODT_ODT15_Pos (15U) +#define GPIO_ODT_ODT15_Msk (0x1U << GPIO_ODT_ODT15_Pos) /*!< 0x00008000 */ +#define GPIO_ODT_ODT15 GPIO_ODT_ODT15_Msk /*!< GPIO x output data, pin 15 */ + +/******************* Bit definition for GPIO_SCR register *******************/ +#define GPIO_SCR_IOSB0_Pos (0U) +#define GPIO_SCR_IOSB0_Msk (0x1U << GPIO_SCR_IOSB0_Pos) /*!< 0x00000001 */ +#define GPIO_SCR_IOSB0 GPIO_SCR_IOSB0_Msk /*!< GPIO x set bit, pin 0 */ +#define GPIO_SCR_IOSB1_Pos (1U) +#define GPIO_SCR_IOSB1_Msk (0x1U << GPIO_SCR_IOSB1_Pos) /*!< 0x00000002 */ +#define GPIO_SCR_IOSB1 GPIO_SCR_IOSB1_Msk /*!< GPIO x set bit, pin 1 */ +#define GPIO_SCR_IOSB2_Pos (2U) +#define GPIO_SCR_IOSB2_Msk (0x1U << GPIO_SCR_IOSB2_Pos) /*!< 0x00000004 */ +#define GPIO_SCR_IOSB2 GPIO_SCR_IOSB2_Msk /*!< GPIO x set bit, pin 2 */ +#define GPIO_SCR_IOSB3_Pos (3U) +#define GPIO_SCR_IOSB3_Msk (0x1U << GPIO_SCR_IOSB3_Pos) /*!< 0x00000008 */ +#define GPIO_SCR_IOSB3 GPIO_SCR_IOSB3_Msk /*!< GPIO x set bit, pin 3 */ +#define GPIO_SCR_IOSB4_Pos (4U) +#define GPIO_SCR_IOSB4_Msk (0x1U << GPIO_SCR_IOSB4_Pos) /*!< 0x00000010 */ +#define GPIO_SCR_IOSB4 GPIO_SCR_IOSB4_Msk /*!< GPIO x set bit, pin 4 */ +#define GPIO_SCR_IOSB5_Pos (5U) +#define GPIO_SCR_IOSB5_Msk (0x1U << GPIO_SCR_IOSB5_Pos) /*!< 0x00000020 */ +#define GPIO_SCR_IOSB5 GPIO_SCR_IOSB5_Msk /*!< GPIO x set bit, pin 5 */ +#define GPIO_SCR_IOSB6_Pos (6U) +#define GPIO_SCR_IOSB6_Msk (0x1U << GPIO_SCR_IOSB6_Pos) /*!< 0x00000040 */ +#define GPIO_SCR_IOSB6 GPIO_SCR_IOSB6_Msk /*!< GPIO x set bit, pin 6 */ +#define GPIO_SCR_IOSB7_Pos (7U) +#define GPIO_SCR_IOSB7_Msk (0x1U << GPIO_SCR_IOSB7_Pos) /*!< 0x00000080 */ +#define GPIO_SCR_IOSB7 GPIO_SCR_IOSB7_Msk /*!< GPIO x set bit, pin 7 */ +#define GPIO_SCR_IOSB8_Pos (8U) +#define GPIO_SCR_IOSB8_Msk (0x1U << GPIO_SCR_IOSB8_Pos) /*!< 0x00000100 */ +#define GPIO_SCR_IOSB8 GPIO_SCR_IOSB8_Msk /*!< GPIO x set bit, pin 8 */ +#define GPIO_SCR_IOSB9_Pos (9U) +#define GPIO_SCR_IOSB9_Msk (0x1U << GPIO_SCR_IOSB9_Pos) /*!< 0x00000200 */ +#define GPIO_SCR_IOSB9 GPIO_SCR_IOSB9_Msk /*!< GPIO x set bit, pin 9 */ +#define GPIO_SCR_IOSB10_Pos (10U) +#define GPIO_SCR_IOSB10_Msk (0x1U << GPIO_SCR_IOSB10_Pos) /*!< 0x00000400 */ +#define GPIO_SCR_IOSB10 GPIO_SCR_IOSB10_Msk /*!< GPIO x set bit, pin 10 */ +#define GPIO_SCR_IOSB11_Pos (11U) +#define GPIO_SCR_IOSB11_Msk (0x1U << GPIO_SCR_IOSB11_Pos) /*!< 0x00000800 */ +#define GPIO_SCR_IOSB11 GPIO_SCR_IOSB11_Msk /*!< GPIO x set bit, pin 11 */ +#define GPIO_SCR_IOSB12_Pos (12U) +#define GPIO_SCR_IOSB12_Msk (0x1U << GPIO_SCR_IOSB12_Pos) /*!< 0x00001000 */ +#define GPIO_SCR_IOSB12 GPIO_SCR_IOSB12_Msk /*!< GPIO x set bit, pin 12 */ +#define GPIO_SCR_IOSB13_Pos (13U) +#define GPIO_SCR_IOSB13_Msk (0x1U << GPIO_SCR_IOSB13_Pos) /*!< 0x00002000 */ +#define GPIO_SCR_IOSB13 GPIO_SCR_IOSB13_Msk /*!< GPIO x set bit, pin 13 */ +#define GPIO_SCR_IOSB14_Pos (14U) +#define GPIO_SCR_IOSB14_Msk (0x1U << GPIO_SCR_IOSB14_Pos) /*!< 0x00004000 */ +#define GPIO_SCR_IOSB14 GPIO_SCR_IOSB14_Msk /*!< GPIO x set bit, pin 14 */ +#define GPIO_SCR_IOSB15_Pos (15U) +#define GPIO_SCR_IOSB15_Msk (0x1U << GPIO_SCR_IOSB15_Pos) /*!< 0x00008000 */ +#define GPIO_SCR_IOSB15 GPIO_SCR_IOSB15_Msk /*!< GPIO x set bit, pin 15 */ +#define GPIO_SCR_IOCB0_Pos (16U) +#define GPIO_SCR_IOCB0_Msk (0x1U << GPIO_SCR_IOCB0_Pos) /*!< 0x00010000 */ +#define GPIO_SCR_IOCB0 GPIO_SCR_IOCB0_Msk /*!< GPIO x clear bit, pin 0 */ +#define GPIO_SCR_IOCB1_Pos (17U) +#define GPIO_SCR_IOCB1_Msk (0x1U << GPIO_SCR_IOCB1_Pos) /*!< 0x00020000 */ +#define GPIO_SCR_IOCB1 GPIO_SCR_IOCB1_Msk /*!< GPIO x clear bit, pin 1 */ +#define GPIO_SCR_IOCB2_Pos (18U) +#define GPIO_SCR_IOCB2_Msk (0x1U << GPIO_SCR_IOCB2_Pos) /*!< 0x00040000 */ +#define GPIO_SCR_IOCB2 GPIO_SCR_IOCB2_Msk /*!< GPIO x clear bit, pin 2 */ +#define GPIO_SCR_IOCB3_Pos (19U) +#define GPIO_SCR_IOCB3_Msk (0x1U << GPIO_SCR_IOCB3_Pos) /*!< 0x00080000 */ +#define GPIO_SCR_IOCB3 GPIO_SCR_IOCB3_Msk /*!< GPIO x clear bit, pin 3 */ +#define GPIO_SCR_IOCB4_Pos (20U) +#define GPIO_SCR_IOCB4_Msk (0x1U << GPIO_SCR_IOCB4_Pos) /*!< 0x00100000 */ +#define GPIO_SCR_IOCB4 GPIO_SCR_IOCB4_Msk /*!< GPIO x clear bit, pin 4 */ +#define GPIO_SCR_IOCB5_Pos (21U) +#define GPIO_SCR_IOCB5_Msk (0x1U << GPIO_SCR_IOCB5_Pos) /*!< 0x00200000 */ +#define GPIO_SCR_IOCB5 GPIO_SCR_IOCB5_Msk /*!< GPIO x clear bit, pin 5 */ +#define GPIO_SCR_IOCB6_Pos (22U) +#define GPIO_SCR_IOCB6_Msk (0x1U << GPIO_SCR_IOCB6_Pos) /*!< 0x00400000 */ +#define GPIO_SCR_IOCB6 GPIO_SCR_IOCB6_Msk /*!< GPIO x clear bit, pin 6 */ +#define GPIO_SCR_IOCB7_Pos (23U) +#define GPIO_SCR_IOCB7_Msk (0x1U << GPIO_SCR_IOCB7_Pos) /*!< 0x00800000 */ +#define GPIO_SCR_IOCB7 GPIO_SCR_IOCB7_Msk /*!< GPIO x clear bit, pin 7 */ +#define GPIO_SCR_IOCB8_Pos (24U) +#define GPIO_SCR_IOCB8_Msk (0x1U << GPIO_SCR_IOCB8_Pos) /*!< 0x01000000 */ +#define GPIO_SCR_IOCB8 GPIO_SCR_IOCB8_Msk /*!< GPIO x clear bit, pin 8 */ +#define GPIO_SCR_IOCB9_Pos (25U) +#define GPIO_SCR_IOCB9_Msk (0x1U << GPIO_SCR_IOCB9_Pos) /*!< 0x02000000 */ +#define GPIO_SCR_IOCB9 GPIO_SCR_IOCB9_Msk /*!< GPIO x clear bit, pin 9 */ +#define GPIO_SCR_IOCB10_Pos (26U) +#define GPIO_SCR_IOCB10_Msk (0x1U << GPIO_SCR_IOCB10_Pos) /*!< 0x04000000 */ +#define GPIO_SCR_IOCB10 GPIO_SCR_IOCB10_Msk /*!< GPIO x clear bit, pin 10 */ +#define GPIO_SCR_IOCB11_Pos (27U) +#define GPIO_SCR_IOCB11_Msk (0x1U << GPIO_SCR_IOCB11_Pos) /*!< 0x08000000 */ +#define GPIO_SCR_IOCB11 GPIO_SCR_IOCB11_Msk /*!< GPIO x clear bit, pin 11 */ +#define GPIO_SCR_IOCB12_Pos (28U) +#define GPIO_SCR_IOCB12_Msk (0x1U << GPIO_SCR_IOCB12_Pos) /*!< 0x10000000 */ +#define GPIO_SCR_IOCB12 GPIO_SCR_IOCB12_Msk /*!< GPIO x clear bit, pin 12 */ +#define GPIO_SCR_IOCB13_Pos (29U) +#define GPIO_SCR_IOCB13_Msk (0x1U << GPIO_SCR_IOCB13_Pos) /*!< 0x20000000 */ +#define GPIO_SCR_IOCB13 GPIO_SCR_IOCB13_Msk /*!< GPIO x clear bit, pin 13 */ +#define GPIO_SCR_IOCB14_Pos (30U) +#define GPIO_SCR_IOCB14_Msk (0x1U << GPIO_SCR_IOCB14_Pos) /*!< 0x40000000 */ +#define GPIO_SCR_IOCB14 GPIO_SCR_IOCB14_Msk /*!< GPIO x clear bit, pin 14 */ +#define GPIO_SCR_IOCB15_Pos (31U) +#define GPIO_SCR_IOCB15_Msk (0x1U << GPIO_SCR_IOCB15_Pos) /*!< 0x80000000 */ +#define GPIO_SCR_IOCB15 GPIO_SCR_IOCB15_Msk /*!< GPIO x clear bit, pin 15 */ + +/******************* Bit definition for GPIO_WPR register *******************/ +#define GPIO_WPR_WPEN0_Pos (0U) +#define GPIO_WPR_WPEN0_Msk (0x1U << GPIO_WPR_WPEN0_Pos) /*!< 0x00000001 */ +#define GPIO_WPR_WPEN0 GPIO_WPR_WPEN0_Msk /*!< Write protect enable, pin 0 */ +#define GPIO_WPR_WPEN1_Pos (1U) +#define GPIO_WPR_WPEN1_Msk (0x1U << GPIO_WPR_WPEN1_Pos) /*!< 0x00000002 */ +#define GPIO_WPR_WPEN1 GPIO_WPR_WPEN1_Msk /*!< Write protect enable, pin 1 */ +#define GPIO_WPR_WPEN2_Pos (2U) +#define GPIO_WPR_WPEN2_Msk (0x1U << GPIO_WPR_WPEN2_Pos) /*!< 0x00000004 */ +#define GPIO_WPR_WPEN2 GPIO_WPR_WPEN2_Msk /*!< Write protect enable, pin 2 */ +#define GPIO_WPR_WPEN3_Pos (3U) +#define GPIO_WPR_WPEN3_Msk (0x1U << GPIO_WPR_WPEN3_Pos) /*!< 0x00000008 */ +#define GPIO_WPR_WPEN3 GPIO_WPR_WPEN3_Msk /*!< Write protect enable, pin 3 */ +#define GPIO_WPR_WPEN4_Pos (4U) +#define GPIO_WPR_WPEN4_Msk (0x1U << GPIO_WPR_WPEN4_Pos) /*!< 0x00000010 */ +#define GPIO_WPR_WPEN4 GPIO_WPR_WPEN4_Msk /*!< Write protect enable, pin 4 */ +#define GPIO_WPR_WPEN5_Pos (5U) +#define GPIO_WPR_WPEN5_Msk (0x1U << GPIO_WPR_WPEN5_Pos) /*!< 0x00000020 */ +#define GPIO_WPR_WPEN5 GPIO_WPR_WPEN5_Msk /*!< Write protect enable, pin 5 */ +#define GPIO_WPR_WPEN6_Pos (6U) +#define GPIO_WPR_WPEN6_Msk (0x1U << GPIO_WPR_WPEN6_Pos) /*!< 0x00000040 */ +#define GPIO_WPR_WPEN6 GPIO_WPR_WPEN6_Msk /*!< Write protect enable, pin 6 */ +#define GPIO_WPR_WPEN7_Pos (7U) +#define GPIO_WPR_WPEN7_Msk (0x1U << GPIO_WPR_WPEN7_Pos) /*!< 0x00000080 */ +#define GPIO_WPR_WPEN7 GPIO_WPR_WPEN7_Msk /*!< Write protect enable, pin 7 */ +#define GPIO_WPR_WPEN8_Pos (8U) +#define GPIO_WPR_WPEN8_Msk (0x1U << GPIO_WPR_WPEN8_Pos) /*!< 0x00000100 */ +#define GPIO_WPR_WPEN8 GPIO_WPR_WPEN8_Msk /*!< Write protect enable, pin 8 */ +#define GPIO_WPR_WPEN9_Pos (9U) +#define GPIO_WPR_WPEN9_Msk (0x1U << GPIO_WPR_WPEN9_Pos) /*!< 0x00000200 */ +#define GPIO_WPR_WPEN9 GPIO_WPR_WPEN9_Msk /*!< Write protect enable, pin 9 */ +#define GPIO_WPR_WPEN10_Pos (10U) +#define GPIO_WPR_WPEN10_Msk (0x1U << GPIO_WPR_WPEN10_Pos) /*!< 0x00000400 */ +#define GPIO_WPR_WPEN10 GPIO_WPR_WPEN10_Msk /*!< Write protect enable, pin 10 */ +#define GPIO_WPR_WPEN11_Pos (11U) +#define GPIO_WPR_WPEN11_Msk (0x1U << GPIO_WPR_WPEN11_Pos) /*!< 0x00000800 */ +#define GPIO_WPR_WPEN11 GPIO_WPR_WPEN11_Msk /*!< Write protect enable, pin 11 */ +#define GPIO_WPR_WPEN12_Pos (12U) +#define GPIO_WPR_WPEN12_Msk (0x1U << GPIO_WPR_WPEN12_Pos) /*!< 0x00001000 */ +#define GPIO_WPR_WPEN12 GPIO_WPR_WPEN12_Msk /*!< Write protect enable, pin 12 */ +#define GPIO_WPR_WPEN13_Pos (13U) +#define GPIO_WPR_WPEN13_Msk (0x1U << GPIO_WPR_WPEN13_Pos) /*!< 0x00002000 */ +#define GPIO_WPR_WPEN13 GPIO_WPR_WPEN13_Msk /*!< Write protect enable, pin 13 */ +#define GPIO_WPR_WPEN14_Pos (14U) +#define GPIO_WPR_WPEN14_Msk (0x1U << GPIO_WPR_WPEN14_Pos) /*!< 0x00004000 */ +#define GPIO_WPR_WPEN14 GPIO_WPR_WPEN14_Msk /*!< Write protect enable, pin 14 */ +#define GPIO_WPR_WPEN15_Pos (15U) +#define GPIO_WPR_WPEN15_Msk (0x1U << GPIO_WPR_WPEN15_Pos) /*!< 0x00008000 */ +#define GPIO_WPR_WPEN15 GPIO_WPR_WPEN15_Msk /*!< Write protect enable, pin 15 */ +#define GPIO_WPR_WPSEQ_Pos (16U) +#define GPIO_WPR_WPSEQ_Msk (0x1U << GPIO_WPR_WPSEQ_Pos) /*!< 0x00010000 */ +#define GPIO_WPR_WPSEQ GPIO_WPR_WPSEQ_Msk /*!< Write protect sequence */ + +/****************** Bit definition for GPIO_MUXL register *******************/ +#define GPIO_MUXL_MUXL_Pos (0U) +#define GPIO_MUXL_MUXL_Msk (0xFFFFFFFFU << GPIO_MUXL_MUXL_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_MUXL_MUXL GPIO_MUXL_MUXL_Msk /*!< Multiplexed function select for GPIO x */ + +/*!< MUXL0 configuration */ +#define GPIO_MUXL_MUXL0_Pos (0U) +#define GPIO_MUXL_MUXL0_Msk (0xFU << GPIO_MUXL_MUXL0_Pos) /*!< 0x0000000F */ +#define GPIO_MUXL_MUXL0 GPIO_MUXL_MUXL0_Msk /*!< MUXL0[3:0] bits (Multiplexed function select for GPIO x, pin 0) */ +#define GPIO_MUXL_MUXL0_0 (0x1U << GPIO_MUXL_MUXL0_Pos) /*!< 0x00000001 */ +#define GPIO_MUXL_MUXL0_1 (0x2U << GPIO_MUXL_MUXL0_Pos) /*!< 0x00000002 */ +#define GPIO_MUXL_MUXL0_2 (0x4U << GPIO_MUXL_MUXL0_Pos) /*!< 0x00000004 */ +#define GPIO_MUXL_MUXL0_3 (0x8U << GPIO_MUXL_MUXL0_Pos) /*!< 0x00000008 */ + +/*!< MUXL1 configuration */ +#define GPIO_MUXL_MUXL1_Pos (4U) +#define GPIO_MUXL_MUXL1_Msk (0xFU << GPIO_MUXL_MUXL1_Pos) /*!< 0x000000F0 */ +#define GPIO_MUXL_MUXL1 GPIO_MUXL_MUXL1_Msk /*!< MUXL1[3:0] bits (Multiplexed function select for GPIO x, pin 1) */ +#define GPIO_MUXL_MUXL1_0 (0x1U << GPIO_MUXL_MUXL1_Pos) /*!< 0x00000010 */ +#define GPIO_MUXL_MUXL1_1 (0x2U << GPIO_MUXL_MUXL1_Pos) /*!< 0x00000020 */ +#define GPIO_MUXL_MUXL1_2 (0x4U << GPIO_MUXL_MUXL1_Pos) /*!< 0x00000040 */ +#define GPIO_MUXL_MUXL1_3 (0x8U << GPIO_MUXL_MUXL1_Pos) /*!< 0x00000080 */ + +/*!< MUXL2 configuration */ +#define GPIO_MUXL_MUXL2_Pos (8U) +#define GPIO_MUXL_MUXL2_Msk (0xFU << GPIO_MUXL_MUXL2_Pos) /*!< 0x00000F00 */ +#define GPIO_MUXL_MUXL2 GPIO_MUXL_MUXL2_Msk /*!< MUXL2[3:0] bits (Multiplexed function select for GPIO x, pin 2) */ +#define GPIO_MUXL_MUXL2_0 (0x1U << GPIO_MUXL_MUXL2_Pos) /*!< 0x00000100 */ +#define GPIO_MUXL_MUXL2_1 (0x2U << GPIO_MUXL_MUXL2_Pos) /*!< 0x00000200 */ +#define GPIO_MUXL_MUXL2_2 (0x4U << GPIO_MUXL_MUXL2_Pos) /*!< 0x00000400 */ +#define GPIO_MUXL_MUXL2_3 (0x8U << GPIO_MUXL_MUXL2_Pos) /*!< 0x00000800 */ + +/*!< MUXL3 configuration */ +#define GPIO_MUXL_MUXL3_Pos (12U) +#define GPIO_MUXL_MUXL3_Msk (0xFU << GPIO_MUXL_MUXL3_Pos) /*!< 0x0000F000 */ +#define GPIO_MUXL_MUXL3 GPIO_MUXL_MUXL3_Msk /*!< MUXL3[3:0] bits (Multiplexed function select for GPIO x, pin 3) */ +#define GPIO_MUXL_MUXL3_0 (0x1U << GPIO_MUXL_MUXL3_Pos) /*!< 0x00001000 */ +#define GPIO_MUXL_MUXL3_1 (0x2U << GPIO_MUXL_MUXL3_Pos) /*!< 0x00002000 */ +#define GPIO_MUXL_MUXL3_2 (0x4U << GPIO_MUXL_MUXL3_Pos) /*!< 0x00004000 */ +#define GPIO_MUXL_MUXL3_3 (0x8U << GPIO_MUXL_MUXL3_Pos) /*!< 0x00008000 */ + +/*!< MUXL4 configuration */ +#define GPIO_MUXL_MUXL4_Pos (16U) +#define GPIO_MUXL_MUXL4_Msk (0xFU << GPIO_MUXL_MUXL4_Pos) /*!< 0x000F0000 */ +#define GPIO_MUXL_MUXL4 GPIO_MUXL_MUXL4_Msk /*!< MUXL4[3:0] bits (Multiplexed function select for GPIO x, pin 4) */ +#define GPIO_MUXL_MUXL4_0 (0x1U << GPIO_MUXL_MUXL4_Pos) /*!< 0x00010000 */ +#define GPIO_MUXL_MUXL4_1 (0x2U << GPIO_MUXL_MUXL4_Pos) /*!< 0x00020000 */ +#define GPIO_MUXL_MUXL4_2 (0x4U << GPIO_MUXL_MUXL4_Pos) /*!< 0x00040000 */ +#define GPIO_MUXL_MUXL4_3 (0x8U << GPIO_MUXL_MUXL4_Pos) /*!< 0x00080000 */ + +/*!< MUXL5 configuration */ +#define GPIO_MUXL_MUXL5_Pos (20U) +#define GPIO_MUXL_MUXL5_Msk (0xFU << GPIO_MUXL_MUXL5_Pos) /*!< 0x00F00000 */ +#define GPIO_MUXL_MUXL5 GPIO_MUXL_MUXL5_Msk /*!< MUXL5[3:0] bits (Multiplexed function select for GPIO x, pin 5) */ +#define GPIO_MUXL_MUXL5_0 (0x1U << GPIO_MUXL_MUXL5_Pos) /*!< 0x00100000 */ +#define GPIO_MUXL_MUXL5_1 (0x2U << GPIO_MUXL_MUXL5_Pos) /*!< 0x00200000 */ +#define GPIO_MUXL_MUXL5_2 (0x4U << GPIO_MUXL_MUXL5_Pos) /*!< 0x00400000 */ +#define GPIO_MUXL_MUXL5_3 (0x8U << GPIO_MUXL_MUXL5_Pos) /*!< 0x00800000 */ + +/*!< MUXL6 configuration */ +#define GPIO_MUXL_MUXL6_Pos (24U) +#define GPIO_MUXL_MUXL6_Msk (0xFU << GPIO_MUXL_MUXL6_Pos) /*!< 0x0F000000 */ +#define GPIO_MUXL_MUXL6 GPIO_MUXL_MUXL6_Msk /*!< MUXL6[3:0] bits (Multiplexed function select for GPIO x, pin 6) */ +#define GPIO_MUXL_MUXL6_0 (0x1U << GPIO_MUXL_MUXL6_Pos) /*!< 0x01000000 */ +#define GPIO_MUXL_MUXL6_1 (0x2U << GPIO_MUXL_MUXL6_Pos) /*!< 0x02000000 */ +#define GPIO_MUXL_MUXL6_2 (0x4U << GPIO_MUXL_MUXL6_Pos) /*!< 0x04000000 */ +#define GPIO_MUXL_MUXL6_3 (0x8U << GPIO_MUXL_MUXL6_Pos) /*!< 0x08000000 */ + +/*!< MUXL7 configuration */ +#define GPIO_MUXL_MUXL7_Pos (28U) +#define GPIO_MUXL_MUXL7_Msk (0xFU << GPIO_MUXL_MUXL7_Pos) /*!< 0xF0000000 */ +#define GPIO_MUXL_MUXL7 GPIO_MUXL_MUXL7_Msk /*!< MUXL7[3:0] bits (Multiplexed function select for GPIO x, pin 7) */ +#define GPIO_MUXL_MUXL7_0 (0x1U << GPIO_MUXL_MUXL7_Pos) /*!< 0x10000000 */ +#define GPIO_MUXL_MUXL7_1 (0x2U << GPIO_MUXL_MUXL7_Pos) /*!< 0x20000000 */ +#define GPIO_MUXL_MUXL7_2 (0x4U << GPIO_MUXL_MUXL7_Pos) /*!< 0x40000000 */ +#define GPIO_MUXL_MUXL7_3 (0x8U << GPIO_MUXL_MUXL7_Pos) /*!< 0x80000000 */ + +/****************** Bit definition for GPIO_MUXH register *******************/ +#define GPIO_MUXH_MUXH_Pos (0U) +#define GPIO_MUXH_MUXH_Msk (0xFFFFFFFFU << GPIO_MUXH_MUXH_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_MUXH_MUXH GPIO_MUXH_MUXH_Msk /*!< Multiplexed function select for GPIO x */ + +/*!< MUXH8 configuration */ +#define GPIO_MUXH_MUXH8_Pos (0U) +#define GPIO_MUXH_MUXH8_Msk (0xFU << GPIO_MUXH_MUXH8_Pos) /*!< 0x0000000F */ +#define GPIO_MUXH_MUXH8 GPIO_MUXH_MUXH8_Msk /*!< MUXH8[3:0] bits (Multiplexed function select for GPIO x, pin 8) */ +#define GPIO_MUXH_MUXH8_0 (0x1U << GPIO_MUXH_MUXH8_Pos) /*!< 0x00000001 */ +#define GPIO_MUXH_MUXH8_1 (0x2U << GPIO_MUXH_MUXH8_Pos) /*!< 0x00000002 */ +#define GPIO_MUXH_MUXH8_2 (0x4U << GPIO_MUXH_MUXH8_Pos) /*!< 0x00000004 */ +#define GPIO_MUXH_MUXH8_3 (0x8U << GPIO_MUXH_MUXH8_Pos) /*!< 0x00000008 */ + +/*!< MUXH9 configuration */ +#define GPIO_MUXH_MUXH9_Pos (4U) +#define GPIO_MUXH_MUXH9_Msk (0xFU << GPIO_MUXH_MUXH9_Pos) /*!< 0x000000F0 */ +#define GPIO_MUXH_MUXH9 GPIO_MUXH_MUXH9_Msk /*!< MUXH9[3:0] bits (Multiplexed function select for GPIO x, pin 9) */ +#define GPIO_MUXH_MUXH9_0 (0x1U << GPIO_MUXH_MUXH9_Pos) /*!< 0x00000010 */ +#define GPIO_MUXH_MUXH9_1 (0x2U << GPIO_MUXH_MUXH9_Pos) /*!< 0x00000020 */ +#define GPIO_MUXH_MUXH9_2 (0x4U << GPIO_MUXH_MUXH9_Pos) /*!< 0x00000040 */ +#define GPIO_MUXH_MUXH9_3 (0x8U << GPIO_MUXH_MUXH9_Pos) /*!< 0x00000080 */ + +/*!< MUXH10 configuration */ +#define GPIO_MUXH_MUXH10_Pos (8U) +#define GPIO_MUXH_MUXH10_Msk (0xFU << GPIO_MUXH_MUXH10_Pos) /*!< 0x00000F00 */ +#define GPIO_MUXH_MUXH10 GPIO_MUXH_MUXH10_Msk /*!< MUXH10[3:0] bits (Multiplexed function select for GPIO x, pin 10) */ +#define GPIO_MUXH_MUXH10_0 (0x1U << GPIO_MUXH_MUXH10_Pos) /*!< 0x00000100 */ +#define GPIO_MUXH_MUXH10_1 (0x2U << GPIO_MUXH_MUXH10_Pos) /*!< 0x00000200 */ +#define GPIO_MUXH_MUXH10_2 (0x4U << GPIO_MUXH_MUXH10_Pos) /*!< 0x00000400 */ +#define GPIO_MUXH_MUXH10_3 (0x8U << GPIO_MUXH_MUXH10_Pos) /*!< 0x00000800 */ + +/*!< MUXH11 configuration */ +#define GPIO_MUXH_MUXH11_Pos (12U) +#define GPIO_MUXH_MUXH11_Msk (0xFU << GPIO_MUXH_MUXH11_Pos) /*!< 0x0000F000 */ +#define GPIO_MUXH_MUXH11 GPIO_MUXH_MUXH11_Msk /*!< MUXH11[3:0] bits (Multiplexed function select for GPIO x, pin 11) */ +#define GPIO_MUXH_MUXH11_0 (0x1U << GPIO_MUXH_MUXH11_Pos) /*!< 0x00001000 */ +#define GPIO_MUXH_MUXH11_1 (0x2U << GPIO_MUXH_MUXH11_Pos) /*!< 0x00002000 */ +#define GPIO_MUXH_MUXH11_2 (0x4U << GPIO_MUXH_MUXH11_Pos) /*!< 0x00004000 */ +#define GPIO_MUXH_MUXH11_3 (0x8U << GPIO_MUXH_MUXH11_Pos) /*!< 0x00008000 */ + +/*!< MUXH12 configuration */ +#define GPIO_MUXH_MUXH12_Pos (16U) +#define GPIO_MUXH_MUXH12_Msk (0xFU << GPIO_MUXH_MUXH12_Pos) /*!< 0x000F0000 */ +#define GPIO_MUXH_MUXH12 GPIO_MUXH_MUXH12_Msk /*!< MUXH12[3:0] bits (Multiplexed function select for GPIO x, pin 12) */ +#define GPIO_MUXH_MUXH12_0 (0x1U << GPIO_MUXH_MUXH12_Pos) /*!< 0x00010000 */ +#define GPIO_MUXH_MUXH12_1 (0x2U << GPIO_MUXH_MUXH12_Pos) /*!< 0x00020000 */ +#define GPIO_MUXH_MUXH12_2 (0x4U << GPIO_MUXH_MUXH12_Pos) /*!< 0x00040000 */ +#define GPIO_MUXH_MUXH12_3 (0x8U << GPIO_MUXH_MUXH12_Pos) /*!< 0x00080000 */ + +/*!< MUXH13 configuration */ +#define GPIO_MUXH_MUXH13_Pos (20U) +#define GPIO_MUXH_MUXH13_Msk (0xFU << GPIO_MUXH_MUXH13_Pos) /*!< 0x00F00000 */ +#define GPIO_MUXH_MUXH13 GPIO_MUXH_MUXH13_Msk /*!< MUXH13[3:0] bits (Multiplexed function select for GPIO x, pin 13) */ +#define GPIO_MUXH_MUXH13_0 (0x1U << GPIO_MUXH_MUXH13_Pos) /*!< 0x00100000 */ +#define GPIO_MUXH_MUXH13_1 (0x2U << GPIO_MUXH_MUXH13_Pos) /*!< 0x00200000 */ +#define GPIO_MUXH_MUXH13_2 (0x4U << GPIO_MUXH_MUXH13_Pos) /*!< 0x00400000 */ +#define GPIO_MUXH_MUXH13_3 (0x8U << GPIO_MUXH_MUXH13_Pos) /*!< 0x00800000 */ + +/*!< MUXH14 configuration */ +#define GPIO_MUXH_MUXH14_Pos (24U) +#define GPIO_MUXH_MUXH14_Msk (0xFU << GPIO_MUXH_MUXH14_Pos) /*!< 0x0F000000 */ +#define GPIO_MUXH_MUXH14 GPIO_MUXH_MUXH14_Msk /*!< MUXH14[3:0] bits (Multiplexed function select for GPIO x, pin 14) */ +#define GPIO_MUXH_MUXH14_0 (0x1U << GPIO_MUXH_MUXH14_Pos) /*!< 0x01000000 */ +#define GPIO_MUXH_MUXH14_1 (0x2U << GPIO_MUXH_MUXH14_Pos) /*!< 0x02000000 */ +#define GPIO_MUXH_MUXH14_2 (0x4U << GPIO_MUXH_MUXH14_Pos) /*!< 0x04000000 */ +#define GPIO_MUXH_MUXH14_3 (0x8U << GPIO_MUXH_MUXH14_Pos) /*!< 0x08000000 */ + +/*!< MUXH15 configuration */ +#define GPIO_MUXH_MUXH15_Pos (28U) +#define GPIO_MUXH_MUXH15_Msk (0xFU << GPIO_MUXH_MUXH15_Pos) /*!< 0xF0000000 */ +#define GPIO_MUXH_MUXH15 GPIO_MUXH_MUXH15_Msk /*!< MUXH15[3:0] bits (Multiplexed function select for GPIO x, pin 15) */ +#define GPIO_MUXH_MUXH15_0 (0x1U << GPIO_MUXH_MUXH15_Pos) /*!< 0x10000000 */ +#define GPIO_MUXH_MUXH15_1 (0x2U << GPIO_MUXH_MUXH15_Pos) /*!< 0x20000000 */ +#define GPIO_MUXH_MUXH15_2 (0x4U << GPIO_MUXH_MUXH15_Pos) /*!< 0x40000000 */ +#define GPIO_MUXH_MUXH15_3 (0x8U << GPIO_MUXH_MUXH15_Pos) /*!< 0x80000000 */ + +/******************* Bit definition for GPIO_CLR register *******************/ +#define GPIO_CLR_IOCB0_Pos (0U) +#define GPIO_CLR_IOCB0_Msk (0x1U << GPIO_CLR_IOCB0_Pos) /*!< 0x00000001 */ +#define GPIO_CLR_IOCB0 GPIO_CLR_IOCB0_Msk /*!< GPIO x clear bit, pin 0 */ +#define GPIO_CLR_IOCB1_Pos (1U) +#define GPIO_CLR_IOCB1_Msk (0x1U << GPIO_CLR_IOCB1_Pos) /*!< 0x00000002 */ +#define GPIO_CLR_IOCB1 GPIO_CLR_IOCB1_Msk /*!< GPIO x clear bit, pin 1 */ +#define GPIO_CLR_IOCB2_Pos (2U) +#define GPIO_CLR_IOCB2_Msk (0x1U << GPIO_CLR_IOCB2_Pos) /*!< 0x00000004 */ +#define GPIO_CLR_IOCB2 GPIO_CLR_IOCB2_Msk /*!< GPIO x clear bit, pin 2 */ +#define GPIO_CLR_IOCB3_Pos (3U) +#define GPIO_CLR_IOCB3_Msk (0x1U << GPIO_CLR_IOCB3_Pos) /*!< 0x00000008 */ +#define GPIO_CLR_IOCB3 GPIO_CLR_IOCB3_Msk /*!< GPIO x clear bit, pin 3 */ +#define GPIO_CLR_IOCB4_Pos (4U) +#define GPIO_CLR_IOCB4_Msk (0x1U << GPIO_CLR_IOCB4_Pos) /*!< 0x00000010 */ +#define GPIO_CLR_IOCB4 GPIO_CLR_IOCB4_Msk /*!< GPIO x clear bit, pin 4 */ +#define GPIO_CLR_IOCB5_Pos (5U) +#define GPIO_CLR_IOCB5_Msk (0x1U << GPIO_CLR_IOCB5_Pos) /*!< 0x00000020 */ +#define GPIO_CLR_IOCB5 GPIO_CLR_IOCB5_Msk /*!< GPIO x clear bit, pin 5 */ +#define GPIO_CLR_IOCB6_Pos (6U) +#define GPIO_CLR_IOCB6_Msk (0x1U << GPIO_CLR_IOCB6_Pos) /*!< 0x00000040 */ +#define GPIO_CLR_IOCB6 GPIO_CLR_IOCB6_Msk /*!< GPIO x clear bit, pin 6 */ +#define GPIO_CLR_IOCB7_Pos (7U) +#define GPIO_CLR_IOCB7_Msk (0x1U << GPIO_CLR_IOCB7_Pos) /*!< 0x00000080 */ +#define GPIO_CLR_IOCB7 GPIO_CLR_IOCB7_Msk /*!< GPIO x clear bit, pin 7 */ +#define GPIO_CLR_IOCB8_Pos (8U) +#define GPIO_CLR_IOCB8_Msk (0x1U << GPIO_CLR_IOCB8_Pos) /*!< 0x00000100 */ +#define GPIO_CLR_IOCB8 GPIO_CLR_IOCB8_Msk /*!< GPIO x clear bit, pin 8 */ +#define GPIO_CLR_IOCB9_Pos (9U) +#define GPIO_CLR_IOCB9_Msk (0x1U << GPIO_CLR_IOCB9_Pos) /*!< 0x00000200 */ +#define GPIO_CLR_IOCB9 GPIO_CLR_IOCB9_Msk /*!< GPIO x clear bit, pin 9 */ +#define GPIO_CLR_IOCB10_Pos (10U) +#define GPIO_CLR_IOCB10_Msk (0x1U << GPIO_CLR_IOCB10_Pos) /*!< 0x00000400 */ +#define GPIO_CLR_IOCB10 GPIO_CLR_IOCB10_Msk /*!< GPIO x clear bit, pin 10 */ +#define GPIO_CLR_IOCB11_Pos (11U) +#define GPIO_CLR_IOCB11_Msk (0x1U << GPIO_CLR_IOCB11_Pos) /*!< 0x00000800 */ +#define GPIO_CLR_IOCB11 GPIO_CLR_IOCB11_Msk /*!< GPIO x clear bit, pin 11 */ +#define GPIO_CLR_IOCB12_Pos (12U) +#define GPIO_CLR_IOCB12_Msk (0x1U << GPIO_CLR_IOCB12_Pos) /*!< 0x00001000 */ +#define GPIO_CLR_IOCB12 GPIO_CLR_IOCB12_Msk /*!< GPIO x clear bit, pin 12 */ +#define GPIO_CLR_IOCB13_Pos (13U) +#define GPIO_CLR_IOCB13_Msk (0x1U << GPIO_CLR_IOCB13_Pos) /*!< 0x00002000 */ +#define GPIO_CLR_IOCB13 GPIO_CLR_IOCB13_Msk /*!< GPIO x clear bit, pin 13 */ +#define GPIO_CLR_IOCB14_Pos (14U) +#define GPIO_CLR_IOCB14_Msk (0x1U << GPIO_CLR_IOCB14_Pos) /*!< 0x00004000 */ +#define GPIO_CLR_IOCB14 GPIO_CLR_IOCB14_Msk /*!< GPIO x clear bit, pin 14 */ +#define GPIO_CLR_IOCB15_Pos (15U) +#define GPIO_CLR_IOCB15_Msk (0x1U << GPIO_CLR_IOCB15_Pos) /*!< 0x00008000 */ +#define GPIO_CLR_IOCB15 GPIO_CLR_IOCB15_Msk /*!< GPIO x clear bit, pin 15 */ + +/****************** Bit definition for GPIO_TOGR register *******************/ +#define GPIO_TOGR_IOTB0_Pos (0U) +#define GPIO_TOGR_IOTB0_Msk (0x1U << GPIO_TOGR_IOTB0_Pos) /*!< 0x00000001 */ +#define GPIO_TOGR_IOTB0 GPIO_TOGR_IOTB0_Msk /*!< GPIO x toggle bit, pin 0 */ +#define GPIO_TOGR_IOTB1_Pos (1U) +#define GPIO_TOGR_IOTB1_Msk (0x1U << GPIO_TOGR_IOTB1_Pos) /*!< 0x00000002 */ +#define GPIO_TOGR_IOTB1 GPIO_TOGR_IOTB1_Msk /*!< GPIO x toggle bit, pin 1 */ +#define GPIO_TOGR_IOTB2_Pos (2U) +#define GPIO_TOGR_IOTB2_Msk (0x1U << GPIO_TOGR_IOTB2_Pos) /*!< 0x00000004 */ +#define GPIO_TOGR_IOTB2 GPIO_TOGR_IOTB2_Msk /*!< GPIO x toggle bit, pin 2 */ +#define GPIO_TOGR_IOTB3_Pos (3U) +#define GPIO_TOGR_IOTB3_Msk (0x1U << GPIO_TOGR_IOTB3_Pos) /*!< 0x00000008 */ +#define GPIO_TOGR_IOTB3 GPIO_TOGR_IOTB3_Msk /*!< GPIO x toggle bit, pin 3 */ +#define GPIO_TOGR_IOTB4_Pos (4U) +#define GPIO_TOGR_IOTB4_Msk (0x1U << GPIO_TOGR_IOTB4_Pos) /*!< 0x00000010 */ +#define GPIO_TOGR_IOTB4 GPIO_TOGR_IOTB4_Msk /*!< GPIO x toggle bit, pin 4 */ +#define GPIO_TOGR_IOTB5_Pos (5U) +#define GPIO_TOGR_IOTB5_Msk (0x1U << GPIO_TOGR_IOTB5_Pos) /*!< 0x00000020 */ +#define GPIO_TOGR_IOTB5 GPIO_TOGR_IOTB5_Msk /*!< GPIO x toggle bit, pin 5 */ +#define GPIO_TOGR_IOTB6_Pos (6U) +#define GPIO_TOGR_IOTB6_Msk (0x1U << GPIO_TOGR_IOTB6_Pos) /*!< 0x00000040 */ +#define GPIO_TOGR_IOTB6 GPIO_TOGR_IOTB6_Msk /*!< GPIO x toggle bit, pin 6 */ +#define GPIO_TOGR_IOTB7_Pos (7U) +#define GPIO_TOGR_IOTB7_Msk (0x1U << GPIO_TOGR_IOTB7_Pos) /*!< 0x00000080 */ +#define GPIO_TOGR_IOTB7 GPIO_TOGR_IOTB7_Msk /*!< GPIO x toggle bit, pin 7 */ +#define GPIO_TOGR_IOTB8_Pos (8U) +#define GPIO_TOGR_IOTB8_Msk (0x1U << GPIO_TOGR_IOTB8_Pos) /*!< 0x00000100 */ +#define GPIO_TOGR_IOTB8 GPIO_TOGR_IOTB8_Msk /*!< GPIO x toggle bit, pin 8 */ +#define GPIO_TOGR_IOTB9_Pos (9U) +#define GPIO_TOGR_IOTB9_Msk (0x1U << GPIO_TOGR_IOTB9_Pos) /*!< 0x00000200 */ +#define GPIO_TOGR_IOTB9 GPIO_TOGR_IOTB9_Msk /*!< GPIO x toggle bit, pin 9 */ +#define GPIO_TOGR_IOTB10_Pos (10U) +#define GPIO_TOGR_IOTB10_Msk (0x1U << GPIO_TOGR_IOTB10_Pos) /*!< 0x00000400 */ +#define GPIO_TOGR_IOTB10 GPIO_TOGR_IOTB10_Msk /*!< GPIO x toggle bit, pin 10 */ +#define GPIO_TOGR_IOTB11_Pos (11U) +#define GPIO_TOGR_IOTB11_Msk (0x1U << GPIO_TOGR_IOTB11_Pos) /*!< 0x00000800 */ +#define GPIO_TOGR_IOTB11 GPIO_TOGR_IOTB11_Msk /*!< GPIO x toggle bit, pin 11 */ +#define GPIO_TOGR_IOTB12_Pos (12U) +#define GPIO_TOGR_IOTB12_Msk (0x1U << GPIO_TOGR_IOTB12_Pos) /*!< 0x00001000 */ +#define GPIO_TOGR_IOTB12 GPIO_TOGR_IOTB12_Msk /*!< GPIO x toggle bit, pin 12 */ +#define GPIO_TOGR_IOTB13_Pos (13U) +#define GPIO_TOGR_IOTB13_Msk (0x1U << GPIO_TOGR_IOTB13_Pos) /*!< 0x00002000 */ +#define GPIO_TOGR_IOTB13 GPIO_TOGR_IOTB13_Msk /*!< GPIO x toggle bit, pin 13 */ +#define GPIO_TOGR_IOTB14_Pos (14U) +#define GPIO_TOGR_IOTB14_Msk (0x1U << GPIO_TOGR_IOTB14_Pos) /*!< 0x00004000 */ +#define GPIO_TOGR_IOTB14 GPIO_TOGR_IOTB14_Msk /*!< GPIO x toggle bit, pin 14 */ +#define GPIO_TOGR_IOTB15_Pos (15U) +#define GPIO_TOGR_IOTB15_Msk (0x1U << GPIO_TOGR_IOTB15_Pos) /*!< 0x00008000 */ +#define GPIO_TOGR_IOTB15 GPIO_TOGR_IOTB15_Msk /*!< GPIO x toggle bit, pin 15 */ + +/****************** Bit definition for GPIO_HDRV register *******************/ +#define GPIO_HDRV_HDRV0_Pos (0U) +#define GPIO_HDRV_HDRV0_Msk (0x1U << GPIO_HDRV_HDRV0_Pos) /*!< 0x00000001 */ +#define GPIO_HDRV_HDRV0 GPIO_HDRV_HDRV0_Msk /*!< GPIO x huge sourcing/sinking strength control, pin 0 */ +#define GPIO_HDRV_HDRV1_Pos (1U) +#define GPIO_HDRV_HDRV1_Msk (0x1U << GPIO_HDRV_HDRV1_Pos) /*!< 0x00000002 */ +#define GPIO_HDRV_HDRV1 GPIO_HDRV_HDRV1_Msk /*!< GPIO x huge sourcing/sinking strength control, pin 1 */ +#define GPIO_HDRV_HDRV2_Pos (2U) +#define GPIO_HDRV_HDRV2_Msk (0x1U << GPIO_HDRV_HDRV2_Pos) /*!< 0x00000004 */ +#define GPIO_HDRV_HDRV2 GPIO_HDRV_HDRV2_Msk /*!< GPIO x huge sourcing/sinking strength control, pin 2 */ +#define GPIO_HDRV_HDRV3_Pos (3U) +#define GPIO_HDRV_HDRV3_Msk (0x1U << GPIO_HDRV_HDRV3_Pos) /*!< 0x00000008 */ +#define GPIO_HDRV_HDRV3 GPIO_HDRV_HDRV3_Msk /*!< GPIO x huge sourcing/sinking strength control, pin 3 */ +#define GPIO_HDRV_HDRV4_Pos (4U) +#define GPIO_HDRV_HDRV4_Msk (0x1U << GPIO_HDRV_HDRV4_Pos) /*!< 0x00000010 */ +#define GPIO_HDRV_HDRV4 GPIO_HDRV_HDRV4_Msk /*!< GPIO x huge sourcing/sinking strength control, pin 4 */ +#define GPIO_HDRV_HDRV5_Pos (5U) +#define GPIO_HDRV_HDRV5_Msk (0x1U << GPIO_HDRV_HDRV5_Pos) /*!< 0x00000020 */ +#define GPIO_HDRV_HDRV5 GPIO_HDRV_HDRV5_Msk /*!< GPIO x huge sourcing/sinking strength control, pin 5 */ +#define GPIO_HDRV_HDRV6_Pos (6U) +#define GPIO_HDRV_HDRV6_Msk (0x1U << GPIO_HDRV_HDRV6_Pos) /*!< 0x00000040 */ +#define GPIO_HDRV_HDRV6 GPIO_HDRV_HDRV6_Msk /*!< GPIO x huge sourcing/sinking strength control, pin 6 */ +#define GPIO_HDRV_HDRV7_Pos (7U) +#define GPIO_HDRV_HDRV7_Msk (0x1U << GPIO_HDRV_HDRV7_Pos) /*!< 0x00000080 */ +#define GPIO_HDRV_HDRV7 GPIO_HDRV_HDRV7_Msk /*!< GPIO x huge sourcing/sinking strength control, pin 7 */ +#define GPIO_HDRV_HDRV8_Pos (8U) +#define GPIO_HDRV_HDRV8_Msk (0x1U << GPIO_HDRV_HDRV8_Pos) /*!< 0x00000100 */ +#define GPIO_HDRV_HDRV8 GPIO_HDRV_HDRV8_Msk /*!< GPIO x huge sourcing/sinking strength control, pin 8 */ +#define GPIO_HDRV_HDRV9_Pos (9U) +#define GPIO_HDRV_HDRV9_Msk (0x1U << GPIO_HDRV_HDRV9_Pos) /*!< 0x00000200 */ +#define GPIO_HDRV_HDRV9 GPIO_HDRV_HDRV9_Msk /*!< GPIO x huge sourcing/sinking strength control, pin 9 */ +#define GPIO_HDRV_HDRV10_Pos (10U) +#define GPIO_HDRV_HDRV10_Msk (0x1U << GPIO_HDRV_HDRV10_Pos) /*!< 0x00000400 */ +#define GPIO_HDRV_HDRV10 GPIO_HDRV_HDRV10_Msk /*!< GPIO x huge sourcing/sinking strength control, pin 10 */ +#define GPIO_HDRV_HDRV11_Pos (11U) +#define GPIO_HDRV_HDRV11_Msk (0x1U << GPIO_HDRV_HDRV11_Pos) /*!< 0x00000800 */ +#define GPIO_HDRV_HDRV11 GPIO_HDRV_HDRV11_Msk /*!< GPIO x huge sourcing/sinking strength control, pin 11 */ +#define GPIO_HDRV_HDRV12_Pos (12U) +#define GPIO_HDRV_HDRV12_Msk (0x1U << GPIO_HDRV_HDRV12_Pos) /*!< 0x00001000 */ +#define GPIO_HDRV_HDRV12 GPIO_HDRV_HDRV12_Msk /*!< GPIO x huge sourcing/sinking strength control, pin 12 */ +#define GPIO_HDRV_HDRV13_Pos (13U) +#define GPIO_HDRV_HDRV13_Msk (0x1U << GPIO_HDRV_HDRV13_Pos) /*!< 0x00002000 */ +#define GPIO_HDRV_HDRV13 GPIO_HDRV_HDRV13_Msk /*!< GPIO x huge sourcing/sinking strength control, pin 13 */ +#define GPIO_HDRV_HDRV14_Pos (14U) +#define GPIO_HDRV_HDRV14_Msk (0x1U << GPIO_HDRV_HDRV14_Pos) /*!< 0x00004000 */ +#define GPIO_HDRV_HDRV14 GPIO_HDRV_HDRV14_Msk /*!< GPIO x huge sourcing/sinking strength control, pin 14 */ +#define GPIO_HDRV_HDRV15_Pos (15U) +#define GPIO_HDRV_HDRV15_Msk (0x1U << GPIO_HDRV_HDRV15_Pos) /*!< 0x00008000 */ +#define GPIO_HDRV_HDRV15 GPIO_HDRV_HDRV15_Msk /*!< GPIO x huge sourcing/sinking strength control, pin 15 */ + +/****************** Bit definition for GPIO_SRCTR register ******************/ +#define GPIO_SRCTR_SRCTR0_Pos (0U) +#define GPIO_SRCTR_SRCTR0_Msk (0x1U << GPIO_SRCTR_SRCTR0_Pos) /*!< 0x00000001 */ +#define GPIO_SRCTR_SRCTR0 GPIO_SRCTR_SRCTR0_Msk /*!< GPIO x SRCTR, pin 0 */ +#define GPIO_SRCTR_SRCTR1_Pos (1U) +#define GPIO_SRCTR_SRCTR1_Msk (0x1U << GPIO_SRCTR_SRCTR1_Pos) /*!< 0x00000002 */ +#define GPIO_SRCTR_SRCTR1 GPIO_SRCTR_SRCTR1_Msk /*!< GPIO x SRCTR, pin 1 */ +#define GPIO_SRCTR_SRCTR2_Pos (2U) +#define GPIO_SRCTR_SRCTR2_Msk (0x1U << GPIO_SRCTR_SRCTR2_Pos) /*!< 0x00000004 */ +#define GPIO_SRCTR_SRCTR2 GPIO_SRCTR_SRCTR2_Msk /*!< GPIO x SRCTR, pin 2 */ +#define GPIO_SRCTR_SRCTR3_Pos (3U) +#define GPIO_SRCTR_SRCTR3_Msk (0x1U << GPIO_SRCTR_SRCTR3_Pos) /*!< 0x00000008 */ +#define GPIO_SRCTR_SRCTR3 GPIO_SRCTR_SRCTR3_Msk /*!< GPIO x SRCTR, pin 3 */ +#define GPIO_SRCTR_SRCTR4_Pos (4U) +#define GPIO_SRCTR_SRCTR4_Msk (0x1U << GPIO_SRCTR_SRCTR4_Pos) /*!< 0x00000010 */ +#define GPIO_SRCTR_SRCTR4 GPIO_SRCTR_SRCTR4_Msk /*!< GPIO x SRCTR, pin 4 */ +#define GPIO_SRCTR_SRCTR5_Pos (5U) +#define GPIO_SRCTR_SRCTR5_Msk (0x1U << GPIO_SRCTR_SRCTR5_Pos) /*!< 0x00000020 */ +#define GPIO_SRCTR_SRCTR5 GPIO_SRCTR_SRCTR5_Msk /*!< GPIO x SRCTR, pin 5 */ +#define GPIO_SRCTR_SRCTR6_Pos (6U) +#define GPIO_SRCTR_SRCTR6_Msk (0x1U << GPIO_SRCTR_SRCTR6_Pos) /*!< 0x00000040 */ +#define GPIO_SRCTR_SRCTR6 GPIO_SRCTR_SRCTR6_Msk /*!< GPIO x SRCTR, pin 6 */ +#define GPIO_SRCTR_SRCTR7_Pos (7U) +#define GPIO_SRCTR_SRCTR7_Msk (0x1U << GPIO_SRCTR_SRCTR7_Pos) /*!< 0x00000080 */ +#define GPIO_SRCTR_SRCTR7 GPIO_SRCTR_SRCTR7_Msk /*!< GPIO x SRCTR, pin 7 */ +#define GPIO_SRCTR_SRCTR8_Pos (8U) +#define GPIO_SRCTR_SRCTR8_Msk (0x1U << GPIO_SRCTR_SRCTR8_Pos) /*!< 0x00000100 */ +#define GPIO_SRCTR_SRCTR8 GPIO_SRCTR_SRCTR8_Msk /*!< GPIO x SRCTR, pin 8 */ +#define GPIO_SRCTR_SRCTR9_Pos (9U) +#define GPIO_SRCTR_SRCTR9_Msk (0x1U << GPIO_SRCTR_SRCTR9_Pos) /*!< 0x00000200 */ +#define GPIO_SRCTR_SRCTR9 GPIO_SRCTR_SRCTR9_Msk /*!< GPIO x SRCTR, pin 9 */ +#define GPIO_SRCTR_SRCTR10_Pos (10U) +#define GPIO_SRCTR_SRCTR10_Msk (0x1U << GPIO_SRCTR_SRCTR10_Pos) /*!< 0x00000400 */ +#define GPIO_SRCTR_SRCTR10 GPIO_SRCTR_SRCTR10_Msk /*!< GPIO x SRCTR, pin 10 */ +#define GPIO_SRCTR_SRCTR11_Pos (11U) +#define GPIO_SRCTR_SRCTR11_Msk (0x1U << GPIO_SRCTR_SRCTR11_Pos) /*!< 0x00000800 */ +#define GPIO_SRCTR_SRCTR11 GPIO_SRCTR_SRCTR11_Msk /*!< GPIO x SRCTR, pin 11 */ +#define GPIO_SRCTR_SRCTR12_Pos (12U) +#define GPIO_SRCTR_SRCTR12_Msk (0x1U << GPIO_SRCTR_SRCTR12_Pos) /*!< 0x00001000 */ +#define GPIO_SRCTR_SRCTR12 GPIO_SRCTR_SRCTR12_Msk /*!< GPIO x SRCTR, pin 12 */ +#define GPIO_SRCTR_SRCTR13_Pos (13U) +#define GPIO_SRCTR_SRCTR13_Msk (0x1U << GPIO_SRCTR_SRCTR13_Pos) /*!< 0x00002000 */ +#define GPIO_SRCTR_SRCTR13 GPIO_SRCTR_SRCTR13_Msk /*!< GPIO x SRCTR, pin 13 */ +#define GPIO_SRCTR_SRCTR14_Pos (14U) +#define GPIO_SRCTR_SRCTR14_Msk (0x1U << GPIO_SRCTR_SRCTR14_Pos) /*!< 0x00004000 */ +#define GPIO_SRCTR_SRCTR14 GPIO_SRCTR_SRCTR14_Msk /*!< GPIO x SRCTR, pin 14 */ +#define GPIO_SRCTR_SRCTR15_Pos (15U) +#define GPIO_SRCTR_SRCTR15_Msk (0x1U << GPIO_SRCTR_SRCTR15_Pos) /*!< 0x00008000 */ +#define GPIO_SRCTR_SRCTR15 GPIO_SRCTR_SRCTR15_Msk /*!< GPIO x SRCTR, pin 15 */ + +/******************************************************************************/ +/* */ +/* System configuration controller (SCFG) */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for SCFG_CFG1 register *******************/ +/*!< MEM_MAP_SEL configuration */ +#define SCFG_CFG1_MEM_MAP_SEL_Pos (0U) +#define SCFG_CFG1_MEM_MAP_SEL_Msk (0x3U << SCFG_CFG1_MEM_MAP_SEL_Pos) /*!< 0x00000003 */ +#define SCFG_CFG1_MEM_MAP_SEL SCFG_CFG1_MEM_MAP_SEL_Msk /*!< MEM_MAP_SEL[1:0] bits (Boot mode status bit) */ +#define SCFG_CFG1_MEM_MAP_SEL_0 (0x1U << SCFG_CFG1_MEM_MAP_SEL_Pos) /*!< 0x00000001 */ +#define SCFG_CFG1_MEM_MAP_SEL_1 (0x2U << SCFG_CFG1_MEM_MAP_SEL_Pos) /*!< 0x00000002 */ + +#define SCFG_CFG1_MEM_MAP_SEL_FLASHMEM 0x00000000U /*!< Boot from main flash memory */ +#define SCFG_CFG1_MEM_MAP_SEL_SYSMEM 0x00000001U /*!< Boot from system memory */ +#define SCFG_CFG1_MEM_MAP_SEL_INTSRAM 0x00000003U /*!< Boot from internal SRAM */ + +#define SCFG_CFG1_IR_POL_Pos (5U) +#define SCFG_CFG1_IR_POL_Msk (0x1U << SCFG_CFG1_IR_POL_Pos) /*!< 0x00000020 */ +#define SCFG_CFG1_IR_POL SCFG_CFG1_IR_POL_Msk /*!< Infrared output polarity selection */ + +/*!< IR_SRC_SEL configuration */ +#define SCFG_CFG1_IR_SRC_SEL_Pos (6U) +#define SCFG_CFG1_IR_SRC_SEL_Msk (0x3U << SCFG_CFG1_IR_SRC_SEL_Pos) /*!< 0x000000C0 */ +#define SCFG_CFG1_IR_SRC_SEL SCFG_CFG1_IR_SRC_SEL_Msk /*!< IR_SRC_SEL[1:0] bits (IR modulation envelope signal source selection) */ +#define SCFG_CFG1_IR_SRC_SEL_0 (0x1U << SCFG_CFG1_IR_SRC_SEL_Pos) /*!< 0x00000040 */ +#define SCFG_CFG1_IR_SRC_SEL_1 (0x2U << SCFG_CFG1_IR_SRC_SEL_Pos) /*!< 0x00000080 */ + +#define SCFG_CFG1_IR_SRC_SEL_TMR10 0x00000000U /*!< TMR10 */ +#define SCFG_CFG1_IR_SRC_SEL_USART1 0x00000040U /*!< USART1 */ +#define SCFG_CFG1_IR_SRC_SEL_USART2 0x00000080U /*!< USART2 */ + +/****************** Bit definition for SCFG_CFG2 register *******************/ +#define SCFG_CFG2_LOCKUP_LK_Pos (0U) +#define SCFG_CFG2_LOCKUP_LK_Msk (0x1U << SCFG_CFG2_LOCKUP_LK_Pos) /*!< 0x00000001 */ +#define SCFG_CFG2_LOCKUP_LK SCFG_CFG2_LOCKUP_LK_Msk /*!< Cortex-M4F lockup bit enable */ +#define SCFG_CFG2_SRAM_OPERR_LK_Pos (1U) +#define SCFG_CFG2_SRAM_OPERR_LK_Msk (0x1U << SCFG_CFG2_SRAM_OPERR_LK_Pos) /*!< 0x00000002 */ +#define SCFG_CFG2_SRAM_OPERR_LK SCFG_CFG2_SRAM_OPERR_LK_Msk /*!< SRAM odd parity error lock enable */ +#define SCFG_CFG2_PVM_LK_Pos (2U) +#define SCFG_CFG2_PVM_LK_Msk (0x1U << SCFG_CFG2_PVM_LK_Pos) /*!< 0x00000004 */ +#define SCFG_CFG2_PVM_LK SCFG_CFG2_PVM_LK_Msk /*!< PVM lock enable */ +#define SCFG_CFG2_SRAM_OPERR_STS_Pos (8U) +#define SCFG_CFG2_SRAM_OPERR_STS_Msk (0x1U << SCFG_CFG2_SRAM_OPERR_STS_Pos) /*!< 0x00000100 */ +#define SCFG_CFG2_SRAM_OPERR_STS SCFG_CFG2_SRAM_OPERR_STS_Msk /*!< SRAM odd parity error status */ + +/*!< I2S_FD configuration */ +#define SCFG_CFG2_I2S_FD_Pos (30U) +#define SCFG_CFG2_I2S_FD_Msk (0x3U << SCFG_CFG2_I2S_FD_Pos) /*!< 0xC0000000 */ +#define SCFG_CFG2_I2S_FD SCFG_CFG2_I2S_FD_Msk /*!< I2S_FD[1:0] bits (I2S full duplex configuration bit) */ +#define SCFG_CFG2_I2S_FD_0 (0x1U << SCFG_CFG2_I2S_FD_Pos) /*!< 0x40000000 */ +#define SCFG_CFG2_I2S_FD_1 (0x2U << SCFG_CFG2_I2S_FD_Pos) /*!< 0x80000000 */ + +#define SCFG_CFG2_I2S_FD_SPI_I2S 0x00000000U /*!< SPI / I2S1 ~ 3 operates separately */ +#define SCFG_CFG2_I2S_FD_I2S1_3_FD 0x40000000U /*!< I2S1 and I2S3 are configured as full-duplex mode */ +#define SCFG_CFG2_I2S_FD_I2S2_3_FD 0x80000000U /*!< I2S2 and I2S3 are configured as full-duplex mode */ +#define SCFG_CFG2_I2S_FD_I2S1_2_FD 0xC0000000U /*!< I2S1 and I2S2 are configured as full-duplex mode */ + +/***************** Bit definition for SCFG_EXINTC1 register *****************/ +/*!< EXINT0 configuration */ +#define SCFG_EXINTC1_EXINT0_Pos (0U) +#define SCFG_EXINTC1_EXINT0_Msk (0xFU << SCFG_EXINTC1_EXINT0_Pos) /*!< 0x0000000F */ +#define SCFG_EXINTC1_EXINT0 SCFG_EXINTC1_EXINT0_Msk /*!< EXINT0[3:0] bits (EXINT0 input source configuration) */ + +#define SCFG_EXINTC1_EXINT0_GPA 0x00000000U /*!< GPIOA pin 0 */ +#define SCFG_EXINTC1_EXINT0_GPB_Pos (0U) +#define SCFG_EXINTC1_EXINT0_GPB_Msk (0x1U << SCFG_EXINTC1_EXINT0_GPB_Pos) /*!< 0x00000001 */ +#define SCFG_EXINTC1_EXINT0_GPB SCFG_EXINTC1_EXINT0_GPB_Msk /*!< GPIOB pin 0 */ +#define SCFG_EXINTC1_EXINT0_GPC_Pos (1U) +#define SCFG_EXINTC1_EXINT0_GPC_Msk (0x1U << SCFG_EXINTC1_EXINT0_GPC_Pos) /*!< 0x00000002 */ +#define SCFG_EXINTC1_EXINT0_GPC SCFG_EXINTC1_EXINT0_GPC_Msk /*!< GPIOC pin 0 */ +#define SCFG_EXINTC1_EXINT0_GPD_Pos (0U) +#define SCFG_EXINTC1_EXINT0_GPD_Msk (0x3U << SCFG_EXINTC1_EXINT0_GPD_Pos) /*!< 0x00000003 */ +#define SCFG_EXINTC1_EXINT0_GPD SCFG_EXINTC1_EXINT0_GPD_Msk /*!< GPIOD pin 0 */ +#define SCFG_EXINTC1_EXINT0_GPF_Pos (2U) +#define SCFG_EXINTC1_EXINT0_GPF_Msk (0x1U << SCFG_EXINTC1_EXINT0_GPF_Pos) /*!< 0x00000004 */ +#define SCFG_EXINTC1_EXINT0_GPF SCFG_EXINTC1_EXINT0_GPF_Msk /*!< GPIOF pin 0 */ + +/*!< EXINT1 configuration */ +#define SCFG_EXINTC1_EXINT1_Pos (4U) +#define SCFG_EXINTC1_EXINT1_Msk (0xFU << SCFG_EXINTC1_EXINT1_Pos) /*!< 0x000000F0 */ +#define SCFG_EXINTC1_EXINT1 SCFG_EXINTC1_EXINT1_Msk /*!< EXINT1[3:0] bits (EXINT1 input source configuration) */ + +#define SCFG_EXINTC1_EXINT1_GPA 0x00000000U /*!< GPIOA pin 1 */ +#define SCFG_EXINTC1_EXINT1_GPB_Pos (4U) +#define SCFG_EXINTC1_EXINT1_GPB_Msk (0x1U << SCFG_EXINTC1_EXINT1_GPB_Pos) /*!< 0x00000010 */ +#define SCFG_EXINTC1_EXINT1_GPB SCFG_EXINTC1_EXINT1_GPB_Msk /*!< GPIOB pin 1 */ +#define SCFG_EXINTC1_EXINT1_GPC_Pos (5U) +#define SCFG_EXINTC1_EXINT1_GPC_Msk (0x1U << SCFG_EXINTC1_EXINT1_GPC_Pos) /*!< 0x00000020 */ +#define SCFG_EXINTC1_EXINT1_GPC SCFG_EXINTC1_EXINT1_GPC_Msk /*!< GPIOC pin 1 */ +#define SCFG_EXINTC1_EXINT1_GPD_Pos (4U) +#define SCFG_EXINTC1_EXINT1_GPD_Msk (0x3U << SCFG_EXINTC1_EXINT1_GPD_Pos) /*!< 0x00000030 */ +#define SCFG_EXINTC1_EXINT1_GPD SCFG_EXINTC1_EXINT1_GPD_Msk /*!< GPIOD pin 1 */ +#define SCFG_EXINTC1_EXINT1_GPF_Pos (6U) +#define SCFG_EXINTC1_EXINT1_GPF_Msk (0x1U << SCFG_EXINTC1_EXINT1_GPF_Pos) /*!< 0x00000040 */ +#define SCFG_EXINTC1_EXINT1_GPF SCFG_EXINTC1_EXINT1_GPF_Msk /*!< GPIOF pin 1 */ + +/*!< EXINT2 configuration */ +#define SCFG_EXINTC1_EXINT2_Pos (8U) +#define SCFG_EXINTC1_EXINT2_Msk (0xFU << SCFG_EXINTC1_EXINT2_Pos) /*!< 0x00000F00 */ +#define SCFG_EXINTC1_EXINT2 SCFG_EXINTC1_EXINT2_Msk /*!< EXINT2[3:0] bits (EXINT2 input source configuration) */ + +#define SCFG_EXINTC1_EXINT2_GPA 0x00000000U /*!< GPIOA pin 2 */ +#define SCFG_EXINTC1_EXINT2_GPB_Pos (8U) +#define SCFG_EXINTC1_EXINT2_GPB_Msk (0x1U << SCFG_EXINTC1_EXINT2_GPB_Pos) /*!< 0x00000100 */ +#define SCFG_EXINTC1_EXINT2_GPB SCFG_EXINTC1_EXINT2_GPB_Msk /*!< GPIOB pin 2 */ +#define SCFG_EXINTC1_EXINT2_GPC_Pos (9U) +#define SCFG_EXINTC1_EXINT2_GPC_Msk (0x1U << SCFG_EXINTC1_EXINT2_GPC_Pos) /*!< 0x00000200 */ +#define SCFG_EXINTC1_EXINT2_GPC SCFG_EXINTC1_EXINT2_GPC_Msk /*!< GPIOC pin 2 */ +#define SCFG_EXINTC1_EXINT2_GPD_Pos (8U) +#define SCFG_EXINTC1_EXINT2_GPD_Msk (0x3U << SCFG_EXINTC1_EXINT2_GPD_Pos) /*!< 0x00000300 */ +#define SCFG_EXINTC1_EXINT2_GPD SCFG_EXINTC1_EXINT2_GPD_Msk /*!< GPIOD pin 2 */ +#define SCFG_EXINTC1_EXINT2_GPF_Pos (10U) +#define SCFG_EXINTC1_EXINT2_GPF_Msk (0x1U << SCFG_EXINTC1_EXINT2_GPF_Pos) /*!< 0x00000400 */ +#define SCFG_EXINTC1_EXINT2_GPF SCFG_EXINTC1_EXINT2_GPF_Msk /*!< GPIOF pin 2 */ + +/*!< EXINT3 configuration */ +#define SCFG_EXINTC1_EXINT3_Pos (12U) +#define SCFG_EXINTC1_EXINT3_Msk (0xFU << SCFG_EXINTC1_EXINT3_Pos) /*!< 0x0000F000 */ +#define SCFG_EXINTC1_EXINT3 SCFG_EXINTC1_EXINT3_Msk /*!< EXINT3[3:0] bits (EXINT3 input source configuration) */ + +#define SCFG_EXINTC1_EXINT3_GPA 0x00000000U /*!< GPIOA pin 3 */ +#define SCFG_EXINTC1_EXINT3_GPB_Pos (12U) +#define SCFG_EXINTC1_EXINT3_GPB_Msk (0x1U << SCFG_EXINTC1_EXINT3_GPB_Pos) /*!< 0x00001000 */ +#define SCFG_EXINTC1_EXINT3_GPB SCFG_EXINTC1_EXINT3_GPB_Msk /*!< GPIOB pin 3 */ +#define SCFG_EXINTC1_EXINT3_GPC_Pos (13U) +#define SCFG_EXINTC1_EXINT3_GPC_Msk (0x1U << SCFG_EXINTC1_EXINT3_GPC_Pos) /*!< 0x00002000 */ +#define SCFG_EXINTC1_EXINT3_GPC SCFG_EXINTC1_EXINT3_GPC_Msk /*!< GPIOC pin 3 */ +#define SCFG_EXINTC1_EXINT3_GPD_Pos (12U) +#define SCFG_EXINTC1_EXINT3_GPD_Msk (0x3U << SCFG_EXINTC1_EXINT3_GPD_Pos) /*!< 0x00003000 */ +#define SCFG_EXINTC1_EXINT3_GPD SCFG_EXINTC1_EXINT3_GPD_Msk /*!< GPIOD pin 3 */ +#define SCFG_EXINTC1_EXINT3_GPF_Pos (14U) +#define SCFG_EXINTC1_EXINT3_GPF_Msk (0x1U << SCFG_EXINTC1_EXINT3_GPF_Pos) /*!< 0x00004000 */ +#define SCFG_EXINTC1_EXINT3_GPF SCFG_EXINTC1_EXINT3_GPF_Msk /*!< GPIOF pin 3 */ + +/***************** Bit definition for SCFG_EXINTC2 register *****************/ +/*!< EXINT4 configuration */ +#define SCFG_EXINTC2_EXINT4_Pos (0U) +#define SCFG_EXINTC2_EXINT4_Msk (0xFU << SCFG_EXINTC2_EXINT4_Pos) /*!< 0x0000000F */ +#define SCFG_EXINTC2_EXINT4 SCFG_EXINTC2_EXINT4_Msk /*!< EXINT4[3:0] bits (EXINT4 input source configuration) */ + +#define SCFG_EXINTC2_EXINT4_GPA 0x00000000U /*!< GPIOA pin 4 */ +#define SCFG_EXINTC2_EXINT4_GPB_Pos (0U) +#define SCFG_EXINTC2_EXINT4_GPB_Msk (0x1U << SCFG_EXINTC2_EXINT4_GPB_Pos) /*!< 0x00000001 */ +#define SCFG_EXINTC2_EXINT4_GPB SCFG_EXINTC2_EXINT4_GPB_Msk /*!< GPIOB pin 4 */ +#define SCFG_EXINTC2_EXINT4_GPC_Pos (1U) +#define SCFG_EXINTC2_EXINT4_GPC_Msk (0x1U << SCFG_EXINTC2_EXINT4_GPC_Pos) /*!< 0x00000002 */ +#define SCFG_EXINTC2_EXINT4_GPC SCFG_EXINTC2_EXINT4_GPC_Msk /*!< GPIOC pin 4 */ +#define SCFG_EXINTC2_EXINT4_GPD_Pos (0U) +#define SCFG_EXINTC2_EXINT4_GPD_Msk (0x3U << SCFG_EXINTC2_EXINT4_GPD_Pos) /*!< 0x00000003 */ +#define SCFG_EXINTC2_EXINT4_GPD SCFG_EXINTC2_EXINT4_GPD_Msk /*!< GPIOD pin 4 */ +#define SCFG_EXINTC2_EXINT4_GPF_Pos (2U) +#define SCFG_EXINTC2_EXINT4_GPF_Msk (0x1U << SCFG_EXINTC2_EXINT4_GPF_Pos) /*!< 0x00000004 */ +#define SCFG_EXINTC2_EXINT4_GPF SCFG_EXINTC2_EXINT4_GPF_Msk /*!< GPIOF pin 4 */ + +/* EXINT5 configuration */ +#define SCFG_EXINTC2_EXINT5_Pos (4U) +#define SCFG_EXINTC2_EXINT5_Msk (0xFU << SCFG_EXINTC2_EXINT5_Pos) /*!< 0x000000F0 */ +#define SCFG_EXINTC2_EXINT5 SCFG_EXINTC2_EXINT5_Msk /*!< EXINT5[3:0] bits (EXINT5 input source configuration) */ + +#define SCFG_EXINTC2_EXINT5_GPA 0x00000000U /*!< GPIOA pin 5 */ +#define SCFG_EXINTC2_EXINT5_GPB_Pos (4U) +#define SCFG_EXINTC2_EXINT5_GPB_Msk (0x1U << SCFG_EXINTC2_EXINT5_GPB_Pos) /*!< 0x00000010 */ +#define SCFG_EXINTC2_EXINT5_GPB SCFG_EXINTC2_EXINT5_GPB_Msk /*!< GPIOB pin 5 */ +#define SCFG_EXINTC2_EXINT5_GPC_Pos (5U) +#define SCFG_EXINTC2_EXINT5_GPC_Msk (0x1U << SCFG_EXINTC2_EXINT5_GPC_Pos) /*!< 0x00000020 */ +#define SCFG_EXINTC2_EXINT5_GPC SCFG_EXINTC2_EXINT5_GPC_Msk /*!< GPIOC pin 5 */ +#define SCFG_EXINTC2_EXINT5_GPD_Pos (4U) +#define SCFG_EXINTC2_EXINT5_GPD_Msk (0x3U << SCFG_EXINTC2_EXINT5_GPD_Pos) /*!< 0x00000030 */ +#define SCFG_EXINTC2_EXINT5_GPD SCFG_EXINTC2_EXINT5_GPD_Msk /*!< GPIOD pin 5 */ +#define SCFG_EXINTC2_EXINT5_GPF_Pos (6U) +#define SCFG_EXINTC2_EXINT5_GPF_Msk (0x1U << SCFG_EXINTC2_EXINT5_GPF_Pos) /*!< 0x00000040 */ +#define SCFG_EXINTC2_EXINT5_GPF SCFG_EXINTC2_EXINT5_GPF_Msk /*!< GPIOF pin 5 */ + +/*!< EXINT6 configuration */ +#define SCFG_EXINTC2_EXINT6_Pos (8U) +#define SCFG_EXINTC2_EXINT6_Msk (0xFU << SCFG_EXINTC2_EXINT6_Pos) /*!< 0x00000F00 */ +#define SCFG_EXINTC2_EXINT6 SCFG_EXINTC2_EXINT6_Msk /*!< EXINT6[3:0] bits (EXINT6 input source configuration) */ + +#define SCFG_EXINTC2_EXINT6_GPA 0x00000000U /*!< GPIOA pin 6 */ +#define SCFG_EXINTC2_EXINT6_GPB_Pos (8U) +#define SCFG_EXINTC2_EXINT6_GPB_Msk (0x1U << SCFG_EXINTC2_EXINT6_GPB_Pos) /*!< 0x00000100 */ +#define SCFG_EXINTC2_EXINT6_GPB SCFG_EXINTC2_EXINT6_GPB_Msk /*!< GPIOB pin 6 */ +#define SCFG_EXINTC2_EXINT6_GPC_Pos (9U) +#define SCFG_EXINTC2_EXINT6_GPC_Msk (0x1U << SCFG_EXINTC2_EXINT6_GPC_Pos) /*!< 0x00000200 */ +#define SCFG_EXINTC2_EXINT6_GPC SCFG_EXINTC2_EXINT6_GPC_Msk /*!< GPIOC pin 6 */ +#define SCFG_EXINTC2_EXINT6_GPD_Pos (8U) +#define SCFG_EXINTC2_EXINT6_GPD_Msk (0x3U << SCFG_EXINTC2_EXINT6_GPD_Pos) /*!< 0x00000300 */ +#define SCFG_EXINTC2_EXINT6_GPD SCFG_EXINTC2_EXINT6_GPD_Msk /*!< GPIOD pin 6 */ +#define SCFG_EXINTC2_EXINT6_GPF_Pos (10U) +#define SCFG_EXINTC2_EXINT6_GPF_Msk (0x1U << SCFG_EXINTC2_EXINT6_GPF_Pos) /*!< 0x00000400 */ +#define SCFG_EXINTC2_EXINT6_GPF SCFG_EXINTC2_EXINT6_GPF_Msk /*!< GPIOF pin 6 */ + +/*!< EXINT7 configuration */ +#define SCFG_EXINTC2_EXINT7_Pos (12U) +#define SCFG_EXINTC2_EXINT7_Msk (0xFU << SCFG_EXINTC2_EXINT7_Pos) /*!< 0x0000F000 */ +#define SCFG_EXINTC2_EXINT7 SCFG_EXINTC2_EXINT7_Msk /*!< EXINT7[3:0] bits (EXINT7 input source configuration) */ + +#define SCFG_EXINTC2_EXINT7_GPA 0x00000000U /*!< GPIOA pin 7 */ +#define SCFG_EXINTC2_EXINT7_GPB_Pos (12U) +#define SCFG_EXINTC2_EXINT7_GPB_Msk (0x1U << SCFG_EXINTC2_EXINT7_GPB_Pos) /*!< 0x00001000 */ +#define SCFG_EXINTC2_EXINT7_GPB SCFG_EXINTC2_EXINT7_GPB_Msk /*!< GPIOB pin 7 */ +#define SCFG_EXINTC2_EXINT7_GPC_Pos (13U) +#define SCFG_EXINTC2_EXINT7_GPC_Msk (0x1U << SCFG_EXINTC2_EXINT7_GPC_Pos) /*!< 0x00002000 */ +#define SCFG_EXINTC2_EXINT7_GPC SCFG_EXINTC2_EXINT7_GPC_Msk /*!< GPIOC pin 7 */ +#define SCFG_EXINTC2_EXINT7_GPD_Pos (12U) +#define SCFG_EXINTC2_EXINT7_GPD_Msk (0x3U << SCFG_EXINTC2_EXINT7_GPD_Pos) /*!< 0x00003000 */ +#define SCFG_EXINTC2_EXINT7_GPD SCFG_EXINTC2_EXINT7_GPD_Msk /*!< GPIOD pin 7 */ +#define SCFG_EXINTC2_EXINT7_GPF_Pos (14U) +#define SCFG_EXINTC2_EXINT7_GPF_Msk (0x1U << SCFG_EXINTC2_EXINT7_GPF_Pos) /*!< 0x00004000 */ +#define SCFG_EXINTC2_EXINT7_GPF SCFG_EXINTC2_EXINT7_GPF_Msk /*!< GPIOF pin 7 */ + +/***************** Bit definition for SCFG_EXINTC3 register *****************/ +/*!< EXINT8 configuration */ +#define SCFG_EXINTC3_EXINT8_Pos (0U) +#define SCFG_EXINTC3_EXINT8_Msk (0xFU << SCFG_EXINTC3_EXINT8_Pos) /*!< 0x0000000F */ +#define SCFG_EXINTC3_EXINT8 SCFG_EXINTC3_EXINT8_Msk /*!< EXINT8[3:0] bits (EXINT8 input source configuration) */ + +#define SCFG_EXINTC3_EXINT8_GPA 0x00000000U /*!< GPIOA pin 8 */ +#define SCFG_EXINTC3_EXINT8_GPB_Pos (0U) +#define SCFG_EXINTC3_EXINT8_GPB_Msk (0x1U << SCFG_EXINTC3_EXINT8_GPB_Pos) /*!< 0x00000001 */ +#define SCFG_EXINTC3_EXINT8_GPB SCFG_EXINTC3_EXINT8_GPB_Msk /*!< GPIOB pin 8 */ +#define SCFG_EXINTC3_EXINT8_GPC_Pos (1U) +#define SCFG_EXINTC3_EXINT8_GPC_Msk (0x1U << SCFG_EXINTC3_EXINT8_GPC_Pos) /*!< 0x00000002 */ +#define SCFG_EXINTC3_EXINT8_GPC SCFG_EXINTC3_EXINT8_GPC_Msk /*!< GPIOC pin 8 */ +#define SCFG_EXINTC3_EXINT8_GPD_Pos (0U) +#define SCFG_EXINTC3_EXINT8_GPD_Msk (0x3U << SCFG_EXINTC3_EXINT8_GPD_Pos) /*!< 0x00000003 */ +#define SCFG_EXINTC3_EXINT8_GPD SCFG_EXINTC3_EXINT8_GPD_Msk /*!< GPIOD pin 8 */ +#define SCFG_EXINTC3_EXINT8_GPF_Pos (2U) +#define SCFG_EXINTC3_EXINT8_GPF_Msk (0x1U << SCFG_EXINTC3_EXINT8_GPF_Pos) /*!< 0x00000004 */ +#define SCFG_EXINTC3_EXINT8_GPF SCFG_EXINTC3_EXINT8_GPF_Msk /*!< GPIOF pin 8 */ + +/*!< EXINT9 configuration */ +#define SCFG_EXINTC3_EXINT9_Pos (4U) +#define SCFG_EXINTC3_EXINT9_Msk (0xFU << SCFG_EXINTC3_EXINT9_Pos) /*!< 0x000000F0 */ +#define SCFG_EXINTC3_EXINT9 SCFG_EXINTC3_EXINT9_Msk /*!< EXINT9[3:0] bits (EXINT9 input source configuration) */ + +#define SCFG_EXINTC3_EXINT9_GPA 0x00000000U /*!< GPIOA pin 9 */ +#define SCFG_EXINTC3_EXINT9_GPB_Pos (4U) +#define SCFG_EXINTC3_EXINT9_GPB_Msk (0x1U << SCFG_EXINTC3_EXINT9_GPB_Pos) /*!< 0x00000010 */ +#define SCFG_EXINTC3_EXINT9_GPB SCFG_EXINTC3_EXINT9_GPB_Msk /*!< GPIOB pin 9 */ +#define SCFG_EXINTC3_EXINT9_GPC_Pos (5U) +#define SCFG_EXINTC3_EXINT9_GPC_Msk (0x1U << SCFG_EXINTC3_EXINT9_GPC_Pos) /*!< 0x00000020 */ +#define SCFG_EXINTC3_EXINT9_GPC SCFG_EXINTC3_EXINT9_GPC_Msk /*!< GPIOC pin 9 */ +#define SCFG_EXINTC3_EXINT9_GPD_Pos (4U) +#define SCFG_EXINTC3_EXINT9_GPD_Msk (0x3U << SCFG_EXINTC3_EXINT9_GPD_Pos) /*!< 0x00000030 */ +#define SCFG_EXINTC3_EXINT9_GPD SCFG_EXINTC3_EXINT9_GPD_Msk /*!< GPIOD pin 9 */ +#define SCFG_EXINTC3_EXINT9_GPF_Pos (6U) +#define SCFG_EXINTC3_EXINT9_GPF_Msk (0x1U << SCFG_EXINTC3_EXINT9_GPF_Pos) /*!< 0x00000040 */ +#define SCFG_EXINTC3_EXINT9_GPF SCFG_EXINTC3_EXINT9_GPF_Msk /*!< GPIOF pin 9 */ + +/*!< EXINT10 configuration */ +#define SCFG_EXINTC3_EXINT10_Pos (8U) +#define SCFG_EXINTC3_EXINT10_Msk (0xFU << SCFG_EXINTC3_EXINT10_Pos) /*!< 0x00000F00 */ +#define SCFG_EXINTC3_EXINT10 SCFG_EXINTC3_EXINT10_Msk /*!< EXINT10[3:0] bits (EXINT10 input source configuration) */ + +#define SCFG_EXINTC3_EXINT10_GPA 0x00000000U /*!< GPIOA pin 10 */ +#define SCFG_EXINTC3_EXINT10_GPB_Pos (8U) +#define SCFG_EXINTC3_EXINT10_GPB_Msk (0x1U << SCFG_EXINTC3_EXINT10_GPB_Pos) /*!< 0x00000100 */ +#define SCFG_EXINTC3_EXINT10_GPB SCFG_EXINTC3_EXINT10_GPB_Msk /*!< GPIOB pin 10 */ +#define SCFG_EXINTC3_EXINT10_GPC_Pos (9U) +#define SCFG_EXINTC3_EXINT10_GPC_Msk (0x1U << SCFG_EXINTC3_EXINT10_GPC_Pos) /*!< 0x00000200 */ +#define SCFG_EXINTC3_EXINT10_GPC SCFG_EXINTC3_EXINT10_GPC_Msk /*!< GPIOC pin 10 */ +#define SCFG_EXINTC3_EXINT10_GPD_Pos (8U) +#define SCFG_EXINTC3_EXINT10_GPD_Msk (0x3U << SCFG_EXINTC3_EXINT10_GPD_Pos) /*!< 0x00000300 */ +#define SCFG_EXINTC3_EXINT10_GPD SCFG_EXINTC3_EXINT10_GPD_Msk /*!< GPIOD pin 10 */ +#define SCFG_EXINTC3_EXINT10_GPF_Pos (10U) +#define SCFG_EXINTC3_EXINT10_GPF_Msk (0x1U << SCFG_EXINTC3_EXINT10_GPF_Pos) /*!< 0x00000400 */ +#define SCFG_EXINTC3_EXINT10_GPF SCFG_EXINTC3_EXINT10_GPF_Msk /*!< GPIOF pin 10 */ + +/*!< EXINT11 configuration */ +#define SCFG_EXINTC3_EXINT11_Pos (12U) +#define SCFG_EXINTC3_EXINT11_Msk (0xFU << SCFG_EXINTC3_EXINT11_Pos) /*!< 0x0000F000 */ +#define SCFG_EXINTC3_EXINT11 SCFG_EXINTC3_EXINT11_Msk /*!< EXINT11[3:0] bits (EXINT11 input source configuration) */ + +#define SCFG_EXINTC3_EXINT11_GPA 0x00000000U /*!< GPIOA pin 11 */ +#define SCFG_EXINTC3_EXINT11_GPB_Pos (12U) +#define SCFG_EXINTC3_EXINT11_GPB_Msk (0x1U << SCFG_EXINTC3_EXINT11_GPB_Pos) /*!< 0x00001000 */ +#define SCFG_EXINTC3_EXINT11_GPB SCFG_EXINTC3_EXINT11_GPB_Msk /*!< GPIOB pin 11 */ +#define SCFG_EXINTC3_EXINT11_GPC_Pos (13U) +#define SCFG_EXINTC3_EXINT11_GPC_Msk (0x1U << SCFG_EXINTC3_EXINT11_GPC_Pos) /*!< 0x00002000 */ +#define SCFG_EXINTC3_EXINT11_GPC SCFG_EXINTC3_EXINT11_GPC_Msk /*!< GPIOC pin 11 */ +#define SCFG_EXINTC3_EXINT11_GPD_Pos (12U) +#define SCFG_EXINTC3_EXINT11_GPD_Msk (0x3U << SCFG_EXINTC3_EXINT11_GPD_Pos) /*!< 0x00003000 */ +#define SCFG_EXINTC3_EXINT11_GPD SCFG_EXINTC3_EXINT11_GPD_Msk /*!< GPIOD pin 11 */ +#define SCFG_EXINTC3_EXINT11_GPF_Pos (14U) +#define SCFG_EXINTC3_EXINT11_GPF_Msk (0x1U << SCFG_EXINTC3_EXINT11_GPF_Pos) /*!< 0x00004000 */ +#define SCFG_EXINTC3_EXINT11_GPF SCFG_EXINTC3_EXINT11_GPF_Msk /*!< GPIOF pin 11 */ + +/***************** Bit definition for SCFG_EXINTC4 register *****************/ +/* EXINT12 configuration */ +#define SCFG_EXINTC4_EXINT12_Pos (0U) +#define SCFG_EXINTC4_EXINT12_Msk (0xFU << SCFG_EXINTC4_EXINT12_Pos) /*!< 0x0000000F */ +#define SCFG_EXINTC4_EXINT12 SCFG_EXINTC4_EXINT12_Msk /*!< EXINT12[3:0] bits (EXINT12 input source configuration) */ + +#define SCFG_EXINTC4_EXINT12_GPA 0x00000000U /*!< GPIOA pin 12 */ +#define SCFG_EXINTC4_EXINT12_GPB_Pos (0U) +#define SCFG_EXINTC4_EXINT12_GPB_Msk (0x1U << SCFG_EXINTC4_EXINT12_GPB_Pos) /*!< 0x00000001 */ +#define SCFG_EXINTC4_EXINT12_GPB SCFG_EXINTC4_EXINT12_GPB_Msk /*!< GPIOB pin 12 */ +#define SCFG_EXINTC4_EXINT12_GPC_Pos (1U) +#define SCFG_EXINTC4_EXINT12_GPC_Msk (0x1U << SCFG_EXINTC4_EXINT12_GPC_Pos) /*!< 0x00000002 */ +#define SCFG_EXINTC4_EXINT12_GPC SCFG_EXINTC4_EXINT12_GPC_Msk /*!< GPIOC pin 12 */ +#define SCFG_EXINTC4_EXINT12_GPD_Pos (0U) +#define SCFG_EXINTC4_EXINT12_GPD_Msk (0x3U << SCFG_EXINTC4_EXINT12_GPD_Pos) /*!< 0x00000003 */ +#define SCFG_EXINTC4_EXINT12_GPD SCFG_EXINTC4_EXINT12_GPD_Msk /*!< GPIOD pin 12 */ +#define SCFG_EXINTC4_EXINT12_GPF_Pos (2U) +#define SCFG_EXINTC4_EXINT12_GPF_Msk (0x1U << SCFG_EXINTC4_EXINT12_GPF_Pos) /*!< 0x00000004 */ +#define SCFG_EXINTC4_EXINT12_GPF SCFG_EXINTC4_EXINT12_GPF_Msk /*!< GPIOF pin 12 */ + +/* EXINT13 configuration */ +#define SCFG_EXINTC4_EXINT13_Pos (4U) +#define SCFG_EXINTC4_EXINT13_Msk (0xFU << SCFG_EXINTC4_EXINT13_Pos) /*!< 0x000000F0 */ +#define SCFG_EXINTC4_EXINT13 SCFG_EXINTC4_EXINT13_Msk /*!< EXINT13[3:0] bits (EXINT13 input source configuration) */ + +#define SCFG_EXINTC4_EXINT13_GPA 0x00000000U /*!< GPIOA pin 13 */ +#define SCFG_EXINTC4_EXINT13_GPB_Pos (4U) +#define SCFG_EXINTC4_EXINT13_GPB_Msk (0x1U << SCFG_EXINTC4_EXINT13_GPB_Pos) /*!< 0x00000010 */ +#define SCFG_EXINTC4_EXINT13_GPB SCFG_EXINTC4_EXINT13_GPB_Msk /*!< GPIOB pin 13 */ +#define SCFG_EXINTC4_EXINT13_GPC_Pos (5U) +#define SCFG_EXINTC4_EXINT13_GPC_Msk (0x1U << SCFG_EXINTC4_EXINT13_GPC_Pos) /*!< 0x00000020 */ +#define SCFG_EXINTC4_EXINT13_GPC SCFG_EXINTC4_EXINT13_GPC_Msk /*!< GPIOC pin 13 */ +#define SCFG_EXINTC4_EXINT13_GPD_Pos (4U) +#define SCFG_EXINTC4_EXINT13_GPD_Msk (0x3U << SCFG_EXINTC4_EXINT13_GPD_Pos) /*!< 0x00000030 */ +#define SCFG_EXINTC4_EXINT13_GPD SCFG_EXINTC4_EXINT13_GPD_Msk /*!< GPIOD pin 13 */ +#define SCFG_EXINTC4_EXINT13_GPF_Pos (6U) +#define SCFG_EXINTC4_EXINT13_GPF_Msk (0x1U << SCFG_EXINTC4_EXINT13_GPF_Pos) /*!< 0x00000040 */ +#define SCFG_EXINTC4_EXINT13_GPF SCFG_EXINTC4_EXINT13_GPF_Msk /*!< GPIOF pin 13 */ + +/*!< EXINT14 configuration */ +#define SCFG_EXINTC4_EXINT14_Pos (8U) +#define SCFG_EXINTC4_EXINT14_Msk (0xFU << SCFG_EXINTC4_EXINT14_Pos) /*!< 0x00000F00 */ +#define SCFG_EXINTC4_EXINT14 SCFG_EXINTC4_EXINT14_Msk /*!< EXINT14[3:0] bits (EXINT14 input source configuration) */ + +#define SCFG_EXINTC4_EXINT14_GPA 0x00000000U /*!< GPIOA pin 14 */ +#define SCFG_EXINTC4_EXINT14_GPB_Pos (8U) +#define SCFG_EXINTC4_EXINT14_GPB_Msk (0x1U << SCFG_EXINTC4_EXINT14_GPB_Pos) /*!< 0x00000100 */ +#define SCFG_EXINTC4_EXINT14_GPB SCFG_EXINTC4_EXINT14_GPB_Msk /*!< GPIOB pin 14 */ +#define SCFG_EXINTC4_EXINT14_GPC_Pos (9U) +#define SCFG_EXINTC4_EXINT14_GPC_Msk (0x1U << SCFG_EXINTC4_EXINT14_GPC_Pos) /*!< 0x00000200 */ +#define SCFG_EXINTC4_EXINT14_GPC SCFG_EXINTC4_EXINT14_GPC_Msk /*!< GPIOC pin 14 */ +#define SCFG_EXINTC4_EXINT14_GPD_Pos (8U) +#define SCFG_EXINTC4_EXINT14_GPD_Msk (0x3U << SCFG_EXINTC4_EXINT14_GPD_Pos) /*!< 0x00000300 */ +#define SCFG_EXINTC4_EXINT14_GPD SCFG_EXINTC4_EXINT14_GPD_Msk /*!< GPIOD pin 14 */ +#define SCFG_EXINTC4_EXINT14_GPF_Pos (10U) +#define SCFG_EXINTC4_EXINT14_GPF_Msk (0x1U << SCFG_EXINTC4_EXINT14_GPF_Pos) /*!< 0x00000400 */ +#define SCFG_EXINTC4_EXINT14_GPF SCFG_EXINTC4_EXINT14_GPF_Msk /*!< GPIOF pin 14 */ + +/*!< EXINT15 configuration */ +#define SCFG_EXINTC4_EXINT15_Pos (12U) +#define SCFG_EXINTC4_EXINT15_Msk (0xFU << SCFG_EXINTC4_EXINT15_Pos) /*!< 0x0000F000 */ +#define SCFG_EXINTC4_EXINT15 SCFG_EXINTC4_EXINT15_Msk /*!< EXINT15[3:0] bits (EXINT15 input source configuration) */ + +#define SCFG_EXINTC4_EXINT15_GPA 0x00000000U /*!< GPIOA pin 15 */ +#define SCFG_EXINTC4_EXINT15_GPB_Pos (12U) +#define SCFG_EXINTC4_EXINT15_GPB_Msk (0x1U << SCFG_EXINTC4_EXINT15_GPB_Pos) /*!< 0x00001000 */ +#define SCFG_EXINTC4_EXINT15_GPB SCFG_EXINTC4_EXINT15_GPB_Msk /*!< GPIOB pin 15 */ +#define SCFG_EXINTC4_EXINT15_GPC_Pos (13U) +#define SCFG_EXINTC4_EXINT15_GPC_Msk (0x1U << SCFG_EXINTC4_EXINT15_GPC_Pos) /*!< 0x00002000 */ +#define SCFG_EXINTC4_EXINT15_GPC SCFG_EXINTC4_EXINT15_GPC_Msk /*!< GPIOC pin 15 */ +#define SCFG_EXINTC4_EXINT15_GPD_Pos (12U) +#define SCFG_EXINTC4_EXINT15_GPD_Msk (0x3U << SCFG_EXINTC4_EXINT15_GPD_Pos) /*!< 0x00003000 */ +#define SCFG_EXINTC4_EXINT15_GPD SCFG_EXINTC4_EXINT15_GPD_Msk /*!< GPIOD pin 15 */ +#define SCFG_EXINTC4_EXINT15_GPF_Pos (14U) +#define SCFG_EXINTC4_EXINT15_GPF_Msk (0x1U << SCFG_EXINTC4_EXINT15_GPF_Pos) /*!< 0x00004000 */ +#define SCFG_EXINTC4_EXINT15_GPF SCFG_EXINTC4_EXINT15_GPF_Msk /*!< GPIOF pin 15 */ + +/****************** Bit definition for SCFG_UHDRV register ******************/ +#define SCFG_UHDRV_PB3_UH_Pos (0U) +#define SCFG_UHDRV_PB3_UH_Msk (0x1U << SCFG_UHDRV_PB3_UH_Pos) /*!< 0x00000001 */ +#define SCFG_UHDRV_PB3_UH SCFG_UHDRV_PB3_UH_Msk /*!< PB3 Ultra high sourcing/sinking strength */ +#define SCFG_UHDRV_PB9_UH_Pos (1U) +#define SCFG_UHDRV_PB9_UH_Msk (0x1U << SCFG_UHDRV_PB9_UH_Pos) /*!< 0x00000002 */ +#define SCFG_UHDRV_PB9_UH SCFG_UHDRV_PB9_UH_Msk /*!< PB9 Ultra high sourcing/sinking strength */ +#define SCFG_UHDRV_PB10_UH_Pos (2U) +#define SCFG_UHDRV_PB10_UH_Msk (0x1U << SCFG_UHDRV_PB10_UH_Pos) /*!< 0x00000004 */ +#define SCFG_UHDRV_PB10_UH SCFG_UHDRV_PB10_UH_Msk /*!< PB10 Ultra high sourcing/sinking strength */ + +/******************************************************************************/ +/* */ +/* External interrupt/Event controller (EXINT) */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for EXINT_INTEN register ******************/ +#define EXINT_INTEN_INTEN0_Pos (0U) +#define EXINT_INTEN_INTEN0_Msk (0x1U << EXINT_INTEN_INTEN0_Pos) /*!< 0x00000001 */ +#define EXINT_INTEN_INTEN0 EXINT_INTEN_INTEN0_Msk /*!< Interrupt enable or disable on line 0 */ +#define EXINT_INTEN_INTEN1_Pos (1U) +#define EXINT_INTEN_INTEN1_Msk (0x1U << EXINT_INTEN_INTEN1_Pos) /*!< 0x00000002 */ +#define EXINT_INTEN_INTEN1 EXINT_INTEN_INTEN1_Msk /*!< Interrupt enable or disable on line 1 */ +#define EXINT_INTEN_INTEN2_Pos (2U) +#define EXINT_INTEN_INTEN2_Msk (0x1U << EXINT_INTEN_INTEN2_Pos) /*!< 0x00000004 */ +#define EXINT_INTEN_INTEN2 EXINT_INTEN_INTEN2_Msk /*!< Interrupt enable or disable on line 2 */ +#define EXINT_INTEN_INTEN3_Pos (3U) +#define EXINT_INTEN_INTEN3_Msk (0x1U << EXINT_INTEN_INTEN3_Pos) /*!< 0x00000008 */ +#define EXINT_INTEN_INTEN3 EXINT_INTEN_INTEN3_Msk /*!< Interrupt enable or disable on line 3 */ +#define EXINT_INTEN_INTEN4_Pos (4U) +#define EXINT_INTEN_INTEN4_Msk (0x1U << EXINT_INTEN_INTEN4_Pos) /*!< 0x00000010 */ +#define EXINT_INTEN_INTEN4 EXINT_INTEN_INTEN4_Msk /*!< Interrupt enable or disable on line 4 */ +#define EXINT_INTEN_INTEN5_Pos (5U) +#define EXINT_INTEN_INTEN5_Msk (0x1U << EXINT_INTEN_INTEN5_Pos) /*!< 0x00000020 */ +#define EXINT_INTEN_INTEN5 EXINT_INTEN_INTEN5_Msk /*!< Interrupt enable or disable on line 5 */ +#define EXINT_INTEN_INTEN6_Pos (6U) +#define EXINT_INTEN_INTEN6_Msk (0x1U << EXINT_INTEN_INTEN6_Pos) /*!< 0x00000040 */ +#define EXINT_INTEN_INTEN6 EXINT_INTEN_INTEN6_Msk /*!< Interrupt enable or disable on line 6 */ +#define EXINT_INTEN_INTEN7_Pos (7U) +#define EXINT_INTEN_INTEN7_Msk (0x1U << EXINT_INTEN_INTEN7_Pos) /*!< 0x00000080 */ +#define EXINT_INTEN_INTEN7 EXINT_INTEN_INTEN7_Msk /*!< Interrupt enable or disable on line 7 */ +#define EXINT_INTEN_INTEN8_Pos (8U) +#define EXINT_INTEN_INTEN8_Msk (0x1U << EXINT_INTEN_INTEN8_Pos) /*!< 0x00000100 */ +#define EXINT_INTEN_INTEN8 EXINT_INTEN_INTEN8_Msk /*!< Interrupt enable or disable on line 8 */ +#define EXINT_INTEN_INTEN9_Pos (9U) +#define EXINT_INTEN_INTEN9_Msk (0x1U << EXINT_INTEN_INTEN9_Pos) /*!< 0x00000200 */ +#define EXINT_INTEN_INTEN9 EXINT_INTEN_INTEN9_Msk /*!< Interrupt enable or disable on line 9 */ +#define EXINT_INTEN_INTEN10_Pos (10U) +#define EXINT_INTEN_INTEN10_Msk (0x1U << EXINT_INTEN_INTEN10_Pos) /*!< 0x00000400 */ +#define EXINT_INTEN_INTEN10 EXINT_INTEN_INTEN10_Msk /*!< Interrupt enable or disable on line 10 */ +#define EXINT_INTEN_INTEN11_Pos (11U) +#define EXINT_INTEN_INTEN11_Msk (0x1U << EXINT_INTEN_INTEN11_Pos) /*!< 0x00000800 */ +#define EXINT_INTEN_INTEN11 EXINT_INTEN_INTEN11_Msk /*!< Interrupt enable or disable on line 11 */ +#define EXINT_INTEN_INTEN12_Pos (12U) +#define EXINT_INTEN_INTEN12_Msk (0x1U << EXINT_INTEN_INTEN12_Pos) /*!< 0x00001000 */ +#define EXINT_INTEN_INTEN12 EXINT_INTEN_INTEN12_Msk /*!< Interrupt enable or disable on line 12 */ +#define EXINT_INTEN_INTEN13_Pos (13U) +#define EXINT_INTEN_INTEN13_Msk (0x1U << EXINT_INTEN_INTEN13_Pos) /*!< 0x00002000 */ +#define EXINT_INTEN_INTEN13 EXINT_INTEN_INTEN13_Msk /*!< Interrupt enable or disable on line 13 */ +#define EXINT_INTEN_INTEN14_Pos (14U) +#define EXINT_INTEN_INTEN14_Msk (0x1U << EXINT_INTEN_INTEN14_Pos) /*!< 0x00004000 */ +#define EXINT_INTEN_INTEN14 EXINT_INTEN_INTEN14_Msk /*!< Interrupt enable or disable on line 14 */ +#define EXINT_INTEN_INTEN15_Pos (15U) +#define EXINT_INTEN_INTEN15_Msk (0x1U << EXINT_INTEN_INTEN15_Pos) /*!< 0x00008000 */ +#define EXINT_INTEN_INTEN15 EXINT_INTEN_INTEN15_Msk /*!< Interrupt enable or disable on line 15 */ +#define EXINT_INTEN_INTEN16_Pos (16U) +#define EXINT_INTEN_INTEN16_Msk (0x1U << EXINT_INTEN_INTEN16_Pos) /*!< 0x00010000 */ +#define EXINT_INTEN_INTEN16 EXINT_INTEN_INTEN16_Msk /*!< Interrupt enable or disable on line 16 */ +#define EXINT_INTEN_INTEN17_Pos (17U) +#define EXINT_INTEN_INTEN17_Msk (0x1U << EXINT_INTEN_INTEN17_Pos) /*!< 0x00020000 */ +#define EXINT_INTEN_INTEN17 EXINT_INTEN_INTEN17_Msk /*!< Interrupt enable or disable on line 17 */ +#define EXINT_INTEN_INTEN18_Pos (18U) +#define EXINT_INTEN_INTEN18_Msk (0x1U << EXINT_INTEN_INTEN18_Pos) /*!< 0x00040000 */ +#define EXINT_INTEN_INTEN18 EXINT_INTEN_INTEN18_Msk /*!< Interrupt enable or disable on line 18 */ +#define EXINT_INTEN_INTEN20_Pos (20U) +#define EXINT_INTEN_INTEN20_Msk (0x1U << EXINT_INTEN_INTEN20_Pos) /*!< 0x00100000 */ +#define EXINT_INTEN_INTEN20 EXINT_INTEN_INTEN20_Msk /*!< Interrupt enable or disable on line 20 (F405 only) */ +#define EXINT_INTEN_INTEN21_Pos (21U) +#define EXINT_INTEN_INTEN21_Msk (0x1U << EXINT_INTEN_INTEN21_Pos) /*!< 0x00200000 */ +#define EXINT_INTEN_INTEN21 EXINT_INTEN_INTEN21_Msk /*!< Interrupt enable or disable on line 21 */ +#define EXINT_INTEN_INTEN22_Pos (22U) +#define EXINT_INTEN_INTEN22_Msk (0x1U << EXINT_INTEN_INTEN22_Pos) /*!< 0x00400000 */ +#define EXINT_INTEN_INTEN22 EXINT_INTEN_INTEN22_Msk /*!< Interrupt enable or disable on line 22 */ + +/* References Defines */ +#define EXINT_INTEN_INT0 EXINT_INTEN_INTEN0 +#define EXINT_INTEN_INT1 EXINT_INTEN_INTEN1 +#define EXINT_INTEN_INT2 EXINT_INTEN_INTEN2 +#define EXINT_INTEN_INT3 EXINT_INTEN_INTEN3 +#define EXINT_INTEN_INT4 EXINT_INTEN_INTEN4 +#define EXINT_INTEN_INT5 EXINT_INTEN_INTEN5 +#define EXINT_INTEN_INT6 EXINT_INTEN_INTEN6 +#define EXINT_INTEN_INT7 EXINT_INTEN_INTEN7 +#define EXINT_INTEN_INT8 EXINT_INTEN_INTEN8 +#define EXINT_INTEN_INT9 EXINT_INTEN_INTEN9 +#define EXINT_INTEN_INT10 EXINT_INTEN_INTEN10 +#define EXINT_INTEN_INT11 EXINT_INTEN_INTEN11 +#define EXINT_INTEN_INT12 EXINT_INTEN_INTEN12 +#define EXINT_INTEN_INT13 EXINT_INTEN_INTEN13 +#define EXINT_INTEN_INT14 EXINT_INTEN_INTEN14 +#define EXINT_INTEN_INT15 EXINT_INTEN_INTEN15 +#define EXINT_INTEN_INT16 EXINT_INTEN_INTEN16 +#define EXINT_INTEN_INT17 EXINT_INTEN_INTEN17 +#define EXINT_INTEN_INT18 EXINT_INTEN_INTEN18 +#define EXINT_INTEN_INT20 EXINT_INTEN_INTEN20 +#define EXINT_INTEN_INT21 EXINT_INTEN_INTEN21 +#define EXINT_INTEN_INT22 EXINT_INTEN_INTEN22 +#define EXINT_INTEN_INT 0x0077FFFFU /*!< Interrupt enable or disable all */ + +/***************** Bit definition for EXINT_EVTEN register ******************/ +#define EXINT_EVTEN_EVTEN0_Pos (0U) +#define EXINT_EVTEN_EVTEN0_Msk (0x1U << EXINT_EVTEN_EVTEN0_Pos) /*!< 0x00000001 */ +#define EXINT_EVTEN_EVTEN0 EXINT_EVTEN_EVTEN0_Msk /*!< Event enable or disable on line 0 */ +#define EXINT_EVTEN_EVTEN1_Pos (1U) +#define EXINT_EVTEN_EVTEN1_Msk (0x1U << EXINT_EVTEN_EVTEN1_Pos) /*!< 0x00000002 */ +#define EXINT_EVTEN_EVTEN1 EXINT_EVTEN_EVTEN1_Msk /*!< Event enable or disable on line 1 */ +#define EXINT_EVTEN_EVTEN2_Pos (2U) +#define EXINT_EVTEN_EVTEN2_Msk (0x1U << EXINT_EVTEN_EVTEN2_Pos) /*!< 0x00000004 */ +#define EXINT_EVTEN_EVTEN2 EXINT_EVTEN_EVTEN2_Msk /*!< Event enable or disable on line 2 */ +#define EXINT_EVTEN_EVTEN3_Pos (3U) +#define EXINT_EVTEN_EVTEN3_Msk (0x1U << EXINT_EVTEN_EVTEN3_Pos) /*!< 0x00000008 */ +#define EXINT_EVTEN_EVTEN3 EXINT_EVTEN_EVTEN3_Msk /*!< Event enable or disable on line 3 */ +#define EXINT_EVTEN_EVTEN4_Pos (4U) +#define EXINT_EVTEN_EVTEN4_Msk (0x1U << EXINT_EVTEN_EVTEN4_Pos) /*!< 0x00000010 */ +#define EXINT_EVTEN_EVTEN4 EXINT_EVTEN_EVTEN4_Msk /*!< Event enable or disable on line 4 */ +#define EXINT_EVTEN_EVTEN5_Pos (5U) +#define EXINT_EVTEN_EVTEN5_Msk (0x1U << EXINT_EVTEN_EVTEN5_Pos) /*!< 0x00000020 */ +#define EXINT_EVTEN_EVTEN5 EXINT_EVTEN_EVTEN5_Msk /*!< Event enable or disable on line 5 */ +#define EXINT_EVTEN_EVTEN6_Pos (6U) +#define EXINT_EVTEN_EVTEN6_Msk (0x1U << EXINT_EVTEN_EVTEN6_Pos) /*!< 0x00000040 */ +#define EXINT_EVTEN_EVTEN6 EXINT_EVTEN_EVTEN6_Msk /*!< Event enable or disable on line 6 */ +#define EXINT_EVTEN_EVTEN7_Pos (7U) +#define EXINT_EVTEN_EVTEN7_Msk (0x1U << EXINT_EVTEN_EVTEN7_Pos) /*!< 0x00000080 */ +#define EXINT_EVTEN_EVTEN7 EXINT_EVTEN_EVTEN7_Msk /*!< Event enable or disable on line 7 */ +#define EXINT_EVTEN_EVTEN8_Pos (8U) +#define EXINT_EVTEN_EVTEN8_Msk (0x1U << EXINT_EVTEN_EVTEN8_Pos) /*!< 0x00000100 */ +#define EXINT_EVTEN_EVTEN8 EXINT_EVTEN_EVTEN8_Msk /*!< Event enable or disable on line 8 */ +#define EXINT_EVTEN_EVTEN9_Pos (9U) +#define EXINT_EVTEN_EVTEN9_Msk (0x1U << EXINT_EVTEN_EVTEN9_Pos) /*!< 0x00000200 */ +#define EXINT_EVTEN_EVTEN9 EXINT_EVTEN_EVTEN9_Msk /*!< Event enable or disable on line 9 */ +#define EXINT_EVTEN_EVTEN10_Pos (10U) +#define EXINT_EVTEN_EVTEN10_Msk (0x1U << EXINT_EVTEN_EVTEN10_Pos) /*!< 0x00000400 */ +#define EXINT_EVTEN_EVTEN10 EXINT_EVTEN_EVTEN10_Msk /*!< Event enable or disable on line 10 */ +#define EXINT_EVTEN_EVTEN11_Pos (11U) +#define EXINT_EVTEN_EVTEN11_Msk (0x1U << EXINT_EVTEN_EVTEN11_Pos) /*!< 0x00000800 */ +#define EXINT_EVTEN_EVTEN11 EXINT_EVTEN_EVTEN11_Msk /*!< Event enable or disable on line 11 */ +#define EXINT_EVTEN_EVTEN12_Pos (12U) +#define EXINT_EVTEN_EVTEN12_Msk (0x1U << EXINT_EVTEN_EVTEN12_Pos) /*!< 0x00001000 */ +#define EXINT_EVTEN_EVTEN12 EXINT_EVTEN_EVTEN12_Msk /*!< Event enable or disable on line 12 */ +#define EXINT_EVTEN_EVTEN13_Pos (13U) +#define EXINT_EVTEN_EVTEN13_Msk (0x1U << EXINT_EVTEN_EVTEN13_Pos) /*!< 0x00002000 */ +#define EXINT_EVTEN_EVTEN13 EXINT_EVTEN_EVTEN13_Msk /*!< Event enable or disable on line 13 */ +#define EXINT_EVTEN_EVTEN14_Pos (14U) +#define EXINT_EVTEN_EVTEN14_Msk (0x1U << EXINT_EVTEN_EVTEN14_Pos) /*!< 0x00004000 */ +#define EXINT_EVTEN_EVTEN14 EXINT_EVTEN_EVTEN14_Msk /*!< Event enable or disable on line 14 */ +#define EXINT_EVTEN_EVTEN15_Pos (15U) +#define EXINT_EVTEN_EVTEN15_Msk (0x1U << EXINT_EVTEN_EVTEN15_Pos) /*!< 0x00008000 */ +#define EXINT_EVTEN_EVTEN15 EXINT_EVTEN_EVTEN15_Msk /*!< Event enable or disable on line 15 */ +#define EXINT_EVTEN_EVTEN16_Pos (16U) +#define EXINT_EVTEN_EVTEN16_Msk (0x1U << EXINT_EVTEN_EVTEN16_Pos) /*!< 0x00010000 */ +#define EXINT_EVTEN_EVTEN16 EXINT_EVTEN_EVTEN16_Msk /*!< Event enable or disable on line 16 */ +#define EXINT_EVTEN_EVTEN17_Pos (17U) +#define EXINT_EVTEN_EVTEN17_Msk (0x1U << EXINT_EVTEN_EVTEN17_Pos) /*!< 0x00020000 */ +#define EXINT_EVTEN_EVTEN17 EXINT_EVTEN_EVTEN17_Msk /*!< Event enable or disable on line 17 */ +#define EXINT_EVTEN_EVTEN18_Pos (18U) +#define EXINT_EVTEN_EVTEN18_Msk (0x1U << EXINT_EVTEN_EVTEN18_Pos) /*!< 0x00040000 */ +#define EXINT_EVTEN_EVTEN18 EXINT_EVTEN_EVTEN18_Msk /*!< Event enable or disable on line 18 */ +#define EXINT_EVTEN_EVTEN20_Pos (20U) +#define EXINT_EVTEN_EVTEN20_Msk (0x1U << EXINT_EVTEN_EVTEN20_Pos) /*!< 0x00100000 */ +#define EXINT_EVTEN_EVTEN20 EXINT_EVTEN_EVTEN20_Msk /*!< Event enable or disable on line 20 (F405 only) */ +#define EXINT_EVTEN_EVTEN21_Pos (21U) +#define EXINT_EVTEN_EVTEN21_Msk (0x1U << EXINT_EVTEN_EVTEN21_Pos) /*!< 0x00200000 */ +#define EXINT_EVTEN_EVTEN21 EXINT_EVTEN_EVTEN21_Msk /*!< Event enable or disable on line 21 */ +#define EXINT_EVTEN_EVTEN22_Pos (22U) +#define EXINT_EVTEN_EVTEN22_Msk (0x1U << EXINT_EVTEN_EVTEN22_Pos) /*!< 0x00400000 */ +#define EXINT_EVTEN_EVTEN22 EXINT_EVTEN_EVTEN22_Msk /*!< Event enable or disable on line 22 */ + +/* References Defines */ +#define EXINT_EVTEN_EVT0 EXINT_EVTEN_EVTEN0 +#define EXINT_EVTEN_EVT1 EXINT_EVTEN_EVTEN1 +#define EXINT_EVTEN_EVT2 EXINT_EVTEN_EVTEN2 +#define EXINT_EVTEN_EVT3 EXINT_EVTEN_EVTEN3 +#define EXINT_EVTEN_EVT4 EXINT_EVTEN_EVTEN4 +#define EXINT_EVTEN_EVT5 EXINT_EVTEN_EVTEN5 +#define EXINT_EVTEN_EVT6 EXINT_EVTEN_EVTEN6 +#define EXINT_EVTEN_EVT7 EXINT_EVTEN_EVTEN7 +#define EXINT_EVTEN_EVT8 EXINT_EVTEN_EVTEN8 +#define EXINT_EVTEN_EVT9 EXINT_EVTEN_EVTEN9 +#define EXINT_EVTEN_EVT10 EXINT_EVTEN_EVTEN10 +#define EXINT_EVTEN_EVT11 EXINT_EVTEN_EVTEN11 +#define EXINT_EVTEN_EVT12 EXINT_EVTEN_EVTEN12 +#define EXINT_EVTEN_EVT13 EXINT_EVTEN_EVTEN13 +#define EXINT_EVTEN_EVT14 EXINT_EVTEN_EVTEN14 +#define EXINT_EVTEN_EVT15 EXINT_EVTEN_EVTEN15 +#define EXINT_EVTEN_EVT16 EXINT_EVTEN_EVTEN16 +#define EXINT_EVTEN_EVT17 EXINT_EVTEN_EVTEN17 +#define EXINT_EVTEN_EVT18 EXINT_EVTEN_EVTEN18 +#define EXINT_EVTEN_EVT20 EXINT_EVTEN_EVTEN20 +#define EXINT_EVTEN_EVT21 EXINT_EVTEN_EVTEN21 +#define EXINT_EVTEN_EVT22 EXINT_EVTEN_EVTEN22 + +/**************** Bit definition for EXINT_POLCFG1 register *****************/ +#define EXINT_POLCFG1_RP0_Pos (0U) +#define EXINT_POLCFG1_RP0_Msk (0x1U << EXINT_POLCFG1_RP0_Pos) /*!< 0x00000001 */ +#define EXINT_POLCFG1_RP0 EXINT_POLCFG1_RP0_Msk /*!< Rising edge event configuration bit on line 0 */ +#define EXINT_POLCFG1_RP1_Pos (1U) +#define EXINT_POLCFG1_RP1_Msk (0x1U << EXINT_POLCFG1_RP1_Pos) /*!< 0x00000002 */ +#define EXINT_POLCFG1_RP1 EXINT_POLCFG1_RP1_Msk /*!< Rising edge event configuration bit on line 1 */ +#define EXINT_POLCFG1_RP2_Pos (2U) +#define EXINT_POLCFG1_RP2_Msk (0x1U << EXINT_POLCFG1_RP2_Pos) /*!< 0x00000004 */ +#define EXINT_POLCFG1_RP2 EXINT_POLCFG1_RP2_Msk /*!< Rising edge event configuration bit on line 2 */ +#define EXINT_POLCFG1_RP3_Pos (3U) +#define EXINT_POLCFG1_RP3_Msk (0x1U << EXINT_POLCFG1_RP3_Pos) /*!< 0x00000008 */ +#define EXINT_POLCFG1_RP3 EXINT_POLCFG1_RP3_Msk /*!< Rising edge event configuration bit on line 3 */ +#define EXINT_POLCFG1_RP4_Pos (4U) +#define EXINT_POLCFG1_RP4_Msk (0x1U << EXINT_POLCFG1_RP4_Pos) /*!< 0x00000010 */ +#define EXINT_POLCFG1_RP4 EXINT_POLCFG1_RP4_Msk /*!< Rising edge event configuration bit on line 4 */ +#define EXINT_POLCFG1_RP5_Pos (5U) +#define EXINT_POLCFG1_RP5_Msk (0x1U << EXINT_POLCFG1_RP5_Pos) /*!< 0x00000020 */ +#define EXINT_POLCFG1_RP5 EXINT_POLCFG1_RP5_Msk /*!< Rising edge event configuration bit on line 5 */ +#define EXINT_POLCFG1_RP6_Pos (6U) +#define EXINT_POLCFG1_RP6_Msk (0x1U << EXINT_POLCFG1_RP6_Pos) /*!< 0x00000040 */ +#define EXINT_POLCFG1_RP6 EXINT_POLCFG1_RP6_Msk /*!< Rising edge event configuration bit on line 6 */ +#define EXINT_POLCFG1_RP7_Pos (7U) +#define EXINT_POLCFG1_RP7_Msk (0x1U << EXINT_POLCFG1_RP7_Pos) /*!< 0x00000080 */ +#define EXINT_POLCFG1_RP7 EXINT_POLCFG1_RP7_Msk /*!< Rising edge event configuration bit on line 7 */ +#define EXINT_POLCFG1_RP8_Pos (8U) +#define EXINT_POLCFG1_RP8_Msk (0x1U << EXINT_POLCFG1_RP8_Pos) /*!< 0x00000100 */ +#define EXINT_POLCFG1_RP8 EXINT_POLCFG1_RP8_Msk /*!< Rising edge event configuration bit on line 8 */ +#define EXINT_POLCFG1_RP9_Pos (9U) +#define EXINT_POLCFG1_RP9_Msk (0x1U << EXINT_POLCFG1_RP9_Pos) /*!< 0x00000200 */ +#define EXINT_POLCFG1_RP9 EXINT_POLCFG1_RP9_Msk /*!< Rising edge event configuration bit on line 9 */ +#define EXINT_POLCFG1_RP10_Pos (10U) +#define EXINT_POLCFG1_RP10_Msk (0x1U << EXINT_POLCFG1_RP10_Pos) /*!< 0x00000400 */ +#define EXINT_POLCFG1_RP10 EXINT_POLCFG1_RP10_Msk /*!< Rising edge event configuration bit on line 10 */ +#define EXINT_POLCFG1_RP11_Pos (11U) +#define EXINT_POLCFG1_RP11_Msk (0x1U << EXINT_POLCFG1_RP11_Pos) /*!< 0x00000800 */ +#define EXINT_POLCFG1_RP11 EXINT_POLCFG1_RP11_Msk /*!< Rising edge event configuration bit on line 11 */ +#define EXINT_POLCFG1_RP12_Pos (12U) +#define EXINT_POLCFG1_RP12_Msk (0x1U << EXINT_POLCFG1_RP12_Pos) /*!< 0x00001000 */ +#define EXINT_POLCFG1_RP12 EXINT_POLCFG1_RP12_Msk /*!< Rising edge event configuration bit on line 12 */ +#define EXINT_POLCFG1_RP13_Pos (13U) +#define EXINT_POLCFG1_RP13_Msk (0x1U << EXINT_POLCFG1_RP13_Pos) /*!< 0x00002000 */ +#define EXINT_POLCFG1_RP13 EXINT_POLCFG1_RP13_Msk /*!< Rising edge event configuration bit on line 13 */ +#define EXINT_POLCFG1_RP14_Pos (14U) +#define EXINT_POLCFG1_RP14_Msk (0x1U << EXINT_POLCFG1_RP14_Pos) /*!< 0x00004000 */ +#define EXINT_POLCFG1_RP14 EXINT_POLCFG1_RP14_Msk /*!< Rising edge event configuration bit on line 14 */ +#define EXINT_POLCFG1_RP15_Pos (15U) +#define EXINT_POLCFG1_RP15_Msk (0x1U << EXINT_POLCFG1_RP15_Pos) /*!< 0x00008000 */ +#define EXINT_POLCFG1_RP15 EXINT_POLCFG1_RP15_Msk /*!< Rising edge event configuration bit on line 15 */ +#define EXINT_POLCFG1_RP16_Pos (16U) +#define EXINT_POLCFG1_RP16_Msk (0x1U << EXINT_POLCFG1_RP16_Pos) /*!< 0x00010000 */ +#define EXINT_POLCFG1_RP16 EXINT_POLCFG1_RP16_Msk /*!< Rising edge event configuration bit on line 16 */ +#define EXINT_POLCFG1_RP17_Pos (17U) +#define EXINT_POLCFG1_RP17_Msk (0x1U << EXINT_POLCFG1_RP17_Pos) /*!< 0x00020000 */ +#define EXINT_POLCFG1_RP17 EXINT_POLCFG1_RP17_Msk /*!< Rising edge event configuration bit on line 17 */ +#define EXINT_POLCFG1_RP18_Pos (18U) +#define EXINT_POLCFG1_RP18_Msk (0x1U << EXINT_POLCFG1_RP18_Pos) /*!< 0x00040000 */ +#define EXINT_POLCFG1_RP18 EXINT_POLCFG1_RP18_Msk /*!< Rising edge event configuration bit on line 18 */ +#define EXINT_POLCFG1_RP20_Pos (20U) +#define EXINT_POLCFG1_RP20_Msk (0x1U << EXINT_POLCFG1_RP20_Pos) /*!< 0x00100000 */ +#define EXINT_POLCFG1_RP20 EXINT_POLCFG1_RP20_Msk /*!< Rising edge event configuration bit on line 20 (F405 only) */ +#define EXINT_POLCFG1_RP21_Pos (21U) +#define EXINT_POLCFG1_RP21_Msk (0x1U << EXINT_POLCFG1_RP21_Pos) /*!< 0x00200000 */ +#define EXINT_POLCFG1_RP21 EXINT_POLCFG1_RP21_Msk /*!< Rising edge event configuration bit on line 21 */ +#define EXINT_POLCFG1_RP22_Pos (22U) +#define EXINT_POLCFG1_RP22_Msk (0x1U << EXINT_POLCFG1_RP22_Pos) /*!< 0x00400000 */ +#define EXINT_POLCFG1_RP22 EXINT_POLCFG1_RP22_Msk /*!< Rising edge event configuration bit on line 22 */ + +/* References Defines */ +#define EXINT_POLCFG1_POL0 EXINT_POLCFG1_RP0 +#define EXINT_POLCFG1_POL1 EXINT_POLCFG1_RP1 +#define EXINT_POLCFG1_POL2 EXINT_POLCFG1_RP2 +#define EXINT_POLCFG1_POL3 EXINT_POLCFG1_RP3 +#define EXINT_POLCFG1_POL4 EXINT_POLCFG1_RP4 +#define EXINT_POLCFG1_POL5 EXINT_POLCFG1_RP5 +#define EXINT_POLCFG1_POL6 EXINT_POLCFG1_RP6 +#define EXINT_POLCFG1_POL7 EXINT_POLCFG1_RP7 +#define EXINT_POLCFG1_POL8 EXINT_POLCFG1_RP8 +#define EXINT_POLCFG1_POL9 EXINT_POLCFG1_RP9 +#define EXINT_POLCFG1_POL10 EXINT_POLCFG1_RP10 +#define EXINT_POLCFG1_POL11 EXINT_POLCFG1_RP11 +#define EXINT_POLCFG1_POL12 EXINT_POLCFG1_RP12 +#define EXINT_POLCFG1_POL13 EXINT_POLCFG1_RP13 +#define EXINT_POLCFG1_POL14 EXINT_POLCFG1_RP14 +#define EXINT_POLCFG1_POL15 EXINT_POLCFG1_RP15 +#define EXINT_POLCFG1_POL16 EXINT_POLCFG1_RP16 +#define EXINT_POLCFG1_POL17 EXINT_POLCFG1_RP17 +#define EXINT_POLCFG1_POL18 EXINT_POLCFG1_RP18 +#define EXINT_POLCFG1_POL20 EXINT_POLCFG1_RP20 +#define EXINT_POLCFG1_POL21 EXINT_POLCFG1_RP21 +#define EXINT_POLCFG1_POL22 EXINT_POLCFG1_RP22 + +/**************** Bit definition for EXINT_POLCFG2 register *****************/ +#define EXINT_POLCFG2_FP0_Pos (0U) +#define EXINT_POLCFG2_FP0_Msk (0x1U << EXINT_POLCFG2_FP0_Pos) /*!< 0x00000001 */ +#define EXINT_POLCFG2_FP0 EXINT_POLCFG2_FP0_Msk /*!< Falling edge event configuration bit on line 0 */ +#define EXINT_POLCFG2_FP1_Pos (1U) +#define EXINT_POLCFG2_FP1_Msk (0x1U << EXINT_POLCFG2_FP1_Pos) /*!< 0x00000002 */ +#define EXINT_POLCFG2_FP1 EXINT_POLCFG2_FP1_Msk /*!< Falling edge event configuration bit on line 1 */ +#define EXINT_POLCFG2_FP2_Pos (2U) +#define EXINT_POLCFG2_FP2_Msk (0x1U << EXINT_POLCFG2_FP2_Pos) /*!< 0x00000004 */ +#define EXINT_POLCFG2_FP2 EXINT_POLCFG2_FP2_Msk /*!< Falling edge event configuration bit on line 2 */ +#define EXINT_POLCFG2_FP3_Pos (3U) +#define EXINT_POLCFG2_FP3_Msk (0x1U << EXINT_POLCFG2_FP3_Pos) /*!< 0x00000008 */ +#define EXINT_POLCFG2_FP3 EXINT_POLCFG2_FP3_Msk /*!< Falling edge event configuration bit on line 3 */ +#define EXINT_POLCFG2_FP4_Pos (4U) +#define EXINT_POLCFG2_FP4_Msk (0x1U << EXINT_POLCFG2_FP4_Pos) /*!< 0x00000010 */ +#define EXINT_POLCFG2_FP4 EXINT_POLCFG2_FP4_Msk /*!< Falling edge event configuration bit on line 4 */ +#define EXINT_POLCFG2_FP5_Pos (5U) +#define EXINT_POLCFG2_FP5_Msk (0x1U << EXINT_POLCFG2_FP5_Pos) /*!< 0x00000020 */ +#define EXINT_POLCFG2_FP5 EXINT_POLCFG2_FP5_Msk /*!< Falling edge event configuration bit on line 5 */ +#define EXINT_POLCFG2_FP6_Pos (6U) +#define EXINT_POLCFG2_FP6_Msk (0x1U << EXINT_POLCFG2_FP6_Pos) /*!< 0x00000040 */ +#define EXINT_POLCFG2_FP6 EXINT_POLCFG2_FP6_Msk /*!< Falling edge event configuration bit on line 6 */ +#define EXINT_POLCFG2_FP7_Pos (7U) +#define EXINT_POLCFG2_FP7_Msk (0x1U << EXINT_POLCFG2_FP7_Pos) /*!< 0x00000080 */ +#define EXINT_POLCFG2_FP7 EXINT_POLCFG2_FP7_Msk /*!< Falling edge event configuration bit on line 7 */ +#define EXINT_POLCFG2_FP8_Pos (8U) +#define EXINT_POLCFG2_FP8_Msk (0x1U << EXINT_POLCFG2_FP8_Pos) /*!< 0x00000100 */ +#define EXINT_POLCFG2_FP8 EXINT_POLCFG2_FP8_Msk /*!< Falling edge event configuration bit on line 8 */ +#define EXINT_POLCFG2_FP9_Pos (9U) +#define EXINT_POLCFG2_FP9_Msk (0x1U << EXINT_POLCFG2_FP9_Pos) /*!< 0x00000200 */ +#define EXINT_POLCFG2_FP9 EXINT_POLCFG2_FP9_Msk /*!< Falling edge event configuration bit on line 9 */ +#define EXINT_POLCFG2_FP10_Pos (10U) +#define EXINT_POLCFG2_FP10_Msk (0x1U << EXINT_POLCFG2_FP10_Pos) /*!< 0x00000400 */ +#define EXINT_POLCFG2_FP10 EXINT_POLCFG2_FP10_Msk /*!< Falling edge event configuration bit on line 10 */ +#define EXINT_POLCFG2_FP11_Pos (11U) +#define EXINT_POLCFG2_FP11_Msk (0x1U << EXINT_POLCFG2_FP11_Pos) /*!< 0x00000800 */ +#define EXINT_POLCFG2_FP11 EXINT_POLCFG2_FP11_Msk /*!< Falling edge event configuration bit on line 11 */ +#define EXINT_POLCFG2_FP12_Pos (12U) +#define EXINT_POLCFG2_FP12_Msk (0x1U << EXINT_POLCFG2_FP12_Pos) /*!< 0x00001000 */ +#define EXINT_POLCFG2_FP12 EXINT_POLCFG2_FP12_Msk /*!< Falling edge event configuration bit on line 12 */ +#define EXINT_POLCFG2_FP13_Pos (13U) +#define EXINT_POLCFG2_FP13_Msk (0x1U << EXINT_POLCFG2_FP13_Pos) /*!< 0x00002000 */ +#define EXINT_POLCFG2_FP13 EXINT_POLCFG2_FP13_Msk /*!< Falling edge event configuration bit on line 13 */ +#define EXINT_POLCFG2_FP14_Pos (14U) +#define EXINT_POLCFG2_FP14_Msk (0x1U << EXINT_POLCFG2_FP14_Pos) /*!< 0x00004000 */ +#define EXINT_POLCFG2_FP14 EXINT_POLCFG2_FP14_Msk /*!< Falling edge event configuration bit on line 14 */ +#define EXINT_POLCFG2_FP15_Pos (15U) +#define EXINT_POLCFG2_FP15_Msk (0x1U << EXINT_POLCFG2_FP15_Pos) /*!< 0x00008000 */ +#define EXINT_POLCFG2_FP15 EXINT_POLCFG2_FP15_Msk /*!< Falling edge event configuration bit on line 15 */ +#define EXINT_POLCFG2_FP16_Pos (16U) +#define EXINT_POLCFG2_FP16_Msk (0x1U << EXINT_POLCFG2_FP16_Pos) /*!< 0x00010000 */ +#define EXINT_POLCFG2_FP16 EXINT_POLCFG2_FP16_Msk /*!< Falling edge event configuration bit on line 16 */ +#define EXINT_POLCFG2_FP17_Pos (17U) +#define EXINT_POLCFG2_FP17_Msk (0x1U << EXINT_POLCFG2_FP17_Pos) /*!< 0x00020000 */ +#define EXINT_POLCFG2_FP17 EXINT_POLCFG2_FP17_Msk /*!< Falling edge event configuration bit on line 17 */ +#define EXINT_POLCFG2_FP18_Pos (18U) +#define EXINT_POLCFG2_FP18_Msk (0x1U << EXINT_POLCFG2_FP18_Pos) /*!< 0x00040000 */ +#define EXINT_POLCFG2_FP18 EXINT_POLCFG2_FP18_Msk /*!< Falling edge event configuration bit on line 18 */ +#define EXINT_POLCFG2_FP20_Pos (20U) +#define EXINT_POLCFG2_FP20_Msk (0x1U << EXINT_POLCFG2_FP20_Pos) /*!< 0x00100000 */ +#define EXINT_POLCFG2_FP20 EXINT_POLCFG2_FP20_Msk /*!< Falling edge event configuration bit on line 20 (F405 only) */ +#define EXINT_POLCFG2_FP21_Pos (21U) +#define EXINT_POLCFG2_FP21_Msk (0x1U << EXINT_POLCFG2_FP21_Pos) /*!< 0x00200000 */ +#define EXINT_POLCFG2_FP21 EXINT_POLCFG2_FP21_Msk /*!< Falling edge event configuration bit on line 21 */ +#define EXINT_POLCFG2_FP22_Pos (22U) +#define EXINT_POLCFG2_FP22_Msk (0x1U << EXINT_POLCFG2_FP22_Pos) /*!< 0x00400000 */ +#define EXINT_POLCFG2_FP22 EXINT_POLCFG2_FP22_Msk /*!< Falling edge event configuration bit on line 22 */ + +/* References Defines */ +#define EXINT_POLCFG2_POL0 EXINT_POLCFG2_FP0 +#define EXINT_POLCFG2_POL1 EXINT_POLCFG2_FP1 +#define EXINT_POLCFG2_POL2 EXINT_POLCFG2_FP2 +#define EXINT_POLCFG2_POL3 EXINT_POLCFG2_FP3 +#define EXINT_POLCFG2_POL4 EXINT_POLCFG2_FP4 +#define EXINT_POLCFG2_POL5 EXINT_POLCFG2_FP5 +#define EXINT_POLCFG2_POL6 EXINT_POLCFG2_FP6 +#define EXINT_POLCFG2_POL7 EXINT_POLCFG2_FP7 +#define EXINT_POLCFG2_POL8 EXINT_POLCFG2_FP8 +#define EXINT_POLCFG2_POL9 EXINT_POLCFG2_FP9 +#define EXINT_POLCFG2_POL10 EXINT_POLCFG2_FP10 +#define EXINT_POLCFG2_POL11 EXINT_POLCFG2_FP11 +#define EXINT_POLCFG2_POL12 EXINT_POLCFG2_FP12 +#define EXINT_POLCFG2_POL13 EXINT_POLCFG2_FP13 +#define EXINT_POLCFG2_POL14 EXINT_POLCFG2_FP14 +#define EXINT_POLCFG2_POL15 EXINT_POLCFG2_FP15 +#define EXINT_POLCFG2_POL16 EXINT_POLCFG2_FP16 +#define EXINT_POLCFG2_POL17 EXINT_POLCFG2_FP17 +#define EXINT_POLCFG2_POL18 EXINT_POLCFG2_FP18 +#define EXINT_POLCFG2_POL20 EXINT_POLCFG2_FP20 +#define EXINT_POLCFG2_POL21 EXINT_POLCFG2_FP21 +#define EXINT_POLCFG2_POL22 EXINT_POLCFG2_FP22 + +/***************** Bit definition for EXINT_SWTRG register ******************/ +#define EXINT_SWTRG_SWT0_Pos (0U) +#define EXINT_SWTRG_SWT0_Msk (0x1U << EXINT_SWTRG_SWT0_Pos) /*!< 0x00000001 */ +#define EXINT_SWTRG_SWT0 EXINT_SWTRG_SWT0_Msk /*!< Software trigger on line 0 */ +#define EXINT_SWTRG_SWT1_Pos (1U) +#define EXINT_SWTRG_SWT1_Msk (0x1U << EXINT_SWTRG_SWT1_Pos) /*!< 0x00000002 */ +#define EXINT_SWTRG_SWT1 EXINT_SWTRG_SWT1_Msk /*!< Software trigger on line 1 */ +#define EXINT_SWTRG_SWT2_Pos (2U) +#define EXINT_SWTRG_SWT2_Msk (0x1U << EXINT_SWTRG_SWT2_Pos) /*!< 0x00000004 */ +#define EXINT_SWTRG_SWT2 EXINT_SWTRG_SWT2_Msk /*!< Software trigger on line 2 */ +#define EXINT_SWTRG_SWT3_Pos (3U) +#define EXINT_SWTRG_SWT3_Msk (0x1U << EXINT_SWTRG_SWT3_Pos) /*!< 0x00000008 */ +#define EXINT_SWTRG_SWT3 EXINT_SWTRG_SWT3_Msk /*!< Software trigger on line 3 */ +#define EXINT_SWTRG_SWT4_Pos (4U) +#define EXINT_SWTRG_SWT4_Msk (0x1U << EXINT_SWTRG_SWT4_Pos) /*!< 0x00000010 */ +#define EXINT_SWTRG_SWT4 EXINT_SWTRG_SWT4_Msk /*!< Software trigger on line 4 */ +#define EXINT_SWTRG_SWT5_Pos (5U) +#define EXINT_SWTRG_SWT5_Msk (0x1U << EXINT_SWTRG_SWT5_Pos) /*!< 0x00000020 */ +#define EXINT_SWTRG_SWT5 EXINT_SWTRG_SWT5_Msk /*!< Software trigger on line 5 */ +#define EXINT_SWTRG_SWT6_Pos (6U) +#define EXINT_SWTRG_SWT6_Msk (0x1U << EXINT_SWTRG_SWT6_Pos) /*!< 0x00000040 */ +#define EXINT_SWTRG_SWT6 EXINT_SWTRG_SWT6_Msk /*!< Software trigger on line 6 */ +#define EXINT_SWTRG_SWT7_Pos (7U) +#define EXINT_SWTRG_SWT7_Msk (0x1U << EXINT_SWTRG_SWT7_Pos) /*!< 0x00000080 */ +#define EXINT_SWTRG_SWT7 EXINT_SWTRG_SWT7_Msk /*!< Software trigger on line 7 */ +#define EXINT_SWTRG_SWT8_Pos (8U) +#define EXINT_SWTRG_SWT8_Msk (0x1U << EXINT_SWTRG_SWT8_Pos) /*!< 0x00000100 */ +#define EXINT_SWTRG_SWT8 EXINT_SWTRG_SWT8_Msk /*!< Software trigger on line 8 */ +#define EXINT_SWTRG_SWT9_Pos (9U) +#define EXINT_SWTRG_SWT9_Msk (0x1U << EXINT_SWTRG_SWT9_Pos) /*!< 0x00000200 */ +#define EXINT_SWTRG_SWT9 EXINT_SWTRG_SWT9_Msk /*!< Software trigger on line 9 */ +#define EXINT_SWTRG_SWT10_Pos (10U) +#define EXINT_SWTRG_SWT10_Msk (0x1U << EXINT_SWTRG_SWT10_Pos) /*!< 0x00000400 */ +#define EXINT_SWTRG_SWT10 EXINT_SWTRG_SWT10_Msk /*!< Software trigger on line 10 */ +#define EXINT_SWTRG_SWT11_Pos (11U) +#define EXINT_SWTRG_SWT11_Msk (0x1U << EXINT_SWTRG_SWT11_Pos) /*!< 0x00000800 */ +#define EXINT_SWTRG_SWT11 EXINT_SWTRG_SWT11_Msk /*!< Software trigger on line 11 */ +#define EXINT_SWTRG_SWT12_Pos (12U) +#define EXINT_SWTRG_SWT12_Msk (0x1U << EXINT_SWTRG_SWT12_Pos) /*!< 0x00001000 */ +#define EXINT_SWTRG_SWT12 EXINT_SWTRG_SWT12_Msk /*!< Software trigger on line 12 */ +#define EXINT_SWTRG_SWT13_Pos (13U) +#define EXINT_SWTRG_SWT13_Msk (0x1U << EXINT_SWTRG_SWT13_Pos) /*!< 0x00002000 */ +#define EXINT_SWTRG_SWT13 EXINT_SWTRG_SWT13_Msk /*!< Software trigger on line 13 */ +#define EXINT_SWTRG_SWT14_Pos (14U) +#define EXINT_SWTRG_SWT14_Msk (0x1U << EXINT_SWTRG_SWT14_Pos) /*!< 0x00004000 */ +#define EXINT_SWTRG_SWT14 EXINT_SWTRG_SWT14_Msk /*!< Software trigger on line 14 */ +#define EXINT_SWTRG_SWT15_Pos (15U) +#define EXINT_SWTRG_SWT15_Msk (0x1U << EXINT_SWTRG_SWT15_Pos) /*!< 0x00008000 */ +#define EXINT_SWTRG_SWT15 EXINT_SWTRG_SWT15_Msk /*!< Software trigger on line 15 */ +#define EXINT_SWTRG_SWT16_Pos (16U) +#define EXINT_SWTRG_SWT16_Msk (0x1U << EXINT_SWTRG_SWT16_Pos) /*!< 0x00010000 */ +#define EXINT_SWTRG_SWT16 EXINT_SWTRG_SWT16_Msk /*!< Software trigger on line 16 */ +#define EXINT_SWTRG_SWT17_Pos (17U) +#define EXINT_SWTRG_SWT17_Msk (0x1U << EXINT_SWTRG_SWT17_Pos) /*!< 0x00020000 */ +#define EXINT_SWTRG_SWT17 EXINT_SWTRG_SWT17_Msk /*!< Software trigger on line 17 */ +#define EXINT_SWTRG_SWT18_Pos (18U) +#define EXINT_SWTRG_SWT18_Msk (0x1U << EXINT_SWTRG_SWT18_Pos) /*!< 0x00040000 */ +#define EXINT_SWTRG_SWT18 EXINT_SWTRG_SWT18_Msk /*!< Software trigger on line 18 */ +#define EXINT_SWTRG_SWT20_Pos (20U) +#define EXINT_SWTRG_SWT20_Msk (0x1U << EXINT_SWTRG_SWT20_Pos) /*!< 0x00100000 */ +#define EXINT_SWTRG_SWT20 EXINT_SWTRG_SWT20_Msk /*!< Software trigger on line 20 (F405 only) */ +#define EXINT_SWTRG_SWT21_Pos (21U) +#define EXINT_SWTRG_SWT21_Msk (0x1U << EXINT_SWTRG_SWT21_Pos) /*!< 0x00200000 */ +#define EXINT_SWTRG_SWT21 EXINT_SWTRG_SWT21_Msk /*!< Software trigger on line 21 */ +#define EXINT_SWTRG_SWT22_Pos (22U) +#define EXINT_SWTRG_SWT22_Msk (0x1U << EXINT_SWTRG_SWT22_Pos) /*!< 0x00400000 */ +#define EXINT_SWTRG_SWT22 EXINT_SWTRG_SWT22_Msk /*!< Software trigger on line 22 */ + +/* References Defines */ +#define EXINT_SWTRG_SW0 EXINT_SWTRG_SWT0 +#define EXINT_SWTRG_SW1 EXINT_SWTRG_SWT1 +#define EXINT_SWTRG_SW2 EXINT_SWTRG_SWT2 +#define EXINT_SWTRG_SW3 EXINT_SWTRG_SWT3 +#define EXINT_SWTRG_SW4 EXINT_SWTRG_SWT4 +#define EXINT_SWTRG_SW5 EXINT_SWTRG_SWT5 +#define EXINT_SWTRG_SW6 EXINT_SWTRG_SWT6 +#define EXINT_SWTRG_SW7 EXINT_SWTRG_SWT7 +#define EXINT_SWTRG_SW8 EXINT_SWTRG_SWT8 +#define EXINT_SWTRG_SW9 EXINT_SWTRG_SWT9 +#define EXINT_SWTRG_SW10 EXINT_SWTRG_SWT10 +#define EXINT_SWTRG_SW11 EXINT_SWTRG_SWT11 +#define EXINT_SWTRG_SW12 EXINT_SWTRG_SWT12 +#define EXINT_SWTRG_SW13 EXINT_SWTRG_SWT13 +#define EXINT_SWTRG_SW14 EXINT_SWTRG_SWT14 +#define EXINT_SWTRG_SW15 EXINT_SWTRG_SWT15 +#define EXINT_SWTRG_SW16 EXINT_SWTRG_SWT16 +#define EXINT_SWTRG_SW17 EXINT_SWTRG_SWT17 +#define EXINT_SWTRG_SW18 EXINT_SWTRG_SWT18 +#define EXINT_SWTRG_SW20 EXINT_SWTRG_SWT20 +#define EXINT_SWTRG_SW21 EXINT_SWTRG_SWT21 +#define EXINT_SWTRG_SW22 EXINT_SWTRG_SWT22 + +/***************** Bit definition for EXINT_INTSTS register *****************/ +#define EXINT_INTSTS_LINE0_Pos (0U) +#define EXINT_INTSTS_LINE0_Msk (0x1U << EXINT_INTSTS_LINE0_Pos) /*!< 0x00000001 */ +#define EXINT_INTSTS_LINE0 EXINT_INTSTS_LINE0_Msk /*!< Status bit for line 0 */ +#define EXINT_INTSTS_LINE1_Pos (1U) +#define EXINT_INTSTS_LINE1_Msk (0x1U << EXINT_INTSTS_LINE1_Pos) /*!< 0x00000002 */ +#define EXINT_INTSTS_LINE1 EXINT_INTSTS_LINE1_Msk /*!< Status bit for line 1 */ +#define EXINT_INTSTS_LINE2_Pos (2U) +#define EXINT_INTSTS_LINE2_Msk (0x1U << EXINT_INTSTS_LINE2_Pos) /*!< 0x00000004 */ +#define EXINT_INTSTS_LINE2 EXINT_INTSTS_LINE2_Msk /*!< Status bit for line 2 */ +#define EXINT_INTSTS_LINE3_Pos (3U) +#define EXINT_INTSTS_LINE3_Msk (0x1U << EXINT_INTSTS_LINE3_Pos) /*!< 0x00000008 */ +#define EXINT_INTSTS_LINE3 EXINT_INTSTS_LINE3_Msk /*!< Status bit for line 3 */ +#define EXINT_INTSTS_LINE4_Pos (4U) +#define EXINT_INTSTS_LINE4_Msk (0x1U << EXINT_INTSTS_LINE4_Pos) /*!< 0x00000010 */ +#define EXINT_INTSTS_LINE4 EXINT_INTSTS_LINE4_Msk /*!< Status bit for line 4 */ +#define EXINT_INTSTS_LINE5_Pos (5U) +#define EXINT_INTSTS_LINE5_Msk (0x1U << EXINT_INTSTS_LINE5_Pos) /*!< 0x00000020 */ +#define EXINT_INTSTS_LINE5 EXINT_INTSTS_LINE5_Msk /*!< Status bit for line 5 */ +#define EXINT_INTSTS_LINE6_Pos (6U) +#define EXINT_INTSTS_LINE6_Msk (0x1U << EXINT_INTSTS_LINE6_Pos) /*!< 0x00000040 */ +#define EXINT_INTSTS_LINE6 EXINT_INTSTS_LINE6_Msk /*!< Status bit for line 6 */ +#define EXINT_INTSTS_LINE7_Pos (7U) +#define EXINT_INTSTS_LINE7_Msk (0x1U << EXINT_INTSTS_LINE7_Pos) /*!< 0x00000080 */ +#define EXINT_INTSTS_LINE7 EXINT_INTSTS_LINE7_Msk /*!< Status bit for line 7 */ +#define EXINT_INTSTS_LINE8_Pos (8U) +#define EXINT_INTSTS_LINE8_Msk (0x1U << EXINT_INTSTS_LINE8_Pos) /*!< 0x00000100 */ +#define EXINT_INTSTS_LINE8 EXINT_INTSTS_LINE8_Msk /*!< Status bit for line 8 */ +#define EXINT_INTSTS_LINE9_Pos (9U) +#define EXINT_INTSTS_LINE9_Msk (0x1U << EXINT_INTSTS_LINE9_Pos) /*!< 0x00000200 */ +#define EXINT_INTSTS_LINE9 EXINT_INTSTS_LINE9_Msk /*!< Status bit for line 9 */ +#define EXINT_INTSTS_LINE10_Pos (10U) +#define EXINT_INTSTS_LINE10_Msk (0x1U << EXINT_INTSTS_LINE10_Pos) /*!< 0x00000400 */ +#define EXINT_INTSTS_LINE10 EXINT_INTSTS_LINE10_Msk /*!< Status bit for line 10 */ +#define EXINT_INTSTS_LINE11_Pos (11U) +#define EXINT_INTSTS_LINE11_Msk (0x1U << EXINT_INTSTS_LINE11_Pos) /*!< 0x00000800 */ +#define EXINT_INTSTS_LINE11 EXINT_INTSTS_LINE11_Msk /*!< Status bit for line 11 */ +#define EXINT_INTSTS_LINE12_Pos (12U) +#define EXINT_INTSTS_LINE12_Msk (0x1U << EXINT_INTSTS_LINE12_Pos) /*!< 0x00001000 */ +#define EXINT_INTSTS_LINE12 EXINT_INTSTS_LINE12_Msk /*!< Status bit for line 12 */ +#define EXINT_INTSTS_LINE13_Pos (13U) +#define EXINT_INTSTS_LINE13_Msk (0x1U << EXINT_INTSTS_LINE13_Pos) /*!< 0x00002000 */ +#define EXINT_INTSTS_LINE13 EXINT_INTSTS_LINE13_Msk /*!< Status bit for line 13 */ +#define EXINT_INTSTS_LINE14_Pos (14U) +#define EXINT_INTSTS_LINE14_Msk (0x1U << EXINT_INTSTS_LINE14_Pos) /*!< 0x00004000 */ +#define EXINT_INTSTS_LINE14 EXINT_INTSTS_LINE14_Msk /*!< Status bit for line 14 */ +#define EXINT_INTSTS_LINE15_Pos (15U) +#define EXINT_INTSTS_LINE15_Msk (0x1U << EXINT_INTSTS_LINE15_Pos) /*!< 0x00008000 */ +#define EXINT_INTSTS_LINE15 EXINT_INTSTS_LINE15_Msk /*!< Status bit for line 15 */ +#define EXINT_INTSTS_LINE16_Pos (16U) +#define EXINT_INTSTS_LINE16_Msk (0x1U << EXINT_INTSTS_LINE16_Pos) /*!< 0x00010000 */ +#define EXINT_INTSTS_LINE16 EXINT_INTSTS_LINE16_Msk /*!< Status bit for line 16 */ +#define EXINT_INTSTS_LINE17_Pos (17U) +#define EXINT_INTSTS_LINE17_Msk (0x1U << EXINT_INTSTS_LINE17_Pos) /*!< 0x00020000 */ +#define EXINT_INTSTS_LINE17 EXINT_INTSTS_LINE17_Msk /*!< Status bit for line 17 */ +#define EXINT_INTSTS_LINE18_Pos (18U) +#define EXINT_INTSTS_LINE18_Msk (0x1U << EXINT_INTSTS_LINE18_Pos) /*!< 0x00040000 */ +#define EXINT_INTSTS_LINE18 EXINT_INTSTS_LINE18_Msk /*!< Status bit for line 18 */ +#define EXINT_INTSTS_LINE20_Pos (20U) +#define EXINT_INTSTS_LINE20_Msk (0x1U << EXINT_INTSTS_LINE20_Pos) /*!< 0x00100000 */ +#define EXINT_INTSTS_LINE20 EXINT_INTSTS_LINE20_Msk /*!< Status bit for line 20 (F405 only) */ +#define EXINT_INTSTS_LINE21_Pos (21U) +#define EXINT_INTSTS_LINE21_Msk (0x1U << EXINT_INTSTS_LINE21_Pos) /*!< 0x00200000 */ +#define EXINT_INTSTS_LINE21 EXINT_INTSTS_LINE21_Msk /*!< Status bit for line 21 */ +#define EXINT_INTSTS_LINE22_Pos (22U) +#define EXINT_INTSTS_LINE22_Msk (0x1U << EXINT_INTSTS_LINE22_Pos) /*!< 0x00400000 */ +#define EXINT_INTSTS_LINE22 EXINT_INTSTS_LINE22_Msk /*!< Status bit for line 22 */ + +/* References Defines */ +#define EXINT_INTSTS_INT0 EXINT_INTSTS_LINE0 +#define EXINT_INTSTS_INT1 EXINT_INTSTS_LINE1 +#define EXINT_INTSTS_INT2 EXINT_INTSTS_LINE2 +#define EXINT_INTSTS_INT3 EXINT_INTSTS_LINE3 +#define EXINT_INTSTS_INT4 EXINT_INTSTS_LINE4 +#define EXINT_INTSTS_INT5 EXINT_INTSTS_LINE5 +#define EXINT_INTSTS_INT6 EXINT_INTSTS_LINE6 +#define EXINT_INTSTS_INT7 EXINT_INTSTS_LINE7 +#define EXINT_INTSTS_INT8 EXINT_INTSTS_LINE8 +#define EXINT_INTSTS_INT9 EXINT_INTSTS_LINE9 +#define EXINT_INTSTS_INT10 EXINT_INTSTS_LINE10 +#define EXINT_INTSTS_INT11 EXINT_INTSTS_LINE11 +#define EXINT_INTSTS_INT12 EXINT_INTSTS_LINE12 +#define EXINT_INTSTS_INT13 EXINT_INTSTS_LINE13 +#define EXINT_INTSTS_INT14 EXINT_INTSTS_LINE14 +#define EXINT_INTSTS_INT15 EXINT_INTSTS_LINE15 +#define EXINT_INTSTS_INT16 EXINT_INTSTS_LINE16 +#define EXINT_INTSTS_INT17 EXINT_INTSTS_LINE17 +#define EXINT_INTSTS_INT18 EXINT_INTSTS_LINE18 +#define EXINT_INTSTS_INT20 EXINT_INTSTS_LINE20 +#define EXINT_INTSTS_INT21 EXINT_INTSTS_LINE21 +#define EXINT_INTSTS_INT22 EXINT_INTSTS_LINE22 + +/******************************************************************************/ +/* */ +/* DMA controller (DMA) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for DMA_STS register ********************/ +#define DMA_STS_GF1_Pos (0U) +#define DMA_STS_GF1_Msk (0x1U << DMA_STS_GF1_Pos) /*!< 0x00000001 */ +#define DMA_STS_GF1 DMA_STS_GF1_Msk /*!< Channel 1 global event flag */ +#define DMA_STS_FDTF1_Pos (1U) +#define DMA_STS_FDTF1_Msk (0x1U << DMA_STS_FDTF1_Pos) /*!< 0x00000002 */ +#define DMA_STS_FDTF1 DMA_STS_FDTF1_Msk /*!< Channel 1 transfer complete event flag */ +#define DMA_STS_HDTF1_Pos (2U) +#define DMA_STS_HDTF1_Msk (0x1U << DMA_STS_HDTF1_Pos) /*!< 0x00000004 */ +#define DMA_STS_HDTF1 DMA_STS_HDTF1_Msk /*!< Channel 1 half transfer event flag */ +#define DMA_STS_DTERRF1_Pos (3U) +#define DMA_STS_DTERRF1_Msk (0x1U << DMA_STS_DTERRF1_Pos) /*!< 0x00000008 */ +#define DMA_STS_DTERRF1 DMA_STS_DTERRF1_Msk /*!< Channel 1 transfer error event flag */ +#define DMA_STS_GF2_Pos (4U) +#define DMA_STS_GF2_Msk (0x1U << DMA_STS_GF2_Pos) /*!< 0x00000010 */ +#define DMA_STS_GF2 DMA_STS_GF2_Msk /*!< Channel 2 global event flag */ +#define DMA_STS_FDTF2_Pos (5U) +#define DMA_STS_FDTF2_Msk (0x1U << DMA_STS_FDTF2_Pos) /*!< 0x00000020 */ +#define DMA_STS_FDTF2 DMA_STS_FDTF2_Msk /*!< Channel 2 transfer complete event flag */ +#define DMA_STS_HDTF2_Pos (6U) +#define DMA_STS_HDTF2_Msk (0x1U << DMA_STS_HDTF2_Pos) /*!< 0x00000040 */ +#define DMA_STS_HDTF2 DMA_STS_HDTF2_Msk /*!< Channel 2 half transfer event flag */ +#define DMA_STS_DTERRF2_Pos (7U) +#define DMA_STS_DTERRF2_Msk (0x1U << DMA_STS_DTERRF2_Pos) /*!< 0x00000080 */ +#define DMA_STS_DTERRF2 DMA_STS_DTERRF2_Msk /*!< Channel 2 transfer error event flag */ +#define DMA_STS_GF3_Pos (8U) +#define DMA_STS_GF3_Msk (0x1U << DMA_STS_GF3_Pos) /*!< 0x00000100 */ +#define DMA_STS_GF3 DMA_STS_GF3_Msk /*!< Channel 3 global event flag */ +#define DMA_STS_FDTF3_Pos (9U) +#define DMA_STS_FDTF3_Msk (0x1U << DMA_STS_FDTF3_Pos) /*!< 0x00000200 */ +#define DMA_STS_FDTF3 DMA_STS_FDTF3_Msk /*!< Channel 3 transfer complete event flag */ +#define DMA_STS_HDTF3_Pos (10U) +#define DMA_STS_HDTF3_Msk (0x1U << DMA_STS_HDTF3_Pos) /*!< 0x00000400 */ +#define DMA_STS_HDTF3 DMA_STS_HDTF3_Msk /*!< Channel 3 half transfer event flag */ +#define DMA_STS_DTERRF3_Pos (11U) +#define DMA_STS_DTERRF3_Msk (0x1U << DMA_STS_DTERRF3_Pos) /*!< 0x00000800 */ +#define DMA_STS_DTERRF3 DMA_STS_DTERRF3_Msk /*!< Channel 3 transfer error event flag */ +#define DMA_STS_GF4_Pos (12U) +#define DMA_STS_GF4_Msk (0x1U << DMA_STS_GF4_Pos) /*!< 0x00001000 */ +#define DMA_STS_GF4 DMA_STS_GF4_Msk /*!< Channel 4 global event flag */ +#define DMA_STS_FDTF4_Pos (13U) +#define DMA_STS_FDTF4_Msk (0x1U << DMA_STS_FDTF4_Pos) /*!< 0x00002000 */ +#define DMA_STS_FDTF4 DMA_STS_FDTF4_Msk /*!< Channel 4 transfer complete event flag */ +#define DMA_STS_HDTF4_Pos (14U) +#define DMA_STS_HDTF4_Msk (0x1U << DMA_STS_HDTF4_Pos) /*!< 0x00004000 */ +#define DMA_STS_HDTF4 DMA_STS_HDTF4_Msk /*!< Channel 4 half transfer event flag */ +#define DMA_STS_DTERRF4_Pos (15U) +#define DMA_STS_DTERRF4_Msk (0x1U << DMA_STS_DTERRF4_Pos) /*!< 0x00008000 */ +#define DMA_STS_DTERRF4 DMA_STS_DTERRF4_Msk /*!< Channel 4 transfer error event flag */ +#define DMA_STS_GF5_Pos (16U) +#define DMA_STS_GF5_Msk (0x1U << DMA_STS_GF5_Pos) /*!< 0x00010000 */ +#define DMA_STS_GF5 DMA_STS_GF5_Msk /*!< Channel 5 global event flag */ +#define DMA_STS_FDTF5_Pos (17U) +#define DMA_STS_FDTF5_Msk (0x1U << DMA_STS_FDTF5_Pos) /*!< 0x00020000 */ +#define DMA_STS_FDTF5 DMA_STS_FDTF5_Msk /*!< Channel 5 transfer complete event flag */ +#define DMA_STS_HDTF5_Pos (18U) +#define DMA_STS_HDTF5_Msk (0x1U << DMA_STS_HDTF5_Pos) /*!< 0x00040000 */ +#define DMA_STS_HDTF5 DMA_STS_HDTF5_Msk /*!< Channel 5 half transfer event flag */ +#define DMA_STS_DTERRF5_Pos (19U) +#define DMA_STS_DTERRF5_Msk (0x1U << DMA_STS_DTERRF5_Pos) /*!< 0x00080000 */ +#define DMA_STS_DTERRF5 DMA_STS_DTERRF5_Msk /*!< Channel 5 transfer error event flag */ +#define DMA_STS_GF6_Pos (20U) +#define DMA_STS_GF6_Msk (0x1U << DMA_STS_GF6_Pos) /*!< 0x00100000 */ +#define DMA_STS_GF6 DMA_STS_GF6_Msk /*!< Channel 6 global event flag */ +#define DMA_STS_FDTF6_Pos (21U) +#define DMA_STS_FDTF6_Msk (0x1U << DMA_STS_FDTF6_Pos) /*!< 0x00200000 */ +#define DMA_STS_FDTF6 DMA_STS_FDTF6_Msk /*!< Channel 6 transfer complete event flag */ +#define DMA_STS_HDTF6_Pos (22U) +#define DMA_STS_HDTF6_Msk (0x1U << DMA_STS_HDTF6_Pos) /*!< 0x00400000 */ +#define DMA_STS_HDTF6 DMA_STS_HDTF6_Msk /*!< Channel 6 half transfer event flag */ +#define DMA_STS_DTERRF6_Pos (23U) +#define DMA_STS_DTERRF6_Msk (0x1U << DMA_STS_DTERRF6_Pos) /*!< 0x00800000 */ +#define DMA_STS_DTERRF6 DMA_STS_DTERRF6_Msk /*!< Channel 6 transfer error event flag */ +#define DMA_STS_GF7_Pos (24U) +#define DMA_STS_GF7_Msk (0x1U << DMA_STS_GF7_Pos) /*!< 0x01000000 */ +#define DMA_STS_GF7 DMA_STS_GF7_Msk /*!< Channel 7 global event flag */ +#define DMA_STS_FDTF7_Pos (25U) +#define DMA_STS_FDTF7_Msk (0x1U << DMA_STS_FDTF7_Pos) /*!< 0x02000000 */ +#define DMA_STS_FDTF7 DMA_STS_FDTF7_Msk /*!< Channel 7 transfer complete event flag */ +#define DMA_STS_HDTF7_Pos (26U) +#define DMA_STS_HDTF7_Msk (0x1U << DMA_STS_HDTF7_Pos) /*!< 0x04000000 */ +#define DMA_STS_HDTF7 DMA_STS_HDTF7_Msk /*!< Channel 7 half transfer event flag */ +#define DMA_STS_DTERRF7_Pos (27U) +#define DMA_STS_DTERRF7_Msk (0x1U << DMA_STS_DTERRF7_Pos) /*!< 0x08000000 */ +#define DMA_STS_DTERRF7 DMA_STS_DTERRF7_Msk /*!< Channel 7 transfer error event flag */ + +/******************* Bit definition for DMA_CLR register ********************/ +#define DMA_CLR_GFC1_Pos (0U) +#define DMA_CLR_GFC1_Msk (0x1U << DMA_CLR_GFC1_Pos) /*!< 0x00000001 */ +#define DMA_CLR_GFC1 DMA_CLR_GFC1_Msk /*!< Channel 1 global interrupt flag clear */ +#define DMA_CLR_FDTFC1_Pos (1U) +#define DMA_CLR_FDTFC1_Msk (0x1U << DMA_CLR_FDTFC1_Pos) /*!< 0x00000002 */ +#define DMA_CLR_FDTFC1 DMA_CLR_FDTFC1_Msk /*!< Channel 1 transfer complete flag clear */ +#define DMA_CLR_HDTFC1_Pos (2U) +#define DMA_CLR_HDTFC1_Msk (0x1U << DMA_CLR_HDTFC1_Pos) /*!< 0x00000004 */ +#define DMA_CLR_HDTFC1 DMA_CLR_HDTFC1_Msk /*!< Channel 1 half transfer flag clear */ +#define DMA_CLR_DTERRFC1_Pos (3U) +#define DMA_CLR_DTERRFC1_Msk (0x1U << DMA_CLR_DTERRFC1_Pos) /*!< 0x00000008 */ +#define DMA_CLR_DTERRFC1 DMA_CLR_DTERRFC1_Msk /*!< Channel 1 data transfer error flag clear */ +#define DMA_CLR_GFC2_Pos (4U) +#define DMA_CLR_GFC2_Msk (0x1U << DMA_CLR_GFC2_Pos) /*!< 0x00000010 */ +#define DMA_CLR_GFC2 DMA_CLR_GFC2_Msk /*!< Channel 2 global interrupt flag clear */ +#define DMA_CLR_FDTFC2_Pos (5U) +#define DMA_CLR_FDTFC2_Msk (0x1U << DMA_CLR_FDTFC2_Pos) /*!< 0x00000020 */ +#define DMA_CLR_FDTFC2 DMA_CLR_FDTFC2_Msk /*!< Channel 2 transfer complete flag clear */ +#define DMA_CLR_HDTFC2_Pos (6U) +#define DMA_CLR_HDTFC2_Msk (0x1U << DMA_CLR_HDTFC2_Pos) /*!< 0x00000040 */ +#define DMA_CLR_HDTFC2 DMA_CLR_HDTFC2_Msk /*!< Channel 2 half transfer flag clear */ +#define DMA_CLR_DTERRFC2_Pos (7U) +#define DMA_CLR_DTERRFC2_Msk (0x1U << DMA_CLR_DTERRFC2_Pos) /*!< 0x00000080 */ +#define DMA_CLR_DTERRFC2 DMA_CLR_DTERRFC2_Msk /*!< Channel 2 data transfer error flag clear */ +#define DMA_CLR_GFC3_Pos (8U) +#define DMA_CLR_GFC3_Msk (0x1U << DMA_CLR_GFC3_Pos) /*!< 0x00000100 */ +#define DMA_CLR_GFC3 DMA_CLR_GFC3_Msk /*!< Channel 3 global interrupt flag clear */ +#define DMA_CLR_FDTFC3_Pos (9U) +#define DMA_CLR_FDTFC3_Msk (0x1U << DMA_CLR_FDTFC3_Pos) /*!< 0x00000200 */ +#define DMA_CLR_FDTFC3 DMA_CLR_FDTFC3_Msk /*!< Channel 3 transfer complete flag clear */ +#define DMA_CLR_HDTFC3_Pos (10U) +#define DMA_CLR_HDTFC3_Msk (0x1U << DMA_CLR_HDTFC3_Pos) /*!< 0x00000400 */ +#define DMA_CLR_HDTFC3 DMA_CLR_HDTFC3_Msk /*!< Channel 3 half transfer flag clear */ +#define DMA_CLR_DTERRFC3_Pos (11U) +#define DMA_CLR_DTERRFC3_Msk (0x1U << DMA_CLR_DTERRFC3_Pos) /*!< 0x00000800 */ +#define DMA_CLR_DTERRFC3 DMA_CLR_DTERRFC3_Msk /*!< Channel 3 data transfer error flag clear */ +#define DMA_CLR_GFC4_Pos (12U) +#define DMA_CLR_GFC4_Msk (0x1U << DMA_CLR_GFC4_Pos) /*!< 0x00001000 */ +#define DMA_CLR_GFC4 DMA_CLR_GFC4_Msk /*!< Channel 4 global interrupt flag clear */ +#define DMA_CLR_FDTFC4_Pos (13U) +#define DMA_CLR_FDTFC4_Msk (0x1U << DMA_CLR_FDTFC4_Pos) /*!< 0x00002000 */ +#define DMA_CLR_FDTFC4 DMA_CLR_FDTFC4_Msk /*!< Channel 4 transfer complete flag clear */ +#define DMA_CLR_HDTFC4_Pos (14U) +#define DMA_CLR_HDTFC4_Msk (0x1U << DMA_CLR_HDTFC4_Pos) /*!< 0x00004000 */ +#define DMA_CLR_HDTFC4 DMA_CLR_HDTFC4_Msk /*!< Channel 4 half transfer flag clear */ +#define DMA_CLR_DTERRFC4_Pos (15U) +#define DMA_CLR_DTERRFC4_Msk (0x1U << DMA_CLR_DTERRFC4_Pos) /*!< 0x00008000 */ +#define DMA_CLR_DTERRFC4 DMA_CLR_DTERRFC4_Msk /*!< Channel 4 data transfer error flag clear */ +#define DMA_CLR_GFC5_Pos (16U) +#define DMA_CLR_GFC5_Msk (0x1U << DMA_CLR_GFC5_Pos) /*!< 0x00010000 */ +#define DMA_CLR_GFC5 DMA_CLR_GFC5_Msk /*!< Channel 5 global interrupt flag clear */ +#define DMA_CLR_FDTFC5_Pos (17U) +#define DMA_CLR_FDTFC5_Msk (0x1U << DMA_CLR_FDTFC5_Pos) /*!< 0x00020000 */ +#define DMA_CLR_FDTFC5 DMA_CLR_FDTFC5_Msk /*!< Channel 5 transfer complete flag clear */ +#define DMA_CLR_HDTFC5_Pos (18U) +#define DMA_CLR_HDTFC5_Msk (0x1U << DMA_CLR_HDTFC5_Pos) /*!< 0x00040000 */ +#define DMA_CLR_HDTFC5 DMA_CLR_HDTFC5_Msk /*!< Channel 5 half transfer flag clear */ +#define DMA_CLR_DTERRFC5_Pos (19U) +#define DMA_CLR_DTERRFC5_Msk (0x1U << DMA_CLR_DTERRFC5_Pos) /*!< 0x00080000 */ +#define DMA_CLR_DTERRFC5 DMA_CLR_DTERRFC5_Msk /*!< Channel 5 data transfer error flag clear */ +#define DMA_CLR_GFC6_Pos (20U) +#define DMA_CLR_GFC6_Msk (0x1U << DMA_CLR_GFC6_Pos) /*!< 0x00100000 */ +#define DMA_CLR_GFC6 DMA_CLR_GFC6_Msk /*!< Channel 6 global interrupt flag clear */ +#define DMA_CLR_FDTFC6_Pos (21U) +#define DMA_CLR_FDTFC6_Msk (0x1U << DMA_CLR_FDTFC6_Pos) /*!< 0x00200000 */ +#define DMA_CLR_FDTFC6 DMA_CLR_FDTFC6_Msk /*!< Channel 6 transfer complete flag clear */ +#define DMA_CLR_HDTFC6_Pos (22U) +#define DMA_CLR_HDTFC6_Msk (0x1U << DMA_CLR_HDTFC6_Pos) /*!< 0x00400000 */ +#define DMA_CLR_HDTFC6 DMA_CLR_HDTFC6_Msk /*!< Channel 6 half transfer flag clear */ +#define DMA_CLR_DTERRFC6_Pos (23U) +#define DMA_CLR_DTERRFC6_Msk (0x1U << DMA_CLR_DTERRFC6_Pos) /*!< 0x00800000 */ +#define DMA_CLR_DTERRFC6 DMA_CLR_DTERRFC6_Msk /*!< Channel 6 data transfer error flag clear */ +#define DMA_CLR_GFC7_Pos (24U) +#define DMA_CLR_GFC7_Msk (0x1U << DMA_CLR_GFC7_Pos) /*!< 0x01000000 */ +#define DMA_CLR_GFC7 DMA_CLR_GFC7_Msk /*!< Channel 7 global interrupt flag clear */ +#define DMA_CLR_FDTFC7_Pos (25U) +#define DMA_CLR_FDTFC7_Msk (0x1U << DMA_CLR_FDTFC7_Pos) /*!< 0x02000000 */ +#define DMA_CLR_FDTFC7 DMA_CLR_FDTFC7_Msk /*!< Channel 7 transfer complete flag clear */ +#define DMA_CLR_HDTFC7_Pos (26U) +#define DMA_CLR_HDTFC7_Msk (0x1U << DMA_CLR_HDTFC7_Pos) /*!< 0x04000000 */ +#define DMA_CLR_HDTFC7 DMA_CLR_HDTFC7_Msk /*!< Channel 7 half transfer flag clear */ +#define DMA_CLR_DTERRFC7_Pos (27U) +#define DMA_CLR_DTERRFC7_Msk (0x1U << DMA_CLR_DTERRFC7_Pos) /*!< 0x08000000 */ +#define DMA_CLR_DTERRFC7 DMA_CLR_DTERRFC7_Msk /*!< Channel 7 data transfer error flag clear */ + +/****************** Bit definition for DMA_CCTRL register *******************/ +#define DMA_CCTRL_CHEN_Pos (0U) +#define DMA_CCTRL_CHEN_Msk (0x1U << DMA_CCTRL_CHEN_Pos) /*!< 0x00000001 */ +#define DMA_CCTRL_CHEN DMA_CCTRL_CHEN_Msk /*!< Channel enable */ +#define DMA_CCTRL_FDTIEN_Pos (1U) +#define DMA_CCTRL_FDTIEN_Msk (0x1U << DMA_CCTRL_FDTIEN_Pos) /*!< 0x00000002 */ +#define DMA_CCTRL_FDTIEN DMA_CCTRL_FDTIEN_Msk /*!< Transfer complete interrupt enable */ +#define DMA_CCTRL_HDTIEN_Pos (2U) +#define DMA_CCTRL_HDTIEN_Msk (0x1U << DMA_CCTRL_HDTIEN_Pos) /*!< 0x00000004 */ +#define DMA_CCTRL_HDTIEN DMA_CCTRL_HDTIEN_Msk /*!< Half-transfer interrupt enable */ +#define DMA_CCTRL_DTERRIEN_Pos (3U) +#define DMA_CCTRL_DTERRIEN_Msk (0x1U << DMA_CCTRL_DTERRIEN_Pos) /*!< 0x00000008 */ +#define DMA_CCTRL_DTERRIEN DMA_CCTRL_DTERRIEN_Msk /*!< Data transfer error interrupt enable */ +#define DMA_CCTRL_DTD_Pos (4U) +#define DMA_CCTRL_DTD_Msk (0x1U << DMA_CCTRL_DTD_Pos) /*!< 0x00000010 */ +#define DMA_CCTRL_DTD DMA_CCTRL_DTD_Msk /*!< Data transfer direction */ +#define DMA_CCTRL_LM_Pos (5U) +#define DMA_CCTRL_LM_Msk (0x1U << DMA_CCTRL_LM_Pos) /*!< 0x00000020 */ +#define DMA_CCTRL_LM DMA_CCTRL_LM_Msk /*!< Circular mode */ +#define DMA_CCTRL_PINCM_Pos (6U) +#define DMA_CCTRL_PINCM_Msk (0x1U << DMA_CCTRL_PINCM_Pos) /*!< 0x00000040 */ +#define DMA_CCTRL_PINCM DMA_CCTRL_PINCM_Msk /*!< Peripheral address increment mode */ +#define DMA_CCTRL_MINCM_Pos (7U) +#define DMA_CCTRL_MINCM_Msk (0x1U << DMA_CCTRL_MINCM_Pos) /*!< 0x00000080 */ +#define DMA_CCTRL_MINCM DMA_CCTRL_MINCM_Msk /*!< Memory address increment mode */ + +/*!< PWIDTH configuration */ +#define DMA_CCTRL_PWIDTH_Pos (8U) +#define DMA_CCTRL_PWIDTH_Msk (0x3U << DMA_CCTRL_PWIDTH_Pos) /*!< 0x00000300 */ +#define DMA_CCTRL_PWIDTH DMA_CCTRL_PWIDTH_Msk /*!< PWIDTH[1:0] bits (Peripheral data bit width) */ +#define DMA_CCTRL_PWIDTH_0 (0x1U << DMA_CCTRL_PWIDTH_Pos) /*!< 0x00000100 */ +#define DMA_CCTRL_PWIDTH_1 (0x2U << DMA_CCTRL_PWIDTH_Pos) /*!< 0x00000200 */ + +/*!< MWIDTH configuration */ +#define DMA_CCTRL_MWIDTH_Pos (10U) +#define DMA_CCTRL_MWIDTH_Msk (0x3U << DMA_CCTRL_MWIDTH_Pos) /*!< 0x00000C00 */ +#define DMA_CCTRL_MWIDTH DMA_CCTRL_MWIDTH_Msk /*!< MWIDTH[1:0] bits (Memory data bit width) */ +#define DMA_CCTRL_MWIDTH_0 (0x1U << DMA_CCTRL_MWIDTH_Pos) /*!< 0x00000400 */ +#define DMA_CCTRL_MWIDTH_1 (0x2U << DMA_CCTRL_MWIDTH_Pos) /*!< 0x00000800 */ + +/*!< CHPL configuration */ +#define DMA_CCTRL_CHPL_Pos (12U) +#define DMA_CCTRL_CHPL_Msk (0x3U << DMA_CCTRL_CHPL_Pos) /*!< 0x00003000 */ +#define DMA_CCTRL_CHPL DMA_CCTRL_CHPL_Msk /*!< CHPL[1:0] bits(Channel priority level) */ +#define DMA_CCTRL_CHPL_0 (0x1U << DMA_CCTRL_CHPL_Pos) /*!< 0x00001000 */ +#define DMA_CCTRL_CHPL_1 (0x2U << DMA_CCTRL_CHPL_Pos) /*!< 0x00002000 */ + +#define DMA_CCTRL_M2M_Pos (14U) +#define DMA_CCTRL_M2M_Msk (0x1U << DMA_CCTRL_M2M_Pos) /*!< 0x00004000 */ +#define DMA_CCTRL_M2M DMA_CCTRL_M2M_Msk /*!< Memory to memory mode */ + +/****************** Bit definition for DMA_CDTCNT register ******************/ +#define DMA_CDTCNT_CNT_Pos (0U) +#define DMA_CDTCNT_CNT_Msk (0xFFFFU << DMA_CDTCNT_CNT_Pos) /*!< 0x0000FFFF */ +#define DMA_CDTCNT_CNT DMA_CDTCNT_CNT_Msk /*!< Number of data to transfer */ + +/****************** Bit definition for DMA_CPADDR register ******************/ +#define DMA_CPADDR_PADDR_Pos (0U) +#define DMA_CPADDR_PADDR_Msk (0xFFFFFFFFU << DMA_CPADDR_PADDR_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CPADDR_PADDR DMA_CPADDR_PADDR_Msk /*!< Peripheral base address */ + +/****************** Bit definition for DMA_CMADDR register ******************/ +#define DMA_CMADDR_MADDR_Pos (0U) +#define DMA_CMADDR_MADDR_Msk (0xFFFFFFFFU << DMA_CMADDR_MADDR_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CMADDR_MADDR DMA_CMADDR_MADDR_Msk /*!< Memory base address */ + +/****************** Bit definition for DMA_MUXSEL register ******************/ +#define DMA_MUXSEL_TBL_SEL_Pos (0U) +#define DMA_MUXSEL_TBL_SEL_Msk (0x1U << DMA_MUXSEL_TBL_SEL_Pos) /*!< 0x00000001 */ +#define DMA_MUXSEL_TBL_SEL DMA_MUXSEL_TBL_SEL_Msk /*!< Multiplexer table select */ + +/***************** Bit definition for DMA_MUXCCTRL register *****************/ +#define DMA_MUXCCTRL_REQSEL_Pos (0U) +#define DMA_MUXCCTRL_REQSEL_Msk (0x7FU << DMA_MUXCCTRL_REQSEL_Pos) /*!< 0x0000007F */ +#define DMA_MUXCCTRL_REQSEL DMA_MUXCCTRL_REQSEL_Msk /*!< DMA request select */ +#define DMA_MUXCCTRL_SYNCOVIEN_Pos (8U) +#define DMA_MUXCCTRL_SYNCOVIEN_Msk (0x1U << DMA_MUXCCTRL_SYNCOVIEN_Pos) /*!< 0x00000100 */ +#define DMA_MUXCCTRL_SYNCOVIEN DMA_MUXCCTRL_SYNCOVIEN_Msk /*!< Synchronization overrun interrupt enable */ +#define DMA_MUXCCTRL_EVTGEN_Pos (9U) +#define DMA_MUXCCTRL_EVTGEN_Msk (0x1U << DMA_MUXCCTRL_EVTGEN_Pos) /*!< 0x00000200 */ +#define DMA_MUXCCTRL_EVTGEN DMA_MUXCCTRL_EVTGEN_Msk /*!< Event generate enable */ +#define DMA_MUXCCTRL_SYNCEN_Pos (16U) +#define DMA_MUXCCTRL_SYNCEN_Msk (0x1U << DMA_MUXCCTRL_SYNCEN_Pos) /*!< 0x00010000 */ +#define DMA_MUXCCTRL_SYNCEN DMA_MUXCCTRL_SYNCEN_Msk /*!< Synchronization enable */ + +/*!< SYNCPOL configuration */ +#define DMA_MUXCCTRL_SYNCPOL_Pos (17U) +#define DMA_MUXCCTRL_SYNCPOL_Msk (0x3U << DMA_MUXCCTRL_SYNCPOL_Pos) /*!< 0x00060000 */ +#define DMA_MUXCCTRL_SYNCPOL DMA_MUXCCTRL_SYNCPOL_Msk /*!< SYNCPOL[1:0] bits (Synchronization polarity) */ +#define DMA_MUXCCTRL_SYNCPOL_0 (0x1U << DMA_MUXCCTRL_SYNCPOL_Pos) /*!< 0x00020000 */ +#define DMA_MUXCCTRL_SYNCPOL_1 (0x2U << DMA_MUXCCTRL_SYNCPOL_Pos) /*!< 0x00040000 */ + +/*!< REQCNT configuration */ +#define DMA_MUXCCTRL_REQCNT_Pos (19U) +#define DMA_MUXCCTRL_REQCNT_Msk (0x1FU << DMA_MUXCCTRL_REQCNT_Pos) /*!< 0x00F80000 */ +#define DMA_MUXCCTRL_REQCNT DMA_MUXCCTRL_REQCNT_Msk /*!< REQCNT[4:0] bits (DMA request count) */ +#define DMA_MUXCCTRL_REQCNT_0 (0x1U << DMA_MUXCCTRL_REQCNT_Pos) /*!< 0x00080000 */ +#define DMA_MUXCCTRL_REQCNT_1 (0x2U << DMA_MUXCCTRL_REQCNT_Pos) /*!< 0x00100000 */ +#define DMA_MUXCCTRL_REQCNT_2 (0x4U << DMA_MUXCCTRL_REQCNT_Pos) /*!< 0x00200000 */ +#define DMA_MUXCCTRL_REQCNT_3 (0x8U << DMA_MUXCCTRL_REQCNT_Pos) /*!< 0x00400000 */ +#define DMA_MUXCCTRL_REQCNT_4 (0x10U << DMA_MUXCCTRL_REQCNT_Pos) /*!< 0x00800000 */ + +/*!< SYNCSEL configuration */ +#define DMA_MUXCCTRL_SYNCSEL_Pos (24U) +#define DMA_MUXCCTRL_SYNCSEL_Msk (0x1FU << DMA_MUXCCTRL_SYNCSEL_Pos) /*!< 0x1F000000 */ +#define DMA_MUXCCTRL_SYNCSEL DMA_MUXCCTRL_SYNCSEL_Msk /*!< SYNCSEL[4:0] bits (Synchronization select) */ +#define DMA_MUXCCTRL_SYNCSEL_0 (0x1U << DMA_MUXCCTRL_SYNCSEL_Pos) /*!< 0x01000000 */ +#define DMA_MUXCCTRL_SYNCSEL_1 (0x2U << DMA_MUXCCTRL_SYNCSEL_Pos) /*!< 0x02000000 */ +#define DMA_MUXCCTRL_SYNCSEL_2 (0x4U << DMA_MUXCCTRL_SYNCSEL_Pos) /*!< 0x04000000 */ +#define DMA_MUXCCTRL_SYNCSEL_3 (0x8U << DMA_MUXCCTRL_SYNCSEL_Pos) /*!< 0x08000000 */ +#define DMA_MUXCCTRL_SYNCSEL_4 (0x10U << DMA_MUXCCTRL_SYNCSEL_Pos) /*!< 0x10000000 */ + +/***************** Bit definition for DMA_MUXGCTRL register *****************/ +#define DMA_MUXGCTRL_SIGSEL_Pos (0U) +#define DMA_MUXGCTRL_SIGSEL_Msk (0x1FU << DMA_MUXGCTRL_SIGSEL_Pos) /*!< 0x0000001F */ +#define DMA_MUXGCTRL_SIGSEL DMA_MUXGCTRL_SIGSEL_Msk /*!< Signal select */ +#define DMA_MUXGCTRL_TRGOVIEN_Pos (8U) +#define DMA_MUXGCTRL_TRGOVIEN_Msk (0x1U << DMA_MUXGCTRL_TRGOVIEN_Pos) /*!< 0x00000100 */ +#define DMA_MUXGCTRL_TRGOVIEN DMA_MUXGCTRL_TRGOVIEN_Msk /*!< Trigger overrun interrupt enable */ +#define DMA_MUXGCTRL_GEN_Pos (16U) +#define DMA_MUXGCTRL_GEN_Msk (0x1U << DMA_MUXGCTRL_GEN_Pos) /*!< 0x00010000 */ +#define DMA_MUXGCTRL_GEN DMA_MUXGCTRL_GEN_Msk /*!< DMA request generation enable */ + +/*!< GPOL configuration */ +#define DMA_MUXGCTRL_GPOL_Pos (17U) +#define DMA_MUXGCTRL_GPOL_Msk (0x3U << DMA_MUXGCTRL_GPOL_Pos) /*!< 0x00060000 */ +#define DMA_MUXGCTRL_GPOL DMA_MUXGCTRL_GPOL_Msk /*!< GPOL[1:0] bits (DMA request generation polarity) */ +#define DMA_MUXGCTRL_GPOL_0 (0x1U << DMA_MUXGCTRL_GPOL_Pos) /*!< 0x00020000 */ +#define DMA_MUXGCTRL_GPOL_1 (0x2U << DMA_MUXGCTRL_GPOL_Pos) /*!< 0x00040000 */ + +/*!< GREQCNT configuration */ +#define DMA_MUXGCTRL_GREQCNT_Pos (19U) +#define DMA_MUXGCTRL_GREQCNT_Msk (0x1FU << DMA_MUXGCTRL_GREQCNT_Pos) /*!< 0x00F80000 */ +#define DMA_MUXGCTRL_GREQCNT DMA_MUXGCTRL_GREQCNT_Msk /*!< GREQCNT[4:0] bits (DMA request generation count) */ +#define DMA_MUXGCTRL_GREQCNT_0 (0x1U << DMA_MUXGCTRL_GREQCNT_Pos) /*!< 0x00080000 */ +#define DMA_MUXGCTRL_GREQCNT_1 (0x2U << DMA_MUXGCTRL_GREQCNT_Pos) /*!< 0x00100000 */ +#define DMA_MUXGCTRL_GREQCNT_2 (0x4U << DMA_MUXGCTRL_GREQCNT_Pos) /*!< 0x00200000 */ +#define DMA_MUXGCTRL_GREQCNT_3 (0x8U << DMA_MUXGCTRL_GREQCNT_Pos) /*!< 0x00400000 */ +#define DMA_MUXGCTRL_GREQCNT_4 (0x10U << DMA_MUXGCTRL_GREQCNT_Pos) /*!< 0x00800000 */ + +/**************** Bit definition for DMA_MUXSYNCSTS register ****************/ +#define DMA_MUXSYNCSTS_SYNCOVF_Pos (0U) +#define DMA_MUXSYNCSTS_SYNCOVF_Msk (0xFFU << DMA_MUXSYNCSTS_SYNCOVF_Pos) /*!< 0x000000FF */ +#define DMA_MUXSYNCSTS_SYNCOVF DMA_MUXSYNCSTS_SYNCOVF_Msk /*!< Synchronization overrun interrupt flag */ + +/**************** Bit definition for DMA_MUXSYNCCLR register ****************/ +#define DMA_MUXSYNCCLR_SYNCOVFC_Pos (0U) +#define DMA_MUXSYNCCLR_SYNCOVFC_Msk (0xFFU << DMA_MUXSYNCCLR_SYNCOVFC_Pos) /*!< 0x000000FF */ +#define DMA_MUXSYNCCLR_SYNCOVFC DMA_MUXSYNCCLR_SYNCOVFC_Msk /*!< Synchronization overrun interrupt flag clear */ + +/***************** Bit definition for DMA_MUXGSTS register ******************/ +#define DMA_MUXGSTS_TRGOVF_Pos (0U) +#define DMA_MUXGSTS_TRGOVF_Msk (0xFU << DMA_MUXGSTS_TRGOVF_Pos) /*!< 0x0000000F */ +#define DMA_MUXGSTS_TRGOVF DMA_MUXGSTS_TRGOVF_Msk /*!< Trigger overrun interrupt flag */ + +/***************** Bit definition for DMA_MUXGCLR register ******************/ +#define DMA_MUXGCLR_TRGOVFC_Pos (0U) +#define DMA_MUXGCLR_TRGOVFC_Msk (0xFU << DMA_MUXGCLR_TRGOVFC_Pos) /*!< 0x0000000F */ +#define DMA_MUXGCLR_TRGOVFC DMA_MUXGCLR_TRGOVFC_Msk /*!< Trigger overrun interrupt flag clear */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit (CRC) */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for CRC_DT register ********************/ +#define CRC_DT_DT_Pos (0U) +#define CRC_DT_DT_Msk (0xFFFFFFFFU << CRC_DT_DT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DT_DT CRC_DT_DT_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_CDT register ********************/ +#define CRC_CDT_CDT_Pos (0U) +#define CRC_CDT_CDT_Msk (0xFFU << CRC_CDT_CDT_Pos) /*!< 0x000000FF */ +#define CRC_CDT_CDT CRC_CDT_CDT_Msk /*!< General-purpose 8-bit data register bits */ + +/******************* Bit definition for CRC_CTRL register *******************/ +#define CRC_CTRL_RST_Pos (0U) +#define CRC_CTRL_RST_Msk (0x1U << CRC_CTRL_RST_Pos) /*!< 0x00000001 */ +#define CRC_CTRL_RST CRC_CTRL_RST_Msk /*!< Reset CRC calculation unit */ + +/*!< POLY_SIZE configuration */ +#define CRC_CTRL_POLY_SIZE_Pos (3U) +#define CRC_CTRL_POLY_SIZE_Msk (0x3U << CRC_CTRL_POLY_SIZE_Pos) /*!< 0x00000018 */ +#define CRC_CTRL_POLY_SIZE CRC_CTRL_POLY_SIZE_Msk /*!< POLY_SIZE[1:0] bits (Polynomial size) */ +#define CRC_CTRL_POLY_SIZE_0 (0x1U << CRC_CTRL_POLY_SIZE_Pos) /*!< 0x00000008 */ +#define CRC_CTRL_POLY_SIZE_1 (0x2U << CRC_CTRL_POLY_SIZE_Pos) /*!< 0x00000010 */ + +#define CRC_CTRL_POLY_SIZE_32BIT 0x00000000U /*!< 32-bit */ +#define CRC_CTRL_POLY_SIZE_16BIT_Pos (3U) +#define CRC_CTRL_POLY_SIZE_16BIT_Msk (0x1U << CRC_CTRL_POLY_SIZE_16BIT_Pos) /*!< 0x00000008 */ +#define CRC_CTRL_POLY_SIZE_16BIT CRC_CTRL_POLY_SIZE_16BIT_Msk /*!< 16-bit */ +#define CRC_CTRL_POLY_SIZE_8BIT_Pos (4U) +#define CRC_CTRL_POLY_SIZE_8BIT_Msk (0x1U << CRC_CTRL_POLY_SIZE_8BIT_Pos) /*!< 0x00000010 */ +#define CRC_CTRL_POLY_SIZE_8BIT CRC_CTRL_POLY_SIZE_8BIT_Msk /*!< 8-bit */ +#define CRC_CTRL_POLY_SIZE_7BIT_Pos (3U) +#define CRC_CTRL_POLY_SIZE_7BIT_Msk (0x3U << CRC_CTRL_POLY_SIZE_7BIT_Pos) /*!< 0x00000018 */ +#define CRC_CTRL_POLY_SIZE_7BIT CRC_CTRL_POLY_SIZE_7BIT_Msk /*!< 7-bit */ + +/*!< REVID configuration */ +#define CRC_CTRL_REVID_Pos (5U) +#define CRC_CTRL_REVID_Msk (0x3U << CRC_CTRL_REVID_Pos) /*!< 0x00000060 */ +#define CRC_CTRL_REVID CRC_CTRL_REVID_Msk /*!< REVID[1:0] bits (Reverse input data) */ +#define CRC_CTRL_REVID_0 (0x1U << CRC_CTRL_REVID_Pos) /*!< 0x00000020 */ +#define CRC_CTRL_REVID_1 (0x2U << CRC_CTRL_REVID_Pos) /*!< 0x00000040 */ + +#define CRC_CTRL_REVID_NOREV 0x00000000U /*!< No effect */ +#define CRC_CTRL_REVID_BYTEREV_Pos (5U) +#define CRC_CTRL_REVID_BYTEREV_Msk (0x1U << CRC_CTRL_REVID_BYTEREV_Pos) /*!< 0x00000020 */ +#define CRC_CTRL_REVID_BYTEREV CRC_CTRL_REVID_BYTEREV_Msk /*!< Byte reverse */ +#define CRC_CTRL_REVID_HALFREV_Pos (6U) +#define CRC_CTRL_REVID_HALFREV_Msk (0x1U << CRC_CTRL_REVID_HALFREV_Pos) /*!< 0x00000040 */ +#define CRC_CTRL_REVID_HALFREV CRC_CTRL_REVID_HALFREV_Msk /*!< Half-word reverse */ +#define CRC_CTRL_REVID_WORDREV_Pos (5U) +#define CRC_CTRL_REVID_WORDREV_Msk (0x3U << CRC_CTRL_REVID_WORDREV_Pos) /*!< 0x00000060 */ +#define CRC_CTRL_REVID_WORDREV CRC_CTRL_REVID_WORDREV_Msk /*!< Word reverse */ + +#define CRC_CTRL_REVOD_Pos (7U) +#define CRC_CTRL_REVOD_Msk (0x1U << CRC_CTRL_REVOD_Pos) /*!< 0x00000080 */ +#define CRC_CTRL_REVOD CRC_CTRL_REVOD_Msk /*!< Reverse output data */ + +/******************* Bit definition for CRC_IDT register ********************/ +#define CRC_IDT_IDT_Pos (0U) +#define CRC_IDT_IDT_Msk (0xFFFFFFFFU << CRC_IDT_IDT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDT_IDT CRC_IDT_IDT_Msk /*!< Initialization data register */ + +/******************* Bit definition for CRC_POLY register *******************/ +#define CRC_POLY_POLY_Pos (0U) +#define CRC_POLY_POLY_Msk (0xFFFFFFFFU << CRC_POLY_POLY_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POLY_POLY CRC_POLY_POLY_Msk /*!< Polynomial coefficient */ + +/******************************************************************************/ +/* */ +/* Inter-integrated circuit interface (I2C) */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for I2C_CTRL1 register *******************/ +#define I2C_CTRL1_I2CEN_Pos (0U) +#define I2C_CTRL1_I2CEN_Msk (0x1U << I2C_CTRL1_I2CEN_Pos) /*!< 0x00000001 */ +#define I2C_CTRL1_I2CEN I2C_CTRL1_I2CEN_Msk /*!< I2C peripheral enable */ +#define I2C_CTRL1_TDIEN_Pos (1U) +#define I2C_CTRL1_TDIEN_Msk (0x1U << I2C_CTRL1_TDIEN_Pos) /*!< 0x00000002 */ +#define I2C_CTRL1_TDIEN I2C_CTRL1_TDIEN_Msk /*!< Data transmit data interrupt enable */ +#define I2C_CTRL1_RDIEN_Pos (2U) +#define I2C_CTRL1_RDIEN_Msk (0x1U << I2C_CTRL1_RDIEN_Pos) /*!< 0x00000004 */ +#define I2C_CTRL1_RDIEN I2C_CTRL1_RDIEN_Msk /*!< Data receive interrupt enable */ +#define I2C_CTRL1_ADDRIEN_Pos (3U) +#define I2C_CTRL1_ADDRIEN_Msk (0x1U << I2C_CTRL1_ADDRIEN_Pos) /*!< 0x00000008 */ +#define I2C_CTRL1_ADDRIEN I2C_CTRL1_ADDRIEN_Msk /*!< Address match interrupt enable */ +#define I2C_CTRL1_ACKFAILIEN_Pos (4U) +#define I2C_CTRL1_ACKFAILIEN_Msk (0x1U << I2C_CTRL1_ACKFAILIEN_Pos) /*!< 0x00000010 */ +#define I2C_CTRL1_ACKFAILIEN I2C_CTRL1_ACKFAILIEN_Msk /*!< Acknowledge fail interrupt enable */ +#define I2C_CTRL1_STOPIEN_Pos (5U) +#define I2C_CTRL1_STOPIEN_Msk (0x1U << I2C_CTRL1_STOPIEN_Pos) /*!< 0x00000020 */ +#define I2C_CTRL1_STOPIEN I2C_CTRL1_STOPIEN_Msk /*!< Stop generation complete interrupt enable */ +#define I2C_CTRL1_TDCIEN_Pos (6U) +#define I2C_CTRL1_TDCIEN_Msk (0x1U << I2C_CTRL1_TDCIEN_Pos) /*!< 0x00000040 */ +#define I2C_CTRL1_TDCIEN I2C_CTRL1_TDCIEN_Msk /*!< Data transfer complete interrupt enable */ +#define I2C_CTRL1_ERRIEN_Pos (7U) +#define I2C_CTRL1_ERRIEN_Msk (0x1U << I2C_CTRL1_ERRIEN_Pos) /*!< 0x00000080 */ +#define I2C_CTRL1_ERRIEN I2C_CTRL1_ERRIEN_Msk /*!< Error interrupt enable */ +#define I2C_CTRL1_DFLT_Pos (8U) +#define I2C_CTRL1_DFLT_Msk (0xFU << I2C_CTRL1_DFLT_Pos) /*!< 0x00000F00 */ +#define I2C_CTRL1_DFLT I2C_CTRL1_DFLT_Msk /*!< Digital filter value */ +#define I2C_CTRL1_DMATEN_Pos (14U) +#define I2C_CTRL1_DMATEN_Msk (0x1U << I2C_CTRL1_DMATEN_Pos) /*!< 0x00004000 */ +#define I2C_CTRL1_DMATEN I2C_CTRL1_DMATEN_Msk /*!< DMA transmit data request enable */ +#define I2C_CTRL1_DMAREN_Pos (15U) +#define I2C_CTRL1_DMAREN_Msk (0x1U << I2C_CTRL1_DMAREN_Pos) /*!< 0x00008000 */ +#define I2C_CTRL1_DMAREN I2C_CTRL1_DMAREN_Msk /*!< DMA receive data request enable */ +#define I2C_CTRL1_SCTRL_Pos (16U) +#define I2C_CTRL1_SCTRL_Msk (0x1U << I2C_CTRL1_SCTRL_Pos) /*!< 0x00010000 */ +#define I2C_CTRL1_SCTRL I2C_CTRL1_SCTRL_Msk /*!< Slave receiving data control */ +#define I2C_CTRL1_STRETCH_Pos (17U) +#define I2C_CTRL1_STRETCH_Msk (0x1U << I2C_CTRL1_STRETCH_Pos) /*!< 0x00020000 */ +#define I2C_CTRL1_STRETCH I2C_CTRL1_STRETCH_Msk /*!< Clock stretching mode */ +#define I2C_CTRL1_GCAEN_Pos (19U) +#define I2C_CTRL1_GCAEN_Msk (0x1U << I2C_CTRL1_GCAEN_Pos) /*!< 0x00080000 */ +#define I2C_CTRL1_GCAEN I2C_CTRL1_GCAEN_Msk /*!< General call address enable */ +#define I2C_CTRL1_HADDREN_Pos (20U) +#define I2C_CTRL1_HADDREN_Msk (0x1U << I2C_CTRL1_HADDREN_Pos) /*!< 0x00100000 */ +#define I2C_CTRL1_HADDREN I2C_CTRL1_HADDREN_Msk /*!< SMBus host address enable */ +#define I2C_CTRL1_DEVADDREN_Pos (21U) +#define I2C_CTRL1_DEVADDREN_Msk (0x1U << I2C_CTRL1_DEVADDREN_Pos) /*!< 0x00200000 */ +#define I2C_CTRL1_DEVADDREN I2C_CTRL1_DEVADDREN_Msk /*!< SMBus device default address enable */ +#define I2C_CTRL1_SMBALERT_Pos (22U) +#define I2C_CTRL1_SMBALERT_Msk (0x1U << I2C_CTRL1_SMBALERT_Pos) /*!< 0x00400000 */ +#define I2C_CTRL1_SMBALERT I2C_CTRL1_SMBALERT_Msk /*!< SMBus alert enable / pin set */ +#define I2C_CTRL1_PECEN_Pos (23U) +#define I2C_CTRL1_PECEN_Msk (0x1U << I2C_CTRL1_PECEN_Pos) /*!< 0x00800000 */ +#define I2C_CTRL1_PECEN I2C_CTRL1_PECEN_Msk /*!< PEC calculation enable */ + +/****************** Bit definition for I2C_CTRL2 register *******************/ +/*!< SADDR configuration */ +#define I2C_CTRL2_SADDR_Pos (0U) +#define I2C_CTRL2_SADDR_Msk (0x3FFU << I2C_CTRL2_SADDR_Pos) /*!< 0x000003FF */ +#define I2C_CTRL2_SADDR I2C_CTRL2_SADDR_Msk /*!< SADDR[9:0] bits (Slave address sent by the master) */ +#define I2C_CTRL2_SADDR_0 (0x001U << I2C_CTRL2_SADDR_Pos) /*!< 0x00000001 */ +#define I2C_CTRL2_SADDR_1 (0x002U << I2C_CTRL2_SADDR_Pos) /*!< 0x00000002 */ +#define I2C_CTRL2_SADDR_2 (0x004U << I2C_CTRL2_SADDR_Pos) /*!< 0x00000004 */ +#define I2C_CTRL2_SADDR_3 (0x008U << I2C_CTRL2_SADDR_Pos) /*!< 0x00000008 */ +#define I2C_CTRL2_SADDR_4 (0x010U << I2C_CTRL2_SADDR_Pos) /*!< 0x00000010 */ +#define I2C_CTRL2_SADDR_5 (0x020U << I2C_CTRL2_SADDR_Pos) /*!< 0x00000020 */ +#define I2C_CTRL2_SADDR_6 (0x040U << I2C_CTRL2_SADDR_Pos) /*!< 0x00000040 */ +#define I2C_CTRL2_SADDR_7 (0x080U << I2C_CTRL2_SADDR_Pos) /*!< 0x00000080 */ +#define I2C_CTRL2_SADDR_8 (0x100U << I2C_CTRL2_SADDR_Pos) /*!< 0x00000100 */ +#define I2C_CTRL2_SADDR_9 (0x200U << I2C_CTRL2_SADDR_Pos) /*!< 0x00000200 */ + +#define I2C_CTRL2_DIR_Pos (10U) +#define I2C_CTRL2_DIR_Msk (0x1U << I2C_CTRL2_DIR_Pos) /*!< 0x00000400 */ +#define I2C_CTRL2_DIR I2C_CTRL2_DIR_Msk /*!< Master data transmission direction */ +#define I2C_CTRL2_ADDR10_Pos (11U) +#define I2C_CTRL2_ADDR10_Msk (0x1U << I2C_CTRL2_ADDR10_Pos) /*!< 0x00000800 */ +#define I2C_CTRL2_ADDR10 I2C_CTRL2_ADDR10_Msk /*!< Host sends 10-bit address mode enable */ +#define I2C_CTRL2_READH10_Pos (12U) +#define I2C_CTRL2_READH10_Msk (0x1U << I2C_CTRL2_READH10_Pos) /*!< 0x00001000 */ +#define I2C_CTRL2_READH10 I2C_CTRL2_READH10_Msk /*!< 10-bit address header read enable */ +#define I2C_CTRL2_GENSTART_Pos (13U) +#define I2C_CTRL2_GENSTART_Msk (0x1U << I2C_CTRL2_GENSTART_Pos) /*!< 0x00002000 */ +#define I2C_CTRL2_GENSTART I2C_CTRL2_GENSTART_Msk /*!< Generate start condition */ +#define I2C_CTRL2_GENSTOP_Pos (14U) +#define I2C_CTRL2_GENSTOP_Msk (0x1U << I2C_CTRL2_GENSTOP_Pos) /*!< 0x00004000 */ +#define I2C_CTRL2_GENSTOP I2C_CTRL2_GENSTOP_Msk /*!< Generate stop condition */ +#define I2C_CTRL2_NACKEN_Pos (15U) +#define I2C_CTRL2_NACKEN_Msk (0x1U << I2C_CTRL2_NACKEN_Pos) /*!< 0x00008000 */ +#define I2C_CTRL2_NACKEN I2C_CTRL2_NACKEN_Msk /*!< Not acknowledge enable */ + +/*!< CNT configuration */ +#define I2C_CTRL2_CNT_Pos (16U) +#define I2C_CTRL2_CNT_Msk (0xFFU << I2C_CTRL2_CNT_Pos) /*!< 0x00FF0000 */ +#define I2C_CTRL2_CNT I2C_CTRL2_CNT_Msk /*!< CNT[7:0] bits (CNT) */ +#define I2C_CTRL2_CNT_0 (0x01U << I2C_CTRL2_CNT_Pos) /*!< 0x00010000 */ +#define I2C_CTRL2_CNT_1 (0x02U << I2C_CTRL2_CNT_Pos) /*!< 0x00020000 */ +#define I2C_CTRL2_CNT_2 (0x04U << I2C_CTRL2_CNT_Pos) /*!< 0x00040000 */ +#define I2C_CTRL2_CNT_3 (0x08U << I2C_CTRL2_CNT_Pos) /*!< 0x00080000 */ +#define I2C_CTRL2_CNT_4 (0x10U << I2C_CTRL2_CNT_Pos) /*!< 0x00100000 */ +#define I2C_CTRL2_CNT_5 (0x20U << I2C_CTRL2_CNT_Pos) /*!< 0x00200000 */ +#define I2C_CTRL2_CNT_6 (0x40U << I2C_CTRL2_CNT_Pos) /*!< 0x00400000 */ +#define I2C_CTRL2_CNT_7 (0x80U << I2C_CTRL2_CNT_Pos) /*!< 0x00800000 */ + +#define I2C_CTRL2_RLDEN_Pos (24U) +#define I2C_CTRL2_RLDEN_Msk (0x1U << I2C_CTRL2_RLDEN_Pos) /*!< 0x01000000 */ +#define I2C_CTRL2_RLDEN I2C_CTRL2_RLDEN_Msk /*!< Send data reload mode enable */ +#define I2C_CTRL2_ASTOPEN_Pos (25U) +#define I2C_CTRL2_ASTOPEN_Msk (0x1U << I2C_CTRL2_ASTOPEN_Pos) /*!< 0x02000000 */ +#define I2C_CTRL2_ASTOPEN I2C_CTRL2_ASTOPEN_Msk /*!< Automatically send stop condition enable */ +#define I2C_CTRL2_PECTEN_Pos (26U) +#define I2C_CTRL2_PECTEN_Msk (0x1U << I2C_CTRL2_PECTEN_Pos) /*!< 0x04000000 */ +#define I2C_CTRL2_PECTEN I2C_CTRL2_PECTEN_Msk /*!< Request PEC transmission enable */ + +/****************** Bit definition for I2C_OADDR1 register ******************/ +/*!< ADDR1 configuration */ +#define I2C_OADDR1_ADDR1_1_7 0x000000FEU /*!< Interface Address */ +#define I2C_OADDR1_ADDR1_8_9 0x00000300U /*!< Interface Address */ + +#define I2C_OADDR1_ADDR1_0_Pos (0U) +#define I2C_OADDR1_ADDR1_0_Msk (0x1U << I2C_OADDR1_ADDR1_0_Pos) /*!< 0x00000001 */ +#define I2C_OADDR1_ADDR1_0 I2C_OADDR1_ADDR1_0_Msk /*!< Bit 0 */ +#define I2C_OADDR1_ADDR1_1_Pos (1U) +#define I2C_OADDR1_ADDR1_1_Msk (0x1U << I2C_OADDR1_ADDR1_1_Pos) /*!< 0x00000002 */ +#define I2C_OADDR1_ADDR1_1 I2C_OADDR1_ADDR1_1_Msk /*!< Bit 1 */ +#define I2C_OADDR1_ADDR1_2_Pos (2U) +#define I2C_OADDR1_ADDR1_2_Msk (0x1U << I2C_OADDR1_ADDR1_2_Pos) /*!< 0x00000004 */ +#define I2C_OADDR1_ADDR1_2 I2C_OADDR1_ADDR1_2_Msk /*!< Bit 2 */ +#define I2C_OADDR1_ADDR1_3_Pos (3U) +#define I2C_OADDR1_ADDR1_3_Msk (0x1U << I2C_OADDR1_ADDR1_3_Pos) /*!< 0x00000008 */ +#define I2C_OADDR1_ADDR1_3 I2C_OADDR1_ADDR1_3_Msk /*!< Bit 3 */ +#define I2C_OADDR1_ADDR1_4_Pos (4U) +#define I2C_OADDR1_ADDR1_4_Msk (0x1U << I2C_OADDR1_ADDR1_4_Pos) /*!< 0x00000010 */ +#define I2C_OADDR1_ADDR1_4 I2C_OADDR1_ADDR1_4_Msk /*!< Bit 4 */ +#define I2C_OADDR1_ADDR1_5_Pos (5U) +#define I2C_OADDR1_ADDR1_5_Msk (0x1U << I2C_OADDR1_ADDR1_5_Pos) /*!< 0x00000020 */ +#define I2C_OADDR1_ADDR1_5 I2C_OADDR1_ADDR1_5_Msk /*!< Bit 5 */ +#define I2C_OADDR1_ADDR1_6_Pos (6U) +#define I2C_OADDR1_ADDR1_6_Msk (0x1U << I2C_OADDR1_ADDR1_6_Pos) /*!< 0x00000040 */ +#define I2C_OADDR1_ADDR1_6 I2C_OADDR1_ADDR1_6_Msk /*!< Bit 6 */ +#define I2C_OADDR1_ADDR1_7_Pos (7U) +#define I2C_OADDR1_ADDR1_7_Msk (0x1U << I2C_OADDR1_ADDR1_7_Pos) /*!< 0x00000080 */ +#define I2C_OADDR1_ADDR1_7 I2C_OADDR1_ADDR1_7_Msk /*!< Bit 7 */ +#define I2C_OADDR1_ADDR1_8_Pos (8U) +#define I2C_OADDR1_ADDR1_8_Msk (0x1U << I2C_OADDR1_ADDR1_8_Pos) /*!< 0x00000100 */ +#define I2C_OADDR1_ADDR1_8 I2C_OADDR1_ADDR1_8_Msk /*!< Bit 8 */ +#define I2C_OADDR1_ADDR1_9_Pos (9U) +#define I2C_OADDR1_ADDR1_9_Msk (0x1U << I2C_OADDR1_ADDR1_9_Pos) /*!< 0x00000200 */ +#define I2C_OADDR1_ADDR1_9 I2C_OADDR1_ADDR1_9_Msk /*!< Bit 9 */ + +#define I2C_OADDR1_ADDR1MODE_Pos (10U) +#define I2C_OADDR1_ADDR1MODE_Msk (0x1U << I2C_OADDR1_ADDR1MODE_Pos) /*!< 0x00000400 */ +#define I2C_OADDR1_ADDR1MODE I2C_OADDR1_ADDR1MODE_Msk /*!< Own Address 1 mode */ +#define I2C_OADDR1_ADDR1EN_Pos (15U) +#define I2C_OADDR1_ADDR1EN_Msk (0x1U << I2C_OADDR1_ADDR1EN_Pos) /*!< 0x00008000 */ +#define I2C_OADDR1_ADDR1EN I2C_OADDR1_ADDR1EN_Msk /*!< Own Address 1 enable */ + +/****************** Bit definition for I2C_OADDR2 register ******************/ +#define I2C_OADDR2_ADDR2_Pos (1U) +#define I2C_OADDR2_ADDR2_Msk (0x7FU << I2C_OADDR2_ADDR2_Pos) /*!< 0x000000FE */ +#define I2C_OADDR2_ADDR2 I2C_OADDR2_ADDR2_Msk /*!< Own address 2 */ + +/*!< ADDR2MASK configuration */ +#define I2C_OADDR2_ADDR2MASK_Pos (8U) +#define I2C_OADDR2_ADDR2MASK_Msk (0x7U << I2C_OADDR2_ADDR2MASK_Pos) /*!< 0x00000700 */ +#define I2C_OADDR2_ADDR2MASK I2C_OADDR2_ADDR2MASK_Msk /*!< CNT[2:0] bits (Own address 2 bit mask) */ +#define I2C_OADDR2_ADDR2MASK_0 (0x01U << I2C_OADDR2_ADDR2MASK_Pos) /*!< 0x00000100 */ +#define I2C_OADDR2_ADDR2MASK_1 (0x02U << I2C_OADDR2_ADDR2MASK_Pos) /*!< 0x00000200 */ +#define I2C_OADDR2_ADDR2MASK_2 (0x04U << I2C_OADDR2_ADDR2MASK_Pos) /*!< 0x00000400 */ + +#define I2C_OADDR2_ADDR2EN_Pos (15U) +#define I2C_OADDR2_ADDR2EN_Msk (0x1U << I2C_OADDR2_ADDR2EN_Pos) /*!< 0x00008000 */ +#define I2C_OADDR2_ADDR2EN I2C_OADDR2_ADDR2EN_Msk /*!< Own Address 2 enable */ + +/***************** Bit definition for I2C_CLKCTRL register ******************/ +#define I2C_CLKCTRL_SCLL_Pos (0U) +#define I2C_CLKCTRL_SCLL_Msk (0xFFU << I2C_CLKCTRL_SCLL_Pos) /*!< 0x000000FF */ +#define I2C_CLKCTRL_SCLL I2C_CLKCTRL_SCLL_Msk /*!< SCL low level */ +#define I2C_CLKCTRL_SCLH_Pos (8U) +#define I2C_CLKCTRL_SCLH_Msk (0xFFU << I2C_CLKCTRL_SCLH_Pos) /*!< 0x0000FF00 */ +#define I2C_CLKCTRL_SCLH I2C_CLKCTRL_SCLH_Msk /*!< SCL high level */ +#define I2C_CLKCTRL_SDAD_Pos (16U) +#define I2C_CLKCTRL_SDAD_Msk (0xFU << I2C_CLKCTRL_SDAD_Pos) /*!< 0x000F0000 */ +#define I2C_CLKCTRL_SDAD I2C_CLKCTRL_SDAD_Msk /*!< SDA output delay */ +#define I2C_CLKCTRL_SCLD_Pos (20U) +#define I2C_CLKCTRL_SCLD_Msk (0xFU << I2C_CLKCTRL_SCLD_Pos) /*!< 0x00F00000 */ +#define I2C_CLKCTRL_SCLD I2C_CLKCTRL_SCLD_Msk /*!< SCL output delay */ +#define I2C_CLKCTRL_DIVH_Pos (24U) +#define I2C_CLKCTRL_DIVH_Msk (0xFU << I2C_CLKCTRL_DIVH_Pos) /*!< 0x0F000000 */ +#define I2C_CLKCTRL_DIVH I2C_CLKCTRL_DIVH_Msk /*!< High 4 bits of clock divider value */ +#define I2C_CLKCTRL_DIVL_Pos (28U) +#define I2C_CLKCTRL_DIVL_Msk (0xFU << I2C_CLKCTRL_DIVL_Pos) /*!< 0xF0000000 */ +#define I2C_CLKCTRL_DIVL I2C_CLKCTRL_DIVL_Msk /*!< Low 4 bits of clock divider value */ + +/***************** Bit definition for I2C_TIMEOUT register ******************/ +#define I2C_TIMEOUT_TOTIME_Pos (0U) +#define I2C_TIMEOUT_TOTIME_Msk (0xFFFU << I2C_TIMEOUT_TOTIME_Pos) /*!< 0x00000FFF */ +#define I2C_TIMEOUT_TOTIME I2C_TIMEOUT_TOTIME_Msk /*!< Clock timeout detection time */ +#define I2C_TIMEOUT_TOMODE_Pos (12U) +#define I2C_TIMEOUT_TOMODE_Msk (0x1U << I2C_TIMEOUT_TOMODE_Pos) /*!< 0x00001000 */ +#define I2C_TIMEOUT_TOMODE I2C_TIMEOUT_TOMODE_Msk /*!< Clock timeout detection mode */ +#define I2C_TIMEOUT_TOEN_Pos (15U) +#define I2C_TIMEOUT_TOEN_Msk (0x1U << I2C_TIMEOUT_TOEN_Pos) /*!< 0x00008000 */ +#define I2C_TIMEOUT_TOEN I2C_TIMEOUT_TOEN_Msk /*!< Detect clock low/high timeout enable */ +#define I2C_TIMEOUT_EXTTIME_Pos (16U) +#define I2C_TIMEOUT_EXTTIME_Msk (0xFFFU << I2C_TIMEOUT_EXTTIME_Pos) /*!< 0x0FFF0000 */ +#define I2C_TIMEOUT_EXTTIME I2C_TIMEOUT_EXTTIME_Msk /*!< Cumulative clock low extend timeout value */ +#define I2C_TIMEOUT_EXTEN_Pos (31U) +#define I2C_TIMEOUT_EXTEN_Msk (0x1U << I2C_TIMEOUT_EXTEN_Pos) /*!< 0x80000000 */ +#define I2C_TIMEOUT_EXTEN I2C_TIMEOUT_EXTEN_Msk /*!< Cumulative clock low extend timeout enable */ + +/******************* Bit definition for I2C_STS register ********************/ +#define I2C_STS_TDBE_Pos (0U) +#define I2C_STS_TDBE_Msk (0x1U << I2C_STS_TDBE_Pos) /*!< 0x00000001 */ +#define I2C_STS_TDBE I2C_STS_TDBE_Msk /*!< Transmit data buffer empty flag */ +#define I2C_STS_TDIS_Pos (1U) +#define I2C_STS_TDIS_Msk (0x1U << I2C_STS_TDIS_Pos) /*!< 0x00000002 */ +#define I2C_STS_TDIS I2C_STS_TDIS_Msk /*!< Transmit data interrupt status */ +#define I2C_STS_RDBF_Pos (2U) +#define I2C_STS_RDBF_Msk (0x1U << I2C_STS_RDBF_Pos) /*!< 0x00000004 */ +#define I2C_STS_RDBF I2C_STS_RDBF_Msk /*!< Receive data buffer full flag */ +#define I2C_STS_ADDRF_Pos (3U) +#define I2C_STS_ADDRF_Msk (0x1U << I2C_STS_ADDRF_Pos) /*!< 0x00000008 */ +#define I2C_STS_ADDRF I2C_STS_ADDRF_Msk /*!< 0 ~ 7 bit address match flag */ +#define I2C_STS_ACKFAILF_Pos (4U) +#define I2C_STS_ACKFAILF_Msk (0x1U << I2C_STS_ACKFAILF_Pos) /*!< 0x00000010 */ +#define I2C_STS_ACKFAILF I2C_STS_ACKFAILF_Msk /*!< Acknowledge failure flag */ +#define I2C_STS_STOPF_Pos (5U) +#define I2C_STS_STOPF_Msk (0x1U << I2C_STS_STOPF_Pos) /*!< 0x00000020 */ +#define I2C_STS_STOPF I2C_STS_STOPF_Msk /*!< Stop condition generation complete flag */ +#define I2C_STS_TDC_Pos (6U) +#define I2C_STS_TDC_Msk (0x1U << I2C_STS_TDC_Pos) /*!< 0x00000040 */ +#define I2C_STS_TDC I2C_STS_TDC_Msk /*!< Data transfer complete flag */ +#define I2C_STS_TCRLD_Pos (7U) +#define I2C_STS_TCRLD_Msk (0x1U << I2C_STS_TCRLD_Pos) /*!< 0x00000080 */ +#define I2C_STS_TCRLD I2C_STS_TCRLD_Msk /*!< Transmission is complete, waiting to load data */ +#define I2C_STS_BUSERR_Pos (8U) +#define I2C_STS_BUSERR_Msk (0x1U << I2C_STS_BUSERR_Pos) /*!< 0x00000100 */ +#define I2C_STS_BUSERR I2C_STS_BUSERR_Msk /*!< Bus error flag */ +#define I2C_STS_ARLOST_Pos (9U) +#define I2C_STS_ARLOST_Msk (0x1U << I2C_STS_ARLOST_Pos) /*!< 0x00000200 */ +#define I2C_STS_ARLOST I2C_STS_ARLOST_Msk /*!< Arbitration lost flag */ +#define I2C_STS_OUF_Pos (10U) +#define I2C_STS_OUF_Msk (0x1U << I2C_STS_OUF_Pos) /*!< 0x00000400 */ +#define I2C_STS_OUF I2C_STS_OUF_Msk /*!< Overflow or underflow flag */ +#define I2C_STS_PECERR_Pos (11U) +#define I2C_STS_PECERR_Msk (0x1U << I2C_STS_PECERR_Pos) /*!< 0x00000800 */ +#define I2C_STS_PECERR I2C_STS_PECERR_Msk /*!< PEC receive error flag */ +#define I2C_STS_TMOUT_Pos (12U) +#define I2C_STS_TMOUT_Msk (0x1U << I2C_STS_TMOUT_Pos) /*!< 0x00001000 */ +#define I2C_STS_TMOUT I2C_STS_TMOUT_Msk /*!< SMBus timeout flag */ +#define I2C_STS_ALERTF_Pos (13U) +#define I2C_STS_ALERTF_Msk (0x1U << I2C_STS_ALERTF_Pos) /*!< 0x00002000 */ +#define I2C_STS_ALERTF I2C_STS_ALERTF_Msk /*!< SMBus alert flag */ +#define I2C_STS_BUSYF_Pos (15U) +#define I2C_STS_BUSYF_Msk (0x1U << I2C_STS_BUSYF_Pos) /*!< 0x00008000 */ +#define I2C_STS_BUSYF I2C_STS_BUSYF_Msk /*!< Bus busy flag transmission mode */ +#define I2C_STS_SDIR_Pos (16U) +#define I2C_STS_SDIR_Msk (0x1U << I2C_STS_SDIR_Pos) /*!< 0x00010000 */ +#define I2C_STS_SDIR I2C_STS_SDIR_Msk /*!< Slave data transmit direction */ +#define I2C_STS_ADDR_Pos (17U) +#define I2C_STS_ADDR_Msk (0x7FU << I2C_STS_ADDR_Pos) /*!< 0x00FE0000 */ +#define I2C_STS_ADDR I2C_STS_ADDR_Msk /*!< Slave address matching value */ + +/******************* Bit definition for I2C_CLR register ********************/ +#define I2C_CLR_ADDRC_Pos (3U) +#define I2C_CLR_ADDRC_Msk (0x1U << I2C_CLR_ADDRC_Pos) /*!< 0x00000008 */ +#define I2C_CLR_ADDRC I2C_CLR_ADDRC_Msk /*!< Clear 0 ~ 7 bit address match flag */ +#define I2C_CLR_ACKFAILC_Pos (4U) +#define I2C_CLR_ACKFAILC_Msk (0x1U << I2C_CLR_ACKFAILC_Pos) /*!< 0x00000010 */ +#define I2C_CLR_ACKFAILC I2C_CLR_ACKFAILC_Msk /*!< Clear acknowledge failure flag */ +#define I2C_CLR_STOPC_Pos (5U) +#define I2C_CLR_STOPC_Msk (0x1U << I2C_CLR_STOPC_Pos) /*!< 0x00000020 */ +#define I2C_CLR_STOPC I2C_CLR_STOPC_Msk /*!< Clear stop condition generation complete flag */ +#define I2C_CLR_BUSERRC_Pos (8U) +#define I2C_CLR_BUSERRC_Msk (0x1U << I2C_CLR_BUSERRC_Pos) /*!< 0x00000100 */ +#define I2C_CLR_BUSERRC I2C_CLR_BUSERRC_Msk /*!< Clear bus error flag */ +#define I2C_CLR_ARLOSTC_Pos (9U) +#define I2C_CLR_ARLOSTC_Msk (0x1U << I2C_CLR_ARLOSTC_Pos) /*!< 0x00000200 */ +#define I2C_CLR_ARLOSTC I2C_CLR_ARLOSTC_Msk /*!< Clear arbitration lost flag */ +#define I2C_CLR_OUFC_Pos (10U) +#define I2C_CLR_OUFC_Msk (0x1U << I2C_CLR_OUFC_Pos) /*!< 0x00000400 */ +#define I2C_CLR_OUFC I2C_CLR_OUFC_Msk /*!< Clear overload / underload flag */ +#define I2C_CLR_PECERRC_Pos (11U) +#define I2C_CLR_PECERRC_Msk (0x1U << I2C_CLR_PECERRC_Pos) /*!< 0x00000800 */ +#define I2C_CLR_PECERRC I2C_CLR_PECERRC_Msk /*!< Clear PEC receive error flag */ +#define I2C_CLR_TMOUTC_Pos (12U) +#define I2C_CLR_TMOUTC_Msk (0x1U << I2C_CLR_TMOUTC_Pos) /*!< 0x00001000 */ +#define I2C_CLR_TMOUTC I2C_CLR_TMOUTC_Msk /*!< Clear SMBus timeout flag */ +#define I2C_CLR_ALERTC_Pos (13U) +#define I2C_CLR_ALERTC_Msk (0x1U << I2C_CLR_ALERTC_Pos) /*!< 0x00002000 */ +#define I2C_CLR_ALERTC I2C_CLR_ALERTC_Msk /*!< Clear SMBus alert flag */ + +/******************* Bit definition for I2C_PEC register ********************/ +#define I2C_PEC_PECVAL_Pos (0U) +#define I2C_PEC_PECVAL_Msk (0xFFU << I2C_PEC_PECVAL_Pos) /*!< 0x000000FF */ +#define I2C_PEC_PECVAL I2C_PEC_PECVAL_Msk /*!< PEC value */ + +/******************* Bit definition for I2C_RXDT register *******************/ +#define I2C_RXDT_DT_Pos (0U) +#define I2C_RXDT_DT_Msk (0xFFU << I2C_RXDT_DT_Pos) /*!< 0x000000FF */ +#define I2C_RXDT_DT I2C_RXDT_DT_Msk /*!< Receive data register */ + +/******************* Bit definition for I2C_TXDT register *******************/ +#define I2C_TXDT_DT_Pos (0U) +#define I2C_TXDT_DT_Msk (0xFFU << I2C_TXDT_DT_Pos) /*!< 0x000000FF */ +#define I2C_TXDT_DT I2C_TXDT_DT_Msk /*!< Transmit data register */ + +/******************************************************************************/ +/* */ +/* Universal synchronous/asynchronous receiver/transmitter (USART) */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for USART_STS register *******************/ +#define USART_STS_PERR_Pos (0U) +#define USART_STS_PERR_Msk (0x1U << USART_STS_PERR_Pos) /*!< 0x00000001 */ +#define USART_STS_PERR USART_STS_PERR_Msk /*!< Parity error */ +#define USART_STS_FERR_Pos (1U) +#define USART_STS_FERR_Msk (0x1U << USART_STS_FERR_Pos) /*!< 0x00000002 */ +#define USART_STS_FERR USART_STS_FERR_Msk /*!< Framing error */ +#define USART_STS_NERR_Pos (2U) +#define USART_STS_NERR_Msk (0x1U << USART_STS_NERR_Pos) /*!< 0x00000004 */ +#define USART_STS_NERR USART_STS_NERR_Msk /*!< Noise error */ +#define USART_STS_ROERR_Pos (3U) +#define USART_STS_ROERR_Msk (0x1U << USART_STS_ROERR_Pos) /*!< 0x00000008 */ +#define USART_STS_ROERR USART_STS_ROERR_Msk /*!< Receiver overflow error */ +#define USART_STS_IDLEF_Pos (4U) +#define USART_STS_IDLEF_Msk (0x1U << USART_STS_IDLEF_Pos) /*!< 0x00000010 */ +#define USART_STS_IDLEF USART_STS_IDLEF_Msk /*!< Idle flag */ +#define USART_STS_RDBF_Pos (5U) +#define USART_STS_RDBF_Msk (0x1U << USART_STS_RDBF_Pos) /*!< 0x00000020 */ +#define USART_STS_RDBF USART_STS_RDBF_Msk /*!< Receive data buffer full */ +#define USART_STS_TDC_Pos (6U) +#define USART_STS_TDC_Msk (0x1U << USART_STS_TDC_Pos) /*!< 0x00000040 */ +#define USART_STS_TDC USART_STS_TDC_Msk /*!< Transmit data complete */ +#define USART_STS_TDBE_Pos (7U) +#define USART_STS_TDBE_Msk (0x1U << USART_STS_TDBE_Pos) /*!< 0x00000080 */ +#define USART_STS_TDBE USART_STS_TDBE_Msk /*!< Transmit data buffer empty */ +#define USART_STS_BFF_Pos (8U) +#define USART_STS_BFF_Msk (0x1U << USART_STS_BFF_Pos) /*!< 0x00000100 */ +#define USART_STS_BFF USART_STS_BFF_Msk /*!< Break frame flag */ +#define USART_STS_CTSCF_Pos (9U) +#define USART_STS_CTSCF_Msk (0x1U << USART_STS_CTSCF_Pos) /*!< 0x00000200 */ +#define USART_STS_CTSCF USART_STS_CTSCF_Msk /*!< CTS change flag */ +#define USART_STS_RTODF_Pos (11U) +#define USART_STS_RTODF_Msk (0x1U << USART_STS_RTODF_Pos) /*!< 0x00000800 */ +#define USART_STS_RTODF USART_STS_RTODF_Msk /*!< Receiver timeout detection flag */ +#define USART_STS_CMDF_Pos (17U) +#define USART_STS_CMDF_Msk (0x1U << USART_STS_CMDF_Pos) /*!< 0x00020000 */ +#define USART_STS_CMDF USART_STS_CMDF_Msk /*!< Byte match detection flag */ + +/******************* Bit definition for USART_DT register *******************/ +#define USART_DT_DT_Pos (0U) +#define USART_DT_DT_Msk (0x1FFU << USART_DT_DT_Pos) /*!< 0x000001FF */ +#define USART_DT_DT USART_DT_DT_Msk /*!< Data value */ + +/***************** Bit definition for USART_BAUDR register ******************/ +#define USART_BAUDR_DIV_Pos (0U) +#define USART_BAUDR_DIV_Msk (0xFFFFU << USART_BAUDR_DIV_Pos) /*!< 0x0000FFFF */ +#define USART_BAUDR_DIV USART_BAUDR_DIV_Msk /*!< Divider */ + +/***************** Bit definition for USART_CTRL1 register ******************/ +#define USART_CTRL1_SBF_Pos (0U) +#define USART_CTRL1_SBF_Msk (0x1U << USART_CTRL1_SBF_Pos) /*!< 0x00000001 */ +#define USART_CTRL1_SBF USART_CTRL1_SBF_Msk /*!< Send break frame */ +#define USART_CTRL1_RM_Pos (1U) +#define USART_CTRL1_RM_Msk (0x1U << USART_CTRL1_RM_Pos) /*!< 0x00000002 */ +#define USART_CTRL1_RM USART_CTRL1_RM_Msk /*!< Receiver mute */ +#define USART_CTRL1_REN_Pos (2U) +#define USART_CTRL1_REN_Msk (0x1U << USART_CTRL1_REN_Pos) /*!< 0x00000004 */ +#define USART_CTRL1_REN USART_CTRL1_REN_Msk /*!< Receiver enable */ +#define USART_CTRL1_TEN_Pos (3U) +#define USART_CTRL1_TEN_Msk (0x1U << USART_CTRL1_TEN_Pos) /*!< 0x00000008 */ +#define USART_CTRL1_TEN USART_CTRL1_TEN_Msk /*!< Transmitter enable */ +#define USART_CTRL1_IDLEIEN_Pos (4U) +#define USART_CTRL1_IDLEIEN_Msk (0x1U << USART_CTRL1_IDLEIEN_Pos) /*!< 0x00000010 */ +#define USART_CTRL1_IDLEIEN USART_CTRL1_IDLEIEN_Msk /*!< IDLE interrupt enable */ +#define USART_CTRL1_RDBFIEN_Pos (5U) +#define USART_CTRL1_RDBFIEN_Msk (0x1U << USART_CTRL1_RDBFIEN_Pos) /*!< 0x00000020 */ +#define USART_CTRL1_RDBFIEN USART_CTRL1_RDBFIEN_Msk /*!< RDBF interrupt enable */ +#define USART_CTRL1_TDCIEN_Pos (6U) +#define USART_CTRL1_TDCIEN_Msk (0x1U << USART_CTRL1_TDCIEN_Pos) /*!< 0x00000040 */ +#define USART_CTRL1_TDCIEN USART_CTRL1_TDCIEN_Msk /*!< TDC interrupt enable */ +#define USART_CTRL1_TDBEIEN_Pos (7U) +#define USART_CTRL1_TDBEIEN_Msk (0x1U << USART_CTRL1_TDBEIEN_Pos) /*!< 0x00000080 */ +#define USART_CTRL1_TDBEIEN USART_CTRL1_TDBEIEN_Msk /*!< TDBE interrupt enable */ +#define USART_CTRL1_PERRIEN_Pos (8U) +#define USART_CTRL1_PERRIEN_Msk (0x1U << USART_CTRL1_PERRIEN_Pos) /*!< 0x00000100 */ +#define USART_CTRL1_PERRIEN USART_CTRL1_PERRIEN_Msk /*!< PERR interrupt enable */ +#define USART_CTRL1_PSEL_Pos (9U) +#define USART_CTRL1_PSEL_Msk (0x1U << USART_CTRL1_PSEL_Pos) /*!< 0x00000200 */ +#define USART_CTRL1_PSEL USART_CTRL1_PSEL_Msk /*!< Parity selection */ +#define USART_CTRL1_PEN_Pos (10U) +#define USART_CTRL1_PEN_Msk (0x1U << USART_CTRL1_PEN_Pos) /*!< 0x00000400 */ +#define USART_CTRL1_PEN USART_CTRL1_PEN_Msk /*!< Parity enable */ +#define USART_CTRL1_WUM_Pos (11U) +#define USART_CTRL1_WUM_Msk (0x1U << USART_CTRL1_WUM_Pos) /*!< 0x00000800 */ +#define USART_CTRL1_WUM USART_CTRL1_WUM_Msk /*!< Wakeup mode */ +#define USART_CTRL1_DBN0_Pos (12U) +#define USART_CTRL1_DBN0_Msk (0x1U << USART_CTRL1_DBN0_Pos) /*!< 0x00001000 */ +#define USART_CTRL1_DBN0 USART_CTRL1_DBN0_Msk /*!< Data bit num 0 */ +#define USART_CTRL1_UEN_Pos (13U) +#define USART_CTRL1_UEN_Msk (0x1U << USART_CTRL1_UEN_Pos) /*!< 0x00002000 */ +#define USART_CTRL1_UEN USART_CTRL1_UEN_Msk /*!< USART enable */ +#define USART_CTRL1_CMDIE_Pos (14U) +#define USART_CTRL1_CMDIE_Msk (0x1U << USART_CTRL1_CMDIE_Pos) /*!< 0x00004000 */ +#define USART_CTRL1_CMDIE USART_CTRL1_CMDIE_Msk /*!< Character match detection interrupt enable */ +#define USART_CTRL1_TCDT_Pos (16U) +#define USART_CTRL1_TCDT_Msk (0x1FU << USART_CTRL1_TCDT_Pos) /*!< 0x001F0000 */ +#define USART_CTRL1_TCDT USART_CTRL1_TCDT_Msk /*!< Transmit complete delay time */ +#define USART_CTRL1_TSDT_Pos (21U) +#define USART_CTRL1_TSDT_Msk (0x1FU << USART_CTRL1_TSDT_Pos) /*!< 0x03E00000 */ +#define USART_CTRL1_TSDT USART_CTRL1_TSDT_Msk /*!< Transmit start delay time */ +#define USART_CTRL1_RETODIE_Pos (26U) +#define USART_CTRL1_RETODIE_Msk (0x1U << USART_CTRL1_RETODIE_Pos) /*!< 0x04000000 */ +#define USART_CTRL1_RETODIE USART_CTRL1_RETODIE_Msk /*!< Receiver timeout detection interrupt enable */ +#define USART_CTRL1_RTODEN_Pos (27U) +#define USART_CTRL1_RTODEN_Msk (0x1U << USART_CTRL1_RTODEN_Pos) /*!< 0x08000000 */ +#define USART_CTRL1_RTODEN USART_CTRL1_RTODEN_Msk /*!< Receiver timeout detection enable */ +#define USART_CTRL1_DBN1_Pos (28U) +#define USART_CTRL1_DBN1_Msk (0x1U << USART_CTRL1_DBN1_Pos) /*!< 0x10000000 */ +#define USART_CTRL1_DBN1 USART_CTRL1_DBN1_Msk /*!< Data bit num 1 */ + +/***************** Bit definition for USART_CTRL2 register ******************/ +#define USART_CTRL2_IDL_Pos (0U) +#define USART_CTRL2_IDL_Msk (0xFU << USART_CTRL2_IDL_Pos) /*!< 0x0000000F */ +#define USART_CTRL2_IDL USART_CTRL2_IDL_Msk /*!< USART identification low */ +#define USART_CTRL2_IDBN_Pos (4U) +#define USART_CTRL2_IDBN_Msk (0x1U << USART_CTRL2_IDBN_Pos) /*!< 0x00000010 */ +#define USART_CTRL2_IDBN USART_CTRL2_IDBN_Msk /*!< Identification bit number */ +#define USART_CTRL2_BFBN_Pos (5U) +#define USART_CTRL2_BFBN_Msk (0x1U << USART_CTRL2_BFBN_Pos) /*!< 0x00000020 */ +#define USART_CTRL2_BFBN USART_CTRL2_BFBN_Msk /*!< Break frame bit num */ +#define USART_CTRL2_BFIEN_Pos (6U) +#define USART_CTRL2_BFIEN_Msk (0x1U << USART_CTRL2_BFIEN_Pos) /*!< 0x00000040 */ +#define USART_CTRL2_BFIEN USART_CTRL2_BFIEN_Msk /*!< Break frame interrupt enable */ +#define USART_CTRL2_LBCP_Pos (8U) +#define USART_CTRL2_LBCP_Msk (0x1U << USART_CTRL2_LBCP_Pos) /*!< 0x00000100 */ +#define USART_CTRL2_LBCP USART_CTRL2_LBCP_Msk /*!< Last bit clock pulse */ +#define USART_CTRL2_CLKPHA_Pos (9U) +#define USART_CTRL2_CLKPHA_Msk (0x1U << USART_CTRL2_CLKPHA_Pos) /*!< 0x00000200 */ +#define USART_CTRL2_CLKPHA USART_CTRL2_CLKPHA_Msk /*!< Clock phase */ +#define USART_CTRL2_CLKPOL_Pos (10U) +#define USART_CTRL2_CLKPOL_Msk (0x1U << USART_CTRL2_CLKPOL_Pos) /*!< 0x00000400 */ +#define USART_CTRL2_CLKPOL USART_CTRL2_CLKPOL_Msk /*!< Clock polarity */ +#define USART_CTRL2_CLKEN_Pos (11U) +#define USART_CTRL2_CLKEN_Msk (0x1U << USART_CTRL2_CLKEN_Pos) /*!< 0x00000800 */ +#define USART_CTRL2_CLKEN USART_CTRL2_CLKEN_Msk /*!< Clock enable */ + +/*!< STOPBN configuration */ +#define USART_CTRL2_STOPBN_Pos (12U) +#define USART_CTRL2_STOPBN_Msk (0x3U << USART_CTRL2_STOPBN_Pos) /*!< 0x00003000 */ +#define USART_CTRL2_STOPBN USART_CTRL2_STOPBN_Msk /*!< STOPBN[1:0] bits (STOP bit num) */ +#define USART_CTRL2_STOPBN_0 (0x1U << USART_CTRL2_STOPBN_Pos) /*!< 0x00001000 */ +#define USART_CTRL2_STOPBN_1 (0x2U << USART_CTRL2_STOPBN_Pos) /*!< 0x00002000 */ + +#define USART_CTRL2_LINEN_Pos (14U) +#define USART_CTRL2_LINEN_Msk (0x1U << USART_CTRL2_LINEN_Pos) /*!< 0x00004000 */ +#define USART_CTRL2_LINEN USART_CTRL2_LINEN_Msk /*!< LIN mode enable */ +#define USART_CTRL2_TRPSWAP_Pos (15U) +#define USART_CTRL2_TRPSWAP_Msk (0x1U << USART_CTRL2_TRPSWAP_Pos) /*!< 0x00008000 */ +#define USART_CTRL2_TRPSWAP USART_CTRL2_TRPSWAP_Msk /*!< Transmit/receive pin swap */ +#define USART_CTRL2_RXREV_Pos (16U) +#define USART_CTRL2_RXREV_Msk (0x1U << USART_CTRL2_RXREV_Pos) /*!< 0x00010000 */ +#define USART_CTRL2_RXREV USART_CTRL2_RXREV_Msk /*!< RX polarity reverse */ +#define USART_CTRL2_TXREV_Pos (17U) +#define USART_CTRL2_TXREV_Msk (0x1U << USART_CTRL2_TXREV_Pos) /*!< 0x00020000 */ +#define USART_CTRL2_TXREV USART_CTRL2_TXREV_Msk /*!< TX polarity reverse */ +#define USART_CTRL2_DTREV_Pos (18U) +#define USART_CTRL2_DTREV_Msk (0x1U << USART_CTRL2_DTREV_Pos) /*!< 0x00040000 */ +#define USART_CTRL2_DTREV USART_CTRL2_DTREV_Msk /*!< DT register polarity reverse */ +#define USART_CTRL2_MTF_Pos (19U) +#define USART_CTRL2_MTF_Msk (0x1U << USART_CTRL2_MTF_Pos) /*!< 0x00080000 */ +#define USART_CTRL2_MTF USART_CTRL2_MTF_Msk /*!< MSB transmit first */ +#define USART_CTRL2_IDH_Pos (28U) +#define USART_CTRL2_IDH_Msk (0xFU << USART_CTRL2_IDH_Pos) /*!< 0xF0000000 */ +#define USART_CTRL2_IDH USART_CTRL2_IDH_Msk /*!< USART identification high */ + +/***************** Bit definition for USART_CTRL3 register ******************/ +#define USART_CTRL3_ERRIEN_Pos (0U) +#define USART_CTRL3_ERRIEN_Msk (0x1U << USART_CTRL3_ERRIEN_Pos) /*!< 0x00000001 */ +#define USART_CTRL3_ERRIEN USART_CTRL3_ERRIEN_Msk /*!< Error interrupt enable */ +#define USART_CTRL3_IRDAEN_Pos (1U) +#define USART_CTRL3_IRDAEN_Msk (0x1U << USART_CTRL3_IRDAEN_Pos) /*!< 0x00000002 */ +#define USART_CTRL3_IRDAEN USART_CTRL3_IRDAEN_Msk /*!< IrDA enable */ +#define USART_CTRL3_IRDALP_Pos (2U) +#define USART_CTRL3_IRDALP_Msk (0x1U << USART_CTRL3_IRDALP_Pos) /*!< 0x00000004 */ +#define USART_CTRL3_IRDALP USART_CTRL3_IRDALP_Msk /*!< IrDA low-power mode */ +#define USART_CTRL3_SLBEN_Pos (3U) +#define USART_CTRL3_SLBEN_Msk (0x1U << USART_CTRL3_SLBEN_Pos) /*!< 0x00000008 */ +#define USART_CTRL3_SLBEN USART_CTRL3_SLBEN_Msk /*!< Single-wire bidirectional half-duplex enable */ +#define USART_CTRL3_SCNACKEN_Pos (4U) +#define USART_CTRL3_SCNACKEN_Msk (0x1U << USART_CTRL3_SCNACKEN_Pos) /*!< 0x00000010 */ +#define USART_CTRL3_SCNACKEN USART_CTRL3_SCNACKEN_Msk /*!< Smart Card NACK enable */ +#define USART_CTRL3_SCMEN_Pos (5U) +#define USART_CTRL3_SCMEN_Msk (0x1U << USART_CTRL3_SCMEN_Pos) /*!< 0x00000020 */ +#define USART_CTRL3_SCMEN USART_CTRL3_SCMEN_Msk /*!< Smart Card mode enable */ +#define USART_CTRL3_DMAREN_Pos (6U) +#define USART_CTRL3_DMAREN_Msk (0x1U << USART_CTRL3_DMAREN_Pos) /*!< 0x00000040 */ +#define USART_CTRL3_DMAREN USART_CTRL3_DMAREN_Msk /*!< DMA receiver enable */ +#define USART_CTRL3_DMATEN_Pos (7U) +#define USART_CTRL3_DMATEN_Msk (0x1U << USART_CTRL3_DMATEN_Pos) /*!< 0x00000080 */ +#define USART_CTRL3_DMATEN USART_CTRL3_DMATEN_Msk /*!< DMA transmitter enable */ +#define USART_CTRL3_RTSEN_Pos (8U) +#define USART_CTRL3_RTSEN_Msk (0x1U << USART_CTRL3_RTSEN_Pos) /*!< 0x00000100 */ +#define USART_CTRL3_RTSEN USART_CTRL3_RTSEN_Msk /*!< RTS enable */ +#define USART_CTRL3_CTSEN_Pos (9U) +#define USART_CTRL3_CTSEN_Msk (0x1U << USART_CTRL3_CTSEN_Pos) /*!< 0x00000200 */ +#define USART_CTRL3_CTSEN USART_CTRL3_CTSEN_Msk /*!< CTS enable */ +#define USART_CTRL3_CTSCFIEN_Pos (10U) +#define USART_CTRL3_CTSCFIEN_Msk (0x1U << USART_CTRL3_CTSCFIEN_Pos) /*!< 0x00000400 */ +#define USART_CTRL3_CTSCFIEN USART_CTRL3_CTSCFIEN_Msk /*!< CTSCF interrupt enable */ +#define USART_CTRL3_RS485EN_Pos (14U) +#define USART_CTRL3_RS485EN_Msk (0x1U << USART_CTRL3_RS485EN_Pos) /*!< 0x00004000 */ +#define USART_CTRL3_RS485EN USART_CTRL3_RS485EN_Msk /*!< RS485 enable */ +#define USART_CTRL3_DEP_Pos (15U) +#define USART_CTRL3_DEP_Msk (0x1U << USART_CTRL3_DEP_Pos) /*!< 0x00008000 */ +#define USART_CTRL3_DEP USART_CTRL3_DEP_Msk /*!< DE polarity selection */ + +/****************** Bit definition for USART_GDIV register ******************/ +/*!< ISDIV configuration */ +#define USART_GDIV_ISDIV_Pos (0U) +#define USART_GDIV_ISDIV_Msk (0xFFU << USART_GDIV_ISDIV_Pos) /*!< 0x000000FF */ +#define USART_GDIV_ISDIV USART_GDIV_ISDIV_Msk /*!< ISDIV[7:0] bits (IrDA/Smart Card division) */ +#define USART_GDIV_ISDIV_0 (0x01U << USART_GDIV_ISDIV_Pos) /*!< 0x00000001 */ +#define USART_GDIV_ISDIV_1 (0x02U << USART_GDIV_ISDIV_Pos) /*!< 0x00000002 */ +#define USART_GDIV_ISDIV_2 (0x04U << USART_GDIV_ISDIV_Pos) /*!< 0x00000004 */ +#define USART_GDIV_ISDIV_3 (0x08U << USART_GDIV_ISDIV_Pos) /*!< 0x00000008 */ +#define USART_GDIV_ISDIV_4 (0x10U << USART_GDIV_ISDIV_Pos) /*!< 0x00000010 */ +#define USART_GDIV_ISDIV_5 (0x20U << USART_GDIV_ISDIV_Pos) /*!< 0x00000020 */ +#define USART_GDIV_ISDIV_6 (0x40U << USART_GDIV_ISDIV_Pos) /*!< 0x00000040 */ +#define USART_GDIV_ISDIV_7 (0x80U << USART_GDIV_ISDIV_Pos) /*!< 0x00000080 */ + +#define USART_GDIV_SCGT_Pos (8U) +#define USART_GDIV_SCGT_Msk (0xFFU << USART_GDIV_SCGT_Pos) /*!< 0x0000FF00 */ +#define USART_GDIV_SCGT USART_GDIV_SCGT_Msk /*!< Smart Card guard time value */ + +/****************** Bit definition for USART_RTOV register ******************/ +#define USART_RTOV_RTOV_Pos (0U) +#define USART_RTOV_RTOV_Msk (0xFFFFFFU << USART_RTOV_RTOV_Pos) /*!< 0x00FFFFFF */ +#define USART_RTOV_RTOV USART_RTOV_RTOV_Msk /*!< Receiver timeout value */ + +/****************** Bit definition for USART_IFC register *******************/ +#define USART_IFC_RTODFC_Pos (11U) +#define USART_IFC_RTODFC_Msk (0x1U << USART_IFC_RTODFC_Pos) /*!< 0x00000800 */ +#define USART_IFC_RTODFC USART_IFC_RTODFC_Msk /*!< Receiver timeout detection flag clear */ +#define USART_IFC_CMDFC_Pos (17U) +#define USART_IFC_CMDFC_Msk (0x1U << USART_IFC_CMDFC_Pos) /*!< 0x00020000 */ +#define USART_IFC_CMDFC USART_IFC_CMDFC_Msk /*!< Character match detection flag clear */ + +/******************************************************************************/ +/* */ +/* Serial peripheral interface (SPI) */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for SPI_CTRL1 register *******************/ +#define SPI_CTRL1_CLKPHA_Pos (0U) +#define SPI_CTRL1_CLKPHA_Msk (0x1U << SPI_CTRL1_CLKPHA_Pos) /*!< 0x00000001 */ +#define SPI_CTRL1_CLKPHA SPI_CTRL1_CLKPHA_Msk /*!< Clock phase */ +#define SPI_CTRL1_CLKPOL_Pos (1U) +#define SPI_CTRL1_CLKPOL_Msk (0x1U << SPI_CTRL1_CLKPOL_Pos) /*!< 0x00000002 */ +#define SPI_CTRL1_CLKPOL SPI_CTRL1_CLKPOL_Msk /*!< Clock polarity */ +#define SPI_CTRL1_MSTEN_Pos (2U) +#define SPI_CTRL1_MSTEN_Msk (0x1U << SPI_CTRL1_MSTEN_Pos) /*!< 0x00000004 */ +#define SPI_CTRL1_MSTEN SPI_CTRL1_MSTEN_Msk /*!< Master enable */ + +/*!< MDIV configuration */ +#define SPI_CTRL1_MDIV_Msk ((SPI_CTRL2_MDIV) | (0x7U << 3) /*!< 0x00000138 */ +#define SPI_CTRL1_MDIV SPI_CTRL1_MDIV_Msk /*!< MDIV[3:0] bits (Master clock frequency division) */ +#define SPI_CTRL1_MDIV_0 (0x1U << 3) /*!< 0x00000008 */ +#define SPI_CTRL1_MDIV_1 (0x2U << 3) /*!< 0x00000010 */ +#define SPI_CTRL1_MDIV_2 (0x4U << 3) /*!< 0x00000020 */ +#define SPI_CTRL1_MDIV_3 SPI_CTRL2_MDIV /*!< 0x00000100 */ + +#define SPI_CTRL1_SPIEN_Pos (6U) +#define SPI_CTRL1_SPIEN_Msk (0x1U << SPI_CTRL1_SPIEN_Pos) /*!< 0x00000040 */ +#define SPI_CTRL1_SPIEN SPI_CTRL1_SPIEN_Msk /*!< SPI enable */ +#define SPI_CTRL1_LTF_Pos (7U) +#define SPI_CTRL1_LTF_Msk (0x1U << SPI_CTRL1_LTF_Pos) /*!< 0x00000080 */ +#define SPI_CTRL1_LTF SPI_CTRL1_LTF_Msk /*!< LSB transmit first */ +#define SPI_CTRL1_SWCSIL_Pos (8U) +#define SPI_CTRL1_SWCSIL_Msk (0x1U << SPI_CTRL1_SWCSIL_Pos) /*!< 0x00000100 */ +#define SPI_CTRL1_SWCSIL SPI_CTRL1_SWCSIL_Msk /*!< Software CS internal level */ +#define SPI_CTRL1_SWCSEN_Pos (9U) +#define SPI_CTRL1_SWCSEN_Msk (0x1U << SPI_CTRL1_SWCSEN_Pos) /*!< 0x00000200 */ +#define SPI_CTRL1_SWCSEN SPI_CTRL1_SWCSEN_Msk /*!< Software CS enable */ +#define SPI_CTRL1_ORA_Pos (10U) +#define SPI_CTRL1_ORA_Msk (0x1U << SPI_CTRL1_ORA_Pos) /*!< 0x00000400 */ +#define SPI_CTRL1_ORA SPI_CTRL1_ORA_Msk /*!< Receive-only active */ +#define SPI_CTRL1_FBN_Pos (11U) +#define SPI_CTRL1_FBN_Msk (0x1U << SPI_CTRL1_FBN_Pos) /*!< 0x00000800 */ +#define SPI_CTRL1_FBN SPI_CTRL1_FBN_Msk /*!< Frame bit num */ +#define SPI_CTRL1_NTC_Pos (12U) +#define SPI_CTRL1_NTC_Msk (0x1U << SPI_CTRL1_NTC_Pos) /*!< 0x00001000 */ +#define SPI_CTRL1_NTC SPI_CTRL1_NTC_Msk /*!< Transmit CRC next */ +#define SPI_CTRL1_CCEN_Pos (13U) +#define SPI_CTRL1_CCEN_Msk (0x1U << SPI_CTRL1_CCEN_Pos) /*!< 0x00002000 */ +#define SPI_CTRL1_CCEN SPI_CTRL1_CCEN_Msk /*!< RC calculation enable */ +#define SPI_CTRL1_SLBTD_Pos (14U) +#define SPI_CTRL1_SLBTD_Msk (0x1U << SPI_CTRL1_SLBTD_Pos) /*!< 0x00004000 */ +#define SPI_CTRL1_SLBTD SPI_CTRL1_SLBTD_Msk /*!< Single line bidirectional half-duplex transmission direction */ +#define SPI_CTRL1_SLBEN_Pos (15U) +#define SPI_CTRL1_SLBEN_Msk (0x1U << SPI_CTRL1_SLBEN_Pos) /*!< 0x00008000 */ +#define SPI_CTRL1_SLBEN SPI_CTRL1_SLBEN_Msk /*!< Single line bidirectional half-duplex enable */ + +/****************** Bit definition for SPI_CTRL2 register *******************/ +#define SPI_CTRL2_DMAREN_Pos (0U) +#define SPI_CTRL2_DMAREN_Msk (0x1U << SPI_CTRL2_DMAREN_Pos) /*!< 0x00000001 */ +#define SPI_CTRL2_DMAREN SPI_CTRL2_DMAREN_Msk /*!< DMA receive enable */ +#define SPI_CTRL2_DMATEN_Pos (1U) +#define SPI_CTRL2_DMATEN_Msk (0x1U << SPI_CTRL2_DMATEN_Pos) /*!< 0x00000002 */ +#define SPI_CTRL2_DMATEN SPI_CTRL2_DMATEN_Msk /*!< DMA transmit enable */ +#define SPI_CTRL2_HWCSOE_Pos (2U) +#define SPI_CTRL2_HWCSOE_Msk (0x1U << SPI_CTRL2_HWCSOE_Pos) /*!< 0x00000004 */ +#define SPI_CTRL2_HWCSOE SPI_CTRL2_HWCSOE_Msk /*!< Hardware CS output enable */ +#define SPI_CTRL2_TIEN_Pos (4U) +#define SPI_CTRL2_TIEN_Msk (0x1U << SPI_CTRL2_TIEN_Pos) /*!< 0x00000010 */ +#define SPI_CTRL2_TIEN SPI_CTRL2_TIEN_Msk /*!< TI mode enable */ +#define SPI_CTRL2_ERRIE_Pos (5U) +#define SPI_CTRL2_ERRIE_Msk (0x1U << SPI_CTRL2_ERRIE_Pos) /*!< 0x00000020 */ +#define SPI_CTRL2_ERRIE SPI_CTRL2_ERRIE_Msk /*!< Error interrupt enable */ +#define SPI_CTRL2_RDBFIE_Pos (6U) +#define SPI_CTRL2_RDBFIE_Msk (0x1U << SPI_CTRL2_RDBFIE_Pos) /*!< 0x00000040 */ +#define SPI_CTRL2_RDBFIE SPI_CTRL2_RDBFIE_Msk /*!< Receive data buffer full interrupt enable */ +#define SPI_CTRL2_TDBEIE_Pos (7U) +#define SPI_CTRL2_TDBEIE_Msk (0x1U << SPI_CTRL2_TDBEIE_Pos) /*!< 0x00000080 */ +#define SPI_CTRL2_TDBEIE SPI_CTRL2_TDBEIE_Msk /*!< Transmit data buffer empty interrupt enable */ +#define SPI_CTRL2_MDIV_Pos (8U) +#define SPI_CTRL2_MDIV_Msk (0x1U << SPI_CTRL2_MDIV_Pos) /*!< 0x00000100 */ +#define SPI_CTRL2_MDIV SPI_CTRL2_MDIV_Msk /*!< Master clock frequency division */ +#define SPI_CTRL2_MDIV3EN_Pos (9U) +#define SPI_CTRL2_MDIV3EN_Msk (0x1U << SPI_CTRL2_MDIV3EN_Pos) /*!< 0x00000200 */ +#define SPI_CTRL2_MDIV3EN SPI_CTRL2_MDIV3EN_Msk /*!< Master clock frequency divided by 3 enable */ + +/******************* Bit definition for SPI_STS register ********************/ +#define SPI_STS_RDBF_Pos (0U) +#define SPI_STS_RDBF_Msk (0x1U << SPI_STS_RDBF_Pos) /*!< 0x00000001 */ +#define SPI_STS_RDBF SPI_STS_RDBF_Msk /*!< Receive data buffer full */ +#define SPI_STS_TDBE_Pos (1U) +#define SPI_STS_TDBE_Msk (0x1U << SPI_STS_TDBE_Pos) /*!< 0x00000002 */ +#define SPI_STS_TDBE SPI_STS_TDBE_Msk /*!< Transmit data buffer empty */ +#define SPI_STS_ACS_Pos (2U) +#define SPI_STS_ACS_Msk (0x1U << SPI_STS_ACS_Pos) /*!< 0x00000004 */ +#define SPI_STS_ACS SPI_STS_ACS_Msk /*!< Audio channel state */ +#define SPI_STS_TUERR_Pos (3U) +#define SPI_STS_TUERR_Msk (0x1U << SPI_STS_TUERR_Pos) /*!< 0x00000008 */ +#define SPI_STS_TUERR SPI_STS_TUERR_Msk /*!< Transmitter underload error */ +#define SPI_STS_CCERR_Pos (4U) +#define SPI_STS_CCERR_Msk (0x1U << SPI_STS_CCERR_Pos) /*!< 0x00000010 */ +#define SPI_STS_CCERR SPI_STS_CCERR_Msk /*!< CRC error */ +#define SPI_STS_MMERR_Pos (5U) +#define SPI_STS_MMERR_Msk (0x1U << SPI_STS_MMERR_Pos) /*!< 0x00000020 */ +#define SPI_STS_MMERR SPI_STS_MMERR_Msk /*!< Master mode error */ +#define SPI_STS_ROERR_Pos (6U) +#define SPI_STS_ROERR_Msk (0x1U << SPI_STS_ROERR_Pos) /*!< 0x00000040 */ +#define SPI_STS_ROERR SPI_STS_ROERR_Msk /*!< Receiver overflow error */ +#define SPI_STS_BF_Pos (7U) +#define SPI_STS_BF_Msk (0x1U << SPI_STS_BF_Pos) /*!< 0x00000080 */ +#define SPI_STS_BF SPI_STS_BF_Msk /*!< Busy flag */ +#define SPI_STS_CSPAS_Pos (8U) +#define SPI_STS_CSPAS_Msk (0x1U << SPI_STS_CSPAS_Pos) /*!< 0x00000100 */ +#define SPI_STS_CSPAS SPI_STS_CSPAS_Msk /*!< CS pulse abnormal setting flag */ + +/******************** Bit definition for SPI_DT register ********************/ +#define SPI_DT_DT_Pos (0U) +#define SPI_DT_DT_Msk (0xFFFFU << SPI_DT_DT_Pos) /*!< 0x0000FFFF */ +#define SPI_DT_DT SPI_DT_DT_Msk /*!< Data value */ + +/******************* Bit definition for SPI_CPOLY register ******************/ +#define SPI_CPOLY_CPOLY_Pos (0U) +#define SPI_CPOLY_CPOLY_Msk (0xFFFFU << SPI_CPOLY_CPOLY_Pos) /*!< 0x0000FFFF */ +#define SPI_CPOLY_CPOLY SPI_CPOLY_CPOLY_Msk /*!< CRC polynomial */ + +/******************* Bit definition for SPI_RCRC register *******************/ +#define SPI_RCRC_RCRC_Pos (0U) +#define SPI_RCRC_RCRC_Msk (0xFFFFU << SPI_RCRC_RCRC_Pos) /*!< 0x0000FFFF */ +#define SPI_RCRC_RCRC SPI_RCRC_RCRC_Msk /*!< Receive CRC */ + +/******************* Bit definition for SPI_TCRC register *******************/ +#define SPI_TCRC_TCRC_Pos (0U) +#define SPI_TCRC_TCRC_Msk (0xFFFFU << SPI_TCRC_TCRC_Pos) /*!< 0x0000FFFF */ +#define SPI_TCRC_TCRC SPI_TCRC_TCRC_Msk /*!< Transmit CRC */ + +/***************** Bit definition for SPI_I2SCTRL register ******************/ +#define SPI_I2SCTRL_I2SCBN_Pos (0U) +#define SPI_I2SCTRL_I2SCBN_Msk (0x1U << SPI_I2SCTRL_I2SCBN_Pos) /*!< 0x00000001 */ +#define SPI_I2SCTRL_I2SCBN SPI_I2SCTRL_I2SCBN_Msk /*!< Channel length (I2S channel bit num) */ + +/*!< I2SDBN configuration */ +#define SPI_I2SCTRL_I2SDBN_Pos (1U) +#define SPI_I2SCTRL_I2SDBN_Msk (0x3U << SPI_I2SCTRL_I2SDBN_Pos) /*!< 0x00000006 */ +#define SPI_I2SCTRL_I2SDBN SPI_I2SCTRL_I2SDBN_Msk /*!< I2SDBN[1:0] bits (I2S data bit num) */ +#define SPI_I2SCTRL_I2SDBN_0 (0x1U << SPI_I2SCTRL_I2SDBN_Pos) /*!< 0x00000002 */ +#define SPI_I2SCTRL_I2SDBN_1 (0x2U << SPI_I2SCTRL_I2SDBN_Pos) /*!< 0x00000004 */ + +#define SPI_I2SCTRL_I2SCLKPOL_Pos (3U) +#define SPI_I2SCTRL_I2SCLKPOL_Msk (0x1U << SPI_I2SCTRL_I2SCLKPOL_Pos) /*!< 0x00000008 */ +#define SPI_I2SCTRL_I2SCLKPOL SPI_I2SCTRL_I2SCLKPOL_Msk /*!< I2S clock polarity */ + +/*!< STDSEL configuration */ +#define SPI_I2SCTRL_STDSEL_Pos (4U) +#define SPI_I2SCTRL_STDSEL_Msk (0x3U << SPI_I2SCTRL_STDSEL_Pos) /*!< 0x00000030 */ +#define SPI_I2SCTRL_STDSEL SPI_I2SCTRL_STDSEL_Msk /*!< STDSEL[1:0] bits (I2S standard select) */ +#define SPI_I2SCTRL_STDSEL_0 (0x1U << SPI_I2SCTRL_STDSEL_Pos) /*!< 0x00000010 */ +#define SPI_I2SCTRL_STDSEL_1 (0x2U << SPI_I2SCTRL_STDSEL_Pos) /*!< 0x00000020 */ + +#define SPI_I2SCTRL_PCMFSSEL_Pos (7U) +#define SPI_I2SCTRL_PCMFSSEL_Msk (0x1U << SPI_I2SCTRL_PCMFSSEL_Pos) /*!< 0x00000080 */ +#define SPI_I2SCTRL_PCMFSSEL SPI_I2SCTRL_PCMFSSEL_Msk /*!< PCM frame synchronization */ + +/*!< OPERSEL configuration */ +#define SPI_I2SCTRL_OPERSEL_Pos (8U) +#define SPI_I2SCTRL_OPERSEL_Msk (0x3U << SPI_I2SCTRL_OPERSEL_Pos) /*!< 0x00000300 */ +#define SPI_I2SCTRL_OPERSEL SPI_I2SCTRL_OPERSEL_Msk /*!< OPERSEL[1:0] bits (I2S operation mode select) */ +#define SPI_I2SCTRL_OPERSEL_0 (0x1U << SPI_I2SCTRL_OPERSEL_Pos) /*!< 0x00000100 */ +#define SPI_I2SCTRL_OPERSEL_1 (0x2U << SPI_I2SCTRL_OPERSEL_Pos) /*!< 0x00000200 */ + +#define SPI_I2SCTRL_I2SEN_Pos (10U) +#define SPI_I2SCTRL_I2SEN_Msk (0x1U << SPI_I2SCTRL_I2SEN_Pos) /*!< 0x00000400 */ +#define SPI_I2SCTRL_I2SEN SPI_I2SCTRL_I2SEN_Msk /*!< I2S enable */ +#define SPI_I2SCTRL_I2SMSEL_Pos (11U) +#define SPI_I2SCTRL_I2SMSEL_Msk (0x1U << SPI_I2SCTRL_I2SMSEL_Pos) /*!< 0x00000800 */ +#define SPI_I2SCTRL_I2SMSEL SPI_I2SCTRL_I2SMSEL_Msk /*!< I2S mode select */ +#define SPI_I2SCTRL_I2SFDUPEN_Pos (13U) +#define SPI_I2SCTRL_I2SFDUPEN_Msk (0x1U << SPI_I2SCTRL_I2SFDUPEN_Pos) /*!< 0x00002000 */ +#define SPI_I2SCTRL_I2SFDUPEN SPI_I2SCTRL_I2SFDUPEN_Msk /*!< I2S full duplex enable */ + +/***************** Bit definition for SPI_I2SCLKP register ******************/ +#define SPI_I2SCLKP_I2SDIV_Msk ((0xFFU << 0) | (0x3U << 10)) /*!< 0x00000CFF */ +#define SPI_I2SCLKP_I2SDIV SPI_I2SCLKP_I2SDIV_Msk /*!< I2SDIV[9:0] bits (I2S division) */ +#define SPI_I2SCLKP_I2SODD_Pos (8U) +#define SPI_I2SCLKP_I2SODD_Msk (0x1U << SPI_I2SCLKP_I2SODD_Pos) /*!< 0x00000100 */ +#define SPI_I2SCLKP_I2SODD SPI_I2SCLKP_I2SODD_Msk /*!< Odd factor for I2S division */ +#define SPI_I2SCLKP_I2SMCLKOE_Pos (9U) +#define SPI_I2SCLKP_I2SMCLKOE_Msk (0x1U << SPI_I2SCLKP_I2SMCLKOE_Pos) /*!< 0x00000200 */ +#define SPI_I2SCLKP_I2SMCLKOE SPI_I2SCLKP_I2SMCLKOE_Msk /*!< I2S Master clock output enable */ + +/****************** Bit definition for SPI_MISC1 register *******************/ +#define SPI_MISC1_I2SFPCMCKSEL_Pos (0U) +#define SPI_MISC1_I2SFPCMCKSEL_Msk (0x1U << SPI_MISC1_I2SFPCMCKSEL_Pos) /*!< 0x00000001 */ +#define SPI_MISC1_I2SFPCMCKSEL SPI_MISC1_I2SFPCMCKSEL_Msk /*!< I2S PCM clock edge select */ + +/******************************************************************************/ +/* */ +/* Window watchdog timer (WWDT) */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for WWDT_CTRL register *******************/ +/*!< CNT configuration */ +#define WWDT_CTRL_CNT_Pos (0U) +#define WWDT_CTRL_CNT_Msk (0x7FU << WWDT_CTRL_CNT_Pos) /*!< 0x0000007F */ +#define WWDT_CTRL_CNT WWDT_CTRL_CNT_Msk /*!< CNT[6:0] bits (Down counter) */ +#define WWDT_CTRL_CNT_0 (0x01U << WWDT_CTRL_CNT_Pos) /*!< 0x00000001 */ +#define WWDT_CTRL_CNT_1 (0x02U << WWDT_CTRL_CNT_Pos) /*!< 0x00000002 */ +#define WWDT_CTRL_CNT_2 (0x04U << WWDT_CTRL_CNT_Pos) /*!< 0x00000004 */ +#define WWDT_CTRL_CNT_3 (0x08U << WWDT_CTRL_CNT_Pos) /*!< 0x00000008 */ +#define WWDT_CTRL_CNT_4 (0x10U << WWDT_CTRL_CNT_Pos) /*!< 0x00000010 */ +#define WWDT_CTRL_CNT_5 (0x20U << WWDT_CTRL_CNT_Pos) /*!< 0x00000020 */ +#define WWDT_CTRL_CNT_6 (0x40U << WWDT_CTRL_CNT_Pos) /*!< 0x00000040 */ + +/* Legacy defines */ +#define WWDT_CTRL_CNT0 WWDT_CTRL_CNT_0 +#define WWDT_CTRL_CNT1 WWDT_CTRL_CNT_1 +#define WWDT_CTRL_CNT2 WWDT_CTRL_CNT_2 +#define WWDT_CTRL_CNT3 WWDT_CTRL_CNT_3 +#define WWDT_CTRL_CNT4 WWDT_CTRL_CNT_4 +#define WWDT_CTRL_CNT5 WWDT_CTRL_CNT_5 +#define WWDT_CTRL_CNT6 WWDT_CTRL_CNT_6 + +#define WWDT_CTRL_WWDTEN_Pos (7U) +#define WWDT_CTRL_WWDTEN_Msk (0x1U << WWDT_CTRL_WWDTEN_Pos) /*!< 0x00000080 */ +#define WWDT_CTRL_WWDTEN WWDT_CTRL_WWDTEN_Msk /*!< Window watchdog enable */ + +/******************* Bit definition for WWDT_CFG register *******************/ +/*!< WIN configuration */ +#define WWDT_CFG_WIN_Pos (0U) +#define WWDT_CFG_WIN_Msk (0x7FU << WWDT_CFG_WIN_Pos) /*!< 0x0000007F */ +#define WWDT_CFG_WIN WWDT_CFG_WIN_Msk /*!< WIN[6:0] bits (Window value) */ +#define WWDT_CFG_WIN_0 (0x01U << WWDT_CFG_WIN_Pos) /*!< 0x00000001 */ +#define WWDT_CFG_WIN_1 (0x02U << WWDT_CFG_WIN_Pos) /*!< 0x00000002 */ +#define WWDT_CFG_WIN_2 (0x04U << WWDT_CFG_WIN_Pos) /*!< 0x00000004 */ +#define WWDT_CFG_WIN_3 (0x08U << WWDT_CFG_WIN_Pos) /*!< 0x00000008 */ +#define WWDT_CFG_WIN_4 (0x10U << WWDT_CFG_WIN_Pos) /*!< 0x00000010 */ +#define WWDT_CFG_WIN_5 (0x20U << WWDT_CFG_WIN_Pos) /*!< 0x00000020 */ +#define WWDT_CFG_WIN_6 (0x40U << WWDT_CFG_WIN_Pos) /*!< 0x00000040 */ + +/* Legacy defines */ +#define WWDT_CFG_WIN0 WWDT_CFG_WIN_0 +#define WWDT_CFG_WIN1 WWDT_CFG_WIN_1 +#define WWDT_CFG_WIN2 WWDT_CFG_WIN_2 +#define WWDT_CFG_WIN3 WWDT_CFG_WIN_3 +#define WWDT_CFG_WIN4 WWDT_CFG_WIN_4 +#define WWDT_CFG_WIN5 WWDT_CFG_WIN_5 +#define WWDT_CFG_WIN6 WWDT_CFG_WIN_6 + +/*!< DIV configuration */ +#define WWDT_CFG_DIV_Pos (7U) +#define WWDT_CFG_DIV_Msk (0x3U << WWDT_CFG_DIV_Pos) /*!< 0x00000180 */ +#define WWDT_CFG_DIV WWDT_CFG_DIV_Msk /*!< DIV[1:0] bits (Clock division value) */ +#define WWDT_CFG_DIV_0 (0x1U << WWDT_CFG_DIV_Pos) /*!< 0x00000080 */ +#define WWDT_CFG_DIV_1 (0x2U << WWDT_CFG_DIV_Pos) /*!< 0x00000100 */ + +/* Legacy defines */ +#define WWDT_CFG_DIV0 WWDT_CFG_DIV_0 +#define WWDT_CFG_DIV1 WWDT_CFG_DIV_1 + +#define WWDT_CFG_RLDIEN_Pos (9U) +#define WWDT_CFG_RLDIEN_Msk (0x1U << WWDT_CFG_RLDIEN_Pos) /*!< 0x00000200 */ +#define WWDT_CFG_RLDIEN WWDT_CFG_RLDIEN_Msk /*!< Reload counter interrupt */ + +/******************* Bit definition for WWDT_STS register *******************/ +#define WWDT_STS_RLDF_Pos (0U) +#define WWDT_STS_RLDF_Msk (0x1U << WWDT_STS_RLDF_Pos) /*!< 0x00000001 */ +#define WWDT_STS_RLDF WWDT_STS_RLDF_Msk /*!< Reload counter interrupt flag */ + +/******************************************************************************/ +/* */ +/* Watchdog timer (WDT) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for WDT_CMD register ********************/ +#define WDT_CMD_CMD_Pos (0U) +#define WDT_CMD_CMD_Msk (0xFFFFU << WDT_CMD_CMD_Pos) /*!< 0x0000FFFF */ +#define WDT_CMD_CMD WDT_CMD_CMD_Msk /*!< Command register */ + +/******************* Bit definition for WDT_DIV register ********************/ +/*!< DIV configuration */ +#define WDT_DIV_DIV_Pos (0U) +#define WDT_DIV_DIV_Msk (0x7U << WDT_DIV_DIV_Pos) /*!< 0x00000007 */ +#define WDT_DIV_DIV WDT_DIV_DIV_Msk /*!< DIV[2:0] (Clock division value) */ +#define WDT_DIV_DIV_0 (0x1U << WDT_DIV_DIV_Pos) /*!< 0x00000001 */ +#define WDT_DIV_DIV_1 (0x2U << WDT_DIV_DIV_Pos) /*!< 0x00000002 */ +#define WDT_DIV_DIV_2 (0x4U << WDT_DIV_DIV_Pos) /*!< 0x00000004 */ + +/******************* Bit definition for WDT_RLD register ********************/ +#define WDT_RLD_RLD_Pos (0U) +#define WDT_RLD_RLD_Msk (0xFFFU << WDT_RLD_RLD_Pos) /*!< 0x00000FFF */ +#define WDT_RLD_RLD WDT_RLD_RLD_Msk /*!< Reload value */ + +/******************* Bit definition for WDT_STS register ********************/ +#define WDT_STS_DIVF_Pos (0U) +#define WDT_STS_DIVF_Msk (0x1U << WDT_STS_DIVF_Pos) /*!< 0x00000001 */ +#define WDT_STS_DIVF WDT_STS_DIVF_Msk /*!< Division value update complete flag */ +#define WDT_STS_RLDF_Pos (1U) +#define WDT_STS_RLDF_Msk (0x1U << WDT_STS_RLDF_Pos) /*!< 0x00000002 */ +#define WDT_STS_RLDF WDT_STS_RLDF_Msk /*!< Reload value update complete flag */ +#define WDT_STS_WINF_Pos (2U) +#define WDT_STS_WINF_Msk (0x1U << WDT_STS_WINF_Pos) /*!< 0x00000004 */ +#define WDT_STS_WINF WDT_STS_WINF_Msk /*!< Window value update complete flag */ + +/******************* Bit definition for WDT_WIN register ********************/ +#define WDT_WIN_WIN_Pos (0U) +#define WDT_WIN_WIN_Msk (0xFFFU << WDT_WIN_WIN_Pos) /*!< 0x00000FFF */ +#define WDT_WIN_WIN WDT_WIN_WIN_Msk /*!< Window value */ + +/******************************************************************************/ +/* */ +/* Enhanced real-time clock (ERTC) */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for ERTC_TIME register *******************/ +/*!< SU configuration */ +#define ERTC_TIME_SU_Pos (0U) +#define ERTC_TIME_SU_Msk (0xFU << ERTC_TIME_SU_Pos) /*!< 0x0000000F */ +#define ERTC_TIME_SU ERTC_TIME_SU_Msk /*!< SU[3:0] (Second units) */ +#define ERTC_TIME_SU_0 (0x1U << ERTC_TIME_SU_Pos) /*!< 0x00000001 */ +#define ERTC_TIME_SU_1 (0x2U << ERTC_TIME_SU_Pos) /*!< 0x00000002 */ +#define ERTC_TIME_SU_2 (0x4U << ERTC_TIME_SU_Pos) /*!< 0x00000004 */ +#define ERTC_TIME_SU_3 (0x8U << ERTC_TIME_SU_Pos) /*!< 0x00000008 */ + +/*!< ST configuration */ +#define ERTC_TIME_ST_Pos (4U) +#define ERTC_TIME_ST_Msk (0x7U << ERTC_TIME_ST_Pos) /*!< 0x00000070 */ +#define ERTC_TIME_ST ERTC_TIME_ST_Msk /*!< ST[2:0] (Second tens) */ +#define ERTC_TIME_ST_0 (0x1U << ERTC_TIME_ST_Pos) /*!< 0x00000010 */ +#define ERTC_TIME_ST_1 (0x2U << ERTC_TIME_ST_Pos) /*!< 0x00000020 */ +#define ERTC_TIME_ST_2 (0x4U << ERTC_TIME_ST_Pos) /*!< 0x00000040 */ + +/*!< MU configuration */ +#define ERTC_TIME_MU_Pos (8U) +#define ERTC_TIME_MU_Msk (0xFU << ERTC_TIME_MU_Pos) /*!< 0x00000F00 */ +#define ERTC_TIME_MU ERTC_TIME_MU_Msk /*!< MU[3:0] (Minute units) */ +#define ERTC_TIME_MU_0 (0x1U << ERTC_TIME_MU_Pos) /*!< 0x00000100 */ +#define ERTC_TIME_MU_1 (0x2U << ERTC_TIME_MU_Pos) /*!< 0x00000200 */ +#define ERTC_TIME_MU_2 (0x4U << ERTC_TIME_MU_Pos) /*!< 0x00000400 */ +#define ERTC_TIME_MU_3 (0x8U << ERTC_TIME_MU_Pos) /*!< 0x00000800 */ + +/*!< MT configuration */ +#define ERTC_TIME_MT_Pos (12U) +#define ERTC_TIME_MT_Msk (0x7U << ERTC_TIME_MT_Pos) /*!< 0x00007000 */ +#define ERTC_TIME_MT ERTC_TIME_MT_Msk /*!< MT[2:0] (Minute tens) */ +#define ERTC_TIME_MT_0 (0x1U << ERTC_TIME_MT_Pos) /*!< 0x00001000 */ +#define ERTC_TIME_MT_1 (0x2U << ERTC_TIME_MT_Pos) /*!< 0x00002000 */ +#define ERTC_TIME_MT_2 (0x4U << ERTC_TIME_MT_Pos) /*!< 0x00004000 */ + +/*!< HU configuration */ +#define ERTC_TIME_HU_Pos (16U) +#define ERTC_TIME_HU_Msk (0xFU << ERTC_TIME_HU_Pos) /*!< 0x000F0000 */ +#define ERTC_TIME_HU ERTC_TIME_HU_Msk /*!< HU[3:0] (Hour units) */ +#define ERTC_TIME_HU_0 (0x1U << ERTC_TIME_HU_Pos) /*!< 0x00010000 */ +#define ERTC_TIME_HU_1 (0x2U << ERTC_TIME_HU_Pos) /*!< 0x00020000 */ +#define ERTC_TIME_HU_2 (0x4U << ERTC_TIME_HU_Pos) /*!< 0x00040000 */ +#define ERTC_TIME_HU_3 (0x8U << ERTC_TIME_HU_Pos) /*!< 0x00080000 */ + +/*!< HT configuration */ +#define ERTC_TIME_HT_Pos (20U) +#define ERTC_TIME_HT_Msk (0x3U << ERTC_TIME_HT_Pos) /*!< 0x00300000 */ +#define ERTC_TIME_HT ERTC_TIME_HT_Msk /*!< HT[1:0] (Hour tens) */ +#define ERTC_TIME_HT_0 (0x1U << ERTC_TIME_HT_Pos) /*!< 0x00100000 */ +#define ERTC_TIME_HT_1 (0x2U << ERTC_TIME_HT_Pos) /*!< 0x00200000 */ + +#define ERTC_TIME_AMPM_Pos (22U) +#define ERTC_TIME_AMPM_Msk (0x1U << ERTC_TIME_AMPM_Pos) /*!< 0x00400000 */ +#define ERTC_TIME_AMPM ERTC_TIME_AMPM_Msk /*!< AM/PM */ + +/****************** Bit definition for ERTC_DATE register *******************/ +/*!< DU configuration */ +#define ERTC_DATE_DU_Pos (0U) +#define ERTC_DATE_DU_Msk (0xFU << ERTC_DATE_DU_Pos) /*!< 0x0000000F */ +#define ERTC_DATE_DU ERTC_DATE_DU_Msk /*!< DU[3:0] (Date units) */ +#define ERTC_DATE_DU_0 (0x1U << ERTC_DATE_DU_Pos) /*!< 0x00000001 */ +#define ERTC_DATE_DU_1 (0x2U << ERTC_DATE_DU_Pos) /*!< 0x00000002 */ +#define ERTC_DATE_DU_2 (0x4U << ERTC_DATE_DU_Pos) /*!< 0x00000004 */ +#define ERTC_DATE_DU_3 (0x8U << ERTC_DATE_DU_Pos) /*!< 0x00000008 */ + +/*!< DT configuration */ +#define ERTC_DATE_DT_Pos (4U) +#define ERTC_DATE_DT_Msk (0x3U << ERTC_DATE_DT_Pos) /*!< 0x00300000 */ +#define ERTC_DATE_DT ERTC_DATE_DT_Msk /*!< DT[1:0] (Date tens) */ +#define ERTC_DATE_DT_0 (0x1U << ERTC_DATE_DT_Pos) /*!< 0x00000010 */ +#define ERTC_DATE_DT_1 (0x2U << ERTC_DATE_DT_Pos) /*!< 0x00000020 */ + +/*!< MU configuration */ +#define ERTC_DATE_MU_Pos (8U) +#define ERTC_DATE_MU_Msk (0xFU << ERTC_DATE_MU_Pos) /*!< 0x00000F00 */ +#define ERTC_DATE_MU ERTC_DATE_MU_Msk /*!< MU[3:0] (Month units) */ +#define ERTC_DATE_MU_0 (0x1U << ERTC_DATE_MU_Pos) /*!< 0x00000100 */ +#define ERTC_DATE_MU_1 (0x2U << ERTC_DATE_MU_Pos) /*!< 0x00000200 */ +#define ERTC_DATE_MU_2 (0x4U << ERTC_DATE_MU_Pos) /*!< 0x00000400 */ +#define ERTC_DATE_MU_3 (0x8U << ERTC_DATE_MU_Pos) /*!< 0x00000800 */ + +#define ERTC_DATE_MT_Pos (12U) +#define ERTC_DATE_MT_Msk (0x1U << ERTC_DATE_MT_Pos) /*!< 0x00001000 */ +#define ERTC_DATE_MT ERTC_DATE_MT_Msk /*!< Month tens */ + +/*!< WK configuration */ +#define ERTC_DATE_WK_Pos (13U) +#define ERTC_DATE_WK_Msk (0x7U << ERTC_DATE_WK_Pos) /*!< 0x0000E000 */ +#define ERTC_DATE_WK ERTC_DATE_WK_Msk /*!< WK[2:0] (Week day) */ +#define ERTC_DATE_WK_0 (0x1U << ERTC_DATE_WK_Pos) /*!< 0x00002000 */ +#define ERTC_DATE_WK_1 (0x2U << ERTC_DATE_WK_Pos) /*!< 0x00004000 */ +#define ERTC_DATE_WK_2 (0x4U << ERTC_DATE_WK_Pos) /*!< 0x00008000 */ + +/*!< YU configuration */ +#define ERTC_DATE_YU_Pos (16U) +#define ERTC_DATE_YU_Msk (0xFU << ERTC_DATE_YU_Pos) /*!< 0x000F0000 */ +#define ERTC_DATE_YU ERTC_DATE_YU_Msk /*!< YU[3:0] (Year units) */ +#define ERTC_DATE_YU_0 (0x1U << ERTC_DATE_YU_Pos) /*!< 0x00010000 */ +#define ERTC_DATE_YU_1 (0x2U << ERTC_DATE_YU_Pos) /*!< 0x00020000 */ +#define ERTC_DATE_YU_2 (0x4U << ERTC_DATE_YU_Pos) /*!< 0x00040000 */ +#define ERTC_DATE_YU_3 (0x8U << ERTC_DATE_YU_Pos) /*!< 0x00080000 */ + +/*!< YT configuration */ +#define ERTC_DATE_YT_Pos (20U) +#define ERTC_DATE_YT_Msk (0xFU << ERTC_DATE_YT_Pos) /*!< 0x00F00000 */ +#define ERTC_DATE_YT ERTC_DATE_YT_Msk /*!< YT[3:0] (Year tens) */ +#define ERTC_DATE_YT_0 (0x1U << ERTC_DATE_YT_Pos) /*!< 0x00100000 */ +#define ERTC_DATE_YT_1 (0x2U << ERTC_DATE_YT_Pos) /*!< 0x00200000 */ +#define ERTC_DATE_YT_2 (0x4U << ERTC_DATE_YT_Pos) /*!< 0x00400000 */ +#define ERTC_DATE_YT_3 (0x8U << ERTC_DATE_YT_Pos) /*!< 0x00800000 */ + +/****************** Bit definition for ERTC_CTRL register *******************/ +/*!< WATCLK configuration */ +#define ERTC_CTRL_WATCLK_Pos (0U) +#define ERTC_CTRL_WATCLK_Msk (0x7U << ERTC_CTRL_WATCLK_Pos) /*!< 0x00000007 */ +#define ERTC_CTRL_WATCLK ERTC_CTRL_WATCLK_Msk /*!< WATCLK[2:0] (Wakeup timer clock selection) */ +#define ERTC_CTRL_WATCLK_0 (0x1U << ERTC_CTRL_WATCLK_Pos) /*!< 0x00000001 */ +#define ERTC_CTRL_WATCLK_1 (0x2U << ERTC_CTRL_WATCLK_Pos) /*!< 0x00000002 */ +#define ERTC_CTRL_WATCLK_2 (0x4U << ERTC_CTRL_WATCLK_Pos) /*!< 0x00000004 */ + +#define ERTC_CTRL_TSEDG_Pos (3U) +#define ERTC_CTRL_TSEDG_Msk (0x1U << ERTC_CTRL_TSEDG_Pos) /*!< 0x00000008 */ +#define ERTC_CTRL_TSEDG ERTC_CTRL_TSEDG_Msk /*!< Timestamp trigger edge */ +#define ERTC_CTRL_RCDEN_Pos (4U) +#define ERTC_CTRL_RCDEN_Msk (0x1U << ERTC_CTRL_RCDEN_Pos) /*!< 0x00000010 */ +#define ERTC_CTRL_RCDEN ERTC_CTRL_RCDEN_Msk /*!< Reference clock detection enable */ +#define ERTC_CTRL_DREN_Pos (5U) +#define ERTC_CTRL_DREN_Msk (0x1U << ERTC_CTRL_DREN_Pos) /*!< 0x00000020 */ +#define ERTC_CTRL_DREN ERTC_CTRL_DREN_Msk /*!< Date/time register direct read enable */ +#define ERTC_CTRL_HM_Pos (6U) +#define ERTC_CTRL_HM_Msk (0x1U << ERTC_CTRL_HM_Pos) /*!< 0x00000040 */ +#define ERTC_CTRL_HM ERTC_CTRL_HM_Msk /*!< Hour mode */ +#define ERTC_CTRL_ALAEN_Pos (8U) +#define ERTC_CTRL_ALAEN_Msk (0x1U << ERTC_CTRL_ALAEN_Pos) /*!< 0x00000100 */ +#define ERTC_CTRL_ALAEN ERTC_CTRL_ALAEN_Msk /*!< Alarm A enable */ +#define ERTC_CTRL_ALBEN_Pos (9U) +#define ERTC_CTRL_ALBEN_Msk (0x1U << ERTC_CTRL_ALBEN_Pos) /*!< 0x00000200 */ +#define ERTC_CTRL_ALBEN ERTC_CTRL_ALBEN_Msk /*!< Alarm B enable */ +#define ERTC_CTRL_WATEN_Pos (10U) +#define ERTC_CTRL_WATEN_Msk (0x1U << ERTC_CTRL_WATEN_Pos) /*!< 0x00000400 */ +#define ERTC_CTRL_WATEN ERTC_CTRL_WATEN_Msk /*!< Wakeup timer enable */ +#define ERTC_CTRL_TSEN_Pos (11U) +#define ERTC_CTRL_TSEN_Msk (0x1U << ERTC_CTRL_TSEN_Pos) /*!< 0x00000800 */ +#define ERTC_CTRL_TSEN ERTC_CTRL_TSEN_Msk /*!< Timestamp enable */ +#define ERTC_CTRL_ALAIEN_Pos (12U) +#define ERTC_CTRL_ALAIEN_Msk (0x1U << ERTC_CTRL_ALAIEN_Pos) /*!< 0x00001000 */ +#define ERTC_CTRL_ALAIEN ERTC_CTRL_ALAIEN_Msk /*!< Alarm A interrupt enable */ +#define ERTC_CTRL_ALBIEN_Pos (13U) +#define ERTC_CTRL_ALBIEN_Msk (0x1U << ERTC_CTRL_ALBIEN_Pos) /*!< 0x00002000 */ +#define ERTC_CTRL_ALBIEN ERTC_CTRL_ALBIEN_Msk /*!< Alarm B interrupt enable */ +#define ERTC_CTRL_WATIEN_Pos (14U) +#define ERTC_CTRL_WATIEN_Msk (0x1U << ERTC_CTRL_WATIEN_Pos) /*!< 0x00004000 */ +#define ERTC_CTRL_WATIEN ERTC_CTRL_WATIEN_Msk /*!< Wakeup timer interrupt enable */ +#define ERTC_CTRL_TSIEN_Pos (15U) +#define ERTC_CTRL_TSIEN_Msk (0x1U << ERTC_CTRL_TSIEN_Pos) /*!< 0x000008000 */ +#define ERTC_CTRL_TSIEN ERTC_CTRL_TSIEN_Msk /*!< Timestamp interrupt enable */ +#define ERTC_CTRL_ADD1H_Pos (16U) +#define ERTC_CTRL_ADD1H_Msk (0x1U << ERTC_CTRL_ADD1H_Pos) /*!< 0x00010000 */ +#define ERTC_CTRL_ADD1H ERTC_CTRL_ADD1H_Msk /*!< Add 1 hour */ +#define ERTC_CTRL_DEC1H_Pos (17U) +#define ERTC_CTRL_DEC1H_Msk (0x1U << ERTC_CTRL_DEC1H_Pos) /*!< 0x00020000 */ +#define ERTC_CTRL_DEC1H ERTC_CTRL_DEC1H_Msk /*!< Decrease 1 hour */ +#define ERTC_CTRL_BPR_Pos (18U) +#define ERTC_CTRL_BPR_Msk (0x1U << ERTC_CTRL_BPR_Pos) /*!< 0x00040000 */ +#define ERTC_CTRL_BPR ERTC_CTRL_BPR_Msk /*!< Battery powered domain data register */ +#define ERTC_CTRL_CALOSEL_Pos (19U) +#define ERTC_CTRL_CALOSEL_Msk (0x1U << ERTC_CTRL_CALOSEL_Pos) /*!< 0x00080000 */ +#define ERTC_CTRL_CALOSEL ERTC_CTRL_CALOSEL_Msk /*!< Calibration output selection */ +#define ERTC_CTRL_OUTP_Pos (20U) +#define ERTC_CTRL_OUTP_Msk (0x1U << ERTC_CTRL_OUTP_Pos) /*!< 0x00100000 */ +#define ERTC_CTRL_OUTP ERTC_CTRL_OUTP_Msk /*!< Output polarity */ + +/*!< OUTSEL configuration */ +#define ERTC_CTRL_OUTSEL_Pos (21U) +#define ERTC_CTRL_OUTSEL_Msk (0x3U << ERTC_CTRL_OUTSEL_Pos) /*!< 0x00600000 */ +#define ERTC_CTRL_OUTSEL ERTC_CTRL_OUTSEL_Msk /*!< OUTSEL[1:0] (Output source selection) */ +#define ERTC_CTRL_OUTSEL_0 (0x1U << ERTC_CTRL_OUTSEL_Pos) /*!< 0x00200000 */ +#define ERTC_CTRL_OUTSEL_1 (0x2U << ERTC_CTRL_OUTSEL_Pos) /*!< 0x00400000 */ + +#define ERTC_CTRL_CALOEN_Pos (23U) +#define ERTC_CTRL_CALOEN_Msk (0x1U << ERTC_CTRL_CALOEN_Pos) /*!< 0x00800000 */ +#define ERTC_CTRL_CALOEN ERTC_CTRL_CALOEN_Msk /*!< Calibration output enable */ + +/******************* Bit definition for ERTC_STS register *******************/ +#define ERTC_STS_ALAWF_Pos (0U) +#define ERTC_STS_ALAWF_Msk (0x1U << ERTC_STS_ALAWF_Pos) /*!< 0x00000001 */ +#define ERTC_STS_ALAWF ERTC_STS_ALAWF_Msk /*!< Alarm A register allows write flag */ +#define ERTC_STS_ALBWF_Pos (1U) +#define ERTC_STS_ALBWF_Msk (0x1U << ERTC_STS_ALBWF_Pos) /*!< 0x00000002 */ +#define ERTC_STS_ALBWF ERTC_STS_ALBWF_Msk /*!< Alarm B register allows write flag */ +#define ERTC_STS_WATWF_Pos (2U) +#define ERTC_STS_WATWF_Msk (0x1U << ERTC_STS_WATWF_Pos) /*!< 0x00000004 */ +#define ERTC_STS_WATWF ERTC_STS_WATWF_Msk /*!< Wakeup timer register allows write flag */ +#define ERTC_STS_TADJF_Pos (3U) +#define ERTC_STS_TADJF_Msk (0x1U << ERTC_STS_TADJF_Pos) /*!< 0x00000008 */ +#define ERTC_STS_TADJF ERTC_STS_TADJF_Msk /*!< Time adjustment flag */ +#define ERTC_STS_INITF_Pos (4U) +#define ERTC_STS_INITF_Msk (0x1U << ERTC_STS_INITF_Pos) /*!< 0x00000010 */ +#define ERTC_STS_INITF ERTC_STS_INITF_Msk /*!< Calendar initialization flag */ +#define ERTC_STS_UPDF_Pos (5U) +#define ERTC_STS_UPDF_Msk (0x1U << ERTC_STS_UPDF_Pos) /*!< 0x00000020 */ +#define ERTC_STS_UPDF ERTC_STS_UPDF_Msk /*!< Calendar update flag */ +#define ERTC_STS_IMF_Pos (6U) +#define ERTC_STS_IMF_Msk (0x1U << ERTC_STS_IMF_Pos) /*!< 0x00000040 */ +#define ERTC_STS_IMF ERTC_STS_IMF_Msk /*!< Enter initialization mode flag */ +#define ERTC_STS_IMEN_Pos (7U) +#define ERTC_STS_IMEN_Msk (0x1U << ERTC_STS_IMEN_Pos) /*!< 0x00000080 */ +#define ERTC_STS_IMEN ERTC_STS_IMEN_Msk /*!< Initialization mode enable */ +#define ERTC_STS_ALAF_Pos (8U) +#define ERTC_STS_ALAF_Msk (0x1U << ERTC_STS_ALAF_Pos) /*!< 0x00000100 */ +#define ERTC_STS_ALAF ERTC_STS_ALAF_Msk /*!< Alarm clock A flag */ +#define ERTC_STS_ALBF_Pos (9U) +#define ERTC_STS_ALBF_Msk (0x1U << ERTC_STS_ALBF_Pos) /*!< 0x00000200 */ +#define ERTC_STS_ALBF ERTC_STS_ALBF_Msk /*!< Alarm clock B flag */ +#define ERTC_STS_WATF_Pos (10U) +#define ERTC_STS_WATF_Msk (0x1U << ERTC_STS_WATF_Pos) /*!< 0x00000400 */ +#define ERTC_STS_WATF ERTC_STS_WATF_Msk /*!< Wakeup timer flag */ +#define ERTC_STS_TSF_Pos (11U) +#define ERTC_STS_TSF_Msk (0x1U << ERTC_STS_TSF_Pos) /*!< 0x00000800 */ +#define ERTC_STS_TSF ERTC_STS_TSF_Msk /*!< Timestamp flag */ +#define ERTC_STS_TSOF_Pos (12U) +#define ERTC_STS_TSOF_Msk (0x1U << ERTC_STS_TSOF_Pos) /*!< 0x00001000 */ +#define ERTC_STS_TSOF ERTC_STS_TSOF_Msk /*!< Timestamp overflow flag */ +#define ERTC_STS_TP1F_Pos (13U) +#define ERTC_STS_TP1F_Msk (0x1U << ERTC_STS_TP1F_Pos) /*!< 0x00002000 */ +#define ERTC_STS_TP1F ERTC_STS_TP1F_Msk /*!< Tamper detection 1 flag */ +#define ERTC_STS_TP2F_Pos (14U) +#define ERTC_STS_TP2F_Msk (0x1U << ERTC_STS_TP2F_Pos) /*!< 0x00004000 */ +#define ERTC_STS_TP2F ERTC_STS_TP2F_Msk /*!< Tamper detection 2 flag */ +#define ERTC_STS_CALUPDF_Pos (16U) +#define ERTC_STS_CALUPDF_Msk (0x1U << ERTC_STS_CALUPDF_Pos) /*!< 0x00010000 */ +#define ERTC_STS_CALUPDF ERTC_STS_CALUPDF_Msk /*!< Calibration value update complete flag */ + +/******************* Bit definition for ERTC_DIV register *******************/ +#define ERTC_DIV_DIVB_Pos (0U) +#define ERTC_DIV_DIVB_Msk (0x7FFFU << ERTC_DIV_DIVB_Pos) /*!< 0x00007FFF */ +#define ERTC_DIV_DIVB ERTC_DIV_DIVB_Msk /*!< Divider B */ +#define ERTC_DIV_DIVA_Pos (16U) +#define ERTC_DIV_DIVA_Msk (0x7FU << ERTC_DIV_DIVA_Pos) /*!< 0x007F0000 */ +#define ERTC_DIV_DIVA ERTC_DIV_DIVA_Msk /*!< Divider A */ + +/******************* Bit definition for ERTC_WAT register *******************/ +#define ERTC_WAT_VAL_Pos (0U) +#define ERTC_WAT_VAL_Msk (0xFFFFU << ERTC_WAT_VAL_Pos) /*!< 0x0000FFFF */ +#define ERTC_WAT_VAL ERTC_WAT_VAL_Msk /*!< Wakeup timer reload value */ + +/******************* Bit definition for ERTC_ALA register *******************/ +/*!< SU configuration */ +#define ERTC_ALA_SU_Pos (0U) +#define ERTC_ALA_SU_Msk (0xFU << ERTC_ALA_SU_Pos) /*!< 0x0000000F */ +#define ERTC_ALA_SU ERTC_ALA_SU_Msk /*!< SU[3:0] (Second units) */ +#define ERTC_ALA_SU_0 (0x1U << ERTC_ALA_SU_Pos) /*!< 0x00000001 */ +#define ERTC_ALA_SU_1 (0x2U << ERTC_ALA_SU_Pos) /*!< 0x00000002 */ +#define ERTC_ALA_SU_2 (0x4U << ERTC_ALA_SU_Pos) /*!< 0x00000004 */ +#define ERTC_ALA_SU_3 (0x8U << ERTC_ALA_SU_Pos) /*!< 0x00000008 */ + +/*!< ST configuration */ +#define ERTC_ALA_ST_Pos (4U) +#define ERTC_ALA_ST_Msk (0x7U << ERTC_ALA_ST_Pos) /*!< 0x00000070 */ +#define ERTC_ALA_ST ERTC_ALA_ST_Msk /*!< ST[2:0] (Second tens) */ +#define ERTC_ALA_ST_0 (0x1U << ERTC_ALA_ST_Pos) /*!< 0x00000010 */ +#define ERTC_ALA_ST_1 (0x2U << ERTC_ALA_ST_Pos) /*!< 0x00000020 */ +#define ERTC_ALA_ST_2 (0x4U << ERTC_ALA_ST_Pos) /*!< 0x00000040 */ + +#define ERTC_ALA_MASK1_Pos (7U) +#define ERTC_ALA_MASK1_Msk (0x1U << ERTC_ALA_MASK1_Pos) /*!< 0x00000080 */ +#define ERTC_ALA_MASK1 ERTC_ALA_MASK1_Msk /*!< Second mask */ + +/*!< MU configuration */ +#define ERTC_ALA_MU_Pos (8U) +#define ERTC_ALA_MU_Msk (0xFU << ERTC_ALA_MU_Pos) /*!< 0x00000F00 */ +#define ERTC_ALA_MU ERTC_ALA_MU_Msk /*!< MU[3:0] (Minute units) */ +#define ERTC_ALA_MU_0 (0x1U << ERTC_ALA_MU_Pos) /*!< 0x00000100 */ +#define ERTC_ALA_MU_1 (0x2U << ERTC_ALA_MU_Pos) /*!< 0x00000200 */ +#define ERTC_ALA_MU_2 (0x4U << ERTC_ALA_MU_Pos) /*!< 0x00000400 */ +#define ERTC_ALA_MU_3 (0x8U << ERTC_ALA_MU_Pos) /*!< 0x00000800 */ + +/*!< MT configuration */ +#define ERTC_ALA_MT_Pos (12U) +#define ERTC_ALA_MT_Msk (0x7U << ERTC_ALA_MT_Pos) /*!< 0x00007000 */ +#define ERTC_ALA_MT ERTC_ALA_MT_Msk /*!< MT[2:0] (Minute tens) */ +#define ERTC_ALA_MT_0 (0x1U << ERTC_ALA_MT_Pos) /*!< 0x00001000 */ +#define ERTC_ALA_MT_1 (0x2U << ERTC_ALA_MT_Pos) /*!< 0x00002000 */ +#define ERTC_ALA_MT_2 (0x4U << ERTC_ALA_MT_Pos) /*!< 0x00004000 */ + +#define ERTC_ALA_MASK2_Pos (15U) +#define ERTC_ALA_MASK2_Msk (0x1U << ERTC_ALA_MASK2_Pos) /*!< 0x00008000 */ +#define ERTC_ALA_MASK2 ERTC_ALA_MASK2_Msk /*!< Minute mask */ + +/*!< HU configuration */ +#define ERTC_ALA_HU_Pos (16U) +#define ERTC_ALA_HU_Msk (0xFU << ERTC_ALA_HU_Pos) /*!< 0x000F0000 */ +#define ERTC_ALA_HU ERTC_ALA_HU_Msk /*!< HU[3:0] (Hour units) */ +#define ERTC_ALA_HU_0 (0x1U << ERTC_ALA_HU_Pos) /*!< 0x00010000 */ +#define ERTC_ALA_HU_1 (0x2U << ERTC_ALA_HU_Pos) /*!< 0x00020000 */ +#define ERTC_ALA_HU_2 (0x4U << ERTC_ALA_HU_Pos) /*!< 0x00040000 */ +#define ERTC_ALA_HU_3 (0x8U << ERTC_ALA_HU_Pos) /*!< 0x00080000 */ + +/*!< HT configuration */ +#define ERTC_ALA_HT_Pos (20U) +#define ERTC_ALA_HT_Msk (0x3U << ERTC_ALA_HT_Pos) /*!< 0x00300000 */ +#define ERTC_ALA_HT ERTC_ALA_HT_Msk /*!< HT[1:0] (Hour tens) */ +#define ERTC_ALA_HT_0 (0x1U << ERTC_ALA_HT_Pos) /*!< 0x00100000 */ +#define ERTC_ALA_HT_1 (0x2U << ERTC_ALA_HT_Pos) /*!< 0x00200000 */ + +#define ERTC_ALA_AMPM_Pos (22U) +#define ERTC_ALA_AMPM_Msk (0x1U << ERTC_ALA_AMPM_Pos) /*!< 0x00400000 */ +#define ERTC_ALA_AMPM ERTC_ALA_AMPM_Msk /*!< AM/PM */ +#define ERTC_ALA_MASK3_Pos (23U) +#define ERTC_ALA_MASK3_Msk (0x1U << ERTC_ALA_MASK3_Pos) /*!< 0x00800000 */ +#define ERTC_ALA_MASK3 ERTC_ALA_MASK3_Msk /*!< Hour mask */ + +/*!< DU configuration */ +#define ERTC_ALA_DU_Pos (24U) +#define ERTC_ALA_DU_Msk (0xFU << ERTC_ALA_DU_Pos) /*!< 0x0F000000 */ +#define ERTC_ALA_DU ERTC_ALA_DU_Msk /*!< DU[3:0] (Date/week day units) */ +#define ERTC_ALA_DU_0 (0x1U << ERTC_ALA_DU_Pos) /*!< 0x01000000 */ +#define ERTC_ALA_DU_1 (0x2U << ERTC_ALA_DU_Pos) /*!< 0x02000000 */ +#define ERTC_ALA_DU_2 (0x4U << ERTC_ALA_DU_Pos) /*!< 0x04000000 */ +#define ERTC_ALA_DU_3 (0x8U << ERTC_ALA_DU_Pos) /*!< 0x08000000 */ + +/*!< DT configuration */ +#define ERTC_ALA_DT_Pos (28U) +#define ERTC_ALA_DT_Msk (0x3U << ERTC_ALA_DT_Pos) /*!< 0x30000000 */ +#define ERTC_ALA_DT ERTC_ALA_DT_Msk /*!< DT[1:0] (Date/week day tens) */ +#define ERTC_ALA_DT_0 (0x1U << ERTC_ALA_DT_Pos) /*!< 0x10000000 */ +#define ERTC_ALA_DT_1 (0x2U << ERTC_ALA_DT_Pos) /*!< 0x20000000 */ + +#define ERTC_ALA_WKSEL_Pos (30U) +#define ERTC_ALA_WKSEL_Msk (0x1U << ERTC_ALA_WKSEL_Pos) /*!< 0x40000000 */ +#define ERTC_ALA_WKSEL ERTC_ALA_WKSEL_Msk /*!< Date/week day select */ +#define ERTC_ALA_MASK4_Pos (31U) +#define ERTC_ALA_MASK4_Msk (0x1U << ERTC_ALA_MASK4_Pos) /*!< 0x80000000 */ +#define ERTC_ALA_MASK4 ERTC_ALA_MASK4_Msk /*!< Date/week day mask */ + +/******************* Bit definition for ERTC_ALB register *******************/ +/*!< SU configuration */ +#define ERTC_ALB_SU_Pos (0U) +#define ERTC_ALB_SU_Msk (0xFU << ERTC_ALB_SU_Pos) /*!< 0x0000000F */ +#define ERTC_ALB_SU ERTC_ALB_SU_Msk /*!< SU[3:0] (Second units) */ +#define ERTC_ALB_SU_0 (0x1U << ERTC_ALB_SU_Pos) /*!< 0x00000001 */ +#define ERTC_ALB_SU_1 (0x2U << ERTC_ALB_SU_Pos) /*!< 0x00000002 */ +#define ERTC_ALB_SU_2 (0x4U << ERTC_ALB_SU_Pos) /*!< 0x00000004 */ +#define ERTC_ALB_SU_3 (0x8U << ERTC_ALB_SU_Pos) /*!< 0x00000008 */ + +/*!< ST configuration */ +#define ERTC_ALB_ST_Pos (4U) +#define ERTC_ALB_ST_Msk (0x7U << ERTC_ALB_ST_Pos) /*!< 0x00000070 */ +#define ERTC_ALB_ST ERTC_ALB_ST_Msk /*!< ST[2:0] (Second tens) */ +#define ERTC_ALB_ST_0 (0x1U << ERTC_ALB_ST_Pos) /*!< 0x00000010 */ +#define ERTC_ALB_ST_1 (0x2U << ERTC_ALB_ST_Pos) /*!< 0x00000020 */ +#define ERTC_ALB_ST_2 (0x4U << ERTC_ALB_ST_Pos) /*!< 0x00000040 */ + +#define ERTC_ALB_MASK1_Pos (7U) +#define ERTC_ALB_MASK1_Msk (0x1U << ERTC_ALB_MASK1_Pos) /*!< 0x00000080 */ +#define ERTC_ALB_MASK1 ERTC_ALB_MASK1_Msk /*!< Second mask */ + +/*!< MU configuration */ +#define ERTC_ALB_MU_Pos (8U) +#define ERTC_ALB_MU_Msk (0xFU << ERTC_ALB_MU_Pos) /*!< 0x00000F00 */ +#define ERTC_ALB_MU ERTC_ALB_MU_Msk /*!< MU[3:0] (Minute units) */ +#define ERTC_ALB_MU_0 (0x1U << ERTC_ALB_MU_Pos) /*!< 0x00000100 */ +#define ERTC_ALB_MU_1 (0x2U << ERTC_ALB_MU_Pos) /*!< 0x00000200 */ +#define ERTC_ALB_MU_2 (0x4U << ERTC_ALB_MU_Pos) /*!< 0x00000400 */ +#define ERTC_ALB_MU_3 (0x8U << ERTC_ALB_MU_Pos) /*!< 0x00000800 */ + +/*!< MT configuration */ +#define ERTC_ALB_MT_Pos (12U) +#define ERTC_ALB_MT_Msk (0x7U << ERTC_ALB_MT_Pos) /*!< 0x00007000 */ +#define ERTC_ALB_MT ERTC_ALB_MT_Msk /*!< MT[2:0] (Minute tens) */ +#define ERTC_ALB_MT_0 (0x1U << ERTC_ALB_MT_Pos) /*!< 0x00001000 */ +#define ERTC_ALB_MT_1 (0x2U << ERTC_ALB_MT_Pos) /*!< 0x00002000 */ +#define ERTC_ALB_MT_2 (0x4U << ERTC_ALB_MT_Pos) /*!< 0x00004000 */ + +#define ERTC_ALB_MASK2_Pos (15U) +#define ERTC_ALB_MASK2_Msk (0x1U << ERTC_ALB_MASK2_Pos) /*!< 0x00008000 */ +#define ERTC_ALB_MASK2 ERTC_ALB_MASK2_Msk /*!< Minute mask */ + +/*!< HU configuration */ +#define ERTC_ALB_HU_Pos (16U) +#define ERTC_ALB_HU_Msk (0xFU << ERTC_ALB_HU_Pos) /*!< 0x000F0000 */ +#define ERTC_ALB_HU ERTC_ALB_HU_Msk /*!< HU[3:0] (Hour units) */ +#define ERTC_ALB_HU_0 (0x1U << ERTC_ALB_HU_Pos) /*!< 0x00010000 */ +#define ERTC_ALB_HU_1 (0x2U << ERTC_ALB_HU_Pos) /*!< 0x00020000 */ +#define ERTC_ALB_HU_2 (0x4U << ERTC_ALB_HU_Pos) /*!< 0x00040000 */ +#define ERTC_ALB_HU_3 (0x8U << ERTC_ALB_HU_Pos) /*!< 0x00080000 */ + +/*!< HT configuration */ +#define ERTC_ALB_HT_Pos (20U) +#define ERTC_ALB_HT_Msk (0x3U << ERTC_ALB_HT_Pos) /*!< 0x00300000 */ +#define ERTC_ALB_HT ERTC_ALB_HT_Msk /*!< HT[1:0] (Hour tens) */ +#define ERTC_ALB_HT_0 (0x1U << ERTC_ALB_HT_Pos) /*!< 0x00100000 */ +#define ERTC_ALB_HT_1 (0x2U << ERTC_ALB_HT_Pos) /*!< 0x00200000 */ + +#define ERTC_ALB_AMPM_Pos (22U) +#define ERTC_ALB_AMPM_Msk (0x1U << ERTC_ALB_AMPM_Pos) /*!< 0x00400000 */ +#define ERTC_ALB_AMPM ERTC_ALB_AMPM_Msk /*!< AM/PM */ +#define ERTC_ALB_MASK3_Pos (23U) +#define ERTC_ALB_MASK3_Msk (0x1U << ERTC_ALB_MASK3_Pos) /*!< 0x00800000 */ +#define ERTC_ALB_MASK3 ERTC_ALB_MASK3_Msk /*!< Hour mask */ + +/*!< DU configuration */ +#define ERTC_ALB_DU_Pos (24U) +#define ERTC_ALB_DU_Msk (0xFU << ERTC_ALB_DU_Pos) /*!< 0x0F000000 */ +#define ERTC_ALB_DU ERTC_ALB_DU_Msk /*!< DU[3:0] (Date/week day units) */ +#define ERTC_ALB_DU_0 (0x1U << ERTC_ALB_DU_Pos) /*!< 0x01000000 */ +#define ERTC_ALB_DU_1 (0x2U << ERTC_ALB_DU_Pos) /*!< 0x02000000 */ +#define ERTC_ALB_DU_2 (0x4U << ERTC_ALB_DU_Pos) /*!< 0x04000000 */ +#define ERTC_ALB_DU_3 (0x8U << ERTC_ALB_DU_Pos) /*!< 0x08000000 */ + +/*!< DT configuration */ +#define ERTC_ALB_DT_Pos (28U) +#define ERTC_ALB_DT_Msk (0x3U << ERTC_ALB_DT_Pos) /*!< 0x30000000 */ +#define ERTC_ALB_DT ERTC_ALB_DT_Msk /*!< DT[1:0] (Date/week day tens) */ +#define ERTC_ALB_DT_0 (0x1U << ERTC_ALB_DT_Pos) /*!< 0x10000000 */ +#define ERTC_ALB_DT_1 (0x2U << ERTC_ALB_DT_Pos) /*!< 0x20000000 */ + +#define ERTC_ALB_WKSEL_Pos (30U) +#define ERTC_ALB_WKSEL_Msk (0x1U << ERTC_ALB_WKSEL_Pos) /*!< 0x40000000 */ +#define ERTC_ALB_WKSEL ERTC_ALB_WKSEL_Msk /*!< Date/week day select */ +#define ERTC_ALB_MASK4_Pos (31U) +#define ERTC_ALB_MASK4_Msk (0x1U << ERTC_ALB_MASK4_Pos) /*!< 0x80000000 */ +#define ERTC_ALB_MASK4 ERTC_ALB_MASK4_Msk /*!< Date/week day mask */ + +/******************* Bit definition for ERTC_WP register ********************/ +#define ERTC_WP_CMD_Pos (0U) +#define ERTC_WP_CMD_Msk (0xFFU << ERTC_WP_CMD_Pos) /*!< 0x000000FF */ +#define ERTC_WP_CMD ERTC_WP_CMD_Msk /*!< Command register */ + +/******************* Bit definition for ERTC_SBS register *******************/ +#define ERTC_SBS_SBS_Pos (0U) +#define ERTC_SBS_SBS_Msk (0xFFFFU << ERTC_SBS_SBS_Pos) /*!< 0x0000FFFF */ +#define ERTC_SBS_SBS ERTC_SBS_SBS_Msk /*!< Sub-second value */ + +/****************** Bit definition for ERTC_TADJ register *******************/ +#define ERTC_TADJ_DECSBS_Pos (0U) +#define ERTC_TADJ_DECSBS_Msk (0x7FFFU << ERTC_TADJ_DECSBS_Pos) /*!< 0x00007FFF */ +#define ERTC_TADJ_DECSBS ERTC_TADJ_DECSBS_Msk /*!< Decrease sub-second value */ +#define ERTC_TADJ_ADD1S_Pos (31U) +#define ERTC_TADJ_ADD1S_Msk (0x1U << ERTC_TADJ_ADD1S_Pos) /*!< 0x80000000 */ +#define ERTC_TADJ_ADD1S ERTC_TADJ_ADD1S_Msk /*!< Add 1 second */ + +/****************** Bit definition for ERTC_TSTM register *******************/ +/*!< SU configuration */ +#define ERTC_TSTM_SU_Pos (0U) +#define ERTC_TSTM_SU_Msk (0xFU << ERTC_TSTM_SU_Pos) /*!< 0x0000000F */ +#define ERTC_TSTM_SU ERTC_TSTM_SU_Msk /*!< SU[3:0] (Second units) */ +#define ERTC_TSTM_SU_0 (0x1U << ERTC_TSTM_SU_Pos) /*!< 0x00000001 */ +#define ERTC_TSTM_SU_1 (0x2U << ERTC_TSTM_SU_Pos) /*!< 0x00000002 */ +#define ERTC_TSTM_SU_2 (0x4U << ERTC_TSTM_SU_Pos) /*!< 0x00000004 */ +#define ERTC_TSTM_SU_3 (0x8U << ERTC_TSTM_SU_Pos) /*!< 0x00000008 */ + +/*!< ST configuration */ +#define ERTC_TSTM_ST_Pos (4U) +#define ERTC_TSTM_ST_Msk (0x7U << ERTC_TSTM_ST_Pos) /*!< 0x00000070 */ +#define ERTC_TSTM_ST ERTC_TSTM_ST_Msk /*!< ST[2:0] (Second tens) */ +#define ERTC_TSTM_ST_0 (0x1U << ERTC_TSTM_ST_Pos) /*!< 0x00000010 */ +#define ERTC_TSTM_ST_1 (0x2U << ERTC_TSTM_ST_Pos) /*!< 0x00000020 */ +#define ERTC_TSTM_ST_2 (0x4U << ERTC_TSTM_ST_Pos) /*!< 0x00000040 */ + +/*!< MU configuration */ +#define ERTC_TSTM_MU_Pos (8U) +#define ERTC_TSTM_MU_Msk (0xFU << ERTC_TSTM_MU_Pos) /*!< 0x00000F00 */ +#define ERTC_TSTM_MU ERTC_TSTM_MU_Msk /*!< MU[3:0] (Minute units) */ +#define ERTC_TSTM_MU_0 (0x1U << ERTC_TSTM_MU_Pos) /*!< 0x00000100 */ +#define ERTC_TSTM_MU_1 (0x2U << ERTC_TSTM_MU_Pos) /*!< 0x00000200 */ +#define ERTC_TSTM_MU_2 (0x4U << ERTC_TSTM_MU_Pos) /*!< 0x00000400 */ +#define ERTC_TSTM_MU_3 (0x8U << ERTC_TSTM_MU_Pos) /*!< 0x00000800 */ + +/*!< MT configuration */ +#define ERTC_TSTM_MT_Pos (12U) +#define ERTC_TSTM_MT_Msk (0x7U << ERTC_TSTM_MT_Pos) /*!< 0x00007000 */ +#define ERTC_TSTM_MT ERTC_TSTM_MT_Msk /*!< MT[2:0] (Minute tens) */ +#define ERTC_TSTM_MT_0 (0x1U << ERTC_TSTM_MT_Pos) /*!< 0x00001000 */ +#define ERTC_TSTM_MT_1 (0x2U << ERTC_TSTM_MT_Pos) /*!< 0x00002000 */ +#define ERTC_TSTM_MT_2 (0x4U << ERTC_TSTM_MT_Pos) /*!< 0x00004000 */ + +/*!< HU configuration */ +#define ERTC_TSTM_HU_Pos (16U) +#define ERTC_TSTM_HU_Msk (0xFU << ERTC_TSTM_HU_Pos) /*!< 0x000F0000 */ +#define ERTC_TSTM_HU ERTC_TSTM_HU_Msk /*!< HU[3:0] (Hour units) */ +#define ERTC_TSTM_HU_0 (0x1U << ERTC_TSTM_HU_Pos) /*!< 0x00010000 */ +#define ERTC_TSTM_HU_1 (0x2U << ERTC_TSTM_HU_Pos) /*!< 0x00020000 */ +#define ERTC_TSTM_HU_2 (0x4U << ERTC_TSTM_HU_Pos) /*!< 0x00040000 */ +#define ERTC_TSTM_HU_3 (0x8U << ERTC_TSTM_HU_Pos) /*!< 0x00080000 */ + +/*!< HT configuration */ +#define ERTC_TSTM_HT_Pos (20U) +#define ERTC_TSTM_HT_Msk (0x3U << ERTC_TSTM_HT_Pos) /*!< 0x00300000 */ +#define ERTC_TSTM_HT ERTC_TSTM_HT_Msk /*!< HT[1:0] (Hour tens) */ +#define ERTC_TSTM_HT_0 (0x1U << ERTC_TSTM_HT_Pos) /*!< 0x00100000 */ +#define ERTC_TSTM_HT_1 (0x2U << ERTC_TSTM_HT_Pos) /*!< 0x00200000 */ + +#define ERTC_TSTM_AMPM_Pos (22U) +#define ERTC_TSTM_AMPM_Msk (0x1U << ERTC_TSTM_AMPM_Pos) /*!< 0x00400000 */ +#define ERTC_TSTM_AMPM ERTC_TSTM_AMPM_Msk /*!< AM/PM */ + +/****************** Bit definition for ERTC_TSDT register *******************/ +/*!< DU configuration */ +#define ERTC_TSDT_DU_Pos (0U) +#define ERTC_TSDT_DU_Msk (0xFU << ERTC_TSDT_DU_Pos) /*!< 0x0000000F */ +#define ERTC_TSDT_DU ERTC_TSDT_DU_Msk /*!< DU[3:0] (Date units) */ +#define ERTC_TSDT_DU_0 (0x1U << ERTC_TSDT_DU_Pos) /*!< 0x00000001 */ +#define ERTC_TSDT_DU_1 (0x2U << ERTC_TSDT_DU_Pos) /*!< 0x00000002 */ +#define ERTC_TSDT_DU_2 (0x4U << ERTC_TSDT_DU_Pos) /*!< 0x00000004 */ +#define ERTC_TSDT_DU_3 (0x8U << ERTC_TSDT_DU_Pos) /*!< 0x00000008 */ + +/*!< DT configuration */ +#define ERTC_TSDT_DT_Pos (4U) +#define ERTC_TSDT_DT_Msk (0x3U << ERTC_TSDT_DT_Pos) /*!< 0x00000030 */ +#define ERTC_TSDT_DT ERTC_TSDT_DT_Msk /*!< DT[1:0] (Date tens) */ +#define ERTC_TSDT_DT_0 (0x1U << ERTC_TSDT_DT_Pos) /*!< 0x00000010 */ +#define ERTC_TSDT_DT_1 (0x2U << ERTC_TSDT_DT_Pos) /*!< 0x00000020 */ + +/*!< MU configuration */ +#define ERTC_TSDT_MU_Pos (8U) +#define ERTC_TSDT_MU_Msk (0xFU << ERTC_TSDT_MU_Pos) /*!< 0x00000F00 */ +#define ERTC_TSDT_MU ERTC_TSDT_MU_Msk /*!< MU[3:0] (Month units) */ +#define ERTC_TSDT_MU_0 (0x1U << ERTC_TSDT_MU_Pos) /*!< 0x00000100 */ +#define ERTC_TSDT_MU_1 (0x2U << ERTC_TSDT_MU_Pos) /*!< 0x00000200 */ +#define ERTC_TSDT_MU_2 (0x4U << ERTC_TSDT_MU_Pos) /*!< 0x00000400 */ +#define ERTC_TSDT_MU_3 (0x8U << ERTC_TSDT_MU_Pos) /*!< 0x00000800 */ + +#define ERTC_TSDT_MT_Pos (12U) +#define ERTC_TSDT_MT_Msk (0x1U << ERTC_TSDT_MT_Pos) /*!< 0x00001000 */ +#define ERTC_TSDT_MT ERTC_TSDT_MT_Msk /*!< Month tens */ + +/*!< WK configuration */ +#define ERTC_TSDT_WK_Pos (13U) +#define ERTC_TSDT_WK_Msk (0x7U << ERTC_TSDT_WK_Pos) /*!< 0x0000E000 */ +#define ERTC_TSDT_WK ERTC_TSDT_WK_Msk /*!< WK[2:0] (Week day) */ +#define ERTC_TSDT_WK_0 (0x1U << ERTC_TSDT_WK_Pos) /*!< 0x00002000 */ +#define ERTC_TSDT_WK_1 (0x2U << ERTC_TSDT_WK_Pos) /*!< 0x00004000 */ +#define ERTC_TSDT_WK_2 (0x4U << ERTC_TSDT_WK_Pos) /*!< 0x00008000 */ + +/****************** Bit definition for ERTC_TSSBS register ******************/ +#define ERTC_TSSBS_SBS_Pos (0U) +#define ERTC_TSSBS_SBS_Msk (0xFFFFU << ERTC_TSSBS_SBS_Pos) /*!< 0x0000FFFF */ +#define ERTC_TSSBS_SBS ERTC_TSSBS_SBS_Msk /*!< Sub-second value */ + +/****************** Bit definition for ERTC_SCAL register *******************/ +#define ERTC_SCAL_DEC_Pos (0U) +#define ERTC_SCAL_DEC_Msk (0x1FFU << ERTC_SCAL_DEC_Pos) /*!< 0x000001FF */ +#define ERTC_SCAL_DEC ERTC_SCAL_DEC_Msk /*!< Decrease ERTC clock */ +#define ERTC_SCAL_CAL16_Pos (13U) +#define ERTC_SCAL_CAL16_Msk (0x1U << ERTC_SCAL_CAL16_Pos) /*!< 0x00002000 */ +#define ERTC_SCAL_CAL16 ERTC_SCAL_CAL16_Msk /*!< 16 second calibration period */ +#define ERTC_SCAL_CAL8_Pos (14U) +#define ERTC_SCAL_CAL8_Msk (0x1U << ERTC_SCAL_CAL8_Pos) /*!< 0x00004000 */ +#define ERTC_SCAL_CAL8 ERTC_SCAL_CAL8_Msk /*!< 8 second calibration period */ +#define ERTC_SCAL_ADD_Pos (15U) +#define ERTC_SCAL_ADD_Msk (0x1U << ERTC_SCAL_ADD_Pos) /*!< 0x00008000 */ +#define ERTC_SCAL_ADD ERTC_SCAL_ADD_Msk /*!< Add ERTC clock */ + +/****************** Bit definition for ERTC_TAMP register *******************/ +#define ERTC_TAMP_TP1EN_Pos (0U) +#define ERTC_TAMP_TP1EN_Msk (0x1U << ERTC_TAMP_TP1EN_Pos) /*!< 0x00000001 */ +#define ERTC_TAMP_TP1EN ERTC_TAMP_TP1EN_Msk /*!< Tamper detection 1 enable */ +#define ERTC_TAMP_TP1EDG_Pos (1U) +#define ERTC_TAMP_TP1EDG_Msk (0x1U << ERTC_TAMP_TP1EDG_Pos) /*!< 0x00000002 */ +#define ERTC_TAMP_TP1EDG ERTC_TAMP_TP1EDG_Msk /*!< Tamper detection 1 valid edge */ +#define ERTC_TAMP_TPIEN_Pos (2U) +#define ERTC_TAMP_TPIEN_Msk (0x1U << ERTC_TAMP_TPIEN_Pos) /*!< 0x00000004 */ +#define ERTC_TAMP_TPIEN ERTC_TAMP_TPIEN_Msk /*!< Tamper detection interrupt enable */ +#define ERTC_TAMP_TP2EN_Pos (3U) +#define ERTC_TAMP_TP2EN_Msk (0x1U << ERTC_TAMP_TP2EN_Pos) /*!< 0x00000008 */ +#define ERTC_TAMP_TP2EN ERTC_TAMP_TP2EN_Msk /*!< Tamper detection 2 enable */ +#define ERTC_TAMP_TP2EDG_Pos (4U) +#define ERTC_TAMP_TP2EDG_Msk (0x1U << ERTC_TAMP_TP2EDG_Pos) /*!< 0x00000010 */ +#define ERTC_TAMP_TP2EDG ERTC_TAMP_TP2EDG_Msk /*!< Tamper detection 2 valid edge */ +#define ERTC_TAMP_TPTSEN_Pos (7U) +#define ERTC_TAMP_TPTSEN_Msk (0x1U << ERTC_TAMP_TPTSEN_Pos) /*!< 0x00000080 */ +#define ERTC_TAMP_TPTSEN ERTC_TAMP_TPTSEN_Msk /*!< Tamper detection timestamp enable */ + +/*!< TPFREQ configuration */ +#define ERTC_TAMP_TPFREQ_Pos (8U) +#define ERTC_TAMP_TPFREQ_Msk (0x7U << ERTC_TAMP_TPFREQ_Pos) /*!< 0x00000700 */ +#define ERTC_TAMP_TPFREQ ERTC_TAMP_TPFREQ_Msk /*!< TPFREQ[2:0] (Tamper detection frequency) */ +#define ERTC_TAMP_TPFREQ_0 (0x1U << ERTC_TAMP_TPFREQ_Pos) /*!< 0x00000100 */ +#define ERTC_TAMP_TPFREQ_1 (0x2U << ERTC_TAMP_TPFREQ_Pos) /*!< 0x00000200 */ +#define ERTC_TAMP_TPFREQ_2 (0x4U << ERTC_TAMP_TPFREQ_Pos) /*!< 0x00000400 */ + +/*!< TPFLT configuration */ +#define ERTC_TAMP_TPFLT_Pos (11U) +#define ERTC_TAMP_TPFLT_Msk (0x3U << ERTC_TAMP_TPFLT_Pos) /*!< 0x00001800 */ +#define ERTC_TAMP_TPFLT ERTC_TAMP_TPFLT_Msk /*!< TPFLT[1:0] (Tamper detection filter time) */ +#define ERTC_TAMP_TPFLT_0 (0x1U << ERTC_TAMP_TPFLT_Pos) /*!< 0x00000800 */ +#define ERTC_TAMP_TPFLT_1 (0x2U << ERTC_TAMP_TPFLT_Pos) /*!< 0x00001000 */ + +/*!< TPPR configuration */ +#define ERTC_TAMP_TPPR_Pos (13U) +#define ERTC_TAMP_TPPR_Msk (0x3U << ERTC_TAMP_TPPR_Pos) /*!< 0x00006000 */ +#define ERTC_TAMP_TPPR ERTC_TAMP_TPPR_Msk /*!< TPPR[1:0] (Tamper detection pre-charge time) */ +#define ERTC_TAMP_TPPR_0 (0x1U << ERTC_TAMP_TPPR_Pos) /*!< 0x00002000 */ +#define ERTC_TAMP_TPPR_1 (0x2U << ERTC_TAMP_TPPR_Pos) /*!< 0x00004000 */ + +#define ERTC_TAMP_TPPU_Pos (15U) +#define ERTC_TAMP_TPPU_Msk (0x1U << ERTC_TAMP_TPPU_Pos) /*!< 0x00008000 */ +#define ERTC_TAMP_TPPU ERTC_TAMP_TPPU_Msk /*!< Tamper detection pull-up */ +#define ERTC_TAMP_TP1PIN_Pos (16U) +#define ERTC_TAMP_TP1PIN_Msk (0x1U << ERTC_TAMP_TP1PIN_Pos) /*!< 0x00010000 */ +#define ERTC_TAMP_TP1PIN ERTC_TAMP_TP1PIN_Msk /*!< Tamper detection pin selection */ +#define ERTC_TAMP_TSPIN_Pos (17U) +#define ERTC_TAMP_TSPIN_Msk (0x1U << ERTC_TAMP_TSPIN_Pos) /*!< 0x00020000 */ +#define ERTC_TAMP_TSPIN ERTC_TAMP_TSPIN_Msk /*!< Time stamp detection pin selection */ +#define ERTC_TAMP_OUTTYPE_Pos (18U) +#define ERTC_TAMP_OUTTYPE_Msk (0x1U << ERTC_TAMP_OUTTYPE_Pos) /*!< 0x00040000 */ +#define ERTC_TAMP_OUTTYPE ERTC_TAMP_OUTTYPE_Msk /*!< Output type */ + +/***************** Bit definition for ERTC_ALASBS register ******************/ +#define ERTC_ALASBS_SBS_Pos (0U) +#define ERTC_ALASBS_SBS_Msk (0x7FFFU << ERTC_ALASBS_SBS_Pos) /*!< 0x00007FFF */ +#define ERTC_ALASBS_SBS ERTC_ALASBS_SBS_Msk /*!< Sub-second value */ + +/*!< SBSMSK configuration */ +#define ERTC_ALASBS_SBSMSK_Pos (24U) +#define ERTC_ALASBS_SBSMSK_Msk (0xFU << ERTC_ALASBS_SBSMSK_Pos) /*!< 0x0F000000 */ +#define ERTC_ALASBS_SBSMSK ERTC_ALASBS_SBSMSK_Msk /*!< SBSMSK[3:0] (Sub-second mask) */ +#define ERTC_ALASBS_SBSMSK_0 (0x1U << ERTC_ALASBS_SBSMSK_Pos) /*!< 0x01000000 */ +#define ERTC_ALASBS_SBSMSK_1 (0x2U << ERTC_ALASBS_SBSMSK_Pos) /*!< 0x02000000 */ +#define ERTC_ALASBS_SBSMSK_2 (0x4U << ERTC_ALASBS_SBSMSK_Pos) /*!< 0x04000000 */ +#define ERTC_ALASBS_SBSMSK_3 (0x8U << ERTC_ALASBS_SBSMSK_Pos) /*!< 0x08000000 */ + +/***************** Bit definition for ERTC_ALBSBS register ******************/ +#define ERTC_ALBSBS_SBS_Pos (0U) +#define ERTC_ALBSBS_SBS_Msk (0x7FFFU << ERTC_ALBSBS_SBS_Pos) /*!< 0x00007FFF */ +#define ERTC_ALBSBS_SBS ERTC_ALBSBS_SBS_Msk /*!< Sub-second value */ + +/*!< SBSMSK configuration */ +#define ERTC_ALBSBS_SBSMSK_Pos (24U) +#define ERTC_ALBSBS_SBSMSK_Msk (0xFU << ERTC_ALBSBS_SBSMSK_Pos) /*!< 0x0F000000 */ +#define ERTC_ALBSBS_SBSMSK ERTC_ALBSBS_SBSMSK_Msk /*!< SBSMSK[3:0] (Sub-second mask) */ +#define ERTC_ALBSBS_SBSMSK_0 (0x1U << ERTC_ALBSBS_SBSMSK_Pos) /*!< 0x01000000 */ +#define ERTC_ALBSBS_SBSMSK_1 (0x2U << ERTC_ALBSBS_SBSMSK_Pos) /*!< 0x02000000 */ +#define ERTC_ALBSBS_SBSMSK_2 (0x4U << ERTC_ALBSBS_SBSMSK_Pos) /*!< 0x04000000 */ +#define ERTC_ALBSBS_SBSMSK_3 (0x8U << ERTC_ALBSBS_SBSMSK_Pos) /*!< 0x08000000 */ + +/****************** Bit definition for ERTC_BPR1 register *******************/ +#define ERTC_BPR1_DT_Pos (0U) +#define ERTC_BPR1_DT_Msk (0xFFFFFFFFU << ERTC_BPR1_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR1_DT ERTC_BPR1_DT_Msk /*!< Battery powered domain data 1 */ + +/****************** Bit definition for ERTC_BPR2 register *******************/ +#define ERTC_BPR2_DT_Pos (0U) +#define ERTC_BPR2_DT_Msk (0xFFFFFFFFU << ERTC_BPR2_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR2_DT ERTC_BPR2_DT_Msk /*!< Battery powered domain data 2 */ + +/****************** Bit definition for ERTC_BPR3 register *******************/ +#define ERTC_BPR3_DT_Pos (0U) +#define ERTC_BPR3_DT_Msk (0xFFFFFFFFU << ERTC_BPR3_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR3_DT ERTC_BPR3_DT_Msk /*!< Battery powered domain data 3 */ + +/****************** Bit definition for ERTC_BPR4 register *******************/ +#define ERTC_BPR4_DT_Pos (0U) +#define ERTC_BPR4_DT_Msk (0xFFFFFFFFU << ERTC_BPR4_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR4_DT ERTC_BPR4_DT_Msk /*!< Battery powered domain data 4 */ + +/****************** Bit definition for ERTC_BPR5 register *******************/ +#define ERTC_BPR5_DT_Pos (0U) +#define ERTC_BPR5_DT_Msk (0xFFFFFFFFU << ERTC_BPR5_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR5_DT ERTC_BPR5_DT_Msk /*!< Battery powered domain data 5 */ + +/****************** Bit definition for ERTC_BPR6 register *******************/ +#define ERTC_BPR6_DT_Pos (0U) +#define ERTC_BPR6_DT_Msk (0xFFFFFFFFU << ERTC_BPR6_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR6_DT ERTC_BPR6_DT_Msk /*!< Battery powered domain data 6 */ + +/****************** Bit definition for ERTC_BPR7 register *******************/ +#define ERTC_BPR7_DT_Pos (0U) +#define ERTC_BPR7_DT_Msk (0xFFFFFFFFU << ERTC_BPR7_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR7_DT ERTC_BPR7_DT_Msk /*!< Battery powered domain data 7 */ + +/****************** Bit definition for ERTC_BPR8 register *******************/ +#define ERTC_BPR8_DT_Pos (0U) +#define ERTC_BPR8_DT_Msk (0xFFFFFFFFU << ERTC_BPR8_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR8_DT ERTC_BPR8_DT_Msk /*!< Battery powered domain data 8 */ + +/****************** Bit definition for ERTC_BPR9 register *******************/ +#define ERTC_BPR9_DT_Pos (0U) +#define ERTC_BPR9_DT_Msk (0xFFFFFFFFU << ERTC_BPR9_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR9_DT ERTC_BPR9_DT_Msk /*!< Battery powered domain data 9 */ + +/****************** Bit definition for ERTC_BPR10 register ******************/ +#define ERTC_BPR10_DT_Pos (0U) +#define ERTC_BPR10_DT_Msk (0xFFFFFFFFU << ERTC_BPR10_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR10_DT ERTC_BPR10_DT_Msk /*!< Battery powered domain data 10 */ + +/****************** Bit definition for ERTC_BPR11 register ******************/ +#define ERTC_BPR11_DT_Pos (0U) +#define ERTC_BPR11_DT_Msk (0xFFFFFFFFU << ERTC_BPR11_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR11_DT ERTC_BPR11_DT_Msk /*!< Battery powered domain data 11 */ + +/****************** Bit definition for ERTC_BPR12 register ******************/ +#define ERTC_BPR12_DT_Pos (0U) +#define ERTC_BPR12_DT_Msk (0xFFFFFFFFU << ERTC_BPR12_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR12_DT ERTC_BPR12_DT_Msk /*!< Battery powered domain data 12 */ + +/****************** Bit definition for ERTC_BPR13 register ******************/ +#define ERTC_BPR13_DT_Pos (0U) +#define ERTC_BPR13_DT_Msk (0xFFFFFFFFU << ERTC_BPR13_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR13_DT ERTC_BPR13_DT_Msk /*!< Battery powered domain data 13 */ + +/****************** Bit definition for ERTC_BPR14 register ******************/ +#define ERTC_BPR14_DT_Pos (0U) +#define ERTC_BPR14_DT_Msk (0xFFFFFFFFU << ERTC_BPR14_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR14_DT ERTC_BPR14_DT_Msk /*!< Battery powered domain data 14 */ + +/****************** Bit definition for ERTC_BPR15 register ******************/ +#define ERTC_BPR15_DT_Pos (0U) +#define ERTC_BPR15_DT_Msk (0xFFFFFFFFU << ERTC_BPR15_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR15_DT ERTC_BPR15_DT_Msk /*!< Battery powered domain data 15 */ + +/****************** Bit definition for ERTC_BPR16 register ******************/ +#define ERTC_BPR16_DT_Pos (0U) +#define ERTC_BPR16_DT_Msk (0xFFFFFFFFU << ERTC_BPR16_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR16_DT ERTC_BPR16_DT_Msk /*!< Battery powered domain data 16 */ + +/****************** Bit definition for ERTC_BPR17 register ******************/ +#define ERTC_BPR17_DT_Pos (0U) +#define ERTC_BPR17_DT_Msk (0xFFFFFFFFU << ERTC_BPR17_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR17_DT ERTC_BPR17_DT_Msk /*!< Battery powered domain data 17 */ + +/****************** Bit definition for ERTC_BPR18 register ******************/ +#define ERTC_BPR18_DT_Pos (0U) +#define ERTC_BPR18_DT_Msk (0xFFFFFFFFU << ERTC_BPR18_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR18_DT ERTC_BPR18_DT_Msk /*!< Battery powered domain data 18 */ + +/****************** Bit definition for ERTC_BPR19 register ******************/ +#define ERTC_BPR19_DT_Pos (0U) +#define ERTC_BPR19_DT_Msk (0xFFFFFFFFU << ERTC_BPR19_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR19_DT ERTC_BPR19_DT_Msk /*!< Battery powered domain data 19 */ + +/****************** Bit definition for ERTC_BPR20 register ******************/ +#define ERTC_BPR20_DT_Pos (0U) +#define ERTC_BPR20_DT_Msk (0xFFFFFFFFU << ERTC_BPR20_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR20_DT ERTC_BPR20_DT_Msk /*!< Battery powered domain data 20 */ + +/************************* Number of backup registers *************************/ +#define ERTC_BPR_NUMBER 0x000000014U + +/******************************************************************************/ +/* */ +/* Analog-to-digital converter (ADC) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for ADC_STS register ********************/ +#define ADC_STS_VMOR_Pos (0U) +#define ADC_STS_VMOR_Msk (0x1U << ADC_STS_VMOR_Pos) /*!< 0x00000001 */ +#define ADC_STS_VMOR ADC_STS_VMOR_Msk /*!< Voltage monitoring out of range flag */ +#define ADC_STS_OCCC_Pos (1U) +#define ADC_STS_OCCC_Msk (0x1U << ADC_STS_OCCC_Pos) /*!< 0x00000002 */ +#define ADC_STS_OCCC ADC_STS_OCCC_Msk /*!< End of conversion flag */ +#define ADC_STS_PCCC_Pos (2U) +#define ADC_STS_PCCC_Msk (0x1U << ADC_STS_PCCC_Pos) /*!< 0x00000004 */ +#define ADC_STS_PCCC ADC_STS_PCCC_Msk /*!< Preempted channel end of conversion flag */ +#define ADC_STS_PCCS_Pos (3U) +#define ADC_STS_PCCS_Msk (0x1U << ADC_STS_PCCS_Pos) /*!< 0x00000008 */ +#define ADC_STS_PCCS ADC_STS_PCCS_Msk /*!< Preempted channel conversion start flag */ +#define ADC_STS_OCCS_Pos (4U) +#define ADC_STS_OCCS_Msk (0x1U << ADC_STS_OCCS_Pos) /*!< 0x00000010 */ +#define ADC_STS_OCCS ADC_STS_OCCS_Msk /*!< Ordinary channel conversion start flag */ + +/* Legacy defines */ +#define ADC_STS_OCCE (ADC_STS_OCCC) +#define ADC_STS_PCCE (ADC_STS_PCCC) + +/****************** Bit definition for ADC_CTRL1 register *******************/ +/*!< VMCSEL configuration */ +#define ADC_CTRL1_VMCSEL_Pos (0U) +#define ADC_CTRL1_VMCSEL_Msk (0x1FU << ADC_CTRL1_VMCSEL_Pos) /*!< 0x0000001F */ +#define ADC_CTRL1_VMCSEL ADC_CTRL1_VMCSEL_Msk /*!< VMCSEL[4:0] bits (Voltage monitoring channel select) */ +#define ADC_CTRL1_VMCSEL_0 (0x01U << ADC_CTRL1_VMCSEL_Pos) /*!< 0x00000001 */ +#define ADC_CTRL1_VMCSEL_1 (0x02U << ADC_CTRL1_VMCSEL_Pos) /*!< 0x00000002 */ +#define ADC_CTRL1_VMCSEL_2 (0x04U << ADC_CTRL1_VMCSEL_Pos) /*!< 0x00000004 */ +#define ADC_CTRL1_VMCSEL_3 (0x08U << ADC_CTRL1_VMCSEL_Pos) /*!< 0x00000008 */ +#define ADC_CTRL1_VMCSEL_4 (0x10U << ADC_CTRL1_VMCSEL_Pos) /*!< 0x00000010 */ + +#define ADC_CTRL1_CCCIEN_Pos (5U) +#define ADC_CTRL1_CCCIEN_Msk (0x1U << ADC_CTRL1_CCCIEN_Pos) /*!< 0x00000020 */ +#define ADC_CTRL1_CCCIEN ADC_CTRL1_CCCIEN_Msk /*!< Channel conversion end interrupt enable */ +#define ADC_CTRL1_VMORIEN_Pos (6U) +#define ADC_CTRL1_VMORIEN_Msk (0x1U << ADC_CTRL1_VMORIEN_Pos) /*!< 0x00000040 */ +#define ADC_CTRL1_VMORIEN ADC_CTRL1_VMORIEN_Msk /*!< Voltage monitoring out of range interrupt enable */ +#define ADC_CTRL1_PCCCIEN_Pos (7U) +#define ADC_CTRL1_PCCCIEN_Msk (0x1U << ADC_CTRL1_PCCCIEN_Pos) /*!< 0x00000080 */ +#define ADC_CTRL1_PCCCIEN ADC_CTRL1_PCCCIEN_Msk /*!< Conversion end interrupt enable on Preempted channels */ +#define ADC_CTRL1_SQEN_Pos (8U) +#define ADC_CTRL1_SQEN_Msk (0x1U << ADC_CTRL1_SQEN_Pos) /*!< 0x00000100 */ +#define ADC_CTRL1_SQEN ADC_CTRL1_SQEN_Msk /*!< Sequence mode enable */ +#define ADC_CTRL1_VMSGEN_Pos (9U) +#define ADC_CTRL1_VMSGEN_Msk (0x1U << ADC_CTRL1_VMSGEN_Pos) /*!< 0x00000200 */ +#define ADC_CTRL1_VMSGEN ADC_CTRL1_VMSGEN_Msk /*!< Voltage monitoring enable on a single channel */ +#define ADC_CTRL1_PCAUTOEN_Pos (10U) +#define ADC_CTRL1_PCAUTOEN_Msk (0x1U << ADC_CTRL1_PCAUTOEN_Pos) /*!< 0x00000400 */ +#define ADC_CTRL1_PCAUTOEN ADC_CTRL1_PCAUTOEN_Msk /*!< Preempted group automatic conversion enable after ordinary group */ +#define ADC_CTRL1_OCPEN_Pos (11U) +#define ADC_CTRL1_OCPEN_Msk (0x1U << ADC_CTRL1_OCPEN_Pos) /*!< 0x00000800 */ +#define ADC_CTRL1_OCPEN ADC_CTRL1_OCPEN_Msk /*!< Partitioned mode enable on ordinary channels */ +#define ADC_CTRL1_PCPEN_Pos (12U) +#define ADC_CTRL1_PCPEN_Msk (0x1U << ADC_CTRL1_PCPEN_Pos) /*!< 0x00001000 */ +#define ADC_CTRL1_PCPEN ADC_CTRL1_PCPEN_Msk /*!< Partitioned mode enable on preempted channels */ + +/*!< OCPCNT configuration */ +#define ADC_CTRL1_OCPCNT_Pos (13U) +#define ADC_CTRL1_OCPCNT_Msk (0x7U << ADC_CTRL1_OCPCNT_Pos) /*!< 0x0000E000 */ +#define ADC_CTRL1_OCPCNT ADC_CTRL1_OCPCNT_Msk /*!< OCPCNT[2:0] bits (Partitioned mode conversion count of ordinary channels) */ +#define ADC_CTRL1_OCPCNT_0 (0x1U << ADC_CTRL1_OCPCNT_Pos) /*!< 0x00002000 */ +#define ADC_CTRL1_OCPCNT_1 (0x2U << ADC_CTRL1_OCPCNT_Pos) /*!< 0x00004000 */ +#define ADC_CTRL1_OCPCNT_2 (0x4U << ADC_CTRL1_OCPCNT_Pos) /*!< 0x00008000 */ + +#define ADC_CTRL1_PCVMEN_Pos (22U) +#define ADC_CTRL1_PCVMEN_Msk (0x1U << ADC_CTRL1_PCVMEN_Pos) /*!< 0x00400000 */ +#define ADC_CTRL1_PCVMEN ADC_CTRL1_PCVMEN_Msk /*!< Voltage monitoring enable on preempted channels */ +#define ADC_CTRL1_OCVMEN_Pos (23U) +#define ADC_CTRL1_OCVMEN_Msk (0x1U << ADC_CTRL1_OCVMEN_Pos) /*!< 0x00800000 */ +#define ADC_CTRL1_OCVMEN ADC_CTRL1_OCVMEN_Msk /*!< Voltage monitoring enable on ordinary channels */ + +/* Legacy defines */ +#define ADC_CTRL1_CCEIEN (ADC_CTRL1_CCCIEN) +#define ADC_CTRL1_PCCEIEN (ADC_CTRL1_PCCCIEN) + +/****************** Bit definition for ADC_CTRL2 register *******************/ +#define ADC_CTRL2_ADCEN_Pos (0U) +#define ADC_CTRL2_ADCEN_Msk (0x1U << ADC_CTRL2_ADCEN_Pos) /*!< 0x00000001 */ +#define ADC_CTRL2_ADCEN ADC_CTRL2_ADCEN_Msk /*!< A/D converter enable */ +#define ADC_CTRL2_RPEN_Pos (1U) +#define ADC_CTRL2_RPEN_Msk (0x1U << ADC_CTRL2_RPEN_Pos) /*!< 0x00000002 */ +#define ADC_CTRL2_RPEN ADC_CTRL2_RPEN_Msk /*!< Repetition mode enable */ +#define ADC_CTRL2_ADCAL_Pos (2U) +#define ADC_CTRL2_ADCAL_Msk (0x1U << ADC_CTRL2_ADCAL_Pos) /*!< 0x00000004 */ +#define ADC_CTRL2_ADCAL ADC_CTRL2_ADCAL_Msk /*!< A/D calibration */ +#define ADC_CTRL2_ADCALINIT_Pos (3U) +#define ADC_CTRL2_ADCALINIT_Msk (0x1U << ADC_CTRL2_ADCALINIT_Pos) /*!< 0x00000008 */ +#define ADC_CTRL2_ADCALINIT ADC_CTRL2_ADCALINIT_Msk /*!< Initialize A/D calibration */ +#define ADC_CTRL2_OCDMAEN_Pos (8U) +#define ADC_CTRL2_OCDMAEN_Msk (0x1U << ADC_CTRL2_OCDMAEN_Pos) /*!< 0x00000100 */ +#define ADC_CTRL2_OCDMAEN ADC_CTRL2_OCDMAEN_Msk /*!< DMA transfer enable of ordinary channels */ +#define ADC_CTRL2_DTALIGN_Pos (11U) +#define ADC_CTRL2_DTALIGN_Msk (0x1U << ADC_CTRL2_DTALIGN_Pos) /*!< 0x00000800 */ +#define ADC_CTRL2_DTALIGN ADC_CTRL2_DTALIGN_Msk /*!< Data alignment */ + +/*!< PCTESEL configuration */ +#define ADC_CTRL2_PCTESEL_Pos (12U) +#define ADC_CTRL2_PCTESEL_Msk (0x7U << ADC_CTRL2_PCTESEL_Pos) /*!< 0x00007000 */ +#define ADC_CTRL2_PCTESEL ADC_CTRL2_PCTESEL_Msk /*!< PCTESEL[2:0] bits (Trigger event select for preempted channels conversion) */ +#define ADC_CTRL2_PCTESEL_0 (0x1U << ADC_CTRL2_PCTESEL_Pos) /*!< 0x00001000 */ +#define ADC_CTRL2_PCTESEL_1 (0x2U << ADC_CTRL2_PCTESEL_Pos) /*!< 0x00002000 */ +#define ADC_CTRL2_PCTESEL_2 (0x4U << ADC_CTRL2_PCTESEL_Pos) /*!< 0x00004000 */ + +#define ADC_CTRL2_PCTEN_Pos (15U) +#define ADC_CTRL2_PCTEN_Msk (0x1U << ADC_CTRL2_PCTEN_Pos) /*!< 0x00008000 */ +#define ADC_CTRL2_PCTEN ADC_CTRL2_PCTEN_Msk /*!< Trigger mode enable for preempted channels conversion */ + +/*!< OCTESEL configuration */ +#define ADC_CTRL2_OCTESEL_Pos (17U) +#define ADC_CTRL2_OCTESEL_Msk (0x7U << ADC_CTRL2_OCTESEL_Pos) /*!< 0x000E0000 */ +#define ADC_CTRL2_OCTESEL ADC_CTRL2_OCTESEL_Msk /*!< OCTESEL[2:0] bits (Trigger event select for ordinary channels conversion) */ +#define ADC_CTRL2_OCTESEL_0 (0x1U << ADC_CTRL2_OCTESEL_Pos) /*!< 0x00020000 */ +#define ADC_CTRL2_OCTESEL_1 (0x2U << ADC_CTRL2_OCTESEL_Pos) /*!< 0x00040000 */ +#define ADC_CTRL2_OCTESEL_2 (0x4U << ADC_CTRL2_OCTESEL_Pos) /*!< 0x00080000 */ + +#define ADC_CTRL2_OCTEN_Pos (20U) +#define ADC_CTRL2_OCTEN_Msk (0x1U << ADC_CTRL2_OCTEN_Pos) /*!< 0x00100000 */ +#define ADC_CTRL2_OCTEN ADC_CTRL2_OCTEN_Msk /*!< Trigger mode enable for ordinary channels conversion */ +#define ADC_CTRL2_PCSWTRG_Pos (21U) +#define ADC_CTRL2_PCSWTRG_Msk (0x1U << ADC_CTRL2_PCSWTRG_Pos) /*!< 0x00200000 */ +#define ADC_CTRL2_PCSWTRG ADC_CTRL2_PCSWTRG_Msk /*!< Conversion of preempted channels triggered by software */ +#define ADC_CTRL2_OCSWTRG_Pos (22U) +#define ADC_CTRL2_OCSWTRG_Msk (0x1U << ADC_CTRL2_OCSWTRG_Pos) /*!< 0x00400000 */ +#define ADC_CTRL2_OCSWTRG ADC_CTRL2_OCSWTRG_Msk /*!< Conversion of ordinary channels triggered by software */ +#define ADC_CTRL2_ITSRVEN_Pos (23U) +#define ADC_CTRL2_ITSRVEN_Msk (0x1U << ADC_CTRL2_ITSRVEN_Pos) /*!< 0x00800000 */ +#define ADC_CTRL2_ITSRVEN ADC_CTRL2_ITSRVEN_Msk /*!< Internal temperature sensor and VINTRV enable */ + +/******************* Bit definition for ADC_SPT1 register *******************/ +/*!< CSPT10 configuration */ +#define ADC_SPT1_CSPT10_Pos (0U) +#define ADC_SPT1_CSPT10_Msk (0x7U << ADC_SPT1_CSPT10_Pos) /*!< 0x00000007 */ +#define ADC_SPT1_CSPT10 ADC_SPT1_CSPT10_Msk /*!< CSPT10[2:0] bits (Sample time selection of channel ADC_IN10) */ +#define ADC_SPT1_CSPT10_0 (0x1U << ADC_SPT1_CSPT10_Pos) /*!< 0x00000001 */ +#define ADC_SPT1_CSPT10_1 (0x2U << ADC_SPT1_CSPT10_Pos) /*!< 0x00000002 */ +#define ADC_SPT1_CSPT10_2 (0x4U << ADC_SPT1_CSPT10_Pos) /*!< 0x00000004 */ + +/*!< CSPT11 configuration */ +#define ADC_SPT1_CSPT11_Pos (3U) +#define ADC_SPT1_CSPT11_Msk (0x7U << ADC_SPT1_CSPT11_Pos) /*!< 0x00000038 */ +#define ADC_SPT1_CSPT11 ADC_SPT1_CSPT11_Msk /*!< CSPT11[2:0] bits (Sample time selection of channel ADC_IN11) */ +#define ADC_SPT1_CSPT11_0 (0x1U << ADC_SPT1_CSPT11_Pos) /*!< 0x00000008 */ +#define ADC_SPT1_CSPT11_1 (0x2U << ADC_SPT1_CSPT11_Pos) /*!< 0x00000010 */ +#define ADC_SPT1_CSPT11_2 (0x4U << ADC_SPT1_CSPT11_Pos) /*!< 0x00000020 */ + +/*!< CSPT12 configuration */ +#define ADC_SPT1_CSPT12_Pos (6U) +#define ADC_SPT1_CSPT12_Msk (0x7U << ADC_SPT1_CSPT12_Pos) /*!< 0x000001C0 */ +#define ADC_SPT1_CSPT12 ADC_SPT1_CSPT12_Msk /*!< CSPT12[2:0] bits (Sample time selection of channel ADC_IN12) */ +#define ADC_SPT1_CSPT12_0 (0x1U << ADC_SPT1_CSPT12_Pos) /*!< 0x00000040 */ +#define ADC_SPT1_CSPT12_1 (0x2U << ADC_SPT1_CSPT12_Pos) /*!< 0x00000080 */ +#define ADC_SPT1_CSPT12_2 (0x4U << ADC_SPT1_CSPT12_Pos) /*!< 0x00000100 */ + +/*!< CSPT13 configuration */ +#define ADC_SPT1_CSPT13_Pos (9U) +#define ADC_SPT1_CSPT13_Msk (0x7U << ADC_SPT1_CSPT13_Pos) /*!< 0x00000E00 */ +#define ADC_SPT1_CSPT13 ADC_SPT1_CSPT13_Msk /*!< CSPT13[2:0] bits (Sample time selection of channel ADC_IN13) */ +#define ADC_SPT1_CSPT13_0 (0x1U << ADC_SPT1_CSPT13_Pos) /*!< 0x00000200 */ +#define ADC_SPT1_CSPT13_1 (0x2U << ADC_SPT1_CSPT13_Pos) /*!< 0x00000400 */ +#define ADC_SPT1_CSPT13_2 (0x4U << ADC_SPT1_CSPT13_Pos) /*!< 0x00000800 */ + +/*!< CSPT14 configuration */ +#define ADC_SPT1_CSPT14_Pos (12U) +#define ADC_SPT1_CSPT14_Msk (0x7U << ADC_SPT1_CSPT14_Pos) /*!< 0x00007000 */ +#define ADC_SPT1_CSPT14 ADC_SPT1_CSPT14_Msk /*!< CSPT14[2:0] bits (Sample time selection of channel ADC_IN14) */ +#define ADC_SPT1_CSPT14_0 (0x1U << ADC_SPT1_CSPT14_Pos) /*!< 0x00001000 */ +#define ADC_SPT1_CSPT14_1 (0x2U << ADC_SPT1_CSPT14_Pos) /*!< 0x00002000 */ +#define ADC_SPT1_CSPT14_2 (0x4U << ADC_SPT1_CSPT14_Pos) /*!< 0x00004000 */ + +/*!< CSPT15 configuration */ +#define ADC_SPT1_CSPT15_Pos (15U) +#define ADC_SPT1_CSPT15_Msk (0x7U << ADC_SPT1_CSPT15_Pos) /*!< 0x00038000 */ +#define ADC_SPT1_CSPT15 ADC_SPT1_CSPT15_Msk /*!< CSPT15[2:0] bits (Sample time selection of channel ADC_IN15) */ +#define ADC_SPT1_CSPT15_0 (0x1U << ADC_SPT1_CSPT15_Pos) /*!< 0x00008000 */ +#define ADC_SPT1_CSPT15_1 (0x2U << ADC_SPT1_CSPT15_Pos) /*!< 0x00010000 */ +#define ADC_SPT1_CSPT15_2 (0x4U << ADC_SPT1_CSPT15_Pos) /*!< 0x00020000 */ + +/*!< CSPT16 configuration */ +#define ADC_SPT1_CSPT16_Pos (18U) +#define ADC_SPT1_CSPT16_Msk (0x7U << ADC_SPT1_CSPT16_Pos) /*!< 0x001C0000 */ +#define ADC_SPT1_CSPT16 ADC_SPT1_CSPT16_Msk /*!< CSPT16[2:0] bits (Sample time selection of channel ADC_IN16) */ +#define ADC_SPT1_CSPT16_0 (0x1U << ADC_SPT1_CSPT16_Pos) /*!< 0x00040000 */ +#define ADC_SPT1_CSPT16_1 (0x2U << ADC_SPT1_CSPT16_Pos) /*!< 0x00080000 */ +#define ADC_SPT1_CSPT16_2 (0x4U << ADC_SPT1_CSPT16_Pos) /*!< 0x00100000 */ + +/*!< CSPT17 configuration */ +#define ADC_SPT1_CSPT17_Pos (21U) +#define ADC_SPT1_CSPT17_Msk (0x7U << ADC_SPT1_CSPT17_Pos) /*!< 0x00E00000 */ +#define ADC_SPT1_CSPT17 ADC_SPT1_CSPT17_Msk /*!< CSPT17[2:0] bits (Sample time selection of channel ADC_IN17) */ +#define ADC_SPT1_CSPT17_0 (0x1U << ADC_SPT1_CSPT17_Pos) /*!< 0x00200000 */ +#define ADC_SPT1_CSPT17_1 (0x2U << ADC_SPT1_CSPT17_Pos) /*!< 0x00400000 */ +#define ADC_SPT1_CSPT17_2 (0x4U << ADC_SPT1_CSPT17_Pos) /*!< 0x00800000 */ + +/******************* Bit definition for ADC_SPT2 register *******************/ +/*!< CSPT0 configuration */ +#define ADC_SPT2_CSPT0_Pos (0U) +#define ADC_SPT2_CSPT0_Msk (0x7U << ADC_SPT2_CSPT0_Pos) /*!< 0x00000007 */ +#define ADC_SPT2_CSPT0 ADC_SPT2_CSPT0_Msk /*!< CSPT0[2:0] bits (Sample time selection of channel ADC_IN0) */ +#define ADC_SPT2_CSPT0_0 (0x1U << ADC_SPT2_CSPT0_Pos) /*!< 0x00000001 */ +#define ADC_SPT2_CSPT0_1 (0x2U << ADC_SPT2_CSPT0_Pos) /*!< 0x00000002 */ +#define ADC_SPT2_CSPT0_2 (0x4U << ADC_SPT2_CSPT0_Pos) /*!< 0x00000004 */ + +/*!< CSPT1 configuration */ +#define ADC_SPT2_CSPT1_Pos (3U) +#define ADC_SPT2_CSPT1_Msk (0x7U << ADC_SPT2_CSPT1_Pos) /*!< 0x00000038 */ +#define ADC_SPT2_CSPT1 ADC_SPT2_CSPT1_Msk /*!< CSPT1[2:0] bits (Sample time selection of channel ADC_IN1) */ +#define ADC_SPT2_CSPT1_0 (0x1U << ADC_SPT2_CSPT1_Pos) /*!< 0x00000008 */ +#define ADC_SPT2_CSPT1_1 (0x2U << ADC_SPT2_CSPT1_Pos) /*!< 0x00000010 */ +#define ADC_SPT2_CSPT1_2 (0x4U << ADC_SPT2_CSPT1_Pos) /*!< 0x00000020 */ + +/*!< CSPT2 configuration */ +#define ADC_SPT2_CSPT2_Pos (6U) +#define ADC_SPT2_CSPT2_Msk (0x7U << ADC_SPT2_CSPT2_Pos) /*!< 0x000001C0 */ +#define ADC_SPT2_CSPT2 ADC_SPT2_CSPT2_Msk /*!< CSPT2[2:0] bits (Sample time selection of channel ADC_IN2) */ +#define ADC_SPT2_CSPT2_0 (0x1U << ADC_SPT2_CSPT2_Pos) /*!< 0x00000040 */ +#define ADC_SPT2_CSPT2_1 (0x2U << ADC_SPT2_CSPT2_Pos) /*!< 0x00000080 */ +#define ADC_SPT2_CSPT2_2 (0x4U << ADC_SPT2_CSPT2_Pos) /*!< 0x00000100 */ + +/*!< CSPT3 configuration */ +#define ADC_SPT2_CSPT3_Pos (9U) +#define ADC_SPT2_CSPT3_Msk (0x7U << ADC_SPT2_CSPT3_Pos) /*!< 0x00000E00 */ +#define ADC_SPT2_CSPT3 ADC_SPT2_CSPT3_Msk /*!< CSPT3[2:0] bits (Sample time selection of channel ADC_IN3) */ +#define ADC_SPT2_CSPT3_0 (0x1U << ADC_SPT2_CSPT3_Pos) /*!< 0x00000200 */ +#define ADC_SPT2_CSPT3_1 (0x2U << ADC_SPT2_CSPT3_Pos) /*!< 0x00000400 */ +#define ADC_SPT2_CSPT3_2 (0x4U << ADC_SPT2_CSPT3_Pos) /*!< 0x00000800 */ + +/*!< CSPT4 configuration */ +#define ADC_SPT2_CSPT4_Pos (12U) +#define ADC_SPT2_CSPT4_Msk (0x7U << ADC_SPT2_CSPT4_Pos) /*!< 0x00007000 */ +#define ADC_SPT2_CSPT4 ADC_SPT2_CSPT4_Msk /*!< CSPT4[2:0] bits (Sample time selection of channel ADC_IN4) */ +#define ADC_SPT2_CSPT4_0 (0x1U << ADC_SPT2_CSPT4_Pos) /*!< 0x00001000 */ +#define ADC_SPT2_CSPT4_1 (0x2U << ADC_SPT2_CSPT4_Pos) /*!< 0x00002000 */ +#define ADC_SPT2_CSPT4_2 (0x4U << ADC_SPT2_CSPT4_Pos) /*!< 0x00004000 */ + +/*!< CSPT5 configuration */ +#define ADC_SPT2_CSPT5_Pos (15U) +#define ADC_SPT2_CSPT5_Msk (0x7U << ADC_SPT2_CSPT5_Pos) /*!< 0x00038000 */ +#define ADC_SPT2_CSPT5 ADC_SPT2_CSPT5_Msk /*!< CSPT5[2:0] bits (Sample time selection of channel ADC_IN5) */ +#define ADC_SPT2_CSPT5_0 (0x1U << ADC_SPT2_CSPT5_Pos) /*!< 0x00008000 */ +#define ADC_SPT2_CSPT5_1 (0x2U << ADC_SPT2_CSPT5_Pos) /*!< 0x00010000 */ +#define ADC_SPT2_CSPT5_2 (0x4U << ADC_SPT2_CSPT5_Pos) /*!< 0x00020000 */ + +/*!< CSPT6 configuration */ +#define ADC_SPT2_CSPT6_Pos (18U) +#define ADC_SPT2_CSPT6_Msk (0x7U << ADC_SPT2_CSPT6_Pos) /*!< 0x001C0000 */ +#define ADC_SPT2_CSPT6 ADC_SPT2_CSPT6_Msk /*!< CSPT6[2:0] bits (Sample time selection of channel ADC_IN6) */ +#define ADC_SPT2_CSPT6_0 (0x1U << ADC_SPT2_CSPT6_Pos) /*!< 0x00040000 */ +#define ADC_SPT2_CSPT6_1 (0x2U << ADC_SPT2_CSPT6_Pos) /*!< 0x00080000 */ +#define ADC_SPT2_CSPT6_2 (0x4U << ADC_SPT2_CSPT6_Pos) /*!< 0x00100000 */ + +/*!< CSPT7 configuration */ +#define ADC_SPT2_CSPT7_Pos (21U) +#define ADC_SPT2_CSPT7_Msk (0x7U << ADC_SPT2_CSPT7_Pos) /*!< 0x00E00000 */ +#define ADC_SPT2_CSPT7 ADC_SPT2_CSPT7_Msk /*!< CSPT7[2:0] bits (Sample time selection of channel ADC_IN7) */ +#define ADC_SPT2_CSPT7_0 (0x1U << ADC_SPT2_CSPT7_Pos) /*!< 0x00200000 */ +#define ADC_SPT2_CSPT7_1 (0x2U << ADC_SPT2_CSPT7_Pos) /*!< 0x00400000 */ +#define ADC_SPT2_CSPT7_2 (0x4U << ADC_SPT2_CSPT7_Pos) /*!< 0x00800000 */ + +/*!< CSPT8 configuration */ +#define ADC_SPT2_CSPT8_Pos (24U) +#define ADC_SPT2_CSPT8_Msk (0x7U << ADC_SPT2_CSPT8_Pos) /*!< 0x07000000 */ +#define ADC_SPT2_CSPT8 ADC_SPT2_CSPT8_Msk /*!< CSPT8[2:0] bits (Sample time selection of channel ADC_IN8) */ +#define ADC_SPT2_CSPT8_0 (0x1U << ADC_SPT2_CSPT8_Pos) /*!< 0x01000000 */ +#define ADC_SPT2_CSPT8_1 (0x2U << ADC_SPT2_CSPT8_Pos) /*!< 0x02000000 */ +#define ADC_SPT2_CSPT8_2 (0x4U << ADC_SPT2_CSPT8_Pos) /*!< 0x04000000 */ + +/*!< CSPT9 configuration */ +#define ADC_SPT2_CSPT9_Pos (27U) +#define ADC_SPT2_CSPT9_Msk (0x7U << ADC_SPT2_CSPT9_Pos) /*!< 0x38000000 */ +#define ADC_SPT2_CSPT9 ADC_SPT2_CSPT9_Msk /*!< CSPT9[2:0] bits (Sample time selection of channel ADC_IN9) */ +#define ADC_SPT2_CSPT9_0 (0x1U << ADC_SPT2_CSPT9_Pos) /*!< 0x08000000 */ +#define ADC_SPT2_CSPT9_1 (0x2U << ADC_SPT2_CSPT9_Pos) /*!< 0x10000000 */ +#define ADC_SPT2_CSPT9_2 (0x4U << ADC_SPT2_CSPT9_Pos) /*!< 0x20000000 */ + +/****************** Bit definition for ADC_PCDTO1 register ******************/ +#define ADC_PCDTO1_PCDTO1_Pos (0U) +#define ADC_PCDTO1_PCDTO1_Msk (0xFFFU << ADC_PCDTO1_PCDTO1_Pos) /*!< 0x00000FFF */ +#define ADC_PCDTO1_PCDTO1 ADC_PCDTO1_PCDTO1_Msk /*!< Data offset for Preempted channel 1 */ + +/****************** Bit definition for ADC_PCDTO2 register ******************/ +#define ADC_PCDTO2_PCDTO2_Pos (0U) +#define ADC_PCDTO2_PCDTO2_Msk (0xFFFU << ADC_PCDTO2_PCDTO2_Pos) /*!< 0x00000FFF */ +#define ADC_PCDTO2_PCDTO2 ADC_PCDTO2_PCDTO2_Msk /*!< Data offset for Preempted channel 2 */ + +/****************** Bit definition for ADC_PCDTO3 register ******************/ +#define ADC_PCDTO3_PCDTO3_Pos (0U) +#define ADC_PCDTO3_PCDTO3_Msk (0xFFFU << ADC_PCDTO3_PCDTO3_Pos) /*!< 0x00000FFF */ +#define ADC_PCDTO3_PCDTO3 ADC_PCDTO3_PCDTO3_Msk /*!< Data offset for Preempted channel 3 */ + +/****************** Bit definition for ADC_PCDTO4 register ******************/ +#define ADC_PCDTO4_PCDTO4_Pos (0U) +#define ADC_PCDTO4_PCDTO4_Msk (0xFFFU << ADC_PCDTO4_PCDTO4_Pos) /*!< 0x00000FFF */ +#define ADC_PCDTO4_PCDTO4 ADC_PCDTO4_PCDTO4_Msk /*!< Data offset for Preempted channel 4 */ + +/******************* Bit definition for ADC_VMHB register ********************/ +#define ADC_VMHB_VMHB_Pos (0U) +#define ADC_VMHB_VMHB_Msk (0xFFFFU << ADC_VMHB_VMHB_Pos) /*!< 0x0000FFFF */ +#define ADC_VMHB_VMHB ADC_VMHB_VMHB_Msk /*!< Voltage monitoring high boundary */ + +/******************* Bit definition for ADC_VMLB register ********************/ +#define ADC_VMLB_VMLB_Pos (0U) +#define ADC_VMLB_VMLB_Msk (0xFFFFU << ADC_VMLB_VMLB_Pos) /*!< 0x0000FFFF */ +#define ADC_VMLB_VMLB ADC_VMLB_VMLB_Msk /*!< Voltage monitoring low boundary */ + +/******************* Bit definition for ADC_OSQ1 register *******************/ +/*!< OSN13 configuration */ +#define ADC_OSQ1_OSN13_Pos (0U) +#define ADC_OSQ1_OSN13_Msk (0x1FU << ADC_OSQ1_OSN13_Pos) /*!< 0x0000001F */ +#define ADC_OSQ1_OSN13 ADC_OSQ1_OSN13_Msk /*!< OSN13[4:0] bits (Number of 13th conversion in ordinary sequence) */ +#define ADC_OSQ1_OSN13_0 (0x01U << ADC_OSQ1_OSN13_Pos) /*!< 0x00000001 */ +#define ADC_OSQ1_OSN13_1 (0x02U << ADC_OSQ1_OSN13_Pos) /*!< 0x00000002 */ +#define ADC_OSQ1_OSN13_2 (0x04U << ADC_OSQ1_OSN13_Pos) /*!< 0x00000004 */ +#define ADC_OSQ1_OSN13_3 (0x08U << ADC_OSQ1_OSN13_Pos) /*!< 0x00000008 */ +#define ADC_OSQ1_OSN13_4 (0x10U << ADC_OSQ1_OSN13_Pos) /*!< 0x00000010 */ + +/*!< OSN14 configuration */ +#define ADC_OSQ1_OSN14_Pos (5U) +#define ADC_OSQ1_OSN14_Msk (0x1FU << ADC_OSQ1_OSN14_Pos) /*!< 0x000003E0 */ +#define ADC_OSQ1_OSN14 ADC_OSQ1_OSN14_Msk /*!< OSN14[4:0] bits (Number of 14th conversion in ordinary sequence) */ +#define ADC_OSQ1_OSN14_0 (0x01U << ADC_OSQ1_OSN14_Pos) /*!< 0x00000020 */ +#define ADC_OSQ1_OSN14_1 (0x02U << ADC_OSQ1_OSN14_Pos) /*!< 0x00000040 */ +#define ADC_OSQ1_OSN14_2 (0x04U << ADC_OSQ1_OSN14_Pos) /*!< 0x00000080 */ +#define ADC_OSQ1_OSN14_3 (0x08U << ADC_OSQ1_OSN14_Pos) /*!< 0x00000100 */ +#define ADC_OSQ1_OSN14_4 (0x10U << ADC_OSQ1_OSN14_Pos) /*!< 0x00000200 */ + +/*!< OSN15 configuration */ +#define ADC_OSQ1_OSN15_Pos (10U) +#define ADC_OSQ1_OSN15_Msk (0x1FU << ADC_OSQ1_OSN15_Pos) /*!< 0x00007C00 */ +#define ADC_OSQ1_OSN15 ADC_OSQ1_OSN15_Msk /*!< OSN15[4:0] bits (Number of 15th conversion in ordinary sequence) */ +#define ADC_OSQ1_OSN15_0 (0x01U << ADC_OSQ1_OSN15_Pos) /*!< 0x00000400 */ +#define ADC_OSQ1_OSN15_1 (0x02U << ADC_OSQ1_OSN15_Pos) /*!< 0x00000800 */ +#define ADC_OSQ1_OSN15_2 (0x04U << ADC_OSQ1_OSN15_Pos) /*!< 0x00001000 */ +#define ADC_OSQ1_OSN15_3 (0x08U << ADC_OSQ1_OSN15_Pos) /*!< 0x00002000 */ +#define ADC_OSQ1_OSN15_4 (0x10U << ADC_OSQ1_OSN15_Pos) /*!< 0x00004000 */ + +/*!< OSN16 configuration */ +#define ADC_OSQ1_OSN16_Pos (15U) +#define ADC_OSQ1_OSN16_Msk (0x1FU << ADC_OSQ1_OSN16_Pos) /*!< 0x000F8000 */ +#define ADC_OSQ1_OSN16 ADC_OSQ1_OSN16_Msk /*!< OSN16[4:0] bits (Number of 16th conversion in ordinary sequence) */ +#define ADC_OSQ1_OSN16_0 (0x01U << ADC_OSQ1_OSN16_Pos) /*!< 0x00008000 */ +#define ADC_OSQ1_OSN16_1 (0x02U << ADC_OSQ1_OSN16_Pos) /*!< 0x00010000 */ +#define ADC_OSQ1_OSN16_2 (0x04U << ADC_OSQ1_OSN16_Pos) /*!< 0x00020000 */ +#define ADC_OSQ1_OSN16_3 (0x08U << ADC_OSQ1_OSN16_Pos) /*!< 0x00040000 */ +#define ADC_OSQ1_OSN16_4 (0x10U << ADC_OSQ1_OSN16_Pos) /*!< 0x00080000 */ + +/*!< OCLEN configuration */ +#define ADC_OSQ1_OCLEN_Pos (20U) +#define ADC_OSQ1_OCLEN_Msk (0xFU << ADC_OSQ1_OCLEN_Pos) /*!< 0x00F00000 */ +#define ADC_OSQ1_OCLEN ADC_OSQ1_OCLEN_Msk /*!< OCLEN[3:0] bits (Ordinary conversion sequence length) */ +#define ADC_OSQ1_OCLEN_0 (0x1U << ADC_OSQ1_OCLEN_Pos) /*!< 0x00100000 */ +#define ADC_OSQ1_OCLEN_1 (0x2U << ADC_OSQ1_OCLEN_Pos) /*!< 0x00200000 */ +#define ADC_OSQ1_OCLEN_2 (0x4U << ADC_OSQ1_OCLEN_Pos) /*!< 0x00400000 */ +#define ADC_OSQ1_OCLEN_3 (0x8U << ADC_OSQ1_OCLEN_Pos) /*!< 0x00800000 */ + +/******************* Bit definition for ADC_OSQ2 register *******************/ +/*!< OSN7 configuration */ +#define ADC_OSQ2_OSN7_Pos (0U) +#define ADC_OSQ2_OSN7_Msk (0x1FU << ADC_OSQ2_OSN7_Pos) /*!< 0x0000001F */ +#define ADC_OSQ2_OSN7 ADC_OSQ2_OSN7_Msk /*!< OSN7[4:0] bits (Number of 7th conversion in ordinary sequence) */ +#define ADC_OSQ2_OSN7_0 (0x01U << ADC_OSQ2_OSN7_Pos) /*!< 0x00000001 */ +#define ADC_OSQ2_OSN7_1 (0x02U << ADC_OSQ2_OSN7_Pos) /*!< 0x00000002 */ +#define ADC_OSQ2_OSN7_2 (0x04U << ADC_OSQ2_OSN7_Pos) /*!< 0x00000004 */ +#define ADC_OSQ2_OSN7_3 (0x08U << ADC_OSQ2_OSN7_Pos) /*!< 0x00000008 */ +#define ADC_OSQ2_OSN7_4 (0x10U << ADC_OSQ2_OSN7_Pos) /*!< 0x00000010 */ + +/*!< OSN8 configuration */ +#define ADC_OSQ2_OSN8_Pos (5U) +#define ADC_OSQ2_OSN8_Msk (0x1FU << ADC_OSQ2_OSN8_Pos) /*!< 0x000003E0 */ +#define ADC_OSQ2_OSN8 ADC_OSQ2_OSN8_Msk /*!< OSN8[4:0] bits (Number of 8th conversion in ordinary sequence) */ +#define ADC_OSQ2_OSN8_0 (0x01U << ADC_OSQ2_OSN8_Pos) /*!< 0x00000020 */ +#define ADC_OSQ2_OSN8_1 (0x02U << ADC_OSQ2_OSN8_Pos) /*!< 0x00000040 */ +#define ADC_OSQ2_OSN8_2 (0x04U << ADC_OSQ2_OSN8_Pos) /*!< 0x00000080 */ +#define ADC_OSQ2_OSN8_3 (0x08U << ADC_OSQ2_OSN8_Pos) /*!< 0x00000100 */ +#define ADC_OSQ2_OSN8_4 (0x10U << ADC_OSQ2_OSN8_Pos) /*!< 0x00000200 */ + +/*!< OSN9 configuration */ +#define ADC_OSQ2_OSN9_Pos (10U) +#define ADC_OSQ2_OSN9_Msk (0x1FU << ADC_OSQ2_OSN9_Pos) /*!< 0x00007C00 */ +#define ADC_OSQ2_OSN9 ADC_OSQ2_OSN9_Msk /*!< OSN9[4:0] bits (Number of 9th conversion in ordinary sequence) */ +#define ADC_OSQ2_OSN9_0 (0x01U << ADC_OSQ2_OSN9_Pos) /*!< 0x00000400 */ +#define ADC_OSQ2_OSN9_1 (0x02U << ADC_OSQ2_OSN9_Pos) /*!< 0x00000800 */ +#define ADC_OSQ2_OSN9_2 (0x04U << ADC_OSQ2_OSN9_Pos) /*!< 0x00001000 */ +#define ADC_OSQ2_OSN9_3 (0x08U << ADC_OSQ2_OSN9_Pos) /*!< 0x00002000 */ +#define ADC_OSQ2_OSN9_4 (0x10U << ADC_OSQ2_OSN9_Pos) /*!< 0x00004000 */ + +/*!< OSN10 configuration */ +#define ADC_OSQ2_OSN10_Pos (15U) +#define ADC_OSQ2_OSN10_Msk (0x1FU << ADC_OSQ2_OSN10_Pos) /*!< 0x000F8000 */ +#define ADC_OSQ2_OSN10 ADC_OSQ2_OSN10_Msk /*!< OSN10[4:0] bits (Number of 10th conversion in ordinary sequence) */ +#define ADC_OSQ2_OSN10_0 (0x01U << ADC_OSQ2_OSN10_Pos) /*!< 0x00008000 */ +#define ADC_OSQ2_OSN10_1 (0x02U << ADC_OSQ2_OSN10_Pos) /*!< 0x00010000 */ +#define ADC_OSQ2_OSN10_2 (0x04U << ADC_OSQ2_OSN10_Pos) /*!< 0x00020000 */ +#define ADC_OSQ2_OSN10_3 (0x08U << ADC_OSQ2_OSN10_Pos) /*!< 0x00040000 */ +#define ADC_OSQ2_OSN10_4 (0x10U << ADC_OSQ2_OSN10_Pos) /*!< 0x00080000 */ + +/*!< OSN11 configuration */ +#define ADC_OSQ2_OSN11_Pos (20U) +#define ADC_OSQ2_OSN11_Msk (0x1FU << ADC_OSQ2_OSN11_Pos) /*!< 0x01F00000 */ +#define ADC_OSQ2_OSN11 ADC_OSQ2_OSN11_Msk /*!< OSN11[4:0] bits (Number of 11th conversion in ordinary sequence) */ +#define ADC_OSQ2_OSN11_0 (0x01U << ADC_OSQ2_OSN11_Pos) /*!< 0x00100000 */ +#define ADC_OSQ2_OSN11_1 (0x02U << ADC_OSQ2_OSN11_Pos) /*!< 0x00200000 */ +#define ADC_OSQ2_OSN11_2 (0x04U << ADC_OSQ2_OSN11_Pos) /*!< 0x00400000 */ +#define ADC_OSQ2_OSN11_3 (0x08U << ADC_OSQ2_OSN11_Pos) /*!< 0x00800000 */ +#define ADC_OSQ2_OSN11_4 (0x10U << ADC_OSQ2_OSN11_Pos) /*!< 0x01000000 */ + +/*!< OSN12 configuration */ +#define ADC_OSQ2_OSN12_Pos (25U) +#define ADC_OSQ2_OSN12_Msk (0x1FU << ADC_OSQ2_OSN12_Pos) /*!< 0x3E000000 */ +#define ADC_OSQ2_OSN12 ADC_OSQ2_OSN12_Msk /*!< OSN12[4:0] bits (Number of 12th conversion in ordinary sequence) */ +#define ADC_OSQ2_OSN12_0 (0x01U << ADC_OSQ2_OSN12_Pos) /*!< 0x02000000 */ +#define ADC_OSQ2_OSN12_1 (0x02U << ADC_OSQ2_OSN12_Pos) /*!< 0x04000000 */ +#define ADC_OSQ2_OSN12_2 (0x04U << ADC_OSQ2_OSN12_Pos) /*!< 0x08000000 */ +#define ADC_OSQ2_OSN12_3 (0x08U << ADC_OSQ2_OSN12_Pos) /*!< 0x10000000 */ +#define ADC_OSQ2_OSN12_4 (0x10U << ADC_OSQ2_OSN12_Pos) /*!< 0x20000000 */ + +/******************* Bit definition for ADC_OSQ3 register *******************/ +/*!< OSN1 configuration */ +#define ADC_OSQ3_OSN1_Pos (0U) +#define ADC_OSQ3_OSN1_Msk (0x1FU << ADC_OSQ3_OSN1_Pos) /*!< 0x0000001F */ +#define ADC_OSQ3_OSN1 ADC_OSQ3_OSN1_Msk /*!< OSN1[4:0] bits (Number of 1st conversion in ordinary sequence) */ +#define ADC_OSQ3_OSN1_0 (0x01U << ADC_OSQ3_OSN1_Pos) /*!< 0x00000001 */ +#define ADC_OSQ3_OSN1_1 (0x02U << ADC_OSQ3_OSN1_Pos) /*!< 0x00000002 */ +#define ADC_OSQ3_OSN1_2 (0x04U << ADC_OSQ3_OSN1_Pos) /*!< 0x00000004 */ +#define ADC_OSQ3_OSN1_3 (0x08U << ADC_OSQ3_OSN1_Pos) /*!< 0x00000008 */ +#define ADC_OSQ3_OSN1_4 (0x10U << ADC_OSQ3_OSN1_Pos) /*!< 0x00000010 */ + +/*!< OSN2 configuration */ +#define ADC_OSQ3_OSN2_Pos (5U) +#define ADC_OSQ3_OSN2_Msk (0x1FU << ADC_OSQ3_OSN2_Pos) /*!< 0x000003E0 */ +#define ADC_OSQ3_OSN2 ADC_OSQ3_OSN2_Msk /*!< OSN2[4:0] bits (Number of 2nd conversion in ordinary sequence) */ +#define ADC_OSQ3_OSN2_0 (0x01U << ADC_OSQ3_OSN2_Pos) /*!< 0x00000020 */ +#define ADC_OSQ3_OSN2_1 (0x02U << ADC_OSQ3_OSN2_Pos) /*!< 0x00000040 */ +#define ADC_OSQ3_OSN2_2 (0x04U << ADC_OSQ3_OSN2_Pos) /*!< 0x00000080 */ +#define ADC_OSQ3_OSN2_3 (0x08U << ADC_OSQ3_OSN2_Pos) /*!< 0x00000100 */ +#define ADC_OSQ3_OSN2_4 (0x10U << ADC_OSQ3_OSN2_Pos) /*!< 0x00000200 */ + +/*!< OSN3 configuration */ +#define ADC_OSQ3_OSN3_Pos (10U) +#define ADC_OSQ3_OSN3_Msk (0x1FU << ADC_OSQ3_OSN3_Pos) /*!< 0x00007C00 */ +#define ADC_OSQ3_OSN3 ADC_OSQ3_OSN3_Msk /*!< OSN3[4:0] bits (Number of 3rd conversion in ordinary sequence) */ +#define ADC_OSQ3_OSN3_0 (0x01U << ADC_OSQ3_OSN3_Pos) /*!< 0x00000400 */ +#define ADC_OSQ3_OSN3_1 (0x02U << ADC_OSQ3_OSN3_Pos) /*!< 0x00000800 */ +#define ADC_OSQ3_OSN3_2 (0x04U << ADC_OSQ3_OSN3_Pos) /*!< 0x00001000 */ +#define ADC_OSQ3_OSN3_3 (0x08U << ADC_OSQ3_OSN3_Pos) /*!< 0x00002000 */ +#define ADC_OSQ3_OSN3_4 (0x10U << ADC_OSQ3_OSN3_Pos) /*!< 0x00004000 */ + +/*!< OSN4 configuration */ +#define ADC_OSQ3_OSN4_Pos (15U) +#define ADC_OSQ3_OSN4_Msk (0x1FU << ADC_OSQ3_OSN4_Pos) /*!< 0x000F8000 */ +#define ADC_OSQ3_OSN4 ADC_OSQ3_OSN4_Msk /*!< OSN4[4:0] bits (Number of 4th conversion in ordinary sequence) */ +#define ADC_OSQ3_OSN4_0 (0x01U << ADC_OSQ3_OSN4_Pos) /*!< 0x00008000 */ +#define ADC_OSQ3_OSN4_1 (0x02U << ADC_OSQ3_OSN4_Pos) /*!< 0x00010000 */ +#define ADC_OSQ3_OSN4_2 (0x04U << ADC_OSQ3_OSN4_Pos) /*!< 0x00020000 */ +#define ADC_OSQ3_OSN4_3 (0x08U << ADC_OSQ3_OSN4_Pos) /*!< 0x00040000 */ +#define ADC_OSQ3_OSN4_4 (0x10U << ADC_OSQ3_OSN4_Pos) /*!< 0x00080000 */ + +/*!< OSN5 configuration */ +#define ADC_OSQ3_OSN5_Pos (20U) +#define ADC_OSQ3_OSN5_Msk (0x1FU << ADC_OSQ3_OSN5_Pos) /*!< 0x01F00000 */ +#define ADC_OSQ3_OSN5 ADC_OSQ3_OSN5_Msk /*!< OSN5[4:0] bits (Number of 5th conversion in ordinary sequence) */ +#define ADC_OSQ3_OSN5_0 (0x01U << ADC_OSQ3_OSN5_Pos) /*!< 0x00100000 */ +#define ADC_OSQ3_OSN5_1 (0x02U << ADC_OSQ3_OSN5_Pos) /*!< 0x00200000 */ +#define ADC_OSQ3_OSN5_2 (0x04U << ADC_OSQ3_OSN5_Pos) /*!< 0x00400000 */ +#define ADC_OSQ3_OSN5_3 (0x08U << ADC_OSQ3_OSN5_Pos) /*!< 0x00800000 */ +#define ADC_OSQ3_OSN5_4 (0x10U << ADC_OSQ3_OSN5_Pos) /*!< 0x01000000 */ + +/*!< OSN6 configuration */ +#define ADC_OSQ3_OSN6_Pos (25U) +#define ADC_OSQ3_OSN6_Msk (0x1FU << ADC_OSQ3_OSN6_Pos) /*!< 0x3E000000 */ +#define ADC_OSQ3_OSN6 ADC_OSQ3_OSN6_Msk /*!< OSN6[4:0] bits (Number of 6th conversion in ordinary sequence) */ +#define ADC_OSQ3_OSN6_0 (0x01U << ADC_OSQ3_OSN6_Pos) /*!< 0x02000000 */ +#define ADC_OSQ3_OSN6_1 (0x02U << ADC_OSQ3_OSN6_Pos) /*!< 0x04000000 */ +#define ADC_OSQ3_OSN6_2 (0x04U << ADC_OSQ3_OSN6_Pos) /*!< 0x08000000 */ +#define ADC_OSQ3_OSN6_3 (0x08U << ADC_OSQ3_OSN6_Pos) /*!< 0x10000000 */ +#define ADC_OSQ3_OSN6_4 (0x10U << ADC_OSQ3_OSN6_Pos) /*!< 0x20000000 */ + +/******************* Bit definition for ADC_PSQ register ********************/ +/*!< PSN1 configuration */ +#define ADC_PSQ_PSN1_Pos (0U) +#define ADC_PSQ_PSN1_Msk (0x1FU << ADC_PSQ_PSN1_Pos) /*!< 0x0000001F */ +#define ADC_PSQ_PSN1 ADC_PSQ_PSN1_Msk /*!< PSN1[4:0] bits (Number of 1st conversion in preempted sequence) */ +#define ADC_PSQ_PSN1_0 (0x01U << ADC_PSQ_PSN1_Pos) /*!< 0x00000001 */ +#define ADC_PSQ_PSN1_1 (0x02U << ADC_PSQ_PSN1_Pos) /*!< 0x00000002 */ +#define ADC_PSQ_PSN1_2 (0x04U << ADC_PSQ_PSN1_Pos) /*!< 0x00000004 */ +#define ADC_PSQ_PSN1_3 (0x08U << ADC_PSQ_PSN1_Pos) /*!< 0x00000008 */ +#define ADC_PSQ_PSN1_4 (0x10U << ADC_PSQ_PSN1_Pos) /*!< 0x00000010 */ + +/*!< PSN2 configuration */ +#define ADC_PSQ_PSN2_Pos (5U) +#define ADC_PSQ_PSN2_Msk (0x1FU << ADC_PSQ_PSN2_Pos) /*!< 0x000003E0 */ +#define ADC_PSQ_PSN2 ADC_PSQ_PSN2_Msk /*!< PSN2[4:0] bits (Number of 2nd conversion in preempted sequence) */ +#define ADC_PSQ_PSN2_0 (0x01U << ADC_PSQ_PSN2_Pos) /*!< 0x00000020 */ +#define ADC_PSQ_PSN2_1 (0x02U << ADC_PSQ_PSN2_Pos) /*!< 0x00000040 */ +#define ADC_PSQ_PSN2_2 (0x04U << ADC_PSQ_PSN2_Pos) /*!< 0x00000080 */ +#define ADC_PSQ_PSN2_3 (0x08U << ADC_PSQ_PSN2_Pos) /*!< 0x00000100 */ +#define ADC_PSQ_PSN2_4 (0x10U << ADC_PSQ_PSN2_Pos) /*!< 0x00000200 */ + +/*!< PSN3 configuration */ +#define ADC_PSQ_PSN3_Pos (10U) +#define ADC_PSQ_PSN3_Msk (0x1FU << ADC_PSQ_PSN3_Pos) /*!< 0x00007C00 */ +#define ADC_PSQ_PSN3 ADC_PSQ_PSN3_Msk /*!< PSN3[4:0] bits (Number of 3rd conversion in preempted sequence) */ +#define ADC_PSQ_PSN3_0 (0x01U << ADC_PSQ_PSN3_Pos) /*!< 0x00000400 */ +#define ADC_PSQ_PSN3_1 (0x02U << ADC_PSQ_PSN3_Pos) /*!< 0x00000800 */ +#define ADC_PSQ_PSN3_2 (0x04U << ADC_PSQ_PSN3_Pos) /*!< 0x00001000 */ +#define ADC_PSQ_PSN3_3 (0x08U << ADC_PSQ_PSN3_Pos) /*!< 0x00002000 */ +#define ADC_PSQ_PSN3_4 (0x10U << ADC_PSQ_PSN3_Pos) /*!< 0x00004000 */ + +/*!< PSN4 configuration */ +#define ADC_PSQ_PSN4_Pos (15U) +#define ADC_PSQ_PSN4_Msk (0x1FU << ADC_PSQ_PSN4_Pos) /*!< 0x000F8000 */ +#define ADC_PSQ_PSN4 ADC_PSQ_PSN4_Msk /*!< PSN4[4:0] bits (Number of 4th conversion in preempted sequence) */ +#define ADC_PSQ_PSN4_0 (0x01U << ADC_PSQ_PSN4_Pos) /*!< 0x00008000 */ +#define ADC_PSQ_PSN4_1 (0x02U << ADC_PSQ_PSN4_Pos) /*!< 0x00010000 */ +#define ADC_PSQ_PSN4_2 (0x04U << ADC_PSQ_PSN4_Pos) /*!< 0x00020000 */ +#define ADC_PSQ_PSN4_3 (0x08U << ADC_PSQ_PSN4_Pos) /*!< 0x00040000 */ +#define ADC_PSQ_PSN4_4 (0x10U << ADC_PSQ_PSN4_Pos) /*!< 0x00080000 */ + +/*!< PCLEN configuration */ +#define ADC_PSQ_PCLEN_Pos (20U) +#define ADC_PSQ_PCLEN_Msk (0x3U << ADC_PSQ_PCLEN_Pos) /*!< 0x00300000 */ +#define ADC_PSQ_PCLEN ADC_PSQ_PCLEN_Msk /*!< PCLEN[1:0] bits (Preempted conversion sequence length) */ +#define ADC_PSQ_PCLEN_0 (0x1U << ADC_PSQ_PCLEN_Pos) /*!< 0x00100000 */ +#define ADC_PSQ_PCLEN_1 (0x2U << ADC_PSQ_PCLEN_Pos) /*!< 0x00200000 */ + +/******************* Bit definition for ADC_PDT1 register *******************/ +#define ADC_PDT1_PDT1_Pos (0U) +#define ADC_PDT1_PDT1_Msk (0xFFFFU << ADC_PDT1_PDT1_Pos) /*!< 0x0000FFFF */ +#define ADC_PDT1_PDT1 ADC_PDT1_PDT1_Msk /*!< Conversion data from preempted channel 1 */ + +/******************* Bit definition for ADC_PDT2 register *******************/ +#define ADC_PDT2_PDT2_Pos (0U) +#define ADC_PDT2_PDT2_Msk (0xFFFFU << ADC_PDT2_PDT2_Pos) /*!< 0x0000FFFF */ +#define ADC_PDT2_PDT2 ADC_PDT2_PDT2_Msk /*!< Conversion data from preempted channel 2 */ + +/******************* Bit definition for ADC_PDT3 register *******************/ +#define ADC_PDT3_PDT3_Pos (0U) +#define ADC_PDT3_PDT3_Msk (0xFFFFU << ADC_PDT3_PDT3_Pos) /*!< 0x0000FFFF */ +#define ADC_PDT3_PDT3 ADC_PDT3_PDT3_Msk /*!< Conversion data from preempted channel 3 */ + +/******************* Bit definition for ADC_PDT4 register *******************/ +#define ADC_PDT4_PDT4_Pos (0U) +#define ADC_PDT4_PDT4_Msk (0xFFFFU << ADC_PDT4_PDT4_Pos) /*!< 0x0000FFFF */ +#define ADC_PDT4_PDT4 ADC_PDT4_PDT4_Msk /*!< Conversion data from preempted channel 4 */ + +/******************* Bit definition for ADC_ODT register ********************/ +#define ADC_ODT_ODT_Pos (0U) +#define ADC_ODT_ODT_Msk (0xFFFFU << ADC_ODT_ODT_Pos) /*!< 0x0000FFFF */ +#define ADC_ODT_ODT ADC_ODT_ODT_Msk /*!< Conversion data of ordinary channel */ + +/******************* Bit definition for ADC_OVSP register *******************/ +#define ADC_OVSP_OOSEN_Pos (0U) +#define ADC_OVSP_OOSEN_Msk (0x1U << ADC_OVSP_OOSEN_Pos) /*!< 0x00000001 */ +#define ADC_OVSP_OOSEN ADC_OVSP_OOSEN_Msk /*!< Ordinary oversampling enable */ +#define ADC_OVSP_POSEN_Pos (1U) +#define ADC_OVSP_POSEN_Msk (0x1U << ADC_OVSP_POSEN_Pos) /*!< 0x00000002 */ +#define ADC_OVSP_POSEN ADC_OVSP_POSEN_Msk /*!< Preempted oversampling enable */ + +/*!< OSRSEL configuration */ +#define ADC_OVSP_OSRSEL_Pos (2U) +#define ADC_OVSP_OSRSEL_Msk (0x7U << ADC_OVSP_OSRSEL_Pos) /*!< 0x0000001C */ +#define ADC_OVSP_OSRSEL ADC_OVSP_OSRSEL_Msk /*!< OSRSEL[2:0] bits (Oversampling ratio select) */ +#define ADC_OVSP_OSRSEL_0 (0x1U << ADC_OVSP_OSRSEL_Pos) /*!< 0x00000004 */ +#define ADC_OVSP_OSRSEL_1 (0x2U << ADC_OVSP_OSRSEL_Pos) /*!< 0x00000008 */ +#define ADC_OVSP_OSRSEL_2 (0x4U << ADC_OVSP_OSRSEL_Pos) /*!< 0x00000010 */ + +#define ADC_OVSP_OSRSEL_MULTI2 0x00000000U /*!< 2x */ +#define ADC_OVSP_OSRSEL_MULTI4 0x00000004U /*!< 4x */ +#define ADC_OVSP_OSRSEL_MULTI8 0x00000008U /*!< 8x */ +#define ADC_OVSP_OSRSEL_MULTI16 0x0000000CU /*!< 16x */ +#define ADC_OVSP_OSRSEL_MULTI32 0x00000010U /*!< 32x */ +#define ADC_OVSP_OSRSEL_MULTI64 0x00000014U /*!< 64x */ +#define ADC_OVSP_OSRSEL_MULTI128 0x00000018U /*!< 128x */ +#define ADC_OVSP_OSRSEL_MULTI256 0x0000001CU /*!< 256x */ + +/*!< OSSSEL configuration */ +#define ADC_OVSP_OSSSEL_Pos (5U) +#define ADC_OVSP_OSSSEL_Msk (0xFU << ADC_OVSP_OSSSEL_Pos) /*!< 0x000001E0 */ +#define ADC_OVSP_OSSSEL ADC_OVSP_OSSSEL_Msk /*!< OSSSEL[3:0] bits (Oversampling shift select) */ +#define ADC_OVSP_OSSSEL_0 (0x1U << ADC_OVSP_OSSSEL_Pos) /*!< 0x00000020 */ +#define ADC_OVSP_OSSSEL_1 (0x2U << ADC_OVSP_OSSSEL_Pos) /*!< 0x00000040 */ +#define ADC_OVSP_OSSSEL_2 (0x4U << ADC_OVSP_OSSSEL_Pos) /*!< 0x00000080 */ +#define ADC_OVSP_OSSSEL_3 (0x8U << ADC_OVSP_OSSSEL_Pos) /*!< 0x00000100 */ + +#define ADC_OVSP_OSSSEL_NOSHIFT 0x00000000U /*!< No shift */ +#define ADC_OVSP_OSSSEL_SHIFT1 0x00000020U /*!< Shift 1 bit */ +#define ADC_OVSP_OSSSEL_SHIFT2 0x00000040U /*!< Shift 2 bit */ +#define ADC_OVSP_OSSSEL_SHIFT3 0x00000060U /*!< Shift 3 bit */ +#define ADC_OVSP_OSSSEL_SHIFT4 0x00000080U /*!< Shift 4 bit */ +#define ADC_OVSP_OSSSEL_SHIFT5 0x000000A0U /*!< Shift 5 bit */ +#define ADC_OVSP_OSSSEL_SHIFT6 0x000000C0U /*!< Shift 6 bit */ +#define ADC_OVSP_OSSSEL_SHIFT7 0x000000E0U /*!< Shift 7 bit */ +#define ADC_OVSP_OSSSEL_SHIFT8 0x00000100U /*!< Shift 8 bit */ + +#define ADC_OVSP_OOSTREN_Pos (9U) +#define ADC_OVSP_OOSTREN_Msk (0x1U << ADC_OVSP_OOSTREN_Pos) /*!< 0x00000200 */ +#define ADC_OVSP_OOSTREN ADC_OVSP_OOSTREN_Msk /*!< Ordinary oversampling trigger mode enable */ +#define ADC_OVSP_OOSRSEL_Pos (10U) +#define ADC_OVSP_OOSRSEL_Msk (0x1U << ADC_OVSP_OOSRSEL_Pos) /*!< 0x00000400 */ +#define ADC_OVSP_OOSRSEL ADC_OVSP_OOSRSEL_Msk /*!< Ordinary oversampling restart mode select */ + +/****************** Bit definition for ADC_CCTRL register *******************/ +/*!< ADCDIV configuration */ +#define ADC_CCTRL_ADCDIV_Pos (16U) +#define ADC_CCTRL_ADCDIV_Msk (0xFU << ADC_CCTRL_ADCDIV_Pos) /*!< 0x000F0000 */ +#define ADC_CCTRL_ADCDIV ADC_CCTRL_ADCDIV_Msk /*!< ADCDIV[3:0] bits (ADC division) */ +#define ADC_CCTRL_ADCDIV_0 (0x1U << ADC_CCTRL_ADCDIV_Pos) /*!< 0x00010000 */ +#define ADC_CCTRL_ADCDIV_1 (0x2U << ADC_CCTRL_ADCDIV_Pos) /*!< 0x00020000 */ +#define ADC_CCTRL_ADCDIV_2 (0x4U << ADC_CCTRL_ADCDIV_Pos) /*!< 0x00040000 */ +#define ADC_CCTRL_ADCDIV_3 (0x8U << ADC_CCTRL_ADCDIV_Pos) /*!< 0x00080000 */ + +#define ADC_CCTRL_ADCDIV_DIV2 0x00000000U /*!< HCLK/2 */ +#define ADC_CCTRL_ADCDIV_DIV3 0x00010000U /*!< HCLK/3 */ +#define ADC_CCTRL_ADCDIV_DIV4 0x00020000U /*!< HCLK/4 */ +#define ADC_CCTRL_ADCDIV_DIV5 0x00030000U /*!< HCLK/5 */ +#define ADC_CCTRL_ADCDIV_DIV6 0x00040000U /*!< HCLK/6 */ +#define ADC_CCTRL_ADCDIV_DIV7 0x00050000U /*!< HCLK/7 */ +#define ADC_CCTRL_ADCDIV_DIV8 0x00060000U /*!< HCLK/8 */ +#define ADC_CCTRL_ADCDIV_DIV9 0x00070000U /*!< HCLK/9 */ +#define ADC_CCTRL_ADCDIV_DIV10 0x00080000U /*!< HCLK/10 */ +#define ADC_CCTRL_ADCDIV_DIV11 0x00090000U /*!< HCLK/11 */ +#define ADC_CCTRL_ADCDIV_DIV12 0x000A0000U /*!< HCLK/12 */ +#define ADC_CCTRL_ADCDIV_DIV13 0x000B0000U /*!< HCLK/13 */ +#define ADC_CCTRL_ADCDIV_DIV14 0x000C0000U /*!< HCLK/14 */ +#define ADC_CCTRL_ADCDIV_DIV15 0x000D0000U /*!< HCLK/15 */ +#define ADC_CCTRL_ADCDIV_DIV16 0x000E0000U /*!< HCLK/16 */ +#define ADC_CCTRL_ADCDIV_DIV17 0x000F0000U /*!< HCLK/17 */ + +/******************************************************************************/ +/* */ +/* Controller Area Network (CAN) */ +/* */ +/******************************************************************************/ + +/*!< CAN control and status registers */ +/****************** Bit definition for CAN_MCTRL register *******************/ +#define CAN_MCTRL_FZEN_Pos (0U) +#define CAN_MCTRL_FZEN_Msk (0x1U << CAN_MCTRL_FZEN_Pos) /*!< 0x00000001 */ +#define CAN_MCTRL_FZEN CAN_MCTRL_FZEN_Msk /*!< Freeze mode enable */ +#define CAN_MCTRL_DZEN_Pos (1U) +#define CAN_MCTRL_DZEN_Msk (0x1U << CAN_MCTRL_DZEN_Pos) /*!< 0x00000002 */ +#define CAN_MCTRL_DZEN CAN_MCTRL_DZEN_Msk /*!< Doze mode enable */ +#define CAN_MCTRL_MMSSR_Pos (2U) +#define CAN_MCTRL_MMSSR_Msk (0x1U << CAN_MCTRL_MMSSR_Pos) /*!< 0x00000004 */ +#define CAN_MCTRL_MMSSR CAN_MCTRL_MMSSR_Msk /*!< Multiple message transmit sequence rule */ +#define CAN_MCTRL_MDRSEL_Pos (3U) +#define CAN_MCTRL_MDRSEL_Msk (0x1U << CAN_MCTRL_MDRSEL_Pos) /*!< 0x00000008 */ +#define CAN_MCTRL_MDRSEL CAN_MCTRL_MDRSEL_Msk /*!< Message discard rule select when overflow */ +#define CAN_MCTRL_PRSFEN_Pos (4U) +#define CAN_MCTRL_PRSFEN_Msk (0x1U << CAN_MCTRL_PRSFEN_Pos) /*!< 0x00000010 */ +#define CAN_MCTRL_PRSFEN CAN_MCTRL_PRSFEN_Msk /*!< Prohibit retransmission enable when sending fails enable */ +#define CAN_MCTRL_AEDEN_Pos (5U) +#define CAN_MCTRL_AEDEN_Msk (0x1U << CAN_MCTRL_AEDEN_Pos) /*!< 0x00000020 */ +#define CAN_MCTRL_AEDEN CAN_MCTRL_AEDEN_Msk /*!< Automatic exit doze mode enable */ +#define CAN_MCTRL_AEBOEN_Pos (6U) +#define CAN_MCTRL_AEBOEN_Msk (0x1U << CAN_MCTRL_AEBOEN_Pos) /*!< 0x00000040 */ +#define CAN_MCTRL_AEBOEN CAN_MCTRL_AEBOEN_Msk /*!< Automatic exit bus-off enable */ +#define CAN_MCTRL_TTCEN_Pos (7U) +#define CAN_MCTRL_TTCEN_Msk (0x1U << CAN_MCTRL_TTCEN_Pos) /*!< 0x00000080 */ +#define CAN_MCTRL_TTCEN CAN_MCTRL_TTCEN_Msk /*!< Time triggered communication mode enable */ +#define CAN_MCTRL_SPRST_Pos (15U) +#define CAN_MCTRL_SPRST_Msk (0x1U << CAN_MCTRL_SPRST_Pos) /*!< 0x00008000 */ +#define CAN_MCTRL_SPRST CAN_MCTRL_SPRST_Msk /*!< Software partial reset */ +#define CAN_MCTRL_PTD_Pos (16U) +#define CAN_MCTRL_PTD_Msk (0x1U << CAN_MCTRL_PTD_Pos) /*!< 0x00010000 */ +#define CAN_MCTRL_PTD CAN_MCTRL_PTD_Msk /*!< Prohibit trans when debug */ + +/******************* Bit definition for CAN_MSTS register *******************/ +#define CAN_MSTS_FZC_Pos (0U) +#define CAN_MSTS_FZC_Msk (0x1U << CAN_MSTS_FZC_Pos) /*!< 0x00000001 */ +#define CAN_MSTS_FZC CAN_MSTS_FZC_Msk /*!< Freeze mode confirm */ +#define CAN_MSTS_DZC_Pos (1U) +#define CAN_MSTS_DZC_Msk (0x1U << CAN_MSTS_DZC_Pos) /*!< 0x00000002 */ +#define CAN_MSTS_DZC CAN_MSTS_DZC_Msk /*!< Doze mode acknowledge */ +#define CAN_MSTS_EOIF_Pos (2U) +#define CAN_MSTS_EOIF_Msk (0x1U << CAN_MSTS_EOIF_Pos) /*!< 0x00000004 */ +#define CAN_MSTS_EOIF CAN_MSTS_EOIF_Msk /*!< Error occur interrupt flag */ +#define CAN_MSTS_QDZIF_Pos (3U) +#define CAN_MSTS_QDZIF_Msk (0x1U << CAN_MSTS_QDZIF_Pos) /*!< 0x00000008 */ +#define CAN_MSTS_QDZIF CAN_MSTS_QDZIF_Msk /*!< Exit doze mode interrupt flag */ +#define CAN_MSTS_EDZIF_Pos (4U) +#define CAN_MSTS_EDZIF_Msk (0x1U << CAN_MSTS_EDZIF_Pos) /*!< 0x00000010 */ +#define CAN_MSTS_EDZIF CAN_MSTS_EDZIF_Msk /*!< Enter doze mode interrupt flag */ +#define CAN_MSTS_CUSS_Pos (8U) +#define CAN_MSTS_CUSS_Msk (0x1U << CAN_MSTS_CUSS_Pos) /*!< 0x00000100 */ +#define CAN_MSTS_CUSS CAN_MSTS_CUSS_Msk /*!< Current transmit status */ +#define CAN_MSTS_CURS_Pos (9U) +#define CAN_MSTS_CURS_Msk (0x1U << CAN_MSTS_CURS_Pos) /*!< 0x00000200 */ +#define CAN_MSTS_CURS CAN_MSTS_CURS_Msk /*!< Current receive status */ +#define CAN_MSTS_LSAMPRX_Pos (10U) +#define CAN_MSTS_LSAMPRX_Msk (0x1U << CAN_MSTS_LSAMPRX_Pos) /*!< 0x00000400 */ +#define CAN_MSTS_LSAMPRX CAN_MSTS_LSAMPRX_Msk /*!< Last sample level on RX pin */ +#define CAN_MSTS_REALRX_Pos (11U) +#define CAN_MSTS_REALRX_Msk (0x1U << CAN_MSTS_REALRX_Pos) /*!< 0x00000800 */ +#define CAN_MSTS_REALRX CAN_MSTS_REALRX_Msk /*!< Real time level on RX pin */ + +/******************* Bit definition for CAN_TSTS register *******************/ +#define CAN_TSTS_TM0TCF_Pos (0U) +#define CAN_TSTS_TM0TCF_Msk (0x1U << CAN_TSTS_TM0TCF_Pos) /*!< 0x00000001 */ +#define CAN_TSTS_TM0TCF CAN_TSTS_TM0TCF_Msk /*!< Transmit mailbox 0 transmission completed flag */ +#define CAN_TSTS_TM0TSF_Pos (1U) +#define CAN_TSTS_TM0TSF_Msk (0x1U << CAN_TSTS_TM0TSF_Pos) /*!< 0x00000002 */ +#define CAN_TSTS_TM0TSF CAN_TSTS_TM0TSF_Msk /*!< Transmit mailbox 0 transmission success flag */ +#define CAN_TSTS_TM0ALF_Pos (2U) +#define CAN_TSTS_TM0ALF_Msk (0x1U << CAN_TSTS_TM0ALF_Pos) /*!< 0x00000004 */ +#define CAN_TSTS_TM0ALF CAN_TSTS_TM0ALF_Msk /*!< Transmit mailbox 0 arbitration lost flag */ +#define CAN_TSTS_TM0TEF_Pos (3U) +#define CAN_TSTS_TM0TEF_Msk (0x1U << CAN_TSTS_TM0TEF_Pos) /*!< 0x00000008 */ +#define CAN_TSTS_TM0TEF CAN_TSTS_TM0TEF_Msk /*!< Transmit mailbox 0 transmission error flag */ +#define CAN_TSTS_TM0CT_Pos (7U) +#define CAN_TSTS_TM0CT_Msk (0x1U << CAN_TSTS_TM0CT_Pos) /*!< 0x00000080 */ +#define CAN_TSTS_TM0CT CAN_TSTS_TM0CT_Msk /*!< Transmit mailbox 0 cancel transmit */ +#define CAN_TSTS_TM1TCF_Pos (8U) +#define CAN_TSTS_TM1TCF_Msk (0x1U << CAN_TSTS_TM1TCF_Pos) /*!< 0x00000100 */ +#define CAN_TSTS_TM1TCF CAN_TSTS_TM1TCF_Msk /*!< Transmit mailbox 1 transmission completed flag */ +#define CAN_TSTS_TM1TSF_Pos (9U) +#define CAN_TSTS_TM1TSF_Msk (0x1U << CAN_TSTS_TM1TSF_Pos) /*!< 0x00000200 */ +#define CAN_TSTS_TM1TSF CAN_TSTS_TM1TSF_Msk /*!< Transmit mailbox 1 transmission success flag */ +#define CAN_TSTS_TM1ALF_Pos (10U) +#define CAN_TSTS_TM1ALF_Msk (0x1U << CAN_TSTS_TM1ALF_Pos) /*!< 0x00000400 */ +#define CAN_TSTS_TM1ALF CAN_TSTS_TM1ALF_Msk /*!< Transmit mailbox 1 arbitration lost flag */ +#define CAN_TSTS_TM1TEF_Pos (11U) +#define CAN_TSTS_TM1TEF_Msk (0x1U << CAN_TSTS_TM1TEF_Pos) /*!< 0x00000800 */ +#define CAN_TSTS_TM1TEF CAN_TSTS_TM1TEF_Msk /*!< Transmit mailbox 1 transmission error flag */ +#define CAN_TSTS_TM1CT_Pos (15U) +#define CAN_TSTS_TM1CT_Msk (0x1U << CAN_TSTS_TM1CT_Pos) /*!< 0x00008000 */ +#define CAN_TSTS_TM1CT CAN_TSTS_TM1CT_Msk /*!< Transmit mailbox 1 cancel transmit */ +#define CAN_TSTS_TM2TCF_Pos (16U) +#define CAN_TSTS_TM2TCF_Msk (0x1U << CAN_TSTS_TM2TCF_Pos) /*!< 0x00010000 */ +#define CAN_TSTS_TM2TCF CAN_TSTS_TM2TCF_Msk /*!< Transmit mailbox 2 transmission completed flag */ +#define CAN_TSTS_TM2TSF_Pos (17U) +#define CAN_TSTS_TM2TSF_Msk (0x1U << CAN_TSTS_TM2TSF_Pos) /*!< 0x00020000 */ +#define CAN_TSTS_TM2TSF CAN_TSTS_TM2TSF_Msk /*!< Transmit mailbox 2 transmission success flag */ +#define CAN_TSTS_TM2ALF_Pos (18U) +#define CAN_TSTS_TM2ALF_Msk (0x1U << CAN_TSTS_TM2ALF_Pos) /*!< 0x00040000 */ +#define CAN_TSTS_TM2ALF CAN_TSTS_TM2ALF_Msk /*!< Transmit mailbox 2 arbitration lost flag */ +#define CAN_TSTS_TM2TEF_Pos (19U) +#define CAN_TSTS_TM2TEF_Msk (0x1U << CAN_TSTS_TM2TEF_Pos) /*!< 0x00080000 */ +#define CAN_TSTS_TM2TEF CAN_TSTS_TM2TEF_Msk /*!< Transmit mailbox 2 transmission error flag */ +#define CAN_TSTS_TM2CT_Pos (23U) +#define CAN_TSTS_TM2CT_Msk (0x1U << CAN_TSTS_TM2CT_Pos) /*!< 0x00800000 */ +#define CAN_TSTS_TM2CT CAN_TSTS_TM2CT_Msk /*!< Transmit mailbox 2 cancel transmit */ +#define CAN_TSTS_TMNR_Pos (24U) +#define CAN_TSTS_TMNR_Msk (0x3U << CAN_TSTS_TMNR_Pos) /*!< 0x03000000 */ +#define CAN_TSTS_TMNR CAN_TSTS_TMNR_Msk /*!< TMNR[1:0] bits (Transmit mailbox number record) */ + +/*!< TMEF congiguration */ +#define CAN_TSTS_TMEF_Pos (26U) +#define CAN_TSTS_TMEF_Msk (0x7U << CAN_TSTS_TMEF_Pos) /*!< 0x1C000000 */ +#define CAN_TSTS_TMEF CAN_TSTS_TMEF_Msk /*!< TMEF[2:0] bits (Transmit mailbox empty flag) */ +#define CAN_TSTS_TM0EF_Pos (26U) +#define CAN_TSTS_TM0EF_Msk (0x1U << CAN_TSTS_TM0EF_Pos) /*!< 0x04000000 */ +#define CAN_TSTS_TM0EF CAN_TSTS_TM0EF_Msk /*!< Transmit mailbox 0 empty flag */ +#define CAN_TSTS_TM1EF_Pos (27U) +#define CAN_TSTS_TM1EF_Msk (0x1U << CAN_TSTS_TM1EF_Pos) /*!< 0x08000000 */ +#define CAN_TSTS_TM1EF CAN_TSTS_TM1EF_Msk /*!< Transmit mailbox 1 empty flag */ +#define CAN_TSTS_TM2EF_Pos (28U) +#define CAN_TSTS_TM2EF_Msk (0x1U << CAN_TSTS_TM2EF_Pos) /*!< 0x10000000 */ +#define CAN_TSTS_TM2EF CAN_TSTS_TM2EF_Msk /*!< Transmit mailbox 2 empty flag */ + +/*!< TMLPF congiguration */ +#define CAN_TSTS_TMLPF_Pos (29U) +#define CAN_TSTS_TMLPF_Msk (0x7U << CAN_TSTS_TMLPF_Pos) /*!< 0xE0000000 */ +#define CAN_TSTS_TMLPF CAN_TSTS_TMLPF_Msk /*!< TMLPF[2:0] bits (Transmit mailbox lowest priority flag) */ +#define CAN_TSTS_TM0LPF_Pos (29U) +#define CAN_TSTS_TM0LPF_Msk (0x1U << CAN_TSTS_TM0LPF_Pos) /*!< 0x20000000 */ +#define CAN_TSTS_TM0LPF CAN_TSTS_TM0LPF_Msk /*!< Transmit mailbox 0 lowest priority flag */ +#define CAN_TSTS_TM1LPF_Pos (30U) +#define CAN_TSTS_TM1LPF_Msk (0x1U << CAN_TSTS_TM1LPF_Pos) /*!< 0x40000000 */ +#define CAN_TSTS_TM1LPF CAN_TSTS_TM1LPF_Msk /*!< Transmit mailbox 1 lowest priority flag */ +#define CAN_TSTS_TM2LPF_Pos (31U) +#define CAN_TSTS_TM2LPF_Msk (0x1U << CAN_TSTS_TM2LPF_Pos) /*!< 0x80000000 */ +#define CAN_TSTS_TM2LPF CAN_TSTS_TM2LPF_Msk /*!< Transmit mailbox 2 lowest priority flag */ + +/******************* Bit definition for CAN_RF0 register ********************/ +#define CAN_RF0_RF0MN_Pos (0U) +#define CAN_RF0_RF0MN_Msk (0x3U << CAN_RF0_RF0MN_Pos) /*!< 0x00000003 */ +#define CAN_RF0_RF0MN CAN_RF0_RF0MN_Msk /*!< Receive FIFO 0 message num */ +#define CAN_RF0_RF0FF_Pos (3U) +#define CAN_RF0_RF0FF_Msk (0x1U << CAN_RF0_RF0FF_Pos) /*!< 0x00000008 */ +#define CAN_RF0_RF0FF CAN_RF0_RF0FF_Msk /*!< Receive FIFO 0 full flag */ +#define CAN_RF0_RF0OF_Pos (4U) +#define CAN_RF0_RF0OF_Msk (0x1U << CAN_RF0_RF0OF_Pos) /*!< 0x00000010 */ +#define CAN_RF0_RF0OF CAN_RF0_RF0OF_Msk /*!< Receive FIFO 0 overflow flag */ +#define CAN_RF0_RF0R_Pos (5U) +#define CAN_RF0_RF0R_Msk (0x1U << CAN_RF0_RF0R_Pos) /*!< 0x00000020 */ +#define CAN_RF0_RF0R CAN_RF0_RF0R_Msk /*!< Receive FIFO 0 release */ + +/******************* Bit definition for CAN_RF1 register ********************/ +#define CAN_RF1_RF1MN_Pos (0U) +#define CAN_RF1_RF1MN_Msk (0x3U << CAN_RF1_RF1MN_Pos) /*!< 0x00000003 */ +#define CAN_RF1_RF1MN CAN_RF1_RF1MN_Msk /*!< Receive FIFO 1 message num */ +#define CAN_RF1_RF1FF_Pos (3U) +#define CAN_RF1_RF1FF_Msk (0x1U << CAN_RF1_RF1FF_Pos) /*!< 0x00000008 */ +#define CAN_RF1_RF1FF CAN_RF1_RF1FF_Msk /*!< Receive FIFO 1 full flag */ +#define CAN_RF1_RF1OF_Pos (4U) +#define CAN_RF1_RF1OF_Msk (0x1U << CAN_RF1_RF1OF_Pos) /*!< 0x00000010 */ +#define CAN_RF1_RF1OF CAN_RF1_RF1OF_Msk /*!< Receive FIFO 1 overflow flag */ +#define CAN_RF1_RF1R_Pos (5U) +#define CAN_RF1_RF1R_Msk (0x1U << CAN_RF1_RF1R_Pos) /*!< 0x00000020 */ +#define CAN_RF1_RF1R CAN_RF1_RF1R_Msk /*!< Receive FIFO 1 release */ + +/****************** Bit definition for CAN_INTEN register *******************/ +#define CAN_INTEN_TCIEN_Pos (0U) +#define CAN_INTEN_TCIEN_Msk (0x1U << CAN_INTEN_TCIEN_Pos) /*!< 0x00000001 */ +#define CAN_INTEN_TCIEN CAN_INTEN_TCIEN_Msk /*!< Transmit mailbox empty interrupt enable */ +#define CAN_INTEN_RF0MIEN_Pos (1U) +#define CAN_INTEN_RF0MIEN_Msk (0x1U << CAN_INTEN_RF0MIEN_Pos) /*!< 0x00000002 */ +#define CAN_INTEN_RF0MIEN CAN_INTEN_RF0MIEN_Msk /*!< FIFO 0 receive message interrupt enable */ +#define CAN_INTEN_RF0FIEN_Pos (2U) +#define CAN_INTEN_RF0FIEN_Msk (0x1U << CAN_INTEN_RF0FIEN_Pos) /*!< 0x00000004 */ +#define CAN_INTEN_RF0FIEN CAN_INTEN_RF0FIEN_Msk /*!< Receive FIFO 0 full interrupt enable */ +#define CAN_INTEN_RF0OIEN_Pos (3U) +#define CAN_INTEN_RF0OIEN_Msk (0x1U << CAN_INTEN_RF0OIEN_Pos) /*!< 0x00000008 */ +#define CAN_INTEN_RF0OIEN CAN_INTEN_RF0OIEN_Msk /*!< Receive FIFO 0 overflow interrupt enable */ +#define CAN_INTEN_RF1MIEN_Pos (4U) +#define CAN_INTEN_RF1MIEN_Msk (0x1U << CAN_INTEN_RF1MIEN_Pos) /*!< 0x00000010 */ +#define CAN_INTEN_RF1MIEN CAN_INTEN_RF1MIEN_Msk /*!< FIFO 1 receive message interrupt enable */ +#define CAN_INTEN_RF1FIEN_Pos (5U) +#define CAN_INTEN_RF1FIEN_Msk (0x1U << CAN_INTEN_RF1FIEN_Pos) /*!< 0x00000020 */ +#define CAN_INTEN_RF1FIEN CAN_INTEN_RF1FIEN_Msk /*!< Receive FIFO 1 full interrupt enable */ +#define CAN_INTEN_RF1OIEN_Pos (6U) +#define CAN_INTEN_RF1OIEN_Msk (0x1U << CAN_INTEN_RF1OIEN_Pos) /*!< 0x00000040 */ +#define CAN_INTEN_RF1OIEN CAN_INTEN_RF1OIEN_Msk /*!< Receive FIFO 1 overflow interrupt enable */ +#define CAN_INTEN_EAIEN_Pos (8U) +#define CAN_INTEN_EAIEN_Msk (0x1U << CAN_INTEN_EAIEN_Pos) /*!< 0x00000100 */ +#define CAN_INTEN_EAIEN CAN_INTEN_EAIEN_Msk /*!< Error active interrupt enable */ +#define CAN_INTEN_EPIEN_Pos (9U) +#define CAN_INTEN_EPIEN_Msk (0x1U << CAN_INTEN_EPIEN_Pos) /*!< 0x00000200 */ +#define CAN_INTEN_EPIEN CAN_INTEN_EPIEN_Msk /*!< Error passive interrupt enable */ +#define CAN_INTEN_BOIEN_Pos (10U) +#define CAN_INTEN_BOIEN_Msk (0x1U << CAN_INTEN_BOIEN_Pos) /*!< 0x00000400 */ +#define CAN_INTEN_BOIEN CAN_INTEN_BOIEN_Msk /*!< Bus-off interrupt enable */ +#define CAN_INTEN_ETRIEN_Pos (11U) +#define CAN_INTEN_ETRIEN_Msk (0x1U << CAN_INTEN_ETRIEN_Pos) /*!< 0x00000800 */ +#define CAN_INTEN_ETRIEN CAN_INTEN_ETRIEN_Msk /*!< Error type record interrupt enable */ +#define CAN_INTEN_EOIEN_Pos (15U) +#define CAN_INTEN_EOIEN_Msk (0x1U << CAN_INTEN_EOIEN_Pos) /*!< 0x00008000 */ +#define CAN_INTEN_EOIEN CAN_INTEN_EOIEN_Msk /*!< Error occur interrupt enable */ +#define CAN_INTEN_QDZIEN_Pos (16U) +#define CAN_INTEN_QDZIEN_Msk (0x1U << CAN_INTEN_QDZIEN_Pos) /*!< 0x00010000 */ +#define CAN_INTEN_QDZIEN CAN_INTEN_QDZIEN_Msk /*!< Quit doze mode interrupt enable */ +#define CAN_INTEN_EDZIEN_Pos (17U) +#define CAN_INTEN_EDZIEN_Msk (0x1U << CAN_INTEN_EDZIEN_Pos) /*!< 0x00020000 */ +#define CAN_INTEN_EDZIEN CAN_INTEN_EDZIEN_Msk /*!< Enter doze mode interrupt enable */ + +/******************* Bit definition for CAN_ESTS register *******************/ +#define CAN_ESTS_EAF_Pos (0U) +#define CAN_ESTS_EAF_Msk (0x1U << CAN_ESTS_EAF_Pos) /*!< 0x00000001 */ +#define CAN_ESTS_EAF CAN_ESTS_EAF_Msk /*!< Error active flag */ +#define CAN_ESTS_EPF_Pos (1U) +#define CAN_ESTS_EPF_Msk (0x1U << CAN_ESTS_EPF_Pos) /*!< 0x00000002 */ +#define CAN_ESTS_EPF CAN_ESTS_EPF_Msk /*!< Error passive flag */ +#define CAN_ESTS_BOF_Pos (2U) +#define CAN_ESTS_BOF_Msk (0x1U << CAN_ESTS_BOF_Pos) /*!< 0x00000004 */ +#define CAN_ESTS_BOF CAN_ESTS_BOF_Msk /*!< Bus-off flag */ + +/*!< ETR congiguration */ +#define CAN_ESTS_ETR_Pos (4U) +#define CAN_ESTS_ETR_Msk (0x7U << CAN_ESTS_ETR_Pos) /*!< 0x00000070 */ +#define CAN_ESTS_ETR CAN_ESTS_ETR_Msk /*!< ETR[2:0] bits (Error type record) */ +#define CAN_ESTS_ETR_0 (0x1U << CAN_ESTS_ETR_Pos) /*!< 0x00000010 */ +#define CAN_ESTS_ETR_1 (0x2U << CAN_ESTS_ETR_Pos) /*!< 0x00000020 */ +#define CAN_ESTS_ETR_2 (0x4U << CAN_ESTS_ETR_Pos) /*!< 0x00000040 */ + +#define CAN_ESTS_TEC_Pos (16U) +#define CAN_ESTS_TEC_Msk (0xFFU << CAN_ESTS_TEC_Pos) /*!< 0x00FF0000 */ +#define CAN_ESTS_TEC CAN_ESTS_TEC_Msk /*!< Transmit error counter */ +#define CAN_ESTS_REC_Pos (24U) +#define CAN_ESTS_REC_Msk (0xFFU << CAN_ESTS_REC_Pos) /*!< 0xFF000000 */ +#define CAN_ESTS_REC CAN_ESTS_REC_Msk /*!< Receive error counter */ + +/******************* Bit definition for CAN_BTMG register ********************/ +#define CAN_BTMG_BRDIV_Pos (0U) +#define CAN_BTMG_BRDIV_Msk (0xFFFU << CAN_BTMG_BRDIV_Pos) /*!< 0x00000FFF */ +#define CAN_BTMG_BRDIV CAN_BTMG_BRDIV_Msk /*!< Baud rate division */ + +/*!< BTS1 congiguration */ +#define CAN_BTMG_BTS1_Pos (16U) +#define CAN_BTMG_BTS1_Msk (0xFU << CAN_BTMG_BTS1_Pos) /*!< 0x000F0000 */ +#define CAN_BTMG_BTS1 CAN_BTMG_BTS1_Msk /*!< BTS1[3:0] bits (Bit time segment 1) */ +#define CAN_BTMG_BTS1_0 (0x1U << CAN_BTMG_BTS1_Pos) /*!< 0x00010000 */ +#define CAN_BTMG_BTS1_1 (0x2U << CAN_BTMG_BTS1_Pos) /*!< 0x00020000 */ +#define CAN_BTMG_BTS1_2 (0x4U << CAN_BTMG_BTS1_Pos) /*!< 0x00040000 */ +#define CAN_BTMG_BTS1_3 (0x8U << CAN_BTMG_BTS1_Pos) /*!< 0x00080000 */ + +/*!< BTS2 congiguration */ +#define CAN_BTMG_BTS2_Pos (20U) +#define CAN_BTMG_BTS2_Msk (0x7U << CAN_BTMG_BTS2_Pos) /*!< 0x00700000 */ +#define CAN_BTMG_BTS2 CAN_BTMG_BTS2_Msk /*!< BTS2[2:0] bits (Bit time segment 2) */ +#define CAN_BTMG_BTS2_0 (0x1U << CAN_BTMG_BTS2_Pos) /*!< 0x00100000 */ +#define CAN_BTMG_BTS2_1 (0x2U << CAN_BTMG_BTS2_Pos) /*!< 0x00200000 */ +#define CAN_BTMG_BTS2_2 (0x4U << CAN_BTMG_BTS2_Pos) /*!< 0x00400000 */ + +/*!< RSAW congiguration */ +#define CAN_BTMG_RSAW_Pos (24U) +#define CAN_BTMG_RSAW_Msk (0x3U << CAN_BTMG_RSAW_Pos) /*!< 0x03000000 */ +#define CAN_BTMG_RSAW CAN_BTMG_RSAW_Msk /*!< RSAW[1:0] bits (Resynchronization width) */ +#define CAN_BTMG_RSAW_0 (0x1U << CAN_BTMG_RSAW_Pos) /*!< 0x01000000 */ +#define CAN_BTMG_RSAW_1 (0x2U << CAN_BTMG_RSAW_Pos) /*!< 0x02000000 */ + +#define CAN_BTMG_LBEN_Pos (30U) +#define CAN_BTMG_LBEN_Msk (0x1U << CAN_BTMG_LBEN_Pos) /*!< 0x40000000 */ +#define CAN_BTMG_LBEN CAN_BTMG_LBEN_Msk /*!< Loop back mode */ +#define CAN_BTMG_LOEN_Pos (31U) +#define CAN_BTMG_LOEN_Msk (0x1U << CAN_BTMG_LOEN_Pos) /*!< 0x80000000 */ +#define CAN_BTMG_LOEN CAN_BTMG_LOEN_Msk /*!< Listen-Only mode */ + +/*!< Mailbox registers */ +/******************* Bit definition for CAN_TMI0 register *******************/ +#define CAN_TMI0_TMSR_Pos (0U) +#define CAN_TMI0_TMSR_Msk (0x1U << CAN_TMI0_TMSR_Pos) /*!< 0x00000001 */ +#define CAN_TMI0_TMSR CAN_TMI0_TMSR_Msk /*!< Transmit mailbox send request */ +#define CAN_TMI0_TMFRSEL_Pos (1U) +#define CAN_TMI0_TMFRSEL_Msk (0x1U << CAN_TMI0_TMFRSEL_Pos) /*!< 0x00000002 */ +#define CAN_TMI0_TMFRSEL CAN_TMI0_TMFRSEL_Msk /*!< Transmit mailbox frame type select */ +#define CAN_TMI0_TMIDSEL_Pos (2U) +#define CAN_TMI0_TMIDSEL_Msk (0x1U << CAN_TMI0_TMIDSEL_Pos) /*!< 0x00000004 */ +#define CAN_TMI0_TMIDSEL CAN_TMI0_TMIDSEL_Msk /*!< Transmit mailbox identifier type select */ +#define CAN_TMI0_TMEID_Pos (3U) +#define CAN_TMI0_TMEID_Msk (0x3FFFFU << CAN_TMI0_TMEID_Pos) /*!< 0x001FFFF8 */ +#define CAN_TMI0_TMEID CAN_TMI0_TMEID_Msk /*!< Transmit mailbox extended identifier */ +#define CAN_TMI0_TMSID_Pos (21U) +#define CAN_TMI0_TMSID_Msk (0x7FFU << CAN_TMI0_TMSID_Pos) /*!< 0xFFE00000 */ +#define CAN_TMI0_TMSID CAN_TMI0_TMSID_Msk /*!< Transmit mailbox standard identifier or extended identifier high bytes */ + +/******************* Bit definition for CAN_TMC0 register *******************/ +#define CAN_TMC0_TMDTBL_Pos (0U) +#define CAN_TMC0_TMDTBL_Msk (0xFU << CAN_TMC0_TMDTBL_Pos) /*!< 0x0000000F */ +#define CAN_TMC0_TMDTBL CAN_TMC0_TMDTBL_Msk /*!< Transmit mailbox data byte length */ +#define CAN_TMC0_TMTSTEN_Pos (8U) +#define CAN_TMC0_TMTSTEN_Msk (0x1U << CAN_TMC0_TMTSTEN_Pos) /*!< 0x00000100 */ +#define CAN_TMC0_TMTSTEN CAN_TMC0_TMTSTEN_Msk /*!< Transmit mailbox time stamp transmit enable */ +#define CAN_TMC0_TMTS_Pos (16U) +#define CAN_TMC0_TMTS_Msk (0xFFFFU << CAN_TMC0_TMTS_Pos) /*!< 0xFFFF0000 */ +#define CAN_TMC0_TMTS CAN_TMC0_TMTS_Msk /*!< Transmit mailbox time stamp */ + +/****************** Bit definition for CAN_TMDTL0 register ******************/ +#define CAN_TMDTL0_TMDT0_Pos (0U) +#define CAN_TMDTL0_TMDT0_Msk (0xFFU << CAN_TMDTL0_TMDT0_Pos) /*!< 0x000000FF */ +#define CAN_TMDTL0_TMDT0 CAN_TMDTL0_TMDT0_Msk /*!< Transmit mailbox data byte 0 */ +#define CAN_TMDTL0_TMDT1_Pos (8U) +#define CAN_TMDTL0_TMDT1_Msk (0xFFU << CAN_TMDTL0_TMDT1_Pos) /*!< 0x0000FF00 */ +#define CAN_TMDTL0_TMDT1 CAN_TMDTL0_TMDT1_Msk /*!< Transmit mailbox data byte 1 */ +#define CAN_TMDTL0_TMDT2_Pos (16U) +#define CAN_TMDTL0_TMDT2_Msk (0xFFU << CAN_TMDTL0_TMDT2_Pos) /*!< 0x00FF0000 */ +#define CAN_TMDTL0_TMDT2 CAN_TMDTL0_TMDT2_Msk /*!< Transmit mailbox data byte 2 */ +#define CAN_TMDTL0_TMDT3_Pos (24U) +#define CAN_TMDTL0_TMDT3_Msk (0xFFU << CAN_TMDTL0_TMDT3_Pos) /*!< 0xFF000000 */ +#define CAN_TMDTL0_TMDT3 CAN_TMDTL0_TMDT3_Msk /*!< Transmit mailbox data byte 3 */ + +/****************** Bit definition for CAN_TMDTH0 register ******************/ +#define CAN_TMDTH0_TMDT4_Pos (0U) +#define CAN_TMDTH0_TMDT4_Msk (0xFFU << CAN_TMDTH0_TMDT4_Pos) /*!< 0x000000FF */ +#define CAN_TMDTH0_TMDT4 CAN_TMDTH0_TMDT4_Msk /*!< Transmit mailbox data byte 4 */ +#define CAN_TMDTH0_TMDT5_Pos (8U) +#define CAN_TMDTH0_TMDT5_Msk (0xFFU << CAN_TMDTH0_TMDT5_Pos) /*!< 0x0000FF00 */ +#define CAN_TMDTH0_TMDT5 CAN_TMDTH0_TMDT5_Msk /*!< Transmit mailbox data byte 5 */ +#define CAN_TMDTH0_TMDT6_Pos (16U) +#define CAN_TMDTH0_TMDT6_Msk (0xFFU << CAN_TMDTH0_TMDT6_Pos) /*!< 0x00FF0000 */ +#define CAN_TMDTH0_TMDT6 CAN_TMDTH0_TMDT6_Msk /*!< Transmit mailbox data byte 6 */ +#define CAN_TMDTH0_TMDT7_Pos (24U) +#define CAN_TMDTH0_TMDT7_Msk (0xFFU << CAN_TMDTH0_TMDT7_Pos) /*!< 0xFF000000 */ +#define CAN_TMDTH0_TMDT7 CAN_TMDTH0_TMDT7_Msk /*!< Transmit mailbox data byte 7 */ + +/******************* Bit definition for CAN_TMI1 register *******************/ +#define CAN_TMI1_TMSR_Pos (0U) +#define CAN_TMI1_TMSR_Msk (0x1U << CAN_TMI1_TMSR_Pos) /*!< 0x00000001 */ +#define CAN_TMI1_TMSR CAN_TMI1_TMSR_Msk /*!< Transmit mailbox send request */ +#define CAN_TMI1_TMFRSEL_Pos (1U) +#define CAN_TMI1_TMFRSEL_Msk (0x1U << CAN_TMI1_TMFRSEL_Pos) /*!< 0x00000002 */ +#define CAN_TMI1_TMFRSEL CAN_TMI1_TMFRSEL_Msk /*!< Transmit mailbox frame type select */ +#define CAN_TMI1_TMIDSEL_Pos (2U) +#define CAN_TMI1_TMIDSEL_Msk (0x1U << CAN_TMI1_TMIDSEL_Pos) /*!< 0x00000004 */ +#define CAN_TMI1_TMIDSEL CAN_TMI1_TMIDSEL_Msk /*!< Transmit mailbox identifier type select */ +#define CAN_TMI1_TMEID_Pos (3U) +#define CAN_TMI1_TMEID_Msk (0x3FFFFU << CAN_TMI1_TMEID_Pos) /*!< 0x001FFFF8 */ +#define CAN_TMI1_TMEID CAN_TMI1_TMEID_Msk /*!< Transmit mailbox extended identifier */ +#define CAN_TMI1_TMSID_Pos (21U) +#define CAN_TMI1_TMSID_Msk (0x7FFU << CAN_TMI1_TMSID_Pos) /*!< 0xFFE00000 */ +#define CAN_TMI1_TMSID CAN_TMI1_TMSID_Msk /*!< Transmit mailbox standard identifier or extended identifier high bytes */ + +/******************* Bit definition for CAN_TMC1 register *******************/ +#define CAN_TMC1_TMDTBL_Pos (0U) +#define CAN_TMC1_TMDTBL_Msk (0xFU << CAN_TMC1_TMDTBL_Pos) /*!< 0x0000000F */ +#define CAN_TMC1_TMDTBL CAN_TMC1_TMDTBL_Msk /*!< Transmit mailbox data byte length */ +#define CAN_TMC1_TMTSTEN_Pos (8U) +#define CAN_TMC1_TMTSTEN_Msk (0x1U << CAN_TMC1_TMTSTEN_Pos) /*!< 0x00000100 */ +#define CAN_TMC1_TMTSTEN CAN_TMC1_TMTSTEN_Msk /*!< Transmit mailbox time stamp transmit enable */ +#define CAN_TMC1_TMTS_Pos (16U) +#define CAN_TMC1_TMTS_Msk (0xFFFFU << CAN_TMC1_TMTS_Pos) /*!< 0xFFFF0000 */ +#define CAN_TMC1_TMTS CAN_TMC1_TMTS_Msk /*!< Transmit mailbox time stamp */ + +/****************** Bit definition for CAN_TMDTL1 register ******************/ +#define CAN_TMDTL1_TMDT0_Pos (0U) +#define CAN_TMDTL1_TMDT0_Msk (0xFFU << CAN_TMDTL1_TMDT0_Pos) /*!< 0x000000FF */ +#define CAN_TMDTL1_TMDT0 CAN_TMDTL1_TMDT0_Msk /*!< Transmit mailbox data byte 0 */ +#define CAN_TMDTL1_TMDT1_Pos (8U) +#define CAN_TMDTL1_TMDT1_Msk (0xFFU << CAN_TMDTL1_TMDT1_Pos) /*!< 0x0000FF00 */ +#define CAN_TMDTL1_TMDT1 CAN_TMDTL1_TMDT1_Msk /*!< Transmit mailbox data byte 1 */ +#define CAN_TMDTL1_TMDT2_Pos (16U) +#define CAN_TMDTL1_TMDT2_Msk (0xFFU << CAN_TMDTL1_TMDT2_Pos) /*!< 0x00FF0000 */ +#define CAN_TMDTL1_TMDT2 CAN_TMDTL1_TMDT2_Msk /*!< Transmit mailbox data byte 2 */ +#define CAN_TMDTL1_TMDT3_Pos (24U) +#define CAN_TMDTL1_TMDT3_Msk (0xFFU << CAN_TMDTL1_TMDT3_Pos) /*!< 0xFF000000 */ +#define CAN_TMDTL1_TMDT3 CAN_TMDTL1_TMDT3_Msk /*!< Transmit mailbox data byte 3 */ + +/****************** Bit definition for CAN_TMDTH1 register ******************/ +#define CAN_TMDTH1_TMDT4_Pos (0U) +#define CAN_TMDTH1_TMDT4_Msk (0xFFU << CAN_TMDTH1_TMDT4_Pos) /*!< 0x000000FF */ +#define CAN_TMDTH1_TMDT4 CAN_TMDTH1_TMDT4_Msk /*!< Transmit mailbox data byte 4 */ +#define CAN_TMDTH1_TMDT5_Pos (8U) +#define CAN_TMDTH1_TMDT5_Msk (0xFFU << CAN_TMDTH1_TMDT5_Pos) /*!< 0x0000FF00 */ +#define CAN_TMDTH1_TMDT5 CAN_TMDTH1_TMDT5_Msk /*!< Transmit mailbox data byte 5 */ +#define CAN_TMDTH1_TMDT6_Pos (16U) +#define CAN_TMDTH1_TMDT6_Msk (0xFFU << CAN_TMDTH1_TMDT6_Pos) /*!< 0x00FF0000 */ +#define CAN_TMDTH1_TMDT6 CAN_TMDTH1_TMDT6_Msk /*!< Transmit mailbox data byte 6 */ +#define CAN_TMDTH1_TMDT7_Pos (24U) +#define CAN_TMDTH1_TMDT7_Msk (0xFFU << CAN_TMDTH1_TMDT7_Pos) /*!< 0xFF000000 */ +#define CAN_TMDTH1_TMDT7 CAN_TMDTH1_TMDT7_Msk /*!< Transmit mailbox data byte 7 */ + +/******************* Bit definition for CAN_TMI2 register *******************/ +#define CAN_TMI2_TMSR_Pos (0U) +#define CAN_TMI2_TMSR_Msk (0x1U << CAN_TMI2_TMSR_Pos) /*!< 0x00000001 */ +#define CAN_TMI2_TMSR CAN_TMI2_TMSR_Msk /*!< Transmit mailbox send request */ +#define CAN_TMI2_TMFRSEL_Pos (1U) +#define CAN_TMI2_TMFRSEL_Msk (0x1U << CAN_TMI2_TMFRSEL_Pos) /*!< 0x00000002 */ +#define CAN_TMI2_TMFRSEL CAN_TMI2_TMFRSEL_Msk /*!< Transmit mailbox frame type select */ +#define CAN_TMI2_TMIDSEL_Pos (2U) +#define CAN_TMI2_TMIDSEL_Msk (0x1U << CAN_TMI2_TMIDSEL_Pos) /*!< 0x00000004 */ +#define CAN_TMI2_TMIDSEL CAN_TMI2_TMIDSEL_Msk /*!< Transmit mailbox identifier type select */ +#define CAN_TMI2_TMEID_Pos (3U) +#define CAN_TMI2_TMEID_Msk (0x3FFFFU << CAN_TMI2_TMEID_Pos) /*!< 0x001FFFF8 */ +#define CAN_TMI2_TMEID CAN_TMI2_TMEID_Msk /*!< Transmit mailbox extended identifier */ +#define CAN_TMI2_TMSID_Pos (21U) +#define CAN_TMI2_TMSID_Msk (0x7FFU << CAN_TMI2_TMSID_Pos) /*!< 0xFFE00000 */ +#define CAN_TMI2_TMSID CAN_TMI2_TMSID_Msk /*!< Transmit mailbox standard identifier or extended identifier high bytes */ + +/******************* Bit definition for CAN_TMC2 register *******************/ +#define CAN_TMC2_TMDTBL_Pos (0U) +#define CAN_TMC2_TMDTBL_Msk (0xFU << CAN_TMC2_TMDTBL_Pos) /*!< 0x0000000F */ +#define CAN_TMC2_TMDTBL CAN_TMC2_TMDTBL_Msk /*!< Transmit mailbox data byte length */ +#define CAN_TMC2_TMTSTEN_Pos (8U) +#define CAN_TMC2_TMTSTEN_Msk (0x1U << CAN_TMC2_TMTSTEN_Pos) /*!< 0x00000100 */ +#define CAN_TMC2_TMTSTEN CAN_TMC2_TMTSTEN_Msk /*!< Transmit mailbox time stamp transmit enable */ +#define CAN_TMC2_TMTS_Pos (16U) +#define CAN_TMC2_TMTS_Msk (0xFFFFU << CAN_TMC2_TMTS_Pos) /*!< 0xFFFF0000 */ +#define CAN_TMC2_TMTS CAN_TMC2_TMTS_Msk /*!< Transmit mailbox time stamp */ + +/****************** Bit definition for CAN_TMDTL2 register ******************/ +#define CAN_TMDTL2_TMDT0_Pos (0U) +#define CAN_TMDTL2_TMDT0_Msk (0xFFU << CAN_TMDTL2_TMDT0_Pos) /*!< 0x000000FF */ +#define CAN_TMDTL2_TMDT0 CAN_TMDTL2_TMDT0_Msk /*!< Transmit mailbox data byte 0 */ +#define CAN_TMDTL2_TMDT1_Pos (8U) +#define CAN_TMDTL2_TMDT1_Msk (0xFFU << CAN_TMDTL2_TMDT1_Pos) /*!< 0x0000FF00 */ +#define CAN_TMDTL2_TMDT1 CAN_TMDTL2_TMDT1_Msk /*!< Transmit mailbox data byte 1 */ +#define CAN_TMDTL2_TMDT2_Pos (16U) +#define CAN_TMDTL2_TMDT2_Msk (0xFFU << CAN_TMDTL2_TMDT2_Pos) /*!< 0x00FF0000 */ +#define CAN_TMDTL2_TMDT2 CAN_TMDTL2_TMDT2_Msk /*!< Transmit mailbox data byte 2 */ +#define CAN_TMDTL2_TMDT3_Pos (24U) +#define CAN_TMDTL2_TMDT3_Msk (0xFFU << CAN_TMDTL2_TMDT3_Pos) /*!< 0xFF000000 */ +#define CAN_TMDTL2_TMDT3 CAN_TMDTL2_TMDT3_Msk /*!< Transmit mailbox data byte 3 */ + +/****************** Bit definition for CAN_TMDTH2 register ******************/ +#define CAN_TMDTH2_TMDT4_Pos (0U) +#define CAN_TMDTH2_TMDT4_Msk (0xFFU << CAN_TMDTH2_TMDT4_Pos) /*!< 0x000000FF */ +#define CAN_TMDTH2_TMDT4 CAN_TMDTH2_TMDT4_Msk /*!< Transmit mailbox data byte 4 */ +#define CAN_TMDTH2_TMDT5_Pos (8U) +#define CAN_TMDTH2_TMDT5_Msk (0xFFU << CAN_TMDTH2_TMDT5_Pos) /*!< 0x0000FF00 */ +#define CAN_TMDTH2_TMDT5 CAN_TMDTH2_TMDT5_Msk /*!< Transmit mailbox data byte 5 */ +#define CAN_TMDTH2_TMDT6_Pos (16U) +#define CAN_TMDTH2_TMDT6_Msk (0xFFU << CAN_TMDTH2_TMDT6_Pos) /*!< 0x00FF0000 */ +#define CAN_TMDTH2_TMDT6 CAN_TMDTH2_TMDT6_Msk /*!< Transmit mailbox data byte 6 */ +#define CAN_TMDTH2_TMDT7_Pos (24U) +#define CAN_TMDTH2_TMDT7_Msk (0xFFU << CAN_TMDTH2_TMDT7_Pos) /*!< 0xFF000000 */ +#define CAN_TMDTH2_TMDT7 CAN_TMDTH2_TMDT7_Msk /*!< Transmit mailbox data byte 7 */ + +/******************* Bit definition for CAN_RFI0 register *******************/ +#define CAN_RFI0_RFFRI_Pos (1U) +#define CAN_RFI0_RFFRI_Msk (0x1U << CAN_RFI0_RFFRI_Pos) /*!< 0x00000002 */ +#define CAN_RFI0_RFFRI CAN_RFI0_RFFRI_Msk /*!< Receive FIFO frame type indication */ +#define CAN_RFI0_RFIDI_Pos (2U) +#define CAN_RFI0_RFIDI_Msk (0x1U << CAN_RFI0_RFIDI_Pos) /*!< 0x00000004 */ +#define CAN_RFI0_RFIDI CAN_RFI0_RFIDI_Msk /*!< Receive FIFO identifier type indication */ +#define CAN_RFI0_RFEID_Pos (3U) +#define CAN_RFI0_RFEID_Msk (0x3FFFFU << CAN_RFI0_RFEID_Pos) /*!< 0x001FFFF8 */ +#define CAN_RFI0_RFEID CAN_RFI0_RFEID_Msk /*!< Receive FIFO extended identifier */ +#define CAN_RFI0_RFSID_Pos (21U) +#define CAN_RFI0_RFSID_Msk (0x7FFU << CAN_RFI0_RFSID_Pos) /*!< 0xFFE00000 */ +#define CAN_RFI0_RFSID CAN_RFI0_RFSID_Msk /*!< Receive FIFO standard identifier or receive FIFO extended identifier */ + +/******************* Bit definition for CAN_RFC0 register *******************/ +#define CAN_RFC0_RFDTL_Pos (0U) +#define CAN_RFC0_RFDTL_Msk (0xFU << CAN_RFC0_RFDTL_Pos) /*!< 0x0000000F */ +#define CAN_RFC0_RFDTL CAN_RFC0_RFDTL_Msk /*!< Receive FIFO data length */ +#define CAN_RFC0_RFFMN_Pos (8U) +#define CAN_RFC0_RFFMN_Msk (0xFFU << CAN_RFC0_RFFMN_Pos) /*!< 0x0000FF00 */ +#define CAN_RFC0_RFFMN CAN_RFC0_RFFMN_Msk /*!< Receive FIFO filter match number */ +#define CAN_RFC0_RFTS_Pos (16U) +#define CAN_RFC0_RFTS_Msk (0xFFFFU << CAN_RFC0_RFTS_Pos) /*!< 0xFFFF0000 */ +#define CAN_RFC0_RFTS CAN_RFC0_RFTS_Msk /*!< Receive FIFO time stamp */ + +/****************** Bit definition for CAN_RFDTL0 register ******************/ +#define CAN_RFDTL0_RFDT0_Pos (0U) +#define CAN_RFDTL0_RFDT0_Msk (0xFFU << CAN_RFDTL0_RFDT0_Pos) /*!< 0x000000FF */ +#define CAN_RFDTL0_RFDT0 CAN_RFDTL0_RFDT0_Msk /*!< Receive FIFO data byte 0 */ +#define CAN_RFDTL0_RFDT1_Pos (8U) +#define CAN_RFDTL0_RFDT1_Msk (0xFFU << CAN_RFDTL0_RFDT1_Pos) /*!< 0x0000FF00 */ +#define CAN_RFDTL0_RFDT1 CAN_RFDTL0_RFDT1_Msk /*!< Receive FIFO data byte 1 */ +#define CAN_RFDTL0_RFDT2_Pos (16U) +#define CAN_RFDTL0_RFDT2_Msk (0xFFU << CAN_RFDTL0_RFDT2_Pos) /*!< 0x00FF0000 */ +#define CAN_RFDTL0_RFDT2 CAN_RFDTL0_RFDT2_Msk /*!< Receive FIFO data byte 2 */ +#define CAN_RFDTL0_RFDT3_Pos (24U) +#define CAN_RFDTL0_RFDT3_Msk (0xFFU << CAN_RFDTL0_RFDT3_Pos) /*!< 0xFF000000 */ +#define CAN_RFDTL0_RFDT3 CAN_RFDTL0_RFDT3_Msk /*!< Receive FIFO data byte 3 */ + +/****************** Bit definition for CAN_RFDTH0 register ******************/ +#define CAN_RFDTH0_RFDT4_Pos (0U) +#define CAN_RFDTH0_RFDT4_Msk (0xFFU << CAN_RFDTH0_RFDT4_Pos) /*!< 0x000000FF */ +#define CAN_RFDTH0_RFDT4 CAN_RFDTH0_RFDT4_Msk /*!< Receive FIFO data byte 4 */ +#define CAN_RFDTH0_RFDT5_Pos (8U) +#define CAN_RFDTH0_RFDT5_Msk (0xFFU << CAN_RFDTH0_RFDT5_Pos) /*!< 0x0000FF00 */ +#define CAN_RFDTH0_RFDT5 CAN_RFDTH0_RFDT5_Msk /*!< Receive FIFO data byte 5 */ +#define CAN_RFDTH0_RFDT6_Pos (16U) +#define CAN_RFDTH0_RFDT6_Msk (0xFFU << CAN_RFDTH0_RFDT6_Pos) /*!< 0x00FF0000 */ +#define CAN_RFDTH0_RFDT6 CAN_RFDTH0_RFDT6_Msk /*!< Receive FIFO data byte 6 */ +#define CAN_RFDTH0_RFDT7_Pos (24U) +#define CAN_RFDTH0_RFDT7_Msk (0xFFU << CAN_RFDTH0_RFDT7_Pos) /*!< 0xFF000000 */ +#define CAN_RFDTH0_RFDT7 CAN_RFDTH0_RFDT7_Msk /*!< Receive FIFO data byte 7 */ + +/******************* Bit definition for CAN_RFI1 register *******************/ +#define CAN_RFI1_RFFRI_Pos (1U) +#define CAN_RFI1_RFFRI_Msk (0x1U << CAN_RFI1_RFFRI_Pos) /*!< 0x00000002 */ +#define CAN_RFI1_RFFRI CAN_RFI1_RFFRI_Msk /*!< Receive FIFO frame type indication */ +#define CAN_RFI1_RFIDI_Pos (2U) +#define CAN_RFI1_RFIDI_Msk (0x1U << CAN_RFI1_RFIDI_Pos) /*!< 0x00000004 */ +#define CAN_RFI1_RFIDI CAN_RFI1_RFIDI_Msk /*!< Receive FIFO identifier type indication */ +#define CAN_RFI1_RFEID_Pos (3U) +#define CAN_RFI1_RFEID_Msk (0x3FFFFU << CAN_RFI1_RFEID_Pos) /*!< 0x001FFFF8 */ +#define CAN_RFI1_RFEID CAN_RFI1_RFEID_Msk /*!< Receive FIFO extended identifier */ +#define CAN_RFI1_RFSID_Pos (21U) +#define CAN_RFI1_RFSID_Msk (0x7FFU << CAN_RFI1_RFSID_Pos) /*!< 0xFFE00000 */ +#define CAN_RFI1_RFSID CAN_RFI1_RFSID_Msk /*!< Receive FIFO standard identifier or receive FIFO extended identifier */ + +/******************* Bit definition for CAN_RFC1 register *******************/ +#define CAN_RFC1_RFDTL_Pos (0U) +#define CAN_RFC1_RFDTL_Msk (0xFU << CAN_RFC1_RFDTL_Pos) /*!< 0x0000000F */ +#define CAN_RFC1_RFDTL CAN_RFC1_RFDTL_Msk /*!< Receive FIFO data length */ +#define CAN_RFC1_RFFMN_Pos (8U) +#define CAN_RFC1_RFFMN_Msk (0xFFU << CAN_RFC1_RFFMN_Pos) /*!< 0x0000FF00 */ +#define CAN_RFC1_RFFMN CAN_RFC1_RFFMN_Msk /*!< Receive FIFO filter match number */ +#define CAN_RFC1_RFTS_Pos (16U) +#define CAN_RFC1_RFTS_Msk (0xFFFFU << CAN_RFC1_RFTS_Pos) /*!< 0xFFFF0000 */ +#define CAN_RFC1_RFTS CAN_RFC1_RFTS_Msk /*!< Receive FIFO time stamp */ + +/****************** Bit definition for CAN_RFDTL1 register ******************/ +#define CAN_RFDTL1_RFDT0_Pos (0U) +#define CAN_RFDTL1_RFDT0_Msk (0xFFU << CAN_RFDTL1_RFDT0_Pos) /*!< 0x000000FF */ +#define CAN_RFDTL1_RFDT0 CAN_RFDTL1_RFDT0_Msk /*!< Receive FIFO data byte 0 */ +#define CAN_RFDTL1_RFDT1_Pos (8U) +#define CAN_RFDTL1_RFDT1_Msk (0xFFU << CAN_RFDTL1_RFDT1_Pos) /*!< 0x0000FF00 */ +#define CAN_RFDTL1_RFDT1 CAN_RFDTL1_RFDT1_Msk /*!< Receive FIFO data byte 1 */ +#define CAN_RFDTL1_RFDT2_Pos (16U) +#define CAN_RFDTL1_RFDT2_Msk (0xFFU << CAN_RFDTL1_RFDT2_Pos) /*!< 0x00FF0000 */ +#define CAN_RFDTL1_RFDT2 CAN_RFDTL1_RFDT2_Msk /*!< Receive FIFO data byte 2 */ +#define CAN_RFDTL1_RFDT3_Pos (24U) +#define CAN_RFDTL1_RFDT3_Msk (0xFFU << CAN_RFDTL1_RFDT3_Pos) /*!< 0xFF000000 */ +#define CAN_RFDTL1_RFDT3 CAN_RFDTL1_RFDT3_Msk /*!< Receive FIFO data byte 3 */ + +/****************** Bit definition for CAN_RFDTH1 register ******************/ +#define CAN_RFDTH1_RFDT4_Pos (0U) +#define CAN_RFDTH1_RFDT4_Msk (0xFFU << CAN_RFDTH1_RFDT4_Pos) /*!< 0x000000FF */ +#define CAN_RFDTH1_RFDT4 CAN_RFDTH1_RFDT4_Msk /*!< Receive FIFO data byte 4 */ +#define CAN_RFDTH1_RFDT5_Pos (8U) +#define CAN_RFDTH1_RFDT5_Msk (0xFFU << CAN_RFDTH1_RFDT5_Pos) /*!< 0x0000FF00 */ +#define CAN_RFDTH1_RFDT5 CAN_RFDTH1_RFDT5_Msk /*!< Receive FIFO data byte 5 */ +#define CAN_RFDTH1_RFDT6_Pos (16U) +#define CAN_RFDTH1_RFDT6_Msk (0xFFU << CAN_RFDTH1_RFDT6_Pos) /*!< 0x00FF0000 */ +#define CAN_RFDTH1_RFDT6 CAN_RFDTH1_RFDT6_Msk /*!< Receive FIFO data byte 6 */ +#define CAN_RFDTH1_RFDT7_Pos (24U) +#define CAN_RFDTH1_RFDT7_Msk (0xFFU << CAN_RFDTH1_RFDT7_Pos) /*!< 0xFF000000 */ +#define CAN_RFDTH1_RFDT7 CAN_RFDTH1_RFDT7_Msk /*!< Receive FIFO data byte 7 */ + +/*!< CAN filter registers */ +/****************** Bit definition for CAN_FCTRL register *******************/ +#define CAN_FCTRL_FCS_Pos (0U) +#define CAN_FCTRL_FCS_Msk (0x1U << CAN_FCTRL_FCS_Pos) /*!< 0x00000001 */ +#define CAN_FCTRL_FCS CAN_FCTRL_FCS_Msk /*!< Filter configuration switch */ + +/****************** Bit definition for CAN_FMCFG register *******************/ +#define CAN_FMCFG_FMSEL_Pos (0U) +#define CAN_FMCFG_FMSEL_Msk (0xFFFFFFFU << CAN_FMCFG_FMSEL_Pos) /*!< 0x0FFFFFFF */ +#define CAN_FMCFG_FMSEL CAN_FMCFG_FMSEL_Msk /*!< Filter mode select */ +#define CAN_FMCFG_FMSEL0_Pos (0U) +#define CAN_FMCFG_FMSEL0_Msk (0x1U << CAN_FMCFG_FMSEL0_Pos) /*!< 0x00000001 */ +#define CAN_FMCFG_FMSEL0 CAN_FMCFG_FMSEL0_Msk /*!< Filter mode select for filter 0 */ +#define CAN_FMCFG_FMSEL1_Pos (1U) +#define CAN_FMCFG_FMSEL1_Msk (0x1U << CAN_FMCFG_FMSEL1_Pos) /*!< 0x00000002 */ +#define CAN_FMCFG_FMSEL1 CAN_FMCFG_FMSEL1_Msk /*!< Filter mode select for filter 1 */ +#define CAN_FMCFG_FMSEL2_Pos (2U) +#define CAN_FMCFG_FMSEL2_Msk (0x1U << CAN_FMCFG_FMSEL2_Pos) /*!< 0x00000004 */ +#define CAN_FMCFG_FMSEL2 CAN_FMCFG_FMSEL2_Msk /*!< Filter mode select for filter 2 */ +#define CAN_FMCFG_FMSEL3_Pos (3U) +#define CAN_FMCFG_FMSEL3_Msk (0x1U << CAN_FMCFG_FMSEL3_Pos) /*!< 0x00000008 */ +#define CAN_FMCFG_FMSEL3 CAN_FMCFG_FMSEL3_Msk /*!< Filter mode select for filter 3 */ +#define CAN_FMCFG_FMSEL4_Pos (4U) +#define CAN_FMCFG_FMSEL4_Msk (0x1U << CAN_FMCFG_FMSEL4_Pos) /*!< 0x00000010 */ +#define CAN_FMCFG_FMSEL4 CAN_FMCFG_FMSEL4_Msk /*!< Filter mode select for filter 4 */ +#define CAN_FMCFG_FMSEL5_Pos (5U) +#define CAN_FMCFG_FMSEL5_Msk (0x1U << CAN_FMCFG_FMSEL5_Pos) /*!< 0x00000020 */ +#define CAN_FMCFG_FMSEL5 CAN_FMCFG_FMSEL5_Msk /*!< Filter mode select for filter 5 */ +#define CAN_FMCFG_FMSEL6_Pos (6U) +#define CAN_FMCFG_FMSEL6_Msk (0x1U << CAN_FMCFG_FMSEL6_Pos) /*!< 0x00000040 */ +#define CAN_FMCFG_FMSEL6 CAN_FMCFG_FMSEL6_Msk /*!< Filter mode select for filter 6 */ +#define CAN_FMCFG_FMSEL7_Pos (7U) +#define CAN_FMCFG_FMSEL7_Msk (0x1U << CAN_FMCFG_FMSEL7_Pos) /*!< 0x00000080 */ +#define CAN_FMCFG_FMSEL7 CAN_FMCFG_FMSEL7_Msk /*!< Filter mode select for filter 7 */ +#define CAN_FMCFG_FMSEL8_Pos (8U) +#define CAN_FMCFG_FMSEL8_Msk (0x1U << CAN_FMCFG_FMSEL8_Pos) /*!< 0x00000100 */ +#define CAN_FMCFG_FMSEL8 CAN_FMCFG_FMSEL8_Msk /*!< Filter mode select for filter 8 */ +#define CAN_FMCFG_FMSEL9_Pos (9U) +#define CAN_FMCFG_FMSEL9_Msk (0x1U << CAN_FMCFG_FMSEL9_Pos) /*!< 0x00000200 */ +#define CAN_FMCFG_FMSEL9 CAN_FMCFG_FMSEL9_Msk /*!< Filter mode select for filter 9 */ +#define CAN_FMCFG_FMSEL10_Pos (10U) +#define CAN_FMCFG_FMSEL10_Msk (0x1U << CAN_FMCFG_FMSEL10_Pos) /*!< 0x00000400 */ +#define CAN_FMCFG_FMSEL10 CAN_FMCFG_FMSEL10_Msk /*!< Filter mode select for filter 10 */ +#define CAN_FMCFG_FMSEL11_Pos (11U) +#define CAN_FMCFG_FMSEL11_Msk (0x1U << CAN_FMCFG_FMSEL11_Pos) /*!< 0x00000800 */ +#define CAN_FMCFG_FMSEL11 CAN_FMCFG_FMSEL11_Msk /*!< Filter mode select for filter 11 */ +#define CAN_FMCFG_FMSEL12_Pos (12U) +#define CAN_FMCFG_FMSEL12_Msk (0x1U << CAN_FMCFG_FMSEL12_Pos) /*!< 0x00001000 */ +#define CAN_FMCFG_FMSEL12 CAN_FMCFG_FMSEL12_Msk /*!< Filter mode select for filter 12 */ +#define CAN_FMCFG_FMSEL13_Pos (13U) +#define CAN_FMCFG_FMSEL13_Msk (0x1U << CAN_FMCFG_FMSEL13_Pos) /*!< 0x00002000 */ +#define CAN_FMCFG_FMSEL13 CAN_FMCFG_FMSEL13_Msk /*!< Filter mode select for filter 13 */ +#define CAN_FMCFG_FMSEL14_Pos (14U) +#define CAN_FMCFG_FMSEL14_Msk (0x1U << CAN_FMCFG_FMSEL14_Pos) /*!< 0x00004000 */ +#define CAN_FMCFG_FMSEL14 CAN_FMCFG_FMSEL14_Msk /*!< Filter mode select for filter 14 */ +#define CAN_FMCFG_FMSEL15_Pos (15U) +#define CAN_FMCFG_FMSEL15_Msk (0x1U << CAN_FMCFG_FMSEL15_Pos) /*!< 0x00008000 */ +#define CAN_FMCFG_FMSEL15 CAN_FMCFG_FMSEL15_Msk /*!< Filter mode select for filter 15 */ +#define CAN_FMCFG_FMSEL16_Pos (16U) +#define CAN_FMCFG_FMSEL16_Msk (0x1U << CAN_FMCFG_FMSEL16_Pos) /*!< 0x00010000 */ +#define CAN_FMCFG_FMSEL16 CAN_FMCFG_FMSEL16_Msk /*!< Filter mode select for filter 16 */ +#define CAN_FMCFG_FMSEL17_Pos (17U) +#define CAN_FMCFG_FMSEL17_Msk (0x1U << CAN_FMCFG_FMSEL17_Pos) /*!< 0x00020000 */ +#define CAN_FMCFG_FMSEL17 CAN_FMCFG_FMSEL17_Msk /*!< Filter mode select for filter 17 */ +#define CAN_FMCFG_FMSEL18_Pos (18U) +#define CAN_FMCFG_FMSEL18_Msk (0x1U << CAN_FMCFG_FMSEL18_Pos) /*!< 0x00040000 */ +#define CAN_FMCFG_FMSEL18 CAN_FMCFG_FMSEL18_Msk /*!< Filter mode select for filter 18 */ +#define CAN_FMCFG_FMSEL19_Pos (19U) +#define CAN_FMCFG_FMSEL19_Msk (0x1U << CAN_FMCFG_FMSEL19_Pos) /*!< 0x00080000 */ +#define CAN_FMCFG_FMSEL19 CAN_FMCFG_FMSEL19_Msk /*!< Filter mode select for filter 19 */ +#define CAN_FMCFG_FMSEL20_Pos (20U) +#define CAN_FMCFG_FMSEL20_Msk (0x1U << CAN_FMCFG_FMSEL20_Pos) /*!< 0x00100000 */ +#define CAN_FMCFG_FMSEL20 CAN_FMCFG_FMSEL20_Msk /*!< Filter mode select for filter 20 */ +#define CAN_FMCFG_FMSEL21_Pos (21U) +#define CAN_FMCFG_FMSEL21_Msk (0x1U << CAN_FMCFG_FMSEL21_Pos) /*!< 0x00200000 */ +#define CAN_FMCFG_FMSEL21 CAN_FMCFG_FMSEL21_Msk /*!< Filter mode select for filter 21 */ +#define CAN_FMCFG_FMSEL22_Pos (22U) +#define CAN_FMCFG_FMSEL22_Msk (0x1U << CAN_FMCFG_FMSEL22_Pos) /*!< 0x00400000 */ +#define CAN_FMCFG_FMSEL22 CAN_FMCFG_FMSEL22_Msk /*!< Filter mode select for filter 22 */ +#define CAN_FMCFG_FMSEL23_Pos (23U) +#define CAN_FMCFG_FMSEL23_Msk (0x1U << CAN_FMCFG_FMSEL23_Pos) /*!< 0x00800000 */ +#define CAN_FMCFG_FMSEL23 CAN_FMCFG_FMSEL23_Msk /*!< Filter mode select for filter 23 */ +#define CAN_FMCFG_FMSEL24_Pos (24U) +#define CAN_FMCFG_FMSEL24_Msk (0x1U << CAN_FMCFG_FMSEL24_Pos) /*!< 0x01000000 */ +#define CAN_FMCFG_FMSEL24 CAN_FMCFG_FMSEL24_Msk /*!< Filter mode select for filter 24 */ +#define CAN_FMCFG_FMSEL25_Pos (25U) +#define CAN_FMCFG_FMSEL25_Msk (0x1U << CAN_FMCFG_FMSEL25_Pos) /*!< 0x02000000 */ +#define CAN_FMCFG_FMSEL25 CAN_FMCFG_FMSEL25_Msk /*!< Filter mode select for filter 25 */ +#define CAN_FMCFG_FMSEL26_Pos (26U) +#define CAN_FMCFG_FMSEL26_Msk (0x1U << CAN_FMCFG_FMSEL26_Pos) /*!< 0x04000000 */ +#define CAN_FMCFG_FMSEL26 CAN_FMCFG_FMSEL26_Msk /*!< Filter mode select for filter 26 */ +#define CAN_FMCFG_FMSEL27_Pos (27U) +#define CAN_FMCFG_FMSEL27_Msk (0x1U << CAN_FMCFG_FMSEL27_Pos) /*!< 0x08000000 */ +#define CAN_FMCFG_FMSEL27 CAN_FMCFG_FMSEL27_Msk /*!< Filter mode select for filter 27 */ + +/****************** Bit definition for CAN_FBWCFG register ******************/ +#define CAN_FBWCFG_FBWSEL_Pos (0U) +#define CAN_FBWCFG_FBWSEL_Msk (0xFFFFFFFU << CAN_FBWCFG_FBWSEL_Pos) /*!< 0x0FFFFFFF */ +#define CAN_FBWCFG_FBWSEL CAN_FBWCFG_FBWSEL_Msk /*!< Filter bit width select */ +#define CAN_FBWCFG_FBWSEL0_Pos (0U) +#define CAN_FBWCFG_FBWSEL0_Msk (0x1U << CAN_FBWCFG_FBWSEL0_Pos) /*!< 0x00000001 */ +#define CAN_FBWCFG_FBWSEL0 CAN_FBWCFG_FBWSEL0_Msk /*!< Filter bit width select for filter 0 */ +#define CAN_FBWCFG_FBWSEL1_Pos (1U) +#define CAN_FBWCFG_FBWSEL1_Msk (0x1U << CAN_FBWCFG_FBWSEL1_Pos) /*!< 0x00000002 */ +#define CAN_FBWCFG_FBWSEL1 CAN_FBWCFG_FBWSEL1_Msk /*!< Filter bit width select for filter 1 */ +#define CAN_FBWCFG_FBWSEL2_Pos (2U) +#define CAN_FBWCFG_FBWSEL2_Msk (0x1U << CAN_FBWCFG_FBWSEL2_Pos) /*!< 0x00000004 */ +#define CAN_FBWCFG_FBWSEL2 CAN_FBWCFG_FBWSEL2_Msk /*!< Filter bit width select for filter 2 */ +#define CAN_FBWCFG_FBWSEL3_Pos (3U) +#define CAN_FBWCFG_FBWSEL3_Msk (0x1U << CAN_FBWCFG_FBWSEL3_Pos) /*!< 0x00000008 */ +#define CAN_FBWCFG_FBWSEL3 CAN_FBWCFG_FBWSEL3_Msk /*!< Filter bit width select for filter 3 */ +#define CAN_FBWCFG_FBWSEL4_Pos (4U) +#define CAN_FBWCFG_FBWSEL4_Msk (0x1U << CAN_FBWCFG_FBWSEL4_Pos) /*!< 0x00000010 */ +#define CAN_FBWCFG_FBWSEL4 CAN_FBWCFG_FBWSEL4_Msk /*!< Filter bit width select for filter 4 */ +#define CAN_FBWCFG_FBWSEL5_Pos (5U) +#define CAN_FBWCFG_FBWSEL5_Msk (0x1U << CAN_FBWCFG_FBWSEL5_Pos) /*!< 0x00000020 */ +#define CAN_FBWCFG_FBWSEL5 CAN_FBWCFG_FBWSEL5_Msk /*!< Filter bit width select for filter 5 */ +#define CAN_FBWCFG_FBWSEL6_Pos (6U) +#define CAN_FBWCFG_FBWSEL6_Msk (0x1U << CAN_FBWCFG_FBWSEL6_Pos) /*!< 0x00000040 */ +#define CAN_FBWCFG_FBWSEL6 CAN_FBWCFG_FBWSEL6_Msk /*!< Filter bit width select for filter 6 */ +#define CAN_FBWCFG_FBWSEL7_Pos (7U) +#define CAN_FBWCFG_FBWSEL7_Msk (0x1U << CAN_FBWCFG_FBWSEL7_Pos) /*!< 0x00000080 */ +#define CAN_FBWCFG_FBWSEL7 CAN_FBWCFG_FBWSEL7_Msk /*!< Filter bit width select for filter 7 */ +#define CAN_FBWCFG_FBWSEL8_Pos (8U) +#define CAN_FBWCFG_FBWSEL8_Msk (0x1U << CAN_FBWCFG_FBWSEL8_Pos) /*!< 0x00000100 */ +#define CAN_FBWCFG_FBWSEL8 CAN_FBWCFG_FBWSEL8_Msk /*!< Filter bit width select for filter 8 */ +#define CAN_FBWCFG_FBWSEL9_Pos (9U) +#define CAN_FBWCFG_FBWSEL9_Msk (0x1U << CAN_FBWCFG_FBWSEL9_Pos) /*!< 0x00000200 */ +#define CAN_FBWCFG_FBWSEL9 CAN_FBWCFG_FBWSEL9_Msk /*!< Filter bit width select for filter 9 */ +#define CAN_FBWCFG_FBWSEL10_Pos (10U) +#define CAN_FBWCFG_FBWSEL10_Msk (0x1U << CAN_FBWCFG_FBWSEL10_Pos) /*!< 0x00000400 */ +#define CAN_FBWCFG_FBWSEL10 CAN_FBWCFG_FBWSEL10_Msk /*!< Filter bit width select for filter 10 */ +#define CAN_FBWCFG_FBWSEL11_Pos (11U) +#define CAN_FBWCFG_FBWSEL11_Msk (0x1U << CAN_FBWCFG_FBWSEL11_Pos) /*!< 0x00000800 */ +#define CAN_FBWCFG_FBWSEL11 CAN_FBWCFG_FBWSEL11_Msk /*!< Filter bit width select for filter 11 */ +#define CAN_FBWCFG_FBWSEL12_Pos (12U) +#define CAN_FBWCFG_FBWSEL12_Msk (0x1U << CAN_FBWCFG_FBWSEL12_Pos) /*!< 0x00001000 */ +#define CAN_FBWCFG_FBWSEL12 CAN_FBWCFG_FBWSEL12_Msk /*!< Filter bit width select for filter 12 */ +#define CAN_FBWCFG_FBWSEL13_Pos (13U) +#define CAN_FBWCFG_FBWSEL13_Msk (0x1U << CAN_FBWCFG_FBWSEL13_Pos) /*!< 0x00002000 */ +#define CAN_FBWCFG_FBWSEL13 CAN_FBWCFG_FBWSEL13_Msk /*!< Filter bit width select for filter 13 */ +#define CAN_FBWCFG_FBWSEL14_Pos (14U) +#define CAN_FBWCFG_FBWSEL14_Msk (0x1U << CAN_FBWCFG_FBWSEL14_Pos) /*!< 0x00004000 */ +#define CAN_FBWCFG_FBWSEL14 CAN_FBWCFG_FBWSEL14_Msk /*!< Filter bit width select for filter 14 */ +#define CAN_FBWCFG_FBWSEL15_Pos (15U) +#define CAN_FBWCFG_FBWSEL15_Msk (0x1U << CAN_FBWCFG_FBWSEL15_Pos) /*!< 0x00008000 */ +#define CAN_FBWCFG_FBWSEL15 CAN_FBWCFG_FBWSEL15_Msk /*!< Filter bit width select for filter 15 */ +#define CAN_FBWCFG_FBWSEL16_Pos (16U) +#define CAN_FBWCFG_FBWSEL16_Msk (0x1U << CAN_FBWCFG_FBWSEL16_Pos) /*!< 0x00010000 */ +#define CAN_FBWCFG_FBWSEL16 CAN_FBWCFG_FBWSEL16_Msk /*!< Filter bit width select for filter 16 */ +#define CAN_FBWCFG_FBWSEL17_Pos (17U) +#define CAN_FBWCFG_FBWSEL17_Msk (0x1U << CAN_FBWCFG_FBWSEL17_Pos) /*!< 0x00020000 */ +#define CAN_FBWCFG_FBWSEL17 CAN_FBWCFG_FBWSEL17_Msk /*!< Filter bit width select for filter 17 */ +#define CAN_FBWCFG_FBWSEL18_Pos (18U) +#define CAN_FBWCFG_FBWSEL18_Msk (0x1U << CAN_FBWCFG_FBWSEL18_Pos) /*!< 0x00040000 */ +#define CAN_FBWCFG_FBWSEL18 CAN_FBWCFG_FBWSEL18_Msk /*!< Filter bit width select for filter 18 */ +#define CAN_FBWCFG_FBWSEL19_Pos (19U) +#define CAN_FBWCFG_FBWSEL19_Msk (0x1U << CAN_FBWCFG_FBWSEL19_Pos) /*!< 0x00080000 */ +#define CAN_FBWCFG_FBWSEL19 CAN_FBWCFG_FBWSEL19_Msk /*!< Filter bit width select for filter 19 */ +#define CAN_FBWCFG_FBWSEL20_Pos (20U) +#define CAN_FBWCFG_FBWSEL20_Msk (0x1U << CAN_FBWCFG_FBWSEL20_Pos) /*!< 0x00100000 */ +#define CAN_FBWCFG_FBWSEL20 CAN_FBWCFG_FBWSEL20_Msk /*!< Filter bit width select for filter 20 */ +#define CAN_FBWCFG_FBWSEL21_Pos (21U) +#define CAN_FBWCFG_FBWSEL21_Msk (0x1U << CAN_FBWCFG_FBWSEL21_Pos) /*!< 0x00200000 */ +#define CAN_FBWCFG_FBWSEL21 CAN_FBWCFG_FBWSEL21_Msk /*!< Filter bit width select for filter 21 */ +#define CAN_FBWCFG_FBWSEL22_Pos (22U) +#define CAN_FBWCFG_FBWSEL22_Msk (0x1U << CAN_FBWCFG_FBWSEL22_Pos) /*!< 0x00400000 */ +#define CAN_FBWCFG_FBWSEL22 CAN_FBWCFG_FBWSEL22_Msk /*!< Filter bit width select for filter 22 */ +#define CAN_FBWCFG_FBWSEL23_Pos (23U) +#define CAN_FBWCFG_FBWSEL23_Msk (0x1U << CAN_FBWCFG_FBWSEL23_Pos) /*!< 0x00800000 */ +#define CAN_FBWCFG_FBWSEL23 CAN_FBWCFG_FBWSEL23_Msk /*!< Filter bit width select for filter 23 */ +#define CAN_FBWCFG_FBWSEL24_Pos (24U) +#define CAN_FBWCFG_FBWSEL24_Msk (0x1U << CAN_FBWCFG_FBWSEL24_Pos) /*!< 0x01000000 */ +#define CAN_FBWCFG_FBWSEL24 CAN_FBWCFG_FBWSEL24_Msk /*!< Filter bit width select for filter 24 */ +#define CAN_FBWCFG_FBWSEL25_Pos (25U) +#define CAN_FBWCFG_FBWSEL25_Msk (0x1U << CAN_FBWCFG_FBWSEL25_Pos) /*!< 0x02000000 */ +#define CAN_FBWCFG_FBWSEL25 CAN_FBWCFG_FBWSEL25_Msk /*!< Filter bit width select for filter 25 */ +#define CAN_FBWCFG_FBWSEL26_Pos (26U) +#define CAN_FBWCFG_FBWSEL26_Msk (0x1U << CAN_FBWCFG_FBWSEL26_Pos) /*!< 0x04000000 */ +#define CAN_FBWCFG_FBWSEL26 CAN_FBWCFG_FBWSEL26_Msk /*!< Filter bit width select for filter 26 */ +#define CAN_FBWCFG_FBWSEL27_Pos (27U) +#define CAN_FBWCFG_FBWSEL27_Msk (0x1U << CAN_FBWCFG_FBWSEL27_Pos) /*!< 0x08000000 */ +#define CAN_FBWCFG_FBWSEL27 CAN_FBWCFG_FBWSEL27_Msk /*!< Filter bit width select for filter 27 */ + +/******************* Bit definition for CAN_FRF register ********************/ +#define CAN_FRF_FRFSEL_Pos (0U) +#define CAN_FRF_FRFSEL_Msk (0xFFFFFFFU << CAN_FRF_FRFSEL_Pos) /*!< 0x0FFFFFFF */ +#define CAN_FRF_FRFSEL CAN_FRF_FRFSEL_Msk /*!< Filter relation FIFO select */ +#define CAN_FRF_FRFSEL0_Pos (0U) +#define CAN_FRF_FRFSEL0_Msk (0x1U << CAN_FRF_FRFSEL0_Pos) /*!< 0x00000001 */ +#define CAN_FRF_FRFSEL0 CAN_FRF_FRFSEL0_Msk /*!< Filter relation FIFO select for filter 0 */ +#define CAN_FRF_FRFSEL1_Pos (1U) +#define CAN_FRF_FRFSEL1_Msk (0x1U << CAN_FRF_FRFSEL1_Pos) /*!< 0x00000002 */ +#define CAN_FRF_FRFSEL1 CAN_FRF_FRFSEL1_Msk /*!< Filter relation FIFO select for filter 1 */ +#define CAN_FRF_FRFSEL2_Pos (2U) +#define CAN_FRF_FRFSEL2_Msk (0x1U << CAN_FRF_FRFSEL2_Pos) /*!< 0x00000004 */ +#define CAN_FRF_FRFSEL2 CAN_FRF_FRFSEL2_Msk /*!< Filter relation FIFO select for filter 2 */ +#define CAN_FRF_FRFSEL3_Pos (3U) +#define CAN_FRF_FRFSEL3_Msk (0x1U << CAN_FRF_FRFSEL3_Pos) /*!< 0x00000008 */ +#define CAN_FRF_FRFSEL3 CAN_FRF_FRFSEL3_Msk /*!< Filter relation FIFO select for filter 3 */ +#define CAN_FRF_FRFSEL4_Pos (4U) +#define CAN_FRF_FRFSEL4_Msk (0x1U << CAN_FRF_FRFSEL4_Pos) /*!< 0x00000010 */ +#define CAN_FRF_FRFSEL4 CAN_FRF_FRFSEL4_Msk /*!< Filter relation FIFO select for filter 4 */ +#define CAN_FRF_FRFSEL5_Pos (5U) +#define CAN_FRF_FRFSEL5_Msk (0x1U << CAN_FRF_FRFSEL5_Pos) /*!< 0x00000020 */ +#define CAN_FRF_FRFSEL5 CAN_FRF_FRFSEL5_Msk /*!< Filter relation FIFO select for filter 5 */ +#define CAN_FRF_FRFSEL6_Pos (6U) +#define CAN_FRF_FRFSEL6_Msk (0x1U << CAN_FRF_FRFSEL6_Pos) /*!< 0x00000040 */ +#define CAN_FRF_FRFSEL6 CAN_FRF_FRFSEL6_Msk /*!< Filter relation FIFO select for filter 6 */ +#define CAN_FRF_FRFSEL7_Pos (7U) +#define CAN_FRF_FRFSEL7_Msk (0x1U << CAN_FRF_FRFSEL7_Pos) /*!< 0x00000080 */ +#define CAN_FRF_FRFSEL7 CAN_FRF_FRFSEL7_Msk /*!< Filter relation FIFO select for filter 7 */ +#define CAN_FRF_FRFSEL8_Pos (8U) +#define CAN_FRF_FRFSEL8_Msk (0x1U << CAN_FRF_FRFSEL8_Pos) /*!< 0x00000100 */ +#define CAN_FRF_FRFSEL8 CAN_FRF_FRFSEL8_Msk /*!< Filter relation FIFO select for filter 8 */ +#define CAN_FRF_FRFSEL9_Pos (9U) +#define CAN_FRF_FRFSEL9_Msk (0x1U << CAN_FRF_FRFSEL9_Pos) /*!< 0x00000200 */ +#define CAN_FRF_FRFSEL9 CAN_FRF_FRFSEL9_Msk /*!< Filter relation FIFO select for filter 9 */ +#define CAN_FRF_FRFSEL10_Pos (10U) +#define CAN_FRF_FRFSEL10_Msk (0x1U << CAN_FRF_FRFSEL10_Pos) /*!< 0x00000400 */ +#define CAN_FRF_FRFSEL10 CAN_FRF_FRFSEL10_Msk /*!< Filter relation FIFO select for filter 10 */ +#define CAN_FRF_FRFSEL11_Pos (11U) +#define CAN_FRF_FRFSEL11_Msk (0x1U << CAN_FRF_FRFSEL11_Pos) /*!< 0x00000800 */ +#define CAN_FRF_FRFSEL11 CAN_FRF_FRFSEL11_Msk /*!< Filter relation FIFO select for filter 11 */ +#define CAN_FRF_FRFSEL12_Pos (12U) +#define CAN_FRF_FRFSEL12_Msk (0x1U << CAN_FRF_FRFSEL12_Pos) /*!< 0x00001000 */ +#define CAN_FRF_FRFSEL12 CAN_FRF_FRFSEL12_Msk /*!< Filter relation FIFO select for filter 12 */ +#define CAN_FRF_FRFSEL13_Pos (13U) +#define CAN_FRF_FRFSEL13_Msk (0x1U << CAN_FRF_FRFSEL13_Pos) /*!< 0x00002000 */ +#define CAN_FRF_FRFSEL13 CAN_FRF_FRFSEL13_Msk /*!< Filter relation FIFO select for filter 13 */ +#define CAN_FRF_FRFSEL14_Pos (14U) +#define CAN_FRF_FRFSEL14_Msk (0x1U << CAN_FRF_FRFSEL14_Pos) /*!< 0x00004000 */ +#define CAN_FRF_FRFSEL14 CAN_FRF_FRFSEL14_Msk /*!< Filter relation FIFO select for filter 14 */ +#define CAN_FRF_FRFSEL15_Pos (15U) +#define CAN_FRF_FRFSEL15_Msk (0x1U << CAN_FRF_FRFSEL15_Pos) /*!< 0x00008000 */ +#define CAN_FRF_FRFSEL15 CAN_FRF_FRFSEL15_Msk /*!< Filter relation FIFO select for filter 15 */ +#define CAN_FRF_FRFSEL16_Pos (16U) +#define CAN_FRF_FRFSEL16_Msk (0x1U << CAN_FRF_FRFSEL16_Pos) /*!< 0x00010000 */ +#define CAN_FRF_FRFSEL16 CAN_FRF_FRFSEL16_Msk /*!< Filter relation FIFO select for filter 16 */ +#define CAN_FRF_FRFSEL17_Pos (17U) +#define CAN_FRF_FRFSEL17_Msk (0x1U << CAN_FRF_FRFSEL17_Pos) /*!< 0x00020000 */ +#define CAN_FRF_FRFSEL17 CAN_FRF_FRFSEL17_Msk /*!< Filter relation FIFO select for filter 17 */ +#define CAN_FRF_FRFSEL18_Pos (18U) +#define CAN_FRF_FRFSEL18_Msk (0x1U << CAN_FRF_FRFSEL18_Pos) /*!< 0x00040000 */ +#define CAN_FRF_FRFSEL18 CAN_FRF_FRFSEL18_Msk /*!< Filter relation FIFO select for filter 18 */ +#define CAN_FRF_FRFSEL19_Pos (19U) +#define CAN_FRF_FRFSEL19_Msk (0x1U << CAN_FRF_FRFSEL19_Pos) /*!< 0x00080000 */ +#define CAN_FRF_FRFSEL19 CAN_FRF_FRFSEL19_Msk /*!< Filter relation FIFO select for filter 19 */ +#define CAN_FRF_FRFSEL20_Pos (20U) +#define CAN_FRF_FRFSEL20_Msk (0x1U << CAN_FRF_FRFSEL20_Pos) /*!< 0x00100000 */ +#define CAN_FRF_FRFSEL20 CAN_FRF_FRFSEL20_Msk /*!< Filter relation FIFO select for filter 20 */ +#define CAN_FRF_FRFSEL21_Pos (21U) +#define CAN_FRF_FRFSEL21_Msk (0x1U << CAN_FRF_FRFSEL21_Pos) /*!< 0x00200000 */ +#define CAN_FRF_FRFSEL21 CAN_FRF_FRFSEL21_Msk /*!< Filter relation FIFO select for filter 21 */ +#define CAN_FRF_FRFSEL22_Pos (22U) +#define CAN_FRF_FRFSEL22_Msk (0x1U << CAN_FRF_FRFSEL22_Pos) /*!< 0x00400000 */ +#define CAN_FRF_FRFSEL22 CAN_FRF_FRFSEL22_Msk /*!< Filter relation FIFO select for filter 22 */ +#define CAN_FRF_FRFSEL23_Pos (23U) +#define CAN_FRF_FRFSEL23_Msk (0x1U << CAN_FRF_FRFSEL23_Pos) /*!< 0x00800000 */ +#define CAN_FRF_FRFSEL23 CAN_FRF_FRFSEL23_Msk /*!< Filter relation FIFO select for filter 23 */ +#define CAN_FRF_FRFSEL24_Pos (24U) +#define CAN_FRF_FRFSEL24_Msk (0x1U << CAN_FRF_FRFSEL24_Pos) /*!< 0x01000000 */ +#define CAN_FRF_FRFSEL24 CAN_FRF_FRFSEL24_Msk /*!< Filter relation FIFO select for filter 24 */ +#define CAN_FRF_FRFSEL25_Pos (25U) +#define CAN_FRF_FRFSEL25_Msk (0x1U << CAN_FRF_FRFSEL25_Pos) /*!< 0x02000000 */ +#define CAN_FRF_FRFSEL25 CAN_FRF_FRFSEL25_Msk /*!< Filter relation FIFO select for filter 25 */ +#define CAN_FRF_FRFSEL26_Pos (26U) +#define CAN_FRF_FRFSEL26_Msk (0x1U << CAN_FRF_FRFSEL26_Pos) /*!< 0x04000000 */ +#define CAN_FRF_FRFSEL26 CAN_FRF_FRFSEL26_Msk /*!< Filter relation FIFO select for filter 26 */ +#define CAN_FRF_FRFSEL27_Pos (27U) +#define CAN_FRF_FRFSEL27_Msk (0x1U << CAN_FRF_FRFSEL27_Pos) /*!< 0x08000000 */ +#define CAN_FRF_FRFSEL27 CAN_FRF_FRFSEL27_Msk /*!< Filter relation FIFO select for filter 27 */ + +/****************** Bit definition for CAN_FACFG register *******************/ +#define CAN_FACFG_FAEN_Pos (0U) +#define CAN_FACFG_FAEN_Msk (0xFFFFFFFU << CAN_FACFG_FAEN_Pos) /*!< 0x0FFFFFFF */ +#define CAN_FACFG_FAEN CAN_FACFG_FAEN_Msk /*!< Filter active enable */ +#define CAN_FACFG_FAEN0_Pos (0U) +#define CAN_FACFG_FAEN0_Msk (0x1U << CAN_FACFG_FAEN0_Pos) /*!< 0x00000001 */ +#define CAN_FACFG_FAEN0 CAN_FACFG_FAEN0_Msk /*!< Filter 0 active enable */ +#define CAN_FACFG_FAEN1_Pos (1U) +#define CAN_FACFG_FAEN1_Msk (0x1U << CAN_FACFG_FAEN1_Pos) /*!< 0x00000002 */ +#define CAN_FACFG_FAEN1 CAN_FACFG_FAEN1_Msk /*!< Filter 1 active enable */ +#define CAN_FACFG_FAEN2_Pos (2U) +#define CAN_FACFG_FAEN2_Msk (0x1U << CAN_FACFG_FAEN2_Pos) /*!< 0x00000004 */ +#define CAN_FACFG_FAEN2 CAN_FACFG_FAEN2_Msk /*!< Filter 2 active enable */ +#define CAN_FACFG_FAEN3_Pos (3U) +#define CAN_FACFG_FAEN3_Msk (0x1U << CAN_FACFG_FAEN3_Pos) /*!< 0x00000008 */ +#define CAN_FACFG_FAEN3 CAN_FACFG_FAEN3_Msk /*!< Filter 3 active enable */ +#define CAN_FACFG_FAEN4_Pos (4U) +#define CAN_FACFG_FAEN4_Msk (0x1U << CAN_FACFG_FAEN4_Pos) /*!< 0x00000010 */ +#define CAN_FACFG_FAEN4 CAN_FACFG_FAEN4_Msk /*!< Filter 4 active enable */ +#define CAN_FACFG_FAEN5_Pos (5U) +#define CAN_FACFG_FAEN5_Msk (0x1U << CAN_FACFG_FAEN5_Pos) /*!< 0x00000020 */ +#define CAN_FACFG_FAEN5 CAN_FACFG_FAEN5_Msk /*!< Filter 5 active enable */ +#define CAN_FACFG_FAEN6_Pos (6U) +#define CAN_FACFG_FAEN6_Msk (0x1U << CAN_FACFG_FAEN6_Pos) /*!< 0x00000040 */ +#define CAN_FACFG_FAEN6 CAN_FACFG_FAEN6_Msk /*!< Filter 6 active enable */ +#define CAN_FACFG_FAEN7_Pos (7U) +#define CAN_FACFG_FAEN7_Msk (0x1U << CAN_FACFG_FAEN7_Pos) /*!< 0x00000080 */ +#define CAN_FACFG_FAEN7 CAN_FACFG_FAEN7_Msk /*!< Filter 7 active enable */ +#define CAN_FACFG_FAEN8_Pos (8U) +#define CAN_FACFG_FAEN8_Msk (0x1U << CAN_FACFG_FAEN8_Pos) /*!< 0x00000100 */ +#define CAN_FACFG_FAEN8 CAN_FACFG_FAEN8_Msk /*!< Filter 8 active enable */ +#define CAN_FACFG_FAEN9_Pos (9U) +#define CAN_FACFG_FAEN9_Msk (0x1U << CAN_FACFG_FAEN9_Pos) /*!< 0x00000200 */ +#define CAN_FACFG_FAEN9 CAN_FACFG_FAEN9_Msk /*!< Filter 9 active enable */ +#define CAN_FACFG_FAEN10_Pos (10U) +#define CAN_FACFG_FAEN10_Msk (0x1U << CAN_FACFG_FAEN10_Pos) /*!< 0x00000400 */ +#define CAN_FACFG_FAEN10 CAN_FACFG_FAEN10_Msk /*!< Filter 10 active enable */ +#define CAN_FACFG_FAEN11_Pos (11U) +#define CAN_FACFG_FAEN11_Msk (0x1U << CAN_FACFG_FAEN11_Pos) /*!< 0x00000800 */ +#define CAN_FACFG_FAEN11 CAN_FACFG_FAEN11_Msk /*!< Filter 11 active enable */ +#define CAN_FACFG_FAEN12_Pos (12U) +#define CAN_FACFG_FAEN12_Msk (0x1U << CAN_FACFG_FAEN12_Pos) /*!< 0x00001000 */ +#define CAN_FACFG_FAEN12 CAN_FACFG_FAEN12_Msk /*!< Filter 12 active enable */ +#define CAN_FACFG_FAEN13_Pos (13U) +#define CAN_FACFG_FAEN13_Msk (0x1U << CAN_FACFG_FAEN13_Pos) /*!< 0x00002000 */ +#define CAN_FACFG_FAEN13 CAN_FACFG_FAEN13_Msk /*!< Filter 13 active enable */ +#define CAN_FACFG_FAEN14_Pos (14U) +#define CAN_FACFG_FAEN14_Msk (0x1U << CAN_FACFG_FAEN14_Pos) /*!< 0x00004000 */ +#define CAN_FACFG_FAEN14 CAN_FACFG_FAEN14_Msk /*!< Filter 14 active enable */ +#define CAN_FACFG_FAEN15_Pos (15U) +#define CAN_FACFG_FAEN15_Msk (0x1U << CAN_FACFG_FAEN15_Pos) /*!< 0x00008000 */ +#define CAN_FACFG_FAEN15 CAN_FACFG_FAEN15_Msk /*!< Filter 15 active enable */ +#define CAN_FACFG_FAEN16_Pos (16U) +#define CAN_FACFG_FAEN16_Msk (0x1U << CAN_FACFG_FAEN16_Pos) /*!< 0x00010000 */ +#define CAN_FACFG_FAEN16 CAN_FACFG_FAEN16_Msk /*!< Filter 16 active enable */ +#define CAN_FACFG_FAEN17_Pos (17U) +#define CAN_FACFG_FAEN17_Msk (0x1U << CAN_FACFG_FAEN17_Pos) /*!< 0x00020000 */ +#define CAN_FACFG_FAEN17 CAN_FACFG_FAEN17_Msk /*!< Filter 17 active enable */ +#define CAN_FACFG_FAEN18_Pos (18U) +#define CAN_FACFG_FAEN18_Msk (0x1U << CAN_FACFG_FAEN18_Pos) /*!< 0x00040000 */ +#define CAN_FACFG_FAEN18 CAN_FACFG_FAEN18_Msk /*!< Filter 18 active enable */ +#define CAN_FACFG_FAEN19_Pos (19U) +#define CAN_FACFG_FAEN19_Msk (0x1U << CAN_FACFG_FAEN19_Pos) /*!< 0x00080000 */ +#define CAN_FACFG_FAEN19 CAN_FACFG_FAEN19_Msk /*!< Filter 19 active enable */ +#define CAN_FACFG_FAEN20_Pos (20U) +#define CAN_FACFG_FAEN20_Msk (0x1U << CAN_FACFG_FAEN20_Pos) /*!< 0x00100000 */ +#define CAN_FACFG_FAEN20 CAN_FACFG_FAEN20_Msk /*!< Filter 20 active enable */ +#define CAN_FACFG_FAEN21_Pos (21U) +#define CAN_FACFG_FAEN21_Msk (0x1U << CAN_FACFG_FAEN21_Pos) /*!< 0x00200000 */ +#define CAN_FACFG_FAEN21 CAN_FACFG_FAEN21_Msk /*!< Filter 21 active enable */ +#define CAN_FACFG_FAEN22_Pos (22U) +#define CAN_FACFG_FAEN22_Msk (0x1U << CAN_FACFG_FAEN22_Pos) /*!< 0x00400000 */ +#define CAN_FACFG_FAEN22 CAN_FACFG_FAEN22_Msk /*!< Filter 22 active enable */ +#define CAN_FACFG_FAEN23_Pos (23U) +#define CAN_FACFG_FAEN23_Msk (0x1U << CAN_FACFG_FAEN23_Pos) /*!< 0x00800000 */ +#define CAN_FACFG_FAEN23 CAN_FACFG_FAEN23_Msk /*!< Filter 23 active enable */ +#define CAN_FACFG_FAEN24_Pos (24U) +#define CAN_FACFG_FAEN24_Msk (0x1U << CAN_FACFG_FAEN24_Pos) /*!< 0x01000000 */ +#define CAN_FACFG_FAEN24 CAN_FACFG_FAEN24_Msk /*!< Filter 24 active enable */ +#define CAN_FACFG_FAEN25_Pos (25U) +#define CAN_FACFG_FAEN25_Msk (0x1U << CAN_FACFG_FAEN25_Pos) /*!< 0x02000000 */ +#define CAN_FACFG_FAEN25 CAN_FACFG_FAEN25_Msk /*!< Filter 25 active enable */ +#define CAN_FACFG_FAEN26_Pos (26U) +#define CAN_FACFG_FAEN26_Msk (0x1U << CAN_FACFG_FAEN26_Pos) /*!< 0x04000000 */ +#define CAN_FACFG_FAEN26 CAN_FACFG_FAEN26_Msk /*!< Filter 26 active enable */ +#define CAN_FACFG_FAEN27_Pos (27U) +#define CAN_FACFG_FAEN27_Msk (0x1U << CAN_FACFG_FAEN27_Pos) /*!< 0x08000000 */ +#define CAN_FACFG_FAEN27 CAN_FACFG_FAEN27_Msk /*!< Filter 27 active enable */ + +/****************** Bit definition for CAN_F0FB1 register *******************/ +#define CAN_F0FB1_FFDB0_Pos (0U) +#define CAN_F0FB1_FFDB0_Msk (0x1U << CAN_F0FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F0FB1_FFDB0 CAN_F0FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F0FB1_FFDB1_Pos (1U) +#define CAN_F0FB1_FFDB1_Msk (0x1U << CAN_F0FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F0FB1_FFDB1 CAN_F0FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F0FB1_FFDB2_Pos (2U) +#define CAN_F0FB1_FFDB2_Msk (0x1U << CAN_F0FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F0FB1_FFDB2 CAN_F0FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F0FB1_FFDB3_Pos (3U) +#define CAN_F0FB1_FFDB3_Msk (0x1U << CAN_F0FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F0FB1_FFDB3 CAN_F0FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F0FB1_FFDB4_Pos (4U) +#define CAN_F0FB1_FFDB4_Msk (0x1U << CAN_F0FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F0FB1_FFDB4 CAN_F0FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F0FB1_FFDB5_Pos (5U) +#define CAN_F0FB1_FFDB5_Msk (0x1U << CAN_F0FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F0FB1_FFDB5 CAN_F0FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F0FB1_FFDB6_Pos (6U) +#define CAN_F0FB1_FFDB6_Msk (0x1U << CAN_F0FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F0FB1_FFDB6 CAN_F0FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F0FB1_FFDB7_Pos (7U) +#define CAN_F0FB1_FFDB7_Msk (0x1U << CAN_F0FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F0FB1_FFDB7 CAN_F0FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F0FB1_FFDB8_Pos (8U) +#define CAN_F0FB1_FFDB8_Msk (0x1U << CAN_F0FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F0FB1_FFDB8 CAN_F0FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F0FB1_FFDB9_Pos (9U) +#define CAN_F0FB1_FFDB9_Msk (0x1U << CAN_F0FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F0FB1_FFDB9 CAN_F0FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F0FB1_FFDB10_Pos (10U) +#define CAN_F0FB1_FFDB10_Msk (0x1U << CAN_F0FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F0FB1_FFDB10 CAN_F0FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F0FB1_FFDB11_Pos (11U) +#define CAN_F0FB1_FFDB11_Msk (0x1U << CAN_F0FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F0FB1_FFDB11 CAN_F0FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F0FB1_FFDB12_Pos (12U) +#define CAN_F0FB1_FFDB12_Msk (0x1U << CAN_F0FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F0FB1_FFDB12 CAN_F0FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F0FB1_FFDB13_Pos (13U) +#define CAN_F0FB1_FFDB13_Msk (0x1U << CAN_F0FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F0FB1_FFDB13 CAN_F0FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F0FB1_FFDB14_Pos (14U) +#define CAN_F0FB1_FFDB14_Msk (0x1U << CAN_F0FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F0FB1_FFDB14 CAN_F0FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F0FB1_FFDB15_Pos (15U) +#define CAN_F0FB1_FFDB15_Msk (0x1U << CAN_F0FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F0FB1_FFDB15 CAN_F0FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F0FB1_FFDB16_Pos (16U) +#define CAN_F0FB1_FFDB16_Msk (0x1U << CAN_F0FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F0FB1_FFDB16 CAN_F0FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F0FB1_FFDB17_Pos (17U) +#define CAN_F0FB1_FFDB17_Msk (0x1U << CAN_F0FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F0FB1_FFDB17 CAN_F0FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F0FB1_FFDB18_Pos (18U) +#define CAN_F0FB1_FFDB18_Msk (0x1U << CAN_F0FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F0FB1_FFDB18 CAN_F0FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F0FB1_FFDB19_Pos (19U) +#define CAN_F0FB1_FFDB19_Msk (0x1U << CAN_F0FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F0FB1_FFDB19 CAN_F0FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F0FB1_FFDB20_Pos (20U) +#define CAN_F0FB1_FFDB20_Msk (0x1U << CAN_F0FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F0FB1_FFDB20 CAN_F0FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F0FB1_FFDB21_Pos (21U) +#define CAN_F0FB1_FFDB21_Msk (0x1U << CAN_F0FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F0FB1_FFDB21 CAN_F0FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F0FB1_FFDB22_Pos (22U) +#define CAN_F0FB1_FFDB22_Msk (0x1U << CAN_F0FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F0FB1_FFDB22 CAN_F0FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F0FB1_FFDB23_Pos (23U) +#define CAN_F0FB1_FFDB23_Msk (0x1U << CAN_F0FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F0FB1_FFDB23 CAN_F0FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F0FB1_FFDB24_Pos (24U) +#define CAN_F0FB1_FFDB24_Msk (0x1U << CAN_F0FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F0FB1_FFDB24 CAN_F0FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F0FB1_FFDB25_Pos (25U) +#define CAN_F0FB1_FFDB25_Msk (0x1U << CAN_F0FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F0FB1_FFDB25 CAN_F0FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F0FB1_FFDB26_Pos (26U) +#define CAN_F0FB1_FFDB26_Msk (0x1U << CAN_F0FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F0FB1_FFDB26 CAN_F0FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F0FB1_FFDB27_Pos (27U) +#define CAN_F0FB1_FFDB27_Msk (0x1U << CAN_F0FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F0FB1_FFDB27 CAN_F0FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F0FB1_FFDB28_Pos (28U) +#define CAN_F0FB1_FFDB28_Msk (0x1U << CAN_F0FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F0FB1_FFDB28 CAN_F0FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F0FB1_FFDB29_Pos (29U) +#define CAN_F0FB1_FFDB29_Msk (0x1U << CAN_F0FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F0FB1_FFDB29 CAN_F0FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F0FB1_FFDB30_Pos (30U) +#define CAN_F0FB1_FFDB30_Msk (0x1U << CAN_F0FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F0FB1_FFDB30 CAN_F0FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F0FB1_FFDB31_Pos (31U) +#define CAN_F0FB1_FFDB31_Msk (0x1U << CAN_F0FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F0FB1_FFDB31 CAN_F0FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F1FB1 register *******************/ +#define CAN_F1FB1_FFDB0_Pos (0U) +#define CAN_F1FB1_FFDB0_Msk (0x1U << CAN_F1FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F1FB1_FFDB0 CAN_F1FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F1FB1_FFDB1_Pos (1U) +#define CAN_F1FB1_FFDB1_Msk (0x1U << CAN_F1FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F1FB1_FFDB1 CAN_F1FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F1FB1_FFDB2_Pos (2U) +#define CAN_F1FB1_FFDB2_Msk (0x1U << CAN_F1FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F1FB1_FFDB2 CAN_F1FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F1FB1_FFDB3_Pos (3U) +#define CAN_F1FB1_FFDB3_Msk (0x1U << CAN_F1FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F1FB1_FFDB3 CAN_F1FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F1FB1_FFDB4_Pos (4U) +#define CAN_F1FB1_FFDB4_Msk (0x1U << CAN_F1FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F1FB1_FFDB4 CAN_F1FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F1FB1_FFDB5_Pos (5U) +#define CAN_F1FB1_FFDB5_Msk (0x1U << CAN_F1FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F1FB1_FFDB5 CAN_F1FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F1FB1_FFDB6_Pos (6U) +#define CAN_F1FB1_FFDB6_Msk (0x1U << CAN_F1FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F1FB1_FFDB6 CAN_F1FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F1FB1_FFDB7_Pos (7U) +#define CAN_F1FB1_FFDB7_Msk (0x1U << CAN_F1FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F1FB1_FFDB7 CAN_F1FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F1FB1_FFDB8_Pos (8U) +#define CAN_F1FB1_FFDB8_Msk (0x1U << CAN_F1FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F1FB1_FFDB8 CAN_F1FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F1FB1_FFDB9_Pos (9U) +#define CAN_F1FB1_FFDB9_Msk (0x1U << CAN_F1FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F1FB1_FFDB9 CAN_F1FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F1FB1_FFDB10_Pos (10U) +#define CAN_F1FB1_FFDB10_Msk (0x1U << CAN_F1FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F1FB1_FFDB10 CAN_F1FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F1FB1_FFDB11_Pos (11U) +#define CAN_F1FB1_FFDB11_Msk (0x1U << CAN_F1FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F1FB1_FFDB11 CAN_F1FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F1FB1_FFDB12_Pos (12U) +#define CAN_F1FB1_FFDB12_Msk (0x1U << CAN_F1FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F1FB1_FFDB12 CAN_F1FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F1FB1_FFDB13_Pos (13U) +#define CAN_F1FB1_FFDB13_Msk (0x1U << CAN_F1FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F1FB1_FFDB13 CAN_F1FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F1FB1_FFDB14_Pos (14U) +#define CAN_F1FB1_FFDB14_Msk (0x1U << CAN_F1FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F1FB1_FFDB14 CAN_F1FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F1FB1_FFDB15_Pos (15U) +#define CAN_F1FB1_FFDB15_Msk (0x1U << CAN_F1FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F1FB1_FFDB15 CAN_F1FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F1FB1_FFDB16_Pos (16U) +#define CAN_F1FB1_FFDB16_Msk (0x1U << CAN_F1FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F1FB1_FFDB16 CAN_F1FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F1FB1_FFDB17_Pos (17U) +#define CAN_F1FB1_FFDB17_Msk (0x1U << CAN_F1FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F1FB1_FFDB17 CAN_F1FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F1FB1_FFDB18_Pos (18U) +#define CAN_F1FB1_FFDB18_Msk (0x1U << CAN_F1FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F1FB1_FFDB18 CAN_F1FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F1FB1_FFDB19_Pos (19U) +#define CAN_F1FB1_FFDB19_Msk (0x1U << CAN_F1FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F1FB1_FFDB19 CAN_F1FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F1FB1_FFDB20_Pos (20U) +#define CAN_F1FB1_FFDB20_Msk (0x1U << CAN_F1FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F1FB1_FFDB20 CAN_F1FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F1FB1_FFDB21_Pos (21U) +#define CAN_F1FB1_FFDB21_Msk (0x1U << CAN_F1FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F1FB1_FFDB21 CAN_F1FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F1FB1_FFDB22_Pos (22U) +#define CAN_F1FB1_FFDB22_Msk (0x1U << CAN_F1FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F1FB1_FFDB22 CAN_F1FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F1FB1_FFDB23_Pos (23U) +#define CAN_F1FB1_FFDB23_Msk (0x1U << CAN_F1FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F1FB1_FFDB23 CAN_F1FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F1FB1_FFDB24_Pos (24U) +#define CAN_F1FB1_FFDB24_Msk (0x1U << CAN_F1FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F1FB1_FFDB24 CAN_F1FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F1FB1_FFDB25_Pos (25U) +#define CAN_F1FB1_FFDB25_Msk (0x1U << CAN_F1FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F1FB1_FFDB25 CAN_F1FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F1FB1_FFDB26_Pos (26U) +#define CAN_F1FB1_FFDB26_Msk (0x1U << CAN_F1FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F1FB1_FFDB26 CAN_F1FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F1FB1_FFDB27_Pos (27U) +#define CAN_F1FB1_FFDB27_Msk (0x1U << CAN_F1FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F1FB1_FFDB27 CAN_F1FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F1FB1_FFDB28_Pos (28U) +#define CAN_F1FB1_FFDB28_Msk (0x1U << CAN_F1FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F1FB1_FFDB28 CAN_F1FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F1FB1_FFDB29_Pos (29U) +#define CAN_F1FB1_FFDB29_Msk (0x1U << CAN_F1FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F1FB1_FFDB29 CAN_F1FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F1FB1_FFDB30_Pos (30U) +#define CAN_F1FB1_FFDB30_Msk (0x1U << CAN_F1FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F1FB1_FFDB30 CAN_F1FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F1FB1_FFDB31_Pos (31U) +#define CAN_F1FB1_FFDB31_Msk (0x1U << CAN_F1FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F1FB1_FFDB31 CAN_F1FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F2FB1 register *******************/ +#define CAN_F2FB1_FFDB0_Pos (0U) +#define CAN_F2FB1_FFDB0_Msk (0x1U << CAN_F2FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F2FB1_FFDB0 CAN_F2FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F2FB1_FFDB1_Pos (1U) +#define CAN_F2FB1_FFDB1_Msk (0x1U << CAN_F2FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F2FB1_FFDB1 CAN_F2FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F2FB1_FFDB2_Pos (2U) +#define CAN_F2FB1_FFDB2_Msk (0x1U << CAN_F2FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F2FB1_FFDB2 CAN_F2FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F2FB1_FFDB3_Pos (3U) +#define CAN_F2FB1_FFDB3_Msk (0x1U << CAN_F2FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F2FB1_FFDB3 CAN_F2FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F2FB1_FFDB4_Pos (4U) +#define CAN_F2FB1_FFDB4_Msk (0x1U << CAN_F2FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F2FB1_FFDB4 CAN_F2FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F2FB1_FFDB5_Pos (5U) +#define CAN_F2FB1_FFDB5_Msk (0x1U << CAN_F2FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F2FB1_FFDB5 CAN_F2FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F2FB1_FFDB6_Pos (6U) +#define CAN_F2FB1_FFDB6_Msk (0x1U << CAN_F2FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F2FB1_FFDB6 CAN_F2FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F2FB1_FFDB7_Pos (7U) +#define CAN_F2FB1_FFDB7_Msk (0x1U << CAN_F2FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F2FB1_FFDB7 CAN_F2FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F2FB1_FFDB8_Pos (8U) +#define CAN_F2FB1_FFDB8_Msk (0x1U << CAN_F2FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F2FB1_FFDB8 CAN_F2FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F2FB1_FFDB9_Pos (9U) +#define CAN_F2FB1_FFDB9_Msk (0x1U << CAN_F2FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F2FB1_FFDB9 CAN_F2FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F2FB1_FFDB10_Pos (10U) +#define CAN_F2FB1_FFDB10_Msk (0x1U << CAN_F2FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F2FB1_FFDB10 CAN_F2FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F2FB1_FFDB11_Pos (11U) +#define CAN_F2FB1_FFDB11_Msk (0x1U << CAN_F2FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F2FB1_FFDB11 CAN_F2FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F2FB1_FFDB12_Pos (12U) +#define CAN_F2FB1_FFDB12_Msk (0x1U << CAN_F2FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F2FB1_FFDB12 CAN_F2FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F2FB1_FFDB13_Pos (13U) +#define CAN_F2FB1_FFDB13_Msk (0x1U << CAN_F2FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F2FB1_FFDB13 CAN_F2FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F2FB1_FFDB14_Pos (14U) +#define CAN_F2FB1_FFDB14_Msk (0x1U << CAN_F2FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F2FB1_FFDB14 CAN_F2FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F2FB1_FFDB15_Pos (15U) +#define CAN_F2FB1_FFDB15_Msk (0x1U << CAN_F2FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F2FB1_FFDB15 CAN_F2FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F2FB1_FFDB16_Pos (16U) +#define CAN_F2FB1_FFDB16_Msk (0x1U << CAN_F2FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F2FB1_FFDB16 CAN_F2FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F2FB1_FFDB17_Pos (17U) +#define CAN_F2FB1_FFDB17_Msk (0x1U << CAN_F2FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F2FB1_FFDB17 CAN_F2FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F2FB1_FFDB18_Pos (18U) +#define CAN_F2FB1_FFDB18_Msk (0x1U << CAN_F2FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F2FB1_FFDB18 CAN_F2FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F2FB1_FFDB19_Pos (19U) +#define CAN_F2FB1_FFDB19_Msk (0x1U << CAN_F2FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F2FB1_FFDB19 CAN_F2FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F2FB1_FFDB20_Pos (20U) +#define CAN_F2FB1_FFDB20_Msk (0x1U << CAN_F2FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F2FB1_FFDB20 CAN_F2FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F2FB1_FFDB21_Pos (21U) +#define CAN_F2FB1_FFDB21_Msk (0x1U << CAN_F2FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F2FB1_FFDB21 CAN_F2FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F2FB1_FFDB22_Pos (22U) +#define CAN_F2FB1_FFDB22_Msk (0x1U << CAN_F2FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F2FB1_FFDB22 CAN_F2FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F2FB1_FFDB23_Pos (23U) +#define CAN_F2FB1_FFDB23_Msk (0x1U << CAN_F2FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F2FB1_FFDB23 CAN_F2FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F2FB1_FFDB24_Pos (24U) +#define CAN_F2FB1_FFDB24_Msk (0x1U << CAN_F2FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F2FB1_FFDB24 CAN_F2FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F2FB1_FFDB25_Pos (25U) +#define CAN_F2FB1_FFDB25_Msk (0x1U << CAN_F2FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F2FB1_FFDB25 CAN_F2FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F2FB1_FFDB26_Pos (26U) +#define CAN_F2FB1_FFDB26_Msk (0x1U << CAN_F2FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F2FB1_FFDB26 CAN_F2FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F2FB1_FFDB27_Pos (27U) +#define CAN_F2FB1_FFDB27_Msk (0x1U << CAN_F2FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F2FB1_FFDB27 CAN_F2FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F2FB1_FFDB28_Pos (28U) +#define CAN_F2FB1_FFDB28_Msk (0x1U << CAN_F2FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F2FB1_FFDB28 CAN_F2FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F2FB1_FFDB29_Pos (29U) +#define CAN_F2FB1_FFDB29_Msk (0x1U << CAN_F2FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F2FB1_FFDB29 CAN_F2FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F2FB1_FFDB30_Pos (30U) +#define CAN_F2FB1_FFDB30_Msk (0x1U << CAN_F2FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F2FB1_FFDB30 CAN_F2FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F2FB1_FFDB31_Pos (31U) +#define CAN_F2FB1_FFDB31_Msk (0x1U << CAN_F2FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F2FB1_FFDB31 CAN_F2FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F3FB1 register *******************/ +#define CAN_F3FB1_FFDB0_Pos (0U) +#define CAN_F3FB1_FFDB0_Msk (0x1U << CAN_F3FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F3FB1_FFDB0 CAN_F3FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F3FB1_FFDB1_Pos (1U) +#define CAN_F3FB1_FFDB1_Msk (0x1U << CAN_F3FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F3FB1_FFDB1 CAN_F3FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F3FB1_FFDB2_Pos (2U) +#define CAN_F3FB1_FFDB2_Msk (0x1U << CAN_F3FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F3FB1_FFDB2 CAN_F3FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F3FB1_FFDB3_Pos (3U) +#define CAN_F3FB1_FFDB3_Msk (0x1U << CAN_F3FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F3FB1_FFDB3 CAN_F3FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F3FB1_FFDB4_Pos (4U) +#define CAN_F3FB1_FFDB4_Msk (0x1U << CAN_F3FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F3FB1_FFDB4 CAN_F3FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F3FB1_FFDB5_Pos (5U) +#define CAN_F3FB1_FFDB5_Msk (0x1U << CAN_F3FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F3FB1_FFDB5 CAN_F3FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F3FB1_FFDB6_Pos (6U) +#define CAN_F3FB1_FFDB6_Msk (0x1U << CAN_F3FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F3FB1_FFDB6 CAN_F3FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F3FB1_FFDB7_Pos (7U) +#define CAN_F3FB1_FFDB7_Msk (0x1U << CAN_F3FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F3FB1_FFDB7 CAN_F3FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F3FB1_FFDB8_Pos (8U) +#define CAN_F3FB1_FFDB8_Msk (0x1U << CAN_F3FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F3FB1_FFDB8 CAN_F3FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F3FB1_FFDB9_Pos (9U) +#define CAN_F3FB1_FFDB9_Msk (0x1U << CAN_F3FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F3FB1_FFDB9 CAN_F3FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F3FB1_FFDB10_Pos (10U) +#define CAN_F3FB1_FFDB10_Msk (0x1U << CAN_F3FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F3FB1_FFDB10 CAN_F3FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F3FB1_FFDB11_Pos (11U) +#define CAN_F3FB1_FFDB11_Msk (0x1U << CAN_F3FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F3FB1_FFDB11 CAN_F3FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F3FB1_FFDB12_Pos (12U) +#define CAN_F3FB1_FFDB12_Msk (0x1U << CAN_F3FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F3FB1_FFDB12 CAN_F3FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F3FB1_FFDB13_Pos (13U) +#define CAN_F3FB1_FFDB13_Msk (0x1U << CAN_F3FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F3FB1_FFDB13 CAN_F3FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F3FB1_FFDB14_Pos (14U) +#define CAN_F3FB1_FFDB14_Msk (0x1U << CAN_F3FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F3FB1_FFDB14 CAN_F3FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F3FB1_FFDB15_Pos (15U) +#define CAN_F3FB1_FFDB15_Msk (0x1U << CAN_F3FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F3FB1_FFDB15 CAN_F3FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F3FB1_FFDB16_Pos (16U) +#define CAN_F3FB1_FFDB16_Msk (0x1U << CAN_F3FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F3FB1_FFDB16 CAN_F3FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F3FB1_FFDB17_Pos (17U) +#define CAN_F3FB1_FFDB17_Msk (0x1U << CAN_F3FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F3FB1_FFDB17 CAN_F3FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F3FB1_FFDB18_Pos (18U) +#define CAN_F3FB1_FFDB18_Msk (0x1U << CAN_F3FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F3FB1_FFDB18 CAN_F3FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F3FB1_FFDB19_Pos (19U) +#define CAN_F3FB1_FFDB19_Msk (0x1U << CAN_F3FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F3FB1_FFDB19 CAN_F3FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F3FB1_FFDB20_Pos (20U) +#define CAN_F3FB1_FFDB20_Msk (0x1U << CAN_F3FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F3FB1_FFDB20 CAN_F3FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F3FB1_FFDB21_Pos (21U) +#define CAN_F3FB1_FFDB21_Msk (0x1U << CAN_F3FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F3FB1_FFDB21 CAN_F3FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F3FB1_FFDB22_Pos (22U) +#define CAN_F3FB1_FFDB22_Msk (0x1U << CAN_F3FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F3FB1_FFDB22 CAN_F3FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F3FB1_FFDB23_Pos (23U) +#define CAN_F3FB1_FFDB23_Msk (0x1U << CAN_F3FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F3FB1_FFDB23 CAN_F3FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F3FB1_FFDB24_Pos (24U) +#define CAN_F3FB1_FFDB24_Msk (0x1U << CAN_F3FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F3FB1_FFDB24 CAN_F3FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F3FB1_FFDB25_Pos (25U) +#define CAN_F3FB1_FFDB25_Msk (0x1U << CAN_F3FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F3FB1_FFDB25 CAN_F3FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F3FB1_FFDB26_Pos (26U) +#define CAN_F3FB1_FFDB26_Msk (0x1U << CAN_F3FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F3FB1_FFDB26 CAN_F3FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F3FB1_FFDB27_Pos (27U) +#define CAN_F3FB1_FFDB27_Msk (0x1U << CAN_F3FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F3FB1_FFDB27 CAN_F3FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F3FB1_FFDB28_Pos (28U) +#define CAN_F3FB1_FFDB28_Msk (0x1U << CAN_F3FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F3FB1_FFDB28 CAN_F3FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F3FB1_FFDB29_Pos (29U) +#define CAN_F3FB1_FFDB29_Msk (0x1U << CAN_F3FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F3FB1_FFDB29 CAN_F3FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F3FB1_FFDB30_Pos (30U) +#define CAN_F3FB1_FFDB30_Msk (0x1U << CAN_F3FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F3FB1_FFDB30 CAN_F3FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F3FB1_FFDB31_Pos (31U) +#define CAN_F3FB1_FFDB31_Msk (0x1U << CAN_F3FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F3FB1_FFDB31 CAN_F3FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F4FB1 register *******************/ +#define CAN_F4FB1_FFDB0_Pos (0U) +#define CAN_F4FB1_FFDB0_Msk (0x1U << CAN_F4FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F4FB1_FFDB0 CAN_F4FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F4FB1_FFDB1_Pos (1U) +#define CAN_F4FB1_FFDB1_Msk (0x1U << CAN_F4FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F4FB1_FFDB1 CAN_F4FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F4FB1_FFDB2_Pos (2U) +#define CAN_F4FB1_FFDB2_Msk (0x1U << CAN_F4FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F4FB1_FFDB2 CAN_F4FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F4FB1_FFDB3_Pos (3U) +#define CAN_F4FB1_FFDB3_Msk (0x1U << CAN_F4FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F4FB1_FFDB3 CAN_F4FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F4FB1_FFDB4_Pos (4U) +#define CAN_F4FB1_FFDB4_Msk (0x1U << CAN_F4FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F4FB1_FFDB4 CAN_F4FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F4FB1_FFDB5_Pos (5U) +#define CAN_F4FB1_FFDB5_Msk (0x1U << CAN_F4FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F4FB1_FFDB5 CAN_F4FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F4FB1_FFDB6_Pos (6U) +#define CAN_F4FB1_FFDB6_Msk (0x1U << CAN_F4FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F4FB1_FFDB6 CAN_F4FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F4FB1_FFDB7_Pos (7U) +#define CAN_F4FB1_FFDB7_Msk (0x1U << CAN_F4FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F4FB1_FFDB7 CAN_F4FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F4FB1_FFDB8_Pos (8U) +#define CAN_F4FB1_FFDB8_Msk (0x1U << CAN_F4FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F4FB1_FFDB8 CAN_F4FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F4FB1_FFDB9_Pos (9U) +#define CAN_F4FB1_FFDB9_Msk (0x1U << CAN_F4FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F4FB1_FFDB9 CAN_F4FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F4FB1_FFDB10_Pos (10U) +#define CAN_F4FB1_FFDB10_Msk (0x1U << CAN_F4FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F4FB1_FFDB10 CAN_F4FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F4FB1_FFDB11_Pos (11U) +#define CAN_F4FB1_FFDB11_Msk (0x1U << CAN_F4FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F4FB1_FFDB11 CAN_F4FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F4FB1_FFDB12_Pos (12U) +#define CAN_F4FB1_FFDB12_Msk (0x1U << CAN_F4FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F4FB1_FFDB12 CAN_F4FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F4FB1_FFDB13_Pos (13U) +#define CAN_F4FB1_FFDB13_Msk (0x1U << CAN_F4FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F4FB1_FFDB13 CAN_F4FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F4FB1_FFDB14_Pos (14U) +#define CAN_F4FB1_FFDB14_Msk (0x1U << CAN_F4FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F4FB1_FFDB14 CAN_F4FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F4FB1_FFDB15_Pos (15U) +#define CAN_F4FB1_FFDB15_Msk (0x1U << CAN_F4FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F4FB1_FFDB15 CAN_F4FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F4FB1_FFDB16_Pos (16U) +#define CAN_F4FB1_FFDB16_Msk (0x1U << CAN_F4FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F4FB1_FFDB16 CAN_F4FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F4FB1_FFDB17_Pos (17U) +#define CAN_F4FB1_FFDB17_Msk (0x1U << CAN_F4FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F4FB1_FFDB17 CAN_F4FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F4FB1_FFDB18_Pos (18U) +#define CAN_F4FB1_FFDB18_Msk (0x1U << CAN_F4FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F4FB1_FFDB18 CAN_F4FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F4FB1_FFDB19_Pos (19U) +#define CAN_F4FB1_FFDB19_Msk (0x1U << CAN_F4FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F4FB1_FFDB19 CAN_F4FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F4FB1_FFDB20_Pos (20U) +#define CAN_F4FB1_FFDB20_Msk (0x1U << CAN_F4FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F4FB1_FFDB20 CAN_F4FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F4FB1_FFDB21_Pos (21U) +#define CAN_F4FB1_FFDB21_Msk (0x1U << CAN_F4FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F4FB1_FFDB21 CAN_F4FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F4FB1_FFDB22_Pos (22U) +#define CAN_F4FB1_FFDB22_Msk (0x1U << CAN_F4FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F4FB1_FFDB22 CAN_F4FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F4FB1_FFDB23_Pos (23U) +#define CAN_F4FB1_FFDB23_Msk (0x1U << CAN_F4FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F4FB1_FFDB23 CAN_F4FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F4FB1_FFDB24_Pos (24U) +#define CAN_F4FB1_FFDB24_Msk (0x1U << CAN_F4FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F4FB1_FFDB24 CAN_F4FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F4FB1_FFDB25_Pos (25U) +#define CAN_F4FB1_FFDB25_Msk (0x1U << CAN_F4FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F4FB1_FFDB25 CAN_F4FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F4FB1_FFDB26_Pos (26U) +#define CAN_F4FB1_FFDB26_Msk (0x1U << CAN_F4FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F4FB1_FFDB26 CAN_F4FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F4FB1_FFDB27_Pos (27U) +#define CAN_F4FB1_FFDB27_Msk (0x1U << CAN_F4FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F4FB1_FFDB27 CAN_F4FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F4FB1_FFDB28_Pos (28U) +#define CAN_F4FB1_FFDB28_Msk (0x1U << CAN_F4FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F4FB1_FFDB28 CAN_F4FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F4FB1_FFDB29_Pos (29U) +#define CAN_F4FB1_FFDB29_Msk (0x1U << CAN_F4FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F4FB1_FFDB29 CAN_F4FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F4FB1_FFDB30_Pos (30U) +#define CAN_F4FB1_FFDB30_Msk (0x1U << CAN_F4FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F4FB1_FFDB30 CAN_F4FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F4FB1_FFDB31_Pos (31U) +#define CAN_F4FB1_FFDB31_Msk (0x1U << CAN_F4FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F4FB1_FFDB31 CAN_F4FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F5FB1 register *******************/ +#define CAN_F5FB1_FFDB0_Pos (0U) +#define CAN_F5FB1_FFDB0_Msk (0x1U << CAN_F5FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F5FB1_FFDB0 CAN_F5FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F5FB1_FFDB1_Pos (1U) +#define CAN_F5FB1_FFDB1_Msk (0x1U << CAN_F5FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F5FB1_FFDB1 CAN_F5FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F5FB1_FFDB2_Pos (2U) +#define CAN_F5FB1_FFDB2_Msk (0x1U << CAN_F5FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F5FB1_FFDB2 CAN_F5FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F5FB1_FFDB3_Pos (3U) +#define CAN_F5FB1_FFDB3_Msk (0x1U << CAN_F5FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F5FB1_FFDB3 CAN_F5FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F5FB1_FFDB4_Pos (4U) +#define CAN_F5FB1_FFDB4_Msk (0x1U << CAN_F5FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F5FB1_FFDB4 CAN_F5FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F5FB1_FFDB5_Pos (5U) +#define CAN_F5FB1_FFDB5_Msk (0x1U << CAN_F5FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F5FB1_FFDB5 CAN_F5FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F5FB1_FFDB6_Pos (6U) +#define CAN_F5FB1_FFDB6_Msk (0x1U << CAN_F5FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F5FB1_FFDB6 CAN_F5FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F5FB1_FFDB7_Pos (7U) +#define CAN_F5FB1_FFDB7_Msk (0x1U << CAN_F5FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F5FB1_FFDB7 CAN_F5FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F5FB1_FFDB8_Pos (8U) +#define CAN_F5FB1_FFDB8_Msk (0x1U << CAN_F5FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F5FB1_FFDB8 CAN_F5FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F5FB1_FFDB9_Pos (9U) +#define CAN_F5FB1_FFDB9_Msk (0x1U << CAN_F5FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F5FB1_FFDB9 CAN_F5FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F5FB1_FFDB10_Pos (10U) +#define CAN_F5FB1_FFDB10_Msk (0x1U << CAN_F5FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F5FB1_FFDB10 CAN_F5FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F5FB1_FFDB11_Pos (11U) +#define CAN_F5FB1_FFDB11_Msk (0x1U << CAN_F5FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F5FB1_FFDB11 CAN_F5FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F5FB1_FFDB12_Pos (12U) +#define CAN_F5FB1_FFDB12_Msk (0x1U << CAN_F5FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F5FB1_FFDB12 CAN_F5FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F5FB1_FFDB13_Pos (13U) +#define CAN_F5FB1_FFDB13_Msk (0x1U << CAN_F5FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F5FB1_FFDB13 CAN_F5FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F5FB1_FFDB14_Pos (14U) +#define CAN_F5FB1_FFDB14_Msk (0x1U << CAN_F5FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F5FB1_FFDB14 CAN_F5FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F5FB1_FFDB15_Pos (15U) +#define CAN_F5FB1_FFDB15_Msk (0x1U << CAN_F5FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F5FB1_FFDB15 CAN_F5FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F5FB1_FFDB16_Pos (16U) +#define CAN_F5FB1_FFDB16_Msk (0x1U << CAN_F5FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F5FB1_FFDB16 CAN_F5FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F5FB1_FFDB17_Pos (17U) +#define CAN_F5FB1_FFDB17_Msk (0x1U << CAN_F5FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F5FB1_FFDB17 CAN_F5FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F5FB1_FFDB18_Pos (18U) +#define CAN_F5FB1_FFDB18_Msk (0x1U << CAN_F5FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F5FB1_FFDB18 CAN_F5FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F5FB1_FFDB19_Pos (19U) +#define CAN_F5FB1_FFDB19_Msk (0x1U << CAN_F5FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F5FB1_FFDB19 CAN_F5FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F5FB1_FFDB20_Pos (20U) +#define CAN_F5FB1_FFDB20_Msk (0x1U << CAN_F5FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F5FB1_FFDB20 CAN_F5FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F5FB1_FFDB21_Pos (21U) +#define CAN_F5FB1_FFDB21_Msk (0x1U << CAN_F5FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F5FB1_FFDB21 CAN_F5FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F5FB1_FFDB22_Pos (22U) +#define CAN_F5FB1_FFDB22_Msk (0x1U << CAN_F5FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F5FB1_FFDB22 CAN_F5FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F5FB1_FFDB23_Pos (23U) +#define CAN_F5FB1_FFDB23_Msk (0x1U << CAN_F5FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F5FB1_FFDB23 CAN_F5FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F5FB1_FFDB24_Pos (24U) +#define CAN_F5FB1_FFDB24_Msk (0x1U << CAN_F5FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F5FB1_FFDB24 CAN_F5FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F5FB1_FFDB25_Pos (25U) +#define CAN_F5FB1_FFDB25_Msk (0x1U << CAN_F5FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F5FB1_FFDB25 CAN_F5FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F5FB1_FFDB26_Pos (26U) +#define CAN_F5FB1_FFDB26_Msk (0x1U << CAN_F5FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F5FB1_FFDB26 CAN_F5FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F5FB1_FFDB27_Pos (27U) +#define CAN_F5FB1_FFDB27_Msk (0x1U << CAN_F5FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F5FB1_FFDB27 CAN_F5FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F5FB1_FFDB28_Pos (28U) +#define CAN_F5FB1_FFDB28_Msk (0x1U << CAN_F5FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F5FB1_FFDB28 CAN_F5FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F5FB1_FFDB29_Pos (29U) +#define CAN_F5FB1_FFDB29_Msk (0x1U << CAN_F5FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F5FB1_FFDB29 CAN_F5FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F5FB1_FFDB30_Pos (30U) +#define CAN_F5FB1_FFDB30_Msk (0x1U << CAN_F5FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F5FB1_FFDB30 CAN_F5FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F5FB1_FFDB31_Pos (31U) +#define CAN_F5FB1_FFDB31_Msk (0x1U << CAN_F5FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F5FB1_FFDB31 CAN_F5FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F6FB1 register *******************/ +#define CAN_F6FB1_FFDB0_Pos (0U) +#define CAN_F6FB1_FFDB0_Msk (0x1U << CAN_F6FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F6FB1_FFDB0 CAN_F6FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F6FB1_FFDB1_Pos (1U) +#define CAN_F6FB1_FFDB1_Msk (0x1U << CAN_F6FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F6FB1_FFDB1 CAN_F6FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F6FB1_FFDB2_Pos (2U) +#define CAN_F6FB1_FFDB2_Msk (0x1U << CAN_F6FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F6FB1_FFDB2 CAN_F6FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F6FB1_FFDB3_Pos (3U) +#define CAN_F6FB1_FFDB3_Msk (0x1U << CAN_F6FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F6FB1_FFDB3 CAN_F6FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F6FB1_FFDB4_Pos (4U) +#define CAN_F6FB1_FFDB4_Msk (0x1U << CAN_F6FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F6FB1_FFDB4 CAN_F6FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F6FB1_FFDB5_Pos (5U) +#define CAN_F6FB1_FFDB5_Msk (0x1U << CAN_F6FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F6FB1_FFDB5 CAN_F6FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F6FB1_FFDB6_Pos (6U) +#define CAN_F6FB1_FFDB6_Msk (0x1U << CAN_F6FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F6FB1_FFDB6 CAN_F6FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F6FB1_FFDB7_Pos (7U) +#define CAN_F6FB1_FFDB7_Msk (0x1U << CAN_F6FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F6FB1_FFDB7 CAN_F6FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F6FB1_FFDB8_Pos (8U) +#define CAN_F6FB1_FFDB8_Msk (0x1U << CAN_F6FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F6FB1_FFDB8 CAN_F6FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F6FB1_FFDB9_Pos (9U) +#define CAN_F6FB1_FFDB9_Msk (0x1U << CAN_F6FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F6FB1_FFDB9 CAN_F6FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F6FB1_FFDB10_Pos (10U) +#define CAN_F6FB1_FFDB10_Msk (0x1U << CAN_F6FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F6FB1_FFDB10 CAN_F6FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F6FB1_FFDB11_Pos (11U) +#define CAN_F6FB1_FFDB11_Msk (0x1U << CAN_F6FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F6FB1_FFDB11 CAN_F6FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F6FB1_FFDB12_Pos (12U) +#define CAN_F6FB1_FFDB12_Msk (0x1U << CAN_F6FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F6FB1_FFDB12 CAN_F6FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F6FB1_FFDB13_Pos (13U) +#define CAN_F6FB1_FFDB13_Msk (0x1U << CAN_F6FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F6FB1_FFDB13 CAN_F6FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F6FB1_FFDB14_Pos (14U) +#define CAN_F6FB1_FFDB14_Msk (0x1U << CAN_F6FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F6FB1_FFDB14 CAN_F6FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F6FB1_FFDB15_Pos (15U) +#define CAN_F6FB1_FFDB15_Msk (0x1U << CAN_F6FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F6FB1_FFDB15 CAN_F6FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F6FB1_FFDB16_Pos (16U) +#define CAN_F6FB1_FFDB16_Msk (0x1U << CAN_F6FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F6FB1_FFDB16 CAN_F6FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F6FB1_FFDB17_Pos (17U) +#define CAN_F6FB1_FFDB17_Msk (0x1U << CAN_F6FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F6FB1_FFDB17 CAN_F6FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F6FB1_FFDB18_Pos (18U) +#define CAN_F6FB1_FFDB18_Msk (0x1U << CAN_F6FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F6FB1_FFDB18 CAN_F6FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F6FB1_FFDB19_Pos (19U) +#define CAN_F6FB1_FFDB19_Msk (0x1U << CAN_F6FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F6FB1_FFDB19 CAN_F6FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F6FB1_FFDB20_Pos (20U) +#define CAN_F6FB1_FFDB20_Msk (0x1U << CAN_F6FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F6FB1_FFDB20 CAN_F6FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F6FB1_FFDB21_Pos (21U) +#define CAN_F6FB1_FFDB21_Msk (0x1U << CAN_F6FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F6FB1_FFDB21 CAN_F6FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F6FB1_FFDB22_Pos (22U) +#define CAN_F6FB1_FFDB22_Msk (0x1U << CAN_F6FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F6FB1_FFDB22 CAN_F6FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F6FB1_FFDB23_Pos (23U) +#define CAN_F6FB1_FFDB23_Msk (0x1U << CAN_F6FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F6FB1_FFDB23 CAN_F6FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F6FB1_FFDB24_Pos (24U) +#define CAN_F6FB1_FFDB24_Msk (0x1U << CAN_F6FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F6FB1_FFDB24 CAN_F6FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F6FB1_FFDB25_Pos (25U) +#define CAN_F6FB1_FFDB25_Msk (0x1U << CAN_F6FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F6FB1_FFDB25 CAN_F6FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F6FB1_FFDB26_Pos (26U) +#define CAN_F6FB1_FFDB26_Msk (0x1U << CAN_F6FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F6FB1_FFDB26 CAN_F6FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F6FB1_FFDB27_Pos (27U) +#define CAN_F6FB1_FFDB27_Msk (0x1U << CAN_F6FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F6FB1_FFDB27 CAN_F6FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F6FB1_FFDB28_Pos (28U) +#define CAN_F6FB1_FFDB28_Msk (0x1U << CAN_F6FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F6FB1_FFDB28 CAN_F6FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F6FB1_FFDB29_Pos (29U) +#define CAN_F6FB1_FFDB29_Msk (0x1U << CAN_F6FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F6FB1_FFDB29 CAN_F6FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F6FB1_FFDB30_Pos (30U) +#define CAN_F6FB1_FFDB30_Msk (0x1U << CAN_F6FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F6FB1_FFDB30 CAN_F6FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F6FB1_FFDB31_Pos (31U) +#define CAN_F6FB1_FFDB31_Msk (0x1U << CAN_F6FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F6FB1_FFDB31 CAN_F6FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F7FB1 register *******************/ +#define CAN_F7FB1_FFDB0_Pos (0U) +#define CAN_F7FB1_FFDB0_Msk (0x1U << CAN_F7FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F7FB1_FFDB0 CAN_F7FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F7FB1_FFDB1_Pos (1U) +#define CAN_F7FB1_FFDB1_Msk (0x1U << CAN_F7FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F7FB1_FFDB1 CAN_F7FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F7FB1_FFDB2_Pos (2U) +#define CAN_F7FB1_FFDB2_Msk (0x1U << CAN_F7FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F7FB1_FFDB2 CAN_F7FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F7FB1_FFDB3_Pos (3U) +#define CAN_F7FB1_FFDB3_Msk (0x1U << CAN_F7FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F7FB1_FFDB3 CAN_F7FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F7FB1_FFDB4_Pos (4U) +#define CAN_F7FB1_FFDB4_Msk (0x1U << CAN_F7FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F7FB1_FFDB4 CAN_F7FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F7FB1_FFDB5_Pos (5U) +#define CAN_F7FB1_FFDB5_Msk (0x1U << CAN_F7FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F7FB1_FFDB5 CAN_F7FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F7FB1_FFDB6_Pos (6U) +#define CAN_F7FB1_FFDB6_Msk (0x1U << CAN_F7FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F7FB1_FFDB6 CAN_F7FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F7FB1_FFDB7_Pos (7U) +#define CAN_F7FB1_FFDB7_Msk (0x1U << CAN_F7FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F7FB1_FFDB7 CAN_F7FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F7FB1_FFDB8_Pos (8U) +#define CAN_F7FB1_FFDB8_Msk (0x1U << CAN_F7FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F7FB1_FFDB8 CAN_F7FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F7FB1_FFDB9_Pos (9U) +#define CAN_F7FB1_FFDB9_Msk (0x1U << CAN_F7FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F7FB1_FFDB9 CAN_F7FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F7FB1_FFDB10_Pos (10U) +#define CAN_F7FB1_FFDB10_Msk (0x1U << CAN_F7FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F7FB1_FFDB10 CAN_F7FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F7FB1_FFDB11_Pos (11U) +#define CAN_F7FB1_FFDB11_Msk (0x1U << CAN_F7FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F7FB1_FFDB11 CAN_F7FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F7FB1_FFDB12_Pos (12U) +#define CAN_F7FB1_FFDB12_Msk (0x1U << CAN_F7FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F7FB1_FFDB12 CAN_F7FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F7FB1_FFDB13_Pos (13U) +#define CAN_F7FB1_FFDB13_Msk (0x1U << CAN_F7FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F7FB1_FFDB13 CAN_F7FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F7FB1_FFDB14_Pos (14U) +#define CAN_F7FB1_FFDB14_Msk (0x1U << CAN_F7FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F7FB1_FFDB14 CAN_F7FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F7FB1_FFDB15_Pos (15U) +#define CAN_F7FB1_FFDB15_Msk (0x1U << CAN_F7FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F7FB1_FFDB15 CAN_F7FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F7FB1_FFDB16_Pos (16U) +#define CAN_F7FB1_FFDB16_Msk (0x1U << CAN_F7FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F7FB1_FFDB16 CAN_F7FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F7FB1_FFDB17_Pos (17U) +#define CAN_F7FB1_FFDB17_Msk (0x1U << CAN_F7FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F7FB1_FFDB17 CAN_F7FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F7FB1_FFDB18_Pos (18U) +#define CAN_F7FB1_FFDB18_Msk (0x1U << CAN_F7FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F7FB1_FFDB18 CAN_F7FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F7FB1_FFDB19_Pos (19U) +#define CAN_F7FB1_FFDB19_Msk (0x1U << CAN_F7FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F7FB1_FFDB19 CAN_F7FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F7FB1_FFDB20_Pos (20U) +#define CAN_F7FB1_FFDB20_Msk (0x1U << CAN_F7FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F7FB1_FFDB20 CAN_F7FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F7FB1_FFDB21_Pos (21U) +#define CAN_F7FB1_FFDB21_Msk (0x1U << CAN_F7FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F7FB1_FFDB21 CAN_F7FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F7FB1_FFDB22_Pos (22U) +#define CAN_F7FB1_FFDB22_Msk (0x1U << CAN_F7FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F7FB1_FFDB22 CAN_F7FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F7FB1_FFDB23_Pos (23U) +#define CAN_F7FB1_FFDB23_Msk (0x1U << CAN_F7FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F7FB1_FFDB23 CAN_F7FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F7FB1_FFDB24_Pos (24U) +#define CAN_F7FB1_FFDB24_Msk (0x1U << CAN_F7FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F7FB1_FFDB24 CAN_F7FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F7FB1_FFDB25_Pos (25U) +#define CAN_F7FB1_FFDB25_Msk (0x1U << CAN_F7FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F7FB1_FFDB25 CAN_F7FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F7FB1_FFDB26_Pos (26U) +#define CAN_F7FB1_FFDB26_Msk (0x1U << CAN_F7FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F7FB1_FFDB26 CAN_F7FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F7FB1_FFDB27_Pos (27U) +#define CAN_F7FB1_FFDB27_Msk (0x1U << CAN_F7FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F7FB1_FFDB27 CAN_F7FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F7FB1_FFDB28_Pos (28U) +#define CAN_F7FB1_FFDB28_Msk (0x1U << CAN_F7FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F7FB1_FFDB28 CAN_F7FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F7FB1_FFDB29_Pos (29U) +#define CAN_F7FB1_FFDB29_Msk (0x1U << CAN_F7FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F7FB1_FFDB29 CAN_F7FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F7FB1_FFDB30_Pos (30U) +#define CAN_F7FB1_FFDB30_Msk (0x1U << CAN_F7FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F7FB1_FFDB30 CAN_F7FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F7FB1_FFDB31_Pos (31U) +#define CAN_F7FB1_FFDB31_Msk (0x1U << CAN_F7FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F7FB1_FFDB31 CAN_F7FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F8FB1 register *******************/ +#define CAN_F8FB1_FFDB0_Pos (0U) +#define CAN_F8FB1_FFDB0_Msk (0x1U << CAN_F8FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F8FB1_FFDB0 CAN_F8FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F8FB1_FFDB1_Pos (1U) +#define CAN_F8FB1_FFDB1_Msk (0x1U << CAN_F8FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F8FB1_FFDB1 CAN_F8FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F8FB1_FFDB2_Pos (2U) +#define CAN_F8FB1_FFDB2_Msk (0x1U << CAN_F8FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F8FB1_FFDB2 CAN_F8FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F8FB1_FFDB3_Pos (3U) +#define CAN_F8FB1_FFDB3_Msk (0x1U << CAN_F8FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F8FB1_FFDB3 CAN_F8FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F8FB1_FFDB4_Pos (4U) +#define CAN_F8FB1_FFDB4_Msk (0x1U << CAN_F8FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F8FB1_FFDB4 CAN_F8FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F8FB1_FFDB5_Pos (5U) +#define CAN_F8FB1_FFDB5_Msk (0x1U << CAN_F8FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F8FB1_FFDB5 CAN_F8FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F8FB1_FFDB6_Pos (6U) +#define CAN_F8FB1_FFDB6_Msk (0x1U << CAN_F8FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F8FB1_FFDB6 CAN_F8FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F8FB1_FFDB7_Pos (7U) +#define CAN_F8FB1_FFDB7_Msk (0x1U << CAN_F8FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F8FB1_FFDB7 CAN_F8FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F8FB1_FFDB8_Pos (8U) +#define CAN_F8FB1_FFDB8_Msk (0x1U << CAN_F8FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F8FB1_FFDB8 CAN_F8FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F8FB1_FFDB9_Pos (9U) +#define CAN_F8FB1_FFDB9_Msk (0x1U << CAN_F8FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F8FB1_FFDB9 CAN_F8FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F8FB1_FFDB10_Pos (10U) +#define CAN_F8FB1_FFDB10_Msk (0x1U << CAN_F8FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F8FB1_FFDB10 CAN_F8FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F8FB1_FFDB11_Pos (11U) +#define CAN_F8FB1_FFDB11_Msk (0x1U << CAN_F8FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F8FB1_FFDB11 CAN_F8FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F8FB1_FFDB12_Pos (12U) +#define CAN_F8FB1_FFDB12_Msk (0x1U << CAN_F8FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F8FB1_FFDB12 CAN_F8FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F8FB1_FFDB13_Pos (13U) +#define CAN_F8FB1_FFDB13_Msk (0x1U << CAN_F8FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F8FB1_FFDB13 CAN_F8FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F8FB1_FFDB14_Pos (14U) +#define CAN_F8FB1_FFDB14_Msk (0x1U << CAN_F8FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F8FB1_FFDB14 CAN_F8FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F8FB1_FFDB15_Pos (15U) +#define CAN_F8FB1_FFDB15_Msk (0x1U << CAN_F8FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F8FB1_FFDB15 CAN_F8FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F8FB1_FFDB16_Pos (16U) +#define CAN_F8FB1_FFDB16_Msk (0x1U << CAN_F8FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F8FB1_FFDB16 CAN_F8FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F8FB1_FFDB17_Pos (17U) +#define CAN_F8FB1_FFDB17_Msk (0x1U << CAN_F8FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F8FB1_FFDB17 CAN_F8FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F8FB1_FFDB18_Pos (18U) +#define CAN_F8FB1_FFDB18_Msk (0x1U << CAN_F8FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F8FB1_FFDB18 CAN_F8FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F8FB1_FFDB19_Pos (19U) +#define CAN_F8FB1_FFDB19_Msk (0x1U << CAN_F8FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F8FB1_FFDB19 CAN_F8FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F8FB1_FFDB20_Pos (20U) +#define CAN_F8FB1_FFDB20_Msk (0x1U << CAN_F8FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F8FB1_FFDB20 CAN_F8FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F8FB1_FFDB21_Pos (21U) +#define CAN_F8FB1_FFDB21_Msk (0x1U << CAN_F8FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F8FB1_FFDB21 CAN_F8FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F8FB1_FFDB22_Pos (22U) +#define CAN_F8FB1_FFDB22_Msk (0x1U << CAN_F8FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F8FB1_FFDB22 CAN_F8FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F8FB1_FFDB23_Pos (23U) +#define CAN_F8FB1_FFDB23_Msk (0x1U << CAN_F8FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F8FB1_FFDB23 CAN_F8FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F8FB1_FFDB24_Pos (24U) +#define CAN_F8FB1_FFDB24_Msk (0x1U << CAN_F8FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F8FB1_FFDB24 CAN_F8FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F8FB1_FFDB25_Pos (25U) +#define CAN_F8FB1_FFDB25_Msk (0x1U << CAN_F8FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F8FB1_FFDB25 CAN_F8FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F8FB1_FFDB26_Pos (26U) +#define CAN_F8FB1_FFDB26_Msk (0x1U << CAN_F8FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F8FB1_FFDB26 CAN_F8FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F8FB1_FFDB27_Pos (27U) +#define CAN_F8FB1_FFDB27_Msk (0x1U << CAN_F8FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F8FB1_FFDB27 CAN_F8FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F8FB1_FFDB28_Pos (28U) +#define CAN_F8FB1_FFDB28_Msk (0x1U << CAN_F8FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F8FB1_FFDB28 CAN_F8FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F8FB1_FFDB29_Pos (29U) +#define CAN_F8FB1_FFDB29_Msk (0x1U << CAN_F8FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F8FB1_FFDB29 CAN_F8FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F8FB1_FFDB30_Pos (30U) +#define CAN_F8FB1_FFDB30_Msk (0x1U << CAN_F8FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F8FB1_FFDB30 CAN_F8FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F8FB1_FFDB31_Pos (31U) +#define CAN_F8FB1_FFDB31_Msk (0x1U << CAN_F8FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F8FB1_FFDB31 CAN_F8FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F9FB1 register *******************/ +#define CAN_F9FB1_FFDB0_Pos (0U) +#define CAN_F9FB1_FFDB0_Msk (0x1U << CAN_F9FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F9FB1_FFDB0 CAN_F9FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F9FB1_FFDB1_Pos (1U) +#define CAN_F9FB1_FFDB1_Msk (0x1U << CAN_F9FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F9FB1_FFDB1 CAN_F9FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F9FB1_FFDB2_Pos (2U) +#define CAN_F9FB1_FFDB2_Msk (0x1U << CAN_F9FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F9FB1_FFDB2 CAN_F9FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F9FB1_FFDB3_Pos (3U) +#define CAN_F9FB1_FFDB3_Msk (0x1U << CAN_F9FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F9FB1_FFDB3 CAN_F9FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F9FB1_FFDB4_Pos (4U) +#define CAN_F9FB1_FFDB4_Msk (0x1U << CAN_F9FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F9FB1_FFDB4 CAN_F9FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F9FB1_FFDB5_Pos (5U) +#define CAN_F9FB1_FFDB5_Msk (0x1U << CAN_F9FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F9FB1_FFDB5 CAN_F9FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F9FB1_FFDB6_Pos (6U) +#define CAN_F9FB1_FFDB6_Msk (0x1U << CAN_F9FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F9FB1_FFDB6 CAN_F9FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F9FB1_FFDB7_Pos (7U) +#define CAN_F9FB1_FFDB7_Msk (0x1U << CAN_F9FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F9FB1_FFDB7 CAN_F9FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F9FB1_FFDB8_Pos (8U) +#define CAN_F9FB1_FFDB8_Msk (0x1U << CAN_F9FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F9FB1_FFDB8 CAN_F9FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F9FB1_FFDB9_Pos (9U) +#define CAN_F9FB1_FFDB9_Msk (0x1U << CAN_F9FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F9FB1_FFDB9 CAN_F9FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F9FB1_FFDB10_Pos (10U) +#define CAN_F9FB1_FFDB10_Msk (0x1U << CAN_F9FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F9FB1_FFDB10 CAN_F9FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F9FB1_FFDB11_Pos (11U) +#define CAN_F9FB1_FFDB11_Msk (0x1U << CAN_F9FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F9FB1_FFDB11 CAN_F9FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F9FB1_FFDB12_Pos (12U) +#define CAN_F9FB1_FFDB12_Msk (0x1U << CAN_F9FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F9FB1_FFDB12 CAN_F9FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F9FB1_FFDB13_Pos (13U) +#define CAN_F9FB1_FFDB13_Msk (0x1U << CAN_F9FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F9FB1_FFDB13 CAN_F9FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F9FB1_FFDB14_Pos (14U) +#define CAN_F9FB1_FFDB14_Msk (0x1U << CAN_F9FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F9FB1_FFDB14 CAN_F9FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F9FB1_FFDB15_Pos (15U) +#define CAN_F9FB1_FFDB15_Msk (0x1U << CAN_F9FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F9FB1_FFDB15 CAN_F9FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F9FB1_FFDB16_Pos (16U) +#define CAN_F9FB1_FFDB16_Msk (0x1U << CAN_F9FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F9FB1_FFDB16 CAN_F9FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F9FB1_FFDB17_Pos (17U) +#define CAN_F9FB1_FFDB17_Msk (0x1U << CAN_F9FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F9FB1_FFDB17 CAN_F9FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F9FB1_FFDB18_Pos (18U) +#define CAN_F9FB1_FFDB18_Msk (0x1U << CAN_F9FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F9FB1_FFDB18 CAN_F9FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F9FB1_FFDB19_Pos (19U) +#define CAN_F9FB1_FFDB19_Msk (0x1U << CAN_F9FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F9FB1_FFDB19 CAN_F9FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F9FB1_FFDB20_Pos (20U) +#define CAN_F9FB1_FFDB20_Msk (0x1U << CAN_F9FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F9FB1_FFDB20 CAN_F9FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F9FB1_FFDB21_Pos (21U) +#define CAN_F9FB1_FFDB21_Msk (0x1U << CAN_F9FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F9FB1_FFDB21 CAN_F9FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F9FB1_FFDB22_Pos (22U) +#define CAN_F9FB1_FFDB22_Msk (0x1U << CAN_F9FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F9FB1_FFDB22 CAN_F9FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F9FB1_FFDB23_Pos (23U) +#define CAN_F9FB1_FFDB23_Msk (0x1U << CAN_F9FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F9FB1_FFDB23 CAN_F9FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F9FB1_FFDB24_Pos (24U) +#define CAN_F9FB1_FFDB24_Msk (0x1U << CAN_F9FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F9FB1_FFDB24 CAN_F9FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F9FB1_FFDB25_Pos (25U) +#define CAN_F9FB1_FFDB25_Msk (0x1U << CAN_F9FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F9FB1_FFDB25 CAN_F9FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F9FB1_FFDB26_Pos (26U) +#define CAN_F9FB1_FFDB26_Msk (0x1U << CAN_F9FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F9FB1_FFDB26 CAN_F9FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F9FB1_FFDB27_Pos (27U) +#define CAN_F9FB1_FFDB27_Msk (0x1U << CAN_F9FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F9FB1_FFDB27 CAN_F9FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F9FB1_FFDB28_Pos (28U) +#define CAN_F9FB1_FFDB28_Msk (0x1U << CAN_F9FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F9FB1_FFDB28 CAN_F9FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F9FB1_FFDB29_Pos (29U) +#define CAN_F9FB1_FFDB29_Msk (0x1U << CAN_F9FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F9FB1_FFDB29 CAN_F9FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F9FB1_FFDB30_Pos (30U) +#define CAN_F9FB1_FFDB30_Msk (0x1U << CAN_F9FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F9FB1_FFDB30 CAN_F9FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F9FB1_FFDB31_Pos (31U) +#define CAN_F9FB1_FFDB31_Msk (0x1U << CAN_F9FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F9FB1_FFDB31 CAN_F9FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F10FB1 register ******************/ +#define CAN_F10FB1_FFDB0_Pos (0U) +#define CAN_F10FB1_FFDB0_Msk (0x1U << CAN_F10FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F10FB1_FFDB0 CAN_F10FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F10FB1_FFDB1_Pos (1U) +#define CAN_F10FB1_FFDB1_Msk (0x1U << CAN_F10FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F10FB1_FFDB1 CAN_F10FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F10FB1_FFDB2_Pos (2U) +#define CAN_F10FB1_FFDB2_Msk (0x1U << CAN_F10FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F10FB1_FFDB2 CAN_F10FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F10FB1_FFDB3_Pos (3U) +#define CAN_F10FB1_FFDB3_Msk (0x1U << CAN_F10FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F10FB1_FFDB3 CAN_F10FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F10FB1_FFDB4_Pos (4U) +#define CAN_F10FB1_FFDB4_Msk (0x1U << CAN_F10FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F10FB1_FFDB4 CAN_F10FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F10FB1_FFDB5_Pos (5U) +#define CAN_F10FB1_FFDB5_Msk (0x1U << CAN_F10FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F10FB1_FFDB5 CAN_F10FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F10FB1_FFDB6_Pos (6U) +#define CAN_F10FB1_FFDB6_Msk (0x1U << CAN_F10FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F10FB1_FFDB6 CAN_F10FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F10FB1_FFDB7_Pos (7U) +#define CAN_F10FB1_FFDB7_Msk (0x1U << CAN_F10FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F10FB1_FFDB7 CAN_F10FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F10FB1_FFDB8_Pos (8U) +#define CAN_F10FB1_FFDB8_Msk (0x1U << CAN_F10FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F10FB1_FFDB8 CAN_F10FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F10FB1_FFDB9_Pos (9U) +#define CAN_F10FB1_FFDB9_Msk (0x1U << CAN_F10FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F10FB1_FFDB9 CAN_F10FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F10FB1_FFDB10_Pos (10U) +#define CAN_F10FB1_FFDB10_Msk (0x1U << CAN_F10FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F10FB1_FFDB10 CAN_F10FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F10FB1_FFDB11_Pos (11U) +#define CAN_F10FB1_FFDB11_Msk (0x1U << CAN_F10FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F10FB1_FFDB11 CAN_F10FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F10FB1_FFDB12_Pos (12U) +#define CAN_F10FB1_FFDB12_Msk (0x1U << CAN_F10FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F10FB1_FFDB12 CAN_F10FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F10FB1_FFDB13_Pos (13U) +#define CAN_F10FB1_FFDB13_Msk (0x1U << CAN_F10FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F10FB1_FFDB13 CAN_F10FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F10FB1_FFDB14_Pos (14U) +#define CAN_F10FB1_FFDB14_Msk (0x1U << CAN_F10FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F10FB1_FFDB14 CAN_F10FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F10FB1_FFDB15_Pos (15U) +#define CAN_F10FB1_FFDB15_Msk (0x1U << CAN_F10FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F10FB1_FFDB15 CAN_F10FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F10FB1_FFDB16_Pos (16U) +#define CAN_F10FB1_FFDB16_Msk (0x1U << CAN_F10FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F10FB1_FFDB16 CAN_F10FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F10FB1_FFDB17_Pos (17U) +#define CAN_F10FB1_FFDB17_Msk (0x1U << CAN_F10FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F10FB1_FFDB17 CAN_F10FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F10FB1_FFDB18_Pos (18U) +#define CAN_F10FB1_FFDB18_Msk (0x1U << CAN_F10FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F10FB1_FFDB18 CAN_F10FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F10FB1_FFDB19_Pos (19U) +#define CAN_F10FB1_FFDB19_Msk (0x1U << CAN_F10FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F10FB1_FFDB19 CAN_F10FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F10FB1_FFDB20_Pos (20U) +#define CAN_F10FB1_FFDB20_Msk (0x1U << CAN_F10FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F10FB1_FFDB20 CAN_F10FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F10FB1_FFDB21_Pos (21U) +#define CAN_F10FB1_FFDB21_Msk (0x1U << CAN_F10FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F10FB1_FFDB21 CAN_F10FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F10FB1_FFDB22_Pos (22U) +#define CAN_F10FB1_FFDB22_Msk (0x1U << CAN_F10FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F10FB1_FFDB22 CAN_F10FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F10FB1_FFDB23_Pos (23U) +#define CAN_F10FB1_FFDB23_Msk (0x1U << CAN_F10FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F10FB1_FFDB23 CAN_F10FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F10FB1_FFDB24_Pos (24U) +#define CAN_F10FB1_FFDB24_Msk (0x1U << CAN_F10FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F10FB1_FFDB24 CAN_F10FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F10FB1_FFDB25_Pos (25U) +#define CAN_F10FB1_FFDB25_Msk (0x1U << CAN_F10FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F10FB1_FFDB25 CAN_F10FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F10FB1_FFDB26_Pos (26U) +#define CAN_F10FB1_FFDB26_Msk (0x1U << CAN_F10FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F10FB1_FFDB26 CAN_F10FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F10FB1_FFDB27_Pos (27U) +#define CAN_F10FB1_FFDB27_Msk (0x1U << CAN_F10FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F10FB1_FFDB27 CAN_F10FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F10FB1_FFDB28_Pos (28U) +#define CAN_F10FB1_FFDB28_Msk (0x1U << CAN_F10FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F10FB1_FFDB28 CAN_F10FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F10FB1_FFDB29_Pos (29U) +#define CAN_F10FB1_FFDB29_Msk (0x1U << CAN_F10FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F10FB1_FFDB29 CAN_F10FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F10FB1_FFDB30_Pos (30U) +#define CAN_F10FB1_FFDB30_Msk (0x1U << CAN_F10FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F10FB1_FFDB30 CAN_F10FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F10FB1_FFDB31_Pos (31U) +#define CAN_F10FB1_FFDB31_Msk (0x1U << CAN_F10FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F10FB1_FFDB31 CAN_F10FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F11FB1 register ******************/ +#define CAN_F11FB1_FFDB0_Pos (0U) +#define CAN_F11FB1_FFDB0_Msk (0x1U << CAN_F11FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F11FB1_FFDB0 CAN_F11FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F11FB1_FFDB1_Pos (1U) +#define CAN_F11FB1_FFDB1_Msk (0x1U << CAN_F11FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F11FB1_FFDB1 CAN_F11FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F11FB1_FFDB2_Pos (2U) +#define CAN_F11FB1_FFDB2_Msk (0x1U << CAN_F11FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F11FB1_FFDB2 CAN_F11FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F11FB1_FFDB3_Pos (3U) +#define CAN_F11FB1_FFDB3_Msk (0x1U << CAN_F11FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F11FB1_FFDB3 CAN_F11FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F11FB1_FFDB4_Pos (4U) +#define CAN_F11FB1_FFDB4_Msk (0x1U << CAN_F11FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F11FB1_FFDB4 CAN_F11FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F11FB1_FFDB5_Pos (5U) +#define CAN_F11FB1_FFDB5_Msk (0x1U << CAN_F11FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F11FB1_FFDB5 CAN_F11FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F11FB1_FFDB6_Pos (6U) +#define CAN_F11FB1_FFDB6_Msk (0x1U << CAN_F11FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F11FB1_FFDB6 CAN_F11FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F11FB1_FFDB7_Pos (7U) +#define CAN_F11FB1_FFDB7_Msk (0x1U << CAN_F11FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F11FB1_FFDB7 CAN_F11FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F11FB1_FFDB8_Pos (8U) +#define CAN_F11FB1_FFDB8_Msk (0x1U << CAN_F11FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F11FB1_FFDB8 CAN_F11FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F11FB1_FFDB9_Pos (9U) +#define CAN_F11FB1_FFDB9_Msk (0x1U << CAN_F11FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F11FB1_FFDB9 CAN_F11FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F11FB1_FFDB10_Pos (10U) +#define CAN_F11FB1_FFDB10_Msk (0x1U << CAN_F11FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F11FB1_FFDB10 CAN_F11FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F11FB1_FFDB11_Pos (11U) +#define CAN_F11FB1_FFDB11_Msk (0x1U << CAN_F11FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F11FB1_FFDB11 CAN_F11FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F11FB1_FFDB12_Pos (12U) +#define CAN_F11FB1_FFDB12_Msk (0x1U << CAN_F11FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F11FB1_FFDB12 CAN_F11FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F11FB1_FFDB13_Pos (13U) +#define CAN_F11FB1_FFDB13_Msk (0x1U << CAN_F11FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F11FB1_FFDB13 CAN_F11FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F11FB1_FFDB14_Pos (14U) +#define CAN_F11FB1_FFDB14_Msk (0x1U << CAN_F11FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F11FB1_FFDB14 CAN_F11FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F11FB1_FFDB15_Pos (15U) +#define CAN_F11FB1_FFDB15_Msk (0x1U << CAN_F11FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F11FB1_FFDB15 CAN_F11FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F11FB1_FFDB16_Pos (16U) +#define CAN_F11FB1_FFDB16_Msk (0x1U << CAN_F11FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F11FB1_FFDB16 CAN_F11FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F11FB1_FFDB17_Pos (17U) +#define CAN_F11FB1_FFDB17_Msk (0x1U << CAN_F11FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F11FB1_FFDB17 CAN_F11FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F11FB1_FFDB18_Pos (18U) +#define CAN_F11FB1_FFDB18_Msk (0x1U << CAN_F11FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F11FB1_FFDB18 CAN_F11FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F11FB1_FFDB19_Pos (19U) +#define CAN_F11FB1_FFDB19_Msk (0x1U << CAN_F11FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F11FB1_FFDB19 CAN_F11FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F11FB1_FFDB20_Pos (20U) +#define CAN_F11FB1_FFDB20_Msk (0x1U << CAN_F11FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F11FB1_FFDB20 CAN_F11FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F11FB1_FFDB21_Pos (21U) +#define CAN_F11FB1_FFDB21_Msk (0x1U << CAN_F11FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F11FB1_FFDB21 CAN_F11FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F11FB1_FFDB22_Pos (22U) +#define CAN_F11FB1_FFDB22_Msk (0x1U << CAN_F11FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F11FB1_FFDB22 CAN_F11FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F11FB1_FFDB23_Pos (23U) +#define CAN_F11FB1_FFDB23_Msk (0x1U << CAN_F11FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F11FB1_FFDB23 CAN_F11FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F11FB1_FFDB24_Pos (24U) +#define CAN_F11FB1_FFDB24_Msk (0x1U << CAN_F11FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F11FB1_FFDB24 CAN_F11FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F11FB1_FFDB25_Pos (25U) +#define CAN_F11FB1_FFDB25_Msk (0x1U << CAN_F11FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F11FB1_FFDB25 CAN_F11FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F11FB1_FFDB26_Pos (26U) +#define CAN_F11FB1_FFDB26_Msk (0x1U << CAN_F11FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F11FB1_FFDB26 CAN_F11FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F11FB1_FFDB27_Pos (27U) +#define CAN_F11FB1_FFDB27_Msk (0x1U << CAN_F11FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F11FB1_FFDB27 CAN_F11FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F11FB1_FFDB28_Pos (28U) +#define CAN_F11FB1_FFDB28_Msk (0x1U << CAN_F11FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F11FB1_FFDB28 CAN_F11FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F11FB1_FFDB29_Pos (29U) +#define CAN_F11FB1_FFDB29_Msk (0x1U << CAN_F11FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F11FB1_FFDB29 CAN_F11FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F11FB1_FFDB30_Pos (30U) +#define CAN_F11FB1_FFDB30_Msk (0x1U << CAN_F11FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F11FB1_FFDB30 CAN_F11FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F11FB1_FFDB31_Pos (31U) +#define CAN_F11FB1_FFDB31_Msk (0x1U << CAN_F11FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F11FB1_FFDB31 CAN_F11FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F12FB1 register ******************/ +#define CAN_F12FB1_FFDB0_Pos (0U) +#define CAN_F12FB1_FFDB0_Msk (0x1U << CAN_F12FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F12FB1_FFDB0 CAN_F12FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F12FB1_FFDB1_Pos (1U) +#define CAN_F12FB1_FFDB1_Msk (0x1U << CAN_F12FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F12FB1_FFDB1 CAN_F12FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F12FB1_FFDB2_Pos (2U) +#define CAN_F12FB1_FFDB2_Msk (0x1U << CAN_F12FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F12FB1_FFDB2 CAN_F12FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F12FB1_FFDB3_Pos (3U) +#define CAN_F12FB1_FFDB3_Msk (0x1U << CAN_F12FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F12FB1_FFDB3 CAN_F12FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F12FB1_FFDB4_Pos (4U) +#define CAN_F12FB1_FFDB4_Msk (0x1U << CAN_F12FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F12FB1_FFDB4 CAN_F12FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F12FB1_FFDB5_Pos (5U) +#define CAN_F12FB1_FFDB5_Msk (0x1U << CAN_F12FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F12FB1_FFDB5 CAN_F12FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F12FB1_FFDB6_Pos (6U) +#define CAN_F12FB1_FFDB6_Msk (0x1U << CAN_F12FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F12FB1_FFDB6 CAN_F12FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F12FB1_FFDB7_Pos (7U) +#define CAN_F12FB1_FFDB7_Msk (0x1U << CAN_F12FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F12FB1_FFDB7 CAN_F12FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F12FB1_FFDB8_Pos (8U) +#define CAN_F12FB1_FFDB8_Msk (0x1U << CAN_F12FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F12FB1_FFDB8 CAN_F12FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F12FB1_FFDB9_Pos (9U) +#define CAN_F12FB1_FFDB9_Msk (0x1U << CAN_F12FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F12FB1_FFDB9 CAN_F12FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F12FB1_FFDB10_Pos (10U) +#define CAN_F12FB1_FFDB10_Msk (0x1U << CAN_F12FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F12FB1_FFDB10 CAN_F12FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F12FB1_FFDB11_Pos (11U) +#define CAN_F12FB1_FFDB11_Msk (0x1U << CAN_F12FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F12FB1_FFDB11 CAN_F12FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F12FB1_FFDB12_Pos (12U) +#define CAN_F12FB1_FFDB12_Msk (0x1U << CAN_F12FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F12FB1_FFDB12 CAN_F12FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F12FB1_FFDB13_Pos (13U) +#define CAN_F12FB1_FFDB13_Msk (0x1U << CAN_F12FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F12FB1_FFDB13 CAN_F12FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F12FB1_FFDB14_Pos (14U) +#define CAN_F12FB1_FFDB14_Msk (0x1U << CAN_F12FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F12FB1_FFDB14 CAN_F12FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F12FB1_FFDB15_Pos (15U) +#define CAN_F12FB1_FFDB15_Msk (0x1U << CAN_F12FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F12FB1_FFDB15 CAN_F12FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F12FB1_FFDB16_Pos (16U) +#define CAN_F12FB1_FFDB16_Msk (0x1U << CAN_F12FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F12FB1_FFDB16 CAN_F12FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F12FB1_FFDB17_Pos (17U) +#define CAN_F12FB1_FFDB17_Msk (0x1U << CAN_F12FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F12FB1_FFDB17 CAN_F12FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F12FB1_FFDB18_Pos (18U) +#define CAN_F12FB1_FFDB18_Msk (0x1U << CAN_F12FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F12FB1_FFDB18 CAN_F12FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F12FB1_FFDB19_Pos (19U) +#define CAN_F12FB1_FFDB19_Msk (0x1U << CAN_F12FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F12FB1_FFDB19 CAN_F12FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F12FB1_FFDB20_Pos (20U) +#define CAN_F12FB1_FFDB20_Msk (0x1U << CAN_F12FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F12FB1_FFDB20 CAN_F12FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F12FB1_FFDB21_Pos (21U) +#define CAN_F12FB1_FFDB21_Msk (0x1U << CAN_F12FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F12FB1_FFDB21 CAN_F12FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F12FB1_FFDB22_Pos (22U) +#define CAN_F12FB1_FFDB22_Msk (0x1U << CAN_F12FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F12FB1_FFDB22 CAN_F12FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F12FB1_FFDB23_Pos (23U) +#define CAN_F12FB1_FFDB23_Msk (0x1U << CAN_F12FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F12FB1_FFDB23 CAN_F12FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F12FB1_FFDB24_Pos (24U) +#define CAN_F12FB1_FFDB24_Msk (0x1U << CAN_F12FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F12FB1_FFDB24 CAN_F12FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F12FB1_FFDB25_Pos (25U) +#define CAN_F12FB1_FFDB25_Msk (0x1U << CAN_F12FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F12FB1_FFDB25 CAN_F12FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F12FB1_FFDB26_Pos (26U) +#define CAN_F12FB1_FFDB26_Msk (0x1U << CAN_F12FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F12FB1_FFDB26 CAN_F12FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F12FB1_FFDB27_Pos (27U) +#define CAN_F12FB1_FFDB27_Msk (0x1U << CAN_F12FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F12FB1_FFDB27 CAN_F12FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F12FB1_FFDB28_Pos (28U) +#define CAN_F12FB1_FFDB28_Msk (0x1U << CAN_F12FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F12FB1_FFDB28 CAN_F12FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F12FB1_FFDB29_Pos (29U) +#define CAN_F12FB1_FFDB29_Msk (0x1U << CAN_F12FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F12FB1_FFDB29 CAN_F12FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F12FB1_FFDB30_Pos (30U) +#define CAN_F12FB1_FFDB30_Msk (0x1U << CAN_F12FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F12FB1_FFDB30 CAN_F12FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F12FB1_FFDB31_Pos (31U) +#define CAN_F12FB1_FFDB31_Msk (0x1U << CAN_F12FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F12FB1_FFDB31 CAN_F12FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F13FB1 register ******************/ +#define CAN_F13FB1_FFDB0_Pos (0U) +#define CAN_F13FB1_FFDB0_Msk (0x1U << CAN_F13FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F13FB1_FFDB0 CAN_F13FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F13FB1_FFDB1_Pos (1U) +#define CAN_F13FB1_FFDB1_Msk (0x1U << CAN_F13FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F13FB1_FFDB1 CAN_F13FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F13FB1_FFDB2_Pos (2U) +#define CAN_F13FB1_FFDB2_Msk (0x1U << CAN_F13FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F13FB1_FFDB2 CAN_F13FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F13FB1_FFDB3_Pos (3U) +#define CAN_F13FB1_FFDB3_Msk (0x1U << CAN_F13FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F13FB1_FFDB3 CAN_F13FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F13FB1_FFDB4_Pos (4U) +#define CAN_F13FB1_FFDB4_Msk (0x1U << CAN_F13FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F13FB1_FFDB4 CAN_F13FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F13FB1_FFDB5_Pos (5U) +#define CAN_F13FB1_FFDB5_Msk (0x1U << CAN_F13FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F13FB1_FFDB5 CAN_F13FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F13FB1_FFDB6_Pos (6U) +#define CAN_F13FB1_FFDB6_Msk (0x1U << CAN_F13FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F13FB1_FFDB6 CAN_F13FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F13FB1_FFDB7_Pos (7U) +#define CAN_F13FB1_FFDB7_Msk (0x1U << CAN_F13FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F13FB1_FFDB7 CAN_F13FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F13FB1_FFDB8_Pos (8U) +#define CAN_F13FB1_FFDB8_Msk (0x1U << CAN_F13FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F13FB1_FFDB8 CAN_F13FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F13FB1_FFDB9_Pos (9U) +#define CAN_F13FB1_FFDB9_Msk (0x1U << CAN_F13FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F13FB1_FFDB9 CAN_F13FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F13FB1_FFDB10_Pos (10U) +#define CAN_F13FB1_FFDB10_Msk (0x1U << CAN_F13FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F13FB1_FFDB10 CAN_F13FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F13FB1_FFDB11_Pos (11U) +#define CAN_F13FB1_FFDB11_Msk (0x1U << CAN_F13FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F13FB1_FFDB11 CAN_F13FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F13FB1_FFDB12_Pos (12U) +#define CAN_F13FB1_FFDB12_Msk (0x1U << CAN_F13FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F13FB1_FFDB12 CAN_F13FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F13FB1_FFDB13_Pos (13U) +#define CAN_F13FB1_FFDB13_Msk (0x1U << CAN_F13FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F13FB1_FFDB13 CAN_F13FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F13FB1_FFDB14_Pos (14U) +#define CAN_F13FB1_FFDB14_Msk (0x1U << CAN_F13FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F13FB1_FFDB14 CAN_F13FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F13FB1_FFDB15_Pos (15U) +#define CAN_F13FB1_FFDB15_Msk (0x1U << CAN_F13FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F13FB1_FFDB15 CAN_F13FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F13FB1_FFDB16_Pos (16U) +#define CAN_F13FB1_FFDB16_Msk (0x1U << CAN_F13FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F13FB1_FFDB16 CAN_F13FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F13FB1_FFDB17_Pos (17U) +#define CAN_F13FB1_FFDB17_Msk (0x1U << CAN_F13FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F13FB1_FFDB17 CAN_F13FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F13FB1_FFDB18_Pos (18U) +#define CAN_F13FB1_FFDB18_Msk (0x1U << CAN_F13FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F13FB1_FFDB18 CAN_F13FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F13FB1_FFDB19_Pos (19U) +#define CAN_F13FB1_FFDB19_Msk (0x1U << CAN_F13FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F13FB1_FFDB19 CAN_F13FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F13FB1_FFDB20_Pos (20U) +#define CAN_F13FB1_FFDB20_Msk (0x1U << CAN_F13FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F13FB1_FFDB20 CAN_F13FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F13FB1_FFDB21_Pos (21U) +#define CAN_F13FB1_FFDB21_Msk (0x1U << CAN_F13FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F13FB1_FFDB21 CAN_F13FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F13FB1_FFDB22_Pos (22U) +#define CAN_F13FB1_FFDB22_Msk (0x1U << CAN_F13FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F13FB1_FFDB22 CAN_F13FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F13FB1_FFDB23_Pos (23U) +#define CAN_F13FB1_FFDB23_Msk (0x1U << CAN_F13FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F13FB1_FFDB23 CAN_F13FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F13FB1_FFDB24_Pos (24U) +#define CAN_F13FB1_FFDB24_Msk (0x1U << CAN_F13FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F13FB1_FFDB24 CAN_F13FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F13FB1_FFDB25_Pos (25U) +#define CAN_F13FB1_FFDB25_Msk (0x1U << CAN_F13FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F13FB1_FFDB25 CAN_F13FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F13FB1_FFDB26_Pos (26U) +#define CAN_F13FB1_FFDB26_Msk (0x1U << CAN_F13FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F13FB1_FFDB26 CAN_F13FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F13FB1_FFDB27_Pos (27U) +#define CAN_F13FB1_FFDB27_Msk (0x1U << CAN_F13FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F13FB1_FFDB27 CAN_F13FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F13FB1_FFDB28_Pos (28U) +#define CAN_F13FB1_FFDB28_Msk (0x1U << CAN_F13FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F13FB1_FFDB28 CAN_F13FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F13FB1_FFDB29_Pos (29U) +#define CAN_F13FB1_FFDB29_Msk (0x1U << CAN_F13FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F13FB1_FFDB29 CAN_F13FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F13FB1_FFDB30_Pos (30U) +#define CAN_F13FB1_FFDB30_Msk (0x1U << CAN_F13FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F13FB1_FFDB30 CAN_F13FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F13FB1_FFDB31_Pos (31U) +#define CAN_F13FB1_FFDB31_Msk (0x1U << CAN_F13FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F13FB1_FFDB31 CAN_F13FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F0FB2 register *******************/ +#define CAN_F0FB2_FFDB0_Pos (0U) +#define CAN_F0FB2_FFDB0_Msk (0x1U << CAN_F0FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F0FB2_FFDB0 CAN_F0FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F0FB2_FFDB1_Pos (1U) +#define CAN_F0FB2_FFDB1_Msk (0x1U << CAN_F0FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F0FB2_FFDB1 CAN_F0FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F0FB2_FFDB2_Pos (2U) +#define CAN_F0FB2_FFDB2_Msk (0x1U << CAN_F0FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F0FB2_FFDB2 CAN_F0FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F0FB2_FFDB3_Pos (3U) +#define CAN_F0FB2_FFDB3_Msk (0x1U << CAN_F0FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F0FB2_FFDB3 CAN_F0FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F0FB2_FFDB4_Pos (4U) +#define CAN_F0FB2_FFDB4_Msk (0x1U << CAN_F0FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F0FB2_FFDB4 CAN_F0FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F0FB2_FFDB5_Pos (5U) +#define CAN_F0FB2_FFDB5_Msk (0x1U << CAN_F0FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F0FB2_FFDB5 CAN_F0FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F0FB2_FFDB6_Pos (6U) +#define CAN_F0FB2_FFDB6_Msk (0x1U << CAN_F0FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F0FB2_FFDB6 CAN_F0FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F0FB2_FFDB7_Pos (7U) +#define CAN_F0FB2_FFDB7_Msk (0x1U << CAN_F0FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F0FB2_FFDB7 CAN_F0FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F0FB2_FFDB8_Pos (8U) +#define CAN_F0FB2_FFDB8_Msk (0x1U << CAN_F0FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F0FB2_FFDB8 CAN_F0FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F0FB2_FFDB9_Pos (9U) +#define CAN_F0FB2_FFDB9_Msk (0x1U << CAN_F0FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F0FB2_FFDB9 CAN_F0FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F0FB2_FFDB10_Pos (10U) +#define CAN_F0FB2_FFDB10_Msk (0x1U << CAN_F0FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F0FB2_FFDB10 CAN_F0FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F0FB2_FFDB11_Pos (11U) +#define CAN_F0FB2_FFDB11_Msk (0x1U << CAN_F0FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F0FB2_FFDB11 CAN_F0FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F0FB2_FFDB12_Pos (12U) +#define CAN_F0FB2_FFDB12_Msk (0x1U << CAN_F0FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F0FB2_FFDB12 CAN_F0FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F0FB2_FFDB13_Pos (13U) +#define CAN_F0FB2_FFDB13_Msk (0x1U << CAN_F0FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F0FB2_FFDB13 CAN_F0FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F0FB2_FFDB14_Pos (14U) +#define CAN_F0FB2_FFDB14_Msk (0x1U << CAN_F0FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F0FB2_FFDB14 CAN_F0FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F0FB2_FFDB15_Pos (15U) +#define CAN_F0FB2_FFDB15_Msk (0x1U << CAN_F0FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F0FB2_FFDB15 CAN_F0FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F0FB2_FFDB16_Pos (16U) +#define CAN_F0FB2_FFDB16_Msk (0x1U << CAN_F0FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F0FB2_FFDB16 CAN_F0FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F0FB2_FFDB17_Pos (17U) +#define CAN_F0FB2_FFDB17_Msk (0x1U << CAN_F0FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F0FB2_FFDB17 CAN_F0FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F0FB2_FFDB18_Pos (18U) +#define CAN_F0FB2_FFDB18_Msk (0x1U << CAN_F0FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F0FB2_FFDB18 CAN_F0FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F0FB2_FFDB19_Pos (19U) +#define CAN_F0FB2_FFDB19_Msk (0x1U << CAN_F0FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F0FB2_FFDB19 CAN_F0FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F0FB2_FFDB20_Pos (20U) +#define CAN_F0FB2_FFDB20_Msk (0x1U << CAN_F0FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F0FB2_FFDB20 CAN_F0FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F0FB2_FFDB21_Pos (21U) +#define CAN_F0FB2_FFDB21_Msk (0x1U << CAN_F0FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F0FB2_FFDB21 CAN_F0FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F0FB2_FFDB22_Pos (22U) +#define CAN_F0FB2_FFDB22_Msk (0x1U << CAN_F0FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F0FB2_FFDB22 CAN_F0FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F0FB2_FFDB23_Pos (23U) +#define CAN_F0FB2_FFDB23_Msk (0x1U << CAN_F0FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F0FB2_FFDB23 CAN_F0FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F0FB2_FFDB24_Pos (24U) +#define CAN_F0FB2_FFDB24_Msk (0x1U << CAN_F0FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F0FB2_FFDB24 CAN_F0FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F0FB2_FFDB25_Pos (25U) +#define CAN_F0FB2_FFDB25_Msk (0x1U << CAN_F0FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F0FB2_FFDB25 CAN_F0FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F0FB2_FFDB26_Pos (26U) +#define CAN_F0FB2_FFDB26_Msk (0x1U << CAN_F0FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F0FB2_FFDB26 CAN_F0FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F0FB2_FFDB27_Pos (27U) +#define CAN_F0FB2_FFDB27_Msk (0x1U << CAN_F0FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F0FB2_FFDB27 CAN_F0FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F0FB2_FFDB28_Pos (28U) +#define CAN_F0FB2_FFDB28_Msk (0x1U << CAN_F0FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F0FB2_FFDB28 CAN_F0FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F0FB2_FFDB29_Pos (29U) +#define CAN_F0FB2_FFDB29_Msk (0x1U << CAN_F0FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F0FB2_FFDB29 CAN_F0FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F0FB2_FFDB30_Pos (30U) +#define CAN_F0FB2_FFDB30_Msk (0x1U << CAN_F0FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F0FB2_FFDB30 CAN_F0FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F0FB2_FFDB31_Pos (31U) +#define CAN_F0FB2_FFDB31_Msk (0x1U << CAN_F0FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F0FB2_FFDB31 CAN_F0FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F1FB2 register *******************/ +#define CAN_F1FB2_FFDB0_Pos (0U) +#define CAN_F1FB2_FFDB0_Msk (0x1U << CAN_F1FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F1FB2_FFDB0 CAN_F1FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F1FB2_FFDB1_Pos (1U) +#define CAN_F1FB2_FFDB1_Msk (0x1U << CAN_F1FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F1FB2_FFDB1 CAN_F1FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F1FB2_FFDB2_Pos (2U) +#define CAN_F1FB2_FFDB2_Msk (0x1U << CAN_F1FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F1FB2_FFDB2 CAN_F1FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F1FB2_FFDB3_Pos (3U) +#define CAN_F1FB2_FFDB3_Msk (0x1U << CAN_F1FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F1FB2_FFDB3 CAN_F1FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F1FB2_FFDB4_Pos (4U) +#define CAN_F1FB2_FFDB4_Msk (0x1U << CAN_F1FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F1FB2_FFDB4 CAN_F1FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F1FB2_FFDB5_Pos (5U) +#define CAN_F1FB2_FFDB5_Msk (0x1U << CAN_F1FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F1FB2_FFDB5 CAN_F1FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F1FB2_FFDB6_Pos (6U) +#define CAN_F1FB2_FFDB6_Msk (0x1U << CAN_F1FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F1FB2_FFDB6 CAN_F1FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F1FB2_FFDB7_Pos (7U) +#define CAN_F1FB2_FFDB7_Msk (0x1U << CAN_F1FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F1FB2_FFDB7 CAN_F1FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F1FB2_FFDB8_Pos (8U) +#define CAN_F1FB2_FFDB8_Msk (0x1U << CAN_F1FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F1FB2_FFDB8 CAN_F1FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F1FB2_FFDB9_Pos (9U) +#define CAN_F1FB2_FFDB9_Msk (0x1U << CAN_F1FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F1FB2_FFDB9 CAN_F1FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F1FB2_FFDB10_Pos (10U) +#define CAN_F1FB2_FFDB10_Msk (0x1U << CAN_F1FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F1FB2_FFDB10 CAN_F1FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F1FB2_FFDB11_Pos (11U) +#define CAN_F1FB2_FFDB11_Msk (0x1U << CAN_F1FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F1FB2_FFDB11 CAN_F1FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F1FB2_FFDB12_Pos (12U) +#define CAN_F1FB2_FFDB12_Msk (0x1U << CAN_F1FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F1FB2_FFDB12 CAN_F1FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F1FB2_FFDB13_Pos (13U) +#define CAN_F1FB2_FFDB13_Msk (0x1U << CAN_F1FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F1FB2_FFDB13 CAN_F1FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F1FB2_FFDB14_Pos (14U) +#define CAN_F1FB2_FFDB14_Msk (0x1U << CAN_F1FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F1FB2_FFDB14 CAN_F1FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F1FB2_FFDB15_Pos (15U) +#define CAN_F1FB2_FFDB15_Msk (0x1U << CAN_F1FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F1FB2_FFDB15 CAN_F1FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F1FB2_FFDB16_Pos (16U) +#define CAN_F1FB2_FFDB16_Msk (0x1U << CAN_F1FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F1FB2_FFDB16 CAN_F1FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F1FB2_FFDB17_Pos (17U) +#define CAN_F1FB2_FFDB17_Msk (0x1U << CAN_F1FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F1FB2_FFDB17 CAN_F1FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F1FB2_FFDB18_Pos (18U) +#define CAN_F1FB2_FFDB18_Msk (0x1U << CAN_F1FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F1FB2_FFDB18 CAN_F1FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F1FB2_FFDB19_Pos (19U) +#define CAN_F1FB2_FFDB19_Msk (0x1U << CAN_F1FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F1FB2_FFDB19 CAN_F1FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F1FB2_FFDB20_Pos (20U) +#define CAN_F1FB2_FFDB20_Msk (0x1U << CAN_F1FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F1FB2_FFDB20 CAN_F1FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F1FB2_FFDB21_Pos (21U) +#define CAN_F1FB2_FFDB21_Msk (0x1U << CAN_F1FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F1FB2_FFDB21 CAN_F1FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F1FB2_FFDB22_Pos (22U) +#define CAN_F1FB2_FFDB22_Msk (0x1U << CAN_F1FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F1FB2_FFDB22 CAN_F1FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F1FB2_FFDB23_Pos (23U) +#define CAN_F1FB2_FFDB23_Msk (0x1U << CAN_F1FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F1FB2_FFDB23 CAN_F1FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F1FB2_FFDB24_Pos (24U) +#define CAN_F1FB2_FFDB24_Msk (0x1U << CAN_F1FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F1FB2_FFDB24 CAN_F1FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F1FB2_FFDB25_Pos (25U) +#define CAN_F1FB2_FFDB25_Msk (0x1U << CAN_F1FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F1FB2_FFDB25 CAN_F1FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F1FB2_FFDB26_Pos (26U) +#define CAN_F1FB2_FFDB26_Msk (0x1U << CAN_F1FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F1FB2_FFDB26 CAN_F1FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F1FB2_FFDB27_Pos (27U) +#define CAN_F1FB2_FFDB27_Msk (0x1U << CAN_F1FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F1FB2_FFDB27 CAN_F1FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F1FB2_FFDB28_Pos (28U) +#define CAN_F1FB2_FFDB28_Msk (0x1U << CAN_F1FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F1FB2_FFDB28 CAN_F1FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F1FB2_FFDB29_Pos (29U) +#define CAN_F1FB2_FFDB29_Msk (0x1U << CAN_F1FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F1FB2_FFDB29 CAN_F1FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F1FB2_FFDB30_Pos (30U) +#define CAN_F1FB2_FFDB30_Msk (0x1U << CAN_F1FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F1FB2_FFDB30 CAN_F1FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F1FB2_FFDB31_Pos (31U) +#define CAN_F1FB2_FFDB31_Msk (0x1U << CAN_F1FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F1FB2_FFDB31 CAN_F1FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F2FB2 register *******************/ +#define CAN_F2FB2_FFDB0_Pos (0U) +#define CAN_F2FB2_FFDB0_Msk (0x1U << CAN_F2FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F2FB2_FFDB0 CAN_F2FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F2FB2_FFDB1_Pos (1U) +#define CAN_F2FB2_FFDB1_Msk (0x1U << CAN_F2FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F2FB2_FFDB1 CAN_F2FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F2FB2_FFDB2_Pos (2U) +#define CAN_F2FB2_FFDB2_Msk (0x1U << CAN_F2FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F2FB2_FFDB2 CAN_F2FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F2FB2_FFDB3_Pos (3U) +#define CAN_F2FB2_FFDB3_Msk (0x1U << CAN_F2FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F2FB2_FFDB3 CAN_F2FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F2FB2_FFDB4_Pos (4U) +#define CAN_F2FB2_FFDB4_Msk (0x1U << CAN_F2FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F2FB2_FFDB4 CAN_F2FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F2FB2_FFDB5_Pos (5U) +#define CAN_F2FB2_FFDB5_Msk (0x1U << CAN_F2FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F2FB2_FFDB5 CAN_F2FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F2FB2_FFDB6_Pos (6U) +#define CAN_F2FB2_FFDB6_Msk (0x1U << CAN_F2FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F2FB2_FFDB6 CAN_F2FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F2FB2_FFDB7_Pos (7U) +#define CAN_F2FB2_FFDB7_Msk (0x1U << CAN_F2FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F2FB2_FFDB7 CAN_F2FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F2FB2_FFDB8_Pos (8U) +#define CAN_F2FB2_FFDB8_Msk (0x1U << CAN_F2FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F2FB2_FFDB8 CAN_F2FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F2FB2_FFDB9_Pos (9U) +#define CAN_F2FB2_FFDB9_Msk (0x1U << CAN_F2FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F2FB2_FFDB9 CAN_F2FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F2FB2_FFDB10_Pos (10U) +#define CAN_F2FB2_FFDB10_Msk (0x1U << CAN_F2FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F2FB2_FFDB10 CAN_F2FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F2FB2_FFDB11_Pos (11U) +#define CAN_F2FB2_FFDB11_Msk (0x1U << CAN_F2FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F2FB2_FFDB11 CAN_F2FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F2FB2_FFDB12_Pos (12U) +#define CAN_F2FB2_FFDB12_Msk (0x1U << CAN_F2FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F2FB2_FFDB12 CAN_F2FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F2FB2_FFDB13_Pos (13U) +#define CAN_F2FB2_FFDB13_Msk (0x1U << CAN_F2FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F2FB2_FFDB13 CAN_F2FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F2FB2_FFDB14_Pos (14U) +#define CAN_F2FB2_FFDB14_Msk (0x1U << CAN_F2FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F2FB2_FFDB14 CAN_F2FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F2FB2_FFDB15_Pos (15U) +#define CAN_F2FB2_FFDB15_Msk (0x1U << CAN_F2FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F2FB2_FFDB15 CAN_F2FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F2FB2_FFDB16_Pos (16U) +#define CAN_F2FB2_FFDB16_Msk (0x1U << CAN_F2FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F2FB2_FFDB16 CAN_F2FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F2FB2_FFDB17_Pos (17U) +#define CAN_F2FB2_FFDB17_Msk (0x1U << CAN_F2FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F2FB2_FFDB17 CAN_F2FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F2FB2_FFDB18_Pos (18U) +#define CAN_F2FB2_FFDB18_Msk (0x1U << CAN_F2FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F2FB2_FFDB18 CAN_F2FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F2FB2_FFDB19_Pos (19U) +#define CAN_F2FB2_FFDB19_Msk (0x1U << CAN_F2FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F2FB2_FFDB19 CAN_F2FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F2FB2_FFDB20_Pos (20U) +#define CAN_F2FB2_FFDB20_Msk (0x1U << CAN_F2FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F2FB2_FFDB20 CAN_F2FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F2FB2_FFDB21_Pos (21U) +#define CAN_F2FB2_FFDB21_Msk (0x1U << CAN_F2FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F2FB2_FFDB21 CAN_F2FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F2FB2_FFDB22_Pos (22U) +#define CAN_F2FB2_FFDB22_Msk (0x1U << CAN_F2FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F2FB2_FFDB22 CAN_F2FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F2FB2_FFDB23_Pos (23U) +#define CAN_F2FB2_FFDB23_Msk (0x1U << CAN_F2FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F2FB2_FFDB23 CAN_F2FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F2FB2_FFDB24_Pos (24U) +#define CAN_F2FB2_FFDB24_Msk (0x1U << CAN_F2FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F2FB2_FFDB24 CAN_F2FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F2FB2_FFDB25_Pos (25U) +#define CAN_F2FB2_FFDB25_Msk (0x1U << CAN_F2FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F2FB2_FFDB25 CAN_F2FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F2FB2_FFDB26_Pos (26U) +#define CAN_F2FB2_FFDB26_Msk (0x1U << CAN_F2FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F2FB2_FFDB26 CAN_F2FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F2FB2_FFDB27_Pos (27U) +#define CAN_F2FB2_FFDB27_Msk (0x1U << CAN_F2FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F2FB2_FFDB27 CAN_F2FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F2FB2_FFDB28_Pos (28U) +#define CAN_F2FB2_FFDB28_Msk (0x1U << CAN_F2FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F2FB2_FFDB28 CAN_F2FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F2FB2_FFDB29_Pos (29U) +#define CAN_F2FB2_FFDB29_Msk (0x1U << CAN_F2FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F2FB2_FFDB29 CAN_F2FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F2FB2_FFDB30_Pos (30U) +#define CAN_F2FB2_FFDB30_Msk (0x1U << CAN_F2FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F2FB2_FFDB30 CAN_F2FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F2FB2_FFDB31_Pos (31U) +#define CAN_F2FB2_FFDB31_Msk (0x1U << CAN_F2FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F2FB2_FFDB31 CAN_F2FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F3FB2 register *******************/ +#define CAN_F3FB2_FFDB0_Pos (0U) +#define CAN_F3FB2_FFDB0_Msk (0x1U << CAN_F3FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F3FB2_FFDB0 CAN_F3FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F3FB2_FFDB1_Pos (1U) +#define CAN_F3FB2_FFDB1_Msk (0x1U << CAN_F3FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F3FB2_FFDB1 CAN_F3FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F3FB2_FFDB2_Pos (2U) +#define CAN_F3FB2_FFDB2_Msk (0x1U << CAN_F3FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F3FB2_FFDB2 CAN_F3FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F3FB2_FFDB3_Pos (3U) +#define CAN_F3FB2_FFDB3_Msk (0x1U << CAN_F3FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F3FB2_FFDB3 CAN_F3FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F3FB2_FFDB4_Pos (4U) +#define CAN_F3FB2_FFDB4_Msk (0x1U << CAN_F3FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F3FB2_FFDB4 CAN_F3FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F3FB2_FFDB5_Pos (5U) +#define CAN_F3FB2_FFDB5_Msk (0x1U << CAN_F3FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F3FB2_FFDB5 CAN_F3FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F3FB2_FFDB6_Pos (6U) +#define CAN_F3FB2_FFDB6_Msk (0x1U << CAN_F3FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F3FB2_FFDB6 CAN_F3FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F3FB2_FFDB7_Pos (7U) +#define CAN_F3FB2_FFDB7_Msk (0x1U << CAN_F3FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F3FB2_FFDB7 CAN_F3FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F3FB2_FFDB8_Pos (8U) +#define CAN_F3FB2_FFDB8_Msk (0x1U << CAN_F3FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F3FB2_FFDB8 CAN_F3FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F3FB2_FFDB9_Pos (9U) +#define CAN_F3FB2_FFDB9_Msk (0x1U << CAN_F3FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F3FB2_FFDB9 CAN_F3FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F3FB2_FFDB10_Pos (10U) +#define CAN_F3FB2_FFDB10_Msk (0x1U << CAN_F3FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F3FB2_FFDB10 CAN_F3FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F3FB2_FFDB11_Pos (11U) +#define CAN_F3FB2_FFDB11_Msk (0x1U << CAN_F3FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F3FB2_FFDB11 CAN_F3FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F3FB2_FFDB12_Pos (12U) +#define CAN_F3FB2_FFDB12_Msk (0x1U << CAN_F3FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F3FB2_FFDB12 CAN_F3FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F3FB2_FFDB13_Pos (13U) +#define CAN_F3FB2_FFDB13_Msk (0x1U << CAN_F3FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F3FB2_FFDB13 CAN_F3FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F3FB2_FFDB14_Pos (14U) +#define CAN_F3FB2_FFDB14_Msk (0x1U << CAN_F3FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F3FB2_FFDB14 CAN_F3FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F3FB2_FFDB15_Pos (15U) +#define CAN_F3FB2_FFDB15_Msk (0x1U << CAN_F3FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F3FB2_FFDB15 CAN_F3FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F3FB2_FFDB16_Pos (16U) +#define CAN_F3FB2_FFDB16_Msk (0x1U << CAN_F3FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F3FB2_FFDB16 CAN_F3FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F3FB2_FFDB17_Pos (17U) +#define CAN_F3FB2_FFDB17_Msk (0x1U << CAN_F3FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F3FB2_FFDB17 CAN_F3FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F3FB2_FFDB18_Pos (18U) +#define CAN_F3FB2_FFDB18_Msk (0x1U << CAN_F3FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F3FB2_FFDB18 CAN_F3FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F3FB2_FFDB19_Pos (19U) +#define CAN_F3FB2_FFDB19_Msk (0x1U << CAN_F3FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F3FB2_FFDB19 CAN_F3FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F3FB2_FFDB20_Pos (20U) +#define CAN_F3FB2_FFDB20_Msk (0x1U << CAN_F3FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F3FB2_FFDB20 CAN_F3FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F3FB2_FFDB21_Pos (21U) +#define CAN_F3FB2_FFDB21_Msk (0x1U << CAN_F3FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F3FB2_FFDB21 CAN_F3FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F3FB2_FFDB22_Pos (22U) +#define CAN_F3FB2_FFDB22_Msk (0x1U << CAN_F3FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F3FB2_FFDB22 CAN_F3FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F3FB2_FFDB23_Pos (23U) +#define CAN_F3FB2_FFDB23_Msk (0x1U << CAN_F3FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F3FB2_FFDB23 CAN_F3FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F3FB2_FFDB24_Pos (24U) +#define CAN_F3FB2_FFDB24_Msk (0x1U << CAN_F3FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F3FB2_FFDB24 CAN_F3FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F3FB2_FFDB25_Pos (25U) +#define CAN_F3FB2_FFDB25_Msk (0x1U << CAN_F3FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F3FB2_FFDB25 CAN_F3FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F3FB2_FFDB26_Pos (26U) +#define CAN_F3FB2_FFDB26_Msk (0x1U << CAN_F3FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F3FB2_FFDB26 CAN_F3FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F3FB2_FFDB27_Pos (27U) +#define CAN_F3FB2_FFDB27_Msk (0x1U << CAN_F3FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F3FB2_FFDB27 CAN_F3FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F3FB2_FFDB28_Pos (28U) +#define CAN_F3FB2_FFDB28_Msk (0x1U << CAN_F3FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F3FB2_FFDB28 CAN_F3FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F3FB2_FFDB29_Pos (29U) +#define CAN_F3FB2_FFDB29_Msk (0x1U << CAN_F3FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F3FB2_FFDB29 CAN_F3FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F3FB2_FFDB30_Pos (30U) +#define CAN_F3FB2_FFDB30_Msk (0x1U << CAN_F3FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F3FB2_FFDB30 CAN_F3FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F3FB2_FFDB31_Pos (31U) +#define CAN_F3FB2_FFDB31_Msk (0x1U << CAN_F3FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F3FB2_FFDB31 CAN_F3FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F4FB2 register *******************/ +#define CAN_F4FB2_FFDB0_Pos (0U) +#define CAN_F4FB2_FFDB0_Msk (0x1U << CAN_F4FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F4FB2_FFDB0 CAN_F4FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F4FB2_FFDB1_Pos (1U) +#define CAN_F4FB2_FFDB1_Msk (0x1U << CAN_F4FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F4FB2_FFDB1 CAN_F4FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F4FB2_FFDB2_Pos (2U) +#define CAN_F4FB2_FFDB2_Msk (0x1U << CAN_F4FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F4FB2_FFDB2 CAN_F4FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F4FB2_FFDB3_Pos (3U) +#define CAN_F4FB2_FFDB3_Msk (0x1U << CAN_F4FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F4FB2_FFDB3 CAN_F4FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F4FB2_FFDB4_Pos (4U) +#define CAN_F4FB2_FFDB4_Msk (0x1U << CAN_F4FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F4FB2_FFDB4 CAN_F4FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F4FB2_FFDB5_Pos (5U) +#define CAN_F4FB2_FFDB5_Msk (0x1U << CAN_F4FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F4FB2_FFDB5 CAN_F4FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F4FB2_FFDB6_Pos (6U) +#define CAN_F4FB2_FFDB6_Msk (0x1U << CAN_F4FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F4FB2_FFDB6 CAN_F4FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F4FB2_FFDB7_Pos (7U) +#define CAN_F4FB2_FFDB7_Msk (0x1U << CAN_F4FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F4FB2_FFDB7 CAN_F4FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F4FB2_FFDB8_Pos (8U) +#define CAN_F4FB2_FFDB8_Msk (0x1U << CAN_F4FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F4FB2_FFDB8 CAN_F4FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F4FB2_FFDB9_Pos (9U) +#define CAN_F4FB2_FFDB9_Msk (0x1U << CAN_F4FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F4FB2_FFDB9 CAN_F4FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F4FB2_FFDB10_Pos (10U) +#define CAN_F4FB2_FFDB10_Msk (0x1U << CAN_F4FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F4FB2_FFDB10 CAN_F4FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F4FB2_FFDB11_Pos (11U) +#define CAN_F4FB2_FFDB11_Msk (0x1U << CAN_F4FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F4FB2_FFDB11 CAN_F4FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F4FB2_FFDB12_Pos (12U) +#define CAN_F4FB2_FFDB12_Msk (0x1U << CAN_F4FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F4FB2_FFDB12 CAN_F4FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F4FB2_FFDB13_Pos (13U) +#define CAN_F4FB2_FFDB13_Msk (0x1U << CAN_F4FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F4FB2_FFDB13 CAN_F4FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F4FB2_FFDB14_Pos (14U) +#define CAN_F4FB2_FFDB14_Msk (0x1U << CAN_F4FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F4FB2_FFDB14 CAN_F4FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F4FB2_FFDB15_Pos (15U) +#define CAN_F4FB2_FFDB15_Msk (0x1U << CAN_F4FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F4FB2_FFDB15 CAN_F4FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F4FB2_FFDB16_Pos (16U) +#define CAN_F4FB2_FFDB16_Msk (0x1U << CAN_F4FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F4FB2_FFDB16 CAN_F4FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F4FB2_FFDB17_Pos (17U) +#define CAN_F4FB2_FFDB17_Msk (0x1U << CAN_F4FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F4FB2_FFDB17 CAN_F4FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F4FB2_FFDB18_Pos (18U) +#define CAN_F4FB2_FFDB18_Msk (0x1U << CAN_F4FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F4FB2_FFDB18 CAN_F4FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F4FB2_FFDB19_Pos (19U) +#define CAN_F4FB2_FFDB19_Msk (0x1U << CAN_F4FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F4FB2_FFDB19 CAN_F4FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F4FB2_FFDB20_Pos (20U) +#define CAN_F4FB2_FFDB20_Msk (0x1U << CAN_F4FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F4FB2_FFDB20 CAN_F4FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F4FB2_FFDB21_Pos (21U) +#define CAN_F4FB2_FFDB21_Msk (0x1U << CAN_F4FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F4FB2_FFDB21 CAN_F4FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F4FB2_FFDB22_Pos (22U) +#define CAN_F4FB2_FFDB22_Msk (0x1U << CAN_F4FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F4FB2_FFDB22 CAN_F4FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F4FB2_FFDB23_Pos (23U) +#define CAN_F4FB2_FFDB23_Msk (0x1U << CAN_F4FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F4FB2_FFDB23 CAN_F4FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F4FB2_FFDB24_Pos (24U) +#define CAN_F4FB2_FFDB24_Msk (0x1U << CAN_F4FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F4FB2_FFDB24 CAN_F4FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F4FB2_FFDB25_Pos (25U) +#define CAN_F4FB2_FFDB25_Msk (0x1U << CAN_F4FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F4FB2_FFDB25 CAN_F4FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F4FB2_FFDB26_Pos (26U) +#define CAN_F4FB2_FFDB26_Msk (0x1U << CAN_F4FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F4FB2_FFDB26 CAN_F4FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F4FB2_FFDB27_Pos (27U) +#define CAN_F4FB2_FFDB27_Msk (0x1U << CAN_F4FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F4FB2_FFDB27 CAN_F4FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F4FB2_FFDB28_Pos (28U) +#define CAN_F4FB2_FFDB28_Msk (0x1U << CAN_F4FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F4FB2_FFDB28 CAN_F4FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F4FB2_FFDB29_Pos (29U) +#define CAN_F4FB2_FFDB29_Msk (0x1U << CAN_F4FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F4FB2_FFDB29 CAN_F4FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F4FB2_FFDB30_Pos (30U) +#define CAN_F4FB2_FFDB30_Msk (0x1U << CAN_F4FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F4FB2_FFDB30 CAN_F4FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F4FB2_FFDB31_Pos (31U) +#define CAN_F4FB2_FFDB31_Msk (0x1U << CAN_F4FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F4FB2_FFDB31 CAN_F4FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F5FB2 register *******************/ +#define CAN_F5FB2_FFDB0_Pos (0U) +#define CAN_F5FB2_FFDB0_Msk (0x1U << CAN_F5FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F5FB2_FFDB0 CAN_F5FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F5FB2_FFDB1_Pos (1U) +#define CAN_F5FB2_FFDB1_Msk (0x1U << CAN_F5FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F5FB2_FFDB1 CAN_F5FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F5FB2_FFDB2_Pos (2U) +#define CAN_F5FB2_FFDB2_Msk (0x1U << CAN_F5FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F5FB2_FFDB2 CAN_F5FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F5FB2_FFDB3_Pos (3U) +#define CAN_F5FB2_FFDB3_Msk (0x1U << CAN_F5FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F5FB2_FFDB3 CAN_F5FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F5FB2_FFDB4_Pos (4U) +#define CAN_F5FB2_FFDB4_Msk (0x1U << CAN_F5FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F5FB2_FFDB4 CAN_F5FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F5FB2_FFDB5_Pos (5U) +#define CAN_F5FB2_FFDB5_Msk (0x1U << CAN_F5FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F5FB2_FFDB5 CAN_F5FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F5FB2_FFDB6_Pos (6U) +#define CAN_F5FB2_FFDB6_Msk (0x1U << CAN_F5FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F5FB2_FFDB6 CAN_F5FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F5FB2_FFDB7_Pos (7U) +#define CAN_F5FB2_FFDB7_Msk (0x1U << CAN_F5FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F5FB2_FFDB7 CAN_F5FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F5FB2_FFDB8_Pos (8U) +#define CAN_F5FB2_FFDB8_Msk (0x1U << CAN_F5FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F5FB2_FFDB8 CAN_F5FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F5FB2_FFDB9_Pos (9U) +#define CAN_F5FB2_FFDB9_Msk (0x1U << CAN_F5FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F5FB2_FFDB9 CAN_F5FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F5FB2_FFDB10_Pos (10U) +#define CAN_F5FB2_FFDB10_Msk (0x1U << CAN_F5FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F5FB2_FFDB10 CAN_F5FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F5FB2_FFDB11_Pos (11U) +#define CAN_F5FB2_FFDB11_Msk (0x1U << CAN_F5FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F5FB2_FFDB11 CAN_F5FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F5FB2_FFDB12_Pos (12U) +#define CAN_F5FB2_FFDB12_Msk (0x1U << CAN_F5FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F5FB2_FFDB12 CAN_F5FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F5FB2_FFDB13_Pos (13U) +#define CAN_F5FB2_FFDB13_Msk (0x1U << CAN_F5FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F5FB2_FFDB13 CAN_F5FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F5FB2_FFDB14_Pos (14U) +#define CAN_F5FB2_FFDB14_Msk (0x1U << CAN_F5FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F5FB2_FFDB14 CAN_F5FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F5FB2_FFDB15_Pos (15U) +#define CAN_F5FB2_FFDB15_Msk (0x1U << CAN_F5FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F5FB2_FFDB15 CAN_F5FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F5FB2_FFDB16_Pos (16U) +#define CAN_F5FB2_FFDB16_Msk (0x1U << CAN_F5FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F5FB2_FFDB16 CAN_F5FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F5FB2_FFDB17_Pos (17U) +#define CAN_F5FB2_FFDB17_Msk (0x1U << CAN_F5FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F5FB2_FFDB17 CAN_F5FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F5FB2_FFDB18_Pos (18U) +#define CAN_F5FB2_FFDB18_Msk (0x1U << CAN_F5FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F5FB2_FFDB18 CAN_F5FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F5FB2_FFDB19_Pos (19U) +#define CAN_F5FB2_FFDB19_Msk (0x1U << CAN_F5FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F5FB2_FFDB19 CAN_F5FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F5FB2_FFDB20_Pos (20U) +#define CAN_F5FB2_FFDB20_Msk (0x1U << CAN_F5FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F5FB2_FFDB20 CAN_F5FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F5FB2_FFDB21_Pos (21U) +#define CAN_F5FB2_FFDB21_Msk (0x1U << CAN_F5FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F5FB2_FFDB21 CAN_F5FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F5FB2_FFDB22_Pos (22U) +#define CAN_F5FB2_FFDB22_Msk (0x1U << CAN_F5FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F5FB2_FFDB22 CAN_F5FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F5FB2_FFDB23_Pos (23U) +#define CAN_F5FB2_FFDB23_Msk (0x1U << CAN_F5FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F5FB2_FFDB23 CAN_F5FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F5FB2_FFDB24_Pos (24U) +#define CAN_F5FB2_FFDB24_Msk (0x1U << CAN_F5FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F5FB2_FFDB24 CAN_F5FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F5FB2_FFDB25_Pos (25U) +#define CAN_F5FB2_FFDB25_Msk (0x1U << CAN_F5FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F5FB2_FFDB25 CAN_F5FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F5FB2_FFDB26_Pos (26U) +#define CAN_F5FB2_FFDB26_Msk (0x1U << CAN_F5FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F5FB2_FFDB26 CAN_F5FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F5FB2_FFDB27_Pos (27U) +#define CAN_F5FB2_FFDB27_Msk (0x1U << CAN_F5FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F5FB2_FFDB27 CAN_F5FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F5FB2_FFDB28_Pos (28U) +#define CAN_F5FB2_FFDB28_Msk (0x1U << CAN_F5FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F5FB2_FFDB28 CAN_F5FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F5FB2_FFDB29_Pos (29U) +#define CAN_F5FB2_FFDB29_Msk (0x1U << CAN_F5FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F5FB2_FFDB29 CAN_F5FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F5FB2_FFDB30_Pos (30U) +#define CAN_F5FB2_FFDB30_Msk (0x1U << CAN_F5FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F5FB2_FFDB30 CAN_F5FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F5FB2_FFDB31_Pos (31U) +#define CAN_F5FB2_FFDB31_Msk (0x1U << CAN_F5FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F5FB2_FFDB31 CAN_F5FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F6FB2 register *******************/ +#define CAN_F6FB2_FFDB0_Pos (0U) +#define CAN_F6FB2_FFDB0_Msk (0x1U << CAN_F6FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F6FB2_FFDB0 CAN_F6FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F6FB2_FFDB1_Pos (1U) +#define CAN_F6FB2_FFDB1_Msk (0x1U << CAN_F6FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F6FB2_FFDB1 CAN_F6FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F6FB2_FFDB2_Pos (2U) +#define CAN_F6FB2_FFDB2_Msk (0x1U << CAN_F6FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F6FB2_FFDB2 CAN_F6FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F6FB2_FFDB3_Pos (3U) +#define CAN_F6FB2_FFDB3_Msk (0x1U << CAN_F6FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F6FB2_FFDB3 CAN_F6FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F6FB2_FFDB4_Pos (4U) +#define CAN_F6FB2_FFDB4_Msk (0x1U << CAN_F6FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F6FB2_FFDB4 CAN_F6FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F6FB2_FFDB5_Pos (5U) +#define CAN_F6FB2_FFDB5_Msk (0x1U << CAN_F6FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F6FB2_FFDB5 CAN_F6FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F6FB2_FFDB6_Pos (6U) +#define CAN_F6FB2_FFDB6_Msk (0x1U << CAN_F6FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F6FB2_FFDB6 CAN_F6FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F6FB2_FFDB7_Pos (7U) +#define CAN_F6FB2_FFDB7_Msk (0x1U << CAN_F6FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F6FB2_FFDB7 CAN_F6FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F6FB2_FFDB8_Pos (8U) +#define CAN_F6FB2_FFDB8_Msk (0x1U << CAN_F6FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F6FB2_FFDB8 CAN_F6FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F6FB2_FFDB9_Pos (9U) +#define CAN_F6FB2_FFDB9_Msk (0x1U << CAN_F6FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F6FB2_FFDB9 CAN_F6FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F6FB2_FFDB10_Pos (10U) +#define CAN_F6FB2_FFDB10_Msk (0x1U << CAN_F6FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F6FB2_FFDB10 CAN_F6FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F6FB2_FFDB11_Pos (11U) +#define CAN_F6FB2_FFDB11_Msk (0x1U << CAN_F6FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F6FB2_FFDB11 CAN_F6FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F6FB2_FFDB12_Pos (12U) +#define CAN_F6FB2_FFDB12_Msk (0x1U << CAN_F6FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F6FB2_FFDB12 CAN_F6FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F6FB2_FFDB13_Pos (13U) +#define CAN_F6FB2_FFDB13_Msk (0x1U << CAN_F6FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F6FB2_FFDB13 CAN_F6FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F6FB2_FFDB14_Pos (14U) +#define CAN_F6FB2_FFDB14_Msk (0x1U << CAN_F6FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F6FB2_FFDB14 CAN_F6FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F6FB2_FFDB15_Pos (15U) +#define CAN_F6FB2_FFDB15_Msk (0x1U << CAN_F6FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F6FB2_FFDB15 CAN_F6FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F6FB2_FFDB16_Pos (16U) +#define CAN_F6FB2_FFDB16_Msk (0x1U << CAN_F6FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F6FB2_FFDB16 CAN_F6FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F6FB2_FFDB17_Pos (17U) +#define CAN_F6FB2_FFDB17_Msk (0x1U << CAN_F6FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F6FB2_FFDB17 CAN_F6FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F6FB2_FFDB18_Pos (18U) +#define CAN_F6FB2_FFDB18_Msk (0x1U << CAN_F6FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F6FB2_FFDB18 CAN_F6FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F6FB2_FFDB19_Pos (19U) +#define CAN_F6FB2_FFDB19_Msk (0x1U << CAN_F6FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F6FB2_FFDB19 CAN_F6FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F6FB2_FFDB20_Pos (20U) +#define CAN_F6FB2_FFDB20_Msk (0x1U << CAN_F6FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F6FB2_FFDB20 CAN_F6FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F6FB2_FFDB21_Pos (21U) +#define CAN_F6FB2_FFDB21_Msk (0x1U << CAN_F6FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F6FB2_FFDB21 CAN_F6FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F6FB2_FFDB22_Pos (22U) +#define CAN_F6FB2_FFDB22_Msk (0x1U << CAN_F6FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F6FB2_FFDB22 CAN_F6FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F6FB2_FFDB23_Pos (23U) +#define CAN_F6FB2_FFDB23_Msk (0x1U << CAN_F6FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F6FB2_FFDB23 CAN_F6FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F6FB2_FFDB24_Pos (24U) +#define CAN_F6FB2_FFDB24_Msk (0x1U << CAN_F6FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F6FB2_FFDB24 CAN_F6FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F6FB2_FFDB25_Pos (25U) +#define CAN_F6FB2_FFDB25_Msk (0x1U << CAN_F6FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F6FB2_FFDB25 CAN_F6FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F6FB2_FFDB26_Pos (26U) +#define CAN_F6FB2_FFDB26_Msk (0x1U << CAN_F6FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F6FB2_FFDB26 CAN_F6FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F6FB2_FFDB27_Pos (27U) +#define CAN_F6FB2_FFDB27_Msk (0x1U << CAN_F6FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F6FB2_FFDB27 CAN_F6FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F6FB2_FFDB28_Pos (28U) +#define CAN_F6FB2_FFDB28_Msk (0x1U << CAN_F6FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F6FB2_FFDB28 CAN_F6FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F6FB2_FFDB29_Pos (29U) +#define CAN_F6FB2_FFDB29_Msk (0x1U << CAN_F6FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F6FB2_FFDB29 CAN_F6FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F6FB2_FFDB30_Pos (30U) +#define CAN_F6FB2_FFDB30_Msk (0x1U << CAN_F6FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F6FB2_FFDB30 CAN_F6FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F6FB2_FFDB31_Pos (31U) +#define CAN_F6FB2_FFDB31_Msk (0x1U << CAN_F6FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F6FB2_FFDB31 CAN_F6FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F7FB2 register *******************/ +#define CAN_F7FB2_FFDB0_Pos (0U) +#define CAN_F7FB2_FFDB0_Msk (0x1U << CAN_F7FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F7FB2_FFDB0 CAN_F7FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F7FB2_FFDB1_Pos (1U) +#define CAN_F7FB2_FFDB1_Msk (0x1U << CAN_F7FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F7FB2_FFDB1 CAN_F7FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F7FB2_FFDB2_Pos (2U) +#define CAN_F7FB2_FFDB2_Msk (0x1U << CAN_F7FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F7FB2_FFDB2 CAN_F7FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F7FB2_FFDB3_Pos (3U) +#define CAN_F7FB2_FFDB3_Msk (0x1U << CAN_F7FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F7FB2_FFDB3 CAN_F7FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F7FB2_FFDB4_Pos (4U) +#define CAN_F7FB2_FFDB4_Msk (0x1U << CAN_F7FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F7FB2_FFDB4 CAN_F7FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F7FB2_FFDB5_Pos (5U) +#define CAN_F7FB2_FFDB5_Msk (0x1U << CAN_F7FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F7FB2_FFDB5 CAN_F7FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F7FB2_FFDB6_Pos (6U) +#define CAN_F7FB2_FFDB6_Msk (0x1U << CAN_F7FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F7FB2_FFDB6 CAN_F7FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F7FB2_FFDB7_Pos (7U) +#define CAN_F7FB2_FFDB7_Msk (0x1U << CAN_F7FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F7FB2_FFDB7 CAN_F7FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F7FB2_FFDB8_Pos (8U) +#define CAN_F7FB2_FFDB8_Msk (0x1U << CAN_F7FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F7FB2_FFDB8 CAN_F7FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F7FB2_FFDB9_Pos (9U) +#define CAN_F7FB2_FFDB9_Msk (0x1U << CAN_F7FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F7FB2_FFDB9 CAN_F7FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F7FB2_FFDB10_Pos (10U) +#define CAN_F7FB2_FFDB10_Msk (0x1U << CAN_F7FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F7FB2_FFDB10 CAN_F7FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F7FB2_FFDB11_Pos (11U) +#define CAN_F7FB2_FFDB11_Msk (0x1U << CAN_F7FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F7FB2_FFDB11 CAN_F7FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F7FB2_FFDB12_Pos (12U) +#define CAN_F7FB2_FFDB12_Msk (0x1U << CAN_F7FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F7FB2_FFDB12 CAN_F7FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F7FB2_FFDB13_Pos (13U) +#define CAN_F7FB2_FFDB13_Msk (0x1U << CAN_F7FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F7FB2_FFDB13 CAN_F7FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F7FB2_FFDB14_Pos (14U) +#define CAN_F7FB2_FFDB14_Msk (0x1U << CAN_F7FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F7FB2_FFDB14 CAN_F7FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F7FB2_FFDB15_Pos (15U) +#define CAN_F7FB2_FFDB15_Msk (0x1U << CAN_F7FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F7FB2_FFDB15 CAN_F7FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F7FB2_FFDB16_Pos (16U) +#define CAN_F7FB2_FFDB16_Msk (0x1U << CAN_F7FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F7FB2_FFDB16 CAN_F7FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F7FB2_FFDB17_Pos (17U) +#define CAN_F7FB2_FFDB17_Msk (0x1U << CAN_F7FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F7FB2_FFDB17 CAN_F7FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F7FB2_FFDB18_Pos (18U) +#define CAN_F7FB2_FFDB18_Msk (0x1U << CAN_F7FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F7FB2_FFDB18 CAN_F7FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F7FB2_FFDB19_Pos (19U) +#define CAN_F7FB2_FFDB19_Msk (0x1U << CAN_F7FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F7FB2_FFDB19 CAN_F7FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F7FB2_FFDB20_Pos (20U) +#define CAN_F7FB2_FFDB20_Msk (0x1U << CAN_F7FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F7FB2_FFDB20 CAN_F7FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F7FB2_FFDB21_Pos (21U) +#define CAN_F7FB2_FFDB21_Msk (0x1U << CAN_F7FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F7FB2_FFDB21 CAN_F7FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F7FB2_FFDB22_Pos (22U) +#define CAN_F7FB2_FFDB22_Msk (0x1U << CAN_F7FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F7FB2_FFDB22 CAN_F7FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F7FB2_FFDB23_Pos (23U) +#define CAN_F7FB2_FFDB23_Msk (0x1U << CAN_F7FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F7FB2_FFDB23 CAN_F7FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F7FB2_FFDB24_Pos (24U) +#define CAN_F7FB2_FFDB24_Msk (0x1U << CAN_F7FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F7FB2_FFDB24 CAN_F7FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F7FB2_FFDB25_Pos (25U) +#define CAN_F7FB2_FFDB25_Msk (0x1U << CAN_F7FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F7FB2_FFDB25 CAN_F7FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F7FB2_FFDB26_Pos (26U) +#define CAN_F7FB2_FFDB26_Msk (0x1U << CAN_F7FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F7FB2_FFDB26 CAN_F7FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F7FB2_FFDB27_Pos (27U) +#define CAN_F7FB2_FFDB27_Msk (0x1U << CAN_F7FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F7FB2_FFDB27 CAN_F7FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F7FB2_FFDB28_Pos (28U) +#define CAN_F7FB2_FFDB28_Msk (0x1U << CAN_F7FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F7FB2_FFDB28 CAN_F7FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F7FB2_FFDB29_Pos (29U) +#define CAN_F7FB2_FFDB29_Msk (0x1U << CAN_F7FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F7FB2_FFDB29 CAN_F7FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F7FB2_FFDB30_Pos (30U) +#define CAN_F7FB2_FFDB30_Msk (0x1U << CAN_F7FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F7FB2_FFDB30 CAN_F7FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F7FB2_FFDB31_Pos (31U) +#define CAN_F7FB2_FFDB31_Msk (0x1U << CAN_F7FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F7FB2_FFDB31 CAN_F7FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F8FB2 register *******************/ +#define CAN_F8FB2_FFDB0_Pos (0U) +#define CAN_F8FB2_FFDB0_Msk (0x1U << CAN_F8FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F8FB2_FFDB0 CAN_F8FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F8FB2_FFDB1_Pos (1U) +#define CAN_F8FB2_FFDB1_Msk (0x1U << CAN_F8FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F8FB2_FFDB1 CAN_F8FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F8FB2_FFDB2_Pos (2U) +#define CAN_F8FB2_FFDB2_Msk (0x1U << CAN_F8FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F8FB2_FFDB2 CAN_F8FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F8FB2_FFDB3_Pos (3U) +#define CAN_F8FB2_FFDB3_Msk (0x1U << CAN_F8FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F8FB2_FFDB3 CAN_F8FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F8FB2_FFDB4_Pos (4U) +#define CAN_F8FB2_FFDB4_Msk (0x1U << CAN_F8FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F8FB2_FFDB4 CAN_F8FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F8FB2_FFDB5_Pos (5U) +#define CAN_F8FB2_FFDB5_Msk (0x1U << CAN_F8FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F8FB2_FFDB5 CAN_F8FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F8FB2_FFDB6_Pos (6U) +#define CAN_F8FB2_FFDB6_Msk (0x1U << CAN_F8FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F8FB2_FFDB6 CAN_F8FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F8FB2_FFDB7_Pos (7U) +#define CAN_F8FB2_FFDB7_Msk (0x1U << CAN_F8FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F8FB2_FFDB7 CAN_F8FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F8FB2_FFDB8_Pos (8U) +#define CAN_F8FB2_FFDB8_Msk (0x1U << CAN_F8FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F8FB2_FFDB8 CAN_F8FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F8FB2_FFDB9_Pos (9U) +#define CAN_F8FB2_FFDB9_Msk (0x1U << CAN_F8FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F8FB2_FFDB9 CAN_F8FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F8FB2_FFDB10_Pos (10U) +#define CAN_F8FB2_FFDB10_Msk (0x1U << CAN_F8FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F8FB2_FFDB10 CAN_F8FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F8FB2_FFDB11_Pos (11U) +#define CAN_F8FB2_FFDB11_Msk (0x1U << CAN_F8FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F8FB2_FFDB11 CAN_F8FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F8FB2_FFDB12_Pos (12U) +#define CAN_F8FB2_FFDB12_Msk (0x1U << CAN_F8FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F8FB2_FFDB12 CAN_F8FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F8FB2_FFDB13_Pos (13U) +#define CAN_F8FB2_FFDB13_Msk (0x1U << CAN_F8FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F8FB2_FFDB13 CAN_F8FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F8FB2_FFDB14_Pos (14U) +#define CAN_F8FB2_FFDB14_Msk (0x1U << CAN_F8FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F8FB2_FFDB14 CAN_F8FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F8FB2_FFDB15_Pos (15U) +#define CAN_F8FB2_FFDB15_Msk (0x1U << CAN_F8FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F8FB2_FFDB15 CAN_F8FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F8FB2_FFDB16_Pos (16U) +#define CAN_F8FB2_FFDB16_Msk (0x1U << CAN_F8FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F8FB2_FFDB16 CAN_F8FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F8FB2_FFDB17_Pos (17U) +#define CAN_F8FB2_FFDB17_Msk (0x1U << CAN_F8FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F8FB2_FFDB17 CAN_F8FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F8FB2_FFDB18_Pos (18U) +#define CAN_F8FB2_FFDB18_Msk (0x1U << CAN_F8FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F8FB2_FFDB18 CAN_F8FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F8FB2_FFDB19_Pos (19U) +#define CAN_F8FB2_FFDB19_Msk (0x1U << CAN_F8FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F8FB2_FFDB19 CAN_F8FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F8FB2_FFDB20_Pos (20U) +#define CAN_F8FB2_FFDB20_Msk (0x1U << CAN_F8FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F8FB2_FFDB20 CAN_F8FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F8FB2_FFDB21_Pos (21U) +#define CAN_F8FB2_FFDB21_Msk (0x1U << CAN_F8FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F8FB2_FFDB21 CAN_F8FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F8FB2_FFDB22_Pos (22U) +#define CAN_F8FB2_FFDB22_Msk (0x1U << CAN_F8FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F8FB2_FFDB22 CAN_F8FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F8FB2_FFDB23_Pos (23U) +#define CAN_F8FB2_FFDB23_Msk (0x1U << CAN_F8FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F8FB2_FFDB23 CAN_F8FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F8FB2_FFDB24_Pos (24U) +#define CAN_F8FB2_FFDB24_Msk (0x1U << CAN_F8FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F8FB2_FFDB24 CAN_F8FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F8FB2_FFDB25_Pos (25U) +#define CAN_F8FB2_FFDB25_Msk (0x1U << CAN_F8FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F8FB2_FFDB25 CAN_F8FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F8FB2_FFDB26_Pos (26U) +#define CAN_F8FB2_FFDB26_Msk (0x1U << CAN_F8FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F8FB2_FFDB26 CAN_F8FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F8FB2_FFDB27_Pos (27U) +#define CAN_F8FB2_FFDB27_Msk (0x1U << CAN_F8FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F8FB2_FFDB27 CAN_F8FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F8FB2_FFDB28_Pos (28U) +#define CAN_F8FB2_FFDB28_Msk (0x1U << CAN_F8FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F8FB2_FFDB28 CAN_F8FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F8FB2_FFDB29_Pos (29U) +#define CAN_F8FB2_FFDB29_Msk (0x1U << CAN_F8FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F8FB2_FFDB29 CAN_F8FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F8FB2_FFDB30_Pos (30U) +#define CAN_F8FB2_FFDB30_Msk (0x1U << CAN_F8FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F8FB2_FFDB30 CAN_F8FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F8FB2_FFDB31_Pos (31U) +#define CAN_F8FB2_FFDB31_Msk (0x1U << CAN_F8FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F8FB2_FFDB31 CAN_F8FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F9FB2 register *******************/ +#define CAN_F9FB2_FFDB0_Pos (0U) +#define CAN_F9FB2_FFDB0_Msk (0x1U << CAN_F9FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F9FB2_FFDB0 CAN_F9FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F9FB2_FFDB1_Pos (1U) +#define CAN_F9FB2_FFDB1_Msk (0x1U << CAN_F9FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F9FB2_FFDB1 CAN_F9FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F9FB2_FFDB2_Pos (2U) +#define CAN_F9FB2_FFDB2_Msk (0x1U << CAN_F9FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F9FB2_FFDB2 CAN_F9FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F9FB2_FFDB3_Pos (3U) +#define CAN_F9FB2_FFDB3_Msk (0x1U << CAN_F9FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F9FB2_FFDB3 CAN_F9FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F9FB2_FFDB4_Pos (4U) +#define CAN_F9FB2_FFDB4_Msk (0x1U << CAN_F9FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F9FB2_FFDB4 CAN_F9FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F9FB2_FFDB5_Pos (5U) +#define CAN_F9FB2_FFDB5_Msk (0x1U << CAN_F9FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F9FB2_FFDB5 CAN_F9FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F9FB2_FFDB6_Pos (6U) +#define CAN_F9FB2_FFDB6_Msk (0x1U << CAN_F9FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F9FB2_FFDB6 CAN_F9FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F9FB2_FFDB7_Pos (7U) +#define CAN_F9FB2_FFDB7_Msk (0x1U << CAN_F9FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F9FB2_FFDB7 CAN_F9FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F9FB2_FFDB8_Pos (8U) +#define CAN_F9FB2_FFDB8_Msk (0x1U << CAN_F9FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F9FB2_FFDB8 CAN_F9FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F9FB2_FFDB9_Pos (9U) +#define CAN_F9FB2_FFDB9_Msk (0x1U << CAN_F9FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F9FB2_FFDB9 CAN_F9FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F9FB2_FFDB10_Pos (10U) +#define CAN_F9FB2_FFDB10_Msk (0x1U << CAN_F9FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F9FB2_FFDB10 CAN_F9FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F9FB2_FFDB11_Pos (11U) +#define CAN_F9FB2_FFDB11_Msk (0x1U << CAN_F9FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F9FB2_FFDB11 CAN_F9FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F9FB2_FFDB12_Pos (12U) +#define CAN_F9FB2_FFDB12_Msk (0x1U << CAN_F9FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F9FB2_FFDB12 CAN_F9FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F9FB2_FFDB13_Pos (13U) +#define CAN_F9FB2_FFDB13_Msk (0x1U << CAN_F9FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F9FB2_FFDB13 CAN_F9FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F9FB2_FFDB14_Pos (14U) +#define CAN_F9FB2_FFDB14_Msk (0x1U << CAN_F9FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F9FB2_FFDB14 CAN_F9FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F9FB2_FFDB15_Pos (15U) +#define CAN_F9FB2_FFDB15_Msk (0x1U << CAN_F9FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F9FB2_FFDB15 CAN_F9FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F9FB2_FFDB16_Pos (16U) +#define CAN_F9FB2_FFDB16_Msk (0x1U << CAN_F9FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F9FB2_FFDB16 CAN_F9FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F9FB2_FFDB17_Pos (17U) +#define CAN_F9FB2_FFDB17_Msk (0x1U << CAN_F9FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F9FB2_FFDB17 CAN_F9FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F9FB2_FFDB18_Pos (18U) +#define CAN_F9FB2_FFDB18_Msk (0x1U << CAN_F9FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F9FB2_FFDB18 CAN_F9FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F9FB2_FFDB19_Pos (19U) +#define CAN_F9FB2_FFDB19_Msk (0x1U << CAN_F9FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F9FB2_FFDB19 CAN_F9FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F9FB2_FFDB20_Pos (20U) +#define CAN_F9FB2_FFDB20_Msk (0x1U << CAN_F9FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F9FB2_FFDB20 CAN_F9FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F9FB2_FFDB21_Pos (21U) +#define CAN_F9FB2_FFDB21_Msk (0x1U << CAN_F9FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F9FB2_FFDB21 CAN_F9FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F9FB2_FFDB22_Pos (22U) +#define CAN_F9FB2_FFDB22_Msk (0x1U << CAN_F9FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F9FB2_FFDB22 CAN_F9FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F9FB2_FFDB23_Pos (23U) +#define CAN_F9FB2_FFDB23_Msk (0x1U << CAN_F9FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F9FB2_FFDB23 CAN_F9FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F9FB2_FFDB24_Pos (24U) +#define CAN_F9FB2_FFDB24_Msk (0x1U << CAN_F9FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F9FB2_FFDB24 CAN_F9FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F9FB2_FFDB25_Pos (25U) +#define CAN_F9FB2_FFDB25_Msk (0x1U << CAN_F9FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F9FB2_FFDB25 CAN_F9FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F9FB2_FFDB26_Pos (26U) +#define CAN_F9FB2_FFDB26_Msk (0x1U << CAN_F9FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F9FB2_FFDB26 CAN_F9FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F9FB2_FFDB27_Pos (27U) +#define CAN_F9FB2_FFDB27_Msk (0x1U << CAN_F9FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F9FB2_FFDB27 CAN_F9FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F9FB2_FFDB28_Pos (28U) +#define CAN_F9FB2_FFDB28_Msk (0x1U << CAN_F9FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F9FB2_FFDB28 CAN_F9FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F9FB2_FFDB29_Pos (29U) +#define CAN_F9FB2_FFDB29_Msk (0x1U << CAN_F9FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F9FB2_FFDB29 CAN_F9FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F9FB2_FFDB30_Pos (30U) +#define CAN_F9FB2_FFDB30_Msk (0x1U << CAN_F9FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F9FB2_FFDB30 CAN_F9FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F9FB2_FFDB31_Pos (31U) +#define CAN_F9FB2_FFDB31_Msk (0x1U << CAN_F9FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F9FB2_FFDB31 CAN_F9FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F10FB2 register ******************/ +#define CAN_F10FB2_FFDB0_Pos (0U) +#define CAN_F10FB2_FFDB0_Msk (0x1U << CAN_F10FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F10FB2_FFDB0 CAN_F10FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F10FB2_FFDB1_Pos (1U) +#define CAN_F10FB2_FFDB1_Msk (0x1U << CAN_F10FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F10FB2_FFDB1 CAN_F10FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F10FB2_FFDB2_Pos (2U) +#define CAN_F10FB2_FFDB2_Msk (0x1U << CAN_F10FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F10FB2_FFDB2 CAN_F10FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F10FB2_FFDB3_Pos (3U) +#define CAN_F10FB2_FFDB3_Msk (0x1U << CAN_F10FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F10FB2_FFDB3 CAN_F10FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F10FB2_FFDB4_Pos (4U) +#define CAN_F10FB2_FFDB4_Msk (0x1U << CAN_F10FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F10FB2_FFDB4 CAN_F10FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F10FB2_FFDB5_Pos (5U) +#define CAN_F10FB2_FFDB5_Msk (0x1U << CAN_F10FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F10FB2_FFDB5 CAN_F10FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F10FB2_FFDB6_Pos (6U) +#define CAN_F10FB2_FFDB6_Msk (0x1U << CAN_F10FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F10FB2_FFDB6 CAN_F10FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F10FB2_FFDB7_Pos (7U) +#define CAN_F10FB2_FFDB7_Msk (0x1U << CAN_F10FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F10FB2_FFDB7 CAN_F10FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F10FB2_FFDB8_Pos (8U) +#define CAN_F10FB2_FFDB8_Msk (0x1U << CAN_F10FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F10FB2_FFDB8 CAN_F10FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F10FB2_FFDB9_Pos (9U) +#define CAN_F10FB2_FFDB9_Msk (0x1U << CAN_F10FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F10FB2_FFDB9 CAN_F10FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F10FB2_FFDB10_Pos (10U) +#define CAN_F10FB2_FFDB10_Msk (0x1U << CAN_F10FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F10FB2_FFDB10 CAN_F10FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F10FB2_FFDB11_Pos (11U) +#define CAN_F10FB2_FFDB11_Msk (0x1U << CAN_F10FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F10FB2_FFDB11 CAN_F10FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F10FB2_FFDB12_Pos (12U) +#define CAN_F10FB2_FFDB12_Msk (0x1U << CAN_F10FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F10FB2_FFDB12 CAN_F10FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F10FB2_FFDB13_Pos (13U) +#define CAN_F10FB2_FFDB13_Msk (0x1U << CAN_F10FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F10FB2_FFDB13 CAN_F10FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F10FB2_FFDB14_Pos (14U) +#define CAN_F10FB2_FFDB14_Msk (0x1U << CAN_F10FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F10FB2_FFDB14 CAN_F10FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F10FB2_FFDB15_Pos (15U) +#define CAN_F10FB2_FFDB15_Msk (0x1U << CAN_F10FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F10FB2_FFDB15 CAN_F10FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F10FB2_FFDB16_Pos (16U) +#define CAN_F10FB2_FFDB16_Msk (0x1U << CAN_F10FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F10FB2_FFDB16 CAN_F10FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F10FB2_FFDB17_Pos (17U) +#define CAN_F10FB2_FFDB17_Msk (0x1U << CAN_F10FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F10FB2_FFDB17 CAN_F10FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F10FB2_FFDB18_Pos (18U) +#define CAN_F10FB2_FFDB18_Msk (0x1U << CAN_F10FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F10FB2_FFDB18 CAN_F10FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F10FB2_FFDB19_Pos (19U) +#define CAN_F10FB2_FFDB19_Msk (0x1U << CAN_F10FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F10FB2_FFDB19 CAN_F10FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F10FB2_FFDB20_Pos (20U) +#define CAN_F10FB2_FFDB20_Msk (0x1U << CAN_F10FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F10FB2_FFDB20 CAN_F10FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F10FB2_FFDB21_Pos (21U) +#define CAN_F10FB2_FFDB21_Msk (0x1U << CAN_F10FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F10FB2_FFDB21 CAN_F10FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F10FB2_FFDB22_Pos (22U) +#define CAN_F10FB2_FFDB22_Msk (0x1U << CAN_F10FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F10FB2_FFDB22 CAN_F10FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F10FB2_FFDB23_Pos (23U) +#define CAN_F10FB2_FFDB23_Msk (0x1U << CAN_F10FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F10FB2_FFDB23 CAN_F10FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F10FB2_FFDB24_Pos (24U) +#define CAN_F10FB2_FFDB24_Msk (0x1U << CAN_F10FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F10FB2_FFDB24 CAN_F10FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F10FB2_FFDB25_Pos (25U) +#define CAN_F10FB2_FFDB25_Msk (0x1U << CAN_F10FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F10FB2_FFDB25 CAN_F10FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F10FB2_FFDB26_Pos (26U) +#define CAN_F10FB2_FFDB26_Msk (0x1U << CAN_F10FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F10FB2_FFDB26 CAN_F10FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F10FB2_FFDB27_Pos (27U) +#define CAN_F10FB2_FFDB27_Msk (0x1U << CAN_F10FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F10FB2_FFDB27 CAN_F10FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F10FB2_FFDB28_Pos (28U) +#define CAN_F10FB2_FFDB28_Msk (0x1U << CAN_F10FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F10FB2_FFDB28 CAN_F10FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F10FB2_FFDB29_Pos (29U) +#define CAN_F10FB2_FFDB29_Msk (0x1U << CAN_F10FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F10FB2_FFDB29 CAN_F10FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F10FB2_FFDB30_Pos (30U) +#define CAN_F10FB2_FFDB30_Msk (0x1U << CAN_F10FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F10FB2_FFDB30 CAN_F10FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F10FB2_FFDB31_Pos (31U) +#define CAN_F10FB2_FFDB31_Msk (0x1U << CAN_F10FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F10FB2_FFDB31 CAN_F10FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F11FB2 register ******************/ +#define CAN_F11FB2_FFDB0_Pos (0U) +#define CAN_F11FB2_FFDB0_Msk (0x1U << CAN_F11FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F11FB2_FFDB0 CAN_F11FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F11FB2_FFDB1_Pos (1U) +#define CAN_F11FB2_FFDB1_Msk (0x1U << CAN_F11FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F11FB2_FFDB1 CAN_F11FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F11FB2_FFDB2_Pos (2U) +#define CAN_F11FB2_FFDB2_Msk (0x1U << CAN_F11FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F11FB2_FFDB2 CAN_F11FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F11FB2_FFDB3_Pos (3U) +#define CAN_F11FB2_FFDB3_Msk (0x1U << CAN_F11FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F11FB2_FFDB3 CAN_F11FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F11FB2_FFDB4_Pos (4U) +#define CAN_F11FB2_FFDB4_Msk (0x1U << CAN_F11FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F11FB2_FFDB4 CAN_F11FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F11FB2_FFDB5_Pos (5U) +#define CAN_F11FB2_FFDB5_Msk (0x1U << CAN_F11FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F11FB2_FFDB5 CAN_F11FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F11FB2_FFDB6_Pos (6U) +#define CAN_F11FB2_FFDB6_Msk (0x1U << CAN_F11FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F11FB2_FFDB6 CAN_F11FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F11FB2_FFDB7_Pos (7U) +#define CAN_F11FB2_FFDB7_Msk (0x1U << CAN_F11FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F11FB2_FFDB7 CAN_F11FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F11FB2_FFDB8_Pos (8U) +#define CAN_F11FB2_FFDB8_Msk (0x1U << CAN_F11FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F11FB2_FFDB8 CAN_F11FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F11FB2_FFDB9_Pos (9U) +#define CAN_F11FB2_FFDB9_Msk (0x1U << CAN_F11FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F11FB2_FFDB9 CAN_F11FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F11FB2_FFDB10_Pos (10U) +#define CAN_F11FB2_FFDB10_Msk (0x1U << CAN_F11FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F11FB2_FFDB10 CAN_F11FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F11FB2_FFDB11_Pos (11U) +#define CAN_F11FB2_FFDB11_Msk (0x1U << CAN_F11FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F11FB2_FFDB11 CAN_F11FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F11FB2_FFDB12_Pos (12U) +#define CAN_F11FB2_FFDB12_Msk (0x1U << CAN_F11FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F11FB2_FFDB12 CAN_F11FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F11FB2_FFDB13_Pos (13U) +#define CAN_F11FB2_FFDB13_Msk (0x1U << CAN_F11FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F11FB2_FFDB13 CAN_F11FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F11FB2_FFDB14_Pos (14U) +#define CAN_F11FB2_FFDB14_Msk (0x1U << CAN_F11FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F11FB2_FFDB14 CAN_F11FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F11FB2_FFDB15_Pos (15U) +#define CAN_F11FB2_FFDB15_Msk (0x1U << CAN_F11FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F11FB2_FFDB15 CAN_F11FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F11FB2_FFDB16_Pos (16U) +#define CAN_F11FB2_FFDB16_Msk (0x1U << CAN_F11FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F11FB2_FFDB16 CAN_F11FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F11FB2_FFDB17_Pos (17U) +#define CAN_F11FB2_FFDB17_Msk (0x1U << CAN_F11FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F11FB2_FFDB17 CAN_F11FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F11FB2_FFDB18_Pos (18U) +#define CAN_F11FB2_FFDB18_Msk (0x1U << CAN_F11FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F11FB2_FFDB18 CAN_F11FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F11FB2_FFDB19_Pos (19U) +#define CAN_F11FB2_FFDB19_Msk (0x1U << CAN_F11FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F11FB2_FFDB19 CAN_F11FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F11FB2_FFDB20_Pos (20U) +#define CAN_F11FB2_FFDB20_Msk (0x1U << CAN_F11FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F11FB2_FFDB20 CAN_F11FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F11FB2_FFDB21_Pos (21U) +#define CAN_F11FB2_FFDB21_Msk (0x1U << CAN_F11FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F11FB2_FFDB21 CAN_F11FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F11FB2_FFDB22_Pos (22U) +#define CAN_F11FB2_FFDB22_Msk (0x1U << CAN_F11FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F11FB2_FFDB22 CAN_F11FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F11FB2_FFDB23_Pos (23U) +#define CAN_F11FB2_FFDB23_Msk (0x1U << CAN_F11FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F11FB2_FFDB23 CAN_F11FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F11FB2_FFDB24_Pos (24U) +#define CAN_F11FB2_FFDB24_Msk (0x1U << CAN_F11FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F11FB2_FFDB24 CAN_F11FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F11FB2_FFDB25_Pos (25U) +#define CAN_F11FB2_FFDB25_Msk (0x1U << CAN_F11FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F11FB2_FFDB25 CAN_F11FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F11FB2_FFDB26_Pos (26U) +#define CAN_F11FB2_FFDB26_Msk (0x1U << CAN_F11FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F11FB2_FFDB26 CAN_F11FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F11FB2_FFDB27_Pos (27U) +#define CAN_F11FB2_FFDB27_Msk (0x1U << CAN_F11FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F11FB2_FFDB27 CAN_F11FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F11FB2_FFDB28_Pos (28U) +#define CAN_F11FB2_FFDB28_Msk (0x1U << CAN_F11FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F11FB2_FFDB28 CAN_F11FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F11FB2_FFDB29_Pos (29U) +#define CAN_F11FB2_FFDB29_Msk (0x1U << CAN_F11FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F11FB2_FFDB29 CAN_F11FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F11FB2_FFDB30_Pos (30U) +#define CAN_F11FB2_FFDB30_Msk (0x1U << CAN_F11FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F11FB2_FFDB30 CAN_F11FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F11FB2_FFDB31_Pos (31U) +#define CAN_F11FB2_FFDB31_Msk (0x1U << CAN_F11FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F11FB2_FFDB31 CAN_F11FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F12FB2 register ******************/ +#define CAN_F12FB2_FFDB0_Pos (0U) +#define CAN_F12FB2_FFDB0_Msk (0x1U << CAN_F12FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F12FB2_FFDB0 CAN_F12FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F12FB2_FFDB1_Pos (1U) +#define CAN_F12FB2_FFDB1_Msk (0x1U << CAN_F12FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F12FB2_FFDB1 CAN_F12FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F12FB2_FFDB2_Pos (2U) +#define CAN_F12FB2_FFDB2_Msk (0x1U << CAN_F12FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F12FB2_FFDB2 CAN_F12FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F12FB2_FFDB3_Pos (3U) +#define CAN_F12FB2_FFDB3_Msk (0x1U << CAN_F12FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F12FB2_FFDB3 CAN_F12FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F12FB2_FFDB4_Pos (4U) +#define CAN_F12FB2_FFDB4_Msk (0x1U << CAN_F12FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F12FB2_FFDB4 CAN_F12FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F12FB2_FFDB5_Pos (5U) +#define CAN_F12FB2_FFDB5_Msk (0x1U << CAN_F12FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F12FB2_FFDB5 CAN_F12FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F12FB2_FFDB6_Pos (6U) +#define CAN_F12FB2_FFDB6_Msk (0x1U << CAN_F12FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F12FB2_FFDB6 CAN_F12FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F12FB2_FFDB7_Pos (7U) +#define CAN_F12FB2_FFDB7_Msk (0x1U << CAN_F12FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F12FB2_FFDB7 CAN_F12FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F12FB2_FFDB8_Pos (8U) +#define CAN_F12FB2_FFDB8_Msk (0x1U << CAN_F12FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F12FB2_FFDB8 CAN_F12FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F12FB2_FFDB9_Pos (9U) +#define CAN_F12FB2_FFDB9_Msk (0x1U << CAN_F12FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F12FB2_FFDB9 CAN_F12FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F12FB2_FFDB10_Pos (10U) +#define CAN_F12FB2_FFDB10_Msk (0x1U << CAN_F12FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F12FB2_FFDB10 CAN_F12FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F12FB2_FFDB11_Pos (11U) +#define CAN_F12FB2_FFDB11_Msk (0x1U << CAN_F12FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F12FB2_FFDB11 CAN_F12FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F12FB2_FFDB12_Pos (12U) +#define CAN_F12FB2_FFDB12_Msk (0x1U << CAN_F12FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F12FB2_FFDB12 CAN_F12FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F12FB2_FFDB13_Pos (13U) +#define CAN_F12FB2_FFDB13_Msk (0x1U << CAN_F12FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F12FB2_FFDB13 CAN_F12FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F12FB2_FFDB14_Pos (14U) +#define CAN_F12FB2_FFDB14_Msk (0x1U << CAN_F12FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F12FB2_FFDB14 CAN_F12FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F12FB2_FFDB15_Pos (15U) +#define CAN_F12FB2_FFDB15_Msk (0x1U << CAN_F12FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F12FB2_FFDB15 CAN_F12FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F12FB2_FFDB16_Pos (16U) +#define CAN_F12FB2_FFDB16_Msk (0x1U << CAN_F12FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F12FB2_FFDB16 CAN_F12FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F12FB2_FFDB17_Pos (17U) +#define CAN_F12FB2_FFDB17_Msk (0x1U << CAN_F12FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F12FB2_FFDB17 CAN_F12FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F12FB2_FFDB18_Pos (18U) +#define CAN_F12FB2_FFDB18_Msk (0x1U << CAN_F12FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F12FB2_FFDB18 CAN_F12FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F12FB2_FFDB19_Pos (19U) +#define CAN_F12FB2_FFDB19_Msk (0x1U << CAN_F12FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F12FB2_FFDB19 CAN_F12FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F12FB2_FFDB20_Pos (20U) +#define CAN_F12FB2_FFDB20_Msk (0x1U << CAN_F12FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F12FB2_FFDB20 CAN_F12FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F12FB2_FFDB21_Pos (21U) +#define CAN_F12FB2_FFDB21_Msk (0x1U << CAN_F12FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F12FB2_FFDB21 CAN_F12FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F12FB2_FFDB22_Pos (22U) +#define CAN_F12FB2_FFDB22_Msk (0x1U << CAN_F12FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F12FB2_FFDB22 CAN_F12FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F12FB2_FFDB23_Pos (23U) +#define CAN_F12FB2_FFDB23_Msk (0x1U << CAN_F12FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F12FB2_FFDB23 CAN_F12FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F12FB2_FFDB24_Pos (24U) +#define CAN_F12FB2_FFDB24_Msk (0x1U << CAN_F12FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F12FB2_FFDB24 CAN_F12FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F12FB2_FFDB25_Pos (25U) +#define CAN_F12FB2_FFDB25_Msk (0x1U << CAN_F12FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F12FB2_FFDB25 CAN_F12FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F12FB2_FFDB26_Pos (26U) +#define CAN_F12FB2_FFDB26_Msk (0x1U << CAN_F12FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F12FB2_FFDB26 CAN_F12FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F12FB2_FFDB27_Pos (27U) +#define CAN_F12FB2_FFDB27_Msk (0x1U << CAN_F12FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F12FB2_FFDB27 CAN_F12FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F12FB2_FFDB28_Pos (28U) +#define CAN_F12FB2_FFDB28_Msk (0x1U << CAN_F12FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F12FB2_FFDB28 CAN_F12FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F12FB2_FFDB29_Pos (29U) +#define CAN_F12FB2_FFDB29_Msk (0x1U << CAN_F12FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F12FB2_FFDB29 CAN_F12FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F12FB2_FFDB30_Pos (30U) +#define CAN_F12FB2_FFDB30_Msk (0x1U << CAN_F12FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F12FB2_FFDB30 CAN_F12FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F12FB2_FFDB31_Pos (31U) +#define CAN_F12FB2_FFDB31_Msk (0x1U << CAN_F12FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F12FB2_FFDB31 CAN_F12FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F13FB2 register ******************/ +#define CAN_F13FB2_FFDB0_Pos (0U) +#define CAN_F13FB2_FFDB0_Msk (0x1U << CAN_F13FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F13FB2_FFDB0 CAN_F13FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F13FB2_FFDB1_Pos (1U) +#define CAN_F13FB2_FFDB1_Msk (0x1U << CAN_F13FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F13FB2_FFDB1 CAN_F13FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F13FB2_FFDB2_Pos (2U) +#define CAN_F13FB2_FFDB2_Msk (0x1U << CAN_F13FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F13FB2_FFDB2 CAN_F13FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F13FB2_FFDB3_Pos (3U) +#define CAN_F13FB2_FFDB3_Msk (0x1U << CAN_F13FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F13FB2_FFDB3 CAN_F13FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F13FB2_FFDB4_Pos (4U) +#define CAN_F13FB2_FFDB4_Msk (0x1U << CAN_F13FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F13FB2_FFDB4 CAN_F13FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F13FB2_FFDB5_Pos (5U) +#define CAN_F13FB2_FFDB5_Msk (0x1U << CAN_F13FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F13FB2_FFDB5 CAN_F13FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F13FB2_FFDB6_Pos (6U) +#define CAN_F13FB2_FFDB6_Msk (0x1U << CAN_F13FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F13FB2_FFDB6 CAN_F13FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F13FB2_FFDB7_Pos (7U) +#define CAN_F13FB2_FFDB7_Msk (0x1U << CAN_F13FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F13FB2_FFDB7 CAN_F13FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F13FB2_FFDB8_Pos (8U) +#define CAN_F13FB2_FFDB8_Msk (0x1U << CAN_F13FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F13FB2_FFDB8 CAN_F13FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F13FB2_FFDB9_Pos (9U) +#define CAN_F13FB2_FFDB9_Msk (0x1U << CAN_F13FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F13FB2_FFDB9 CAN_F13FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F13FB2_FFDB10_Pos (10U) +#define CAN_F13FB2_FFDB10_Msk (0x1U << CAN_F13FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F13FB2_FFDB10 CAN_F13FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F13FB2_FFDB11_Pos (11U) +#define CAN_F13FB2_FFDB11_Msk (0x1U << CAN_F13FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F13FB2_FFDB11 CAN_F13FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F13FB2_FFDB12_Pos (12U) +#define CAN_F13FB2_FFDB12_Msk (0x1U << CAN_F13FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F13FB2_FFDB12 CAN_F13FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F13FB2_FFDB13_Pos (13U) +#define CAN_F13FB2_FFDB13_Msk (0x1U << CAN_F13FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F13FB2_FFDB13 CAN_F13FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F13FB2_FFDB14_Pos (14U) +#define CAN_F13FB2_FFDB14_Msk (0x1U << CAN_F13FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F13FB2_FFDB14 CAN_F13FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F13FB2_FFDB15_Pos (15U) +#define CAN_F13FB2_FFDB15_Msk (0x1U << CAN_F13FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F13FB2_FFDB15 CAN_F13FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F13FB2_FFDB16_Pos (16U) +#define CAN_F13FB2_FFDB16_Msk (0x1U << CAN_F13FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F13FB2_FFDB16 CAN_F13FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F13FB2_FFDB17_Pos (17U) +#define CAN_F13FB2_FFDB17_Msk (0x1U << CAN_F13FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F13FB2_FFDB17 CAN_F13FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F13FB2_FFDB18_Pos (18U) +#define CAN_F13FB2_FFDB18_Msk (0x1U << CAN_F13FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F13FB2_FFDB18 CAN_F13FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F13FB2_FFDB19_Pos (19U) +#define CAN_F13FB2_FFDB19_Msk (0x1U << CAN_F13FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F13FB2_FFDB19 CAN_F13FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F13FB2_FFDB20_Pos (20U) +#define CAN_F13FB2_FFDB20_Msk (0x1U << CAN_F13FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F13FB2_FFDB20 CAN_F13FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F13FB2_FFDB21_Pos (21U) +#define CAN_F13FB2_FFDB21_Msk (0x1U << CAN_F13FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F13FB2_FFDB21 CAN_F13FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F13FB2_FFDB22_Pos (22U) +#define CAN_F13FB2_FFDB22_Msk (0x1U << CAN_F13FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F13FB2_FFDB22 CAN_F13FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F13FB2_FFDB23_Pos (23U) +#define CAN_F13FB2_FFDB23_Msk (0x1U << CAN_F13FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F13FB2_FFDB23 CAN_F13FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F13FB2_FFDB24_Pos (24U) +#define CAN_F13FB2_FFDB24_Msk (0x1U << CAN_F13FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F13FB2_FFDB24 CAN_F13FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F13FB2_FFDB25_Pos (25U) +#define CAN_F13FB2_FFDB25_Msk (0x1U << CAN_F13FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F13FB2_FFDB25 CAN_F13FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F13FB2_FFDB26_Pos (26U) +#define CAN_F13FB2_FFDB26_Msk (0x1U << CAN_F13FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F13FB2_FFDB26 CAN_F13FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F13FB2_FFDB27_Pos (27U) +#define CAN_F13FB2_FFDB27_Msk (0x1U << CAN_F13FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F13FB2_FFDB27 CAN_F13FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F13FB2_FFDB28_Pos (28U) +#define CAN_F13FB2_FFDB28_Msk (0x1U << CAN_F13FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F13FB2_FFDB28 CAN_F13FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F13FB2_FFDB29_Pos (29U) +#define CAN_F13FB2_FFDB29_Msk (0x1U << CAN_F13FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F13FB2_FFDB29 CAN_F13FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F13FB2_FFDB30_Pos (30U) +#define CAN_F13FB2_FFDB30_Msk (0x1U << CAN_F13FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F13FB2_FFDB30 CAN_F13FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F13FB2_FFDB31_Pos (31U) +#define CAN_F13FB2_FFDB31_Msk (0x1U << CAN_F13FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F13FB2_FFDB31 CAN_F13FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/******************************************************************************/ +/* */ +/* HICK auto clock calibration (ACC) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for ACC_STS register ********************/ +#define ACC_STS_CALRDY_Pos (0U) +#define ACC_STS_CALRDY_Msk (0x1U << ACC_STS_CALRDY_Pos) /*!< 0x00000001 */ +#define ACC_STS_CALRDY ACC_STS_CALRDY_Msk /*!< Internal high-speed clock calibration ready */ +#define ACC_STS_RSLOST_Pos (1U) +#define ACC_STS_RSLOST_Msk (0x1U << ACC_STS_RSLOST_Pos) /*!< 0x00000002 */ +#define ACC_STS_RSLOST ACC_STS_RSLOST_Msk /*!< Reference signal lost */ + +/****************** Bit definition for ACC_CTRL1 register *******************/ +#define ACC_CTRL1_CALON_Pos (0U) +#define ACC_CTRL1_CALON_Msk (0x1U << ACC_CTRL1_CALON_Pos) /*!< 0x00000001 */ +#define ACC_CTRL1_CALON ACC_CTRL1_CALON_Msk /*!< Calibration on */ +#define ACC_CTRL1_ENTRIM_Pos (1U) +#define ACC_CTRL1_ENTRIM_Msk (0x1U << ACC_CTRL1_ENTRIM_Pos) /*!< 0x00000002 */ +#define ACC_CTRL1_ENTRIM ACC_CTRL1_ENTRIM_Msk /*!< Enable trim */ +#define ACC_CTRL1_EIEN_Pos (4U) +#define ACC_CTRL1_EIEN_Msk (0x1U << ACC_CTRL1_EIEN_Pos) /*!< 0x00000010 */ +#define ACC_CTRL1_EIEN ACC_CTRL1_EIEN_Msk /*!< RSLOST error interrupt enable */ +#define ACC_CTRL1_CALRDYIEN_Pos (5U) +#define ACC_CTRL1_CALRDYIEN_Msk (0x1U << ACC_CTRL1_CALRDYIEN_Pos) /*!< 0x00000020 */ +#define ACC_CTRL1_CALRDYIEN ACC_CTRL1_CALRDYIEN_Msk /*!< CALRDY interrupt enable */ +#define ACC_CTRL1_STEP_Pos (8U) +#define ACC_CTRL1_STEP_Msk (0xFU << ACC_CTRL1_STEP_Pos) /*!< 0x00000F00 */ +#define ACC_CTRL1_STEP ACC_CTRL1_STEP_Msk /*!< Calibrated step */ + +/****************** Bit definition for ACC_CTRL2 register *******************/ +#define ACC_CTRL2_HICKCAL_Pos (0U) +#define ACC_CTRL2_HICKCAL_Msk (0xFFU << ACC_CTRL2_HICKCAL_Pos) /*!< 0x000000FF */ +#define ACC_CTRL2_HICKCAL ACC_CTRL2_HICKCAL_Msk /*!< Internal high-speed auto clock calibration */ +#define ACC_CTRL2_HICKTRIM_Pos (8U) +#define ACC_CTRL2_HICKTRIM_Msk (0x3FU << ACC_CTRL2_HICKTRIM_Pos) /*!< 0x00003F00 */ +#define ACC_CTRL2_HICKTRIM ACC_CTRL2_HICKTRIM_Msk /*!< Internal high-speed auto clock trimming */ + +/******************* Bit definition for ACC_CP1 register ********************/ +#define ACC_CP1_C1_Pos (0U) +#define ACC_CP1_C1_Msk (0xFFFFU << ACC_CP1_C1_Pos) /*!< 0x0000FFFF */ +#define ACC_CP1_C1 ACC_CP1_C1_Msk /*!< Compare 1 */ + +/******************* Bit definition for ACC_CP2 register ********************/ +#define ACC_CP2_C2_Pos (0U) +#define ACC_CP2_C2_Msk (0xFFFFU << ACC_CP2_C2_Pos) /*!< 0x0000FFFF */ +#define ACC_CP2_C2 ACC_CP2_C2_Msk /*!< Compare 2 */ + +/******************* Bit definition for ACC_CP3 register ********************/ +#define ACC_CP3_C3_Pos (0U) +#define ACC_CP3_C3_Msk (0xFFFFU << ACC_CP3_C3_Pos) /*!< 0x0000FFFF */ +#define ACC_CP3_C3 ACC_CP3_C3_Msk /*!< Compare 3 */ + +/******************************************************************************/ +/* */ +/* Quad-SPI interface (QSPI) */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for QSPI_CMD_W0 register ******************/ +#define QSPI_CMD_W0_SPIADR_Pos (0U) +#define QSPI_CMD_W0_SPIADR_Msk (0xFFFFFFFFU << QSPI_CMD_W0_SPIADR_Pos) /*!< 0xFFFFFFFF */ +#define QSPI_CMD_W0_SPIADR QSPI_CMD_W0_SPIADR_Msk /*!< SPI Flash address */ + +/***************** Bit definition for QSPI_CMD_W1 register ******************/ +/*!< ADRLEN congiguration */ +#define QSPI_CMD_W1_ADRLEN_Pos (0U) +#define QSPI_CMD_W1_ADRLEN_Msk (0x7U << QSPI_CMD_W1_ADRLEN_Pos) /*!< 0x00000007 */ +#define QSPI_CMD_W1_ADRLEN QSPI_CMD_W1_ADRLEN_Msk /*!< ADRLEN[2:0] bits (SPI address length) */ +#define QSPI_CMD_W1_ADRLEN_0 (0x1U << QSPI_CMD_W1_ADRLEN_Pos) /*!< 0x00000001 */ +#define QSPI_CMD_W1_ADRLEN_1 (0x2U << QSPI_CMD_W1_ADRLEN_Pos) /*!< 0x00000002 */ +#define QSPI_CMD_W1_ADRLEN_2 (0x4U << QSPI_CMD_W1_ADRLEN_Pos) /*!< 0x00000004 */ + +#define QSPI_CMD_W1_ADRLEN_NOBYTE 0x00000000U /*!< No address state */ +#define QSPI_CMD_W1_ADRLEN_1BYTE 0x00000001U /*!< 1-byte address */ +#define QSPI_CMD_W1_ADRLEN_2BYTE 0x00000002U /*!< 2-byte address */ +#define QSPI_CMD_W1_ADRLEN_3BYTE 0x00000003U /*!< 3-byte address */ +#define QSPI_CMD_W1_ADRLEN_4BYTE 0x00000004U /*!< 4-byte address */ + +/*!< DUM2 congiguration */ +#define QSPI_CMD_W1_DUM2_Pos (16U) +#define QSPI_CMD_W1_DUM2_Msk (0xFFU << QSPI_CMD_W1_DUM2_Pos) /*!< 0x00FF0000 */ +#define QSPI_CMD_W1_DUM2 QSPI_CMD_W1_DUM2_Msk /*!< DUM2[7:0] bits (Second dummy state cycle) */ +#define QSPI_CMD_W1_DUM2_0 (0x01U << QSPI_CMD_W1_DUM2_Pos) /*!< 0x00010000 */ +#define QSPI_CMD_W1_DUM2_1 (0x02U << QSPI_CMD_W1_DUM2_Pos) /*!< 0x00020000 */ +#define QSPI_CMD_W1_DUM2_2 (0x04U << QSPI_CMD_W1_DUM2_Pos) /*!< 0x00040000 */ +#define QSPI_CMD_W1_DUM2_3 (0x08U << QSPI_CMD_W1_DUM2_Pos) /*!< 0x00080000 */ +#define QSPI_CMD_W1_DUM2_4 (0x10U << QSPI_CMD_W1_DUM2_Pos) /*!< 0x00100000 */ +#define QSPI_CMD_W1_DUM2_5 (0x20U << QSPI_CMD_W1_DUM2_Pos) /*!< 0x00200000 */ +#define QSPI_CMD_W1_DUM2_6 (0x40U << QSPI_CMD_W1_DUM2_Pos) /*!< 0x00400000 */ +#define QSPI_CMD_W1_DUM2_7 (0x80U << QSPI_CMD_W1_DUM2_Pos) /*!< 0x00800000 */ + +/*!< INSLEN congiguration */ +#define QSPI_CMD_W1_INSLEN_Pos (24U) +#define QSPI_CMD_W1_INSLEN_Msk (0x3U << QSPI_CMD_W1_INSLEN_Pos) /*!< 0x03000000 */ +#define QSPI_CMD_W1_INSLEN QSPI_CMD_W1_INSLEN_Msk /*!< INSLEN[1:0] bits (Instruction code length) */ +#define QSPI_CMD_W1_INSLEN_0 (0x1U << QSPI_CMD_W1_INSLEN_Pos) /*!< 0x01000000 */ +#define QSPI_CMD_W1_INSLEN_1 (0x2U << QSPI_CMD_W1_INSLEN_Pos) /*!< 0x02000000 */ + +#define QSPI_CMD_W1_INSLEN_NOINS 0x00000000U /*!< No instruction code */ +#define QSPI_CMD_W1_INSLEN_1INS 0x01000000U /*!< 1-byte instruction code */ +#define QSPI_CMD_W1_INSLEN_2INS 0x02000000U /*!< 2-byte instruction code (repeated instruction code) */ + +#define QSPI_CMD_W1_PEMEN_Pos (28U) +#define QSPI_CMD_W1_PEMEN_Msk (0x1U << QSPI_CMD_W1_PEMEN_Pos) /*!< 0x10000000 */ +#define QSPI_CMD_W1_PEMEN QSPI_CMD_W1_PEMEN_Msk /*!< Performance enhanced mode enable */ + +/***************** Bit definition for QSPI_CMD_W2 register ******************/ +#define QSPI_CMD_W2_DCNT_Pos (0U) +#define QSPI_CMD_W2_DCNT_Msk (0xFFFFFFFFU << QSPI_CMD_W2_DCNT_Pos) /*!< 0xFFFFFFFF */ +#define QSPI_CMD_W2_DCNT QSPI_CMD_W2_DCNT_Msk /*!< Read/Write data counter */ + +/***************** Bit definition for QSPI_CMD_W3 register ******************/ +#define QSPI_CMD_W3_WEN_Pos (1U) +#define QSPI_CMD_W3_WEN_Msk (0x1U << QSPI_CMD_W3_WEN_Pos) /*!< 0x00000002 */ +#define QSPI_CMD_W3_WEN QSPI_CMD_W3_WEN_Msk /*!< Write data enable */ +#define QSPI_CMD_W3_RSTSEN_Pos (2U) +#define QSPI_CMD_W3_RSTSEN_Msk (0x1U << QSPI_CMD_W3_RSTSEN_Pos) /*!< 0x00000004 */ +#define QSPI_CMD_W3_RSTSEN QSPI_CMD_W3_RSTSEN_Msk /*!< Read SPI status enable */ +#define QSPI_CMD_W3_RSTSC_Pos (3U) +#define QSPI_CMD_W3_RSTSC_Msk (0x1U << QSPI_CMD_W3_RSTSC_Pos) /*!< 0x00000008 */ +#define QSPI_CMD_W3_RSTSC QSPI_CMD_W3_RSTSC_Msk /*!< Read SPI status configuration */ + +/*!< OPMODE congiguration */ +#define QSPI_CMD_W3_OPMODE_Pos (5U) +#define QSPI_CMD_W3_OPMODE_Msk (0x7U << QSPI_CMD_W3_OPMODE_Pos) /*!< 0x000000E0 */ +#define QSPI_CMD_W3_OPMODE QSPI_CMD_W3_OPMODE_Msk /*!< OPMODE[2:0] bits (SPI Operation mode) */ +#define QSPI_CMD_W3_OPMODE_0 (0x1U << QSPI_CMD_W3_OPMODE_Pos) /*!< 0x00000020 */ +#define QSPI_CMD_W3_OPMODE_1 (0x2U << QSPI_CMD_W3_OPMODE_Pos) /*!< 0x00000040 */ +#define QSPI_CMD_W3_OPMODE_2 (0x4U << QSPI_CMD_W3_OPMODE_Pos) /*!< 0x00000080 */ + +#define QSPI_CMD_W3_OPMODE_SERIAL 0x00000000U /*!< Serial mode (1-1-1) */ +#define QSPI_CMD_W3_OPMODE_DUAL 0x00000020U /*!< Dual-wire mode (1-1-2) */ +#define QSPI_CMD_W3_OPMODE_QUAD 0x00000040U /*!< Quad mode (1-1-4) */ +#define QSPI_CMD_W3_OPMODE_DUALIO 0x00000060U /*!< Dual-wire I/O mode (1-2-2) */ +#define QSPI_CMD_W3_OPMODE_QUADIO 0x00000080U /*!< Quad I/O mode (1-4-4) */ +#define QSPI_CMD_W3_OPMODE_DPI 0x000000A0U /*!< DPI mode (2-2-2) */ +#define QSPI_CMD_W3_OPMODE_QPI 0x000000C0U /*!< QPI mode (4-4-4) */ + +#define QSPI_CMD_W3_PEMOPC_Pos (16U) +#define QSPI_CMD_W3_PEMOPC_Msk (0xFFU << QSPI_CMD_W3_PEMOPC_Pos) /*!< 0x00FF0000 */ +#define QSPI_CMD_W3_PEMOPC QSPI_CMD_W3_PEMOPC_Msk /*!< Performance enhanced mode operation code */ +#define QSPI_CMD_W3_INSC_Pos (24U) +#define QSPI_CMD_W3_INSC_Msk (0xFFU << QSPI_CMD_W3_INSC_Pos) /*!< 0xFF000000 */ +#define QSPI_CMD_W3_INSC QSPI_CMD_W3_INSC_Msk /*!< Instruction code */ + +/****************** Bit definition for QSPI_CTRL register *******************/ +/*!< CLKDIV congiguration */ +#define QSPI_CTRL_CLKDIV_Pos (0U) +#define QSPI_CTRL_CLKDIV_Msk (0x7U << QSPI_CTRL_CLKDIV_Pos) /*!< 0x00000007 */ +#define QSPI_CTRL_CLKDIV QSPI_CTRL_CLKDIV_Msk /*!< CLKDIV[2:0] bits (Clock divider) */ +#define QSPI_CTRL_CLKDIV_0 (0x1U << QSPI_CTRL_CLKDIV_Pos) /*!< 0x00000001 */ +#define QSPI_CTRL_CLKDIV_1 (0x2U << QSPI_CTRL_CLKDIV_Pos) /*!< 0x00000002 */ +#define QSPI_CTRL_CLKDIV_2 (0x4U << QSPI_CTRL_CLKDIV_Pos) /*!< 0x00000004 */ + +#define QSPI_CTRL_CLKDIV_DIV2 0x00000000U /*!< Clock is divided by 2 */ +#define QSPI_CTRL_CLKDIV_DIV4 0x00000001U /*!< Clock is divided by 4 */ +#define QSPI_CTRL_CLKDIV_DIV6 0x00000002U /*!< Clock is divided by 6 */ +#define QSPI_CTRL_CLKDIV_DIV8 0x00000003U /*!< Clock is divided by 8 */ +#define QSPI_CTRL_CLKDIV_DIV3 0x00000004U /*!< Clock is divided by 3 */ +#define QSPI_CTRL_CLKDIV_DIV5 0x00000005U /*!< Clock is divided by 5 */ +#define QSPI_CTRL_CLKDIV_DIV10 0x00000006U /*!< Clock is divided by 10 */ +#define QSPI_CTRL_CLKDIV_DIV12 0x00000007U /*!< Clock is divided by 12 */ + +#define QSPI_CTRL_SCKMODE_Pos (4U) +#define QSPI_CTRL_SCKMODE_Msk (0x1U << QSPI_CTRL_SCKMODE_Pos) /*!< 0x00000010 */ +#define QSPI_CTRL_SCKMODE QSPI_CTRL_SCKMODE_Msk /*!< SCK output mode */ +#define QSPI_CTRL_XIPIDLE_Pos (7U) +#define QSPI_CTRL_XIPIDLE_Msk (0x1U << QSPI_CTRL_XIPIDLE_Pos) /*!< 0x00000080 */ +#define QSPI_CTRL_XIPIDLE QSPI_CTRL_XIPIDLE_Msk /*!< XIP port idle status */ +#define QSPI_CTRL_ABORT_Pos (8U) +#define QSPI_CTRL_ABORT_Msk (0x1U << QSPI_CTRL_ABORT_Pos) /*!< 0x00000100 */ +#define QSPI_CTRL_ABORT QSPI_CTRL_ABORT_Msk /*!< Refresh all commands/FIFOs and reset state machine */ + +/*!< BUSY congiguration */ +#define QSPI_CTRL_BUSY_Pos (16U) +#define QSPI_CTRL_BUSY_Msk (0x7U << QSPI_CTRL_BUSY_Pos) /*!< 0x00070000 */ +#define QSPI_CTRL_BUSY QSPI_CTRL_BUSY_Msk /*!< BUSY[2:0] bits (Busy bit of SPI status) */ +#define QSPI_CTRL_BUSY_0 (0x1U << QSPI_CTRL_BUSY_Pos) /*!< 0x00010000 */ +#define QSPI_CTRL_BUSY_1 (0x2U << QSPI_CTRL_BUSY_Pos) /*!< 0x00020000 */ +#define QSPI_CTRL_BUSY_2 (0x4U << QSPI_CTRL_BUSY_Pos) /*!< 0x00040000 */ + +#define QSPI_CTRL_BUSY_BIT0 0x00000000U /*!< Bit 0 */ +#define QSPI_CTRL_BUSY_BIT1 0x00010000U /*!< Bit 1 */ +#define QSPI_CTRL_BUSY_BIT2 0x00020000U /*!< Bit 2 */ +#define QSPI_CTRL_BUSY_BIT3 0x00030000U /*!< Bit 3 */ +#define QSPI_CTRL_BUSY_BIT4 0x00040000U /*!< Bit 4 */ +#define QSPI_CTRL_BUSY_BIT5 0x00050000U /*!< Bit 5 */ +#define QSPI_CTRL_BUSY_BIT6 0x00060000U /*!< Bit 6 */ +#define QSPI_CTRL_BUSY_BIT7 0x00070000U /*!< Bit 7 */ + +#define QSPI_CTRL_XIPRCMDF_Pos (19U) +#define QSPI_CTRL_XIPRCMDF_Msk (0x1U << QSPI_CTRL_XIPRCMDF_Pos) /*!< 0x00080000 */ +#define QSPI_CTRL_XIPRCMDF QSPI_CTRL_XIPRCMDF_Msk /*!< XIP read command flush */ +#define QSPI_CTRL_XIPSEL_Pos (20U) +#define QSPI_CTRL_XIPSEL_Msk (0x1U << QSPI_CTRL_XIPSEL_Pos) /*!< 0x00100000 */ +#define QSPI_CTRL_XIPSEL QSPI_CTRL_XIPSEL_Msk /*!< XIP port selection */ +#define QSPI_CTRL_KEYEN_Pos (21U) +#define QSPI_CTRL_KEYEN_Msk (0x1U << QSPI_CTRL_KEYEN_Pos) /*!< 0x00200000 */ +#define QSPI_CTRL_KEYEN QSPI_CTRL_KEYEN_Msk /*!< SPI data encryption key enable */ + +/***************** Bit definition for QSPI_FIFOSTS register *****************/ +#define QSPI_FIFOSTS_TXFIFORDY_Pos (0U) +#define QSPI_FIFOSTS_TXFIFORDY_Msk (0x1U << QSPI_FIFOSTS_TXFIFORDY_Pos) /*!< 0x00000001 */ +#define QSPI_FIFOSTS_TXFIFORDY QSPI_FIFOSTS_TXFIFORDY_Msk /*!< TX FIFO ready status */ +#define QSPI_FIFOSTS_RXFIFORDY_Pos (1U) +#define QSPI_FIFOSTS_RXFIFORDY_Msk (0x1U << QSPI_FIFOSTS_RXFIFORDY_Pos) /*!< 0x00000002 */ +#define QSPI_FIFOSTS_RXFIFORDY QSPI_FIFOSTS_RXFIFORDY_Msk /*!< RX FIFO ready status */ + +/****************** Bit definition for QSPI_CTRL2 register ******************/ +#define QSPI_CTRL2_DMAEN_Pos (0U) +#define QSPI_CTRL2_DMAEN_Msk (0x1U << QSPI_CTRL2_DMAEN_Pos) /*!< 0x00000001 */ +#define QSPI_CTRL2_DMAEN QSPI_CTRL2_DMAEN_Msk /*!< DMA enable */ +#define QSPI_CTRL2_CMDIE_Pos (1U) +#define QSPI_CTRL2_CMDIE_Msk (0x1U << QSPI_CTRL2_CMDIE_Pos) /*!< 0x00000002 */ +#define QSPI_CTRL2_CMDIE QSPI_CTRL2_CMDIE_Msk /*!< Command complete Interrupt enable */ + +/*!< TXFIFO_THOD congiguration */ +#define QSPI_CTRL2_TXFIFO_THOD_Pos (8U) +#define QSPI_CTRL2_TXFIFO_THOD_Msk (0x3U << QSPI_CTRL2_TXFIFO_THOD_Pos) /*!< 0x00000300 */ +#define QSPI_CTRL2_TXFIFO_THOD QSPI_CTRL2_TXFIFO_THOD_Msk /*!< TXFIFO_THOD[1:0] bits (Program the level value to trigger TX FIFO threshold IRQ) */ +#define QSPI_CTRL2_TXFIFO_THOD_0 (0x1U << QSPI_CTRL2_TXFIFO_THOD_Pos) /*!< 0x00000100 */ +#define QSPI_CTRL2_TXFIFO_THOD_1 (0x2U << QSPI_CTRL2_TXFIFO_THOD_Pos) /*!< 0x00000200 */ + +#define QSPI_CTRL2_TXFIFO_THOD_8WORD 0x00000000U /*!< 8 WORD */ +#define QSPI_CTRL2_TXFIFO_THOD_16WORD 0x00000100U /*!< 16 WORD */ +#define QSPI_CTRL2_TXFIFO_THOD_24WORD 0x00000200U /*!< 24 WORD */ + +/*!< RXFIFO_THOD congiguration */ +#define QSPI_CTRL2_RXFIFO_THOD_Pos (12U) +#define QSPI_CTRL2_RXFIFO_THOD_Msk (0x3U << QSPI_CTRL2_RXFIFO_THOD_Pos) /*!< 0x00003000 */ +#define QSPI_CTRL2_RXFIFO_THOD QSPI_CTRL2_RXFIFO_THOD_Msk /*!< RXFIFO_THOD[1:0] bits (Program the level value to trigger RX FIFO threshold IRQ) */ +#define QSPI_CTRL2_RXFIFO_THOD_0 (0x1U << QSPI_CTRL2_RXFIFO_THOD_Pos) /*!< 0x00001000 */ +#define QSPI_CTRL2_RXFIFO_THOD_1 (0x2U << QSPI_CTRL2_RXFIFO_THOD_Pos) /*!< 0x00002000 */ + +#define QSPI_CTRL2_RXFIFO_THOD_8WORD 0x00000000U /*!< 8 WORD */ +#define QSPI_CTRL2_RXFIFO_THOD_16WORD 0x00001000U /*!< 16 WORD */ +#define QSPI_CTRL2_RXFIFO_THOD_24WORD 0x00002000U /*!< 24 WORD */ + +/***************** Bit definition for QSPI_CMDSTS register ******************/ +#define QSPI_CMDSTS_CMDSTS_Pos (0U) +#define QSPI_CMDSTS_CMDSTS_Msk (0x1U << QSPI_CMDSTS_CMDSTS_Pos) /*!< 0x00000001 */ +#define QSPI_CMDSTS_CMDSTS QSPI_CMDSTS_CMDSTS_Msk /*!< Command complete status */ + +/****************** Bit definition for QSPI_RSTS register *******************/ +#define QSPI_RSTS_SPISTS_Pos (0U) +#define QSPI_RSTS_SPISTS_Msk (0xFFU << QSPI_RSTS_SPISTS_Pos) /*!< 0x000000FF */ +#define QSPI_RSTS_SPISTS QSPI_RSTS_SPISTS_Msk /*!< SPI read status */ + +/****************** Bit definition for QSPI_FSIZE register ******************/ +#define QSPI_FSIZE_SPIFSIZE_Pos (0U) /*!< 0xFFFFFFFF */ +#define QSPI_FSIZE_SPIFSIZE_Msk (0xFFFFFFFFU << QSPI_FSIZE_SPIFSIZE_Pos) +#define QSPI_FSIZE_SPIFSIZE QSPI_FSIZE_SPIFSIZE_Msk /*!< SPI flash size */ + +/*************** Bit definition for QSPI_XIP_CMD_W0 register ****************/ +/*!< XIPR_DUM2 congiguration */ +#define QSPI_XIP_CMD_W0_XIPR_DUM2_Pos (0U) +#define QSPI_XIP_CMD_W0_XIPR_DUM2_Msk (0xFFU << QSPI_XIP_CMD_W0_XIPR_DUM2_Pos) /*!< 0x000000FF */ +#define QSPI_XIP_CMD_W0_XIPR_DUM2 QSPI_XIP_CMD_W0_XIPR_DUM2_Msk /*!< XIPR_DUM2[7:0] bits (XIP read second dummy cycle) */ +#define QSPI_XIP_CMD_W0_XIPR_DUM2_0 (0x01U << QSPI_XIP_CMD_W0_XIPR_DUM2_Pos) /*!< 0x00000001 */ +#define QSPI_XIP_CMD_W0_XIPR_DUM2_1 (0x02U << QSPI_XIP_CMD_W0_XIPR_DUM2_Pos) /*!< 0x00000002 */ +#define QSPI_XIP_CMD_W0_XIPR_DUM2_2 (0x04U << QSPI_XIP_CMD_W0_XIPR_DUM2_Pos) /*!< 0x00000004 */ +#define QSPI_XIP_CMD_W0_XIPR_DUM2_3 (0x08U << QSPI_XIP_CMD_W0_XIPR_DUM2_Pos) /*!< 0x00000008 */ +#define QSPI_XIP_CMD_W0_XIPR_DUM2_4 (0x10U << QSPI_XIP_CMD_W0_XIPR_DUM2_Pos) /*!< 0x00000010 */ +#define QSPI_XIP_CMD_W0_XIPR_DUM2_5 (0x20U << QSPI_XIP_CMD_W0_XIPR_DUM2_Pos) /*!< 0x00000020 */ +#define QSPI_XIP_CMD_W0_XIPR_DUM2_6 (0x40U << QSPI_XIP_CMD_W0_XIPR_DUM2_Pos) /*!< 0x00000040 */ +#define QSPI_XIP_CMD_W0_XIPR_DUM2_7 (0x80U << QSPI_XIP_CMD_W0_XIPR_DUM2_Pos) /*!< 0x00000080 */ + +/*!< XIPR_OPMODE congiguration */ +#define QSPI_XIP_CMD_W0_XIPR_OPMODE_Pos (8U) /*!< 0x00000700 */ +#define QSPI_XIP_CMD_W0_XIPR_OPMODE_Msk (0x7U << QSPI_XIP_CMD_W0_XIPR_OPMODE_Pos) +#define QSPI_XIP_CMD_W0_XIPR_OPMODE QSPI_XIP_CMD_W0_XIPR_OPMODE_Msk /*!< XIPR_OPMODE[2:0] bits (XIP read operation mode) */ +#define QSPI_XIP_CMD_W0_XIPR_OPMODE_0 (0x1U << QSPI_XIP_CMD_W0_XIPR_OPMODE_Pos) /*!< 0x00000100 */ +#define QSPI_XIP_CMD_W0_XIPR_OPMODE_1 (0x2U << QSPI_XIP_CMD_W0_XIPR_OPMODE_Pos) /*!< 0x00000200 */ +#define QSPI_XIP_CMD_W0_XIPR_OPMODE_2 (0x4U << QSPI_XIP_CMD_W0_XIPR_OPMODE_Pos) /*!< 0x00000400 */ + +#define QSPI_XIP_CMD_W0_XIPR_OPMODE_SERIAL 0x00000000U /*!< Serial mode (1-1-1) */ +#define QSPI_XIP_CMD_W0_XIPR_OPMODE_DUAL 0x00000100U /*!< Dual-wire mode (1-1-2) */ +#define QSPI_XIP_CMD_W0_XIPR_OPMODE_QUAD 0x00000200U /*!< Quad mode (1-1-4) */ +#define QSPI_XIP_CMD_W0_XIPR_OPMODE_DUALIO 0x00000300U /*!< Dual-wire I/O mode (1-2-2) */ +#define QSPI_XIP_CMD_W0_XIPR_OPMODE_QUADIO 0x00000400U /*!< Quad I/O mode (1-4-4) */ +#define QSPI_XIP_CMD_W0_XIPR_OPMODE_DPI 0x00000500U /*!< DPI mode (2-2-2) */ +#define QSPI_XIP_CMD_W0_XIPR_OPMODE_QPI 0x00000600U /*!< QPI mode (4-4-4) */ + +#define QSPI_XIP_CMD_W0_XIPR_ADRLEN_Pos (11U) /*!< 0x00000800 */ +#define QSPI_XIP_CMD_W0_XIPR_ADRLEN_Msk (0x1U << QSPI_XIP_CMD_W0_XIPR_ADRLEN_Pos) +#define QSPI_XIP_CMD_W0_XIPR_ADRLEN QSPI_XIP_CMD_W0_XIPR_ADRLEN_Msk /*!< XIP read address length */ +#define QSPI_XIP_CMD_W0_XIPR_INSC_Pos (12U) /*!< 0x000FF000 */ +#define QSPI_XIP_CMD_W0_XIPR_INSC_Msk (0xFFU << QSPI_XIP_CMD_W0_XIPR_INSC_Pos) +#define QSPI_XIP_CMD_W0_XIPR_INSC QSPI_XIP_CMD_W0_XIPR_INSC_Msk /*!< XIP read instruction code */ + +/*************** Bit definition for QSPI_XIP_CMD_W1 register ****************/ +/*!< XIPW_DUM2 congiguration */ +#define QSPI_XIP_CMD_W1_XIPW_DUM2_Pos (0U) +#define QSPI_XIP_CMD_W1_XIPW_DUM2_Msk (0xFFU << QSPI_XIP_CMD_W1_XIPW_DUM2_Pos) /*!< 0x000000FF */ +#define QSPI_XIP_CMD_W1_XIPW_DUM2 QSPI_XIP_CMD_W1_XIPW_DUM2_Msk /*!< XIPW_DUM2[7:0] bits (XIP write second dummy cycle) */ +#define QSPI_XIP_CMD_W1_XIPW_DUM2_0 (0x01U << QSPI_XIP_CMD_W1_XIPW_DUM2_Pos) /*!< 0x00000001 */ +#define QSPI_XIP_CMD_W1_XIPW_DUM2_1 (0x02U << QSPI_XIP_CMD_W1_XIPW_DUM2_Pos) /*!< 0x00000002 */ +#define QSPI_XIP_CMD_W1_XIPW_DUM2_2 (0x04U << QSPI_XIP_CMD_W1_XIPW_DUM2_Pos) /*!< 0x00000004 */ +#define QSPI_XIP_CMD_W1_XIPW_DUM2_3 (0x08U << QSPI_XIP_CMD_W1_XIPW_DUM2_Pos) /*!< 0x00000008 */ +#define QSPI_XIP_CMD_W1_XIPW_DUM2_4 (0x10U << QSPI_XIP_CMD_W1_XIPW_DUM2_Pos) /*!< 0x00000010 */ +#define QSPI_XIP_CMD_W1_XIPW_DUM2_5 (0x20U << QSPI_XIP_CMD_W1_XIPW_DUM2_Pos) /*!< 0x00000020 */ +#define QSPI_XIP_CMD_W1_XIPW_DUM2_6 (0x40U << QSPI_XIP_CMD_W1_XIPW_DUM2_Pos) /*!< 0x00000040 */ +#define QSPI_XIP_CMD_W1_XIPW_DUM2_7 (0x80U << QSPI_XIP_CMD_W1_XIPW_DUM2_Pos) /*!< 0x00000080 */ + +/*!< XIPW_OPMODE congiguration */ +#define QSPI_XIP_CMD_W1_XIPW_OPMODE_Pos (8U) /*!< 0x00000700 */ +#define QSPI_XIP_CMD_W1_XIPW_OPMODE_Msk (0x7U << QSPI_XIP_CMD_W1_XIPW_OPMODE_Pos) +#define QSPI_XIP_CMD_W1_XIPW_OPMODE QSPI_XIP_CMD_W1_XIPW_OPMODE_Msk /*!< XIPW_OPMODE[2:0] bits (XIP write operation mode) */ +#define QSPI_XIP_CMD_W1_XIPW_OPMODE_0 (0x1U << QSPI_XIP_CMD_W1_XIPW_OPMODE_Pos) /*!< 0x00000100 */ +#define QSPI_XIP_CMD_W1_XIPW_OPMODE_1 (0x2U << QSPI_XIP_CMD_W1_XIPW_OPMODE_Pos) /*!< 0x00000200 */ +#define QSPI_XIP_CMD_W1_XIPW_OPMODE_2 (0x4U << QSPI_XIP_CMD_W1_XIPW_OPMODE_Pos) /*!< 0x00000400 */ + +#define QSPI_XIP_CMD_W1_XIPW_OPMODE_SERIAL 0x00000000U /*!< Serial mode (1-1-1) */ +#define QSPI_XIP_CMD_W1_XIPW_OPMODE_DUAL 0x00000100U /*!< Dual-wire mode (1-1-2) */ +#define QSPI_XIP_CMD_W1_XIPW_OPMODE_QUAD 0x00000200U /*!< Quad mode (1-1-4) */ +#define QSPI_XIP_CMD_W1_XIPW_OPMODE_DUALIO 0x00000300U /*!< Dual-wire I/O mode (1-2-2) */ +#define QSPI_XIP_CMD_W1_XIPW_OPMODE_QUADIO 0x00000400U /*!< Quad I/O mode (1-4-4) */ +#define QSPI_XIP_CMD_W1_XIPW_OPMODE_DPI 0x00000500U /*!< DPI mode (2-2-2) */ +#define QSPI_XIP_CMD_W1_XIPW_OPMODE_QPI 0x00000600U /*!< QPI mode (4-4-4) */ + +#define QSPI_XIP_CMD_W1_XIPW_ADRLEN_Pos (11U) /*!< 0x00000800 */ +#define QSPI_XIP_CMD_W1_XIPW_ADRLEN_Msk (0x1U << QSPI_XIP_CMD_W1_XIPW_ADRLEN_Pos) +#define QSPI_XIP_CMD_W1_XIPW_ADRLEN QSPI_XIP_CMD_W1_XIPW_ADRLEN_Msk /*!< XIP write address length */ +#define QSPI_XIP_CMD_W1_XIPW_INSC_Pos (12U) /*!< 0x000FF000 */ +#define QSPI_XIP_CMD_W1_XIPW_INSC_Msk (0xFFU << QSPI_XIP_CMD_W1_XIPW_INSC_Pos) +#define QSPI_XIP_CMD_W1_XIPW_INSC QSPI_XIP_CMD_W1_XIPW_INSC_Msk /*!< XIP write instruction code */ + +/*************** Bit definition for QSPI_XIP_CMD_W2 register ****************/ +#define QSPI_XIP_CMD_W2_XIPR_DCNT_Pos (0U) /*!< 0x0000003F */ +#define QSPI_XIP_CMD_W2_XIPR_DCNT_Msk (0x3FU << QSPI_XIP_CMD_W2_XIPR_DCNT_Pos) +#define QSPI_XIP_CMD_W2_XIPR_DCNT QSPI_XIP_CMD_W2_XIPR_DCNT_Msk /*!< Indicates the time counter to judge maximum data count in mode D */ +#define QSPI_XIP_CMD_W2_XIPR_TCNT_Pos (8U) /*!< 0x00007F00 */ +#define QSPI_XIP_CMD_W2_XIPR_TCNT_Msk (0x7FU << QSPI_XIP_CMD_W2_XIPR_TCNT_Pos) +#define QSPI_XIP_CMD_W2_XIPR_TCNT QSPI_XIP_CMD_W2_XIPR_TCNT_Msk /*!< Indicates the time counter to judge time interval in mode T */ +#define QSPI_XIP_CMD_W2_XIPR_SEL_Pos (15U) +#define QSPI_XIP_CMD_W2_XIPR_SEL_Msk (0x1U << QSPI_XIP_CMD_W2_XIPR_SEL_Pos) /*!< 0x00008000 */ +#define QSPI_XIP_CMD_W2_XIPR_SEL QSPI_XIP_CMD_W2_XIPR_SEL_Msk /*!< XIP read mode select */ +#define QSPI_XIP_CMD_W2_XIPW_DCNT_Pos (16U) /*!< 0x003F0000 */ +#define QSPI_XIP_CMD_W2_XIPW_DCNT_Msk (0x3FU << QSPI_XIP_CMD_W2_XIPW_DCNT_Pos) +#define QSPI_XIP_CMD_W2_XIPW_DCNT QSPI_XIP_CMD_W2_XIPW_DCNT_Msk /*!< Indicates the time counter to judge maximum data count in mode D */ +#define QSPI_XIP_CMD_W2_XIPW_TCNT_Pos (24U) /*!< 0x7F000000 */ +#define QSPI_XIP_CMD_W2_XIPW_TCNT_Msk (0x7FU << QSPI_XIP_CMD_W2_XIPW_TCNT_Pos) +#define QSPI_XIP_CMD_W2_XIPW_TCNT QSPI_XIP_CMD_W2_XIPW_TCNT_Msk /*!< Indicates the time counter to judge time interval in mode T */ +#define QSPI_XIP_CMD_W2_XIPW_SEL_Pos (31U) +#define QSPI_XIP_CMD_W2_XIPW_SEL_Msk (0x1U << QSPI_XIP_CMD_W2_XIPW_SEL_Pos) /*!< 0x80000000 */ +#define QSPI_XIP_CMD_W2_XIPW_SEL QSPI_XIP_CMD_W2_XIPW_SEL_Msk /*!< XIP write mode select */ + +/*************** Bit definition for QSPI_XIP_CMD_W3 register ****************/ +#define QSPI_XIP_CMD_W3_BYPASSC_Pos (0U) +#define QSPI_XIP_CMD_W3_BYPASSC_Msk (0x1U << QSPI_XIP_CMD_W3_BYPASSC_Pos) /*!< 0x00000001 */ +#define QSPI_XIP_CMD_W3_BYPASSC QSPI_XIP_CMD_W3_BYPASSC_Msk /*!< Bypass cache function */ +#define QSPI_XIP_CMD_W3_CSTS_Pos (3U) +#define QSPI_XIP_CMD_W3_CSTS_Msk (0x1U << QSPI_XIP_CMD_W3_CSTS_Pos) /*!< 0x00000008 */ +#define QSPI_XIP_CMD_W3_CSTS QSPI_XIP_CMD_W3_CSTS_Msk /*!< Cache status */ + +/****************** Bit definition for QSPI_CTRL3 register ******************/ +#define QSPI_CTRL3_ISPC_Pos (8U) +#define QSPI_CTRL3_ISPC_Msk (0x1U << QSPI_CTRL3_ISPC_Pos) /*!< 0x00000100 */ +#define QSPI_CTRL3_ISPC QSPI_CTRL3_ISPC_Msk /*!< ISPC */ + +/******************* Bit definition for QSPI_REV register *******************/ +#define QSPI_REV_REV_Pos (0U) +#define QSPI_REV_REV_Msk (0xFFFFFFFFU << QSPI_REV_REV_Pos) /*!< 0xFFFFFFFF */ +#define QSPI_REV_REV QSPI_REV_REV_Msk /*!< Indicates IP version */ + +/******************* Bit definition for QSPI_DT register ********************/ +#define QSPI_DT_DT_Pos (0U) +#define QSPI_DT_DT_Msk (0xFFFFFFFFU << QSPI_DT_DT_Pos) /*!< 0xFFFFFFFF */ +#define QSPI_DT_DT QSPI_DT_DT_Msk /*!< Data port register */ + +/******************************************************************************/ +/* */ +/* Debug MCU (DEBUG) */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for DEBUG_IDCODE register *****************/ +/*!< PID congiguration */ +#define DEBUG_IDCODE_PID_Pos (0U) +#define DEBUG_IDCODE_PID_Msk (0xFFFFFFFFU << DEBUG_IDCODE_PID_Pos) /*!< 0xFFFFFFFF */ +#define DEBUG_IDCODE_PID DEBUG_IDCODE_PID_Msk /*!< PID[31:0] bits (PID information) */ +#define DEBUG_IDCODE_PID_0 (0x00000001U << DEBUG_IDCODE_PID_Pos) /*!< 0x00000001 */ +#define DEBUG_IDCODE_PID_1 (0x00000002U << DEBUG_IDCODE_PID_Pos) /*!< 0x00000002 */ +#define DEBUG_IDCODE_PID_2 (0x00000004U << DEBUG_IDCODE_PID_Pos) /*!< 0x00000004 */ +#define DEBUG_IDCODE_PID_3 (0x00000008U << DEBUG_IDCODE_PID_Pos) /*!< 0x00000008 */ +#define DEBUG_IDCODE_PID_4 (0x00000010U << DEBUG_IDCODE_PID_Pos) /*!< 0x00000010 */ +#define DEBUG_IDCODE_PID_5 (0x00000020U << DEBUG_IDCODE_PID_Pos) /*!< 0x00000020 */ +#define DEBUG_IDCODE_PID_6 (0x00000040U << DEBUG_IDCODE_PID_Pos) /*!< 0x00000040 */ +#define DEBUG_IDCODE_PID_7 (0x00000080U << DEBUG_IDCODE_PID_Pos) /*!< 0x00000080 */ +#define DEBUG_IDCODE_PID_8 (0x00000100U << DEBUG_IDCODE_PID_Pos) /*!< 0x00000100 */ +#define DEBUG_IDCODE_PID_9 (0x00000200U << DEBUG_IDCODE_PID_Pos) /*!< 0x00000200 */ +#define DEBUG_IDCODE_PID_10 (0x00000400U << DEBUG_IDCODE_PID_Pos) /*!< 0x00000400 */ +#define DEBUG_IDCODE_PID_11 (0x00000800U << DEBUG_IDCODE_PID_Pos) /*!< 0x00000800 */ +#define DEBUG_IDCODE_PID_12 (0x00001000U << DEBUG_IDCODE_PID_Pos) /*!< 0x00001000 */ +#define DEBUG_IDCODE_PID_13 (0x00002000U << DEBUG_IDCODE_PID_Pos) /*!< 0x00002000 */ +#define DEBUG_IDCODE_PID_14 (0x00004000U << DEBUG_IDCODE_PID_Pos) /*!< 0x00004000 */ +#define DEBUG_IDCODE_PID_15 (0x00008000U << DEBUG_IDCODE_PID_Pos) /*!< 0x00008000 */ +#define DEBUG_IDCODE_PID_16 (0x00010000U << DEBUG_IDCODE_PID_Pos) /*!< 0x00010000 */ +#define DEBUG_IDCODE_PID_17 (0x00020000U << DEBUG_IDCODE_PID_Pos) /*!< 0x00020000 */ +#define DEBUG_IDCODE_PID_18 (0x00040000U << DEBUG_IDCODE_PID_Pos) /*!< 0x00040000 */ +#define DEBUG_IDCODE_PID_19 (0x00080000U << DEBUG_IDCODE_PID_Pos) /*!< 0x00080000 */ +#define DEBUG_IDCODE_PID_20 (0x00100000U << DEBUG_IDCODE_PID_Pos) /*!< 0x00100000 */ +#define DEBUG_IDCODE_PID_21 (0x00200000U << DEBUG_IDCODE_PID_Pos) /*!< 0x00200000 */ +#define DEBUG_IDCODE_PID_22 (0x00400000U << DEBUG_IDCODE_PID_Pos) /*!< 0x00400000 */ +#define DEBUG_IDCODE_PID_23 (0x00800000U << DEBUG_IDCODE_PID_Pos) /*!< 0x00800000 */ +#define DEBUG_IDCODE_PID_24 (0x01000000U << DEBUG_IDCODE_PID_Pos) /*!< 0x01000000 */ +#define DEBUG_IDCODE_PID_25 (0x02000000U << DEBUG_IDCODE_PID_Pos) /*!< 0x02000000 */ +#define DEBUG_IDCODE_PID_26 (0x04000000U << DEBUG_IDCODE_PID_Pos) /*!< 0x04000000 */ +#define DEBUG_IDCODE_PID_27 (0x08000000U << DEBUG_IDCODE_PID_Pos) /*!< 0x08000000 */ +#define DEBUG_IDCODE_PID_28 (0x10000000U << DEBUG_IDCODE_PID_Pos) /*!< 0x10000000 */ +#define DEBUG_IDCODE_PID_29 (0x20000000U << DEBUG_IDCODE_PID_Pos) /*!< 0x20000000 */ +#define DEBUG_IDCODE_PID_30 (0x40000000U << DEBUG_IDCODE_PID_Pos) /*!< 0x40000000 */ +#define DEBUG_IDCODE_PID_31 (0x80000000U << DEBUG_IDCODE_PID_Pos) /*!< 0x80000000 */ + +/****************** Bit definition for DEBUG_CTRL register ******************/ +#define DEBUG_CTRL_SLEEP_DEBUG_Pos (0U) +#define DEBUG_CTRL_SLEEP_DEBUG_Msk (0x1U << DEBUG_CTRL_SLEEP_DEBUG_Pos) /*!< 0x00000001 */ +#define DEBUG_CTRL_SLEEP_DEBUG DEBUG_CTRL_SLEEP_DEBUG_Msk /*!< Debug Sleep mode control bit */ +#define DEBUG_CTRL_DEEPSLEEP_DEBUG_Pos (1U) /*!< 0x00000002 */ +#define DEBUG_CTRL_DEEPSLEEP_DEBUG_Msk (0x1U << DEBUG_CTRL_DEEPSLEEP_DEBUG_Pos) +#define DEBUG_CTRL_DEEPSLEEP_DEBUG DEBUG_CTRL_DEEPSLEEP_DEBUG_Msk /*!< Debug Deep sleep mode control bit */ +#define DEBUG_CTRL_STANDBY_DEBUG_Pos (2U) +#define DEBUG_CTRL_STANDBY_DEBUG_Msk (0x1U << DEBUG_CTRL_STANDBY_DEBUG_Pos) /*!< 0x00000004 */ +#define DEBUG_CTRL_STANDBY_DEBUG DEBUG_CTRL_STANDBY_DEBUG_Msk /*!< Debug Standby mode control bit */ + +/*************** Bit definition for DEBUG_APB1_PAUSE register ***************/ +#define DEBUG_APB1_PAUSE_TMR2_PAUSE_Pos (0U) /*!< 0x00000001 */ +#define DEBUG_APB1_PAUSE_TMR2_PAUSE_Msk (0x1U << DEBUG_APB1_PAUSE_TMR2_PAUSE_Pos) +#define DEBUG_APB1_PAUSE_TMR2_PAUSE DEBUG_APB1_PAUSE_TMR2_PAUSE_Msk /*!< TMR2 pause control bit */ +#define DEBUG_APB1_PAUSE_TMR3_PAUSE_Pos (1U) /*!< 0x00000002 */ +#define DEBUG_APB1_PAUSE_TMR3_PAUSE_Msk (0x1U << DEBUG_APB1_PAUSE_TMR3_PAUSE_Pos) +#define DEBUG_APB1_PAUSE_TMR3_PAUSE DEBUG_APB1_PAUSE_TMR3_PAUSE_Msk /*!< TMR3 pause control bit */ +#define DEBUG_APB1_PAUSE_TMR4_PAUSE_Pos (2U) /*!< 0x00000004 */ +#define DEBUG_APB1_PAUSE_TMR4_PAUSE_Msk (0x1U << DEBUG_APB1_PAUSE_TMR4_PAUSE_Pos) +#define DEBUG_APB1_PAUSE_TMR4_PAUSE DEBUG_APB1_PAUSE_TMR4_PAUSE_Msk /*!< TMR4 pause control bit */ +#define DEBUG_APB1_PAUSE_TMR6_PAUSE_Pos (4U) /*!< 0x00000010 */ +#define DEBUG_APB1_PAUSE_TMR6_PAUSE_Msk (0x1U << DEBUG_APB1_PAUSE_TMR6_PAUSE_Pos) +#define DEBUG_APB1_PAUSE_TMR6_PAUSE DEBUG_APB1_PAUSE_TMR6_PAUSE_Msk /*!< TMR6 pause control bit */ +#define DEBUG_APB1_PAUSE_TMR7_PAUSE_Pos (5U) /*!< 0x00000020 */ +#define DEBUG_APB1_PAUSE_TMR7_PAUSE_Msk (0x1U << DEBUG_APB1_PAUSE_TMR7_PAUSE_Pos) +#define DEBUG_APB1_PAUSE_TMR7_PAUSE DEBUG_APB1_PAUSE_TMR7_PAUSE_Msk /*!< TMR7 pause control bit */ +#define DEBUG_APB1_PAUSE_TMR13_PAUSE_Pos (7U) /*!< 0x00000080 */ +#define DEBUG_APB1_PAUSE_TMR13_PAUSE_Msk (0x1U << DEBUG_APB1_PAUSE_TMR13_PAUSE_Pos) +#define DEBUG_APB1_PAUSE_TMR13_PAUSE DEBUG_APB1_PAUSE_TMR13_PAUSE_Msk /*!< TMR13 pause control bit */ +#define DEBUG_APB1_PAUSE_TMR14_PAUSE_Pos (8U) /*!< 0x00000100 */ +#define DEBUG_APB1_PAUSE_TMR14_PAUSE_Msk (0x1U << DEBUG_APB1_PAUSE_TMR14_PAUSE_Pos) +#define DEBUG_APB1_PAUSE_TMR14_PAUSE DEBUG_APB1_PAUSE_TMR14_PAUSE_Msk /*!< TMR14 pause control bit */ +#define DEBUG_APB1_PAUSE_ERTC_PAUSE_Pos (10U) /*!< 0x00000400 */ +#define DEBUG_APB1_PAUSE_ERTC_PAUSE_Msk (0x1U << DEBUG_APB1_PAUSE_ERTC_PAUSE_Pos) +#define DEBUG_APB1_PAUSE_ERTC_PAUSE DEBUG_APB1_PAUSE_ERTC_PAUSE_Msk /*!< ERTC pause control bit */ +#define DEBUG_APB1_PAUSE_WWDT_PAUSE_Pos (11U) /*!< 0x00000800 */ +#define DEBUG_APB1_PAUSE_WWDT_PAUSE_Msk (0x1U << DEBUG_APB1_PAUSE_WWDT_PAUSE_Pos) +#define DEBUG_APB1_PAUSE_WWDT_PAUSE DEBUG_APB1_PAUSE_WWDT_PAUSE_Msk /*!< Window watchdog pause control bit */ +#define DEBUG_APB1_PAUSE_WDT_PAUSE_Pos (12U) /*!< 0x00001000 */ +#define DEBUG_APB1_PAUSE_WDT_PAUSE_Msk (0x1U << DEBUG_APB1_PAUSE_WDT_PAUSE_Pos) +#define DEBUG_APB1_PAUSE_WDT_PAUSE DEBUG_APB1_PAUSE_WDT_PAUSE_Msk /*!< Watchdog pause control bit */ +#define DEBUG_APB1_PAUSE_I2C1_SMBUS_TIMEOUT_Pos (24U) /*!< 0x01000000 */ +#define DEBUG_APB1_PAUSE_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DEBUG_APB1_PAUSE_I2C1_SMBUS_TIMEOUT_Pos) +#define DEBUG_APB1_PAUSE_I2C1_SMBUS_TIMEOUT DEBUG_APB1_PAUSE_I2C1_SMBUS_TIMEOUT_Msk /*!< I2C1 pause control bit */ +#define DEBUG_APB1_PAUSE_CAN1_PAUSE_Pos (25U) /*!< 0x02000000 */ +#define DEBUG_APB1_PAUSE_CAN1_PAUSE_Msk (0x1U << DEBUG_APB1_PAUSE_CAN1_PAUSE_Pos) +#define DEBUG_APB1_PAUSE_CAN1_PAUSE DEBUG_APB1_PAUSE_CAN1_PAUSE_Msk /*!< CAN1 pause control bit */ +#define DEBUG_APB1_PAUSE_I2C2_SMBUS_TIMEOUT_Pos (27U) /*!< 0x08000000 */ +#define DEBUG_APB1_PAUSE_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DEBUG_APB1_PAUSE_I2C2_SMBUS_TIMEOUT_Pos) +#define DEBUG_APB1_PAUSE_I2C2_SMBUS_TIMEOUT DEBUG_APB1_PAUSE_I2C2_SMBUS_TIMEOUT_Msk /*!< I2C2 pause control bit */ +#define DEBUG_APB1_PAUSE_I2C3_SMBUS_TIMEOUT_Pos (28U) /*!< 0x10000000 */ +#define DEBUG_APB1_PAUSE_I2C3_SMBUS_TIMEOUT_Msk (0x1U << DEBUG_APB1_PAUSE_I2C3_SMBUS_TIMEOUT_Pos) +#define DEBUG_APB1_PAUSE_I2C3_SMBUS_TIMEOUT DEBUG_APB1_PAUSE_I2C3_SMBUS_TIMEOUT_Msk /*!< I2C3 pause control bit */ + +/*************** Bit definition for DEBUG_APB2_PAUSE register ***************/ +#define DEBUG_APB2_PAUSE_TMR1_PAUSE_Pos (0U) /*!< 0x00000001 */ +#define DEBUG_APB2_PAUSE_TMR1_PAUSE_Msk (0x1U << DEBUG_APB2_PAUSE_TMR1_PAUSE_Pos) +#define DEBUG_APB2_PAUSE_TMR1_PAUSE DEBUG_APB2_PAUSE_TMR1_PAUSE_Msk /*!< TMR1 pause control bit */ +#define DEBUG_APB2_PAUSE_TMR9_PAUSE_Pos (16U) /*!< 0x00010000 */ +#define DEBUG_APB2_PAUSE_TMR9_PAUSE_Msk (0x1U << DEBUG_APB2_PAUSE_TMR9_PAUSE_Pos) +#define DEBUG_APB2_PAUSE_TMR9_PAUSE DEBUG_APB2_PAUSE_TMR9_PAUSE_Msk /*!< TMR9 pause control bit */ +#define DEBUG_APB2_PAUSE_TMR10_PAUSE_Pos (17U) /*!< 0x00020000 */ +#define DEBUG_APB2_PAUSE_TMR10_PAUSE_Msk (0x1U << DEBUG_APB2_PAUSE_TMR10_PAUSE_Pos) +#define DEBUG_APB2_PAUSE_TMR10_PAUSE DEBUG_APB2_PAUSE_TMR10_PAUSE_Msk /*!< TMR10 pause control bit */ +#define DEBUG_APB2_PAUSE_TMR11_PAUSE_Pos (18U) /*!< 0x00040000 */ +#define DEBUG_APB2_PAUSE_TMR11_PAUSE_Msk (0x1U << DEBUG_APB2_PAUSE_TMR11_PAUSE_Pos) +#define DEBUG_APB2_PAUSE_TMR11_PAUSE DEBUG_APB2_PAUSE_TMR11_PAUSE_Msk /*!< TMR11 pause control bit */ + +/***************** Bit definition for DEBUG_SER_ID register *****************/ +/*!< REV_ID congiguration */ +#define DEBUG_SER_ID_REV_ID_Pos (0U) +#define DEBUG_SER_ID_REV_ID_Msk (0x7U << DEBUG_SER_ID_REV_ID_Pos) /*!< 0x00000007 */ +#define DEBUG_SER_ID_REV_ID DEBUG_SER_ID_REV_ID_Msk /*!< REV_ID[2:0] bits (Revision ID) */ +#define DEBUG_SER_ID_REV_ID_0 (0x1U << DEBUG_SER_ID_REV_ID_Pos) /*!< 0x00000001 */ +#define DEBUG_SER_ID_REV_ID_1 (0x2U << DEBUG_SER_ID_REV_ID_Pos) /*!< 0x00000002 */ +#define DEBUG_SER_ID_REV_ID_2 (0x4U << DEBUG_SER_ID_REV_ID_Pos) /*!< 0x00000004 */ + +/*!< SER_ID congiguration */ +#define DEBUG_SER_ID_SER_ID_Pos (8U) +#define DEBUG_SER_ID_SER_ID_Msk (0xFFU << DEBUG_SER_ID_SER_ID_Pos) /*!< 0x0000FF00 */ +#define DEBUG_SER_ID_SER_ID DEBUG_SER_ID_SER_ID_Msk /*!< SER_ID[7:0] bits (Serial ID) */ +#define DEBUG_SER_ID_SER_ID_0 (0x01U << DEBUG_SER_ID_SER_ID_Pos) /*!< 0x00000100 */ +#define DEBUG_SER_ID_SER_ID_1 (0x02U << DEBUG_SER_ID_SER_ID_Pos) /*!< 0x00000200 */ +#define DEBUG_SER_ID_SER_ID_2 (0x04U << DEBUG_SER_ID_SER_ID_Pos) /*!< 0x00000400 */ +#define DEBUG_SER_ID_SER_ID_3 (0x08U << DEBUG_SER_ID_SER_ID_Pos) /*!< 0x00000800 */ +#define DEBUG_SER_ID_SER_ID_4 (0x10U << DEBUG_SER_ID_SER_ID_Pos) /*!< 0x00001000 */ +#define DEBUG_SER_ID_SER_ID_5 (0x20U << DEBUG_SER_ID_SER_ID_Pos) /*!< 0x00002000 */ +#define DEBUG_SER_ID_SER_ID_6 (0x40U << DEBUG_SER_ID_SER_ID_Pos) /*!< 0x00004000 */ +#define DEBUG_SER_ID_SER_ID_7 (0x80U << DEBUG_SER_ID_SER_ID_Pos) /*!< 0x00008000 */ + +/** + * @} +*/ + +/** + * @} +*/ + +/** @addtogroup Exported_macro + * @{ + */ + +#define CRM_HEXT_MIN 4000000U +#define CRM_HEXT_MAX 25000000U + +#define CRM_MAX_FREQUENCY 216000000U + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __AT32F402_405Cx_H */ + +/*********************** (C) COPYRIGHT Artery Technology *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ArteryTek/AT32F402_405/at32f402_405kx.h b/os/common/ext/CMSIS/ArteryTek/AT32F402_405/at32f402_405kx.h new file mode 100644 index 0000000000..8d54614553 --- /dev/null +++ b/os/common/ext/CMSIS/ArteryTek/AT32F402_405/at32f402_405kx.h @@ -0,0 +1,11136 @@ +/** + ************************************************************************** + * @file at32f402_405kx.h + * @author Artery Technology & HorrorTroll & Zhaqian & Maxjta + * @version v2.1.2 + * @date 20-Jan-2025 + * @brief AT32F402_405Kx header file. + * + ************************************************************************** + * Copyright notice & Disclaimer + * + * The software Board Support Package (BSP) that is made available to + * download from Artery official website is the copyrighted work of Artery. + * Artery authorizes customers to use, copy, and distribute the BSP + * software and its related documentation for the purpose of design and + * development in conjunction with Artery microcontrollers. Use of the + * software is governed by this copyright notice and the following disclaimer. + * + * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES, + * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS, + * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR + * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS, + * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. + * + ************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup at32f402_405kx + * @{ + */ + +#ifndef __AT32F402_405Kx_H +#define __AT32F402_405Kx_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** + * @brief CMSIS Device version number V2.1.2 + */ +#define __AT32F402_405_LIBRARY_VERSION_MAJOR (0x02) /*!< [31:24] major version */ +#define __AT32F402_405_LIBRARY_VERSION_MIDDLE (0x01) /*!< [23:16] middle version */ +#define __AT32F402_405_LIBRARY_VERSION_MINOR (0x02) /*!< [15:8] minor version */ +#define __AT32F402_405_LIBRARY_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __AT32F402_405_LIBRARY_VERSION ((__AT32F402_405_LIBRARY_VERSION_MAJOR << 24)\ + |(__AT32F402_405_LIBRARY_VERSION_MIDDLE << 16)\ + |(__AT32F402_405_LIBRARY_VERSION_MINOR << 8 )\ + |(__AT32F402_405_LIBRARY_VERSION_RC)) + +/** + * @} + */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ +#define __CM4_REV 0x0001U /*!< Core Revision r0p1 */ +#define __MPU_PRESENT 1U /*!< AT32 devices provide an MPU */ +#define __NVIC_PRIO_BITS 4U /*!< AT32 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /*!< AT32 devices provide an FPU */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief AT32F402_405Kx Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ + + /*!< Interrupt Number Definition */ +typedef enum +{ +/****** Cortex-M4 Processor Exceptions Numbers ***************************************************/ + Reset_IRQn = -15, /*!< 1 Reset Vector Interrupt */ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + +/****** AT32 specific Interrupt Numbers **********************************************************/ + WWDT_IRQn = 0, /*!< Window WatchDog Timer Interrupt */ + PVM_IRQn = 1, /*!< PVM Interrupt linked to EXINT16 */ + TAMPER_IRQn = 2, /*!< Tamper Interrupt linked to EXINT21 */ + ERTC_WKUP_IRQn = 3, /*!< ERTC Wake Up Interrupt linked to EXINT22 */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + CRM_IRQn = 5, /*!< CRM global Interrupt */ + EXINT0_IRQn = 6, /*!< EXINT Line 0 Interrupt */ + EXINT1_IRQn = 7, /*!< EXINT Line 1 Interrupt */ + EXINT2_IRQn = 8, /*!< EXINT Line 2 Interrupt */ + EXINT3_IRQn = 9, /*!< EXINT Line 3 Interrupt */ + EXINT4_IRQn = 10, /*!< EXINT Line 4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ + ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ + CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ + CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SE_IRQn = 22, /*!< CAN1 SE Interrupt */ + EXINT9_5_IRQn = 23, /*!< EXINT Line[9:5] Interrupts */ + TMR1_BRK_TMR9_IRQn = 24, /*!< TMR1 Break Interrupt and TMR9 global Interrupt */ + TMR1_OVF_TMR10_IRQn = 25, /*!< TMR1 Overflow Interrupt and TMR10 global Interrupt */ + TMR1_TRG_HALL_TMR11_IRQn = 26, /*!< TMR1 Trigger and Hall Interrupt and TMR11 global IRQ */ + TMR1_CH_IRQn = 27, /*!< TMR1 Channel Interrupt */ + TMR2_GLOBAL_IRQn = 28, /*!< TMR2 global Interrupt */ + TMR3_GLOBAL_IRQn = 29, /*!< TMR3 global Interrupt */ + TMR4_GLOBAL_IRQn = 30, /*!< TMR4 global Interrupt */ + I2C1_EVT_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ERR_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EVT_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ERR_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXINT15_10_IRQn = 40, /*!< EXINT Line[15:10] Interrupts */ + ERTCAlarm_IRQn = 41, /*!< ERTC Alarm Interrupt linked to EXINT17 */ + OTGFS_WKUP_IRQn = 42, /*!< OTGFS Wake Up Interrupt linked to EXINT18 */ + TMR13_GLOBAL_IRQn = 44, /*!< TMR13 global Interrupt */ + TMR14_GLOBAL_IRQn = 45, /*!< TMR14 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + USART4_IRQn = 52, /*!< USART4 global Interrupt */ + USART5_IRQn = 53, /*!< USART5 global Interrupt */ + TMR6_GLOBAL_IRQn = 54, /*!< TMR6 global Interrupt */ + TMR7_GLOBAL_IRQn = 55, /*!< TMR7 global Interrupt */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ + DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ + OTGFS_IRQn = 67, /*!< OTGFS global Interrupt */ + DMA2_Channel6_IRQn = 68, /*!< DMA2 Channel 6 global Interrupt */ + DMA2_Channel7_IRQn = 69, /*!< DMA2 Channel 7 global Interrupt */ + USART6_IRQn = 71, /*!< USART6 global Interrupt */ + I2C3_EVT_IRQn = 72, /*!< I2C3 Event Interrupt */ + I2C3_ERR_IRQn = 73, /*!< I2C3 Error Interrupt */ + OTGHS_EP1_OUT_IRQn = 74, /*!< OTGHS Endpoint 1 OUT Interrupt (F405 only) */ + OTGHS_EP1_IN_IRQn = 75, /*!< OTGHS Endpoint 1 IN Interrupt (F405 only) */ + OTGHS_WKUP_IRQn = 76, /*!< OTGHS Wake Up IRQ linked to EXINT20 (F405 only) */ + OTGHS_IRQn = 77, /*!< OTGHS global Interrupt (F405 only) */ + FPU_IRQn = 81, /*!< FPU exception Interrupt */ + UART7_IRQn = 82, /*!< UART7 global Interrupt */ + I2SF5_IRQn = 85, /*!< I2SF5 global Interrupt */ + QSPI1_IRQn = 92, /*!< QSPI1 global Interrupt */ + DMAMUX_IRQn = 94, /*!< DMAMUX overflow Interrupt */ + ACC_IRQn = 103, /*!< ACC global Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm4.h" +#include "system_at32f402_405.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief HICK Auto Clock Calibration + */ + +typedef struct +{ + __IO uint32_t STS; /*!< ACC Status register, Address offset: 0x00 */ + __IO uint32_t CTRL1; /*!< ACC Control register 1, Address offset: 0x04 */ + __IO uint32_t CTRL2; /*!< ACC Control register 2, Address offset: 0x08 */ + __IO uint32_t CP1; /*!< ACC Compare value 1, Address offset: 0x0C */ + __IO uint32_t CP2; /*!< ACC Compare value 2, Address offset: 0x10 */ + __IO uint32_t CP3; /*!< ACC Compare value 3, Address offset: 0x14 */ +} ACC_TypeDef; + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t STS; /*!< ADC status register, Address offset: 0x000 */ + __IO uint32_t CTRL1; /*!< ADC control register 1, Address offset: 0x004 */ + __IO uint32_t CTRL2; /*!< ADC control register 2, Address offset: 0x008 */ + __IO uint32_t SPT1; /*!< ADC sampling time register 1, Address offset: 0x00C */ + __IO uint32_t SPT2; /*!< ADC sampling time register 2, Address offset: 0x010 */ + __IO uint32_t PCDTO1; /*!< ADC preempted channel data offset reg 1, Address offset: 0x014 */ + __IO uint32_t PCDTO2; /*!< ADC preempted channel data offset reg 2, Address offset: 0x018 */ + __IO uint32_t PCDTO3; /*!< ADC preempted channel data offset reg 3, Address offset: 0x01C */ + __IO uint32_t PCDTO4; /*!< ADC preempted channel data offset reg 4, Address offset: 0x020 */ + __IO uint32_t VMHB; /*!< ADC voltage monitor high threshold register, Address offset: 0x024 */ + __IO uint32_t VMLB; /*!< ADC voltage monitor low threshold register, Address offset: 0x028 */ + __IO uint32_t OSQ1; /*!< ADC ordinary sequence register 1, Address offset: 0x02C */ + __IO uint32_t OSQ2; /*!< ADC ordinary sequence register 2, Address offset: 0x030 */ + __IO uint32_t OSQ3; /*!< ADC ordinary sequence register 3, Address offset: 0x034 */ + __IO uint32_t PSQ; /*!< ADC preempted sequence register, Address offset: 0x038 */ + __IO uint32_t PDT1; /*!< ADC preempted data register 1, Address offset: 0x03C */ + __IO uint32_t PDT2; /*!< ADC preempted data register 2, Address offset: 0x040 */ + __IO uint32_t PDT3; /*!< ADC preempted data register 3, Address offset: 0x044 */ + __IO uint32_t PDT4; /*!< ADC preempted data register 4, Address offset: 0x048 */ + __IO uint32_t ODT; /*!< ADC ordinary data register, Address offset: 0x04C */ + uint32_t RESERVED[12]; /*!< Reserved, Address offset: 0x050 ~ 0x07C */ + __IO uint32_t OVSP; /*!< ADC oversampling register, Address offset: 0x080 */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CCTRL; /*!< ADC common control register, Address offset: 0x304 */ +} ADC_Common_TypeDef; + +/** + * @brief Controller Area Network TX Mailbox Registers + */ + +typedef struct +{ + __IO uint32_t TMI; + __IO uint32_t TMC; + __IO uint32_t TMDTL; + __IO uint32_t TMDTH; +} CAN_TxMailBox_TypeDef; + +/** + * @brief Controller Area Network FIFO Mailbox Registers + */ + +typedef struct +{ + __IO uint32_t RFI; + __IO uint32_t RFC; + __IO uint32_t RFDTL; + __IO uint32_t RFDTH; +} CAN_FIFOMailBox_TypeDef; + +/** + * @brief Controller Area Network Filter Registers + */ + +typedef struct +{ + __IO uint32_t FFB1; + __IO uint32_t FFB2; +} CAN_FilterRegister_TypeDef; + +/** + * @brief Controller Area Network + */ + +typedef struct +{ + __IO uint32_t MCTRL; /*!< CAN master control register, Address offset: 0x000 */ + __IO uint32_t MSTS; /*!< CAN master status register, Address offset: 0x004 */ + __IO uint32_t TSTS; /*!< CAN transmit status register, Address offset: 0x008 */ + __IO uint32_t RF0; /*!< CAN receive FIFO 0 register, Address offset: 0x00C */ + __IO uint32_t RF1; /*!< CAN receive FIFO 1 register, Address offset: 0x010 */ + __IO uint32_t INTEN; /*!< CAN interrupt enable register, Address offset: 0x014 */ + __IO uint32_t ESTS; /*!< CAN error status register, Address offset: 0x018 */ + __IO uint32_t BTMG; /*!< CAN bit timing register, Address offset: 0x01C */ + uint32_t RESERVED0[88]; /*!< Reserved, Address offset: 0x020 ~ 0x17C */ + CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN TX Mailbox registers, Address offset: 0x180 ~ 0x1AC */ + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO Mailbox registers, Address offset: 0x1B0 ~ 0x1CC */ + uint32_t RESERVED1[12]; /*!< Reserved, Address offset: 0x1D0 ~ 0x1FC */ + __IO uint32_t FCTRL; /*!< CAN filter control register, Address offset: 0x200 */ + __IO uint32_t FMCFG; /*!< CAN filter mode configuration register, Address offset: 0x204 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x208 */ + __IO uint32_t FBWCFG; /*!< CAN filter bit width configuration register, Address offset: 0x20C */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x210 */ + __IO uint32_t FRF; /*!< CAN filter FIFO association register, Address offset: 0x214 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x218 */ + __IO uint32_t FACFG; /*!< CAN filter activation control register, Address offset: 0x21C */ + uint32_t RESERVED5[8]; /*!< Reserved, Address offset: 0x220 ~ 0x23C */ + CAN_FilterRegister_TypeDef sFilterRegister[14]; /*!< CAN filter registers, Address offset: 0x240 ~ 0x2AC */ +} CAN_TypeDef; + +/** + * @brief CRC Calculation Unit + */ + +typedef struct +{ + __IO uint32_t DT; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t CDT; /*!< CRC Common data register, Address offset: 0x04 */ + __IO uint32_t CTRL; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x0C */ + __IO uint32_t IDT; /*!< CRC Initialization register, Address offset: 0x10 */ + __IO uint32_t POLY; /*!< CRC Polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Clock and Reset Manage + */ + +typedef struct +{ + __IO uint32_t CTRL; /*!< CRM Clock control register, Address offset: 0x00 */ + __IO uint32_t PLLCFG; /*!< CRM PLL clock configuration register, Address offset: 0x04 */ + __IO uint32_t CFG; /*!< CRM Clock configuration register, Address offset: 0x08 */ + __IO uint32_t CLKINT; /*!< CRM Clock interrupt register, Address offset: 0x0C */ + __IO uint32_t AHBRST1; /*!< CRM AHB peripheral reset register 1, Address offset: 0x10 */ + __IO uint32_t AHBRST2; /*!< CRM AHB peripheral reset register 2, Address offset: 0x14 */ + __IO uint32_t AHBRST3; /*!< CRM AHB peripheral reset register 3, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t APB1RST; /*!< CRM APB1 peripheral reset register, Address offset: 0x20 */ + __IO uint32_t APB2RST; /*!< CRM APB2 peripheral reset register, Address offset: 0x24 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x28 ~ 0x2C */ + __IO uint32_t AHBEN1; /*!< CRM AHB peripheral clock enable register 1, Address offset: 0x30 */ + __IO uint32_t AHBEN2; /*!< CRM AHB peripheral clock enable register 2, Address offset: 0x34 */ + __IO uint32_t AHBEN3; /*!< CRM AHB peripheral clock enable register 3, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x3C */ + __IO uint32_t APB1EN; /*!< CRM APB1 peripheral clock enable register, Address offset: 0x40 */ + __IO uint32_t APB2EN; /*!< CRM APB2 peripheral clock enable register, Address offset: 0x44 */ + uint32_t RESERVED3[2]; /*!< Reserved, Address offset: 0x48 ~ 0x4C */ + __IO uint32_t AHBLPEN1; /*!< CRM AHB periph clk enable in LP mode reg 1, Address offset: 0x50 */ + __IO uint32_t AHBLPEN2; /*!< CRM AHB periph clk enable in LP mode reg 2, Address offset: 0x54 */ + __IO uint32_t AHBLPEN3; /*!< CRM AHB periph clk enable in LP mode reg 3, Address offset: 0x58 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x5C */ + __IO uint32_t APB1LPEN; /*!< CRM APB1 periph clk enable in LP mode reg, Address offset: 0x60 */ + __IO uint32_t APB2LPEN; /*!< CRM APB2 periph clk enable in LP mode reg, Address offset: 0x64 */ + uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x68 ~ 0x6C */ + __IO uint32_t BPDC; /*!< CRM Battery powered domain control register, Address offset: 0x70 */ + __IO uint32_t CTRLSTS; /*!< CRM Control/status register, Address offset: 0x74 */ + __IO uint32_t OTGHS; /*!< CRM OTGHS control register (F405 only), Address offset: 0x78 */ + uint32_t RESERVED6[9]; /*!< Reserved, Address offset: 0x7C ~ 0x9C */ + __IO uint32_t MISC1; /*!< CRM Additional register 1, Address offset: 0xA0 */ + __IO uint32_t MISC2; /*!< CRM Additional register 2, Address offset: 0xA4 */ +} CRM_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< DEBUG device ID, Address offset: 0xE004_2000 */ + __IO uint32_t CTRL; /*!< DEBUG control register, Address offset: 0xE004_2004 */ + __IO uint32_t APB1_PAUSE; /*!< DEBUG APB1 pause register, Address offset: 0xE004_2008 */ + __IO uint32_t APB2_PAUSE; /*!< DEBUG APB2 pause register, Address offset: 0xE004_200C */ + uint32_t RESERVED[4]; /*!< Reserved, Address offset: 0xE004_2010 ~ 0xE004_201C */ + __IO uint32_t SER_ID; /*!< DEBUG serial ID, Address offset: 0xE004_2020 */ +} DEBUG_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCTRL; /*!< DMA channel x configuration register, Address offset: 0x008 + 20 * (x - 1) (x = 1 ... 7) */ + __IO uint32_t CDTCNT; /*!< DMA channel x number of data register, Address offset: 0x00C + 20 * (x - 1) (x = 1 ... 7) */ + __IO uint32_t CPADDR; /*!< DMA channel x peripheral address register, Address offset: 0x010 + 20 * (x - 1) (x = 1 ... 7) */ + __IO uint32_t CMADDR; /*!< DMA channel x memory address register, Address offset: 0x014 + 20 * (x - 1) (x = 1 ... 7) */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t MUXCCTRL; /*!< DMA multiplexed channel x control register, Address offset: 0x104 + 4 * (x - 1) (x = 1 ... 7) */ +} DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t MUXSYNCSTS; /*!< DMA multiplexed channel sync status reg, Address offset: 0x130 */ + __IO uint32_t MUXSYNCCLR; /*!< DMA multiplexed channel irq flag clear reg, Address offset: 0x134 */ +} DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t MUXGCTRL; /*!< DMA multiplexed generator x control reg, Address offset: 0x120 + 4 * (x - 1) (x = 1 ... 4) */ +} DMAMUX_Generator_TypeDef; + +typedef struct +{ + __IO uint32_t MUXGSTS; /*!< DMA multiplexed generator irq status reg, Address offset: 0x138 */ + __IO uint32_t MUXGCLR; /*!< DMA mux generator irq flag clear register, Address offset: 0x13c */ +} DMAMUX_GeneratorStatus_TypeDef; + +typedef struct +{ + __IO uint32_t STS; /*!< DMA interrupt status register, Address offset: 0x000 */ + __IO uint32_t CLR; /*!< DMA interrupt flag clear register, Address offset: 0x004 */ + uint32_t RESERVED[62]; /*!< Reserved, Address offset: 0x008 ~ 0x0FC */ + __IO uint32_t MUXSEL; /*!< DMA multiplexed select register, Address offset: 0x100 */ +} DMA_TypeDef; + +/** + * @brief Enhanced Real-Time Clock + */ + +typedef struct +{ + __IO uint32_t TIME; /*!< ERTC time register, Address offset: 0x00 */ + __IO uint32_t DATE; /*!< ERTC date register, Address offset: 0x04 */ + __IO uint32_t CTRL; /*!< ERTC control register, Address offset: 0x08 */ + __IO uint32_t STS; /*!< ERTC initialization and status register, Address offset: 0x0C */ + __IO uint32_t DIV; /*!< ERTC divider register, Address offset: 0x10 */ + __IO uint32_t WAT; /*!< ERTC wakeup timer register, Address offset: 0x14 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x18 */ + __IO uint32_t ALA; /*!< ERTC alarm clock A register, Address offset: 0x1C */ + __IO uint32_t ALB; /*!< ERTC alarm clock B register, Address offset: 0x20 */ + __IO uint32_t WP; /*!< ERTC write protection register, Address offset: 0x24 */ + __IO uint32_t SBS; /*!< ERTC subsecond register, Address offset: 0x28 */ + __IO uint32_t TADJ; /*!< ERTC time adjustment register, Address offset: 0x2C */ + __IO uint32_t TSTM; /*!< ERTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDT; /*!< ERTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSBS; /*!< ERTC time stamp subsecond register, Address offset: 0x38 */ + __IO uint32_t SCAL; /*!< ERTC smooth calibration register, Address offset: 0x3C */ + __IO uint32_t TAMP; /*!< ERTC tamper configuration register, Address offset: 0x40 */ + __IO uint32_t ALASBS; /*!< ERTC alarm clock A subsecond register, Address offset: 0x44 */ + __IO uint32_t ALBSBS; /*!< ERTC alarm clock B subsecond register, Address offset: 0x48 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x4C */ + __IO uint32_t BPR1; /*!< ERTC battery powered domain data register 1, Address offset: 0x50 */ + __IO uint32_t BPR2; /*!< ERTC battery powered domain data register 2, Address offset: 0x54 */ + __IO uint32_t BPR3; /*!< ERTC battery powered domain data register 3, Address offset: 0x58 */ + __IO uint32_t BPR4; /*!< ERTC battery powered domain data register 4, Address offset: 0x5C */ + __IO uint32_t BPR5; /*!< ERTC battery powered domain data register 5, Address offset: 0x60 */ + __IO uint32_t BPR6; /*!< ERTC battery powered domain data register 6, Address offset: 0x64 */ + __IO uint32_t BPR7; /*!< ERTC battery powered domain data register 7, Address offset: 0x68 */ + __IO uint32_t BPR8; /*!< ERTC battery powered domain data register 8, Address offset: 0x6C */ + __IO uint32_t BPR9; /*!< ERTC battery powered domain data register 9, Address offset: 0x70 */ + __IO uint32_t BPR10; /*!< ERTC BAT powered domain data register 10, Address offset: 0x74 */ + __IO uint32_t BPR11; /*!< ERTC BAT powered domain data register 11, Address offset: 0x78 */ + __IO uint32_t BPR12; /*!< ERTC BAT powered domain data register 12, Address offset: 0x7C */ + __IO uint32_t BPR13; /*!< ERTC BAT powered domain data register 13, Address offset: 0x80 */ + __IO uint32_t BPR14; /*!< ERTC BAT powered domain data register 14, Address offset: 0x84 */ + __IO uint32_t BPR15; /*!< ERTC BAT powered domain data register 15, Address offset: 0x88 */ + __IO uint32_t BPR16; /*!< ERTC BAT powered domain data register 16, Address offset: 0x8C */ + __IO uint32_t BPR17; /*!< ERTC BAT powered domain data register 17, Address offset: 0x90 */ + __IO uint32_t BPR18; /*!< ERTC BAT powered domain data register 18, Address offset: 0x94 */ + __IO uint32_t BPR19; /*!< ERTC BAT powered domain data register 19, Address offset: 0x98 */ + __IO uint32_t BPR20; /*!< ERTC BAT powered domain data register 20, Address offset: 0x9C */ +} ERTC_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t INTEN; /*!< EXINT Interrupt enable register, Address offset: 0x00 */ + __IO uint32_t EVTEN; /*!< EXINT Event enable register, Address offset: 0x04 */ + __IO uint32_t POLCFG1; /*!< EXINT Polarity configuration register 1, Address offset: 0x08 */ + __IO uint32_t POLCFG2; /*!< EXINT Polarity configuration register 2, Address offset: 0x0C */ + __IO uint32_t SWTRG; /*!< EXINT Software trigger register, Address offset: 0x10 */ + __IO uint32_t INTSTS; /*!< EXINT Interrupt status register, Address offset: 0x14 */ +} EXINT_TypeDef; + +/** + * @brief Flash Memory Registers + */ + +typedef struct +{ + __IO uint32_t PSR; /*!< FLASH performance select register, Address offset: 0x00 */ + __IO uint32_t UNLOCK; /*!< FLASH unlock register, Address offset: 0x04 */ + __IO uint32_t USD_UNLOCK; /*!< FLASH user system data unlock register, Address offset: 0x08 */ + __IO uint32_t STS; /*!< FLASH status register, Address offset: 0x0C */ + __IO uint32_t CTRL; /*!< FLASH control register, Address offset: 0x10 */ + __IO uint32_t ADDR; /*!< FLASH address register, Address offset: 0x14 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x18 */ + __IO uint32_t USD; /*!< FLASH user system data register, Address offset: 0x1C */ + __IO uint32_t EPPS; /*!< FLASH erase/program protection status reg, Address offset: 0x20 */ + uint32_t RESERVED1[20]; /*!< Reserved, Address offset: 0x24 ~ 0x70 */ + __IO uint32_t SLIB_STS0; /*!< FLASH security library status register 0, Address offset: 0x74 */ + __IO uint32_t SLIB_STS1; /*!< FLASH security library status register 1, Address offset: 0x78 */ + __IO uint32_t SLIB_PWD_CLR; /*!< FLASH security library password clear reg, Address offset: 0x7C */ + __IO uint32_t SLIB_MISC_STS; /*!< FLASH security library additional stat reg, Address offset: 0x80 */ + __IO uint32_t CRC_ADDR; /*!< FLASH CRC address register, Address offset: 0x84 */ + __IO uint32_t CRC_CTRL; /*!< FLASH CRC control register, Address offset: 0x88 */ + __IO uint32_t CRC_CHKR; /*!< FLASH CRC check result register, Address offset: 0x8C */ + uint32_t RESERVED2[52]; /*!< Reserved, Address offset: 0x90 ~ 0x15C */ + __IO uint32_t SLIB_SET_PWD; /*!< FLASH security library password setting reg, Address offset: 0x160 */ + __IO uint32_t SLIB_SET_RANGE; /*!< FLASH security library address setting reg, Address offset: 0x164 */ + __IO uint32_t EM_SLIB_SET; /*!< FLASH extension mem security lib set reg, Address offset: 0x168 */ + __IO uint32_t BTM_MODE_SET; /*!< FLASH boot memory mode setting register, Address offset: 0x16C */ + __IO uint32_t SLIB_UNLOCK; /*!< FLASH security library unlock register, Address offset: 0x170 */ +} FLASH_TypeDef; + +/** + * @brief User System Data Registers + */ + +typedef struct +{ + __IO uint16_t FAP; /*!< USD memory access protection, Address offset: 0x1FFF_F800 */ + __IO uint16_t SSB; /*!< USD System configuration byte, Address offset: 0x1FFF_F802 */ + __IO uint16_t DATA0; /*!< USD User data 0, Address offset: 0x1FFF_F804 */ + __IO uint16_t DATA1; /*!< USD User data 1, Address offset: 0x1FFF_F806 */ + __IO uint16_t EPP0; /*!< USD erase/write protection byte 0, Address offset: 0x1FFF_F808 */ + __IO uint16_t EPP1; /*!< USD erase/write protection byte 1, Address offset: 0x1FFF_F80A */ + __IO uint16_t EPP2; /*!< USD erase/write protection byte 2, Address offset: 0x1FFF_F80C */ + __IO uint16_t EPP3; /*!< USD erase/write protection byte 3, Address offset: 0x1FFF_F80E */ + uint32_t RESERVED0[9]; /*!< Reserved, Address offset: 0x1FFF_F810 ~ 0x1FFF_F830 */ + __IO uint16_t QSPIKEY0; /*!< USD QSPI ciphertext access area + encryption key byte 0, Address offset: 0x1FFF_F834 */ + __IO uint16_t QSPIKEY1; /*!< USD QSPI ciphertext access area + encryption key byte 1, Address offset: 0x1FFF_F836 */ + __IO uint16_t QSPIKEY2; /*!< USD QSPI ciphertext access area + encryption key byte 2, Address offset: 0x1FFF_F838 */ + __IO uint16_t QSPIKEY3; /*!< USD QSPI ciphertext access area + encryption key byte 3, Address offset: 0x1FFF_F83A */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x1FFF_F83C ~ 0x1FFF_F848 */ + __IO uint16_t DATA[218]; /*!< USD User data 2 ~ 219, Address offset: 0x1FFF_F84C ~ 0x1FFF_F9FC */ +} USD_TypeDef; + +/** + * @brief General Purpose I/O or Multiplexed Function I/O + */ + +typedef struct +{ + __IO uint32_t CFGR; /*!< GPIO configuration register, Address offset: 0x00 */ + __IO uint32_t OMODE; /*!< GPIO output mode register, Address offset: 0x04 */ + __IO uint32_t ODRVR; /*!< GPIO drive capability register, Address offset: 0x08 */ + __IO uint32_t PULL; /*!< GPIO pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDT; /*!< GPIO input data register, Address offset: 0x10 */ + __IO uint32_t ODT; /*!< GPIO output data register, Address offset: 0x14 */ + __IO uint32_t SCR; /*!< GPIO set/clear register, Address offset: 0x18 */ + __IO uint32_t WPR; /*!< GPIO write protection register, Address offset: 0x1C */ + __IO uint32_t MUXL; /*!< GPIO multiplexed function low register, Address offset: 0x20 */ + __IO uint32_t MUXH; /*!< GPIO multiplexed function high register, Address offset: 0x24 */ + __IO uint32_t CLR; /*!< GPIO port bit clear register, Address offset: 0x28 */ + __IO uint32_t TOGR; /*!< GPIO port bit toggle register, Address offset: 0x2C */ + uint32_t RESERVED[3]; /*!< Reserved, Address offset: 0x30 ~ 0x38 */ + __IO uint32_t HDRV; /*!< GPIO huge current control register, Address offset: 0x3C */ + __IO uint32_t SRCTR; /*!< GPIO SRCTR register, Address offset: 0x40 */ +} GPIO_TypeDef; + +/** + * @brief Inter Integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CTRL1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CTRL2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OADDR1; /*!< I2C Own address register 1, Address offset: 0x08 */ + __IO uint32_t OADDR2; /*!< I2C Own address register 2, Address offset: 0x0C */ + __IO uint32_t CLKCTRL; /*!< I2C Clock control register, Address offset: 0x10 */ + __IO uint32_t TIMEOUT; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t STS; /*!< I2C Status register, Address offset: 0x18 */ + __IO uint32_t CLR; /*!< I2C Status clear flag register, Address offset: 0x1C */ + __IO uint32_t PEC; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDT; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDT; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CTRL; /*!< PWC Power control register, Address offset: 0x00 */ + __IO uint32_t CTRLSTS; /*!< PWC Power control/status register, Address offset: 0x04 */ + uint32_t RESERVED[2]; /*!< Reserved, Address offset: 0x08 ~ 0x0C */ + __IO uint32_t LDOOV; /*!< PWC LDO output voltage select register, Address offset: 0x10 */ +} PWC_TypeDef; + +/** + * @brief Quad-SPI Interface + */ + +typedef struct +{ + __IO uint32_t CMD_W0; /*!< QSPI Command word 0 register, Address offset: 0x00 */ + __IO uint32_t CMD_W1; /*!< QSPI Command word 1 register, Address offset: 0x04 */ + __IO uint32_t CMD_W2; /*!< QSPI Command word 2 register, Address offset: 0x08 */ + __IO uint32_t CMD_W3; /*!< QSPI Command word 3 register, Address offset: 0x0C */ + __IO uint32_t CTRL; /*!< QSPI Control register, Address offset: 0x10 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t FIFOSTS; /*!< QSPI FIFO status register, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t CTRL2; /*!< QSPI Control register 2, Address offset: 0x20 */ + __IO uint32_t CMDSTS; /*!< QSPI Command status register, Address offset: 0x24 */ + __IO uint32_t RSTS; /*!< QSPI Read status register, Address offset: 0x28 */ + __IO uint32_t FSIZE; /*!< QSPI Flash size register, Address offset: 0x2C */ + __IO uint32_t XIP_CMD_W0; /*!< QSPI XIP command word 0 register, Address offset: 0x30 */ + __IO uint32_t XIP_CMD_W1; /*!< QSPI XIP command word 1 register, Address offset: 0x34 */ + __IO uint32_t XIP_CMD_W2; /*!< QSPI XIP command word 2 register, Address offset: 0x38 */ + __IO uint32_t XIP_CMD_W3; /*!< QSPI XIP command word 3 register, Address offset: 0x3C */ + __IO uint32_t CTRL3; /*!< QSPI Control register 3, Address offset: 0x40 */ + uint32_t RESERVED2[3]; /*!< Reserved, Address offset: 0x44 ~ 0x4C */ + __IO uint32_t REV; /*!< QSPI Revision register, Address offset: 0x50 */ + uint32_t RESERVED3[43]; /*!< Reserved, Address offset: 0x54 ~ 0xFC */ + __IO uint8_t DT_U8; /*!< QSPI Data port (8-bit) register, Address offset: 0x100 */ + __IO uint16_t DT_U16; /*!< QSPI Data port (16-bit) register, Address offset: 0x100 */ + __IO uint32_t DT; /*!< QSPI Data port register, Address offset: 0x100 */ +} QSPI_TypeDef; + +/** + * @brief System Configuration Controller + */ + +typedef struct +{ + __IO uint32_t CFG1; /*!< SCFG configuration register 1, Address offset: 0x00 */ + __IO uint32_t CFG2; /*!< SCFG configuration register 2, Address offset: 0x04 */ + __IO uint32_t EXINTC[4]; /*!< SCFG external interrupt config register x, Address offset: 0x08 ~ 0x14 */ + uint32_t RESERVED[5]; /*!< Reserved, Address offset: 0x18 ~ 0x28 */ + __IO uint32_t UHDRV; /*!< SCFG ultra high source/sinking strength reg, Address offset: 0x2C */ +} SCFG_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CTRL1; /*!< SPI control register 1, Address offset: 0x00 */ + __IO uint32_t CTRL2; /*!< SPI control register 2, Address offset: 0x04 */ + __IO uint32_t STS; /*!< SPI status register, Address offset: 0x08 */ + __IO uint32_t DT; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CPOLY; /*!< SPI CRC register, Address offset: 0x10 */ + __IO uint32_t RCRC; /*!< SPI receive CRC register, Address offset: 0x14 */ + __IO uint32_t TCRC; /*!< SPI transmit CRC register, Address offset: 0x18 */ + __IO uint32_t I2SCTRL; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + __IO uint32_t I2SCLKP; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ + uint32_t RESERVED[3]; /*!< Reserved, Address offset: 0x24 ~ 0x2C */ + __IO uint32_t MISC1; /*!< SPI_I2SF5 additional register, Address offset: 0x30 */ +} SPI_TypeDef; + +/** + * @brief TMR Timers + */ + +typedef struct +{ + __IO uint32_t CTRL1; /*!< TMR control register 1, Address offset: 0x00 */ + __IO uint32_t CTRL2; /*!< TMR control register 2, Address offset: 0x04 */ + __IO uint32_t STCTRL; /*!< TMR slave timer control register, Address offset: 0x08 */ + __IO uint32_t IDEN; /*!< TMR DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t ISTS; /*!< TMR interrupt status register, Address offset: 0x10 */ + __IO uint32_t SWEVT; /*!< TMR software event register, Address offset: 0x14 */ + __IO uint32_t CM1; /*!< TMR channel mode register 1, Address offset: 0x18 */ + __IO uint32_t CM2; /*!< TMR channel mode register 2, Address offset: 0x1C */ + __IO uint32_t CCTRL; /*!< TMR channel control register, Address offset: 0x20 */ + __IO uint32_t CVAL; /*!< TMR counter value register, Address offset: 0x24 */ + __IO uint32_t DIV; /*!< TMR division value register, Address offset: 0x28 */ + __IO uint32_t PR; /*!< TMR period register, Address offset: 0x2C */ + __IO uint32_t RPR; /*!< TMR repetition period register, Address offset: 0x30 */ + __IO uint32_t C1DT; /*!< TMR channel 1 data register, Address offset: 0x34 */ + __IO uint32_t C2DT; /*!< TMR channel 2 data register, Address offset: 0x38 */ + __IO uint32_t C3DT; /*!< TMR channel 3 data register, Address offset: 0x3C */ + __IO uint32_t C4DT; /*!< TMR channel 4 data register, Address offset: 0x40 */ + __IO uint32_t BRK; /*!< TMR break register, Address offset: 0x44 */ + __IO uint32_t DMACTRL; /*!< TMR DMA control register, Address offset: 0x48 */ + __IO uint32_t DMADT; /*!< TMR DMA data register, Address offset: 0x4C */ + __IO uint32_t RMP; /*!< TMR channel input remap register, Address offset: 0x50 */ +} TMR_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint32_t STS; /*!< USART status register, Address offset: 0x00 */ + __IO uint32_t DT; /*!< USART data register, Address offset: 0x04 */ + __IO uint32_t BAUDR; /*!< USART baud rate register, Address offset: 0x08 */ + __IO uint32_t CTRL1; /*!< USART control register 1, Address offset: 0x0C */ + __IO uint32_t CTRL2; /*!< USART control register 2, Address offset: 0x10 */ + __IO uint32_t CTRL3; /*!< USART control register 3, Address offset: 0x14 */ + __IO uint32_t GDIV; /*!< USART guard time and divider register, Address offset: 0x18 */ + __IO uint32_t RTOV; /*!< USART receiver timeout detection register, Address offset: 0x1C */ + __IO uint32_t IFC; /*!< USART interrupt flag clear register, Address offset: 0x20 */ +} USART_TypeDef; + +/** + * @brief WATCHDOG Timer + */ + +typedef struct +{ + __IO uint32_t CMD; /*!< WDT Command register, Address offset: 0x00 */ + __IO uint32_t DIV; /*!< WDT Divider register, Address offset: 0x04 */ + __IO uint32_t RLD; /*!< WDT Reload register, Address offset: 0x08 */ + __IO uint32_t STS; /*!< WDT Status register, Address offset: 0x0C */ + __IO uint32_t WIN; /*!< WDT Window register, Address offset: 0x10 */ +} WDT_TypeDef; + +/** + * @brief Window WATCHDOG Timer + */ + +typedef struct +{ + __IO uint32_t CTRL; /*!< WWDT Control register, Address offset: 0x00 */ + __IO uint32_t CFG; /*!< WWDT Configuration register, Address offset: 0x04 */ + __IO uint32_t STS; /*!< WWDT Status register, Address offset: 0x08 */ +} WWDT_TypeDef; + +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ + +#define FLASH_BASE 0x08000000U /*!< FLASH base address in the alias region */ +#define FLASH_BANK1_END 0x0803FFFFU /*!< FLASH end address of bank 1 */ +#define QSPI1_BASE 0x90000000U /*!< QSPI1 base address */ +#define SRAM_BASE 0x20000000U /*!< SRAM base address in the alias region */ +#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */ + +#define SRAM_BB_BASE 0x22000000U /*!< SRAM base address in the bit-band region */ +#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE /*!< APB1 base address */ +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U) /*!< APB2 base address */ +#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000U) /*!< AHB base address */ + +#define TMR2_BASE (APB1PERIPH_BASE + 0x00000000U) /*!< TMR2 base address */ +#define TMR3_BASE (APB1PERIPH_BASE + 0x00000400U) /*!< TMR3 base address */ +#define TMR4_BASE (APB1PERIPH_BASE + 0x00000800U) /*!< TMR4 base address */ +#define TMR6_BASE (APB1PERIPH_BASE + 0x00001000U) /*!< TMR6 base address */ +#define TMR7_BASE (APB1PERIPH_BASE + 0x00001400U) /*!< TMR7 base address */ +#define TMR13_BASE (APB1PERIPH_BASE + 0x00001C00U) /*!< TMR13 base address */ +#define TMR14_BASE (APB1PERIPH_BASE + 0x00002000U) /*!< TMR14 base address */ +#define ERTC_BASE (APB1PERIPH_BASE + 0x00002800U) /*!< ERTC base address */ +#define WWDT_BASE (APB1PERIPH_BASE + 0x00002C00U) /*!< WWDT base address */ +#define WDT_BASE (APB1PERIPH_BASE + 0x00003000U) /*!< WDT base address */ +#define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00U) /*!< SPI3 base address */ +#define USART2_BASE (APB1PERIPH_BASE + 0x00004400U) /*!< USART2 base address */ +#define USART3_BASE (APB1PERIPH_BASE + 0x00004800U) /*!< USART3 base address */ +#define USART4_BASE (APB1PERIPH_BASE + 0x00004C00U) /*!< USART4 base address */ +#define USART5_BASE (APB1PERIPH_BASE + 0x00005000U) /*!< USART5 base address */ +#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400U) /*!< I2C1 base address */ +#define I2C2_BASE (APB1PERIPH_BASE + 0x00005800U) /*!< I2C2 base address */ +#define I2C3_BASE (APB1PERIPH_BASE + 0x00005C00U) /*!< I2C3 base address */ +#define CAN1_BASE (APB1PERIPH_BASE + 0x00006400U) /*!< CAN1 base address */ +#define PWC_BASE (APB1PERIPH_BASE + 0x00007000U) /*!< PWC base address */ +#define UART7_BASE (APB1PERIPH_BASE + 0x00007800U) /*!< UART7 base address */ + +#define TMR1_BASE (APB2PERIPH_BASE + 0x00000000U) /*!< TMR1 base address */ +#define USART1_BASE (APB2PERIPH_BASE + 0x00001000U) /*!< USART1 base address */ +#define USART6_BASE (APB2PERIPH_BASE + 0x00001400U) /*!< USART6 base address */ + +#define ADC1_BASE (APB2PERIPH_BASE + 0x00002000U) /*!< ADC1 base address */ +#define ADC_Common_BASE (APB2PERIPH_BASE + 0x00002300U) /*!< ADC Common base address */ + +#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000U) /*!< SPI1 base address */ +#define SCFG_BASE (APB2PERIPH_BASE + 0x00003800U) /*!< SCFG base address */ +#define EXINT_BASE (APB2PERIPH_BASE + 0x00003C00U) /*!< EXINT base address */ +#define TMR9_BASE (APB2PERIPH_BASE + 0x00004000U) /*!< TMR9 base address */ +#define TMR10_BASE (APB2PERIPH_BASE + 0x00004400U) /*!< TMR10 base address */ +#define TMR11_BASE (APB2PERIPH_BASE + 0x00004800U) /*!< TMR11 base address */ +#define I2SF5_BASE (APB2PERIPH_BASE + 0x00005000U) /*!< I2SF5 base address */ +#define ACC_BASE (APB2PERIPH_BASE + 0x00007400U) /*!< ACC base address */ + +#define GPIOA_BASE (AHBPERIPH_BASE + 0x00000000U) /*!< GPIOA base address */ +#define GPIOB_BASE (AHBPERIPH_BASE + 0x00000400U) /*!< GPIOB base address */ +#define GPIOC_BASE (AHBPERIPH_BASE + 0x00000800U) /*!< GPIOC base address */ +#define GPIOD_BASE (AHBPERIPH_BASE + 0x00000C00U) /*!< GPIOD base address */ +#define GPIOF_BASE (AHBPERIPH_BASE + 0x00001400U) /*!< GPIOF base address */ +#define CRC_BASE (AHBPERIPH_BASE + 0x00003000U) /*!< CRC base address */ +#define CRM_BASE (AHBPERIPH_BASE + 0x00003800U) /*!< CRM base address */ + +#define DMA1_BASE (AHBPERIPH_BASE + 0x00006000U) /*!< DMA1 base address */ +#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x00006008U) /*!< DMA1 Channel 1 base address */ +#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x0000601CU) /*!< DMA1 Channel 2 base address */ +#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x00006030U) /*!< DMA1 Channel 3 base address */ +#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x00006044U) /*!< DMA1 Channel 4 base address */ +#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x00006058U) /*!< DMA1 Channel 5 base address */ +#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x0000606CU) /*!< DMA1 Channel 6 base address */ +#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x00006080U) /*!< DMA1 Channel 7 base address */ + +#define DMA1MUX_BASE (AHBPERIPH_BASE + 0x00006104U) /*!< DMA1 Multiplexed base address */ +#define DMA1MUX_Channel1_BASE (DMA1MUX_BASE) /*!< DMA1 Multiplexed Channel 1 base address */ +#define DMA1MUX_Channel2_BASE (AHBPERIPH_BASE + 0x00006108U) /*!< DMA1 Multiplexed Channel 2 base address */ +#define DMA1MUX_Channel3_BASE (AHBPERIPH_BASE + 0x0000610CU) /*!< DMA1 Multiplexed Channel 3 base address */ +#define DMA1MUX_Channel4_BASE (AHBPERIPH_BASE + 0x00006110U) /*!< DMA1 Multiplexed Channel 4 base address */ +#define DMA1MUX_Channel5_BASE (AHBPERIPH_BASE + 0x00006114U) /*!< DMA1 Multiplexed Channel 5 base address */ +#define DMA1MUX_Channel6_BASE (AHBPERIPH_BASE + 0x00006118U) /*!< DMA1 Multiplexed Channel 6 base address */ +#define DMA1MUX_Channel7_BASE (AHBPERIPH_BASE + 0x0000611CU) /*!< DMA1 Multiplexed Channel 7 base address */ +#define DMA1MUX_Generator1_BASE (AHBPERIPH_BASE + 0x00006120U) /*!< DMA1 Multiplexed Generator 1 base address */ +#define DMA1MUX_Generator2_BASE (AHBPERIPH_BASE + 0x00006124U) /*!< DMA1 Multiplexed Generator 2 base address */ +#define DMA1MUX_Generator3_BASE (AHBPERIPH_BASE + 0x00006128U) /*!< DMA1 Multiplexed Generator 3 base address */ +#define DMA1MUX_Generator4_BASE (AHBPERIPH_BASE + 0x0000612CU) /*!< DMA1 Multiplexed Generator 4 base address */ +#define DMA1MUX_ChannelStatus_BASE (AHBPERIPH_BASE + 0x00006130U) /*!< DMA1 Multiplexed Channel status base address */ +#define DMA1MUX_GeneratorStatus_BASE (AHBPERIPH_BASE + 0x00006138U) /*!< DMA1 Multiplexed Generator status base address */ + +#define DMA2_BASE (AHBPERIPH_BASE + 0x00006400U) /*!< DMA2 base address */ +#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x00006408U) /*!< DMA2 Channel 1 base address */ +#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x0000641CU) /*!< DMA2 Channel 2 base address */ +#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x00006430U) /*!< DMA2 Channel 3 base address */ +#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x00006444U) /*!< DMA2 Channel 4 base address */ +#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x00006458U) /*!< DMA2 Channel 5 base address */ +#define DMA2_Channel6_BASE (AHBPERIPH_BASE + 0x0000646CU) /*!< DMA2 Channel 6 base address */ +#define DMA2_Channel7_BASE (AHBPERIPH_BASE + 0x00006480U) /*!< DMA2 Channel 7 base address */ + +#define DMA2MUX_BASE (AHBPERIPH_BASE + 0x00006504U) /*!< DMA2 Multiplexed base address */ +#define DMA2MUX_Channel1_BASE (DMA2MUX_BASE) /*!< DMA2 Multiplexed Channel 1 base address */ +#define DMA2MUX_Channel2_BASE (AHBPERIPH_BASE + 0x00006508U) /*!< DMA2 Multiplexed Channel 2 base address */ +#define DMA2MUX_Channel3_BASE (AHBPERIPH_BASE + 0x0000650CU) /*!< DMA2 Multiplexed Channel 3 base address */ +#define DMA2MUX_Channel4_BASE (AHBPERIPH_BASE + 0x00006510U) /*!< DMA2 Multiplexed Channel 4 base address */ +#define DMA2MUX_Channel5_BASE (AHBPERIPH_BASE + 0x00006514U) /*!< DMA2 Multiplexed Channel 5 base address */ +#define DMA2MUX_Channel6_BASE (AHBPERIPH_BASE + 0x00006518U) /*!< DMA2 Multiplexed Channel 6 base address */ +#define DMA2MUX_Channel7_BASE (AHBPERIPH_BASE + 0x0000651CU) /*!< DMA2 Multiplexed Channel 7 base address */ +#define DMA2MUX_Generator1_BASE (AHBPERIPH_BASE + 0x00006520U) /*!< DMA2 Multiplexed Generator 1 base address */ +#define DMA2MUX_Generator2_BASE (AHBPERIPH_BASE + 0x00006524U) /*!< DMA2 Multiplexed Generator 2 base address */ +#define DMA2MUX_Generator3_BASE (AHBPERIPH_BASE + 0x00006528U) /*!< DMA2 Multiplexed Generator 3 base address */ +#define DMA2MUX_Generator4_BASE (AHBPERIPH_BASE + 0x0000652CU) /*!< DMA2 Multiplexed Generator 4 base address */ +#define DMA2MUX_ChannelStatus_BASE (AHBPERIPH_BASE + 0x00006530U) /*!< DMA2 Multiplexed Channel status base address */ +#define DMA2MUX_GeneratorStatus_BASE (AHBPERIPH_BASE + 0x00006538U) /*!< DMA2 Multiplexed Generator status base address */ + +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00003C00U) /*!< FLASH registers base address */ +#define QSPI1_R_BASE 0xA0001000U /*!< QSPI1 registers base address */ +#define FLASHSIZE_BASE 0x1FFFF7E0U /*!< FLASH Size register base address */ +#define UID_BASE 0x1FFFF7E8U /*!< Unique device ID register base address */ +#define USD_BASE 0x1FFFF800U /*!< FLASH User System Data base address */ + +#define DEBUG_BASE 0xE0042000U /*!< Debug MCU registers base address */ + +/* USB OTG FS */ +#define USB_OTG_FS_PERIPH_BASE 0x50000000U /*!< USB OTG FS Peripheral Registers base address */ + +/* USB OTG HS (F405 only) */ +#define USB_OTG_HS_PERIPH_BASE 0x40040000U /*!< USB OTG HS Peripheral Registers base address */ + +#define USB_OTG_GLOBAL_BASE 0x00000000U /*!< USB OTG Global Registers base address */ +#define USB_OTG_DEVICE_BASE 0x00000800U /*!< USB OTG Device ModeRegisters base address */ +#define USB_OTG_IN_ENDPOINT_BASE 0x00000900U /*!< USB OTG IN Endpoint Registers base address */ +#define USB_OTG_OUT_ENDPOINT_BASE 0x00000B00U /*!< USB OTG OUT Endpoint Registers base address */ +#define USB_OTG_EP_REG_SIZE 0x00000020U /*!< USB OTG All Endpoint Registers size address */ +#define USB_OTG_HOST_BASE 0x00000400U /*!< USB OTG Host Mode Registers base address */ +#define USB_OTG_HOST_PORT_BASE 0x00000440U /*!< USB OTG Host Port Registers base address */ +#define USB_OTG_HOST_CHANNEL_BASE 0x00000500U /*!< USB OTG Host Channel Registers base address */ +#define USB_OTG_HOST_CHANNEL_SIZE 0x00000020U /*!< USB OTG Host Channel Registers size address */ +#define USB_OTG_PCGCCTL_BASE 0x00000E00U /*!< USB OTG Power and Ctrl Registers base address */ +#define USB_OTG_FIFO_BASE 0x00001000U /*!< USB OTG FIFO Registers base address */ +#define USB_OTG_FIFO_SIZE 0x00001000U /*!< USB OTG FIFO Registers size address */ + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ + +#define ACC ((ACC_TypeDef *)ACC_BASE) +#define ADC1 ((ADC_TypeDef *)ADC1_BASE) +#define ADC_COMMON ((ADC_Common_TypeDef *)ADC_Common_BASE) +#define CAN1 ((CAN_TypeDef *)CAN1_BASE) +#define CRC ((CRC_TypeDef *)CRC_BASE) +#define CRM ((CRM_TypeDef *)CRM_BASE) +#define DEBUG ((DEBUG_TypeDef *)DEBUG_BASE) +#define DMA1 ((DMA_TypeDef *)DMA1_BASE) +#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE) +#define DMA1MUX_Channel1 ((DMAMUX_Channel_TypeDef *) DMA1MUX_Channel1_BASE) +#define DMA1MUX_Channel2 ((DMAMUX_Channel_TypeDef *) DMA1MUX_Channel2_BASE) +#define DMA1MUX_Channel3 ((DMAMUX_Channel_TypeDef *) DMA1MUX_Channel3_BASE) +#define DMA1MUX_Channel4 ((DMAMUX_Channel_TypeDef *) DMA1MUX_Channel4_BASE) +#define DMA1MUX_Channel5 ((DMAMUX_Channel_TypeDef *) DMA1MUX_Channel5_BASE) +#define DMA1MUX_Channel6 ((DMAMUX_Channel_TypeDef *) DMA1MUX_Channel6_BASE) +#define DMA1MUX_Channel7 ((DMAMUX_Channel_TypeDef *) DMA1MUX_Channel7_BASE) +#define DMA1MUX_Generator1 ((DMAMUX_Generator_TypeDef *) DMA1MUX_Generator1_BASE) +#define DMA1MUX_Generator2 ((DMAMUX_Generator_TypeDef *) DMA1MUX_Generator2_BASE) +#define DMA1MUX_Generator3 ((DMAMUX_Generator_TypeDef *) DMA1MUX_Generator3_BASE) +#define DMA1MUX_Generator4 ((DMAMUX_Generator_TypeDef *) DMA1MUX_Generator4_BASE) +#define DMA1MUX_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMA1MUX_ChannelStatus_BASE) +#define DMA1MUX_GeneratorStatus ((DMAMUX_GeneratorStatus_TypeDef *) DMA1MUX_GeneratorStatus_BASE) +#define DMA2 ((DMA_TypeDef *)DMA2_BASE) +#define DMA2_Channel1 ((DMA_Channel_TypeDef *)DMA2_Channel1_BASE) +#define DMA2_Channel2 ((DMA_Channel_TypeDef *)DMA2_Channel2_BASE) +#define DMA2_Channel3 ((DMA_Channel_TypeDef *)DMA2_Channel3_BASE) +#define DMA2_Channel4 ((DMA_Channel_TypeDef *)DMA2_Channel4_BASE) +#define DMA2_Channel5 ((DMA_Channel_TypeDef *)DMA2_Channel5_BASE) +#define DMA2_Channel6 ((DMA_Channel_TypeDef *)DMA2_Channel6_BASE) +#define DMA2_Channel7 ((DMA_Channel_TypeDef *)DMA2_Channel7_BASE) +#define DMA2MUX_Channel1 ((DMAMUX_Channel_TypeDef *) DMA2MUX_Channel1_BASE) +#define DMA2MUX_Channel2 ((DMAMUX_Channel_TypeDef *) DMA2MUX_Channel2_BASE) +#define DMA2MUX_Channel3 ((DMAMUX_Channel_TypeDef *) DMA2MUX_Channel3_BASE) +#define DMA2MUX_Channel4 ((DMAMUX_Channel_TypeDef *) DMA2MUX_Channel4_BASE) +#define DMA2MUX_Channel5 ((DMAMUX_Channel_TypeDef *) DMA2MUX_Channel5_BASE) +#define DMA2MUX_Channel6 ((DMAMUX_Channel_TypeDef *) DMA2MUX_Channel6_BASE) +#define DMA2MUX_Channel7 ((DMAMUX_Channel_TypeDef *) DMA2MUX_Channel7_BASE) +#define DMA2MUX_Generator1 ((DMAMUX_Generator_TypeDef *) DMA2MUX_Generator1_BASE) +#define DMA2MUX_Generator2 ((DMAMUX_Generator_TypeDef *) DMA2MUX_Generator2_BASE) +#define DMA2MUX_Generator3 ((DMAMUX_Generator_TypeDef *) DMA2MUX_Generator3_BASE) +#define DMA2MUX_Generator4 ((DMAMUX_Generator_TypeDef *) DMA2MUX_Generator4_BASE) +#define DMA2MUX_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMA2MUX_ChannelStatus_BASE) +#define DMA2MUX_GeneratorStatus ((DMAMUX_GeneratorStatus_TypeDef *) DMA2MUX_GeneratorStatus_BASE) +#define ERTC ((ERTC_TypeDef *)ERTC_BASE) +#define EXINT ((EXINT_TypeDef *)EXINT_BASE) +#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE) +#define USD ((USD_TypeDef *)USD_BASE) +#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE) +#define GPIOF ((GPIO_TypeDef *)GPIOF_BASE) +#define I2C1 ((I2C_TypeDef *)I2C1_BASE) +#define I2C2 ((I2C_TypeDef *)I2C2_BASE) +#define I2C3 ((I2C_TypeDef *)I2C3_BASE) +#define PWC ((PWC_TypeDef *)PWC_BASE) +#define QSPI1 ((QSPI_TypeDef *)QSPI1_R_BASE) +#define SCFG ((SCFG_TypeDef *)SCFG_BASE) +#define SPI1 ((SPI_TypeDef *)SPI1_BASE) +#define SPI3 ((SPI_TypeDef *)SPI3_BASE) +#define I2SF5 ((SPI_TypeDef *)I2SF5_BASE) +#define TMR1 ((TMR_TypeDef *)TMR1_BASE) +#define TMR2 ((TMR_TypeDef *)TMR2_BASE) +#define TMR3 ((TMR_TypeDef *)TMR3_BASE) +#define TMR4 ((TMR_TypeDef *)TMR4_BASE) +#define TMR6 ((TMR_TypeDef *)TMR6_BASE) +#define TMR7 ((TMR_TypeDef *)TMR7_BASE) +#define TMR9 ((TMR_TypeDef *)TMR9_BASE) +#define TMR10 ((TMR_TypeDef *)TMR10_BASE) +#define TMR11 ((TMR_TypeDef *)TMR11_BASE) +#define TMR13 ((TMR_TypeDef *)TMR13_BASE) +#define TMR14 ((TMR_TypeDef *)TMR14_BASE) +#define USART1 ((USART_TypeDef *)USART1_BASE) +#define USART2 ((USART_TypeDef *)USART2_BASE) +#define USART3 ((USART_TypeDef *)USART3_BASE) +#define USART4 ((USART_TypeDef *)USART4_BASE) +#define USART5 ((USART_TypeDef *)USART5_BASE) +#define USART6 ((USART_TypeDef *)USART6_BASE) +#define UART7 ((USART_TypeDef *)UART7_BASE) +#define WDT ((WDT_TypeDef *)WDT_BASE) +#define WWDT ((WWDT_TypeDef *)WWDT_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral registers bits definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Power Control (PWC) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for PWC_CTRL register *******************/ +#define PWC_CTRL_VRSEL_Pos (0U) +#define PWC_CTRL_VRSEL_Msk (0x1U << PWC_CTRL_VRSEL_Pos) /*!< 0x00000001 */ +#define PWC_CTRL_VRSEL PWC_CTRL_VRSEL_Msk /*!< LDO state select in deep sleep mode */ +#define PWC_CTRL_LPSEL_Pos (1U) +#define PWC_CTRL_LPSEL_Msk (0x1U << PWC_CTRL_LPSEL_Pos) /*!< 0x00000002 */ +#define PWC_CTRL_LPSEL PWC_CTRL_LPSEL_Msk /*!< Low power mode select in deep sleep mode */ +#define PWC_CTRL_CLSWEF_Pos (2U) +#define PWC_CTRL_CLSWEF_Msk (0x1U << PWC_CTRL_CLSWEF_Pos) /*!< 0x00000004 */ +#define PWC_CTRL_CLSWEF PWC_CTRL_CLSWEF_Msk /*!< Clear SWEF flag */ +#define PWC_CTRL_CLSEF_Pos (3U) +#define PWC_CTRL_CLSEF_Msk (0x1U << PWC_CTRL_CLSEF_Pos) /*!< 0x00000008 */ +#define PWC_CTRL_CLSEF PWC_CTRL_CLSEF_Msk /*!< Clear SEF flag */ +#define PWC_CTRL_PVMEN_Pos (4U) +#define PWC_CTRL_PVMEN_Msk (0x1U << PWC_CTRL_PVMEN_Pos) /*!< 0x00000010 */ +#define PWC_CTRL_PVMEN PWC_CTRL_PVMEN_Msk /*!< Power voltage monitoring enable */ + +/*!< PVM level configuration */ +#define PWC_CTRL_PVMSEL_Pos (5U) +#define PWC_CTRL_PVMSEL_Msk (0x7U << PWC_CTRL_PVMSEL_Pos) /*!< 0x000000E0 */ +#define PWC_CTRL_PVMSEL PWC_CTRL_PVMSEL_Msk /*!< PVMSEL[2:0] bits (Power voltage monitoring boundary select) */ +#define PWC_CTRL_PVMSEL_0 (0x1U << PWC_CTRL_PVMSEL_Pos) /*!< 0x00000020 */ +#define PWC_CTRL_PVMSEL_1 (0x2U << PWC_CTRL_PVMSEL_Pos) /*!< 0x00000040 */ +#define PWC_CTRL_PVMSEL_2 (0x4U << PWC_CTRL_PVMSEL_Pos) /*!< 0x00000080 */ + +#define PWC_CTRL_PVMSEL_LEV1 0x00000020U /*!< PVM level 2.3V */ +#define PWC_CTRL_PVMSEL_LEV2 0x00000040U /*!< PVM level 2.4V */ +#define PWC_CTRL_PVMSEL_LEV3 0x00000060U /*!< PVM level 2.5V */ +#define PWC_CTRL_PVMSEL_LEV4 0x00000080U /*!< PVM level 2.6V */ +#define PWC_CTRL_PVMSEL_LEV5 0x000000A0U /*!< PVM level 2.7V */ +#define PWC_CTRL_PVMSEL_LEV6 0x000000C0U /*!< PVM level 2.8V */ +#define PWC_CTRL_PVMSEL_LEV7 0x000000E0U /*!< PVM level 2.9V */ + +/* Legacy defines */ +#define PWC_CTRL_PVMSEL_2V3 PWC_CTRL_PVMSEL_LEV1 +#define PWC_CTRL_PVMSEL_2V4 PWC_CTRL_PVMSEL_LEV2 +#define PWC_CTRL_PVMSEL_2V5 PWC_CTRL_PVMSEL_LEV3 +#define PWC_CTRL_PVMSEL_2V6 PWC_CTRL_PVMSEL_LEV4 +#define PWC_CTRL_PVMSEL_2V7 PWC_CTRL_PVMSEL_LEV5 +#define PWC_CTRL_PVMSEL_2V8 PWC_CTRL_PVMSEL_LEV6 +#define PWC_CTRL_PVMSEL_2V9 PWC_CTRL_PVMSEL_LEV7 + +#define PWC_CTRL_BPWEN_Pos (8U) +#define PWC_CTRL_BPWEN_Msk (0x1U << PWC_CTRL_BPWEN_Pos) /*!< 0x00000100 */ +#define PWC_CTRL_BPWEN PWC_CTRL_BPWEN_Msk /*!< Battery powered domain write enable */ + +/***************** Bit definition for PWC_CTRLSTS register ******************/ +#define PWC_CTRLSTS_SWEF_Pos (0U) +#define PWC_CTRLSTS_SWEF_Msk (0x1U << PWC_CTRLSTS_SWEF_Pos) /*!< 0x00000001 */ +#define PWC_CTRLSTS_SWEF PWC_CTRLSTS_SWEF_Msk /*!< Standby wake-up event flag */ +#define PWC_CTRLSTS_SEF_Pos (1U) +#define PWC_CTRLSTS_SEF_Msk (0x1U << PWC_CTRLSTS_SEF_Pos) /*!< 0x00000002 */ +#define PWC_CTRLSTS_SEF PWC_CTRLSTS_SEF_Msk /*!< Standby mode entry flag */ +#define PWC_CTRLSTS_PVMOF_Pos (2U) +#define PWC_CTRLSTS_PVMOF_Msk (0x1U << PWC_CTRLSTS_PVMOF_Pos) /*!< 0x00000004 */ +#define PWC_CTRLSTS_PVMOF PWC_CTRLSTS_PVMOF_Msk /*!< Power voltage monitoring output flag */ +#define PWC_CTRLSTS_SWPEN1_Pos (8U) +#define PWC_CTRLSTS_SWPEN1_Msk (0x1U << PWC_CTRLSTS_SWPEN1_Pos) /*!< 0x00000100 */ +#define PWC_CTRLSTS_SWPEN1 PWC_CTRLSTS_SWPEN1_Msk /*!< Standby wake-up pin 1 enable */ +#define PWC_CTRLSTS_SWPEN2_Pos (9U) +#define PWC_CTRLSTS_SWPEN2_Msk (0x1U << PWC_CTRLSTS_SWPEN2_Pos) /*!< 0x00000200 */ +#define PWC_CTRLSTS_SWPEN2 PWC_CTRLSTS_SWPEN2_Msk /*!< Standby wake-up pin 2 enable */ +#define PWC_CTRLSTS_SWPEN6_Pos (13U) +#define PWC_CTRLSTS_SWPEN6_Msk (0x1U << PWC_CTRLSTS_SWPEN6_Pos) /*!< 0x00002000 */ +#define PWC_CTRLSTS_SWPEN6 PWC_CTRLSTS_SWPEN6_Msk /*!< Standby wake-up pin 6 enable */ + +/****************** Bit definition for PWC_LDOOV register *******************/ +/*!< LDOOVSEL congiguration */ +#define PWC_LDOOV_LDOOVSEL_Pos (0U) +#define PWC_LDOOV_LDOOVSEL_Msk (0x3U << PWC_LDOOV_LDOOVSEL_Pos) /*!< 0x00000003 */ +#define PWC_LDOOV_LDOOVSEL PWC_LDOOV_LDOOVSEL_Msk /*!< LDOOVSEL[1:0] bits (Voltage regulator output voltage select) */ +#define PWC_LDOOV_LDOOVSEL_0 (0x1U << PWC_LDOOV_LDOOVSEL_Pos) /*!< 0x00000001 */ +#define PWC_LDOOV_LDOOVSEL_1 (0x2U << PWC_LDOOV_LDOOVSEL_Pos) /*!< 0x00000002 */ + +#define PWC_LDOOV_LDOOVSEL_LEV0 0x00000000U /*!< Voltage output level 1.0V */ +#define PWC_LDOOV_LDOOVSEL_LEV2 0x00000002U /*!< Voltage output level 1.2V */ +#define PWC_LDOOV_LDOOVSEL_LEV3 0x00000003U /*!< Voltage output level 1.3V */ + +/* Legacy defines */ +#define PWC_LDOOV_LDOOVSEL_1V0 PWC_LDOOV_LDOOVSEL_LEV0 +#define PWC_LDOOV_LDOOVSEL_1V2 PWC_LDOOV_LDOOVSEL_LEV2 +#define PWC_LDOOV_LDOOVSEL_1V3 PWC_LDOOV_LDOOVSEL_LEV3 + +#define PWC_LDOOV_VREXLPEN_Pos (4U) +#define PWC_LDOOV_VREXLPEN_Msk (0x1U << PWC_LDOOV_VREXLPEN_Pos) /*!< 0x00000010 */ +#define PWC_LDOOV_VREXLPEN PWC_LDOOV_VREXLPEN_Msk /*!< Voltage regulator extra low power mode enable */ + +/******************************************************************************/ +/* */ +/* Clock and reset manage (CRM) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for CRM_CTRL register *******************/ +#define CRM_CTRL_HICKEN_Pos (0U) +#define CRM_CTRL_HICKEN_Msk (0x1U << CRM_CTRL_HICKEN_Pos) /*!< 0x00000001 */ +#define CRM_CTRL_HICKEN CRM_CTRL_HICKEN_Msk /*!< High speed internal clock enable */ +#define CRM_CTRL_HICKSTBL_Pos (1U) +#define CRM_CTRL_HICKSTBL_Msk (0x1U << CRM_CTRL_HICKSTBL_Pos) /*!< 0x00000002 */ +#define CRM_CTRL_HICKSTBL CRM_CTRL_HICKSTBL_Msk /*!< High speed internal clock stable */ +#define CRM_CTRL_HICKTRIM_Pos (2U) +#define CRM_CTRL_HICKTRIM_Msk (0x3FU << CRM_CTRL_HICKTRIM_Pos) /*!< 0x000000FC */ +#define CRM_CTRL_HICKTRIM CRM_CTRL_HICKTRIM_Msk /*!< High speed internal clock trimming */ +#define CRM_CTRL_HICKCAL_Pos (8U) +#define CRM_CTRL_HICKCAL_Msk (0xFFU << CRM_CTRL_HICKCAL_Pos) /*!< 0x0000FF00 */ +#define CRM_CTRL_HICKCAL CRM_CTRL_HICKCAL_Msk /*!< High speed internal clock calibration */ +#define CRM_CTRL_HEXTEN_Pos (16U) +#define CRM_CTRL_HEXTEN_Msk (0x1U << CRM_CTRL_HEXTEN_Pos) /*!< 0x00010000 */ +#define CRM_CTRL_HEXTEN CRM_CTRL_HEXTEN_Msk /*!< High speed external crystal enable */ +#define CRM_CTRL_HEXTSTBL_Pos (17U) +#define CRM_CTRL_HEXTSTBL_Msk (0x1U << CRM_CTRL_HEXTSTBL_Pos) /*!< 0x00020000 */ +#define CRM_CTRL_HEXTSTBL CRM_CTRL_HEXTSTBL_Msk /*!< High speed external crystal stable */ +#define CRM_CTRL_HEXTBYPS_Pos (18U) +#define CRM_CTRL_HEXTBYPS_Msk (0x1U << CRM_CTRL_HEXTBYPS_Pos) /*!< 0x00040000 */ +#define CRM_CTRL_HEXTBYPS CRM_CTRL_HEXTBYPS_Msk /*!< High speed external crystal bypass */ +#define CRM_CTRL_CFDEN_Pos (19U) +#define CRM_CTRL_CFDEN_Msk (0x1U << CRM_CTRL_CFDEN_Pos) /*!< 0x00080000 */ +#define CRM_CTRL_CFDEN CRM_CTRL_CFDEN_Msk /*!< Clock failure detector enable */ +#define CRM_CTRL_PLLEN_Pos (24U) +#define CRM_CTRL_PLLEN_Msk (0x1U << CRM_CTRL_PLLEN_Pos) /*!< 0x01000000 */ +#define CRM_CTRL_PLLEN CRM_CTRL_PLLEN_Msk /*!< PLL enable */ +#define CRM_CTRL_PLLSTBL_Pos (25U) +#define CRM_CTRL_PLLSTBL_Msk (0x1U << CRM_CTRL_PLLSTBL_Pos) /*!< 0x02000000 */ +#define CRM_CTRL_PLLSTBL CRM_CTRL_PLLSTBL_Msk /*!< PLL clock stable */ +#define CRM_CTRL_PLLUSTBL_Pos (26U) +#define CRM_CTRL_PLLUSTBL_Msk (0x1U << CRM_CTRL_PLLUSTBL_Pos) /*!< 0x04000000 */ +#define CRM_CTRL_PLLUSTBL CRM_CTRL_PLLUSTBL_Msk /*!< PLLU clock stable */ + +/****************** Bit definition for CRM_PLLCFG register ******************/ +/*!< PLL_MS congiguration */ +#define CRM_PLLCFG_PLL_MS_Pos (0U) +#define CRM_PLLCFG_PLL_MS_Msk (0xFU << CRM_PLLCFG_PLL_MS_Pos) /*!< 0x0000000F */ +#define CRM_PLLCFG_PLL_MS CRM_PLLCFG_PLL_MS_Msk /*!< PLL_MS[3:0] bits (PLL pre-division) */ +#define CRM_PLLCFG_PLL_MS_0 (0x1U << CRM_PLLCFG_PLL_MS_Pos) /*!< 0x00000001 */ +#define CRM_PLLCFG_PLL_MS_1 (0x2U << CRM_PLLCFG_PLL_MS_Pos) /*!< 0x00000002 */ +#define CRM_PLLCFG_PLL_MS_2 (0x4U << CRM_PLLCFG_PLL_MS_Pos) /*!< 0x00000004 */ +#define CRM_PLLCFG_PLL_MS_3 (0x8U << CRM_PLLCFG_PLL_MS_Pos) /*!< 0x00000008 */ + +/*!< PLL_NS congiguration */ +#define CRM_PLLCFG_PLL_NS_Pos (6U) +#define CRM_PLLCFG_PLL_NS_Msk (0x1FFU << CRM_PLLCFG_PLL_NS_Pos) /*!< 0x00007FC0 */ +#define CRM_PLLCFG_PLL_NS CRM_PLLCFG_PLL_NS_Msk /*!< PLL_NS[8:0] bits (PLL multiplication factor) */ +#define CRM_PLLCFG_PLL_NS_0 (0x001U << CRM_PLLCFG_PLL_NS_Pos) /*!< 0x00000040 */ +#define CRM_PLLCFG_PLL_NS_1 (0x002U << CRM_PLLCFG_PLL_NS_Pos) /*!< 0x00000080 */ +#define CRM_PLLCFG_PLL_NS_2 (0x004U << CRM_PLLCFG_PLL_NS_Pos) /*!< 0x00000100 */ +#define CRM_PLLCFG_PLL_NS_3 (0x008U << CRM_PLLCFG_PLL_NS_Pos) /*!< 0x00000200 */ +#define CRM_PLLCFG_PLL_NS_4 (0x010U << CRM_PLLCFG_PLL_NS_Pos) /*!< 0x00000400 */ +#define CRM_PLLCFG_PLL_NS_5 (0x020U << CRM_PLLCFG_PLL_NS_Pos) /*!< 0x00000800 */ +#define CRM_PLLCFG_PLL_NS_6 (0x040U << CRM_PLLCFG_PLL_NS_Pos) /*!< 0x00001000 */ +#define CRM_PLLCFG_PLL_NS_7 (0x080U << CRM_PLLCFG_PLL_NS_Pos) /*!< 0x00002000 */ +#define CRM_PLLCFG_PLL_NS_8 (0x100U << CRM_PLLCFG_PLL_NS_Pos) /*!< 0x00004000 */ + +/*!< PLL_FP congiguration */ +#define CRM_PLLCFG_PLL_FP_Pos (16U) +#define CRM_PLLCFG_PLL_FP_Msk (0xFU << CRM_PLLCFG_PLL_FP_Pos) /*!< 0x000F0000 */ +#define CRM_PLLCFG_PLL_FP CRM_PLLCFG_PLL_FP_Msk /*!< PLL_FP[3:0] bits (PLLP post-division) */ +#define CRM_PLLCFG_PLL_FP_0 (0x1U << CRM_PLLCFG_PLL_FP_Pos) /*!< 0x00010000 */ +#define CRM_PLLCFG_PLL_FP_1 (0x2U << CRM_PLLCFG_PLL_FP_Pos) /*!< 0x00020000 */ +#define CRM_PLLCFG_PLL_FP_2 (0x4U << CRM_PLLCFG_PLL_FP_Pos) /*!< 0x00040000 */ +#define CRM_PLLCFG_PLL_FP_3 (0x8U << CRM_PLLCFG_PLL_FP_Pos) /*!< 0x00080000 */ + +/*!< PLL_FU congiguration */ +#define CRM_PLLCFG_PLL_FU_Pos (20U) +#define CRM_PLLCFG_PLL_FU_Msk (0x7U << CRM_PLLCFG_PLL_FU_Pos) /*!< 0x00700000 */ +#define CRM_PLLCFG_PLL_FU CRM_PLLCFG_PLL_FU_Msk /*!< PLL_FU[2:0] bits (PLLU post-division) */ +#define CRM_PLLCFG_PLL_FU_0 (0x1U << CRM_PLLCFG_PLL_FU_Pos) /*!< 0x00100000 */ +#define CRM_PLLCFG_PLL_FU_1 (0x2U << CRM_PLLCFG_PLL_FU_Pos) /*!< 0x00200000 */ +#define CRM_PLLCFG_PLL_FU_2 (0x4U << CRM_PLLCFG_PLL_FU_Pos) /*!< 0x00400000 */ + +#define CRM_PLLCFG_PLLU_EN_Pos (29U) +#define CRM_PLLCFG_PLLU_EN_Msk (0x1U << CRM_PLLCFG_PLLU_EN_Pos) /*!< 0x20000000 */ +#define CRM_PLLCFG_PLLU_EN CRM_PLLCFG_PLLU_EN_Msk /*!< PLLU enable */ +#define CRM_PLLCFG_PLLRCS_Pos (30U) +#define CRM_PLLCFG_PLLRCS_Msk (0x1U << CRM_PLLCFG_PLLRCS_Pos) /*!< 0x40000000 */ +#define CRM_PLLCFG_PLLRCS CRM_PLLCFG_PLLRCS_Msk /*!< PLL reference clock select */ +#define CRM_PLLCFG_PLLRST_Pos (31U) +#define CRM_PLLCFG_PLLRST_Msk (0x1U << CRM_PLLCFG_PLLRST_Pos) /*!< 0x80000000 */ +#define CRM_PLLCFG_PLLRST CRM_PLLCFG_PLLRST_Msk /*!< PLLRST */ + +/******************* Bit definition for CRM_CFG register ********************/ +/*!< SCLKSEL configuration */ +#define CRM_CFG_SCLKSEL_Pos (0U) +#define CRM_CFG_SCLKSEL_Msk (0x3U << CRM_CFG_SCLKSEL_Pos) /*!< 0x00000003 */ +#define CRM_CFG_SCLKSEL CRM_CFG_SCLKSEL_Msk /*!< SCLKSEL[1:0] bits (System clock select) */ +#define CRM_CFG_SCLKSEL_0 (0x1U << CRM_CFG_SCLKSEL_Pos) /*!< 0x00000001 */ +#define CRM_CFG_SCLKSEL_1 (0x2U << CRM_CFG_SCLKSEL_Pos) /*!< 0x00000002 */ + +#define CRM_CFG_SCLKSEL_HICK 0x00000000U /*!< HICK */ +#define CRM_CFG_SCLKSEL_HEXT 0x00000001U /*!< HEXT */ +#define CRM_CFG_SCLKSEL_PLL 0x00000002U /*!< PLL */ + +/*!< SCLKSTS configuration */ +#define CRM_CFG_SCLKSTS_Pos (2U) +#define CRM_CFG_SCLKSTS_Msk (0x3U << CRM_CFG_SCLKSTS_Pos) /*!< 0x0000000C */ +#define CRM_CFG_SCLKSTS CRM_CFG_SCLKSTS_Msk /*!< SCLKSTS[1:0] bits (System clock select status) */ +#define CRM_CFG_SCLKSTS_0 (0x1U << CRM_CFG_SCLKSTS_Pos) /*!< 0x00000004 */ +#define CRM_CFG_SCLKSTS_1 (0x2U << CRM_CFG_SCLKSTS_Pos) /*!< 0x00000008 */ + +#define CRM_CFG_SCLKSTS_HICK 0x00000000U /*!< HICK */ +#define CRM_CFG_SCLKSTS_HEXT 0x00000004U /*!< HEXT */ +#define CRM_CFG_SCLKSTS_PLL 0x00000008U /*!< PLL */ + +/*!< AHBDIV configuration */ +#define CRM_CFG_AHBDIV_Pos (4U) +#define CRM_CFG_AHBDIV_Msk (0xFU << CRM_CFG_AHBDIV_Pos) /*!< 0x000000F0 */ +#define CRM_CFG_AHBDIV CRM_CFG_AHBDIV_Msk /*!< AHBDIV[3:0] bits (AHB division) */ +#define CRM_CFG_AHBDIV_0 (0x1U << CRM_CFG_AHBDIV_Pos) /*!< 0x00000010 */ +#define CRM_CFG_AHBDIV_1 (0x2U << CRM_CFG_AHBDIV_Pos) /*!< 0x00000020 */ +#define CRM_CFG_AHBDIV_2 (0x4U << CRM_CFG_AHBDIV_Pos) /*!< 0x00000040 */ +#define CRM_CFG_AHBDIV_3 (0x8U << CRM_CFG_AHBDIV_Pos) /*!< 0x00000080 */ + +#define CRM_CFG_AHBDIV_DIV1 0x00000000U /*!< SCLK is not divided */ +#define CRM_CFG_AHBDIV_DIV2 0x00000080U /*!< SCLK is divided by 2 */ +#define CRM_CFG_AHBDIV_DIV4 0x00000090U /*!< SCLK is divided by 4 */ +#define CRM_CFG_AHBDIV_DIV8 0x000000A0U /*!< SCLK is divided by 8 */ +#define CRM_CFG_AHBDIV_DIV16 0x000000B0U /*!< SCLK is divided by 16 */ +#define CRM_CFG_AHBDIV_DIV64 0x000000C0U /*!< SCLK is divided by 64 */ +#define CRM_CFG_AHBDIV_DIV128 0x000000D0U /*!< SCLK is divided by 128 */ +#define CRM_CFG_AHBDIV_DIV256 0x000000E0U /*!< SCLK is divided by 256 */ +#define CRM_CFG_AHBDIV_DIV512 0x000000F0U /*!< SCLK is divided by 512 */ + +/*!< APB1DIV configuration */ +#define CRM_CFG_APB1DIV_Pos (10U) +#define CRM_CFG_APB1DIV_Msk (0x7U << CRM_CFG_APB1DIV_Pos) /*!< 0x00001C00 */ +#define CRM_CFG_APB1DIV CRM_CFG_APB1DIV_Msk /*!< APB1DIV[2:0] bits (APB1 division) */ +#define CRM_CFG_APB1DIV_0 (0x1U << CRM_CFG_APB1DIV_Pos) /*!< 0x00000400 */ +#define CRM_CFG_APB1DIV_1 (0x2U << CRM_CFG_APB1DIV_Pos) /*!< 0x00000800 */ +#define CRM_CFG_APB1DIV_2 (0x4U << CRM_CFG_APB1DIV_Pos) /*!< 0x00001000 */ + +#define CRM_CFG_APB1DIV_DIV1 0x00000000U /*!< HCLK is not divided */ +#define CRM_CFG_APB1DIV_DIV2 0x00001000U /*!< HCLK is divided by 2 */ +#define CRM_CFG_APB1DIV_DIV4 0x00001400U /*!< HCLK is divided by 4 */ +#define CRM_CFG_APB1DIV_DIV8 0x00001800U /*!< HCLK is divided by 8 */ +#define CRM_CFG_APB1DIV_DIV16 0x00001C00U /*!< HCLK is divided by 16 */ + +/*!< APB2DIV configuration */ +#define CRM_CFG_APB2DIV_Pos (13U) +#define CRM_CFG_APB2DIV_Msk (0x7U << CRM_CFG_APB2DIV_Pos) /*!< 0x0000E000 */ +#define CRM_CFG_APB2DIV CRM_CFG_APB2DIV_Msk /*!< APB2DIV[2:0] bits (APB2 division) */ +#define CRM_CFG_APB2DIV_0 (0x1U << CRM_CFG_APB2DIV_Pos) /*!< 0x00002000 */ +#define CRM_CFG_APB2DIV_1 (0x2U << CRM_CFG_APB2DIV_Pos) /*!< 0x00004000 */ +#define CRM_CFG_APB2DIV_2 (0x4U << CRM_CFG_APB2DIV_Pos) /*!< 0x00008000 */ + +#define CRM_CFG_APB2DIV_DIV1 0x00000000U /*!< HCLK is not divided */ +#define CRM_CFG_APB2DIV_DIV2 0x00008000U /*!< HCLK is divided by 2 */ +#define CRM_CFG_APB2DIV_DIV4 0x0000A000U /*!< HCLK is divided by 4 */ +#define CRM_CFG_APB2DIV_DIV8 0x0000C000U /*!< HCLK is divided by 8 */ +#define CRM_CFG_APB2DIV_DIV16 0x0000E000U /*!< HCLK is divided by 16 */ + +/*!< ERTCDIV configuration */ +#define CRM_CFG_ERTCDIV_Pos (16U) +#define CRM_CFG_ERTCDIV_Msk (0x1FU << CRM_CFG_ERTCDIV_Pos) /*!< 0x001F0000 */ +#define CRM_CFG_ERTCDIV CRM_CFG_ERTCDIV_Msk /*!< ERTCDIV[4:0] bits (HEXT division for ERTC clock) */ +#define CRM_CFG_ERTCDIV_0 (0x01U << CRM_CFG_ERTCDIV_Pos) /*!< 0x00010000 */ +#define CRM_CFG_ERTCDIV_1 (0x02U << CRM_CFG_ERTCDIV_Pos) /*!< 0x00020000 */ +#define CRM_CFG_ERTCDIV_2 (0x04U << CRM_CFG_ERTCDIV_Pos) /*!< 0x00040000 */ +#define CRM_CFG_ERTCDIV_3 (0x08U << CRM_CFG_ERTCDIV_Pos) /*!< 0x00080000 */ +#define CRM_CFG_ERTCDIV_4 (0x10U << CRM_CFG_ERTCDIV_Pos) /*!< 0x00100000 */ + +#define CRM_CFG_ERTCDIV_DIV2 0x00020000U /*!< HEXT/2 */ +#define CRM_CFG_ERTCDIV_DIV3 0x00030000U /*!< HEXT/3 */ +#define CRM_CFG_ERTCDIV_DIV4 0x00040000U /*!< HEXT/4 */ +#define CRM_CFG_ERTCDIV_DIV5 0x00050000U /*!< HEXT/5 */ +#define CRM_CFG_ERTCDIV_DIV6 0x00060000U /*!< HEXT/6 */ +#define CRM_CFG_ERTCDIV_DIV7 0x00070000U /*!< HEXT/7 */ +#define CRM_CFG_ERTCDIV_DIV8 0x00080000U /*!< HEXT/8 */ +#define CRM_CFG_ERTCDIV_DIV9 0x00090000U /*!< HEXT/9 */ +#define CRM_CFG_ERTCDIV_DIV10 0x000A0000U /*!< HEXT/10 */ +#define CRM_CFG_ERTCDIV_DIV11 0x000B0000U /*!< HEXT/11 */ +#define CRM_CFG_ERTCDIV_DIV12 0x000C0000U /*!< HEXT/12 */ +#define CRM_CFG_ERTCDIV_DIV13 0x000D0000U /*!< HEXT/13 */ +#define CRM_CFG_ERTCDIV_DIV14 0x000E0000U /*!< HEXT/14 */ +#define CRM_CFG_ERTCDIV_DIV15 0x000F0000U /*!< HEXT/15 */ +#define CRM_CFG_ERTCDIV_DIV16 0x00100000U /*!< HEXT/16 */ +#define CRM_CFG_ERTCDIV_DIV17 0x00110000U /*!< HEXT/17 */ +#define CRM_CFG_ERTCDIV_DIV18 0x00120000U /*!< HEXT/18 */ +#define CRM_CFG_ERTCDIV_DIV19 0x00130000U /*!< HEXT/19 */ +#define CRM_CFG_ERTCDIV_DIV20 0x00140000U /*!< HEXT/20 */ +#define CRM_CFG_ERTCDIV_DIV21 0x00150000U /*!< HEXT/21 */ +#define CRM_CFG_ERTCDIV_DIV22 0x00160000U /*!< HEXT/22 */ +#define CRM_CFG_ERTCDIV_DIV23 0x00170000U /*!< HEXT/23 */ +#define CRM_CFG_ERTCDIV_DIV24 0x00180000U /*!< HEXT/24 */ +#define CRM_CFG_ERTCDIV_DIV25 0x00190000U /*!< HEXT/25 */ +#define CRM_CFG_ERTCDIV_DIV26 0x001A0000U /*!< HEXT/26 */ +#define CRM_CFG_ERTCDIV_DIV27 0x001B0000U /*!< HEXT/27 */ +#define CRM_CFG_ERTCDIV_DIV28 0x001C0000U /*!< HEXT/28 */ +#define CRM_CFG_ERTCDIV_DIV29 0x001D0000U /*!< HEXT/29 */ +#define CRM_CFG_ERTCDIV_DIV30 0x001E0000U /*!< HEXT/30 */ +#define CRM_CFG_ERTCDIV_DIV31 0x001F0000U /*!< HEXT/31 */ + +/*!< I2SF5CLKSEL configuration */ +#define CRM_CFG_I2SF5CLKSEL_Pos (22U) +#define CRM_CFG_I2SF5CLKSEL_Msk (0x3U << CRM_CFG_I2SF5CLKSEL_Pos) /*!< 0x00C00000 */ +#define CRM_CFG_I2SF5CLKSEL CRM_CFG_I2SF5CLKSEL_Msk /*!< I2SF5CLKSEL[1:0] bits (I2SF5 clock source selection) */ +#define CRM_CFG_I2SF5CLKSEL_0 (0x1U << CRM_CFG_I2SF5CLKSEL_Pos) /*!< 0x00400000 */ +#define CRM_CFG_I2SF5CLKSEL_1 (0x2U << CRM_CFG_I2SF5CLKSEL_Pos) /*!< 0x00800000 */ + +#define CRM_CFG_I2SF5CLKSEL_SCLK 0x00000000U /*!< System clock */ +#define CRM_CFG_I2SF5CLKSEL_PLL 0x00400000U /*!< PLL */ +#define CRM_CFG_I2SF5CLKSEL_HICK 0x00800000U /*!< HICK */ +#define CRM_CFG_I2SF5CLKSEL_EXTERNAL 0x00C00000U /*!< External input clock */ + +/*!< CLKOUTDIV1 configuration */ +#define CRM_CFG_CLKOUTDIV1_Pos (27U) +#define CRM_CFG_CLKOUTDIV1_Msk (0x7U << CRM_CFG_CLKOUTDIV1_Pos) /*!< 0x38000000 */ +#define CRM_CFG_CLKOUTDIV1 CRM_CFG_CLKOUTDIV1_Msk /*!< CLKOUTDIV1[2:0] bits (Clock output division 1) */ +#define CRM_CFG_CLKOUTDIV1_0 (0x1U << CRM_CFG_CLKOUTDIV1_Pos) /*!< 0x08000000 */ +#define CRM_CFG_CLKOUTDIV1_1 (0x2U << CRM_CFG_CLKOUTDIV1_Pos) /*!< 0x10000000 */ +#define CRM_CFG_CLKOUTDIV1_2 (0x4U << CRM_CFG_CLKOUTDIV1_Pos) /*!< 0x20000000 */ + +#define CRM_CFG_CLKOUTDIV1_DIV1 0x00000000U /*!< No clock output */ +#define CRM_CFG_CLKOUTDIV1_DIV2 0x20000000U /*!< Clock output divided by 2 */ +#define CRM_CFG_CLKOUTDIV1_DIV3 0x28000000U /*!< Clock output divided by 3 */ +#define CRM_CFG_CLKOUTDIV1_DIV4 0x30000000U /*!< Clock output divided by 4 */ +#define CRM_CFG_CLKOUTDIV1_DIV5 0x38000000U /*!< Clock output divided by 5 */ + +/*!< CLKOUT_SEL1 configuration */ +#define CRM_CFG_CLKOUT_SEL1_Pos (30U) +#define CRM_CFG_CLKOUT_SEL1_Msk (0x3U << CRM_CFG_CLKOUT_SEL1_Pos) /*!< 0xC0000000 */ +#define CRM_CFG_CLKOUT_SEL1 CRM_CFG_CLKOUT_SEL1_Msk /*!< CLKOUT_SEL1[1:0] bits (Clock output selection 1) */ +#define CRM_CFG_CLKOUT_SEL1_0 (0x1U << CRM_CFG_CLKOUT_SEL1_Pos) /*!< 0x40000000 */ +#define CRM_CFG_CLKOUT_SEL1_1 (0x2U << CRM_CFG_CLKOUT_SEL1_Pos) /*!< 0x80000000 */ + +#define CRM_CFG_CLKOUT_SEL1_SCLK 0x00000000U /*!< System clock */ +#define CRM_CFG_CLKOUT_SEL1_CLKOUT_SEL2 0x40000000U /*!< CLKOUT_SEL2 bit in the CRM_MISC1 register */ +#define CRM_CFG_CLKOUT_SEL1_HEXT 0x80000000U /*!< HEXT */ +#define CRM_CFG_CLKOUT_SEL1_PLL 0xC0000000U /*!< PLL */ + +/* Reference defines */ +#define CRM_CFG_CLKSEL1 CRM_CFG_CLKOUT_SEL1 +#define CRM_CFG_CLKSEL1_0 CRM_CFG_CLKOUT_SEL1_0 +#define CRM_CFG_CLKSEL1_1 CRM_CFG_CLKOUT_SEL1_1 +#define CRM_CFG_CLKSEL1_SCLK CRM_CFG_CLKOUT_SEL1_SCLK +#define CRM_CFG_CLKSEL1_CLKOUT_SEL2 CRM_CFG_CLKOUT_SEL1_CLKOUT_SEL2 +#define CRM_CFG_CLKSEL1_HEXT CRM_CFG_CLKOUT_SEL1_HEXT +#define CRM_CFG_CLKSEL1_PLL CRM_CFG_CLKOUT_SEL1_PLL + +/*!<*************** Bit definition for CRM_CLKINT register ******************/ +#define CRM_CLKINT_LICKSTBLF_Pos (0U) +#define CRM_CLKINT_LICKSTBLF_Msk (0x1U << CRM_CLKINT_LICKSTBLF_Pos) /*!< 0x00000001 */ +#define CRM_CLKINT_LICKSTBLF CRM_CLKINT_LICKSTBLF_Msk /*!< LICK stable interrupt flag */ +#define CRM_CLKINT_LEXTSTBLF_Pos (1U) +#define CRM_CLKINT_LEXTSTBLF_Msk (0x1U << CRM_CLKINT_LEXTSTBLF_Pos) /*!< 0x00000002 */ +#define CRM_CLKINT_LEXTSTBLF CRM_CLKINT_LEXTSTBLF_Msk /*!< LEXT stable flag */ +#define CRM_CLKINT_HICKSTBLF_Pos (2U) +#define CRM_CLKINT_HICKSTBLF_Msk (0x1U << CRM_CLKINT_HICKSTBLF_Pos) /*!< 0x00000004 */ +#define CRM_CLKINT_HICKSTBLF CRM_CLKINT_HICKSTBLF_Msk /*!< HICK stable flag */ +#define CRM_CLKINT_HEXTSTBLF_Pos (3U) +#define CRM_CLKINT_HEXTSTBLF_Msk (0x1U << CRM_CLKINT_HEXTSTBLF_Pos) /*!< 0x00000008 */ +#define CRM_CLKINT_HEXTSTBLF CRM_CLKINT_HEXTSTBLF_Msk /*!< HEXT stable flag */ +#define CRM_CLKINT_PLLSTBLF_Pos (4U) +#define CRM_CLKINT_PLLSTBLF_Msk (0x1U << CRM_CLKINT_PLLSTBLF_Pos) /*!< 0x00000010 */ +#define CRM_CLKINT_PLLSTBLF CRM_CLKINT_PLLSTBLF_Msk /*!< PLL stable flag */ +#define CRM_CLKINT_CFDF_Pos (7U) +#define CRM_CLKINT_CFDF_Msk (0x1U << CRM_CLKINT_CFDF_Pos) /*!< 0x00000080 */ +#define CRM_CLKINT_CFDF CRM_CLKINT_CFDF_Msk /*!< Clock failure detection flag */ +#define CRM_CLKINT_LICKSTBLIEN_Pos (8U) +#define CRM_CLKINT_LICKSTBLIEN_Msk (0x1U << CRM_CLKINT_LICKSTBLIEN_Pos) /*!< 0x00000100 */ +#define CRM_CLKINT_LICKSTBLIEN CRM_CLKINT_LICKSTBLIEN_Msk /*!< LICK stable interrupt enable */ +#define CRM_CLKINT_LEXTSTBLIEN_Pos (9U) +#define CRM_CLKINT_LEXTSTBLIEN_Msk (0x1U << CRM_CLKINT_LEXTSTBLIEN_Pos) /*!< 0x00000200 */ +#define CRM_CLKINT_LEXTSTBLIEN CRM_CLKINT_LEXTSTBLIEN_Msk /*!< LEXT stable interrupt enable */ +#define CRM_CLKINT_HICKSTBLIEN_Pos (10U) +#define CRM_CLKINT_HICKSTBLIEN_Msk (0x1U << CRM_CLKINT_HICKSTBLIEN_Pos) /*!< 0x00000400 */ +#define CRM_CLKINT_HICKSTBLIEN CRM_CLKINT_HICKSTBLIEN_Msk /*!< HICK stable interrupt enable */ +#define CRM_CLKINT_HEXTSTBLIEN_Pos (11U) +#define CRM_CLKINT_HEXTSTBLIEN_Msk (0x1U << CRM_CLKINT_HEXTSTBLIEN_Pos) /*!< 0x00000800 */ +#define CRM_CLKINT_HEXTSTBLIEN CRM_CLKINT_HEXTSTBLIEN_Msk /*!< HEXT stable interrupt enable */ +#define CRM_CLKINT_PLLSTBLIEN_Pos (12U) +#define CRM_CLKINT_PLLSTBLIEN_Msk (0x1U << CRM_CLKINT_PLLSTBLIEN_Pos) /*!< 0x00001000 */ +#define CRM_CLKINT_PLLSTBLIEN CRM_CLKINT_PLLSTBLIEN_Msk /*!< PLL stable interrupt enable */ +#define CRM_CLKINT_LICKSTBLFC_Pos (16U) +#define CRM_CLKINT_LICKSTBLFC_Msk (0x1U << CRM_CLKINT_LICKSTBLFC_Pos) /*!< 0x00010000 */ +#define CRM_CLKINT_LICKSTBLFC CRM_CLKINT_LICKSTBLFC_Msk /*!< LICK stable flag clear */ +#define CRM_CLKINT_LEXTSTBLFC_Pos (17U) +#define CRM_CLKINT_LEXTSTBLFC_Msk (0x1U << CRM_CLKINT_LEXTSTBLFC_Pos) /*!< 0x00020000 */ +#define CRM_CLKINT_LEXTSTBLFC CRM_CLKINT_LEXTSTBLFC_Msk /*!< LEXT stable flag clear */ +#define CRM_CLKINT_HICKSTBLFC_Pos (18U) +#define CRM_CLKINT_HICKSTBLFC_Msk (0x1U << CRM_CLKINT_HICKSTBLFC_Pos) /*!< 0x00040000 */ +#define CRM_CLKINT_HICKSTBLFC CRM_CLKINT_HICKSTBLFC_Msk /*!< HICK stable flag clear */ +#define CRM_CLKINT_HEXTSTBLFC_Pos (19U) +#define CRM_CLKINT_HEXTSTBLFC_Msk (0x1U << CRM_CLKINT_HEXTSTBLFC_Pos) /*!< 0x00080000 */ +#define CRM_CLKINT_HEXTSTBLFC CRM_CLKINT_HEXTSTBLFC_Msk /*!< HEXT stable flag clear */ +#define CRM_CLKINT_PLLSTBLFC_Pos (20U) +#define CRM_CLKINT_PLLSTBLFC_Msk (0x1U << CRM_CLKINT_PLLSTBLFC_Pos) /*!< 0x00100000 */ +#define CRM_CLKINT_PLLSTBLFC CRM_CLKINT_PLLSTBLFC_Msk /*!< PLL stable flag clear */ +#define CRM_CLKINT_CFDFC_Pos (23U) +#define CRM_CLKINT_CFDFC_Msk (0x1U << CRM_CLKINT_CFDFC_Pos) /*!< 0x00800000 */ +#define CRM_CLKINT_CFDFC CRM_CLKINT_CFDFC_Msk /*!< Clock failure detection flag clear */ + +/***************** Bit definition for CRM_AHBRST1 register ******************/ +#define CRM_AHBRST1_GPIOARST_Pos (0U) +#define CRM_AHBRST1_GPIOARST_Msk (0x1U << CRM_AHBRST1_GPIOARST_Pos) /*!< 0x00000001 */ +#define CRM_AHBRST1_GPIOARST CRM_AHBRST1_GPIOARST_Msk /*!< IO port A reset */ +#define CRM_AHBRST1_GPIOBRST_Pos (1U) +#define CRM_AHBRST1_GPIOBRST_Msk (0x1U << CRM_AHBRST1_GPIOBRST_Pos) /*!< 0x00000002 */ +#define CRM_AHBRST1_GPIOBRST CRM_AHBRST1_GPIOBRST_Msk /*!< IO port B reset */ +#define CRM_AHBRST1_GPIOCRST_Pos (2U) +#define CRM_AHBRST1_GPIOCRST_Msk (0x1U << CRM_AHBRST1_GPIOCRST_Pos) /*!< 0x00000004 */ +#define CRM_AHBRST1_GPIOCRST CRM_AHBRST1_GPIOCRST_Msk /*!< IO port C reset */ +#define CRM_AHBRST1_GPIODRST_Pos (3U) +#define CRM_AHBRST1_GPIODRST_Msk (0x1U << CRM_AHBRST1_GPIODRST_Pos) /*!< 0x00000008 */ +#define CRM_AHBRST1_GPIODRST CRM_AHBRST1_GPIODRST_Msk /*!< IO port D reset */ +#define CRM_AHBRST1_GPIOFRST_Pos (5U) +#define CRM_AHBRST1_GPIOFRST_Msk (0x1U << CRM_AHBRST1_GPIOFRST_Pos) /*!< 0x00000020 */ +#define CRM_AHBRST1_GPIOFRST CRM_AHBRST1_GPIOFRST_Msk /*!< IO port F reset */ +#define CRM_AHBRST1_CRCRST_Pos (12U) +#define CRM_AHBRST1_CRCRST_Msk (0x1U << CRM_AHBRST1_CRCRST_Pos) /*!< 0x00001000 */ +#define CRM_AHBRST1_CRCRST CRM_AHBRST1_CRCRST_Msk /*!< CRC reset */ +#define CRM_AHBRST1_DMA1RST_Pos (22U) +#define CRM_AHBRST1_DMA1RST_Msk (0x1U << CRM_AHBRST1_DMA1RST_Pos) /*!< 0x00400000 */ +#define CRM_AHBRST1_DMA1RST CRM_AHBRST1_DMA1RST_Msk /*!< DMA1 reset */ +#define CRM_AHBRST1_DMA2RST_Pos (24U) +#define CRM_AHBRST1_DMA2RST_Msk (0x1U << CRM_AHBRST1_DMA2RST_Pos) /*!< 0x01000000 */ +#define CRM_AHBRST1_DMA2RST CRM_AHBRST1_DMA2RST_Msk /*!< DMA2 reset */ +#define CRM_AHBRST1_OTGHSRST_Pos (29U) +#define CRM_AHBRST1_OTGHSRST_Msk (0x1U << CRM_AHBRST1_OTGHSRST_Pos) /*!< 0x20000000 */ +#define CRM_AHBRST1_OTGHSRST CRM_AHBRST1_OTGHSRST_Msk /*!< OTGHS reset (F405 only) */ + +/***************** Bit definition for CRM_AHBRST2 register ******************/ +#define CRM_AHBRST2_OTGFSRST_Pos (7U) +#define CRM_AHBRST2_OTGFSRST_Msk (0x1U << CRM_AHBRST2_OTGFSRST_Pos) /*!< 0x00000080 */ +#define CRM_AHBRST2_OTGFSRST CRM_AHBRST2_OTGFSRST_Msk /*!< OTGFS reset */ + +/***************** Bit definition for CRM_AHBRST3 register ******************/ +#define CRM_AHBRST3_QSPI1RST_Pos (1U) +#define CRM_AHBRST3_QSPI1RST_Msk (0x1U << CRM_AHBRST3_QSPI1RST_Pos) /*!< 0x00000002 */ +#define CRM_AHBRST3_QSPI1RST CRM_AHBRST3_QSPI1RST_Msk /*!< QSPI1 reset */ + +/***************** Bit definition for CRM_APB1RST register ******************/ +#define CRM_APB1RST_TMR2RST_Pos (0U) +#define CRM_APB1RST_TMR2RST_Msk (0x1U << CRM_APB1RST_TMR2RST_Pos) /*!< 0x00000001 */ +#define CRM_APB1RST_TMR2RST CRM_APB1RST_TMR2RST_Msk /*!< TMR2 reset */ +#define CRM_APB1RST_TMR3RST_Pos (1U) +#define CRM_APB1RST_TMR3RST_Msk (0x1U << CRM_APB1RST_TMR3RST_Pos) /*!< 0x00000002 */ +#define CRM_APB1RST_TMR3RST CRM_APB1RST_TMR3RST_Msk /*!< TMR3 reset */ +#define CRM_APB1RST_TMR4RST_Pos (2U) +#define CRM_APB1RST_TMR4RST_Msk (0x1U << CRM_APB1RST_TMR4RST_Pos) /*!< 0x00000004 */ +#define CRM_APB1RST_TMR4RST CRM_APB1RST_TMR4RST_Msk /*!< TMR4 reset */ +#define CRM_APB1RST_TMR6RST_Pos (4U) +#define CRM_APB1RST_TMR6RST_Msk (0x1U << CRM_APB1RST_TMR6RST_Pos) /*!< 0x00000010 */ +#define CRM_APB1RST_TMR6RST CRM_APB1RST_TMR6RST_Msk /*!< TMR6 reset */ +#define CRM_APB1RST_TMR7RST_Pos (5U) +#define CRM_APB1RST_TMR7RST_Msk (0x1U << CRM_APB1RST_TMR7RST_Pos) /*!< 0x00000020 */ +#define CRM_APB1RST_TMR7RST CRM_APB1RST_TMR7RST_Msk /*!< TMR7 reset */ +#define CRM_APB1RST_TMR13RST_Pos (7U) +#define CRM_APB1RST_TMR13RST_Msk (0x1U << CRM_APB1RST_TMR13RST_Pos) /*!< 0x00000080 */ +#define CRM_APB1RST_TMR13RST CRM_APB1RST_TMR13RST_Msk /*!< TMR13 reset */ +#define CRM_APB1RST_TMR14RST_Pos (8U) +#define CRM_APB1RST_TMR14RST_Msk (0x1U << CRM_APB1RST_TMR14RST_Pos) /*!< 0x00000100 */ +#define CRM_APB1RST_TMR14RST CRM_APB1RST_TMR14RST_Msk /*!< TMR14 reset */ +#define CRM_APB1RST_WWDTRST_Pos (11U) +#define CRM_APB1RST_WWDTRST_Msk (0x1U << CRM_APB1RST_WWDTRST_Pos) /*!< 0x00000800 */ +#define CRM_APB1RST_WWDTRST CRM_APB1RST_WWDTRST_Msk /*!< WWDT reset */ +#define CRM_APB1RST_SPI3RST_Pos (15U) +#define CRM_APB1RST_SPI3RST_Msk (0x1U << CRM_APB1RST_SPI3RST_Pos) /*!< 0x00008000 */ +#define CRM_APB1RST_SPI3RST CRM_APB1RST_SPI3RST_Msk /*!< SPI3 reset */ +#define CRM_APB1RST_USART2RST_Pos (17U) +#define CRM_APB1RST_USART2RST_Msk (0x1U << CRM_APB1RST_USART2RST_Pos) /*!< 0x00020000 */ +#define CRM_APB1RST_USART2RST CRM_APB1RST_USART2RST_Msk /*!< USART2 reset */ +#define CRM_APB1RST_USART3RST_Pos (18U) +#define CRM_APB1RST_USART3RST_Msk (0x1U << CRM_APB1RST_USART3RST_Pos) /*!< 0x00040000 */ +#define CRM_APB1RST_USART3RST CRM_APB1RST_USART3RST_Msk /*!< USART3 reset */ +#define CRM_APB1RST_USART4RST_Pos (19U) +#define CRM_APB1RST_USART4RST_Msk (0x1U << CRM_APB1RST_USART4RST_Pos) /*!< 0x00080000 */ +#define CRM_APB1RST_USART4RST CRM_APB1RST_USART4RST_Msk /*!< USART4 reset */ +#define CRM_APB1RST_USART5RST_Pos (20U) +#define CRM_APB1RST_USART5RST_Msk (0x1U << CRM_APB1RST_USART5RST_Pos) /*!< 0x00100000 */ +#define CRM_APB1RST_USART5RST CRM_APB1RST_USART5RST_Msk /*!< USART5 reset */ +#define CRM_APB1RST_I2C1RST_Pos (21U) +#define CRM_APB1RST_I2C1RST_Msk (0x1U << CRM_APB1RST_I2C1RST_Pos) /*!< 0x00200000 */ +#define CRM_APB1RST_I2C1RST CRM_APB1RST_I2C1RST_Msk /*!< I2C1 reset */ +#define CRM_APB1RST_I2C2RST_Pos (22U) +#define CRM_APB1RST_I2C2RST_Msk (0x1U << CRM_APB1RST_I2C2RST_Pos) /*!< 0x00400000 */ +#define CRM_APB1RST_I2C2RST CRM_APB1RST_I2C2RST_Msk /*!< I2C2 reset */ +#define CRM_APB1RST_I2C3RST_Pos (23U) +#define CRM_APB1RST_I2C3RST_Msk (0x1U << CRM_APB1RST_I2C3RST_Pos) /*!< 0x00800000 */ +#define CRM_APB1RST_I2C3RST CRM_APB1RST_I2C3RST_Msk /*!< I2C3 reset */ +#define CRM_APB1RST_CAN1RST_Pos (25U) +#define CRM_APB1RST_CAN1RST_Msk (0x1U << CRM_APB1RST_CAN1RST_Pos) /*!< 0x02000000 */ +#define CRM_APB1RST_CAN1RST CRM_APB1RST_CAN1RST_Msk /*!< CAN1 reset */ +#define CRM_APB1RST_PWCRST_Pos (28U) +#define CRM_APB1RST_PWCRST_Msk (0x1U << CRM_APB1RST_PWCRST_Pos) /*!< 0x10000000 */ +#define CRM_APB1RST_PWCRST CRM_APB1RST_PWCRST_Msk /*!< PWC reset */ +#define CRM_APB1RST_UART7RST_Pos (30U) +#define CRM_APB1RST_UART7RST_Msk (0x1U << CRM_APB1RST_UART7RST_Pos) /*!< 0x40000000 */ +#define CRM_APB1RST_UART7RST CRM_APB1RST_UART7RST_Msk /*!< UART7 reset */ + +/***************** Bit definition for CRM_APB2RST register ******************/ +#define CRM_APB2RST_TMR1RST_Pos (0U) +#define CRM_APB2RST_TMR1RST_Msk (0x1U << CRM_APB2RST_TMR1RST_Pos) /*!< 0x00000001 */ +#define CRM_APB2RST_TMR1RST CRM_APB2RST_TMR1RST_Msk /*!< TMR1 reset */ +#define CRM_APB2RST_USART1RST_Pos (4U) +#define CRM_APB2RST_USART1RST_Msk (0x1U << CRM_APB2RST_USART1RST_Pos) /*!< 0x00000010 */ +#define CRM_APB2RST_USART1RST CRM_APB2RST_USART1RST_Msk /*!< USART1 reset */ +#define CRM_APB2RST_USART6RST_Pos (5U) +#define CRM_APB2RST_USART6RST_Msk (0x1U << CRM_APB2RST_USART6RST_Pos) /*!< 0x00000020 */ +#define CRM_APB2RST_USART6RST CRM_APB2RST_USART6RST_Msk /*!< USART6 reset */ +#define CRM_APB2RST_ADCRST_Pos (8U) +#define CRM_APB2RST_ADCRST_Msk (0x1U << CRM_APB2RST_ADCRST_Pos) /*!< 0x00000100 */ +#define CRM_APB2RST_ADCRST CRM_APB2RST_ADCRST_Msk /*!< ADC reset */ +#define CRM_APB2RST_SPI1RST_Pos (12U) +#define CRM_APB2RST_SPI1RST_Msk (0x1U << CRM_APB2RST_SPI1RST_Pos) /*!< 0x00001000 */ +#define CRM_APB2RST_SPI1RST CRM_APB2RST_SPI1RST_Msk /*!< SPI1 reset */ +#define CRM_APB2RST_SCFGRST_Pos (14U) +#define CRM_APB2RST_SCFGRST_Msk (0x1U << CRM_APB2RST_SCFGRST_Pos) /*!< 0x00004000 */ +#define CRM_APB2RST_SCFGRST CRM_APB2RST_SCFGRST_Msk /*!< SCFG reset */ +#define CRM_APB2RST_EXINTRST_Pos (15U) +#define CRM_APB2RST_EXINTRST_Msk (0x1U << CRM_APB2RST_EXINTRST_Pos) /*!< 0x00008000 */ +#define CRM_APB2RST_EXINTRST CRM_APB2RST_EXINTRST_Msk /*!< EXINT reset */ +#define CRM_APB2RST_TMR9RST_Pos (16U) +#define CRM_APB2RST_TMR9RST_Msk (0x1U << CRM_APB2RST_TMR9RST_Pos) /*!< 0x00010000 */ +#define CRM_APB2RST_TMR9RST CRM_APB2RST_TMR9RST_Msk /*!< TMR9 reset */ +#define CRM_APB2RST_TMR10RST_Pos (17U) +#define CRM_APB2RST_TMR10RST_Msk (0x1U << CRM_APB2RST_TMR10RST_Pos) /*!< 0x00020000 */ +#define CRM_APB2RST_TMR10RST CRM_APB2RST_TMR10RST_Msk /*!< TMR10 reset */ +#define CRM_APB2RST_TMR11RST_Pos (18U) +#define CRM_APB2RST_TMR11RST_Msk (0x1U << CRM_APB2RST_TMR11RST_Pos) /*!< 0x00040000 */ +#define CRM_APB2RST_TMR11RST CRM_APB2RST_TMR11RST_Msk /*!< TMR11 reset */ +#define CRM_APB2RST_I2SF5RST_Pos (20U) +#define CRM_APB2RST_I2SF5RST_Msk (0x1U << CRM_APB2RST_I2SF5RST_Pos) /*!< 0x00100000 */ +#define CRM_APB2RST_I2SF5RST CRM_APB2RST_I2SF5RST_Msk /*!< I2SF5 reset */ +#define CRM_APB2RST_ACCRST_Pos (29U) +#define CRM_APB2RST_ACCRST_Msk (0x1U << CRM_APB2RST_ACCRST_Pos) /*!< 0x20000000 */ +#define CRM_APB2RST_ACCRST CRM_APB2RST_ACCRST_Msk /*!< ACC reset */ + +/****************** Bit definition for CRM_AHBEN1 register ******************/ +#define CRM_AHBEN1_GPIOAEN_Pos (0U) +#define CRM_AHBEN1_GPIOAEN_Msk (0x1U << CRM_AHBEN1_GPIOAEN_Pos) /*!< 0x00000001 */ +#define CRM_AHBEN1_GPIOAEN CRM_AHBEN1_GPIOAEN_Msk /*!< IO port A clock enable */ +#define CRM_AHBEN1_GPIOBEN_Pos (1U) +#define CRM_AHBEN1_GPIOBEN_Msk (0x1U << CRM_AHBEN1_GPIOBEN_Pos) /*!< 0x00000002 */ +#define CRM_AHBEN1_GPIOBEN CRM_AHBEN1_GPIOBEN_Msk /*!< IO port B clock enable */ +#define CRM_AHBEN1_GPIOCEN_Pos (2U) +#define CRM_AHBEN1_GPIOCEN_Msk (0x1U << CRM_AHBEN1_GPIOCEN_Pos) /*!< 0x00000004 */ +#define CRM_AHBEN1_GPIOCEN CRM_AHBEN1_GPIOCEN_Msk /*!< IO port C clock enable */ +#define CRM_AHBEN1_GPIODEN_Pos (3U) +#define CRM_AHBEN1_GPIODEN_Msk (0x1U << CRM_AHBEN1_GPIODEN_Pos) /*!< 0x00000008 */ +#define CRM_AHBEN1_GPIODEN CRM_AHBEN1_GPIODEN_Msk /*!< IO port D clock enable */ +#define CRM_AHBEN1_GPIOFEN_Pos (5U) +#define CRM_AHBEN1_GPIOFEN_Msk (0x1U << CRM_AHBEN1_GPIOFEN_Pos) /*!< 0x00000020 */ +#define CRM_AHBEN1_GPIOFEN CRM_AHBEN1_GPIOFEN_Msk /*!< IO port F clock enable */ +#define CRM_AHBEN1_CRCEN_Pos (12U) +#define CRM_AHBEN1_CRCEN_Msk (0x1U << CRM_AHBEN1_CRCEN_Pos) /*!< 0x00001000 */ +#define CRM_AHBEN1_CRCEN CRM_AHBEN1_CRCEN_Msk /*!< CRC clock enable */ +#define CRM_AHBEN1_DMA1EN_Pos (22U) +#define CRM_AHBEN1_DMA1EN_Msk (0x1U << CRM_AHBEN1_DMA1EN_Pos) /*!< 0x00400000 */ +#define CRM_AHBEN1_DMA1EN CRM_AHBEN1_DMA1EN_Msk /*!< DMA1 clock enable */ +#define CRM_AHBEN1_DMA2EN_Pos (24U) +#define CRM_AHBEN1_DMA2EN_Msk (0x1U << CRM_AHBEN1_DMA2EN_Pos) /*!< 0x01000000 */ +#define CRM_AHBEN1_DMA2EN CRM_AHBEN1_DMA2EN_Msk /*!< DMA2 clock enable */ +#define CRM_AHBEN1_OTGHSEN_Pos (29U) +#define CRM_AHBEN1_OTGHSEN_Msk (0x1U << CRM_AHBEN1_OTGHSEN_Pos) /*!< 0x20000000 */ +#define CRM_AHBEN1_OTGHSEN CRM_AHBEN1_OTGHSEN_Msk /*!< OTGHS clock enable (F405 only) */ + +/****************** Bit definition for CRM_AHBEN2 register ******************/ +#define CRM_AHBEN2_OTGFSEN_Pos (7U) +#define CRM_AHBEN2_OTGFSEN_Msk (0x1U << CRM_AHBEN2_OTGFSEN_Pos) /*!< 0x00000080 */ +#define CRM_AHBEN2_OTGFSEN CRM_AHBEN2_OTGFSEN_Msk /*!< OTGFS clock enable */ + +/****************** Bit definition for CRM_AHBEN3 register ******************/ +#define CRM_AHBEN3_QSPI1EN_Pos (1U) +#define CRM_AHBEN3_QSPI1EN_Msk (0x1U << CRM_AHBEN3_QSPI1EN_Pos) /*!< 0x00000002 */ +#define CRM_AHBEN3_QSPI1EN CRM_AHBEN3_QSPI1EN_Msk /*!< QSPI1 clock enable */ + +/****************** Bit definition for CRM_APB1EN register ******************/ +#define CRM_APB1EN_TMR2EN_Pos (0U) +#define CRM_APB1EN_TMR2EN_Msk (0x1U << CRM_APB1EN_TMR2EN_Pos) /*!< 0x00000001 */ +#define CRM_APB1EN_TMR2EN CRM_APB1EN_TMR2EN_Msk /*!< TMR2 clock enable */ +#define CRM_APB1EN_TMR3EN_Pos (1U) +#define CRM_APB1EN_TMR3EN_Msk (0x1U << CRM_APB1EN_TMR3EN_Pos) /*!< 0x00000002 */ +#define CRM_APB1EN_TMR3EN CRM_APB1EN_TMR3EN_Msk /*!< TMR3 clock enable */ +#define CRM_APB1EN_TMR4EN_Pos (2U) +#define CRM_APB1EN_TMR4EN_Msk (0x1U << CRM_APB1EN_TMR4EN_Pos) /*!< 0x00000004 */ +#define CRM_APB1EN_TMR4EN CRM_APB1EN_TMR4EN_Msk /*!< TMR4 clock enable */ +#define CRM_APB1EN_TMR6EN_Pos (4U) +#define CRM_APB1EN_TMR6EN_Msk (0x1U << CRM_APB1EN_TMR6EN_Pos) /*!< 0x00000010 */ +#define CRM_APB1EN_TMR6EN CRM_APB1EN_TMR6EN_Msk /*!< TMR6 clock enable */ +#define CRM_APB1EN_TMR7EN_Pos (5U) +#define CRM_APB1EN_TMR7EN_Msk (0x1U << CRM_APB1EN_TMR7EN_Pos) /*!< 0x00000020 */ +#define CRM_APB1EN_TMR7EN CRM_APB1EN_TMR7EN_Msk /*!< TMR7 clock enable */ +#define CRM_APB1EN_TMR13EN_Pos (7U) +#define CRM_APB1EN_TMR13EN_Msk (0x1U << CRM_APB1EN_TMR13EN_Pos) /*!< 0x00000080 */ +#define CRM_APB1EN_TMR13EN CRM_APB1EN_TMR13EN_Msk /*!< TMR13 clock enable */ +#define CRM_APB1EN_TMR14EN_Pos (8U) +#define CRM_APB1EN_TMR14EN_Msk (0x1U << CRM_APB1EN_TMR14EN_Pos) /*!< 0x00000100 */ +#define CRM_APB1EN_TMR14EN CRM_APB1EN_TMR14EN_Msk /*!< TMR14 clock enable */ +#define CRM_APB1EN_WWDTEN_Pos (11U) +#define CRM_APB1EN_WWDTEN_Msk (0x1U << CRM_APB1EN_WWDTEN_Pos) /*!< 0x00000800 */ +#define CRM_APB1EN_WWDTEN CRM_APB1EN_WWDTEN_Msk /*!< WWDT clock enable */ +#define CRM_APB1EN_SPI3EN_Pos (15U) +#define CRM_APB1EN_SPI3EN_Msk (0x1U << CRM_APB1EN_SPI3EN_Pos) /*!< 0x00008000 */ +#define CRM_APB1EN_SPI3EN CRM_APB1EN_SPI3EN_Msk /*!< SPI3 clock enable */ +#define CRM_APB1EN_USART2EN_Pos (17U) +#define CRM_APB1EN_USART2EN_Msk (0x1U << CRM_APB1EN_USART2EN_Pos) /*!< 0x00020000 */ +#define CRM_APB1EN_USART2EN CRM_APB1EN_USART2EN_Msk /*!< USART2 clock enable */ +#define CRM_APB1EN_USART3EN_Pos (18U) +#define CRM_APB1EN_USART3EN_Msk (0x1U << CRM_APB1EN_USART3EN_Pos) /*!< 0x00040000 */ +#define CRM_APB1EN_USART3EN CRM_APB1EN_USART3EN_Msk /*!< USART3 clock enable */ +#define CRM_APB1EN_USART4EN_Pos (19U) +#define CRM_APB1EN_USART4EN_Msk (0x1U << CRM_APB1EN_USART4EN_Pos) /*!< 0x00080000 */ +#define CRM_APB1EN_USART4EN CRM_APB1EN_USART4EN_Msk /*!< USART4 clock enable */ +#define CRM_APB1EN_USART5EN_Pos (20U) +#define CRM_APB1EN_USART5EN_Msk (0x1U << CRM_APB1EN_USART5EN_Pos) /*!< 0x00100000 */ +#define CRM_APB1EN_USART5EN CRM_APB1EN_USART5EN_Msk /*!< USART5 clock enable */ +#define CRM_APB1EN_I2C1EN_Pos (21U) +#define CRM_APB1EN_I2C1EN_Msk (0x1U << CRM_APB1EN_I2C1EN_Pos) /*!< 0x00200000 */ +#define CRM_APB1EN_I2C1EN CRM_APB1EN_I2C1EN_Msk /*!< I2C1 clock enable */ +#define CRM_APB1EN_I2C2EN_Pos (22U) +#define CRM_APB1EN_I2C2EN_Msk (0x1U << CRM_APB1EN_I2C2EN_Pos) /*!< 0x00400000 */ +#define CRM_APB1EN_I2C2EN CRM_APB1EN_I2C2EN_Msk /*!< I2C2 clock enable */ +#define CRM_APB1EN_I2C3EN_Pos (23U) +#define CRM_APB1EN_I2C3EN_Msk (0x1U << CRM_APB1EN_I2C3EN_Pos) /*!< 0x00800000 */ +#define CRM_APB1EN_I2C3EN CRM_APB1EN_I2C3EN_Msk /*!< I2C3 clock enable */ +#define CRM_APB1EN_CAN1EN_Pos (25U) +#define CRM_APB1EN_CAN1EN_Msk (0x1U << CRM_APB1EN_CAN1EN_Pos) /*!< 0x02000000 */ +#define CRM_APB1EN_CAN1EN CRM_APB1EN_CAN1EN_Msk /*!< CAN1 clock enable */ +#define CRM_APB1EN_PWCEN_Pos (28U) +#define CRM_APB1EN_PWCEN_Msk (0x1U << CRM_APB1EN_PWCEN_Pos) /*!< 0x10000000 */ +#define CRM_APB1EN_PWCEN CRM_APB1EN_PWCEN_Msk /*!< Power control clock enable */ +#define CRM_APB1EN_UART7EN_Pos (30U) +#define CRM_APB1EN_UART7EN_Msk (0x1U << CRM_APB1EN_UART7EN_Pos) /*!< 0x40000000 */ +#define CRM_APB1EN_UART7EN CRM_APB1EN_UART7EN_Msk /*!< UART7 clock enable */ + +/****************** Bit definition for CRM_APB2EN register ******************/ +#define CRM_APB2EN_TMR1EN_Pos (0U) +#define CRM_APB2EN_TMR1EN_Msk (0x1U << CRM_APB2EN_TMR1EN_Pos) /*!< 0x00000001 */ +#define CRM_APB2EN_TMR1EN CRM_APB2EN_TMR1EN_Msk /*!< TMR1 clock enable */ +#define CRM_APB2EN_USART1EN_Pos (4U) +#define CRM_APB2EN_USART1EN_Msk (0x1U << CRM_APB2EN_USART1EN_Pos) /*!< 0x00000010 */ +#define CRM_APB2EN_USART1EN CRM_APB2EN_USART1EN_Msk /*!< USART1 clock enable */ +#define CRM_APB2EN_USART6EN_Pos (5U) +#define CRM_APB2EN_USART6EN_Msk (0x1U << CRM_APB2EN_USART6EN_Pos) /*!< 0x00000020 */ +#define CRM_APB2EN_USART6EN CRM_APB2EN_USART6EN_Msk /*!< USART6 clock enable */ +#define CRM_APB2EN_ADC1EN_Pos (8U) +#define CRM_APB2EN_ADC1EN_Msk (0x1U << CRM_APB2EN_ADC1EN_Pos) /*!< 0x00000100 */ +#define CRM_APB2EN_ADC1EN CRM_APB2EN_ADC1EN_Msk /*!< ADC1 clock enable */ +#define CRM_APB2EN_SPI1EN_Pos (12U) +#define CRM_APB2EN_SPI1EN_Msk (0x1U << CRM_APB2EN_SPI1EN_Pos) /*!< 0x00001000 */ +#define CRM_APB2EN_SPI1EN CRM_APB2EN_SPI1EN_Msk /*!< SPI1 clock enable */ +#define CRM_APB2EN_SCFGEN_Pos (14U) +#define CRM_APB2EN_SCFGEN_Msk (0x1U << CRM_APB2EN_SCFGEN_Pos) /*!< 0x00004000 */ +#define CRM_APB2EN_SCFGEN CRM_APB2EN_SCFGEN_Msk /*!< SCFG clock enable */ +#define CRM_APB2EN_TMR9EN_Pos (16U) +#define CRM_APB2EN_TMR9EN_Msk (0x1U << CRM_APB2EN_TMR9EN_Pos) /*!< 0x00010000 */ +#define CRM_APB2EN_TMR9EN CRM_APB2EN_TMR9EN_Msk /*!< TMR9 clock enable */ +#define CRM_APB2EN_TMR10EN_Pos (17U) +#define CRM_APB2EN_TMR10EN_Msk (0x1U << CRM_APB2EN_TMR10EN_Pos) /*!< 0x00020000 */ +#define CRM_APB2EN_TMR10EN CRM_APB2EN_TMR10EN_Msk /*!< TMR10 clock enable */ +#define CRM_APB2EN_TMR11EN_Pos (18U) +#define CRM_APB2EN_TMR11EN_Msk (0x1U << CRM_APB2EN_TMR11EN_Pos) /*!< 0x00040000 */ +#define CRM_APB2EN_TMR11EN CRM_APB2EN_TMR11EN_Msk /*!< TMR11 clock enable */ +#define CRM_APB2EN_I2SF5EN_Pos (20U) +#define CRM_APB2EN_I2SF5EN_Msk (0x1U << CRM_APB2EN_I2SF5EN_Pos) /*!< 0x00100000 */ +#define CRM_APB2EN_I2SF5EN CRM_APB2EN_I2SF5EN_Msk /*!< I2SF5 clock enable */ +#define CRM_APB2EN_ACCEN_Pos (29U) +#define CRM_APB2EN_ACCEN_Msk (0x1U << CRM_APB2EN_ACCEN_Pos) /*!< 0x20000000 */ +#define CRM_APB2EN_ACCEN CRM_APB2EN_ACCEN_Msk /*!< ACC clock enable */ + +/***************** Bit definition for CRM_AHBLPEN1 register *****************/ +#define CRM_AHBLPEN1_GPIOALPEN_Pos (0U) +#define CRM_AHBLPEN1_GPIOALPEN_Msk (0x1U << CRM_AHBLPEN1_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define CRM_AHBLPEN1_GPIOALPEN CRM_AHBLPEN1_GPIOALPEN_Msk /*!< IO port A clock enable in sleep mode */ +#define CRM_AHBLPEN1_GPIOBLPEN_Pos (1U) +#define CRM_AHBLPEN1_GPIOBLPEN_Msk (0x1U << CRM_AHBLPEN1_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define CRM_AHBLPEN1_GPIOBLPEN CRM_AHBLPEN1_GPIOBLPEN_Msk /*!< IO port B clock enable in sleep mode */ +#define CRM_AHBLPEN1_GPIOCLPEN_Pos (2U) +#define CRM_AHBLPEN1_GPIOCLPEN_Msk (0x1U << CRM_AHBLPEN1_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define CRM_AHBLPEN1_GPIOCLPEN CRM_AHBLPEN1_GPIOCLPEN_Msk /*!< IO port C clock enable in sleep mode */ +#define CRM_AHBLPEN1_GPIODLPEN_Pos (3U) +#define CRM_AHBLPEN1_GPIODLPEN_Msk (0x1U << CRM_AHBLPEN1_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define CRM_AHBLPEN1_GPIODLPEN CRM_AHBLPEN1_GPIODLPEN_Msk /*!< IO port D clock enable in sleep mode */ +#define CRM_AHBLPEN1_GPIOFLPEN_Pos (5U) +#define CRM_AHBLPEN1_GPIOFLPEN_Msk (0x1U << CRM_AHBLPEN1_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define CRM_AHBLPEN1_GPIOFLPEN CRM_AHBLPEN1_GPIOFLPEN_Msk /*!< IO port F clock enable in sleep mode */ +#define CRM_AHBLPEN1_CRCLPEN_Pos (12U) +#define CRM_AHBLPEN1_CRCLPEN_Msk (0x1U << CRM_AHBLPEN1_CRCLPEN_Pos) /*!< 0x00001000 */ +#define CRM_AHBLPEN1_CRCLPEN CRM_AHBLPEN1_CRCLPEN_Msk /*!< CRC clock enable in sleep mode */ +#define CRM_AHBLPEN1_FLASHLPEN_Pos (15U) +#define CRM_AHBLPEN1_FLASHLPEN_Msk (0x1U << CRM_AHBLPEN1_FLASHLPEN_Pos) /*!< 0x00008000 */ +#define CRM_AHBLPEN1_FLASHLPEN CRM_AHBLPEN1_FLASHLPEN_Msk /*!< FLASH clock enable in sleep mode */ +#define CRM_AHBLPEN1_SRAMLPEN_Pos (16U) +#define CRM_AHBLPEN1_SRAMLPEN_Msk (0x1U << CRM_AHBLPEN1_SRAMLPEN_Pos) /*!< 0x00010000 */ +#define CRM_AHBLPEN1_SRAMLPEN CRM_AHBLPEN1_SRAMLPEN_Msk /*!< SRAM clock enable in sleep mode */ +#define CRM_AHBLPEN1_DMA1LPEN_Pos (22U) +#define CRM_AHBLPEN1_DMA1LPEN_Msk (0x1U << CRM_AHBLPEN1_DMA1LPEN_Pos) /*!< 0x00400000 */ +#define CRM_AHBLPEN1_DMA1LPEN CRM_AHBLPEN1_DMA1LPEN_Msk /*!< DMA1 clock enable in sleep mode */ +#define CRM_AHBLPEN1_DMA2LPEN_Pos (24U) +#define CRM_AHBLPEN1_DMA2LPEN_Msk (0x1U << CRM_AHBLPEN1_DMA2LPEN_Pos) /*!< 0x01000000 */ +#define CRM_AHBLPEN1_DMA2LPEN CRM_AHBLPEN1_DMA2LPEN_Msk /*!< DMA2 clock enable in sleep mode */ +#define CRM_AHBLPEN1_OTGHSLPEN_Pos (29U) +#define CRM_AHBLPEN1_OTGHSLPEN_Msk (0x1U << CRM_AHBLPEN1_OTGHSLPEN_Pos) /*!< 0x20000000 */ +#define CRM_AHBLPEN1_OTGHSLPEN CRM_AHBLPEN1_OTGHSLPEN_Msk /*!< OTGHS clock enable in sleep mode (F405 only) */ + +/***************** Bit definition for CRM_AHBLPEN2 register *****************/ +#define CRM_AHBLPEN2_OTGFSLPEN_Pos (7U) +#define CRM_AHBLPEN2_OTGFSLPEN_Msk (0x1U << CRM_AHBLPEN2_OTGFSLPEN_Pos) /*!< 0x00000080 */ +#define CRM_AHBLPEN2_OTGFSLPEN CRM_AHBLPEN2_OTGFSLPEN_Msk /*!< OTGFS clock enable in sleep mode */ + +/***************** Bit definition for CRM_AHBLPEN3 register *****************/ +#define CRM_AHBLPEN3_QSPI1LPEN_Pos (1U) +#define CRM_AHBLPEN3_QSPI1LPEN_Msk (0x1U << CRM_AHBLPEN3_QSPI1LPEN_Pos) /*!< 0x00000002 */ +#define CRM_AHBLPEN3_QSPI1LPEN CRM_AHBLPEN3_QSPI1LPEN_Msk /*!< QSPI1 clock enable in sleep mode */ + +/***************** Bit definition for CRM_APB1LPEN register *****************/ +#define CRM_APB1LPEN_TMR2LPEN_Pos (0U) +#define CRM_APB1LPEN_TMR2LPEN_Msk (0x1U << CRM_APB1LPEN_TMR2LPEN_Pos) /*!< 0x00000001 */ +#define CRM_APB1LPEN_TMR2LPEN CRM_APB1LPEN_TMR2LPEN_Msk /*!< TMR2 clock enable in sleep mode */ +#define CRM_APB1LPEN_TMR3LPEN_Pos (1U) +#define CRM_APB1LPEN_TMR3LPEN_Msk (0x1U << CRM_APB1LPEN_TMR3LPEN_Pos) /*!< 0x00000002 */ +#define CRM_APB1LPEN_TMR3LPEN CRM_APB1LPEN_TMR3LPEN_Msk /*!< TMR3 clock enable in sleep mode */ +#define CRM_APB1LPEN_TMR4LPEN_Pos (2U) +#define CRM_APB1LPEN_TMR4LPEN_Msk (0x1U << CRM_APB1LPEN_TMR4LPEN_Pos) /*!< 0x00000004 */ +#define CRM_APB1LPEN_TMR4LPEN CRM_APB1LPEN_TMR4LPEN_Msk /*!< TMR4 clock enable in sleep mode */ +#define CRM_APB1LPEN_TMR6LPEN_Pos (4U) +#define CRM_APB1LPEN_TMR6LPEN_Msk (0x1U << CRM_APB1LPEN_TMR6LPEN_Pos) /*!< 0x00000010 */ +#define CRM_APB1LPEN_TMR6LPEN CRM_APB1LPEN_TMR6LPEN_Msk /*!< TMR6 clock enable in sleep mode */ +#define CRM_APB1LPEN_TMR7LPEN_Pos (5U) +#define CRM_APB1LPEN_TMR7LPEN_Msk (0x1U << CRM_APB1LPEN_TMR7LPEN_Pos) /*!< 0x00000020 */ +#define CRM_APB1LPEN_TMR7LPEN CRM_APB1LPEN_TMR7LPEN_Msk /*!< TMR7 clock enable in sleep mode */ +#define CRM_APB1LPEN_TMR13LPEN_Pos (7U) +#define CRM_APB1LPEN_TMR13LPEN_Msk (0x1U << CRM_APB1LPEN_TMR13LPEN_Pos) /*!< 0x00000080 */ +#define CRM_APB1LPEN_TMR13LPEN CRM_APB1LPEN_TMR13LPEN_Msk /*!< TMR13 clock enable in sleep mode */ +#define CRM_APB1LPEN_TMR14LPEN_Pos (8U) +#define CRM_APB1LPEN_TMR14LPEN_Msk (0x1U << CRM_APB1LPEN_TMR14LPEN_Pos) /*!< 0x00000100 */ +#define CRM_APB1LPEN_TMR14LPEN CRM_APB1LPEN_TMR14LPEN_Msk /*!< TMR14 clock enable in sleep mode */ +#define CRM_APB1LPEN_WWDTLPEN_Pos (11U) +#define CRM_APB1LPEN_WWDTLPEN_Msk (0x1U << CRM_APB1LPEN_WWDTLPEN_Pos) /*!< 0x00000800 */ +#define CRM_APB1LPEN_WWDTLPEN CRM_APB1LPEN_WWDTLPEN_Msk /*!< WWDT clock enable in sleep mode */ +#define CRM_APB1LPEN_SPI3LPEN_Pos (15U) +#define CRM_APB1LPEN_SPI3LPEN_Msk (0x1U << CRM_APB1LPEN_SPI3LPEN_Pos) /*!< 0x00008000 */ +#define CRM_APB1LPEN_SPI3LPEN CRM_APB1LPEN_SPI3LPEN_Msk /*!< SPI3 clock enable in sleep mode */ +#define CRM_APB1LPEN_USART2LPEN_Pos (17U) +#define CRM_APB1LPEN_USART2LPEN_Msk (0x1U << CRM_APB1LPEN_USART2LPEN_Pos) /*!< 0x00020000 */ +#define CRM_APB1LPEN_USART2LPEN CRM_APB1LPEN_USART2LPEN_Msk /*!< USART2 clock enable in sleep mode */ +#define CRM_APB1LPEN_USART3LPEN_Pos (18U) +#define CRM_APB1LPEN_USART3LPEN_Msk (0x1U << CRM_APB1LPEN_USART3LPEN_Pos) /*!< 0x00040000 */ +#define CRM_APB1LPEN_USART3LPEN CRM_APB1LPEN_USART3LPEN_Msk /*!< USART3 clock enable in sleep mode */ +#define CRM_APB1LPEN_USART4LPEN_Pos (19U) +#define CRM_APB1LPEN_USART4LPEN_Msk (0x1U << CRM_APB1LPEN_USART4LPEN_Pos) /*!< 0x00080000 */ +#define CRM_APB1LPEN_USART4LPEN CRM_APB1LPEN_USART4LPEN_Msk /*!< USART4 clock enable in sleep mode */ +#define CRM_APB1LPEN_USART5LPEN_Pos (20U) +#define CRM_APB1LPEN_USART5LPEN_Msk (0x1U << CRM_APB1LPEN_USART5LPEN_Pos) /*!< 0x00100000 */ +#define CRM_APB1LPEN_USART5LPEN CRM_APB1LPEN_USART5LPEN_Msk /*!< USART5 clock enable in sleep mode */ +#define CRM_APB1LPEN_I2C1LPEN_Pos (21U) +#define CRM_APB1LPEN_I2C1LPEN_Msk (0x1U << CRM_APB1LPEN_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define CRM_APB1LPEN_I2C1LPEN CRM_APB1LPEN_I2C1LPEN_Msk /*!< I2C1 clock enable in sleep mode */ +#define CRM_APB1LPEN_I2C2LPEN_Pos (22U) +#define CRM_APB1LPEN_I2C2LPEN_Msk (0x1U << CRM_APB1LPEN_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define CRM_APB1LPEN_I2C2LPEN CRM_APB1LPEN_I2C2LPEN_Msk /*!< I2C2 clock enable in sleep mode */ +#define CRM_APB1LPEN_I2C3LPEN_Pos (23U) +#define CRM_APB1LPEN_I2C3LPEN_Msk (0x1U << CRM_APB1LPEN_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define CRM_APB1LPEN_I2C3LPEN CRM_APB1LPEN_I2C3LPEN_Msk /*!< I2C3 clock enable in sleep mode */ +#define CRM_APB1LPEN_CAN1LPEN_Pos (25U) +#define CRM_APB1LPEN_CAN1LPEN_Msk (0x1U << CRM_APB1LPEN_CAN1LPEN_Pos) /*!< 0x02000000 */ +#define CRM_APB1LPEN_CAN1LPEN CRM_APB1LPEN_CAN1LPEN_Msk /*!< CAN1 clock enable in sleep mode */ +#define CRM_APB1LPEN_PWCLPEN_Pos (28U) +#define CRM_APB1LPEN_PWCLPEN_Msk (0x1U << CRM_APB1LPEN_PWCLPEN_Pos) /*!< 0x10000000 */ +#define CRM_APB1LPEN_PWCLPEN CRM_APB1LPEN_PWCLPEN_Msk /*!< Power control clock enable in sleep mode */ +#define CRM_APB1LPEN_UART7LPEN_Pos (30U) +#define CRM_APB1LPEN_UART7LPEN_Msk (0x1U << CRM_APB1LPEN_UART7LPEN_Pos) /*!< 0x40000000 */ +#define CRM_APB1LPEN_UART7LPEN CRM_APB1LPEN_UART7LPEN_Msk /*!< UART7 clock enable in sleep mode */ + +/***************** Bit definition for CRM_APB2LPEN register *****************/ +#define CRM_APB2LPEN_TMR1LPEN_Pos (0U) +#define CRM_APB2LPEN_TMR1LPEN_Msk (0x1U << CRM_APB2LPEN_TMR1LPEN_Pos) /*!< 0x00000001 */ +#define CRM_APB2LPEN_TMR1LPEN CRM_APB2LPEN_TMR1LPEN_Msk /*!< TMR1 clock enable in sleep mode */ +#define CRM_APB2LPEN_USART1LPEN_Pos (4U) +#define CRM_APB2LPEN_USART1LPEN_Msk (0x1U << CRM_APB2LPEN_USART1LPEN_Pos) /*!< 0x00000010 */ +#define CRM_APB2LPEN_USART1LPEN CRM_APB2LPEN_USART1LPEN_Msk /*!< USART1 clock enable in sleep mode */ +#define CRM_APB2LPEN_USART6LPEN_Pos (5U) +#define CRM_APB2LPEN_USART6LPEN_Msk (0x1U << CRM_APB2LPEN_USART6LPEN_Pos) /*!< 0x00000020 */ +#define CRM_APB2LPEN_USART6LPEN CRM_APB2LPEN_USART6LPEN_Msk /*!< USART6 clock enable in sleep mode */ +#define CRM_APB2LPEN_ADC1LPEN_Pos (8U) +#define CRM_APB2LPEN_ADC1LPEN_Msk (0x1U << CRM_APB2LPEN_ADC1LPEN_Pos) /*!< 0x00000100 */ +#define CRM_APB2LPEN_ADC1LPEN CRM_APB2LPEN_ADC1LPEN_Msk /*!< ADC1 clock enable in sleep mode */ +#define CRM_APB2LPEN_SPI1LPEN_Pos (12U) +#define CRM_APB2LPEN_SPI1LPEN_Msk (0x1U << CRM_APB2LPEN_SPI1LPEN_Pos) /*!< 0x00001000 */ +#define CRM_APB2LPEN_SPI1LPEN CRM_APB2LPEN_SPI1LPEN_Msk /*!< SPI1 clock enable in sleep mode */ +#define CRM_APB2LPEN_SCFGLPEN_Pos (14U) +#define CRM_APB2LPEN_SCFGLPEN_Msk (0x1U << CRM_APB2LPEN_SCFGLPEN_Pos) /*!< 0x00004000 */ +#define CRM_APB2LPEN_SCFGLPEN CRM_APB2LPEN_SCFGLPEN_Msk /*!< SCFG clock enable in sleep mode */ +#define CRM_APB2LPEN_TMR9LPEN_Pos (16U) +#define CRM_APB2LPEN_TMR9LPEN_Msk (0x1U << CRM_APB2LPEN_TMR9LPEN_Pos) /*!< 0x00010000 */ +#define CRM_APB2LPEN_TMR9LPEN CRM_APB2LPEN_TMR9LPEN_Msk /*!< TMR9 clock enable in sleep mode */ +#define CRM_APB2LPEN_TMR10LPEN_Pos (17U) +#define CRM_APB2LPEN_TMR10LPEN_Msk (0x1U << CRM_APB2LPEN_TMR10LPEN_Pos) /*!< 0x00020000 */ +#define CRM_APB2LPEN_TMR10LPEN CRM_APB2LPEN_TMR10LPEN_Msk /*!< TMR10 clock enable in sleep mode */ +#define CRM_APB2LPEN_TMR11LPEN_Pos (18U) +#define CRM_APB2LPEN_TMR11LPEN_Msk (0x1U << CRM_APB2LPEN_TMR11LPEN_Pos) /*!< 0x00040000 */ +#define CRM_APB2LPEN_TMR11LPEN CRM_APB2LPEN_TMR11LPEN_Msk /*!< TMR11 clock enable in sleep mode */ +#define CRM_APB2LPEN_I2SF5LPEN_Pos (20U) +#define CRM_APB2LPEN_I2SF5LPEN_Msk (0x1U << CRM_APB2LPEN_I2SF5LPEN_Pos) /*!< 0x00100000 */ +#define CRM_APB2LPEN_I2SF5LPEN CRM_APB2LPEN_I2SF5LPEN_Msk /*!< I2SF5 clock enable in sleep mode */ +#define CRM_APB2LPEN_ACCLPEN_Pos (29U) +#define CRM_APB2LPEN_ACCLPEN_Msk (0x1U << CRM_APB2LPEN_ACCLPEN_Pos) /*!< 0x20000000 */ +#define CRM_APB2LPEN_ACCLPEN CRM_APB2LPEN_ACCLPEN_Msk /*!< ACC clock enable in sleep mode */ + +/******************* Bit definition for CRM_BPDC register *******************/ +#define CRM_BPDC_LEXTEN_Pos (0U) +#define CRM_BPDC_LEXTEN_Msk (0x1U << CRM_BPDC_LEXTEN_Pos) /*!< 0x00000001 */ +#define CRM_BPDC_LEXTEN CRM_BPDC_LEXTEN_Msk /*!< External low-speed oscillator enable */ +#define CRM_BPDC_LEXTSTBL_Pos (1U) +#define CRM_BPDC_LEXTSTBL_Msk (0x1U << CRM_BPDC_LEXTSTBL_Pos) /*!< 0x00000002 */ +#define CRM_BPDC_LEXTSTBL CRM_BPDC_LEXTSTBL_Msk /*!< External low-speed oscillator stable */ +#define CRM_BPDC_LEXTBYPS_Pos (2U) +#define CRM_BPDC_LEXTBYPS_Msk (0x1U << CRM_BPDC_LEXTBYPS_Pos) /*!< 0x00000004 */ +#define CRM_BPDC_LEXTBYPS CRM_BPDC_LEXTBYPS_Msk /*!< External low-speed crystal bypass */ + +/*!< ERTCSEL congiguration */ +#define CRM_BPDC_ERTCSEL_Pos (8U) +#define CRM_BPDC_ERTCSEL_Msk (0x3U << CRM_BPDC_ERTCSEL_Pos) /*!< 0x00000300 */ +#define CRM_BPDC_ERTCSEL CRM_BPDC_ERTCSEL_Msk /*!< ERTCSEL[1:0] bits (ERTC clock selection) */ +#define CRM_BPDC_ERTCSEL_0 (0x1U << CRM_BPDC_ERTCSEL_Pos) /*!< 0x00000100 */ +#define CRM_BPDC_ERTCSEL_1 (0x2U << CRM_BPDC_ERTCSEL_Pos) /*!< 0x00000200 */ + +#define CRM_BPDC_ERTCSEL_NOCLOCK 0x00000000U /*!< No clock */ +#define CRM_BPDC_ERTCSEL_LEXT 0x00000100U /*!< LEXT */ +#define CRM_BPDC_ERTCSEL_LICK 0x00000200U /*!< LICK */ +#define CRM_BPDC_ERTCSEL_HEXT 0x00000300U /*!< Devided HEXT with ERTCDIV bit in CRM_CFG */ + +#define CRM_BPDC_ERTCEN_Pos (15U) +#define CRM_BPDC_ERTCEN_Msk (0x1U << CRM_BPDC_ERTCEN_Pos) /*!< 0x00008000 */ +#define CRM_BPDC_ERTCEN CRM_BPDC_ERTCEN_Msk /*!< ERTC clock enable */ +#define CRM_BPDC_BPDRST_Pos (16U) +#define CRM_BPDC_BPDRST_Msk (0x1U << CRM_BPDC_BPDRST_Pos) /*!< 0x00010000 */ +#define CRM_BPDC_BPDRST CRM_BPDC_BPDRST_Msk /*!< Battery powered domain software reset */ + +/***************** Bit definition for CRM_CTRLSTS register ******************/ +#define CRM_CTRLSTS_LICKEN_Pos (0U) +#define CRM_CTRLSTS_LICKEN_Msk (0x1U << CRM_CTRLSTS_LICKEN_Pos) /*!< 0x00000001 */ +#define CRM_CTRLSTS_LICKEN CRM_CTRLSTS_LICKEN_Msk /*!< LICK enable */ +#define CRM_CTRLSTS_LICKSTBL_Pos (1U) +#define CRM_CTRLSTS_LICKSTBL_Msk (0x1U << CRM_CTRLSTS_LICKSTBL_Pos) /*!< 0x00000002 */ +#define CRM_CTRLSTS_LICKSTBL CRM_CTRLSTS_LICKSTBL_Msk /*!< LICK stable */ +#define CRM_CTRLSTS_RSTFC_Pos (24U) +#define CRM_CTRLSTS_RSTFC_Msk (0x1U << CRM_CTRLSTS_RSTFC_Pos) /*!< 0x01000000 */ +#define CRM_CTRLSTS_RSTFC CRM_CTRLSTS_RSTFC_Msk /*!< Reset flag clear */ +#define CRM_CTRLSTS_NRSTF_Pos (26U) +#define CRM_CTRLSTS_NRSTF_Msk (0x1U << CRM_CTRLSTS_NRSTF_Pos) /*!< 0x04000000 */ +#define CRM_CTRLSTS_NRSTF CRM_CTRLSTS_NRSTF_Msk /*!< NRST pin reset flag */ +#define CRM_CTRLSTS_PORRSTF_Pos (27U) +#define CRM_CTRLSTS_PORRSTF_Msk (0x1U << CRM_CTRLSTS_PORRSTF_Pos) /*!< 0x08000000 */ +#define CRM_CTRLSTS_PORRSTF CRM_CTRLSTS_PORRSTF_Msk /*!< POR/LVR reset flag */ +#define CRM_CTRLSTS_SWRSTF_Pos (28U) +#define CRM_CTRLSTS_SWRSTF_Msk (0x1U << CRM_CTRLSTS_SWRSTF_Pos) /*!< 0x10000000 */ +#define CRM_CTRLSTS_SWRSTF CRM_CTRLSTS_SWRSTF_Msk /*!< Software reset flag */ +#define CRM_CTRLSTS_WDTRSTF_Pos (29U) +#define CRM_CTRLSTS_WDTRSTF_Msk (0x1U << CRM_CTRLSTS_WDTRSTF_Pos) /*!< 0x20000000 */ +#define CRM_CTRLSTS_WDTRSTF CRM_CTRLSTS_WDTRSTF_Msk /*!< Watchdog timer reset flag */ +#define CRM_CTRLSTS_WWDTRSTF_Pos (30U) +#define CRM_CTRLSTS_WWDTRSTF_Msk (0x1U << CRM_CTRLSTS_WWDTRSTF_Pos) /*!< 0x40000000 */ +#define CRM_CTRLSTS_WWDTRSTF CRM_CTRLSTS_WWDTRSTF_Msk /*!< Window watchdog timer reset flag */ +#define CRM_CTRLSTS_LPRSTF_Pos (31U) +#define CRM_CTRLSTS_LPRSTF_Msk (0x1U << CRM_CTRLSTS_LPRSTF_Pos) /*!< 0x80000000 */ +#define CRM_CTRLSTS_LPRSTF CRM_CTRLSTS_LPRSTF_Msk /*!< Low-power reset flag */ + +/****************** Bit definition for CRM_OTGHS register *******************/ +#define CRM_OTGHS_USBHS_PHY12_SEL_Pos (4U) +#define CRM_OTGHS_USBHS_PHY12_SEL_Msk (0x1U << CRM_OTGHS_USBHS_PHY12_SEL_Pos) /*!< 0x00000010 */ +#define CRM_OTGHS_USBHS_PHY12_SEL CRM_OTGHS_USBHS_PHY12_SEL_Msk /*!< USBHS PHY 12M clock source select (F405 only) */ + +/****************** Bit definition for CRM_MISC1 register *******************/ +#define CRM_MISC1_HICKCAL_KEY_Pos (0U) +#define CRM_MISC1_HICKCAL_KEY_Msk (0xFFU << CRM_MISC1_HICKCAL_KEY_Pos) /*!< 0x000000FF */ +#define CRM_MISC1_HICKCAL_KEY CRM_MISC1_HICKCAL_KEY_Msk /*!< HICK calibration key */ +#define CRM_MISC1_HICKDIV_Pos (12U) +#define CRM_MISC1_HICKDIV_Msk (0x1U << CRM_MISC1_HICKDIV_Pos) /*!< 0x00001000 */ +#define CRM_MISC1_HICKDIV CRM_MISC1_HICKDIV_Msk /*!< HICK 6 divider selection */ +#define CRM_MISC1_HICK_TO_SCLK_Pos (14U) +#define CRM_MISC1_HICK_TO_SCLK_Msk (0x1U << CRM_MISC1_HICK_TO_SCLK_Pos) /*!< 0x00004000 */ +#define CRM_MISC1_HICK_TO_SCLK CRM_MISC1_HICK_TO_SCLK_Msk /*!< HICK as system clock frequency select */ +#define CRM_MISC1_HICKRST_Pos (15U) +#define CRM_MISC1_HICKRST_Msk (0x1U << CRM_MISC1_HICKRST_Pos) /*!< 0x00008000 */ +#define CRM_MISC1_HICKRST CRM_MISC1_HICKRST_Msk /*!< HICKRST */ + +/*!< CLKOUT_SEL2 congiguration */ +#define CRM_MISC1_CLKOUT_SEL2_Pos (16U) +#define CRM_MISC1_CLKOUT_SEL2_Msk (0xFU << CRM_MISC1_CLKOUT_SEL2_Pos) /*!< 0x000F0000 */ +#define CRM_MISC1_CLKOUT_SEL2 CRM_MISC1_CLKOUT_SEL2_Msk /*!< CLKOUT_SEL2[3:0] bits (Clock output selection 2) */ +#define CRM_MISC1_CLKOUT_SEL2_0 (0x1U << CRM_MISC1_CLKOUT_SEL2_Pos) /*!< 0x00010000 */ +#define CRM_MISC1_CLKOUT_SEL2_1 (0x2U << CRM_MISC1_CLKOUT_SEL2_Pos) /*!< 0x00020000 */ +#define CRM_MISC1_CLKOUT_SEL2_2 (0x4U << CRM_MISC1_CLKOUT_SEL2_Pos) /*!< 0x00040000 */ +#define CRM_MISC1_CLKOUT_SEL2_3 (0x8U << CRM_MISC1_CLKOUT_SEL2_Pos) /*!< 0x00080000 */ + +#define CRM_MISC1_CLKOUT_SEL2_USBFS 0x00000000U /*!< USBFS 48M */ +#define CRM_MISC1_CLKOUT_SEL2_ADC 0x00010000U /*!< ADC */ +#define CRM_MISC1_CLKOUT_SEL2_HICK 0x00020000U /*!< HICK */ +#define CRM_MISC1_CLKOUT_SEL2_LICK 0x00030000U /*!< LICK */ +#define CRM_MISC1_CLKOUT_SEL2_LEXT 0x00040000U /*!< LEXT */ + +/* Reference defines */ +#define CRM_MISC1_CLKSEL2 CRM_MISC1_CLKOUT_SEL2 +#define CRM_MISC1_CLKSEL2_0 CRM_MISC1_CLKOUT_SEL2_0 +#define CRM_MISC1_CLKSEL2_1 CRM_MISC1_CLKOUT_SEL2_1 +#define CRM_MISC1_CLKSEL2_2 CRM_MISC1_CLKOUT_SEL2_2 +#define CRM_MISC1_CLKSEL2_3 CRM_MISC1_CLKOUT_SEL2_3 +#define CRM_MISC1_CLKSEL2_USBFS CRM_MISC1_CLKOUT_SEL2_USBFS +#define CRM_MISC1_CLKSEL2_ADC CRM_MISC1_CLKOUT_SEL2_ADC +#define CRM_MISC1_CLKSEL2_HICK CRM_MISC1_CLKOUT_SEL2_HICK +#define CRM_MISC1_CLKSEL2_LICK CRM_MISC1_CLKOUT_SEL2_LICK +#define CRM_MISC1_CLKSEL2_LEXT CRM_MISC1_CLKOUT_SEL2_LEXT + +/*!< CLKOUTDIV2 congiguration */ +#define CRM_MISC1_CLKOUTDIV2_Pos (28U) +#define CRM_MISC1_CLKOUTDIV2_Msk (0xFU << CRM_MISC1_CLKOUTDIV2_Pos) /*!< 0xF0000000 */ +#define CRM_MISC1_CLKOUTDIV2 CRM_MISC1_CLKOUTDIV2_Msk /*!< CLKOUTDIV2[3:0] bits (Clock output division 2) */ +#define CRM_MISC1_CLKOUTDIV2_0 (0x1U << CRM_MISC1_CLKOUTDIV2_Pos) /*!< 0x10000000 */ +#define CRM_MISC1_CLKOUTDIV2_1 (0x2U << CRM_MISC1_CLKOUTDIV2_Pos) /*!< 0x20000000 */ +#define CRM_MISC1_CLKOUTDIV2_2 (0x4U << CRM_MISC1_CLKOUTDIV2_Pos) /*!< 0x40000000 */ +#define CRM_MISC1_CLKOUTDIV2_3 (0x8U << CRM_MISC1_CLKOUTDIV2_Pos) /*!< 0x80000000 */ + +#define CRM_MISC1_CLKOUTDIV2_DIV1 0x00000000U /*!< No clock output */ +#define CRM_MISC1_CLKOUTDIV2_DIV2 0x80000000U /*!< Clock output divided by 2 */ +#define CRM_MISC1_CLKOUTDIV2_DIV4 0x90000000U /*!< Clock output divided by 4 */ +#define CRM_MISC1_CLKOUTDIV2_DIV8 0xA0000000U /*!< Clock output divided by 8 */ +#define CRM_MISC1_CLKOUTDIV2_DIV16 0xB0000000U /*!< Clock output divided by 16 */ +#define CRM_MISC1_CLKOUTDIV2_DIV64 0xC0000000U /*!< Clock output divided by 64 */ +#define CRM_MISC1_CLKOUTDIV2_DIV128 0xD0000000U /*!< Clock output divided by 128 */ +#define CRM_MISC1_CLKOUTDIV2_DIV256 0xE0000000U /*!< Clock output divided by 256 */ +#define CRM_MISC1_CLKOUTDIV2_DIV512 0xF0000000U /*!< Clock output divided by 512 */ + +/****************** Bit definition for CRM_MISC2 register *******************/ +/*!< AUTO_STEP_EN congiguration */ +#define CRM_MISC2_AUTO_STEP_EN_Pos (4U) +#define CRM_MISC2_AUTO_STEP_EN_Msk (0x3U << CRM_MISC2_AUTO_STEP_EN_Pos) /*!< 0x00000030 */ +#define CRM_MISC2_AUTO_STEP_EN CRM_MISC2_AUTO_STEP_EN_Msk /*!< AUTO_STEP_EN[1:0] bits (Auto step-by-step SCLK switch enable) */ +#define CRM_MISC2_AUTO_STEP_EN_0 (0x1U << CRM_MISC2_AUTO_STEP_EN_Pos) /*!< 0x00000010 */ +#define CRM_MISC2_AUTO_STEP_EN_1 (0x2U << CRM_MISC2_AUTO_STEP_EN_Pos) /*!< 0x00000020 */ + +#define CRM_MISC2_PLLU_USB48_SEL_Pos (10U) +#define CRM_MISC2_PLLU_USB48_SEL_Msk (0x1U << CRM_MISC2_PLLU_USB48_SEL_Pos) /*!< 0x00000400 */ +#define CRM_MISC2_PLLU_USB48_SEL CRM_MISC2_PLLU_USB48_SEL_Msk /*!< USBFS 48M clock source selection */ + +/*!< HICK_TO_SCLK_DIV congiguration */ +#define CRM_MISC2_HICK_TO_SCLK_DIV_Pos (16U) +#define CRM_MISC2_HICK_TO_SCLK_DIV_Msk (0x7U << CRM_MISC2_HICK_TO_SCLK_DIV_Pos) /*!< 0x00070000 */ +#define CRM_MISC2_HICK_TO_SCLK_DIV CRM_MISC2_HICK_TO_SCLK_DIV_Msk /*!< HICK_TO_SCLK_DIV[2:0] bits (HICK as SCLK frequency division) */ +#define CRM_MISC2_HICK_TO_SCLK_DIV_0 (0x1U << CRM_MISC2_HICK_TO_SCLK_DIV_Pos) /*!< 0x00010000 */ +#define CRM_MISC2_HICK_TO_SCLK_DIV_1 (0x2U << CRM_MISC2_HICK_TO_SCLK_DIV_Pos) /*!< 0x00020000 */ +#define CRM_MISC2_HICK_TO_SCLK_DIV_2 (0x4U << CRM_MISC2_HICK_TO_SCLK_DIV_Pos) /*!< 0x00040000 */ + +#define CRM_MISC2_HICK_TO_SCLK_DIV_DIV1 0x00000000U /*!< HICK */ +#define CRM_MISC2_HICK_TO_SCLK_DIV_DIV2 0x00010000U /*!< HICK/2 */ +#define CRM_MISC2_HICK_TO_SCLK_DIV_DIV4 0x00020000U /*!< HICK/4 */ +#define CRM_MISC2_HICK_TO_SCLK_DIV_DIV8 0x00030000U /*!< HICK/8 */ +#define CRM_MISC2_HICK_TO_SCLK_DIV_DIV16 0x00040000U /*!< HICK/16 */ + +/*!< HEXT_TO_SCLK_DIV congiguration */ +#define CRM_MISC2_HEXT_TO_SCLK_DIV_Pos (19U) +#define CRM_MISC2_HEXT_TO_SCLK_DIV_Msk (0x7U << CRM_MISC2_HEXT_TO_SCLK_DIV_Pos) /*!< 0x00380000 */ +#define CRM_MISC2_HEXT_TO_SCLK_DIV CRM_MISC2_HEXT_TO_SCLK_DIV_Msk /*!< HEXT_TO_SCLK_DIV[2:0] bits (HEXT as SCLK frequency division) */ +#define CRM_MISC2_HEXT_TO_SCLK_DIV_0 (0x1U << CRM_MISC2_HEXT_TO_SCLK_DIV_Pos) /*!< 0x00080000 */ +#define CRM_MISC2_HEXT_TO_SCLK_DIV_1 (0x2U << CRM_MISC2_HEXT_TO_SCLK_DIV_Pos) /*!< 0x00100000 */ +#define CRM_MISC2_HEXT_TO_SCLK_DIV_2 (0x4U << CRM_MISC2_HEXT_TO_SCLK_DIV_Pos) /*!< 0x00200000 */ + +#define CRM_MISC2_HEXT_TO_SCLK_DIV_DIV1 0x00000000U /*!< HEXT */ +#define CRM_MISC2_HEXT_TO_SCLK_DIV_DIV2 0x00080000U /*!< HEXT/2 */ +#define CRM_MISC2_HEXT_TO_SCLK_DIV_DIV4 0x00100000U /*!< HEXT/4 */ +#define CRM_MISC2_HEXT_TO_SCLK_DIV_DIV8 0x00180000U /*!< HEXT/8 */ +#define CRM_MISC2_HEXT_TO_SCLK_DIV_DIV16 0x00200000U /*!< HEXT/16 */ +#define CRM_MISC2_HEXT_TO_SCLK_DIV_DIV32 0x00280000U /*!< HEXT/32 */ + +/******************************************************************************/ +/* */ +/* Flash and User System Data Registers (FLASH) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for FLASH_PSR register ******************/ +/*!< WTCYC congiguration */ +#define FLASH_PSR_WTCYC_Pos (0U) +#define FLASH_PSR_WTCYC_Msk (0x7U << FLASH_PSR_WTCYC_Pos) /*!< 0x00000007 */ +#define FLASH_PSR_WTCYC FLASH_PSR_WTCYC_Msk /*!< WTCYC[2:0] bits (Wait cycle) */ +#define FLASH_PSR_WTCYC_0 (0x1U << FLASH_PSR_WTCYC_Pos) /*!< 0x00000001 */ +#define FLASH_PSR_WTCYC_1 (0x2U << FLASH_PSR_WTCYC_Pos) /*!< 0x00000002 */ +#define FLASH_PSR_WTCYC_2 (0x4U << FLASH_PSR_WTCYC_Pos) /*!< 0x00000004 */ + +#define FLASH_PSR_PFT_EN_Pos (4U) +#define FLASH_PSR_PFT_EN_Msk (0x1U << FLASH_PSR_PFT_EN_Pos) /*!< 0x00000010 */ +#define FLASH_PSR_PFT_EN FLASH_PSR_PFT_EN_Msk /*!< Prefetch enable */ +#define FLASH_PSR_PFT_ENF_Pos (5U) +#define FLASH_PSR_PFT_ENF_Msk (0x1U << FLASH_PSR_PFT_ENF_Pos) /*!< 0x00000020 */ +#define FLASH_PSR_PFT_ENF FLASH_PSR_PFT_ENF_Msk /*!< Prefetch enable flag */ +#define FLASH_PSR_PFT_EN2_Pos (6U) +#define FLASH_PSR_PFT_EN2_Msk (0x1U << FLASH_PSR_PFT_EN2_Pos) /*!< 0x00000040 */ +#define FLASH_PSR_PFT_EN2 FLASH_PSR_PFT_EN2_Msk /*!< Prefetch enable 2 */ +#define FLASH_PSR_PFT_ENF2_Pos (7U) +#define FLASH_PSR_PFT_ENF2_Msk (0x1U << FLASH_PSR_PFT_ENF2_Pos) /*!< 0x00000080 */ +#define FLASH_PSR_PFT_ENF2 FLASH_PSR_PFT_ENF2_Msk /*!< Prefetch enable flag 2 */ +#define FLASH_PSR_PFT_LAT_DIS_Pos (8U) +#define FLASH_PSR_PFT_LAT_DIS_Msk (0x1U << FLASH_PSR_PFT_LAT_DIS_Pos) /*!< 0x00000100 */ +#define FLASH_PSR_PFT_LAT_DIS FLASH_PSR_PFT_LAT_DIS_Msk /*!< Prefetch latency disable */ + +/***************** Bit definition for FLASH_UNLOCK register *****************/ +#define FLASH_UNLOCK_UKVAL_Pos (0U) +#define FLASH_UNLOCK_UKVAL_Msk (0xFFFFFFFFU << FLASH_UNLOCK_UKVAL_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_UNLOCK_UKVAL FLASH_UNLOCK_UKVAL_Msk /*!< Unlock key value */ + +#define FAP_KEY_Pos (0U) +#define FAP_KEY_Msk (0xA5U << FAP_KEY_Pos) /*!< 0x000000A5 */ +#define FAP_KEY FAP_KEY_Msk /*!< Flash access protection key */ +#define FLASH_KEY1_Pos (0U) +#define FLASH_KEY1_Msk (0x45670123U << FLASH_KEY1_Pos) /*!< 0x45670123 */ +#define FLASH_KEY1 FLASH_KEY1_Msk /*!< Flash key 1 */ +#define FLASH_KEY2_Pos (0U) +#define FLASH_KEY2_Msk (0xCDEF89ABU << FLASH_KEY2_Pos) /*!< 0xCDEF89AB */ +#define FLASH_KEY2 FLASH_KEY2_Msk /*!< Flash key 2 */ + +/*************** Bit definition for FLASH_USD_UNLOCK register ***************/ +#define FLASH_USD_UNLOCK_USD_UKVAL_Pos (0U) /*!< 0xFFFFFFFF */ +#define FLASH_USD_UNLOCK_USD_UKVAL_Msk (0xFFFFFFFFU << FLASH_USD_UNLOCK_USD_UKVAL_Pos) +#define FLASH_USD_UNLOCK_USD_UKVAL FLASH_USD_UNLOCK_USD_UKVAL_Msk /*!< User system data unlock key value */ + +#define FLASH_USDKEY1 FLASH_KEY1 /*!< User system data key 1 */ +#define FLASH_USDKEY2 FLASH_KEY2 /*!< User system data key 2 */ + +/****************** Bit definition for FLASH_STS register *******************/ +#define FLASH_STS_OBF_Pos (0U) +#define FLASH_STS_OBF_Msk (0x1U << FLASH_STS_OBF_Pos) /*!< 0x00000001 */ +#define FLASH_STS_OBF FLASH_STS_OBF_Msk /*!< Operation busy flag */ +#define FLASH_STS_PRGMERR_Pos (2U) +#define FLASH_STS_PRGMERR_Msk (0x1U << FLASH_STS_PRGMERR_Pos) /*!< 0x00000004 */ +#define FLASH_STS_PRGMERR FLASH_STS_PRGMERR_Msk /*!< Programming error */ +#define FLASH_STS_EPPERR_Pos (4U) +#define FLASH_STS_EPPERR_Msk (0x1U << FLASH_STS_EPPERR_Pos) /*!< 0x00000010 */ +#define FLASH_STS_EPPERR FLASH_STS_EPPERR_Msk /*!< Erase/program protection error */ +#define FLASH_STS_ODF_Pos (5U) +#define FLASH_STS_ODF_Msk (0x1U << FLASH_STS_ODF_Pos) /*!< 0x00000020 */ +#define FLASH_STS_ODF FLASH_STS_ODF_Msk /*!< Operation done flag */ + +/****************** Bit definition for FLASH_CTRL register ******************/ +#define FLASH_CTRL_FPRGM_Pos (0U) +#define FLASH_CTRL_FPRGM_Msk (0x1U << FLASH_CTRL_FPRGM_Pos) /*!< 0x00000001 */ +#define FLASH_CTRL_FPRGM FLASH_CTRL_FPRGM_Msk /*!< Flash program */ +#define FLASH_CTRL_SECERS_Pos (1U) +#define FLASH_CTRL_SECERS_Msk (0x1U << FLASH_CTRL_SECERS_Pos) /*!< 0x00000002 */ +#define FLASH_CTRL_SECERS FLASH_CTRL_SECERS_Msk /*!< Page erase */ +#define FLASH_CTRL_BANKERS_Pos (2U) +#define FLASH_CTRL_BANKERS_Msk (0x1U << FLASH_CTRL_BANKERS_Pos) /*!< 0x00000004 */ +#define FLASH_CTRL_BANKERS FLASH_CTRL_BANKERS_Msk /*!< Bank erase */ +#define FLASH_CTRL_USDPRGM_Pos (4U) +#define FLASH_CTRL_USDPRGM_Msk (0x1U << FLASH_CTRL_USDPRGM_Pos) /*!< 0x00000010 */ +#define FLASH_CTRL_USDPRGM FLASH_CTRL_USDPRGM_Msk /*!< User system data program */ +#define FLASH_CTRL_USDERS_Pos (5U) +#define FLASH_CTRL_USDERS_Msk (0x1U << FLASH_CTRL_USDERS_Pos) /*!< 0x00000020 */ +#define FLASH_CTRL_USDERS FLASH_CTRL_USDERS_Msk /*!< User system data erase */ +#define FLASH_CTRL_ERSTR_Pos (6U) +#define FLASH_CTRL_ERSTR_Msk (0x1U << FLASH_CTRL_ERSTR_Pos) /*!< 0x00000040 */ +#define FLASH_CTRL_ERSTR FLASH_CTRL_ERSTR_Msk /*!< Erase start */ +#define FLASH_CTRL_OPLK_Pos (7U) +#define FLASH_CTRL_OPLK_Msk (0x1U << FLASH_CTRL_OPLK_Pos) /*!< 0x00000080 */ +#define FLASH_CTRL_OPLK FLASH_CTRL_OPLK_Msk /*!< Operation lock */ +#define FLASH_CTRL_USDULKS_Pos (9U) +#define FLASH_CTRL_USDULKS_Msk (0x1U << FLASH_CTRL_USDULKS_Pos) /*!< 0x00000200 */ +#define FLASH_CTRL_USDULKS FLASH_CTRL_USDULKS_Msk /*!< User system data unlock success */ +#define FLASH_CTRL_ERRIE_Pos (10U) +#define FLASH_CTRL_ERRIE_Msk (0x1U << FLASH_CTRL_ERRIE_Pos) /*!< 0x00000400 */ +#define FLASH_CTRL_ERRIE FLASH_CTRL_ERRIE_Msk /*!< Error interrupt enable */ +#define FLASH_CTRL_ODFIE_Pos (12U) +#define FLASH_CTRL_ODFIE_Msk (0x1U << FLASH_CTRL_ODFIE_Pos) /*!< 0x00001000 */ +#define FLASH_CTRL_ODFIE FLASH_CTRL_ODFIE_Msk /*!< Operation done flag interrupt enable */ + +/****************** Bit definition for FLASH_ADDR register ******************/ +#define FLASH_ADDR_FA_Pos (0U) +#define FLASH_ADDR_FA_Msk (0xFFFFFFFFU << FLASH_ADDR_FA_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_ADDR_FA FLASH_ADDR_FA_Msk /*!< Flash address */ + +/****************** Bit definition for FLASH_USD register *******************/ +#define FLASH_USD_USDERR_Pos (0U) +#define FLASH_USD_USDERR_Msk (0x1U << FLASH_USD_USDERR_Pos) /*!< 0x00000001 */ +#define FLASH_USD_USDERR FLASH_USD_USDERR_Msk /*!< User system data error */ +#define FLASH_USD_FAP_Pos (1U) +#define FLASH_USD_FAP_Msk (0x1U << FLASH_USD_FAP_Pos) /*!< 0x00000002 */ +#define FLASH_USD_FAP FLASH_USD_FAP_Msk /*!< Flash access protection */ + +/*!< SSB congiguration */ +#define FLASH_USD_WDT_ATO_EN_Pos (2U) +#define FLASH_USD_WDT_ATO_EN_Msk (0x1U << FLASH_USD_WDT_ATO_EN_Pos) /*!< 0x00000004 */ +#define FLASH_USD_WDT_ATO_EN FLASH_USD_WDT_ATO_EN_Msk /*!< nWDT_ATO_EN */ +#define FLASH_USD_DEPSLP_RST_Pos (3U) +#define FLASH_USD_DEPSLP_RST_Msk (0x1U << FLASH_USD_DEPSLP_RST_Pos) /*!< 0x00000008 */ +#define FLASH_USD_DEPSLP_RST FLASH_USD_DEPSLP_RST_Msk /*!< nDEPSLP_RST */ +#define FLASH_USD_STDBY_RST_Pos (4U) +#define FLASH_USD_STDBY_RST_Msk (0x1U << FLASH_USD_STDBY_RST_Pos) /*!< 0x00000010 */ +#define FLASH_USD_STDBY_RST FLASH_USD_STDBY_RST_Msk /*!< nSTDBY_RST */ +#define FLASH_USD_BOOT1_Pos (6U) +#define FLASH_USD_BOOT1_Msk (0x1U << FLASH_USD_BOOT1_Pos) /*!< 0x00000040 */ +#define FLASH_USD_BOOT1 FLASH_USD_BOOT1_Msk /*!< nBOOT1 */ +#define FLASH_USD_DEPSLP_WDT_Pos (7U) +#define FLASH_USD_DEPSLP_WDT_Msk (0x1U << FLASH_USD_DEPSLP_WDT_Pos) /*!< 0x00000080 */ +#define FLASH_USD_DEPSLP_WDT FLASH_USD_DEPSLP_WDT_Msk /*!< nDEPSLP_WDT */ +#define FLASH_USD_STDBY_WDT_Pos (8U) +#define FLASH_USD_STDBY_WDT_Msk (0x1U << FLASH_USD_STDBY_WDT_Pos) /*!< 0x00000100 */ +#define FLASH_USD_STDBY_WDT FLASH_USD_STDBY_WDT_Msk /*!< nSTDBY_WDT */ +#define FLASH_USD_RAM_PRT_CHK_Pos (9U) +#define FLASH_USD_RAM_PRT_CHK_Msk (0x1U << FLASH_USD_RAM_PRT_CHK_Pos) /*!< 0x00000200 */ +#define FLASH_USD_RAM_PRT_CHK FLASH_USD_RAM_PRT_CHK_Msk /*!< nRAM_PRT_CHK */ +#define FLASH_USD_SSB_Pos (2U) +#define FLASH_USD_SSB_Msk (0xFFU << FLASH_USD_SSB_Pos) /*!< 0x000003FC */ +#define FLASH_USD_SSB FLASH_USD_SSB_Msk /*!< System setting byte */ + +#define FLASH_USD_USER_D0_Pos (10U) +#define FLASH_USD_USER_D0_Msk (0xFFU << FLASH_USD_USER_D0_Pos) /*!< 0x0003FC00 */ +#define FLASH_USD_USER_D0 FLASH_USD_USER_D0_Msk /*!< User data 0 */ +#define FLASH_USD_USER_D1_Pos (18U) +#define FLASH_USD_USER_D1_Msk (0xFFU << FLASH_USD_USER_D1_Pos) /*!< 0x03FC0000 */ +#define FLASH_USD_USER_D1 FLASH_USD_USER_D1_Msk /*!< User data 1 */ +#define FLASH_USD_FAP_HL_Pos (26U) +#define FLASH_USD_FAP_HL_Msk (0x1U << FLASH_USD_FAP_HL_Pos) /*!< 0x04000000 */ +#define FLASH_USD_FAP_HL FLASH_USD_FAP_HL_Msk /*!< Flash access protection high level */ + +/****************** Bit definition for FLASH_EPPS register ******************/ +#define FLASH_EPPS_EPPS_Pos (0U) +#define FLASH_EPPS_EPPS_Msk (0xFFFFFFFFU << FLASH_EPPS_EPPS_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_EPPS_EPPS FLASH_EPPS_EPPS_Msk /*!< Erase/Program protection status */ + +/******************* Bit definition for SLIB_STS0 register *******************/ +#define SLIB_STS0_BTM_AP_ENF_Pos (0U) +#define SLIB_STS0_BTM_AP_ENF_Msk (0x1U << SLIB_STS0_BTM_AP_ENF_Pos) /*!< 0x00000001 */ +#define SLIB_STS0_BTM_AP_ENF SLIB_STS0_BTM_AP_ENF_Msk /*!< Boot memory store application code enabled flag */ +#define SLIB_STS0_EM_SLIB_ENF_Pos (2U) +#define SLIB_STS0_EM_SLIB_ENF_Msk (0x1U << SLIB_STS0_EM_SLIB_ENF_Pos) /*!< 0x00000004 */ +#define SLIB_STS0_EM_SLIB_ENF SLIB_STS0_EM_SLIB_ENF_Msk /*!< Extension memory sLib enable flag */ +#define SLIB_STS0_SLIB_ENF_Pos (3U) +#define SLIB_STS0_SLIB_ENF_Msk (0x1U << SLIB_STS0_SLIB_ENF_Pos) /*!< 0x00000008 */ +#define SLIB_STS0_SLIB_ENF SLIB_STS0_SLIB_ENF_Msk /*!< Security library enable flag */ +#define SLIB_STS0_EM_SLIB_INST_SS_Pos (16U) /*!< 0x00FF0000 */ +#define SLIB_STS0_EM_SLIB_INST_SS_Msk (0xFFU << SLIB_STS0_EM_SLIB_INST_SS_Pos) +#define SLIB_STS0_EM_SLIB_INST_SS SLIB_STS0_EM_SLIB_INST_SS_Msk /*!< Extension memory sLib instruction start page */ + +/******************* Bit definition for SLIB_STS1 register *******************/ +#define SLIB_STS1_SLIB_SS_Pos (0U) +#define SLIB_STS1_SLIB_SS_Msk (0x7FFU << SLIB_STS1_SLIB_SS_Pos) /*!< 0x000007FF */ +#define SLIB_STS1_SLIB_SS SLIB_STS1_SLIB_SS_Msk /*!< Security library start page */ +#define SLIB_STS1_SLIB_INST_SS_Pos (11U) +#define SLIB_STS1_SLIB_INST_SS_Msk (0x7FFU << SLIB_STS1_SLIB_INST_SS_Pos) /*!< 0x003FF800 */ +#define SLIB_STS1_SLIB_INST_SS SLIB_STS1_SLIB_INST_SS_Msk /*!< Security library instruction start page */ +#define SLIB_STS1_SLIB_ES_Pos (22U) +#define SLIB_STS1_SLIB_ES_Msk (0x3FFU << SLIB_STS1_SLIB_ES_Pos) /*!< 0xFFC00000 */ +#define SLIB_STS1_SLIB_ES SLIB_STS1_SLIB_ES_Msk /*!< Security library end page */ + +/***************** Bit definition for SLIB_PWD_CLR register ******************/ +#define SLIB_PWD_CLR_SLIB_PCLR_VAL_Pos (0U) /*!< 0xFFFFFFFF */ +#define SLIB_PWD_CLR_SLIB_PCLR_VAL_Msk (0xFFFFFFFFU << SLIB_PWD_CLR_SLIB_PCLR_VAL_Pos) +#define SLIB_PWD_CLR_SLIB_PCLR_VAL SLIB_PWD_CLR_SLIB_PCLR_VAL_Msk /*!< Security library password clear value */ + +/***************** Bit definition for SLIB_MISC_STS register *****************/ +#define SLIB_MISC_STS_SLIB_PWD_ERR_Pos (0U) /*!< 0x00000001 */ +#define SLIB_MISC_STS_SLIB_PWD_ERR_Msk (0x1U << SLIB_MISC_STS_SLIB_PWD_ERR_Pos) +#define SLIB_MISC_STS_SLIB_PWD_ERR SLIB_MISC_STS_SLIB_PWD_ERR_Msk /*!< Security library password error */ +#define SLIB_MISC_STS_SLIB_PWD_OK_Pos (1U) +#define SLIB_MISC_STS_SLIB_PWD_OK_Msk (0x1U << SLIB_MISC_STS_SLIB_PWD_OK_Pos) /*!< 0x00000002 */ +#define SLIB_MISC_STS_SLIB_PWD_OK SLIB_MISC_STS_SLIB_PWD_OK_Msk /*!< Security library password ok */ +#define SLIB_MISC_STS_SLIB_ULKF_Pos (2U) +#define SLIB_MISC_STS_SLIB_ULKF_Msk (0x1U << SLIB_MISC_STS_SLIB_ULKF_Pos) /*!< 0x00000004 */ +#define SLIB_MISC_STS_SLIB_ULKF SLIB_MISC_STS_SLIB_ULKF_Msk /*!< Security library unlock flag */ + +/**************** Bit definition for FLASH_CRC_ADDR register *****************/ +#define FLASH_CRC_ADDR_CRC_ADDR_Pos (0U) /*!< 0xFFFFFFFF */ +#define FLASH_CRC_ADDR_CRC_ADDR_Msk (0xFFFFFFFFU << FLASH_CRC_ADDR_CRC_ADDR_Pos) +#define FLASH_CRC_ADDR_CRC_ADDR FLASH_CRC_ADDR_CRC_ADDR_Msk /*!< CRC address */ + +/**************** Bit definition for FLASH_CRC_CTRL register *****************/ +#define FLASH_CRC_CTRL_CRC_SN_Pos (0U) +#define FLASH_CRC_CTRL_CRC_SN_Msk (0xFFFFU << FLASH_CRC_CTRL_CRC_SN_Pos) /*!< 0x0000FFFF */ +#define FLASH_CRC_CTRL_CRC_SN FLASH_CRC_CTRL_CRC_SN_Msk /*!< CRC page number */ +#define FLASH_CRC_CTRL_CRC_STRT_Pos (16U) +#define FLASH_CRC_CTRL_CRC_STRT_Msk (0x1U << FLASH_CRC_CTRL_CRC_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_CRC_CTRL_CRC_STRT FLASH_CRC_CTRL_CRC_STRT_Msk /*!< CRC start */ + +/**************** Bit definition for FLASH_CRC_CHKR register *****************/ +#define FLASH_CRC_CHKR_CRC_CHKR_Pos (0U) /*!< 0xFFFFFFFF */ +#define FLASH_CRC_CHKR_CRC_CHKR_Msk (0xFFFFFFFFU << FLASH_CRC_CHKR_CRC_CHKR_Pos) +#define FLASH_CRC_CHKR_CRC_CHKR FLASH_CRC_CHKR_CRC_CHKR_Msk /*!< CRC check result */ + +/***************** Bit definition for SLIB_SET_PWD register ******************/ +#define SLIB_SET_PWD_SLIB_PSET_VAL_Pos (0U) /*!< 0xFFFFFFFF */ +#define SLIB_SET_PWD_SLIB_PSET_VAL_Msk (0xFFFFFFFFU << SLIB_SET_PWD_SLIB_PSET_VAL_Pos) +#define SLIB_SET_PWD_SLIB_PSET_VAL SLIB_SET_PWD_SLIB_PSET_VAL_Msk /*!< Security library password setting value */ + +/**************** Bit definition for SLIB_SET_RANGE register *****************/ +#define SLIB_SET_RANGE_SLIB_SS_SET_Pos (0U) /*!< 0x000007FF */ +#define SLIB_SET_RANGE_SLIB_SS_SET_Msk (0x7FFU << SLIB_SET_RANGE_SLIB_SS_SET_Pos) +#define SLIB_SET_RANGE_SLIB_SS_SET SLIB_SET_RANGE_SLIB_SS_SET_Msk /*!< Security library start page setting */ +#define SLIB_SET_RANGE_SLIB_ISS_SET_Pos (11U) /*!< 0x003FF800 */ +#define SLIB_SET_RANGE_SLIB_ISS_SET_Msk (0x7FFU << SLIB_SET_RANGE_SLIB_ISS_SET_Pos) +#define SLIB_SET_RANGE_SLIB_ISS_SET SLIB_SET_RANGE_SLIB_ISS_SET_Msk /*!< Security library instruction start page setting */ +#define SLIB_SET_RANGE_SLIB_ES_SET_Pos (22U) /*!< 0xFFC00000 */ +#define SLIB_SET_RANGE_SLIB_ES_SET_Msk (0x3FFU << SLIB_SET_RANGE_SLIB_ES_SET_Pos) +#define SLIB_SET_RANGE_SLIB_ES_SET SLIB_SET_RANGE_SLIB_ES_SET_Msk /*!< Security library end page setting */ + +/****************** Bit definition for EM_SLIB_SET register ******************/ +#define EM_SLIB_SET_EM_SLIB_SET_Pos (0U) /*!< 0x0000FFFF */ +#define EM_SLIB_SET_EM_SLIB_SET_Msk (0xFFFFU << EM_SLIB_SET_EM_SLIB_SET_Pos) +#define EM_SLIB_SET_EM_SLIB_SET EM_SLIB_SET_EM_SLIB_SET_Msk /*!< Extension memory sLib setting */ +#define EM_SLIB_SET_EM_SLIB_ISS_SET_Pos (16U) /*!< 0x00FF0000 */ +#define EM_SLIB_SET_EM_SLIB_ISS_SET_Msk (0xFFU << EM_SLIB_SET_EM_SLIB_ISS_SET_Pos) +#define EM_SLIB_SET_EM_SLIB_ISS_SET EM_SLIB_SET_EM_SLIB_ISS_SET_Msk /*!< Extension memory sLib instruction start page setting */ + +/***************** Bit definition for BTM_MODE_SET register ******************/ +#define BTM_MODE_SET_BTM_MODE_SET_Pos (0U) /*!< 0x000000FF */ +#define BTM_MODE_SET_BTM_MODE_SET_Msk (0xFFU << BTM_MODE_SET_BTM_MODE_SET_Pos) +#define BTM_MODE_SET_BTM_MODE_SET BTM_MODE_SET_BTM_MODE_SET_Msk /*!< Boot memory mode setting */ + +/***************** Bit definition for SLIB_UNLOCK register ******************/ +#define SLIB_UNLOCK_SLIB_UKVAL_Pos (0U) /*!< 0xFFFFFFFF */ +#define SLIB_UNLOCK_SLIB_UKVAL_Msk (0xFFFFFFFFU << SLIB_UNLOCK_SLIB_UKVAL_Pos) +#define SLIB_UNLOCK_SLIB_UKVAL SLIB_UNLOCK_SLIB_UKVAL_Msk /*!< Security library unlock key value */ + +#define SLIB_KEY_Pos (0U) +#define SLIB_KEY_Msk (0xA35F6D24U << SLIB_KEY_Pos) /*!< 0xA35F6D24 */ +#define SLIB_KEY SLIB_KEY_Msk /*!< Security library key */ + +/*----------------------------------------------------------------------------*/ + +/****************** Bit definition for FLASH_FAP register *******************/ +#define FLASH_FAP_FAP_Pos (0U) +#define FLASH_FAP_FAP_Msk (0xFFU << FLASH_FAP_FAP_Pos) /*!< 0x000000FF */ +#define FLASH_FAP_FAP FLASH_FAP_FAP_Msk /*!< Flash memory access protection */ +#define FLASH_FAP_nFAP_Pos (8U) +#define FLASH_FAP_nFAP_Msk (0xFFU << FLASH_FAP_nFAP_Pos) /*!< 0x0000FF00 */ +#define FLASH_FAP_nFAP FLASH_FAP_nFAP_Msk /*!< Inverse code of flash memory access protection */ + +/****************** Bit definition for FLASH_SSB register *******************/ +#define FLASH_SSB_SSB_Pos (16U) +#define FLASH_SSB_SSB_Msk (0xFFU << FLASH_SSB_SSB_Pos) /*!< 0x00FF0000 */ +#define FLASH_SSB_SSB FLASH_SSB_SSB_Msk /*!< System configuration byte */ +#define FLASH_SSB_nSSB_Pos (24U) +#define FLASH_SSB_nSSB_Msk (0xFFU << FLASH_SSB_nSSB_Pos) /*!< 0xFF000000 */ +#define FLASH_SSB_nSSB FLASH_SSB_nSSB_Msk /*!< Inverse code of system configuration byte */ + +/***************** Bit definition for FLASH_DATA0 register ******************/ +#define FLASH_DATA0_DATA0_Pos (0U) +#define FLASH_DATA0_DATA0_Msk (0xFFU << FLASH_DATA0_DATA0_Pos) /*!< 0x000000FF */ +#define FLASH_DATA0_DATA0 FLASH_DATA0_DATA0_Msk /*!< User data 0 */ +#define FLASH_DATA0_nDATA0_Pos (8U) +#define FLASH_DATA0_nDATA0_Msk (0xFFU << FLASH_DATA0_nDATA0_Pos) /*!< 0x0000FF00 */ +#define FLASH_DATA0_nDATA0 FLASH_DATA0_nDATA0_Msk /*!< Inverse code of user data 0 */ + +/***************** Bit definition for FLASH_DATA1 register ******************/ +#define FLASH_DATA1_DATA1_Pos (16U) +#define FLASH_DATA1_DATA1_Msk (0xFFU << FLASH_DATA1_DATA1_Pos) /*!< 0x00FF0000 */ +#define FLASH_DATA1_DATA1 FLASH_DATA1_DATA1_Msk /*!< User data 1 */ +#define FLASH_DATA1_nDATA1_Pos (24U) +#define FLASH_DATA1_nDATA1_Msk (0xFFU << FLASH_DATA1_nDATA1_Pos) /*!< 0xFF000000 */ +#define FLASH_DATA1_nDATA1 FLASH_DATA1_nDATA1_Msk /*!< Inverse code of user data 1 */ + +/****************** Bit definition for FLASH_EPP0 register ******************/ +#define FLASH_EPP0_EPP0_Pos (0U) +#define FLASH_EPP0_EPP0_Msk (0xFFU << FLASH_EPP0_EPP0_Pos) /*!< 0x000000FF */ +#define FLASH_EPP0_EPP0 FLASH_EPP0_EPP0_Msk /*!< Flash erase/write protection byte 0 */ +#define FLASH_EPP0_nEPP0_Pos (8U) +#define FLASH_EPP0_nEPP0_Msk (0xFFU << FLASH_EPP0_nEPP0_Pos) /*!< 0x0000FF00 */ +#define FLASH_EPP0_nEPP0 FLASH_EPP0_nEPP0_Msk /*!< Inverse code of flash erase/write protection byte 0 */ + +/****************** Bit definition for FLASH_EPP1 register ******************/ +#define FLASH_EPP1_EPP1_Pos (16U) +#define FLASH_EPP1_EPP1_Msk (0xFFU << FLASH_EPP1_EPP1_Pos) /*!< 0x00FF0000 */ +#define FLASH_EPP1_EPP1 FLASH_EPP1_EPP1_Msk /*!< Flash erase/write protection byte 1 */ +#define FLASH_EPP1_nEPP1_Pos (24U) +#define FLASH_EPP1_nEPP1_Msk (0xFFU << FLASH_EPP1_nEPP1_Pos) /*!< 0xFF000000 */ +#define FLASH_EPP1_nEPP1 FLASH_EPP1_nEPP1_Msk /*!< Inverse code of flash erase/write protection byte 1 */ + +/****************** Bit definition for FLASH_EPP2 register ******************/ +#define FLASH_EPP2_EPP2_Pos (0U) +#define FLASH_EPP2_EPP2_Msk (0xFFU << FLASH_EPP2_EPP2_Pos) /*!< 0x000000FF */ +#define FLASH_EPP2_EPP2 FLASH_EPP2_EPP2_Msk /*!< Flash erase/write protection byte 2 */ +#define FLASH_EPP2_nEPP2_Pos (8U) +#define FLASH_EPP2_nEPP2_Msk (0xFFU << FLASH_EPP2_nEPP2_Pos) /*!< 0x0000FF00 */ +#define FLASH_EPP2_nEPP2 FLASH_EPP2_nEPP2_Msk /*!< Inverse code of flash erase/write protection byte 2 */ + +/****************** Bit definition for FLASH_EPP3 register ******************/ +#define FLASH_EPP3_EPP3_Pos (16U) +#define FLASH_EPP3_EPP3_Msk (0xFFU << FLASH_EPP3_EPP3_Pos) /*!< 0x00FF0000 */ +#define FLASH_EPP3_EPP3 FLASH_EPP3_EPP3_Msk /*!< Flash erase/write protection byte 3 */ +#define FLASH_EPP3_nEPP3_Pos (24U) +#define FLASH_EPP3_nEPP3_Msk (0xFFU << FLASH_EPP3_nEPP3_Pos) /*!< 0xFF000000 */ +#define FLASH_EPP3_nEPP3 FLASH_EPP3_nEPP3_Msk /*!< Inverse code of flash erase/write protection byte 3 */ + +/**************** Bit definition for FLASH_QSPIKEY0 register ****************/ +#define FLASH_QSPIKEY0_QSPIKEY0_Pos (0U) +#define FLASH_QSPIKEY0_QSPIKEY0_Msk (0xFFU << FLASH_QSPIKEY0_QSPIKEY0_Pos) /*!< 0x000000FF */ +#define FLASH_QSPIKEY0_QSPIKEY0 FLASH_QSPIKEY0_QSPIKEY0_Msk /*!< QSPI ciphertext access area encryption key byte 0 */ +#define FLASH_QSPIKEY0_nQSPIKEY0_Pos (8U) +#define FLASH_QSPIKEY0_nQSPIKEY0_Msk (0xFFU << FLASH_QSPIKEY0_nQSPIKEY0_Pos) /*!< 0x0000FF00 */ +#define FLASH_QSPIKEY0_nQSPIKEY0 FLASH_QSPIKEY0_nQSPIKEY0_Msk /*!< Inverse code of QSPI ciphertext access area encryption key byte 0 */ + +/**************** Bit definition for FLASH_QSPIKEY1 register ****************/ +#define FLASH_QSPIKEY1_QSPIKEY1_Pos (16U) +#define FLASH_QSPIKEY1_QSPIKEY1_Msk (0xFFU << FLASH_QSPIKEY1_QSPIKEY1_Pos) /*!< 0x00FF0000 */ +#define FLASH_QSPIKEY1_QSPIKEY1 FLASH_QSPIKEY1_QSPIKEY1_Msk /*!< QSPI ciphertext access area encryption key byte 1 */ +#define FLASH_QSPIKEY1_nQSPIKEY1_Pos (23U) +#define FLASH_QSPIKEY1_nQSPIKEY1_Msk (0xFFU << FLASH_QSPIKEY1_nQSPIKEY1_Pos) /*!< 0xFF000000 */ +#define FLASH_QSPIKEY1_nQSPIKEY1 FLASH_QSPIKEY1_nQSPIKEY1_Msk /*!< Inverse code of QSPI ciphertext access area encryption key byte 1 */ + +/**************** Bit definition for FLASH_QSPIKEY2 register ****************/ +#define FLASH_QSPIKEY2_QSPIKEY2_Pos (0U) +#define FLASH_QSPIKEY2_QSPIKEY2_Msk (0xFFU << FLASH_QSPIKEY2_QSPIKEY2_Pos) /*!< 0x000000FF */ +#define FLASH_QSPIKEY2_QSPIKEY2 FLASH_QSPIKEY2_QSPIKEY2_Msk /*!< QSPI ciphertext access area encryption key byte 2 */ +#define FLASH_QSPIKEY2_nQSPIKEY2_Pos (8U) +#define FLASH_QSPIKEY2_nQSPIKEY2_Msk (0xFFU << FLASH_QSPIKEY2_nQSPIKEY2_Pos) /*!< 0x0000FF00 */ +#define FLASH_QSPIKEY2_nQSPIKEY2 FLASH_QSPIKEY2_nQSPIKEY2_Msk /*!< Inverse code of QSPI ciphertext access area encryption key byte 2 */ + +/**************** Bit definition for FLASH_QSPIKEY3 register ****************/ +#define FLASH_QSPIKEY3_QSPIKEY3_Pos (16U) +#define FLASH_QSPIKEY3_QSPIKEY3_Msk (0xFFU << FLASH_QSPIKEY3_QSPIKEY3_Pos) /*!< 0x00FF0000 */ +#define FLASH_QSPIKEY3_QSPIKEY3 FLASH_QSPIKEY3_QSPIKEY3_Msk /*!< QSPI ciphertext access area encryption key byte 3 */ +#define FLASH_QSPIKEY3_nQSPIKEY3_Pos (23U) +#define FLASH_QSPIKEY3_nQSPIKEY3_Msk (0xFFU << FLASH_QSPIKEY3_nQSPIKEY3_Pos) /*!< 0xFF000000 */ +#define FLASH_QSPIKEY3_nQSPIKEY3 FLASH_QSPIKEY3_nQSPIKEY3_Msk /*!< Inverse code of QSPI ciphertext access area encryption key byte 3 */ + +/***************** Bit definition for FLASH_DATA2 register ******************/ +#define FLASH_DATA2_DATA2_Pos (0U) +#define FLASH_DATA2_DATA2_Msk (0xFFU << FLASH_DATA2_DATA2_Pos) /*!< 0x000000FF */ +#define FLASH_DATA2_DATA2 FLASH_DATA2_DATA2_Msk /*!< User data 2 */ +#define FLASH_DATA2_nDATA2_Pos (8U) +#define FLASH_DATA2_nDATA2_Msk (0xFFU << FLASH_DATA2_nDATA2_Pos) /*!< 0x0000FF00 */ +#define FLASH_DATA2_nDATA2 FLASH_DATA2_nDATA2_Msk /*!< Inverse code of user data 2 */ + +/***************** Bit definition for FLASH_DATA3 register ******************/ +#define FLASH_DATA3_DATA3_Pos (16U) +#define FLASH_DATA3_DATA3_Msk (0xFFU << FLASH_DATA3_DATA3_Pos) /*!< 0x00FF0000 */ +#define FLASH_DATA3_DATA3 FLASH_DATA3_DATA3_Msk /*!< User data 3 */ +#define FLASH_DATA3_nDATA3_Pos (24U) +#define FLASH_DATA3_nDATA3_Msk (0xFFU << FLASH_DATA3_nDATA3_Pos) /*!< 0xFF000000 */ +#define FLASH_DATA3_nDATA3 FLASH_DATA3_nDATA3_Msk /*!< Inverse code of user data 3 */ + +/***************** Bit definition for FLASH_DATA4 register ******************/ +#define FLASH_DATA4_DATA4_Pos (0U) +#define FLASH_DATA4_DATA4_Msk (0xFFU << FLASH_DATA4_DATA4_Pos) /*!< 0x000000FF */ +#define FLASH_DATA4_DATA4 FLASH_DATA4_DATA4_Msk /*!< User data 4 */ +#define FLASH_DATA4_nDATA4_Pos (8U) +#define FLASH_DATA4_nDATA4_Msk (0xFFU << FLASH_DATA4_nDATA4_Pos) /*!< 0x0000FF00 */ +#define FLASH_DATA4_nDATA4 FLASH_DATA4_nDATA4_Msk /*!< Inverse code of user data 4 */ + +/***************** Bit definition for FLASH_DATA5 register ******************/ +#define FLASH_DATA5_DATA5_Pos (16U) +#define FLASH_DATA5_DATA5_Msk (0xFFU << FLASH_DATA5_DATA5_Pos) /*!< 0x00FF0000 */ +#define FLASH_DATA5_DATA5 FLASH_DATA5_DATA5_Msk /*!< User data 5 */ +#define FLASH_DATA5_nDATA5_Pos (24U) +#define FLASH_DATA5_nDATA5_Msk (0xFFU << FLASH_DATA5_nDATA5_Pos) /*!< 0xFF000000 */ +#define FLASH_DATA5_nDATA5 FLASH_DATA5_nDATA5_Msk /*!< Inverse code of user data 5 */ + +/***************** Bit definition for FLASH_DATA6 register ******************/ +#define FLASH_DATA6_DATA6_Pos (0U) +#define FLASH_DATA6_DATA6_Msk (0xFFU << FLASH_DATA6_DATA6_Pos) /*!< 0x000000FF */ +#define FLASH_DATA6_DATA6 FLASH_DATA6_DATA6_Msk /*!< User data 6 */ +#define FLASH_DATA6_nDATA6_Pos (8U) +#define FLASH_DATA6_nDATA6_Msk (0xFFU << FLASH_DATA6_nDATA6_Pos) /*!< 0x0000FF00 */ +#define FLASH_DATA6_nDATA6 FLASH_DATA6_nDATA6_Msk /*!< Inverse code of user data 6 */ + +/***************** Bit definition for FLASH_DATA7 register ******************/ +#define FLASH_DATA7_DATA7_Pos (16U) +#define FLASH_DATA7_DATA7_Msk (0xFFU << FLASH_DATA7_DATA7_Pos) /*!< 0x00FF0000 */ +#define FLASH_DATA7_DATA7 FLASH_DATA7_DATA7_Msk /*!< User data 7 */ +#define FLASH_DATA7_nDATA7_Pos (24U) +#define FLASH_DATA7_nDATA7_Msk (0xFFU << FLASH_DATA7_nDATA7_Pos) /*!< 0xFF000000 */ +#define FLASH_DATA7_nDATA7 FLASH_DATA7_nDATA7_Msk /*!< Inverse code of user data 7 */ + +/*!< Noted: The FLASH_DATA go up to 219, it too long for added in here */ + +/******************************************************************************/ +/* */ +/* General-purpose I/Os (GPIO) & Multiplex function I/Os (IOMUX) */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for GPIO_CFGR register *******************/ +#define GPIO_CFGR_IOMC_Pos (0U) +#define GPIO_CFGR_IOMC_Msk (0xFFFFFFFFU << GPIO_CFGR_IOMC_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_CFGR_IOMC GPIO_CFGR_IOMC_Msk /*!< GPIO x mode configuration */ + +/*!< IOMC0 configuration */ +#define GPIO_CFGR_IOMC0_Pos (0U) +#define GPIO_CFGR_IOMC0_Msk (0x3U << GPIO_CFGR_IOMC0_Pos) /*!< 0x00000003 */ +#define GPIO_CFGR_IOMC0 GPIO_CFGR_IOMC0_Msk /*!< IOMC0[1:0] bits (GPIO x mode configuration, pin 0) */ +#define GPIO_CFGR_IOMC0_0 (0x1U << GPIO_CFGR_IOMC0_Pos) /*!< 0x00000001 */ +#define GPIO_CFGR_IOMC0_1 (0x2U << GPIO_CFGR_IOMC0_Pos) /*!< 0x00000002 */ + +/*!< IOMC1 configuration */ +#define GPIO_CFGR_IOMC1_Pos (2U) +#define GPIO_CFGR_IOMC1_Msk (0x3U << GPIO_CFGR_IOMC1_Pos) /*!< 0x0000000C */ +#define GPIO_CFGR_IOMC1 GPIO_CFGR_IOMC1_Msk /*!< IOMC1[1:0] bits (GPIO x mode configuration, pin 1) */ +#define GPIO_CFGR_IOMC1_0 (0x1U << GPIO_CFGR_IOMC1_Pos) /*!< 0x00000004 */ +#define GPIO_CFGR_IOMC1_1 (0x2U << GPIO_CFGR_IOMC1_Pos) /*!< 0x00000008 */ + +/*!< IOMC2 configuration */ +#define GPIO_CFGR_IOMC2_Pos (4U) +#define GPIO_CFGR_IOMC2_Msk (0x3U << GPIO_CFGR_IOMC2_Pos) /*!< 0x00000030 */ +#define GPIO_CFGR_IOMC2 GPIO_CFGR_IOMC2_Msk /*!< IOMC2[1:0] bits (GPIO x mode configuration, pin 2) */ +#define GPIO_CFGR_IOMC2_0 (0x1U << GPIO_CFGR_IOMC2_Pos) /*!< 0x00000010 */ +#define GPIO_CFGR_IOMC2_1 (0x2U << GPIO_CFGR_IOMC2_Pos) /*!< 0x00000020 */ + +/*!< IOMC3 configuration */ +#define GPIO_CFGR_IOMC3_Pos (6U) +#define GPIO_CFGR_IOMC3_Msk (0x3U << GPIO_CFGR_IOMC3_Pos) /*!< 0x000000C0 */ +#define GPIO_CFGR_IOMC3 GPIO_CFGR_IOMC3_Msk /*!< IOMC3[1:0] bits (GPIO x mode configuration, pin 3) */ +#define GPIO_CFGR_IOMC3_0 (0x1U << GPIO_CFGR_IOMC3_Pos) /*!< 0x00000040 */ +#define GPIO_CFGR_IOMC3_1 (0x2U << GPIO_CFGR_IOMC3_Pos) /*!< 0x00000080 */ + +/*!< IOMC4 configuration */ +#define GPIO_CFGR_IOMC4_Pos (8U) +#define GPIO_CFGR_IOMC4_Msk (0x3U << GPIO_CFGR_IOMC4_Pos) /*!< 0x00000300 */ +#define GPIO_CFGR_IOMC4 GPIO_CFGR_IOMC4_Msk /*!< IOMC4[1:0] bits (GPIO x mode configuration, pin 4) */ +#define GPIO_CFGR_IOMC4_0 (0x1U << GPIO_CFGR_IOMC4_Pos) /*!< 0x00000100 */ +#define GPIO_CFGR_IOMC4_1 (0x2U << GPIO_CFGR_IOMC4_Pos) /*!< 0x00000200 */ + +/*!< IOMC5 configuration */ +#define GPIO_CFGR_IOMC5_Pos (10U) +#define GPIO_CFGR_IOMC5_Msk (0x3U << GPIO_CFGR_IOMC5_Pos) /*!< 0x00000C00 */ +#define GPIO_CFGR_IOMC5 GPIO_CFGR_IOMC5_Msk /*!< IOMC5[1:0] bits (GPIO x mode configuration, pin 5) */ +#define GPIO_CFGR_IOMC5_0 (0x1U << GPIO_CFGR_IOMC5_Pos) /*!< 0x00000400 */ +#define GPIO_CFGR_IOMC5_1 (0x2U << GPIO_CFGR_IOMC5_Pos) /*!< 0x00000800 */ + +/*!< IOMC6 configuration */ +#define GPIO_CFGR_IOMC6_Pos (12U) +#define GPIO_CFGR_IOMC6_Msk (0x3U << GPIO_CFGR_IOMC6_Pos) /*!< 0x00003000 */ +#define GPIO_CFGR_IOMC6 GPIO_CFGR_IOMC6_Msk /*!< IOMC6[1:0] bits (GPIO x mode configuration, pin 6) */ +#define GPIO_CFGR_IOMC6_0 (0x1U << GPIO_CFGR_IOMC6_Pos) /*!< 0x00001000 */ +#define GPIO_CFGR_IOMC6_1 (0x2U << GPIO_CFGR_IOMC6_Pos) /*!< 0x00002000 */ + +/*!< IOMC7 configuration */ +#define GPIO_CFGR_IOMC7_Pos (14U) +#define GPIO_CFGR_IOMC7_Msk (0x3U << GPIO_CFGR_IOMC7_Pos) /*!< 0x0000C000 */ +#define GPIO_CFGR_IOMC7 GPIO_CFGR_IOMC7_Msk /*!< IOMC7[1:0] bits (GPIO x mode configuration, pin 7) */ +#define GPIO_CFGR_IOMC7_0 (0x1U << GPIO_CFGR_IOMC7_Pos) /*!< 0x00004000 */ +#define GPIO_CFGR_IOMC7_1 (0x2U << GPIO_CFGR_IOMC7_Pos) /*!< 0x00008000 */ + +/*!< IOMC8 configuration */ +#define GPIO_CFGR_IOMC8_Pos (16U) +#define GPIO_CFGR_IOMC8_Msk (0x3U << GPIO_CFGR_IOMC8_Pos) /*!< 0x00030000 */ +#define GPIO_CFGR_IOMC8 GPIO_CFGR_IOMC8_Msk /*!< IOMC8[1:0] bits (GPIO x mode configuration, pin 8) */ +#define GPIO_CFGR_IOMC8_0 (0x1U << GPIO_CFGR_IOMC8_Pos) /*!< 0x00010000 */ +#define GPIO_CFGR_IOMC8_1 (0x2U << GPIO_CFGR_IOMC8_Pos) /*!< 0x00020000 */ + +/*!< IOMC9 configuration */ +#define GPIO_CFGR_IOMC9_Pos (18U) +#define GPIO_CFGR_IOMC9_Msk (0x3U << GPIO_CFGR_IOMC9_Pos) /*!< 0x000C0000 */ +#define GPIO_CFGR_IOMC9 GPIO_CFGR_IOMC9_Msk /*!< IOMC9[1:0] bits (GPIO x mode configuration, pin 9) */ +#define GPIO_CFGR_IOMC9_0 (0x1U << GPIO_CFGR_IOMC9_Pos) /*!< 0x00040000 */ +#define GPIO_CFGR_IOMC9_1 (0x2U << GPIO_CFGR_IOMC9_Pos) /*!< 0x00080000 */ + +/*!< IOMC10 configuration */ +#define GPIO_CFGR_IOMC10_Pos (20U) +#define GPIO_CFGR_IOMC10_Msk (0x3U << GPIO_CFGR_IOMC10_Pos) /*!< 0x00300000 */ +#define GPIO_CFGR_IOMC10 GPIO_CFGR_IOMC10_Msk /*!< IOMC10[1:0] bits (GPIO x mode configuration, pin 10) */ +#define GPIO_CFGR_IOMC10_0 (0x1U << GPIO_CFGR_IOMC10_Pos) /*!< 0x00100000 */ +#define GPIO_CFGR_IOMC10_1 (0x2U << GPIO_CFGR_IOMC10_Pos) /*!< 0x00200000 */ + +/*!< IOMC11 configuration */ +#define GPIO_CFGR_IOMC11_Pos (22U) +#define GPIO_CFGR_IOMC11_Msk (0x3U << GPIO_CFGR_IOMC11_Pos) /*!< 0x00C00000 */ +#define GPIO_CFGR_IOMC11 GPIO_CFGR_IOMC11_Msk /*!< IOMC11[1:0] bits (GPIO x mode configuration, pin 11) */ +#define GPIO_CFGR_IOMC11_0 (0x1U << GPIO_CFGR_IOMC11_Pos) /*!< 0x00400000 */ +#define GPIO_CFGR_IOMC11_1 (0x2U << GPIO_CFGR_IOMC11_Pos) /*!< 0x00800000 */ + +/*!< IOMC12 configuration */ +#define GPIO_CFGR_IOMC12_Pos (24U) +#define GPIO_CFGR_IOMC12_Msk (0x3U << GPIO_CFGR_IOMC12_Pos) /*!< 0x03000000 */ +#define GPIO_CFGR_IOMC12 GPIO_CFGR_IOMC12_Msk /*!< IOMC12[1:0] bits (GPIO x mode configuration, pin 12) */ +#define GPIO_CFGR_IOMC12_0 (0x1U << GPIO_CFGR_IOMC12_Pos) /*!< 0x01000000 */ +#define GPIO_CFGR_IOMC12_1 (0x2U << GPIO_CFGR_IOMC12_Pos) /*!< 0x02000000 */ + +/*!< IOMC13 configuration */ +#define GPIO_CFGR_IOMC13_Pos (26U) +#define GPIO_CFGR_IOMC13_Msk (0x3U << GPIO_CFGR_IOMC13_Pos) /*!< 0x0C000000 */ +#define GPIO_CFGR_IOMC13 GPIO_CFGR_IOMC13_Msk /*!< IOMC13[1:0] bits (GPIO x mode configuration, pin 13) */ +#define GPIO_CFGR_IOMC13_0 (0x1U << GPIO_CFGR_IOMC13_Pos) /*!< 0x04000000 */ +#define GPIO_CFGR_IOMC13_1 (0x2U << GPIO_CFGR_IOMC13_Pos) /*!< 0x08000000 */ + +/*!< IOMC14 configuration */ +#define GPIO_CFGR_IOMC14_Pos (28U) +#define GPIO_CFGR_IOMC14_Msk (0x3U << GPIO_CFGR_IOMC14_Pos) /*!< 0x30000000 */ +#define GPIO_CFGR_IOMC14 GPIO_CFGR_IOMC14_Msk /*!< IOMC14[1:0] bits (GPIO x mode configuration, pin 14) */ +#define GPIO_CFGR_IOMC14_0 (0x1U << GPIO_CFGR_IOMC14_Pos) /*!< 0x10000000 */ +#define GPIO_CFGR_IOMC14_1 (0x2U << GPIO_CFGR_IOMC14_Pos) /*!< 0x20000000 */ + +/*!< IOMC15 configuration */ +#define GPIO_CFGR_IOMC15_Pos (30U) +#define GPIO_CFGR_IOMC15_Msk (0x3U << GPIO_CFGR_IOMC15_Pos) /*!< 0xC0000000 */ +#define GPIO_CFGR_IOMC15 GPIO_CFGR_IOMC15_Msk /*!< IOMC15[1:0] bits (GPIO x mode configuration, pin 15) */ +#define GPIO_CFGR_IOMC15_0 (0x1U << GPIO_CFGR_IOMC15_Pos) /*!< 0x40000000 */ +#define GPIO_CFGR_IOMC15_1 (0x2U << GPIO_CFGR_IOMC15_Pos) /*!< 0x80000000 */ + +/****************** Bit definition for GPIO_OMODE register ******************/ +#define GPIO_OMODE_OM0_Pos (0U) +#define GPIO_OMODE_OM0_Msk (0x1U << GPIO_OMODE_OM0_Pos) /*!< 0x00000001 */ +#define GPIO_OMODE_OM0 GPIO_OMODE_OM0_Msk /*!< GPIO x output mode configuration, pin 0 */ +#define GPIO_OMODE_OM1_Pos (1U) +#define GPIO_OMODE_OM1_Msk (0x3U << GPIO_OMODE_OM1_Pos) /*!< 0x00000002 */ +#define GPIO_OMODE_OM1 GPIO_OMODE_OM1_Msk /*!< GPIO x output mode configuration, pin 1 */ +#define GPIO_OMODE_OM2_Pos (2U) +#define GPIO_OMODE_OM2_Msk (0x3U << GPIO_OMODE_OM2_Pos) /*!< 0x00000004 */ +#define GPIO_OMODE_OM2 GPIO_OMODE_OM2_Msk /*!< GPIO x output mode configuration, pin 2 */ +#define GPIO_OMODE_OM3_Pos (3U) +#define GPIO_OMODE_OM3_Msk (0x3U << GPIO_OMODE_OM3_Pos) /*!< 0x00000008 */ +#define GPIO_OMODE_OM3 GPIO_OMODE_OM3_Msk /*!< GPIO x output mode configuration, pin 3 */ +#define GPIO_OMODE_OM4_Pos (4U) +#define GPIO_OMODE_OM4_Msk (0x3U << GPIO_OMODE_OM4_Pos) /*!< 0x00000010 */ +#define GPIO_OMODE_OM4 GPIO_OMODE_OM4_Msk /*!< GPIO x output mode configuration, pin 4 */ +#define GPIO_OMODE_OM5_Pos (5U) +#define GPIO_OMODE_OM5_Msk (0x3U << GPIO_OMODE_OM5_Pos) /*!< 0x00000020 */ +#define GPIO_OMODE_OM5 GPIO_OMODE_OM5_Msk /*!< GPIO x output mode configuration, pin 5 */ +#define GPIO_OMODE_OM6_Pos (6U) +#define GPIO_OMODE_OM6_Msk (0x3U << GPIO_OMODE_OM6_Pos) /*!< 0x00000040 */ +#define GPIO_OMODE_OM6 GPIO_OMODE_OM6_Msk /*!< GPIO x output mode configuration, pin 6 */ +#define GPIO_OMODE_OM7_Pos (7U) +#define GPIO_OMODE_OM7_Msk (0x3U << GPIO_OMODE_OM7_Pos) /*!< 0x00000080 */ +#define GPIO_OMODE_OM7 GPIO_OMODE_OM7_Msk /*!< GPIO x output mode configuration, pin 7 */ +#define GPIO_OMODE_OM8_Pos (8U) +#define GPIO_OMODE_OM8_Msk (0x1U << GPIO_OMODE_OM8_Pos) /*!< 0x00000100 */ +#define GPIO_OMODE_OM8 GPIO_OMODE_OM8_Msk /*!< GPIO x output mode configuration, pin 8 */ +#define GPIO_OMODE_OM9_Pos (9U) +#define GPIO_OMODE_OM9_Msk (0x1U << GPIO_OMODE_OM9_Pos) /*!< 0x00000200 */ +#define GPIO_OMODE_OM9 GPIO_OMODE_OM9_Msk /*!< GPIO x output mode configuration, pin 9 */ +#define GPIO_OMODE_OM10_Pos (10U) +#define GPIO_OMODE_OM10_Msk (0x1U << GPIO_OMODE_OM10_Pos) /*!< 0x00000400 */ +#define GPIO_OMODE_OM10 GPIO_OMODE_OM10_Msk /*!< GPIO x output mode configuration, pin 10 */ +#define GPIO_OMODE_OM11_Pos (11U) +#define GPIO_OMODE_OM11_Msk (0x1U << GPIO_OMODE_OM11_Pos) /*!< 0x00000800 */ +#define GPIO_OMODE_OM11 GPIO_OMODE_OM11_Msk /*!< GPIO x output mode configuration, pin 11 */ +#define GPIO_OMODE_OM12_Pos (12U) +#define GPIO_OMODE_OM12_Msk (0x1U << GPIO_OMODE_OM12_Pos) /*!< 0x00001000 */ +#define GPIO_OMODE_OM12 GPIO_OMODE_OM12_Msk /*!< GPIO x output mode configuration, pin 12 */ +#define GPIO_OMODE_OM13_Pos (13U) +#define GPIO_OMODE_OM13_Msk (0x1U << GPIO_OMODE_OM13_Pos) /*!< 0x00002000 */ +#define GPIO_OMODE_OM13 GPIO_OMODE_OM13_Msk /*!< GPIO x output mode configuration, pin 13 */ +#define GPIO_OMODE_OM14_Pos (14U) +#define GPIO_OMODE_OM14_Msk (0x1U << GPIO_OMODE_OM14_Pos) /*!< 0x00004000 */ +#define GPIO_OMODE_OM14 GPIO_OMODE_OM14_Msk /*!< GPIO x output mode configuration, pin 14 */ +#define GPIO_OMODE_OM15_Pos (15U) +#define GPIO_OMODE_OM15_Msk (0x1U << GPIO_OMODE_OM15_Pos) /*!< 0x00008000 */ +#define GPIO_OMODE_OM15 GPIO_OMODE_OM15_Msk /*!< GPIO x output mode configuration, pin 15 */ + +/*!<*************** Bit definition for GPIO_ODRVR register ******************/ +#define GPIO_ODRVR_ODRV_Pos (0U) +#define GPIO_ODRVR_ODRV_Msk (0xFFFFFFFFU << GPIO_ODRVR_ODRV_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_ODRVR_ODRV GPIO_ODRVR_ODRV_Msk /*!< GPIO x drive capability */ + +/*!< ODRV0 configuration */ +#define GPIO_ODRVR_ODRV0_Pos (0U) +#define GPIO_ODRVR_ODRV0_Msk (0x3U << GPIO_ODRVR_ODRV0_Pos) /*!< 0x00000003 */ +#define GPIO_ODRVR_ODRV0 GPIO_ODRVR_ODRV0_Msk /*!< ODRV0[1:0] bits (GPIO x drive capability, pin 0) */ +#define GPIO_ODRVR_ODRV0_0 (0x1U << GPIO_ODRVR_ODRV0_Pos) /*!< 0x00000001 */ +#define GPIO_ODRVR_ODRV0_1 (0x2U << GPIO_ODRVR_ODRV0_Pos) /*!< 0x00000002 */ + +/*!< ODRV1 configuration */ +#define GPIO_ODRVR_ODRV1_Pos (2U) +#define GPIO_ODRVR_ODRV1_Msk (0x3U << GPIO_ODRVR_ODRV1_Pos) /*!< 0x0000000C */ +#define GPIO_ODRVR_ODRV1 GPIO_ODRVR_ODRV1_Msk /*!< ODRV1[1:0] bits (GPIO x drive capability, pin 1) */ +#define GPIO_ODRVR_ODRV1_0 (0x1U << GPIO_ODRVR_ODRV1_Pos) /*!< 0x00000004 */ +#define GPIO_ODRVR_ODRV1_1 (0x2U << GPIO_ODRVR_ODRV1_Pos) /*!< 0x00000008 */ + +/*!< ODRV2 configuration */ +#define GPIO_ODRVR_ODRV2_Pos (4U) +#define GPIO_ODRVR_ODRV2_Msk (0x3U << GPIO_ODRVR_ODRV2_Pos) /*!< 0x00000030 */ +#define GPIO_ODRVR_ODRV2 GPIO_ODRVR_ODRV2_Msk /*!< ODRV2[1:0] bits (GPIO x drive capability, pin 2) */ +#define GPIO_ODRVR_ODRV2_0 (0x1U << GPIO_ODRVR_ODRV2_Pos) /*!< 0x00000010 */ +#define GPIO_ODRVR_ODRV2_1 (0x2U << GPIO_ODRVR_ODRV2_Pos) /*!< 0x00000020 */ + +/*!< ODRV3 configuration */ +#define GPIO_ODRVR_ODRV3_Pos (6U) +#define GPIO_ODRVR_ODRV3_Msk (0x3U << GPIO_ODRVR_ODRV3_Pos) /*!< 0x000000C0 */ +#define GPIO_ODRVR_ODRV3 GPIO_ODRVR_ODRV3_Msk /*!< ODRV3[1:0] bits (GPIO x drive capability, pin 3) */ +#define GPIO_ODRVR_ODRV3_0 (0x1U << GPIO_ODRVR_ODRV3_Pos) /*!< 0x00000040 */ +#define GPIO_ODRVR_ODRV3_1 (0x2U << GPIO_ODRVR_ODRV3_Pos) /*!< 0x00000080 */ + +/*!< ODRV4 configuration */ +#define GPIO_ODRVR_ODRV4_Pos (8U) +#define GPIO_ODRVR_ODRV4_Msk (0x3U << GPIO_ODRVR_ODRV4_Pos) /*!< 0x00000300 */ +#define GPIO_ODRVR_ODRV4 GPIO_ODRVR_ODRV4_Msk /*!< ODRV4[1:0] bits (GPIO x drive capability, pin 4) */ +#define GPIO_ODRVR_ODRV4_0 (0x1U << GPIO_ODRVR_ODRV4_Pos) /*!< 0x00000100 */ +#define GPIO_ODRVR_ODRV4_1 (0x2U << GPIO_ODRVR_ODRV4_Pos) /*!< 0x00000200 */ + +/*!< ODRV5 configuration */ +#define GPIO_ODRVR_ODRV5_Pos (10U) +#define GPIO_ODRVR_ODRV5_Msk (0x3U << GPIO_ODRVR_ODRV5_Pos) /*!< 0x00000C00 */ +#define GPIO_ODRVR_ODRV5 GPIO_ODRVR_ODRV5_Msk /*!< ODRV5[1:0] bits (GPIO x drive capability, pin 5) */ +#define GPIO_ODRVR_ODRV5_0 (0x1U << GPIO_ODRVR_ODRV5_Pos) /*!< 0x00000400 */ +#define GPIO_ODRVR_ODRV5_1 (0x2U << GPIO_ODRVR_ODRV5_Pos) /*!< 0x00000800 */ + +/*!< ODRV6 configuration */ +#define GPIO_ODRVR_ODRV6_Pos (12U) +#define GPIO_ODRVR_ODRV6_Msk (0x3U << GPIO_ODRVR_ODRV6_Pos) /*!< 0x00003000 */ +#define GPIO_ODRVR_ODRV6 GPIO_ODRVR_ODRV6_Msk /*!< ODRV6[1:0] bits (GPIO x drive capability, pin 6) */ +#define GPIO_ODRVR_ODRV6_0 (0x1U << GPIO_ODRVR_ODRV6_Pos) /*!< 0x00001000 */ +#define GPIO_ODRVR_ODRV6_1 (0x2U << GPIO_ODRVR_ODRV6_Pos) /*!< 0x00002000 */ + +/*!< ODRV7 configuration */ +#define GPIO_ODRVR_ODRV7_Pos (14U) +#define GPIO_ODRVR_ODRV7_Msk (0x3U << GPIO_ODRVR_ODRV7_Pos) /*!< 0x0000C000 */ +#define GPIO_ODRVR_ODRV7 GPIO_ODRVR_ODRV7_Msk /*!< ODRV7[1:0] bits (GPIO x drive capability, pin 7) */ +#define GPIO_ODRVR_ODRV7_0 (0x1U << GPIO_ODRVR_ODRV7_Pos) /*!< 0x00004000 */ +#define GPIO_ODRVR_ODRV7_1 (0x2U << GPIO_ODRVR_ODRV7_Pos) /*!< 0x00008000 */ + +/*!< ODRV8 configuration */ +#define GPIO_ODRVR_ODRV8_Pos (16U) +#define GPIO_ODRVR_ODRV8_Msk (0x3U << GPIO_ODRVR_ODRV8_Pos) /*!< 0x00030000 */ +#define GPIO_ODRVR_ODRV8 GPIO_ODRVR_ODRV8_Msk /*!< ODRV8[1:0] bits (GPIO x drive capability, pin 8) */ +#define GPIO_ODRVR_ODRV8_0 (0x1U << GPIO_ODRVR_ODRV8_Pos) /*!< 0x00010000 */ +#define GPIO_ODRVR_ODRV8_1 (0x2U << GPIO_ODRVR_ODRV8_Pos) /*!< 0x00020000 */ + +/*!< ODRV9 configuration */ +#define GPIO_ODRVR_ODRV9_Pos (18U) +#define GPIO_ODRVR_ODRV9_Msk (0x3U << GPIO_ODRVR_ODRV9_Pos) /*!< 0x000C0000 */ +#define GPIO_ODRVR_ODRV9 GPIO_ODRVR_ODRV9_Msk /*!< ODRV9[1:0] bits (GPIO x drive capability, pin 9) */ +#define GPIO_ODRVR_ODRV9_0 (0x1U << GPIO_ODRVR_ODRV9_Pos) /*!< 0x00040000 */ +#define GPIO_ODRVR_ODRV9_1 (0x2U << GPIO_ODRVR_ODRV9_Pos) /*!< 0x00080000 */ + +/*!< ODRV10 configuration */ +#define GPIO_ODRVR_ODRV10_Pos (20U) +#define GPIO_ODRVR_ODRV10_Msk (0x3U << GPIO_ODRVR_ODRV10_Pos) /*!< 0x00300000 */ +#define GPIO_ODRVR_ODRV10 GPIO_ODRVR_ODRV10_Msk /*!< ODRV10[1:0] bits (GPIO x drive capability, pin 10) */ +#define GPIO_ODRVR_ODRV10_0 (0x1U << GPIO_ODRVR_ODRV10_Pos) /*!< 0x00100000 */ +#define GPIO_ODRVR_ODRV10_1 (0x2U << GPIO_ODRVR_ODRV10_Pos) /*!< 0x00200000 */ + +/*!< ODRV11 configuration */ +#define GPIO_ODRVR_ODRV11_Pos (22U) +#define GPIO_ODRVR_ODRV11_Msk (0x3U << GPIO_ODRVR_ODRV11_Pos) /*!< 0x00C00000 */ +#define GPIO_ODRVR_ODRV11 GPIO_ODRVR_ODRV11_Msk /*!< ODRV11[1:0] bits (GPIO x drive capability, pin 11) */ +#define GPIO_ODRVR_ODRV11_0 (0x1U << GPIO_ODRVR_ODRV11_Pos) /*!< 0x00400000 */ +#define GPIO_ODRVR_ODRV11_1 (0x2U << GPIO_ODRVR_ODRV11_Pos) /*!< 0x00800000 */ + +/*!< ODRV12 configuration */ +#define GPIO_ODRVR_ODRV12_Pos (24U) +#define GPIO_ODRVR_ODRV12_Msk (0x3U << GPIO_ODRVR_ODRV12_Pos) /*!< 0x03000000 */ +#define GPIO_ODRVR_ODRV12 GPIO_ODRVR_ODRV12_Msk /*!< ODRV12[1:0] bits (GPIO x drive capability, pin 12) */ +#define GPIO_ODRVR_ODRV12_0 (0x1U << GPIO_ODRVR_ODRV12_Pos) /*!< 0x01000000 */ +#define GPIO_ODRVR_ODRV12_1 (0x2U << GPIO_ODRVR_ODRV12_Pos) /*!< 0x02000000 */ + +/*!< ODRV13 configuration */ +#define GPIO_ODRVR_ODRV13_Pos (26U) +#define GPIO_ODRVR_ODRV13_Msk (0x3U << GPIO_ODRVR_ODRV13_Pos) /*!< 0x0C000000 */ +#define GPIO_ODRVR_ODRV13 GPIO_ODRVR_ODRV13_Msk /*!< ODRV13[1:0] bits (GPIO x drive capability, pin 13) */ +#define GPIO_ODRVR_ODRV13_0 (0x1U << GPIO_ODRVR_ODRV13_Pos) /*!< 0x04000000 */ +#define GPIO_ODRVR_ODRV13_1 (0x2U << GPIO_ODRVR_ODRV13_Pos) /*!< 0x08000000 */ + +/*!< ODRV14 configuration */ +#define GPIO_ODRVR_ODRV14_Pos (28U) +#define GPIO_ODRVR_ODRV14_Msk (0x3U << GPIO_ODRVR_ODRV14_Pos) /*!< 0x30000000 */ +#define GPIO_ODRVR_ODRV14 GPIO_ODRVR_ODRV14_Msk /*!< ODRV14[1:0] bits (GPIO x drive capability, pin 14) */ +#define GPIO_ODRVR_ODRV14_0 (0x1U << GPIO_ODRVR_ODRV14_Pos) /*!< 0x10000000 */ +#define GPIO_ODRVR_ODRV14_1 (0x2U << GPIO_ODRVR_ODRV14_Pos) /*!< 0x20000000 */ + +/*!< ODRV15 configuration */ +#define GPIO_ODRVR_ODRV15_Pos (30U) +#define GPIO_ODRVR_ODRV15_Msk (0x3U << GPIO_ODRVR_ODRV15_Pos) /*!< 0xC0000000 */ +#define GPIO_ODRVR_ODRV15 GPIO_ODRVR_ODRV15_Msk /*!< ODRV15[1:0] bits (GPIO x drive capability, pin 15) */ +#define GPIO_ODRVR_ODRV15_0 (0x1U << GPIO_ODRVR_ODRV15_Pos) /*!< 0x40000000 */ +#define GPIO_ODRVR_ODRV15_1 (0x2U << GPIO_ODRVR_ODRV15_Pos) /*!< 0x80000000 */ + +/*!<*************** Bit definition for GPIO_PULL register *******************/ +#define GPIO_PULL_PULL_Pos (0U) +#define GPIO_PULL_PULL_Msk (0xFFFFFFFFU << GPIO_PULL_PULL_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_PULL_PULL GPIO_PULL_PULL_Msk /*!< GPIO x pull-up/pull-down configuration */ + +/*!< PULL0 configuration */ +#define GPIO_PULL_PULL0_Pos (0U) +#define GPIO_PULL_PULL0_Msk (0x3U << GPIO_PULL_PULL0_Pos) /*!< 0x00000003 */ +#define GPIO_PULL_PULL0 GPIO_PULL_PULL0_Msk /*!< PULL0[1:0] bits (GPIO x pull-up/pull-down configuration, pin 0) */ +#define GPIO_PULL_PULL0_0 (0x1U << GPIO_PULL_PULL0_Pos) /*!< 0x00000001 */ +#define GPIO_PULL_PULL0_1 (0x2U << GPIO_PULL_PULL0_Pos) /*!< 0x00000002 */ + +/*!< PULL1 configuration */ +#define GPIO_PULL_PULL1_Pos (2U) +#define GPIO_PULL_PULL1_Msk (0x3U << GPIO_PULL_PULL1_Pos) /*!< 0x0000000C */ +#define GPIO_PULL_PULL1 GPIO_PULL_PULL1_Msk /*!< PULL1[1:0] bits (GPIO x pull-up/pull-down configuration, pin 1) */ +#define GPIO_PULL_PULL1_0 (0x1U << GPIO_PULL_PULL1_Pos) /*!< 0x00000004 */ +#define GPIO_PULL_PULL1_1 (0x2U << GPIO_PULL_PULL1_Pos) /*!< 0x00000008 */ + +/*!< PULL2 configuration */ +#define GPIO_PULL_PULL2_Pos (4U) +#define GPIO_PULL_PULL2_Msk (0x3U << GPIO_PULL_PULL2_Pos) /*!< 0x00000030 */ +#define GPIO_PULL_PULL2 GPIO_PULL_PULL2_Msk /*!< PULL2[1:0] bits (GPIO x pull-up/pull-down configuration, pin 2) */ +#define GPIO_PULL_PULL2_0 (0x1U << GPIO_PULL_PULL2_Pos) /*!< 0x00000010 */ +#define GPIO_PULL_PULL2_1 (0x2U << GPIO_PULL_PULL2_Pos) /*!< 0x00000020 */ + +/*!< PULL3 configuration */ +#define GPIO_PULL_PULL3_Pos (6U) +#define GPIO_PULL_PULL3_Msk (0x3U << GPIO_PULL_PULL3_Pos) /*!< 0x000000C0 */ +#define GPIO_PULL_PULL3 GPIO_PULL_PULL3_Msk /*!< PULL3[1:0] bits (GPIO x pull-up/pull-down configuration, pin 3) */ +#define GPIO_PULL_PULL3_0 (0x1U << GPIO_PULL_PULL3_Pos) /*!< 0x00000040 */ +#define GPIO_PULL_PULL3_1 (0x2U << GPIO_PULL_PULL3_Pos) /*!< 0x00000080 */ + +/*!< PULL4 configuration */ +#define GPIO_PULL_PULL4_Pos (8U) +#define GPIO_PULL_PULL4_Msk (0x3U << GPIO_PULL_PULL4_Pos) /*!< 0x00000300 */ +#define GPIO_PULL_PULL4 GPIO_PULL_PULL4_Msk /*!< PULL4[1:0] bits (GPIO x pull-up/pull-down configuration, pin 4) */ +#define GPIO_PULL_PULL4_0 (0x1U << GPIO_PULL_PULL4_Pos) /*!< 0x00000100 */ +#define GPIO_PULL_PULL4_1 (0x2U << GPIO_PULL_PULL4_Pos) /*!< 0x00000200 */ + +/*!< PULL5 configuration */ +#define GPIO_PULL_PULL5_Pos (10U) +#define GPIO_PULL_PULL5_Msk (0x3U << GPIO_PULL_PULL5_Pos) /*!< 0x00000C00 */ +#define GPIO_PULL_PULL5 GPIO_PULL_PULL5_Msk /*!< PULL5[1:0] bits (GPIO x pull-up/pull-down configuration, pin 5) */ +#define GPIO_PULL_PULL5_0 (0x1U << GPIO_PULL_PULL5_Pos) /*!< 0x00000400 */ +#define GPIO_PULL_PULL5_1 (0x2U << GPIO_PULL_PULL5_Pos) /*!< 0x00000800 */ + +/*!< PULL6 configuration */ +#define GPIO_PULL_PULL6_Pos (12U) +#define GPIO_PULL_PULL6_Msk (0x3U << GPIO_PULL_PULL6_Pos) /*!< 0x00003000 */ +#define GPIO_PULL_PULL6 GPIO_PULL_PULL6_Msk /*!< PULL6[1:0] bits (GPIO x pull-up/pull-down configuration, pin 6) */ +#define GPIO_PULL_PULL6_0 (0x1U << GPIO_PULL_PULL6_Pos) /*!< 0x00001000 */ +#define GPIO_PULL_PULL6_1 (0x2U << GPIO_PULL_PULL6_Pos) /*!< 0x00002000 */ + +/*!< PULL7 configuration */ +#define GPIO_PULL_PULL7_Pos (14U) +#define GPIO_PULL_PULL7_Msk (0x3U << GPIO_PULL_PULL7_Pos) /*!< 0x0000C000 */ +#define GPIO_PULL_PULL7 GPIO_PULL_PULL7_Msk /*!< PULL7[1:0] bits (GPIO x pull-up/pull-down configuration, pin 7) */ +#define GPIO_PULL_PULL7_0 (0x1U << GPIO_PULL_PULL7_Pos) /*!< 0x00004000 */ +#define GPIO_PULL_PULL7_1 (0x2U << GPIO_PULL_PULL7_Pos) /*!< 0x00008000 */ + +/*!< PULL8 configuration */ +#define GPIO_PULL_PULL8_Pos (16U) +#define GPIO_PULL_PULL8_Msk (0x3U << GPIO_PULL_PULL8_Pos) /*!< 0x00030000 */ +#define GPIO_PULL_PULL8 GPIO_PULL_PULL8_Msk /*!< PULL8[1:0] bits (GPIO x pull-up/pull-down configuration, pin 8) */ +#define GPIO_PULL_PULL8_0 (0x1U << GPIO_PULL_PULL8_Pos) /*!< 0x00010000 */ +#define GPIO_PULL_PULL8_1 (0x2U << GPIO_PULL_PULL8_Pos) /*!< 0x00020000 */ + +/*!< PULL9 configuration */ +#define GPIO_PULL_PULL9_Pos (18U) +#define GPIO_PULL_PULL9_Msk (0x3U << GPIO_PULL_PULL9_Pos) /*!< 0x000C0000 */ +#define GPIO_PULL_PULL9 GPIO_PULL_PULL9_Msk /*!< PULL9[1:0] bits (GPIO x pull-up/pull-down configuration, pin 9) */ +#define GPIO_PULL_PULL9_0 (0x1U << GPIO_PULL_PULL9_Pos) /*!< 0x00040000 */ +#define GPIO_PULL_PULL9_1 (0x2U << GPIO_PULL_PULL9_Pos) /*!< 0x00080000 */ + +/*!< PULL10 configuration */ +#define GPIO_PULL_PULL10_Pos (20U) +#define GPIO_PULL_PULL10_Msk (0x3U << GPIO_PULL_PULL10_Pos) /*!< 0x00300000 */ +#define GPIO_PULL_PULL10 GPIO_PULL_PULL10_Msk /*!< PULL10[1:0] bits (GPIO x pull-up/pull-down configuration, pin 10) */ +#define GPIO_PULL_PULL10_0 (0x1U << GPIO_PULL_PULL10_Pos) /*!< 0x00100000 */ +#define GPIO_PULL_PULL10_1 (0x2U << GPIO_PULL_PULL10_Pos) /*!< 0x00200000 */ + +/*!< PULL11 configuration */ +#define GPIO_PULL_PULL11_Pos (22U) +#define GPIO_PULL_PULL11_Msk (0x3U << GPIO_PULL_PULL11_Pos) /*!< 0x00C00000 */ +#define GPIO_PULL_PULL11 GPIO_PULL_PULL11_Msk /*!< PULL11[1:0] bits (GPIO x pull-up/pull-down configuration, pin 11) */ +#define GPIO_PULL_PULL11_0 (0x1U << GPIO_PULL_PULL11_Pos) /*!< 0x00400000 */ +#define GPIO_PULL_PULL11_1 (0x2U << GPIO_PULL_PULL11_Pos) /*!< 0x00800000 */ + +/*!< PULL12 configuration */ +#define GPIO_PULL_PULL12_Pos (24U) +#define GPIO_PULL_PULL12_Msk (0x3U << GPIO_PULL_PULL12_Pos) /*!< 0x03000000 */ +#define GPIO_PULL_PULL12 GPIO_PULL_PULL12_Msk /*!< PULL12[1:0] bits (GPIO x pull-up/pull-down configuration, pin 12) */ +#define GPIO_PULL_PULL12_0 (0x1U << GPIO_PULL_PULL12_Pos) /*!< 0x01000000 */ +#define GPIO_PULL_PULL12_1 (0x2U << GPIO_PULL_PULL12_Pos) /*!< 0x02000000 */ + +/*!< PULL13 configuration */ +#define GPIO_PULL_PULL13_Pos (26U) +#define GPIO_PULL_PULL13_Msk (0x3U << GPIO_PULL_PULL13_Pos) /*!< 0x0C000000 */ +#define GPIO_PULL_PULL13 GPIO_PULL_PULL13_Msk /*!< PULL13[1:0] bits (GPIO x pull-up/pull-down configuration, pin 13) */ +#define GPIO_PULL_PULL13_0 (0x1U << GPIO_PULL_PULL13_Pos) /*!< 0x04000000 */ +#define GPIO_PULL_PULL13_1 (0x2U << GPIO_PULL_PULL13_Pos) /*!< 0x08000000 */ + +/*!< PULL14 configuration */ +#define GPIO_PULL_PULL14_Pos (28U) +#define GPIO_PULL_PULL14_Msk (0x3U << GPIO_PULL_PULL14_Pos) /*!< 0x30000000 */ +#define GPIO_PULL_PULL14 GPIO_PULL_PULL14_Msk /*!< PULL14[1:0] bits (GPIO x pull-up/pull-down configuration, pin 14) */ +#define GPIO_PULL_PULL14_0 (0x1U << GPIO_PULL_PULL14_Pos) /*!< 0x10000000 */ +#define GPIO_PULL_PULL14_1 (0x2U << GPIO_PULL_PULL14_Pos) /*!< 0x20000000 */ + +/*!< PULL15 configuration */ +#define GPIO_PULL_PULL15_Pos (30U) +#define GPIO_PULL_PULL15_Msk (0x3U << GPIO_PULL_PULL15_Pos) /*!< 0xC0000000 */ +#define GPIO_PULL_PULL15 GPIO_PULL_PULL15_Msk /*!< PULL15[1:0] bits (GPIO x pull-up/pull-down configuration, pin 15) */ +#define GPIO_PULL_PULL15_0 (0x1U << GPIO_PULL_PULL15_Pos) /*!< 0x40000000 */ +#define GPIO_PULL_PULL15_1 (0x2U << GPIO_PULL_PULL15_Pos) /*!< 0x80000000 */ + +/*!<**************** Bit definition for GPIO_IDT register *******************/ +#define GPIO_IDT_IDT0_Pos (0U) +#define GPIO_IDT_IDT0_Msk (0x1U << GPIO_IDT_IDT0_Pos) /*!< 0x00000001 */ +#define GPIO_IDT_IDT0 GPIO_IDT_IDT0_Msk /*!< GPIO x input data, pin 0 */ +#define GPIO_IDT_IDT1_Pos (1U) +#define GPIO_IDT_IDT1_Msk (0x1U << GPIO_IDT_IDT1_Pos) /*!< 0x00000002 */ +#define GPIO_IDT_IDT1 GPIO_IDT_IDT1_Msk /*!< GPIO x input data, pin 1 */ +#define GPIO_IDT_IDT2_Pos (2U) +#define GPIO_IDT_IDT2_Msk (0x1U << GPIO_IDT_IDT2_Pos) /*!< 0x00000004 */ +#define GPIO_IDT_IDT2 GPIO_IDT_IDT2_Msk /*!< GPIO x input data, pin 2 */ +#define GPIO_IDT_IDT3_Pos (3U) +#define GPIO_IDT_IDT3_Msk (0x1U << GPIO_IDT_IDT3_Pos) /*!< 0x00000008 */ +#define GPIO_IDT_IDT3 GPIO_IDT_IDT3_Msk /*!< GPIO x input data, pin 3 */ +#define GPIO_IDT_IDT4_Pos (4U) +#define GPIO_IDT_IDT4_Msk (0x1U << GPIO_IDT_IDT4_Pos) /*!< 0x00000010 */ +#define GPIO_IDT_IDT4 GPIO_IDT_IDT4_Msk /*!< GPIO x input data, pin 4 */ +#define GPIO_IDT_IDT5_Pos (5U) +#define GPIO_IDT_IDT5_Msk (0x1U << GPIO_IDT_IDT5_Pos) /*!< 0x00000020 */ +#define GPIO_IDT_IDT5 GPIO_IDT_IDT5_Msk /*!< GPIO x input data, pin 5 */ +#define GPIO_IDT_IDT6_Pos (6U) +#define GPIO_IDT_IDT6_Msk (0x1U << GPIO_IDT_IDT6_Pos) /*!< 0x00000040 */ +#define GPIO_IDT_IDT6 GPIO_IDT_IDT6_Msk /*!< GPIO x input data, pin 6 */ +#define GPIO_IDT_IDT7_Pos (7U) +#define GPIO_IDT_IDT7_Msk (0x1U << GPIO_IDT_IDT7_Pos) /*!< 0x00000080 */ +#define GPIO_IDT_IDT7 GPIO_IDT_IDT7_Msk /*!< GPIO x input data, pin 7 */ +#define GPIO_IDT_IDT8_Pos (8U) +#define GPIO_IDT_IDT8_Msk (0x1U << GPIO_IDT_IDT8_Pos) /*!< 0x00000100 */ +#define GPIO_IDT_IDT8 GPIO_IDT_IDT8_Msk /*!< GPIO x input data, pin 8 */ +#define GPIO_IDT_IDT9_Pos (9U) +#define GPIO_IDT_IDT9_Msk (0x1U << GPIO_IDT_IDT9_Pos) /*!< 0x00000200 */ +#define GPIO_IDT_IDT9 GPIO_IDT_IDT9_Msk /*!< GPIO x input data, pin 9 */ +#define GPIO_IDT_IDT10_Pos (10U) +#define GPIO_IDT_IDT10_Msk (0x1U << GPIO_IDT_IDT10_Pos) /*!< 0x00000400 */ +#define GPIO_IDT_IDT10 GPIO_IDT_IDT10_Msk /*!< GPIO x input data, pin 10 */ +#define GPIO_IDT_IDT11_Pos (11U) +#define GPIO_IDT_IDT11_Msk (0x1U << GPIO_IDT_IDT11_Pos) /*!< 0x00000800 */ +#define GPIO_IDT_IDT11 GPIO_IDT_IDT11_Msk /*!< GPIO x input data, pin 11 */ +#define GPIO_IDT_IDT12_Pos (12U) +#define GPIO_IDT_IDT12_Msk (0x1U << GPIO_IDT_IDT12_Pos) /*!< 0x00001000 */ +#define GPIO_IDT_IDT12 GPIO_IDT_IDT12_Msk /*!< GPIO x input data, pin 12 */ +#define GPIO_IDT_IDT13_Pos (13U) +#define GPIO_IDT_IDT13_Msk (0x1U << GPIO_IDT_IDT13_Pos) /*!< 0x00002000 */ +#define GPIO_IDT_IDT13 GPIO_IDT_IDT13_Msk /*!< GPIO x input data, pin 13 */ +#define GPIO_IDT_IDT14_Pos (14U) +#define GPIO_IDT_IDT14_Msk (0x1U << GPIO_IDT_IDT14_Pos) /*!< 0x00004000 */ +#define GPIO_IDT_IDT14 GPIO_IDT_IDT14_Msk /*!< GPIO x input data, pin 14 */ +#define GPIO_IDT_IDT15_Pos (15U) +#define GPIO_IDT_IDT15_Msk (0x1U << GPIO_IDT_IDT15_Pos) /*!< 0x00008000 */ +#define GPIO_IDT_IDT15 GPIO_IDT_IDT15_Msk /*!< GPIO x input data, pin 15 */ + +/******************* Bit definition for GPIO_ODT register *******************/ +#define GPIO_ODT_ODT0_Pos (0U) +#define GPIO_ODT_ODT0_Msk (0x1U << GPIO_ODT_ODT0_Pos) /*!< 0x00000001 */ +#define GPIO_ODT_ODT0 GPIO_ODT_ODT0_Msk /*!< GPIO x output data, pin 0 */ +#define GPIO_ODT_ODT1_Pos (1U) +#define GPIO_ODT_ODT1_Msk (0x1U << GPIO_ODT_ODT1_Pos) /*!< 0x00000002 */ +#define GPIO_ODT_ODT1 GPIO_ODT_ODT1_Msk /*!< GPIO x output data, pin 1 */ +#define GPIO_ODT_ODT2_Pos (2U) +#define GPIO_ODT_ODT2_Msk (0x1U << GPIO_ODT_ODT2_Pos) /*!< 0x00000004 */ +#define GPIO_ODT_ODT2 GPIO_ODT_ODT2_Msk /*!< GPIO x output data, pin 2 */ +#define GPIO_ODT_ODT3_Pos (3U) +#define GPIO_ODT_ODT3_Msk (0x1U << GPIO_ODT_ODT3_Pos) /*!< 0x00000008 */ +#define GPIO_ODT_ODT3 GPIO_ODT_ODT3_Msk /*!< GPIO x output data, pin 3 */ +#define GPIO_ODT_ODT4_Pos (4U) +#define GPIO_ODT_ODT4_Msk (0x1U << GPIO_ODT_ODT4_Pos) /*!< 0x00000010 */ +#define GPIO_ODT_ODT4 GPIO_ODT_ODT4_Msk /*!< GPIO x output data, pin 4 */ +#define GPIO_ODT_ODT5_Pos (5U) +#define GPIO_ODT_ODT5_Msk (0x1U << GPIO_ODT_ODT5_Pos) /*!< 0x00000020 */ +#define GPIO_ODT_ODT5 GPIO_ODT_ODT5_Msk /*!< GPIO x output data, pin 5 */ +#define GPIO_ODT_ODT6_Pos (6U) +#define GPIO_ODT_ODT6_Msk (0x1U << GPIO_ODT_ODT6_Pos) /*!< 0x00000040 */ +#define GPIO_ODT_ODT6 GPIO_ODT_ODT6_Msk /*!< GPIO x output data, pin 6 */ +#define GPIO_ODT_ODT7_Pos (7U) +#define GPIO_ODT_ODT7_Msk (0x1U << GPIO_ODT_ODT7_Pos) /*!< 0x00000080 */ +#define GPIO_ODT_ODT7 GPIO_ODT_ODT7_Msk /*!< GPIO x output data, pin 7 */ +#define GPIO_ODT_ODT8_Pos (8U) +#define GPIO_ODT_ODT8_Msk (0x1U << GPIO_ODT_ODT8_Pos) /*!< 0x00000100 */ +#define GPIO_ODT_ODT8 GPIO_ODT_ODT8_Msk /*!< GPIO x output data, pin 8 */ +#define GPIO_ODT_ODT9_Pos (9U) +#define GPIO_ODT_ODT9_Msk (0x1U << GPIO_ODT_ODT9_Pos) /*!< 0x00000200 */ +#define GPIO_ODT_ODT9 GPIO_ODT_ODT9_Msk /*!< GPIO x output data, pin 9 */ +#define GPIO_ODT_ODT10_Pos (10U) +#define GPIO_ODT_ODT10_Msk (0x1U << GPIO_ODT_ODT10_Pos) /*!< 0x00000400 */ +#define GPIO_ODT_ODT10 GPIO_ODT_ODT10_Msk /*!< GPIO x output data, pin 10 */ +#define GPIO_ODT_ODT11_Pos (11U) +#define GPIO_ODT_ODT11_Msk (0x1U << GPIO_ODT_ODT11_Pos) /*!< 0x00000800 */ +#define GPIO_ODT_ODT11 GPIO_ODT_ODT11_Msk /*!< GPIO x output data, pin 11 */ +#define GPIO_ODT_ODT12_Pos (12U) +#define GPIO_ODT_ODT12_Msk (0x1U << GPIO_ODT_ODT12_Pos) /*!< 0x00001000 */ +#define GPIO_ODT_ODT12 GPIO_ODT_ODT12_Msk /*!< GPIO x output data, pin 12 */ +#define GPIO_ODT_ODT13_Pos (13U) +#define GPIO_ODT_ODT13_Msk (0x1U << GPIO_ODT_ODT13_Pos) /*!< 0x00002000 */ +#define GPIO_ODT_ODT13 GPIO_ODT_ODT13_Msk /*!< GPIO x output data, pin 13 */ +#define GPIO_ODT_ODT14_Pos (14U) +#define GPIO_ODT_ODT14_Msk (0x1U << GPIO_ODT_ODT14_Pos) /*!< 0x00004000 */ +#define GPIO_ODT_ODT14 GPIO_ODT_ODT14_Msk /*!< GPIO x output data, pin 14 */ +#define GPIO_ODT_ODT15_Pos (15U) +#define GPIO_ODT_ODT15_Msk (0x1U << GPIO_ODT_ODT15_Pos) /*!< 0x00008000 */ +#define GPIO_ODT_ODT15 GPIO_ODT_ODT15_Msk /*!< GPIO x output data, pin 15 */ + +/******************* Bit definition for GPIO_SCR register *******************/ +#define GPIO_SCR_IOSB0_Pos (0U) +#define GPIO_SCR_IOSB0_Msk (0x1U << GPIO_SCR_IOSB0_Pos) /*!< 0x00000001 */ +#define GPIO_SCR_IOSB0 GPIO_SCR_IOSB0_Msk /*!< GPIO x set bit, pin 0 */ +#define GPIO_SCR_IOSB1_Pos (1U) +#define GPIO_SCR_IOSB1_Msk (0x1U << GPIO_SCR_IOSB1_Pos) /*!< 0x00000002 */ +#define GPIO_SCR_IOSB1 GPIO_SCR_IOSB1_Msk /*!< GPIO x set bit, pin 1 */ +#define GPIO_SCR_IOSB2_Pos (2U) +#define GPIO_SCR_IOSB2_Msk (0x1U << GPIO_SCR_IOSB2_Pos) /*!< 0x00000004 */ +#define GPIO_SCR_IOSB2 GPIO_SCR_IOSB2_Msk /*!< GPIO x set bit, pin 2 */ +#define GPIO_SCR_IOSB3_Pos (3U) +#define GPIO_SCR_IOSB3_Msk (0x1U << GPIO_SCR_IOSB3_Pos) /*!< 0x00000008 */ +#define GPIO_SCR_IOSB3 GPIO_SCR_IOSB3_Msk /*!< GPIO x set bit, pin 3 */ +#define GPIO_SCR_IOSB4_Pos (4U) +#define GPIO_SCR_IOSB4_Msk (0x1U << GPIO_SCR_IOSB4_Pos) /*!< 0x00000010 */ +#define GPIO_SCR_IOSB4 GPIO_SCR_IOSB4_Msk /*!< GPIO x set bit, pin 4 */ +#define GPIO_SCR_IOSB5_Pos (5U) +#define GPIO_SCR_IOSB5_Msk (0x1U << GPIO_SCR_IOSB5_Pos) /*!< 0x00000020 */ +#define GPIO_SCR_IOSB5 GPIO_SCR_IOSB5_Msk /*!< GPIO x set bit, pin 5 */ +#define GPIO_SCR_IOSB6_Pos (6U) +#define GPIO_SCR_IOSB6_Msk (0x1U << GPIO_SCR_IOSB6_Pos) /*!< 0x00000040 */ +#define GPIO_SCR_IOSB6 GPIO_SCR_IOSB6_Msk /*!< GPIO x set bit, pin 6 */ +#define GPIO_SCR_IOSB7_Pos (7U) +#define GPIO_SCR_IOSB7_Msk (0x1U << GPIO_SCR_IOSB7_Pos) /*!< 0x00000080 */ +#define GPIO_SCR_IOSB7 GPIO_SCR_IOSB7_Msk /*!< GPIO x set bit, pin 7 */ +#define GPIO_SCR_IOSB8_Pos (8U) +#define GPIO_SCR_IOSB8_Msk (0x1U << GPIO_SCR_IOSB8_Pos) /*!< 0x00000100 */ +#define GPIO_SCR_IOSB8 GPIO_SCR_IOSB8_Msk /*!< GPIO x set bit, pin 8 */ +#define GPIO_SCR_IOSB9_Pos (9U) +#define GPIO_SCR_IOSB9_Msk (0x1U << GPIO_SCR_IOSB9_Pos) /*!< 0x00000200 */ +#define GPIO_SCR_IOSB9 GPIO_SCR_IOSB9_Msk /*!< GPIO x set bit, pin 9 */ +#define GPIO_SCR_IOSB10_Pos (10U) +#define GPIO_SCR_IOSB10_Msk (0x1U << GPIO_SCR_IOSB10_Pos) /*!< 0x00000400 */ +#define GPIO_SCR_IOSB10 GPIO_SCR_IOSB10_Msk /*!< GPIO x set bit, pin 10 */ +#define GPIO_SCR_IOSB11_Pos (11U) +#define GPIO_SCR_IOSB11_Msk (0x1U << GPIO_SCR_IOSB11_Pos) /*!< 0x00000800 */ +#define GPIO_SCR_IOSB11 GPIO_SCR_IOSB11_Msk /*!< GPIO x set bit, pin 11 */ +#define GPIO_SCR_IOSB12_Pos (12U) +#define GPIO_SCR_IOSB12_Msk (0x1U << GPIO_SCR_IOSB12_Pos) /*!< 0x00001000 */ +#define GPIO_SCR_IOSB12 GPIO_SCR_IOSB12_Msk /*!< GPIO x set bit, pin 12 */ +#define GPIO_SCR_IOSB13_Pos (13U) +#define GPIO_SCR_IOSB13_Msk (0x1U << GPIO_SCR_IOSB13_Pos) /*!< 0x00002000 */ +#define GPIO_SCR_IOSB13 GPIO_SCR_IOSB13_Msk /*!< GPIO x set bit, pin 13 */ +#define GPIO_SCR_IOSB14_Pos (14U) +#define GPIO_SCR_IOSB14_Msk (0x1U << GPIO_SCR_IOSB14_Pos) /*!< 0x00004000 */ +#define GPIO_SCR_IOSB14 GPIO_SCR_IOSB14_Msk /*!< GPIO x set bit, pin 14 */ +#define GPIO_SCR_IOSB15_Pos (15U) +#define GPIO_SCR_IOSB15_Msk (0x1U << GPIO_SCR_IOSB15_Pos) /*!< 0x00008000 */ +#define GPIO_SCR_IOSB15 GPIO_SCR_IOSB15_Msk /*!< GPIO x set bit, pin 15 */ +#define GPIO_SCR_IOCB0_Pos (16U) +#define GPIO_SCR_IOCB0_Msk (0x1U << GPIO_SCR_IOCB0_Pos) /*!< 0x00010000 */ +#define GPIO_SCR_IOCB0 GPIO_SCR_IOCB0_Msk /*!< GPIO x clear bit, pin 0 */ +#define GPIO_SCR_IOCB1_Pos (17U) +#define GPIO_SCR_IOCB1_Msk (0x1U << GPIO_SCR_IOCB1_Pos) /*!< 0x00020000 */ +#define GPIO_SCR_IOCB1 GPIO_SCR_IOCB1_Msk /*!< GPIO x clear bit, pin 1 */ +#define GPIO_SCR_IOCB2_Pos (18U) +#define GPIO_SCR_IOCB2_Msk (0x1U << GPIO_SCR_IOCB2_Pos) /*!< 0x00040000 */ +#define GPIO_SCR_IOCB2 GPIO_SCR_IOCB2_Msk /*!< GPIO x clear bit, pin 2 */ +#define GPIO_SCR_IOCB3_Pos (19U) +#define GPIO_SCR_IOCB3_Msk (0x1U << GPIO_SCR_IOCB3_Pos) /*!< 0x00080000 */ +#define GPIO_SCR_IOCB3 GPIO_SCR_IOCB3_Msk /*!< GPIO x clear bit, pin 3 */ +#define GPIO_SCR_IOCB4_Pos (20U) +#define GPIO_SCR_IOCB4_Msk (0x1U << GPIO_SCR_IOCB4_Pos) /*!< 0x00100000 */ +#define GPIO_SCR_IOCB4 GPIO_SCR_IOCB4_Msk /*!< GPIO x clear bit, pin 4 */ +#define GPIO_SCR_IOCB5_Pos (21U) +#define GPIO_SCR_IOCB5_Msk (0x1U << GPIO_SCR_IOCB5_Pos) /*!< 0x00200000 */ +#define GPIO_SCR_IOCB5 GPIO_SCR_IOCB5_Msk /*!< GPIO x clear bit, pin 5 */ +#define GPIO_SCR_IOCB6_Pos (22U) +#define GPIO_SCR_IOCB6_Msk (0x1U << GPIO_SCR_IOCB6_Pos) /*!< 0x00400000 */ +#define GPIO_SCR_IOCB6 GPIO_SCR_IOCB6_Msk /*!< GPIO x clear bit, pin 6 */ +#define GPIO_SCR_IOCB7_Pos (23U) +#define GPIO_SCR_IOCB7_Msk (0x1U << GPIO_SCR_IOCB7_Pos) /*!< 0x00800000 */ +#define GPIO_SCR_IOCB7 GPIO_SCR_IOCB7_Msk /*!< GPIO x clear bit, pin 7 */ +#define GPIO_SCR_IOCB8_Pos (24U) +#define GPIO_SCR_IOCB8_Msk (0x1U << GPIO_SCR_IOCB8_Pos) /*!< 0x01000000 */ +#define GPIO_SCR_IOCB8 GPIO_SCR_IOCB8_Msk /*!< GPIO x clear bit, pin 8 */ +#define GPIO_SCR_IOCB9_Pos (25U) +#define GPIO_SCR_IOCB9_Msk (0x1U << GPIO_SCR_IOCB9_Pos) /*!< 0x02000000 */ +#define GPIO_SCR_IOCB9 GPIO_SCR_IOCB9_Msk /*!< GPIO x clear bit, pin 9 */ +#define GPIO_SCR_IOCB10_Pos (26U) +#define GPIO_SCR_IOCB10_Msk (0x1U << GPIO_SCR_IOCB10_Pos) /*!< 0x04000000 */ +#define GPIO_SCR_IOCB10 GPIO_SCR_IOCB10_Msk /*!< GPIO x clear bit, pin 10 */ +#define GPIO_SCR_IOCB11_Pos (27U) +#define GPIO_SCR_IOCB11_Msk (0x1U << GPIO_SCR_IOCB11_Pos) /*!< 0x08000000 */ +#define GPIO_SCR_IOCB11 GPIO_SCR_IOCB11_Msk /*!< GPIO x clear bit, pin 11 */ +#define GPIO_SCR_IOCB12_Pos (28U) +#define GPIO_SCR_IOCB12_Msk (0x1U << GPIO_SCR_IOCB12_Pos) /*!< 0x10000000 */ +#define GPIO_SCR_IOCB12 GPIO_SCR_IOCB12_Msk /*!< GPIO x clear bit, pin 12 */ +#define GPIO_SCR_IOCB13_Pos (29U) +#define GPIO_SCR_IOCB13_Msk (0x1U << GPIO_SCR_IOCB13_Pos) /*!< 0x20000000 */ +#define GPIO_SCR_IOCB13 GPIO_SCR_IOCB13_Msk /*!< GPIO x clear bit, pin 13 */ +#define GPIO_SCR_IOCB14_Pos (30U) +#define GPIO_SCR_IOCB14_Msk (0x1U << GPIO_SCR_IOCB14_Pos) /*!< 0x40000000 */ +#define GPIO_SCR_IOCB14 GPIO_SCR_IOCB14_Msk /*!< GPIO x clear bit, pin 14 */ +#define GPIO_SCR_IOCB15_Pos (31U) +#define GPIO_SCR_IOCB15_Msk (0x1U << GPIO_SCR_IOCB15_Pos) /*!< 0x80000000 */ +#define GPIO_SCR_IOCB15 GPIO_SCR_IOCB15_Msk /*!< GPIO x clear bit, pin 15 */ + +/******************* Bit definition for GPIO_WPR register *******************/ +#define GPIO_WPR_WPEN0_Pos (0U) +#define GPIO_WPR_WPEN0_Msk (0x1U << GPIO_WPR_WPEN0_Pos) /*!< 0x00000001 */ +#define GPIO_WPR_WPEN0 GPIO_WPR_WPEN0_Msk /*!< Write protect enable, pin 0 */ +#define GPIO_WPR_WPEN1_Pos (1U) +#define GPIO_WPR_WPEN1_Msk (0x1U << GPIO_WPR_WPEN1_Pos) /*!< 0x00000002 */ +#define GPIO_WPR_WPEN1 GPIO_WPR_WPEN1_Msk /*!< Write protect enable, pin 1 */ +#define GPIO_WPR_WPEN2_Pos (2U) +#define GPIO_WPR_WPEN2_Msk (0x1U << GPIO_WPR_WPEN2_Pos) /*!< 0x00000004 */ +#define GPIO_WPR_WPEN2 GPIO_WPR_WPEN2_Msk /*!< Write protect enable, pin 2 */ +#define GPIO_WPR_WPEN3_Pos (3U) +#define GPIO_WPR_WPEN3_Msk (0x1U << GPIO_WPR_WPEN3_Pos) /*!< 0x00000008 */ +#define GPIO_WPR_WPEN3 GPIO_WPR_WPEN3_Msk /*!< Write protect enable, pin 3 */ +#define GPIO_WPR_WPEN4_Pos (4U) +#define GPIO_WPR_WPEN4_Msk (0x1U << GPIO_WPR_WPEN4_Pos) /*!< 0x00000010 */ +#define GPIO_WPR_WPEN4 GPIO_WPR_WPEN4_Msk /*!< Write protect enable, pin 4 */ +#define GPIO_WPR_WPEN5_Pos (5U) +#define GPIO_WPR_WPEN5_Msk (0x1U << GPIO_WPR_WPEN5_Pos) /*!< 0x00000020 */ +#define GPIO_WPR_WPEN5 GPIO_WPR_WPEN5_Msk /*!< Write protect enable, pin 5 */ +#define GPIO_WPR_WPEN6_Pos (6U) +#define GPIO_WPR_WPEN6_Msk (0x1U << GPIO_WPR_WPEN6_Pos) /*!< 0x00000040 */ +#define GPIO_WPR_WPEN6 GPIO_WPR_WPEN6_Msk /*!< Write protect enable, pin 6 */ +#define GPIO_WPR_WPEN7_Pos (7U) +#define GPIO_WPR_WPEN7_Msk (0x1U << GPIO_WPR_WPEN7_Pos) /*!< 0x00000080 */ +#define GPIO_WPR_WPEN7 GPIO_WPR_WPEN7_Msk /*!< Write protect enable, pin 7 */ +#define GPIO_WPR_WPEN8_Pos (8U) +#define GPIO_WPR_WPEN8_Msk (0x1U << GPIO_WPR_WPEN8_Pos) /*!< 0x00000100 */ +#define GPIO_WPR_WPEN8 GPIO_WPR_WPEN8_Msk /*!< Write protect enable, pin 8 */ +#define GPIO_WPR_WPEN9_Pos (9U) +#define GPIO_WPR_WPEN9_Msk (0x1U << GPIO_WPR_WPEN9_Pos) /*!< 0x00000200 */ +#define GPIO_WPR_WPEN9 GPIO_WPR_WPEN9_Msk /*!< Write protect enable, pin 9 */ +#define GPIO_WPR_WPEN10_Pos (10U) +#define GPIO_WPR_WPEN10_Msk (0x1U << GPIO_WPR_WPEN10_Pos) /*!< 0x00000400 */ +#define GPIO_WPR_WPEN10 GPIO_WPR_WPEN10_Msk /*!< Write protect enable, pin 10 */ +#define GPIO_WPR_WPEN11_Pos (11U) +#define GPIO_WPR_WPEN11_Msk (0x1U << GPIO_WPR_WPEN11_Pos) /*!< 0x00000800 */ +#define GPIO_WPR_WPEN11 GPIO_WPR_WPEN11_Msk /*!< Write protect enable, pin 11 */ +#define GPIO_WPR_WPEN12_Pos (12U) +#define GPIO_WPR_WPEN12_Msk (0x1U << GPIO_WPR_WPEN12_Pos) /*!< 0x00001000 */ +#define GPIO_WPR_WPEN12 GPIO_WPR_WPEN12_Msk /*!< Write protect enable, pin 12 */ +#define GPIO_WPR_WPEN13_Pos (13U) +#define GPIO_WPR_WPEN13_Msk (0x1U << GPIO_WPR_WPEN13_Pos) /*!< 0x00002000 */ +#define GPIO_WPR_WPEN13 GPIO_WPR_WPEN13_Msk /*!< Write protect enable, pin 13 */ +#define GPIO_WPR_WPEN14_Pos (14U) +#define GPIO_WPR_WPEN14_Msk (0x1U << GPIO_WPR_WPEN14_Pos) /*!< 0x00004000 */ +#define GPIO_WPR_WPEN14 GPIO_WPR_WPEN14_Msk /*!< Write protect enable, pin 14 */ +#define GPIO_WPR_WPEN15_Pos (15U) +#define GPIO_WPR_WPEN15_Msk (0x1U << GPIO_WPR_WPEN15_Pos) /*!< 0x00008000 */ +#define GPIO_WPR_WPEN15 GPIO_WPR_WPEN15_Msk /*!< Write protect enable, pin 15 */ +#define GPIO_WPR_WPSEQ_Pos (16U) +#define GPIO_WPR_WPSEQ_Msk (0x1U << GPIO_WPR_WPSEQ_Pos) /*!< 0x00010000 */ +#define GPIO_WPR_WPSEQ GPIO_WPR_WPSEQ_Msk /*!< Write protect sequence */ + +/****************** Bit definition for GPIO_MUXL register *******************/ +#define GPIO_MUXL_MUXL_Pos (0U) +#define GPIO_MUXL_MUXL_Msk (0xFFFFFFFFU << GPIO_MUXL_MUXL_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_MUXL_MUXL GPIO_MUXL_MUXL_Msk /*!< Multiplexed function select for GPIO x */ + +/*!< MUXL0 configuration */ +#define GPIO_MUXL_MUXL0_Pos (0U) +#define GPIO_MUXL_MUXL0_Msk (0xFU << GPIO_MUXL_MUXL0_Pos) /*!< 0x0000000F */ +#define GPIO_MUXL_MUXL0 GPIO_MUXL_MUXL0_Msk /*!< MUXL0[3:0] bits (Multiplexed function select for GPIO x, pin 0) */ +#define GPIO_MUXL_MUXL0_0 (0x1U << GPIO_MUXL_MUXL0_Pos) /*!< 0x00000001 */ +#define GPIO_MUXL_MUXL0_1 (0x2U << GPIO_MUXL_MUXL0_Pos) /*!< 0x00000002 */ +#define GPIO_MUXL_MUXL0_2 (0x4U << GPIO_MUXL_MUXL0_Pos) /*!< 0x00000004 */ +#define GPIO_MUXL_MUXL0_3 (0x8U << GPIO_MUXL_MUXL0_Pos) /*!< 0x00000008 */ + +/*!< MUXL1 configuration */ +#define GPIO_MUXL_MUXL1_Pos (4U) +#define GPIO_MUXL_MUXL1_Msk (0xFU << GPIO_MUXL_MUXL1_Pos) /*!< 0x000000F0 */ +#define GPIO_MUXL_MUXL1 GPIO_MUXL_MUXL1_Msk /*!< MUXL1[3:0] bits (Multiplexed function select for GPIO x, pin 1) */ +#define GPIO_MUXL_MUXL1_0 (0x1U << GPIO_MUXL_MUXL1_Pos) /*!< 0x00000010 */ +#define GPIO_MUXL_MUXL1_1 (0x2U << GPIO_MUXL_MUXL1_Pos) /*!< 0x00000020 */ +#define GPIO_MUXL_MUXL1_2 (0x4U << GPIO_MUXL_MUXL1_Pos) /*!< 0x00000040 */ +#define GPIO_MUXL_MUXL1_3 (0x8U << GPIO_MUXL_MUXL1_Pos) /*!< 0x00000080 */ + +/*!< MUXL2 configuration */ +#define GPIO_MUXL_MUXL2_Pos (8U) +#define GPIO_MUXL_MUXL2_Msk (0xFU << GPIO_MUXL_MUXL2_Pos) /*!< 0x00000F00 */ +#define GPIO_MUXL_MUXL2 GPIO_MUXL_MUXL2_Msk /*!< MUXL2[3:0] bits (Multiplexed function select for GPIO x, pin 2) */ +#define GPIO_MUXL_MUXL2_0 (0x1U << GPIO_MUXL_MUXL2_Pos) /*!< 0x00000100 */ +#define GPIO_MUXL_MUXL2_1 (0x2U << GPIO_MUXL_MUXL2_Pos) /*!< 0x00000200 */ +#define GPIO_MUXL_MUXL2_2 (0x4U << GPIO_MUXL_MUXL2_Pos) /*!< 0x00000400 */ +#define GPIO_MUXL_MUXL2_3 (0x8U << GPIO_MUXL_MUXL2_Pos) /*!< 0x00000800 */ + +/*!< MUXL3 configuration */ +#define GPIO_MUXL_MUXL3_Pos (12U) +#define GPIO_MUXL_MUXL3_Msk (0xFU << GPIO_MUXL_MUXL3_Pos) /*!< 0x0000F000 */ +#define GPIO_MUXL_MUXL3 GPIO_MUXL_MUXL3_Msk /*!< MUXL3[3:0] bits (Multiplexed function select for GPIO x, pin 3) */ +#define GPIO_MUXL_MUXL3_0 (0x1U << GPIO_MUXL_MUXL3_Pos) /*!< 0x00001000 */ +#define GPIO_MUXL_MUXL3_1 (0x2U << GPIO_MUXL_MUXL3_Pos) /*!< 0x00002000 */ +#define GPIO_MUXL_MUXL3_2 (0x4U << GPIO_MUXL_MUXL3_Pos) /*!< 0x00004000 */ +#define GPIO_MUXL_MUXL3_3 (0x8U << GPIO_MUXL_MUXL3_Pos) /*!< 0x00008000 */ + +/*!< MUXL4 configuration */ +#define GPIO_MUXL_MUXL4_Pos (16U) +#define GPIO_MUXL_MUXL4_Msk (0xFU << GPIO_MUXL_MUXL4_Pos) /*!< 0x000F0000 */ +#define GPIO_MUXL_MUXL4 GPIO_MUXL_MUXL4_Msk /*!< MUXL4[3:0] bits (Multiplexed function select for GPIO x, pin 4) */ +#define GPIO_MUXL_MUXL4_0 (0x1U << GPIO_MUXL_MUXL4_Pos) /*!< 0x00010000 */ +#define GPIO_MUXL_MUXL4_1 (0x2U << GPIO_MUXL_MUXL4_Pos) /*!< 0x00020000 */ +#define GPIO_MUXL_MUXL4_2 (0x4U << GPIO_MUXL_MUXL4_Pos) /*!< 0x00040000 */ +#define GPIO_MUXL_MUXL4_3 (0x8U << GPIO_MUXL_MUXL4_Pos) /*!< 0x00080000 */ + +/*!< MUXL5 configuration */ +#define GPIO_MUXL_MUXL5_Pos (20U) +#define GPIO_MUXL_MUXL5_Msk (0xFU << GPIO_MUXL_MUXL5_Pos) /*!< 0x00F00000 */ +#define GPIO_MUXL_MUXL5 GPIO_MUXL_MUXL5_Msk /*!< MUXL5[3:0] bits (Multiplexed function select for GPIO x, pin 5) */ +#define GPIO_MUXL_MUXL5_0 (0x1U << GPIO_MUXL_MUXL5_Pos) /*!< 0x00100000 */ +#define GPIO_MUXL_MUXL5_1 (0x2U << GPIO_MUXL_MUXL5_Pos) /*!< 0x00200000 */ +#define GPIO_MUXL_MUXL5_2 (0x4U << GPIO_MUXL_MUXL5_Pos) /*!< 0x00400000 */ +#define GPIO_MUXL_MUXL5_3 (0x8U << GPIO_MUXL_MUXL5_Pos) /*!< 0x00800000 */ + +/*!< MUXL6 configuration */ +#define GPIO_MUXL_MUXL6_Pos (24U) +#define GPIO_MUXL_MUXL6_Msk (0xFU << GPIO_MUXL_MUXL6_Pos) /*!< 0x0F000000 */ +#define GPIO_MUXL_MUXL6 GPIO_MUXL_MUXL6_Msk /*!< MUXL6[3:0] bits (Multiplexed function select for GPIO x, pin 6) */ +#define GPIO_MUXL_MUXL6_0 (0x1U << GPIO_MUXL_MUXL6_Pos) /*!< 0x01000000 */ +#define GPIO_MUXL_MUXL6_1 (0x2U << GPIO_MUXL_MUXL6_Pos) /*!< 0x02000000 */ +#define GPIO_MUXL_MUXL6_2 (0x4U << GPIO_MUXL_MUXL6_Pos) /*!< 0x04000000 */ +#define GPIO_MUXL_MUXL6_3 (0x8U << GPIO_MUXL_MUXL6_Pos) /*!< 0x08000000 */ + +/*!< MUXL7 configuration */ +#define GPIO_MUXL_MUXL7_Pos (28U) +#define GPIO_MUXL_MUXL7_Msk (0xFU << GPIO_MUXL_MUXL7_Pos) /*!< 0xF0000000 */ +#define GPIO_MUXL_MUXL7 GPIO_MUXL_MUXL7_Msk /*!< MUXL7[3:0] bits (Multiplexed function select for GPIO x, pin 7) */ +#define GPIO_MUXL_MUXL7_0 (0x1U << GPIO_MUXL_MUXL7_Pos) /*!< 0x10000000 */ +#define GPIO_MUXL_MUXL7_1 (0x2U << GPIO_MUXL_MUXL7_Pos) /*!< 0x20000000 */ +#define GPIO_MUXL_MUXL7_2 (0x4U << GPIO_MUXL_MUXL7_Pos) /*!< 0x40000000 */ +#define GPIO_MUXL_MUXL7_3 (0x8U << GPIO_MUXL_MUXL7_Pos) /*!< 0x80000000 */ + +/****************** Bit definition for GPIO_MUXH register *******************/ +#define GPIO_MUXH_MUXH_Pos (0U) +#define GPIO_MUXH_MUXH_Msk (0xFFFFFFFFU << GPIO_MUXH_MUXH_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_MUXH_MUXH GPIO_MUXH_MUXH_Msk /*!< Multiplexed function select for GPIO x */ + +/*!< MUXH8 configuration */ +#define GPIO_MUXH_MUXH8_Pos (0U) +#define GPIO_MUXH_MUXH8_Msk (0xFU << GPIO_MUXH_MUXH8_Pos) /*!< 0x0000000F */ +#define GPIO_MUXH_MUXH8 GPIO_MUXH_MUXH8_Msk /*!< MUXH8[3:0] bits (Multiplexed function select for GPIO x, pin 8) */ +#define GPIO_MUXH_MUXH8_0 (0x1U << GPIO_MUXH_MUXH8_Pos) /*!< 0x00000001 */ +#define GPIO_MUXH_MUXH8_1 (0x2U << GPIO_MUXH_MUXH8_Pos) /*!< 0x00000002 */ +#define GPIO_MUXH_MUXH8_2 (0x4U << GPIO_MUXH_MUXH8_Pos) /*!< 0x00000004 */ +#define GPIO_MUXH_MUXH8_3 (0x8U << GPIO_MUXH_MUXH8_Pos) /*!< 0x00000008 */ + +/*!< MUXH9 configuration */ +#define GPIO_MUXH_MUXH9_Pos (4U) +#define GPIO_MUXH_MUXH9_Msk (0xFU << GPIO_MUXH_MUXH9_Pos) /*!< 0x000000F0 */ +#define GPIO_MUXH_MUXH9 GPIO_MUXH_MUXH9_Msk /*!< MUXH9[3:0] bits (Multiplexed function select for GPIO x, pin 9) */ +#define GPIO_MUXH_MUXH9_0 (0x1U << GPIO_MUXH_MUXH9_Pos) /*!< 0x00000010 */ +#define GPIO_MUXH_MUXH9_1 (0x2U << GPIO_MUXH_MUXH9_Pos) /*!< 0x00000020 */ +#define GPIO_MUXH_MUXH9_2 (0x4U << GPIO_MUXH_MUXH9_Pos) /*!< 0x00000040 */ +#define GPIO_MUXH_MUXH9_3 (0x8U << GPIO_MUXH_MUXH9_Pos) /*!< 0x00000080 */ + +/*!< MUXH10 configuration */ +#define GPIO_MUXH_MUXH10_Pos (8U) +#define GPIO_MUXH_MUXH10_Msk (0xFU << GPIO_MUXH_MUXH10_Pos) /*!< 0x00000F00 */ +#define GPIO_MUXH_MUXH10 GPIO_MUXH_MUXH10_Msk /*!< MUXH10[3:0] bits (Multiplexed function select for GPIO x, pin 10) */ +#define GPIO_MUXH_MUXH10_0 (0x1U << GPIO_MUXH_MUXH10_Pos) /*!< 0x00000100 */ +#define GPIO_MUXH_MUXH10_1 (0x2U << GPIO_MUXH_MUXH10_Pos) /*!< 0x00000200 */ +#define GPIO_MUXH_MUXH10_2 (0x4U << GPIO_MUXH_MUXH10_Pos) /*!< 0x00000400 */ +#define GPIO_MUXH_MUXH10_3 (0x8U << GPIO_MUXH_MUXH10_Pos) /*!< 0x00000800 */ + +/*!< MUXH11 configuration */ +#define GPIO_MUXH_MUXH11_Pos (12U) +#define GPIO_MUXH_MUXH11_Msk (0xFU << GPIO_MUXH_MUXH11_Pos) /*!< 0x0000F000 */ +#define GPIO_MUXH_MUXH11 GPIO_MUXH_MUXH11_Msk /*!< MUXH11[3:0] bits (Multiplexed function select for GPIO x, pin 11) */ +#define GPIO_MUXH_MUXH11_0 (0x1U << GPIO_MUXH_MUXH11_Pos) /*!< 0x00001000 */ +#define GPIO_MUXH_MUXH11_1 (0x2U << GPIO_MUXH_MUXH11_Pos) /*!< 0x00002000 */ +#define GPIO_MUXH_MUXH11_2 (0x4U << GPIO_MUXH_MUXH11_Pos) /*!< 0x00004000 */ +#define GPIO_MUXH_MUXH11_3 (0x8U << GPIO_MUXH_MUXH11_Pos) /*!< 0x00008000 */ + +/*!< MUXH12 configuration */ +#define GPIO_MUXH_MUXH12_Pos (16U) +#define GPIO_MUXH_MUXH12_Msk (0xFU << GPIO_MUXH_MUXH12_Pos) /*!< 0x000F0000 */ +#define GPIO_MUXH_MUXH12 GPIO_MUXH_MUXH12_Msk /*!< MUXH12[3:0] bits (Multiplexed function select for GPIO x, pin 12) */ +#define GPIO_MUXH_MUXH12_0 (0x1U << GPIO_MUXH_MUXH12_Pos) /*!< 0x00010000 */ +#define GPIO_MUXH_MUXH12_1 (0x2U << GPIO_MUXH_MUXH12_Pos) /*!< 0x00020000 */ +#define GPIO_MUXH_MUXH12_2 (0x4U << GPIO_MUXH_MUXH12_Pos) /*!< 0x00040000 */ +#define GPIO_MUXH_MUXH12_3 (0x8U << GPIO_MUXH_MUXH12_Pos) /*!< 0x00080000 */ + +/*!< MUXH13 configuration */ +#define GPIO_MUXH_MUXH13_Pos (20U) +#define GPIO_MUXH_MUXH13_Msk (0xFU << GPIO_MUXH_MUXH13_Pos) /*!< 0x00F00000 */ +#define GPIO_MUXH_MUXH13 GPIO_MUXH_MUXH13_Msk /*!< MUXH13[3:0] bits (Multiplexed function select for GPIO x, pin 13) */ +#define GPIO_MUXH_MUXH13_0 (0x1U << GPIO_MUXH_MUXH13_Pos) /*!< 0x00100000 */ +#define GPIO_MUXH_MUXH13_1 (0x2U << GPIO_MUXH_MUXH13_Pos) /*!< 0x00200000 */ +#define GPIO_MUXH_MUXH13_2 (0x4U << GPIO_MUXH_MUXH13_Pos) /*!< 0x00400000 */ +#define GPIO_MUXH_MUXH13_3 (0x8U << GPIO_MUXH_MUXH13_Pos) /*!< 0x00800000 */ + +/*!< MUXH14 configuration */ +#define GPIO_MUXH_MUXH14_Pos (24U) +#define GPIO_MUXH_MUXH14_Msk (0xFU << GPIO_MUXH_MUXH14_Pos) /*!< 0x0F000000 */ +#define GPIO_MUXH_MUXH14 GPIO_MUXH_MUXH14_Msk /*!< MUXH14[3:0] bits (Multiplexed function select for GPIO x, pin 14) */ +#define GPIO_MUXH_MUXH14_0 (0x1U << GPIO_MUXH_MUXH14_Pos) /*!< 0x01000000 */ +#define GPIO_MUXH_MUXH14_1 (0x2U << GPIO_MUXH_MUXH14_Pos) /*!< 0x02000000 */ +#define GPIO_MUXH_MUXH14_2 (0x4U << GPIO_MUXH_MUXH14_Pos) /*!< 0x04000000 */ +#define GPIO_MUXH_MUXH14_3 (0x8U << GPIO_MUXH_MUXH14_Pos) /*!< 0x08000000 */ + +/*!< MUXH15 configuration */ +#define GPIO_MUXH_MUXH15_Pos (28U) +#define GPIO_MUXH_MUXH15_Msk (0xFU << GPIO_MUXH_MUXH15_Pos) /*!< 0xF0000000 */ +#define GPIO_MUXH_MUXH15 GPIO_MUXH_MUXH15_Msk /*!< MUXH15[3:0] bits (Multiplexed function select for GPIO x, pin 15) */ +#define GPIO_MUXH_MUXH15_0 (0x1U << GPIO_MUXH_MUXH15_Pos) /*!< 0x10000000 */ +#define GPIO_MUXH_MUXH15_1 (0x2U << GPIO_MUXH_MUXH15_Pos) /*!< 0x20000000 */ +#define GPIO_MUXH_MUXH15_2 (0x4U << GPIO_MUXH_MUXH15_Pos) /*!< 0x40000000 */ +#define GPIO_MUXH_MUXH15_3 (0x8U << GPIO_MUXH_MUXH15_Pos) /*!< 0x80000000 */ + +/******************* Bit definition for GPIO_CLR register *******************/ +#define GPIO_CLR_IOCB0_Pos (0U) +#define GPIO_CLR_IOCB0_Msk (0x1U << GPIO_CLR_IOCB0_Pos) /*!< 0x00000001 */ +#define GPIO_CLR_IOCB0 GPIO_CLR_IOCB0_Msk /*!< GPIO x clear bit, pin 0 */ +#define GPIO_CLR_IOCB1_Pos (1U) +#define GPIO_CLR_IOCB1_Msk (0x1U << GPIO_CLR_IOCB1_Pos) /*!< 0x00000002 */ +#define GPIO_CLR_IOCB1 GPIO_CLR_IOCB1_Msk /*!< GPIO x clear bit, pin 1 */ +#define GPIO_CLR_IOCB2_Pos (2U) +#define GPIO_CLR_IOCB2_Msk (0x1U << GPIO_CLR_IOCB2_Pos) /*!< 0x00000004 */ +#define GPIO_CLR_IOCB2 GPIO_CLR_IOCB2_Msk /*!< GPIO x clear bit, pin 2 */ +#define GPIO_CLR_IOCB3_Pos (3U) +#define GPIO_CLR_IOCB3_Msk (0x1U << GPIO_CLR_IOCB3_Pos) /*!< 0x00000008 */ +#define GPIO_CLR_IOCB3 GPIO_CLR_IOCB3_Msk /*!< GPIO x clear bit, pin 3 */ +#define GPIO_CLR_IOCB4_Pos (4U) +#define GPIO_CLR_IOCB4_Msk (0x1U << GPIO_CLR_IOCB4_Pos) /*!< 0x00000010 */ +#define GPIO_CLR_IOCB4 GPIO_CLR_IOCB4_Msk /*!< GPIO x clear bit, pin 4 */ +#define GPIO_CLR_IOCB5_Pos (5U) +#define GPIO_CLR_IOCB5_Msk (0x1U << GPIO_CLR_IOCB5_Pos) /*!< 0x00000020 */ +#define GPIO_CLR_IOCB5 GPIO_CLR_IOCB5_Msk /*!< GPIO x clear bit, pin 5 */ +#define GPIO_CLR_IOCB6_Pos (6U) +#define GPIO_CLR_IOCB6_Msk (0x1U << GPIO_CLR_IOCB6_Pos) /*!< 0x00000040 */ +#define GPIO_CLR_IOCB6 GPIO_CLR_IOCB6_Msk /*!< GPIO x clear bit, pin 6 */ +#define GPIO_CLR_IOCB7_Pos (7U) +#define GPIO_CLR_IOCB7_Msk (0x1U << GPIO_CLR_IOCB7_Pos) /*!< 0x00000080 */ +#define GPIO_CLR_IOCB7 GPIO_CLR_IOCB7_Msk /*!< GPIO x clear bit, pin 7 */ +#define GPIO_CLR_IOCB8_Pos (8U) +#define GPIO_CLR_IOCB8_Msk (0x1U << GPIO_CLR_IOCB8_Pos) /*!< 0x00000100 */ +#define GPIO_CLR_IOCB8 GPIO_CLR_IOCB8_Msk /*!< GPIO x clear bit, pin 8 */ +#define GPIO_CLR_IOCB9_Pos (9U) +#define GPIO_CLR_IOCB9_Msk (0x1U << GPIO_CLR_IOCB9_Pos) /*!< 0x00000200 */ +#define GPIO_CLR_IOCB9 GPIO_CLR_IOCB9_Msk /*!< GPIO x clear bit, pin 9 */ +#define GPIO_CLR_IOCB10_Pos (10U) +#define GPIO_CLR_IOCB10_Msk (0x1U << GPIO_CLR_IOCB10_Pos) /*!< 0x00000400 */ +#define GPIO_CLR_IOCB10 GPIO_CLR_IOCB10_Msk /*!< GPIO x clear bit, pin 10 */ +#define GPIO_CLR_IOCB11_Pos (11U) +#define GPIO_CLR_IOCB11_Msk (0x1U << GPIO_CLR_IOCB11_Pos) /*!< 0x00000800 */ +#define GPIO_CLR_IOCB11 GPIO_CLR_IOCB11_Msk /*!< GPIO x clear bit, pin 11 */ +#define GPIO_CLR_IOCB12_Pos (12U) +#define GPIO_CLR_IOCB12_Msk (0x1U << GPIO_CLR_IOCB12_Pos) /*!< 0x00001000 */ +#define GPIO_CLR_IOCB12 GPIO_CLR_IOCB12_Msk /*!< GPIO x clear bit, pin 12 */ +#define GPIO_CLR_IOCB13_Pos (13U) +#define GPIO_CLR_IOCB13_Msk (0x1U << GPIO_CLR_IOCB13_Pos) /*!< 0x00002000 */ +#define GPIO_CLR_IOCB13 GPIO_CLR_IOCB13_Msk /*!< GPIO x clear bit, pin 13 */ +#define GPIO_CLR_IOCB14_Pos (14U) +#define GPIO_CLR_IOCB14_Msk (0x1U << GPIO_CLR_IOCB14_Pos) /*!< 0x00004000 */ +#define GPIO_CLR_IOCB14 GPIO_CLR_IOCB14_Msk /*!< GPIO x clear bit, pin 14 */ +#define GPIO_CLR_IOCB15_Pos (15U) +#define GPIO_CLR_IOCB15_Msk (0x1U << GPIO_CLR_IOCB15_Pos) /*!< 0x00008000 */ +#define GPIO_CLR_IOCB15 GPIO_CLR_IOCB15_Msk /*!< GPIO x clear bit, pin 15 */ + +/****************** Bit definition for GPIO_TOGR register *******************/ +#define GPIO_TOGR_IOTB0_Pos (0U) +#define GPIO_TOGR_IOTB0_Msk (0x1U << GPIO_TOGR_IOTB0_Pos) /*!< 0x00000001 */ +#define GPIO_TOGR_IOTB0 GPIO_TOGR_IOTB0_Msk /*!< GPIO x toggle bit, pin 0 */ +#define GPIO_TOGR_IOTB1_Pos (1U) +#define GPIO_TOGR_IOTB1_Msk (0x1U << GPIO_TOGR_IOTB1_Pos) /*!< 0x00000002 */ +#define GPIO_TOGR_IOTB1 GPIO_TOGR_IOTB1_Msk /*!< GPIO x toggle bit, pin 1 */ +#define GPIO_TOGR_IOTB2_Pos (2U) +#define GPIO_TOGR_IOTB2_Msk (0x1U << GPIO_TOGR_IOTB2_Pos) /*!< 0x00000004 */ +#define GPIO_TOGR_IOTB2 GPIO_TOGR_IOTB2_Msk /*!< GPIO x toggle bit, pin 2 */ +#define GPIO_TOGR_IOTB3_Pos (3U) +#define GPIO_TOGR_IOTB3_Msk (0x1U << GPIO_TOGR_IOTB3_Pos) /*!< 0x00000008 */ +#define GPIO_TOGR_IOTB3 GPIO_TOGR_IOTB3_Msk /*!< GPIO x toggle bit, pin 3 */ +#define GPIO_TOGR_IOTB4_Pos (4U) +#define GPIO_TOGR_IOTB4_Msk (0x1U << GPIO_TOGR_IOTB4_Pos) /*!< 0x00000010 */ +#define GPIO_TOGR_IOTB4 GPIO_TOGR_IOTB4_Msk /*!< GPIO x toggle bit, pin 4 */ +#define GPIO_TOGR_IOTB5_Pos (5U) +#define GPIO_TOGR_IOTB5_Msk (0x1U << GPIO_TOGR_IOTB5_Pos) /*!< 0x00000020 */ +#define GPIO_TOGR_IOTB5 GPIO_TOGR_IOTB5_Msk /*!< GPIO x toggle bit, pin 5 */ +#define GPIO_TOGR_IOTB6_Pos (6U) +#define GPIO_TOGR_IOTB6_Msk (0x1U << GPIO_TOGR_IOTB6_Pos) /*!< 0x00000040 */ +#define GPIO_TOGR_IOTB6 GPIO_TOGR_IOTB6_Msk /*!< GPIO x toggle bit, pin 6 */ +#define GPIO_TOGR_IOTB7_Pos (7U) +#define GPIO_TOGR_IOTB7_Msk (0x1U << GPIO_TOGR_IOTB7_Pos) /*!< 0x00000080 */ +#define GPIO_TOGR_IOTB7 GPIO_TOGR_IOTB7_Msk /*!< GPIO x toggle bit, pin 7 */ +#define GPIO_TOGR_IOTB8_Pos (8U) +#define GPIO_TOGR_IOTB8_Msk (0x1U << GPIO_TOGR_IOTB8_Pos) /*!< 0x00000100 */ +#define GPIO_TOGR_IOTB8 GPIO_TOGR_IOTB8_Msk /*!< GPIO x toggle bit, pin 8 */ +#define GPIO_TOGR_IOTB9_Pos (9U) +#define GPIO_TOGR_IOTB9_Msk (0x1U << GPIO_TOGR_IOTB9_Pos) /*!< 0x00000200 */ +#define GPIO_TOGR_IOTB9 GPIO_TOGR_IOTB9_Msk /*!< GPIO x toggle bit, pin 9 */ +#define GPIO_TOGR_IOTB10_Pos (10U) +#define GPIO_TOGR_IOTB10_Msk (0x1U << GPIO_TOGR_IOTB10_Pos) /*!< 0x00000400 */ +#define GPIO_TOGR_IOTB10 GPIO_TOGR_IOTB10_Msk /*!< GPIO x toggle bit, pin 10 */ +#define GPIO_TOGR_IOTB11_Pos (11U) +#define GPIO_TOGR_IOTB11_Msk (0x1U << GPIO_TOGR_IOTB11_Pos) /*!< 0x00000800 */ +#define GPIO_TOGR_IOTB11 GPIO_TOGR_IOTB11_Msk /*!< GPIO x toggle bit, pin 11 */ +#define GPIO_TOGR_IOTB12_Pos (12U) +#define GPIO_TOGR_IOTB12_Msk (0x1U << GPIO_TOGR_IOTB12_Pos) /*!< 0x00001000 */ +#define GPIO_TOGR_IOTB12 GPIO_TOGR_IOTB12_Msk /*!< GPIO x toggle bit, pin 12 */ +#define GPIO_TOGR_IOTB13_Pos (13U) +#define GPIO_TOGR_IOTB13_Msk (0x1U << GPIO_TOGR_IOTB13_Pos) /*!< 0x00002000 */ +#define GPIO_TOGR_IOTB13 GPIO_TOGR_IOTB13_Msk /*!< GPIO x toggle bit, pin 13 */ +#define GPIO_TOGR_IOTB14_Pos (14U) +#define GPIO_TOGR_IOTB14_Msk (0x1U << GPIO_TOGR_IOTB14_Pos) /*!< 0x00004000 */ +#define GPIO_TOGR_IOTB14 GPIO_TOGR_IOTB14_Msk /*!< GPIO x toggle bit, pin 14 */ +#define GPIO_TOGR_IOTB15_Pos (15U) +#define GPIO_TOGR_IOTB15_Msk (0x1U << GPIO_TOGR_IOTB15_Pos) /*!< 0x00008000 */ +#define GPIO_TOGR_IOTB15 GPIO_TOGR_IOTB15_Msk /*!< GPIO x toggle bit, pin 15 */ + +/****************** Bit definition for GPIO_HDRV register *******************/ +#define GPIO_HDRV_HDRV0_Pos (0U) +#define GPIO_HDRV_HDRV0_Msk (0x1U << GPIO_HDRV_HDRV0_Pos) /*!< 0x00000001 */ +#define GPIO_HDRV_HDRV0 GPIO_HDRV_HDRV0_Msk /*!< GPIO x huge sourcing/sinking strength control, pin 0 */ +#define GPIO_HDRV_HDRV1_Pos (1U) +#define GPIO_HDRV_HDRV1_Msk (0x1U << GPIO_HDRV_HDRV1_Pos) /*!< 0x00000002 */ +#define GPIO_HDRV_HDRV1 GPIO_HDRV_HDRV1_Msk /*!< GPIO x huge sourcing/sinking strength control, pin 1 */ +#define GPIO_HDRV_HDRV2_Pos (2U) +#define GPIO_HDRV_HDRV2_Msk (0x1U << GPIO_HDRV_HDRV2_Pos) /*!< 0x00000004 */ +#define GPIO_HDRV_HDRV2 GPIO_HDRV_HDRV2_Msk /*!< GPIO x huge sourcing/sinking strength control, pin 2 */ +#define GPIO_HDRV_HDRV3_Pos (3U) +#define GPIO_HDRV_HDRV3_Msk (0x1U << GPIO_HDRV_HDRV3_Pos) /*!< 0x00000008 */ +#define GPIO_HDRV_HDRV3 GPIO_HDRV_HDRV3_Msk /*!< GPIO x huge sourcing/sinking strength control, pin 3 */ +#define GPIO_HDRV_HDRV4_Pos (4U) +#define GPIO_HDRV_HDRV4_Msk (0x1U << GPIO_HDRV_HDRV4_Pos) /*!< 0x00000010 */ +#define GPIO_HDRV_HDRV4 GPIO_HDRV_HDRV4_Msk /*!< GPIO x huge sourcing/sinking strength control, pin 4 */ +#define GPIO_HDRV_HDRV5_Pos (5U) +#define GPIO_HDRV_HDRV5_Msk (0x1U << GPIO_HDRV_HDRV5_Pos) /*!< 0x00000020 */ +#define GPIO_HDRV_HDRV5 GPIO_HDRV_HDRV5_Msk /*!< GPIO x huge sourcing/sinking strength control, pin 5 */ +#define GPIO_HDRV_HDRV6_Pos (6U) +#define GPIO_HDRV_HDRV6_Msk (0x1U << GPIO_HDRV_HDRV6_Pos) /*!< 0x00000040 */ +#define GPIO_HDRV_HDRV6 GPIO_HDRV_HDRV6_Msk /*!< GPIO x huge sourcing/sinking strength control, pin 6 */ +#define GPIO_HDRV_HDRV7_Pos (7U) +#define GPIO_HDRV_HDRV7_Msk (0x1U << GPIO_HDRV_HDRV7_Pos) /*!< 0x00000080 */ +#define GPIO_HDRV_HDRV7 GPIO_HDRV_HDRV7_Msk /*!< GPIO x huge sourcing/sinking strength control, pin 7 */ +#define GPIO_HDRV_HDRV8_Pos (8U) +#define GPIO_HDRV_HDRV8_Msk (0x1U << GPIO_HDRV_HDRV8_Pos) /*!< 0x00000100 */ +#define GPIO_HDRV_HDRV8 GPIO_HDRV_HDRV8_Msk /*!< GPIO x huge sourcing/sinking strength control, pin 8 */ +#define GPIO_HDRV_HDRV9_Pos (9U) +#define GPIO_HDRV_HDRV9_Msk (0x1U << GPIO_HDRV_HDRV9_Pos) /*!< 0x00000200 */ +#define GPIO_HDRV_HDRV9 GPIO_HDRV_HDRV9_Msk /*!< GPIO x huge sourcing/sinking strength control, pin 9 */ +#define GPIO_HDRV_HDRV10_Pos (10U) +#define GPIO_HDRV_HDRV10_Msk (0x1U << GPIO_HDRV_HDRV10_Pos) /*!< 0x00000400 */ +#define GPIO_HDRV_HDRV10 GPIO_HDRV_HDRV10_Msk /*!< GPIO x huge sourcing/sinking strength control, pin 10 */ +#define GPIO_HDRV_HDRV11_Pos (11U) +#define GPIO_HDRV_HDRV11_Msk (0x1U << GPIO_HDRV_HDRV11_Pos) /*!< 0x00000800 */ +#define GPIO_HDRV_HDRV11 GPIO_HDRV_HDRV11_Msk /*!< GPIO x huge sourcing/sinking strength control, pin 11 */ +#define GPIO_HDRV_HDRV12_Pos (12U) +#define GPIO_HDRV_HDRV12_Msk (0x1U << GPIO_HDRV_HDRV12_Pos) /*!< 0x00001000 */ +#define GPIO_HDRV_HDRV12 GPIO_HDRV_HDRV12_Msk /*!< GPIO x huge sourcing/sinking strength control, pin 12 */ +#define GPIO_HDRV_HDRV13_Pos (13U) +#define GPIO_HDRV_HDRV13_Msk (0x1U << GPIO_HDRV_HDRV13_Pos) /*!< 0x00002000 */ +#define GPIO_HDRV_HDRV13 GPIO_HDRV_HDRV13_Msk /*!< GPIO x huge sourcing/sinking strength control, pin 13 */ +#define GPIO_HDRV_HDRV14_Pos (14U) +#define GPIO_HDRV_HDRV14_Msk (0x1U << GPIO_HDRV_HDRV14_Pos) /*!< 0x00004000 */ +#define GPIO_HDRV_HDRV14 GPIO_HDRV_HDRV14_Msk /*!< GPIO x huge sourcing/sinking strength control, pin 14 */ +#define GPIO_HDRV_HDRV15_Pos (15U) +#define GPIO_HDRV_HDRV15_Msk (0x1U << GPIO_HDRV_HDRV15_Pos) /*!< 0x00008000 */ +#define GPIO_HDRV_HDRV15 GPIO_HDRV_HDRV15_Msk /*!< GPIO x huge sourcing/sinking strength control, pin 15 */ + +/****************** Bit definition for GPIO_SRCTR register ******************/ +#define GPIO_SRCTR_SRCTR0_Pos (0U) +#define GPIO_SRCTR_SRCTR0_Msk (0x1U << GPIO_SRCTR_SRCTR0_Pos) /*!< 0x00000001 */ +#define GPIO_SRCTR_SRCTR0 GPIO_SRCTR_SRCTR0_Msk /*!< GPIO x SRCTR, pin 0 */ +#define GPIO_SRCTR_SRCTR1_Pos (1U) +#define GPIO_SRCTR_SRCTR1_Msk (0x1U << GPIO_SRCTR_SRCTR1_Pos) /*!< 0x00000002 */ +#define GPIO_SRCTR_SRCTR1 GPIO_SRCTR_SRCTR1_Msk /*!< GPIO x SRCTR, pin 1 */ +#define GPIO_SRCTR_SRCTR2_Pos (2U) +#define GPIO_SRCTR_SRCTR2_Msk (0x1U << GPIO_SRCTR_SRCTR2_Pos) /*!< 0x00000004 */ +#define GPIO_SRCTR_SRCTR2 GPIO_SRCTR_SRCTR2_Msk /*!< GPIO x SRCTR, pin 2 */ +#define GPIO_SRCTR_SRCTR3_Pos (3U) +#define GPIO_SRCTR_SRCTR3_Msk (0x1U << GPIO_SRCTR_SRCTR3_Pos) /*!< 0x00000008 */ +#define GPIO_SRCTR_SRCTR3 GPIO_SRCTR_SRCTR3_Msk /*!< GPIO x SRCTR, pin 3 */ +#define GPIO_SRCTR_SRCTR4_Pos (4U) +#define GPIO_SRCTR_SRCTR4_Msk (0x1U << GPIO_SRCTR_SRCTR4_Pos) /*!< 0x00000010 */ +#define GPIO_SRCTR_SRCTR4 GPIO_SRCTR_SRCTR4_Msk /*!< GPIO x SRCTR, pin 4 */ +#define GPIO_SRCTR_SRCTR5_Pos (5U) +#define GPIO_SRCTR_SRCTR5_Msk (0x1U << GPIO_SRCTR_SRCTR5_Pos) /*!< 0x00000020 */ +#define GPIO_SRCTR_SRCTR5 GPIO_SRCTR_SRCTR5_Msk /*!< GPIO x SRCTR, pin 5 */ +#define GPIO_SRCTR_SRCTR6_Pos (6U) +#define GPIO_SRCTR_SRCTR6_Msk (0x1U << GPIO_SRCTR_SRCTR6_Pos) /*!< 0x00000040 */ +#define GPIO_SRCTR_SRCTR6 GPIO_SRCTR_SRCTR6_Msk /*!< GPIO x SRCTR, pin 6 */ +#define GPIO_SRCTR_SRCTR7_Pos (7U) +#define GPIO_SRCTR_SRCTR7_Msk (0x1U << GPIO_SRCTR_SRCTR7_Pos) /*!< 0x00000080 */ +#define GPIO_SRCTR_SRCTR7 GPIO_SRCTR_SRCTR7_Msk /*!< GPIO x SRCTR, pin 7 */ +#define GPIO_SRCTR_SRCTR8_Pos (8U) +#define GPIO_SRCTR_SRCTR8_Msk (0x1U << GPIO_SRCTR_SRCTR8_Pos) /*!< 0x00000100 */ +#define GPIO_SRCTR_SRCTR8 GPIO_SRCTR_SRCTR8_Msk /*!< GPIO x SRCTR, pin 8 */ +#define GPIO_SRCTR_SRCTR9_Pos (9U) +#define GPIO_SRCTR_SRCTR9_Msk (0x1U << GPIO_SRCTR_SRCTR9_Pos) /*!< 0x00000200 */ +#define GPIO_SRCTR_SRCTR9 GPIO_SRCTR_SRCTR9_Msk /*!< GPIO x SRCTR, pin 9 */ +#define GPIO_SRCTR_SRCTR10_Pos (10U) +#define GPIO_SRCTR_SRCTR10_Msk (0x1U << GPIO_SRCTR_SRCTR10_Pos) /*!< 0x00000400 */ +#define GPIO_SRCTR_SRCTR10 GPIO_SRCTR_SRCTR10_Msk /*!< GPIO x SRCTR, pin 10 */ +#define GPIO_SRCTR_SRCTR11_Pos (11U) +#define GPIO_SRCTR_SRCTR11_Msk (0x1U << GPIO_SRCTR_SRCTR11_Pos) /*!< 0x00000800 */ +#define GPIO_SRCTR_SRCTR11 GPIO_SRCTR_SRCTR11_Msk /*!< GPIO x SRCTR, pin 11 */ +#define GPIO_SRCTR_SRCTR12_Pos (12U) +#define GPIO_SRCTR_SRCTR12_Msk (0x1U << GPIO_SRCTR_SRCTR12_Pos) /*!< 0x00001000 */ +#define GPIO_SRCTR_SRCTR12 GPIO_SRCTR_SRCTR12_Msk /*!< GPIO x SRCTR, pin 12 */ +#define GPIO_SRCTR_SRCTR13_Pos (13U) +#define GPIO_SRCTR_SRCTR13_Msk (0x1U << GPIO_SRCTR_SRCTR13_Pos) /*!< 0x00002000 */ +#define GPIO_SRCTR_SRCTR13 GPIO_SRCTR_SRCTR13_Msk /*!< GPIO x SRCTR, pin 13 */ +#define GPIO_SRCTR_SRCTR14_Pos (14U) +#define GPIO_SRCTR_SRCTR14_Msk (0x1U << GPIO_SRCTR_SRCTR14_Pos) /*!< 0x00004000 */ +#define GPIO_SRCTR_SRCTR14 GPIO_SRCTR_SRCTR14_Msk /*!< GPIO x SRCTR, pin 14 */ +#define GPIO_SRCTR_SRCTR15_Pos (15U) +#define GPIO_SRCTR_SRCTR15_Msk (0x1U << GPIO_SRCTR_SRCTR15_Pos) /*!< 0x00008000 */ +#define GPIO_SRCTR_SRCTR15 GPIO_SRCTR_SRCTR15_Msk /*!< GPIO x SRCTR, pin 15 */ + +/******************************************************************************/ +/* */ +/* System configuration controller (SCFG) */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for SCFG_CFG1 register *******************/ +/*!< MEM_MAP_SEL configuration */ +#define SCFG_CFG1_MEM_MAP_SEL_Pos (0U) +#define SCFG_CFG1_MEM_MAP_SEL_Msk (0x3U << SCFG_CFG1_MEM_MAP_SEL_Pos) /*!< 0x00000003 */ +#define SCFG_CFG1_MEM_MAP_SEL SCFG_CFG1_MEM_MAP_SEL_Msk /*!< MEM_MAP_SEL[1:0] bits (Boot mode status bit) */ +#define SCFG_CFG1_MEM_MAP_SEL_0 (0x1U << SCFG_CFG1_MEM_MAP_SEL_Pos) /*!< 0x00000001 */ +#define SCFG_CFG1_MEM_MAP_SEL_1 (0x2U << SCFG_CFG1_MEM_MAP_SEL_Pos) /*!< 0x00000002 */ + +#define SCFG_CFG1_MEM_MAP_SEL_FLASHMEM 0x00000000U /*!< Boot from main flash memory */ +#define SCFG_CFG1_MEM_MAP_SEL_SYSMEM 0x00000001U /*!< Boot from system memory */ +#define SCFG_CFG1_MEM_MAP_SEL_INTSRAM 0x00000003U /*!< Boot from internal SRAM */ + +#define SCFG_CFG1_IR_POL_Pos (5U) +#define SCFG_CFG1_IR_POL_Msk (0x1U << SCFG_CFG1_IR_POL_Pos) /*!< 0x00000020 */ +#define SCFG_CFG1_IR_POL SCFG_CFG1_IR_POL_Msk /*!< Infrared output polarity selection */ + +/*!< IR_SRC_SEL configuration */ +#define SCFG_CFG1_IR_SRC_SEL_Pos (6U) +#define SCFG_CFG1_IR_SRC_SEL_Msk (0x3U << SCFG_CFG1_IR_SRC_SEL_Pos) /*!< 0x000000C0 */ +#define SCFG_CFG1_IR_SRC_SEL SCFG_CFG1_IR_SRC_SEL_Msk /*!< IR_SRC_SEL[1:0] bits (IR modulation envelope signal source selection) */ +#define SCFG_CFG1_IR_SRC_SEL_0 (0x1U << SCFG_CFG1_IR_SRC_SEL_Pos) /*!< 0x00000040 */ +#define SCFG_CFG1_IR_SRC_SEL_1 (0x2U << SCFG_CFG1_IR_SRC_SEL_Pos) /*!< 0x00000080 */ + +#define SCFG_CFG1_IR_SRC_SEL_TMR10 0x00000000U /*!< TMR10 */ +#define SCFG_CFG1_IR_SRC_SEL_USART1 0x00000040U /*!< USART1 */ +#define SCFG_CFG1_IR_SRC_SEL_USART2 0x00000080U /*!< USART2 */ + +/****************** Bit definition for SCFG_CFG2 register *******************/ +#define SCFG_CFG2_LOCKUP_LK_Pos (0U) +#define SCFG_CFG2_LOCKUP_LK_Msk (0x1U << SCFG_CFG2_LOCKUP_LK_Pos) /*!< 0x00000001 */ +#define SCFG_CFG2_LOCKUP_LK SCFG_CFG2_LOCKUP_LK_Msk /*!< Cortex-M4F lockup bit enable */ +#define SCFG_CFG2_SRAM_OPERR_LK_Pos (1U) +#define SCFG_CFG2_SRAM_OPERR_LK_Msk (0x1U << SCFG_CFG2_SRAM_OPERR_LK_Pos) /*!< 0x00000002 */ +#define SCFG_CFG2_SRAM_OPERR_LK SCFG_CFG2_SRAM_OPERR_LK_Msk /*!< SRAM odd parity error lock enable */ +#define SCFG_CFG2_PVM_LK_Pos (2U) +#define SCFG_CFG2_PVM_LK_Msk (0x1U << SCFG_CFG2_PVM_LK_Pos) /*!< 0x00000004 */ +#define SCFG_CFG2_PVM_LK SCFG_CFG2_PVM_LK_Msk /*!< PVM lock enable */ +#define SCFG_CFG2_SRAM_OPERR_STS_Pos (8U) +#define SCFG_CFG2_SRAM_OPERR_STS_Msk (0x1U << SCFG_CFG2_SRAM_OPERR_STS_Pos) /*!< 0x00000100 */ +#define SCFG_CFG2_SRAM_OPERR_STS SCFG_CFG2_SRAM_OPERR_STS_Msk /*!< SRAM odd parity error status */ + +/*!< I2S_FD configuration */ +#define SCFG_CFG2_I2S_FD_Pos (30U) +#define SCFG_CFG2_I2S_FD_Msk (0x3U << SCFG_CFG2_I2S_FD_Pos) /*!< 0xC0000000 */ +#define SCFG_CFG2_I2S_FD SCFG_CFG2_I2S_FD_Msk /*!< I2S_FD[1:0] bits (I2S full duplex configuration bit) */ +#define SCFG_CFG2_I2S_FD_0 (0x1U << SCFG_CFG2_I2S_FD_Pos) /*!< 0x40000000 */ +#define SCFG_CFG2_I2S_FD_1 (0x2U << SCFG_CFG2_I2S_FD_Pos) /*!< 0x80000000 */ + +#define SCFG_CFG2_I2S_FD_SPI_I2S 0x00000000U /*!< SPI / I2S1 ~ 3 operates separately */ +#define SCFG_CFG2_I2S_FD_I2S1_3_FD 0x40000000U /*!< I2S1 and I2S3 are configured as full-duplex mode */ +#define SCFG_CFG2_I2S_FD_I2S2_3_FD 0x80000000U /*!< I2S2 and I2S3 are configured as full-duplex mode */ +#define SCFG_CFG2_I2S_FD_I2S1_2_FD 0xC0000000U /*!< I2S1 and I2S2 are configured as full-duplex mode */ + +/***************** Bit definition for SCFG_EXINTC1 register *****************/ +/*!< EXINT0 configuration */ +#define SCFG_EXINTC1_EXINT0_Pos (0U) +#define SCFG_EXINTC1_EXINT0_Msk (0xFU << SCFG_EXINTC1_EXINT0_Pos) /*!< 0x0000000F */ +#define SCFG_EXINTC1_EXINT0 SCFG_EXINTC1_EXINT0_Msk /*!< EXINT0[3:0] bits (EXINT0 input source configuration) */ + +#define SCFG_EXINTC1_EXINT0_GPA 0x00000000U /*!< GPIOA pin 0 */ +#define SCFG_EXINTC1_EXINT0_GPB_Pos (0U) +#define SCFG_EXINTC1_EXINT0_GPB_Msk (0x1U << SCFG_EXINTC1_EXINT0_GPB_Pos) /*!< 0x00000001 */ +#define SCFG_EXINTC1_EXINT0_GPB SCFG_EXINTC1_EXINT0_GPB_Msk /*!< GPIOB pin 0 */ +#define SCFG_EXINTC1_EXINT0_GPC_Pos (1U) +#define SCFG_EXINTC1_EXINT0_GPC_Msk (0x1U << SCFG_EXINTC1_EXINT0_GPC_Pos) /*!< 0x00000002 */ +#define SCFG_EXINTC1_EXINT0_GPC SCFG_EXINTC1_EXINT0_GPC_Msk /*!< GPIOC pin 0 */ +#define SCFG_EXINTC1_EXINT0_GPD_Pos (0U) +#define SCFG_EXINTC1_EXINT0_GPD_Msk (0x3U << SCFG_EXINTC1_EXINT0_GPD_Pos) /*!< 0x00000003 */ +#define SCFG_EXINTC1_EXINT0_GPD SCFG_EXINTC1_EXINT0_GPD_Msk /*!< GPIOD pin 0 */ +#define SCFG_EXINTC1_EXINT0_GPF_Pos (2U) +#define SCFG_EXINTC1_EXINT0_GPF_Msk (0x1U << SCFG_EXINTC1_EXINT0_GPF_Pos) /*!< 0x00000004 */ +#define SCFG_EXINTC1_EXINT0_GPF SCFG_EXINTC1_EXINT0_GPF_Msk /*!< GPIOF pin 0 */ + +/*!< EXINT1 configuration */ +#define SCFG_EXINTC1_EXINT1_Pos (4U) +#define SCFG_EXINTC1_EXINT1_Msk (0xFU << SCFG_EXINTC1_EXINT1_Pos) /*!< 0x000000F0 */ +#define SCFG_EXINTC1_EXINT1 SCFG_EXINTC1_EXINT1_Msk /*!< EXINT1[3:0] bits (EXINT1 input source configuration) */ + +#define SCFG_EXINTC1_EXINT1_GPA 0x00000000U /*!< GPIOA pin 1 */ +#define SCFG_EXINTC1_EXINT1_GPB_Pos (4U) +#define SCFG_EXINTC1_EXINT1_GPB_Msk (0x1U << SCFG_EXINTC1_EXINT1_GPB_Pos) /*!< 0x00000010 */ +#define SCFG_EXINTC1_EXINT1_GPB SCFG_EXINTC1_EXINT1_GPB_Msk /*!< GPIOB pin 1 */ +#define SCFG_EXINTC1_EXINT1_GPC_Pos (5U) +#define SCFG_EXINTC1_EXINT1_GPC_Msk (0x1U << SCFG_EXINTC1_EXINT1_GPC_Pos) /*!< 0x00000020 */ +#define SCFG_EXINTC1_EXINT1_GPC SCFG_EXINTC1_EXINT1_GPC_Msk /*!< GPIOC pin 1 */ +#define SCFG_EXINTC1_EXINT1_GPD_Pos (4U) +#define SCFG_EXINTC1_EXINT1_GPD_Msk (0x3U << SCFG_EXINTC1_EXINT1_GPD_Pos) /*!< 0x00000030 */ +#define SCFG_EXINTC1_EXINT1_GPD SCFG_EXINTC1_EXINT1_GPD_Msk /*!< GPIOD pin 1 */ +#define SCFG_EXINTC1_EXINT1_GPF_Pos (6U) +#define SCFG_EXINTC1_EXINT1_GPF_Msk (0x1U << SCFG_EXINTC1_EXINT1_GPF_Pos) /*!< 0x00000040 */ +#define SCFG_EXINTC1_EXINT1_GPF SCFG_EXINTC1_EXINT1_GPF_Msk /*!< GPIOF pin 1 */ + +/*!< EXINT2 configuration */ +#define SCFG_EXINTC1_EXINT2_Pos (8U) +#define SCFG_EXINTC1_EXINT2_Msk (0xFU << SCFG_EXINTC1_EXINT2_Pos) /*!< 0x00000F00 */ +#define SCFG_EXINTC1_EXINT2 SCFG_EXINTC1_EXINT2_Msk /*!< EXINT2[3:0] bits (EXINT2 input source configuration) */ + +#define SCFG_EXINTC1_EXINT2_GPA 0x00000000U /*!< GPIOA pin 2 */ +#define SCFG_EXINTC1_EXINT2_GPB_Pos (8U) +#define SCFG_EXINTC1_EXINT2_GPB_Msk (0x1U << SCFG_EXINTC1_EXINT2_GPB_Pos) /*!< 0x00000100 */ +#define SCFG_EXINTC1_EXINT2_GPB SCFG_EXINTC1_EXINT2_GPB_Msk /*!< GPIOB pin 2 */ +#define SCFG_EXINTC1_EXINT2_GPC_Pos (9U) +#define SCFG_EXINTC1_EXINT2_GPC_Msk (0x1U << SCFG_EXINTC1_EXINT2_GPC_Pos) /*!< 0x00000200 */ +#define SCFG_EXINTC1_EXINT2_GPC SCFG_EXINTC1_EXINT2_GPC_Msk /*!< GPIOC pin 2 */ +#define SCFG_EXINTC1_EXINT2_GPD_Pos (8U) +#define SCFG_EXINTC1_EXINT2_GPD_Msk (0x3U << SCFG_EXINTC1_EXINT2_GPD_Pos) /*!< 0x00000300 */ +#define SCFG_EXINTC1_EXINT2_GPD SCFG_EXINTC1_EXINT2_GPD_Msk /*!< GPIOD pin 2 */ +#define SCFG_EXINTC1_EXINT2_GPF_Pos (10U) +#define SCFG_EXINTC1_EXINT2_GPF_Msk (0x1U << SCFG_EXINTC1_EXINT2_GPF_Pos) /*!< 0x00000400 */ +#define SCFG_EXINTC1_EXINT2_GPF SCFG_EXINTC1_EXINT2_GPF_Msk /*!< GPIOF pin 2 */ + +/*!< EXINT3 configuration */ +#define SCFG_EXINTC1_EXINT3_Pos (12U) +#define SCFG_EXINTC1_EXINT3_Msk (0xFU << SCFG_EXINTC1_EXINT3_Pos) /*!< 0x0000F000 */ +#define SCFG_EXINTC1_EXINT3 SCFG_EXINTC1_EXINT3_Msk /*!< EXINT3[3:0] bits (EXINT3 input source configuration) */ + +#define SCFG_EXINTC1_EXINT3_GPA 0x00000000U /*!< GPIOA pin 3 */ +#define SCFG_EXINTC1_EXINT3_GPB_Pos (12U) +#define SCFG_EXINTC1_EXINT3_GPB_Msk (0x1U << SCFG_EXINTC1_EXINT3_GPB_Pos) /*!< 0x00001000 */ +#define SCFG_EXINTC1_EXINT3_GPB SCFG_EXINTC1_EXINT3_GPB_Msk /*!< GPIOB pin 3 */ +#define SCFG_EXINTC1_EXINT3_GPC_Pos (13U) +#define SCFG_EXINTC1_EXINT3_GPC_Msk (0x1U << SCFG_EXINTC1_EXINT3_GPC_Pos) /*!< 0x00002000 */ +#define SCFG_EXINTC1_EXINT3_GPC SCFG_EXINTC1_EXINT3_GPC_Msk /*!< GPIOC pin 3 */ +#define SCFG_EXINTC1_EXINT3_GPD_Pos (12U) +#define SCFG_EXINTC1_EXINT3_GPD_Msk (0x3U << SCFG_EXINTC1_EXINT3_GPD_Pos) /*!< 0x00003000 */ +#define SCFG_EXINTC1_EXINT3_GPD SCFG_EXINTC1_EXINT3_GPD_Msk /*!< GPIOD pin 3 */ +#define SCFG_EXINTC1_EXINT3_GPF_Pos (14U) +#define SCFG_EXINTC1_EXINT3_GPF_Msk (0x1U << SCFG_EXINTC1_EXINT3_GPF_Pos) /*!< 0x00004000 */ +#define SCFG_EXINTC1_EXINT3_GPF SCFG_EXINTC1_EXINT3_GPF_Msk /*!< GPIOF pin 3 */ + +/***************** Bit definition for SCFG_EXINTC2 register *****************/ +/*!< EXINT4 configuration */ +#define SCFG_EXINTC2_EXINT4_Pos (0U) +#define SCFG_EXINTC2_EXINT4_Msk (0xFU << SCFG_EXINTC2_EXINT4_Pos) /*!< 0x0000000F */ +#define SCFG_EXINTC2_EXINT4 SCFG_EXINTC2_EXINT4_Msk /*!< EXINT4[3:0] bits (EXINT4 input source configuration) */ + +#define SCFG_EXINTC2_EXINT4_GPA 0x00000000U /*!< GPIOA pin 4 */ +#define SCFG_EXINTC2_EXINT4_GPB_Pos (0U) +#define SCFG_EXINTC2_EXINT4_GPB_Msk (0x1U << SCFG_EXINTC2_EXINT4_GPB_Pos) /*!< 0x00000001 */ +#define SCFG_EXINTC2_EXINT4_GPB SCFG_EXINTC2_EXINT4_GPB_Msk /*!< GPIOB pin 4 */ +#define SCFG_EXINTC2_EXINT4_GPC_Pos (1U) +#define SCFG_EXINTC2_EXINT4_GPC_Msk (0x1U << SCFG_EXINTC2_EXINT4_GPC_Pos) /*!< 0x00000002 */ +#define SCFG_EXINTC2_EXINT4_GPC SCFG_EXINTC2_EXINT4_GPC_Msk /*!< GPIOC pin 4 */ +#define SCFG_EXINTC2_EXINT4_GPD_Pos (0U) +#define SCFG_EXINTC2_EXINT4_GPD_Msk (0x3U << SCFG_EXINTC2_EXINT4_GPD_Pos) /*!< 0x00000003 */ +#define SCFG_EXINTC2_EXINT4_GPD SCFG_EXINTC2_EXINT4_GPD_Msk /*!< GPIOD pin 4 */ +#define SCFG_EXINTC2_EXINT4_GPF_Pos (2U) +#define SCFG_EXINTC2_EXINT4_GPF_Msk (0x1U << SCFG_EXINTC2_EXINT4_GPF_Pos) /*!< 0x00000004 */ +#define SCFG_EXINTC2_EXINT4_GPF SCFG_EXINTC2_EXINT4_GPF_Msk /*!< GPIOF pin 4 */ + +/* EXINT5 configuration */ +#define SCFG_EXINTC2_EXINT5_Pos (4U) +#define SCFG_EXINTC2_EXINT5_Msk (0xFU << SCFG_EXINTC2_EXINT5_Pos) /*!< 0x000000F0 */ +#define SCFG_EXINTC2_EXINT5 SCFG_EXINTC2_EXINT5_Msk /*!< EXINT5[3:0] bits (EXINT5 input source configuration) */ + +#define SCFG_EXINTC2_EXINT5_GPA 0x00000000U /*!< GPIOA pin 5 */ +#define SCFG_EXINTC2_EXINT5_GPB_Pos (4U) +#define SCFG_EXINTC2_EXINT5_GPB_Msk (0x1U << SCFG_EXINTC2_EXINT5_GPB_Pos) /*!< 0x00000010 */ +#define SCFG_EXINTC2_EXINT5_GPB SCFG_EXINTC2_EXINT5_GPB_Msk /*!< GPIOB pin 5 */ +#define SCFG_EXINTC2_EXINT5_GPC_Pos (5U) +#define SCFG_EXINTC2_EXINT5_GPC_Msk (0x1U << SCFG_EXINTC2_EXINT5_GPC_Pos) /*!< 0x00000020 */ +#define SCFG_EXINTC2_EXINT5_GPC SCFG_EXINTC2_EXINT5_GPC_Msk /*!< GPIOC pin 5 */ +#define SCFG_EXINTC2_EXINT5_GPD_Pos (4U) +#define SCFG_EXINTC2_EXINT5_GPD_Msk (0x3U << SCFG_EXINTC2_EXINT5_GPD_Pos) /*!< 0x00000030 */ +#define SCFG_EXINTC2_EXINT5_GPD SCFG_EXINTC2_EXINT5_GPD_Msk /*!< GPIOD pin 5 */ +#define SCFG_EXINTC2_EXINT5_GPF_Pos (6U) +#define SCFG_EXINTC2_EXINT5_GPF_Msk (0x1U << SCFG_EXINTC2_EXINT5_GPF_Pos) /*!< 0x00000040 */ +#define SCFG_EXINTC2_EXINT5_GPF SCFG_EXINTC2_EXINT5_GPF_Msk /*!< GPIOF pin 5 */ + +/*!< EXINT6 configuration */ +#define SCFG_EXINTC2_EXINT6_Pos (8U) +#define SCFG_EXINTC2_EXINT6_Msk (0xFU << SCFG_EXINTC2_EXINT6_Pos) /*!< 0x00000F00 */ +#define SCFG_EXINTC2_EXINT6 SCFG_EXINTC2_EXINT6_Msk /*!< EXINT6[3:0] bits (EXINT6 input source configuration) */ + +#define SCFG_EXINTC2_EXINT6_GPA 0x00000000U /*!< GPIOA pin 6 */ +#define SCFG_EXINTC2_EXINT6_GPB_Pos (8U) +#define SCFG_EXINTC2_EXINT6_GPB_Msk (0x1U << SCFG_EXINTC2_EXINT6_GPB_Pos) /*!< 0x00000100 */ +#define SCFG_EXINTC2_EXINT6_GPB SCFG_EXINTC2_EXINT6_GPB_Msk /*!< GPIOB pin 6 */ +#define SCFG_EXINTC2_EXINT6_GPC_Pos (9U) +#define SCFG_EXINTC2_EXINT6_GPC_Msk (0x1U << SCFG_EXINTC2_EXINT6_GPC_Pos) /*!< 0x00000200 */ +#define SCFG_EXINTC2_EXINT6_GPC SCFG_EXINTC2_EXINT6_GPC_Msk /*!< GPIOC pin 6 */ +#define SCFG_EXINTC2_EXINT6_GPD_Pos (8U) +#define SCFG_EXINTC2_EXINT6_GPD_Msk (0x3U << SCFG_EXINTC2_EXINT6_GPD_Pos) /*!< 0x00000300 */ +#define SCFG_EXINTC2_EXINT6_GPD SCFG_EXINTC2_EXINT6_GPD_Msk /*!< GPIOD pin 6 */ +#define SCFG_EXINTC2_EXINT6_GPF_Pos (10U) +#define SCFG_EXINTC2_EXINT6_GPF_Msk (0x1U << SCFG_EXINTC2_EXINT6_GPF_Pos) /*!< 0x00000400 */ +#define SCFG_EXINTC2_EXINT6_GPF SCFG_EXINTC2_EXINT6_GPF_Msk /*!< GPIOF pin 6 */ + +/*!< EXINT7 configuration */ +#define SCFG_EXINTC2_EXINT7_Pos (12U) +#define SCFG_EXINTC2_EXINT7_Msk (0xFU << SCFG_EXINTC2_EXINT7_Pos) /*!< 0x0000F000 */ +#define SCFG_EXINTC2_EXINT7 SCFG_EXINTC2_EXINT7_Msk /*!< EXINT7[3:0] bits (EXINT7 input source configuration) */ + +#define SCFG_EXINTC2_EXINT7_GPA 0x00000000U /*!< GPIOA pin 7 */ +#define SCFG_EXINTC2_EXINT7_GPB_Pos (12U) +#define SCFG_EXINTC2_EXINT7_GPB_Msk (0x1U << SCFG_EXINTC2_EXINT7_GPB_Pos) /*!< 0x00001000 */ +#define SCFG_EXINTC2_EXINT7_GPB SCFG_EXINTC2_EXINT7_GPB_Msk /*!< GPIOB pin 7 */ +#define SCFG_EXINTC2_EXINT7_GPC_Pos (13U) +#define SCFG_EXINTC2_EXINT7_GPC_Msk (0x1U << SCFG_EXINTC2_EXINT7_GPC_Pos) /*!< 0x00002000 */ +#define SCFG_EXINTC2_EXINT7_GPC SCFG_EXINTC2_EXINT7_GPC_Msk /*!< GPIOC pin 7 */ +#define SCFG_EXINTC2_EXINT7_GPD_Pos (12U) +#define SCFG_EXINTC2_EXINT7_GPD_Msk (0x3U << SCFG_EXINTC2_EXINT7_GPD_Pos) /*!< 0x00003000 */ +#define SCFG_EXINTC2_EXINT7_GPD SCFG_EXINTC2_EXINT7_GPD_Msk /*!< GPIOD pin 7 */ +#define SCFG_EXINTC2_EXINT7_GPF_Pos (14U) +#define SCFG_EXINTC2_EXINT7_GPF_Msk (0x1U << SCFG_EXINTC2_EXINT7_GPF_Pos) /*!< 0x00004000 */ +#define SCFG_EXINTC2_EXINT7_GPF SCFG_EXINTC2_EXINT7_GPF_Msk /*!< GPIOF pin 7 */ + +/***************** Bit definition for SCFG_EXINTC3 register *****************/ +/*!< EXINT8 configuration */ +#define SCFG_EXINTC3_EXINT8_Pos (0U) +#define SCFG_EXINTC3_EXINT8_Msk (0xFU << SCFG_EXINTC3_EXINT8_Pos) /*!< 0x0000000F */ +#define SCFG_EXINTC3_EXINT8 SCFG_EXINTC3_EXINT8_Msk /*!< EXINT8[3:0] bits (EXINT8 input source configuration) */ + +#define SCFG_EXINTC3_EXINT8_GPA 0x00000000U /*!< GPIOA pin 8 */ +#define SCFG_EXINTC3_EXINT8_GPB_Pos (0U) +#define SCFG_EXINTC3_EXINT8_GPB_Msk (0x1U << SCFG_EXINTC3_EXINT8_GPB_Pos) /*!< 0x00000001 */ +#define SCFG_EXINTC3_EXINT8_GPB SCFG_EXINTC3_EXINT8_GPB_Msk /*!< GPIOB pin 8 */ +#define SCFG_EXINTC3_EXINT8_GPC_Pos (1U) +#define SCFG_EXINTC3_EXINT8_GPC_Msk (0x1U << SCFG_EXINTC3_EXINT8_GPC_Pos) /*!< 0x00000002 */ +#define SCFG_EXINTC3_EXINT8_GPC SCFG_EXINTC3_EXINT8_GPC_Msk /*!< GPIOC pin 8 */ +#define SCFG_EXINTC3_EXINT8_GPD_Pos (0U) +#define SCFG_EXINTC3_EXINT8_GPD_Msk (0x3U << SCFG_EXINTC3_EXINT8_GPD_Pos) /*!< 0x00000003 */ +#define SCFG_EXINTC3_EXINT8_GPD SCFG_EXINTC3_EXINT8_GPD_Msk /*!< GPIOD pin 8 */ +#define SCFG_EXINTC3_EXINT8_GPF_Pos (2U) +#define SCFG_EXINTC3_EXINT8_GPF_Msk (0x1U << SCFG_EXINTC3_EXINT8_GPF_Pos) /*!< 0x00000004 */ +#define SCFG_EXINTC3_EXINT8_GPF SCFG_EXINTC3_EXINT8_GPF_Msk /*!< GPIOF pin 8 */ + +/*!< EXINT9 configuration */ +#define SCFG_EXINTC3_EXINT9_Pos (4U) +#define SCFG_EXINTC3_EXINT9_Msk (0xFU << SCFG_EXINTC3_EXINT9_Pos) /*!< 0x000000F0 */ +#define SCFG_EXINTC3_EXINT9 SCFG_EXINTC3_EXINT9_Msk /*!< EXINT9[3:0] bits (EXINT9 input source configuration) */ + +#define SCFG_EXINTC3_EXINT9_GPA 0x00000000U /*!< GPIOA pin 9 */ +#define SCFG_EXINTC3_EXINT9_GPB_Pos (4U) +#define SCFG_EXINTC3_EXINT9_GPB_Msk (0x1U << SCFG_EXINTC3_EXINT9_GPB_Pos) /*!< 0x00000010 */ +#define SCFG_EXINTC3_EXINT9_GPB SCFG_EXINTC3_EXINT9_GPB_Msk /*!< GPIOB pin 9 */ +#define SCFG_EXINTC3_EXINT9_GPC_Pos (5U) +#define SCFG_EXINTC3_EXINT9_GPC_Msk (0x1U << SCFG_EXINTC3_EXINT9_GPC_Pos) /*!< 0x00000020 */ +#define SCFG_EXINTC3_EXINT9_GPC SCFG_EXINTC3_EXINT9_GPC_Msk /*!< GPIOC pin 9 */ +#define SCFG_EXINTC3_EXINT9_GPD_Pos (4U) +#define SCFG_EXINTC3_EXINT9_GPD_Msk (0x3U << SCFG_EXINTC3_EXINT9_GPD_Pos) /*!< 0x00000030 */ +#define SCFG_EXINTC3_EXINT9_GPD SCFG_EXINTC3_EXINT9_GPD_Msk /*!< GPIOD pin 9 */ +#define SCFG_EXINTC3_EXINT9_GPF_Pos (6U) +#define SCFG_EXINTC3_EXINT9_GPF_Msk (0x1U << SCFG_EXINTC3_EXINT9_GPF_Pos) /*!< 0x00000040 */ +#define SCFG_EXINTC3_EXINT9_GPF SCFG_EXINTC3_EXINT9_GPF_Msk /*!< GPIOF pin 9 */ + +/*!< EXINT10 configuration */ +#define SCFG_EXINTC3_EXINT10_Pos (8U) +#define SCFG_EXINTC3_EXINT10_Msk (0xFU << SCFG_EXINTC3_EXINT10_Pos) /*!< 0x00000F00 */ +#define SCFG_EXINTC3_EXINT10 SCFG_EXINTC3_EXINT10_Msk /*!< EXINT10[3:0] bits (EXINT10 input source configuration) */ + +#define SCFG_EXINTC3_EXINT10_GPA 0x00000000U /*!< GPIOA pin 10 */ +#define SCFG_EXINTC3_EXINT10_GPB_Pos (8U) +#define SCFG_EXINTC3_EXINT10_GPB_Msk (0x1U << SCFG_EXINTC3_EXINT10_GPB_Pos) /*!< 0x00000100 */ +#define SCFG_EXINTC3_EXINT10_GPB SCFG_EXINTC3_EXINT10_GPB_Msk /*!< GPIOB pin 10 */ +#define SCFG_EXINTC3_EXINT10_GPC_Pos (9U) +#define SCFG_EXINTC3_EXINT10_GPC_Msk (0x1U << SCFG_EXINTC3_EXINT10_GPC_Pos) /*!< 0x00000200 */ +#define SCFG_EXINTC3_EXINT10_GPC SCFG_EXINTC3_EXINT10_GPC_Msk /*!< GPIOC pin 10 */ +#define SCFG_EXINTC3_EXINT10_GPD_Pos (8U) +#define SCFG_EXINTC3_EXINT10_GPD_Msk (0x3U << SCFG_EXINTC3_EXINT10_GPD_Pos) /*!< 0x00000300 */ +#define SCFG_EXINTC3_EXINT10_GPD SCFG_EXINTC3_EXINT10_GPD_Msk /*!< GPIOD pin 10 */ +#define SCFG_EXINTC3_EXINT10_GPF_Pos (10U) +#define SCFG_EXINTC3_EXINT10_GPF_Msk (0x1U << SCFG_EXINTC3_EXINT10_GPF_Pos) /*!< 0x00000400 */ +#define SCFG_EXINTC3_EXINT10_GPF SCFG_EXINTC3_EXINT10_GPF_Msk /*!< GPIOF pin 10 */ + +/*!< EXINT11 configuration */ +#define SCFG_EXINTC3_EXINT11_Pos (12U) +#define SCFG_EXINTC3_EXINT11_Msk (0xFU << SCFG_EXINTC3_EXINT11_Pos) /*!< 0x0000F000 */ +#define SCFG_EXINTC3_EXINT11 SCFG_EXINTC3_EXINT11_Msk /*!< EXINT11[3:0] bits (EXINT11 input source configuration) */ + +#define SCFG_EXINTC3_EXINT11_GPA 0x00000000U /*!< GPIOA pin 11 */ +#define SCFG_EXINTC3_EXINT11_GPB_Pos (12U) +#define SCFG_EXINTC3_EXINT11_GPB_Msk (0x1U << SCFG_EXINTC3_EXINT11_GPB_Pos) /*!< 0x00001000 */ +#define SCFG_EXINTC3_EXINT11_GPB SCFG_EXINTC3_EXINT11_GPB_Msk /*!< GPIOB pin 11 */ +#define SCFG_EXINTC3_EXINT11_GPC_Pos (13U) +#define SCFG_EXINTC3_EXINT11_GPC_Msk (0x1U << SCFG_EXINTC3_EXINT11_GPC_Pos) /*!< 0x00002000 */ +#define SCFG_EXINTC3_EXINT11_GPC SCFG_EXINTC3_EXINT11_GPC_Msk /*!< GPIOC pin 11 */ +#define SCFG_EXINTC3_EXINT11_GPD_Pos (12U) +#define SCFG_EXINTC3_EXINT11_GPD_Msk (0x3U << SCFG_EXINTC3_EXINT11_GPD_Pos) /*!< 0x00003000 */ +#define SCFG_EXINTC3_EXINT11_GPD SCFG_EXINTC3_EXINT11_GPD_Msk /*!< GPIOD pin 11 */ +#define SCFG_EXINTC3_EXINT11_GPF_Pos (14U) +#define SCFG_EXINTC3_EXINT11_GPF_Msk (0x1U << SCFG_EXINTC3_EXINT11_GPF_Pos) /*!< 0x00004000 */ +#define SCFG_EXINTC3_EXINT11_GPF SCFG_EXINTC3_EXINT11_GPF_Msk /*!< GPIOF pin 11 */ + +/***************** Bit definition for SCFG_EXINTC4 register *****************/ +/* EXINT12 configuration */ +#define SCFG_EXINTC4_EXINT12_Pos (0U) +#define SCFG_EXINTC4_EXINT12_Msk (0xFU << SCFG_EXINTC4_EXINT12_Pos) /*!< 0x0000000F */ +#define SCFG_EXINTC4_EXINT12 SCFG_EXINTC4_EXINT12_Msk /*!< EXINT12[3:0] bits (EXINT12 input source configuration) */ + +#define SCFG_EXINTC4_EXINT12_GPA 0x00000000U /*!< GPIOA pin 12 */ +#define SCFG_EXINTC4_EXINT12_GPB_Pos (0U) +#define SCFG_EXINTC4_EXINT12_GPB_Msk (0x1U << SCFG_EXINTC4_EXINT12_GPB_Pos) /*!< 0x00000001 */ +#define SCFG_EXINTC4_EXINT12_GPB SCFG_EXINTC4_EXINT12_GPB_Msk /*!< GPIOB pin 12 */ +#define SCFG_EXINTC4_EXINT12_GPC_Pos (1U) +#define SCFG_EXINTC4_EXINT12_GPC_Msk (0x1U << SCFG_EXINTC4_EXINT12_GPC_Pos) /*!< 0x00000002 */ +#define SCFG_EXINTC4_EXINT12_GPC SCFG_EXINTC4_EXINT12_GPC_Msk /*!< GPIOC pin 12 */ +#define SCFG_EXINTC4_EXINT12_GPD_Pos (0U) +#define SCFG_EXINTC4_EXINT12_GPD_Msk (0x3U << SCFG_EXINTC4_EXINT12_GPD_Pos) /*!< 0x00000003 */ +#define SCFG_EXINTC4_EXINT12_GPD SCFG_EXINTC4_EXINT12_GPD_Msk /*!< GPIOD pin 12 */ +#define SCFG_EXINTC4_EXINT12_GPF_Pos (2U) +#define SCFG_EXINTC4_EXINT12_GPF_Msk (0x1U << SCFG_EXINTC4_EXINT12_GPF_Pos) /*!< 0x00000004 */ +#define SCFG_EXINTC4_EXINT12_GPF SCFG_EXINTC4_EXINT12_GPF_Msk /*!< GPIOF pin 12 */ + +/* EXINT13 configuration */ +#define SCFG_EXINTC4_EXINT13_Pos (4U) +#define SCFG_EXINTC4_EXINT13_Msk (0xFU << SCFG_EXINTC4_EXINT13_Pos) /*!< 0x000000F0 */ +#define SCFG_EXINTC4_EXINT13 SCFG_EXINTC4_EXINT13_Msk /*!< EXINT13[3:0] bits (EXINT13 input source configuration) */ + +#define SCFG_EXINTC4_EXINT13_GPA 0x00000000U /*!< GPIOA pin 13 */ +#define SCFG_EXINTC4_EXINT13_GPB_Pos (4U) +#define SCFG_EXINTC4_EXINT13_GPB_Msk (0x1U << SCFG_EXINTC4_EXINT13_GPB_Pos) /*!< 0x00000010 */ +#define SCFG_EXINTC4_EXINT13_GPB SCFG_EXINTC4_EXINT13_GPB_Msk /*!< GPIOB pin 13 */ +#define SCFG_EXINTC4_EXINT13_GPC_Pos (5U) +#define SCFG_EXINTC4_EXINT13_GPC_Msk (0x1U << SCFG_EXINTC4_EXINT13_GPC_Pos) /*!< 0x00000020 */ +#define SCFG_EXINTC4_EXINT13_GPC SCFG_EXINTC4_EXINT13_GPC_Msk /*!< GPIOC pin 13 */ +#define SCFG_EXINTC4_EXINT13_GPD_Pos (4U) +#define SCFG_EXINTC4_EXINT13_GPD_Msk (0x3U << SCFG_EXINTC4_EXINT13_GPD_Pos) /*!< 0x00000030 */ +#define SCFG_EXINTC4_EXINT13_GPD SCFG_EXINTC4_EXINT13_GPD_Msk /*!< GPIOD pin 13 */ +#define SCFG_EXINTC4_EXINT13_GPF_Pos (6U) +#define SCFG_EXINTC4_EXINT13_GPF_Msk (0x1U << SCFG_EXINTC4_EXINT13_GPF_Pos) /*!< 0x00000040 */ +#define SCFG_EXINTC4_EXINT13_GPF SCFG_EXINTC4_EXINT13_GPF_Msk /*!< GPIOF pin 13 */ + +/*!< EXINT14 configuration */ +#define SCFG_EXINTC4_EXINT14_Pos (8U) +#define SCFG_EXINTC4_EXINT14_Msk (0xFU << SCFG_EXINTC4_EXINT14_Pos) /*!< 0x00000F00 */ +#define SCFG_EXINTC4_EXINT14 SCFG_EXINTC4_EXINT14_Msk /*!< EXINT14[3:0] bits (EXINT14 input source configuration) */ + +#define SCFG_EXINTC4_EXINT14_GPA 0x00000000U /*!< GPIOA pin 14 */ +#define SCFG_EXINTC4_EXINT14_GPB_Pos (8U) +#define SCFG_EXINTC4_EXINT14_GPB_Msk (0x1U << SCFG_EXINTC4_EXINT14_GPB_Pos) /*!< 0x00000100 */ +#define SCFG_EXINTC4_EXINT14_GPB SCFG_EXINTC4_EXINT14_GPB_Msk /*!< GPIOB pin 14 */ +#define SCFG_EXINTC4_EXINT14_GPC_Pos (9U) +#define SCFG_EXINTC4_EXINT14_GPC_Msk (0x1U << SCFG_EXINTC4_EXINT14_GPC_Pos) /*!< 0x00000200 */ +#define SCFG_EXINTC4_EXINT14_GPC SCFG_EXINTC4_EXINT14_GPC_Msk /*!< GPIOC pin 14 */ +#define SCFG_EXINTC4_EXINT14_GPD_Pos (8U) +#define SCFG_EXINTC4_EXINT14_GPD_Msk (0x3U << SCFG_EXINTC4_EXINT14_GPD_Pos) /*!< 0x00000300 */ +#define SCFG_EXINTC4_EXINT14_GPD SCFG_EXINTC4_EXINT14_GPD_Msk /*!< GPIOD pin 14 */ +#define SCFG_EXINTC4_EXINT14_GPF_Pos (10U) +#define SCFG_EXINTC4_EXINT14_GPF_Msk (0x1U << SCFG_EXINTC4_EXINT14_GPF_Pos) /*!< 0x00000400 */ +#define SCFG_EXINTC4_EXINT14_GPF SCFG_EXINTC4_EXINT14_GPF_Msk /*!< GPIOF pin 14 */ + +/*!< EXINT15 configuration */ +#define SCFG_EXINTC4_EXINT15_Pos (12U) +#define SCFG_EXINTC4_EXINT15_Msk (0xFU << SCFG_EXINTC4_EXINT15_Pos) /*!< 0x0000F000 */ +#define SCFG_EXINTC4_EXINT15 SCFG_EXINTC4_EXINT15_Msk /*!< EXINT15[3:0] bits (EXINT15 input source configuration) */ + +#define SCFG_EXINTC4_EXINT15_GPA 0x00000000U /*!< GPIOA pin 15 */ +#define SCFG_EXINTC4_EXINT15_GPB_Pos (12U) +#define SCFG_EXINTC4_EXINT15_GPB_Msk (0x1U << SCFG_EXINTC4_EXINT15_GPB_Pos) /*!< 0x00001000 */ +#define SCFG_EXINTC4_EXINT15_GPB SCFG_EXINTC4_EXINT15_GPB_Msk /*!< GPIOB pin 15 */ +#define SCFG_EXINTC4_EXINT15_GPC_Pos (13U) +#define SCFG_EXINTC4_EXINT15_GPC_Msk (0x1U << SCFG_EXINTC4_EXINT15_GPC_Pos) /*!< 0x00002000 */ +#define SCFG_EXINTC4_EXINT15_GPC SCFG_EXINTC4_EXINT15_GPC_Msk /*!< GPIOC pin 15 */ +#define SCFG_EXINTC4_EXINT15_GPD_Pos (12U) +#define SCFG_EXINTC4_EXINT15_GPD_Msk (0x3U << SCFG_EXINTC4_EXINT15_GPD_Pos) /*!< 0x00003000 */ +#define SCFG_EXINTC4_EXINT15_GPD SCFG_EXINTC4_EXINT15_GPD_Msk /*!< GPIOD pin 15 */ +#define SCFG_EXINTC4_EXINT15_GPF_Pos (14U) +#define SCFG_EXINTC4_EXINT15_GPF_Msk (0x1U << SCFG_EXINTC4_EXINT15_GPF_Pos) /*!< 0x00004000 */ +#define SCFG_EXINTC4_EXINT15_GPF SCFG_EXINTC4_EXINT15_GPF_Msk /*!< GPIOF pin 15 */ + +/****************** Bit definition for SCFG_UHDRV register ******************/ +#define SCFG_UHDRV_PB3_UH_Pos (0U) +#define SCFG_UHDRV_PB3_UH_Msk (0x1U << SCFG_UHDRV_PB3_UH_Pos) /*!< 0x00000001 */ +#define SCFG_UHDRV_PB3_UH SCFG_UHDRV_PB3_UH_Msk /*!< PB3 Ultra high sourcing/sinking strength */ +#define SCFG_UHDRV_PB9_UH_Pos (1U) +#define SCFG_UHDRV_PB9_UH_Msk (0x1U << SCFG_UHDRV_PB9_UH_Pos) /*!< 0x00000002 */ +#define SCFG_UHDRV_PB9_UH SCFG_UHDRV_PB9_UH_Msk /*!< PB9 Ultra high sourcing/sinking strength */ +#define SCFG_UHDRV_PB10_UH_Pos (2U) +#define SCFG_UHDRV_PB10_UH_Msk (0x1U << SCFG_UHDRV_PB10_UH_Pos) /*!< 0x00000004 */ +#define SCFG_UHDRV_PB10_UH SCFG_UHDRV_PB10_UH_Msk /*!< PB10 Ultra high sourcing/sinking strength */ + +/******************************************************************************/ +/* */ +/* External interrupt/Event controller (EXINT) */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for EXINT_INTEN register ******************/ +#define EXINT_INTEN_INTEN0_Pos (0U) +#define EXINT_INTEN_INTEN0_Msk (0x1U << EXINT_INTEN_INTEN0_Pos) /*!< 0x00000001 */ +#define EXINT_INTEN_INTEN0 EXINT_INTEN_INTEN0_Msk /*!< Interrupt enable or disable on line 0 */ +#define EXINT_INTEN_INTEN1_Pos (1U) +#define EXINT_INTEN_INTEN1_Msk (0x1U << EXINT_INTEN_INTEN1_Pos) /*!< 0x00000002 */ +#define EXINT_INTEN_INTEN1 EXINT_INTEN_INTEN1_Msk /*!< Interrupt enable or disable on line 1 */ +#define EXINT_INTEN_INTEN2_Pos (2U) +#define EXINT_INTEN_INTEN2_Msk (0x1U << EXINT_INTEN_INTEN2_Pos) /*!< 0x00000004 */ +#define EXINT_INTEN_INTEN2 EXINT_INTEN_INTEN2_Msk /*!< Interrupt enable or disable on line 2 */ +#define EXINT_INTEN_INTEN3_Pos (3U) +#define EXINT_INTEN_INTEN3_Msk (0x1U << EXINT_INTEN_INTEN3_Pos) /*!< 0x00000008 */ +#define EXINT_INTEN_INTEN3 EXINT_INTEN_INTEN3_Msk /*!< Interrupt enable or disable on line 3 */ +#define EXINT_INTEN_INTEN4_Pos (4U) +#define EXINT_INTEN_INTEN4_Msk (0x1U << EXINT_INTEN_INTEN4_Pos) /*!< 0x00000010 */ +#define EXINT_INTEN_INTEN4 EXINT_INTEN_INTEN4_Msk /*!< Interrupt enable or disable on line 4 */ +#define EXINT_INTEN_INTEN5_Pos (5U) +#define EXINT_INTEN_INTEN5_Msk (0x1U << EXINT_INTEN_INTEN5_Pos) /*!< 0x00000020 */ +#define EXINT_INTEN_INTEN5 EXINT_INTEN_INTEN5_Msk /*!< Interrupt enable or disable on line 5 */ +#define EXINT_INTEN_INTEN6_Pos (6U) +#define EXINT_INTEN_INTEN6_Msk (0x1U << EXINT_INTEN_INTEN6_Pos) /*!< 0x00000040 */ +#define EXINT_INTEN_INTEN6 EXINT_INTEN_INTEN6_Msk /*!< Interrupt enable or disable on line 6 */ +#define EXINT_INTEN_INTEN7_Pos (7U) +#define EXINT_INTEN_INTEN7_Msk (0x1U << EXINT_INTEN_INTEN7_Pos) /*!< 0x00000080 */ +#define EXINT_INTEN_INTEN7 EXINT_INTEN_INTEN7_Msk /*!< Interrupt enable or disable on line 7 */ +#define EXINT_INTEN_INTEN8_Pos (8U) +#define EXINT_INTEN_INTEN8_Msk (0x1U << EXINT_INTEN_INTEN8_Pos) /*!< 0x00000100 */ +#define EXINT_INTEN_INTEN8 EXINT_INTEN_INTEN8_Msk /*!< Interrupt enable or disable on line 8 */ +#define EXINT_INTEN_INTEN9_Pos (9U) +#define EXINT_INTEN_INTEN9_Msk (0x1U << EXINT_INTEN_INTEN9_Pos) /*!< 0x00000200 */ +#define EXINT_INTEN_INTEN9 EXINT_INTEN_INTEN9_Msk /*!< Interrupt enable or disable on line 9 */ +#define EXINT_INTEN_INTEN10_Pos (10U) +#define EXINT_INTEN_INTEN10_Msk (0x1U << EXINT_INTEN_INTEN10_Pos) /*!< 0x00000400 */ +#define EXINT_INTEN_INTEN10 EXINT_INTEN_INTEN10_Msk /*!< Interrupt enable or disable on line 10 */ +#define EXINT_INTEN_INTEN11_Pos (11U) +#define EXINT_INTEN_INTEN11_Msk (0x1U << EXINT_INTEN_INTEN11_Pos) /*!< 0x00000800 */ +#define EXINT_INTEN_INTEN11 EXINT_INTEN_INTEN11_Msk /*!< Interrupt enable or disable on line 11 */ +#define EXINT_INTEN_INTEN12_Pos (12U) +#define EXINT_INTEN_INTEN12_Msk (0x1U << EXINT_INTEN_INTEN12_Pos) /*!< 0x00001000 */ +#define EXINT_INTEN_INTEN12 EXINT_INTEN_INTEN12_Msk /*!< Interrupt enable or disable on line 12 */ +#define EXINT_INTEN_INTEN13_Pos (13U) +#define EXINT_INTEN_INTEN13_Msk (0x1U << EXINT_INTEN_INTEN13_Pos) /*!< 0x00002000 */ +#define EXINT_INTEN_INTEN13 EXINT_INTEN_INTEN13_Msk /*!< Interrupt enable or disable on line 13 */ +#define EXINT_INTEN_INTEN14_Pos (14U) +#define EXINT_INTEN_INTEN14_Msk (0x1U << EXINT_INTEN_INTEN14_Pos) /*!< 0x00004000 */ +#define EXINT_INTEN_INTEN14 EXINT_INTEN_INTEN14_Msk /*!< Interrupt enable or disable on line 14 */ +#define EXINT_INTEN_INTEN15_Pos (15U) +#define EXINT_INTEN_INTEN15_Msk (0x1U << EXINT_INTEN_INTEN15_Pos) /*!< 0x00008000 */ +#define EXINT_INTEN_INTEN15 EXINT_INTEN_INTEN15_Msk /*!< Interrupt enable or disable on line 15 */ +#define EXINT_INTEN_INTEN16_Pos (16U) +#define EXINT_INTEN_INTEN16_Msk (0x1U << EXINT_INTEN_INTEN16_Pos) /*!< 0x00010000 */ +#define EXINT_INTEN_INTEN16 EXINT_INTEN_INTEN16_Msk /*!< Interrupt enable or disable on line 16 */ +#define EXINT_INTEN_INTEN17_Pos (17U) +#define EXINT_INTEN_INTEN17_Msk (0x1U << EXINT_INTEN_INTEN17_Pos) /*!< 0x00020000 */ +#define EXINT_INTEN_INTEN17 EXINT_INTEN_INTEN17_Msk /*!< Interrupt enable or disable on line 17 */ +#define EXINT_INTEN_INTEN18_Pos (18U) +#define EXINT_INTEN_INTEN18_Msk (0x1U << EXINT_INTEN_INTEN18_Pos) /*!< 0x00040000 */ +#define EXINT_INTEN_INTEN18 EXINT_INTEN_INTEN18_Msk /*!< Interrupt enable or disable on line 18 */ +#define EXINT_INTEN_INTEN20_Pos (20U) +#define EXINT_INTEN_INTEN20_Msk (0x1U << EXINT_INTEN_INTEN20_Pos) /*!< 0x00100000 */ +#define EXINT_INTEN_INTEN20 EXINT_INTEN_INTEN20_Msk /*!< Interrupt enable or disable on line 20 (F405 only) */ +#define EXINT_INTEN_INTEN21_Pos (21U) +#define EXINT_INTEN_INTEN21_Msk (0x1U << EXINT_INTEN_INTEN21_Pos) /*!< 0x00200000 */ +#define EXINT_INTEN_INTEN21 EXINT_INTEN_INTEN21_Msk /*!< Interrupt enable or disable on line 21 */ +#define EXINT_INTEN_INTEN22_Pos (22U) +#define EXINT_INTEN_INTEN22_Msk (0x1U << EXINT_INTEN_INTEN22_Pos) /*!< 0x00400000 */ +#define EXINT_INTEN_INTEN22 EXINT_INTEN_INTEN22_Msk /*!< Interrupt enable or disable on line 22 */ + +/* References Defines */ +#define EXINT_INTEN_INT0 EXINT_INTEN_INTEN0 +#define EXINT_INTEN_INT1 EXINT_INTEN_INTEN1 +#define EXINT_INTEN_INT2 EXINT_INTEN_INTEN2 +#define EXINT_INTEN_INT3 EXINT_INTEN_INTEN3 +#define EXINT_INTEN_INT4 EXINT_INTEN_INTEN4 +#define EXINT_INTEN_INT5 EXINT_INTEN_INTEN5 +#define EXINT_INTEN_INT6 EXINT_INTEN_INTEN6 +#define EXINT_INTEN_INT7 EXINT_INTEN_INTEN7 +#define EXINT_INTEN_INT8 EXINT_INTEN_INTEN8 +#define EXINT_INTEN_INT9 EXINT_INTEN_INTEN9 +#define EXINT_INTEN_INT10 EXINT_INTEN_INTEN10 +#define EXINT_INTEN_INT11 EXINT_INTEN_INTEN11 +#define EXINT_INTEN_INT12 EXINT_INTEN_INTEN12 +#define EXINT_INTEN_INT13 EXINT_INTEN_INTEN13 +#define EXINT_INTEN_INT14 EXINT_INTEN_INTEN14 +#define EXINT_INTEN_INT15 EXINT_INTEN_INTEN15 +#define EXINT_INTEN_INT16 EXINT_INTEN_INTEN16 +#define EXINT_INTEN_INT17 EXINT_INTEN_INTEN17 +#define EXINT_INTEN_INT18 EXINT_INTEN_INTEN18 +#define EXINT_INTEN_INT20 EXINT_INTEN_INTEN20 +#define EXINT_INTEN_INT21 EXINT_INTEN_INTEN21 +#define EXINT_INTEN_INT22 EXINT_INTEN_INTEN22 +#define EXINT_INTEN_INT 0x0077FFFFU /*!< Interrupt enable or disable all */ + +/***************** Bit definition for EXINT_EVTEN register ******************/ +#define EXINT_EVTEN_EVTEN0_Pos (0U) +#define EXINT_EVTEN_EVTEN0_Msk (0x1U << EXINT_EVTEN_EVTEN0_Pos) /*!< 0x00000001 */ +#define EXINT_EVTEN_EVTEN0 EXINT_EVTEN_EVTEN0_Msk /*!< Event enable or disable on line 0 */ +#define EXINT_EVTEN_EVTEN1_Pos (1U) +#define EXINT_EVTEN_EVTEN1_Msk (0x1U << EXINT_EVTEN_EVTEN1_Pos) /*!< 0x00000002 */ +#define EXINT_EVTEN_EVTEN1 EXINT_EVTEN_EVTEN1_Msk /*!< Event enable or disable on line 1 */ +#define EXINT_EVTEN_EVTEN2_Pos (2U) +#define EXINT_EVTEN_EVTEN2_Msk (0x1U << EXINT_EVTEN_EVTEN2_Pos) /*!< 0x00000004 */ +#define EXINT_EVTEN_EVTEN2 EXINT_EVTEN_EVTEN2_Msk /*!< Event enable or disable on line 2 */ +#define EXINT_EVTEN_EVTEN3_Pos (3U) +#define EXINT_EVTEN_EVTEN3_Msk (0x1U << EXINT_EVTEN_EVTEN3_Pos) /*!< 0x00000008 */ +#define EXINT_EVTEN_EVTEN3 EXINT_EVTEN_EVTEN3_Msk /*!< Event enable or disable on line 3 */ +#define EXINT_EVTEN_EVTEN4_Pos (4U) +#define EXINT_EVTEN_EVTEN4_Msk (0x1U << EXINT_EVTEN_EVTEN4_Pos) /*!< 0x00000010 */ +#define EXINT_EVTEN_EVTEN4 EXINT_EVTEN_EVTEN4_Msk /*!< Event enable or disable on line 4 */ +#define EXINT_EVTEN_EVTEN5_Pos (5U) +#define EXINT_EVTEN_EVTEN5_Msk (0x1U << EXINT_EVTEN_EVTEN5_Pos) /*!< 0x00000020 */ +#define EXINT_EVTEN_EVTEN5 EXINT_EVTEN_EVTEN5_Msk /*!< Event enable or disable on line 5 */ +#define EXINT_EVTEN_EVTEN6_Pos (6U) +#define EXINT_EVTEN_EVTEN6_Msk (0x1U << EXINT_EVTEN_EVTEN6_Pos) /*!< 0x00000040 */ +#define EXINT_EVTEN_EVTEN6 EXINT_EVTEN_EVTEN6_Msk /*!< Event enable or disable on line 6 */ +#define EXINT_EVTEN_EVTEN7_Pos (7U) +#define EXINT_EVTEN_EVTEN7_Msk (0x1U << EXINT_EVTEN_EVTEN7_Pos) /*!< 0x00000080 */ +#define EXINT_EVTEN_EVTEN7 EXINT_EVTEN_EVTEN7_Msk /*!< Event enable or disable on line 7 */ +#define EXINT_EVTEN_EVTEN8_Pos (8U) +#define EXINT_EVTEN_EVTEN8_Msk (0x1U << EXINT_EVTEN_EVTEN8_Pos) /*!< 0x00000100 */ +#define EXINT_EVTEN_EVTEN8 EXINT_EVTEN_EVTEN8_Msk /*!< Event enable or disable on line 8 */ +#define EXINT_EVTEN_EVTEN9_Pos (9U) +#define EXINT_EVTEN_EVTEN9_Msk (0x1U << EXINT_EVTEN_EVTEN9_Pos) /*!< 0x00000200 */ +#define EXINT_EVTEN_EVTEN9 EXINT_EVTEN_EVTEN9_Msk /*!< Event enable or disable on line 9 */ +#define EXINT_EVTEN_EVTEN10_Pos (10U) +#define EXINT_EVTEN_EVTEN10_Msk (0x1U << EXINT_EVTEN_EVTEN10_Pos) /*!< 0x00000400 */ +#define EXINT_EVTEN_EVTEN10 EXINT_EVTEN_EVTEN10_Msk /*!< Event enable or disable on line 10 */ +#define EXINT_EVTEN_EVTEN11_Pos (11U) +#define EXINT_EVTEN_EVTEN11_Msk (0x1U << EXINT_EVTEN_EVTEN11_Pos) /*!< 0x00000800 */ +#define EXINT_EVTEN_EVTEN11 EXINT_EVTEN_EVTEN11_Msk /*!< Event enable or disable on line 11 */ +#define EXINT_EVTEN_EVTEN12_Pos (12U) +#define EXINT_EVTEN_EVTEN12_Msk (0x1U << EXINT_EVTEN_EVTEN12_Pos) /*!< 0x00001000 */ +#define EXINT_EVTEN_EVTEN12 EXINT_EVTEN_EVTEN12_Msk /*!< Event enable or disable on line 12 */ +#define EXINT_EVTEN_EVTEN13_Pos (13U) +#define EXINT_EVTEN_EVTEN13_Msk (0x1U << EXINT_EVTEN_EVTEN13_Pos) /*!< 0x00002000 */ +#define EXINT_EVTEN_EVTEN13 EXINT_EVTEN_EVTEN13_Msk /*!< Event enable or disable on line 13 */ +#define EXINT_EVTEN_EVTEN14_Pos (14U) +#define EXINT_EVTEN_EVTEN14_Msk (0x1U << EXINT_EVTEN_EVTEN14_Pos) /*!< 0x00004000 */ +#define EXINT_EVTEN_EVTEN14 EXINT_EVTEN_EVTEN14_Msk /*!< Event enable or disable on line 14 */ +#define EXINT_EVTEN_EVTEN15_Pos (15U) +#define EXINT_EVTEN_EVTEN15_Msk (0x1U << EXINT_EVTEN_EVTEN15_Pos) /*!< 0x00008000 */ +#define EXINT_EVTEN_EVTEN15 EXINT_EVTEN_EVTEN15_Msk /*!< Event enable or disable on line 15 */ +#define EXINT_EVTEN_EVTEN16_Pos (16U) +#define EXINT_EVTEN_EVTEN16_Msk (0x1U << EXINT_EVTEN_EVTEN16_Pos) /*!< 0x00010000 */ +#define EXINT_EVTEN_EVTEN16 EXINT_EVTEN_EVTEN16_Msk /*!< Event enable or disable on line 16 */ +#define EXINT_EVTEN_EVTEN17_Pos (17U) +#define EXINT_EVTEN_EVTEN17_Msk (0x1U << EXINT_EVTEN_EVTEN17_Pos) /*!< 0x00020000 */ +#define EXINT_EVTEN_EVTEN17 EXINT_EVTEN_EVTEN17_Msk /*!< Event enable or disable on line 17 */ +#define EXINT_EVTEN_EVTEN18_Pos (18U) +#define EXINT_EVTEN_EVTEN18_Msk (0x1U << EXINT_EVTEN_EVTEN18_Pos) /*!< 0x00040000 */ +#define EXINT_EVTEN_EVTEN18 EXINT_EVTEN_EVTEN18_Msk /*!< Event enable or disable on line 18 */ +#define EXINT_EVTEN_EVTEN20_Pos (20U) +#define EXINT_EVTEN_EVTEN20_Msk (0x1U << EXINT_EVTEN_EVTEN20_Pos) /*!< 0x00100000 */ +#define EXINT_EVTEN_EVTEN20 EXINT_EVTEN_EVTEN20_Msk /*!< Event enable or disable on line 20 (F405 only) */ +#define EXINT_EVTEN_EVTEN21_Pos (21U) +#define EXINT_EVTEN_EVTEN21_Msk (0x1U << EXINT_EVTEN_EVTEN21_Pos) /*!< 0x00200000 */ +#define EXINT_EVTEN_EVTEN21 EXINT_EVTEN_EVTEN21_Msk /*!< Event enable or disable on line 21 */ +#define EXINT_EVTEN_EVTEN22_Pos (22U) +#define EXINT_EVTEN_EVTEN22_Msk (0x1U << EXINT_EVTEN_EVTEN22_Pos) /*!< 0x00400000 */ +#define EXINT_EVTEN_EVTEN22 EXINT_EVTEN_EVTEN22_Msk /*!< Event enable or disable on line 22 */ + +/* References Defines */ +#define EXINT_EVTEN_EVT0 EXINT_EVTEN_EVTEN0 +#define EXINT_EVTEN_EVT1 EXINT_EVTEN_EVTEN1 +#define EXINT_EVTEN_EVT2 EXINT_EVTEN_EVTEN2 +#define EXINT_EVTEN_EVT3 EXINT_EVTEN_EVTEN3 +#define EXINT_EVTEN_EVT4 EXINT_EVTEN_EVTEN4 +#define EXINT_EVTEN_EVT5 EXINT_EVTEN_EVTEN5 +#define EXINT_EVTEN_EVT6 EXINT_EVTEN_EVTEN6 +#define EXINT_EVTEN_EVT7 EXINT_EVTEN_EVTEN7 +#define EXINT_EVTEN_EVT8 EXINT_EVTEN_EVTEN8 +#define EXINT_EVTEN_EVT9 EXINT_EVTEN_EVTEN9 +#define EXINT_EVTEN_EVT10 EXINT_EVTEN_EVTEN10 +#define EXINT_EVTEN_EVT11 EXINT_EVTEN_EVTEN11 +#define EXINT_EVTEN_EVT12 EXINT_EVTEN_EVTEN12 +#define EXINT_EVTEN_EVT13 EXINT_EVTEN_EVTEN13 +#define EXINT_EVTEN_EVT14 EXINT_EVTEN_EVTEN14 +#define EXINT_EVTEN_EVT15 EXINT_EVTEN_EVTEN15 +#define EXINT_EVTEN_EVT16 EXINT_EVTEN_EVTEN16 +#define EXINT_EVTEN_EVT17 EXINT_EVTEN_EVTEN17 +#define EXINT_EVTEN_EVT18 EXINT_EVTEN_EVTEN18 +#define EXINT_EVTEN_EVT20 EXINT_EVTEN_EVTEN20 +#define EXINT_EVTEN_EVT21 EXINT_EVTEN_EVTEN21 +#define EXINT_EVTEN_EVT22 EXINT_EVTEN_EVTEN22 + +/**************** Bit definition for EXINT_POLCFG1 register *****************/ +#define EXINT_POLCFG1_RP0_Pos (0U) +#define EXINT_POLCFG1_RP0_Msk (0x1U << EXINT_POLCFG1_RP0_Pos) /*!< 0x00000001 */ +#define EXINT_POLCFG1_RP0 EXINT_POLCFG1_RP0_Msk /*!< Rising edge event configuration bit on line 0 */ +#define EXINT_POLCFG1_RP1_Pos (1U) +#define EXINT_POLCFG1_RP1_Msk (0x1U << EXINT_POLCFG1_RP1_Pos) /*!< 0x00000002 */ +#define EXINT_POLCFG1_RP1 EXINT_POLCFG1_RP1_Msk /*!< Rising edge event configuration bit on line 1 */ +#define EXINT_POLCFG1_RP2_Pos (2U) +#define EXINT_POLCFG1_RP2_Msk (0x1U << EXINT_POLCFG1_RP2_Pos) /*!< 0x00000004 */ +#define EXINT_POLCFG1_RP2 EXINT_POLCFG1_RP2_Msk /*!< Rising edge event configuration bit on line 2 */ +#define EXINT_POLCFG1_RP3_Pos (3U) +#define EXINT_POLCFG1_RP3_Msk (0x1U << EXINT_POLCFG1_RP3_Pos) /*!< 0x00000008 */ +#define EXINT_POLCFG1_RP3 EXINT_POLCFG1_RP3_Msk /*!< Rising edge event configuration bit on line 3 */ +#define EXINT_POLCFG1_RP4_Pos (4U) +#define EXINT_POLCFG1_RP4_Msk (0x1U << EXINT_POLCFG1_RP4_Pos) /*!< 0x00000010 */ +#define EXINT_POLCFG1_RP4 EXINT_POLCFG1_RP4_Msk /*!< Rising edge event configuration bit on line 4 */ +#define EXINT_POLCFG1_RP5_Pos (5U) +#define EXINT_POLCFG1_RP5_Msk (0x1U << EXINT_POLCFG1_RP5_Pos) /*!< 0x00000020 */ +#define EXINT_POLCFG1_RP5 EXINT_POLCFG1_RP5_Msk /*!< Rising edge event configuration bit on line 5 */ +#define EXINT_POLCFG1_RP6_Pos (6U) +#define EXINT_POLCFG1_RP6_Msk (0x1U << EXINT_POLCFG1_RP6_Pos) /*!< 0x00000040 */ +#define EXINT_POLCFG1_RP6 EXINT_POLCFG1_RP6_Msk /*!< Rising edge event configuration bit on line 6 */ +#define EXINT_POLCFG1_RP7_Pos (7U) +#define EXINT_POLCFG1_RP7_Msk (0x1U << EXINT_POLCFG1_RP7_Pos) /*!< 0x00000080 */ +#define EXINT_POLCFG1_RP7 EXINT_POLCFG1_RP7_Msk /*!< Rising edge event configuration bit on line 7 */ +#define EXINT_POLCFG1_RP8_Pos (8U) +#define EXINT_POLCFG1_RP8_Msk (0x1U << EXINT_POLCFG1_RP8_Pos) /*!< 0x00000100 */ +#define EXINT_POLCFG1_RP8 EXINT_POLCFG1_RP8_Msk /*!< Rising edge event configuration bit on line 8 */ +#define EXINT_POLCFG1_RP9_Pos (9U) +#define EXINT_POLCFG1_RP9_Msk (0x1U << EXINT_POLCFG1_RP9_Pos) /*!< 0x00000200 */ +#define EXINT_POLCFG1_RP9 EXINT_POLCFG1_RP9_Msk /*!< Rising edge event configuration bit on line 9 */ +#define EXINT_POLCFG1_RP10_Pos (10U) +#define EXINT_POLCFG1_RP10_Msk (0x1U << EXINT_POLCFG1_RP10_Pos) /*!< 0x00000400 */ +#define EXINT_POLCFG1_RP10 EXINT_POLCFG1_RP10_Msk /*!< Rising edge event configuration bit on line 10 */ +#define EXINT_POLCFG1_RP11_Pos (11U) +#define EXINT_POLCFG1_RP11_Msk (0x1U << EXINT_POLCFG1_RP11_Pos) /*!< 0x00000800 */ +#define EXINT_POLCFG1_RP11 EXINT_POLCFG1_RP11_Msk /*!< Rising edge event configuration bit on line 11 */ +#define EXINT_POLCFG1_RP12_Pos (12U) +#define EXINT_POLCFG1_RP12_Msk (0x1U << EXINT_POLCFG1_RP12_Pos) /*!< 0x00001000 */ +#define EXINT_POLCFG1_RP12 EXINT_POLCFG1_RP12_Msk /*!< Rising edge event configuration bit on line 12 */ +#define EXINT_POLCFG1_RP13_Pos (13U) +#define EXINT_POLCFG1_RP13_Msk (0x1U << EXINT_POLCFG1_RP13_Pos) /*!< 0x00002000 */ +#define EXINT_POLCFG1_RP13 EXINT_POLCFG1_RP13_Msk /*!< Rising edge event configuration bit on line 13 */ +#define EXINT_POLCFG1_RP14_Pos (14U) +#define EXINT_POLCFG1_RP14_Msk (0x1U << EXINT_POLCFG1_RP14_Pos) /*!< 0x00004000 */ +#define EXINT_POLCFG1_RP14 EXINT_POLCFG1_RP14_Msk /*!< Rising edge event configuration bit on line 14 */ +#define EXINT_POLCFG1_RP15_Pos (15U) +#define EXINT_POLCFG1_RP15_Msk (0x1U << EXINT_POLCFG1_RP15_Pos) /*!< 0x00008000 */ +#define EXINT_POLCFG1_RP15 EXINT_POLCFG1_RP15_Msk /*!< Rising edge event configuration bit on line 15 */ +#define EXINT_POLCFG1_RP16_Pos (16U) +#define EXINT_POLCFG1_RP16_Msk (0x1U << EXINT_POLCFG1_RP16_Pos) /*!< 0x00010000 */ +#define EXINT_POLCFG1_RP16 EXINT_POLCFG1_RP16_Msk /*!< Rising edge event configuration bit on line 16 */ +#define EXINT_POLCFG1_RP17_Pos (17U) +#define EXINT_POLCFG1_RP17_Msk (0x1U << EXINT_POLCFG1_RP17_Pos) /*!< 0x00020000 */ +#define EXINT_POLCFG1_RP17 EXINT_POLCFG1_RP17_Msk /*!< Rising edge event configuration bit on line 17 */ +#define EXINT_POLCFG1_RP18_Pos (18U) +#define EXINT_POLCFG1_RP18_Msk (0x1U << EXINT_POLCFG1_RP18_Pos) /*!< 0x00040000 */ +#define EXINT_POLCFG1_RP18 EXINT_POLCFG1_RP18_Msk /*!< Rising edge event configuration bit on line 18 */ +#define EXINT_POLCFG1_RP20_Pos (20U) +#define EXINT_POLCFG1_RP20_Msk (0x1U << EXINT_POLCFG1_RP20_Pos) /*!< 0x00100000 */ +#define EXINT_POLCFG1_RP20 EXINT_POLCFG1_RP20_Msk /*!< Rising edge event configuration bit on line 20 (F405 only) */ +#define EXINT_POLCFG1_RP21_Pos (21U) +#define EXINT_POLCFG1_RP21_Msk (0x1U << EXINT_POLCFG1_RP21_Pos) /*!< 0x00200000 */ +#define EXINT_POLCFG1_RP21 EXINT_POLCFG1_RP21_Msk /*!< Rising edge event configuration bit on line 21 */ +#define EXINT_POLCFG1_RP22_Pos (22U) +#define EXINT_POLCFG1_RP22_Msk (0x1U << EXINT_POLCFG1_RP22_Pos) /*!< 0x00400000 */ +#define EXINT_POLCFG1_RP22 EXINT_POLCFG1_RP22_Msk /*!< Rising edge event configuration bit on line 22 */ + +/* References Defines */ +#define EXINT_POLCFG1_POL0 EXINT_POLCFG1_RP0 +#define EXINT_POLCFG1_POL1 EXINT_POLCFG1_RP1 +#define EXINT_POLCFG1_POL2 EXINT_POLCFG1_RP2 +#define EXINT_POLCFG1_POL3 EXINT_POLCFG1_RP3 +#define EXINT_POLCFG1_POL4 EXINT_POLCFG1_RP4 +#define EXINT_POLCFG1_POL5 EXINT_POLCFG1_RP5 +#define EXINT_POLCFG1_POL6 EXINT_POLCFG1_RP6 +#define EXINT_POLCFG1_POL7 EXINT_POLCFG1_RP7 +#define EXINT_POLCFG1_POL8 EXINT_POLCFG1_RP8 +#define EXINT_POLCFG1_POL9 EXINT_POLCFG1_RP9 +#define EXINT_POLCFG1_POL10 EXINT_POLCFG1_RP10 +#define EXINT_POLCFG1_POL11 EXINT_POLCFG1_RP11 +#define EXINT_POLCFG1_POL12 EXINT_POLCFG1_RP12 +#define EXINT_POLCFG1_POL13 EXINT_POLCFG1_RP13 +#define EXINT_POLCFG1_POL14 EXINT_POLCFG1_RP14 +#define EXINT_POLCFG1_POL15 EXINT_POLCFG1_RP15 +#define EXINT_POLCFG1_POL16 EXINT_POLCFG1_RP16 +#define EXINT_POLCFG1_POL17 EXINT_POLCFG1_RP17 +#define EXINT_POLCFG1_POL18 EXINT_POLCFG1_RP18 +#define EXINT_POLCFG1_POL20 EXINT_POLCFG1_RP20 +#define EXINT_POLCFG1_POL21 EXINT_POLCFG1_RP21 +#define EXINT_POLCFG1_POL22 EXINT_POLCFG1_RP22 + +/**************** Bit definition for EXINT_POLCFG2 register *****************/ +#define EXINT_POLCFG2_FP0_Pos (0U) +#define EXINT_POLCFG2_FP0_Msk (0x1U << EXINT_POLCFG2_FP0_Pos) /*!< 0x00000001 */ +#define EXINT_POLCFG2_FP0 EXINT_POLCFG2_FP0_Msk /*!< Falling edge event configuration bit on line 0 */ +#define EXINT_POLCFG2_FP1_Pos (1U) +#define EXINT_POLCFG2_FP1_Msk (0x1U << EXINT_POLCFG2_FP1_Pos) /*!< 0x00000002 */ +#define EXINT_POLCFG2_FP1 EXINT_POLCFG2_FP1_Msk /*!< Falling edge event configuration bit on line 1 */ +#define EXINT_POLCFG2_FP2_Pos (2U) +#define EXINT_POLCFG2_FP2_Msk (0x1U << EXINT_POLCFG2_FP2_Pos) /*!< 0x00000004 */ +#define EXINT_POLCFG2_FP2 EXINT_POLCFG2_FP2_Msk /*!< Falling edge event configuration bit on line 2 */ +#define EXINT_POLCFG2_FP3_Pos (3U) +#define EXINT_POLCFG2_FP3_Msk (0x1U << EXINT_POLCFG2_FP3_Pos) /*!< 0x00000008 */ +#define EXINT_POLCFG2_FP3 EXINT_POLCFG2_FP3_Msk /*!< Falling edge event configuration bit on line 3 */ +#define EXINT_POLCFG2_FP4_Pos (4U) +#define EXINT_POLCFG2_FP4_Msk (0x1U << EXINT_POLCFG2_FP4_Pos) /*!< 0x00000010 */ +#define EXINT_POLCFG2_FP4 EXINT_POLCFG2_FP4_Msk /*!< Falling edge event configuration bit on line 4 */ +#define EXINT_POLCFG2_FP5_Pos (5U) +#define EXINT_POLCFG2_FP5_Msk (0x1U << EXINT_POLCFG2_FP5_Pos) /*!< 0x00000020 */ +#define EXINT_POLCFG2_FP5 EXINT_POLCFG2_FP5_Msk /*!< Falling edge event configuration bit on line 5 */ +#define EXINT_POLCFG2_FP6_Pos (6U) +#define EXINT_POLCFG2_FP6_Msk (0x1U << EXINT_POLCFG2_FP6_Pos) /*!< 0x00000040 */ +#define EXINT_POLCFG2_FP6 EXINT_POLCFG2_FP6_Msk /*!< Falling edge event configuration bit on line 6 */ +#define EXINT_POLCFG2_FP7_Pos (7U) +#define EXINT_POLCFG2_FP7_Msk (0x1U << EXINT_POLCFG2_FP7_Pos) /*!< 0x00000080 */ +#define EXINT_POLCFG2_FP7 EXINT_POLCFG2_FP7_Msk /*!< Falling edge event configuration bit on line 7 */ +#define EXINT_POLCFG2_FP8_Pos (8U) +#define EXINT_POLCFG2_FP8_Msk (0x1U << EXINT_POLCFG2_FP8_Pos) /*!< 0x00000100 */ +#define EXINT_POLCFG2_FP8 EXINT_POLCFG2_FP8_Msk /*!< Falling edge event configuration bit on line 8 */ +#define EXINT_POLCFG2_FP9_Pos (9U) +#define EXINT_POLCFG2_FP9_Msk (0x1U << EXINT_POLCFG2_FP9_Pos) /*!< 0x00000200 */ +#define EXINT_POLCFG2_FP9 EXINT_POLCFG2_FP9_Msk /*!< Falling edge event configuration bit on line 9 */ +#define EXINT_POLCFG2_FP10_Pos (10U) +#define EXINT_POLCFG2_FP10_Msk (0x1U << EXINT_POLCFG2_FP10_Pos) /*!< 0x00000400 */ +#define EXINT_POLCFG2_FP10 EXINT_POLCFG2_FP10_Msk /*!< Falling edge event configuration bit on line 10 */ +#define EXINT_POLCFG2_FP11_Pos (11U) +#define EXINT_POLCFG2_FP11_Msk (0x1U << EXINT_POLCFG2_FP11_Pos) /*!< 0x00000800 */ +#define EXINT_POLCFG2_FP11 EXINT_POLCFG2_FP11_Msk /*!< Falling edge event configuration bit on line 11 */ +#define EXINT_POLCFG2_FP12_Pos (12U) +#define EXINT_POLCFG2_FP12_Msk (0x1U << EXINT_POLCFG2_FP12_Pos) /*!< 0x00001000 */ +#define EXINT_POLCFG2_FP12 EXINT_POLCFG2_FP12_Msk /*!< Falling edge event configuration bit on line 12 */ +#define EXINT_POLCFG2_FP13_Pos (13U) +#define EXINT_POLCFG2_FP13_Msk (0x1U << EXINT_POLCFG2_FP13_Pos) /*!< 0x00002000 */ +#define EXINT_POLCFG2_FP13 EXINT_POLCFG2_FP13_Msk /*!< Falling edge event configuration bit on line 13 */ +#define EXINT_POLCFG2_FP14_Pos (14U) +#define EXINT_POLCFG2_FP14_Msk (0x1U << EXINT_POLCFG2_FP14_Pos) /*!< 0x00004000 */ +#define EXINT_POLCFG2_FP14 EXINT_POLCFG2_FP14_Msk /*!< Falling edge event configuration bit on line 14 */ +#define EXINT_POLCFG2_FP15_Pos (15U) +#define EXINT_POLCFG2_FP15_Msk (0x1U << EXINT_POLCFG2_FP15_Pos) /*!< 0x00008000 */ +#define EXINT_POLCFG2_FP15 EXINT_POLCFG2_FP15_Msk /*!< Falling edge event configuration bit on line 15 */ +#define EXINT_POLCFG2_FP16_Pos (16U) +#define EXINT_POLCFG2_FP16_Msk (0x1U << EXINT_POLCFG2_FP16_Pos) /*!< 0x00010000 */ +#define EXINT_POLCFG2_FP16 EXINT_POLCFG2_FP16_Msk /*!< Falling edge event configuration bit on line 16 */ +#define EXINT_POLCFG2_FP17_Pos (17U) +#define EXINT_POLCFG2_FP17_Msk (0x1U << EXINT_POLCFG2_FP17_Pos) /*!< 0x00020000 */ +#define EXINT_POLCFG2_FP17 EXINT_POLCFG2_FP17_Msk /*!< Falling edge event configuration bit on line 17 */ +#define EXINT_POLCFG2_FP18_Pos (18U) +#define EXINT_POLCFG2_FP18_Msk (0x1U << EXINT_POLCFG2_FP18_Pos) /*!< 0x00040000 */ +#define EXINT_POLCFG2_FP18 EXINT_POLCFG2_FP18_Msk /*!< Falling edge event configuration bit on line 18 */ +#define EXINT_POLCFG2_FP20_Pos (20U) +#define EXINT_POLCFG2_FP20_Msk (0x1U << EXINT_POLCFG2_FP20_Pos) /*!< 0x00100000 */ +#define EXINT_POLCFG2_FP20 EXINT_POLCFG2_FP20_Msk /*!< Falling edge event configuration bit on line 20 (F405 only) */ +#define EXINT_POLCFG2_FP21_Pos (21U) +#define EXINT_POLCFG2_FP21_Msk (0x1U << EXINT_POLCFG2_FP21_Pos) /*!< 0x00200000 */ +#define EXINT_POLCFG2_FP21 EXINT_POLCFG2_FP21_Msk /*!< Falling edge event configuration bit on line 21 */ +#define EXINT_POLCFG2_FP22_Pos (22U) +#define EXINT_POLCFG2_FP22_Msk (0x1U << EXINT_POLCFG2_FP22_Pos) /*!< 0x00400000 */ +#define EXINT_POLCFG2_FP22 EXINT_POLCFG2_FP22_Msk /*!< Falling edge event configuration bit on line 22 */ + +/* References Defines */ +#define EXINT_POLCFG2_POL0 EXINT_POLCFG2_FP0 +#define EXINT_POLCFG2_POL1 EXINT_POLCFG2_FP1 +#define EXINT_POLCFG2_POL2 EXINT_POLCFG2_FP2 +#define EXINT_POLCFG2_POL3 EXINT_POLCFG2_FP3 +#define EXINT_POLCFG2_POL4 EXINT_POLCFG2_FP4 +#define EXINT_POLCFG2_POL5 EXINT_POLCFG2_FP5 +#define EXINT_POLCFG2_POL6 EXINT_POLCFG2_FP6 +#define EXINT_POLCFG2_POL7 EXINT_POLCFG2_FP7 +#define EXINT_POLCFG2_POL8 EXINT_POLCFG2_FP8 +#define EXINT_POLCFG2_POL9 EXINT_POLCFG2_FP9 +#define EXINT_POLCFG2_POL10 EXINT_POLCFG2_FP10 +#define EXINT_POLCFG2_POL11 EXINT_POLCFG2_FP11 +#define EXINT_POLCFG2_POL12 EXINT_POLCFG2_FP12 +#define EXINT_POLCFG2_POL13 EXINT_POLCFG2_FP13 +#define EXINT_POLCFG2_POL14 EXINT_POLCFG2_FP14 +#define EXINT_POLCFG2_POL15 EXINT_POLCFG2_FP15 +#define EXINT_POLCFG2_POL16 EXINT_POLCFG2_FP16 +#define EXINT_POLCFG2_POL17 EXINT_POLCFG2_FP17 +#define EXINT_POLCFG2_POL18 EXINT_POLCFG2_FP18 +#define EXINT_POLCFG2_POL20 EXINT_POLCFG2_FP20 +#define EXINT_POLCFG2_POL21 EXINT_POLCFG2_FP21 +#define EXINT_POLCFG2_POL22 EXINT_POLCFG2_FP22 + +/***************** Bit definition for EXINT_SWTRG register ******************/ +#define EXINT_SWTRG_SWT0_Pos (0U) +#define EXINT_SWTRG_SWT0_Msk (0x1U << EXINT_SWTRG_SWT0_Pos) /*!< 0x00000001 */ +#define EXINT_SWTRG_SWT0 EXINT_SWTRG_SWT0_Msk /*!< Software trigger on line 0 */ +#define EXINT_SWTRG_SWT1_Pos (1U) +#define EXINT_SWTRG_SWT1_Msk (0x1U << EXINT_SWTRG_SWT1_Pos) /*!< 0x00000002 */ +#define EXINT_SWTRG_SWT1 EXINT_SWTRG_SWT1_Msk /*!< Software trigger on line 1 */ +#define EXINT_SWTRG_SWT2_Pos (2U) +#define EXINT_SWTRG_SWT2_Msk (0x1U << EXINT_SWTRG_SWT2_Pos) /*!< 0x00000004 */ +#define EXINT_SWTRG_SWT2 EXINT_SWTRG_SWT2_Msk /*!< Software trigger on line 2 */ +#define EXINT_SWTRG_SWT3_Pos (3U) +#define EXINT_SWTRG_SWT3_Msk (0x1U << EXINT_SWTRG_SWT3_Pos) /*!< 0x00000008 */ +#define EXINT_SWTRG_SWT3 EXINT_SWTRG_SWT3_Msk /*!< Software trigger on line 3 */ +#define EXINT_SWTRG_SWT4_Pos (4U) +#define EXINT_SWTRG_SWT4_Msk (0x1U << EXINT_SWTRG_SWT4_Pos) /*!< 0x00000010 */ +#define EXINT_SWTRG_SWT4 EXINT_SWTRG_SWT4_Msk /*!< Software trigger on line 4 */ +#define EXINT_SWTRG_SWT5_Pos (5U) +#define EXINT_SWTRG_SWT5_Msk (0x1U << EXINT_SWTRG_SWT5_Pos) /*!< 0x00000020 */ +#define EXINT_SWTRG_SWT5 EXINT_SWTRG_SWT5_Msk /*!< Software trigger on line 5 */ +#define EXINT_SWTRG_SWT6_Pos (6U) +#define EXINT_SWTRG_SWT6_Msk (0x1U << EXINT_SWTRG_SWT6_Pos) /*!< 0x00000040 */ +#define EXINT_SWTRG_SWT6 EXINT_SWTRG_SWT6_Msk /*!< Software trigger on line 6 */ +#define EXINT_SWTRG_SWT7_Pos (7U) +#define EXINT_SWTRG_SWT7_Msk (0x1U << EXINT_SWTRG_SWT7_Pos) /*!< 0x00000080 */ +#define EXINT_SWTRG_SWT7 EXINT_SWTRG_SWT7_Msk /*!< Software trigger on line 7 */ +#define EXINT_SWTRG_SWT8_Pos (8U) +#define EXINT_SWTRG_SWT8_Msk (0x1U << EXINT_SWTRG_SWT8_Pos) /*!< 0x00000100 */ +#define EXINT_SWTRG_SWT8 EXINT_SWTRG_SWT8_Msk /*!< Software trigger on line 8 */ +#define EXINT_SWTRG_SWT9_Pos (9U) +#define EXINT_SWTRG_SWT9_Msk (0x1U << EXINT_SWTRG_SWT9_Pos) /*!< 0x00000200 */ +#define EXINT_SWTRG_SWT9 EXINT_SWTRG_SWT9_Msk /*!< Software trigger on line 9 */ +#define EXINT_SWTRG_SWT10_Pos (10U) +#define EXINT_SWTRG_SWT10_Msk (0x1U << EXINT_SWTRG_SWT10_Pos) /*!< 0x00000400 */ +#define EXINT_SWTRG_SWT10 EXINT_SWTRG_SWT10_Msk /*!< Software trigger on line 10 */ +#define EXINT_SWTRG_SWT11_Pos (11U) +#define EXINT_SWTRG_SWT11_Msk (0x1U << EXINT_SWTRG_SWT11_Pos) /*!< 0x00000800 */ +#define EXINT_SWTRG_SWT11 EXINT_SWTRG_SWT11_Msk /*!< Software trigger on line 11 */ +#define EXINT_SWTRG_SWT12_Pos (12U) +#define EXINT_SWTRG_SWT12_Msk (0x1U << EXINT_SWTRG_SWT12_Pos) /*!< 0x00001000 */ +#define EXINT_SWTRG_SWT12 EXINT_SWTRG_SWT12_Msk /*!< Software trigger on line 12 */ +#define EXINT_SWTRG_SWT13_Pos (13U) +#define EXINT_SWTRG_SWT13_Msk (0x1U << EXINT_SWTRG_SWT13_Pos) /*!< 0x00002000 */ +#define EXINT_SWTRG_SWT13 EXINT_SWTRG_SWT13_Msk /*!< Software trigger on line 13 */ +#define EXINT_SWTRG_SWT14_Pos (14U) +#define EXINT_SWTRG_SWT14_Msk (0x1U << EXINT_SWTRG_SWT14_Pos) /*!< 0x00004000 */ +#define EXINT_SWTRG_SWT14 EXINT_SWTRG_SWT14_Msk /*!< Software trigger on line 14 */ +#define EXINT_SWTRG_SWT15_Pos (15U) +#define EXINT_SWTRG_SWT15_Msk (0x1U << EXINT_SWTRG_SWT15_Pos) /*!< 0x00008000 */ +#define EXINT_SWTRG_SWT15 EXINT_SWTRG_SWT15_Msk /*!< Software trigger on line 15 */ +#define EXINT_SWTRG_SWT16_Pos (16U) +#define EXINT_SWTRG_SWT16_Msk (0x1U << EXINT_SWTRG_SWT16_Pos) /*!< 0x00010000 */ +#define EXINT_SWTRG_SWT16 EXINT_SWTRG_SWT16_Msk /*!< Software trigger on line 16 */ +#define EXINT_SWTRG_SWT17_Pos (17U) +#define EXINT_SWTRG_SWT17_Msk (0x1U << EXINT_SWTRG_SWT17_Pos) /*!< 0x00020000 */ +#define EXINT_SWTRG_SWT17 EXINT_SWTRG_SWT17_Msk /*!< Software trigger on line 17 */ +#define EXINT_SWTRG_SWT18_Pos (18U) +#define EXINT_SWTRG_SWT18_Msk (0x1U << EXINT_SWTRG_SWT18_Pos) /*!< 0x00040000 */ +#define EXINT_SWTRG_SWT18 EXINT_SWTRG_SWT18_Msk /*!< Software trigger on line 18 */ +#define EXINT_SWTRG_SWT20_Pos (20U) +#define EXINT_SWTRG_SWT20_Msk (0x1U << EXINT_SWTRG_SWT20_Pos) /*!< 0x00100000 */ +#define EXINT_SWTRG_SWT20 EXINT_SWTRG_SWT20_Msk /*!< Software trigger on line 20 (F405 only) */ +#define EXINT_SWTRG_SWT21_Pos (21U) +#define EXINT_SWTRG_SWT21_Msk (0x1U << EXINT_SWTRG_SWT21_Pos) /*!< 0x00200000 */ +#define EXINT_SWTRG_SWT21 EXINT_SWTRG_SWT21_Msk /*!< Software trigger on line 21 */ +#define EXINT_SWTRG_SWT22_Pos (22U) +#define EXINT_SWTRG_SWT22_Msk (0x1U << EXINT_SWTRG_SWT22_Pos) /*!< 0x00400000 */ +#define EXINT_SWTRG_SWT22 EXINT_SWTRG_SWT22_Msk /*!< Software trigger on line 22 */ + +/* References Defines */ +#define EXINT_SWTRG_SW0 EXINT_SWTRG_SWT0 +#define EXINT_SWTRG_SW1 EXINT_SWTRG_SWT1 +#define EXINT_SWTRG_SW2 EXINT_SWTRG_SWT2 +#define EXINT_SWTRG_SW3 EXINT_SWTRG_SWT3 +#define EXINT_SWTRG_SW4 EXINT_SWTRG_SWT4 +#define EXINT_SWTRG_SW5 EXINT_SWTRG_SWT5 +#define EXINT_SWTRG_SW6 EXINT_SWTRG_SWT6 +#define EXINT_SWTRG_SW7 EXINT_SWTRG_SWT7 +#define EXINT_SWTRG_SW8 EXINT_SWTRG_SWT8 +#define EXINT_SWTRG_SW9 EXINT_SWTRG_SWT9 +#define EXINT_SWTRG_SW10 EXINT_SWTRG_SWT10 +#define EXINT_SWTRG_SW11 EXINT_SWTRG_SWT11 +#define EXINT_SWTRG_SW12 EXINT_SWTRG_SWT12 +#define EXINT_SWTRG_SW13 EXINT_SWTRG_SWT13 +#define EXINT_SWTRG_SW14 EXINT_SWTRG_SWT14 +#define EXINT_SWTRG_SW15 EXINT_SWTRG_SWT15 +#define EXINT_SWTRG_SW16 EXINT_SWTRG_SWT16 +#define EXINT_SWTRG_SW17 EXINT_SWTRG_SWT17 +#define EXINT_SWTRG_SW18 EXINT_SWTRG_SWT18 +#define EXINT_SWTRG_SW20 EXINT_SWTRG_SWT20 +#define EXINT_SWTRG_SW21 EXINT_SWTRG_SWT21 +#define EXINT_SWTRG_SW22 EXINT_SWTRG_SWT22 + +/***************** Bit definition for EXINT_INTSTS register *****************/ +#define EXINT_INTSTS_LINE0_Pos (0U) +#define EXINT_INTSTS_LINE0_Msk (0x1U << EXINT_INTSTS_LINE0_Pos) /*!< 0x00000001 */ +#define EXINT_INTSTS_LINE0 EXINT_INTSTS_LINE0_Msk /*!< Status bit for line 0 */ +#define EXINT_INTSTS_LINE1_Pos (1U) +#define EXINT_INTSTS_LINE1_Msk (0x1U << EXINT_INTSTS_LINE1_Pos) /*!< 0x00000002 */ +#define EXINT_INTSTS_LINE1 EXINT_INTSTS_LINE1_Msk /*!< Status bit for line 1 */ +#define EXINT_INTSTS_LINE2_Pos (2U) +#define EXINT_INTSTS_LINE2_Msk (0x1U << EXINT_INTSTS_LINE2_Pos) /*!< 0x00000004 */ +#define EXINT_INTSTS_LINE2 EXINT_INTSTS_LINE2_Msk /*!< Status bit for line 2 */ +#define EXINT_INTSTS_LINE3_Pos (3U) +#define EXINT_INTSTS_LINE3_Msk (0x1U << EXINT_INTSTS_LINE3_Pos) /*!< 0x00000008 */ +#define EXINT_INTSTS_LINE3 EXINT_INTSTS_LINE3_Msk /*!< Status bit for line 3 */ +#define EXINT_INTSTS_LINE4_Pos (4U) +#define EXINT_INTSTS_LINE4_Msk (0x1U << EXINT_INTSTS_LINE4_Pos) /*!< 0x00000010 */ +#define EXINT_INTSTS_LINE4 EXINT_INTSTS_LINE4_Msk /*!< Status bit for line 4 */ +#define EXINT_INTSTS_LINE5_Pos (5U) +#define EXINT_INTSTS_LINE5_Msk (0x1U << EXINT_INTSTS_LINE5_Pos) /*!< 0x00000020 */ +#define EXINT_INTSTS_LINE5 EXINT_INTSTS_LINE5_Msk /*!< Status bit for line 5 */ +#define EXINT_INTSTS_LINE6_Pos (6U) +#define EXINT_INTSTS_LINE6_Msk (0x1U << EXINT_INTSTS_LINE6_Pos) /*!< 0x00000040 */ +#define EXINT_INTSTS_LINE6 EXINT_INTSTS_LINE6_Msk /*!< Status bit for line 6 */ +#define EXINT_INTSTS_LINE7_Pos (7U) +#define EXINT_INTSTS_LINE7_Msk (0x1U << EXINT_INTSTS_LINE7_Pos) /*!< 0x00000080 */ +#define EXINT_INTSTS_LINE7 EXINT_INTSTS_LINE7_Msk /*!< Status bit for line 7 */ +#define EXINT_INTSTS_LINE8_Pos (8U) +#define EXINT_INTSTS_LINE8_Msk (0x1U << EXINT_INTSTS_LINE8_Pos) /*!< 0x00000100 */ +#define EXINT_INTSTS_LINE8 EXINT_INTSTS_LINE8_Msk /*!< Status bit for line 8 */ +#define EXINT_INTSTS_LINE9_Pos (9U) +#define EXINT_INTSTS_LINE9_Msk (0x1U << EXINT_INTSTS_LINE9_Pos) /*!< 0x00000200 */ +#define EXINT_INTSTS_LINE9 EXINT_INTSTS_LINE9_Msk /*!< Status bit for line 9 */ +#define EXINT_INTSTS_LINE10_Pos (10U) +#define EXINT_INTSTS_LINE10_Msk (0x1U << EXINT_INTSTS_LINE10_Pos) /*!< 0x00000400 */ +#define EXINT_INTSTS_LINE10 EXINT_INTSTS_LINE10_Msk /*!< Status bit for line 10 */ +#define EXINT_INTSTS_LINE11_Pos (11U) +#define EXINT_INTSTS_LINE11_Msk (0x1U << EXINT_INTSTS_LINE11_Pos) /*!< 0x00000800 */ +#define EXINT_INTSTS_LINE11 EXINT_INTSTS_LINE11_Msk /*!< Status bit for line 11 */ +#define EXINT_INTSTS_LINE12_Pos (12U) +#define EXINT_INTSTS_LINE12_Msk (0x1U << EXINT_INTSTS_LINE12_Pos) /*!< 0x00001000 */ +#define EXINT_INTSTS_LINE12 EXINT_INTSTS_LINE12_Msk /*!< Status bit for line 12 */ +#define EXINT_INTSTS_LINE13_Pos (13U) +#define EXINT_INTSTS_LINE13_Msk (0x1U << EXINT_INTSTS_LINE13_Pos) /*!< 0x00002000 */ +#define EXINT_INTSTS_LINE13 EXINT_INTSTS_LINE13_Msk /*!< Status bit for line 13 */ +#define EXINT_INTSTS_LINE14_Pos (14U) +#define EXINT_INTSTS_LINE14_Msk (0x1U << EXINT_INTSTS_LINE14_Pos) /*!< 0x00004000 */ +#define EXINT_INTSTS_LINE14 EXINT_INTSTS_LINE14_Msk /*!< Status bit for line 14 */ +#define EXINT_INTSTS_LINE15_Pos (15U) +#define EXINT_INTSTS_LINE15_Msk (0x1U << EXINT_INTSTS_LINE15_Pos) /*!< 0x00008000 */ +#define EXINT_INTSTS_LINE15 EXINT_INTSTS_LINE15_Msk /*!< Status bit for line 15 */ +#define EXINT_INTSTS_LINE16_Pos (16U) +#define EXINT_INTSTS_LINE16_Msk (0x1U << EXINT_INTSTS_LINE16_Pos) /*!< 0x00010000 */ +#define EXINT_INTSTS_LINE16 EXINT_INTSTS_LINE16_Msk /*!< Status bit for line 16 */ +#define EXINT_INTSTS_LINE17_Pos (17U) +#define EXINT_INTSTS_LINE17_Msk (0x1U << EXINT_INTSTS_LINE17_Pos) /*!< 0x00020000 */ +#define EXINT_INTSTS_LINE17 EXINT_INTSTS_LINE17_Msk /*!< Status bit for line 17 */ +#define EXINT_INTSTS_LINE18_Pos (18U) +#define EXINT_INTSTS_LINE18_Msk (0x1U << EXINT_INTSTS_LINE18_Pos) /*!< 0x00040000 */ +#define EXINT_INTSTS_LINE18 EXINT_INTSTS_LINE18_Msk /*!< Status bit for line 18 */ +#define EXINT_INTSTS_LINE20_Pos (20U) +#define EXINT_INTSTS_LINE20_Msk (0x1U << EXINT_INTSTS_LINE20_Pos) /*!< 0x00100000 */ +#define EXINT_INTSTS_LINE20 EXINT_INTSTS_LINE20_Msk /*!< Status bit for line 20 (F405 only) */ +#define EXINT_INTSTS_LINE21_Pos (21U) +#define EXINT_INTSTS_LINE21_Msk (0x1U << EXINT_INTSTS_LINE21_Pos) /*!< 0x00200000 */ +#define EXINT_INTSTS_LINE21 EXINT_INTSTS_LINE21_Msk /*!< Status bit for line 21 */ +#define EXINT_INTSTS_LINE22_Pos (22U) +#define EXINT_INTSTS_LINE22_Msk (0x1U << EXINT_INTSTS_LINE22_Pos) /*!< 0x00400000 */ +#define EXINT_INTSTS_LINE22 EXINT_INTSTS_LINE22_Msk /*!< Status bit for line 22 */ + +/* References Defines */ +#define EXINT_INTSTS_INT0 EXINT_INTSTS_LINE0 +#define EXINT_INTSTS_INT1 EXINT_INTSTS_LINE1 +#define EXINT_INTSTS_INT2 EXINT_INTSTS_LINE2 +#define EXINT_INTSTS_INT3 EXINT_INTSTS_LINE3 +#define EXINT_INTSTS_INT4 EXINT_INTSTS_LINE4 +#define EXINT_INTSTS_INT5 EXINT_INTSTS_LINE5 +#define EXINT_INTSTS_INT6 EXINT_INTSTS_LINE6 +#define EXINT_INTSTS_INT7 EXINT_INTSTS_LINE7 +#define EXINT_INTSTS_INT8 EXINT_INTSTS_LINE8 +#define EXINT_INTSTS_INT9 EXINT_INTSTS_LINE9 +#define EXINT_INTSTS_INT10 EXINT_INTSTS_LINE10 +#define EXINT_INTSTS_INT11 EXINT_INTSTS_LINE11 +#define EXINT_INTSTS_INT12 EXINT_INTSTS_LINE12 +#define EXINT_INTSTS_INT13 EXINT_INTSTS_LINE13 +#define EXINT_INTSTS_INT14 EXINT_INTSTS_LINE14 +#define EXINT_INTSTS_INT15 EXINT_INTSTS_LINE15 +#define EXINT_INTSTS_INT16 EXINT_INTSTS_LINE16 +#define EXINT_INTSTS_INT17 EXINT_INTSTS_LINE17 +#define EXINT_INTSTS_INT18 EXINT_INTSTS_LINE18 +#define EXINT_INTSTS_INT20 EXINT_INTSTS_LINE20 +#define EXINT_INTSTS_INT21 EXINT_INTSTS_LINE21 +#define EXINT_INTSTS_INT22 EXINT_INTSTS_LINE22 + +/******************************************************************************/ +/* */ +/* DMA controller (DMA) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for DMA_STS register ********************/ +#define DMA_STS_GF1_Pos (0U) +#define DMA_STS_GF1_Msk (0x1U << DMA_STS_GF1_Pos) /*!< 0x00000001 */ +#define DMA_STS_GF1 DMA_STS_GF1_Msk /*!< Channel 1 global event flag */ +#define DMA_STS_FDTF1_Pos (1U) +#define DMA_STS_FDTF1_Msk (0x1U << DMA_STS_FDTF1_Pos) /*!< 0x00000002 */ +#define DMA_STS_FDTF1 DMA_STS_FDTF1_Msk /*!< Channel 1 transfer complete event flag */ +#define DMA_STS_HDTF1_Pos (2U) +#define DMA_STS_HDTF1_Msk (0x1U << DMA_STS_HDTF1_Pos) /*!< 0x00000004 */ +#define DMA_STS_HDTF1 DMA_STS_HDTF1_Msk /*!< Channel 1 half transfer event flag */ +#define DMA_STS_DTERRF1_Pos (3U) +#define DMA_STS_DTERRF1_Msk (0x1U << DMA_STS_DTERRF1_Pos) /*!< 0x00000008 */ +#define DMA_STS_DTERRF1 DMA_STS_DTERRF1_Msk /*!< Channel 1 transfer error event flag */ +#define DMA_STS_GF2_Pos (4U) +#define DMA_STS_GF2_Msk (0x1U << DMA_STS_GF2_Pos) /*!< 0x00000010 */ +#define DMA_STS_GF2 DMA_STS_GF2_Msk /*!< Channel 2 global event flag */ +#define DMA_STS_FDTF2_Pos (5U) +#define DMA_STS_FDTF2_Msk (0x1U << DMA_STS_FDTF2_Pos) /*!< 0x00000020 */ +#define DMA_STS_FDTF2 DMA_STS_FDTF2_Msk /*!< Channel 2 transfer complete event flag */ +#define DMA_STS_HDTF2_Pos (6U) +#define DMA_STS_HDTF2_Msk (0x1U << DMA_STS_HDTF2_Pos) /*!< 0x00000040 */ +#define DMA_STS_HDTF2 DMA_STS_HDTF2_Msk /*!< Channel 2 half transfer event flag */ +#define DMA_STS_DTERRF2_Pos (7U) +#define DMA_STS_DTERRF2_Msk (0x1U << DMA_STS_DTERRF2_Pos) /*!< 0x00000080 */ +#define DMA_STS_DTERRF2 DMA_STS_DTERRF2_Msk /*!< Channel 2 transfer error event flag */ +#define DMA_STS_GF3_Pos (8U) +#define DMA_STS_GF3_Msk (0x1U << DMA_STS_GF3_Pos) /*!< 0x00000100 */ +#define DMA_STS_GF3 DMA_STS_GF3_Msk /*!< Channel 3 global event flag */ +#define DMA_STS_FDTF3_Pos (9U) +#define DMA_STS_FDTF3_Msk (0x1U << DMA_STS_FDTF3_Pos) /*!< 0x00000200 */ +#define DMA_STS_FDTF3 DMA_STS_FDTF3_Msk /*!< Channel 3 transfer complete event flag */ +#define DMA_STS_HDTF3_Pos (10U) +#define DMA_STS_HDTF3_Msk (0x1U << DMA_STS_HDTF3_Pos) /*!< 0x00000400 */ +#define DMA_STS_HDTF3 DMA_STS_HDTF3_Msk /*!< Channel 3 half transfer event flag */ +#define DMA_STS_DTERRF3_Pos (11U) +#define DMA_STS_DTERRF3_Msk (0x1U << DMA_STS_DTERRF3_Pos) /*!< 0x00000800 */ +#define DMA_STS_DTERRF3 DMA_STS_DTERRF3_Msk /*!< Channel 3 transfer error event flag */ +#define DMA_STS_GF4_Pos (12U) +#define DMA_STS_GF4_Msk (0x1U << DMA_STS_GF4_Pos) /*!< 0x00001000 */ +#define DMA_STS_GF4 DMA_STS_GF4_Msk /*!< Channel 4 global event flag */ +#define DMA_STS_FDTF4_Pos (13U) +#define DMA_STS_FDTF4_Msk (0x1U << DMA_STS_FDTF4_Pos) /*!< 0x00002000 */ +#define DMA_STS_FDTF4 DMA_STS_FDTF4_Msk /*!< Channel 4 transfer complete event flag */ +#define DMA_STS_HDTF4_Pos (14U) +#define DMA_STS_HDTF4_Msk (0x1U << DMA_STS_HDTF4_Pos) /*!< 0x00004000 */ +#define DMA_STS_HDTF4 DMA_STS_HDTF4_Msk /*!< Channel 4 half transfer event flag */ +#define DMA_STS_DTERRF4_Pos (15U) +#define DMA_STS_DTERRF4_Msk (0x1U << DMA_STS_DTERRF4_Pos) /*!< 0x00008000 */ +#define DMA_STS_DTERRF4 DMA_STS_DTERRF4_Msk /*!< Channel 4 transfer error event flag */ +#define DMA_STS_GF5_Pos (16U) +#define DMA_STS_GF5_Msk (0x1U << DMA_STS_GF5_Pos) /*!< 0x00010000 */ +#define DMA_STS_GF5 DMA_STS_GF5_Msk /*!< Channel 5 global event flag */ +#define DMA_STS_FDTF5_Pos (17U) +#define DMA_STS_FDTF5_Msk (0x1U << DMA_STS_FDTF5_Pos) /*!< 0x00020000 */ +#define DMA_STS_FDTF5 DMA_STS_FDTF5_Msk /*!< Channel 5 transfer complete event flag */ +#define DMA_STS_HDTF5_Pos (18U) +#define DMA_STS_HDTF5_Msk (0x1U << DMA_STS_HDTF5_Pos) /*!< 0x00040000 */ +#define DMA_STS_HDTF5 DMA_STS_HDTF5_Msk /*!< Channel 5 half transfer event flag */ +#define DMA_STS_DTERRF5_Pos (19U) +#define DMA_STS_DTERRF5_Msk (0x1U << DMA_STS_DTERRF5_Pos) /*!< 0x00080000 */ +#define DMA_STS_DTERRF5 DMA_STS_DTERRF5_Msk /*!< Channel 5 transfer error event flag */ +#define DMA_STS_GF6_Pos (20U) +#define DMA_STS_GF6_Msk (0x1U << DMA_STS_GF6_Pos) /*!< 0x00100000 */ +#define DMA_STS_GF6 DMA_STS_GF6_Msk /*!< Channel 6 global event flag */ +#define DMA_STS_FDTF6_Pos (21U) +#define DMA_STS_FDTF6_Msk (0x1U << DMA_STS_FDTF6_Pos) /*!< 0x00200000 */ +#define DMA_STS_FDTF6 DMA_STS_FDTF6_Msk /*!< Channel 6 transfer complete event flag */ +#define DMA_STS_HDTF6_Pos (22U) +#define DMA_STS_HDTF6_Msk (0x1U << DMA_STS_HDTF6_Pos) /*!< 0x00400000 */ +#define DMA_STS_HDTF6 DMA_STS_HDTF6_Msk /*!< Channel 6 half transfer event flag */ +#define DMA_STS_DTERRF6_Pos (23U) +#define DMA_STS_DTERRF6_Msk (0x1U << DMA_STS_DTERRF6_Pos) /*!< 0x00800000 */ +#define DMA_STS_DTERRF6 DMA_STS_DTERRF6_Msk /*!< Channel 6 transfer error event flag */ +#define DMA_STS_GF7_Pos (24U) +#define DMA_STS_GF7_Msk (0x1U << DMA_STS_GF7_Pos) /*!< 0x01000000 */ +#define DMA_STS_GF7 DMA_STS_GF7_Msk /*!< Channel 7 global event flag */ +#define DMA_STS_FDTF7_Pos (25U) +#define DMA_STS_FDTF7_Msk (0x1U << DMA_STS_FDTF7_Pos) /*!< 0x02000000 */ +#define DMA_STS_FDTF7 DMA_STS_FDTF7_Msk /*!< Channel 7 transfer complete event flag */ +#define DMA_STS_HDTF7_Pos (26U) +#define DMA_STS_HDTF7_Msk (0x1U << DMA_STS_HDTF7_Pos) /*!< 0x04000000 */ +#define DMA_STS_HDTF7 DMA_STS_HDTF7_Msk /*!< Channel 7 half transfer event flag */ +#define DMA_STS_DTERRF7_Pos (27U) +#define DMA_STS_DTERRF7_Msk (0x1U << DMA_STS_DTERRF7_Pos) /*!< 0x08000000 */ +#define DMA_STS_DTERRF7 DMA_STS_DTERRF7_Msk /*!< Channel 7 transfer error event flag */ + +/******************* Bit definition for DMA_CLR register ********************/ +#define DMA_CLR_GFC1_Pos (0U) +#define DMA_CLR_GFC1_Msk (0x1U << DMA_CLR_GFC1_Pos) /*!< 0x00000001 */ +#define DMA_CLR_GFC1 DMA_CLR_GFC1_Msk /*!< Channel 1 global interrupt flag clear */ +#define DMA_CLR_FDTFC1_Pos (1U) +#define DMA_CLR_FDTFC1_Msk (0x1U << DMA_CLR_FDTFC1_Pos) /*!< 0x00000002 */ +#define DMA_CLR_FDTFC1 DMA_CLR_FDTFC1_Msk /*!< Channel 1 transfer complete flag clear */ +#define DMA_CLR_HDTFC1_Pos (2U) +#define DMA_CLR_HDTFC1_Msk (0x1U << DMA_CLR_HDTFC1_Pos) /*!< 0x00000004 */ +#define DMA_CLR_HDTFC1 DMA_CLR_HDTFC1_Msk /*!< Channel 1 half transfer flag clear */ +#define DMA_CLR_DTERRFC1_Pos (3U) +#define DMA_CLR_DTERRFC1_Msk (0x1U << DMA_CLR_DTERRFC1_Pos) /*!< 0x00000008 */ +#define DMA_CLR_DTERRFC1 DMA_CLR_DTERRFC1_Msk /*!< Channel 1 data transfer error flag clear */ +#define DMA_CLR_GFC2_Pos (4U) +#define DMA_CLR_GFC2_Msk (0x1U << DMA_CLR_GFC2_Pos) /*!< 0x00000010 */ +#define DMA_CLR_GFC2 DMA_CLR_GFC2_Msk /*!< Channel 2 global interrupt flag clear */ +#define DMA_CLR_FDTFC2_Pos (5U) +#define DMA_CLR_FDTFC2_Msk (0x1U << DMA_CLR_FDTFC2_Pos) /*!< 0x00000020 */ +#define DMA_CLR_FDTFC2 DMA_CLR_FDTFC2_Msk /*!< Channel 2 transfer complete flag clear */ +#define DMA_CLR_HDTFC2_Pos (6U) +#define DMA_CLR_HDTFC2_Msk (0x1U << DMA_CLR_HDTFC2_Pos) /*!< 0x00000040 */ +#define DMA_CLR_HDTFC2 DMA_CLR_HDTFC2_Msk /*!< Channel 2 half transfer flag clear */ +#define DMA_CLR_DTERRFC2_Pos (7U) +#define DMA_CLR_DTERRFC2_Msk (0x1U << DMA_CLR_DTERRFC2_Pos) /*!< 0x00000080 */ +#define DMA_CLR_DTERRFC2 DMA_CLR_DTERRFC2_Msk /*!< Channel 2 data transfer error flag clear */ +#define DMA_CLR_GFC3_Pos (8U) +#define DMA_CLR_GFC3_Msk (0x1U << DMA_CLR_GFC3_Pos) /*!< 0x00000100 */ +#define DMA_CLR_GFC3 DMA_CLR_GFC3_Msk /*!< Channel 3 global interrupt flag clear */ +#define DMA_CLR_FDTFC3_Pos (9U) +#define DMA_CLR_FDTFC3_Msk (0x1U << DMA_CLR_FDTFC3_Pos) /*!< 0x00000200 */ +#define DMA_CLR_FDTFC3 DMA_CLR_FDTFC3_Msk /*!< Channel 3 transfer complete flag clear */ +#define DMA_CLR_HDTFC3_Pos (10U) +#define DMA_CLR_HDTFC3_Msk (0x1U << DMA_CLR_HDTFC3_Pos) /*!< 0x00000400 */ +#define DMA_CLR_HDTFC3 DMA_CLR_HDTFC3_Msk /*!< Channel 3 half transfer flag clear */ +#define DMA_CLR_DTERRFC3_Pos (11U) +#define DMA_CLR_DTERRFC3_Msk (0x1U << DMA_CLR_DTERRFC3_Pos) /*!< 0x00000800 */ +#define DMA_CLR_DTERRFC3 DMA_CLR_DTERRFC3_Msk /*!< Channel 3 data transfer error flag clear */ +#define DMA_CLR_GFC4_Pos (12U) +#define DMA_CLR_GFC4_Msk (0x1U << DMA_CLR_GFC4_Pos) /*!< 0x00001000 */ +#define DMA_CLR_GFC4 DMA_CLR_GFC4_Msk /*!< Channel 4 global interrupt flag clear */ +#define DMA_CLR_FDTFC4_Pos (13U) +#define DMA_CLR_FDTFC4_Msk (0x1U << DMA_CLR_FDTFC4_Pos) /*!< 0x00002000 */ +#define DMA_CLR_FDTFC4 DMA_CLR_FDTFC4_Msk /*!< Channel 4 transfer complete flag clear */ +#define DMA_CLR_HDTFC4_Pos (14U) +#define DMA_CLR_HDTFC4_Msk (0x1U << DMA_CLR_HDTFC4_Pos) /*!< 0x00004000 */ +#define DMA_CLR_HDTFC4 DMA_CLR_HDTFC4_Msk /*!< Channel 4 half transfer flag clear */ +#define DMA_CLR_DTERRFC4_Pos (15U) +#define DMA_CLR_DTERRFC4_Msk (0x1U << DMA_CLR_DTERRFC4_Pos) /*!< 0x00008000 */ +#define DMA_CLR_DTERRFC4 DMA_CLR_DTERRFC4_Msk /*!< Channel 4 data transfer error flag clear */ +#define DMA_CLR_GFC5_Pos (16U) +#define DMA_CLR_GFC5_Msk (0x1U << DMA_CLR_GFC5_Pos) /*!< 0x00010000 */ +#define DMA_CLR_GFC5 DMA_CLR_GFC5_Msk /*!< Channel 5 global interrupt flag clear */ +#define DMA_CLR_FDTFC5_Pos (17U) +#define DMA_CLR_FDTFC5_Msk (0x1U << DMA_CLR_FDTFC5_Pos) /*!< 0x00020000 */ +#define DMA_CLR_FDTFC5 DMA_CLR_FDTFC5_Msk /*!< Channel 5 transfer complete flag clear */ +#define DMA_CLR_HDTFC5_Pos (18U) +#define DMA_CLR_HDTFC5_Msk (0x1U << DMA_CLR_HDTFC5_Pos) /*!< 0x00040000 */ +#define DMA_CLR_HDTFC5 DMA_CLR_HDTFC5_Msk /*!< Channel 5 half transfer flag clear */ +#define DMA_CLR_DTERRFC5_Pos (19U) +#define DMA_CLR_DTERRFC5_Msk (0x1U << DMA_CLR_DTERRFC5_Pos) /*!< 0x00080000 */ +#define DMA_CLR_DTERRFC5 DMA_CLR_DTERRFC5_Msk /*!< Channel 5 data transfer error flag clear */ +#define DMA_CLR_GFC6_Pos (20U) +#define DMA_CLR_GFC6_Msk (0x1U << DMA_CLR_GFC6_Pos) /*!< 0x00100000 */ +#define DMA_CLR_GFC6 DMA_CLR_GFC6_Msk /*!< Channel 6 global interrupt flag clear */ +#define DMA_CLR_FDTFC6_Pos (21U) +#define DMA_CLR_FDTFC6_Msk (0x1U << DMA_CLR_FDTFC6_Pos) /*!< 0x00200000 */ +#define DMA_CLR_FDTFC6 DMA_CLR_FDTFC6_Msk /*!< Channel 6 transfer complete flag clear */ +#define DMA_CLR_HDTFC6_Pos (22U) +#define DMA_CLR_HDTFC6_Msk (0x1U << DMA_CLR_HDTFC6_Pos) /*!< 0x00400000 */ +#define DMA_CLR_HDTFC6 DMA_CLR_HDTFC6_Msk /*!< Channel 6 half transfer flag clear */ +#define DMA_CLR_DTERRFC6_Pos (23U) +#define DMA_CLR_DTERRFC6_Msk (0x1U << DMA_CLR_DTERRFC6_Pos) /*!< 0x00800000 */ +#define DMA_CLR_DTERRFC6 DMA_CLR_DTERRFC6_Msk /*!< Channel 6 data transfer error flag clear */ +#define DMA_CLR_GFC7_Pos (24U) +#define DMA_CLR_GFC7_Msk (0x1U << DMA_CLR_GFC7_Pos) /*!< 0x01000000 */ +#define DMA_CLR_GFC7 DMA_CLR_GFC7_Msk /*!< Channel 7 global interrupt flag clear */ +#define DMA_CLR_FDTFC7_Pos (25U) +#define DMA_CLR_FDTFC7_Msk (0x1U << DMA_CLR_FDTFC7_Pos) /*!< 0x02000000 */ +#define DMA_CLR_FDTFC7 DMA_CLR_FDTFC7_Msk /*!< Channel 7 transfer complete flag clear */ +#define DMA_CLR_HDTFC7_Pos (26U) +#define DMA_CLR_HDTFC7_Msk (0x1U << DMA_CLR_HDTFC7_Pos) /*!< 0x04000000 */ +#define DMA_CLR_HDTFC7 DMA_CLR_HDTFC7_Msk /*!< Channel 7 half transfer flag clear */ +#define DMA_CLR_DTERRFC7_Pos (27U) +#define DMA_CLR_DTERRFC7_Msk (0x1U << DMA_CLR_DTERRFC7_Pos) /*!< 0x08000000 */ +#define DMA_CLR_DTERRFC7 DMA_CLR_DTERRFC7_Msk /*!< Channel 7 data transfer error flag clear */ + +/****************** Bit definition for DMA_CCTRL register *******************/ +#define DMA_CCTRL_CHEN_Pos (0U) +#define DMA_CCTRL_CHEN_Msk (0x1U << DMA_CCTRL_CHEN_Pos) /*!< 0x00000001 */ +#define DMA_CCTRL_CHEN DMA_CCTRL_CHEN_Msk /*!< Channel enable */ +#define DMA_CCTRL_FDTIEN_Pos (1U) +#define DMA_CCTRL_FDTIEN_Msk (0x1U << DMA_CCTRL_FDTIEN_Pos) /*!< 0x00000002 */ +#define DMA_CCTRL_FDTIEN DMA_CCTRL_FDTIEN_Msk /*!< Transfer complete interrupt enable */ +#define DMA_CCTRL_HDTIEN_Pos (2U) +#define DMA_CCTRL_HDTIEN_Msk (0x1U << DMA_CCTRL_HDTIEN_Pos) /*!< 0x00000004 */ +#define DMA_CCTRL_HDTIEN DMA_CCTRL_HDTIEN_Msk /*!< Half-transfer interrupt enable */ +#define DMA_CCTRL_DTERRIEN_Pos (3U) +#define DMA_CCTRL_DTERRIEN_Msk (0x1U << DMA_CCTRL_DTERRIEN_Pos) /*!< 0x00000008 */ +#define DMA_CCTRL_DTERRIEN DMA_CCTRL_DTERRIEN_Msk /*!< Data transfer error interrupt enable */ +#define DMA_CCTRL_DTD_Pos (4U) +#define DMA_CCTRL_DTD_Msk (0x1U << DMA_CCTRL_DTD_Pos) /*!< 0x00000010 */ +#define DMA_CCTRL_DTD DMA_CCTRL_DTD_Msk /*!< Data transfer direction */ +#define DMA_CCTRL_LM_Pos (5U) +#define DMA_CCTRL_LM_Msk (0x1U << DMA_CCTRL_LM_Pos) /*!< 0x00000020 */ +#define DMA_CCTRL_LM DMA_CCTRL_LM_Msk /*!< Circular mode */ +#define DMA_CCTRL_PINCM_Pos (6U) +#define DMA_CCTRL_PINCM_Msk (0x1U << DMA_CCTRL_PINCM_Pos) /*!< 0x00000040 */ +#define DMA_CCTRL_PINCM DMA_CCTRL_PINCM_Msk /*!< Peripheral address increment mode */ +#define DMA_CCTRL_MINCM_Pos (7U) +#define DMA_CCTRL_MINCM_Msk (0x1U << DMA_CCTRL_MINCM_Pos) /*!< 0x00000080 */ +#define DMA_CCTRL_MINCM DMA_CCTRL_MINCM_Msk /*!< Memory address increment mode */ + +/*!< PWIDTH configuration */ +#define DMA_CCTRL_PWIDTH_Pos (8U) +#define DMA_CCTRL_PWIDTH_Msk (0x3U << DMA_CCTRL_PWIDTH_Pos) /*!< 0x00000300 */ +#define DMA_CCTRL_PWIDTH DMA_CCTRL_PWIDTH_Msk /*!< PWIDTH[1:0] bits (Peripheral data bit width) */ +#define DMA_CCTRL_PWIDTH_0 (0x1U << DMA_CCTRL_PWIDTH_Pos) /*!< 0x00000100 */ +#define DMA_CCTRL_PWIDTH_1 (0x2U << DMA_CCTRL_PWIDTH_Pos) /*!< 0x00000200 */ + +/*!< MWIDTH configuration */ +#define DMA_CCTRL_MWIDTH_Pos (10U) +#define DMA_CCTRL_MWIDTH_Msk (0x3U << DMA_CCTRL_MWIDTH_Pos) /*!< 0x00000C00 */ +#define DMA_CCTRL_MWIDTH DMA_CCTRL_MWIDTH_Msk /*!< MWIDTH[1:0] bits (Memory data bit width) */ +#define DMA_CCTRL_MWIDTH_0 (0x1U << DMA_CCTRL_MWIDTH_Pos) /*!< 0x00000400 */ +#define DMA_CCTRL_MWIDTH_1 (0x2U << DMA_CCTRL_MWIDTH_Pos) /*!< 0x00000800 */ + +/*!< CHPL configuration */ +#define DMA_CCTRL_CHPL_Pos (12U) +#define DMA_CCTRL_CHPL_Msk (0x3U << DMA_CCTRL_CHPL_Pos) /*!< 0x00003000 */ +#define DMA_CCTRL_CHPL DMA_CCTRL_CHPL_Msk /*!< CHPL[1:0] bits(Channel priority level) */ +#define DMA_CCTRL_CHPL_0 (0x1U << DMA_CCTRL_CHPL_Pos) /*!< 0x00001000 */ +#define DMA_CCTRL_CHPL_1 (0x2U << DMA_CCTRL_CHPL_Pos) /*!< 0x00002000 */ + +#define DMA_CCTRL_M2M_Pos (14U) +#define DMA_CCTRL_M2M_Msk (0x1U << DMA_CCTRL_M2M_Pos) /*!< 0x00004000 */ +#define DMA_CCTRL_M2M DMA_CCTRL_M2M_Msk /*!< Memory to memory mode */ + +/****************** Bit definition for DMA_CDTCNT register ******************/ +#define DMA_CDTCNT_CNT_Pos (0U) +#define DMA_CDTCNT_CNT_Msk (0xFFFFU << DMA_CDTCNT_CNT_Pos) /*!< 0x0000FFFF */ +#define DMA_CDTCNT_CNT DMA_CDTCNT_CNT_Msk /*!< Number of data to transfer */ + +/****************** Bit definition for DMA_CPADDR register ******************/ +#define DMA_CPADDR_PADDR_Pos (0U) +#define DMA_CPADDR_PADDR_Msk (0xFFFFFFFFU << DMA_CPADDR_PADDR_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CPADDR_PADDR DMA_CPADDR_PADDR_Msk /*!< Peripheral base address */ + +/****************** Bit definition for DMA_CMADDR register ******************/ +#define DMA_CMADDR_MADDR_Pos (0U) +#define DMA_CMADDR_MADDR_Msk (0xFFFFFFFFU << DMA_CMADDR_MADDR_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CMADDR_MADDR DMA_CMADDR_MADDR_Msk /*!< Memory base address */ + +/****************** Bit definition for DMA_MUXSEL register ******************/ +#define DMA_MUXSEL_TBL_SEL_Pos (0U) +#define DMA_MUXSEL_TBL_SEL_Msk (0x1U << DMA_MUXSEL_TBL_SEL_Pos) /*!< 0x00000001 */ +#define DMA_MUXSEL_TBL_SEL DMA_MUXSEL_TBL_SEL_Msk /*!< Multiplexer table select */ + +/***************** Bit definition for DMA_MUXCCTRL register *****************/ +#define DMA_MUXCCTRL_REQSEL_Pos (0U) +#define DMA_MUXCCTRL_REQSEL_Msk (0x7FU << DMA_MUXCCTRL_REQSEL_Pos) /*!< 0x0000007F */ +#define DMA_MUXCCTRL_REQSEL DMA_MUXCCTRL_REQSEL_Msk /*!< DMA request select */ +#define DMA_MUXCCTRL_SYNCOVIEN_Pos (8U) +#define DMA_MUXCCTRL_SYNCOVIEN_Msk (0x1U << DMA_MUXCCTRL_SYNCOVIEN_Pos) /*!< 0x00000100 */ +#define DMA_MUXCCTRL_SYNCOVIEN DMA_MUXCCTRL_SYNCOVIEN_Msk /*!< Synchronization overrun interrupt enable */ +#define DMA_MUXCCTRL_EVTGEN_Pos (9U) +#define DMA_MUXCCTRL_EVTGEN_Msk (0x1U << DMA_MUXCCTRL_EVTGEN_Pos) /*!< 0x00000200 */ +#define DMA_MUXCCTRL_EVTGEN DMA_MUXCCTRL_EVTGEN_Msk /*!< Event generate enable */ +#define DMA_MUXCCTRL_SYNCEN_Pos (16U) +#define DMA_MUXCCTRL_SYNCEN_Msk (0x1U << DMA_MUXCCTRL_SYNCEN_Pos) /*!< 0x00010000 */ +#define DMA_MUXCCTRL_SYNCEN DMA_MUXCCTRL_SYNCEN_Msk /*!< Synchronization enable */ + +/*!< SYNCPOL configuration */ +#define DMA_MUXCCTRL_SYNCPOL_Pos (17U) +#define DMA_MUXCCTRL_SYNCPOL_Msk (0x3U << DMA_MUXCCTRL_SYNCPOL_Pos) /*!< 0x00060000 */ +#define DMA_MUXCCTRL_SYNCPOL DMA_MUXCCTRL_SYNCPOL_Msk /*!< SYNCPOL[1:0] bits (Synchronization polarity) */ +#define DMA_MUXCCTRL_SYNCPOL_0 (0x1U << DMA_MUXCCTRL_SYNCPOL_Pos) /*!< 0x00020000 */ +#define DMA_MUXCCTRL_SYNCPOL_1 (0x2U << DMA_MUXCCTRL_SYNCPOL_Pos) /*!< 0x00040000 */ + +/*!< REQCNT configuration */ +#define DMA_MUXCCTRL_REQCNT_Pos (19U) +#define DMA_MUXCCTRL_REQCNT_Msk (0x1FU << DMA_MUXCCTRL_REQCNT_Pos) /*!< 0x00F80000 */ +#define DMA_MUXCCTRL_REQCNT DMA_MUXCCTRL_REQCNT_Msk /*!< REQCNT[4:0] bits (DMA request count) */ +#define DMA_MUXCCTRL_REQCNT_0 (0x1U << DMA_MUXCCTRL_REQCNT_Pos) /*!< 0x00080000 */ +#define DMA_MUXCCTRL_REQCNT_1 (0x2U << DMA_MUXCCTRL_REQCNT_Pos) /*!< 0x00100000 */ +#define DMA_MUXCCTRL_REQCNT_2 (0x4U << DMA_MUXCCTRL_REQCNT_Pos) /*!< 0x00200000 */ +#define DMA_MUXCCTRL_REQCNT_3 (0x8U << DMA_MUXCCTRL_REQCNT_Pos) /*!< 0x00400000 */ +#define DMA_MUXCCTRL_REQCNT_4 (0x10U << DMA_MUXCCTRL_REQCNT_Pos) /*!< 0x00800000 */ + +/*!< SYNCSEL configuration */ +#define DMA_MUXCCTRL_SYNCSEL_Pos (24U) +#define DMA_MUXCCTRL_SYNCSEL_Msk (0x1FU << DMA_MUXCCTRL_SYNCSEL_Pos) /*!< 0x1F000000 */ +#define DMA_MUXCCTRL_SYNCSEL DMA_MUXCCTRL_SYNCSEL_Msk /*!< SYNCSEL[4:0] bits (Synchronization select) */ +#define DMA_MUXCCTRL_SYNCSEL_0 (0x1U << DMA_MUXCCTRL_SYNCSEL_Pos) /*!< 0x01000000 */ +#define DMA_MUXCCTRL_SYNCSEL_1 (0x2U << DMA_MUXCCTRL_SYNCSEL_Pos) /*!< 0x02000000 */ +#define DMA_MUXCCTRL_SYNCSEL_2 (0x4U << DMA_MUXCCTRL_SYNCSEL_Pos) /*!< 0x04000000 */ +#define DMA_MUXCCTRL_SYNCSEL_3 (0x8U << DMA_MUXCCTRL_SYNCSEL_Pos) /*!< 0x08000000 */ +#define DMA_MUXCCTRL_SYNCSEL_4 (0x10U << DMA_MUXCCTRL_SYNCSEL_Pos) /*!< 0x10000000 */ + +/***************** Bit definition for DMA_MUXGCTRL register *****************/ +#define DMA_MUXGCTRL_SIGSEL_Pos (0U) +#define DMA_MUXGCTRL_SIGSEL_Msk (0x1FU << DMA_MUXGCTRL_SIGSEL_Pos) /*!< 0x0000001F */ +#define DMA_MUXGCTRL_SIGSEL DMA_MUXGCTRL_SIGSEL_Msk /*!< Signal select */ +#define DMA_MUXGCTRL_TRGOVIEN_Pos (8U) +#define DMA_MUXGCTRL_TRGOVIEN_Msk (0x1U << DMA_MUXGCTRL_TRGOVIEN_Pos) /*!< 0x00000100 */ +#define DMA_MUXGCTRL_TRGOVIEN DMA_MUXGCTRL_TRGOVIEN_Msk /*!< Trigger overrun interrupt enable */ +#define DMA_MUXGCTRL_GEN_Pos (16U) +#define DMA_MUXGCTRL_GEN_Msk (0x1U << DMA_MUXGCTRL_GEN_Pos) /*!< 0x00010000 */ +#define DMA_MUXGCTRL_GEN DMA_MUXGCTRL_GEN_Msk /*!< DMA request generation enable */ + +/*!< GPOL configuration */ +#define DMA_MUXGCTRL_GPOL_Pos (17U) +#define DMA_MUXGCTRL_GPOL_Msk (0x3U << DMA_MUXGCTRL_GPOL_Pos) /*!< 0x00060000 */ +#define DMA_MUXGCTRL_GPOL DMA_MUXGCTRL_GPOL_Msk /*!< GPOL[1:0] bits (DMA request generation polarity) */ +#define DMA_MUXGCTRL_GPOL_0 (0x1U << DMA_MUXGCTRL_GPOL_Pos) /*!< 0x00020000 */ +#define DMA_MUXGCTRL_GPOL_1 (0x2U << DMA_MUXGCTRL_GPOL_Pos) /*!< 0x00040000 */ + +/*!< GREQCNT configuration */ +#define DMA_MUXGCTRL_GREQCNT_Pos (19U) +#define DMA_MUXGCTRL_GREQCNT_Msk (0x1FU << DMA_MUXGCTRL_GREQCNT_Pos) /*!< 0x00F80000 */ +#define DMA_MUXGCTRL_GREQCNT DMA_MUXGCTRL_GREQCNT_Msk /*!< GREQCNT[4:0] bits (DMA request generation count) */ +#define DMA_MUXGCTRL_GREQCNT_0 (0x1U << DMA_MUXGCTRL_GREQCNT_Pos) /*!< 0x00080000 */ +#define DMA_MUXGCTRL_GREQCNT_1 (0x2U << DMA_MUXGCTRL_GREQCNT_Pos) /*!< 0x00100000 */ +#define DMA_MUXGCTRL_GREQCNT_2 (0x4U << DMA_MUXGCTRL_GREQCNT_Pos) /*!< 0x00200000 */ +#define DMA_MUXGCTRL_GREQCNT_3 (0x8U << DMA_MUXGCTRL_GREQCNT_Pos) /*!< 0x00400000 */ +#define DMA_MUXGCTRL_GREQCNT_4 (0x10U << DMA_MUXGCTRL_GREQCNT_Pos) /*!< 0x00800000 */ + +/**************** Bit definition for DMA_MUXSYNCSTS register ****************/ +#define DMA_MUXSYNCSTS_SYNCOVF_Pos (0U) +#define DMA_MUXSYNCSTS_SYNCOVF_Msk (0xFFU << DMA_MUXSYNCSTS_SYNCOVF_Pos) /*!< 0x000000FF */ +#define DMA_MUXSYNCSTS_SYNCOVF DMA_MUXSYNCSTS_SYNCOVF_Msk /*!< Synchronization overrun interrupt flag */ + +/**************** Bit definition for DMA_MUXSYNCCLR register ****************/ +#define DMA_MUXSYNCCLR_SYNCOVFC_Pos (0U) +#define DMA_MUXSYNCCLR_SYNCOVFC_Msk (0xFFU << DMA_MUXSYNCCLR_SYNCOVFC_Pos) /*!< 0x000000FF */ +#define DMA_MUXSYNCCLR_SYNCOVFC DMA_MUXSYNCCLR_SYNCOVFC_Msk /*!< Synchronization overrun interrupt flag clear */ + +/***************** Bit definition for DMA_MUXGSTS register ******************/ +#define DMA_MUXGSTS_TRGOVF_Pos (0U) +#define DMA_MUXGSTS_TRGOVF_Msk (0xFU << DMA_MUXGSTS_TRGOVF_Pos) /*!< 0x0000000F */ +#define DMA_MUXGSTS_TRGOVF DMA_MUXGSTS_TRGOVF_Msk /*!< Trigger overrun interrupt flag */ + +/***************** Bit definition for DMA_MUXGCLR register ******************/ +#define DMA_MUXGCLR_TRGOVFC_Pos (0U) +#define DMA_MUXGCLR_TRGOVFC_Msk (0xFU << DMA_MUXGCLR_TRGOVFC_Pos) /*!< 0x0000000F */ +#define DMA_MUXGCLR_TRGOVFC DMA_MUXGCLR_TRGOVFC_Msk /*!< Trigger overrun interrupt flag clear */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit (CRC) */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for CRC_DT register ********************/ +#define CRC_DT_DT_Pos (0U) +#define CRC_DT_DT_Msk (0xFFFFFFFFU << CRC_DT_DT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DT_DT CRC_DT_DT_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_CDT register ********************/ +#define CRC_CDT_CDT_Pos (0U) +#define CRC_CDT_CDT_Msk (0xFFU << CRC_CDT_CDT_Pos) /*!< 0x000000FF */ +#define CRC_CDT_CDT CRC_CDT_CDT_Msk /*!< General-purpose 8-bit data register bits */ + +/******************* Bit definition for CRC_CTRL register *******************/ +#define CRC_CTRL_RST_Pos (0U) +#define CRC_CTRL_RST_Msk (0x1U << CRC_CTRL_RST_Pos) /*!< 0x00000001 */ +#define CRC_CTRL_RST CRC_CTRL_RST_Msk /*!< Reset CRC calculation unit */ + +/*!< POLY_SIZE configuration */ +#define CRC_CTRL_POLY_SIZE_Pos (3U) +#define CRC_CTRL_POLY_SIZE_Msk (0x3U << CRC_CTRL_POLY_SIZE_Pos) /*!< 0x00000018 */ +#define CRC_CTRL_POLY_SIZE CRC_CTRL_POLY_SIZE_Msk /*!< POLY_SIZE[1:0] bits (Polynomial size) */ +#define CRC_CTRL_POLY_SIZE_0 (0x1U << CRC_CTRL_POLY_SIZE_Pos) /*!< 0x00000008 */ +#define CRC_CTRL_POLY_SIZE_1 (0x2U << CRC_CTRL_POLY_SIZE_Pos) /*!< 0x00000010 */ + +#define CRC_CTRL_POLY_SIZE_32BIT 0x00000000U /*!< 32-bit */ +#define CRC_CTRL_POLY_SIZE_16BIT_Pos (3U) +#define CRC_CTRL_POLY_SIZE_16BIT_Msk (0x1U << CRC_CTRL_POLY_SIZE_16BIT_Pos) /*!< 0x00000008 */ +#define CRC_CTRL_POLY_SIZE_16BIT CRC_CTRL_POLY_SIZE_16BIT_Msk /*!< 16-bit */ +#define CRC_CTRL_POLY_SIZE_8BIT_Pos (4U) +#define CRC_CTRL_POLY_SIZE_8BIT_Msk (0x1U << CRC_CTRL_POLY_SIZE_8BIT_Pos) /*!< 0x00000010 */ +#define CRC_CTRL_POLY_SIZE_8BIT CRC_CTRL_POLY_SIZE_8BIT_Msk /*!< 8-bit */ +#define CRC_CTRL_POLY_SIZE_7BIT_Pos (3U) +#define CRC_CTRL_POLY_SIZE_7BIT_Msk (0x3U << CRC_CTRL_POLY_SIZE_7BIT_Pos) /*!< 0x00000018 */ +#define CRC_CTRL_POLY_SIZE_7BIT CRC_CTRL_POLY_SIZE_7BIT_Msk /*!< 7-bit */ + +/*!< REVID configuration */ +#define CRC_CTRL_REVID_Pos (5U) +#define CRC_CTRL_REVID_Msk (0x3U << CRC_CTRL_REVID_Pos) /*!< 0x00000060 */ +#define CRC_CTRL_REVID CRC_CTRL_REVID_Msk /*!< REVID[1:0] bits (Reverse input data) */ +#define CRC_CTRL_REVID_0 (0x1U << CRC_CTRL_REVID_Pos) /*!< 0x00000020 */ +#define CRC_CTRL_REVID_1 (0x2U << CRC_CTRL_REVID_Pos) /*!< 0x00000040 */ + +#define CRC_CTRL_REVID_NOREV 0x00000000U /*!< No effect */ +#define CRC_CTRL_REVID_BYTEREV_Pos (5U) +#define CRC_CTRL_REVID_BYTEREV_Msk (0x1U << CRC_CTRL_REVID_BYTEREV_Pos) /*!< 0x00000020 */ +#define CRC_CTRL_REVID_BYTEREV CRC_CTRL_REVID_BYTEREV_Msk /*!< Byte reverse */ +#define CRC_CTRL_REVID_HALFREV_Pos (6U) +#define CRC_CTRL_REVID_HALFREV_Msk (0x1U << CRC_CTRL_REVID_HALFREV_Pos) /*!< 0x00000040 */ +#define CRC_CTRL_REVID_HALFREV CRC_CTRL_REVID_HALFREV_Msk /*!< Half-word reverse */ +#define CRC_CTRL_REVID_WORDREV_Pos (5U) +#define CRC_CTRL_REVID_WORDREV_Msk (0x3U << CRC_CTRL_REVID_WORDREV_Pos) /*!< 0x00000060 */ +#define CRC_CTRL_REVID_WORDREV CRC_CTRL_REVID_WORDREV_Msk /*!< Word reverse */ + +#define CRC_CTRL_REVOD_Pos (7U) +#define CRC_CTRL_REVOD_Msk (0x1U << CRC_CTRL_REVOD_Pos) /*!< 0x00000080 */ +#define CRC_CTRL_REVOD CRC_CTRL_REVOD_Msk /*!< Reverse output data */ + +/******************* Bit definition for CRC_IDT register ********************/ +#define CRC_IDT_IDT_Pos (0U) +#define CRC_IDT_IDT_Msk (0xFFFFFFFFU << CRC_IDT_IDT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDT_IDT CRC_IDT_IDT_Msk /*!< Initialization data register */ + +/******************* Bit definition for CRC_POLY register *******************/ +#define CRC_POLY_POLY_Pos (0U) +#define CRC_POLY_POLY_Msk (0xFFFFFFFFU << CRC_POLY_POLY_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POLY_POLY CRC_POLY_POLY_Msk /*!< Polynomial coefficient */ + +/******************************************************************************/ +/* */ +/* Inter-integrated circuit interface (I2C) */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for I2C_CTRL1 register *******************/ +#define I2C_CTRL1_I2CEN_Pos (0U) +#define I2C_CTRL1_I2CEN_Msk (0x1U << I2C_CTRL1_I2CEN_Pos) /*!< 0x00000001 */ +#define I2C_CTRL1_I2CEN I2C_CTRL1_I2CEN_Msk /*!< I2C peripheral enable */ +#define I2C_CTRL1_TDIEN_Pos (1U) +#define I2C_CTRL1_TDIEN_Msk (0x1U << I2C_CTRL1_TDIEN_Pos) /*!< 0x00000002 */ +#define I2C_CTRL1_TDIEN I2C_CTRL1_TDIEN_Msk /*!< Data transmit data interrupt enable */ +#define I2C_CTRL1_RDIEN_Pos (2U) +#define I2C_CTRL1_RDIEN_Msk (0x1U << I2C_CTRL1_RDIEN_Pos) /*!< 0x00000004 */ +#define I2C_CTRL1_RDIEN I2C_CTRL1_RDIEN_Msk /*!< Data receive interrupt enable */ +#define I2C_CTRL1_ADDRIEN_Pos (3U) +#define I2C_CTRL1_ADDRIEN_Msk (0x1U << I2C_CTRL1_ADDRIEN_Pos) /*!< 0x00000008 */ +#define I2C_CTRL1_ADDRIEN I2C_CTRL1_ADDRIEN_Msk /*!< Address match interrupt enable */ +#define I2C_CTRL1_ACKFAILIEN_Pos (4U) +#define I2C_CTRL1_ACKFAILIEN_Msk (0x1U << I2C_CTRL1_ACKFAILIEN_Pos) /*!< 0x00000010 */ +#define I2C_CTRL1_ACKFAILIEN I2C_CTRL1_ACKFAILIEN_Msk /*!< Acknowledge fail interrupt enable */ +#define I2C_CTRL1_STOPIEN_Pos (5U) +#define I2C_CTRL1_STOPIEN_Msk (0x1U << I2C_CTRL1_STOPIEN_Pos) /*!< 0x00000020 */ +#define I2C_CTRL1_STOPIEN I2C_CTRL1_STOPIEN_Msk /*!< Stop generation complete interrupt enable */ +#define I2C_CTRL1_TDCIEN_Pos (6U) +#define I2C_CTRL1_TDCIEN_Msk (0x1U << I2C_CTRL1_TDCIEN_Pos) /*!< 0x00000040 */ +#define I2C_CTRL1_TDCIEN I2C_CTRL1_TDCIEN_Msk /*!< Data transfer complete interrupt enable */ +#define I2C_CTRL1_ERRIEN_Pos (7U) +#define I2C_CTRL1_ERRIEN_Msk (0x1U << I2C_CTRL1_ERRIEN_Pos) /*!< 0x00000080 */ +#define I2C_CTRL1_ERRIEN I2C_CTRL1_ERRIEN_Msk /*!< Error interrupt enable */ +#define I2C_CTRL1_DFLT_Pos (8U) +#define I2C_CTRL1_DFLT_Msk (0xFU << I2C_CTRL1_DFLT_Pos) /*!< 0x00000F00 */ +#define I2C_CTRL1_DFLT I2C_CTRL1_DFLT_Msk /*!< Digital filter value */ +#define I2C_CTRL1_DMATEN_Pos (14U) +#define I2C_CTRL1_DMATEN_Msk (0x1U << I2C_CTRL1_DMATEN_Pos) /*!< 0x00004000 */ +#define I2C_CTRL1_DMATEN I2C_CTRL1_DMATEN_Msk /*!< DMA transmit data request enable */ +#define I2C_CTRL1_DMAREN_Pos (15U) +#define I2C_CTRL1_DMAREN_Msk (0x1U << I2C_CTRL1_DMAREN_Pos) /*!< 0x00008000 */ +#define I2C_CTRL1_DMAREN I2C_CTRL1_DMAREN_Msk /*!< DMA receive data request enable */ +#define I2C_CTRL1_SCTRL_Pos (16U) +#define I2C_CTRL1_SCTRL_Msk (0x1U << I2C_CTRL1_SCTRL_Pos) /*!< 0x00010000 */ +#define I2C_CTRL1_SCTRL I2C_CTRL1_SCTRL_Msk /*!< Slave receiving data control */ +#define I2C_CTRL1_STRETCH_Pos (17U) +#define I2C_CTRL1_STRETCH_Msk (0x1U << I2C_CTRL1_STRETCH_Pos) /*!< 0x00020000 */ +#define I2C_CTRL1_STRETCH I2C_CTRL1_STRETCH_Msk /*!< Clock stretching mode */ +#define I2C_CTRL1_GCAEN_Pos (19U) +#define I2C_CTRL1_GCAEN_Msk (0x1U << I2C_CTRL1_GCAEN_Pos) /*!< 0x00080000 */ +#define I2C_CTRL1_GCAEN I2C_CTRL1_GCAEN_Msk /*!< General call address enable */ +#define I2C_CTRL1_HADDREN_Pos (20U) +#define I2C_CTRL1_HADDREN_Msk (0x1U << I2C_CTRL1_HADDREN_Pos) /*!< 0x00100000 */ +#define I2C_CTRL1_HADDREN I2C_CTRL1_HADDREN_Msk /*!< SMBus host address enable */ +#define I2C_CTRL1_DEVADDREN_Pos (21U) +#define I2C_CTRL1_DEVADDREN_Msk (0x1U << I2C_CTRL1_DEVADDREN_Pos) /*!< 0x00200000 */ +#define I2C_CTRL1_DEVADDREN I2C_CTRL1_DEVADDREN_Msk /*!< SMBus device default address enable */ +#define I2C_CTRL1_SMBALERT_Pos (22U) +#define I2C_CTRL1_SMBALERT_Msk (0x1U << I2C_CTRL1_SMBALERT_Pos) /*!< 0x00400000 */ +#define I2C_CTRL1_SMBALERT I2C_CTRL1_SMBALERT_Msk /*!< SMBus alert enable / pin set */ +#define I2C_CTRL1_PECEN_Pos (23U) +#define I2C_CTRL1_PECEN_Msk (0x1U << I2C_CTRL1_PECEN_Pos) /*!< 0x00800000 */ +#define I2C_CTRL1_PECEN I2C_CTRL1_PECEN_Msk /*!< PEC calculation enable */ + +/****************** Bit definition for I2C_CTRL2 register *******************/ +/*!< SADDR configuration */ +#define I2C_CTRL2_SADDR_Pos (0U) +#define I2C_CTRL2_SADDR_Msk (0x3FFU << I2C_CTRL2_SADDR_Pos) /*!< 0x000003FF */ +#define I2C_CTRL2_SADDR I2C_CTRL2_SADDR_Msk /*!< SADDR[9:0] bits (Slave address sent by the master) */ +#define I2C_CTRL2_SADDR_0 (0x001U << I2C_CTRL2_SADDR_Pos) /*!< 0x00000001 */ +#define I2C_CTRL2_SADDR_1 (0x002U << I2C_CTRL2_SADDR_Pos) /*!< 0x00000002 */ +#define I2C_CTRL2_SADDR_2 (0x004U << I2C_CTRL2_SADDR_Pos) /*!< 0x00000004 */ +#define I2C_CTRL2_SADDR_3 (0x008U << I2C_CTRL2_SADDR_Pos) /*!< 0x00000008 */ +#define I2C_CTRL2_SADDR_4 (0x010U << I2C_CTRL2_SADDR_Pos) /*!< 0x00000010 */ +#define I2C_CTRL2_SADDR_5 (0x020U << I2C_CTRL2_SADDR_Pos) /*!< 0x00000020 */ +#define I2C_CTRL2_SADDR_6 (0x040U << I2C_CTRL2_SADDR_Pos) /*!< 0x00000040 */ +#define I2C_CTRL2_SADDR_7 (0x080U << I2C_CTRL2_SADDR_Pos) /*!< 0x00000080 */ +#define I2C_CTRL2_SADDR_8 (0x100U << I2C_CTRL2_SADDR_Pos) /*!< 0x00000100 */ +#define I2C_CTRL2_SADDR_9 (0x200U << I2C_CTRL2_SADDR_Pos) /*!< 0x00000200 */ + +#define I2C_CTRL2_DIR_Pos (10U) +#define I2C_CTRL2_DIR_Msk (0x1U << I2C_CTRL2_DIR_Pos) /*!< 0x00000400 */ +#define I2C_CTRL2_DIR I2C_CTRL2_DIR_Msk /*!< Master data transmission direction */ +#define I2C_CTRL2_ADDR10_Pos (11U) +#define I2C_CTRL2_ADDR10_Msk (0x1U << I2C_CTRL2_ADDR10_Pos) /*!< 0x00000800 */ +#define I2C_CTRL2_ADDR10 I2C_CTRL2_ADDR10_Msk /*!< Host sends 10-bit address mode enable */ +#define I2C_CTRL2_READH10_Pos (12U) +#define I2C_CTRL2_READH10_Msk (0x1U << I2C_CTRL2_READH10_Pos) /*!< 0x00001000 */ +#define I2C_CTRL2_READH10 I2C_CTRL2_READH10_Msk /*!< 10-bit address header read enable */ +#define I2C_CTRL2_GENSTART_Pos (13U) +#define I2C_CTRL2_GENSTART_Msk (0x1U << I2C_CTRL2_GENSTART_Pos) /*!< 0x00002000 */ +#define I2C_CTRL2_GENSTART I2C_CTRL2_GENSTART_Msk /*!< Generate start condition */ +#define I2C_CTRL2_GENSTOP_Pos (14U) +#define I2C_CTRL2_GENSTOP_Msk (0x1U << I2C_CTRL2_GENSTOP_Pos) /*!< 0x00004000 */ +#define I2C_CTRL2_GENSTOP I2C_CTRL2_GENSTOP_Msk /*!< Generate stop condition */ +#define I2C_CTRL2_NACKEN_Pos (15U) +#define I2C_CTRL2_NACKEN_Msk (0x1U << I2C_CTRL2_NACKEN_Pos) /*!< 0x00008000 */ +#define I2C_CTRL2_NACKEN I2C_CTRL2_NACKEN_Msk /*!< Not acknowledge enable */ + +/*!< CNT configuration */ +#define I2C_CTRL2_CNT_Pos (16U) +#define I2C_CTRL2_CNT_Msk (0xFFU << I2C_CTRL2_CNT_Pos) /*!< 0x00FF0000 */ +#define I2C_CTRL2_CNT I2C_CTRL2_CNT_Msk /*!< CNT[7:0] bits (CNT) */ +#define I2C_CTRL2_CNT_0 (0x01U << I2C_CTRL2_CNT_Pos) /*!< 0x00010000 */ +#define I2C_CTRL2_CNT_1 (0x02U << I2C_CTRL2_CNT_Pos) /*!< 0x00020000 */ +#define I2C_CTRL2_CNT_2 (0x04U << I2C_CTRL2_CNT_Pos) /*!< 0x00040000 */ +#define I2C_CTRL2_CNT_3 (0x08U << I2C_CTRL2_CNT_Pos) /*!< 0x00080000 */ +#define I2C_CTRL2_CNT_4 (0x10U << I2C_CTRL2_CNT_Pos) /*!< 0x00100000 */ +#define I2C_CTRL2_CNT_5 (0x20U << I2C_CTRL2_CNT_Pos) /*!< 0x00200000 */ +#define I2C_CTRL2_CNT_6 (0x40U << I2C_CTRL2_CNT_Pos) /*!< 0x00400000 */ +#define I2C_CTRL2_CNT_7 (0x80U << I2C_CTRL2_CNT_Pos) /*!< 0x00800000 */ + +#define I2C_CTRL2_RLDEN_Pos (24U) +#define I2C_CTRL2_RLDEN_Msk (0x1U << I2C_CTRL2_RLDEN_Pos) /*!< 0x01000000 */ +#define I2C_CTRL2_RLDEN I2C_CTRL2_RLDEN_Msk /*!< Send data reload mode enable */ +#define I2C_CTRL2_ASTOPEN_Pos (25U) +#define I2C_CTRL2_ASTOPEN_Msk (0x1U << I2C_CTRL2_ASTOPEN_Pos) /*!< 0x02000000 */ +#define I2C_CTRL2_ASTOPEN I2C_CTRL2_ASTOPEN_Msk /*!< Automatically send stop condition enable */ +#define I2C_CTRL2_PECTEN_Pos (26U) +#define I2C_CTRL2_PECTEN_Msk (0x1U << I2C_CTRL2_PECTEN_Pos) /*!< 0x04000000 */ +#define I2C_CTRL2_PECTEN I2C_CTRL2_PECTEN_Msk /*!< Request PEC transmission enable */ + +/****************** Bit definition for I2C_OADDR1 register ******************/ +/*!< ADDR1 configuration */ +#define I2C_OADDR1_ADDR1_1_7 0x000000FEU /*!< Interface Address */ +#define I2C_OADDR1_ADDR1_8_9 0x00000300U /*!< Interface Address */ + +#define I2C_OADDR1_ADDR1_0_Pos (0U) +#define I2C_OADDR1_ADDR1_0_Msk (0x1U << I2C_OADDR1_ADDR1_0_Pos) /*!< 0x00000001 */ +#define I2C_OADDR1_ADDR1_0 I2C_OADDR1_ADDR1_0_Msk /*!< Bit 0 */ +#define I2C_OADDR1_ADDR1_1_Pos (1U) +#define I2C_OADDR1_ADDR1_1_Msk (0x1U << I2C_OADDR1_ADDR1_1_Pos) /*!< 0x00000002 */ +#define I2C_OADDR1_ADDR1_1 I2C_OADDR1_ADDR1_1_Msk /*!< Bit 1 */ +#define I2C_OADDR1_ADDR1_2_Pos (2U) +#define I2C_OADDR1_ADDR1_2_Msk (0x1U << I2C_OADDR1_ADDR1_2_Pos) /*!< 0x00000004 */ +#define I2C_OADDR1_ADDR1_2 I2C_OADDR1_ADDR1_2_Msk /*!< Bit 2 */ +#define I2C_OADDR1_ADDR1_3_Pos (3U) +#define I2C_OADDR1_ADDR1_3_Msk (0x1U << I2C_OADDR1_ADDR1_3_Pos) /*!< 0x00000008 */ +#define I2C_OADDR1_ADDR1_3 I2C_OADDR1_ADDR1_3_Msk /*!< Bit 3 */ +#define I2C_OADDR1_ADDR1_4_Pos (4U) +#define I2C_OADDR1_ADDR1_4_Msk (0x1U << I2C_OADDR1_ADDR1_4_Pos) /*!< 0x00000010 */ +#define I2C_OADDR1_ADDR1_4 I2C_OADDR1_ADDR1_4_Msk /*!< Bit 4 */ +#define I2C_OADDR1_ADDR1_5_Pos (5U) +#define I2C_OADDR1_ADDR1_5_Msk (0x1U << I2C_OADDR1_ADDR1_5_Pos) /*!< 0x00000020 */ +#define I2C_OADDR1_ADDR1_5 I2C_OADDR1_ADDR1_5_Msk /*!< Bit 5 */ +#define I2C_OADDR1_ADDR1_6_Pos (6U) +#define I2C_OADDR1_ADDR1_6_Msk (0x1U << I2C_OADDR1_ADDR1_6_Pos) /*!< 0x00000040 */ +#define I2C_OADDR1_ADDR1_6 I2C_OADDR1_ADDR1_6_Msk /*!< Bit 6 */ +#define I2C_OADDR1_ADDR1_7_Pos (7U) +#define I2C_OADDR1_ADDR1_7_Msk (0x1U << I2C_OADDR1_ADDR1_7_Pos) /*!< 0x00000080 */ +#define I2C_OADDR1_ADDR1_7 I2C_OADDR1_ADDR1_7_Msk /*!< Bit 7 */ +#define I2C_OADDR1_ADDR1_8_Pos (8U) +#define I2C_OADDR1_ADDR1_8_Msk (0x1U << I2C_OADDR1_ADDR1_8_Pos) /*!< 0x00000100 */ +#define I2C_OADDR1_ADDR1_8 I2C_OADDR1_ADDR1_8_Msk /*!< Bit 8 */ +#define I2C_OADDR1_ADDR1_9_Pos (9U) +#define I2C_OADDR1_ADDR1_9_Msk (0x1U << I2C_OADDR1_ADDR1_9_Pos) /*!< 0x00000200 */ +#define I2C_OADDR1_ADDR1_9 I2C_OADDR1_ADDR1_9_Msk /*!< Bit 9 */ + +#define I2C_OADDR1_ADDR1MODE_Pos (10U) +#define I2C_OADDR1_ADDR1MODE_Msk (0x1U << I2C_OADDR1_ADDR1MODE_Pos) /*!< 0x00000400 */ +#define I2C_OADDR1_ADDR1MODE I2C_OADDR1_ADDR1MODE_Msk /*!< Own Address 1 mode */ +#define I2C_OADDR1_ADDR1EN_Pos (15U) +#define I2C_OADDR1_ADDR1EN_Msk (0x1U << I2C_OADDR1_ADDR1EN_Pos) /*!< 0x00008000 */ +#define I2C_OADDR1_ADDR1EN I2C_OADDR1_ADDR1EN_Msk /*!< Own Address 1 enable */ + +/****************** Bit definition for I2C_OADDR2 register ******************/ +#define I2C_OADDR2_ADDR2_Pos (1U) +#define I2C_OADDR2_ADDR2_Msk (0x7FU << I2C_OADDR2_ADDR2_Pos) /*!< 0x000000FE */ +#define I2C_OADDR2_ADDR2 I2C_OADDR2_ADDR2_Msk /*!< Own address 2 */ + +/*!< ADDR2MASK configuration */ +#define I2C_OADDR2_ADDR2MASK_Pos (8U) +#define I2C_OADDR2_ADDR2MASK_Msk (0x7U << I2C_OADDR2_ADDR2MASK_Pos) /*!< 0x00000700 */ +#define I2C_OADDR2_ADDR2MASK I2C_OADDR2_ADDR2MASK_Msk /*!< CNT[2:0] bits (Own address 2 bit mask) */ +#define I2C_OADDR2_ADDR2MASK_0 (0x01U << I2C_OADDR2_ADDR2MASK_Pos) /*!< 0x00000100 */ +#define I2C_OADDR2_ADDR2MASK_1 (0x02U << I2C_OADDR2_ADDR2MASK_Pos) /*!< 0x00000200 */ +#define I2C_OADDR2_ADDR2MASK_2 (0x04U << I2C_OADDR2_ADDR2MASK_Pos) /*!< 0x00000400 */ + +#define I2C_OADDR2_ADDR2EN_Pos (15U) +#define I2C_OADDR2_ADDR2EN_Msk (0x1U << I2C_OADDR2_ADDR2EN_Pos) /*!< 0x00008000 */ +#define I2C_OADDR2_ADDR2EN I2C_OADDR2_ADDR2EN_Msk /*!< Own Address 2 enable */ + +/***************** Bit definition for I2C_CLKCTRL register ******************/ +#define I2C_CLKCTRL_SCLL_Pos (0U) +#define I2C_CLKCTRL_SCLL_Msk (0xFFU << I2C_CLKCTRL_SCLL_Pos) /*!< 0x000000FF */ +#define I2C_CLKCTRL_SCLL I2C_CLKCTRL_SCLL_Msk /*!< SCL low level */ +#define I2C_CLKCTRL_SCLH_Pos (8U) +#define I2C_CLKCTRL_SCLH_Msk (0xFFU << I2C_CLKCTRL_SCLH_Pos) /*!< 0x0000FF00 */ +#define I2C_CLKCTRL_SCLH I2C_CLKCTRL_SCLH_Msk /*!< SCL high level */ +#define I2C_CLKCTRL_SDAD_Pos (16U) +#define I2C_CLKCTRL_SDAD_Msk (0xFU << I2C_CLKCTRL_SDAD_Pos) /*!< 0x000F0000 */ +#define I2C_CLKCTRL_SDAD I2C_CLKCTRL_SDAD_Msk /*!< SDA output delay */ +#define I2C_CLKCTRL_SCLD_Pos (20U) +#define I2C_CLKCTRL_SCLD_Msk (0xFU << I2C_CLKCTRL_SCLD_Pos) /*!< 0x00F00000 */ +#define I2C_CLKCTRL_SCLD I2C_CLKCTRL_SCLD_Msk /*!< SCL output delay */ +#define I2C_CLKCTRL_DIVH_Pos (24U) +#define I2C_CLKCTRL_DIVH_Msk (0xFU << I2C_CLKCTRL_DIVH_Pos) /*!< 0x0F000000 */ +#define I2C_CLKCTRL_DIVH I2C_CLKCTRL_DIVH_Msk /*!< High 4 bits of clock divider value */ +#define I2C_CLKCTRL_DIVL_Pos (28U) +#define I2C_CLKCTRL_DIVL_Msk (0xFU << I2C_CLKCTRL_DIVL_Pos) /*!< 0xF0000000 */ +#define I2C_CLKCTRL_DIVL I2C_CLKCTRL_DIVL_Msk /*!< Low 4 bits of clock divider value */ + +/***************** Bit definition for I2C_TIMEOUT register ******************/ +#define I2C_TIMEOUT_TOTIME_Pos (0U) +#define I2C_TIMEOUT_TOTIME_Msk (0xFFFU << I2C_TIMEOUT_TOTIME_Pos) /*!< 0x00000FFF */ +#define I2C_TIMEOUT_TOTIME I2C_TIMEOUT_TOTIME_Msk /*!< Clock timeout detection time */ +#define I2C_TIMEOUT_TOMODE_Pos (12U) +#define I2C_TIMEOUT_TOMODE_Msk (0x1U << I2C_TIMEOUT_TOMODE_Pos) /*!< 0x00001000 */ +#define I2C_TIMEOUT_TOMODE I2C_TIMEOUT_TOMODE_Msk /*!< Clock timeout detection mode */ +#define I2C_TIMEOUT_TOEN_Pos (15U) +#define I2C_TIMEOUT_TOEN_Msk (0x1U << I2C_TIMEOUT_TOEN_Pos) /*!< 0x00008000 */ +#define I2C_TIMEOUT_TOEN I2C_TIMEOUT_TOEN_Msk /*!< Detect clock low/high timeout enable */ +#define I2C_TIMEOUT_EXTTIME_Pos (16U) +#define I2C_TIMEOUT_EXTTIME_Msk (0xFFFU << I2C_TIMEOUT_EXTTIME_Pos) /*!< 0x0FFF0000 */ +#define I2C_TIMEOUT_EXTTIME I2C_TIMEOUT_EXTTIME_Msk /*!< Cumulative clock low extend timeout value */ +#define I2C_TIMEOUT_EXTEN_Pos (31U) +#define I2C_TIMEOUT_EXTEN_Msk (0x1U << I2C_TIMEOUT_EXTEN_Pos) /*!< 0x80000000 */ +#define I2C_TIMEOUT_EXTEN I2C_TIMEOUT_EXTEN_Msk /*!< Cumulative clock low extend timeout enable */ + +/******************* Bit definition for I2C_STS register ********************/ +#define I2C_STS_TDBE_Pos (0U) +#define I2C_STS_TDBE_Msk (0x1U << I2C_STS_TDBE_Pos) /*!< 0x00000001 */ +#define I2C_STS_TDBE I2C_STS_TDBE_Msk /*!< Transmit data buffer empty flag */ +#define I2C_STS_TDIS_Pos (1U) +#define I2C_STS_TDIS_Msk (0x1U << I2C_STS_TDIS_Pos) /*!< 0x00000002 */ +#define I2C_STS_TDIS I2C_STS_TDIS_Msk /*!< Transmit data interrupt status */ +#define I2C_STS_RDBF_Pos (2U) +#define I2C_STS_RDBF_Msk (0x1U << I2C_STS_RDBF_Pos) /*!< 0x00000004 */ +#define I2C_STS_RDBF I2C_STS_RDBF_Msk /*!< Receive data buffer full flag */ +#define I2C_STS_ADDRF_Pos (3U) +#define I2C_STS_ADDRF_Msk (0x1U << I2C_STS_ADDRF_Pos) /*!< 0x00000008 */ +#define I2C_STS_ADDRF I2C_STS_ADDRF_Msk /*!< 0 ~ 7 bit address match flag */ +#define I2C_STS_ACKFAILF_Pos (4U) +#define I2C_STS_ACKFAILF_Msk (0x1U << I2C_STS_ACKFAILF_Pos) /*!< 0x00000010 */ +#define I2C_STS_ACKFAILF I2C_STS_ACKFAILF_Msk /*!< Acknowledge failure flag */ +#define I2C_STS_STOPF_Pos (5U) +#define I2C_STS_STOPF_Msk (0x1U << I2C_STS_STOPF_Pos) /*!< 0x00000020 */ +#define I2C_STS_STOPF I2C_STS_STOPF_Msk /*!< Stop condition generation complete flag */ +#define I2C_STS_TDC_Pos (6U) +#define I2C_STS_TDC_Msk (0x1U << I2C_STS_TDC_Pos) /*!< 0x00000040 */ +#define I2C_STS_TDC I2C_STS_TDC_Msk /*!< Data transfer complete flag */ +#define I2C_STS_TCRLD_Pos (7U) +#define I2C_STS_TCRLD_Msk (0x1U << I2C_STS_TCRLD_Pos) /*!< 0x00000080 */ +#define I2C_STS_TCRLD I2C_STS_TCRLD_Msk /*!< Transmission is complete, waiting to load data */ +#define I2C_STS_BUSERR_Pos (8U) +#define I2C_STS_BUSERR_Msk (0x1U << I2C_STS_BUSERR_Pos) /*!< 0x00000100 */ +#define I2C_STS_BUSERR I2C_STS_BUSERR_Msk /*!< Bus error flag */ +#define I2C_STS_ARLOST_Pos (9U) +#define I2C_STS_ARLOST_Msk (0x1U << I2C_STS_ARLOST_Pos) /*!< 0x00000200 */ +#define I2C_STS_ARLOST I2C_STS_ARLOST_Msk /*!< Arbitration lost flag */ +#define I2C_STS_OUF_Pos (10U) +#define I2C_STS_OUF_Msk (0x1U << I2C_STS_OUF_Pos) /*!< 0x00000400 */ +#define I2C_STS_OUF I2C_STS_OUF_Msk /*!< Overflow or underflow flag */ +#define I2C_STS_PECERR_Pos (11U) +#define I2C_STS_PECERR_Msk (0x1U << I2C_STS_PECERR_Pos) /*!< 0x00000800 */ +#define I2C_STS_PECERR I2C_STS_PECERR_Msk /*!< PEC receive error flag */ +#define I2C_STS_TMOUT_Pos (12U) +#define I2C_STS_TMOUT_Msk (0x1U << I2C_STS_TMOUT_Pos) /*!< 0x00001000 */ +#define I2C_STS_TMOUT I2C_STS_TMOUT_Msk /*!< SMBus timeout flag */ +#define I2C_STS_ALERTF_Pos (13U) +#define I2C_STS_ALERTF_Msk (0x1U << I2C_STS_ALERTF_Pos) /*!< 0x00002000 */ +#define I2C_STS_ALERTF I2C_STS_ALERTF_Msk /*!< SMBus alert flag */ +#define I2C_STS_BUSYF_Pos (15U) +#define I2C_STS_BUSYF_Msk (0x1U << I2C_STS_BUSYF_Pos) /*!< 0x00008000 */ +#define I2C_STS_BUSYF I2C_STS_BUSYF_Msk /*!< Bus busy flag transmission mode */ +#define I2C_STS_SDIR_Pos (16U) +#define I2C_STS_SDIR_Msk (0x1U << I2C_STS_SDIR_Pos) /*!< 0x00010000 */ +#define I2C_STS_SDIR I2C_STS_SDIR_Msk /*!< Slave data transmit direction */ +#define I2C_STS_ADDR_Pos (17U) +#define I2C_STS_ADDR_Msk (0x7FU << I2C_STS_ADDR_Pos) /*!< 0x00FE0000 */ +#define I2C_STS_ADDR I2C_STS_ADDR_Msk /*!< Slave address matching value */ + +/******************* Bit definition for I2C_CLR register ********************/ +#define I2C_CLR_ADDRC_Pos (3U) +#define I2C_CLR_ADDRC_Msk (0x1U << I2C_CLR_ADDRC_Pos) /*!< 0x00000008 */ +#define I2C_CLR_ADDRC I2C_CLR_ADDRC_Msk /*!< Clear 0 ~ 7 bit address match flag */ +#define I2C_CLR_ACKFAILC_Pos (4U) +#define I2C_CLR_ACKFAILC_Msk (0x1U << I2C_CLR_ACKFAILC_Pos) /*!< 0x00000010 */ +#define I2C_CLR_ACKFAILC I2C_CLR_ACKFAILC_Msk /*!< Clear acknowledge failure flag */ +#define I2C_CLR_STOPC_Pos (5U) +#define I2C_CLR_STOPC_Msk (0x1U << I2C_CLR_STOPC_Pos) /*!< 0x00000020 */ +#define I2C_CLR_STOPC I2C_CLR_STOPC_Msk /*!< Clear stop condition generation complete flag */ +#define I2C_CLR_BUSERRC_Pos (8U) +#define I2C_CLR_BUSERRC_Msk (0x1U << I2C_CLR_BUSERRC_Pos) /*!< 0x00000100 */ +#define I2C_CLR_BUSERRC I2C_CLR_BUSERRC_Msk /*!< Clear bus error flag */ +#define I2C_CLR_ARLOSTC_Pos (9U) +#define I2C_CLR_ARLOSTC_Msk (0x1U << I2C_CLR_ARLOSTC_Pos) /*!< 0x00000200 */ +#define I2C_CLR_ARLOSTC I2C_CLR_ARLOSTC_Msk /*!< Clear arbitration lost flag */ +#define I2C_CLR_OUFC_Pos (10U) +#define I2C_CLR_OUFC_Msk (0x1U << I2C_CLR_OUFC_Pos) /*!< 0x00000400 */ +#define I2C_CLR_OUFC I2C_CLR_OUFC_Msk /*!< Clear overload / underload flag */ +#define I2C_CLR_PECERRC_Pos (11U) +#define I2C_CLR_PECERRC_Msk (0x1U << I2C_CLR_PECERRC_Pos) /*!< 0x00000800 */ +#define I2C_CLR_PECERRC I2C_CLR_PECERRC_Msk /*!< Clear PEC receive error flag */ +#define I2C_CLR_TMOUTC_Pos (12U) +#define I2C_CLR_TMOUTC_Msk (0x1U << I2C_CLR_TMOUTC_Pos) /*!< 0x00001000 */ +#define I2C_CLR_TMOUTC I2C_CLR_TMOUTC_Msk /*!< Clear SMBus timeout flag */ +#define I2C_CLR_ALERTC_Pos (13U) +#define I2C_CLR_ALERTC_Msk (0x1U << I2C_CLR_ALERTC_Pos) /*!< 0x00002000 */ +#define I2C_CLR_ALERTC I2C_CLR_ALERTC_Msk /*!< Clear SMBus alert flag */ + +/******************* Bit definition for I2C_PEC register ********************/ +#define I2C_PEC_PECVAL_Pos (0U) +#define I2C_PEC_PECVAL_Msk (0xFFU << I2C_PEC_PECVAL_Pos) /*!< 0x000000FF */ +#define I2C_PEC_PECVAL I2C_PEC_PECVAL_Msk /*!< PEC value */ + +/******************* Bit definition for I2C_RXDT register *******************/ +#define I2C_RXDT_DT_Pos (0U) +#define I2C_RXDT_DT_Msk (0xFFU << I2C_RXDT_DT_Pos) /*!< 0x000000FF */ +#define I2C_RXDT_DT I2C_RXDT_DT_Msk /*!< Receive data register */ + +/******************* Bit definition for I2C_TXDT register *******************/ +#define I2C_TXDT_DT_Pos (0U) +#define I2C_TXDT_DT_Msk (0xFFU << I2C_TXDT_DT_Pos) /*!< 0x000000FF */ +#define I2C_TXDT_DT I2C_TXDT_DT_Msk /*!< Transmit data register */ + +/******************************************************************************/ +/* */ +/* Universal synchronous/asynchronous receiver/transmitter (USART) */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for USART_STS register *******************/ +#define USART_STS_PERR_Pos (0U) +#define USART_STS_PERR_Msk (0x1U << USART_STS_PERR_Pos) /*!< 0x00000001 */ +#define USART_STS_PERR USART_STS_PERR_Msk /*!< Parity error */ +#define USART_STS_FERR_Pos (1U) +#define USART_STS_FERR_Msk (0x1U << USART_STS_FERR_Pos) /*!< 0x00000002 */ +#define USART_STS_FERR USART_STS_FERR_Msk /*!< Framing error */ +#define USART_STS_NERR_Pos (2U) +#define USART_STS_NERR_Msk (0x1U << USART_STS_NERR_Pos) /*!< 0x00000004 */ +#define USART_STS_NERR USART_STS_NERR_Msk /*!< Noise error */ +#define USART_STS_ROERR_Pos (3U) +#define USART_STS_ROERR_Msk (0x1U << USART_STS_ROERR_Pos) /*!< 0x00000008 */ +#define USART_STS_ROERR USART_STS_ROERR_Msk /*!< Receiver overflow error */ +#define USART_STS_IDLEF_Pos (4U) +#define USART_STS_IDLEF_Msk (0x1U << USART_STS_IDLEF_Pos) /*!< 0x00000010 */ +#define USART_STS_IDLEF USART_STS_IDLEF_Msk /*!< Idle flag */ +#define USART_STS_RDBF_Pos (5U) +#define USART_STS_RDBF_Msk (0x1U << USART_STS_RDBF_Pos) /*!< 0x00000020 */ +#define USART_STS_RDBF USART_STS_RDBF_Msk /*!< Receive data buffer full */ +#define USART_STS_TDC_Pos (6U) +#define USART_STS_TDC_Msk (0x1U << USART_STS_TDC_Pos) /*!< 0x00000040 */ +#define USART_STS_TDC USART_STS_TDC_Msk /*!< Transmit data complete */ +#define USART_STS_TDBE_Pos (7U) +#define USART_STS_TDBE_Msk (0x1U << USART_STS_TDBE_Pos) /*!< 0x00000080 */ +#define USART_STS_TDBE USART_STS_TDBE_Msk /*!< Transmit data buffer empty */ +#define USART_STS_BFF_Pos (8U) +#define USART_STS_BFF_Msk (0x1U << USART_STS_BFF_Pos) /*!< 0x00000100 */ +#define USART_STS_BFF USART_STS_BFF_Msk /*!< Break frame flag */ +#define USART_STS_CTSCF_Pos (9U) +#define USART_STS_CTSCF_Msk (0x1U << USART_STS_CTSCF_Pos) /*!< 0x00000200 */ +#define USART_STS_CTSCF USART_STS_CTSCF_Msk /*!< CTS change flag */ +#define USART_STS_RTODF_Pos (11U) +#define USART_STS_RTODF_Msk (0x1U << USART_STS_RTODF_Pos) /*!< 0x00000800 */ +#define USART_STS_RTODF USART_STS_RTODF_Msk /*!< Receiver timeout detection flag */ +#define USART_STS_CMDF_Pos (17U) +#define USART_STS_CMDF_Msk (0x1U << USART_STS_CMDF_Pos) /*!< 0x00020000 */ +#define USART_STS_CMDF USART_STS_CMDF_Msk /*!< Byte match detection flag */ + +/******************* Bit definition for USART_DT register *******************/ +#define USART_DT_DT_Pos (0U) +#define USART_DT_DT_Msk (0x1FFU << USART_DT_DT_Pos) /*!< 0x000001FF */ +#define USART_DT_DT USART_DT_DT_Msk /*!< Data value */ + +/***************** Bit definition for USART_BAUDR register ******************/ +#define USART_BAUDR_DIV_Pos (0U) +#define USART_BAUDR_DIV_Msk (0xFFFFU << USART_BAUDR_DIV_Pos) /*!< 0x0000FFFF */ +#define USART_BAUDR_DIV USART_BAUDR_DIV_Msk /*!< Divider */ + +/***************** Bit definition for USART_CTRL1 register ******************/ +#define USART_CTRL1_SBF_Pos (0U) +#define USART_CTRL1_SBF_Msk (0x1U << USART_CTRL1_SBF_Pos) /*!< 0x00000001 */ +#define USART_CTRL1_SBF USART_CTRL1_SBF_Msk /*!< Send break frame */ +#define USART_CTRL1_RM_Pos (1U) +#define USART_CTRL1_RM_Msk (0x1U << USART_CTRL1_RM_Pos) /*!< 0x00000002 */ +#define USART_CTRL1_RM USART_CTRL1_RM_Msk /*!< Receiver mute */ +#define USART_CTRL1_REN_Pos (2U) +#define USART_CTRL1_REN_Msk (0x1U << USART_CTRL1_REN_Pos) /*!< 0x00000004 */ +#define USART_CTRL1_REN USART_CTRL1_REN_Msk /*!< Receiver enable */ +#define USART_CTRL1_TEN_Pos (3U) +#define USART_CTRL1_TEN_Msk (0x1U << USART_CTRL1_TEN_Pos) /*!< 0x00000008 */ +#define USART_CTRL1_TEN USART_CTRL1_TEN_Msk /*!< Transmitter enable */ +#define USART_CTRL1_IDLEIEN_Pos (4U) +#define USART_CTRL1_IDLEIEN_Msk (0x1U << USART_CTRL1_IDLEIEN_Pos) /*!< 0x00000010 */ +#define USART_CTRL1_IDLEIEN USART_CTRL1_IDLEIEN_Msk /*!< IDLE interrupt enable */ +#define USART_CTRL1_RDBFIEN_Pos (5U) +#define USART_CTRL1_RDBFIEN_Msk (0x1U << USART_CTRL1_RDBFIEN_Pos) /*!< 0x00000020 */ +#define USART_CTRL1_RDBFIEN USART_CTRL1_RDBFIEN_Msk /*!< RDBF interrupt enable */ +#define USART_CTRL1_TDCIEN_Pos (6U) +#define USART_CTRL1_TDCIEN_Msk (0x1U << USART_CTRL1_TDCIEN_Pos) /*!< 0x00000040 */ +#define USART_CTRL1_TDCIEN USART_CTRL1_TDCIEN_Msk /*!< TDC interrupt enable */ +#define USART_CTRL1_TDBEIEN_Pos (7U) +#define USART_CTRL1_TDBEIEN_Msk (0x1U << USART_CTRL1_TDBEIEN_Pos) /*!< 0x00000080 */ +#define USART_CTRL1_TDBEIEN USART_CTRL1_TDBEIEN_Msk /*!< TDBE interrupt enable */ +#define USART_CTRL1_PERRIEN_Pos (8U) +#define USART_CTRL1_PERRIEN_Msk (0x1U << USART_CTRL1_PERRIEN_Pos) /*!< 0x00000100 */ +#define USART_CTRL1_PERRIEN USART_CTRL1_PERRIEN_Msk /*!< PERR interrupt enable */ +#define USART_CTRL1_PSEL_Pos (9U) +#define USART_CTRL1_PSEL_Msk (0x1U << USART_CTRL1_PSEL_Pos) /*!< 0x00000200 */ +#define USART_CTRL1_PSEL USART_CTRL1_PSEL_Msk /*!< Parity selection */ +#define USART_CTRL1_PEN_Pos (10U) +#define USART_CTRL1_PEN_Msk (0x1U << USART_CTRL1_PEN_Pos) /*!< 0x00000400 */ +#define USART_CTRL1_PEN USART_CTRL1_PEN_Msk /*!< Parity enable */ +#define USART_CTRL1_WUM_Pos (11U) +#define USART_CTRL1_WUM_Msk (0x1U << USART_CTRL1_WUM_Pos) /*!< 0x00000800 */ +#define USART_CTRL1_WUM USART_CTRL1_WUM_Msk /*!< Wakeup mode */ +#define USART_CTRL1_DBN0_Pos (12U) +#define USART_CTRL1_DBN0_Msk (0x1U << USART_CTRL1_DBN0_Pos) /*!< 0x00001000 */ +#define USART_CTRL1_DBN0 USART_CTRL1_DBN0_Msk /*!< Data bit num 0 */ +#define USART_CTRL1_UEN_Pos (13U) +#define USART_CTRL1_UEN_Msk (0x1U << USART_CTRL1_UEN_Pos) /*!< 0x00002000 */ +#define USART_CTRL1_UEN USART_CTRL1_UEN_Msk /*!< USART enable */ +#define USART_CTRL1_CMDIE_Pos (14U) +#define USART_CTRL1_CMDIE_Msk (0x1U << USART_CTRL1_CMDIE_Pos) /*!< 0x00004000 */ +#define USART_CTRL1_CMDIE USART_CTRL1_CMDIE_Msk /*!< Character match detection interrupt enable */ +#define USART_CTRL1_TCDT_Pos (16U) +#define USART_CTRL1_TCDT_Msk (0x1FU << USART_CTRL1_TCDT_Pos) /*!< 0x001F0000 */ +#define USART_CTRL1_TCDT USART_CTRL1_TCDT_Msk /*!< Transmit complete delay time */ +#define USART_CTRL1_TSDT_Pos (21U) +#define USART_CTRL1_TSDT_Msk (0x1FU << USART_CTRL1_TSDT_Pos) /*!< 0x03E00000 */ +#define USART_CTRL1_TSDT USART_CTRL1_TSDT_Msk /*!< Transmit start delay time */ +#define USART_CTRL1_RETODIE_Pos (26U) +#define USART_CTRL1_RETODIE_Msk (0x1U << USART_CTRL1_RETODIE_Pos) /*!< 0x04000000 */ +#define USART_CTRL1_RETODIE USART_CTRL1_RETODIE_Msk /*!< Receiver timeout detection interrupt enable */ +#define USART_CTRL1_RTODEN_Pos (27U) +#define USART_CTRL1_RTODEN_Msk (0x1U << USART_CTRL1_RTODEN_Pos) /*!< 0x08000000 */ +#define USART_CTRL1_RTODEN USART_CTRL1_RTODEN_Msk /*!< Receiver timeout detection enable */ +#define USART_CTRL1_DBN1_Pos (28U) +#define USART_CTRL1_DBN1_Msk (0x1U << USART_CTRL1_DBN1_Pos) /*!< 0x10000000 */ +#define USART_CTRL1_DBN1 USART_CTRL1_DBN1_Msk /*!< Data bit num 1 */ + +/***************** Bit definition for USART_CTRL2 register ******************/ +#define USART_CTRL2_IDL_Pos (0U) +#define USART_CTRL2_IDL_Msk (0xFU << USART_CTRL2_IDL_Pos) /*!< 0x0000000F */ +#define USART_CTRL2_IDL USART_CTRL2_IDL_Msk /*!< USART identification low */ +#define USART_CTRL2_IDBN_Pos (4U) +#define USART_CTRL2_IDBN_Msk (0x1U << USART_CTRL2_IDBN_Pos) /*!< 0x00000010 */ +#define USART_CTRL2_IDBN USART_CTRL2_IDBN_Msk /*!< Identification bit number */ +#define USART_CTRL2_BFBN_Pos (5U) +#define USART_CTRL2_BFBN_Msk (0x1U << USART_CTRL2_BFBN_Pos) /*!< 0x00000020 */ +#define USART_CTRL2_BFBN USART_CTRL2_BFBN_Msk /*!< Break frame bit num */ +#define USART_CTRL2_BFIEN_Pos (6U) +#define USART_CTRL2_BFIEN_Msk (0x1U << USART_CTRL2_BFIEN_Pos) /*!< 0x00000040 */ +#define USART_CTRL2_BFIEN USART_CTRL2_BFIEN_Msk /*!< Break frame interrupt enable */ +#define USART_CTRL2_LBCP_Pos (8U) +#define USART_CTRL2_LBCP_Msk (0x1U << USART_CTRL2_LBCP_Pos) /*!< 0x00000100 */ +#define USART_CTRL2_LBCP USART_CTRL2_LBCP_Msk /*!< Last bit clock pulse */ +#define USART_CTRL2_CLKPHA_Pos (9U) +#define USART_CTRL2_CLKPHA_Msk (0x1U << USART_CTRL2_CLKPHA_Pos) /*!< 0x00000200 */ +#define USART_CTRL2_CLKPHA USART_CTRL2_CLKPHA_Msk /*!< Clock phase */ +#define USART_CTRL2_CLKPOL_Pos (10U) +#define USART_CTRL2_CLKPOL_Msk (0x1U << USART_CTRL2_CLKPOL_Pos) /*!< 0x00000400 */ +#define USART_CTRL2_CLKPOL USART_CTRL2_CLKPOL_Msk /*!< Clock polarity */ +#define USART_CTRL2_CLKEN_Pos (11U) +#define USART_CTRL2_CLKEN_Msk (0x1U << USART_CTRL2_CLKEN_Pos) /*!< 0x00000800 */ +#define USART_CTRL2_CLKEN USART_CTRL2_CLKEN_Msk /*!< Clock enable */ + +/*!< STOPBN configuration */ +#define USART_CTRL2_STOPBN_Pos (12U) +#define USART_CTRL2_STOPBN_Msk (0x3U << USART_CTRL2_STOPBN_Pos) /*!< 0x00003000 */ +#define USART_CTRL2_STOPBN USART_CTRL2_STOPBN_Msk /*!< STOPBN[1:0] bits (STOP bit num) */ +#define USART_CTRL2_STOPBN_0 (0x1U << USART_CTRL2_STOPBN_Pos) /*!< 0x00001000 */ +#define USART_CTRL2_STOPBN_1 (0x2U << USART_CTRL2_STOPBN_Pos) /*!< 0x00002000 */ + +#define USART_CTRL2_LINEN_Pos (14U) +#define USART_CTRL2_LINEN_Msk (0x1U << USART_CTRL2_LINEN_Pos) /*!< 0x00004000 */ +#define USART_CTRL2_LINEN USART_CTRL2_LINEN_Msk /*!< LIN mode enable */ +#define USART_CTRL2_TRPSWAP_Pos (15U) +#define USART_CTRL2_TRPSWAP_Msk (0x1U << USART_CTRL2_TRPSWAP_Pos) /*!< 0x00008000 */ +#define USART_CTRL2_TRPSWAP USART_CTRL2_TRPSWAP_Msk /*!< Transmit/receive pin swap */ +#define USART_CTRL2_RXREV_Pos (16U) +#define USART_CTRL2_RXREV_Msk (0x1U << USART_CTRL2_RXREV_Pos) /*!< 0x00010000 */ +#define USART_CTRL2_RXREV USART_CTRL2_RXREV_Msk /*!< RX polarity reverse */ +#define USART_CTRL2_TXREV_Pos (17U) +#define USART_CTRL2_TXREV_Msk (0x1U << USART_CTRL2_TXREV_Pos) /*!< 0x00020000 */ +#define USART_CTRL2_TXREV USART_CTRL2_TXREV_Msk /*!< TX polarity reverse */ +#define USART_CTRL2_DTREV_Pos (18U) +#define USART_CTRL2_DTREV_Msk (0x1U << USART_CTRL2_DTREV_Pos) /*!< 0x00040000 */ +#define USART_CTRL2_DTREV USART_CTRL2_DTREV_Msk /*!< DT register polarity reverse */ +#define USART_CTRL2_MTF_Pos (19U) +#define USART_CTRL2_MTF_Msk (0x1U << USART_CTRL2_MTF_Pos) /*!< 0x00080000 */ +#define USART_CTRL2_MTF USART_CTRL2_MTF_Msk /*!< MSB transmit first */ +#define USART_CTRL2_IDH_Pos (28U) +#define USART_CTRL2_IDH_Msk (0xFU << USART_CTRL2_IDH_Pos) /*!< 0xF0000000 */ +#define USART_CTRL2_IDH USART_CTRL2_IDH_Msk /*!< USART identification high */ + +/***************** Bit definition for USART_CTRL3 register ******************/ +#define USART_CTRL3_ERRIEN_Pos (0U) +#define USART_CTRL3_ERRIEN_Msk (0x1U << USART_CTRL3_ERRIEN_Pos) /*!< 0x00000001 */ +#define USART_CTRL3_ERRIEN USART_CTRL3_ERRIEN_Msk /*!< Error interrupt enable */ +#define USART_CTRL3_IRDAEN_Pos (1U) +#define USART_CTRL3_IRDAEN_Msk (0x1U << USART_CTRL3_IRDAEN_Pos) /*!< 0x00000002 */ +#define USART_CTRL3_IRDAEN USART_CTRL3_IRDAEN_Msk /*!< IrDA enable */ +#define USART_CTRL3_IRDALP_Pos (2U) +#define USART_CTRL3_IRDALP_Msk (0x1U << USART_CTRL3_IRDALP_Pos) /*!< 0x00000004 */ +#define USART_CTRL3_IRDALP USART_CTRL3_IRDALP_Msk /*!< IrDA low-power mode */ +#define USART_CTRL3_SLBEN_Pos (3U) +#define USART_CTRL3_SLBEN_Msk (0x1U << USART_CTRL3_SLBEN_Pos) /*!< 0x00000008 */ +#define USART_CTRL3_SLBEN USART_CTRL3_SLBEN_Msk /*!< Single-wire bidirectional half-duplex enable */ +#define USART_CTRL3_SCNACKEN_Pos (4U) +#define USART_CTRL3_SCNACKEN_Msk (0x1U << USART_CTRL3_SCNACKEN_Pos) /*!< 0x00000010 */ +#define USART_CTRL3_SCNACKEN USART_CTRL3_SCNACKEN_Msk /*!< Smart Card NACK enable */ +#define USART_CTRL3_SCMEN_Pos (5U) +#define USART_CTRL3_SCMEN_Msk (0x1U << USART_CTRL3_SCMEN_Pos) /*!< 0x00000020 */ +#define USART_CTRL3_SCMEN USART_CTRL3_SCMEN_Msk /*!< Smart Card mode enable */ +#define USART_CTRL3_DMAREN_Pos (6U) +#define USART_CTRL3_DMAREN_Msk (0x1U << USART_CTRL3_DMAREN_Pos) /*!< 0x00000040 */ +#define USART_CTRL3_DMAREN USART_CTRL3_DMAREN_Msk /*!< DMA receiver enable */ +#define USART_CTRL3_DMATEN_Pos (7U) +#define USART_CTRL3_DMATEN_Msk (0x1U << USART_CTRL3_DMATEN_Pos) /*!< 0x00000080 */ +#define USART_CTRL3_DMATEN USART_CTRL3_DMATEN_Msk /*!< DMA transmitter enable */ +#define USART_CTRL3_RTSEN_Pos (8U) +#define USART_CTRL3_RTSEN_Msk (0x1U << USART_CTRL3_RTSEN_Pos) /*!< 0x00000100 */ +#define USART_CTRL3_RTSEN USART_CTRL3_RTSEN_Msk /*!< RTS enable */ +#define USART_CTRL3_CTSEN_Pos (9U) +#define USART_CTRL3_CTSEN_Msk (0x1U << USART_CTRL3_CTSEN_Pos) /*!< 0x00000200 */ +#define USART_CTRL3_CTSEN USART_CTRL3_CTSEN_Msk /*!< CTS enable */ +#define USART_CTRL3_CTSCFIEN_Pos (10U) +#define USART_CTRL3_CTSCFIEN_Msk (0x1U << USART_CTRL3_CTSCFIEN_Pos) /*!< 0x00000400 */ +#define USART_CTRL3_CTSCFIEN USART_CTRL3_CTSCFIEN_Msk /*!< CTSCF interrupt enable */ +#define USART_CTRL3_RS485EN_Pos (14U) +#define USART_CTRL3_RS485EN_Msk (0x1U << USART_CTRL3_RS485EN_Pos) /*!< 0x00004000 */ +#define USART_CTRL3_RS485EN USART_CTRL3_RS485EN_Msk /*!< RS485 enable */ +#define USART_CTRL3_DEP_Pos (15U) +#define USART_CTRL3_DEP_Msk (0x1U << USART_CTRL3_DEP_Pos) /*!< 0x00008000 */ +#define USART_CTRL3_DEP USART_CTRL3_DEP_Msk /*!< DE polarity selection */ + +/****************** Bit definition for USART_GDIV register ******************/ +/*!< ISDIV configuration */ +#define USART_GDIV_ISDIV_Pos (0U) +#define USART_GDIV_ISDIV_Msk (0xFFU << USART_GDIV_ISDIV_Pos) /*!< 0x000000FF */ +#define USART_GDIV_ISDIV USART_GDIV_ISDIV_Msk /*!< ISDIV[7:0] bits (IrDA/Smart Card division) */ +#define USART_GDIV_ISDIV_0 (0x01U << USART_GDIV_ISDIV_Pos) /*!< 0x00000001 */ +#define USART_GDIV_ISDIV_1 (0x02U << USART_GDIV_ISDIV_Pos) /*!< 0x00000002 */ +#define USART_GDIV_ISDIV_2 (0x04U << USART_GDIV_ISDIV_Pos) /*!< 0x00000004 */ +#define USART_GDIV_ISDIV_3 (0x08U << USART_GDIV_ISDIV_Pos) /*!< 0x00000008 */ +#define USART_GDIV_ISDIV_4 (0x10U << USART_GDIV_ISDIV_Pos) /*!< 0x00000010 */ +#define USART_GDIV_ISDIV_5 (0x20U << USART_GDIV_ISDIV_Pos) /*!< 0x00000020 */ +#define USART_GDIV_ISDIV_6 (0x40U << USART_GDIV_ISDIV_Pos) /*!< 0x00000040 */ +#define USART_GDIV_ISDIV_7 (0x80U << USART_GDIV_ISDIV_Pos) /*!< 0x00000080 */ + +#define USART_GDIV_SCGT_Pos (8U) +#define USART_GDIV_SCGT_Msk (0xFFU << USART_GDIV_SCGT_Pos) /*!< 0x0000FF00 */ +#define USART_GDIV_SCGT USART_GDIV_SCGT_Msk /*!< Smart Card guard time value */ + +/****************** Bit definition for USART_RTOV register ******************/ +#define USART_RTOV_RTOV_Pos (0U) +#define USART_RTOV_RTOV_Msk (0xFFFFFFU << USART_RTOV_RTOV_Pos) /*!< 0x00FFFFFF */ +#define USART_RTOV_RTOV USART_RTOV_RTOV_Msk /*!< Receiver timeout value */ + +/****************** Bit definition for USART_IFC register *******************/ +#define USART_IFC_RTODFC_Pos (11U) +#define USART_IFC_RTODFC_Msk (0x1U << USART_IFC_RTODFC_Pos) /*!< 0x00000800 */ +#define USART_IFC_RTODFC USART_IFC_RTODFC_Msk /*!< Receiver timeout detection flag clear */ +#define USART_IFC_CMDFC_Pos (17U) +#define USART_IFC_CMDFC_Msk (0x1U << USART_IFC_CMDFC_Pos) /*!< 0x00020000 */ +#define USART_IFC_CMDFC USART_IFC_CMDFC_Msk /*!< Character match detection flag clear */ + +/******************************************************************************/ +/* */ +/* Serial peripheral interface (SPI) */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for SPI_CTRL1 register *******************/ +#define SPI_CTRL1_CLKPHA_Pos (0U) +#define SPI_CTRL1_CLKPHA_Msk (0x1U << SPI_CTRL1_CLKPHA_Pos) /*!< 0x00000001 */ +#define SPI_CTRL1_CLKPHA SPI_CTRL1_CLKPHA_Msk /*!< Clock phase */ +#define SPI_CTRL1_CLKPOL_Pos (1U) +#define SPI_CTRL1_CLKPOL_Msk (0x1U << SPI_CTRL1_CLKPOL_Pos) /*!< 0x00000002 */ +#define SPI_CTRL1_CLKPOL SPI_CTRL1_CLKPOL_Msk /*!< Clock polarity */ +#define SPI_CTRL1_MSTEN_Pos (2U) +#define SPI_CTRL1_MSTEN_Msk (0x1U << SPI_CTRL1_MSTEN_Pos) /*!< 0x00000004 */ +#define SPI_CTRL1_MSTEN SPI_CTRL1_MSTEN_Msk /*!< Master enable */ + +/*!< MDIV configuration */ +#define SPI_CTRL1_MDIV_Msk ((SPI_CTRL2_MDIV) | (0x7U << 3) /*!< 0x00000138 */ +#define SPI_CTRL1_MDIV SPI_CTRL1_MDIV_Msk /*!< MDIV[3:0] bits (Master clock frequency division) */ +#define SPI_CTRL1_MDIV_0 (0x1U << 3) /*!< 0x00000008 */ +#define SPI_CTRL1_MDIV_1 (0x2U << 3) /*!< 0x00000010 */ +#define SPI_CTRL1_MDIV_2 (0x4U << 3) /*!< 0x00000020 */ +#define SPI_CTRL1_MDIV_3 SPI_CTRL2_MDIV /*!< 0x00000100 */ + +#define SPI_CTRL1_SPIEN_Pos (6U) +#define SPI_CTRL1_SPIEN_Msk (0x1U << SPI_CTRL1_SPIEN_Pos) /*!< 0x00000040 */ +#define SPI_CTRL1_SPIEN SPI_CTRL1_SPIEN_Msk /*!< SPI enable */ +#define SPI_CTRL1_LTF_Pos (7U) +#define SPI_CTRL1_LTF_Msk (0x1U << SPI_CTRL1_LTF_Pos) /*!< 0x00000080 */ +#define SPI_CTRL1_LTF SPI_CTRL1_LTF_Msk /*!< LSB transmit first */ +#define SPI_CTRL1_SWCSIL_Pos (8U) +#define SPI_CTRL1_SWCSIL_Msk (0x1U << SPI_CTRL1_SWCSIL_Pos) /*!< 0x00000100 */ +#define SPI_CTRL1_SWCSIL SPI_CTRL1_SWCSIL_Msk /*!< Software CS internal level */ +#define SPI_CTRL1_SWCSEN_Pos (9U) +#define SPI_CTRL1_SWCSEN_Msk (0x1U << SPI_CTRL1_SWCSEN_Pos) /*!< 0x00000200 */ +#define SPI_CTRL1_SWCSEN SPI_CTRL1_SWCSEN_Msk /*!< Software CS enable */ +#define SPI_CTRL1_ORA_Pos (10U) +#define SPI_CTRL1_ORA_Msk (0x1U << SPI_CTRL1_ORA_Pos) /*!< 0x00000400 */ +#define SPI_CTRL1_ORA SPI_CTRL1_ORA_Msk /*!< Receive-only active */ +#define SPI_CTRL1_FBN_Pos (11U) +#define SPI_CTRL1_FBN_Msk (0x1U << SPI_CTRL1_FBN_Pos) /*!< 0x00000800 */ +#define SPI_CTRL1_FBN SPI_CTRL1_FBN_Msk /*!< Frame bit num */ +#define SPI_CTRL1_NTC_Pos (12U) +#define SPI_CTRL1_NTC_Msk (0x1U << SPI_CTRL1_NTC_Pos) /*!< 0x00001000 */ +#define SPI_CTRL1_NTC SPI_CTRL1_NTC_Msk /*!< Transmit CRC next */ +#define SPI_CTRL1_CCEN_Pos (13U) +#define SPI_CTRL1_CCEN_Msk (0x1U << SPI_CTRL1_CCEN_Pos) /*!< 0x00002000 */ +#define SPI_CTRL1_CCEN SPI_CTRL1_CCEN_Msk /*!< RC calculation enable */ +#define SPI_CTRL1_SLBTD_Pos (14U) +#define SPI_CTRL1_SLBTD_Msk (0x1U << SPI_CTRL1_SLBTD_Pos) /*!< 0x00004000 */ +#define SPI_CTRL1_SLBTD SPI_CTRL1_SLBTD_Msk /*!< Single line bidirectional half-duplex transmission direction */ +#define SPI_CTRL1_SLBEN_Pos (15U) +#define SPI_CTRL1_SLBEN_Msk (0x1U << SPI_CTRL1_SLBEN_Pos) /*!< 0x00008000 */ +#define SPI_CTRL1_SLBEN SPI_CTRL1_SLBEN_Msk /*!< Single line bidirectional half-duplex enable */ + +/****************** Bit definition for SPI_CTRL2 register *******************/ +#define SPI_CTRL2_DMAREN_Pos (0U) +#define SPI_CTRL2_DMAREN_Msk (0x1U << SPI_CTRL2_DMAREN_Pos) /*!< 0x00000001 */ +#define SPI_CTRL2_DMAREN SPI_CTRL2_DMAREN_Msk /*!< DMA receive enable */ +#define SPI_CTRL2_DMATEN_Pos (1U) +#define SPI_CTRL2_DMATEN_Msk (0x1U << SPI_CTRL2_DMATEN_Pos) /*!< 0x00000002 */ +#define SPI_CTRL2_DMATEN SPI_CTRL2_DMATEN_Msk /*!< DMA transmit enable */ +#define SPI_CTRL2_HWCSOE_Pos (2U) +#define SPI_CTRL2_HWCSOE_Msk (0x1U << SPI_CTRL2_HWCSOE_Pos) /*!< 0x00000004 */ +#define SPI_CTRL2_HWCSOE SPI_CTRL2_HWCSOE_Msk /*!< Hardware CS output enable */ +#define SPI_CTRL2_TIEN_Pos (4U) +#define SPI_CTRL2_TIEN_Msk (0x1U << SPI_CTRL2_TIEN_Pos) /*!< 0x00000010 */ +#define SPI_CTRL2_TIEN SPI_CTRL2_TIEN_Msk /*!< TI mode enable */ +#define SPI_CTRL2_ERRIE_Pos (5U) +#define SPI_CTRL2_ERRIE_Msk (0x1U << SPI_CTRL2_ERRIE_Pos) /*!< 0x00000020 */ +#define SPI_CTRL2_ERRIE SPI_CTRL2_ERRIE_Msk /*!< Error interrupt enable */ +#define SPI_CTRL2_RDBFIE_Pos (6U) +#define SPI_CTRL2_RDBFIE_Msk (0x1U << SPI_CTRL2_RDBFIE_Pos) /*!< 0x00000040 */ +#define SPI_CTRL2_RDBFIE SPI_CTRL2_RDBFIE_Msk /*!< Receive data buffer full interrupt enable */ +#define SPI_CTRL2_TDBEIE_Pos (7U) +#define SPI_CTRL2_TDBEIE_Msk (0x1U << SPI_CTRL2_TDBEIE_Pos) /*!< 0x00000080 */ +#define SPI_CTRL2_TDBEIE SPI_CTRL2_TDBEIE_Msk /*!< Transmit data buffer empty interrupt enable */ +#define SPI_CTRL2_MDIV_Pos (8U) +#define SPI_CTRL2_MDIV_Msk (0x1U << SPI_CTRL2_MDIV_Pos) /*!< 0x00000100 */ +#define SPI_CTRL2_MDIV SPI_CTRL2_MDIV_Msk /*!< Master clock frequency division */ +#define SPI_CTRL2_MDIV3EN_Pos (9U) +#define SPI_CTRL2_MDIV3EN_Msk (0x1U << SPI_CTRL2_MDIV3EN_Pos) /*!< 0x00000200 */ +#define SPI_CTRL2_MDIV3EN SPI_CTRL2_MDIV3EN_Msk /*!< Master clock frequency divided by 3 enable */ + +/******************* Bit definition for SPI_STS register ********************/ +#define SPI_STS_RDBF_Pos (0U) +#define SPI_STS_RDBF_Msk (0x1U << SPI_STS_RDBF_Pos) /*!< 0x00000001 */ +#define SPI_STS_RDBF SPI_STS_RDBF_Msk /*!< Receive data buffer full */ +#define SPI_STS_TDBE_Pos (1U) +#define SPI_STS_TDBE_Msk (0x1U << SPI_STS_TDBE_Pos) /*!< 0x00000002 */ +#define SPI_STS_TDBE SPI_STS_TDBE_Msk /*!< Transmit data buffer empty */ +#define SPI_STS_ACS_Pos (2U) +#define SPI_STS_ACS_Msk (0x1U << SPI_STS_ACS_Pos) /*!< 0x00000004 */ +#define SPI_STS_ACS SPI_STS_ACS_Msk /*!< Audio channel state */ +#define SPI_STS_TUERR_Pos (3U) +#define SPI_STS_TUERR_Msk (0x1U << SPI_STS_TUERR_Pos) /*!< 0x00000008 */ +#define SPI_STS_TUERR SPI_STS_TUERR_Msk /*!< Transmitter underload error */ +#define SPI_STS_CCERR_Pos (4U) +#define SPI_STS_CCERR_Msk (0x1U << SPI_STS_CCERR_Pos) /*!< 0x00000010 */ +#define SPI_STS_CCERR SPI_STS_CCERR_Msk /*!< CRC error */ +#define SPI_STS_MMERR_Pos (5U) +#define SPI_STS_MMERR_Msk (0x1U << SPI_STS_MMERR_Pos) /*!< 0x00000020 */ +#define SPI_STS_MMERR SPI_STS_MMERR_Msk /*!< Master mode error */ +#define SPI_STS_ROERR_Pos (6U) +#define SPI_STS_ROERR_Msk (0x1U << SPI_STS_ROERR_Pos) /*!< 0x00000040 */ +#define SPI_STS_ROERR SPI_STS_ROERR_Msk /*!< Receiver overflow error */ +#define SPI_STS_BF_Pos (7U) +#define SPI_STS_BF_Msk (0x1U << SPI_STS_BF_Pos) /*!< 0x00000080 */ +#define SPI_STS_BF SPI_STS_BF_Msk /*!< Busy flag */ +#define SPI_STS_CSPAS_Pos (8U) +#define SPI_STS_CSPAS_Msk (0x1U << SPI_STS_CSPAS_Pos) /*!< 0x00000100 */ +#define SPI_STS_CSPAS SPI_STS_CSPAS_Msk /*!< CS pulse abnormal setting flag */ + +/******************** Bit definition for SPI_DT register ********************/ +#define SPI_DT_DT_Pos (0U) +#define SPI_DT_DT_Msk (0xFFFFU << SPI_DT_DT_Pos) /*!< 0x0000FFFF */ +#define SPI_DT_DT SPI_DT_DT_Msk /*!< Data value */ + +/******************* Bit definition for SPI_CPOLY register ******************/ +#define SPI_CPOLY_CPOLY_Pos (0U) +#define SPI_CPOLY_CPOLY_Msk (0xFFFFU << SPI_CPOLY_CPOLY_Pos) /*!< 0x0000FFFF */ +#define SPI_CPOLY_CPOLY SPI_CPOLY_CPOLY_Msk /*!< CRC polynomial */ + +/******************* Bit definition for SPI_RCRC register *******************/ +#define SPI_RCRC_RCRC_Pos (0U) +#define SPI_RCRC_RCRC_Msk (0xFFFFU << SPI_RCRC_RCRC_Pos) /*!< 0x0000FFFF */ +#define SPI_RCRC_RCRC SPI_RCRC_RCRC_Msk /*!< Receive CRC */ + +/******************* Bit definition for SPI_TCRC register *******************/ +#define SPI_TCRC_TCRC_Pos (0U) +#define SPI_TCRC_TCRC_Msk (0xFFFFU << SPI_TCRC_TCRC_Pos) /*!< 0x0000FFFF */ +#define SPI_TCRC_TCRC SPI_TCRC_TCRC_Msk /*!< Transmit CRC */ + +/***************** Bit definition for SPI_I2SCTRL register ******************/ +#define SPI_I2SCTRL_I2SCBN_Pos (0U) +#define SPI_I2SCTRL_I2SCBN_Msk (0x1U << SPI_I2SCTRL_I2SCBN_Pos) /*!< 0x00000001 */ +#define SPI_I2SCTRL_I2SCBN SPI_I2SCTRL_I2SCBN_Msk /*!< Channel length (I2S channel bit num) */ + +/*!< I2SDBN configuration */ +#define SPI_I2SCTRL_I2SDBN_Pos (1U) +#define SPI_I2SCTRL_I2SDBN_Msk (0x3U << SPI_I2SCTRL_I2SDBN_Pos) /*!< 0x00000006 */ +#define SPI_I2SCTRL_I2SDBN SPI_I2SCTRL_I2SDBN_Msk /*!< I2SDBN[1:0] bits (I2S data bit num) */ +#define SPI_I2SCTRL_I2SDBN_0 (0x1U << SPI_I2SCTRL_I2SDBN_Pos) /*!< 0x00000002 */ +#define SPI_I2SCTRL_I2SDBN_1 (0x2U << SPI_I2SCTRL_I2SDBN_Pos) /*!< 0x00000004 */ + +#define SPI_I2SCTRL_I2SCLKPOL_Pos (3U) +#define SPI_I2SCTRL_I2SCLKPOL_Msk (0x1U << SPI_I2SCTRL_I2SCLKPOL_Pos) /*!< 0x00000008 */ +#define SPI_I2SCTRL_I2SCLKPOL SPI_I2SCTRL_I2SCLKPOL_Msk /*!< I2S clock polarity */ + +/*!< STDSEL configuration */ +#define SPI_I2SCTRL_STDSEL_Pos (4U) +#define SPI_I2SCTRL_STDSEL_Msk (0x3U << SPI_I2SCTRL_STDSEL_Pos) /*!< 0x00000030 */ +#define SPI_I2SCTRL_STDSEL SPI_I2SCTRL_STDSEL_Msk /*!< STDSEL[1:0] bits (I2S standard select) */ +#define SPI_I2SCTRL_STDSEL_0 (0x1U << SPI_I2SCTRL_STDSEL_Pos) /*!< 0x00000010 */ +#define SPI_I2SCTRL_STDSEL_1 (0x2U << SPI_I2SCTRL_STDSEL_Pos) /*!< 0x00000020 */ + +#define SPI_I2SCTRL_PCMFSSEL_Pos (7U) +#define SPI_I2SCTRL_PCMFSSEL_Msk (0x1U << SPI_I2SCTRL_PCMFSSEL_Pos) /*!< 0x00000080 */ +#define SPI_I2SCTRL_PCMFSSEL SPI_I2SCTRL_PCMFSSEL_Msk /*!< PCM frame synchronization */ + +/*!< OPERSEL configuration */ +#define SPI_I2SCTRL_OPERSEL_Pos (8U) +#define SPI_I2SCTRL_OPERSEL_Msk (0x3U << SPI_I2SCTRL_OPERSEL_Pos) /*!< 0x00000300 */ +#define SPI_I2SCTRL_OPERSEL SPI_I2SCTRL_OPERSEL_Msk /*!< OPERSEL[1:0] bits (I2S operation mode select) */ +#define SPI_I2SCTRL_OPERSEL_0 (0x1U << SPI_I2SCTRL_OPERSEL_Pos) /*!< 0x00000100 */ +#define SPI_I2SCTRL_OPERSEL_1 (0x2U << SPI_I2SCTRL_OPERSEL_Pos) /*!< 0x00000200 */ + +#define SPI_I2SCTRL_I2SEN_Pos (10U) +#define SPI_I2SCTRL_I2SEN_Msk (0x1U << SPI_I2SCTRL_I2SEN_Pos) /*!< 0x00000400 */ +#define SPI_I2SCTRL_I2SEN SPI_I2SCTRL_I2SEN_Msk /*!< I2S enable */ +#define SPI_I2SCTRL_I2SMSEL_Pos (11U) +#define SPI_I2SCTRL_I2SMSEL_Msk (0x1U << SPI_I2SCTRL_I2SMSEL_Pos) /*!< 0x00000800 */ +#define SPI_I2SCTRL_I2SMSEL SPI_I2SCTRL_I2SMSEL_Msk /*!< I2S mode select */ +#define SPI_I2SCTRL_I2SFDUPEN_Pos (13U) +#define SPI_I2SCTRL_I2SFDUPEN_Msk (0x1U << SPI_I2SCTRL_I2SFDUPEN_Pos) /*!< 0x00002000 */ +#define SPI_I2SCTRL_I2SFDUPEN SPI_I2SCTRL_I2SFDUPEN_Msk /*!< I2S full duplex enable */ + +/***************** Bit definition for SPI_I2SCLKP register ******************/ +#define SPI_I2SCLKP_I2SDIV_Msk ((0xFFU << 0) | (0x3U << 10)) /*!< 0x00000CFF */ +#define SPI_I2SCLKP_I2SDIV SPI_I2SCLKP_I2SDIV_Msk /*!< I2SDIV[9:0] bits (I2S division) */ +#define SPI_I2SCLKP_I2SODD_Pos (8U) +#define SPI_I2SCLKP_I2SODD_Msk (0x1U << SPI_I2SCLKP_I2SODD_Pos) /*!< 0x00000100 */ +#define SPI_I2SCLKP_I2SODD SPI_I2SCLKP_I2SODD_Msk /*!< Odd factor for I2S division */ +#define SPI_I2SCLKP_I2SMCLKOE_Pos (9U) +#define SPI_I2SCLKP_I2SMCLKOE_Msk (0x1U << SPI_I2SCLKP_I2SMCLKOE_Pos) /*!< 0x00000200 */ +#define SPI_I2SCLKP_I2SMCLKOE SPI_I2SCLKP_I2SMCLKOE_Msk /*!< I2S Master clock output enable */ + +/****************** Bit definition for SPI_MISC1 register *******************/ +#define SPI_MISC1_I2SFPCMCKSEL_Pos (0U) +#define SPI_MISC1_I2SFPCMCKSEL_Msk (0x1U << SPI_MISC1_I2SFPCMCKSEL_Pos) /*!< 0x00000001 */ +#define SPI_MISC1_I2SFPCMCKSEL SPI_MISC1_I2SFPCMCKSEL_Msk /*!< I2S PCM clock edge select */ + +/******************************************************************************/ +/* */ +/* Window watchdog timer (WWDT) */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for WWDT_CTRL register *******************/ +/*!< CNT configuration */ +#define WWDT_CTRL_CNT_Pos (0U) +#define WWDT_CTRL_CNT_Msk (0x7FU << WWDT_CTRL_CNT_Pos) /*!< 0x0000007F */ +#define WWDT_CTRL_CNT WWDT_CTRL_CNT_Msk /*!< CNT[6:0] bits (Down counter) */ +#define WWDT_CTRL_CNT_0 (0x01U << WWDT_CTRL_CNT_Pos) /*!< 0x00000001 */ +#define WWDT_CTRL_CNT_1 (0x02U << WWDT_CTRL_CNT_Pos) /*!< 0x00000002 */ +#define WWDT_CTRL_CNT_2 (0x04U << WWDT_CTRL_CNT_Pos) /*!< 0x00000004 */ +#define WWDT_CTRL_CNT_3 (0x08U << WWDT_CTRL_CNT_Pos) /*!< 0x00000008 */ +#define WWDT_CTRL_CNT_4 (0x10U << WWDT_CTRL_CNT_Pos) /*!< 0x00000010 */ +#define WWDT_CTRL_CNT_5 (0x20U << WWDT_CTRL_CNT_Pos) /*!< 0x00000020 */ +#define WWDT_CTRL_CNT_6 (0x40U << WWDT_CTRL_CNT_Pos) /*!< 0x00000040 */ + +/* Legacy defines */ +#define WWDT_CTRL_CNT0 WWDT_CTRL_CNT_0 +#define WWDT_CTRL_CNT1 WWDT_CTRL_CNT_1 +#define WWDT_CTRL_CNT2 WWDT_CTRL_CNT_2 +#define WWDT_CTRL_CNT3 WWDT_CTRL_CNT_3 +#define WWDT_CTRL_CNT4 WWDT_CTRL_CNT_4 +#define WWDT_CTRL_CNT5 WWDT_CTRL_CNT_5 +#define WWDT_CTRL_CNT6 WWDT_CTRL_CNT_6 + +#define WWDT_CTRL_WWDTEN_Pos (7U) +#define WWDT_CTRL_WWDTEN_Msk (0x1U << WWDT_CTRL_WWDTEN_Pos) /*!< 0x00000080 */ +#define WWDT_CTRL_WWDTEN WWDT_CTRL_WWDTEN_Msk /*!< Window watchdog enable */ + +/******************* Bit definition for WWDT_CFG register *******************/ +/*!< WIN configuration */ +#define WWDT_CFG_WIN_Pos (0U) +#define WWDT_CFG_WIN_Msk (0x7FU << WWDT_CFG_WIN_Pos) /*!< 0x0000007F */ +#define WWDT_CFG_WIN WWDT_CFG_WIN_Msk /*!< WIN[6:0] bits (Window value) */ +#define WWDT_CFG_WIN_0 (0x01U << WWDT_CFG_WIN_Pos) /*!< 0x00000001 */ +#define WWDT_CFG_WIN_1 (0x02U << WWDT_CFG_WIN_Pos) /*!< 0x00000002 */ +#define WWDT_CFG_WIN_2 (0x04U << WWDT_CFG_WIN_Pos) /*!< 0x00000004 */ +#define WWDT_CFG_WIN_3 (0x08U << WWDT_CFG_WIN_Pos) /*!< 0x00000008 */ +#define WWDT_CFG_WIN_4 (0x10U << WWDT_CFG_WIN_Pos) /*!< 0x00000010 */ +#define WWDT_CFG_WIN_5 (0x20U << WWDT_CFG_WIN_Pos) /*!< 0x00000020 */ +#define WWDT_CFG_WIN_6 (0x40U << WWDT_CFG_WIN_Pos) /*!< 0x00000040 */ + +/* Legacy defines */ +#define WWDT_CFG_WIN0 WWDT_CFG_WIN_0 +#define WWDT_CFG_WIN1 WWDT_CFG_WIN_1 +#define WWDT_CFG_WIN2 WWDT_CFG_WIN_2 +#define WWDT_CFG_WIN3 WWDT_CFG_WIN_3 +#define WWDT_CFG_WIN4 WWDT_CFG_WIN_4 +#define WWDT_CFG_WIN5 WWDT_CFG_WIN_5 +#define WWDT_CFG_WIN6 WWDT_CFG_WIN_6 + +/*!< DIV configuration */ +#define WWDT_CFG_DIV_Pos (7U) +#define WWDT_CFG_DIV_Msk (0x3U << WWDT_CFG_DIV_Pos) /*!< 0x00000180 */ +#define WWDT_CFG_DIV WWDT_CFG_DIV_Msk /*!< DIV[1:0] bits (Clock division value) */ +#define WWDT_CFG_DIV_0 (0x1U << WWDT_CFG_DIV_Pos) /*!< 0x00000080 */ +#define WWDT_CFG_DIV_1 (0x2U << WWDT_CFG_DIV_Pos) /*!< 0x00000100 */ + +/* Legacy defines */ +#define WWDT_CFG_DIV0 WWDT_CFG_DIV_0 +#define WWDT_CFG_DIV1 WWDT_CFG_DIV_1 + +#define WWDT_CFG_RLDIEN_Pos (9U) +#define WWDT_CFG_RLDIEN_Msk (0x1U << WWDT_CFG_RLDIEN_Pos) /*!< 0x00000200 */ +#define WWDT_CFG_RLDIEN WWDT_CFG_RLDIEN_Msk /*!< Reload counter interrupt */ + +/******************* Bit definition for WWDT_STS register *******************/ +#define WWDT_STS_RLDF_Pos (0U) +#define WWDT_STS_RLDF_Msk (0x1U << WWDT_STS_RLDF_Pos) /*!< 0x00000001 */ +#define WWDT_STS_RLDF WWDT_STS_RLDF_Msk /*!< Reload counter interrupt flag */ + +/******************************************************************************/ +/* */ +/* Watchdog timer (WDT) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for WDT_CMD register ********************/ +#define WDT_CMD_CMD_Pos (0U) +#define WDT_CMD_CMD_Msk (0xFFFFU << WDT_CMD_CMD_Pos) /*!< 0x0000FFFF */ +#define WDT_CMD_CMD WDT_CMD_CMD_Msk /*!< Command register */ + +/******************* Bit definition for WDT_DIV register ********************/ +/*!< DIV configuration */ +#define WDT_DIV_DIV_Pos (0U) +#define WDT_DIV_DIV_Msk (0x7U << WDT_DIV_DIV_Pos) /*!< 0x00000007 */ +#define WDT_DIV_DIV WDT_DIV_DIV_Msk /*!< DIV[2:0] (Clock division value) */ +#define WDT_DIV_DIV_0 (0x1U << WDT_DIV_DIV_Pos) /*!< 0x00000001 */ +#define WDT_DIV_DIV_1 (0x2U << WDT_DIV_DIV_Pos) /*!< 0x00000002 */ +#define WDT_DIV_DIV_2 (0x4U << WDT_DIV_DIV_Pos) /*!< 0x00000004 */ + +/******************* Bit definition for WDT_RLD register ********************/ +#define WDT_RLD_RLD_Pos (0U) +#define WDT_RLD_RLD_Msk (0xFFFU << WDT_RLD_RLD_Pos) /*!< 0x00000FFF */ +#define WDT_RLD_RLD WDT_RLD_RLD_Msk /*!< Reload value */ + +/******************* Bit definition for WDT_STS register ********************/ +#define WDT_STS_DIVF_Pos (0U) +#define WDT_STS_DIVF_Msk (0x1U << WDT_STS_DIVF_Pos) /*!< 0x00000001 */ +#define WDT_STS_DIVF WDT_STS_DIVF_Msk /*!< Division value update complete flag */ +#define WDT_STS_RLDF_Pos (1U) +#define WDT_STS_RLDF_Msk (0x1U << WDT_STS_RLDF_Pos) /*!< 0x00000002 */ +#define WDT_STS_RLDF WDT_STS_RLDF_Msk /*!< Reload value update complete flag */ +#define WDT_STS_WINF_Pos (2U) +#define WDT_STS_WINF_Msk (0x1U << WDT_STS_WINF_Pos) /*!< 0x00000004 */ +#define WDT_STS_WINF WDT_STS_WINF_Msk /*!< Window value update complete flag */ + +/******************* Bit definition for WDT_WIN register ********************/ +#define WDT_WIN_WIN_Pos (0U) +#define WDT_WIN_WIN_Msk (0xFFFU << WDT_WIN_WIN_Pos) /*!< 0x00000FFF */ +#define WDT_WIN_WIN WDT_WIN_WIN_Msk /*!< Window value */ + +/******************************************************************************/ +/* */ +/* Enhanced real-time clock (ERTC) */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for ERTC_TIME register *******************/ +/*!< SU configuration */ +#define ERTC_TIME_SU_Pos (0U) +#define ERTC_TIME_SU_Msk (0xFU << ERTC_TIME_SU_Pos) /*!< 0x0000000F */ +#define ERTC_TIME_SU ERTC_TIME_SU_Msk /*!< SU[3:0] (Second units) */ +#define ERTC_TIME_SU_0 (0x1U << ERTC_TIME_SU_Pos) /*!< 0x00000001 */ +#define ERTC_TIME_SU_1 (0x2U << ERTC_TIME_SU_Pos) /*!< 0x00000002 */ +#define ERTC_TIME_SU_2 (0x4U << ERTC_TIME_SU_Pos) /*!< 0x00000004 */ +#define ERTC_TIME_SU_3 (0x8U << ERTC_TIME_SU_Pos) /*!< 0x00000008 */ + +/*!< ST configuration */ +#define ERTC_TIME_ST_Pos (4U) +#define ERTC_TIME_ST_Msk (0x7U << ERTC_TIME_ST_Pos) /*!< 0x00000070 */ +#define ERTC_TIME_ST ERTC_TIME_ST_Msk /*!< ST[2:0] (Second tens) */ +#define ERTC_TIME_ST_0 (0x1U << ERTC_TIME_ST_Pos) /*!< 0x00000010 */ +#define ERTC_TIME_ST_1 (0x2U << ERTC_TIME_ST_Pos) /*!< 0x00000020 */ +#define ERTC_TIME_ST_2 (0x4U << ERTC_TIME_ST_Pos) /*!< 0x00000040 */ + +/*!< MU configuration */ +#define ERTC_TIME_MU_Pos (8U) +#define ERTC_TIME_MU_Msk (0xFU << ERTC_TIME_MU_Pos) /*!< 0x00000F00 */ +#define ERTC_TIME_MU ERTC_TIME_MU_Msk /*!< MU[3:0] (Minute units) */ +#define ERTC_TIME_MU_0 (0x1U << ERTC_TIME_MU_Pos) /*!< 0x00000100 */ +#define ERTC_TIME_MU_1 (0x2U << ERTC_TIME_MU_Pos) /*!< 0x00000200 */ +#define ERTC_TIME_MU_2 (0x4U << ERTC_TIME_MU_Pos) /*!< 0x00000400 */ +#define ERTC_TIME_MU_3 (0x8U << ERTC_TIME_MU_Pos) /*!< 0x00000800 */ + +/*!< MT configuration */ +#define ERTC_TIME_MT_Pos (12U) +#define ERTC_TIME_MT_Msk (0x7U << ERTC_TIME_MT_Pos) /*!< 0x00007000 */ +#define ERTC_TIME_MT ERTC_TIME_MT_Msk /*!< MT[2:0] (Minute tens) */ +#define ERTC_TIME_MT_0 (0x1U << ERTC_TIME_MT_Pos) /*!< 0x00001000 */ +#define ERTC_TIME_MT_1 (0x2U << ERTC_TIME_MT_Pos) /*!< 0x00002000 */ +#define ERTC_TIME_MT_2 (0x4U << ERTC_TIME_MT_Pos) /*!< 0x00004000 */ + +/*!< HU configuration */ +#define ERTC_TIME_HU_Pos (16U) +#define ERTC_TIME_HU_Msk (0xFU << ERTC_TIME_HU_Pos) /*!< 0x000F0000 */ +#define ERTC_TIME_HU ERTC_TIME_HU_Msk /*!< HU[3:0] (Hour units) */ +#define ERTC_TIME_HU_0 (0x1U << ERTC_TIME_HU_Pos) /*!< 0x00010000 */ +#define ERTC_TIME_HU_1 (0x2U << ERTC_TIME_HU_Pos) /*!< 0x00020000 */ +#define ERTC_TIME_HU_2 (0x4U << ERTC_TIME_HU_Pos) /*!< 0x00040000 */ +#define ERTC_TIME_HU_3 (0x8U << ERTC_TIME_HU_Pos) /*!< 0x00080000 */ + +/*!< HT configuration */ +#define ERTC_TIME_HT_Pos (20U) +#define ERTC_TIME_HT_Msk (0x3U << ERTC_TIME_HT_Pos) /*!< 0x00300000 */ +#define ERTC_TIME_HT ERTC_TIME_HT_Msk /*!< HT[1:0] (Hour tens) */ +#define ERTC_TIME_HT_0 (0x1U << ERTC_TIME_HT_Pos) /*!< 0x00100000 */ +#define ERTC_TIME_HT_1 (0x2U << ERTC_TIME_HT_Pos) /*!< 0x00200000 */ + +#define ERTC_TIME_AMPM_Pos (22U) +#define ERTC_TIME_AMPM_Msk (0x1U << ERTC_TIME_AMPM_Pos) /*!< 0x00400000 */ +#define ERTC_TIME_AMPM ERTC_TIME_AMPM_Msk /*!< AM/PM */ + +/****************** Bit definition for ERTC_DATE register *******************/ +/*!< DU configuration */ +#define ERTC_DATE_DU_Pos (0U) +#define ERTC_DATE_DU_Msk (0xFU << ERTC_DATE_DU_Pos) /*!< 0x0000000F */ +#define ERTC_DATE_DU ERTC_DATE_DU_Msk /*!< DU[3:0] (Date units) */ +#define ERTC_DATE_DU_0 (0x1U << ERTC_DATE_DU_Pos) /*!< 0x00000001 */ +#define ERTC_DATE_DU_1 (0x2U << ERTC_DATE_DU_Pos) /*!< 0x00000002 */ +#define ERTC_DATE_DU_2 (0x4U << ERTC_DATE_DU_Pos) /*!< 0x00000004 */ +#define ERTC_DATE_DU_3 (0x8U << ERTC_DATE_DU_Pos) /*!< 0x00000008 */ + +/*!< DT configuration */ +#define ERTC_DATE_DT_Pos (4U) +#define ERTC_DATE_DT_Msk (0x3U << ERTC_DATE_DT_Pos) /*!< 0x00300000 */ +#define ERTC_DATE_DT ERTC_DATE_DT_Msk /*!< DT[1:0] (Date tens) */ +#define ERTC_DATE_DT_0 (0x1U << ERTC_DATE_DT_Pos) /*!< 0x00000010 */ +#define ERTC_DATE_DT_1 (0x2U << ERTC_DATE_DT_Pos) /*!< 0x00000020 */ + +/*!< MU configuration */ +#define ERTC_DATE_MU_Pos (8U) +#define ERTC_DATE_MU_Msk (0xFU << ERTC_DATE_MU_Pos) /*!< 0x00000F00 */ +#define ERTC_DATE_MU ERTC_DATE_MU_Msk /*!< MU[3:0] (Month units) */ +#define ERTC_DATE_MU_0 (0x1U << ERTC_DATE_MU_Pos) /*!< 0x00000100 */ +#define ERTC_DATE_MU_1 (0x2U << ERTC_DATE_MU_Pos) /*!< 0x00000200 */ +#define ERTC_DATE_MU_2 (0x4U << ERTC_DATE_MU_Pos) /*!< 0x00000400 */ +#define ERTC_DATE_MU_3 (0x8U << ERTC_DATE_MU_Pos) /*!< 0x00000800 */ + +#define ERTC_DATE_MT_Pos (12U) +#define ERTC_DATE_MT_Msk (0x1U << ERTC_DATE_MT_Pos) /*!< 0x00001000 */ +#define ERTC_DATE_MT ERTC_DATE_MT_Msk /*!< Month tens */ + +/*!< WK configuration */ +#define ERTC_DATE_WK_Pos (13U) +#define ERTC_DATE_WK_Msk (0x7U << ERTC_DATE_WK_Pos) /*!< 0x0000E000 */ +#define ERTC_DATE_WK ERTC_DATE_WK_Msk /*!< WK[2:0] (Week day) */ +#define ERTC_DATE_WK_0 (0x1U << ERTC_DATE_WK_Pos) /*!< 0x00002000 */ +#define ERTC_DATE_WK_1 (0x2U << ERTC_DATE_WK_Pos) /*!< 0x00004000 */ +#define ERTC_DATE_WK_2 (0x4U << ERTC_DATE_WK_Pos) /*!< 0x00008000 */ + +/*!< YU configuration */ +#define ERTC_DATE_YU_Pos (16U) +#define ERTC_DATE_YU_Msk (0xFU << ERTC_DATE_YU_Pos) /*!< 0x000F0000 */ +#define ERTC_DATE_YU ERTC_DATE_YU_Msk /*!< YU[3:0] (Year units) */ +#define ERTC_DATE_YU_0 (0x1U << ERTC_DATE_YU_Pos) /*!< 0x00010000 */ +#define ERTC_DATE_YU_1 (0x2U << ERTC_DATE_YU_Pos) /*!< 0x00020000 */ +#define ERTC_DATE_YU_2 (0x4U << ERTC_DATE_YU_Pos) /*!< 0x00040000 */ +#define ERTC_DATE_YU_3 (0x8U << ERTC_DATE_YU_Pos) /*!< 0x00080000 */ + +/*!< YT configuration */ +#define ERTC_DATE_YT_Pos (20U) +#define ERTC_DATE_YT_Msk (0xFU << ERTC_DATE_YT_Pos) /*!< 0x00F00000 */ +#define ERTC_DATE_YT ERTC_DATE_YT_Msk /*!< YT[3:0] (Year tens) */ +#define ERTC_DATE_YT_0 (0x1U << ERTC_DATE_YT_Pos) /*!< 0x00100000 */ +#define ERTC_DATE_YT_1 (0x2U << ERTC_DATE_YT_Pos) /*!< 0x00200000 */ +#define ERTC_DATE_YT_2 (0x4U << ERTC_DATE_YT_Pos) /*!< 0x00400000 */ +#define ERTC_DATE_YT_3 (0x8U << ERTC_DATE_YT_Pos) /*!< 0x00800000 */ + +/****************** Bit definition for ERTC_CTRL register *******************/ +/*!< WATCLK configuration */ +#define ERTC_CTRL_WATCLK_Pos (0U) +#define ERTC_CTRL_WATCLK_Msk (0x7U << ERTC_CTRL_WATCLK_Pos) /*!< 0x00000007 */ +#define ERTC_CTRL_WATCLK ERTC_CTRL_WATCLK_Msk /*!< WATCLK[2:0] (Wakeup timer clock selection) */ +#define ERTC_CTRL_WATCLK_0 (0x1U << ERTC_CTRL_WATCLK_Pos) /*!< 0x00000001 */ +#define ERTC_CTRL_WATCLK_1 (0x2U << ERTC_CTRL_WATCLK_Pos) /*!< 0x00000002 */ +#define ERTC_CTRL_WATCLK_2 (0x4U << ERTC_CTRL_WATCLK_Pos) /*!< 0x00000004 */ + +#define ERTC_CTRL_TSEDG_Pos (3U) +#define ERTC_CTRL_TSEDG_Msk (0x1U << ERTC_CTRL_TSEDG_Pos) /*!< 0x00000008 */ +#define ERTC_CTRL_TSEDG ERTC_CTRL_TSEDG_Msk /*!< Timestamp trigger edge */ +#define ERTC_CTRL_RCDEN_Pos (4U) +#define ERTC_CTRL_RCDEN_Msk (0x1U << ERTC_CTRL_RCDEN_Pos) /*!< 0x00000010 */ +#define ERTC_CTRL_RCDEN ERTC_CTRL_RCDEN_Msk /*!< Reference clock detection enable */ +#define ERTC_CTRL_DREN_Pos (5U) +#define ERTC_CTRL_DREN_Msk (0x1U << ERTC_CTRL_DREN_Pos) /*!< 0x00000020 */ +#define ERTC_CTRL_DREN ERTC_CTRL_DREN_Msk /*!< Date/time register direct read enable */ +#define ERTC_CTRL_HM_Pos (6U) +#define ERTC_CTRL_HM_Msk (0x1U << ERTC_CTRL_HM_Pos) /*!< 0x00000040 */ +#define ERTC_CTRL_HM ERTC_CTRL_HM_Msk /*!< Hour mode */ +#define ERTC_CTRL_ALAEN_Pos (8U) +#define ERTC_CTRL_ALAEN_Msk (0x1U << ERTC_CTRL_ALAEN_Pos) /*!< 0x00000100 */ +#define ERTC_CTRL_ALAEN ERTC_CTRL_ALAEN_Msk /*!< Alarm A enable */ +#define ERTC_CTRL_ALBEN_Pos (9U) +#define ERTC_CTRL_ALBEN_Msk (0x1U << ERTC_CTRL_ALBEN_Pos) /*!< 0x00000200 */ +#define ERTC_CTRL_ALBEN ERTC_CTRL_ALBEN_Msk /*!< Alarm B enable */ +#define ERTC_CTRL_WATEN_Pos (10U) +#define ERTC_CTRL_WATEN_Msk (0x1U << ERTC_CTRL_WATEN_Pos) /*!< 0x00000400 */ +#define ERTC_CTRL_WATEN ERTC_CTRL_WATEN_Msk /*!< Wakeup timer enable */ +#define ERTC_CTRL_TSEN_Pos (11U) +#define ERTC_CTRL_TSEN_Msk (0x1U << ERTC_CTRL_TSEN_Pos) /*!< 0x00000800 */ +#define ERTC_CTRL_TSEN ERTC_CTRL_TSEN_Msk /*!< Timestamp enable */ +#define ERTC_CTRL_ALAIEN_Pos (12U) +#define ERTC_CTRL_ALAIEN_Msk (0x1U << ERTC_CTRL_ALAIEN_Pos) /*!< 0x00001000 */ +#define ERTC_CTRL_ALAIEN ERTC_CTRL_ALAIEN_Msk /*!< Alarm A interrupt enable */ +#define ERTC_CTRL_ALBIEN_Pos (13U) +#define ERTC_CTRL_ALBIEN_Msk (0x1U << ERTC_CTRL_ALBIEN_Pos) /*!< 0x00002000 */ +#define ERTC_CTRL_ALBIEN ERTC_CTRL_ALBIEN_Msk /*!< Alarm B interrupt enable */ +#define ERTC_CTRL_WATIEN_Pos (14U) +#define ERTC_CTRL_WATIEN_Msk (0x1U << ERTC_CTRL_WATIEN_Pos) /*!< 0x00004000 */ +#define ERTC_CTRL_WATIEN ERTC_CTRL_WATIEN_Msk /*!< Wakeup timer interrupt enable */ +#define ERTC_CTRL_TSIEN_Pos (15U) +#define ERTC_CTRL_TSIEN_Msk (0x1U << ERTC_CTRL_TSIEN_Pos) /*!< 0x000008000 */ +#define ERTC_CTRL_TSIEN ERTC_CTRL_TSIEN_Msk /*!< Timestamp interrupt enable */ +#define ERTC_CTRL_ADD1H_Pos (16U) +#define ERTC_CTRL_ADD1H_Msk (0x1U << ERTC_CTRL_ADD1H_Pos) /*!< 0x00010000 */ +#define ERTC_CTRL_ADD1H ERTC_CTRL_ADD1H_Msk /*!< Add 1 hour */ +#define ERTC_CTRL_DEC1H_Pos (17U) +#define ERTC_CTRL_DEC1H_Msk (0x1U << ERTC_CTRL_DEC1H_Pos) /*!< 0x00020000 */ +#define ERTC_CTRL_DEC1H ERTC_CTRL_DEC1H_Msk /*!< Decrease 1 hour */ +#define ERTC_CTRL_BPR_Pos (18U) +#define ERTC_CTRL_BPR_Msk (0x1U << ERTC_CTRL_BPR_Pos) /*!< 0x00040000 */ +#define ERTC_CTRL_BPR ERTC_CTRL_BPR_Msk /*!< Battery powered domain data register */ +#define ERTC_CTRL_CALOSEL_Pos (19U) +#define ERTC_CTRL_CALOSEL_Msk (0x1U << ERTC_CTRL_CALOSEL_Pos) /*!< 0x00080000 */ +#define ERTC_CTRL_CALOSEL ERTC_CTRL_CALOSEL_Msk /*!< Calibration output selection */ +#define ERTC_CTRL_OUTP_Pos (20U) +#define ERTC_CTRL_OUTP_Msk (0x1U << ERTC_CTRL_OUTP_Pos) /*!< 0x00100000 */ +#define ERTC_CTRL_OUTP ERTC_CTRL_OUTP_Msk /*!< Output polarity */ + +/*!< OUTSEL configuration */ +#define ERTC_CTRL_OUTSEL_Pos (21U) +#define ERTC_CTRL_OUTSEL_Msk (0x3U << ERTC_CTRL_OUTSEL_Pos) /*!< 0x00600000 */ +#define ERTC_CTRL_OUTSEL ERTC_CTRL_OUTSEL_Msk /*!< OUTSEL[1:0] (Output source selection) */ +#define ERTC_CTRL_OUTSEL_0 (0x1U << ERTC_CTRL_OUTSEL_Pos) /*!< 0x00200000 */ +#define ERTC_CTRL_OUTSEL_1 (0x2U << ERTC_CTRL_OUTSEL_Pos) /*!< 0x00400000 */ + +#define ERTC_CTRL_CALOEN_Pos (23U) +#define ERTC_CTRL_CALOEN_Msk (0x1U << ERTC_CTRL_CALOEN_Pos) /*!< 0x00800000 */ +#define ERTC_CTRL_CALOEN ERTC_CTRL_CALOEN_Msk /*!< Calibration output enable */ + +/******************* Bit definition for ERTC_STS register *******************/ +#define ERTC_STS_ALAWF_Pos (0U) +#define ERTC_STS_ALAWF_Msk (0x1U << ERTC_STS_ALAWF_Pos) /*!< 0x00000001 */ +#define ERTC_STS_ALAWF ERTC_STS_ALAWF_Msk /*!< Alarm A register allows write flag */ +#define ERTC_STS_ALBWF_Pos (1U) +#define ERTC_STS_ALBWF_Msk (0x1U << ERTC_STS_ALBWF_Pos) /*!< 0x00000002 */ +#define ERTC_STS_ALBWF ERTC_STS_ALBWF_Msk /*!< Alarm B register allows write flag */ +#define ERTC_STS_WATWF_Pos (2U) +#define ERTC_STS_WATWF_Msk (0x1U << ERTC_STS_WATWF_Pos) /*!< 0x00000004 */ +#define ERTC_STS_WATWF ERTC_STS_WATWF_Msk /*!< Wakeup timer register allows write flag */ +#define ERTC_STS_TADJF_Pos (3U) +#define ERTC_STS_TADJF_Msk (0x1U << ERTC_STS_TADJF_Pos) /*!< 0x00000008 */ +#define ERTC_STS_TADJF ERTC_STS_TADJF_Msk /*!< Time adjustment flag */ +#define ERTC_STS_INITF_Pos (4U) +#define ERTC_STS_INITF_Msk (0x1U << ERTC_STS_INITF_Pos) /*!< 0x00000010 */ +#define ERTC_STS_INITF ERTC_STS_INITF_Msk /*!< Calendar initialization flag */ +#define ERTC_STS_UPDF_Pos (5U) +#define ERTC_STS_UPDF_Msk (0x1U << ERTC_STS_UPDF_Pos) /*!< 0x00000020 */ +#define ERTC_STS_UPDF ERTC_STS_UPDF_Msk /*!< Calendar update flag */ +#define ERTC_STS_IMF_Pos (6U) +#define ERTC_STS_IMF_Msk (0x1U << ERTC_STS_IMF_Pos) /*!< 0x00000040 */ +#define ERTC_STS_IMF ERTC_STS_IMF_Msk /*!< Enter initialization mode flag */ +#define ERTC_STS_IMEN_Pos (7U) +#define ERTC_STS_IMEN_Msk (0x1U << ERTC_STS_IMEN_Pos) /*!< 0x00000080 */ +#define ERTC_STS_IMEN ERTC_STS_IMEN_Msk /*!< Initialization mode enable */ +#define ERTC_STS_ALAF_Pos (8U) +#define ERTC_STS_ALAF_Msk (0x1U << ERTC_STS_ALAF_Pos) /*!< 0x00000100 */ +#define ERTC_STS_ALAF ERTC_STS_ALAF_Msk /*!< Alarm clock A flag */ +#define ERTC_STS_ALBF_Pos (9U) +#define ERTC_STS_ALBF_Msk (0x1U << ERTC_STS_ALBF_Pos) /*!< 0x00000200 */ +#define ERTC_STS_ALBF ERTC_STS_ALBF_Msk /*!< Alarm clock B flag */ +#define ERTC_STS_WATF_Pos (10U) +#define ERTC_STS_WATF_Msk (0x1U << ERTC_STS_WATF_Pos) /*!< 0x00000400 */ +#define ERTC_STS_WATF ERTC_STS_WATF_Msk /*!< Wakeup timer flag */ +#define ERTC_STS_TSF_Pos (11U) +#define ERTC_STS_TSF_Msk (0x1U << ERTC_STS_TSF_Pos) /*!< 0x00000800 */ +#define ERTC_STS_TSF ERTC_STS_TSF_Msk /*!< Timestamp flag */ +#define ERTC_STS_TSOF_Pos (12U) +#define ERTC_STS_TSOF_Msk (0x1U << ERTC_STS_TSOF_Pos) /*!< 0x00001000 */ +#define ERTC_STS_TSOF ERTC_STS_TSOF_Msk /*!< Timestamp overflow flag */ +#define ERTC_STS_TP1F_Pos (13U) +#define ERTC_STS_TP1F_Msk (0x1U << ERTC_STS_TP1F_Pos) /*!< 0x00002000 */ +#define ERTC_STS_TP1F ERTC_STS_TP1F_Msk /*!< Tamper detection 1 flag */ +#define ERTC_STS_TP2F_Pos (14U) +#define ERTC_STS_TP2F_Msk (0x1U << ERTC_STS_TP2F_Pos) /*!< 0x00004000 */ +#define ERTC_STS_TP2F ERTC_STS_TP2F_Msk /*!< Tamper detection 2 flag */ +#define ERTC_STS_CALUPDF_Pos (16U) +#define ERTC_STS_CALUPDF_Msk (0x1U << ERTC_STS_CALUPDF_Pos) /*!< 0x00010000 */ +#define ERTC_STS_CALUPDF ERTC_STS_CALUPDF_Msk /*!< Calibration value update complete flag */ + +/******************* Bit definition for ERTC_DIV register *******************/ +#define ERTC_DIV_DIVB_Pos (0U) +#define ERTC_DIV_DIVB_Msk (0x7FFFU << ERTC_DIV_DIVB_Pos) /*!< 0x00007FFF */ +#define ERTC_DIV_DIVB ERTC_DIV_DIVB_Msk /*!< Divider B */ +#define ERTC_DIV_DIVA_Pos (16U) +#define ERTC_DIV_DIVA_Msk (0x7FU << ERTC_DIV_DIVA_Pos) /*!< 0x007F0000 */ +#define ERTC_DIV_DIVA ERTC_DIV_DIVA_Msk /*!< Divider A */ + +/******************* Bit definition for ERTC_WAT register *******************/ +#define ERTC_WAT_VAL_Pos (0U) +#define ERTC_WAT_VAL_Msk (0xFFFFU << ERTC_WAT_VAL_Pos) /*!< 0x0000FFFF */ +#define ERTC_WAT_VAL ERTC_WAT_VAL_Msk /*!< Wakeup timer reload value */ + +/******************* Bit definition for ERTC_ALA register *******************/ +/*!< SU configuration */ +#define ERTC_ALA_SU_Pos (0U) +#define ERTC_ALA_SU_Msk (0xFU << ERTC_ALA_SU_Pos) /*!< 0x0000000F */ +#define ERTC_ALA_SU ERTC_ALA_SU_Msk /*!< SU[3:0] (Second units) */ +#define ERTC_ALA_SU_0 (0x1U << ERTC_ALA_SU_Pos) /*!< 0x00000001 */ +#define ERTC_ALA_SU_1 (0x2U << ERTC_ALA_SU_Pos) /*!< 0x00000002 */ +#define ERTC_ALA_SU_2 (0x4U << ERTC_ALA_SU_Pos) /*!< 0x00000004 */ +#define ERTC_ALA_SU_3 (0x8U << ERTC_ALA_SU_Pos) /*!< 0x00000008 */ + +/*!< ST configuration */ +#define ERTC_ALA_ST_Pos (4U) +#define ERTC_ALA_ST_Msk (0x7U << ERTC_ALA_ST_Pos) /*!< 0x00000070 */ +#define ERTC_ALA_ST ERTC_ALA_ST_Msk /*!< ST[2:0] (Second tens) */ +#define ERTC_ALA_ST_0 (0x1U << ERTC_ALA_ST_Pos) /*!< 0x00000010 */ +#define ERTC_ALA_ST_1 (0x2U << ERTC_ALA_ST_Pos) /*!< 0x00000020 */ +#define ERTC_ALA_ST_2 (0x4U << ERTC_ALA_ST_Pos) /*!< 0x00000040 */ + +#define ERTC_ALA_MASK1_Pos (7U) +#define ERTC_ALA_MASK1_Msk (0x1U << ERTC_ALA_MASK1_Pos) /*!< 0x00000080 */ +#define ERTC_ALA_MASK1 ERTC_ALA_MASK1_Msk /*!< Second mask */ + +/*!< MU configuration */ +#define ERTC_ALA_MU_Pos (8U) +#define ERTC_ALA_MU_Msk (0xFU << ERTC_ALA_MU_Pos) /*!< 0x00000F00 */ +#define ERTC_ALA_MU ERTC_ALA_MU_Msk /*!< MU[3:0] (Minute units) */ +#define ERTC_ALA_MU_0 (0x1U << ERTC_ALA_MU_Pos) /*!< 0x00000100 */ +#define ERTC_ALA_MU_1 (0x2U << ERTC_ALA_MU_Pos) /*!< 0x00000200 */ +#define ERTC_ALA_MU_2 (0x4U << ERTC_ALA_MU_Pos) /*!< 0x00000400 */ +#define ERTC_ALA_MU_3 (0x8U << ERTC_ALA_MU_Pos) /*!< 0x00000800 */ + +/*!< MT configuration */ +#define ERTC_ALA_MT_Pos (12U) +#define ERTC_ALA_MT_Msk (0x7U << ERTC_ALA_MT_Pos) /*!< 0x00007000 */ +#define ERTC_ALA_MT ERTC_ALA_MT_Msk /*!< MT[2:0] (Minute tens) */ +#define ERTC_ALA_MT_0 (0x1U << ERTC_ALA_MT_Pos) /*!< 0x00001000 */ +#define ERTC_ALA_MT_1 (0x2U << ERTC_ALA_MT_Pos) /*!< 0x00002000 */ +#define ERTC_ALA_MT_2 (0x4U << ERTC_ALA_MT_Pos) /*!< 0x00004000 */ + +#define ERTC_ALA_MASK2_Pos (15U) +#define ERTC_ALA_MASK2_Msk (0x1U << ERTC_ALA_MASK2_Pos) /*!< 0x00008000 */ +#define ERTC_ALA_MASK2 ERTC_ALA_MASK2_Msk /*!< Minute mask */ + +/*!< HU configuration */ +#define ERTC_ALA_HU_Pos (16U) +#define ERTC_ALA_HU_Msk (0xFU << ERTC_ALA_HU_Pos) /*!< 0x000F0000 */ +#define ERTC_ALA_HU ERTC_ALA_HU_Msk /*!< HU[3:0] (Hour units) */ +#define ERTC_ALA_HU_0 (0x1U << ERTC_ALA_HU_Pos) /*!< 0x00010000 */ +#define ERTC_ALA_HU_1 (0x2U << ERTC_ALA_HU_Pos) /*!< 0x00020000 */ +#define ERTC_ALA_HU_2 (0x4U << ERTC_ALA_HU_Pos) /*!< 0x00040000 */ +#define ERTC_ALA_HU_3 (0x8U << ERTC_ALA_HU_Pos) /*!< 0x00080000 */ + +/*!< HT configuration */ +#define ERTC_ALA_HT_Pos (20U) +#define ERTC_ALA_HT_Msk (0x3U << ERTC_ALA_HT_Pos) /*!< 0x00300000 */ +#define ERTC_ALA_HT ERTC_ALA_HT_Msk /*!< HT[1:0] (Hour tens) */ +#define ERTC_ALA_HT_0 (0x1U << ERTC_ALA_HT_Pos) /*!< 0x00100000 */ +#define ERTC_ALA_HT_1 (0x2U << ERTC_ALA_HT_Pos) /*!< 0x00200000 */ + +#define ERTC_ALA_AMPM_Pos (22U) +#define ERTC_ALA_AMPM_Msk (0x1U << ERTC_ALA_AMPM_Pos) /*!< 0x00400000 */ +#define ERTC_ALA_AMPM ERTC_ALA_AMPM_Msk /*!< AM/PM */ +#define ERTC_ALA_MASK3_Pos (23U) +#define ERTC_ALA_MASK3_Msk (0x1U << ERTC_ALA_MASK3_Pos) /*!< 0x00800000 */ +#define ERTC_ALA_MASK3 ERTC_ALA_MASK3_Msk /*!< Hour mask */ + +/*!< DU configuration */ +#define ERTC_ALA_DU_Pos (24U) +#define ERTC_ALA_DU_Msk (0xFU << ERTC_ALA_DU_Pos) /*!< 0x0F000000 */ +#define ERTC_ALA_DU ERTC_ALA_DU_Msk /*!< DU[3:0] (Date/week day units) */ +#define ERTC_ALA_DU_0 (0x1U << ERTC_ALA_DU_Pos) /*!< 0x01000000 */ +#define ERTC_ALA_DU_1 (0x2U << ERTC_ALA_DU_Pos) /*!< 0x02000000 */ +#define ERTC_ALA_DU_2 (0x4U << ERTC_ALA_DU_Pos) /*!< 0x04000000 */ +#define ERTC_ALA_DU_3 (0x8U << ERTC_ALA_DU_Pos) /*!< 0x08000000 */ + +/*!< DT configuration */ +#define ERTC_ALA_DT_Pos (28U) +#define ERTC_ALA_DT_Msk (0x3U << ERTC_ALA_DT_Pos) /*!< 0x30000000 */ +#define ERTC_ALA_DT ERTC_ALA_DT_Msk /*!< DT[1:0] (Date/week day tens) */ +#define ERTC_ALA_DT_0 (0x1U << ERTC_ALA_DT_Pos) /*!< 0x10000000 */ +#define ERTC_ALA_DT_1 (0x2U << ERTC_ALA_DT_Pos) /*!< 0x20000000 */ + +#define ERTC_ALA_WKSEL_Pos (30U) +#define ERTC_ALA_WKSEL_Msk (0x1U << ERTC_ALA_WKSEL_Pos) /*!< 0x40000000 */ +#define ERTC_ALA_WKSEL ERTC_ALA_WKSEL_Msk /*!< Date/week day select */ +#define ERTC_ALA_MASK4_Pos (31U) +#define ERTC_ALA_MASK4_Msk (0x1U << ERTC_ALA_MASK4_Pos) /*!< 0x80000000 */ +#define ERTC_ALA_MASK4 ERTC_ALA_MASK4_Msk /*!< Date/week day mask */ + +/******************* Bit definition for ERTC_ALB register *******************/ +/*!< SU configuration */ +#define ERTC_ALB_SU_Pos (0U) +#define ERTC_ALB_SU_Msk (0xFU << ERTC_ALB_SU_Pos) /*!< 0x0000000F */ +#define ERTC_ALB_SU ERTC_ALB_SU_Msk /*!< SU[3:0] (Second units) */ +#define ERTC_ALB_SU_0 (0x1U << ERTC_ALB_SU_Pos) /*!< 0x00000001 */ +#define ERTC_ALB_SU_1 (0x2U << ERTC_ALB_SU_Pos) /*!< 0x00000002 */ +#define ERTC_ALB_SU_2 (0x4U << ERTC_ALB_SU_Pos) /*!< 0x00000004 */ +#define ERTC_ALB_SU_3 (0x8U << ERTC_ALB_SU_Pos) /*!< 0x00000008 */ + +/*!< ST configuration */ +#define ERTC_ALB_ST_Pos (4U) +#define ERTC_ALB_ST_Msk (0x7U << ERTC_ALB_ST_Pos) /*!< 0x00000070 */ +#define ERTC_ALB_ST ERTC_ALB_ST_Msk /*!< ST[2:0] (Second tens) */ +#define ERTC_ALB_ST_0 (0x1U << ERTC_ALB_ST_Pos) /*!< 0x00000010 */ +#define ERTC_ALB_ST_1 (0x2U << ERTC_ALB_ST_Pos) /*!< 0x00000020 */ +#define ERTC_ALB_ST_2 (0x4U << ERTC_ALB_ST_Pos) /*!< 0x00000040 */ + +#define ERTC_ALB_MASK1_Pos (7U) +#define ERTC_ALB_MASK1_Msk (0x1U << ERTC_ALB_MASK1_Pos) /*!< 0x00000080 */ +#define ERTC_ALB_MASK1 ERTC_ALB_MASK1_Msk /*!< Second mask */ + +/*!< MU configuration */ +#define ERTC_ALB_MU_Pos (8U) +#define ERTC_ALB_MU_Msk (0xFU << ERTC_ALB_MU_Pos) /*!< 0x00000F00 */ +#define ERTC_ALB_MU ERTC_ALB_MU_Msk /*!< MU[3:0] (Minute units) */ +#define ERTC_ALB_MU_0 (0x1U << ERTC_ALB_MU_Pos) /*!< 0x00000100 */ +#define ERTC_ALB_MU_1 (0x2U << ERTC_ALB_MU_Pos) /*!< 0x00000200 */ +#define ERTC_ALB_MU_2 (0x4U << ERTC_ALB_MU_Pos) /*!< 0x00000400 */ +#define ERTC_ALB_MU_3 (0x8U << ERTC_ALB_MU_Pos) /*!< 0x00000800 */ + +/*!< MT configuration */ +#define ERTC_ALB_MT_Pos (12U) +#define ERTC_ALB_MT_Msk (0x7U << ERTC_ALB_MT_Pos) /*!< 0x00007000 */ +#define ERTC_ALB_MT ERTC_ALB_MT_Msk /*!< MT[2:0] (Minute tens) */ +#define ERTC_ALB_MT_0 (0x1U << ERTC_ALB_MT_Pos) /*!< 0x00001000 */ +#define ERTC_ALB_MT_1 (0x2U << ERTC_ALB_MT_Pos) /*!< 0x00002000 */ +#define ERTC_ALB_MT_2 (0x4U << ERTC_ALB_MT_Pos) /*!< 0x00004000 */ + +#define ERTC_ALB_MASK2_Pos (15U) +#define ERTC_ALB_MASK2_Msk (0x1U << ERTC_ALB_MASK2_Pos) /*!< 0x00008000 */ +#define ERTC_ALB_MASK2 ERTC_ALB_MASK2_Msk /*!< Minute mask */ + +/*!< HU configuration */ +#define ERTC_ALB_HU_Pos (16U) +#define ERTC_ALB_HU_Msk (0xFU << ERTC_ALB_HU_Pos) /*!< 0x000F0000 */ +#define ERTC_ALB_HU ERTC_ALB_HU_Msk /*!< HU[3:0] (Hour units) */ +#define ERTC_ALB_HU_0 (0x1U << ERTC_ALB_HU_Pos) /*!< 0x00010000 */ +#define ERTC_ALB_HU_1 (0x2U << ERTC_ALB_HU_Pos) /*!< 0x00020000 */ +#define ERTC_ALB_HU_2 (0x4U << ERTC_ALB_HU_Pos) /*!< 0x00040000 */ +#define ERTC_ALB_HU_3 (0x8U << ERTC_ALB_HU_Pos) /*!< 0x00080000 */ + +/*!< HT configuration */ +#define ERTC_ALB_HT_Pos (20U) +#define ERTC_ALB_HT_Msk (0x3U << ERTC_ALB_HT_Pos) /*!< 0x00300000 */ +#define ERTC_ALB_HT ERTC_ALB_HT_Msk /*!< HT[1:0] (Hour tens) */ +#define ERTC_ALB_HT_0 (0x1U << ERTC_ALB_HT_Pos) /*!< 0x00100000 */ +#define ERTC_ALB_HT_1 (0x2U << ERTC_ALB_HT_Pos) /*!< 0x00200000 */ + +#define ERTC_ALB_AMPM_Pos (22U) +#define ERTC_ALB_AMPM_Msk (0x1U << ERTC_ALB_AMPM_Pos) /*!< 0x00400000 */ +#define ERTC_ALB_AMPM ERTC_ALB_AMPM_Msk /*!< AM/PM */ +#define ERTC_ALB_MASK3_Pos (23U) +#define ERTC_ALB_MASK3_Msk (0x1U << ERTC_ALB_MASK3_Pos) /*!< 0x00800000 */ +#define ERTC_ALB_MASK3 ERTC_ALB_MASK3_Msk /*!< Hour mask */ + +/*!< DU configuration */ +#define ERTC_ALB_DU_Pos (24U) +#define ERTC_ALB_DU_Msk (0xFU << ERTC_ALB_DU_Pos) /*!< 0x0F000000 */ +#define ERTC_ALB_DU ERTC_ALB_DU_Msk /*!< DU[3:0] (Date/week day units) */ +#define ERTC_ALB_DU_0 (0x1U << ERTC_ALB_DU_Pos) /*!< 0x01000000 */ +#define ERTC_ALB_DU_1 (0x2U << ERTC_ALB_DU_Pos) /*!< 0x02000000 */ +#define ERTC_ALB_DU_2 (0x4U << ERTC_ALB_DU_Pos) /*!< 0x04000000 */ +#define ERTC_ALB_DU_3 (0x8U << ERTC_ALB_DU_Pos) /*!< 0x08000000 */ + +/*!< DT configuration */ +#define ERTC_ALB_DT_Pos (28U) +#define ERTC_ALB_DT_Msk (0x3U << ERTC_ALB_DT_Pos) /*!< 0x30000000 */ +#define ERTC_ALB_DT ERTC_ALB_DT_Msk /*!< DT[1:0] (Date/week day tens) */ +#define ERTC_ALB_DT_0 (0x1U << ERTC_ALB_DT_Pos) /*!< 0x10000000 */ +#define ERTC_ALB_DT_1 (0x2U << ERTC_ALB_DT_Pos) /*!< 0x20000000 */ + +#define ERTC_ALB_WKSEL_Pos (30U) +#define ERTC_ALB_WKSEL_Msk (0x1U << ERTC_ALB_WKSEL_Pos) /*!< 0x40000000 */ +#define ERTC_ALB_WKSEL ERTC_ALB_WKSEL_Msk /*!< Date/week day select */ +#define ERTC_ALB_MASK4_Pos (31U) +#define ERTC_ALB_MASK4_Msk (0x1U << ERTC_ALB_MASK4_Pos) /*!< 0x80000000 */ +#define ERTC_ALB_MASK4 ERTC_ALB_MASK4_Msk /*!< Date/week day mask */ + +/******************* Bit definition for ERTC_WP register ********************/ +#define ERTC_WP_CMD_Pos (0U) +#define ERTC_WP_CMD_Msk (0xFFU << ERTC_WP_CMD_Pos) /*!< 0x000000FF */ +#define ERTC_WP_CMD ERTC_WP_CMD_Msk /*!< Command register */ + +/******************* Bit definition for ERTC_SBS register *******************/ +#define ERTC_SBS_SBS_Pos (0U) +#define ERTC_SBS_SBS_Msk (0xFFFFU << ERTC_SBS_SBS_Pos) /*!< 0x0000FFFF */ +#define ERTC_SBS_SBS ERTC_SBS_SBS_Msk /*!< Sub-second value */ + +/****************** Bit definition for ERTC_TADJ register *******************/ +#define ERTC_TADJ_DECSBS_Pos (0U) +#define ERTC_TADJ_DECSBS_Msk (0x7FFFU << ERTC_TADJ_DECSBS_Pos) /*!< 0x00007FFF */ +#define ERTC_TADJ_DECSBS ERTC_TADJ_DECSBS_Msk /*!< Decrease sub-second value */ +#define ERTC_TADJ_ADD1S_Pos (31U) +#define ERTC_TADJ_ADD1S_Msk (0x1U << ERTC_TADJ_ADD1S_Pos) /*!< 0x80000000 */ +#define ERTC_TADJ_ADD1S ERTC_TADJ_ADD1S_Msk /*!< Add 1 second */ + +/****************** Bit definition for ERTC_TSTM register *******************/ +/*!< SU configuration */ +#define ERTC_TSTM_SU_Pos (0U) +#define ERTC_TSTM_SU_Msk (0xFU << ERTC_TSTM_SU_Pos) /*!< 0x0000000F */ +#define ERTC_TSTM_SU ERTC_TSTM_SU_Msk /*!< SU[3:0] (Second units) */ +#define ERTC_TSTM_SU_0 (0x1U << ERTC_TSTM_SU_Pos) /*!< 0x00000001 */ +#define ERTC_TSTM_SU_1 (0x2U << ERTC_TSTM_SU_Pos) /*!< 0x00000002 */ +#define ERTC_TSTM_SU_2 (0x4U << ERTC_TSTM_SU_Pos) /*!< 0x00000004 */ +#define ERTC_TSTM_SU_3 (0x8U << ERTC_TSTM_SU_Pos) /*!< 0x00000008 */ + +/*!< ST configuration */ +#define ERTC_TSTM_ST_Pos (4U) +#define ERTC_TSTM_ST_Msk (0x7U << ERTC_TSTM_ST_Pos) /*!< 0x00000070 */ +#define ERTC_TSTM_ST ERTC_TSTM_ST_Msk /*!< ST[2:0] (Second tens) */ +#define ERTC_TSTM_ST_0 (0x1U << ERTC_TSTM_ST_Pos) /*!< 0x00000010 */ +#define ERTC_TSTM_ST_1 (0x2U << ERTC_TSTM_ST_Pos) /*!< 0x00000020 */ +#define ERTC_TSTM_ST_2 (0x4U << ERTC_TSTM_ST_Pos) /*!< 0x00000040 */ + +/*!< MU configuration */ +#define ERTC_TSTM_MU_Pos (8U) +#define ERTC_TSTM_MU_Msk (0xFU << ERTC_TSTM_MU_Pos) /*!< 0x00000F00 */ +#define ERTC_TSTM_MU ERTC_TSTM_MU_Msk /*!< MU[3:0] (Minute units) */ +#define ERTC_TSTM_MU_0 (0x1U << ERTC_TSTM_MU_Pos) /*!< 0x00000100 */ +#define ERTC_TSTM_MU_1 (0x2U << ERTC_TSTM_MU_Pos) /*!< 0x00000200 */ +#define ERTC_TSTM_MU_2 (0x4U << ERTC_TSTM_MU_Pos) /*!< 0x00000400 */ +#define ERTC_TSTM_MU_3 (0x8U << ERTC_TSTM_MU_Pos) /*!< 0x00000800 */ + +/*!< MT configuration */ +#define ERTC_TSTM_MT_Pos (12U) +#define ERTC_TSTM_MT_Msk (0x7U << ERTC_TSTM_MT_Pos) /*!< 0x00007000 */ +#define ERTC_TSTM_MT ERTC_TSTM_MT_Msk /*!< MT[2:0] (Minute tens) */ +#define ERTC_TSTM_MT_0 (0x1U << ERTC_TSTM_MT_Pos) /*!< 0x00001000 */ +#define ERTC_TSTM_MT_1 (0x2U << ERTC_TSTM_MT_Pos) /*!< 0x00002000 */ +#define ERTC_TSTM_MT_2 (0x4U << ERTC_TSTM_MT_Pos) /*!< 0x00004000 */ + +/*!< HU configuration */ +#define ERTC_TSTM_HU_Pos (16U) +#define ERTC_TSTM_HU_Msk (0xFU << ERTC_TSTM_HU_Pos) /*!< 0x000F0000 */ +#define ERTC_TSTM_HU ERTC_TSTM_HU_Msk /*!< HU[3:0] (Hour units) */ +#define ERTC_TSTM_HU_0 (0x1U << ERTC_TSTM_HU_Pos) /*!< 0x00010000 */ +#define ERTC_TSTM_HU_1 (0x2U << ERTC_TSTM_HU_Pos) /*!< 0x00020000 */ +#define ERTC_TSTM_HU_2 (0x4U << ERTC_TSTM_HU_Pos) /*!< 0x00040000 */ +#define ERTC_TSTM_HU_3 (0x8U << ERTC_TSTM_HU_Pos) /*!< 0x00080000 */ + +/*!< HT configuration */ +#define ERTC_TSTM_HT_Pos (20U) +#define ERTC_TSTM_HT_Msk (0x3U << ERTC_TSTM_HT_Pos) /*!< 0x00300000 */ +#define ERTC_TSTM_HT ERTC_TSTM_HT_Msk /*!< HT[1:0] (Hour tens) */ +#define ERTC_TSTM_HT_0 (0x1U << ERTC_TSTM_HT_Pos) /*!< 0x00100000 */ +#define ERTC_TSTM_HT_1 (0x2U << ERTC_TSTM_HT_Pos) /*!< 0x00200000 */ + +#define ERTC_TSTM_AMPM_Pos (22U) +#define ERTC_TSTM_AMPM_Msk (0x1U << ERTC_TSTM_AMPM_Pos) /*!< 0x00400000 */ +#define ERTC_TSTM_AMPM ERTC_TSTM_AMPM_Msk /*!< AM/PM */ + +/****************** Bit definition for ERTC_TSDT register *******************/ +/*!< DU configuration */ +#define ERTC_TSDT_DU_Pos (0U) +#define ERTC_TSDT_DU_Msk (0xFU << ERTC_TSDT_DU_Pos) /*!< 0x0000000F */ +#define ERTC_TSDT_DU ERTC_TSDT_DU_Msk /*!< DU[3:0] (Date units) */ +#define ERTC_TSDT_DU_0 (0x1U << ERTC_TSDT_DU_Pos) /*!< 0x00000001 */ +#define ERTC_TSDT_DU_1 (0x2U << ERTC_TSDT_DU_Pos) /*!< 0x00000002 */ +#define ERTC_TSDT_DU_2 (0x4U << ERTC_TSDT_DU_Pos) /*!< 0x00000004 */ +#define ERTC_TSDT_DU_3 (0x8U << ERTC_TSDT_DU_Pos) /*!< 0x00000008 */ + +/*!< DT configuration */ +#define ERTC_TSDT_DT_Pos (4U) +#define ERTC_TSDT_DT_Msk (0x3U << ERTC_TSDT_DT_Pos) /*!< 0x00000030 */ +#define ERTC_TSDT_DT ERTC_TSDT_DT_Msk /*!< DT[1:0] (Date tens) */ +#define ERTC_TSDT_DT_0 (0x1U << ERTC_TSDT_DT_Pos) /*!< 0x00000010 */ +#define ERTC_TSDT_DT_1 (0x2U << ERTC_TSDT_DT_Pos) /*!< 0x00000020 */ + +/*!< MU configuration */ +#define ERTC_TSDT_MU_Pos (8U) +#define ERTC_TSDT_MU_Msk (0xFU << ERTC_TSDT_MU_Pos) /*!< 0x00000F00 */ +#define ERTC_TSDT_MU ERTC_TSDT_MU_Msk /*!< MU[3:0] (Month units) */ +#define ERTC_TSDT_MU_0 (0x1U << ERTC_TSDT_MU_Pos) /*!< 0x00000100 */ +#define ERTC_TSDT_MU_1 (0x2U << ERTC_TSDT_MU_Pos) /*!< 0x00000200 */ +#define ERTC_TSDT_MU_2 (0x4U << ERTC_TSDT_MU_Pos) /*!< 0x00000400 */ +#define ERTC_TSDT_MU_3 (0x8U << ERTC_TSDT_MU_Pos) /*!< 0x00000800 */ + +#define ERTC_TSDT_MT_Pos (12U) +#define ERTC_TSDT_MT_Msk (0x1U << ERTC_TSDT_MT_Pos) /*!< 0x00001000 */ +#define ERTC_TSDT_MT ERTC_TSDT_MT_Msk /*!< Month tens */ + +/*!< WK configuration */ +#define ERTC_TSDT_WK_Pos (13U) +#define ERTC_TSDT_WK_Msk (0x7U << ERTC_TSDT_WK_Pos) /*!< 0x0000E000 */ +#define ERTC_TSDT_WK ERTC_TSDT_WK_Msk /*!< WK[2:0] (Week day) */ +#define ERTC_TSDT_WK_0 (0x1U << ERTC_TSDT_WK_Pos) /*!< 0x00002000 */ +#define ERTC_TSDT_WK_1 (0x2U << ERTC_TSDT_WK_Pos) /*!< 0x00004000 */ +#define ERTC_TSDT_WK_2 (0x4U << ERTC_TSDT_WK_Pos) /*!< 0x00008000 */ + +/****************** Bit definition for ERTC_TSSBS register ******************/ +#define ERTC_TSSBS_SBS_Pos (0U) +#define ERTC_TSSBS_SBS_Msk (0xFFFFU << ERTC_TSSBS_SBS_Pos) /*!< 0x0000FFFF */ +#define ERTC_TSSBS_SBS ERTC_TSSBS_SBS_Msk /*!< Sub-second value */ + +/****************** Bit definition for ERTC_SCAL register *******************/ +#define ERTC_SCAL_DEC_Pos (0U) +#define ERTC_SCAL_DEC_Msk (0x1FFU << ERTC_SCAL_DEC_Pos) /*!< 0x000001FF */ +#define ERTC_SCAL_DEC ERTC_SCAL_DEC_Msk /*!< Decrease ERTC clock */ +#define ERTC_SCAL_CAL16_Pos (13U) +#define ERTC_SCAL_CAL16_Msk (0x1U << ERTC_SCAL_CAL16_Pos) /*!< 0x00002000 */ +#define ERTC_SCAL_CAL16 ERTC_SCAL_CAL16_Msk /*!< 16 second calibration period */ +#define ERTC_SCAL_CAL8_Pos (14U) +#define ERTC_SCAL_CAL8_Msk (0x1U << ERTC_SCAL_CAL8_Pos) /*!< 0x00004000 */ +#define ERTC_SCAL_CAL8 ERTC_SCAL_CAL8_Msk /*!< 8 second calibration period */ +#define ERTC_SCAL_ADD_Pos (15U) +#define ERTC_SCAL_ADD_Msk (0x1U << ERTC_SCAL_ADD_Pos) /*!< 0x00008000 */ +#define ERTC_SCAL_ADD ERTC_SCAL_ADD_Msk /*!< Add ERTC clock */ + +/****************** Bit definition for ERTC_TAMP register *******************/ +#define ERTC_TAMP_TP1EN_Pos (0U) +#define ERTC_TAMP_TP1EN_Msk (0x1U << ERTC_TAMP_TP1EN_Pos) /*!< 0x00000001 */ +#define ERTC_TAMP_TP1EN ERTC_TAMP_TP1EN_Msk /*!< Tamper detection 1 enable */ +#define ERTC_TAMP_TP1EDG_Pos (1U) +#define ERTC_TAMP_TP1EDG_Msk (0x1U << ERTC_TAMP_TP1EDG_Pos) /*!< 0x00000002 */ +#define ERTC_TAMP_TP1EDG ERTC_TAMP_TP1EDG_Msk /*!< Tamper detection 1 valid edge */ +#define ERTC_TAMP_TPIEN_Pos (2U) +#define ERTC_TAMP_TPIEN_Msk (0x1U << ERTC_TAMP_TPIEN_Pos) /*!< 0x00000004 */ +#define ERTC_TAMP_TPIEN ERTC_TAMP_TPIEN_Msk /*!< Tamper detection interrupt enable */ +#define ERTC_TAMP_TP2EN_Pos (3U) +#define ERTC_TAMP_TP2EN_Msk (0x1U << ERTC_TAMP_TP2EN_Pos) /*!< 0x00000008 */ +#define ERTC_TAMP_TP2EN ERTC_TAMP_TP2EN_Msk /*!< Tamper detection 2 enable */ +#define ERTC_TAMP_TP2EDG_Pos (4U) +#define ERTC_TAMP_TP2EDG_Msk (0x1U << ERTC_TAMP_TP2EDG_Pos) /*!< 0x00000010 */ +#define ERTC_TAMP_TP2EDG ERTC_TAMP_TP2EDG_Msk /*!< Tamper detection 2 valid edge */ +#define ERTC_TAMP_TPTSEN_Pos (7U) +#define ERTC_TAMP_TPTSEN_Msk (0x1U << ERTC_TAMP_TPTSEN_Pos) /*!< 0x00000080 */ +#define ERTC_TAMP_TPTSEN ERTC_TAMP_TPTSEN_Msk /*!< Tamper detection timestamp enable */ + +/*!< TPFREQ configuration */ +#define ERTC_TAMP_TPFREQ_Pos (8U) +#define ERTC_TAMP_TPFREQ_Msk (0x7U << ERTC_TAMP_TPFREQ_Pos) /*!< 0x00000700 */ +#define ERTC_TAMP_TPFREQ ERTC_TAMP_TPFREQ_Msk /*!< TPFREQ[2:0] (Tamper detection frequency) */ +#define ERTC_TAMP_TPFREQ_0 (0x1U << ERTC_TAMP_TPFREQ_Pos) /*!< 0x00000100 */ +#define ERTC_TAMP_TPFREQ_1 (0x2U << ERTC_TAMP_TPFREQ_Pos) /*!< 0x00000200 */ +#define ERTC_TAMP_TPFREQ_2 (0x4U << ERTC_TAMP_TPFREQ_Pos) /*!< 0x00000400 */ + +/*!< TPFLT configuration */ +#define ERTC_TAMP_TPFLT_Pos (11U) +#define ERTC_TAMP_TPFLT_Msk (0x3U << ERTC_TAMP_TPFLT_Pos) /*!< 0x00001800 */ +#define ERTC_TAMP_TPFLT ERTC_TAMP_TPFLT_Msk /*!< TPFLT[1:0] (Tamper detection filter time) */ +#define ERTC_TAMP_TPFLT_0 (0x1U << ERTC_TAMP_TPFLT_Pos) /*!< 0x00000800 */ +#define ERTC_TAMP_TPFLT_1 (0x2U << ERTC_TAMP_TPFLT_Pos) /*!< 0x00001000 */ + +/*!< TPPR configuration */ +#define ERTC_TAMP_TPPR_Pos (13U) +#define ERTC_TAMP_TPPR_Msk (0x3U << ERTC_TAMP_TPPR_Pos) /*!< 0x00006000 */ +#define ERTC_TAMP_TPPR ERTC_TAMP_TPPR_Msk /*!< TPPR[1:0] (Tamper detection pre-charge time) */ +#define ERTC_TAMP_TPPR_0 (0x1U << ERTC_TAMP_TPPR_Pos) /*!< 0x00002000 */ +#define ERTC_TAMP_TPPR_1 (0x2U << ERTC_TAMP_TPPR_Pos) /*!< 0x00004000 */ + +#define ERTC_TAMP_TPPU_Pos (15U) +#define ERTC_TAMP_TPPU_Msk (0x1U << ERTC_TAMP_TPPU_Pos) /*!< 0x00008000 */ +#define ERTC_TAMP_TPPU ERTC_TAMP_TPPU_Msk /*!< Tamper detection pull-up */ +#define ERTC_TAMP_TP1PIN_Pos (16U) +#define ERTC_TAMP_TP1PIN_Msk (0x1U << ERTC_TAMP_TP1PIN_Pos) /*!< 0x00010000 */ +#define ERTC_TAMP_TP1PIN ERTC_TAMP_TP1PIN_Msk /*!< Tamper detection pin selection */ +#define ERTC_TAMP_TSPIN_Pos (17U) +#define ERTC_TAMP_TSPIN_Msk (0x1U << ERTC_TAMP_TSPIN_Pos) /*!< 0x00020000 */ +#define ERTC_TAMP_TSPIN ERTC_TAMP_TSPIN_Msk /*!< Time stamp detection pin selection */ +#define ERTC_TAMP_OUTTYPE_Pos (18U) +#define ERTC_TAMP_OUTTYPE_Msk (0x1U << ERTC_TAMP_OUTTYPE_Pos) /*!< 0x00040000 */ +#define ERTC_TAMP_OUTTYPE ERTC_TAMP_OUTTYPE_Msk /*!< Output type */ + +/***************** Bit definition for ERTC_ALASBS register ******************/ +#define ERTC_ALASBS_SBS_Pos (0U) +#define ERTC_ALASBS_SBS_Msk (0x7FFFU << ERTC_ALASBS_SBS_Pos) /*!< 0x00007FFF */ +#define ERTC_ALASBS_SBS ERTC_ALASBS_SBS_Msk /*!< Sub-second value */ + +/*!< SBSMSK configuration */ +#define ERTC_ALASBS_SBSMSK_Pos (24U) +#define ERTC_ALASBS_SBSMSK_Msk (0xFU << ERTC_ALASBS_SBSMSK_Pos) /*!< 0x0F000000 */ +#define ERTC_ALASBS_SBSMSK ERTC_ALASBS_SBSMSK_Msk /*!< SBSMSK[3:0] (Sub-second mask) */ +#define ERTC_ALASBS_SBSMSK_0 (0x1U << ERTC_ALASBS_SBSMSK_Pos) /*!< 0x01000000 */ +#define ERTC_ALASBS_SBSMSK_1 (0x2U << ERTC_ALASBS_SBSMSK_Pos) /*!< 0x02000000 */ +#define ERTC_ALASBS_SBSMSK_2 (0x4U << ERTC_ALASBS_SBSMSK_Pos) /*!< 0x04000000 */ +#define ERTC_ALASBS_SBSMSK_3 (0x8U << ERTC_ALASBS_SBSMSK_Pos) /*!< 0x08000000 */ + +/***************** Bit definition for ERTC_ALBSBS register ******************/ +#define ERTC_ALBSBS_SBS_Pos (0U) +#define ERTC_ALBSBS_SBS_Msk (0x7FFFU << ERTC_ALBSBS_SBS_Pos) /*!< 0x00007FFF */ +#define ERTC_ALBSBS_SBS ERTC_ALBSBS_SBS_Msk /*!< Sub-second value */ + +/*!< SBSMSK configuration */ +#define ERTC_ALBSBS_SBSMSK_Pos (24U) +#define ERTC_ALBSBS_SBSMSK_Msk (0xFU << ERTC_ALBSBS_SBSMSK_Pos) /*!< 0x0F000000 */ +#define ERTC_ALBSBS_SBSMSK ERTC_ALBSBS_SBSMSK_Msk /*!< SBSMSK[3:0] (Sub-second mask) */ +#define ERTC_ALBSBS_SBSMSK_0 (0x1U << ERTC_ALBSBS_SBSMSK_Pos) /*!< 0x01000000 */ +#define ERTC_ALBSBS_SBSMSK_1 (0x2U << ERTC_ALBSBS_SBSMSK_Pos) /*!< 0x02000000 */ +#define ERTC_ALBSBS_SBSMSK_2 (0x4U << ERTC_ALBSBS_SBSMSK_Pos) /*!< 0x04000000 */ +#define ERTC_ALBSBS_SBSMSK_3 (0x8U << ERTC_ALBSBS_SBSMSK_Pos) /*!< 0x08000000 */ + +/****************** Bit definition for ERTC_BPR1 register *******************/ +#define ERTC_BPR1_DT_Pos (0U) +#define ERTC_BPR1_DT_Msk (0xFFFFFFFFU << ERTC_BPR1_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR1_DT ERTC_BPR1_DT_Msk /*!< Battery powered domain data 1 */ + +/****************** Bit definition for ERTC_BPR2 register *******************/ +#define ERTC_BPR2_DT_Pos (0U) +#define ERTC_BPR2_DT_Msk (0xFFFFFFFFU << ERTC_BPR2_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR2_DT ERTC_BPR2_DT_Msk /*!< Battery powered domain data 2 */ + +/****************** Bit definition for ERTC_BPR3 register *******************/ +#define ERTC_BPR3_DT_Pos (0U) +#define ERTC_BPR3_DT_Msk (0xFFFFFFFFU << ERTC_BPR3_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR3_DT ERTC_BPR3_DT_Msk /*!< Battery powered domain data 3 */ + +/****************** Bit definition for ERTC_BPR4 register *******************/ +#define ERTC_BPR4_DT_Pos (0U) +#define ERTC_BPR4_DT_Msk (0xFFFFFFFFU << ERTC_BPR4_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR4_DT ERTC_BPR4_DT_Msk /*!< Battery powered domain data 4 */ + +/****************** Bit definition for ERTC_BPR5 register *******************/ +#define ERTC_BPR5_DT_Pos (0U) +#define ERTC_BPR5_DT_Msk (0xFFFFFFFFU << ERTC_BPR5_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR5_DT ERTC_BPR5_DT_Msk /*!< Battery powered domain data 5 */ + +/****************** Bit definition for ERTC_BPR6 register *******************/ +#define ERTC_BPR6_DT_Pos (0U) +#define ERTC_BPR6_DT_Msk (0xFFFFFFFFU << ERTC_BPR6_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR6_DT ERTC_BPR6_DT_Msk /*!< Battery powered domain data 6 */ + +/****************** Bit definition for ERTC_BPR7 register *******************/ +#define ERTC_BPR7_DT_Pos (0U) +#define ERTC_BPR7_DT_Msk (0xFFFFFFFFU << ERTC_BPR7_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR7_DT ERTC_BPR7_DT_Msk /*!< Battery powered domain data 7 */ + +/****************** Bit definition for ERTC_BPR8 register *******************/ +#define ERTC_BPR8_DT_Pos (0U) +#define ERTC_BPR8_DT_Msk (0xFFFFFFFFU << ERTC_BPR8_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR8_DT ERTC_BPR8_DT_Msk /*!< Battery powered domain data 8 */ + +/****************** Bit definition for ERTC_BPR9 register *******************/ +#define ERTC_BPR9_DT_Pos (0U) +#define ERTC_BPR9_DT_Msk (0xFFFFFFFFU << ERTC_BPR9_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR9_DT ERTC_BPR9_DT_Msk /*!< Battery powered domain data 9 */ + +/****************** Bit definition for ERTC_BPR10 register ******************/ +#define ERTC_BPR10_DT_Pos (0U) +#define ERTC_BPR10_DT_Msk (0xFFFFFFFFU << ERTC_BPR10_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR10_DT ERTC_BPR10_DT_Msk /*!< Battery powered domain data 10 */ + +/****************** Bit definition for ERTC_BPR11 register ******************/ +#define ERTC_BPR11_DT_Pos (0U) +#define ERTC_BPR11_DT_Msk (0xFFFFFFFFU << ERTC_BPR11_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR11_DT ERTC_BPR11_DT_Msk /*!< Battery powered domain data 11 */ + +/****************** Bit definition for ERTC_BPR12 register ******************/ +#define ERTC_BPR12_DT_Pos (0U) +#define ERTC_BPR12_DT_Msk (0xFFFFFFFFU << ERTC_BPR12_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR12_DT ERTC_BPR12_DT_Msk /*!< Battery powered domain data 12 */ + +/****************** Bit definition for ERTC_BPR13 register ******************/ +#define ERTC_BPR13_DT_Pos (0U) +#define ERTC_BPR13_DT_Msk (0xFFFFFFFFU << ERTC_BPR13_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR13_DT ERTC_BPR13_DT_Msk /*!< Battery powered domain data 13 */ + +/****************** Bit definition for ERTC_BPR14 register ******************/ +#define ERTC_BPR14_DT_Pos (0U) +#define ERTC_BPR14_DT_Msk (0xFFFFFFFFU << ERTC_BPR14_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR14_DT ERTC_BPR14_DT_Msk /*!< Battery powered domain data 14 */ + +/****************** Bit definition for ERTC_BPR15 register ******************/ +#define ERTC_BPR15_DT_Pos (0U) +#define ERTC_BPR15_DT_Msk (0xFFFFFFFFU << ERTC_BPR15_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR15_DT ERTC_BPR15_DT_Msk /*!< Battery powered domain data 15 */ + +/****************** Bit definition for ERTC_BPR16 register ******************/ +#define ERTC_BPR16_DT_Pos (0U) +#define ERTC_BPR16_DT_Msk (0xFFFFFFFFU << ERTC_BPR16_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR16_DT ERTC_BPR16_DT_Msk /*!< Battery powered domain data 16 */ + +/****************** Bit definition for ERTC_BPR17 register ******************/ +#define ERTC_BPR17_DT_Pos (0U) +#define ERTC_BPR17_DT_Msk (0xFFFFFFFFU << ERTC_BPR17_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR17_DT ERTC_BPR17_DT_Msk /*!< Battery powered domain data 17 */ + +/****************** Bit definition for ERTC_BPR18 register ******************/ +#define ERTC_BPR18_DT_Pos (0U) +#define ERTC_BPR18_DT_Msk (0xFFFFFFFFU << ERTC_BPR18_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR18_DT ERTC_BPR18_DT_Msk /*!< Battery powered domain data 18 */ + +/****************** Bit definition for ERTC_BPR19 register ******************/ +#define ERTC_BPR19_DT_Pos (0U) +#define ERTC_BPR19_DT_Msk (0xFFFFFFFFU << ERTC_BPR19_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR19_DT ERTC_BPR19_DT_Msk /*!< Battery powered domain data 19 */ + +/****************** Bit definition for ERTC_BPR20 register ******************/ +#define ERTC_BPR20_DT_Pos (0U) +#define ERTC_BPR20_DT_Msk (0xFFFFFFFFU << ERTC_BPR20_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR20_DT ERTC_BPR20_DT_Msk /*!< Battery powered domain data 20 */ + +/************************* Number of backup registers *************************/ +#define ERTC_BPR_NUMBER 0x000000014U + +/******************************************************************************/ +/* */ +/* Analog-to-digital converter (ADC) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for ADC_STS register ********************/ +#define ADC_STS_VMOR_Pos (0U) +#define ADC_STS_VMOR_Msk (0x1U << ADC_STS_VMOR_Pos) /*!< 0x00000001 */ +#define ADC_STS_VMOR ADC_STS_VMOR_Msk /*!< Voltage monitoring out of range flag */ +#define ADC_STS_OCCC_Pos (1U) +#define ADC_STS_OCCC_Msk (0x1U << ADC_STS_OCCC_Pos) /*!< 0x00000002 */ +#define ADC_STS_OCCC ADC_STS_OCCC_Msk /*!< End of conversion flag */ +#define ADC_STS_PCCC_Pos (2U) +#define ADC_STS_PCCC_Msk (0x1U << ADC_STS_PCCC_Pos) /*!< 0x00000004 */ +#define ADC_STS_PCCC ADC_STS_PCCC_Msk /*!< Preempted channel end of conversion flag */ +#define ADC_STS_PCCS_Pos (3U) +#define ADC_STS_PCCS_Msk (0x1U << ADC_STS_PCCS_Pos) /*!< 0x00000008 */ +#define ADC_STS_PCCS ADC_STS_PCCS_Msk /*!< Preempted channel conversion start flag */ +#define ADC_STS_OCCS_Pos (4U) +#define ADC_STS_OCCS_Msk (0x1U << ADC_STS_OCCS_Pos) /*!< 0x00000010 */ +#define ADC_STS_OCCS ADC_STS_OCCS_Msk /*!< Ordinary channel conversion start flag */ + +/* Legacy defines */ +#define ADC_STS_OCCE (ADC_STS_OCCC) +#define ADC_STS_PCCE (ADC_STS_PCCC) + +/****************** Bit definition for ADC_CTRL1 register *******************/ +/*!< VMCSEL configuration */ +#define ADC_CTRL1_VMCSEL_Pos (0U) +#define ADC_CTRL1_VMCSEL_Msk (0x1FU << ADC_CTRL1_VMCSEL_Pos) /*!< 0x0000001F */ +#define ADC_CTRL1_VMCSEL ADC_CTRL1_VMCSEL_Msk /*!< VMCSEL[4:0] bits (Voltage monitoring channel select) */ +#define ADC_CTRL1_VMCSEL_0 (0x01U << ADC_CTRL1_VMCSEL_Pos) /*!< 0x00000001 */ +#define ADC_CTRL1_VMCSEL_1 (0x02U << ADC_CTRL1_VMCSEL_Pos) /*!< 0x00000002 */ +#define ADC_CTRL1_VMCSEL_2 (0x04U << ADC_CTRL1_VMCSEL_Pos) /*!< 0x00000004 */ +#define ADC_CTRL1_VMCSEL_3 (0x08U << ADC_CTRL1_VMCSEL_Pos) /*!< 0x00000008 */ +#define ADC_CTRL1_VMCSEL_4 (0x10U << ADC_CTRL1_VMCSEL_Pos) /*!< 0x00000010 */ + +#define ADC_CTRL1_CCCIEN_Pos (5U) +#define ADC_CTRL1_CCCIEN_Msk (0x1U << ADC_CTRL1_CCCIEN_Pos) /*!< 0x00000020 */ +#define ADC_CTRL1_CCCIEN ADC_CTRL1_CCCIEN_Msk /*!< Channel conversion end interrupt enable */ +#define ADC_CTRL1_VMORIEN_Pos (6U) +#define ADC_CTRL1_VMORIEN_Msk (0x1U << ADC_CTRL1_VMORIEN_Pos) /*!< 0x00000040 */ +#define ADC_CTRL1_VMORIEN ADC_CTRL1_VMORIEN_Msk /*!< Voltage monitoring out of range interrupt enable */ +#define ADC_CTRL1_PCCCIEN_Pos (7U) +#define ADC_CTRL1_PCCCIEN_Msk (0x1U << ADC_CTRL1_PCCCIEN_Pos) /*!< 0x00000080 */ +#define ADC_CTRL1_PCCCIEN ADC_CTRL1_PCCCIEN_Msk /*!< Conversion end interrupt enable on Preempted channels */ +#define ADC_CTRL1_SQEN_Pos (8U) +#define ADC_CTRL1_SQEN_Msk (0x1U << ADC_CTRL1_SQEN_Pos) /*!< 0x00000100 */ +#define ADC_CTRL1_SQEN ADC_CTRL1_SQEN_Msk /*!< Sequence mode enable */ +#define ADC_CTRL1_VMSGEN_Pos (9U) +#define ADC_CTRL1_VMSGEN_Msk (0x1U << ADC_CTRL1_VMSGEN_Pos) /*!< 0x00000200 */ +#define ADC_CTRL1_VMSGEN ADC_CTRL1_VMSGEN_Msk /*!< Voltage monitoring enable on a single channel */ +#define ADC_CTRL1_PCAUTOEN_Pos (10U) +#define ADC_CTRL1_PCAUTOEN_Msk (0x1U << ADC_CTRL1_PCAUTOEN_Pos) /*!< 0x00000400 */ +#define ADC_CTRL1_PCAUTOEN ADC_CTRL1_PCAUTOEN_Msk /*!< Preempted group automatic conversion enable after ordinary group */ +#define ADC_CTRL1_OCPEN_Pos (11U) +#define ADC_CTRL1_OCPEN_Msk (0x1U << ADC_CTRL1_OCPEN_Pos) /*!< 0x00000800 */ +#define ADC_CTRL1_OCPEN ADC_CTRL1_OCPEN_Msk /*!< Partitioned mode enable on ordinary channels */ +#define ADC_CTRL1_PCPEN_Pos (12U) +#define ADC_CTRL1_PCPEN_Msk (0x1U << ADC_CTRL1_PCPEN_Pos) /*!< 0x00001000 */ +#define ADC_CTRL1_PCPEN ADC_CTRL1_PCPEN_Msk /*!< Partitioned mode enable on preempted channels */ + +/*!< OCPCNT configuration */ +#define ADC_CTRL1_OCPCNT_Pos (13U) +#define ADC_CTRL1_OCPCNT_Msk (0x7U << ADC_CTRL1_OCPCNT_Pos) /*!< 0x0000E000 */ +#define ADC_CTRL1_OCPCNT ADC_CTRL1_OCPCNT_Msk /*!< OCPCNT[2:0] bits (Partitioned mode conversion count of ordinary channels) */ +#define ADC_CTRL1_OCPCNT_0 (0x1U << ADC_CTRL1_OCPCNT_Pos) /*!< 0x00002000 */ +#define ADC_CTRL1_OCPCNT_1 (0x2U << ADC_CTRL1_OCPCNT_Pos) /*!< 0x00004000 */ +#define ADC_CTRL1_OCPCNT_2 (0x4U << ADC_CTRL1_OCPCNT_Pos) /*!< 0x00008000 */ + +#define ADC_CTRL1_PCVMEN_Pos (22U) +#define ADC_CTRL1_PCVMEN_Msk (0x1U << ADC_CTRL1_PCVMEN_Pos) /*!< 0x00400000 */ +#define ADC_CTRL1_PCVMEN ADC_CTRL1_PCVMEN_Msk /*!< Voltage monitoring enable on preempted channels */ +#define ADC_CTRL1_OCVMEN_Pos (23U) +#define ADC_CTRL1_OCVMEN_Msk (0x1U << ADC_CTRL1_OCVMEN_Pos) /*!< 0x00800000 */ +#define ADC_CTRL1_OCVMEN ADC_CTRL1_OCVMEN_Msk /*!< Voltage monitoring enable on ordinary channels */ + +/* Legacy defines */ +#define ADC_CTRL1_CCEIEN (ADC_CTRL1_CCCIEN) +#define ADC_CTRL1_PCCEIEN (ADC_CTRL1_PCCCIEN) + +/****************** Bit definition for ADC_CTRL2 register *******************/ +#define ADC_CTRL2_ADCEN_Pos (0U) +#define ADC_CTRL2_ADCEN_Msk (0x1U << ADC_CTRL2_ADCEN_Pos) /*!< 0x00000001 */ +#define ADC_CTRL2_ADCEN ADC_CTRL2_ADCEN_Msk /*!< A/D converter enable */ +#define ADC_CTRL2_RPEN_Pos (1U) +#define ADC_CTRL2_RPEN_Msk (0x1U << ADC_CTRL2_RPEN_Pos) /*!< 0x00000002 */ +#define ADC_CTRL2_RPEN ADC_CTRL2_RPEN_Msk /*!< Repetition mode enable */ +#define ADC_CTRL2_ADCAL_Pos (2U) +#define ADC_CTRL2_ADCAL_Msk (0x1U << ADC_CTRL2_ADCAL_Pos) /*!< 0x00000004 */ +#define ADC_CTRL2_ADCAL ADC_CTRL2_ADCAL_Msk /*!< A/D calibration */ +#define ADC_CTRL2_ADCALINIT_Pos (3U) +#define ADC_CTRL2_ADCALINIT_Msk (0x1U << ADC_CTRL2_ADCALINIT_Pos) /*!< 0x00000008 */ +#define ADC_CTRL2_ADCALINIT ADC_CTRL2_ADCALINIT_Msk /*!< Initialize A/D calibration */ +#define ADC_CTRL2_OCDMAEN_Pos (8U) +#define ADC_CTRL2_OCDMAEN_Msk (0x1U << ADC_CTRL2_OCDMAEN_Pos) /*!< 0x00000100 */ +#define ADC_CTRL2_OCDMAEN ADC_CTRL2_OCDMAEN_Msk /*!< DMA transfer enable of ordinary channels */ +#define ADC_CTRL2_DTALIGN_Pos (11U) +#define ADC_CTRL2_DTALIGN_Msk (0x1U << ADC_CTRL2_DTALIGN_Pos) /*!< 0x00000800 */ +#define ADC_CTRL2_DTALIGN ADC_CTRL2_DTALIGN_Msk /*!< Data alignment */ + +/*!< PCTESEL configuration */ +#define ADC_CTRL2_PCTESEL_Pos (12U) +#define ADC_CTRL2_PCTESEL_Msk (0x7U << ADC_CTRL2_PCTESEL_Pos) /*!< 0x00007000 */ +#define ADC_CTRL2_PCTESEL ADC_CTRL2_PCTESEL_Msk /*!< PCTESEL[2:0] bits (Trigger event select for preempted channels conversion) */ +#define ADC_CTRL2_PCTESEL_0 (0x1U << ADC_CTRL2_PCTESEL_Pos) /*!< 0x00001000 */ +#define ADC_CTRL2_PCTESEL_1 (0x2U << ADC_CTRL2_PCTESEL_Pos) /*!< 0x00002000 */ +#define ADC_CTRL2_PCTESEL_2 (0x4U << ADC_CTRL2_PCTESEL_Pos) /*!< 0x00004000 */ + +#define ADC_CTRL2_PCTEN_Pos (15U) +#define ADC_CTRL2_PCTEN_Msk (0x1U << ADC_CTRL2_PCTEN_Pos) /*!< 0x00008000 */ +#define ADC_CTRL2_PCTEN ADC_CTRL2_PCTEN_Msk /*!< Trigger mode enable for preempted channels conversion */ + +/*!< OCTESEL configuration */ +#define ADC_CTRL2_OCTESEL_Pos (17U) +#define ADC_CTRL2_OCTESEL_Msk (0x7U << ADC_CTRL2_OCTESEL_Pos) /*!< 0x000E0000 */ +#define ADC_CTRL2_OCTESEL ADC_CTRL2_OCTESEL_Msk /*!< OCTESEL[2:0] bits (Trigger event select for ordinary channels conversion) */ +#define ADC_CTRL2_OCTESEL_0 (0x1U << ADC_CTRL2_OCTESEL_Pos) /*!< 0x00020000 */ +#define ADC_CTRL2_OCTESEL_1 (0x2U << ADC_CTRL2_OCTESEL_Pos) /*!< 0x00040000 */ +#define ADC_CTRL2_OCTESEL_2 (0x4U << ADC_CTRL2_OCTESEL_Pos) /*!< 0x00080000 */ + +#define ADC_CTRL2_OCTEN_Pos (20U) +#define ADC_CTRL2_OCTEN_Msk (0x1U << ADC_CTRL2_OCTEN_Pos) /*!< 0x00100000 */ +#define ADC_CTRL2_OCTEN ADC_CTRL2_OCTEN_Msk /*!< Trigger mode enable for ordinary channels conversion */ +#define ADC_CTRL2_PCSWTRG_Pos (21U) +#define ADC_CTRL2_PCSWTRG_Msk (0x1U << ADC_CTRL2_PCSWTRG_Pos) /*!< 0x00200000 */ +#define ADC_CTRL2_PCSWTRG ADC_CTRL2_PCSWTRG_Msk /*!< Conversion of preempted channels triggered by software */ +#define ADC_CTRL2_OCSWTRG_Pos (22U) +#define ADC_CTRL2_OCSWTRG_Msk (0x1U << ADC_CTRL2_OCSWTRG_Pos) /*!< 0x00400000 */ +#define ADC_CTRL2_OCSWTRG ADC_CTRL2_OCSWTRG_Msk /*!< Conversion of ordinary channels triggered by software */ +#define ADC_CTRL2_ITSRVEN_Pos (23U) +#define ADC_CTRL2_ITSRVEN_Msk (0x1U << ADC_CTRL2_ITSRVEN_Pos) /*!< 0x00800000 */ +#define ADC_CTRL2_ITSRVEN ADC_CTRL2_ITSRVEN_Msk /*!< Internal temperature sensor and VINTRV enable */ + +/******************* Bit definition for ADC_SPT1 register *******************/ +/*!< CSPT10 configuration */ +#define ADC_SPT1_CSPT10_Pos (0U) +#define ADC_SPT1_CSPT10_Msk (0x7U << ADC_SPT1_CSPT10_Pos) /*!< 0x00000007 */ +#define ADC_SPT1_CSPT10 ADC_SPT1_CSPT10_Msk /*!< CSPT10[2:0] bits (Sample time selection of channel ADC_IN10) */ +#define ADC_SPT1_CSPT10_0 (0x1U << ADC_SPT1_CSPT10_Pos) /*!< 0x00000001 */ +#define ADC_SPT1_CSPT10_1 (0x2U << ADC_SPT1_CSPT10_Pos) /*!< 0x00000002 */ +#define ADC_SPT1_CSPT10_2 (0x4U << ADC_SPT1_CSPT10_Pos) /*!< 0x00000004 */ + +/*!< CSPT11 configuration */ +#define ADC_SPT1_CSPT11_Pos (3U) +#define ADC_SPT1_CSPT11_Msk (0x7U << ADC_SPT1_CSPT11_Pos) /*!< 0x00000038 */ +#define ADC_SPT1_CSPT11 ADC_SPT1_CSPT11_Msk /*!< CSPT11[2:0] bits (Sample time selection of channel ADC_IN11) */ +#define ADC_SPT1_CSPT11_0 (0x1U << ADC_SPT1_CSPT11_Pos) /*!< 0x00000008 */ +#define ADC_SPT1_CSPT11_1 (0x2U << ADC_SPT1_CSPT11_Pos) /*!< 0x00000010 */ +#define ADC_SPT1_CSPT11_2 (0x4U << ADC_SPT1_CSPT11_Pos) /*!< 0x00000020 */ + +/*!< CSPT12 configuration */ +#define ADC_SPT1_CSPT12_Pos (6U) +#define ADC_SPT1_CSPT12_Msk (0x7U << ADC_SPT1_CSPT12_Pos) /*!< 0x000001C0 */ +#define ADC_SPT1_CSPT12 ADC_SPT1_CSPT12_Msk /*!< CSPT12[2:0] bits (Sample time selection of channel ADC_IN12) */ +#define ADC_SPT1_CSPT12_0 (0x1U << ADC_SPT1_CSPT12_Pos) /*!< 0x00000040 */ +#define ADC_SPT1_CSPT12_1 (0x2U << ADC_SPT1_CSPT12_Pos) /*!< 0x00000080 */ +#define ADC_SPT1_CSPT12_2 (0x4U << ADC_SPT1_CSPT12_Pos) /*!< 0x00000100 */ + +/*!< CSPT13 configuration */ +#define ADC_SPT1_CSPT13_Pos (9U) +#define ADC_SPT1_CSPT13_Msk (0x7U << ADC_SPT1_CSPT13_Pos) /*!< 0x00000E00 */ +#define ADC_SPT1_CSPT13 ADC_SPT1_CSPT13_Msk /*!< CSPT13[2:0] bits (Sample time selection of channel ADC_IN13) */ +#define ADC_SPT1_CSPT13_0 (0x1U << ADC_SPT1_CSPT13_Pos) /*!< 0x00000200 */ +#define ADC_SPT1_CSPT13_1 (0x2U << ADC_SPT1_CSPT13_Pos) /*!< 0x00000400 */ +#define ADC_SPT1_CSPT13_2 (0x4U << ADC_SPT1_CSPT13_Pos) /*!< 0x00000800 */ + +/*!< CSPT14 configuration */ +#define ADC_SPT1_CSPT14_Pos (12U) +#define ADC_SPT1_CSPT14_Msk (0x7U << ADC_SPT1_CSPT14_Pos) /*!< 0x00007000 */ +#define ADC_SPT1_CSPT14 ADC_SPT1_CSPT14_Msk /*!< CSPT14[2:0] bits (Sample time selection of channel ADC_IN14) */ +#define ADC_SPT1_CSPT14_0 (0x1U << ADC_SPT1_CSPT14_Pos) /*!< 0x00001000 */ +#define ADC_SPT1_CSPT14_1 (0x2U << ADC_SPT1_CSPT14_Pos) /*!< 0x00002000 */ +#define ADC_SPT1_CSPT14_2 (0x4U << ADC_SPT1_CSPT14_Pos) /*!< 0x00004000 */ + +/*!< CSPT15 configuration */ +#define ADC_SPT1_CSPT15_Pos (15U) +#define ADC_SPT1_CSPT15_Msk (0x7U << ADC_SPT1_CSPT15_Pos) /*!< 0x00038000 */ +#define ADC_SPT1_CSPT15 ADC_SPT1_CSPT15_Msk /*!< CSPT15[2:0] bits (Sample time selection of channel ADC_IN15) */ +#define ADC_SPT1_CSPT15_0 (0x1U << ADC_SPT1_CSPT15_Pos) /*!< 0x00008000 */ +#define ADC_SPT1_CSPT15_1 (0x2U << ADC_SPT1_CSPT15_Pos) /*!< 0x00010000 */ +#define ADC_SPT1_CSPT15_2 (0x4U << ADC_SPT1_CSPT15_Pos) /*!< 0x00020000 */ + +/*!< CSPT16 configuration */ +#define ADC_SPT1_CSPT16_Pos (18U) +#define ADC_SPT1_CSPT16_Msk (0x7U << ADC_SPT1_CSPT16_Pos) /*!< 0x001C0000 */ +#define ADC_SPT1_CSPT16 ADC_SPT1_CSPT16_Msk /*!< CSPT16[2:0] bits (Sample time selection of channel ADC_IN16) */ +#define ADC_SPT1_CSPT16_0 (0x1U << ADC_SPT1_CSPT16_Pos) /*!< 0x00040000 */ +#define ADC_SPT1_CSPT16_1 (0x2U << ADC_SPT1_CSPT16_Pos) /*!< 0x00080000 */ +#define ADC_SPT1_CSPT16_2 (0x4U << ADC_SPT1_CSPT16_Pos) /*!< 0x00100000 */ + +/*!< CSPT17 configuration */ +#define ADC_SPT1_CSPT17_Pos (21U) +#define ADC_SPT1_CSPT17_Msk (0x7U << ADC_SPT1_CSPT17_Pos) /*!< 0x00E00000 */ +#define ADC_SPT1_CSPT17 ADC_SPT1_CSPT17_Msk /*!< CSPT17[2:0] bits (Sample time selection of channel ADC_IN17) */ +#define ADC_SPT1_CSPT17_0 (0x1U << ADC_SPT1_CSPT17_Pos) /*!< 0x00200000 */ +#define ADC_SPT1_CSPT17_1 (0x2U << ADC_SPT1_CSPT17_Pos) /*!< 0x00400000 */ +#define ADC_SPT1_CSPT17_2 (0x4U << ADC_SPT1_CSPT17_Pos) /*!< 0x00800000 */ + +/******************* Bit definition for ADC_SPT2 register *******************/ +/*!< CSPT0 configuration */ +#define ADC_SPT2_CSPT0_Pos (0U) +#define ADC_SPT2_CSPT0_Msk (0x7U << ADC_SPT2_CSPT0_Pos) /*!< 0x00000007 */ +#define ADC_SPT2_CSPT0 ADC_SPT2_CSPT0_Msk /*!< CSPT0[2:0] bits (Sample time selection of channel ADC_IN0) */ +#define ADC_SPT2_CSPT0_0 (0x1U << ADC_SPT2_CSPT0_Pos) /*!< 0x00000001 */ +#define ADC_SPT2_CSPT0_1 (0x2U << ADC_SPT2_CSPT0_Pos) /*!< 0x00000002 */ +#define ADC_SPT2_CSPT0_2 (0x4U << ADC_SPT2_CSPT0_Pos) /*!< 0x00000004 */ + +/*!< CSPT1 configuration */ +#define ADC_SPT2_CSPT1_Pos (3U) +#define ADC_SPT2_CSPT1_Msk (0x7U << ADC_SPT2_CSPT1_Pos) /*!< 0x00000038 */ +#define ADC_SPT2_CSPT1 ADC_SPT2_CSPT1_Msk /*!< CSPT1[2:0] bits (Sample time selection of channel ADC_IN1) */ +#define ADC_SPT2_CSPT1_0 (0x1U << ADC_SPT2_CSPT1_Pos) /*!< 0x00000008 */ +#define ADC_SPT2_CSPT1_1 (0x2U << ADC_SPT2_CSPT1_Pos) /*!< 0x00000010 */ +#define ADC_SPT2_CSPT1_2 (0x4U << ADC_SPT2_CSPT1_Pos) /*!< 0x00000020 */ + +/*!< CSPT2 configuration */ +#define ADC_SPT2_CSPT2_Pos (6U) +#define ADC_SPT2_CSPT2_Msk (0x7U << ADC_SPT2_CSPT2_Pos) /*!< 0x000001C0 */ +#define ADC_SPT2_CSPT2 ADC_SPT2_CSPT2_Msk /*!< CSPT2[2:0] bits (Sample time selection of channel ADC_IN2) */ +#define ADC_SPT2_CSPT2_0 (0x1U << ADC_SPT2_CSPT2_Pos) /*!< 0x00000040 */ +#define ADC_SPT2_CSPT2_1 (0x2U << ADC_SPT2_CSPT2_Pos) /*!< 0x00000080 */ +#define ADC_SPT2_CSPT2_2 (0x4U << ADC_SPT2_CSPT2_Pos) /*!< 0x00000100 */ + +/*!< CSPT3 configuration */ +#define ADC_SPT2_CSPT3_Pos (9U) +#define ADC_SPT2_CSPT3_Msk (0x7U << ADC_SPT2_CSPT3_Pos) /*!< 0x00000E00 */ +#define ADC_SPT2_CSPT3 ADC_SPT2_CSPT3_Msk /*!< CSPT3[2:0] bits (Sample time selection of channel ADC_IN3) */ +#define ADC_SPT2_CSPT3_0 (0x1U << ADC_SPT2_CSPT3_Pos) /*!< 0x00000200 */ +#define ADC_SPT2_CSPT3_1 (0x2U << ADC_SPT2_CSPT3_Pos) /*!< 0x00000400 */ +#define ADC_SPT2_CSPT3_2 (0x4U << ADC_SPT2_CSPT3_Pos) /*!< 0x00000800 */ + +/*!< CSPT4 configuration */ +#define ADC_SPT2_CSPT4_Pos (12U) +#define ADC_SPT2_CSPT4_Msk (0x7U << ADC_SPT2_CSPT4_Pos) /*!< 0x00007000 */ +#define ADC_SPT2_CSPT4 ADC_SPT2_CSPT4_Msk /*!< CSPT4[2:0] bits (Sample time selection of channel ADC_IN4) */ +#define ADC_SPT2_CSPT4_0 (0x1U << ADC_SPT2_CSPT4_Pos) /*!< 0x00001000 */ +#define ADC_SPT2_CSPT4_1 (0x2U << ADC_SPT2_CSPT4_Pos) /*!< 0x00002000 */ +#define ADC_SPT2_CSPT4_2 (0x4U << ADC_SPT2_CSPT4_Pos) /*!< 0x00004000 */ + +/*!< CSPT5 configuration */ +#define ADC_SPT2_CSPT5_Pos (15U) +#define ADC_SPT2_CSPT5_Msk (0x7U << ADC_SPT2_CSPT5_Pos) /*!< 0x00038000 */ +#define ADC_SPT2_CSPT5 ADC_SPT2_CSPT5_Msk /*!< CSPT5[2:0] bits (Sample time selection of channel ADC_IN5) */ +#define ADC_SPT2_CSPT5_0 (0x1U << ADC_SPT2_CSPT5_Pos) /*!< 0x00008000 */ +#define ADC_SPT2_CSPT5_1 (0x2U << ADC_SPT2_CSPT5_Pos) /*!< 0x00010000 */ +#define ADC_SPT2_CSPT5_2 (0x4U << ADC_SPT2_CSPT5_Pos) /*!< 0x00020000 */ + +/*!< CSPT6 configuration */ +#define ADC_SPT2_CSPT6_Pos (18U) +#define ADC_SPT2_CSPT6_Msk (0x7U << ADC_SPT2_CSPT6_Pos) /*!< 0x001C0000 */ +#define ADC_SPT2_CSPT6 ADC_SPT2_CSPT6_Msk /*!< CSPT6[2:0] bits (Sample time selection of channel ADC_IN6) */ +#define ADC_SPT2_CSPT6_0 (0x1U << ADC_SPT2_CSPT6_Pos) /*!< 0x00040000 */ +#define ADC_SPT2_CSPT6_1 (0x2U << ADC_SPT2_CSPT6_Pos) /*!< 0x00080000 */ +#define ADC_SPT2_CSPT6_2 (0x4U << ADC_SPT2_CSPT6_Pos) /*!< 0x00100000 */ + +/*!< CSPT7 configuration */ +#define ADC_SPT2_CSPT7_Pos (21U) +#define ADC_SPT2_CSPT7_Msk (0x7U << ADC_SPT2_CSPT7_Pos) /*!< 0x00E00000 */ +#define ADC_SPT2_CSPT7 ADC_SPT2_CSPT7_Msk /*!< CSPT7[2:0] bits (Sample time selection of channel ADC_IN7) */ +#define ADC_SPT2_CSPT7_0 (0x1U << ADC_SPT2_CSPT7_Pos) /*!< 0x00200000 */ +#define ADC_SPT2_CSPT7_1 (0x2U << ADC_SPT2_CSPT7_Pos) /*!< 0x00400000 */ +#define ADC_SPT2_CSPT7_2 (0x4U << ADC_SPT2_CSPT7_Pos) /*!< 0x00800000 */ + +/*!< CSPT8 configuration */ +#define ADC_SPT2_CSPT8_Pos (24U) +#define ADC_SPT2_CSPT8_Msk (0x7U << ADC_SPT2_CSPT8_Pos) /*!< 0x07000000 */ +#define ADC_SPT2_CSPT8 ADC_SPT2_CSPT8_Msk /*!< CSPT8[2:0] bits (Sample time selection of channel ADC_IN8) */ +#define ADC_SPT2_CSPT8_0 (0x1U << ADC_SPT2_CSPT8_Pos) /*!< 0x01000000 */ +#define ADC_SPT2_CSPT8_1 (0x2U << ADC_SPT2_CSPT8_Pos) /*!< 0x02000000 */ +#define ADC_SPT2_CSPT8_2 (0x4U << ADC_SPT2_CSPT8_Pos) /*!< 0x04000000 */ + +/*!< CSPT9 configuration */ +#define ADC_SPT2_CSPT9_Pos (27U) +#define ADC_SPT2_CSPT9_Msk (0x7U << ADC_SPT2_CSPT9_Pos) /*!< 0x38000000 */ +#define ADC_SPT2_CSPT9 ADC_SPT2_CSPT9_Msk /*!< CSPT9[2:0] bits (Sample time selection of channel ADC_IN9) */ +#define ADC_SPT2_CSPT9_0 (0x1U << ADC_SPT2_CSPT9_Pos) /*!< 0x08000000 */ +#define ADC_SPT2_CSPT9_1 (0x2U << ADC_SPT2_CSPT9_Pos) /*!< 0x10000000 */ +#define ADC_SPT2_CSPT9_2 (0x4U << ADC_SPT2_CSPT9_Pos) /*!< 0x20000000 */ + +/****************** Bit definition for ADC_PCDTO1 register ******************/ +#define ADC_PCDTO1_PCDTO1_Pos (0U) +#define ADC_PCDTO1_PCDTO1_Msk (0xFFFU << ADC_PCDTO1_PCDTO1_Pos) /*!< 0x00000FFF */ +#define ADC_PCDTO1_PCDTO1 ADC_PCDTO1_PCDTO1_Msk /*!< Data offset for Preempted channel 1 */ + +/****************** Bit definition for ADC_PCDTO2 register ******************/ +#define ADC_PCDTO2_PCDTO2_Pos (0U) +#define ADC_PCDTO2_PCDTO2_Msk (0xFFFU << ADC_PCDTO2_PCDTO2_Pos) /*!< 0x00000FFF */ +#define ADC_PCDTO2_PCDTO2 ADC_PCDTO2_PCDTO2_Msk /*!< Data offset for Preempted channel 2 */ + +/****************** Bit definition for ADC_PCDTO3 register ******************/ +#define ADC_PCDTO3_PCDTO3_Pos (0U) +#define ADC_PCDTO3_PCDTO3_Msk (0xFFFU << ADC_PCDTO3_PCDTO3_Pos) /*!< 0x00000FFF */ +#define ADC_PCDTO3_PCDTO3 ADC_PCDTO3_PCDTO3_Msk /*!< Data offset for Preempted channel 3 */ + +/****************** Bit definition for ADC_PCDTO4 register ******************/ +#define ADC_PCDTO4_PCDTO4_Pos (0U) +#define ADC_PCDTO4_PCDTO4_Msk (0xFFFU << ADC_PCDTO4_PCDTO4_Pos) /*!< 0x00000FFF */ +#define ADC_PCDTO4_PCDTO4 ADC_PCDTO4_PCDTO4_Msk /*!< Data offset for Preempted channel 4 */ + +/******************* Bit definition for ADC_VMHB register ********************/ +#define ADC_VMHB_VMHB_Pos (0U) +#define ADC_VMHB_VMHB_Msk (0xFFFFU << ADC_VMHB_VMHB_Pos) /*!< 0x0000FFFF */ +#define ADC_VMHB_VMHB ADC_VMHB_VMHB_Msk /*!< Voltage monitoring high boundary */ + +/******************* Bit definition for ADC_VMLB register ********************/ +#define ADC_VMLB_VMLB_Pos (0U) +#define ADC_VMLB_VMLB_Msk (0xFFFFU << ADC_VMLB_VMLB_Pos) /*!< 0x0000FFFF */ +#define ADC_VMLB_VMLB ADC_VMLB_VMLB_Msk /*!< Voltage monitoring low boundary */ + +/******************* Bit definition for ADC_OSQ1 register *******************/ +/*!< OSN13 configuration */ +#define ADC_OSQ1_OSN13_Pos (0U) +#define ADC_OSQ1_OSN13_Msk (0x1FU << ADC_OSQ1_OSN13_Pos) /*!< 0x0000001F */ +#define ADC_OSQ1_OSN13 ADC_OSQ1_OSN13_Msk /*!< OSN13[4:0] bits (Number of 13th conversion in ordinary sequence) */ +#define ADC_OSQ1_OSN13_0 (0x01U << ADC_OSQ1_OSN13_Pos) /*!< 0x00000001 */ +#define ADC_OSQ1_OSN13_1 (0x02U << ADC_OSQ1_OSN13_Pos) /*!< 0x00000002 */ +#define ADC_OSQ1_OSN13_2 (0x04U << ADC_OSQ1_OSN13_Pos) /*!< 0x00000004 */ +#define ADC_OSQ1_OSN13_3 (0x08U << ADC_OSQ1_OSN13_Pos) /*!< 0x00000008 */ +#define ADC_OSQ1_OSN13_4 (0x10U << ADC_OSQ1_OSN13_Pos) /*!< 0x00000010 */ + +/*!< OSN14 configuration */ +#define ADC_OSQ1_OSN14_Pos (5U) +#define ADC_OSQ1_OSN14_Msk (0x1FU << ADC_OSQ1_OSN14_Pos) /*!< 0x000003E0 */ +#define ADC_OSQ1_OSN14 ADC_OSQ1_OSN14_Msk /*!< OSN14[4:0] bits (Number of 14th conversion in ordinary sequence) */ +#define ADC_OSQ1_OSN14_0 (0x01U << ADC_OSQ1_OSN14_Pos) /*!< 0x00000020 */ +#define ADC_OSQ1_OSN14_1 (0x02U << ADC_OSQ1_OSN14_Pos) /*!< 0x00000040 */ +#define ADC_OSQ1_OSN14_2 (0x04U << ADC_OSQ1_OSN14_Pos) /*!< 0x00000080 */ +#define ADC_OSQ1_OSN14_3 (0x08U << ADC_OSQ1_OSN14_Pos) /*!< 0x00000100 */ +#define ADC_OSQ1_OSN14_4 (0x10U << ADC_OSQ1_OSN14_Pos) /*!< 0x00000200 */ + +/*!< OSN15 configuration */ +#define ADC_OSQ1_OSN15_Pos (10U) +#define ADC_OSQ1_OSN15_Msk (0x1FU << ADC_OSQ1_OSN15_Pos) /*!< 0x00007C00 */ +#define ADC_OSQ1_OSN15 ADC_OSQ1_OSN15_Msk /*!< OSN15[4:0] bits (Number of 15th conversion in ordinary sequence) */ +#define ADC_OSQ1_OSN15_0 (0x01U << ADC_OSQ1_OSN15_Pos) /*!< 0x00000400 */ +#define ADC_OSQ1_OSN15_1 (0x02U << ADC_OSQ1_OSN15_Pos) /*!< 0x00000800 */ +#define ADC_OSQ1_OSN15_2 (0x04U << ADC_OSQ1_OSN15_Pos) /*!< 0x00001000 */ +#define ADC_OSQ1_OSN15_3 (0x08U << ADC_OSQ1_OSN15_Pos) /*!< 0x00002000 */ +#define ADC_OSQ1_OSN15_4 (0x10U << ADC_OSQ1_OSN15_Pos) /*!< 0x00004000 */ + +/*!< OSN16 configuration */ +#define ADC_OSQ1_OSN16_Pos (15U) +#define ADC_OSQ1_OSN16_Msk (0x1FU << ADC_OSQ1_OSN16_Pos) /*!< 0x000F8000 */ +#define ADC_OSQ1_OSN16 ADC_OSQ1_OSN16_Msk /*!< OSN16[4:0] bits (Number of 16th conversion in ordinary sequence) */ +#define ADC_OSQ1_OSN16_0 (0x01U << ADC_OSQ1_OSN16_Pos) /*!< 0x00008000 */ +#define ADC_OSQ1_OSN16_1 (0x02U << ADC_OSQ1_OSN16_Pos) /*!< 0x00010000 */ +#define ADC_OSQ1_OSN16_2 (0x04U << ADC_OSQ1_OSN16_Pos) /*!< 0x00020000 */ +#define ADC_OSQ1_OSN16_3 (0x08U << ADC_OSQ1_OSN16_Pos) /*!< 0x00040000 */ +#define ADC_OSQ1_OSN16_4 (0x10U << ADC_OSQ1_OSN16_Pos) /*!< 0x00080000 */ + +/*!< OCLEN configuration */ +#define ADC_OSQ1_OCLEN_Pos (20U) +#define ADC_OSQ1_OCLEN_Msk (0xFU << ADC_OSQ1_OCLEN_Pos) /*!< 0x00F00000 */ +#define ADC_OSQ1_OCLEN ADC_OSQ1_OCLEN_Msk /*!< OCLEN[3:0] bits (Ordinary conversion sequence length) */ +#define ADC_OSQ1_OCLEN_0 (0x1U << ADC_OSQ1_OCLEN_Pos) /*!< 0x00100000 */ +#define ADC_OSQ1_OCLEN_1 (0x2U << ADC_OSQ1_OCLEN_Pos) /*!< 0x00200000 */ +#define ADC_OSQ1_OCLEN_2 (0x4U << ADC_OSQ1_OCLEN_Pos) /*!< 0x00400000 */ +#define ADC_OSQ1_OCLEN_3 (0x8U << ADC_OSQ1_OCLEN_Pos) /*!< 0x00800000 */ + +/******************* Bit definition for ADC_OSQ2 register *******************/ +/*!< OSN7 configuration */ +#define ADC_OSQ2_OSN7_Pos (0U) +#define ADC_OSQ2_OSN7_Msk (0x1FU << ADC_OSQ2_OSN7_Pos) /*!< 0x0000001F */ +#define ADC_OSQ2_OSN7 ADC_OSQ2_OSN7_Msk /*!< OSN7[4:0] bits (Number of 7th conversion in ordinary sequence) */ +#define ADC_OSQ2_OSN7_0 (0x01U << ADC_OSQ2_OSN7_Pos) /*!< 0x00000001 */ +#define ADC_OSQ2_OSN7_1 (0x02U << ADC_OSQ2_OSN7_Pos) /*!< 0x00000002 */ +#define ADC_OSQ2_OSN7_2 (0x04U << ADC_OSQ2_OSN7_Pos) /*!< 0x00000004 */ +#define ADC_OSQ2_OSN7_3 (0x08U << ADC_OSQ2_OSN7_Pos) /*!< 0x00000008 */ +#define ADC_OSQ2_OSN7_4 (0x10U << ADC_OSQ2_OSN7_Pos) /*!< 0x00000010 */ + +/*!< OSN8 configuration */ +#define ADC_OSQ2_OSN8_Pos (5U) +#define ADC_OSQ2_OSN8_Msk (0x1FU << ADC_OSQ2_OSN8_Pos) /*!< 0x000003E0 */ +#define ADC_OSQ2_OSN8 ADC_OSQ2_OSN8_Msk /*!< OSN8[4:0] bits (Number of 8th conversion in ordinary sequence) */ +#define ADC_OSQ2_OSN8_0 (0x01U << ADC_OSQ2_OSN8_Pos) /*!< 0x00000020 */ +#define ADC_OSQ2_OSN8_1 (0x02U << ADC_OSQ2_OSN8_Pos) /*!< 0x00000040 */ +#define ADC_OSQ2_OSN8_2 (0x04U << ADC_OSQ2_OSN8_Pos) /*!< 0x00000080 */ +#define ADC_OSQ2_OSN8_3 (0x08U << ADC_OSQ2_OSN8_Pos) /*!< 0x00000100 */ +#define ADC_OSQ2_OSN8_4 (0x10U << ADC_OSQ2_OSN8_Pos) /*!< 0x00000200 */ + +/*!< OSN9 configuration */ +#define ADC_OSQ2_OSN9_Pos (10U) +#define ADC_OSQ2_OSN9_Msk (0x1FU << ADC_OSQ2_OSN9_Pos) /*!< 0x00007C00 */ +#define ADC_OSQ2_OSN9 ADC_OSQ2_OSN9_Msk /*!< OSN9[4:0] bits (Number of 9th conversion in ordinary sequence) */ +#define ADC_OSQ2_OSN9_0 (0x01U << ADC_OSQ2_OSN9_Pos) /*!< 0x00000400 */ +#define ADC_OSQ2_OSN9_1 (0x02U << ADC_OSQ2_OSN9_Pos) /*!< 0x00000800 */ +#define ADC_OSQ2_OSN9_2 (0x04U << ADC_OSQ2_OSN9_Pos) /*!< 0x00001000 */ +#define ADC_OSQ2_OSN9_3 (0x08U << ADC_OSQ2_OSN9_Pos) /*!< 0x00002000 */ +#define ADC_OSQ2_OSN9_4 (0x10U << ADC_OSQ2_OSN9_Pos) /*!< 0x00004000 */ + +/*!< OSN10 configuration */ +#define ADC_OSQ2_OSN10_Pos (15U) +#define ADC_OSQ2_OSN10_Msk (0x1FU << ADC_OSQ2_OSN10_Pos) /*!< 0x000F8000 */ +#define ADC_OSQ2_OSN10 ADC_OSQ2_OSN10_Msk /*!< OSN10[4:0] bits (Number of 10th conversion in ordinary sequence) */ +#define ADC_OSQ2_OSN10_0 (0x01U << ADC_OSQ2_OSN10_Pos) /*!< 0x00008000 */ +#define ADC_OSQ2_OSN10_1 (0x02U << ADC_OSQ2_OSN10_Pos) /*!< 0x00010000 */ +#define ADC_OSQ2_OSN10_2 (0x04U << ADC_OSQ2_OSN10_Pos) /*!< 0x00020000 */ +#define ADC_OSQ2_OSN10_3 (0x08U << ADC_OSQ2_OSN10_Pos) /*!< 0x00040000 */ +#define ADC_OSQ2_OSN10_4 (0x10U << ADC_OSQ2_OSN10_Pos) /*!< 0x00080000 */ + +/*!< OSN11 configuration */ +#define ADC_OSQ2_OSN11_Pos (20U) +#define ADC_OSQ2_OSN11_Msk (0x1FU << ADC_OSQ2_OSN11_Pos) /*!< 0x01F00000 */ +#define ADC_OSQ2_OSN11 ADC_OSQ2_OSN11_Msk /*!< OSN11[4:0] bits (Number of 11th conversion in ordinary sequence) */ +#define ADC_OSQ2_OSN11_0 (0x01U << ADC_OSQ2_OSN11_Pos) /*!< 0x00100000 */ +#define ADC_OSQ2_OSN11_1 (0x02U << ADC_OSQ2_OSN11_Pos) /*!< 0x00200000 */ +#define ADC_OSQ2_OSN11_2 (0x04U << ADC_OSQ2_OSN11_Pos) /*!< 0x00400000 */ +#define ADC_OSQ2_OSN11_3 (0x08U << ADC_OSQ2_OSN11_Pos) /*!< 0x00800000 */ +#define ADC_OSQ2_OSN11_4 (0x10U << ADC_OSQ2_OSN11_Pos) /*!< 0x01000000 */ + +/*!< OSN12 configuration */ +#define ADC_OSQ2_OSN12_Pos (25U) +#define ADC_OSQ2_OSN12_Msk (0x1FU << ADC_OSQ2_OSN12_Pos) /*!< 0x3E000000 */ +#define ADC_OSQ2_OSN12 ADC_OSQ2_OSN12_Msk /*!< OSN12[4:0] bits (Number of 12th conversion in ordinary sequence) */ +#define ADC_OSQ2_OSN12_0 (0x01U << ADC_OSQ2_OSN12_Pos) /*!< 0x02000000 */ +#define ADC_OSQ2_OSN12_1 (0x02U << ADC_OSQ2_OSN12_Pos) /*!< 0x04000000 */ +#define ADC_OSQ2_OSN12_2 (0x04U << ADC_OSQ2_OSN12_Pos) /*!< 0x08000000 */ +#define ADC_OSQ2_OSN12_3 (0x08U << ADC_OSQ2_OSN12_Pos) /*!< 0x10000000 */ +#define ADC_OSQ2_OSN12_4 (0x10U << ADC_OSQ2_OSN12_Pos) /*!< 0x20000000 */ + +/******************* Bit definition for ADC_OSQ3 register *******************/ +/*!< OSN1 configuration */ +#define ADC_OSQ3_OSN1_Pos (0U) +#define ADC_OSQ3_OSN1_Msk (0x1FU << ADC_OSQ3_OSN1_Pos) /*!< 0x0000001F */ +#define ADC_OSQ3_OSN1 ADC_OSQ3_OSN1_Msk /*!< OSN1[4:0] bits (Number of 1st conversion in ordinary sequence) */ +#define ADC_OSQ3_OSN1_0 (0x01U << ADC_OSQ3_OSN1_Pos) /*!< 0x00000001 */ +#define ADC_OSQ3_OSN1_1 (0x02U << ADC_OSQ3_OSN1_Pos) /*!< 0x00000002 */ +#define ADC_OSQ3_OSN1_2 (0x04U << ADC_OSQ3_OSN1_Pos) /*!< 0x00000004 */ +#define ADC_OSQ3_OSN1_3 (0x08U << ADC_OSQ3_OSN1_Pos) /*!< 0x00000008 */ +#define ADC_OSQ3_OSN1_4 (0x10U << ADC_OSQ3_OSN1_Pos) /*!< 0x00000010 */ + +/*!< OSN2 configuration */ +#define ADC_OSQ3_OSN2_Pos (5U) +#define ADC_OSQ3_OSN2_Msk (0x1FU << ADC_OSQ3_OSN2_Pos) /*!< 0x000003E0 */ +#define ADC_OSQ3_OSN2 ADC_OSQ3_OSN2_Msk /*!< OSN2[4:0] bits (Number of 2nd conversion in ordinary sequence) */ +#define ADC_OSQ3_OSN2_0 (0x01U << ADC_OSQ3_OSN2_Pos) /*!< 0x00000020 */ +#define ADC_OSQ3_OSN2_1 (0x02U << ADC_OSQ3_OSN2_Pos) /*!< 0x00000040 */ +#define ADC_OSQ3_OSN2_2 (0x04U << ADC_OSQ3_OSN2_Pos) /*!< 0x00000080 */ +#define ADC_OSQ3_OSN2_3 (0x08U << ADC_OSQ3_OSN2_Pos) /*!< 0x00000100 */ +#define ADC_OSQ3_OSN2_4 (0x10U << ADC_OSQ3_OSN2_Pos) /*!< 0x00000200 */ + +/*!< OSN3 configuration */ +#define ADC_OSQ3_OSN3_Pos (10U) +#define ADC_OSQ3_OSN3_Msk (0x1FU << ADC_OSQ3_OSN3_Pos) /*!< 0x00007C00 */ +#define ADC_OSQ3_OSN3 ADC_OSQ3_OSN3_Msk /*!< OSN3[4:0] bits (Number of 3rd conversion in ordinary sequence) */ +#define ADC_OSQ3_OSN3_0 (0x01U << ADC_OSQ3_OSN3_Pos) /*!< 0x00000400 */ +#define ADC_OSQ3_OSN3_1 (0x02U << ADC_OSQ3_OSN3_Pos) /*!< 0x00000800 */ +#define ADC_OSQ3_OSN3_2 (0x04U << ADC_OSQ3_OSN3_Pos) /*!< 0x00001000 */ +#define ADC_OSQ3_OSN3_3 (0x08U << ADC_OSQ3_OSN3_Pos) /*!< 0x00002000 */ +#define ADC_OSQ3_OSN3_4 (0x10U << ADC_OSQ3_OSN3_Pos) /*!< 0x00004000 */ + +/*!< OSN4 configuration */ +#define ADC_OSQ3_OSN4_Pos (15U) +#define ADC_OSQ3_OSN4_Msk (0x1FU << ADC_OSQ3_OSN4_Pos) /*!< 0x000F8000 */ +#define ADC_OSQ3_OSN4 ADC_OSQ3_OSN4_Msk /*!< OSN4[4:0] bits (Number of 4th conversion in ordinary sequence) */ +#define ADC_OSQ3_OSN4_0 (0x01U << ADC_OSQ3_OSN4_Pos) /*!< 0x00008000 */ +#define ADC_OSQ3_OSN4_1 (0x02U << ADC_OSQ3_OSN4_Pos) /*!< 0x00010000 */ +#define ADC_OSQ3_OSN4_2 (0x04U << ADC_OSQ3_OSN4_Pos) /*!< 0x00020000 */ +#define ADC_OSQ3_OSN4_3 (0x08U << ADC_OSQ3_OSN4_Pos) /*!< 0x00040000 */ +#define ADC_OSQ3_OSN4_4 (0x10U << ADC_OSQ3_OSN4_Pos) /*!< 0x00080000 */ + +/*!< OSN5 configuration */ +#define ADC_OSQ3_OSN5_Pos (20U) +#define ADC_OSQ3_OSN5_Msk (0x1FU << ADC_OSQ3_OSN5_Pos) /*!< 0x01F00000 */ +#define ADC_OSQ3_OSN5 ADC_OSQ3_OSN5_Msk /*!< OSN5[4:0] bits (Number of 5th conversion in ordinary sequence) */ +#define ADC_OSQ3_OSN5_0 (0x01U << ADC_OSQ3_OSN5_Pos) /*!< 0x00100000 */ +#define ADC_OSQ3_OSN5_1 (0x02U << ADC_OSQ3_OSN5_Pos) /*!< 0x00200000 */ +#define ADC_OSQ3_OSN5_2 (0x04U << ADC_OSQ3_OSN5_Pos) /*!< 0x00400000 */ +#define ADC_OSQ3_OSN5_3 (0x08U << ADC_OSQ3_OSN5_Pos) /*!< 0x00800000 */ +#define ADC_OSQ3_OSN5_4 (0x10U << ADC_OSQ3_OSN5_Pos) /*!< 0x01000000 */ + +/*!< OSN6 configuration */ +#define ADC_OSQ3_OSN6_Pos (25U) +#define ADC_OSQ3_OSN6_Msk (0x1FU << ADC_OSQ3_OSN6_Pos) /*!< 0x3E000000 */ +#define ADC_OSQ3_OSN6 ADC_OSQ3_OSN6_Msk /*!< OSN6[4:0] bits (Number of 6th conversion in ordinary sequence) */ +#define ADC_OSQ3_OSN6_0 (0x01U << ADC_OSQ3_OSN6_Pos) /*!< 0x02000000 */ +#define ADC_OSQ3_OSN6_1 (0x02U << ADC_OSQ3_OSN6_Pos) /*!< 0x04000000 */ +#define ADC_OSQ3_OSN6_2 (0x04U << ADC_OSQ3_OSN6_Pos) /*!< 0x08000000 */ +#define ADC_OSQ3_OSN6_3 (0x08U << ADC_OSQ3_OSN6_Pos) /*!< 0x10000000 */ +#define ADC_OSQ3_OSN6_4 (0x10U << ADC_OSQ3_OSN6_Pos) /*!< 0x20000000 */ + +/******************* Bit definition for ADC_PSQ register ********************/ +/*!< PSN1 configuration */ +#define ADC_PSQ_PSN1_Pos (0U) +#define ADC_PSQ_PSN1_Msk (0x1FU << ADC_PSQ_PSN1_Pos) /*!< 0x0000001F */ +#define ADC_PSQ_PSN1 ADC_PSQ_PSN1_Msk /*!< PSN1[4:0] bits (Number of 1st conversion in preempted sequence) */ +#define ADC_PSQ_PSN1_0 (0x01U << ADC_PSQ_PSN1_Pos) /*!< 0x00000001 */ +#define ADC_PSQ_PSN1_1 (0x02U << ADC_PSQ_PSN1_Pos) /*!< 0x00000002 */ +#define ADC_PSQ_PSN1_2 (0x04U << ADC_PSQ_PSN1_Pos) /*!< 0x00000004 */ +#define ADC_PSQ_PSN1_3 (0x08U << ADC_PSQ_PSN1_Pos) /*!< 0x00000008 */ +#define ADC_PSQ_PSN1_4 (0x10U << ADC_PSQ_PSN1_Pos) /*!< 0x00000010 */ + +/*!< PSN2 configuration */ +#define ADC_PSQ_PSN2_Pos (5U) +#define ADC_PSQ_PSN2_Msk (0x1FU << ADC_PSQ_PSN2_Pos) /*!< 0x000003E0 */ +#define ADC_PSQ_PSN2 ADC_PSQ_PSN2_Msk /*!< PSN2[4:0] bits (Number of 2nd conversion in preempted sequence) */ +#define ADC_PSQ_PSN2_0 (0x01U << ADC_PSQ_PSN2_Pos) /*!< 0x00000020 */ +#define ADC_PSQ_PSN2_1 (0x02U << ADC_PSQ_PSN2_Pos) /*!< 0x00000040 */ +#define ADC_PSQ_PSN2_2 (0x04U << ADC_PSQ_PSN2_Pos) /*!< 0x00000080 */ +#define ADC_PSQ_PSN2_3 (0x08U << ADC_PSQ_PSN2_Pos) /*!< 0x00000100 */ +#define ADC_PSQ_PSN2_4 (0x10U << ADC_PSQ_PSN2_Pos) /*!< 0x00000200 */ + +/*!< PSN3 configuration */ +#define ADC_PSQ_PSN3_Pos (10U) +#define ADC_PSQ_PSN3_Msk (0x1FU << ADC_PSQ_PSN3_Pos) /*!< 0x00007C00 */ +#define ADC_PSQ_PSN3 ADC_PSQ_PSN3_Msk /*!< PSN3[4:0] bits (Number of 3rd conversion in preempted sequence) */ +#define ADC_PSQ_PSN3_0 (0x01U << ADC_PSQ_PSN3_Pos) /*!< 0x00000400 */ +#define ADC_PSQ_PSN3_1 (0x02U << ADC_PSQ_PSN3_Pos) /*!< 0x00000800 */ +#define ADC_PSQ_PSN3_2 (0x04U << ADC_PSQ_PSN3_Pos) /*!< 0x00001000 */ +#define ADC_PSQ_PSN3_3 (0x08U << ADC_PSQ_PSN3_Pos) /*!< 0x00002000 */ +#define ADC_PSQ_PSN3_4 (0x10U << ADC_PSQ_PSN3_Pos) /*!< 0x00004000 */ + +/*!< PSN4 configuration */ +#define ADC_PSQ_PSN4_Pos (15U) +#define ADC_PSQ_PSN4_Msk (0x1FU << ADC_PSQ_PSN4_Pos) /*!< 0x000F8000 */ +#define ADC_PSQ_PSN4 ADC_PSQ_PSN4_Msk /*!< PSN4[4:0] bits (Number of 4th conversion in preempted sequence) */ +#define ADC_PSQ_PSN4_0 (0x01U << ADC_PSQ_PSN4_Pos) /*!< 0x00008000 */ +#define ADC_PSQ_PSN4_1 (0x02U << ADC_PSQ_PSN4_Pos) /*!< 0x00010000 */ +#define ADC_PSQ_PSN4_2 (0x04U << ADC_PSQ_PSN4_Pos) /*!< 0x00020000 */ +#define ADC_PSQ_PSN4_3 (0x08U << ADC_PSQ_PSN4_Pos) /*!< 0x00040000 */ +#define ADC_PSQ_PSN4_4 (0x10U << ADC_PSQ_PSN4_Pos) /*!< 0x00080000 */ + +/*!< PCLEN configuration */ +#define ADC_PSQ_PCLEN_Pos (20U) +#define ADC_PSQ_PCLEN_Msk (0x3U << ADC_PSQ_PCLEN_Pos) /*!< 0x00300000 */ +#define ADC_PSQ_PCLEN ADC_PSQ_PCLEN_Msk /*!< PCLEN[1:0] bits (Preempted conversion sequence length) */ +#define ADC_PSQ_PCLEN_0 (0x1U << ADC_PSQ_PCLEN_Pos) /*!< 0x00100000 */ +#define ADC_PSQ_PCLEN_1 (0x2U << ADC_PSQ_PCLEN_Pos) /*!< 0x00200000 */ + +/******************* Bit definition for ADC_PDT1 register *******************/ +#define ADC_PDT1_PDT1_Pos (0U) +#define ADC_PDT1_PDT1_Msk (0xFFFFU << ADC_PDT1_PDT1_Pos) /*!< 0x0000FFFF */ +#define ADC_PDT1_PDT1 ADC_PDT1_PDT1_Msk /*!< Conversion data from preempted channel 1 */ + +/******************* Bit definition for ADC_PDT2 register *******************/ +#define ADC_PDT2_PDT2_Pos (0U) +#define ADC_PDT2_PDT2_Msk (0xFFFFU << ADC_PDT2_PDT2_Pos) /*!< 0x0000FFFF */ +#define ADC_PDT2_PDT2 ADC_PDT2_PDT2_Msk /*!< Conversion data from preempted channel 2 */ + +/******************* Bit definition for ADC_PDT3 register *******************/ +#define ADC_PDT3_PDT3_Pos (0U) +#define ADC_PDT3_PDT3_Msk (0xFFFFU << ADC_PDT3_PDT3_Pos) /*!< 0x0000FFFF */ +#define ADC_PDT3_PDT3 ADC_PDT3_PDT3_Msk /*!< Conversion data from preempted channel 3 */ + +/******************* Bit definition for ADC_PDT4 register *******************/ +#define ADC_PDT4_PDT4_Pos (0U) +#define ADC_PDT4_PDT4_Msk (0xFFFFU << ADC_PDT4_PDT4_Pos) /*!< 0x0000FFFF */ +#define ADC_PDT4_PDT4 ADC_PDT4_PDT4_Msk /*!< Conversion data from preempted channel 4 */ + +/******************* Bit definition for ADC_ODT register ********************/ +#define ADC_ODT_ODT_Pos (0U) +#define ADC_ODT_ODT_Msk (0xFFFFU << ADC_ODT_ODT_Pos) /*!< 0x0000FFFF */ +#define ADC_ODT_ODT ADC_ODT_ODT_Msk /*!< Conversion data of ordinary channel */ + +/******************* Bit definition for ADC_OVSP register *******************/ +#define ADC_OVSP_OOSEN_Pos (0U) +#define ADC_OVSP_OOSEN_Msk (0x1U << ADC_OVSP_OOSEN_Pos) /*!< 0x00000001 */ +#define ADC_OVSP_OOSEN ADC_OVSP_OOSEN_Msk /*!< Ordinary oversampling enable */ +#define ADC_OVSP_POSEN_Pos (1U) +#define ADC_OVSP_POSEN_Msk (0x1U << ADC_OVSP_POSEN_Pos) /*!< 0x00000002 */ +#define ADC_OVSP_POSEN ADC_OVSP_POSEN_Msk /*!< Preempted oversampling enable */ + +/*!< OSRSEL configuration */ +#define ADC_OVSP_OSRSEL_Pos (2U) +#define ADC_OVSP_OSRSEL_Msk (0x7U << ADC_OVSP_OSRSEL_Pos) /*!< 0x0000001C */ +#define ADC_OVSP_OSRSEL ADC_OVSP_OSRSEL_Msk /*!< OSRSEL[2:0] bits (Oversampling ratio select) */ +#define ADC_OVSP_OSRSEL_0 (0x1U << ADC_OVSP_OSRSEL_Pos) /*!< 0x00000004 */ +#define ADC_OVSP_OSRSEL_1 (0x2U << ADC_OVSP_OSRSEL_Pos) /*!< 0x00000008 */ +#define ADC_OVSP_OSRSEL_2 (0x4U << ADC_OVSP_OSRSEL_Pos) /*!< 0x00000010 */ + +#define ADC_OVSP_OSRSEL_MULTI2 0x00000000U /*!< 2x */ +#define ADC_OVSP_OSRSEL_MULTI4 0x00000004U /*!< 4x */ +#define ADC_OVSP_OSRSEL_MULTI8 0x00000008U /*!< 8x */ +#define ADC_OVSP_OSRSEL_MULTI16 0x0000000CU /*!< 16x */ +#define ADC_OVSP_OSRSEL_MULTI32 0x00000010U /*!< 32x */ +#define ADC_OVSP_OSRSEL_MULTI64 0x00000014U /*!< 64x */ +#define ADC_OVSP_OSRSEL_MULTI128 0x00000018U /*!< 128x */ +#define ADC_OVSP_OSRSEL_MULTI256 0x0000001CU /*!< 256x */ + +/*!< OSSSEL configuration */ +#define ADC_OVSP_OSSSEL_Pos (5U) +#define ADC_OVSP_OSSSEL_Msk (0xFU << ADC_OVSP_OSSSEL_Pos) /*!< 0x000001E0 */ +#define ADC_OVSP_OSSSEL ADC_OVSP_OSSSEL_Msk /*!< OSSSEL[3:0] bits (Oversampling shift select) */ +#define ADC_OVSP_OSSSEL_0 (0x1U << ADC_OVSP_OSSSEL_Pos) /*!< 0x00000020 */ +#define ADC_OVSP_OSSSEL_1 (0x2U << ADC_OVSP_OSSSEL_Pos) /*!< 0x00000040 */ +#define ADC_OVSP_OSSSEL_2 (0x4U << ADC_OVSP_OSSSEL_Pos) /*!< 0x00000080 */ +#define ADC_OVSP_OSSSEL_3 (0x8U << ADC_OVSP_OSSSEL_Pos) /*!< 0x00000100 */ + +#define ADC_OVSP_OSSSEL_NOSHIFT 0x00000000U /*!< No shift */ +#define ADC_OVSP_OSSSEL_SHIFT1 0x00000020U /*!< Shift 1 bit */ +#define ADC_OVSP_OSSSEL_SHIFT2 0x00000040U /*!< Shift 2 bit */ +#define ADC_OVSP_OSSSEL_SHIFT3 0x00000060U /*!< Shift 3 bit */ +#define ADC_OVSP_OSSSEL_SHIFT4 0x00000080U /*!< Shift 4 bit */ +#define ADC_OVSP_OSSSEL_SHIFT5 0x000000A0U /*!< Shift 5 bit */ +#define ADC_OVSP_OSSSEL_SHIFT6 0x000000C0U /*!< Shift 6 bit */ +#define ADC_OVSP_OSSSEL_SHIFT7 0x000000E0U /*!< Shift 7 bit */ +#define ADC_OVSP_OSSSEL_SHIFT8 0x00000100U /*!< Shift 8 bit */ + +#define ADC_OVSP_OOSTREN_Pos (9U) +#define ADC_OVSP_OOSTREN_Msk (0x1U << ADC_OVSP_OOSTREN_Pos) /*!< 0x00000200 */ +#define ADC_OVSP_OOSTREN ADC_OVSP_OOSTREN_Msk /*!< Ordinary oversampling trigger mode enable */ +#define ADC_OVSP_OOSRSEL_Pos (10U) +#define ADC_OVSP_OOSRSEL_Msk (0x1U << ADC_OVSP_OOSRSEL_Pos) /*!< 0x00000400 */ +#define ADC_OVSP_OOSRSEL ADC_OVSP_OOSRSEL_Msk /*!< Ordinary oversampling restart mode select */ + +/****************** Bit definition for ADC_CCTRL register *******************/ +/*!< ADCDIV configuration */ +#define ADC_CCTRL_ADCDIV_Pos (16U) +#define ADC_CCTRL_ADCDIV_Msk (0xFU << ADC_CCTRL_ADCDIV_Pos) /*!< 0x000F0000 */ +#define ADC_CCTRL_ADCDIV ADC_CCTRL_ADCDIV_Msk /*!< ADCDIV[3:0] bits (ADC division) */ +#define ADC_CCTRL_ADCDIV_0 (0x1U << ADC_CCTRL_ADCDIV_Pos) /*!< 0x00010000 */ +#define ADC_CCTRL_ADCDIV_1 (0x2U << ADC_CCTRL_ADCDIV_Pos) /*!< 0x00020000 */ +#define ADC_CCTRL_ADCDIV_2 (0x4U << ADC_CCTRL_ADCDIV_Pos) /*!< 0x00040000 */ +#define ADC_CCTRL_ADCDIV_3 (0x8U << ADC_CCTRL_ADCDIV_Pos) /*!< 0x00080000 */ + +#define ADC_CCTRL_ADCDIV_DIV2 0x00000000U /*!< HCLK/2 */ +#define ADC_CCTRL_ADCDIV_DIV3 0x00010000U /*!< HCLK/3 */ +#define ADC_CCTRL_ADCDIV_DIV4 0x00020000U /*!< HCLK/4 */ +#define ADC_CCTRL_ADCDIV_DIV5 0x00030000U /*!< HCLK/5 */ +#define ADC_CCTRL_ADCDIV_DIV6 0x00040000U /*!< HCLK/6 */ +#define ADC_CCTRL_ADCDIV_DIV7 0x00050000U /*!< HCLK/7 */ +#define ADC_CCTRL_ADCDIV_DIV8 0x00060000U /*!< HCLK/8 */ +#define ADC_CCTRL_ADCDIV_DIV9 0x00070000U /*!< HCLK/9 */ +#define ADC_CCTRL_ADCDIV_DIV10 0x00080000U /*!< HCLK/10 */ +#define ADC_CCTRL_ADCDIV_DIV11 0x00090000U /*!< HCLK/11 */ +#define ADC_CCTRL_ADCDIV_DIV12 0x000A0000U /*!< HCLK/12 */ +#define ADC_CCTRL_ADCDIV_DIV13 0x000B0000U /*!< HCLK/13 */ +#define ADC_CCTRL_ADCDIV_DIV14 0x000C0000U /*!< HCLK/14 */ +#define ADC_CCTRL_ADCDIV_DIV15 0x000D0000U /*!< HCLK/15 */ +#define ADC_CCTRL_ADCDIV_DIV16 0x000E0000U /*!< HCLK/16 */ +#define ADC_CCTRL_ADCDIV_DIV17 0x000F0000U /*!< HCLK/17 */ + +/******************************************************************************/ +/* */ +/* Controller Area Network (CAN) */ +/* */ +/******************************************************************************/ + +/*!< CAN control and status registers */ +/****************** Bit definition for CAN_MCTRL register *******************/ +#define CAN_MCTRL_FZEN_Pos (0U) +#define CAN_MCTRL_FZEN_Msk (0x1U << CAN_MCTRL_FZEN_Pos) /*!< 0x00000001 */ +#define CAN_MCTRL_FZEN CAN_MCTRL_FZEN_Msk /*!< Freeze mode enable */ +#define CAN_MCTRL_DZEN_Pos (1U) +#define CAN_MCTRL_DZEN_Msk (0x1U << CAN_MCTRL_DZEN_Pos) /*!< 0x00000002 */ +#define CAN_MCTRL_DZEN CAN_MCTRL_DZEN_Msk /*!< Doze mode enable */ +#define CAN_MCTRL_MMSSR_Pos (2U) +#define CAN_MCTRL_MMSSR_Msk (0x1U << CAN_MCTRL_MMSSR_Pos) /*!< 0x00000004 */ +#define CAN_MCTRL_MMSSR CAN_MCTRL_MMSSR_Msk /*!< Multiple message transmit sequence rule */ +#define CAN_MCTRL_MDRSEL_Pos (3U) +#define CAN_MCTRL_MDRSEL_Msk (0x1U << CAN_MCTRL_MDRSEL_Pos) /*!< 0x00000008 */ +#define CAN_MCTRL_MDRSEL CAN_MCTRL_MDRSEL_Msk /*!< Message discard rule select when overflow */ +#define CAN_MCTRL_PRSFEN_Pos (4U) +#define CAN_MCTRL_PRSFEN_Msk (0x1U << CAN_MCTRL_PRSFEN_Pos) /*!< 0x00000010 */ +#define CAN_MCTRL_PRSFEN CAN_MCTRL_PRSFEN_Msk /*!< Prohibit retransmission enable when sending fails enable */ +#define CAN_MCTRL_AEDEN_Pos (5U) +#define CAN_MCTRL_AEDEN_Msk (0x1U << CAN_MCTRL_AEDEN_Pos) /*!< 0x00000020 */ +#define CAN_MCTRL_AEDEN CAN_MCTRL_AEDEN_Msk /*!< Automatic exit doze mode enable */ +#define CAN_MCTRL_AEBOEN_Pos (6U) +#define CAN_MCTRL_AEBOEN_Msk (0x1U << CAN_MCTRL_AEBOEN_Pos) /*!< 0x00000040 */ +#define CAN_MCTRL_AEBOEN CAN_MCTRL_AEBOEN_Msk /*!< Automatic exit bus-off enable */ +#define CAN_MCTRL_TTCEN_Pos (7U) +#define CAN_MCTRL_TTCEN_Msk (0x1U << CAN_MCTRL_TTCEN_Pos) /*!< 0x00000080 */ +#define CAN_MCTRL_TTCEN CAN_MCTRL_TTCEN_Msk /*!< Time triggered communication mode enable */ +#define CAN_MCTRL_SPRST_Pos (15U) +#define CAN_MCTRL_SPRST_Msk (0x1U << CAN_MCTRL_SPRST_Pos) /*!< 0x00008000 */ +#define CAN_MCTRL_SPRST CAN_MCTRL_SPRST_Msk /*!< Software partial reset */ +#define CAN_MCTRL_PTD_Pos (16U) +#define CAN_MCTRL_PTD_Msk (0x1U << CAN_MCTRL_PTD_Pos) /*!< 0x00010000 */ +#define CAN_MCTRL_PTD CAN_MCTRL_PTD_Msk /*!< Prohibit trans when debug */ + +/******************* Bit definition for CAN_MSTS register *******************/ +#define CAN_MSTS_FZC_Pos (0U) +#define CAN_MSTS_FZC_Msk (0x1U << CAN_MSTS_FZC_Pos) /*!< 0x00000001 */ +#define CAN_MSTS_FZC CAN_MSTS_FZC_Msk /*!< Freeze mode confirm */ +#define CAN_MSTS_DZC_Pos (1U) +#define CAN_MSTS_DZC_Msk (0x1U << CAN_MSTS_DZC_Pos) /*!< 0x00000002 */ +#define CAN_MSTS_DZC CAN_MSTS_DZC_Msk /*!< Doze mode acknowledge */ +#define CAN_MSTS_EOIF_Pos (2U) +#define CAN_MSTS_EOIF_Msk (0x1U << CAN_MSTS_EOIF_Pos) /*!< 0x00000004 */ +#define CAN_MSTS_EOIF CAN_MSTS_EOIF_Msk /*!< Error occur interrupt flag */ +#define CAN_MSTS_QDZIF_Pos (3U) +#define CAN_MSTS_QDZIF_Msk (0x1U << CAN_MSTS_QDZIF_Pos) /*!< 0x00000008 */ +#define CAN_MSTS_QDZIF CAN_MSTS_QDZIF_Msk /*!< Exit doze mode interrupt flag */ +#define CAN_MSTS_EDZIF_Pos (4U) +#define CAN_MSTS_EDZIF_Msk (0x1U << CAN_MSTS_EDZIF_Pos) /*!< 0x00000010 */ +#define CAN_MSTS_EDZIF CAN_MSTS_EDZIF_Msk /*!< Enter doze mode interrupt flag */ +#define CAN_MSTS_CUSS_Pos (8U) +#define CAN_MSTS_CUSS_Msk (0x1U << CAN_MSTS_CUSS_Pos) /*!< 0x00000100 */ +#define CAN_MSTS_CUSS CAN_MSTS_CUSS_Msk /*!< Current transmit status */ +#define CAN_MSTS_CURS_Pos (9U) +#define CAN_MSTS_CURS_Msk (0x1U << CAN_MSTS_CURS_Pos) /*!< 0x00000200 */ +#define CAN_MSTS_CURS CAN_MSTS_CURS_Msk /*!< Current receive status */ +#define CAN_MSTS_LSAMPRX_Pos (10U) +#define CAN_MSTS_LSAMPRX_Msk (0x1U << CAN_MSTS_LSAMPRX_Pos) /*!< 0x00000400 */ +#define CAN_MSTS_LSAMPRX CAN_MSTS_LSAMPRX_Msk /*!< Last sample level on RX pin */ +#define CAN_MSTS_REALRX_Pos (11U) +#define CAN_MSTS_REALRX_Msk (0x1U << CAN_MSTS_REALRX_Pos) /*!< 0x00000800 */ +#define CAN_MSTS_REALRX CAN_MSTS_REALRX_Msk /*!< Real time level on RX pin */ + +/******************* Bit definition for CAN_TSTS register *******************/ +#define CAN_TSTS_TM0TCF_Pos (0U) +#define CAN_TSTS_TM0TCF_Msk (0x1U << CAN_TSTS_TM0TCF_Pos) /*!< 0x00000001 */ +#define CAN_TSTS_TM0TCF CAN_TSTS_TM0TCF_Msk /*!< Transmit mailbox 0 transmission completed flag */ +#define CAN_TSTS_TM0TSF_Pos (1U) +#define CAN_TSTS_TM0TSF_Msk (0x1U << CAN_TSTS_TM0TSF_Pos) /*!< 0x00000002 */ +#define CAN_TSTS_TM0TSF CAN_TSTS_TM0TSF_Msk /*!< Transmit mailbox 0 transmission success flag */ +#define CAN_TSTS_TM0ALF_Pos (2U) +#define CAN_TSTS_TM0ALF_Msk (0x1U << CAN_TSTS_TM0ALF_Pos) /*!< 0x00000004 */ +#define CAN_TSTS_TM0ALF CAN_TSTS_TM0ALF_Msk /*!< Transmit mailbox 0 arbitration lost flag */ +#define CAN_TSTS_TM0TEF_Pos (3U) +#define CAN_TSTS_TM0TEF_Msk (0x1U << CAN_TSTS_TM0TEF_Pos) /*!< 0x00000008 */ +#define CAN_TSTS_TM0TEF CAN_TSTS_TM0TEF_Msk /*!< Transmit mailbox 0 transmission error flag */ +#define CAN_TSTS_TM0CT_Pos (7U) +#define CAN_TSTS_TM0CT_Msk (0x1U << CAN_TSTS_TM0CT_Pos) /*!< 0x00000080 */ +#define CAN_TSTS_TM0CT CAN_TSTS_TM0CT_Msk /*!< Transmit mailbox 0 cancel transmit */ +#define CAN_TSTS_TM1TCF_Pos (8U) +#define CAN_TSTS_TM1TCF_Msk (0x1U << CAN_TSTS_TM1TCF_Pos) /*!< 0x00000100 */ +#define CAN_TSTS_TM1TCF CAN_TSTS_TM1TCF_Msk /*!< Transmit mailbox 1 transmission completed flag */ +#define CAN_TSTS_TM1TSF_Pos (9U) +#define CAN_TSTS_TM1TSF_Msk (0x1U << CAN_TSTS_TM1TSF_Pos) /*!< 0x00000200 */ +#define CAN_TSTS_TM1TSF CAN_TSTS_TM1TSF_Msk /*!< Transmit mailbox 1 transmission success flag */ +#define CAN_TSTS_TM1ALF_Pos (10U) +#define CAN_TSTS_TM1ALF_Msk (0x1U << CAN_TSTS_TM1ALF_Pos) /*!< 0x00000400 */ +#define CAN_TSTS_TM1ALF CAN_TSTS_TM1ALF_Msk /*!< Transmit mailbox 1 arbitration lost flag */ +#define CAN_TSTS_TM1TEF_Pos (11U) +#define CAN_TSTS_TM1TEF_Msk (0x1U << CAN_TSTS_TM1TEF_Pos) /*!< 0x00000800 */ +#define CAN_TSTS_TM1TEF CAN_TSTS_TM1TEF_Msk /*!< Transmit mailbox 1 transmission error flag */ +#define CAN_TSTS_TM1CT_Pos (15U) +#define CAN_TSTS_TM1CT_Msk (0x1U << CAN_TSTS_TM1CT_Pos) /*!< 0x00008000 */ +#define CAN_TSTS_TM1CT CAN_TSTS_TM1CT_Msk /*!< Transmit mailbox 1 cancel transmit */ +#define CAN_TSTS_TM2TCF_Pos (16U) +#define CAN_TSTS_TM2TCF_Msk (0x1U << CAN_TSTS_TM2TCF_Pos) /*!< 0x00010000 */ +#define CAN_TSTS_TM2TCF CAN_TSTS_TM2TCF_Msk /*!< Transmit mailbox 2 transmission completed flag */ +#define CAN_TSTS_TM2TSF_Pos (17U) +#define CAN_TSTS_TM2TSF_Msk (0x1U << CAN_TSTS_TM2TSF_Pos) /*!< 0x00020000 */ +#define CAN_TSTS_TM2TSF CAN_TSTS_TM2TSF_Msk /*!< Transmit mailbox 2 transmission success flag */ +#define CAN_TSTS_TM2ALF_Pos (18U) +#define CAN_TSTS_TM2ALF_Msk (0x1U << CAN_TSTS_TM2ALF_Pos) /*!< 0x00040000 */ +#define CAN_TSTS_TM2ALF CAN_TSTS_TM2ALF_Msk /*!< Transmit mailbox 2 arbitration lost flag */ +#define CAN_TSTS_TM2TEF_Pos (19U) +#define CAN_TSTS_TM2TEF_Msk (0x1U << CAN_TSTS_TM2TEF_Pos) /*!< 0x00080000 */ +#define CAN_TSTS_TM2TEF CAN_TSTS_TM2TEF_Msk /*!< Transmit mailbox 2 transmission error flag */ +#define CAN_TSTS_TM2CT_Pos (23U) +#define CAN_TSTS_TM2CT_Msk (0x1U << CAN_TSTS_TM2CT_Pos) /*!< 0x00800000 */ +#define CAN_TSTS_TM2CT CAN_TSTS_TM2CT_Msk /*!< Transmit mailbox 2 cancel transmit */ +#define CAN_TSTS_TMNR_Pos (24U) +#define CAN_TSTS_TMNR_Msk (0x3U << CAN_TSTS_TMNR_Pos) /*!< 0x03000000 */ +#define CAN_TSTS_TMNR CAN_TSTS_TMNR_Msk /*!< TMNR[1:0] bits (Transmit mailbox number record) */ + +/*!< TMEF congiguration */ +#define CAN_TSTS_TMEF_Pos (26U) +#define CAN_TSTS_TMEF_Msk (0x7U << CAN_TSTS_TMEF_Pos) /*!< 0x1C000000 */ +#define CAN_TSTS_TMEF CAN_TSTS_TMEF_Msk /*!< TMEF[2:0] bits (Transmit mailbox empty flag) */ +#define CAN_TSTS_TM0EF_Pos (26U) +#define CAN_TSTS_TM0EF_Msk (0x1U << CAN_TSTS_TM0EF_Pos) /*!< 0x04000000 */ +#define CAN_TSTS_TM0EF CAN_TSTS_TM0EF_Msk /*!< Transmit mailbox 0 empty flag */ +#define CAN_TSTS_TM1EF_Pos (27U) +#define CAN_TSTS_TM1EF_Msk (0x1U << CAN_TSTS_TM1EF_Pos) /*!< 0x08000000 */ +#define CAN_TSTS_TM1EF CAN_TSTS_TM1EF_Msk /*!< Transmit mailbox 1 empty flag */ +#define CAN_TSTS_TM2EF_Pos (28U) +#define CAN_TSTS_TM2EF_Msk (0x1U << CAN_TSTS_TM2EF_Pos) /*!< 0x10000000 */ +#define CAN_TSTS_TM2EF CAN_TSTS_TM2EF_Msk /*!< Transmit mailbox 2 empty flag */ + +/*!< TMLPF congiguration */ +#define CAN_TSTS_TMLPF_Pos (29U) +#define CAN_TSTS_TMLPF_Msk (0x7U << CAN_TSTS_TMLPF_Pos) /*!< 0xE0000000 */ +#define CAN_TSTS_TMLPF CAN_TSTS_TMLPF_Msk /*!< TMLPF[2:0] bits (Transmit mailbox lowest priority flag) */ +#define CAN_TSTS_TM0LPF_Pos (29U) +#define CAN_TSTS_TM0LPF_Msk (0x1U << CAN_TSTS_TM0LPF_Pos) /*!< 0x20000000 */ +#define CAN_TSTS_TM0LPF CAN_TSTS_TM0LPF_Msk /*!< Transmit mailbox 0 lowest priority flag */ +#define CAN_TSTS_TM1LPF_Pos (30U) +#define CAN_TSTS_TM1LPF_Msk (0x1U << CAN_TSTS_TM1LPF_Pos) /*!< 0x40000000 */ +#define CAN_TSTS_TM1LPF CAN_TSTS_TM1LPF_Msk /*!< Transmit mailbox 1 lowest priority flag */ +#define CAN_TSTS_TM2LPF_Pos (31U) +#define CAN_TSTS_TM2LPF_Msk (0x1U << CAN_TSTS_TM2LPF_Pos) /*!< 0x80000000 */ +#define CAN_TSTS_TM2LPF CAN_TSTS_TM2LPF_Msk /*!< Transmit mailbox 2 lowest priority flag */ + +/******************* Bit definition for CAN_RF0 register ********************/ +#define CAN_RF0_RF0MN_Pos (0U) +#define CAN_RF0_RF0MN_Msk (0x3U << CAN_RF0_RF0MN_Pos) /*!< 0x00000003 */ +#define CAN_RF0_RF0MN CAN_RF0_RF0MN_Msk /*!< Receive FIFO 0 message num */ +#define CAN_RF0_RF0FF_Pos (3U) +#define CAN_RF0_RF0FF_Msk (0x1U << CAN_RF0_RF0FF_Pos) /*!< 0x00000008 */ +#define CAN_RF0_RF0FF CAN_RF0_RF0FF_Msk /*!< Receive FIFO 0 full flag */ +#define CAN_RF0_RF0OF_Pos (4U) +#define CAN_RF0_RF0OF_Msk (0x1U << CAN_RF0_RF0OF_Pos) /*!< 0x00000010 */ +#define CAN_RF0_RF0OF CAN_RF0_RF0OF_Msk /*!< Receive FIFO 0 overflow flag */ +#define CAN_RF0_RF0R_Pos (5U) +#define CAN_RF0_RF0R_Msk (0x1U << CAN_RF0_RF0R_Pos) /*!< 0x00000020 */ +#define CAN_RF0_RF0R CAN_RF0_RF0R_Msk /*!< Receive FIFO 0 release */ + +/******************* Bit definition for CAN_RF1 register ********************/ +#define CAN_RF1_RF1MN_Pos (0U) +#define CAN_RF1_RF1MN_Msk (0x3U << CAN_RF1_RF1MN_Pos) /*!< 0x00000003 */ +#define CAN_RF1_RF1MN CAN_RF1_RF1MN_Msk /*!< Receive FIFO 1 message num */ +#define CAN_RF1_RF1FF_Pos (3U) +#define CAN_RF1_RF1FF_Msk (0x1U << CAN_RF1_RF1FF_Pos) /*!< 0x00000008 */ +#define CAN_RF1_RF1FF CAN_RF1_RF1FF_Msk /*!< Receive FIFO 1 full flag */ +#define CAN_RF1_RF1OF_Pos (4U) +#define CAN_RF1_RF1OF_Msk (0x1U << CAN_RF1_RF1OF_Pos) /*!< 0x00000010 */ +#define CAN_RF1_RF1OF CAN_RF1_RF1OF_Msk /*!< Receive FIFO 1 overflow flag */ +#define CAN_RF1_RF1R_Pos (5U) +#define CAN_RF1_RF1R_Msk (0x1U << CAN_RF1_RF1R_Pos) /*!< 0x00000020 */ +#define CAN_RF1_RF1R CAN_RF1_RF1R_Msk /*!< Receive FIFO 1 release */ + +/****************** Bit definition for CAN_INTEN register *******************/ +#define CAN_INTEN_TCIEN_Pos (0U) +#define CAN_INTEN_TCIEN_Msk (0x1U << CAN_INTEN_TCIEN_Pos) /*!< 0x00000001 */ +#define CAN_INTEN_TCIEN CAN_INTEN_TCIEN_Msk /*!< Transmit mailbox empty interrupt enable */ +#define CAN_INTEN_RF0MIEN_Pos (1U) +#define CAN_INTEN_RF0MIEN_Msk (0x1U << CAN_INTEN_RF0MIEN_Pos) /*!< 0x00000002 */ +#define CAN_INTEN_RF0MIEN CAN_INTEN_RF0MIEN_Msk /*!< FIFO 0 receive message interrupt enable */ +#define CAN_INTEN_RF0FIEN_Pos (2U) +#define CAN_INTEN_RF0FIEN_Msk (0x1U << CAN_INTEN_RF0FIEN_Pos) /*!< 0x00000004 */ +#define CAN_INTEN_RF0FIEN CAN_INTEN_RF0FIEN_Msk /*!< Receive FIFO 0 full interrupt enable */ +#define CAN_INTEN_RF0OIEN_Pos (3U) +#define CAN_INTEN_RF0OIEN_Msk (0x1U << CAN_INTEN_RF0OIEN_Pos) /*!< 0x00000008 */ +#define CAN_INTEN_RF0OIEN CAN_INTEN_RF0OIEN_Msk /*!< Receive FIFO 0 overflow interrupt enable */ +#define CAN_INTEN_RF1MIEN_Pos (4U) +#define CAN_INTEN_RF1MIEN_Msk (0x1U << CAN_INTEN_RF1MIEN_Pos) /*!< 0x00000010 */ +#define CAN_INTEN_RF1MIEN CAN_INTEN_RF1MIEN_Msk /*!< FIFO 1 receive message interrupt enable */ +#define CAN_INTEN_RF1FIEN_Pos (5U) +#define CAN_INTEN_RF1FIEN_Msk (0x1U << CAN_INTEN_RF1FIEN_Pos) /*!< 0x00000020 */ +#define CAN_INTEN_RF1FIEN CAN_INTEN_RF1FIEN_Msk /*!< Receive FIFO 1 full interrupt enable */ +#define CAN_INTEN_RF1OIEN_Pos (6U) +#define CAN_INTEN_RF1OIEN_Msk (0x1U << CAN_INTEN_RF1OIEN_Pos) /*!< 0x00000040 */ +#define CAN_INTEN_RF1OIEN CAN_INTEN_RF1OIEN_Msk /*!< Receive FIFO 1 overflow interrupt enable */ +#define CAN_INTEN_EAIEN_Pos (8U) +#define CAN_INTEN_EAIEN_Msk (0x1U << CAN_INTEN_EAIEN_Pos) /*!< 0x00000100 */ +#define CAN_INTEN_EAIEN CAN_INTEN_EAIEN_Msk /*!< Error active interrupt enable */ +#define CAN_INTEN_EPIEN_Pos (9U) +#define CAN_INTEN_EPIEN_Msk (0x1U << CAN_INTEN_EPIEN_Pos) /*!< 0x00000200 */ +#define CAN_INTEN_EPIEN CAN_INTEN_EPIEN_Msk /*!< Error passive interrupt enable */ +#define CAN_INTEN_BOIEN_Pos (10U) +#define CAN_INTEN_BOIEN_Msk (0x1U << CAN_INTEN_BOIEN_Pos) /*!< 0x00000400 */ +#define CAN_INTEN_BOIEN CAN_INTEN_BOIEN_Msk /*!< Bus-off interrupt enable */ +#define CAN_INTEN_ETRIEN_Pos (11U) +#define CAN_INTEN_ETRIEN_Msk (0x1U << CAN_INTEN_ETRIEN_Pos) /*!< 0x00000800 */ +#define CAN_INTEN_ETRIEN CAN_INTEN_ETRIEN_Msk /*!< Error type record interrupt enable */ +#define CAN_INTEN_EOIEN_Pos (15U) +#define CAN_INTEN_EOIEN_Msk (0x1U << CAN_INTEN_EOIEN_Pos) /*!< 0x00008000 */ +#define CAN_INTEN_EOIEN CAN_INTEN_EOIEN_Msk /*!< Error occur interrupt enable */ +#define CAN_INTEN_QDZIEN_Pos (16U) +#define CAN_INTEN_QDZIEN_Msk (0x1U << CAN_INTEN_QDZIEN_Pos) /*!< 0x00010000 */ +#define CAN_INTEN_QDZIEN CAN_INTEN_QDZIEN_Msk /*!< Quit doze mode interrupt enable */ +#define CAN_INTEN_EDZIEN_Pos (17U) +#define CAN_INTEN_EDZIEN_Msk (0x1U << CAN_INTEN_EDZIEN_Pos) /*!< 0x00020000 */ +#define CAN_INTEN_EDZIEN CAN_INTEN_EDZIEN_Msk /*!< Enter doze mode interrupt enable */ + +/******************* Bit definition for CAN_ESTS register *******************/ +#define CAN_ESTS_EAF_Pos (0U) +#define CAN_ESTS_EAF_Msk (0x1U << CAN_ESTS_EAF_Pos) /*!< 0x00000001 */ +#define CAN_ESTS_EAF CAN_ESTS_EAF_Msk /*!< Error active flag */ +#define CAN_ESTS_EPF_Pos (1U) +#define CAN_ESTS_EPF_Msk (0x1U << CAN_ESTS_EPF_Pos) /*!< 0x00000002 */ +#define CAN_ESTS_EPF CAN_ESTS_EPF_Msk /*!< Error passive flag */ +#define CAN_ESTS_BOF_Pos (2U) +#define CAN_ESTS_BOF_Msk (0x1U << CAN_ESTS_BOF_Pos) /*!< 0x00000004 */ +#define CAN_ESTS_BOF CAN_ESTS_BOF_Msk /*!< Bus-off flag */ + +/*!< ETR congiguration */ +#define CAN_ESTS_ETR_Pos (4U) +#define CAN_ESTS_ETR_Msk (0x7U << CAN_ESTS_ETR_Pos) /*!< 0x00000070 */ +#define CAN_ESTS_ETR CAN_ESTS_ETR_Msk /*!< ETR[2:0] bits (Error type record) */ +#define CAN_ESTS_ETR_0 (0x1U << CAN_ESTS_ETR_Pos) /*!< 0x00000010 */ +#define CAN_ESTS_ETR_1 (0x2U << CAN_ESTS_ETR_Pos) /*!< 0x00000020 */ +#define CAN_ESTS_ETR_2 (0x4U << CAN_ESTS_ETR_Pos) /*!< 0x00000040 */ + +#define CAN_ESTS_TEC_Pos (16U) +#define CAN_ESTS_TEC_Msk (0xFFU << CAN_ESTS_TEC_Pos) /*!< 0x00FF0000 */ +#define CAN_ESTS_TEC CAN_ESTS_TEC_Msk /*!< Transmit error counter */ +#define CAN_ESTS_REC_Pos (24U) +#define CAN_ESTS_REC_Msk (0xFFU << CAN_ESTS_REC_Pos) /*!< 0xFF000000 */ +#define CAN_ESTS_REC CAN_ESTS_REC_Msk /*!< Receive error counter */ + +/******************* Bit definition for CAN_BTMG register ********************/ +#define CAN_BTMG_BRDIV_Pos (0U) +#define CAN_BTMG_BRDIV_Msk (0xFFFU << CAN_BTMG_BRDIV_Pos) /*!< 0x00000FFF */ +#define CAN_BTMG_BRDIV CAN_BTMG_BRDIV_Msk /*!< Baud rate division */ + +/*!< BTS1 congiguration */ +#define CAN_BTMG_BTS1_Pos (16U) +#define CAN_BTMG_BTS1_Msk (0xFU << CAN_BTMG_BTS1_Pos) /*!< 0x000F0000 */ +#define CAN_BTMG_BTS1 CAN_BTMG_BTS1_Msk /*!< BTS1[3:0] bits (Bit time segment 1) */ +#define CAN_BTMG_BTS1_0 (0x1U << CAN_BTMG_BTS1_Pos) /*!< 0x00010000 */ +#define CAN_BTMG_BTS1_1 (0x2U << CAN_BTMG_BTS1_Pos) /*!< 0x00020000 */ +#define CAN_BTMG_BTS1_2 (0x4U << CAN_BTMG_BTS1_Pos) /*!< 0x00040000 */ +#define CAN_BTMG_BTS1_3 (0x8U << CAN_BTMG_BTS1_Pos) /*!< 0x00080000 */ + +/*!< BTS2 congiguration */ +#define CAN_BTMG_BTS2_Pos (20U) +#define CAN_BTMG_BTS2_Msk (0x7U << CAN_BTMG_BTS2_Pos) /*!< 0x00700000 */ +#define CAN_BTMG_BTS2 CAN_BTMG_BTS2_Msk /*!< BTS2[2:0] bits (Bit time segment 2) */ +#define CAN_BTMG_BTS2_0 (0x1U << CAN_BTMG_BTS2_Pos) /*!< 0x00100000 */ +#define CAN_BTMG_BTS2_1 (0x2U << CAN_BTMG_BTS2_Pos) /*!< 0x00200000 */ +#define CAN_BTMG_BTS2_2 (0x4U << CAN_BTMG_BTS2_Pos) /*!< 0x00400000 */ + +/*!< RSAW congiguration */ +#define CAN_BTMG_RSAW_Pos (24U) +#define CAN_BTMG_RSAW_Msk (0x3U << CAN_BTMG_RSAW_Pos) /*!< 0x03000000 */ +#define CAN_BTMG_RSAW CAN_BTMG_RSAW_Msk /*!< RSAW[1:0] bits (Resynchronization width) */ +#define CAN_BTMG_RSAW_0 (0x1U << CAN_BTMG_RSAW_Pos) /*!< 0x01000000 */ +#define CAN_BTMG_RSAW_1 (0x2U << CAN_BTMG_RSAW_Pos) /*!< 0x02000000 */ + +#define CAN_BTMG_LBEN_Pos (30U) +#define CAN_BTMG_LBEN_Msk (0x1U << CAN_BTMG_LBEN_Pos) /*!< 0x40000000 */ +#define CAN_BTMG_LBEN CAN_BTMG_LBEN_Msk /*!< Loop back mode */ +#define CAN_BTMG_LOEN_Pos (31U) +#define CAN_BTMG_LOEN_Msk (0x1U << CAN_BTMG_LOEN_Pos) /*!< 0x80000000 */ +#define CAN_BTMG_LOEN CAN_BTMG_LOEN_Msk /*!< Listen-Only mode */ + +/*!< Mailbox registers */ +/******************* Bit definition for CAN_TMI0 register *******************/ +#define CAN_TMI0_TMSR_Pos (0U) +#define CAN_TMI0_TMSR_Msk (0x1U << CAN_TMI0_TMSR_Pos) /*!< 0x00000001 */ +#define CAN_TMI0_TMSR CAN_TMI0_TMSR_Msk /*!< Transmit mailbox send request */ +#define CAN_TMI0_TMFRSEL_Pos (1U) +#define CAN_TMI0_TMFRSEL_Msk (0x1U << CAN_TMI0_TMFRSEL_Pos) /*!< 0x00000002 */ +#define CAN_TMI0_TMFRSEL CAN_TMI0_TMFRSEL_Msk /*!< Transmit mailbox frame type select */ +#define CAN_TMI0_TMIDSEL_Pos (2U) +#define CAN_TMI0_TMIDSEL_Msk (0x1U << CAN_TMI0_TMIDSEL_Pos) /*!< 0x00000004 */ +#define CAN_TMI0_TMIDSEL CAN_TMI0_TMIDSEL_Msk /*!< Transmit mailbox identifier type select */ +#define CAN_TMI0_TMEID_Pos (3U) +#define CAN_TMI0_TMEID_Msk (0x3FFFFU << CAN_TMI0_TMEID_Pos) /*!< 0x001FFFF8 */ +#define CAN_TMI0_TMEID CAN_TMI0_TMEID_Msk /*!< Transmit mailbox extended identifier */ +#define CAN_TMI0_TMSID_Pos (21U) +#define CAN_TMI0_TMSID_Msk (0x7FFU << CAN_TMI0_TMSID_Pos) /*!< 0xFFE00000 */ +#define CAN_TMI0_TMSID CAN_TMI0_TMSID_Msk /*!< Transmit mailbox standard identifier or extended identifier high bytes */ + +/******************* Bit definition for CAN_TMC0 register *******************/ +#define CAN_TMC0_TMDTBL_Pos (0U) +#define CAN_TMC0_TMDTBL_Msk (0xFU << CAN_TMC0_TMDTBL_Pos) /*!< 0x0000000F */ +#define CAN_TMC0_TMDTBL CAN_TMC0_TMDTBL_Msk /*!< Transmit mailbox data byte length */ +#define CAN_TMC0_TMTSTEN_Pos (8U) +#define CAN_TMC0_TMTSTEN_Msk (0x1U << CAN_TMC0_TMTSTEN_Pos) /*!< 0x00000100 */ +#define CAN_TMC0_TMTSTEN CAN_TMC0_TMTSTEN_Msk /*!< Transmit mailbox time stamp transmit enable */ +#define CAN_TMC0_TMTS_Pos (16U) +#define CAN_TMC0_TMTS_Msk (0xFFFFU << CAN_TMC0_TMTS_Pos) /*!< 0xFFFF0000 */ +#define CAN_TMC0_TMTS CAN_TMC0_TMTS_Msk /*!< Transmit mailbox time stamp */ + +/****************** Bit definition for CAN_TMDTL0 register ******************/ +#define CAN_TMDTL0_TMDT0_Pos (0U) +#define CAN_TMDTL0_TMDT0_Msk (0xFFU << CAN_TMDTL0_TMDT0_Pos) /*!< 0x000000FF */ +#define CAN_TMDTL0_TMDT0 CAN_TMDTL0_TMDT0_Msk /*!< Transmit mailbox data byte 0 */ +#define CAN_TMDTL0_TMDT1_Pos (8U) +#define CAN_TMDTL0_TMDT1_Msk (0xFFU << CAN_TMDTL0_TMDT1_Pos) /*!< 0x0000FF00 */ +#define CAN_TMDTL0_TMDT1 CAN_TMDTL0_TMDT1_Msk /*!< Transmit mailbox data byte 1 */ +#define CAN_TMDTL0_TMDT2_Pos (16U) +#define CAN_TMDTL0_TMDT2_Msk (0xFFU << CAN_TMDTL0_TMDT2_Pos) /*!< 0x00FF0000 */ +#define CAN_TMDTL0_TMDT2 CAN_TMDTL0_TMDT2_Msk /*!< Transmit mailbox data byte 2 */ +#define CAN_TMDTL0_TMDT3_Pos (24U) +#define CAN_TMDTL0_TMDT3_Msk (0xFFU << CAN_TMDTL0_TMDT3_Pos) /*!< 0xFF000000 */ +#define CAN_TMDTL0_TMDT3 CAN_TMDTL0_TMDT3_Msk /*!< Transmit mailbox data byte 3 */ + +/****************** Bit definition for CAN_TMDTH0 register ******************/ +#define CAN_TMDTH0_TMDT4_Pos (0U) +#define CAN_TMDTH0_TMDT4_Msk (0xFFU << CAN_TMDTH0_TMDT4_Pos) /*!< 0x000000FF */ +#define CAN_TMDTH0_TMDT4 CAN_TMDTH0_TMDT4_Msk /*!< Transmit mailbox data byte 4 */ +#define CAN_TMDTH0_TMDT5_Pos (8U) +#define CAN_TMDTH0_TMDT5_Msk (0xFFU << CAN_TMDTH0_TMDT5_Pos) /*!< 0x0000FF00 */ +#define CAN_TMDTH0_TMDT5 CAN_TMDTH0_TMDT5_Msk /*!< Transmit mailbox data byte 5 */ +#define CAN_TMDTH0_TMDT6_Pos (16U) +#define CAN_TMDTH0_TMDT6_Msk (0xFFU << CAN_TMDTH0_TMDT6_Pos) /*!< 0x00FF0000 */ +#define CAN_TMDTH0_TMDT6 CAN_TMDTH0_TMDT6_Msk /*!< Transmit mailbox data byte 6 */ +#define CAN_TMDTH0_TMDT7_Pos (24U) +#define CAN_TMDTH0_TMDT7_Msk (0xFFU << CAN_TMDTH0_TMDT7_Pos) /*!< 0xFF000000 */ +#define CAN_TMDTH0_TMDT7 CAN_TMDTH0_TMDT7_Msk /*!< Transmit mailbox data byte 7 */ + +/******************* Bit definition for CAN_TMI1 register *******************/ +#define CAN_TMI1_TMSR_Pos (0U) +#define CAN_TMI1_TMSR_Msk (0x1U << CAN_TMI1_TMSR_Pos) /*!< 0x00000001 */ +#define CAN_TMI1_TMSR CAN_TMI1_TMSR_Msk /*!< Transmit mailbox send request */ +#define CAN_TMI1_TMFRSEL_Pos (1U) +#define CAN_TMI1_TMFRSEL_Msk (0x1U << CAN_TMI1_TMFRSEL_Pos) /*!< 0x00000002 */ +#define CAN_TMI1_TMFRSEL CAN_TMI1_TMFRSEL_Msk /*!< Transmit mailbox frame type select */ +#define CAN_TMI1_TMIDSEL_Pos (2U) +#define CAN_TMI1_TMIDSEL_Msk (0x1U << CAN_TMI1_TMIDSEL_Pos) /*!< 0x00000004 */ +#define CAN_TMI1_TMIDSEL CAN_TMI1_TMIDSEL_Msk /*!< Transmit mailbox identifier type select */ +#define CAN_TMI1_TMEID_Pos (3U) +#define CAN_TMI1_TMEID_Msk (0x3FFFFU << CAN_TMI1_TMEID_Pos) /*!< 0x001FFFF8 */ +#define CAN_TMI1_TMEID CAN_TMI1_TMEID_Msk /*!< Transmit mailbox extended identifier */ +#define CAN_TMI1_TMSID_Pos (21U) +#define CAN_TMI1_TMSID_Msk (0x7FFU << CAN_TMI1_TMSID_Pos) /*!< 0xFFE00000 */ +#define CAN_TMI1_TMSID CAN_TMI1_TMSID_Msk /*!< Transmit mailbox standard identifier or extended identifier high bytes */ + +/******************* Bit definition for CAN_TMC1 register *******************/ +#define CAN_TMC1_TMDTBL_Pos (0U) +#define CAN_TMC1_TMDTBL_Msk (0xFU << CAN_TMC1_TMDTBL_Pos) /*!< 0x0000000F */ +#define CAN_TMC1_TMDTBL CAN_TMC1_TMDTBL_Msk /*!< Transmit mailbox data byte length */ +#define CAN_TMC1_TMTSTEN_Pos (8U) +#define CAN_TMC1_TMTSTEN_Msk (0x1U << CAN_TMC1_TMTSTEN_Pos) /*!< 0x00000100 */ +#define CAN_TMC1_TMTSTEN CAN_TMC1_TMTSTEN_Msk /*!< Transmit mailbox time stamp transmit enable */ +#define CAN_TMC1_TMTS_Pos (16U) +#define CAN_TMC1_TMTS_Msk (0xFFFFU << CAN_TMC1_TMTS_Pos) /*!< 0xFFFF0000 */ +#define CAN_TMC1_TMTS CAN_TMC1_TMTS_Msk /*!< Transmit mailbox time stamp */ + +/****************** Bit definition for CAN_TMDTL1 register ******************/ +#define CAN_TMDTL1_TMDT0_Pos (0U) +#define CAN_TMDTL1_TMDT0_Msk (0xFFU << CAN_TMDTL1_TMDT0_Pos) /*!< 0x000000FF */ +#define CAN_TMDTL1_TMDT0 CAN_TMDTL1_TMDT0_Msk /*!< Transmit mailbox data byte 0 */ +#define CAN_TMDTL1_TMDT1_Pos (8U) +#define CAN_TMDTL1_TMDT1_Msk (0xFFU << CAN_TMDTL1_TMDT1_Pos) /*!< 0x0000FF00 */ +#define CAN_TMDTL1_TMDT1 CAN_TMDTL1_TMDT1_Msk /*!< Transmit mailbox data byte 1 */ +#define CAN_TMDTL1_TMDT2_Pos (16U) +#define CAN_TMDTL1_TMDT2_Msk (0xFFU << CAN_TMDTL1_TMDT2_Pos) /*!< 0x00FF0000 */ +#define CAN_TMDTL1_TMDT2 CAN_TMDTL1_TMDT2_Msk /*!< Transmit mailbox data byte 2 */ +#define CAN_TMDTL1_TMDT3_Pos (24U) +#define CAN_TMDTL1_TMDT3_Msk (0xFFU << CAN_TMDTL1_TMDT3_Pos) /*!< 0xFF000000 */ +#define CAN_TMDTL1_TMDT3 CAN_TMDTL1_TMDT3_Msk /*!< Transmit mailbox data byte 3 */ + +/****************** Bit definition for CAN_TMDTH1 register ******************/ +#define CAN_TMDTH1_TMDT4_Pos (0U) +#define CAN_TMDTH1_TMDT4_Msk (0xFFU << CAN_TMDTH1_TMDT4_Pos) /*!< 0x000000FF */ +#define CAN_TMDTH1_TMDT4 CAN_TMDTH1_TMDT4_Msk /*!< Transmit mailbox data byte 4 */ +#define CAN_TMDTH1_TMDT5_Pos (8U) +#define CAN_TMDTH1_TMDT5_Msk (0xFFU << CAN_TMDTH1_TMDT5_Pos) /*!< 0x0000FF00 */ +#define CAN_TMDTH1_TMDT5 CAN_TMDTH1_TMDT5_Msk /*!< Transmit mailbox data byte 5 */ +#define CAN_TMDTH1_TMDT6_Pos (16U) +#define CAN_TMDTH1_TMDT6_Msk (0xFFU << CAN_TMDTH1_TMDT6_Pos) /*!< 0x00FF0000 */ +#define CAN_TMDTH1_TMDT6 CAN_TMDTH1_TMDT6_Msk /*!< Transmit mailbox data byte 6 */ +#define CAN_TMDTH1_TMDT7_Pos (24U) +#define CAN_TMDTH1_TMDT7_Msk (0xFFU << CAN_TMDTH1_TMDT7_Pos) /*!< 0xFF000000 */ +#define CAN_TMDTH1_TMDT7 CAN_TMDTH1_TMDT7_Msk /*!< Transmit mailbox data byte 7 */ + +/******************* Bit definition for CAN_TMI2 register *******************/ +#define CAN_TMI2_TMSR_Pos (0U) +#define CAN_TMI2_TMSR_Msk (0x1U << CAN_TMI2_TMSR_Pos) /*!< 0x00000001 */ +#define CAN_TMI2_TMSR CAN_TMI2_TMSR_Msk /*!< Transmit mailbox send request */ +#define CAN_TMI2_TMFRSEL_Pos (1U) +#define CAN_TMI2_TMFRSEL_Msk (0x1U << CAN_TMI2_TMFRSEL_Pos) /*!< 0x00000002 */ +#define CAN_TMI2_TMFRSEL CAN_TMI2_TMFRSEL_Msk /*!< Transmit mailbox frame type select */ +#define CAN_TMI2_TMIDSEL_Pos (2U) +#define CAN_TMI2_TMIDSEL_Msk (0x1U << CAN_TMI2_TMIDSEL_Pos) /*!< 0x00000004 */ +#define CAN_TMI2_TMIDSEL CAN_TMI2_TMIDSEL_Msk /*!< Transmit mailbox identifier type select */ +#define CAN_TMI2_TMEID_Pos (3U) +#define CAN_TMI2_TMEID_Msk (0x3FFFFU << CAN_TMI2_TMEID_Pos) /*!< 0x001FFFF8 */ +#define CAN_TMI2_TMEID CAN_TMI2_TMEID_Msk /*!< Transmit mailbox extended identifier */ +#define CAN_TMI2_TMSID_Pos (21U) +#define CAN_TMI2_TMSID_Msk (0x7FFU << CAN_TMI2_TMSID_Pos) /*!< 0xFFE00000 */ +#define CAN_TMI2_TMSID CAN_TMI2_TMSID_Msk /*!< Transmit mailbox standard identifier or extended identifier high bytes */ + +/******************* Bit definition for CAN_TMC2 register *******************/ +#define CAN_TMC2_TMDTBL_Pos (0U) +#define CAN_TMC2_TMDTBL_Msk (0xFU << CAN_TMC2_TMDTBL_Pos) /*!< 0x0000000F */ +#define CAN_TMC2_TMDTBL CAN_TMC2_TMDTBL_Msk /*!< Transmit mailbox data byte length */ +#define CAN_TMC2_TMTSTEN_Pos (8U) +#define CAN_TMC2_TMTSTEN_Msk (0x1U << CAN_TMC2_TMTSTEN_Pos) /*!< 0x00000100 */ +#define CAN_TMC2_TMTSTEN CAN_TMC2_TMTSTEN_Msk /*!< Transmit mailbox time stamp transmit enable */ +#define CAN_TMC2_TMTS_Pos (16U) +#define CAN_TMC2_TMTS_Msk (0xFFFFU << CAN_TMC2_TMTS_Pos) /*!< 0xFFFF0000 */ +#define CAN_TMC2_TMTS CAN_TMC2_TMTS_Msk /*!< Transmit mailbox time stamp */ + +/****************** Bit definition for CAN_TMDTL2 register ******************/ +#define CAN_TMDTL2_TMDT0_Pos (0U) +#define CAN_TMDTL2_TMDT0_Msk (0xFFU << CAN_TMDTL2_TMDT0_Pos) /*!< 0x000000FF */ +#define CAN_TMDTL2_TMDT0 CAN_TMDTL2_TMDT0_Msk /*!< Transmit mailbox data byte 0 */ +#define CAN_TMDTL2_TMDT1_Pos (8U) +#define CAN_TMDTL2_TMDT1_Msk (0xFFU << CAN_TMDTL2_TMDT1_Pos) /*!< 0x0000FF00 */ +#define CAN_TMDTL2_TMDT1 CAN_TMDTL2_TMDT1_Msk /*!< Transmit mailbox data byte 1 */ +#define CAN_TMDTL2_TMDT2_Pos (16U) +#define CAN_TMDTL2_TMDT2_Msk (0xFFU << CAN_TMDTL2_TMDT2_Pos) /*!< 0x00FF0000 */ +#define CAN_TMDTL2_TMDT2 CAN_TMDTL2_TMDT2_Msk /*!< Transmit mailbox data byte 2 */ +#define CAN_TMDTL2_TMDT3_Pos (24U) +#define CAN_TMDTL2_TMDT3_Msk (0xFFU << CAN_TMDTL2_TMDT3_Pos) /*!< 0xFF000000 */ +#define CAN_TMDTL2_TMDT3 CAN_TMDTL2_TMDT3_Msk /*!< Transmit mailbox data byte 3 */ + +/****************** Bit definition for CAN_TMDTH2 register ******************/ +#define CAN_TMDTH2_TMDT4_Pos (0U) +#define CAN_TMDTH2_TMDT4_Msk (0xFFU << CAN_TMDTH2_TMDT4_Pos) /*!< 0x000000FF */ +#define CAN_TMDTH2_TMDT4 CAN_TMDTH2_TMDT4_Msk /*!< Transmit mailbox data byte 4 */ +#define CAN_TMDTH2_TMDT5_Pos (8U) +#define CAN_TMDTH2_TMDT5_Msk (0xFFU << CAN_TMDTH2_TMDT5_Pos) /*!< 0x0000FF00 */ +#define CAN_TMDTH2_TMDT5 CAN_TMDTH2_TMDT5_Msk /*!< Transmit mailbox data byte 5 */ +#define CAN_TMDTH2_TMDT6_Pos (16U) +#define CAN_TMDTH2_TMDT6_Msk (0xFFU << CAN_TMDTH2_TMDT6_Pos) /*!< 0x00FF0000 */ +#define CAN_TMDTH2_TMDT6 CAN_TMDTH2_TMDT6_Msk /*!< Transmit mailbox data byte 6 */ +#define CAN_TMDTH2_TMDT7_Pos (24U) +#define CAN_TMDTH2_TMDT7_Msk (0xFFU << CAN_TMDTH2_TMDT7_Pos) /*!< 0xFF000000 */ +#define CAN_TMDTH2_TMDT7 CAN_TMDTH2_TMDT7_Msk /*!< Transmit mailbox data byte 7 */ + +/******************* Bit definition for CAN_RFI0 register *******************/ +#define CAN_RFI0_RFFRI_Pos (1U) +#define CAN_RFI0_RFFRI_Msk (0x1U << CAN_RFI0_RFFRI_Pos) /*!< 0x00000002 */ +#define CAN_RFI0_RFFRI CAN_RFI0_RFFRI_Msk /*!< Receive FIFO frame type indication */ +#define CAN_RFI0_RFIDI_Pos (2U) +#define CAN_RFI0_RFIDI_Msk (0x1U << CAN_RFI0_RFIDI_Pos) /*!< 0x00000004 */ +#define CAN_RFI0_RFIDI CAN_RFI0_RFIDI_Msk /*!< Receive FIFO identifier type indication */ +#define CAN_RFI0_RFEID_Pos (3U) +#define CAN_RFI0_RFEID_Msk (0x3FFFFU << CAN_RFI0_RFEID_Pos) /*!< 0x001FFFF8 */ +#define CAN_RFI0_RFEID CAN_RFI0_RFEID_Msk /*!< Receive FIFO extended identifier */ +#define CAN_RFI0_RFSID_Pos (21U) +#define CAN_RFI0_RFSID_Msk (0x7FFU << CAN_RFI0_RFSID_Pos) /*!< 0xFFE00000 */ +#define CAN_RFI0_RFSID CAN_RFI0_RFSID_Msk /*!< Receive FIFO standard identifier or receive FIFO extended identifier */ + +/******************* Bit definition for CAN_RFC0 register *******************/ +#define CAN_RFC0_RFDTL_Pos (0U) +#define CAN_RFC0_RFDTL_Msk (0xFU << CAN_RFC0_RFDTL_Pos) /*!< 0x0000000F */ +#define CAN_RFC0_RFDTL CAN_RFC0_RFDTL_Msk /*!< Receive FIFO data length */ +#define CAN_RFC0_RFFMN_Pos (8U) +#define CAN_RFC0_RFFMN_Msk (0xFFU << CAN_RFC0_RFFMN_Pos) /*!< 0x0000FF00 */ +#define CAN_RFC0_RFFMN CAN_RFC0_RFFMN_Msk /*!< Receive FIFO filter match number */ +#define CAN_RFC0_RFTS_Pos (16U) +#define CAN_RFC0_RFTS_Msk (0xFFFFU << CAN_RFC0_RFTS_Pos) /*!< 0xFFFF0000 */ +#define CAN_RFC0_RFTS CAN_RFC0_RFTS_Msk /*!< Receive FIFO time stamp */ + +/****************** Bit definition for CAN_RFDTL0 register ******************/ +#define CAN_RFDTL0_RFDT0_Pos (0U) +#define CAN_RFDTL0_RFDT0_Msk (0xFFU << CAN_RFDTL0_RFDT0_Pos) /*!< 0x000000FF */ +#define CAN_RFDTL0_RFDT0 CAN_RFDTL0_RFDT0_Msk /*!< Receive FIFO data byte 0 */ +#define CAN_RFDTL0_RFDT1_Pos (8U) +#define CAN_RFDTL0_RFDT1_Msk (0xFFU << CAN_RFDTL0_RFDT1_Pos) /*!< 0x0000FF00 */ +#define CAN_RFDTL0_RFDT1 CAN_RFDTL0_RFDT1_Msk /*!< Receive FIFO data byte 1 */ +#define CAN_RFDTL0_RFDT2_Pos (16U) +#define CAN_RFDTL0_RFDT2_Msk (0xFFU << CAN_RFDTL0_RFDT2_Pos) /*!< 0x00FF0000 */ +#define CAN_RFDTL0_RFDT2 CAN_RFDTL0_RFDT2_Msk /*!< Receive FIFO data byte 2 */ +#define CAN_RFDTL0_RFDT3_Pos (24U) +#define CAN_RFDTL0_RFDT3_Msk (0xFFU << CAN_RFDTL0_RFDT3_Pos) /*!< 0xFF000000 */ +#define CAN_RFDTL0_RFDT3 CAN_RFDTL0_RFDT3_Msk /*!< Receive FIFO data byte 3 */ + +/****************** Bit definition for CAN_RFDTH0 register ******************/ +#define CAN_RFDTH0_RFDT4_Pos (0U) +#define CAN_RFDTH0_RFDT4_Msk (0xFFU << CAN_RFDTH0_RFDT4_Pos) /*!< 0x000000FF */ +#define CAN_RFDTH0_RFDT4 CAN_RFDTH0_RFDT4_Msk /*!< Receive FIFO data byte 4 */ +#define CAN_RFDTH0_RFDT5_Pos (8U) +#define CAN_RFDTH0_RFDT5_Msk (0xFFU << CAN_RFDTH0_RFDT5_Pos) /*!< 0x0000FF00 */ +#define CAN_RFDTH0_RFDT5 CAN_RFDTH0_RFDT5_Msk /*!< Receive FIFO data byte 5 */ +#define CAN_RFDTH0_RFDT6_Pos (16U) +#define CAN_RFDTH0_RFDT6_Msk (0xFFU << CAN_RFDTH0_RFDT6_Pos) /*!< 0x00FF0000 */ +#define CAN_RFDTH0_RFDT6 CAN_RFDTH0_RFDT6_Msk /*!< Receive FIFO data byte 6 */ +#define CAN_RFDTH0_RFDT7_Pos (24U) +#define CAN_RFDTH0_RFDT7_Msk (0xFFU << CAN_RFDTH0_RFDT7_Pos) /*!< 0xFF000000 */ +#define CAN_RFDTH0_RFDT7 CAN_RFDTH0_RFDT7_Msk /*!< Receive FIFO data byte 7 */ + +/******************* Bit definition for CAN_RFI1 register *******************/ +#define CAN_RFI1_RFFRI_Pos (1U) +#define CAN_RFI1_RFFRI_Msk (0x1U << CAN_RFI1_RFFRI_Pos) /*!< 0x00000002 */ +#define CAN_RFI1_RFFRI CAN_RFI1_RFFRI_Msk /*!< Receive FIFO frame type indication */ +#define CAN_RFI1_RFIDI_Pos (2U) +#define CAN_RFI1_RFIDI_Msk (0x1U << CAN_RFI1_RFIDI_Pos) /*!< 0x00000004 */ +#define CAN_RFI1_RFIDI CAN_RFI1_RFIDI_Msk /*!< Receive FIFO identifier type indication */ +#define CAN_RFI1_RFEID_Pos (3U) +#define CAN_RFI1_RFEID_Msk (0x3FFFFU << CAN_RFI1_RFEID_Pos) /*!< 0x001FFFF8 */ +#define CAN_RFI1_RFEID CAN_RFI1_RFEID_Msk /*!< Receive FIFO extended identifier */ +#define CAN_RFI1_RFSID_Pos (21U) +#define CAN_RFI1_RFSID_Msk (0x7FFU << CAN_RFI1_RFSID_Pos) /*!< 0xFFE00000 */ +#define CAN_RFI1_RFSID CAN_RFI1_RFSID_Msk /*!< Receive FIFO standard identifier or receive FIFO extended identifier */ + +/******************* Bit definition for CAN_RFC1 register *******************/ +#define CAN_RFC1_RFDTL_Pos (0U) +#define CAN_RFC1_RFDTL_Msk (0xFU << CAN_RFC1_RFDTL_Pos) /*!< 0x0000000F */ +#define CAN_RFC1_RFDTL CAN_RFC1_RFDTL_Msk /*!< Receive FIFO data length */ +#define CAN_RFC1_RFFMN_Pos (8U) +#define CAN_RFC1_RFFMN_Msk (0xFFU << CAN_RFC1_RFFMN_Pos) /*!< 0x0000FF00 */ +#define CAN_RFC1_RFFMN CAN_RFC1_RFFMN_Msk /*!< Receive FIFO filter match number */ +#define CAN_RFC1_RFTS_Pos (16U) +#define CAN_RFC1_RFTS_Msk (0xFFFFU << CAN_RFC1_RFTS_Pos) /*!< 0xFFFF0000 */ +#define CAN_RFC1_RFTS CAN_RFC1_RFTS_Msk /*!< Receive FIFO time stamp */ + +/****************** Bit definition for CAN_RFDTL1 register ******************/ +#define CAN_RFDTL1_RFDT0_Pos (0U) +#define CAN_RFDTL1_RFDT0_Msk (0xFFU << CAN_RFDTL1_RFDT0_Pos) /*!< 0x000000FF */ +#define CAN_RFDTL1_RFDT0 CAN_RFDTL1_RFDT0_Msk /*!< Receive FIFO data byte 0 */ +#define CAN_RFDTL1_RFDT1_Pos (8U) +#define CAN_RFDTL1_RFDT1_Msk (0xFFU << CAN_RFDTL1_RFDT1_Pos) /*!< 0x0000FF00 */ +#define CAN_RFDTL1_RFDT1 CAN_RFDTL1_RFDT1_Msk /*!< Receive FIFO data byte 1 */ +#define CAN_RFDTL1_RFDT2_Pos (16U) +#define CAN_RFDTL1_RFDT2_Msk (0xFFU << CAN_RFDTL1_RFDT2_Pos) /*!< 0x00FF0000 */ +#define CAN_RFDTL1_RFDT2 CAN_RFDTL1_RFDT2_Msk /*!< Receive FIFO data byte 2 */ +#define CAN_RFDTL1_RFDT3_Pos (24U) +#define CAN_RFDTL1_RFDT3_Msk (0xFFU << CAN_RFDTL1_RFDT3_Pos) /*!< 0xFF000000 */ +#define CAN_RFDTL1_RFDT3 CAN_RFDTL1_RFDT3_Msk /*!< Receive FIFO data byte 3 */ + +/****************** Bit definition for CAN_RFDTH1 register ******************/ +#define CAN_RFDTH1_RFDT4_Pos (0U) +#define CAN_RFDTH1_RFDT4_Msk (0xFFU << CAN_RFDTH1_RFDT4_Pos) /*!< 0x000000FF */ +#define CAN_RFDTH1_RFDT4 CAN_RFDTH1_RFDT4_Msk /*!< Receive FIFO data byte 4 */ +#define CAN_RFDTH1_RFDT5_Pos (8U) +#define CAN_RFDTH1_RFDT5_Msk (0xFFU << CAN_RFDTH1_RFDT5_Pos) /*!< 0x0000FF00 */ +#define CAN_RFDTH1_RFDT5 CAN_RFDTH1_RFDT5_Msk /*!< Receive FIFO data byte 5 */ +#define CAN_RFDTH1_RFDT6_Pos (16U) +#define CAN_RFDTH1_RFDT6_Msk (0xFFU << CAN_RFDTH1_RFDT6_Pos) /*!< 0x00FF0000 */ +#define CAN_RFDTH1_RFDT6 CAN_RFDTH1_RFDT6_Msk /*!< Receive FIFO data byte 6 */ +#define CAN_RFDTH1_RFDT7_Pos (24U) +#define CAN_RFDTH1_RFDT7_Msk (0xFFU << CAN_RFDTH1_RFDT7_Pos) /*!< 0xFF000000 */ +#define CAN_RFDTH1_RFDT7 CAN_RFDTH1_RFDT7_Msk /*!< Receive FIFO data byte 7 */ + +/*!< CAN filter registers */ +/****************** Bit definition for CAN_FCTRL register *******************/ +#define CAN_FCTRL_FCS_Pos (0U) +#define CAN_FCTRL_FCS_Msk (0x1U << CAN_FCTRL_FCS_Pos) /*!< 0x00000001 */ +#define CAN_FCTRL_FCS CAN_FCTRL_FCS_Msk /*!< Filter configuration switch */ + +/****************** Bit definition for CAN_FMCFG register *******************/ +#define CAN_FMCFG_FMSEL_Pos (0U) +#define CAN_FMCFG_FMSEL_Msk (0xFFFFFFFU << CAN_FMCFG_FMSEL_Pos) /*!< 0x0FFFFFFF */ +#define CAN_FMCFG_FMSEL CAN_FMCFG_FMSEL_Msk /*!< Filter mode select */ +#define CAN_FMCFG_FMSEL0_Pos (0U) +#define CAN_FMCFG_FMSEL0_Msk (0x1U << CAN_FMCFG_FMSEL0_Pos) /*!< 0x00000001 */ +#define CAN_FMCFG_FMSEL0 CAN_FMCFG_FMSEL0_Msk /*!< Filter mode select for filter 0 */ +#define CAN_FMCFG_FMSEL1_Pos (1U) +#define CAN_FMCFG_FMSEL1_Msk (0x1U << CAN_FMCFG_FMSEL1_Pos) /*!< 0x00000002 */ +#define CAN_FMCFG_FMSEL1 CAN_FMCFG_FMSEL1_Msk /*!< Filter mode select for filter 1 */ +#define CAN_FMCFG_FMSEL2_Pos (2U) +#define CAN_FMCFG_FMSEL2_Msk (0x1U << CAN_FMCFG_FMSEL2_Pos) /*!< 0x00000004 */ +#define CAN_FMCFG_FMSEL2 CAN_FMCFG_FMSEL2_Msk /*!< Filter mode select for filter 2 */ +#define CAN_FMCFG_FMSEL3_Pos (3U) +#define CAN_FMCFG_FMSEL3_Msk (0x1U << CAN_FMCFG_FMSEL3_Pos) /*!< 0x00000008 */ +#define CAN_FMCFG_FMSEL3 CAN_FMCFG_FMSEL3_Msk /*!< Filter mode select for filter 3 */ +#define CAN_FMCFG_FMSEL4_Pos (4U) +#define CAN_FMCFG_FMSEL4_Msk (0x1U << CAN_FMCFG_FMSEL4_Pos) /*!< 0x00000010 */ +#define CAN_FMCFG_FMSEL4 CAN_FMCFG_FMSEL4_Msk /*!< Filter mode select for filter 4 */ +#define CAN_FMCFG_FMSEL5_Pos (5U) +#define CAN_FMCFG_FMSEL5_Msk (0x1U << CAN_FMCFG_FMSEL5_Pos) /*!< 0x00000020 */ +#define CAN_FMCFG_FMSEL5 CAN_FMCFG_FMSEL5_Msk /*!< Filter mode select for filter 5 */ +#define CAN_FMCFG_FMSEL6_Pos (6U) +#define CAN_FMCFG_FMSEL6_Msk (0x1U << CAN_FMCFG_FMSEL6_Pos) /*!< 0x00000040 */ +#define CAN_FMCFG_FMSEL6 CAN_FMCFG_FMSEL6_Msk /*!< Filter mode select for filter 6 */ +#define CAN_FMCFG_FMSEL7_Pos (7U) +#define CAN_FMCFG_FMSEL7_Msk (0x1U << CAN_FMCFG_FMSEL7_Pos) /*!< 0x00000080 */ +#define CAN_FMCFG_FMSEL7 CAN_FMCFG_FMSEL7_Msk /*!< Filter mode select for filter 7 */ +#define CAN_FMCFG_FMSEL8_Pos (8U) +#define CAN_FMCFG_FMSEL8_Msk (0x1U << CAN_FMCFG_FMSEL8_Pos) /*!< 0x00000100 */ +#define CAN_FMCFG_FMSEL8 CAN_FMCFG_FMSEL8_Msk /*!< Filter mode select for filter 8 */ +#define CAN_FMCFG_FMSEL9_Pos (9U) +#define CAN_FMCFG_FMSEL9_Msk (0x1U << CAN_FMCFG_FMSEL9_Pos) /*!< 0x00000200 */ +#define CAN_FMCFG_FMSEL9 CAN_FMCFG_FMSEL9_Msk /*!< Filter mode select for filter 9 */ +#define CAN_FMCFG_FMSEL10_Pos (10U) +#define CAN_FMCFG_FMSEL10_Msk (0x1U << CAN_FMCFG_FMSEL10_Pos) /*!< 0x00000400 */ +#define CAN_FMCFG_FMSEL10 CAN_FMCFG_FMSEL10_Msk /*!< Filter mode select for filter 10 */ +#define CAN_FMCFG_FMSEL11_Pos (11U) +#define CAN_FMCFG_FMSEL11_Msk (0x1U << CAN_FMCFG_FMSEL11_Pos) /*!< 0x00000800 */ +#define CAN_FMCFG_FMSEL11 CAN_FMCFG_FMSEL11_Msk /*!< Filter mode select for filter 11 */ +#define CAN_FMCFG_FMSEL12_Pos (12U) +#define CAN_FMCFG_FMSEL12_Msk (0x1U << CAN_FMCFG_FMSEL12_Pos) /*!< 0x00001000 */ +#define CAN_FMCFG_FMSEL12 CAN_FMCFG_FMSEL12_Msk /*!< Filter mode select for filter 12 */ +#define CAN_FMCFG_FMSEL13_Pos (13U) +#define CAN_FMCFG_FMSEL13_Msk (0x1U << CAN_FMCFG_FMSEL13_Pos) /*!< 0x00002000 */ +#define CAN_FMCFG_FMSEL13 CAN_FMCFG_FMSEL13_Msk /*!< Filter mode select for filter 13 */ +#define CAN_FMCFG_FMSEL14_Pos (14U) +#define CAN_FMCFG_FMSEL14_Msk (0x1U << CAN_FMCFG_FMSEL14_Pos) /*!< 0x00004000 */ +#define CAN_FMCFG_FMSEL14 CAN_FMCFG_FMSEL14_Msk /*!< Filter mode select for filter 14 */ +#define CAN_FMCFG_FMSEL15_Pos (15U) +#define CAN_FMCFG_FMSEL15_Msk (0x1U << CAN_FMCFG_FMSEL15_Pos) /*!< 0x00008000 */ +#define CAN_FMCFG_FMSEL15 CAN_FMCFG_FMSEL15_Msk /*!< Filter mode select for filter 15 */ +#define CAN_FMCFG_FMSEL16_Pos (16U) +#define CAN_FMCFG_FMSEL16_Msk (0x1U << CAN_FMCFG_FMSEL16_Pos) /*!< 0x00010000 */ +#define CAN_FMCFG_FMSEL16 CAN_FMCFG_FMSEL16_Msk /*!< Filter mode select for filter 16 */ +#define CAN_FMCFG_FMSEL17_Pos (17U) +#define CAN_FMCFG_FMSEL17_Msk (0x1U << CAN_FMCFG_FMSEL17_Pos) /*!< 0x00020000 */ +#define CAN_FMCFG_FMSEL17 CAN_FMCFG_FMSEL17_Msk /*!< Filter mode select for filter 17 */ +#define CAN_FMCFG_FMSEL18_Pos (18U) +#define CAN_FMCFG_FMSEL18_Msk (0x1U << CAN_FMCFG_FMSEL18_Pos) /*!< 0x00040000 */ +#define CAN_FMCFG_FMSEL18 CAN_FMCFG_FMSEL18_Msk /*!< Filter mode select for filter 18 */ +#define CAN_FMCFG_FMSEL19_Pos (19U) +#define CAN_FMCFG_FMSEL19_Msk (0x1U << CAN_FMCFG_FMSEL19_Pos) /*!< 0x00080000 */ +#define CAN_FMCFG_FMSEL19 CAN_FMCFG_FMSEL19_Msk /*!< Filter mode select for filter 19 */ +#define CAN_FMCFG_FMSEL20_Pos (20U) +#define CAN_FMCFG_FMSEL20_Msk (0x1U << CAN_FMCFG_FMSEL20_Pos) /*!< 0x00100000 */ +#define CAN_FMCFG_FMSEL20 CAN_FMCFG_FMSEL20_Msk /*!< Filter mode select for filter 20 */ +#define CAN_FMCFG_FMSEL21_Pos (21U) +#define CAN_FMCFG_FMSEL21_Msk (0x1U << CAN_FMCFG_FMSEL21_Pos) /*!< 0x00200000 */ +#define CAN_FMCFG_FMSEL21 CAN_FMCFG_FMSEL21_Msk /*!< Filter mode select for filter 21 */ +#define CAN_FMCFG_FMSEL22_Pos (22U) +#define CAN_FMCFG_FMSEL22_Msk (0x1U << CAN_FMCFG_FMSEL22_Pos) /*!< 0x00400000 */ +#define CAN_FMCFG_FMSEL22 CAN_FMCFG_FMSEL22_Msk /*!< Filter mode select for filter 22 */ +#define CAN_FMCFG_FMSEL23_Pos (23U) +#define CAN_FMCFG_FMSEL23_Msk (0x1U << CAN_FMCFG_FMSEL23_Pos) /*!< 0x00800000 */ +#define CAN_FMCFG_FMSEL23 CAN_FMCFG_FMSEL23_Msk /*!< Filter mode select for filter 23 */ +#define CAN_FMCFG_FMSEL24_Pos (24U) +#define CAN_FMCFG_FMSEL24_Msk (0x1U << CAN_FMCFG_FMSEL24_Pos) /*!< 0x01000000 */ +#define CAN_FMCFG_FMSEL24 CAN_FMCFG_FMSEL24_Msk /*!< Filter mode select for filter 24 */ +#define CAN_FMCFG_FMSEL25_Pos (25U) +#define CAN_FMCFG_FMSEL25_Msk (0x1U << CAN_FMCFG_FMSEL25_Pos) /*!< 0x02000000 */ +#define CAN_FMCFG_FMSEL25 CAN_FMCFG_FMSEL25_Msk /*!< Filter mode select for filter 25 */ +#define CAN_FMCFG_FMSEL26_Pos (26U) +#define CAN_FMCFG_FMSEL26_Msk (0x1U << CAN_FMCFG_FMSEL26_Pos) /*!< 0x04000000 */ +#define CAN_FMCFG_FMSEL26 CAN_FMCFG_FMSEL26_Msk /*!< Filter mode select for filter 26 */ +#define CAN_FMCFG_FMSEL27_Pos (27U) +#define CAN_FMCFG_FMSEL27_Msk (0x1U << CAN_FMCFG_FMSEL27_Pos) /*!< 0x08000000 */ +#define CAN_FMCFG_FMSEL27 CAN_FMCFG_FMSEL27_Msk /*!< Filter mode select for filter 27 */ + +/****************** Bit definition for CAN_FBWCFG register ******************/ +#define CAN_FBWCFG_FBWSEL_Pos (0U) +#define CAN_FBWCFG_FBWSEL_Msk (0xFFFFFFFU << CAN_FBWCFG_FBWSEL_Pos) /*!< 0x0FFFFFFF */ +#define CAN_FBWCFG_FBWSEL CAN_FBWCFG_FBWSEL_Msk /*!< Filter bit width select */ +#define CAN_FBWCFG_FBWSEL0_Pos (0U) +#define CAN_FBWCFG_FBWSEL0_Msk (0x1U << CAN_FBWCFG_FBWSEL0_Pos) /*!< 0x00000001 */ +#define CAN_FBWCFG_FBWSEL0 CAN_FBWCFG_FBWSEL0_Msk /*!< Filter bit width select for filter 0 */ +#define CAN_FBWCFG_FBWSEL1_Pos (1U) +#define CAN_FBWCFG_FBWSEL1_Msk (0x1U << CAN_FBWCFG_FBWSEL1_Pos) /*!< 0x00000002 */ +#define CAN_FBWCFG_FBWSEL1 CAN_FBWCFG_FBWSEL1_Msk /*!< Filter bit width select for filter 1 */ +#define CAN_FBWCFG_FBWSEL2_Pos (2U) +#define CAN_FBWCFG_FBWSEL2_Msk (0x1U << CAN_FBWCFG_FBWSEL2_Pos) /*!< 0x00000004 */ +#define CAN_FBWCFG_FBWSEL2 CAN_FBWCFG_FBWSEL2_Msk /*!< Filter bit width select for filter 2 */ +#define CAN_FBWCFG_FBWSEL3_Pos (3U) +#define CAN_FBWCFG_FBWSEL3_Msk (0x1U << CAN_FBWCFG_FBWSEL3_Pos) /*!< 0x00000008 */ +#define CAN_FBWCFG_FBWSEL3 CAN_FBWCFG_FBWSEL3_Msk /*!< Filter bit width select for filter 3 */ +#define CAN_FBWCFG_FBWSEL4_Pos (4U) +#define CAN_FBWCFG_FBWSEL4_Msk (0x1U << CAN_FBWCFG_FBWSEL4_Pos) /*!< 0x00000010 */ +#define CAN_FBWCFG_FBWSEL4 CAN_FBWCFG_FBWSEL4_Msk /*!< Filter bit width select for filter 4 */ +#define CAN_FBWCFG_FBWSEL5_Pos (5U) +#define CAN_FBWCFG_FBWSEL5_Msk (0x1U << CAN_FBWCFG_FBWSEL5_Pos) /*!< 0x00000020 */ +#define CAN_FBWCFG_FBWSEL5 CAN_FBWCFG_FBWSEL5_Msk /*!< Filter bit width select for filter 5 */ +#define CAN_FBWCFG_FBWSEL6_Pos (6U) +#define CAN_FBWCFG_FBWSEL6_Msk (0x1U << CAN_FBWCFG_FBWSEL6_Pos) /*!< 0x00000040 */ +#define CAN_FBWCFG_FBWSEL6 CAN_FBWCFG_FBWSEL6_Msk /*!< Filter bit width select for filter 6 */ +#define CAN_FBWCFG_FBWSEL7_Pos (7U) +#define CAN_FBWCFG_FBWSEL7_Msk (0x1U << CAN_FBWCFG_FBWSEL7_Pos) /*!< 0x00000080 */ +#define CAN_FBWCFG_FBWSEL7 CAN_FBWCFG_FBWSEL7_Msk /*!< Filter bit width select for filter 7 */ +#define CAN_FBWCFG_FBWSEL8_Pos (8U) +#define CAN_FBWCFG_FBWSEL8_Msk (0x1U << CAN_FBWCFG_FBWSEL8_Pos) /*!< 0x00000100 */ +#define CAN_FBWCFG_FBWSEL8 CAN_FBWCFG_FBWSEL8_Msk /*!< Filter bit width select for filter 8 */ +#define CAN_FBWCFG_FBWSEL9_Pos (9U) +#define CAN_FBWCFG_FBWSEL9_Msk (0x1U << CAN_FBWCFG_FBWSEL9_Pos) /*!< 0x00000200 */ +#define CAN_FBWCFG_FBWSEL9 CAN_FBWCFG_FBWSEL9_Msk /*!< Filter bit width select for filter 9 */ +#define CAN_FBWCFG_FBWSEL10_Pos (10U) +#define CAN_FBWCFG_FBWSEL10_Msk (0x1U << CAN_FBWCFG_FBWSEL10_Pos) /*!< 0x00000400 */ +#define CAN_FBWCFG_FBWSEL10 CAN_FBWCFG_FBWSEL10_Msk /*!< Filter bit width select for filter 10 */ +#define CAN_FBWCFG_FBWSEL11_Pos (11U) +#define CAN_FBWCFG_FBWSEL11_Msk (0x1U << CAN_FBWCFG_FBWSEL11_Pos) /*!< 0x00000800 */ +#define CAN_FBWCFG_FBWSEL11 CAN_FBWCFG_FBWSEL11_Msk /*!< Filter bit width select for filter 11 */ +#define CAN_FBWCFG_FBWSEL12_Pos (12U) +#define CAN_FBWCFG_FBWSEL12_Msk (0x1U << CAN_FBWCFG_FBWSEL12_Pos) /*!< 0x00001000 */ +#define CAN_FBWCFG_FBWSEL12 CAN_FBWCFG_FBWSEL12_Msk /*!< Filter bit width select for filter 12 */ +#define CAN_FBWCFG_FBWSEL13_Pos (13U) +#define CAN_FBWCFG_FBWSEL13_Msk (0x1U << CAN_FBWCFG_FBWSEL13_Pos) /*!< 0x00002000 */ +#define CAN_FBWCFG_FBWSEL13 CAN_FBWCFG_FBWSEL13_Msk /*!< Filter bit width select for filter 13 */ +#define CAN_FBWCFG_FBWSEL14_Pos (14U) +#define CAN_FBWCFG_FBWSEL14_Msk (0x1U << CAN_FBWCFG_FBWSEL14_Pos) /*!< 0x00004000 */ +#define CAN_FBWCFG_FBWSEL14 CAN_FBWCFG_FBWSEL14_Msk /*!< Filter bit width select for filter 14 */ +#define CAN_FBWCFG_FBWSEL15_Pos (15U) +#define CAN_FBWCFG_FBWSEL15_Msk (0x1U << CAN_FBWCFG_FBWSEL15_Pos) /*!< 0x00008000 */ +#define CAN_FBWCFG_FBWSEL15 CAN_FBWCFG_FBWSEL15_Msk /*!< Filter bit width select for filter 15 */ +#define CAN_FBWCFG_FBWSEL16_Pos (16U) +#define CAN_FBWCFG_FBWSEL16_Msk (0x1U << CAN_FBWCFG_FBWSEL16_Pos) /*!< 0x00010000 */ +#define CAN_FBWCFG_FBWSEL16 CAN_FBWCFG_FBWSEL16_Msk /*!< Filter bit width select for filter 16 */ +#define CAN_FBWCFG_FBWSEL17_Pos (17U) +#define CAN_FBWCFG_FBWSEL17_Msk (0x1U << CAN_FBWCFG_FBWSEL17_Pos) /*!< 0x00020000 */ +#define CAN_FBWCFG_FBWSEL17 CAN_FBWCFG_FBWSEL17_Msk /*!< Filter bit width select for filter 17 */ +#define CAN_FBWCFG_FBWSEL18_Pos (18U) +#define CAN_FBWCFG_FBWSEL18_Msk (0x1U << CAN_FBWCFG_FBWSEL18_Pos) /*!< 0x00040000 */ +#define CAN_FBWCFG_FBWSEL18 CAN_FBWCFG_FBWSEL18_Msk /*!< Filter bit width select for filter 18 */ +#define CAN_FBWCFG_FBWSEL19_Pos (19U) +#define CAN_FBWCFG_FBWSEL19_Msk (0x1U << CAN_FBWCFG_FBWSEL19_Pos) /*!< 0x00080000 */ +#define CAN_FBWCFG_FBWSEL19 CAN_FBWCFG_FBWSEL19_Msk /*!< Filter bit width select for filter 19 */ +#define CAN_FBWCFG_FBWSEL20_Pos (20U) +#define CAN_FBWCFG_FBWSEL20_Msk (0x1U << CAN_FBWCFG_FBWSEL20_Pos) /*!< 0x00100000 */ +#define CAN_FBWCFG_FBWSEL20 CAN_FBWCFG_FBWSEL20_Msk /*!< Filter bit width select for filter 20 */ +#define CAN_FBWCFG_FBWSEL21_Pos (21U) +#define CAN_FBWCFG_FBWSEL21_Msk (0x1U << CAN_FBWCFG_FBWSEL21_Pos) /*!< 0x00200000 */ +#define CAN_FBWCFG_FBWSEL21 CAN_FBWCFG_FBWSEL21_Msk /*!< Filter bit width select for filter 21 */ +#define CAN_FBWCFG_FBWSEL22_Pos (22U) +#define CAN_FBWCFG_FBWSEL22_Msk (0x1U << CAN_FBWCFG_FBWSEL22_Pos) /*!< 0x00400000 */ +#define CAN_FBWCFG_FBWSEL22 CAN_FBWCFG_FBWSEL22_Msk /*!< Filter bit width select for filter 22 */ +#define CAN_FBWCFG_FBWSEL23_Pos (23U) +#define CAN_FBWCFG_FBWSEL23_Msk (0x1U << CAN_FBWCFG_FBWSEL23_Pos) /*!< 0x00800000 */ +#define CAN_FBWCFG_FBWSEL23 CAN_FBWCFG_FBWSEL23_Msk /*!< Filter bit width select for filter 23 */ +#define CAN_FBWCFG_FBWSEL24_Pos (24U) +#define CAN_FBWCFG_FBWSEL24_Msk (0x1U << CAN_FBWCFG_FBWSEL24_Pos) /*!< 0x01000000 */ +#define CAN_FBWCFG_FBWSEL24 CAN_FBWCFG_FBWSEL24_Msk /*!< Filter bit width select for filter 24 */ +#define CAN_FBWCFG_FBWSEL25_Pos (25U) +#define CAN_FBWCFG_FBWSEL25_Msk (0x1U << CAN_FBWCFG_FBWSEL25_Pos) /*!< 0x02000000 */ +#define CAN_FBWCFG_FBWSEL25 CAN_FBWCFG_FBWSEL25_Msk /*!< Filter bit width select for filter 25 */ +#define CAN_FBWCFG_FBWSEL26_Pos (26U) +#define CAN_FBWCFG_FBWSEL26_Msk (0x1U << CAN_FBWCFG_FBWSEL26_Pos) /*!< 0x04000000 */ +#define CAN_FBWCFG_FBWSEL26 CAN_FBWCFG_FBWSEL26_Msk /*!< Filter bit width select for filter 26 */ +#define CAN_FBWCFG_FBWSEL27_Pos (27U) +#define CAN_FBWCFG_FBWSEL27_Msk (0x1U << CAN_FBWCFG_FBWSEL27_Pos) /*!< 0x08000000 */ +#define CAN_FBWCFG_FBWSEL27 CAN_FBWCFG_FBWSEL27_Msk /*!< Filter bit width select for filter 27 */ + +/******************* Bit definition for CAN_FRF register ********************/ +#define CAN_FRF_FRFSEL_Pos (0U) +#define CAN_FRF_FRFSEL_Msk (0xFFFFFFFU << CAN_FRF_FRFSEL_Pos) /*!< 0x0FFFFFFF */ +#define CAN_FRF_FRFSEL CAN_FRF_FRFSEL_Msk /*!< Filter relation FIFO select */ +#define CAN_FRF_FRFSEL0_Pos (0U) +#define CAN_FRF_FRFSEL0_Msk (0x1U << CAN_FRF_FRFSEL0_Pos) /*!< 0x00000001 */ +#define CAN_FRF_FRFSEL0 CAN_FRF_FRFSEL0_Msk /*!< Filter relation FIFO select for filter 0 */ +#define CAN_FRF_FRFSEL1_Pos (1U) +#define CAN_FRF_FRFSEL1_Msk (0x1U << CAN_FRF_FRFSEL1_Pos) /*!< 0x00000002 */ +#define CAN_FRF_FRFSEL1 CAN_FRF_FRFSEL1_Msk /*!< Filter relation FIFO select for filter 1 */ +#define CAN_FRF_FRFSEL2_Pos (2U) +#define CAN_FRF_FRFSEL2_Msk (0x1U << CAN_FRF_FRFSEL2_Pos) /*!< 0x00000004 */ +#define CAN_FRF_FRFSEL2 CAN_FRF_FRFSEL2_Msk /*!< Filter relation FIFO select for filter 2 */ +#define CAN_FRF_FRFSEL3_Pos (3U) +#define CAN_FRF_FRFSEL3_Msk (0x1U << CAN_FRF_FRFSEL3_Pos) /*!< 0x00000008 */ +#define CAN_FRF_FRFSEL3 CAN_FRF_FRFSEL3_Msk /*!< Filter relation FIFO select for filter 3 */ +#define CAN_FRF_FRFSEL4_Pos (4U) +#define CAN_FRF_FRFSEL4_Msk (0x1U << CAN_FRF_FRFSEL4_Pos) /*!< 0x00000010 */ +#define CAN_FRF_FRFSEL4 CAN_FRF_FRFSEL4_Msk /*!< Filter relation FIFO select for filter 4 */ +#define CAN_FRF_FRFSEL5_Pos (5U) +#define CAN_FRF_FRFSEL5_Msk (0x1U << CAN_FRF_FRFSEL5_Pos) /*!< 0x00000020 */ +#define CAN_FRF_FRFSEL5 CAN_FRF_FRFSEL5_Msk /*!< Filter relation FIFO select for filter 5 */ +#define CAN_FRF_FRFSEL6_Pos (6U) +#define CAN_FRF_FRFSEL6_Msk (0x1U << CAN_FRF_FRFSEL6_Pos) /*!< 0x00000040 */ +#define CAN_FRF_FRFSEL6 CAN_FRF_FRFSEL6_Msk /*!< Filter relation FIFO select for filter 6 */ +#define CAN_FRF_FRFSEL7_Pos (7U) +#define CAN_FRF_FRFSEL7_Msk (0x1U << CAN_FRF_FRFSEL7_Pos) /*!< 0x00000080 */ +#define CAN_FRF_FRFSEL7 CAN_FRF_FRFSEL7_Msk /*!< Filter relation FIFO select for filter 7 */ +#define CAN_FRF_FRFSEL8_Pos (8U) +#define CAN_FRF_FRFSEL8_Msk (0x1U << CAN_FRF_FRFSEL8_Pos) /*!< 0x00000100 */ +#define CAN_FRF_FRFSEL8 CAN_FRF_FRFSEL8_Msk /*!< Filter relation FIFO select for filter 8 */ +#define CAN_FRF_FRFSEL9_Pos (9U) +#define CAN_FRF_FRFSEL9_Msk (0x1U << CAN_FRF_FRFSEL9_Pos) /*!< 0x00000200 */ +#define CAN_FRF_FRFSEL9 CAN_FRF_FRFSEL9_Msk /*!< Filter relation FIFO select for filter 9 */ +#define CAN_FRF_FRFSEL10_Pos (10U) +#define CAN_FRF_FRFSEL10_Msk (0x1U << CAN_FRF_FRFSEL10_Pos) /*!< 0x00000400 */ +#define CAN_FRF_FRFSEL10 CAN_FRF_FRFSEL10_Msk /*!< Filter relation FIFO select for filter 10 */ +#define CAN_FRF_FRFSEL11_Pos (11U) +#define CAN_FRF_FRFSEL11_Msk (0x1U << CAN_FRF_FRFSEL11_Pos) /*!< 0x00000800 */ +#define CAN_FRF_FRFSEL11 CAN_FRF_FRFSEL11_Msk /*!< Filter relation FIFO select for filter 11 */ +#define CAN_FRF_FRFSEL12_Pos (12U) +#define CAN_FRF_FRFSEL12_Msk (0x1U << CAN_FRF_FRFSEL12_Pos) /*!< 0x00001000 */ +#define CAN_FRF_FRFSEL12 CAN_FRF_FRFSEL12_Msk /*!< Filter relation FIFO select for filter 12 */ +#define CAN_FRF_FRFSEL13_Pos (13U) +#define CAN_FRF_FRFSEL13_Msk (0x1U << CAN_FRF_FRFSEL13_Pos) /*!< 0x00002000 */ +#define CAN_FRF_FRFSEL13 CAN_FRF_FRFSEL13_Msk /*!< Filter relation FIFO select for filter 13 */ +#define CAN_FRF_FRFSEL14_Pos (14U) +#define CAN_FRF_FRFSEL14_Msk (0x1U << CAN_FRF_FRFSEL14_Pos) /*!< 0x00004000 */ +#define CAN_FRF_FRFSEL14 CAN_FRF_FRFSEL14_Msk /*!< Filter relation FIFO select for filter 14 */ +#define CAN_FRF_FRFSEL15_Pos (15U) +#define CAN_FRF_FRFSEL15_Msk (0x1U << CAN_FRF_FRFSEL15_Pos) /*!< 0x00008000 */ +#define CAN_FRF_FRFSEL15 CAN_FRF_FRFSEL15_Msk /*!< Filter relation FIFO select for filter 15 */ +#define CAN_FRF_FRFSEL16_Pos (16U) +#define CAN_FRF_FRFSEL16_Msk (0x1U << CAN_FRF_FRFSEL16_Pos) /*!< 0x00010000 */ +#define CAN_FRF_FRFSEL16 CAN_FRF_FRFSEL16_Msk /*!< Filter relation FIFO select for filter 16 */ +#define CAN_FRF_FRFSEL17_Pos (17U) +#define CAN_FRF_FRFSEL17_Msk (0x1U << CAN_FRF_FRFSEL17_Pos) /*!< 0x00020000 */ +#define CAN_FRF_FRFSEL17 CAN_FRF_FRFSEL17_Msk /*!< Filter relation FIFO select for filter 17 */ +#define CAN_FRF_FRFSEL18_Pos (18U) +#define CAN_FRF_FRFSEL18_Msk (0x1U << CAN_FRF_FRFSEL18_Pos) /*!< 0x00040000 */ +#define CAN_FRF_FRFSEL18 CAN_FRF_FRFSEL18_Msk /*!< Filter relation FIFO select for filter 18 */ +#define CAN_FRF_FRFSEL19_Pos (19U) +#define CAN_FRF_FRFSEL19_Msk (0x1U << CAN_FRF_FRFSEL19_Pos) /*!< 0x00080000 */ +#define CAN_FRF_FRFSEL19 CAN_FRF_FRFSEL19_Msk /*!< Filter relation FIFO select for filter 19 */ +#define CAN_FRF_FRFSEL20_Pos (20U) +#define CAN_FRF_FRFSEL20_Msk (0x1U << CAN_FRF_FRFSEL20_Pos) /*!< 0x00100000 */ +#define CAN_FRF_FRFSEL20 CAN_FRF_FRFSEL20_Msk /*!< Filter relation FIFO select for filter 20 */ +#define CAN_FRF_FRFSEL21_Pos (21U) +#define CAN_FRF_FRFSEL21_Msk (0x1U << CAN_FRF_FRFSEL21_Pos) /*!< 0x00200000 */ +#define CAN_FRF_FRFSEL21 CAN_FRF_FRFSEL21_Msk /*!< Filter relation FIFO select for filter 21 */ +#define CAN_FRF_FRFSEL22_Pos (22U) +#define CAN_FRF_FRFSEL22_Msk (0x1U << CAN_FRF_FRFSEL22_Pos) /*!< 0x00400000 */ +#define CAN_FRF_FRFSEL22 CAN_FRF_FRFSEL22_Msk /*!< Filter relation FIFO select for filter 22 */ +#define CAN_FRF_FRFSEL23_Pos (23U) +#define CAN_FRF_FRFSEL23_Msk (0x1U << CAN_FRF_FRFSEL23_Pos) /*!< 0x00800000 */ +#define CAN_FRF_FRFSEL23 CAN_FRF_FRFSEL23_Msk /*!< Filter relation FIFO select for filter 23 */ +#define CAN_FRF_FRFSEL24_Pos (24U) +#define CAN_FRF_FRFSEL24_Msk (0x1U << CAN_FRF_FRFSEL24_Pos) /*!< 0x01000000 */ +#define CAN_FRF_FRFSEL24 CAN_FRF_FRFSEL24_Msk /*!< Filter relation FIFO select for filter 24 */ +#define CAN_FRF_FRFSEL25_Pos (25U) +#define CAN_FRF_FRFSEL25_Msk (0x1U << CAN_FRF_FRFSEL25_Pos) /*!< 0x02000000 */ +#define CAN_FRF_FRFSEL25 CAN_FRF_FRFSEL25_Msk /*!< Filter relation FIFO select for filter 25 */ +#define CAN_FRF_FRFSEL26_Pos (26U) +#define CAN_FRF_FRFSEL26_Msk (0x1U << CAN_FRF_FRFSEL26_Pos) /*!< 0x04000000 */ +#define CAN_FRF_FRFSEL26 CAN_FRF_FRFSEL26_Msk /*!< Filter relation FIFO select for filter 26 */ +#define CAN_FRF_FRFSEL27_Pos (27U) +#define CAN_FRF_FRFSEL27_Msk (0x1U << CAN_FRF_FRFSEL27_Pos) /*!< 0x08000000 */ +#define CAN_FRF_FRFSEL27 CAN_FRF_FRFSEL27_Msk /*!< Filter relation FIFO select for filter 27 */ + +/****************** Bit definition for CAN_FACFG register *******************/ +#define CAN_FACFG_FAEN_Pos (0U) +#define CAN_FACFG_FAEN_Msk (0xFFFFFFFU << CAN_FACFG_FAEN_Pos) /*!< 0x0FFFFFFF */ +#define CAN_FACFG_FAEN CAN_FACFG_FAEN_Msk /*!< Filter active enable */ +#define CAN_FACFG_FAEN0_Pos (0U) +#define CAN_FACFG_FAEN0_Msk (0x1U << CAN_FACFG_FAEN0_Pos) /*!< 0x00000001 */ +#define CAN_FACFG_FAEN0 CAN_FACFG_FAEN0_Msk /*!< Filter 0 active enable */ +#define CAN_FACFG_FAEN1_Pos (1U) +#define CAN_FACFG_FAEN1_Msk (0x1U << CAN_FACFG_FAEN1_Pos) /*!< 0x00000002 */ +#define CAN_FACFG_FAEN1 CAN_FACFG_FAEN1_Msk /*!< Filter 1 active enable */ +#define CAN_FACFG_FAEN2_Pos (2U) +#define CAN_FACFG_FAEN2_Msk (0x1U << CAN_FACFG_FAEN2_Pos) /*!< 0x00000004 */ +#define CAN_FACFG_FAEN2 CAN_FACFG_FAEN2_Msk /*!< Filter 2 active enable */ +#define CAN_FACFG_FAEN3_Pos (3U) +#define CAN_FACFG_FAEN3_Msk (0x1U << CAN_FACFG_FAEN3_Pos) /*!< 0x00000008 */ +#define CAN_FACFG_FAEN3 CAN_FACFG_FAEN3_Msk /*!< Filter 3 active enable */ +#define CAN_FACFG_FAEN4_Pos (4U) +#define CAN_FACFG_FAEN4_Msk (0x1U << CAN_FACFG_FAEN4_Pos) /*!< 0x00000010 */ +#define CAN_FACFG_FAEN4 CAN_FACFG_FAEN4_Msk /*!< Filter 4 active enable */ +#define CAN_FACFG_FAEN5_Pos (5U) +#define CAN_FACFG_FAEN5_Msk (0x1U << CAN_FACFG_FAEN5_Pos) /*!< 0x00000020 */ +#define CAN_FACFG_FAEN5 CAN_FACFG_FAEN5_Msk /*!< Filter 5 active enable */ +#define CAN_FACFG_FAEN6_Pos (6U) +#define CAN_FACFG_FAEN6_Msk (0x1U << CAN_FACFG_FAEN6_Pos) /*!< 0x00000040 */ +#define CAN_FACFG_FAEN6 CAN_FACFG_FAEN6_Msk /*!< Filter 6 active enable */ +#define CAN_FACFG_FAEN7_Pos (7U) +#define CAN_FACFG_FAEN7_Msk (0x1U << CAN_FACFG_FAEN7_Pos) /*!< 0x00000080 */ +#define CAN_FACFG_FAEN7 CAN_FACFG_FAEN7_Msk /*!< Filter 7 active enable */ +#define CAN_FACFG_FAEN8_Pos (8U) +#define CAN_FACFG_FAEN8_Msk (0x1U << CAN_FACFG_FAEN8_Pos) /*!< 0x00000100 */ +#define CAN_FACFG_FAEN8 CAN_FACFG_FAEN8_Msk /*!< Filter 8 active enable */ +#define CAN_FACFG_FAEN9_Pos (9U) +#define CAN_FACFG_FAEN9_Msk (0x1U << CAN_FACFG_FAEN9_Pos) /*!< 0x00000200 */ +#define CAN_FACFG_FAEN9 CAN_FACFG_FAEN9_Msk /*!< Filter 9 active enable */ +#define CAN_FACFG_FAEN10_Pos (10U) +#define CAN_FACFG_FAEN10_Msk (0x1U << CAN_FACFG_FAEN10_Pos) /*!< 0x00000400 */ +#define CAN_FACFG_FAEN10 CAN_FACFG_FAEN10_Msk /*!< Filter 10 active enable */ +#define CAN_FACFG_FAEN11_Pos (11U) +#define CAN_FACFG_FAEN11_Msk (0x1U << CAN_FACFG_FAEN11_Pos) /*!< 0x00000800 */ +#define CAN_FACFG_FAEN11 CAN_FACFG_FAEN11_Msk /*!< Filter 11 active enable */ +#define CAN_FACFG_FAEN12_Pos (12U) +#define CAN_FACFG_FAEN12_Msk (0x1U << CAN_FACFG_FAEN12_Pos) /*!< 0x00001000 */ +#define CAN_FACFG_FAEN12 CAN_FACFG_FAEN12_Msk /*!< Filter 12 active enable */ +#define CAN_FACFG_FAEN13_Pos (13U) +#define CAN_FACFG_FAEN13_Msk (0x1U << CAN_FACFG_FAEN13_Pos) /*!< 0x00002000 */ +#define CAN_FACFG_FAEN13 CAN_FACFG_FAEN13_Msk /*!< Filter 13 active enable */ +#define CAN_FACFG_FAEN14_Pos (14U) +#define CAN_FACFG_FAEN14_Msk (0x1U << CAN_FACFG_FAEN14_Pos) /*!< 0x00004000 */ +#define CAN_FACFG_FAEN14 CAN_FACFG_FAEN14_Msk /*!< Filter 14 active enable */ +#define CAN_FACFG_FAEN15_Pos (15U) +#define CAN_FACFG_FAEN15_Msk (0x1U << CAN_FACFG_FAEN15_Pos) /*!< 0x00008000 */ +#define CAN_FACFG_FAEN15 CAN_FACFG_FAEN15_Msk /*!< Filter 15 active enable */ +#define CAN_FACFG_FAEN16_Pos (16U) +#define CAN_FACFG_FAEN16_Msk (0x1U << CAN_FACFG_FAEN16_Pos) /*!< 0x00010000 */ +#define CAN_FACFG_FAEN16 CAN_FACFG_FAEN16_Msk /*!< Filter 16 active enable */ +#define CAN_FACFG_FAEN17_Pos (17U) +#define CAN_FACFG_FAEN17_Msk (0x1U << CAN_FACFG_FAEN17_Pos) /*!< 0x00020000 */ +#define CAN_FACFG_FAEN17 CAN_FACFG_FAEN17_Msk /*!< Filter 17 active enable */ +#define CAN_FACFG_FAEN18_Pos (18U) +#define CAN_FACFG_FAEN18_Msk (0x1U << CAN_FACFG_FAEN18_Pos) /*!< 0x00040000 */ +#define CAN_FACFG_FAEN18 CAN_FACFG_FAEN18_Msk /*!< Filter 18 active enable */ +#define CAN_FACFG_FAEN19_Pos (19U) +#define CAN_FACFG_FAEN19_Msk (0x1U << CAN_FACFG_FAEN19_Pos) /*!< 0x00080000 */ +#define CAN_FACFG_FAEN19 CAN_FACFG_FAEN19_Msk /*!< Filter 19 active enable */ +#define CAN_FACFG_FAEN20_Pos (20U) +#define CAN_FACFG_FAEN20_Msk (0x1U << CAN_FACFG_FAEN20_Pos) /*!< 0x00100000 */ +#define CAN_FACFG_FAEN20 CAN_FACFG_FAEN20_Msk /*!< Filter 20 active enable */ +#define CAN_FACFG_FAEN21_Pos (21U) +#define CAN_FACFG_FAEN21_Msk (0x1U << CAN_FACFG_FAEN21_Pos) /*!< 0x00200000 */ +#define CAN_FACFG_FAEN21 CAN_FACFG_FAEN21_Msk /*!< Filter 21 active enable */ +#define CAN_FACFG_FAEN22_Pos (22U) +#define CAN_FACFG_FAEN22_Msk (0x1U << CAN_FACFG_FAEN22_Pos) /*!< 0x00400000 */ +#define CAN_FACFG_FAEN22 CAN_FACFG_FAEN22_Msk /*!< Filter 22 active enable */ +#define CAN_FACFG_FAEN23_Pos (23U) +#define CAN_FACFG_FAEN23_Msk (0x1U << CAN_FACFG_FAEN23_Pos) /*!< 0x00800000 */ +#define CAN_FACFG_FAEN23 CAN_FACFG_FAEN23_Msk /*!< Filter 23 active enable */ +#define CAN_FACFG_FAEN24_Pos (24U) +#define CAN_FACFG_FAEN24_Msk (0x1U << CAN_FACFG_FAEN24_Pos) /*!< 0x01000000 */ +#define CAN_FACFG_FAEN24 CAN_FACFG_FAEN24_Msk /*!< Filter 24 active enable */ +#define CAN_FACFG_FAEN25_Pos (25U) +#define CAN_FACFG_FAEN25_Msk (0x1U << CAN_FACFG_FAEN25_Pos) /*!< 0x02000000 */ +#define CAN_FACFG_FAEN25 CAN_FACFG_FAEN25_Msk /*!< Filter 25 active enable */ +#define CAN_FACFG_FAEN26_Pos (26U) +#define CAN_FACFG_FAEN26_Msk (0x1U << CAN_FACFG_FAEN26_Pos) /*!< 0x04000000 */ +#define CAN_FACFG_FAEN26 CAN_FACFG_FAEN26_Msk /*!< Filter 26 active enable */ +#define CAN_FACFG_FAEN27_Pos (27U) +#define CAN_FACFG_FAEN27_Msk (0x1U << CAN_FACFG_FAEN27_Pos) /*!< 0x08000000 */ +#define CAN_FACFG_FAEN27 CAN_FACFG_FAEN27_Msk /*!< Filter 27 active enable */ + +/****************** Bit definition for CAN_F0FB1 register *******************/ +#define CAN_F0FB1_FFDB0_Pos (0U) +#define CAN_F0FB1_FFDB0_Msk (0x1U << CAN_F0FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F0FB1_FFDB0 CAN_F0FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F0FB1_FFDB1_Pos (1U) +#define CAN_F0FB1_FFDB1_Msk (0x1U << CAN_F0FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F0FB1_FFDB1 CAN_F0FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F0FB1_FFDB2_Pos (2U) +#define CAN_F0FB1_FFDB2_Msk (0x1U << CAN_F0FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F0FB1_FFDB2 CAN_F0FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F0FB1_FFDB3_Pos (3U) +#define CAN_F0FB1_FFDB3_Msk (0x1U << CAN_F0FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F0FB1_FFDB3 CAN_F0FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F0FB1_FFDB4_Pos (4U) +#define CAN_F0FB1_FFDB4_Msk (0x1U << CAN_F0FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F0FB1_FFDB4 CAN_F0FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F0FB1_FFDB5_Pos (5U) +#define CAN_F0FB1_FFDB5_Msk (0x1U << CAN_F0FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F0FB1_FFDB5 CAN_F0FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F0FB1_FFDB6_Pos (6U) +#define CAN_F0FB1_FFDB6_Msk (0x1U << CAN_F0FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F0FB1_FFDB6 CAN_F0FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F0FB1_FFDB7_Pos (7U) +#define CAN_F0FB1_FFDB7_Msk (0x1U << CAN_F0FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F0FB1_FFDB7 CAN_F0FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F0FB1_FFDB8_Pos (8U) +#define CAN_F0FB1_FFDB8_Msk (0x1U << CAN_F0FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F0FB1_FFDB8 CAN_F0FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F0FB1_FFDB9_Pos (9U) +#define CAN_F0FB1_FFDB9_Msk (0x1U << CAN_F0FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F0FB1_FFDB9 CAN_F0FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F0FB1_FFDB10_Pos (10U) +#define CAN_F0FB1_FFDB10_Msk (0x1U << CAN_F0FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F0FB1_FFDB10 CAN_F0FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F0FB1_FFDB11_Pos (11U) +#define CAN_F0FB1_FFDB11_Msk (0x1U << CAN_F0FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F0FB1_FFDB11 CAN_F0FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F0FB1_FFDB12_Pos (12U) +#define CAN_F0FB1_FFDB12_Msk (0x1U << CAN_F0FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F0FB1_FFDB12 CAN_F0FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F0FB1_FFDB13_Pos (13U) +#define CAN_F0FB1_FFDB13_Msk (0x1U << CAN_F0FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F0FB1_FFDB13 CAN_F0FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F0FB1_FFDB14_Pos (14U) +#define CAN_F0FB1_FFDB14_Msk (0x1U << CAN_F0FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F0FB1_FFDB14 CAN_F0FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F0FB1_FFDB15_Pos (15U) +#define CAN_F0FB1_FFDB15_Msk (0x1U << CAN_F0FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F0FB1_FFDB15 CAN_F0FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F0FB1_FFDB16_Pos (16U) +#define CAN_F0FB1_FFDB16_Msk (0x1U << CAN_F0FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F0FB1_FFDB16 CAN_F0FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F0FB1_FFDB17_Pos (17U) +#define CAN_F0FB1_FFDB17_Msk (0x1U << CAN_F0FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F0FB1_FFDB17 CAN_F0FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F0FB1_FFDB18_Pos (18U) +#define CAN_F0FB1_FFDB18_Msk (0x1U << CAN_F0FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F0FB1_FFDB18 CAN_F0FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F0FB1_FFDB19_Pos (19U) +#define CAN_F0FB1_FFDB19_Msk (0x1U << CAN_F0FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F0FB1_FFDB19 CAN_F0FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F0FB1_FFDB20_Pos (20U) +#define CAN_F0FB1_FFDB20_Msk (0x1U << CAN_F0FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F0FB1_FFDB20 CAN_F0FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F0FB1_FFDB21_Pos (21U) +#define CAN_F0FB1_FFDB21_Msk (0x1U << CAN_F0FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F0FB1_FFDB21 CAN_F0FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F0FB1_FFDB22_Pos (22U) +#define CAN_F0FB1_FFDB22_Msk (0x1U << CAN_F0FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F0FB1_FFDB22 CAN_F0FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F0FB1_FFDB23_Pos (23U) +#define CAN_F0FB1_FFDB23_Msk (0x1U << CAN_F0FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F0FB1_FFDB23 CAN_F0FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F0FB1_FFDB24_Pos (24U) +#define CAN_F0FB1_FFDB24_Msk (0x1U << CAN_F0FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F0FB1_FFDB24 CAN_F0FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F0FB1_FFDB25_Pos (25U) +#define CAN_F0FB1_FFDB25_Msk (0x1U << CAN_F0FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F0FB1_FFDB25 CAN_F0FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F0FB1_FFDB26_Pos (26U) +#define CAN_F0FB1_FFDB26_Msk (0x1U << CAN_F0FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F0FB1_FFDB26 CAN_F0FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F0FB1_FFDB27_Pos (27U) +#define CAN_F0FB1_FFDB27_Msk (0x1U << CAN_F0FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F0FB1_FFDB27 CAN_F0FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F0FB1_FFDB28_Pos (28U) +#define CAN_F0FB1_FFDB28_Msk (0x1U << CAN_F0FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F0FB1_FFDB28 CAN_F0FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F0FB1_FFDB29_Pos (29U) +#define CAN_F0FB1_FFDB29_Msk (0x1U << CAN_F0FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F0FB1_FFDB29 CAN_F0FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F0FB1_FFDB30_Pos (30U) +#define CAN_F0FB1_FFDB30_Msk (0x1U << CAN_F0FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F0FB1_FFDB30 CAN_F0FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F0FB1_FFDB31_Pos (31U) +#define CAN_F0FB1_FFDB31_Msk (0x1U << CAN_F0FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F0FB1_FFDB31 CAN_F0FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F1FB1 register *******************/ +#define CAN_F1FB1_FFDB0_Pos (0U) +#define CAN_F1FB1_FFDB0_Msk (0x1U << CAN_F1FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F1FB1_FFDB0 CAN_F1FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F1FB1_FFDB1_Pos (1U) +#define CAN_F1FB1_FFDB1_Msk (0x1U << CAN_F1FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F1FB1_FFDB1 CAN_F1FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F1FB1_FFDB2_Pos (2U) +#define CAN_F1FB1_FFDB2_Msk (0x1U << CAN_F1FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F1FB1_FFDB2 CAN_F1FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F1FB1_FFDB3_Pos (3U) +#define CAN_F1FB1_FFDB3_Msk (0x1U << CAN_F1FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F1FB1_FFDB3 CAN_F1FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F1FB1_FFDB4_Pos (4U) +#define CAN_F1FB1_FFDB4_Msk (0x1U << CAN_F1FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F1FB1_FFDB4 CAN_F1FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F1FB1_FFDB5_Pos (5U) +#define CAN_F1FB1_FFDB5_Msk (0x1U << CAN_F1FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F1FB1_FFDB5 CAN_F1FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F1FB1_FFDB6_Pos (6U) +#define CAN_F1FB1_FFDB6_Msk (0x1U << CAN_F1FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F1FB1_FFDB6 CAN_F1FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F1FB1_FFDB7_Pos (7U) +#define CAN_F1FB1_FFDB7_Msk (0x1U << CAN_F1FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F1FB1_FFDB7 CAN_F1FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F1FB1_FFDB8_Pos (8U) +#define CAN_F1FB1_FFDB8_Msk (0x1U << CAN_F1FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F1FB1_FFDB8 CAN_F1FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F1FB1_FFDB9_Pos (9U) +#define CAN_F1FB1_FFDB9_Msk (0x1U << CAN_F1FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F1FB1_FFDB9 CAN_F1FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F1FB1_FFDB10_Pos (10U) +#define CAN_F1FB1_FFDB10_Msk (0x1U << CAN_F1FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F1FB1_FFDB10 CAN_F1FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F1FB1_FFDB11_Pos (11U) +#define CAN_F1FB1_FFDB11_Msk (0x1U << CAN_F1FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F1FB1_FFDB11 CAN_F1FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F1FB1_FFDB12_Pos (12U) +#define CAN_F1FB1_FFDB12_Msk (0x1U << CAN_F1FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F1FB1_FFDB12 CAN_F1FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F1FB1_FFDB13_Pos (13U) +#define CAN_F1FB1_FFDB13_Msk (0x1U << CAN_F1FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F1FB1_FFDB13 CAN_F1FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F1FB1_FFDB14_Pos (14U) +#define CAN_F1FB1_FFDB14_Msk (0x1U << CAN_F1FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F1FB1_FFDB14 CAN_F1FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F1FB1_FFDB15_Pos (15U) +#define CAN_F1FB1_FFDB15_Msk (0x1U << CAN_F1FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F1FB1_FFDB15 CAN_F1FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F1FB1_FFDB16_Pos (16U) +#define CAN_F1FB1_FFDB16_Msk (0x1U << CAN_F1FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F1FB1_FFDB16 CAN_F1FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F1FB1_FFDB17_Pos (17U) +#define CAN_F1FB1_FFDB17_Msk (0x1U << CAN_F1FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F1FB1_FFDB17 CAN_F1FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F1FB1_FFDB18_Pos (18U) +#define CAN_F1FB1_FFDB18_Msk (0x1U << CAN_F1FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F1FB1_FFDB18 CAN_F1FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F1FB1_FFDB19_Pos (19U) +#define CAN_F1FB1_FFDB19_Msk (0x1U << CAN_F1FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F1FB1_FFDB19 CAN_F1FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F1FB1_FFDB20_Pos (20U) +#define CAN_F1FB1_FFDB20_Msk (0x1U << CAN_F1FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F1FB1_FFDB20 CAN_F1FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F1FB1_FFDB21_Pos (21U) +#define CAN_F1FB1_FFDB21_Msk (0x1U << CAN_F1FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F1FB1_FFDB21 CAN_F1FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F1FB1_FFDB22_Pos (22U) +#define CAN_F1FB1_FFDB22_Msk (0x1U << CAN_F1FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F1FB1_FFDB22 CAN_F1FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F1FB1_FFDB23_Pos (23U) +#define CAN_F1FB1_FFDB23_Msk (0x1U << CAN_F1FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F1FB1_FFDB23 CAN_F1FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F1FB1_FFDB24_Pos (24U) +#define CAN_F1FB1_FFDB24_Msk (0x1U << CAN_F1FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F1FB1_FFDB24 CAN_F1FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F1FB1_FFDB25_Pos (25U) +#define CAN_F1FB1_FFDB25_Msk (0x1U << CAN_F1FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F1FB1_FFDB25 CAN_F1FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F1FB1_FFDB26_Pos (26U) +#define CAN_F1FB1_FFDB26_Msk (0x1U << CAN_F1FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F1FB1_FFDB26 CAN_F1FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F1FB1_FFDB27_Pos (27U) +#define CAN_F1FB1_FFDB27_Msk (0x1U << CAN_F1FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F1FB1_FFDB27 CAN_F1FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F1FB1_FFDB28_Pos (28U) +#define CAN_F1FB1_FFDB28_Msk (0x1U << CAN_F1FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F1FB1_FFDB28 CAN_F1FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F1FB1_FFDB29_Pos (29U) +#define CAN_F1FB1_FFDB29_Msk (0x1U << CAN_F1FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F1FB1_FFDB29 CAN_F1FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F1FB1_FFDB30_Pos (30U) +#define CAN_F1FB1_FFDB30_Msk (0x1U << CAN_F1FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F1FB1_FFDB30 CAN_F1FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F1FB1_FFDB31_Pos (31U) +#define CAN_F1FB1_FFDB31_Msk (0x1U << CAN_F1FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F1FB1_FFDB31 CAN_F1FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F2FB1 register *******************/ +#define CAN_F2FB1_FFDB0_Pos (0U) +#define CAN_F2FB1_FFDB0_Msk (0x1U << CAN_F2FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F2FB1_FFDB0 CAN_F2FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F2FB1_FFDB1_Pos (1U) +#define CAN_F2FB1_FFDB1_Msk (0x1U << CAN_F2FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F2FB1_FFDB1 CAN_F2FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F2FB1_FFDB2_Pos (2U) +#define CAN_F2FB1_FFDB2_Msk (0x1U << CAN_F2FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F2FB1_FFDB2 CAN_F2FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F2FB1_FFDB3_Pos (3U) +#define CAN_F2FB1_FFDB3_Msk (0x1U << CAN_F2FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F2FB1_FFDB3 CAN_F2FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F2FB1_FFDB4_Pos (4U) +#define CAN_F2FB1_FFDB4_Msk (0x1U << CAN_F2FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F2FB1_FFDB4 CAN_F2FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F2FB1_FFDB5_Pos (5U) +#define CAN_F2FB1_FFDB5_Msk (0x1U << CAN_F2FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F2FB1_FFDB5 CAN_F2FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F2FB1_FFDB6_Pos (6U) +#define CAN_F2FB1_FFDB6_Msk (0x1U << CAN_F2FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F2FB1_FFDB6 CAN_F2FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F2FB1_FFDB7_Pos (7U) +#define CAN_F2FB1_FFDB7_Msk (0x1U << CAN_F2FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F2FB1_FFDB7 CAN_F2FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F2FB1_FFDB8_Pos (8U) +#define CAN_F2FB1_FFDB8_Msk (0x1U << CAN_F2FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F2FB1_FFDB8 CAN_F2FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F2FB1_FFDB9_Pos (9U) +#define CAN_F2FB1_FFDB9_Msk (0x1U << CAN_F2FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F2FB1_FFDB9 CAN_F2FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F2FB1_FFDB10_Pos (10U) +#define CAN_F2FB1_FFDB10_Msk (0x1U << CAN_F2FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F2FB1_FFDB10 CAN_F2FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F2FB1_FFDB11_Pos (11U) +#define CAN_F2FB1_FFDB11_Msk (0x1U << CAN_F2FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F2FB1_FFDB11 CAN_F2FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F2FB1_FFDB12_Pos (12U) +#define CAN_F2FB1_FFDB12_Msk (0x1U << CAN_F2FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F2FB1_FFDB12 CAN_F2FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F2FB1_FFDB13_Pos (13U) +#define CAN_F2FB1_FFDB13_Msk (0x1U << CAN_F2FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F2FB1_FFDB13 CAN_F2FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F2FB1_FFDB14_Pos (14U) +#define CAN_F2FB1_FFDB14_Msk (0x1U << CAN_F2FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F2FB1_FFDB14 CAN_F2FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F2FB1_FFDB15_Pos (15U) +#define CAN_F2FB1_FFDB15_Msk (0x1U << CAN_F2FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F2FB1_FFDB15 CAN_F2FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F2FB1_FFDB16_Pos (16U) +#define CAN_F2FB1_FFDB16_Msk (0x1U << CAN_F2FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F2FB1_FFDB16 CAN_F2FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F2FB1_FFDB17_Pos (17U) +#define CAN_F2FB1_FFDB17_Msk (0x1U << CAN_F2FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F2FB1_FFDB17 CAN_F2FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F2FB1_FFDB18_Pos (18U) +#define CAN_F2FB1_FFDB18_Msk (0x1U << CAN_F2FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F2FB1_FFDB18 CAN_F2FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F2FB1_FFDB19_Pos (19U) +#define CAN_F2FB1_FFDB19_Msk (0x1U << CAN_F2FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F2FB1_FFDB19 CAN_F2FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F2FB1_FFDB20_Pos (20U) +#define CAN_F2FB1_FFDB20_Msk (0x1U << CAN_F2FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F2FB1_FFDB20 CAN_F2FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F2FB1_FFDB21_Pos (21U) +#define CAN_F2FB1_FFDB21_Msk (0x1U << CAN_F2FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F2FB1_FFDB21 CAN_F2FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F2FB1_FFDB22_Pos (22U) +#define CAN_F2FB1_FFDB22_Msk (0x1U << CAN_F2FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F2FB1_FFDB22 CAN_F2FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F2FB1_FFDB23_Pos (23U) +#define CAN_F2FB1_FFDB23_Msk (0x1U << CAN_F2FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F2FB1_FFDB23 CAN_F2FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F2FB1_FFDB24_Pos (24U) +#define CAN_F2FB1_FFDB24_Msk (0x1U << CAN_F2FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F2FB1_FFDB24 CAN_F2FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F2FB1_FFDB25_Pos (25U) +#define CAN_F2FB1_FFDB25_Msk (0x1U << CAN_F2FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F2FB1_FFDB25 CAN_F2FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F2FB1_FFDB26_Pos (26U) +#define CAN_F2FB1_FFDB26_Msk (0x1U << CAN_F2FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F2FB1_FFDB26 CAN_F2FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F2FB1_FFDB27_Pos (27U) +#define CAN_F2FB1_FFDB27_Msk (0x1U << CAN_F2FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F2FB1_FFDB27 CAN_F2FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F2FB1_FFDB28_Pos (28U) +#define CAN_F2FB1_FFDB28_Msk (0x1U << CAN_F2FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F2FB1_FFDB28 CAN_F2FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F2FB1_FFDB29_Pos (29U) +#define CAN_F2FB1_FFDB29_Msk (0x1U << CAN_F2FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F2FB1_FFDB29 CAN_F2FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F2FB1_FFDB30_Pos (30U) +#define CAN_F2FB1_FFDB30_Msk (0x1U << CAN_F2FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F2FB1_FFDB30 CAN_F2FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F2FB1_FFDB31_Pos (31U) +#define CAN_F2FB1_FFDB31_Msk (0x1U << CAN_F2FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F2FB1_FFDB31 CAN_F2FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F3FB1 register *******************/ +#define CAN_F3FB1_FFDB0_Pos (0U) +#define CAN_F3FB1_FFDB0_Msk (0x1U << CAN_F3FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F3FB1_FFDB0 CAN_F3FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F3FB1_FFDB1_Pos (1U) +#define CAN_F3FB1_FFDB1_Msk (0x1U << CAN_F3FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F3FB1_FFDB1 CAN_F3FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F3FB1_FFDB2_Pos (2U) +#define CAN_F3FB1_FFDB2_Msk (0x1U << CAN_F3FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F3FB1_FFDB2 CAN_F3FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F3FB1_FFDB3_Pos (3U) +#define CAN_F3FB1_FFDB3_Msk (0x1U << CAN_F3FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F3FB1_FFDB3 CAN_F3FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F3FB1_FFDB4_Pos (4U) +#define CAN_F3FB1_FFDB4_Msk (0x1U << CAN_F3FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F3FB1_FFDB4 CAN_F3FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F3FB1_FFDB5_Pos (5U) +#define CAN_F3FB1_FFDB5_Msk (0x1U << CAN_F3FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F3FB1_FFDB5 CAN_F3FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F3FB1_FFDB6_Pos (6U) +#define CAN_F3FB1_FFDB6_Msk (0x1U << CAN_F3FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F3FB1_FFDB6 CAN_F3FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F3FB1_FFDB7_Pos (7U) +#define CAN_F3FB1_FFDB7_Msk (0x1U << CAN_F3FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F3FB1_FFDB7 CAN_F3FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F3FB1_FFDB8_Pos (8U) +#define CAN_F3FB1_FFDB8_Msk (0x1U << CAN_F3FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F3FB1_FFDB8 CAN_F3FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F3FB1_FFDB9_Pos (9U) +#define CAN_F3FB1_FFDB9_Msk (0x1U << CAN_F3FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F3FB1_FFDB9 CAN_F3FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F3FB1_FFDB10_Pos (10U) +#define CAN_F3FB1_FFDB10_Msk (0x1U << CAN_F3FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F3FB1_FFDB10 CAN_F3FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F3FB1_FFDB11_Pos (11U) +#define CAN_F3FB1_FFDB11_Msk (0x1U << CAN_F3FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F3FB1_FFDB11 CAN_F3FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F3FB1_FFDB12_Pos (12U) +#define CAN_F3FB1_FFDB12_Msk (0x1U << CAN_F3FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F3FB1_FFDB12 CAN_F3FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F3FB1_FFDB13_Pos (13U) +#define CAN_F3FB1_FFDB13_Msk (0x1U << CAN_F3FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F3FB1_FFDB13 CAN_F3FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F3FB1_FFDB14_Pos (14U) +#define CAN_F3FB1_FFDB14_Msk (0x1U << CAN_F3FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F3FB1_FFDB14 CAN_F3FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F3FB1_FFDB15_Pos (15U) +#define CAN_F3FB1_FFDB15_Msk (0x1U << CAN_F3FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F3FB1_FFDB15 CAN_F3FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F3FB1_FFDB16_Pos (16U) +#define CAN_F3FB1_FFDB16_Msk (0x1U << CAN_F3FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F3FB1_FFDB16 CAN_F3FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F3FB1_FFDB17_Pos (17U) +#define CAN_F3FB1_FFDB17_Msk (0x1U << CAN_F3FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F3FB1_FFDB17 CAN_F3FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F3FB1_FFDB18_Pos (18U) +#define CAN_F3FB1_FFDB18_Msk (0x1U << CAN_F3FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F3FB1_FFDB18 CAN_F3FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F3FB1_FFDB19_Pos (19U) +#define CAN_F3FB1_FFDB19_Msk (0x1U << CAN_F3FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F3FB1_FFDB19 CAN_F3FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F3FB1_FFDB20_Pos (20U) +#define CAN_F3FB1_FFDB20_Msk (0x1U << CAN_F3FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F3FB1_FFDB20 CAN_F3FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F3FB1_FFDB21_Pos (21U) +#define CAN_F3FB1_FFDB21_Msk (0x1U << CAN_F3FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F3FB1_FFDB21 CAN_F3FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F3FB1_FFDB22_Pos (22U) +#define CAN_F3FB1_FFDB22_Msk (0x1U << CAN_F3FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F3FB1_FFDB22 CAN_F3FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F3FB1_FFDB23_Pos (23U) +#define CAN_F3FB1_FFDB23_Msk (0x1U << CAN_F3FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F3FB1_FFDB23 CAN_F3FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F3FB1_FFDB24_Pos (24U) +#define CAN_F3FB1_FFDB24_Msk (0x1U << CAN_F3FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F3FB1_FFDB24 CAN_F3FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F3FB1_FFDB25_Pos (25U) +#define CAN_F3FB1_FFDB25_Msk (0x1U << CAN_F3FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F3FB1_FFDB25 CAN_F3FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F3FB1_FFDB26_Pos (26U) +#define CAN_F3FB1_FFDB26_Msk (0x1U << CAN_F3FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F3FB1_FFDB26 CAN_F3FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F3FB1_FFDB27_Pos (27U) +#define CAN_F3FB1_FFDB27_Msk (0x1U << CAN_F3FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F3FB1_FFDB27 CAN_F3FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F3FB1_FFDB28_Pos (28U) +#define CAN_F3FB1_FFDB28_Msk (0x1U << CAN_F3FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F3FB1_FFDB28 CAN_F3FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F3FB1_FFDB29_Pos (29U) +#define CAN_F3FB1_FFDB29_Msk (0x1U << CAN_F3FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F3FB1_FFDB29 CAN_F3FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F3FB1_FFDB30_Pos (30U) +#define CAN_F3FB1_FFDB30_Msk (0x1U << CAN_F3FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F3FB1_FFDB30 CAN_F3FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F3FB1_FFDB31_Pos (31U) +#define CAN_F3FB1_FFDB31_Msk (0x1U << CAN_F3FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F3FB1_FFDB31 CAN_F3FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F4FB1 register *******************/ +#define CAN_F4FB1_FFDB0_Pos (0U) +#define CAN_F4FB1_FFDB0_Msk (0x1U << CAN_F4FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F4FB1_FFDB0 CAN_F4FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F4FB1_FFDB1_Pos (1U) +#define CAN_F4FB1_FFDB1_Msk (0x1U << CAN_F4FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F4FB1_FFDB1 CAN_F4FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F4FB1_FFDB2_Pos (2U) +#define CAN_F4FB1_FFDB2_Msk (0x1U << CAN_F4FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F4FB1_FFDB2 CAN_F4FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F4FB1_FFDB3_Pos (3U) +#define CAN_F4FB1_FFDB3_Msk (0x1U << CAN_F4FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F4FB1_FFDB3 CAN_F4FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F4FB1_FFDB4_Pos (4U) +#define CAN_F4FB1_FFDB4_Msk (0x1U << CAN_F4FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F4FB1_FFDB4 CAN_F4FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F4FB1_FFDB5_Pos (5U) +#define CAN_F4FB1_FFDB5_Msk (0x1U << CAN_F4FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F4FB1_FFDB5 CAN_F4FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F4FB1_FFDB6_Pos (6U) +#define CAN_F4FB1_FFDB6_Msk (0x1U << CAN_F4FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F4FB1_FFDB6 CAN_F4FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F4FB1_FFDB7_Pos (7U) +#define CAN_F4FB1_FFDB7_Msk (0x1U << CAN_F4FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F4FB1_FFDB7 CAN_F4FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F4FB1_FFDB8_Pos (8U) +#define CAN_F4FB1_FFDB8_Msk (0x1U << CAN_F4FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F4FB1_FFDB8 CAN_F4FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F4FB1_FFDB9_Pos (9U) +#define CAN_F4FB1_FFDB9_Msk (0x1U << CAN_F4FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F4FB1_FFDB9 CAN_F4FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F4FB1_FFDB10_Pos (10U) +#define CAN_F4FB1_FFDB10_Msk (0x1U << CAN_F4FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F4FB1_FFDB10 CAN_F4FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F4FB1_FFDB11_Pos (11U) +#define CAN_F4FB1_FFDB11_Msk (0x1U << CAN_F4FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F4FB1_FFDB11 CAN_F4FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F4FB1_FFDB12_Pos (12U) +#define CAN_F4FB1_FFDB12_Msk (0x1U << CAN_F4FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F4FB1_FFDB12 CAN_F4FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F4FB1_FFDB13_Pos (13U) +#define CAN_F4FB1_FFDB13_Msk (0x1U << CAN_F4FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F4FB1_FFDB13 CAN_F4FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F4FB1_FFDB14_Pos (14U) +#define CAN_F4FB1_FFDB14_Msk (0x1U << CAN_F4FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F4FB1_FFDB14 CAN_F4FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F4FB1_FFDB15_Pos (15U) +#define CAN_F4FB1_FFDB15_Msk (0x1U << CAN_F4FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F4FB1_FFDB15 CAN_F4FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F4FB1_FFDB16_Pos (16U) +#define CAN_F4FB1_FFDB16_Msk (0x1U << CAN_F4FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F4FB1_FFDB16 CAN_F4FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F4FB1_FFDB17_Pos (17U) +#define CAN_F4FB1_FFDB17_Msk (0x1U << CAN_F4FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F4FB1_FFDB17 CAN_F4FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F4FB1_FFDB18_Pos (18U) +#define CAN_F4FB1_FFDB18_Msk (0x1U << CAN_F4FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F4FB1_FFDB18 CAN_F4FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F4FB1_FFDB19_Pos (19U) +#define CAN_F4FB1_FFDB19_Msk (0x1U << CAN_F4FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F4FB1_FFDB19 CAN_F4FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F4FB1_FFDB20_Pos (20U) +#define CAN_F4FB1_FFDB20_Msk (0x1U << CAN_F4FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F4FB1_FFDB20 CAN_F4FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F4FB1_FFDB21_Pos (21U) +#define CAN_F4FB1_FFDB21_Msk (0x1U << CAN_F4FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F4FB1_FFDB21 CAN_F4FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F4FB1_FFDB22_Pos (22U) +#define CAN_F4FB1_FFDB22_Msk (0x1U << CAN_F4FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F4FB1_FFDB22 CAN_F4FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F4FB1_FFDB23_Pos (23U) +#define CAN_F4FB1_FFDB23_Msk (0x1U << CAN_F4FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F4FB1_FFDB23 CAN_F4FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F4FB1_FFDB24_Pos (24U) +#define CAN_F4FB1_FFDB24_Msk (0x1U << CAN_F4FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F4FB1_FFDB24 CAN_F4FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F4FB1_FFDB25_Pos (25U) +#define CAN_F4FB1_FFDB25_Msk (0x1U << CAN_F4FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F4FB1_FFDB25 CAN_F4FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F4FB1_FFDB26_Pos (26U) +#define CAN_F4FB1_FFDB26_Msk (0x1U << CAN_F4FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F4FB1_FFDB26 CAN_F4FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F4FB1_FFDB27_Pos (27U) +#define CAN_F4FB1_FFDB27_Msk (0x1U << CAN_F4FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F4FB1_FFDB27 CAN_F4FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F4FB1_FFDB28_Pos (28U) +#define CAN_F4FB1_FFDB28_Msk (0x1U << CAN_F4FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F4FB1_FFDB28 CAN_F4FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F4FB1_FFDB29_Pos (29U) +#define CAN_F4FB1_FFDB29_Msk (0x1U << CAN_F4FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F4FB1_FFDB29 CAN_F4FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F4FB1_FFDB30_Pos (30U) +#define CAN_F4FB1_FFDB30_Msk (0x1U << CAN_F4FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F4FB1_FFDB30 CAN_F4FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F4FB1_FFDB31_Pos (31U) +#define CAN_F4FB1_FFDB31_Msk (0x1U << CAN_F4FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F4FB1_FFDB31 CAN_F4FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F5FB1 register *******************/ +#define CAN_F5FB1_FFDB0_Pos (0U) +#define CAN_F5FB1_FFDB0_Msk (0x1U << CAN_F5FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F5FB1_FFDB0 CAN_F5FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F5FB1_FFDB1_Pos (1U) +#define CAN_F5FB1_FFDB1_Msk (0x1U << CAN_F5FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F5FB1_FFDB1 CAN_F5FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F5FB1_FFDB2_Pos (2U) +#define CAN_F5FB1_FFDB2_Msk (0x1U << CAN_F5FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F5FB1_FFDB2 CAN_F5FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F5FB1_FFDB3_Pos (3U) +#define CAN_F5FB1_FFDB3_Msk (0x1U << CAN_F5FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F5FB1_FFDB3 CAN_F5FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F5FB1_FFDB4_Pos (4U) +#define CAN_F5FB1_FFDB4_Msk (0x1U << CAN_F5FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F5FB1_FFDB4 CAN_F5FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F5FB1_FFDB5_Pos (5U) +#define CAN_F5FB1_FFDB5_Msk (0x1U << CAN_F5FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F5FB1_FFDB5 CAN_F5FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F5FB1_FFDB6_Pos (6U) +#define CAN_F5FB1_FFDB6_Msk (0x1U << CAN_F5FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F5FB1_FFDB6 CAN_F5FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F5FB1_FFDB7_Pos (7U) +#define CAN_F5FB1_FFDB7_Msk (0x1U << CAN_F5FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F5FB1_FFDB7 CAN_F5FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F5FB1_FFDB8_Pos (8U) +#define CAN_F5FB1_FFDB8_Msk (0x1U << CAN_F5FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F5FB1_FFDB8 CAN_F5FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F5FB1_FFDB9_Pos (9U) +#define CAN_F5FB1_FFDB9_Msk (0x1U << CAN_F5FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F5FB1_FFDB9 CAN_F5FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F5FB1_FFDB10_Pos (10U) +#define CAN_F5FB1_FFDB10_Msk (0x1U << CAN_F5FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F5FB1_FFDB10 CAN_F5FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F5FB1_FFDB11_Pos (11U) +#define CAN_F5FB1_FFDB11_Msk (0x1U << CAN_F5FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F5FB1_FFDB11 CAN_F5FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F5FB1_FFDB12_Pos (12U) +#define CAN_F5FB1_FFDB12_Msk (0x1U << CAN_F5FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F5FB1_FFDB12 CAN_F5FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F5FB1_FFDB13_Pos (13U) +#define CAN_F5FB1_FFDB13_Msk (0x1U << CAN_F5FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F5FB1_FFDB13 CAN_F5FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F5FB1_FFDB14_Pos (14U) +#define CAN_F5FB1_FFDB14_Msk (0x1U << CAN_F5FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F5FB1_FFDB14 CAN_F5FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F5FB1_FFDB15_Pos (15U) +#define CAN_F5FB1_FFDB15_Msk (0x1U << CAN_F5FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F5FB1_FFDB15 CAN_F5FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F5FB1_FFDB16_Pos (16U) +#define CAN_F5FB1_FFDB16_Msk (0x1U << CAN_F5FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F5FB1_FFDB16 CAN_F5FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F5FB1_FFDB17_Pos (17U) +#define CAN_F5FB1_FFDB17_Msk (0x1U << CAN_F5FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F5FB1_FFDB17 CAN_F5FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F5FB1_FFDB18_Pos (18U) +#define CAN_F5FB1_FFDB18_Msk (0x1U << CAN_F5FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F5FB1_FFDB18 CAN_F5FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F5FB1_FFDB19_Pos (19U) +#define CAN_F5FB1_FFDB19_Msk (0x1U << CAN_F5FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F5FB1_FFDB19 CAN_F5FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F5FB1_FFDB20_Pos (20U) +#define CAN_F5FB1_FFDB20_Msk (0x1U << CAN_F5FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F5FB1_FFDB20 CAN_F5FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F5FB1_FFDB21_Pos (21U) +#define CAN_F5FB1_FFDB21_Msk (0x1U << CAN_F5FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F5FB1_FFDB21 CAN_F5FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F5FB1_FFDB22_Pos (22U) +#define CAN_F5FB1_FFDB22_Msk (0x1U << CAN_F5FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F5FB1_FFDB22 CAN_F5FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F5FB1_FFDB23_Pos (23U) +#define CAN_F5FB1_FFDB23_Msk (0x1U << CAN_F5FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F5FB1_FFDB23 CAN_F5FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F5FB1_FFDB24_Pos (24U) +#define CAN_F5FB1_FFDB24_Msk (0x1U << CAN_F5FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F5FB1_FFDB24 CAN_F5FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F5FB1_FFDB25_Pos (25U) +#define CAN_F5FB1_FFDB25_Msk (0x1U << CAN_F5FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F5FB1_FFDB25 CAN_F5FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F5FB1_FFDB26_Pos (26U) +#define CAN_F5FB1_FFDB26_Msk (0x1U << CAN_F5FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F5FB1_FFDB26 CAN_F5FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F5FB1_FFDB27_Pos (27U) +#define CAN_F5FB1_FFDB27_Msk (0x1U << CAN_F5FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F5FB1_FFDB27 CAN_F5FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F5FB1_FFDB28_Pos (28U) +#define CAN_F5FB1_FFDB28_Msk (0x1U << CAN_F5FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F5FB1_FFDB28 CAN_F5FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F5FB1_FFDB29_Pos (29U) +#define CAN_F5FB1_FFDB29_Msk (0x1U << CAN_F5FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F5FB1_FFDB29 CAN_F5FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F5FB1_FFDB30_Pos (30U) +#define CAN_F5FB1_FFDB30_Msk (0x1U << CAN_F5FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F5FB1_FFDB30 CAN_F5FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F5FB1_FFDB31_Pos (31U) +#define CAN_F5FB1_FFDB31_Msk (0x1U << CAN_F5FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F5FB1_FFDB31 CAN_F5FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F6FB1 register *******************/ +#define CAN_F6FB1_FFDB0_Pos (0U) +#define CAN_F6FB1_FFDB0_Msk (0x1U << CAN_F6FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F6FB1_FFDB0 CAN_F6FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F6FB1_FFDB1_Pos (1U) +#define CAN_F6FB1_FFDB1_Msk (0x1U << CAN_F6FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F6FB1_FFDB1 CAN_F6FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F6FB1_FFDB2_Pos (2U) +#define CAN_F6FB1_FFDB2_Msk (0x1U << CAN_F6FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F6FB1_FFDB2 CAN_F6FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F6FB1_FFDB3_Pos (3U) +#define CAN_F6FB1_FFDB3_Msk (0x1U << CAN_F6FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F6FB1_FFDB3 CAN_F6FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F6FB1_FFDB4_Pos (4U) +#define CAN_F6FB1_FFDB4_Msk (0x1U << CAN_F6FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F6FB1_FFDB4 CAN_F6FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F6FB1_FFDB5_Pos (5U) +#define CAN_F6FB1_FFDB5_Msk (0x1U << CAN_F6FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F6FB1_FFDB5 CAN_F6FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F6FB1_FFDB6_Pos (6U) +#define CAN_F6FB1_FFDB6_Msk (0x1U << CAN_F6FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F6FB1_FFDB6 CAN_F6FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F6FB1_FFDB7_Pos (7U) +#define CAN_F6FB1_FFDB7_Msk (0x1U << CAN_F6FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F6FB1_FFDB7 CAN_F6FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F6FB1_FFDB8_Pos (8U) +#define CAN_F6FB1_FFDB8_Msk (0x1U << CAN_F6FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F6FB1_FFDB8 CAN_F6FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F6FB1_FFDB9_Pos (9U) +#define CAN_F6FB1_FFDB9_Msk (0x1U << CAN_F6FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F6FB1_FFDB9 CAN_F6FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F6FB1_FFDB10_Pos (10U) +#define CAN_F6FB1_FFDB10_Msk (0x1U << CAN_F6FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F6FB1_FFDB10 CAN_F6FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F6FB1_FFDB11_Pos (11U) +#define CAN_F6FB1_FFDB11_Msk (0x1U << CAN_F6FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F6FB1_FFDB11 CAN_F6FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F6FB1_FFDB12_Pos (12U) +#define CAN_F6FB1_FFDB12_Msk (0x1U << CAN_F6FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F6FB1_FFDB12 CAN_F6FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F6FB1_FFDB13_Pos (13U) +#define CAN_F6FB1_FFDB13_Msk (0x1U << CAN_F6FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F6FB1_FFDB13 CAN_F6FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F6FB1_FFDB14_Pos (14U) +#define CAN_F6FB1_FFDB14_Msk (0x1U << CAN_F6FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F6FB1_FFDB14 CAN_F6FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F6FB1_FFDB15_Pos (15U) +#define CAN_F6FB1_FFDB15_Msk (0x1U << CAN_F6FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F6FB1_FFDB15 CAN_F6FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F6FB1_FFDB16_Pos (16U) +#define CAN_F6FB1_FFDB16_Msk (0x1U << CAN_F6FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F6FB1_FFDB16 CAN_F6FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F6FB1_FFDB17_Pos (17U) +#define CAN_F6FB1_FFDB17_Msk (0x1U << CAN_F6FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F6FB1_FFDB17 CAN_F6FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F6FB1_FFDB18_Pos (18U) +#define CAN_F6FB1_FFDB18_Msk (0x1U << CAN_F6FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F6FB1_FFDB18 CAN_F6FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F6FB1_FFDB19_Pos (19U) +#define CAN_F6FB1_FFDB19_Msk (0x1U << CAN_F6FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F6FB1_FFDB19 CAN_F6FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F6FB1_FFDB20_Pos (20U) +#define CAN_F6FB1_FFDB20_Msk (0x1U << CAN_F6FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F6FB1_FFDB20 CAN_F6FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F6FB1_FFDB21_Pos (21U) +#define CAN_F6FB1_FFDB21_Msk (0x1U << CAN_F6FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F6FB1_FFDB21 CAN_F6FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F6FB1_FFDB22_Pos (22U) +#define CAN_F6FB1_FFDB22_Msk (0x1U << CAN_F6FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F6FB1_FFDB22 CAN_F6FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F6FB1_FFDB23_Pos (23U) +#define CAN_F6FB1_FFDB23_Msk (0x1U << CAN_F6FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F6FB1_FFDB23 CAN_F6FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F6FB1_FFDB24_Pos (24U) +#define CAN_F6FB1_FFDB24_Msk (0x1U << CAN_F6FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F6FB1_FFDB24 CAN_F6FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F6FB1_FFDB25_Pos (25U) +#define CAN_F6FB1_FFDB25_Msk (0x1U << CAN_F6FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F6FB1_FFDB25 CAN_F6FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F6FB1_FFDB26_Pos (26U) +#define CAN_F6FB1_FFDB26_Msk (0x1U << CAN_F6FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F6FB1_FFDB26 CAN_F6FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F6FB1_FFDB27_Pos (27U) +#define CAN_F6FB1_FFDB27_Msk (0x1U << CAN_F6FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F6FB1_FFDB27 CAN_F6FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F6FB1_FFDB28_Pos (28U) +#define CAN_F6FB1_FFDB28_Msk (0x1U << CAN_F6FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F6FB1_FFDB28 CAN_F6FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F6FB1_FFDB29_Pos (29U) +#define CAN_F6FB1_FFDB29_Msk (0x1U << CAN_F6FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F6FB1_FFDB29 CAN_F6FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F6FB1_FFDB30_Pos (30U) +#define CAN_F6FB1_FFDB30_Msk (0x1U << CAN_F6FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F6FB1_FFDB30 CAN_F6FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F6FB1_FFDB31_Pos (31U) +#define CAN_F6FB1_FFDB31_Msk (0x1U << CAN_F6FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F6FB1_FFDB31 CAN_F6FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F7FB1 register *******************/ +#define CAN_F7FB1_FFDB0_Pos (0U) +#define CAN_F7FB1_FFDB0_Msk (0x1U << CAN_F7FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F7FB1_FFDB0 CAN_F7FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F7FB1_FFDB1_Pos (1U) +#define CAN_F7FB1_FFDB1_Msk (0x1U << CAN_F7FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F7FB1_FFDB1 CAN_F7FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F7FB1_FFDB2_Pos (2U) +#define CAN_F7FB1_FFDB2_Msk (0x1U << CAN_F7FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F7FB1_FFDB2 CAN_F7FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F7FB1_FFDB3_Pos (3U) +#define CAN_F7FB1_FFDB3_Msk (0x1U << CAN_F7FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F7FB1_FFDB3 CAN_F7FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F7FB1_FFDB4_Pos (4U) +#define CAN_F7FB1_FFDB4_Msk (0x1U << CAN_F7FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F7FB1_FFDB4 CAN_F7FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F7FB1_FFDB5_Pos (5U) +#define CAN_F7FB1_FFDB5_Msk (0x1U << CAN_F7FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F7FB1_FFDB5 CAN_F7FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F7FB1_FFDB6_Pos (6U) +#define CAN_F7FB1_FFDB6_Msk (0x1U << CAN_F7FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F7FB1_FFDB6 CAN_F7FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F7FB1_FFDB7_Pos (7U) +#define CAN_F7FB1_FFDB7_Msk (0x1U << CAN_F7FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F7FB1_FFDB7 CAN_F7FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F7FB1_FFDB8_Pos (8U) +#define CAN_F7FB1_FFDB8_Msk (0x1U << CAN_F7FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F7FB1_FFDB8 CAN_F7FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F7FB1_FFDB9_Pos (9U) +#define CAN_F7FB1_FFDB9_Msk (0x1U << CAN_F7FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F7FB1_FFDB9 CAN_F7FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F7FB1_FFDB10_Pos (10U) +#define CAN_F7FB1_FFDB10_Msk (0x1U << CAN_F7FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F7FB1_FFDB10 CAN_F7FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F7FB1_FFDB11_Pos (11U) +#define CAN_F7FB1_FFDB11_Msk (0x1U << CAN_F7FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F7FB1_FFDB11 CAN_F7FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F7FB1_FFDB12_Pos (12U) +#define CAN_F7FB1_FFDB12_Msk (0x1U << CAN_F7FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F7FB1_FFDB12 CAN_F7FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F7FB1_FFDB13_Pos (13U) +#define CAN_F7FB1_FFDB13_Msk (0x1U << CAN_F7FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F7FB1_FFDB13 CAN_F7FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F7FB1_FFDB14_Pos (14U) +#define CAN_F7FB1_FFDB14_Msk (0x1U << CAN_F7FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F7FB1_FFDB14 CAN_F7FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F7FB1_FFDB15_Pos (15U) +#define CAN_F7FB1_FFDB15_Msk (0x1U << CAN_F7FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F7FB1_FFDB15 CAN_F7FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F7FB1_FFDB16_Pos (16U) +#define CAN_F7FB1_FFDB16_Msk (0x1U << CAN_F7FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F7FB1_FFDB16 CAN_F7FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F7FB1_FFDB17_Pos (17U) +#define CAN_F7FB1_FFDB17_Msk (0x1U << CAN_F7FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F7FB1_FFDB17 CAN_F7FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F7FB1_FFDB18_Pos (18U) +#define CAN_F7FB1_FFDB18_Msk (0x1U << CAN_F7FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F7FB1_FFDB18 CAN_F7FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F7FB1_FFDB19_Pos (19U) +#define CAN_F7FB1_FFDB19_Msk (0x1U << CAN_F7FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F7FB1_FFDB19 CAN_F7FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F7FB1_FFDB20_Pos (20U) +#define CAN_F7FB1_FFDB20_Msk (0x1U << CAN_F7FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F7FB1_FFDB20 CAN_F7FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F7FB1_FFDB21_Pos (21U) +#define CAN_F7FB1_FFDB21_Msk (0x1U << CAN_F7FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F7FB1_FFDB21 CAN_F7FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F7FB1_FFDB22_Pos (22U) +#define CAN_F7FB1_FFDB22_Msk (0x1U << CAN_F7FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F7FB1_FFDB22 CAN_F7FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F7FB1_FFDB23_Pos (23U) +#define CAN_F7FB1_FFDB23_Msk (0x1U << CAN_F7FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F7FB1_FFDB23 CAN_F7FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F7FB1_FFDB24_Pos (24U) +#define CAN_F7FB1_FFDB24_Msk (0x1U << CAN_F7FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F7FB1_FFDB24 CAN_F7FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F7FB1_FFDB25_Pos (25U) +#define CAN_F7FB1_FFDB25_Msk (0x1U << CAN_F7FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F7FB1_FFDB25 CAN_F7FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F7FB1_FFDB26_Pos (26U) +#define CAN_F7FB1_FFDB26_Msk (0x1U << CAN_F7FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F7FB1_FFDB26 CAN_F7FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F7FB1_FFDB27_Pos (27U) +#define CAN_F7FB1_FFDB27_Msk (0x1U << CAN_F7FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F7FB1_FFDB27 CAN_F7FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F7FB1_FFDB28_Pos (28U) +#define CAN_F7FB1_FFDB28_Msk (0x1U << CAN_F7FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F7FB1_FFDB28 CAN_F7FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F7FB1_FFDB29_Pos (29U) +#define CAN_F7FB1_FFDB29_Msk (0x1U << CAN_F7FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F7FB1_FFDB29 CAN_F7FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F7FB1_FFDB30_Pos (30U) +#define CAN_F7FB1_FFDB30_Msk (0x1U << CAN_F7FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F7FB1_FFDB30 CAN_F7FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F7FB1_FFDB31_Pos (31U) +#define CAN_F7FB1_FFDB31_Msk (0x1U << CAN_F7FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F7FB1_FFDB31 CAN_F7FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F8FB1 register *******************/ +#define CAN_F8FB1_FFDB0_Pos (0U) +#define CAN_F8FB1_FFDB0_Msk (0x1U << CAN_F8FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F8FB1_FFDB0 CAN_F8FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F8FB1_FFDB1_Pos (1U) +#define CAN_F8FB1_FFDB1_Msk (0x1U << CAN_F8FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F8FB1_FFDB1 CAN_F8FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F8FB1_FFDB2_Pos (2U) +#define CAN_F8FB1_FFDB2_Msk (0x1U << CAN_F8FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F8FB1_FFDB2 CAN_F8FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F8FB1_FFDB3_Pos (3U) +#define CAN_F8FB1_FFDB3_Msk (0x1U << CAN_F8FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F8FB1_FFDB3 CAN_F8FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F8FB1_FFDB4_Pos (4U) +#define CAN_F8FB1_FFDB4_Msk (0x1U << CAN_F8FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F8FB1_FFDB4 CAN_F8FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F8FB1_FFDB5_Pos (5U) +#define CAN_F8FB1_FFDB5_Msk (0x1U << CAN_F8FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F8FB1_FFDB5 CAN_F8FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F8FB1_FFDB6_Pos (6U) +#define CAN_F8FB1_FFDB6_Msk (0x1U << CAN_F8FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F8FB1_FFDB6 CAN_F8FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F8FB1_FFDB7_Pos (7U) +#define CAN_F8FB1_FFDB7_Msk (0x1U << CAN_F8FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F8FB1_FFDB7 CAN_F8FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F8FB1_FFDB8_Pos (8U) +#define CAN_F8FB1_FFDB8_Msk (0x1U << CAN_F8FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F8FB1_FFDB8 CAN_F8FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F8FB1_FFDB9_Pos (9U) +#define CAN_F8FB1_FFDB9_Msk (0x1U << CAN_F8FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F8FB1_FFDB9 CAN_F8FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F8FB1_FFDB10_Pos (10U) +#define CAN_F8FB1_FFDB10_Msk (0x1U << CAN_F8FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F8FB1_FFDB10 CAN_F8FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F8FB1_FFDB11_Pos (11U) +#define CAN_F8FB1_FFDB11_Msk (0x1U << CAN_F8FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F8FB1_FFDB11 CAN_F8FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F8FB1_FFDB12_Pos (12U) +#define CAN_F8FB1_FFDB12_Msk (0x1U << CAN_F8FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F8FB1_FFDB12 CAN_F8FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F8FB1_FFDB13_Pos (13U) +#define CAN_F8FB1_FFDB13_Msk (0x1U << CAN_F8FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F8FB1_FFDB13 CAN_F8FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F8FB1_FFDB14_Pos (14U) +#define CAN_F8FB1_FFDB14_Msk (0x1U << CAN_F8FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F8FB1_FFDB14 CAN_F8FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F8FB1_FFDB15_Pos (15U) +#define CAN_F8FB1_FFDB15_Msk (0x1U << CAN_F8FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F8FB1_FFDB15 CAN_F8FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F8FB1_FFDB16_Pos (16U) +#define CAN_F8FB1_FFDB16_Msk (0x1U << CAN_F8FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F8FB1_FFDB16 CAN_F8FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F8FB1_FFDB17_Pos (17U) +#define CAN_F8FB1_FFDB17_Msk (0x1U << CAN_F8FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F8FB1_FFDB17 CAN_F8FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F8FB1_FFDB18_Pos (18U) +#define CAN_F8FB1_FFDB18_Msk (0x1U << CAN_F8FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F8FB1_FFDB18 CAN_F8FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F8FB1_FFDB19_Pos (19U) +#define CAN_F8FB1_FFDB19_Msk (0x1U << CAN_F8FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F8FB1_FFDB19 CAN_F8FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F8FB1_FFDB20_Pos (20U) +#define CAN_F8FB1_FFDB20_Msk (0x1U << CAN_F8FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F8FB1_FFDB20 CAN_F8FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F8FB1_FFDB21_Pos (21U) +#define CAN_F8FB1_FFDB21_Msk (0x1U << CAN_F8FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F8FB1_FFDB21 CAN_F8FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F8FB1_FFDB22_Pos (22U) +#define CAN_F8FB1_FFDB22_Msk (0x1U << CAN_F8FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F8FB1_FFDB22 CAN_F8FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F8FB1_FFDB23_Pos (23U) +#define CAN_F8FB1_FFDB23_Msk (0x1U << CAN_F8FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F8FB1_FFDB23 CAN_F8FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F8FB1_FFDB24_Pos (24U) +#define CAN_F8FB1_FFDB24_Msk (0x1U << CAN_F8FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F8FB1_FFDB24 CAN_F8FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F8FB1_FFDB25_Pos (25U) +#define CAN_F8FB1_FFDB25_Msk (0x1U << CAN_F8FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F8FB1_FFDB25 CAN_F8FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F8FB1_FFDB26_Pos (26U) +#define CAN_F8FB1_FFDB26_Msk (0x1U << CAN_F8FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F8FB1_FFDB26 CAN_F8FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F8FB1_FFDB27_Pos (27U) +#define CAN_F8FB1_FFDB27_Msk (0x1U << CAN_F8FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F8FB1_FFDB27 CAN_F8FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F8FB1_FFDB28_Pos (28U) +#define CAN_F8FB1_FFDB28_Msk (0x1U << CAN_F8FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F8FB1_FFDB28 CAN_F8FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F8FB1_FFDB29_Pos (29U) +#define CAN_F8FB1_FFDB29_Msk (0x1U << CAN_F8FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F8FB1_FFDB29 CAN_F8FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F8FB1_FFDB30_Pos (30U) +#define CAN_F8FB1_FFDB30_Msk (0x1U << CAN_F8FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F8FB1_FFDB30 CAN_F8FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F8FB1_FFDB31_Pos (31U) +#define CAN_F8FB1_FFDB31_Msk (0x1U << CAN_F8FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F8FB1_FFDB31 CAN_F8FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F9FB1 register *******************/ +#define CAN_F9FB1_FFDB0_Pos (0U) +#define CAN_F9FB1_FFDB0_Msk (0x1U << CAN_F9FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F9FB1_FFDB0 CAN_F9FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F9FB1_FFDB1_Pos (1U) +#define CAN_F9FB1_FFDB1_Msk (0x1U << CAN_F9FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F9FB1_FFDB1 CAN_F9FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F9FB1_FFDB2_Pos (2U) +#define CAN_F9FB1_FFDB2_Msk (0x1U << CAN_F9FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F9FB1_FFDB2 CAN_F9FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F9FB1_FFDB3_Pos (3U) +#define CAN_F9FB1_FFDB3_Msk (0x1U << CAN_F9FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F9FB1_FFDB3 CAN_F9FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F9FB1_FFDB4_Pos (4U) +#define CAN_F9FB1_FFDB4_Msk (0x1U << CAN_F9FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F9FB1_FFDB4 CAN_F9FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F9FB1_FFDB5_Pos (5U) +#define CAN_F9FB1_FFDB5_Msk (0x1U << CAN_F9FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F9FB1_FFDB5 CAN_F9FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F9FB1_FFDB6_Pos (6U) +#define CAN_F9FB1_FFDB6_Msk (0x1U << CAN_F9FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F9FB1_FFDB6 CAN_F9FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F9FB1_FFDB7_Pos (7U) +#define CAN_F9FB1_FFDB7_Msk (0x1U << CAN_F9FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F9FB1_FFDB7 CAN_F9FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F9FB1_FFDB8_Pos (8U) +#define CAN_F9FB1_FFDB8_Msk (0x1U << CAN_F9FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F9FB1_FFDB8 CAN_F9FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F9FB1_FFDB9_Pos (9U) +#define CAN_F9FB1_FFDB9_Msk (0x1U << CAN_F9FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F9FB1_FFDB9 CAN_F9FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F9FB1_FFDB10_Pos (10U) +#define CAN_F9FB1_FFDB10_Msk (0x1U << CAN_F9FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F9FB1_FFDB10 CAN_F9FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F9FB1_FFDB11_Pos (11U) +#define CAN_F9FB1_FFDB11_Msk (0x1U << CAN_F9FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F9FB1_FFDB11 CAN_F9FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F9FB1_FFDB12_Pos (12U) +#define CAN_F9FB1_FFDB12_Msk (0x1U << CAN_F9FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F9FB1_FFDB12 CAN_F9FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F9FB1_FFDB13_Pos (13U) +#define CAN_F9FB1_FFDB13_Msk (0x1U << CAN_F9FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F9FB1_FFDB13 CAN_F9FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F9FB1_FFDB14_Pos (14U) +#define CAN_F9FB1_FFDB14_Msk (0x1U << CAN_F9FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F9FB1_FFDB14 CAN_F9FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F9FB1_FFDB15_Pos (15U) +#define CAN_F9FB1_FFDB15_Msk (0x1U << CAN_F9FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F9FB1_FFDB15 CAN_F9FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F9FB1_FFDB16_Pos (16U) +#define CAN_F9FB1_FFDB16_Msk (0x1U << CAN_F9FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F9FB1_FFDB16 CAN_F9FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F9FB1_FFDB17_Pos (17U) +#define CAN_F9FB1_FFDB17_Msk (0x1U << CAN_F9FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F9FB1_FFDB17 CAN_F9FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F9FB1_FFDB18_Pos (18U) +#define CAN_F9FB1_FFDB18_Msk (0x1U << CAN_F9FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F9FB1_FFDB18 CAN_F9FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F9FB1_FFDB19_Pos (19U) +#define CAN_F9FB1_FFDB19_Msk (0x1U << CAN_F9FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F9FB1_FFDB19 CAN_F9FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F9FB1_FFDB20_Pos (20U) +#define CAN_F9FB1_FFDB20_Msk (0x1U << CAN_F9FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F9FB1_FFDB20 CAN_F9FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F9FB1_FFDB21_Pos (21U) +#define CAN_F9FB1_FFDB21_Msk (0x1U << CAN_F9FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F9FB1_FFDB21 CAN_F9FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F9FB1_FFDB22_Pos (22U) +#define CAN_F9FB1_FFDB22_Msk (0x1U << CAN_F9FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F9FB1_FFDB22 CAN_F9FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F9FB1_FFDB23_Pos (23U) +#define CAN_F9FB1_FFDB23_Msk (0x1U << CAN_F9FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F9FB1_FFDB23 CAN_F9FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F9FB1_FFDB24_Pos (24U) +#define CAN_F9FB1_FFDB24_Msk (0x1U << CAN_F9FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F9FB1_FFDB24 CAN_F9FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F9FB1_FFDB25_Pos (25U) +#define CAN_F9FB1_FFDB25_Msk (0x1U << CAN_F9FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F9FB1_FFDB25 CAN_F9FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F9FB1_FFDB26_Pos (26U) +#define CAN_F9FB1_FFDB26_Msk (0x1U << CAN_F9FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F9FB1_FFDB26 CAN_F9FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F9FB1_FFDB27_Pos (27U) +#define CAN_F9FB1_FFDB27_Msk (0x1U << CAN_F9FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F9FB1_FFDB27 CAN_F9FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F9FB1_FFDB28_Pos (28U) +#define CAN_F9FB1_FFDB28_Msk (0x1U << CAN_F9FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F9FB1_FFDB28 CAN_F9FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F9FB1_FFDB29_Pos (29U) +#define CAN_F9FB1_FFDB29_Msk (0x1U << CAN_F9FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F9FB1_FFDB29 CAN_F9FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F9FB1_FFDB30_Pos (30U) +#define CAN_F9FB1_FFDB30_Msk (0x1U << CAN_F9FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F9FB1_FFDB30 CAN_F9FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F9FB1_FFDB31_Pos (31U) +#define CAN_F9FB1_FFDB31_Msk (0x1U << CAN_F9FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F9FB1_FFDB31 CAN_F9FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F10FB1 register ******************/ +#define CAN_F10FB1_FFDB0_Pos (0U) +#define CAN_F10FB1_FFDB0_Msk (0x1U << CAN_F10FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F10FB1_FFDB0 CAN_F10FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F10FB1_FFDB1_Pos (1U) +#define CAN_F10FB1_FFDB1_Msk (0x1U << CAN_F10FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F10FB1_FFDB1 CAN_F10FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F10FB1_FFDB2_Pos (2U) +#define CAN_F10FB1_FFDB2_Msk (0x1U << CAN_F10FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F10FB1_FFDB2 CAN_F10FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F10FB1_FFDB3_Pos (3U) +#define CAN_F10FB1_FFDB3_Msk (0x1U << CAN_F10FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F10FB1_FFDB3 CAN_F10FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F10FB1_FFDB4_Pos (4U) +#define CAN_F10FB1_FFDB4_Msk (0x1U << CAN_F10FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F10FB1_FFDB4 CAN_F10FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F10FB1_FFDB5_Pos (5U) +#define CAN_F10FB1_FFDB5_Msk (0x1U << CAN_F10FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F10FB1_FFDB5 CAN_F10FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F10FB1_FFDB6_Pos (6U) +#define CAN_F10FB1_FFDB6_Msk (0x1U << CAN_F10FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F10FB1_FFDB6 CAN_F10FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F10FB1_FFDB7_Pos (7U) +#define CAN_F10FB1_FFDB7_Msk (0x1U << CAN_F10FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F10FB1_FFDB7 CAN_F10FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F10FB1_FFDB8_Pos (8U) +#define CAN_F10FB1_FFDB8_Msk (0x1U << CAN_F10FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F10FB1_FFDB8 CAN_F10FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F10FB1_FFDB9_Pos (9U) +#define CAN_F10FB1_FFDB9_Msk (0x1U << CAN_F10FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F10FB1_FFDB9 CAN_F10FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F10FB1_FFDB10_Pos (10U) +#define CAN_F10FB1_FFDB10_Msk (0x1U << CAN_F10FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F10FB1_FFDB10 CAN_F10FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F10FB1_FFDB11_Pos (11U) +#define CAN_F10FB1_FFDB11_Msk (0x1U << CAN_F10FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F10FB1_FFDB11 CAN_F10FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F10FB1_FFDB12_Pos (12U) +#define CAN_F10FB1_FFDB12_Msk (0x1U << CAN_F10FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F10FB1_FFDB12 CAN_F10FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F10FB1_FFDB13_Pos (13U) +#define CAN_F10FB1_FFDB13_Msk (0x1U << CAN_F10FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F10FB1_FFDB13 CAN_F10FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F10FB1_FFDB14_Pos (14U) +#define CAN_F10FB1_FFDB14_Msk (0x1U << CAN_F10FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F10FB1_FFDB14 CAN_F10FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F10FB1_FFDB15_Pos (15U) +#define CAN_F10FB1_FFDB15_Msk (0x1U << CAN_F10FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F10FB1_FFDB15 CAN_F10FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F10FB1_FFDB16_Pos (16U) +#define CAN_F10FB1_FFDB16_Msk (0x1U << CAN_F10FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F10FB1_FFDB16 CAN_F10FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F10FB1_FFDB17_Pos (17U) +#define CAN_F10FB1_FFDB17_Msk (0x1U << CAN_F10FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F10FB1_FFDB17 CAN_F10FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F10FB1_FFDB18_Pos (18U) +#define CAN_F10FB1_FFDB18_Msk (0x1U << CAN_F10FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F10FB1_FFDB18 CAN_F10FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F10FB1_FFDB19_Pos (19U) +#define CAN_F10FB1_FFDB19_Msk (0x1U << CAN_F10FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F10FB1_FFDB19 CAN_F10FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F10FB1_FFDB20_Pos (20U) +#define CAN_F10FB1_FFDB20_Msk (0x1U << CAN_F10FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F10FB1_FFDB20 CAN_F10FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F10FB1_FFDB21_Pos (21U) +#define CAN_F10FB1_FFDB21_Msk (0x1U << CAN_F10FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F10FB1_FFDB21 CAN_F10FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F10FB1_FFDB22_Pos (22U) +#define CAN_F10FB1_FFDB22_Msk (0x1U << CAN_F10FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F10FB1_FFDB22 CAN_F10FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F10FB1_FFDB23_Pos (23U) +#define CAN_F10FB1_FFDB23_Msk (0x1U << CAN_F10FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F10FB1_FFDB23 CAN_F10FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F10FB1_FFDB24_Pos (24U) +#define CAN_F10FB1_FFDB24_Msk (0x1U << CAN_F10FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F10FB1_FFDB24 CAN_F10FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F10FB1_FFDB25_Pos (25U) +#define CAN_F10FB1_FFDB25_Msk (0x1U << CAN_F10FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F10FB1_FFDB25 CAN_F10FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F10FB1_FFDB26_Pos (26U) +#define CAN_F10FB1_FFDB26_Msk (0x1U << CAN_F10FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F10FB1_FFDB26 CAN_F10FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F10FB1_FFDB27_Pos (27U) +#define CAN_F10FB1_FFDB27_Msk (0x1U << CAN_F10FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F10FB1_FFDB27 CAN_F10FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F10FB1_FFDB28_Pos (28U) +#define CAN_F10FB1_FFDB28_Msk (0x1U << CAN_F10FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F10FB1_FFDB28 CAN_F10FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F10FB1_FFDB29_Pos (29U) +#define CAN_F10FB1_FFDB29_Msk (0x1U << CAN_F10FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F10FB1_FFDB29 CAN_F10FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F10FB1_FFDB30_Pos (30U) +#define CAN_F10FB1_FFDB30_Msk (0x1U << CAN_F10FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F10FB1_FFDB30 CAN_F10FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F10FB1_FFDB31_Pos (31U) +#define CAN_F10FB1_FFDB31_Msk (0x1U << CAN_F10FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F10FB1_FFDB31 CAN_F10FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F11FB1 register ******************/ +#define CAN_F11FB1_FFDB0_Pos (0U) +#define CAN_F11FB1_FFDB0_Msk (0x1U << CAN_F11FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F11FB1_FFDB0 CAN_F11FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F11FB1_FFDB1_Pos (1U) +#define CAN_F11FB1_FFDB1_Msk (0x1U << CAN_F11FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F11FB1_FFDB1 CAN_F11FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F11FB1_FFDB2_Pos (2U) +#define CAN_F11FB1_FFDB2_Msk (0x1U << CAN_F11FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F11FB1_FFDB2 CAN_F11FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F11FB1_FFDB3_Pos (3U) +#define CAN_F11FB1_FFDB3_Msk (0x1U << CAN_F11FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F11FB1_FFDB3 CAN_F11FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F11FB1_FFDB4_Pos (4U) +#define CAN_F11FB1_FFDB4_Msk (0x1U << CAN_F11FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F11FB1_FFDB4 CAN_F11FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F11FB1_FFDB5_Pos (5U) +#define CAN_F11FB1_FFDB5_Msk (0x1U << CAN_F11FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F11FB1_FFDB5 CAN_F11FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F11FB1_FFDB6_Pos (6U) +#define CAN_F11FB1_FFDB6_Msk (0x1U << CAN_F11FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F11FB1_FFDB6 CAN_F11FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F11FB1_FFDB7_Pos (7U) +#define CAN_F11FB1_FFDB7_Msk (0x1U << CAN_F11FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F11FB1_FFDB7 CAN_F11FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F11FB1_FFDB8_Pos (8U) +#define CAN_F11FB1_FFDB8_Msk (0x1U << CAN_F11FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F11FB1_FFDB8 CAN_F11FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F11FB1_FFDB9_Pos (9U) +#define CAN_F11FB1_FFDB9_Msk (0x1U << CAN_F11FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F11FB1_FFDB9 CAN_F11FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F11FB1_FFDB10_Pos (10U) +#define CAN_F11FB1_FFDB10_Msk (0x1U << CAN_F11FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F11FB1_FFDB10 CAN_F11FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F11FB1_FFDB11_Pos (11U) +#define CAN_F11FB1_FFDB11_Msk (0x1U << CAN_F11FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F11FB1_FFDB11 CAN_F11FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F11FB1_FFDB12_Pos (12U) +#define CAN_F11FB1_FFDB12_Msk (0x1U << CAN_F11FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F11FB1_FFDB12 CAN_F11FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F11FB1_FFDB13_Pos (13U) +#define CAN_F11FB1_FFDB13_Msk (0x1U << CAN_F11FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F11FB1_FFDB13 CAN_F11FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F11FB1_FFDB14_Pos (14U) +#define CAN_F11FB1_FFDB14_Msk (0x1U << CAN_F11FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F11FB1_FFDB14 CAN_F11FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F11FB1_FFDB15_Pos (15U) +#define CAN_F11FB1_FFDB15_Msk (0x1U << CAN_F11FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F11FB1_FFDB15 CAN_F11FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F11FB1_FFDB16_Pos (16U) +#define CAN_F11FB1_FFDB16_Msk (0x1U << CAN_F11FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F11FB1_FFDB16 CAN_F11FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F11FB1_FFDB17_Pos (17U) +#define CAN_F11FB1_FFDB17_Msk (0x1U << CAN_F11FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F11FB1_FFDB17 CAN_F11FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F11FB1_FFDB18_Pos (18U) +#define CAN_F11FB1_FFDB18_Msk (0x1U << CAN_F11FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F11FB1_FFDB18 CAN_F11FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F11FB1_FFDB19_Pos (19U) +#define CAN_F11FB1_FFDB19_Msk (0x1U << CAN_F11FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F11FB1_FFDB19 CAN_F11FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F11FB1_FFDB20_Pos (20U) +#define CAN_F11FB1_FFDB20_Msk (0x1U << CAN_F11FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F11FB1_FFDB20 CAN_F11FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F11FB1_FFDB21_Pos (21U) +#define CAN_F11FB1_FFDB21_Msk (0x1U << CAN_F11FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F11FB1_FFDB21 CAN_F11FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F11FB1_FFDB22_Pos (22U) +#define CAN_F11FB1_FFDB22_Msk (0x1U << CAN_F11FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F11FB1_FFDB22 CAN_F11FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F11FB1_FFDB23_Pos (23U) +#define CAN_F11FB1_FFDB23_Msk (0x1U << CAN_F11FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F11FB1_FFDB23 CAN_F11FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F11FB1_FFDB24_Pos (24U) +#define CAN_F11FB1_FFDB24_Msk (0x1U << CAN_F11FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F11FB1_FFDB24 CAN_F11FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F11FB1_FFDB25_Pos (25U) +#define CAN_F11FB1_FFDB25_Msk (0x1U << CAN_F11FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F11FB1_FFDB25 CAN_F11FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F11FB1_FFDB26_Pos (26U) +#define CAN_F11FB1_FFDB26_Msk (0x1U << CAN_F11FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F11FB1_FFDB26 CAN_F11FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F11FB1_FFDB27_Pos (27U) +#define CAN_F11FB1_FFDB27_Msk (0x1U << CAN_F11FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F11FB1_FFDB27 CAN_F11FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F11FB1_FFDB28_Pos (28U) +#define CAN_F11FB1_FFDB28_Msk (0x1U << CAN_F11FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F11FB1_FFDB28 CAN_F11FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F11FB1_FFDB29_Pos (29U) +#define CAN_F11FB1_FFDB29_Msk (0x1U << CAN_F11FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F11FB1_FFDB29 CAN_F11FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F11FB1_FFDB30_Pos (30U) +#define CAN_F11FB1_FFDB30_Msk (0x1U << CAN_F11FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F11FB1_FFDB30 CAN_F11FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F11FB1_FFDB31_Pos (31U) +#define CAN_F11FB1_FFDB31_Msk (0x1U << CAN_F11FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F11FB1_FFDB31 CAN_F11FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F12FB1 register ******************/ +#define CAN_F12FB1_FFDB0_Pos (0U) +#define CAN_F12FB1_FFDB0_Msk (0x1U << CAN_F12FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F12FB1_FFDB0 CAN_F12FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F12FB1_FFDB1_Pos (1U) +#define CAN_F12FB1_FFDB1_Msk (0x1U << CAN_F12FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F12FB1_FFDB1 CAN_F12FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F12FB1_FFDB2_Pos (2U) +#define CAN_F12FB1_FFDB2_Msk (0x1U << CAN_F12FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F12FB1_FFDB2 CAN_F12FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F12FB1_FFDB3_Pos (3U) +#define CAN_F12FB1_FFDB3_Msk (0x1U << CAN_F12FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F12FB1_FFDB3 CAN_F12FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F12FB1_FFDB4_Pos (4U) +#define CAN_F12FB1_FFDB4_Msk (0x1U << CAN_F12FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F12FB1_FFDB4 CAN_F12FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F12FB1_FFDB5_Pos (5U) +#define CAN_F12FB1_FFDB5_Msk (0x1U << CAN_F12FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F12FB1_FFDB5 CAN_F12FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F12FB1_FFDB6_Pos (6U) +#define CAN_F12FB1_FFDB6_Msk (0x1U << CAN_F12FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F12FB1_FFDB6 CAN_F12FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F12FB1_FFDB7_Pos (7U) +#define CAN_F12FB1_FFDB7_Msk (0x1U << CAN_F12FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F12FB1_FFDB7 CAN_F12FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F12FB1_FFDB8_Pos (8U) +#define CAN_F12FB1_FFDB8_Msk (0x1U << CAN_F12FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F12FB1_FFDB8 CAN_F12FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F12FB1_FFDB9_Pos (9U) +#define CAN_F12FB1_FFDB9_Msk (0x1U << CAN_F12FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F12FB1_FFDB9 CAN_F12FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F12FB1_FFDB10_Pos (10U) +#define CAN_F12FB1_FFDB10_Msk (0x1U << CAN_F12FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F12FB1_FFDB10 CAN_F12FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F12FB1_FFDB11_Pos (11U) +#define CAN_F12FB1_FFDB11_Msk (0x1U << CAN_F12FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F12FB1_FFDB11 CAN_F12FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F12FB1_FFDB12_Pos (12U) +#define CAN_F12FB1_FFDB12_Msk (0x1U << CAN_F12FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F12FB1_FFDB12 CAN_F12FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F12FB1_FFDB13_Pos (13U) +#define CAN_F12FB1_FFDB13_Msk (0x1U << CAN_F12FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F12FB1_FFDB13 CAN_F12FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F12FB1_FFDB14_Pos (14U) +#define CAN_F12FB1_FFDB14_Msk (0x1U << CAN_F12FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F12FB1_FFDB14 CAN_F12FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F12FB1_FFDB15_Pos (15U) +#define CAN_F12FB1_FFDB15_Msk (0x1U << CAN_F12FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F12FB1_FFDB15 CAN_F12FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F12FB1_FFDB16_Pos (16U) +#define CAN_F12FB1_FFDB16_Msk (0x1U << CAN_F12FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F12FB1_FFDB16 CAN_F12FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F12FB1_FFDB17_Pos (17U) +#define CAN_F12FB1_FFDB17_Msk (0x1U << CAN_F12FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F12FB1_FFDB17 CAN_F12FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F12FB1_FFDB18_Pos (18U) +#define CAN_F12FB1_FFDB18_Msk (0x1U << CAN_F12FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F12FB1_FFDB18 CAN_F12FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F12FB1_FFDB19_Pos (19U) +#define CAN_F12FB1_FFDB19_Msk (0x1U << CAN_F12FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F12FB1_FFDB19 CAN_F12FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F12FB1_FFDB20_Pos (20U) +#define CAN_F12FB1_FFDB20_Msk (0x1U << CAN_F12FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F12FB1_FFDB20 CAN_F12FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F12FB1_FFDB21_Pos (21U) +#define CAN_F12FB1_FFDB21_Msk (0x1U << CAN_F12FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F12FB1_FFDB21 CAN_F12FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F12FB1_FFDB22_Pos (22U) +#define CAN_F12FB1_FFDB22_Msk (0x1U << CAN_F12FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F12FB1_FFDB22 CAN_F12FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F12FB1_FFDB23_Pos (23U) +#define CAN_F12FB1_FFDB23_Msk (0x1U << CAN_F12FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F12FB1_FFDB23 CAN_F12FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F12FB1_FFDB24_Pos (24U) +#define CAN_F12FB1_FFDB24_Msk (0x1U << CAN_F12FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F12FB1_FFDB24 CAN_F12FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F12FB1_FFDB25_Pos (25U) +#define CAN_F12FB1_FFDB25_Msk (0x1U << CAN_F12FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F12FB1_FFDB25 CAN_F12FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F12FB1_FFDB26_Pos (26U) +#define CAN_F12FB1_FFDB26_Msk (0x1U << CAN_F12FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F12FB1_FFDB26 CAN_F12FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F12FB1_FFDB27_Pos (27U) +#define CAN_F12FB1_FFDB27_Msk (0x1U << CAN_F12FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F12FB1_FFDB27 CAN_F12FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F12FB1_FFDB28_Pos (28U) +#define CAN_F12FB1_FFDB28_Msk (0x1U << CAN_F12FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F12FB1_FFDB28 CAN_F12FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F12FB1_FFDB29_Pos (29U) +#define CAN_F12FB1_FFDB29_Msk (0x1U << CAN_F12FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F12FB1_FFDB29 CAN_F12FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F12FB1_FFDB30_Pos (30U) +#define CAN_F12FB1_FFDB30_Msk (0x1U << CAN_F12FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F12FB1_FFDB30 CAN_F12FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F12FB1_FFDB31_Pos (31U) +#define CAN_F12FB1_FFDB31_Msk (0x1U << CAN_F12FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F12FB1_FFDB31 CAN_F12FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F13FB1 register ******************/ +#define CAN_F13FB1_FFDB0_Pos (0U) +#define CAN_F13FB1_FFDB0_Msk (0x1U << CAN_F13FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F13FB1_FFDB0 CAN_F13FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F13FB1_FFDB1_Pos (1U) +#define CAN_F13FB1_FFDB1_Msk (0x1U << CAN_F13FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F13FB1_FFDB1 CAN_F13FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F13FB1_FFDB2_Pos (2U) +#define CAN_F13FB1_FFDB2_Msk (0x1U << CAN_F13FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F13FB1_FFDB2 CAN_F13FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F13FB1_FFDB3_Pos (3U) +#define CAN_F13FB1_FFDB3_Msk (0x1U << CAN_F13FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F13FB1_FFDB3 CAN_F13FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F13FB1_FFDB4_Pos (4U) +#define CAN_F13FB1_FFDB4_Msk (0x1U << CAN_F13FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F13FB1_FFDB4 CAN_F13FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F13FB1_FFDB5_Pos (5U) +#define CAN_F13FB1_FFDB5_Msk (0x1U << CAN_F13FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F13FB1_FFDB5 CAN_F13FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F13FB1_FFDB6_Pos (6U) +#define CAN_F13FB1_FFDB6_Msk (0x1U << CAN_F13FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F13FB1_FFDB6 CAN_F13FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F13FB1_FFDB7_Pos (7U) +#define CAN_F13FB1_FFDB7_Msk (0x1U << CAN_F13FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F13FB1_FFDB7 CAN_F13FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F13FB1_FFDB8_Pos (8U) +#define CAN_F13FB1_FFDB8_Msk (0x1U << CAN_F13FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F13FB1_FFDB8 CAN_F13FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F13FB1_FFDB9_Pos (9U) +#define CAN_F13FB1_FFDB9_Msk (0x1U << CAN_F13FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F13FB1_FFDB9 CAN_F13FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F13FB1_FFDB10_Pos (10U) +#define CAN_F13FB1_FFDB10_Msk (0x1U << CAN_F13FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F13FB1_FFDB10 CAN_F13FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F13FB1_FFDB11_Pos (11U) +#define CAN_F13FB1_FFDB11_Msk (0x1U << CAN_F13FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F13FB1_FFDB11 CAN_F13FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F13FB1_FFDB12_Pos (12U) +#define CAN_F13FB1_FFDB12_Msk (0x1U << CAN_F13FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F13FB1_FFDB12 CAN_F13FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F13FB1_FFDB13_Pos (13U) +#define CAN_F13FB1_FFDB13_Msk (0x1U << CAN_F13FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F13FB1_FFDB13 CAN_F13FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F13FB1_FFDB14_Pos (14U) +#define CAN_F13FB1_FFDB14_Msk (0x1U << CAN_F13FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F13FB1_FFDB14 CAN_F13FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F13FB1_FFDB15_Pos (15U) +#define CAN_F13FB1_FFDB15_Msk (0x1U << CAN_F13FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F13FB1_FFDB15 CAN_F13FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F13FB1_FFDB16_Pos (16U) +#define CAN_F13FB1_FFDB16_Msk (0x1U << CAN_F13FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F13FB1_FFDB16 CAN_F13FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F13FB1_FFDB17_Pos (17U) +#define CAN_F13FB1_FFDB17_Msk (0x1U << CAN_F13FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F13FB1_FFDB17 CAN_F13FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F13FB1_FFDB18_Pos (18U) +#define CAN_F13FB1_FFDB18_Msk (0x1U << CAN_F13FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F13FB1_FFDB18 CAN_F13FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F13FB1_FFDB19_Pos (19U) +#define CAN_F13FB1_FFDB19_Msk (0x1U << CAN_F13FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F13FB1_FFDB19 CAN_F13FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F13FB1_FFDB20_Pos (20U) +#define CAN_F13FB1_FFDB20_Msk (0x1U << CAN_F13FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F13FB1_FFDB20 CAN_F13FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F13FB1_FFDB21_Pos (21U) +#define CAN_F13FB1_FFDB21_Msk (0x1U << CAN_F13FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F13FB1_FFDB21 CAN_F13FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F13FB1_FFDB22_Pos (22U) +#define CAN_F13FB1_FFDB22_Msk (0x1U << CAN_F13FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F13FB1_FFDB22 CAN_F13FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F13FB1_FFDB23_Pos (23U) +#define CAN_F13FB1_FFDB23_Msk (0x1U << CAN_F13FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F13FB1_FFDB23 CAN_F13FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F13FB1_FFDB24_Pos (24U) +#define CAN_F13FB1_FFDB24_Msk (0x1U << CAN_F13FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F13FB1_FFDB24 CAN_F13FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F13FB1_FFDB25_Pos (25U) +#define CAN_F13FB1_FFDB25_Msk (0x1U << CAN_F13FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F13FB1_FFDB25 CAN_F13FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F13FB1_FFDB26_Pos (26U) +#define CAN_F13FB1_FFDB26_Msk (0x1U << CAN_F13FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F13FB1_FFDB26 CAN_F13FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F13FB1_FFDB27_Pos (27U) +#define CAN_F13FB1_FFDB27_Msk (0x1U << CAN_F13FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F13FB1_FFDB27 CAN_F13FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F13FB1_FFDB28_Pos (28U) +#define CAN_F13FB1_FFDB28_Msk (0x1U << CAN_F13FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F13FB1_FFDB28 CAN_F13FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F13FB1_FFDB29_Pos (29U) +#define CAN_F13FB1_FFDB29_Msk (0x1U << CAN_F13FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F13FB1_FFDB29 CAN_F13FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F13FB1_FFDB30_Pos (30U) +#define CAN_F13FB1_FFDB30_Msk (0x1U << CAN_F13FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F13FB1_FFDB30 CAN_F13FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F13FB1_FFDB31_Pos (31U) +#define CAN_F13FB1_FFDB31_Msk (0x1U << CAN_F13FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F13FB1_FFDB31 CAN_F13FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F0FB2 register *******************/ +#define CAN_F0FB2_FFDB0_Pos (0U) +#define CAN_F0FB2_FFDB0_Msk (0x1U << CAN_F0FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F0FB2_FFDB0 CAN_F0FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F0FB2_FFDB1_Pos (1U) +#define CAN_F0FB2_FFDB1_Msk (0x1U << CAN_F0FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F0FB2_FFDB1 CAN_F0FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F0FB2_FFDB2_Pos (2U) +#define CAN_F0FB2_FFDB2_Msk (0x1U << CAN_F0FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F0FB2_FFDB2 CAN_F0FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F0FB2_FFDB3_Pos (3U) +#define CAN_F0FB2_FFDB3_Msk (0x1U << CAN_F0FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F0FB2_FFDB3 CAN_F0FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F0FB2_FFDB4_Pos (4U) +#define CAN_F0FB2_FFDB4_Msk (0x1U << CAN_F0FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F0FB2_FFDB4 CAN_F0FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F0FB2_FFDB5_Pos (5U) +#define CAN_F0FB2_FFDB5_Msk (0x1U << CAN_F0FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F0FB2_FFDB5 CAN_F0FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F0FB2_FFDB6_Pos (6U) +#define CAN_F0FB2_FFDB6_Msk (0x1U << CAN_F0FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F0FB2_FFDB6 CAN_F0FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F0FB2_FFDB7_Pos (7U) +#define CAN_F0FB2_FFDB7_Msk (0x1U << CAN_F0FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F0FB2_FFDB7 CAN_F0FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F0FB2_FFDB8_Pos (8U) +#define CAN_F0FB2_FFDB8_Msk (0x1U << CAN_F0FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F0FB2_FFDB8 CAN_F0FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F0FB2_FFDB9_Pos (9U) +#define CAN_F0FB2_FFDB9_Msk (0x1U << CAN_F0FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F0FB2_FFDB9 CAN_F0FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F0FB2_FFDB10_Pos (10U) +#define CAN_F0FB2_FFDB10_Msk (0x1U << CAN_F0FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F0FB2_FFDB10 CAN_F0FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F0FB2_FFDB11_Pos (11U) +#define CAN_F0FB2_FFDB11_Msk (0x1U << CAN_F0FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F0FB2_FFDB11 CAN_F0FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F0FB2_FFDB12_Pos (12U) +#define CAN_F0FB2_FFDB12_Msk (0x1U << CAN_F0FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F0FB2_FFDB12 CAN_F0FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F0FB2_FFDB13_Pos (13U) +#define CAN_F0FB2_FFDB13_Msk (0x1U << CAN_F0FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F0FB2_FFDB13 CAN_F0FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F0FB2_FFDB14_Pos (14U) +#define CAN_F0FB2_FFDB14_Msk (0x1U << CAN_F0FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F0FB2_FFDB14 CAN_F0FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F0FB2_FFDB15_Pos (15U) +#define CAN_F0FB2_FFDB15_Msk (0x1U << CAN_F0FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F0FB2_FFDB15 CAN_F0FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F0FB2_FFDB16_Pos (16U) +#define CAN_F0FB2_FFDB16_Msk (0x1U << CAN_F0FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F0FB2_FFDB16 CAN_F0FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F0FB2_FFDB17_Pos (17U) +#define CAN_F0FB2_FFDB17_Msk (0x1U << CAN_F0FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F0FB2_FFDB17 CAN_F0FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F0FB2_FFDB18_Pos (18U) +#define CAN_F0FB2_FFDB18_Msk (0x1U << CAN_F0FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F0FB2_FFDB18 CAN_F0FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F0FB2_FFDB19_Pos (19U) +#define CAN_F0FB2_FFDB19_Msk (0x1U << CAN_F0FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F0FB2_FFDB19 CAN_F0FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F0FB2_FFDB20_Pos (20U) +#define CAN_F0FB2_FFDB20_Msk (0x1U << CAN_F0FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F0FB2_FFDB20 CAN_F0FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F0FB2_FFDB21_Pos (21U) +#define CAN_F0FB2_FFDB21_Msk (0x1U << CAN_F0FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F0FB2_FFDB21 CAN_F0FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F0FB2_FFDB22_Pos (22U) +#define CAN_F0FB2_FFDB22_Msk (0x1U << CAN_F0FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F0FB2_FFDB22 CAN_F0FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F0FB2_FFDB23_Pos (23U) +#define CAN_F0FB2_FFDB23_Msk (0x1U << CAN_F0FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F0FB2_FFDB23 CAN_F0FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F0FB2_FFDB24_Pos (24U) +#define CAN_F0FB2_FFDB24_Msk (0x1U << CAN_F0FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F0FB2_FFDB24 CAN_F0FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F0FB2_FFDB25_Pos (25U) +#define CAN_F0FB2_FFDB25_Msk (0x1U << CAN_F0FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F0FB2_FFDB25 CAN_F0FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F0FB2_FFDB26_Pos (26U) +#define CAN_F0FB2_FFDB26_Msk (0x1U << CAN_F0FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F0FB2_FFDB26 CAN_F0FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F0FB2_FFDB27_Pos (27U) +#define CAN_F0FB2_FFDB27_Msk (0x1U << CAN_F0FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F0FB2_FFDB27 CAN_F0FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F0FB2_FFDB28_Pos (28U) +#define CAN_F0FB2_FFDB28_Msk (0x1U << CAN_F0FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F0FB2_FFDB28 CAN_F0FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F0FB2_FFDB29_Pos (29U) +#define CAN_F0FB2_FFDB29_Msk (0x1U << CAN_F0FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F0FB2_FFDB29 CAN_F0FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F0FB2_FFDB30_Pos (30U) +#define CAN_F0FB2_FFDB30_Msk (0x1U << CAN_F0FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F0FB2_FFDB30 CAN_F0FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F0FB2_FFDB31_Pos (31U) +#define CAN_F0FB2_FFDB31_Msk (0x1U << CAN_F0FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F0FB2_FFDB31 CAN_F0FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F1FB2 register *******************/ +#define CAN_F1FB2_FFDB0_Pos (0U) +#define CAN_F1FB2_FFDB0_Msk (0x1U << CAN_F1FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F1FB2_FFDB0 CAN_F1FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F1FB2_FFDB1_Pos (1U) +#define CAN_F1FB2_FFDB1_Msk (0x1U << CAN_F1FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F1FB2_FFDB1 CAN_F1FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F1FB2_FFDB2_Pos (2U) +#define CAN_F1FB2_FFDB2_Msk (0x1U << CAN_F1FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F1FB2_FFDB2 CAN_F1FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F1FB2_FFDB3_Pos (3U) +#define CAN_F1FB2_FFDB3_Msk (0x1U << CAN_F1FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F1FB2_FFDB3 CAN_F1FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F1FB2_FFDB4_Pos (4U) +#define CAN_F1FB2_FFDB4_Msk (0x1U << CAN_F1FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F1FB2_FFDB4 CAN_F1FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F1FB2_FFDB5_Pos (5U) +#define CAN_F1FB2_FFDB5_Msk (0x1U << CAN_F1FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F1FB2_FFDB5 CAN_F1FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F1FB2_FFDB6_Pos (6U) +#define CAN_F1FB2_FFDB6_Msk (0x1U << CAN_F1FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F1FB2_FFDB6 CAN_F1FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F1FB2_FFDB7_Pos (7U) +#define CAN_F1FB2_FFDB7_Msk (0x1U << CAN_F1FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F1FB2_FFDB7 CAN_F1FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F1FB2_FFDB8_Pos (8U) +#define CAN_F1FB2_FFDB8_Msk (0x1U << CAN_F1FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F1FB2_FFDB8 CAN_F1FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F1FB2_FFDB9_Pos (9U) +#define CAN_F1FB2_FFDB9_Msk (0x1U << CAN_F1FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F1FB2_FFDB9 CAN_F1FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F1FB2_FFDB10_Pos (10U) +#define CAN_F1FB2_FFDB10_Msk (0x1U << CAN_F1FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F1FB2_FFDB10 CAN_F1FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F1FB2_FFDB11_Pos (11U) +#define CAN_F1FB2_FFDB11_Msk (0x1U << CAN_F1FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F1FB2_FFDB11 CAN_F1FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F1FB2_FFDB12_Pos (12U) +#define CAN_F1FB2_FFDB12_Msk (0x1U << CAN_F1FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F1FB2_FFDB12 CAN_F1FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F1FB2_FFDB13_Pos (13U) +#define CAN_F1FB2_FFDB13_Msk (0x1U << CAN_F1FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F1FB2_FFDB13 CAN_F1FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F1FB2_FFDB14_Pos (14U) +#define CAN_F1FB2_FFDB14_Msk (0x1U << CAN_F1FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F1FB2_FFDB14 CAN_F1FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F1FB2_FFDB15_Pos (15U) +#define CAN_F1FB2_FFDB15_Msk (0x1U << CAN_F1FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F1FB2_FFDB15 CAN_F1FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F1FB2_FFDB16_Pos (16U) +#define CAN_F1FB2_FFDB16_Msk (0x1U << CAN_F1FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F1FB2_FFDB16 CAN_F1FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F1FB2_FFDB17_Pos (17U) +#define CAN_F1FB2_FFDB17_Msk (0x1U << CAN_F1FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F1FB2_FFDB17 CAN_F1FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F1FB2_FFDB18_Pos (18U) +#define CAN_F1FB2_FFDB18_Msk (0x1U << CAN_F1FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F1FB2_FFDB18 CAN_F1FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F1FB2_FFDB19_Pos (19U) +#define CAN_F1FB2_FFDB19_Msk (0x1U << CAN_F1FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F1FB2_FFDB19 CAN_F1FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F1FB2_FFDB20_Pos (20U) +#define CAN_F1FB2_FFDB20_Msk (0x1U << CAN_F1FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F1FB2_FFDB20 CAN_F1FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F1FB2_FFDB21_Pos (21U) +#define CAN_F1FB2_FFDB21_Msk (0x1U << CAN_F1FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F1FB2_FFDB21 CAN_F1FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F1FB2_FFDB22_Pos (22U) +#define CAN_F1FB2_FFDB22_Msk (0x1U << CAN_F1FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F1FB2_FFDB22 CAN_F1FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F1FB2_FFDB23_Pos (23U) +#define CAN_F1FB2_FFDB23_Msk (0x1U << CAN_F1FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F1FB2_FFDB23 CAN_F1FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F1FB2_FFDB24_Pos (24U) +#define CAN_F1FB2_FFDB24_Msk (0x1U << CAN_F1FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F1FB2_FFDB24 CAN_F1FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F1FB2_FFDB25_Pos (25U) +#define CAN_F1FB2_FFDB25_Msk (0x1U << CAN_F1FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F1FB2_FFDB25 CAN_F1FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F1FB2_FFDB26_Pos (26U) +#define CAN_F1FB2_FFDB26_Msk (0x1U << CAN_F1FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F1FB2_FFDB26 CAN_F1FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F1FB2_FFDB27_Pos (27U) +#define CAN_F1FB2_FFDB27_Msk (0x1U << CAN_F1FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F1FB2_FFDB27 CAN_F1FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F1FB2_FFDB28_Pos (28U) +#define CAN_F1FB2_FFDB28_Msk (0x1U << CAN_F1FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F1FB2_FFDB28 CAN_F1FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F1FB2_FFDB29_Pos (29U) +#define CAN_F1FB2_FFDB29_Msk (0x1U << CAN_F1FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F1FB2_FFDB29 CAN_F1FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F1FB2_FFDB30_Pos (30U) +#define CAN_F1FB2_FFDB30_Msk (0x1U << CAN_F1FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F1FB2_FFDB30 CAN_F1FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F1FB2_FFDB31_Pos (31U) +#define CAN_F1FB2_FFDB31_Msk (0x1U << CAN_F1FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F1FB2_FFDB31 CAN_F1FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F2FB2 register *******************/ +#define CAN_F2FB2_FFDB0_Pos (0U) +#define CAN_F2FB2_FFDB0_Msk (0x1U << CAN_F2FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F2FB2_FFDB0 CAN_F2FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F2FB2_FFDB1_Pos (1U) +#define CAN_F2FB2_FFDB1_Msk (0x1U << CAN_F2FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F2FB2_FFDB1 CAN_F2FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F2FB2_FFDB2_Pos (2U) +#define CAN_F2FB2_FFDB2_Msk (0x1U << CAN_F2FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F2FB2_FFDB2 CAN_F2FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F2FB2_FFDB3_Pos (3U) +#define CAN_F2FB2_FFDB3_Msk (0x1U << CAN_F2FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F2FB2_FFDB3 CAN_F2FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F2FB2_FFDB4_Pos (4U) +#define CAN_F2FB2_FFDB4_Msk (0x1U << CAN_F2FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F2FB2_FFDB4 CAN_F2FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F2FB2_FFDB5_Pos (5U) +#define CAN_F2FB2_FFDB5_Msk (0x1U << CAN_F2FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F2FB2_FFDB5 CAN_F2FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F2FB2_FFDB6_Pos (6U) +#define CAN_F2FB2_FFDB6_Msk (0x1U << CAN_F2FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F2FB2_FFDB6 CAN_F2FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F2FB2_FFDB7_Pos (7U) +#define CAN_F2FB2_FFDB7_Msk (0x1U << CAN_F2FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F2FB2_FFDB7 CAN_F2FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F2FB2_FFDB8_Pos (8U) +#define CAN_F2FB2_FFDB8_Msk (0x1U << CAN_F2FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F2FB2_FFDB8 CAN_F2FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F2FB2_FFDB9_Pos (9U) +#define CAN_F2FB2_FFDB9_Msk (0x1U << CAN_F2FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F2FB2_FFDB9 CAN_F2FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F2FB2_FFDB10_Pos (10U) +#define CAN_F2FB2_FFDB10_Msk (0x1U << CAN_F2FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F2FB2_FFDB10 CAN_F2FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F2FB2_FFDB11_Pos (11U) +#define CAN_F2FB2_FFDB11_Msk (0x1U << CAN_F2FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F2FB2_FFDB11 CAN_F2FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F2FB2_FFDB12_Pos (12U) +#define CAN_F2FB2_FFDB12_Msk (0x1U << CAN_F2FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F2FB2_FFDB12 CAN_F2FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F2FB2_FFDB13_Pos (13U) +#define CAN_F2FB2_FFDB13_Msk (0x1U << CAN_F2FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F2FB2_FFDB13 CAN_F2FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F2FB2_FFDB14_Pos (14U) +#define CAN_F2FB2_FFDB14_Msk (0x1U << CAN_F2FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F2FB2_FFDB14 CAN_F2FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F2FB2_FFDB15_Pos (15U) +#define CAN_F2FB2_FFDB15_Msk (0x1U << CAN_F2FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F2FB2_FFDB15 CAN_F2FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F2FB2_FFDB16_Pos (16U) +#define CAN_F2FB2_FFDB16_Msk (0x1U << CAN_F2FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F2FB2_FFDB16 CAN_F2FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F2FB2_FFDB17_Pos (17U) +#define CAN_F2FB2_FFDB17_Msk (0x1U << CAN_F2FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F2FB2_FFDB17 CAN_F2FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F2FB2_FFDB18_Pos (18U) +#define CAN_F2FB2_FFDB18_Msk (0x1U << CAN_F2FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F2FB2_FFDB18 CAN_F2FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F2FB2_FFDB19_Pos (19U) +#define CAN_F2FB2_FFDB19_Msk (0x1U << CAN_F2FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F2FB2_FFDB19 CAN_F2FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F2FB2_FFDB20_Pos (20U) +#define CAN_F2FB2_FFDB20_Msk (0x1U << CAN_F2FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F2FB2_FFDB20 CAN_F2FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F2FB2_FFDB21_Pos (21U) +#define CAN_F2FB2_FFDB21_Msk (0x1U << CAN_F2FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F2FB2_FFDB21 CAN_F2FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F2FB2_FFDB22_Pos (22U) +#define CAN_F2FB2_FFDB22_Msk (0x1U << CAN_F2FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F2FB2_FFDB22 CAN_F2FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F2FB2_FFDB23_Pos (23U) +#define CAN_F2FB2_FFDB23_Msk (0x1U << CAN_F2FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F2FB2_FFDB23 CAN_F2FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F2FB2_FFDB24_Pos (24U) +#define CAN_F2FB2_FFDB24_Msk (0x1U << CAN_F2FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F2FB2_FFDB24 CAN_F2FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F2FB2_FFDB25_Pos (25U) +#define CAN_F2FB2_FFDB25_Msk (0x1U << CAN_F2FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F2FB2_FFDB25 CAN_F2FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F2FB2_FFDB26_Pos (26U) +#define CAN_F2FB2_FFDB26_Msk (0x1U << CAN_F2FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F2FB2_FFDB26 CAN_F2FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F2FB2_FFDB27_Pos (27U) +#define CAN_F2FB2_FFDB27_Msk (0x1U << CAN_F2FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F2FB2_FFDB27 CAN_F2FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F2FB2_FFDB28_Pos (28U) +#define CAN_F2FB2_FFDB28_Msk (0x1U << CAN_F2FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F2FB2_FFDB28 CAN_F2FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F2FB2_FFDB29_Pos (29U) +#define CAN_F2FB2_FFDB29_Msk (0x1U << CAN_F2FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F2FB2_FFDB29 CAN_F2FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F2FB2_FFDB30_Pos (30U) +#define CAN_F2FB2_FFDB30_Msk (0x1U << CAN_F2FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F2FB2_FFDB30 CAN_F2FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F2FB2_FFDB31_Pos (31U) +#define CAN_F2FB2_FFDB31_Msk (0x1U << CAN_F2FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F2FB2_FFDB31 CAN_F2FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F3FB2 register *******************/ +#define CAN_F3FB2_FFDB0_Pos (0U) +#define CAN_F3FB2_FFDB0_Msk (0x1U << CAN_F3FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F3FB2_FFDB0 CAN_F3FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F3FB2_FFDB1_Pos (1U) +#define CAN_F3FB2_FFDB1_Msk (0x1U << CAN_F3FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F3FB2_FFDB1 CAN_F3FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F3FB2_FFDB2_Pos (2U) +#define CAN_F3FB2_FFDB2_Msk (0x1U << CAN_F3FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F3FB2_FFDB2 CAN_F3FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F3FB2_FFDB3_Pos (3U) +#define CAN_F3FB2_FFDB3_Msk (0x1U << CAN_F3FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F3FB2_FFDB3 CAN_F3FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F3FB2_FFDB4_Pos (4U) +#define CAN_F3FB2_FFDB4_Msk (0x1U << CAN_F3FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F3FB2_FFDB4 CAN_F3FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F3FB2_FFDB5_Pos (5U) +#define CAN_F3FB2_FFDB5_Msk (0x1U << CAN_F3FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F3FB2_FFDB5 CAN_F3FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F3FB2_FFDB6_Pos (6U) +#define CAN_F3FB2_FFDB6_Msk (0x1U << CAN_F3FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F3FB2_FFDB6 CAN_F3FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F3FB2_FFDB7_Pos (7U) +#define CAN_F3FB2_FFDB7_Msk (0x1U << CAN_F3FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F3FB2_FFDB7 CAN_F3FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F3FB2_FFDB8_Pos (8U) +#define CAN_F3FB2_FFDB8_Msk (0x1U << CAN_F3FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F3FB2_FFDB8 CAN_F3FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F3FB2_FFDB9_Pos (9U) +#define CAN_F3FB2_FFDB9_Msk (0x1U << CAN_F3FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F3FB2_FFDB9 CAN_F3FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F3FB2_FFDB10_Pos (10U) +#define CAN_F3FB2_FFDB10_Msk (0x1U << CAN_F3FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F3FB2_FFDB10 CAN_F3FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F3FB2_FFDB11_Pos (11U) +#define CAN_F3FB2_FFDB11_Msk (0x1U << CAN_F3FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F3FB2_FFDB11 CAN_F3FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F3FB2_FFDB12_Pos (12U) +#define CAN_F3FB2_FFDB12_Msk (0x1U << CAN_F3FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F3FB2_FFDB12 CAN_F3FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F3FB2_FFDB13_Pos (13U) +#define CAN_F3FB2_FFDB13_Msk (0x1U << CAN_F3FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F3FB2_FFDB13 CAN_F3FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F3FB2_FFDB14_Pos (14U) +#define CAN_F3FB2_FFDB14_Msk (0x1U << CAN_F3FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F3FB2_FFDB14 CAN_F3FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F3FB2_FFDB15_Pos (15U) +#define CAN_F3FB2_FFDB15_Msk (0x1U << CAN_F3FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F3FB2_FFDB15 CAN_F3FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F3FB2_FFDB16_Pos (16U) +#define CAN_F3FB2_FFDB16_Msk (0x1U << CAN_F3FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F3FB2_FFDB16 CAN_F3FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F3FB2_FFDB17_Pos (17U) +#define CAN_F3FB2_FFDB17_Msk (0x1U << CAN_F3FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F3FB2_FFDB17 CAN_F3FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F3FB2_FFDB18_Pos (18U) +#define CAN_F3FB2_FFDB18_Msk (0x1U << CAN_F3FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F3FB2_FFDB18 CAN_F3FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F3FB2_FFDB19_Pos (19U) +#define CAN_F3FB2_FFDB19_Msk (0x1U << CAN_F3FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F3FB2_FFDB19 CAN_F3FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F3FB2_FFDB20_Pos (20U) +#define CAN_F3FB2_FFDB20_Msk (0x1U << CAN_F3FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F3FB2_FFDB20 CAN_F3FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F3FB2_FFDB21_Pos (21U) +#define CAN_F3FB2_FFDB21_Msk (0x1U << CAN_F3FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F3FB2_FFDB21 CAN_F3FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F3FB2_FFDB22_Pos (22U) +#define CAN_F3FB2_FFDB22_Msk (0x1U << CAN_F3FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F3FB2_FFDB22 CAN_F3FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F3FB2_FFDB23_Pos (23U) +#define CAN_F3FB2_FFDB23_Msk (0x1U << CAN_F3FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F3FB2_FFDB23 CAN_F3FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F3FB2_FFDB24_Pos (24U) +#define CAN_F3FB2_FFDB24_Msk (0x1U << CAN_F3FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F3FB2_FFDB24 CAN_F3FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F3FB2_FFDB25_Pos (25U) +#define CAN_F3FB2_FFDB25_Msk (0x1U << CAN_F3FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F3FB2_FFDB25 CAN_F3FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F3FB2_FFDB26_Pos (26U) +#define CAN_F3FB2_FFDB26_Msk (0x1U << CAN_F3FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F3FB2_FFDB26 CAN_F3FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F3FB2_FFDB27_Pos (27U) +#define CAN_F3FB2_FFDB27_Msk (0x1U << CAN_F3FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F3FB2_FFDB27 CAN_F3FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F3FB2_FFDB28_Pos (28U) +#define CAN_F3FB2_FFDB28_Msk (0x1U << CAN_F3FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F3FB2_FFDB28 CAN_F3FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F3FB2_FFDB29_Pos (29U) +#define CAN_F3FB2_FFDB29_Msk (0x1U << CAN_F3FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F3FB2_FFDB29 CAN_F3FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F3FB2_FFDB30_Pos (30U) +#define CAN_F3FB2_FFDB30_Msk (0x1U << CAN_F3FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F3FB2_FFDB30 CAN_F3FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F3FB2_FFDB31_Pos (31U) +#define CAN_F3FB2_FFDB31_Msk (0x1U << CAN_F3FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F3FB2_FFDB31 CAN_F3FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F4FB2 register *******************/ +#define CAN_F4FB2_FFDB0_Pos (0U) +#define CAN_F4FB2_FFDB0_Msk (0x1U << CAN_F4FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F4FB2_FFDB0 CAN_F4FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F4FB2_FFDB1_Pos (1U) +#define CAN_F4FB2_FFDB1_Msk (0x1U << CAN_F4FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F4FB2_FFDB1 CAN_F4FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F4FB2_FFDB2_Pos (2U) +#define CAN_F4FB2_FFDB2_Msk (0x1U << CAN_F4FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F4FB2_FFDB2 CAN_F4FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F4FB2_FFDB3_Pos (3U) +#define CAN_F4FB2_FFDB3_Msk (0x1U << CAN_F4FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F4FB2_FFDB3 CAN_F4FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F4FB2_FFDB4_Pos (4U) +#define CAN_F4FB2_FFDB4_Msk (0x1U << CAN_F4FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F4FB2_FFDB4 CAN_F4FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F4FB2_FFDB5_Pos (5U) +#define CAN_F4FB2_FFDB5_Msk (0x1U << CAN_F4FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F4FB2_FFDB5 CAN_F4FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F4FB2_FFDB6_Pos (6U) +#define CAN_F4FB2_FFDB6_Msk (0x1U << CAN_F4FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F4FB2_FFDB6 CAN_F4FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F4FB2_FFDB7_Pos (7U) +#define CAN_F4FB2_FFDB7_Msk (0x1U << CAN_F4FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F4FB2_FFDB7 CAN_F4FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F4FB2_FFDB8_Pos (8U) +#define CAN_F4FB2_FFDB8_Msk (0x1U << CAN_F4FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F4FB2_FFDB8 CAN_F4FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F4FB2_FFDB9_Pos (9U) +#define CAN_F4FB2_FFDB9_Msk (0x1U << CAN_F4FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F4FB2_FFDB9 CAN_F4FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F4FB2_FFDB10_Pos (10U) +#define CAN_F4FB2_FFDB10_Msk (0x1U << CAN_F4FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F4FB2_FFDB10 CAN_F4FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F4FB2_FFDB11_Pos (11U) +#define CAN_F4FB2_FFDB11_Msk (0x1U << CAN_F4FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F4FB2_FFDB11 CAN_F4FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F4FB2_FFDB12_Pos (12U) +#define CAN_F4FB2_FFDB12_Msk (0x1U << CAN_F4FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F4FB2_FFDB12 CAN_F4FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F4FB2_FFDB13_Pos (13U) +#define CAN_F4FB2_FFDB13_Msk (0x1U << CAN_F4FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F4FB2_FFDB13 CAN_F4FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F4FB2_FFDB14_Pos (14U) +#define CAN_F4FB2_FFDB14_Msk (0x1U << CAN_F4FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F4FB2_FFDB14 CAN_F4FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F4FB2_FFDB15_Pos (15U) +#define CAN_F4FB2_FFDB15_Msk (0x1U << CAN_F4FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F4FB2_FFDB15 CAN_F4FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F4FB2_FFDB16_Pos (16U) +#define CAN_F4FB2_FFDB16_Msk (0x1U << CAN_F4FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F4FB2_FFDB16 CAN_F4FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F4FB2_FFDB17_Pos (17U) +#define CAN_F4FB2_FFDB17_Msk (0x1U << CAN_F4FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F4FB2_FFDB17 CAN_F4FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F4FB2_FFDB18_Pos (18U) +#define CAN_F4FB2_FFDB18_Msk (0x1U << CAN_F4FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F4FB2_FFDB18 CAN_F4FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F4FB2_FFDB19_Pos (19U) +#define CAN_F4FB2_FFDB19_Msk (0x1U << CAN_F4FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F4FB2_FFDB19 CAN_F4FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F4FB2_FFDB20_Pos (20U) +#define CAN_F4FB2_FFDB20_Msk (0x1U << CAN_F4FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F4FB2_FFDB20 CAN_F4FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F4FB2_FFDB21_Pos (21U) +#define CAN_F4FB2_FFDB21_Msk (0x1U << CAN_F4FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F4FB2_FFDB21 CAN_F4FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F4FB2_FFDB22_Pos (22U) +#define CAN_F4FB2_FFDB22_Msk (0x1U << CAN_F4FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F4FB2_FFDB22 CAN_F4FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F4FB2_FFDB23_Pos (23U) +#define CAN_F4FB2_FFDB23_Msk (0x1U << CAN_F4FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F4FB2_FFDB23 CAN_F4FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F4FB2_FFDB24_Pos (24U) +#define CAN_F4FB2_FFDB24_Msk (0x1U << CAN_F4FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F4FB2_FFDB24 CAN_F4FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F4FB2_FFDB25_Pos (25U) +#define CAN_F4FB2_FFDB25_Msk (0x1U << CAN_F4FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F4FB2_FFDB25 CAN_F4FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F4FB2_FFDB26_Pos (26U) +#define CAN_F4FB2_FFDB26_Msk (0x1U << CAN_F4FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F4FB2_FFDB26 CAN_F4FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F4FB2_FFDB27_Pos (27U) +#define CAN_F4FB2_FFDB27_Msk (0x1U << CAN_F4FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F4FB2_FFDB27 CAN_F4FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F4FB2_FFDB28_Pos (28U) +#define CAN_F4FB2_FFDB28_Msk (0x1U << CAN_F4FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F4FB2_FFDB28 CAN_F4FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F4FB2_FFDB29_Pos (29U) +#define CAN_F4FB2_FFDB29_Msk (0x1U << CAN_F4FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F4FB2_FFDB29 CAN_F4FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F4FB2_FFDB30_Pos (30U) +#define CAN_F4FB2_FFDB30_Msk (0x1U << CAN_F4FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F4FB2_FFDB30 CAN_F4FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F4FB2_FFDB31_Pos (31U) +#define CAN_F4FB2_FFDB31_Msk (0x1U << CAN_F4FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F4FB2_FFDB31 CAN_F4FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F5FB2 register *******************/ +#define CAN_F5FB2_FFDB0_Pos (0U) +#define CAN_F5FB2_FFDB0_Msk (0x1U << CAN_F5FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F5FB2_FFDB0 CAN_F5FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F5FB2_FFDB1_Pos (1U) +#define CAN_F5FB2_FFDB1_Msk (0x1U << CAN_F5FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F5FB2_FFDB1 CAN_F5FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F5FB2_FFDB2_Pos (2U) +#define CAN_F5FB2_FFDB2_Msk (0x1U << CAN_F5FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F5FB2_FFDB2 CAN_F5FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F5FB2_FFDB3_Pos (3U) +#define CAN_F5FB2_FFDB3_Msk (0x1U << CAN_F5FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F5FB2_FFDB3 CAN_F5FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F5FB2_FFDB4_Pos (4U) +#define CAN_F5FB2_FFDB4_Msk (0x1U << CAN_F5FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F5FB2_FFDB4 CAN_F5FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F5FB2_FFDB5_Pos (5U) +#define CAN_F5FB2_FFDB5_Msk (0x1U << CAN_F5FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F5FB2_FFDB5 CAN_F5FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F5FB2_FFDB6_Pos (6U) +#define CAN_F5FB2_FFDB6_Msk (0x1U << CAN_F5FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F5FB2_FFDB6 CAN_F5FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F5FB2_FFDB7_Pos (7U) +#define CAN_F5FB2_FFDB7_Msk (0x1U << CAN_F5FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F5FB2_FFDB7 CAN_F5FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F5FB2_FFDB8_Pos (8U) +#define CAN_F5FB2_FFDB8_Msk (0x1U << CAN_F5FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F5FB2_FFDB8 CAN_F5FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F5FB2_FFDB9_Pos (9U) +#define CAN_F5FB2_FFDB9_Msk (0x1U << CAN_F5FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F5FB2_FFDB9 CAN_F5FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F5FB2_FFDB10_Pos (10U) +#define CAN_F5FB2_FFDB10_Msk (0x1U << CAN_F5FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F5FB2_FFDB10 CAN_F5FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F5FB2_FFDB11_Pos (11U) +#define CAN_F5FB2_FFDB11_Msk (0x1U << CAN_F5FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F5FB2_FFDB11 CAN_F5FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F5FB2_FFDB12_Pos (12U) +#define CAN_F5FB2_FFDB12_Msk (0x1U << CAN_F5FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F5FB2_FFDB12 CAN_F5FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F5FB2_FFDB13_Pos (13U) +#define CAN_F5FB2_FFDB13_Msk (0x1U << CAN_F5FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F5FB2_FFDB13 CAN_F5FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F5FB2_FFDB14_Pos (14U) +#define CAN_F5FB2_FFDB14_Msk (0x1U << CAN_F5FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F5FB2_FFDB14 CAN_F5FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F5FB2_FFDB15_Pos (15U) +#define CAN_F5FB2_FFDB15_Msk (0x1U << CAN_F5FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F5FB2_FFDB15 CAN_F5FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F5FB2_FFDB16_Pos (16U) +#define CAN_F5FB2_FFDB16_Msk (0x1U << CAN_F5FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F5FB2_FFDB16 CAN_F5FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F5FB2_FFDB17_Pos (17U) +#define CAN_F5FB2_FFDB17_Msk (0x1U << CAN_F5FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F5FB2_FFDB17 CAN_F5FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F5FB2_FFDB18_Pos (18U) +#define CAN_F5FB2_FFDB18_Msk (0x1U << CAN_F5FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F5FB2_FFDB18 CAN_F5FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F5FB2_FFDB19_Pos (19U) +#define CAN_F5FB2_FFDB19_Msk (0x1U << CAN_F5FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F5FB2_FFDB19 CAN_F5FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F5FB2_FFDB20_Pos (20U) +#define CAN_F5FB2_FFDB20_Msk (0x1U << CAN_F5FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F5FB2_FFDB20 CAN_F5FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F5FB2_FFDB21_Pos (21U) +#define CAN_F5FB2_FFDB21_Msk (0x1U << CAN_F5FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F5FB2_FFDB21 CAN_F5FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F5FB2_FFDB22_Pos (22U) +#define CAN_F5FB2_FFDB22_Msk (0x1U << CAN_F5FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F5FB2_FFDB22 CAN_F5FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F5FB2_FFDB23_Pos (23U) +#define CAN_F5FB2_FFDB23_Msk (0x1U << CAN_F5FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F5FB2_FFDB23 CAN_F5FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F5FB2_FFDB24_Pos (24U) +#define CAN_F5FB2_FFDB24_Msk (0x1U << CAN_F5FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F5FB2_FFDB24 CAN_F5FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F5FB2_FFDB25_Pos (25U) +#define CAN_F5FB2_FFDB25_Msk (0x1U << CAN_F5FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F5FB2_FFDB25 CAN_F5FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F5FB2_FFDB26_Pos (26U) +#define CAN_F5FB2_FFDB26_Msk (0x1U << CAN_F5FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F5FB2_FFDB26 CAN_F5FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F5FB2_FFDB27_Pos (27U) +#define CAN_F5FB2_FFDB27_Msk (0x1U << CAN_F5FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F5FB2_FFDB27 CAN_F5FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F5FB2_FFDB28_Pos (28U) +#define CAN_F5FB2_FFDB28_Msk (0x1U << CAN_F5FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F5FB2_FFDB28 CAN_F5FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F5FB2_FFDB29_Pos (29U) +#define CAN_F5FB2_FFDB29_Msk (0x1U << CAN_F5FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F5FB2_FFDB29 CAN_F5FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F5FB2_FFDB30_Pos (30U) +#define CAN_F5FB2_FFDB30_Msk (0x1U << CAN_F5FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F5FB2_FFDB30 CAN_F5FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F5FB2_FFDB31_Pos (31U) +#define CAN_F5FB2_FFDB31_Msk (0x1U << CAN_F5FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F5FB2_FFDB31 CAN_F5FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F6FB2 register *******************/ +#define CAN_F6FB2_FFDB0_Pos (0U) +#define CAN_F6FB2_FFDB0_Msk (0x1U << CAN_F6FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F6FB2_FFDB0 CAN_F6FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F6FB2_FFDB1_Pos (1U) +#define CAN_F6FB2_FFDB1_Msk (0x1U << CAN_F6FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F6FB2_FFDB1 CAN_F6FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F6FB2_FFDB2_Pos (2U) +#define CAN_F6FB2_FFDB2_Msk (0x1U << CAN_F6FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F6FB2_FFDB2 CAN_F6FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F6FB2_FFDB3_Pos (3U) +#define CAN_F6FB2_FFDB3_Msk (0x1U << CAN_F6FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F6FB2_FFDB3 CAN_F6FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F6FB2_FFDB4_Pos (4U) +#define CAN_F6FB2_FFDB4_Msk (0x1U << CAN_F6FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F6FB2_FFDB4 CAN_F6FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F6FB2_FFDB5_Pos (5U) +#define CAN_F6FB2_FFDB5_Msk (0x1U << CAN_F6FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F6FB2_FFDB5 CAN_F6FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F6FB2_FFDB6_Pos (6U) +#define CAN_F6FB2_FFDB6_Msk (0x1U << CAN_F6FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F6FB2_FFDB6 CAN_F6FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F6FB2_FFDB7_Pos (7U) +#define CAN_F6FB2_FFDB7_Msk (0x1U << CAN_F6FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F6FB2_FFDB7 CAN_F6FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F6FB2_FFDB8_Pos (8U) +#define CAN_F6FB2_FFDB8_Msk (0x1U << CAN_F6FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F6FB2_FFDB8 CAN_F6FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F6FB2_FFDB9_Pos (9U) +#define CAN_F6FB2_FFDB9_Msk (0x1U << CAN_F6FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F6FB2_FFDB9 CAN_F6FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F6FB2_FFDB10_Pos (10U) +#define CAN_F6FB2_FFDB10_Msk (0x1U << CAN_F6FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F6FB2_FFDB10 CAN_F6FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F6FB2_FFDB11_Pos (11U) +#define CAN_F6FB2_FFDB11_Msk (0x1U << CAN_F6FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F6FB2_FFDB11 CAN_F6FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F6FB2_FFDB12_Pos (12U) +#define CAN_F6FB2_FFDB12_Msk (0x1U << CAN_F6FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F6FB2_FFDB12 CAN_F6FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F6FB2_FFDB13_Pos (13U) +#define CAN_F6FB2_FFDB13_Msk (0x1U << CAN_F6FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F6FB2_FFDB13 CAN_F6FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F6FB2_FFDB14_Pos (14U) +#define CAN_F6FB2_FFDB14_Msk (0x1U << CAN_F6FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F6FB2_FFDB14 CAN_F6FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F6FB2_FFDB15_Pos (15U) +#define CAN_F6FB2_FFDB15_Msk (0x1U << CAN_F6FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F6FB2_FFDB15 CAN_F6FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F6FB2_FFDB16_Pos (16U) +#define CAN_F6FB2_FFDB16_Msk (0x1U << CAN_F6FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F6FB2_FFDB16 CAN_F6FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F6FB2_FFDB17_Pos (17U) +#define CAN_F6FB2_FFDB17_Msk (0x1U << CAN_F6FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F6FB2_FFDB17 CAN_F6FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F6FB2_FFDB18_Pos (18U) +#define CAN_F6FB2_FFDB18_Msk (0x1U << CAN_F6FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F6FB2_FFDB18 CAN_F6FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F6FB2_FFDB19_Pos (19U) +#define CAN_F6FB2_FFDB19_Msk (0x1U << CAN_F6FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F6FB2_FFDB19 CAN_F6FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F6FB2_FFDB20_Pos (20U) +#define CAN_F6FB2_FFDB20_Msk (0x1U << CAN_F6FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F6FB2_FFDB20 CAN_F6FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F6FB2_FFDB21_Pos (21U) +#define CAN_F6FB2_FFDB21_Msk (0x1U << CAN_F6FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F6FB2_FFDB21 CAN_F6FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F6FB2_FFDB22_Pos (22U) +#define CAN_F6FB2_FFDB22_Msk (0x1U << CAN_F6FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F6FB2_FFDB22 CAN_F6FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F6FB2_FFDB23_Pos (23U) +#define CAN_F6FB2_FFDB23_Msk (0x1U << CAN_F6FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F6FB2_FFDB23 CAN_F6FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F6FB2_FFDB24_Pos (24U) +#define CAN_F6FB2_FFDB24_Msk (0x1U << CAN_F6FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F6FB2_FFDB24 CAN_F6FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F6FB2_FFDB25_Pos (25U) +#define CAN_F6FB2_FFDB25_Msk (0x1U << CAN_F6FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F6FB2_FFDB25 CAN_F6FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F6FB2_FFDB26_Pos (26U) +#define CAN_F6FB2_FFDB26_Msk (0x1U << CAN_F6FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F6FB2_FFDB26 CAN_F6FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F6FB2_FFDB27_Pos (27U) +#define CAN_F6FB2_FFDB27_Msk (0x1U << CAN_F6FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F6FB2_FFDB27 CAN_F6FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F6FB2_FFDB28_Pos (28U) +#define CAN_F6FB2_FFDB28_Msk (0x1U << CAN_F6FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F6FB2_FFDB28 CAN_F6FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F6FB2_FFDB29_Pos (29U) +#define CAN_F6FB2_FFDB29_Msk (0x1U << CAN_F6FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F6FB2_FFDB29 CAN_F6FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F6FB2_FFDB30_Pos (30U) +#define CAN_F6FB2_FFDB30_Msk (0x1U << CAN_F6FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F6FB2_FFDB30 CAN_F6FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F6FB2_FFDB31_Pos (31U) +#define CAN_F6FB2_FFDB31_Msk (0x1U << CAN_F6FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F6FB2_FFDB31 CAN_F6FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F7FB2 register *******************/ +#define CAN_F7FB2_FFDB0_Pos (0U) +#define CAN_F7FB2_FFDB0_Msk (0x1U << CAN_F7FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F7FB2_FFDB0 CAN_F7FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F7FB2_FFDB1_Pos (1U) +#define CAN_F7FB2_FFDB1_Msk (0x1U << CAN_F7FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F7FB2_FFDB1 CAN_F7FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F7FB2_FFDB2_Pos (2U) +#define CAN_F7FB2_FFDB2_Msk (0x1U << CAN_F7FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F7FB2_FFDB2 CAN_F7FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F7FB2_FFDB3_Pos (3U) +#define CAN_F7FB2_FFDB3_Msk (0x1U << CAN_F7FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F7FB2_FFDB3 CAN_F7FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F7FB2_FFDB4_Pos (4U) +#define CAN_F7FB2_FFDB4_Msk (0x1U << CAN_F7FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F7FB2_FFDB4 CAN_F7FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F7FB2_FFDB5_Pos (5U) +#define CAN_F7FB2_FFDB5_Msk (0x1U << CAN_F7FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F7FB2_FFDB5 CAN_F7FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F7FB2_FFDB6_Pos (6U) +#define CAN_F7FB2_FFDB6_Msk (0x1U << CAN_F7FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F7FB2_FFDB6 CAN_F7FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F7FB2_FFDB7_Pos (7U) +#define CAN_F7FB2_FFDB7_Msk (0x1U << CAN_F7FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F7FB2_FFDB7 CAN_F7FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F7FB2_FFDB8_Pos (8U) +#define CAN_F7FB2_FFDB8_Msk (0x1U << CAN_F7FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F7FB2_FFDB8 CAN_F7FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F7FB2_FFDB9_Pos (9U) +#define CAN_F7FB2_FFDB9_Msk (0x1U << CAN_F7FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F7FB2_FFDB9 CAN_F7FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F7FB2_FFDB10_Pos (10U) +#define CAN_F7FB2_FFDB10_Msk (0x1U << CAN_F7FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F7FB2_FFDB10 CAN_F7FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F7FB2_FFDB11_Pos (11U) +#define CAN_F7FB2_FFDB11_Msk (0x1U << CAN_F7FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F7FB2_FFDB11 CAN_F7FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F7FB2_FFDB12_Pos (12U) +#define CAN_F7FB2_FFDB12_Msk (0x1U << CAN_F7FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F7FB2_FFDB12 CAN_F7FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F7FB2_FFDB13_Pos (13U) +#define CAN_F7FB2_FFDB13_Msk (0x1U << CAN_F7FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F7FB2_FFDB13 CAN_F7FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F7FB2_FFDB14_Pos (14U) +#define CAN_F7FB2_FFDB14_Msk (0x1U << CAN_F7FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F7FB2_FFDB14 CAN_F7FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F7FB2_FFDB15_Pos (15U) +#define CAN_F7FB2_FFDB15_Msk (0x1U << CAN_F7FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F7FB2_FFDB15 CAN_F7FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F7FB2_FFDB16_Pos (16U) +#define CAN_F7FB2_FFDB16_Msk (0x1U << CAN_F7FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F7FB2_FFDB16 CAN_F7FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F7FB2_FFDB17_Pos (17U) +#define CAN_F7FB2_FFDB17_Msk (0x1U << CAN_F7FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F7FB2_FFDB17 CAN_F7FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F7FB2_FFDB18_Pos (18U) +#define CAN_F7FB2_FFDB18_Msk (0x1U << CAN_F7FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F7FB2_FFDB18 CAN_F7FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F7FB2_FFDB19_Pos (19U) +#define CAN_F7FB2_FFDB19_Msk (0x1U << CAN_F7FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F7FB2_FFDB19 CAN_F7FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F7FB2_FFDB20_Pos (20U) +#define CAN_F7FB2_FFDB20_Msk (0x1U << CAN_F7FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F7FB2_FFDB20 CAN_F7FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F7FB2_FFDB21_Pos (21U) +#define CAN_F7FB2_FFDB21_Msk (0x1U << CAN_F7FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F7FB2_FFDB21 CAN_F7FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F7FB2_FFDB22_Pos (22U) +#define CAN_F7FB2_FFDB22_Msk (0x1U << CAN_F7FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F7FB2_FFDB22 CAN_F7FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F7FB2_FFDB23_Pos (23U) +#define CAN_F7FB2_FFDB23_Msk (0x1U << CAN_F7FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F7FB2_FFDB23 CAN_F7FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F7FB2_FFDB24_Pos (24U) +#define CAN_F7FB2_FFDB24_Msk (0x1U << CAN_F7FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F7FB2_FFDB24 CAN_F7FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F7FB2_FFDB25_Pos (25U) +#define CAN_F7FB2_FFDB25_Msk (0x1U << CAN_F7FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F7FB2_FFDB25 CAN_F7FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F7FB2_FFDB26_Pos (26U) +#define CAN_F7FB2_FFDB26_Msk (0x1U << CAN_F7FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F7FB2_FFDB26 CAN_F7FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F7FB2_FFDB27_Pos (27U) +#define CAN_F7FB2_FFDB27_Msk (0x1U << CAN_F7FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F7FB2_FFDB27 CAN_F7FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F7FB2_FFDB28_Pos (28U) +#define CAN_F7FB2_FFDB28_Msk (0x1U << CAN_F7FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F7FB2_FFDB28 CAN_F7FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F7FB2_FFDB29_Pos (29U) +#define CAN_F7FB2_FFDB29_Msk (0x1U << CAN_F7FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F7FB2_FFDB29 CAN_F7FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F7FB2_FFDB30_Pos (30U) +#define CAN_F7FB2_FFDB30_Msk (0x1U << CAN_F7FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F7FB2_FFDB30 CAN_F7FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F7FB2_FFDB31_Pos (31U) +#define CAN_F7FB2_FFDB31_Msk (0x1U << CAN_F7FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F7FB2_FFDB31 CAN_F7FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F8FB2 register *******************/ +#define CAN_F8FB2_FFDB0_Pos (0U) +#define CAN_F8FB2_FFDB0_Msk (0x1U << CAN_F8FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F8FB2_FFDB0 CAN_F8FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F8FB2_FFDB1_Pos (1U) +#define CAN_F8FB2_FFDB1_Msk (0x1U << CAN_F8FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F8FB2_FFDB1 CAN_F8FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F8FB2_FFDB2_Pos (2U) +#define CAN_F8FB2_FFDB2_Msk (0x1U << CAN_F8FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F8FB2_FFDB2 CAN_F8FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F8FB2_FFDB3_Pos (3U) +#define CAN_F8FB2_FFDB3_Msk (0x1U << CAN_F8FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F8FB2_FFDB3 CAN_F8FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F8FB2_FFDB4_Pos (4U) +#define CAN_F8FB2_FFDB4_Msk (0x1U << CAN_F8FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F8FB2_FFDB4 CAN_F8FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F8FB2_FFDB5_Pos (5U) +#define CAN_F8FB2_FFDB5_Msk (0x1U << CAN_F8FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F8FB2_FFDB5 CAN_F8FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F8FB2_FFDB6_Pos (6U) +#define CAN_F8FB2_FFDB6_Msk (0x1U << CAN_F8FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F8FB2_FFDB6 CAN_F8FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F8FB2_FFDB7_Pos (7U) +#define CAN_F8FB2_FFDB7_Msk (0x1U << CAN_F8FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F8FB2_FFDB7 CAN_F8FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F8FB2_FFDB8_Pos (8U) +#define CAN_F8FB2_FFDB8_Msk (0x1U << CAN_F8FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F8FB2_FFDB8 CAN_F8FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F8FB2_FFDB9_Pos (9U) +#define CAN_F8FB2_FFDB9_Msk (0x1U << CAN_F8FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F8FB2_FFDB9 CAN_F8FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F8FB2_FFDB10_Pos (10U) +#define CAN_F8FB2_FFDB10_Msk (0x1U << CAN_F8FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F8FB2_FFDB10 CAN_F8FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F8FB2_FFDB11_Pos (11U) +#define CAN_F8FB2_FFDB11_Msk (0x1U << CAN_F8FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F8FB2_FFDB11 CAN_F8FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F8FB2_FFDB12_Pos (12U) +#define CAN_F8FB2_FFDB12_Msk (0x1U << CAN_F8FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F8FB2_FFDB12 CAN_F8FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F8FB2_FFDB13_Pos (13U) +#define CAN_F8FB2_FFDB13_Msk (0x1U << CAN_F8FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F8FB2_FFDB13 CAN_F8FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F8FB2_FFDB14_Pos (14U) +#define CAN_F8FB2_FFDB14_Msk (0x1U << CAN_F8FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F8FB2_FFDB14 CAN_F8FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F8FB2_FFDB15_Pos (15U) +#define CAN_F8FB2_FFDB15_Msk (0x1U << CAN_F8FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F8FB2_FFDB15 CAN_F8FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F8FB2_FFDB16_Pos (16U) +#define CAN_F8FB2_FFDB16_Msk (0x1U << CAN_F8FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F8FB2_FFDB16 CAN_F8FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F8FB2_FFDB17_Pos (17U) +#define CAN_F8FB2_FFDB17_Msk (0x1U << CAN_F8FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F8FB2_FFDB17 CAN_F8FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F8FB2_FFDB18_Pos (18U) +#define CAN_F8FB2_FFDB18_Msk (0x1U << CAN_F8FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F8FB2_FFDB18 CAN_F8FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F8FB2_FFDB19_Pos (19U) +#define CAN_F8FB2_FFDB19_Msk (0x1U << CAN_F8FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F8FB2_FFDB19 CAN_F8FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F8FB2_FFDB20_Pos (20U) +#define CAN_F8FB2_FFDB20_Msk (0x1U << CAN_F8FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F8FB2_FFDB20 CAN_F8FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F8FB2_FFDB21_Pos (21U) +#define CAN_F8FB2_FFDB21_Msk (0x1U << CAN_F8FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F8FB2_FFDB21 CAN_F8FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F8FB2_FFDB22_Pos (22U) +#define CAN_F8FB2_FFDB22_Msk (0x1U << CAN_F8FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F8FB2_FFDB22 CAN_F8FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F8FB2_FFDB23_Pos (23U) +#define CAN_F8FB2_FFDB23_Msk (0x1U << CAN_F8FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F8FB2_FFDB23 CAN_F8FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F8FB2_FFDB24_Pos (24U) +#define CAN_F8FB2_FFDB24_Msk (0x1U << CAN_F8FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F8FB2_FFDB24 CAN_F8FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F8FB2_FFDB25_Pos (25U) +#define CAN_F8FB2_FFDB25_Msk (0x1U << CAN_F8FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F8FB2_FFDB25 CAN_F8FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F8FB2_FFDB26_Pos (26U) +#define CAN_F8FB2_FFDB26_Msk (0x1U << CAN_F8FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F8FB2_FFDB26 CAN_F8FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F8FB2_FFDB27_Pos (27U) +#define CAN_F8FB2_FFDB27_Msk (0x1U << CAN_F8FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F8FB2_FFDB27 CAN_F8FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F8FB2_FFDB28_Pos (28U) +#define CAN_F8FB2_FFDB28_Msk (0x1U << CAN_F8FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F8FB2_FFDB28 CAN_F8FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F8FB2_FFDB29_Pos (29U) +#define CAN_F8FB2_FFDB29_Msk (0x1U << CAN_F8FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F8FB2_FFDB29 CAN_F8FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F8FB2_FFDB30_Pos (30U) +#define CAN_F8FB2_FFDB30_Msk (0x1U << CAN_F8FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F8FB2_FFDB30 CAN_F8FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F8FB2_FFDB31_Pos (31U) +#define CAN_F8FB2_FFDB31_Msk (0x1U << CAN_F8FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F8FB2_FFDB31 CAN_F8FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F9FB2 register *******************/ +#define CAN_F9FB2_FFDB0_Pos (0U) +#define CAN_F9FB2_FFDB0_Msk (0x1U << CAN_F9FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F9FB2_FFDB0 CAN_F9FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F9FB2_FFDB1_Pos (1U) +#define CAN_F9FB2_FFDB1_Msk (0x1U << CAN_F9FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F9FB2_FFDB1 CAN_F9FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F9FB2_FFDB2_Pos (2U) +#define CAN_F9FB2_FFDB2_Msk (0x1U << CAN_F9FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F9FB2_FFDB2 CAN_F9FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F9FB2_FFDB3_Pos (3U) +#define CAN_F9FB2_FFDB3_Msk (0x1U << CAN_F9FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F9FB2_FFDB3 CAN_F9FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F9FB2_FFDB4_Pos (4U) +#define CAN_F9FB2_FFDB4_Msk (0x1U << CAN_F9FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F9FB2_FFDB4 CAN_F9FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F9FB2_FFDB5_Pos (5U) +#define CAN_F9FB2_FFDB5_Msk (0x1U << CAN_F9FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F9FB2_FFDB5 CAN_F9FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F9FB2_FFDB6_Pos (6U) +#define CAN_F9FB2_FFDB6_Msk (0x1U << CAN_F9FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F9FB2_FFDB6 CAN_F9FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F9FB2_FFDB7_Pos (7U) +#define CAN_F9FB2_FFDB7_Msk (0x1U << CAN_F9FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F9FB2_FFDB7 CAN_F9FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F9FB2_FFDB8_Pos (8U) +#define CAN_F9FB2_FFDB8_Msk (0x1U << CAN_F9FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F9FB2_FFDB8 CAN_F9FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F9FB2_FFDB9_Pos (9U) +#define CAN_F9FB2_FFDB9_Msk (0x1U << CAN_F9FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F9FB2_FFDB9 CAN_F9FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F9FB2_FFDB10_Pos (10U) +#define CAN_F9FB2_FFDB10_Msk (0x1U << CAN_F9FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F9FB2_FFDB10 CAN_F9FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F9FB2_FFDB11_Pos (11U) +#define CAN_F9FB2_FFDB11_Msk (0x1U << CAN_F9FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F9FB2_FFDB11 CAN_F9FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F9FB2_FFDB12_Pos (12U) +#define CAN_F9FB2_FFDB12_Msk (0x1U << CAN_F9FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F9FB2_FFDB12 CAN_F9FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F9FB2_FFDB13_Pos (13U) +#define CAN_F9FB2_FFDB13_Msk (0x1U << CAN_F9FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F9FB2_FFDB13 CAN_F9FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F9FB2_FFDB14_Pos (14U) +#define CAN_F9FB2_FFDB14_Msk (0x1U << CAN_F9FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F9FB2_FFDB14 CAN_F9FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F9FB2_FFDB15_Pos (15U) +#define CAN_F9FB2_FFDB15_Msk (0x1U << CAN_F9FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F9FB2_FFDB15 CAN_F9FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F9FB2_FFDB16_Pos (16U) +#define CAN_F9FB2_FFDB16_Msk (0x1U << CAN_F9FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F9FB2_FFDB16 CAN_F9FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F9FB2_FFDB17_Pos (17U) +#define CAN_F9FB2_FFDB17_Msk (0x1U << CAN_F9FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F9FB2_FFDB17 CAN_F9FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F9FB2_FFDB18_Pos (18U) +#define CAN_F9FB2_FFDB18_Msk (0x1U << CAN_F9FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F9FB2_FFDB18 CAN_F9FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F9FB2_FFDB19_Pos (19U) +#define CAN_F9FB2_FFDB19_Msk (0x1U << CAN_F9FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F9FB2_FFDB19 CAN_F9FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F9FB2_FFDB20_Pos (20U) +#define CAN_F9FB2_FFDB20_Msk (0x1U << CAN_F9FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F9FB2_FFDB20 CAN_F9FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F9FB2_FFDB21_Pos (21U) +#define CAN_F9FB2_FFDB21_Msk (0x1U << CAN_F9FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F9FB2_FFDB21 CAN_F9FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F9FB2_FFDB22_Pos (22U) +#define CAN_F9FB2_FFDB22_Msk (0x1U << CAN_F9FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F9FB2_FFDB22 CAN_F9FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F9FB2_FFDB23_Pos (23U) +#define CAN_F9FB2_FFDB23_Msk (0x1U << CAN_F9FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F9FB2_FFDB23 CAN_F9FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F9FB2_FFDB24_Pos (24U) +#define CAN_F9FB2_FFDB24_Msk (0x1U << CAN_F9FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F9FB2_FFDB24 CAN_F9FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F9FB2_FFDB25_Pos (25U) +#define CAN_F9FB2_FFDB25_Msk (0x1U << CAN_F9FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F9FB2_FFDB25 CAN_F9FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F9FB2_FFDB26_Pos (26U) +#define CAN_F9FB2_FFDB26_Msk (0x1U << CAN_F9FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F9FB2_FFDB26 CAN_F9FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F9FB2_FFDB27_Pos (27U) +#define CAN_F9FB2_FFDB27_Msk (0x1U << CAN_F9FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F9FB2_FFDB27 CAN_F9FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F9FB2_FFDB28_Pos (28U) +#define CAN_F9FB2_FFDB28_Msk (0x1U << CAN_F9FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F9FB2_FFDB28 CAN_F9FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F9FB2_FFDB29_Pos (29U) +#define CAN_F9FB2_FFDB29_Msk (0x1U << CAN_F9FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F9FB2_FFDB29 CAN_F9FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F9FB2_FFDB30_Pos (30U) +#define CAN_F9FB2_FFDB30_Msk (0x1U << CAN_F9FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F9FB2_FFDB30 CAN_F9FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F9FB2_FFDB31_Pos (31U) +#define CAN_F9FB2_FFDB31_Msk (0x1U << CAN_F9FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F9FB2_FFDB31 CAN_F9FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F10FB2 register ******************/ +#define CAN_F10FB2_FFDB0_Pos (0U) +#define CAN_F10FB2_FFDB0_Msk (0x1U << CAN_F10FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F10FB2_FFDB0 CAN_F10FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F10FB2_FFDB1_Pos (1U) +#define CAN_F10FB2_FFDB1_Msk (0x1U << CAN_F10FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F10FB2_FFDB1 CAN_F10FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F10FB2_FFDB2_Pos (2U) +#define CAN_F10FB2_FFDB2_Msk (0x1U << CAN_F10FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F10FB2_FFDB2 CAN_F10FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F10FB2_FFDB3_Pos (3U) +#define CAN_F10FB2_FFDB3_Msk (0x1U << CAN_F10FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F10FB2_FFDB3 CAN_F10FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F10FB2_FFDB4_Pos (4U) +#define CAN_F10FB2_FFDB4_Msk (0x1U << CAN_F10FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F10FB2_FFDB4 CAN_F10FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F10FB2_FFDB5_Pos (5U) +#define CAN_F10FB2_FFDB5_Msk (0x1U << CAN_F10FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F10FB2_FFDB5 CAN_F10FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F10FB2_FFDB6_Pos (6U) +#define CAN_F10FB2_FFDB6_Msk (0x1U << CAN_F10FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F10FB2_FFDB6 CAN_F10FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F10FB2_FFDB7_Pos (7U) +#define CAN_F10FB2_FFDB7_Msk (0x1U << CAN_F10FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F10FB2_FFDB7 CAN_F10FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F10FB2_FFDB8_Pos (8U) +#define CAN_F10FB2_FFDB8_Msk (0x1U << CAN_F10FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F10FB2_FFDB8 CAN_F10FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F10FB2_FFDB9_Pos (9U) +#define CAN_F10FB2_FFDB9_Msk (0x1U << CAN_F10FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F10FB2_FFDB9 CAN_F10FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F10FB2_FFDB10_Pos (10U) +#define CAN_F10FB2_FFDB10_Msk (0x1U << CAN_F10FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F10FB2_FFDB10 CAN_F10FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F10FB2_FFDB11_Pos (11U) +#define CAN_F10FB2_FFDB11_Msk (0x1U << CAN_F10FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F10FB2_FFDB11 CAN_F10FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F10FB2_FFDB12_Pos (12U) +#define CAN_F10FB2_FFDB12_Msk (0x1U << CAN_F10FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F10FB2_FFDB12 CAN_F10FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F10FB2_FFDB13_Pos (13U) +#define CAN_F10FB2_FFDB13_Msk (0x1U << CAN_F10FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F10FB2_FFDB13 CAN_F10FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F10FB2_FFDB14_Pos (14U) +#define CAN_F10FB2_FFDB14_Msk (0x1U << CAN_F10FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F10FB2_FFDB14 CAN_F10FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F10FB2_FFDB15_Pos (15U) +#define CAN_F10FB2_FFDB15_Msk (0x1U << CAN_F10FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F10FB2_FFDB15 CAN_F10FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F10FB2_FFDB16_Pos (16U) +#define CAN_F10FB2_FFDB16_Msk (0x1U << CAN_F10FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F10FB2_FFDB16 CAN_F10FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F10FB2_FFDB17_Pos (17U) +#define CAN_F10FB2_FFDB17_Msk (0x1U << CAN_F10FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F10FB2_FFDB17 CAN_F10FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F10FB2_FFDB18_Pos (18U) +#define CAN_F10FB2_FFDB18_Msk (0x1U << CAN_F10FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F10FB2_FFDB18 CAN_F10FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F10FB2_FFDB19_Pos (19U) +#define CAN_F10FB2_FFDB19_Msk (0x1U << CAN_F10FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F10FB2_FFDB19 CAN_F10FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F10FB2_FFDB20_Pos (20U) +#define CAN_F10FB2_FFDB20_Msk (0x1U << CAN_F10FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F10FB2_FFDB20 CAN_F10FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F10FB2_FFDB21_Pos (21U) +#define CAN_F10FB2_FFDB21_Msk (0x1U << CAN_F10FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F10FB2_FFDB21 CAN_F10FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F10FB2_FFDB22_Pos (22U) +#define CAN_F10FB2_FFDB22_Msk (0x1U << CAN_F10FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F10FB2_FFDB22 CAN_F10FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F10FB2_FFDB23_Pos (23U) +#define CAN_F10FB2_FFDB23_Msk (0x1U << CAN_F10FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F10FB2_FFDB23 CAN_F10FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F10FB2_FFDB24_Pos (24U) +#define CAN_F10FB2_FFDB24_Msk (0x1U << CAN_F10FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F10FB2_FFDB24 CAN_F10FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F10FB2_FFDB25_Pos (25U) +#define CAN_F10FB2_FFDB25_Msk (0x1U << CAN_F10FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F10FB2_FFDB25 CAN_F10FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F10FB2_FFDB26_Pos (26U) +#define CAN_F10FB2_FFDB26_Msk (0x1U << CAN_F10FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F10FB2_FFDB26 CAN_F10FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F10FB2_FFDB27_Pos (27U) +#define CAN_F10FB2_FFDB27_Msk (0x1U << CAN_F10FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F10FB2_FFDB27 CAN_F10FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F10FB2_FFDB28_Pos (28U) +#define CAN_F10FB2_FFDB28_Msk (0x1U << CAN_F10FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F10FB2_FFDB28 CAN_F10FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F10FB2_FFDB29_Pos (29U) +#define CAN_F10FB2_FFDB29_Msk (0x1U << CAN_F10FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F10FB2_FFDB29 CAN_F10FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F10FB2_FFDB30_Pos (30U) +#define CAN_F10FB2_FFDB30_Msk (0x1U << CAN_F10FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F10FB2_FFDB30 CAN_F10FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F10FB2_FFDB31_Pos (31U) +#define CAN_F10FB2_FFDB31_Msk (0x1U << CAN_F10FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F10FB2_FFDB31 CAN_F10FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F11FB2 register ******************/ +#define CAN_F11FB2_FFDB0_Pos (0U) +#define CAN_F11FB2_FFDB0_Msk (0x1U << CAN_F11FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F11FB2_FFDB0 CAN_F11FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F11FB2_FFDB1_Pos (1U) +#define CAN_F11FB2_FFDB1_Msk (0x1U << CAN_F11FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F11FB2_FFDB1 CAN_F11FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F11FB2_FFDB2_Pos (2U) +#define CAN_F11FB2_FFDB2_Msk (0x1U << CAN_F11FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F11FB2_FFDB2 CAN_F11FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F11FB2_FFDB3_Pos (3U) +#define CAN_F11FB2_FFDB3_Msk (0x1U << CAN_F11FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F11FB2_FFDB3 CAN_F11FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F11FB2_FFDB4_Pos (4U) +#define CAN_F11FB2_FFDB4_Msk (0x1U << CAN_F11FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F11FB2_FFDB4 CAN_F11FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F11FB2_FFDB5_Pos (5U) +#define CAN_F11FB2_FFDB5_Msk (0x1U << CAN_F11FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F11FB2_FFDB5 CAN_F11FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F11FB2_FFDB6_Pos (6U) +#define CAN_F11FB2_FFDB6_Msk (0x1U << CAN_F11FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F11FB2_FFDB6 CAN_F11FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F11FB2_FFDB7_Pos (7U) +#define CAN_F11FB2_FFDB7_Msk (0x1U << CAN_F11FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F11FB2_FFDB7 CAN_F11FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F11FB2_FFDB8_Pos (8U) +#define CAN_F11FB2_FFDB8_Msk (0x1U << CAN_F11FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F11FB2_FFDB8 CAN_F11FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F11FB2_FFDB9_Pos (9U) +#define CAN_F11FB2_FFDB9_Msk (0x1U << CAN_F11FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F11FB2_FFDB9 CAN_F11FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F11FB2_FFDB10_Pos (10U) +#define CAN_F11FB2_FFDB10_Msk (0x1U << CAN_F11FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F11FB2_FFDB10 CAN_F11FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F11FB2_FFDB11_Pos (11U) +#define CAN_F11FB2_FFDB11_Msk (0x1U << CAN_F11FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F11FB2_FFDB11 CAN_F11FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F11FB2_FFDB12_Pos (12U) +#define CAN_F11FB2_FFDB12_Msk (0x1U << CAN_F11FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F11FB2_FFDB12 CAN_F11FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F11FB2_FFDB13_Pos (13U) +#define CAN_F11FB2_FFDB13_Msk (0x1U << CAN_F11FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F11FB2_FFDB13 CAN_F11FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F11FB2_FFDB14_Pos (14U) +#define CAN_F11FB2_FFDB14_Msk (0x1U << CAN_F11FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F11FB2_FFDB14 CAN_F11FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F11FB2_FFDB15_Pos (15U) +#define CAN_F11FB2_FFDB15_Msk (0x1U << CAN_F11FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F11FB2_FFDB15 CAN_F11FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F11FB2_FFDB16_Pos (16U) +#define CAN_F11FB2_FFDB16_Msk (0x1U << CAN_F11FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F11FB2_FFDB16 CAN_F11FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F11FB2_FFDB17_Pos (17U) +#define CAN_F11FB2_FFDB17_Msk (0x1U << CAN_F11FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F11FB2_FFDB17 CAN_F11FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F11FB2_FFDB18_Pos (18U) +#define CAN_F11FB2_FFDB18_Msk (0x1U << CAN_F11FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F11FB2_FFDB18 CAN_F11FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F11FB2_FFDB19_Pos (19U) +#define CAN_F11FB2_FFDB19_Msk (0x1U << CAN_F11FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F11FB2_FFDB19 CAN_F11FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F11FB2_FFDB20_Pos (20U) +#define CAN_F11FB2_FFDB20_Msk (0x1U << CAN_F11FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F11FB2_FFDB20 CAN_F11FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F11FB2_FFDB21_Pos (21U) +#define CAN_F11FB2_FFDB21_Msk (0x1U << CAN_F11FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F11FB2_FFDB21 CAN_F11FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F11FB2_FFDB22_Pos (22U) +#define CAN_F11FB2_FFDB22_Msk (0x1U << CAN_F11FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F11FB2_FFDB22 CAN_F11FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F11FB2_FFDB23_Pos (23U) +#define CAN_F11FB2_FFDB23_Msk (0x1U << CAN_F11FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F11FB2_FFDB23 CAN_F11FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F11FB2_FFDB24_Pos (24U) +#define CAN_F11FB2_FFDB24_Msk (0x1U << CAN_F11FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F11FB2_FFDB24 CAN_F11FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F11FB2_FFDB25_Pos (25U) +#define CAN_F11FB2_FFDB25_Msk (0x1U << CAN_F11FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F11FB2_FFDB25 CAN_F11FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F11FB2_FFDB26_Pos (26U) +#define CAN_F11FB2_FFDB26_Msk (0x1U << CAN_F11FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F11FB2_FFDB26 CAN_F11FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F11FB2_FFDB27_Pos (27U) +#define CAN_F11FB2_FFDB27_Msk (0x1U << CAN_F11FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F11FB2_FFDB27 CAN_F11FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F11FB2_FFDB28_Pos (28U) +#define CAN_F11FB2_FFDB28_Msk (0x1U << CAN_F11FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F11FB2_FFDB28 CAN_F11FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F11FB2_FFDB29_Pos (29U) +#define CAN_F11FB2_FFDB29_Msk (0x1U << CAN_F11FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F11FB2_FFDB29 CAN_F11FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F11FB2_FFDB30_Pos (30U) +#define CAN_F11FB2_FFDB30_Msk (0x1U << CAN_F11FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F11FB2_FFDB30 CAN_F11FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F11FB2_FFDB31_Pos (31U) +#define CAN_F11FB2_FFDB31_Msk (0x1U << CAN_F11FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F11FB2_FFDB31 CAN_F11FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F12FB2 register ******************/ +#define CAN_F12FB2_FFDB0_Pos (0U) +#define CAN_F12FB2_FFDB0_Msk (0x1U << CAN_F12FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F12FB2_FFDB0 CAN_F12FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F12FB2_FFDB1_Pos (1U) +#define CAN_F12FB2_FFDB1_Msk (0x1U << CAN_F12FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F12FB2_FFDB1 CAN_F12FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F12FB2_FFDB2_Pos (2U) +#define CAN_F12FB2_FFDB2_Msk (0x1U << CAN_F12FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F12FB2_FFDB2 CAN_F12FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F12FB2_FFDB3_Pos (3U) +#define CAN_F12FB2_FFDB3_Msk (0x1U << CAN_F12FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F12FB2_FFDB3 CAN_F12FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F12FB2_FFDB4_Pos (4U) +#define CAN_F12FB2_FFDB4_Msk (0x1U << CAN_F12FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F12FB2_FFDB4 CAN_F12FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F12FB2_FFDB5_Pos (5U) +#define CAN_F12FB2_FFDB5_Msk (0x1U << CAN_F12FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F12FB2_FFDB5 CAN_F12FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F12FB2_FFDB6_Pos (6U) +#define CAN_F12FB2_FFDB6_Msk (0x1U << CAN_F12FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F12FB2_FFDB6 CAN_F12FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F12FB2_FFDB7_Pos (7U) +#define CAN_F12FB2_FFDB7_Msk (0x1U << CAN_F12FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F12FB2_FFDB7 CAN_F12FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F12FB2_FFDB8_Pos (8U) +#define CAN_F12FB2_FFDB8_Msk (0x1U << CAN_F12FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F12FB2_FFDB8 CAN_F12FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F12FB2_FFDB9_Pos (9U) +#define CAN_F12FB2_FFDB9_Msk (0x1U << CAN_F12FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F12FB2_FFDB9 CAN_F12FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F12FB2_FFDB10_Pos (10U) +#define CAN_F12FB2_FFDB10_Msk (0x1U << CAN_F12FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F12FB2_FFDB10 CAN_F12FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F12FB2_FFDB11_Pos (11U) +#define CAN_F12FB2_FFDB11_Msk (0x1U << CAN_F12FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F12FB2_FFDB11 CAN_F12FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F12FB2_FFDB12_Pos (12U) +#define CAN_F12FB2_FFDB12_Msk (0x1U << CAN_F12FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F12FB2_FFDB12 CAN_F12FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F12FB2_FFDB13_Pos (13U) +#define CAN_F12FB2_FFDB13_Msk (0x1U << CAN_F12FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F12FB2_FFDB13 CAN_F12FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F12FB2_FFDB14_Pos (14U) +#define CAN_F12FB2_FFDB14_Msk (0x1U << CAN_F12FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F12FB2_FFDB14 CAN_F12FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F12FB2_FFDB15_Pos (15U) +#define CAN_F12FB2_FFDB15_Msk (0x1U << CAN_F12FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F12FB2_FFDB15 CAN_F12FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F12FB2_FFDB16_Pos (16U) +#define CAN_F12FB2_FFDB16_Msk (0x1U << CAN_F12FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F12FB2_FFDB16 CAN_F12FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F12FB2_FFDB17_Pos (17U) +#define CAN_F12FB2_FFDB17_Msk (0x1U << CAN_F12FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F12FB2_FFDB17 CAN_F12FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F12FB2_FFDB18_Pos (18U) +#define CAN_F12FB2_FFDB18_Msk (0x1U << CAN_F12FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F12FB2_FFDB18 CAN_F12FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F12FB2_FFDB19_Pos (19U) +#define CAN_F12FB2_FFDB19_Msk (0x1U << CAN_F12FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F12FB2_FFDB19 CAN_F12FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F12FB2_FFDB20_Pos (20U) +#define CAN_F12FB2_FFDB20_Msk (0x1U << CAN_F12FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F12FB2_FFDB20 CAN_F12FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F12FB2_FFDB21_Pos (21U) +#define CAN_F12FB2_FFDB21_Msk (0x1U << CAN_F12FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F12FB2_FFDB21 CAN_F12FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F12FB2_FFDB22_Pos (22U) +#define CAN_F12FB2_FFDB22_Msk (0x1U << CAN_F12FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F12FB2_FFDB22 CAN_F12FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F12FB2_FFDB23_Pos (23U) +#define CAN_F12FB2_FFDB23_Msk (0x1U << CAN_F12FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F12FB2_FFDB23 CAN_F12FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F12FB2_FFDB24_Pos (24U) +#define CAN_F12FB2_FFDB24_Msk (0x1U << CAN_F12FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F12FB2_FFDB24 CAN_F12FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F12FB2_FFDB25_Pos (25U) +#define CAN_F12FB2_FFDB25_Msk (0x1U << CAN_F12FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F12FB2_FFDB25 CAN_F12FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F12FB2_FFDB26_Pos (26U) +#define CAN_F12FB2_FFDB26_Msk (0x1U << CAN_F12FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F12FB2_FFDB26 CAN_F12FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F12FB2_FFDB27_Pos (27U) +#define CAN_F12FB2_FFDB27_Msk (0x1U << CAN_F12FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F12FB2_FFDB27 CAN_F12FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F12FB2_FFDB28_Pos (28U) +#define CAN_F12FB2_FFDB28_Msk (0x1U << CAN_F12FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F12FB2_FFDB28 CAN_F12FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F12FB2_FFDB29_Pos (29U) +#define CAN_F12FB2_FFDB29_Msk (0x1U << CAN_F12FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F12FB2_FFDB29 CAN_F12FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F12FB2_FFDB30_Pos (30U) +#define CAN_F12FB2_FFDB30_Msk (0x1U << CAN_F12FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F12FB2_FFDB30 CAN_F12FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F12FB2_FFDB31_Pos (31U) +#define CAN_F12FB2_FFDB31_Msk (0x1U << CAN_F12FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F12FB2_FFDB31 CAN_F12FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F13FB2 register ******************/ +#define CAN_F13FB2_FFDB0_Pos (0U) +#define CAN_F13FB2_FFDB0_Msk (0x1U << CAN_F13FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F13FB2_FFDB0 CAN_F13FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F13FB2_FFDB1_Pos (1U) +#define CAN_F13FB2_FFDB1_Msk (0x1U << CAN_F13FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F13FB2_FFDB1 CAN_F13FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F13FB2_FFDB2_Pos (2U) +#define CAN_F13FB2_FFDB2_Msk (0x1U << CAN_F13FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F13FB2_FFDB2 CAN_F13FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F13FB2_FFDB3_Pos (3U) +#define CAN_F13FB2_FFDB3_Msk (0x1U << CAN_F13FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F13FB2_FFDB3 CAN_F13FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F13FB2_FFDB4_Pos (4U) +#define CAN_F13FB2_FFDB4_Msk (0x1U << CAN_F13FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F13FB2_FFDB4 CAN_F13FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F13FB2_FFDB5_Pos (5U) +#define CAN_F13FB2_FFDB5_Msk (0x1U << CAN_F13FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F13FB2_FFDB5 CAN_F13FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F13FB2_FFDB6_Pos (6U) +#define CAN_F13FB2_FFDB6_Msk (0x1U << CAN_F13FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F13FB2_FFDB6 CAN_F13FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F13FB2_FFDB7_Pos (7U) +#define CAN_F13FB2_FFDB7_Msk (0x1U << CAN_F13FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F13FB2_FFDB7 CAN_F13FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F13FB2_FFDB8_Pos (8U) +#define CAN_F13FB2_FFDB8_Msk (0x1U << CAN_F13FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F13FB2_FFDB8 CAN_F13FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F13FB2_FFDB9_Pos (9U) +#define CAN_F13FB2_FFDB9_Msk (0x1U << CAN_F13FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F13FB2_FFDB9 CAN_F13FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F13FB2_FFDB10_Pos (10U) +#define CAN_F13FB2_FFDB10_Msk (0x1U << CAN_F13FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F13FB2_FFDB10 CAN_F13FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F13FB2_FFDB11_Pos (11U) +#define CAN_F13FB2_FFDB11_Msk (0x1U << CAN_F13FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F13FB2_FFDB11 CAN_F13FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F13FB2_FFDB12_Pos (12U) +#define CAN_F13FB2_FFDB12_Msk (0x1U << CAN_F13FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F13FB2_FFDB12 CAN_F13FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F13FB2_FFDB13_Pos (13U) +#define CAN_F13FB2_FFDB13_Msk (0x1U << CAN_F13FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F13FB2_FFDB13 CAN_F13FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F13FB2_FFDB14_Pos (14U) +#define CAN_F13FB2_FFDB14_Msk (0x1U << CAN_F13FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F13FB2_FFDB14 CAN_F13FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F13FB2_FFDB15_Pos (15U) +#define CAN_F13FB2_FFDB15_Msk (0x1U << CAN_F13FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F13FB2_FFDB15 CAN_F13FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F13FB2_FFDB16_Pos (16U) +#define CAN_F13FB2_FFDB16_Msk (0x1U << CAN_F13FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F13FB2_FFDB16 CAN_F13FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F13FB2_FFDB17_Pos (17U) +#define CAN_F13FB2_FFDB17_Msk (0x1U << CAN_F13FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F13FB2_FFDB17 CAN_F13FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F13FB2_FFDB18_Pos (18U) +#define CAN_F13FB2_FFDB18_Msk (0x1U << CAN_F13FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F13FB2_FFDB18 CAN_F13FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F13FB2_FFDB19_Pos (19U) +#define CAN_F13FB2_FFDB19_Msk (0x1U << CAN_F13FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F13FB2_FFDB19 CAN_F13FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F13FB2_FFDB20_Pos (20U) +#define CAN_F13FB2_FFDB20_Msk (0x1U << CAN_F13FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F13FB2_FFDB20 CAN_F13FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F13FB2_FFDB21_Pos (21U) +#define CAN_F13FB2_FFDB21_Msk (0x1U << CAN_F13FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F13FB2_FFDB21 CAN_F13FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F13FB2_FFDB22_Pos (22U) +#define CAN_F13FB2_FFDB22_Msk (0x1U << CAN_F13FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F13FB2_FFDB22 CAN_F13FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F13FB2_FFDB23_Pos (23U) +#define CAN_F13FB2_FFDB23_Msk (0x1U << CAN_F13FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F13FB2_FFDB23 CAN_F13FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F13FB2_FFDB24_Pos (24U) +#define CAN_F13FB2_FFDB24_Msk (0x1U << CAN_F13FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F13FB2_FFDB24 CAN_F13FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F13FB2_FFDB25_Pos (25U) +#define CAN_F13FB2_FFDB25_Msk (0x1U << CAN_F13FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F13FB2_FFDB25 CAN_F13FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F13FB2_FFDB26_Pos (26U) +#define CAN_F13FB2_FFDB26_Msk (0x1U << CAN_F13FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F13FB2_FFDB26 CAN_F13FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F13FB2_FFDB27_Pos (27U) +#define CAN_F13FB2_FFDB27_Msk (0x1U << CAN_F13FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F13FB2_FFDB27 CAN_F13FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F13FB2_FFDB28_Pos (28U) +#define CAN_F13FB2_FFDB28_Msk (0x1U << CAN_F13FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F13FB2_FFDB28 CAN_F13FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F13FB2_FFDB29_Pos (29U) +#define CAN_F13FB2_FFDB29_Msk (0x1U << CAN_F13FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F13FB2_FFDB29 CAN_F13FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F13FB2_FFDB30_Pos (30U) +#define CAN_F13FB2_FFDB30_Msk (0x1U << CAN_F13FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F13FB2_FFDB30 CAN_F13FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F13FB2_FFDB31_Pos (31U) +#define CAN_F13FB2_FFDB31_Msk (0x1U << CAN_F13FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F13FB2_FFDB31 CAN_F13FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/******************************************************************************/ +/* */ +/* HICK auto clock calibration (ACC) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for ACC_STS register ********************/ +#define ACC_STS_CALRDY_Pos (0U) +#define ACC_STS_CALRDY_Msk (0x1U << ACC_STS_CALRDY_Pos) /*!< 0x00000001 */ +#define ACC_STS_CALRDY ACC_STS_CALRDY_Msk /*!< Internal high-speed clock calibration ready */ +#define ACC_STS_RSLOST_Pos (1U) +#define ACC_STS_RSLOST_Msk (0x1U << ACC_STS_RSLOST_Pos) /*!< 0x00000002 */ +#define ACC_STS_RSLOST ACC_STS_RSLOST_Msk /*!< Reference signal lost */ + +/****************** Bit definition for ACC_CTRL1 register *******************/ +#define ACC_CTRL1_CALON_Pos (0U) +#define ACC_CTRL1_CALON_Msk (0x1U << ACC_CTRL1_CALON_Pos) /*!< 0x00000001 */ +#define ACC_CTRL1_CALON ACC_CTRL1_CALON_Msk /*!< Calibration on */ +#define ACC_CTRL1_ENTRIM_Pos (1U) +#define ACC_CTRL1_ENTRIM_Msk (0x1U << ACC_CTRL1_ENTRIM_Pos) /*!< 0x00000002 */ +#define ACC_CTRL1_ENTRIM ACC_CTRL1_ENTRIM_Msk /*!< Enable trim */ +#define ACC_CTRL1_EIEN_Pos (4U) +#define ACC_CTRL1_EIEN_Msk (0x1U << ACC_CTRL1_EIEN_Pos) /*!< 0x00000010 */ +#define ACC_CTRL1_EIEN ACC_CTRL1_EIEN_Msk /*!< RSLOST error interrupt enable */ +#define ACC_CTRL1_CALRDYIEN_Pos (5U) +#define ACC_CTRL1_CALRDYIEN_Msk (0x1U << ACC_CTRL1_CALRDYIEN_Pos) /*!< 0x00000020 */ +#define ACC_CTRL1_CALRDYIEN ACC_CTRL1_CALRDYIEN_Msk /*!< CALRDY interrupt enable */ +#define ACC_CTRL1_STEP_Pos (8U) +#define ACC_CTRL1_STEP_Msk (0xFU << ACC_CTRL1_STEP_Pos) /*!< 0x00000F00 */ +#define ACC_CTRL1_STEP ACC_CTRL1_STEP_Msk /*!< Calibrated step */ + +/****************** Bit definition for ACC_CTRL2 register *******************/ +#define ACC_CTRL2_HICKCAL_Pos (0U) +#define ACC_CTRL2_HICKCAL_Msk (0xFFU << ACC_CTRL2_HICKCAL_Pos) /*!< 0x000000FF */ +#define ACC_CTRL2_HICKCAL ACC_CTRL2_HICKCAL_Msk /*!< Internal high-speed auto clock calibration */ +#define ACC_CTRL2_HICKTRIM_Pos (8U) +#define ACC_CTRL2_HICKTRIM_Msk (0x3FU << ACC_CTRL2_HICKTRIM_Pos) /*!< 0x00003F00 */ +#define ACC_CTRL2_HICKTRIM ACC_CTRL2_HICKTRIM_Msk /*!< Internal high-speed auto clock trimming */ + +/******************* Bit definition for ACC_CP1 register ********************/ +#define ACC_CP1_C1_Pos (0U) +#define ACC_CP1_C1_Msk (0xFFFFU << ACC_CP1_C1_Pos) /*!< 0x0000FFFF */ +#define ACC_CP1_C1 ACC_CP1_C1_Msk /*!< Compare 1 */ + +/******************* Bit definition for ACC_CP2 register ********************/ +#define ACC_CP2_C2_Pos (0U) +#define ACC_CP2_C2_Msk (0xFFFFU << ACC_CP2_C2_Pos) /*!< 0x0000FFFF */ +#define ACC_CP2_C2 ACC_CP2_C2_Msk /*!< Compare 2 */ + +/******************* Bit definition for ACC_CP3 register ********************/ +#define ACC_CP3_C3_Pos (0U) +#define ACC_CP3_C3_Msk (0xFFFFU << ACC_CP3_C3_Pos) /*!< 0x0000FFFF */ +#define ACC_CP3_C3 ACC_CP3_C3_Msk /*!< Compare 3 */ + +/******************************************************************************/ +/* */ +/* Quad-SPI interface (QSPI) */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for QSPI_CMD_W0 register ******************/ +#define QSPI_CMD_W0_SPIADR_Pos (0U) +#define QSPI_CMD_W0_SPIADR_Msk (0xFFFFFFFFU << QSPI_CMD_W0_SPIADR_Pos) /*!< 0xFFFFFFFF */ +#define QSPI_CMD_W0_SPIADR QSPI_CMD_W0_SPIADR_Msk /*!< SPI Flash address */ + +/***************** Bit definition for QSPI_CMD_W1 register ******************/ +/*!< ADRLEN congiguration */ +#define QSPI_CMD_W1_ADRLEN_Pos (0U) +#define QSPI_CMD_W1_ADRLEN_Msk (0x7U << QSPI_CMD_W1_ADRLEN_Pos) /*!< 0x00000007 */ +#define QSPI_CMD_W1_ADRLEN QSPI_CMD_W1_ADRLEN_Msk /*!< ADRLEN[2:0] bits (SPI address length) */ +#define QSPI_CMD_W1_ADRLEN_0 (0x1U << QSPI_CMD_W1_ADRLEN_Pos) /*!< 0x00000001 */ +#define QSPI_CMD_W1_ADRLEN_1 (0x2U << QSPI_CMD_W1_ADRLEN_Pos) /*!< 0x00000002 */ +#define QSPI_CMD_W1_ADRLEN_2 (0x4U << QSPI_CMD_W1_ADRLEN_Pos) /*!< 0x00000004 */ + +#define QSPI_CMD_W1_ADRLEN_NOBYTE 0x00000000U /*!< No address state */ +#define QSPI_CMD_W1_ADRLEN_1BYTE 0x00000001U /*!< 1-byte address */ +#define QSPI_CMD_W1_ADRLEN_2BYTE 0x00000002U /*!< 2-byte address */ +#define QSPI_CMD_W1_ADRLEN_3BYTE 0x00000003U /*!< 3-byte address */ +#define QSPI_CMD_W1_ADRLEN_4BYTE 0x00000004U /*!< 4-byte address */ + +/*!< DUM2 congiguration */ +#define QSPI_CMD_W1_DUM2_Pos (16U) +#define QSPI_CMD_W1_DUM2_Msk (0xFFU << QSPI_CMD_W1_DUM2_Pos) /*!< 0x00FF0000 */ +#define QSPI_CMD_W1_DUM2 QSPI_CMD_W1_DUM2_Msk /*!< DUM2[7:0] bits (Second dummy state cycle) */ +#define QSPI_CMD_W1_DUM2_0 (0x01U << QSPI_CMD_W1_DUM2_Pos) /*!< 0x00010000 */ +#define QSPI_CMD_W1_DUM2_1 (0x02U << QSPI_CMD_W1_DUM2_Pos) /*!< 0x00020000 */ +#define QSPI_CMD_W1_DUM2_2 (0x04U << QSPI_CMD_W1_DUM2_Pos) /*!< 0x00040000 */ +#define QSPI_CMD_W1_DUM2_3 (0x08U << QSPI_CMD_W1_DUM2_Pos) /*!< 0x00080000 */ +#define QSPI_CMD_W1_DUM2_4 (0x10U << QSPI_CMD_W1_DUM2_Pos) /*!< 0x00100000 */ +#define QSPI_CMD_W1_DUM2_5 (0x20U << QSPI_CMD_W1_DUM2_Pos) /*!< 0x00200000 */ +#define QSPI_CMD_W1_DUM2_6 (0x40U << QSPI_CMD_W1_DUM2_Pos) /*!< 0x00400000 */ +#define QSPI_CMD_W1_DUM2_7 (0x80U << QSPI_CMD_W1_DUM2_Pos) /*!< 0x00800000 */ + +/*!< INSLEN congiguration */ +#define QSPI_CMD_W1_INSLEN_Pos (24U) +#define QSPI_CMD_W1_INSLEN_Msk (0x3U << QSPI_CMD_W1_INSLEN_Pos) /*!< 0x03000000 */ +#define QSPI_CMD_W1_INSLEN QSPI_CMD_W1_INSLEN_Msk /*!< INSLEN[1:0] bits (Instruction code length) */ +#define QSPI_CMD_W1_INSLEN_0 (0x1U << QSPI_CMD_W1_INSLEN_Pos) /*!< 0x01000000 */ +#define QSPI_CMD_W1_INSLEN_1 (0x2U << QSPI_CMD_W1_INSLEN_Pos) /*!< 0x02000000 */ + +#define QSPI_CMD_W1_INSLEN_NOINS 0x00000000U /*!< No instruction code */ +#define QSPI_CMD_W1_INSLEN_1INS 0x01000000U /*!< 1-byte instruction code */ +#define QSPI_CMD_W1_INSLEN_2INS 0x02000000U /*!< 2-byte instruction code (repeated instruction code) */ + +#define QSPI_CMD_W1_PEMEN_Pos (28U) +#define QSPI_CMD_W1_PEMEN_Msk (0x1U << QSPI_CMD_W1_PEMEN_Pos) /*!< 0x10000000 */ +#define QSPI_CMD_W1_PEMEN QSPI_CMD_W1_PEMEN_Msk /*!< Performance enhanced mode enable */ + +/***************** Bit definition for QSPI_CMD_W2 register ******************/ +#define QSPI_CMD_W2_DCNT_Pos (0U) +#define QSPI_CMD_W2_DCNT_Msk (0xFFFFFFFFU << QSPI_CMD_W2_DCNT_Pos) /*!< 0xFFFFFFFF */ +#define QSPI_CMD_W2_DCNT QSPI_CMD_W2_DCNT_Msk /*!< Read/Write data counter */ + +/***************** Bit definition for QSPI_CMD_W3 register ******************/ +#define QSPI_CMD_W3_WEN_Pos (1U) +#define QSPI_CMD_W3_WEN_Msk (0x1U << QSPI_CMD_W3_WEN_Pos) /*!< 0x00000002 */ +#define QSPI_CMD_W3_WEN QSPI_CMD_W3_WEN_Msk /*!< Write data enable */ +#define QSPI_CMD_W3_RSTSEN_Pos (2U) +#define QSPI_CMD_W3_RSTSEN_Msk (0x1U << QSPI_CMD_W3_RSTSEN_Pos) /*!< 0x00000004 */ +#define QSPI_CMD_W3_RSTSEN QSPI_CMD_W3_RSTSEN_Msk /*!< Read SPI status enable */ +#define QSPI_CMD_W3_RSTSC_Pos (3U) +#define QSPI_CMD_W3_RSTSC_Msk (0x1U << QSPI_CMD_W3_RSTSC_Pos) /*!< 0x00000008 */ +#define QSPI_CMD_W3_RSTSC QSPI_CMD_W3_RSTSC_Msk /*!< Read SPI status configuration */ + +/*!< OPMODE congiguration */ +#define QSPI_CMD_W3_OPMODE_Pos (5U) +#define QSPI_CMD_W3_OPMODE_Msk (0x7U << QSPI_CMD_W3_OPMODE_Pos) /*!< 0x000000E0 */ +#define QSPI_CMD_W3_OPMODE QSPI_CMD_W3_OPMODE_Msk /*!< OPMODE[2:0] bits (SPI Operation mode) */ +#define QSPI_CMD_W3_OPMODE_0 (0x1U << QSPI_CMD_W3_OPMODE_Pos) /*!< 0x00000020 */ +#define QSPI_CMD_W3_OPMODE_1 (0x2U << QSPI_CMD_W3_OPMODE_Pos) /*!< 0x00000040 */ +#define QSPI_CMD_W3_OPMODE_2 (0x4U << QSPI_CMD_W3_OPMODE_Pos) /*!< 0x00000080 */ + +#define QSPI_CMD_W3_OPMODE_SERIAL 0x00000000U /*!< Serial mode (1-1-1) */ +#define QSPI_CMD_W3_OPMODE_DUAL 0x00000020U /*!< Dual-wire mode (1-1-2) */ +#define QSPI_CMD_W3_OPMODE_QUAD 0x00000040U /*!< Quad mode (1-1-4) */ +#define QSPI_CMD_W3_OPMODE_DUALIO 0x00000060U /*!< Dual-wire I/O mode (1-2-2) */ +#define QSPI_CMD_W3_OPMODE_QUADIO 0x00000080U /*!< Quad I/O mode (1-4-4) */ +#define QSPI_CMD_W3_OPMODE_DPI 0x000000A0U /*!< DPI mode (2-2-2) */ +#define QSPI_CMD_W3_OPMODE_QPI 0x000000C0U /*!< QPI mode (4-4-4) */ + +#define QSPI_CMD_W3_PEMOPC_Pos (16U) +#define QSPI_CMD_W3_PEMOPC_Msk (0xFFU << QSPI_CMD_W3_PEMOPC_Pos) /*!< 0x00FF0000 */ +#define QSPI_CMD_W3_PEMOPC QSPI_CMD_W3_PEMOPC_Msk /*!< Performance enhanced mode operation code */ +#define QSPI_CMD_W3_INSC_Pos (24U) +#define QSPI_CMD_W3_INSC_Msk (0xFFU << QSPI_CMD_W3_INSC_Pos) /*!< 0xFF000000 */ +#define QSPI_CMD_W3_INSC QSPI_CMD_W3_INSC_Msk /*!< Instruction code */ + +/****************** Bit definition for QSPI_CTRL register *******************/ +/*!< CLKDIV congiguration */ +#define QSPI_CTRL_CLKDIV_Pos (0U) +#define QSPI_CTRL_CLKDIV_Msk (0x7U << QSPI_CTRL_CLKDIV_Pos) /*!< 0x00000007 */ +#define QSPI_CTRL_CLKDIV QSPI_CTRL_CLKDIV_Msk /*!< CLKDIV[2:0] bits (Clock divider) */ +#define QSPI_CTRL_CLKDIV_0 (0x1U << QSPI_CTRL_CLKDIV_Pos) /*!< 0x00000001 */ +#define QSPI_CTRL_CLKDIV_1 (0x2U << QSPI_CTRL_CLKDIV_Pos) /*!< 0x00000002 */ +#define QSPI_CTRL_CLKDIV_2 (0x4U << QSPI_CTRL_CLKDIV_Pos) /*!< 0x00000004 */ + +#define QSPI_CTRL_CLKDIV_DIV2 0x00000000U /*!< Clock is divided by 2 */ +#define QSPI_CTRL_CLKDIV_DIV4 0x00000001U /*!< Clock is divided by 4 */ +#define QSPI_CTRL_CLKDIV_DIV6 0x00000002U /*!< Clock is divided by 6 */ +#define QSPI_CTRL_CLKDIV_DIV8 0x00000003U /*!< Clock is divided by 8 */ +#define QSPI_CTRL_CLKDIV_DIV3 0x00000004U /*!< Clock is divided by 3 */ +#define QSPI_CTRL_CLKDIV_DIV5 0x00000005U /*!< Clock is divided by 5 */ +#define QSPI_CTRL_CLKDIV_DIV10 0x00000006U /*!< Clock is divided by 10 */ +#define QSPI_CTRL_CLKDIV_DIV12 0x00000007U /*!< Clock is divided by 12 */ + +#define QSPI_CTRL_SCKMODE_Pos (4U) +#define QSPI_CTRL_SCKMODE_Msk (0x1U << QSPI_CTRL_SCKMODE_Pos) /*!< 0x00000010 */ +#define QSPI_CTRL_SCKMODE QSPI_CTRL_SCKMODE_Msk /*!< SCK output mode */ +#define QSPI_CTRL_XIPIDLE_Pos (7U) +#define QSPI_CTRL_XIPIDLE_Msk (0x1U << QSPI_CTRL_XIPIDLE_Pos) /*!< 0x00000080 */ +#define QSPI_CTRL_XIPIDLE QSPI_CTRL_XIPIDLE_Msk /*!< XIP port idle status */ +#define QSPI_CTRL_ABORT_Pos (8U) +#define QSPI_CTRL_ABORT_Msk (0x1U << QSPI_CTRL_ABORT_Pos) /*!< 0x00000100 */ +#define QSPI_CTRL_ABORT QSPI_CTRL_ABORT_Msk /*!< Refresh all commands/FIFOs and reset state machine */ + +/*!< BUSY congiguration */ +#define QSPI_CTRL_BUSY_Pos (16U) +#define QSPI_CTRL_BUSY_Msk (0x7U << QSPI_CTRL_BUSY_Pos) /*!< 0x00070000 */ +#define QSPI_CTRL_BUSY QSPI_CTRL_BUSY_Msk /*!< BUSY[2:0] bits (Busy bit of SPI status) */ +#define QSPI_CTRL_BUSY_0 (0x1U << QSPI_CTRL_BUSY_Pos) /*!< 0x00010000 */ +#define QSPI_CTRL_BUSY_1 (0x2U << QSPI_CTRL_BUSY_Pos) /*!< 0x00020000 */ +#define QSPI_CTRL_BUSY_2 (0x4U << QSPI_CTRL_BUSY_Pos) /*!< 0x00040000 */ + +#define QSPI_CTRL_BUSY_BIT0 0x00000000U /*!< Bit 0 */ +#define QSPI_CTRL_BUSY_BIT1 0x00010000U /*!< Bit 1 */ +#define QSPI_CTRL_BUSY_BIT2 0x00020000U /*!< Bit 2 */ +#define QSPI_CTRL_BUSY_BIT3 0x00030000U /*!< Bit 3 */ +#define QSPI_CTRL_BUSY_BIT4 0x00040000U /*!< Bit 4 */ +#define QSPI_CTRL_BUSY_BIT5 0x00050000U /*!< Bit 5 */ +#define QSPI_CTRL_BUSY_BIT6 0x00060000U /*!< Bit 6 */ +#define QSPI_CTRL_BUSY_BIT7 0x00070000U /*!< Bit 7 */ + +#define QSPI_CTRL_XIPRCMDF_Pos (19U) +#define QSPI_CTRL_XIPRCMDF_Msk (0x1U << QSPI_CTRL_XIPRCMDF_Pos) /*!< 0x00080000 */ +#define QSPI_CTRL_XIPRCMDF QSPI_CTRL_XIPRCMDF_Msk /*!< XIP read command flush */ +#define QSPI_CTRL_XIPSEL_Pos (20U) +#define QSPI_CTRL_XIPSEL_Msk (0x1U << QSPI_CTRL_XIPSEL_Pos) /*!< 0x00100000 */ +#define QSPI_CTRL_XIPSEL QSPI_CTRL_XIPSEL_Msk /*!< XIP port selection */ +#define QSPI_CTRL_KEYEN_Pos (21U) +#define QSPI_CTRL_KEYEN_Msk (0x1U << QSPI_CTRL_KEYEN_Pos) /*!< 0x00200000 */ +#define QSPI_CTRL_KEYEN QSPI_CTRL_KEYEN_Msk /*!< SPI data encryption key enable */ + +/***************** Bit definition for QSPI_FIFOSTS register *****************/ +#define QSPI_FIFOSTS_TXFIFORDY_Pos (0U) +#define QSPI_FIFOSTS_TXFIFORDY_Msk (0x1U << QSPI_FIFOSTS_TXFIFORDY_Pos) /*!< 0x00000001 */ +#define QSPI_FIFOSTS_TXFIFORDY QSPI_FIFOSTS_TXFIFORDY_Msk /*!< TX FIFO ready status */ +#define QSPI_FIFOSTS_RXFIFORDY_Pos (1U) +#define QSPI_FIFOSTS_RXFIFORDY_Msk (0x1U << QSPI_FIFOSTS_RXFIFORDY_Pos) /*!< 0x00000002 */ +#define QSPI_FIFOSTS_RXFIFORDY QSPI_FIFOSTS_RXFIFORDY_Msk /*!< RX FIFO ready status */ + +/****************** Bit definition for QSPI_CTRL2 register ******************/ +#define QSPI_CTRL2_DMAEN_Pos (0U) +#define QSPI_CTRL2_DMAEN_Msk (0x1U << QSPI_CTRL2_DMAEN_Pos) /*!< 0x00000001 */ +#define QSPI_CTRL2_DMAEN QSPI_CTRL2_DMAEN_Msk /*!< DMA enable */ +#define QSPI_CTRL2_CMDIE_Pos (1U) +#define QSPI_CTRL2_CMDIE_Msk (0x1U << QSPI_CTRL2_CMDIE_Pos) /*!< 0x00000002 */ +#define QSPI_CTRL2_CMDIE QSPI_CTRL2_CMDIE_Msk /*!< Command complete Interrupt enable */ + +/*!< TXFIFO_THOD congiguration */ +#define QSPI_CTRL2_TXFIFO_THOD_Pos (8U) +#define QSPI_CTRL2_TXFIFO_THOD_Msk (0x3U << QSPI_CTRL2_TXFIFO_THOD_Pos) /*!< 0x00000300 */ +#define QSPI_CTRL2_TXFIFO_THOD QSPI_CTRL2_TXFIFO_THOD_Msk /*!< TXFIFO_THOD[1:0] bits (Program the level value to trigger TX FIFO threshold IRQ) */ +#define QSPI_CTRL2_TXFIFO_THOD_0 (0x1U << QSPI_CTRL2_TXFIFO_THOD_Pos) /*!< 0x00000100 */ +#define QSPI_CTRL2_TXFIFO_THOD_1 (0x2U << QSPI_CTRL2_TXFIFO_THOD_Pos) /*!< 0x00000200 */ + +#define QSPI_CTRL2_TXFIFO_THOD_8WORD 0x00000000U /*!< 8 WORD */ +#define QSPI_CTRL2_TXFIFO_THOD_16WORD 0x00000100U /*!< 16 WORD */ +#define QSPI_CTRL2_TXFIFO_THOD_24WORD 0x00000200U /*!< 24 WORD */ + +/*!< RXFIFO_THOD congiguration */ +#define QSPI_CTRL2_RXFIFO_THOD_Pos (12U) +#define QSPI_CTRL2_RXFIFO_THOD_Msk (0x3U << QSPI_CTRL2_RXFIFO_THOD_Pos) /*!< 0x00003000 */ +#define QSPI_CTRL2_RXFIFO_THOD QSPI_CTRL2_RXFIFO_THOD_Msk /*!< RXFIFO_THOD[1:0] bits (Program the level value to trigger RX FIFO threshold IRQ) */ +#define QSPI_CTRL2_RXFIFO_THOD_0 (0x1U << QSPI_CTRL2_RXFIFO_THOD_Pos) /*!< 0x00001000 */ +#define QSPI_CTRL2_RXFIFO_THOD_1 (0x2U << QSPI_CTRL2_RXFIFO_THOD_Pos) /*!< 0x00002000 */ + +#define QSPI_CTRL2_RXFIFO_THOD_8WORD 0x00000000U /*!< 8 WORD */ +#define QSPI_CTRL2_RXFIFO_THOD_16WORD 0x00001000U /*!< 16 WORD */ +#define QSPI_CTRL2_RXFIFO_THOD_24WORD 0x00002000U /*!< 24 WORD */ + +/***************** Bit definition for QSPI_CMDSTS register ******************/ +#define QSPI_CMDSTS_CMDSTS_Pos (0U) +#define QSPI_CMDSTS_CMDSTS_Msk (0x1U << QSPI_CMDSTS_CMDSTS_Pos) /*!< 0x00000001 */ +#define QSPI_CMDSTS_CMDSTS QSPI_CMDSTS_CMDSTS_Msk /*!< Command complete status */ + +/****************** Bit definition for QSPI_RSTS register *******************/ +#define QSPI_RSTS_SPISTS_Pos (0U) +#define QSPI_RSTS_SPISTS_Msk (0xFFU << QSPI_RSTS_SPISTS_Pos) /*!< 0x000000FF */ +#define QSPI_RSTS_SPISTS QSPI_RSTS_SPISTS_Msk /*!< SPI read status */ + +/****************** Bit definition for QSPI_FSIZE register ******************/ +#define QSPI_FSIZE_SPIFSIZE_Pos (0U) /*!< 0xFFFFFFFF */ +#define QSPI_FSIZE_SPIFSIZE_Msk (0xFFFFFFFFU << QSPI_FSIZE_SPIFSIZE_Pos) +#define QSPI_FSIZE_SPIFSIZE QSPI_FSIZE_SPIFSIZE_Msk /*!< SPI flash size */ + +/*************** Bit definition for QSPI_XIP_CMD_W0 register ****************/ +/*!< XIPR_DUM2 congiguration */ +#define QSPI_XIP_CMD_W0_XIPR_DUM2_Pos (0U) +#define QSPI_XIP_CMD_W0_XIPR_DUM2_Msk (0xFFU << QSPI_XIP_CMD_W0_XIPR_DUM2_Pos) /*!< 0x000000FF */ +#define QSPI_XIP_CMD_W0_XIPR_DUM2 QSPI_XIP_CMD_W0_XIPR_DUM2_Msk /*!< XIPR_DUM2[7:0] bits (XIP read second dummy cycle) */ +#define QSPI_XIP_CMD_W0_XIPR_DUM2_0 (0x01U << QSPI_XIP_CMD_W0_XIPR_DUM2_Pos) /*!< 0x00000001 */ +#define QSPI_XIP_CMD_W0_XIPR_DUM2_1 (0x02U << QSPI_XIP_CMD_W0_XIPR_DUM2_Pos) /*!< 0x00000002 */ +#define QSPI_XIP_CMD_W0_XIPR_DUM2_2 (0x04U << QSPI_XIP_CMD_W0_XIPR_DUM2_Pos) /*!< 0x00000004 */ +#define QSPI_XIP_CMD_W0_XIPR_DUM2_3 (0x08U << QSPI_XIP_CMD_W0_XIPR_DUM2_Pos) /*!< 0x00000008 */ +#define QSPI_XIP_CMD_W0_XIPR_DUM2_4 (0x10U << QSPI_XIP_CMD_W0_XIPR_DUM2_Pos) /*!< 0x00000010 */ +#define QSPI_XIP_CMD_W0_XIPR_DUM2_5 (0x20U << QSPI_XIP_CMD_W0_XIPR_DUM2_Pos) /*!< 0x00000020 */ +#define QSPI_XIP_CMD_W0_XIPR_DUM2_6 (0x40U << QSPI_XIP_CMD_W0_XIPR_DUM2_Pos) /*!< 0x00000040 */ +#define QSPI_XIP_CMD_W0_XIPR_DUM2_7 (0x80U << QSPI_XIP_CMD_W0_XIPR_DUM2_Pos) /*!< 0x00000080 */ + +/*!< XIPR_OPMODE congiguration */ +#define QSPI_XIP_CMD_W0_XIPR_OPMODE_Pos (8U) /*!< 0x00000700 */ +#define QSPI_XIP_CMD_W0_XIPR_OPMODE_Msk (0x7U << QSPI_XIP_CMD_W0_XIPR_OPMODE_Pos) +#define QSPI_XIP_CMD_W0_XIPR_OPMODE QSPI_XIP_CMD_W0_XIPR_OPMODE_Msk /*!< XIPR_OPMODE[2:0] bits (XIP read operation mode) */ +#define QSPI_XIP_CMD_W0_XIPR_OPMODE_0 (0x1U << QSPI_XIP_CMD_W0_XIPR_OPMODE_Pos) /*!< 0x00000100 */ +#define QSPI_XIP_CMD_W0_XIPR_OPMODE_1 (0x2U << QSPI_XIP_CMD_W0_XIPR_OPMODE_Pos) /*!< 0x00000200 */ +#define QSPI_XIP_CMD_W0_XIPR_OPMODE_2 (0x4U << QSPI_XIP_CMD_W0_XIPR_OPMODE_Pos) /*!< 0x00000400 */ + +#define QSPI_XIP_CMD_W0_XIPR_OPMODE_SERIAL 0x00000000U /*!< Serial mode (1-1-1) */ +#define QSPI_XIP_CMD_W0_XIPR_OPMODE_DUAL 0x00000100U /*!< Dual-wire mode (1-1-2) */ +#define QSPI_XIP_CMD_W0_XIPR_OPMODE_QUAD 0x00000200U /*!< Quad mode (1-1-4) */ +#define QSPI_XIP_CMD_W0_XIPR_OPMODE_DUALIO 0x00000300U /*!< Dual-wire I/O mode (1-2-2) */ +#define QSPI_XIP_CMD_W0_XIPR_OPMODE_QUADIO 0x00000400U /*!< Quad I/O mode (1-4-4) */ +#define QSPI_XIP_CMD_W0_XIPR_OPMODE_DPI 0x00000500U /*!< DPI mode (2-2-2) */ +#define QSPI_XIP_CMD_W0_XIPR_OPMODE_QPI 0x00000600U /*!< QPI mode (4-4-4) */ + +#define QSPI_XIP_CMD_W0_XIPR_ADRLEN_Pos (11U) /*!< 0x00000800 */ +#define QSPI_XIP_CMD_W0_XIPR_ADRLEN_Msk (0x1U << QSPI_XIP_CMD_W0_XIPR_ADRLEN_Pos) +#define QSPI_XIP_CMD_W0_XIPR_ADRLEN QSPI_XIP_CMD_W0_XIPR_ADRLEN_Msk /*!< XIP read address length */ +#define QSPI_XIP_CMD_W0_XIPR_INSC_Pos (12U) /*!< 0x000FF000 */ +#define QSPI_XIP_CMD_W0_XIPR_INSC_Msk (0xFFU << QSPI_XIP_CMD_W0_XIPR_INSC_Pos) +#define QSPI_XIP_CMD_W0_XIPR_INSC QSPI_XIP_CMD_W0_XIPR_INSC_Msk /*!< XIP read instruction code */ + +/*************** Bit definition for QSPI_XIP_CMD_W1 register ****************/ +/*!< XIPW_DUM2 congiguration */ +#define QSPI_XIP_CMD_W1_XIPW_DUM2_Pos (0U) +#define QSPI_XIP_CMD_W1_XIPW_DUM2_Msk (0xFFU << QSPI_XIP_CMD_W1_XIPW_DUM2_Pos) /*!< 0x000000FF */ +#define QSPI_XIP_CMD_W1_XIPW_DUM2 QSPI_XIP_CMD_W1_XIPW_DUM2_Msk /*!< XIPW_DUM2[7:0] bits (XIP write second dummy cycle) */ +#define QSPI_XIP_CMD_W1_XIPW_DUM2_0 (0x01U << QSPI_XIP_CMD_W1_XIPW_DUM2_Pos) /*!< 0x00000001 */ +#define QSPI_XIP_CMD_W1_XIPW_DUM2_1 (0x02U << QSPI_XIP_CMD_W1_XIPW_DUM2_Pos) /*!< 0x00000002 */ +#define QSPI_XIP_CMD_W1_XIPW_DUM2_2 (0x04U << QSPI_XIP_CMD_W1_XIPW_DUM2_Pos) /*!< 0x00000004 */ +#define QSPI_XIP_CMD_W1_XIPW_DUM2_3 (0x08U << QSPI_XIP_CMD_W1_XIPW_DUM2_Pos) /*!< 0x00000008 */ +#define QSPI_XIP_CMD_W1_XIPW_DUM2_4 (0x10U << QSPI_XIP_CMD_W1_XIPW_DUM2_Pos) /*!< 0x00000010 */ +#define QSPI_XIP_CMD_W1_XIPW_DUM2_5 (0x20U << QSPI_XIP_CMD_W1_XIPW_DUM2_Pos) /*!< 0x00000020 */ +#define QSPI_XIP_CMD_W1_XIPW_DUM2_6 (0x40U << QSPI_XIP_CMD_W1_XIPW_DUM2_Pos) /*!< 0x00000040 */ +#define QSPI_XIP_CMD_W1_XIPW_DUM2_7 (0x80U << QSPI_XIP_CMD_W1_XIPW_DUM2_Pos) /*!< 0x00000080 */ + +/*!< XIPW_OPMODE congiguration */ +#define QSPI_XIP_CMD_W1_XIPW_OPMODE_Pos (8U) /*!< 0x00000700 */ +#define QSPI_XIP_CMD_W1_XIPW_OPMODE_Msk (0x7U << QSPI_XIP_CMD_W1_XIPW_OPMODE_Pos) +#define QSPI_XIP_CMD_W1_XIPW_OPMODE QSPI_XIP_CMD_W1_XIPW_OPMODE_Msk /*!< XIPW_OPMODE[2:0] bits (XIP write operation mode) */ +#define QSPI_XIP_CMD_W1_XIPW_OPMODE_0 (0x1U << QSPI_XIP_CMD_W1_XIPW_OPMODE_Pos) /*!< 0x00000100 */ +#define QSPI_XIP_CMD_W1_XIPW_OPMODE_1 (0x2U << QSPI_XIP_CMD_W1_XIPW_OPMODE_Pos) /*!< 0x00000200 */ +#define QSPI_XIP_CMD_W1_XIPW_OPMODE_2 (0x4U << QSPI_XIP_CMD_W1_XIPW_OPMODE_Pos) /*!< 0x00000400 */ + +#define QSPI_XIP_CMD_W1_XIPW_OPMODE_SERIAL 0x00000000U /*!< Serial mode (1-1-1) */ +#define QSPI_XIP_CMD_W1_XIPW_OPMODE_DUAL 0x00000100U /*!< Dual-wire mode (1-1-2) */ +#define QSPI_XIP_CMD_W1_XIPW_OPMODE_QUAD 0x00000200U /*!< Quad mode (1-1-4) */ +#define QSPI_XIP_CMD_W1_XIPW_OPMODE_DUALIO 0x00000300U /*!< Dual-wire I/O mode (1-2-2) */ +#define QSPI_XIP_CMD_W1_XIPW_OPMODE_QUADIO 0x00000400U /*!< Quad I/O mode (1-4-4) */ +#define QSPI_XIP_CMD_W1_XIPW_OPMODE_DPI 0x00000500U /*!< DPI mode (2-2-2) */ +#define QSPI_XIP_CMD_W1_XIPW_OPMODE_QPI 0x00000600U /*!< QPI mode (4-4-4) */ + +#define QSPI_XIP_CMD_W1_XIPW_ADRLEN_Pos (11U) /*!< 0x00000800 */ +#define QSPI_XIP_CMD_W1_XIPW_ADRLEN_Msk (0x1U << QSPI_XIP_CMD_W1_XIPW_ADRLEN_Pos) +#define QSPI_XIP_CMD_W1_XIPW_ADRLEN QSPI_XIP_CMD_W1_XIPW_ADRLEN_Msk /*!< XIP write address length */ +#define QSPI_XIP_CMD_W1_XIPW_INSC_Pos (12U) /*!< 0x000FF000 */ +#define QSPI_XIP_CMD_W1_XIPW_INSC_Msk (0xFFU << QSPI_XIP_CMD_W1_XIPW_INSC_Pos) +#define QSPI_XIP_CMD_W1_XIPW_INSC QSPI_XIP_CMD_W1_XIPW_INSC_Msk /*!< XIP write instruction code */ + +/*************** Bit definition for QSPI_XIP_CMD_W2 register ****************/ +#define QSPI_XIP_CMD_W2_XIPR_DCNT_Pos (0U) /*!< 0x0000003F */ +#define QSPI_XIP_CMD_W2_XIPR_DCNT_Msk (0x3FU << QSPI_XIP_CMD_W2_XIPR_DCNT_Pos) +#define QSPI_XIP_CMD_W2_XIPR_DCNT QSPI_XIP_CMD_W2_XIPR_DCNT_Msk /*!< Indicates the time counter to judge maximum data count in mode D */ +#define QSPI_XIP_CMD_W2_XIPR_TCNT_Pos (8U) /*!< 0x00007F00 */ +#define QSPI_XIP_CMD_W2_XIPR_TCNT_Msk (0x7FU << QSPI_XIP_CMD_W2_XIPR_TCNT_Pos) +#define QSPI_XIP_CMD_W2_XIPR_TCNT QSPI_XIP_CMD_W2_XIPR_TCNT_Msk /*!< Indicates the time counter to judge time interval in mode T */ +#define QSPI_XIP_CMD_W2_XIPR_SEL_Pos (15U) +#define QSPI_XIP_CMD_W2_XIPR_SEL_Msk (0x1U << QSPI_XIP_CMD_W2_XIPR_SEL_Pos) /*!< 0x00008000 */ +#define QSPI_XIP_CMD_W2_XIPR_SEL QSPI_XIP_CMD_W2_XIPR_SEL_Msk /*!< XIP read mode select */ +#define QSPI_XIP_CMD_W2_XIPW_DCNT_Pos (16U) /*!< 0x003F0000 */ +#define QSPI_XIP_CMD_W2_XIPW_DCNT_Msk (0x3FU << QSPI_XIP_CMD_W2_XIPW_DCNT_Pos) +#define QSPI_XIP_CMD_W2_XIPW_DCNT QSPI_XIP_CMD_W2_XIPW_DCNT_Msk /*!< Indicates the time counter to judge maximum data count in mode D */ +#define QSPI_XIP_CMD_W2_XIPW_TCNT_Pos (24U) /*!< 0x7F000000 */ +#define QSPI_XIP_CMD_W2_XIPW_TCNT_Msk (0x7FU << QSPI_XIP_CMD_W2_XIPW_TCNT_Pos) +#define QSPI_XIP_CMD_W2_XIPW_TCNT QSPI_XIP_CMD_W2_XIPW_TCNT_Msk /*!< Indicates the time counter to judge time interval in mode T */ +#define QSPI_XIP_CMD_W2_XIPW_SEL_Pos (31U) +#define QSPI_XIP_CMD_W2_XIPW_SEL_Msk (0x1U << QSPI_XIP_CMD_W2_XIPW_SEL_Pos) /*!< 0x80000000 */ +#define QSPI_XIP_CMD_W2_XIPW_SEL QSPI_XIP_CMD_W2_XIPW_SEL_Msk /*!< XIP write mode select */ + +/*************** Bit definition for QSPI_XIP_CMD_W3 register ****************/ +#define QSPI_XIP_CMD_W3_BYPASSC_Pos (0U) +#define QSPI_XIP_CMD_W3_BYPASSC_Msk (0x1U << QSPI_XIP_CMD_W3_BYPASSC_Pos) /*!< 0x00000001 */ +#define QSPI_XIP_CMD_W3_BYPASSC QSPI_XIP_CMD_W3_BYPASSC_Msk /*!< Bypass cache function */ +#define QSPI_XIP_CMD_W3_CSTS_Pos (3U) +#define QSPI_XIP_CMD_W3_CSTS_Msk (0x1U << QSPI_XIP_CMD_W3_CSTS_Pos) /*!< 0x00000008 */ +#define QSPI_XIP_CMD_W3_CSTS QSPI_XIP_CMD_W3_CSTS_Msk /*!< Cache status */ + +/****************** Bit definition for QSPI_CTRL3 register ******************/ +#define QSPI_CTRL3_ISPC_Pos (8U) +#define QSPI_CTRL3_ISPC_Msk (0x1U << QSPI_CTRL3_ISPC_Pos) /*!< 0x00000100 */ +#define QSPI_CTRL3_ISPC QSPI_CTRL3_ISPC_Msk /*!< ISPC */ + +/******************* Bit definition for QSPI_REV register *******************/ +#define QSPI_REV_REV_Pos (0U) +#define QSPI_REV_REV_Msk (0xFFFFFFFFU << QSPI_REV_REV_Pos) /*!< 0xFFFFFFFF */ +#define QSPI_REV_REV QSPI_REV_REV_Msk /*!< Indicates IP version */ + +/******************* Bit definition for QSPI_DT register ********************/ +#define QSPI_DT_DT_Pos (0U) +#define QSPI_DT_DT_Msk (0xFFFFFFFFU << QSPI_DT_DT_Pos) /*!< 0xFFFFFFFF */ +#define QSPI_DT_DT QSPI_DT_DT_Msk /*!< Data port register */ + +/******************************************************************************/ +/* */ +/* Debug MCU (DEBUG) */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for DEBUG_IDCODE register *****************/ +/*!< PID congiguration */ +#define DEBUG_IDCODE_PID_Pos (0U) +#define DEBUG_IDCODE_PID_Msk (0xFFFFFFFFU << DEBUG_IDCODE_PID_Pos) /*!< 0xFFFFFFFF */ +#define DEBUG_IDCODE_PID DEBUG_IDCODE_PID_Msk /*!< PID[31:0] bits (PID information) */ +#define DEBUG_IDCODE_PID_0 (0x00000001U << DEBUG_IDCODE_PID_Pos) /*!< 0x00000001 */ +#define DEBUG_IDCODE_PID_1 (0x00000002U << DEBUG_IDCODE_PID_Pos) /*!< 0x00000002 */ +#define DEBUG_IDCODE_PID_2 (0x00000004U << DEBUG_IDCODE_PID_Pos) /*!< 0x00000004 */ +#define DEBUG_IDCODE_PID_3 (0x00000008U << DEBUG_IDCODE_PID_Pos) /*!< 0x00000008 */ +#define DEBUG_IDCODE_PID_4 (0x00000010U << DEBUG_IDCODE_PID_Pos) /*!< 0x00000010 */ +#define DEBUG_IDCODE_PID_5 (0x00000020U << DEBUG_IDCODE_PID_Pos) /*!< 0x00000020 */ +#define DEBUG_IDCODE_PID_6 (0x00000040U << DEBUG_IDCODE_PID_Pos) /*!< 0x00000040 */ +#define DEBUG_IDCODE_PID_7 (0x00000080U << DEBUG_IDCODE_PID_Pos) /*!< 0x00000080 */ +#define DEBUG_IDCODE_PID_8 (0x00000100U << DEBUG_IDCODE_PID_Pos) /*!< 0x00000100 */ +#define DEBUG_IDCODE_PID_9 (0x00000200U << DEBUG_IDCODE_PID_Pos) /*!< 0x00000200 */ +#define DEBUG_IDCODE_PID_10 (0x00000400U << DEBUG_IDCODE_PID_Pos) /*!< 0x00000400 */ +#define DEBUG_IDCODE_PID_11 (0x00000800U << DEBUG_IDCODE_PID_Pos) /*!< 0x00000800 */ +#define DEBUG_IDCODE_PID_12 (0x00001000U << DEBUG_IDCODE_PID_Pos) /*!< 0x00001000 */ +#define DEBUG_IDCODE_PID_13 (0x00002000U << DEBUG_IDCODE_PID_Pos) /*!< 0x00002000 */ +#define DEBUG_IDCODE_PID_14 (0x00004000U << DEBUG_IDCODE_PID_Pos) /*!< 0x00004000 */ +#define DEBUG_IDCODE_PID_15 (0x00008000U << DEBUG_IDCODE_PID_Pos) /*!< 0x00008000 */ +#define DEBUG_IDCODE_PID_16 (0x00010000U << DEBUG_IDCODE_PID_Pos) /*!< 0x00010000 */ +#define DEBUG_IDCODE_PID_17 (0x00020000U << DEBUG_IDCODE_PID_Pos) /*!< 0x00020000 */ +#define DEBUG_IDCODE_PID_18 (0x00040000U << DEBUG_IDCODE_PID_Pos) /*!< 0x00040000 */ +#define DEBUG_IDCODE_PID_19 (0x00080000U << DEBUG_IDCODE_PID_Pos) /*!< 0x00080000 */ +#define DEBUG_IDCODE_PID_20 (0x00100000U << DEBUG_IDCODE_PID_Pos) /*!< 0x00100000 */ +#define DEBUG_IDCODE_PID_21 (0x00200000U << DEBUG_IDCODE_PID_Pos) /*!< 0x00200000 */ +#define DEBUG_IDCODE_PID_22 (0x00400000U << DEBUG_IDCODE_PID_Pos) /*!< 0x00400000 */ +#define DEBUG_IDCODE_PID_23 (0x00800000U << DEBUG_IDCODE_PID_Pos) /*!< 0x00800000 */ +#define DEBUG_IDCODE_PID_24 (0x01000000U << DEBUG_IDCODE_PID_Pos) /*!< 0x01000000 */ +#define DEBUG_IDCODE_PID_25 (0x02000000U << DEBUG_IDCODE_PID_Pos) /*!< 0x02000000 */ +#define DEBUG_IDCODE_PID_26 (0x04000000U << DEBUG_IDCODE_PID_Pos) /*!< 0x04000000 */ +#define DEBUG_IDCODE_PID_27 (0x08000000U << DEBUG_IDCODE_PID_Pos) /*!< 0x08000000 */ +#define DEBUG_IDCODE_PID_28 (0x10000000U << DEBUG_IDCODE_PID_Pos) /*!< 0x10000000 */ +#define DEBUG_IDCODE_PID_29 (0x20000000U << DEBUG_IDCODE_PID_Pos) /*!< 0x20000000 */ +#define DEBUG_IDCODE_PID_30 (0x40000000U << DEBUG_IDCODE_PID_Pos) /*!< 0x40000000 */ +#define DEBUG_IDCODE_PID_31 (0x80000000U << DEBUG_IDCODE_PID_Pos) /*!< 0x80000000 */ + +/****************** Bit definition for DEBUG_CTRL register ******************/ +#define DEBUG_CTRL_SLEEP_DEBUG_Pos (0U) +#define DEBUG_CTRL_SLEEP_DEBUG_Msk (0x1U << DEBUG_CTRL_SLEEP_DEBUG_Pos) /*!< 0x00000001 */ +#define DEBUG_CTRL_SLEEP_DEBUG DEBUG_CTRL_SLEEP_DEBUG_Msk /*!< Debug Sleep mode control bit */ +#define DEBUG_CTRL_DEEPSLEEP_DEBUG_Pos (1U) /*!< 0x00000002 */ +#define DEBUG_CTRL_DEEPSLEEP_DEBUG_Msk (0x1U << DEBUG_CTRL_DEEPSLEEP_DEBUG_Pos) +#define DEBUG_CTRL_DEEPSLEEP_DEBUG DEBUG_CTRL_DEEPSLEEP_DEBUG_Msk /*!< Debug Deep sleep mode control bit */ +#define DEBUG_CTRL_STANDBY_DEBUG_Pos (2U) +#define DEBUG_CTRL_STANDBY_DEBUG_Msk (0x1U << DEBUG_CTRL_STANDBY_DEBUG_Pos) /*!< 0x00000004 */ +#define DEBUG_CTRL_STANDBY_DEBUG DEBUG_CTRL_STANDBY_DEBUG_Msk /*!< Debug Standby mode control bit */ + +/*************** Bit definition for DEBUG_APB1_PAUSE register ***************/ +#define DEBUG_APB1_PAUSE_TMR2_PAUSE_Pos (0U) /*!< 0x00000001 */ +#define DEBUG_APB1_PAUSE_TMR2_PAUSE_Msk (0x1U << DEBUG_APB1_PAUSE_TMR2_PAUSE_Pos) +#define DEBUG_APB1_PAUSE_TMR2_PAUSE DEBUG_APB1_PAUSE_TMR2_PAUSE_Msk /*!< TMR2 pause control bit */ +#define DEBUG_APB1_PAUSE_TMR3_PAUSE_Pos (1U) /*!< 0x00000002 */ +#define DEBUG_APB1_PAUSE_TMR3_PAUSE_Msk (0x1U << DEBUG_APB1_PAUSE_TMR3_PAUSE_Pos) +#define DEBUG_APB1_PAUSE_TMR3_PAUSE DEBUG_APB1_PAUSE_TMR3_PAUSE_Msk /*!< TMR3 pause control bit */ +#define DEBUG_APB1_PAUSE_TMR4_PAUSE_Pos (2U) /*!< 0x00000004 */ +#define DEBUG_APB1_PAUSE_TMR4_PAUSE_Msk (0x1U << DEBUG_APB1_PAUSE_TMR4_PAUSE_Pos) +#define DEBUG_APB1_PAUSE_TMR4_PAUSE DEBUG_APB1_PAUSE_TMR4_PAUSE_Msk /*!< TMR4 pause control bit */ +#define DEBUG_APB1_PAUSE_TMR6_PAUSE_Pos (4U) /*!< 0x00000010 */ +#define DEBUG_APB1_PAUSE_TMR6_PAUSE_Msk (0x1U << DEBUG_APB1_PAUSE_TMR6_PAUSE_Pos) +#define DEBUG_APB1_PAUSE_TMR6_PAUSE DEBUG_APB1_PAUSE_TMR6_PAUSE_Msk /*!< TMR6 pause control bit */ +#define DEBUG_APB1_PAUSE_TMR7_PAUSE_Pos (5U) /*!< 0x00000020 */ +#define DEBUG_APB1_PAUSE_TMR7_PAUSE_Msk (0x1U << DEBUG_APB1_PAUSE_TMR7_PAUSE_Pos) +#define DEBUG_APB1_PAUSE_TMR7_PAUSE DEBUG_APB1_PAUSE_TMR7_PAUSE_Msk /*!< TMR7 pause control bit */ +#define DEBUG_APB1_PAUSE_TMR13_PAUSE_Pos (7U) /*!< 0x00000080 */ +#define DEBUG_APB1_PAUSE_TMR13_PAUSE_Msk (0x1U << DEBUG_APB1_PAUSE_TMR13_PAUSE_Pos) +#define DEBUG_APB1_PAUSE_TMR13_PAUSE DEBUG_APB1_PAUSE_TMR13_PAUSE_Msk /*!< TMR13 pause control bit */ +#define DEBUG_APB1_PAUSE_TMR14_PAUSE_Pos (8U) /*!< 0x00000100 */ +#define DEBUG_APB1_PAUSE_TMR14_PAUSE_Msk (0x1U << DEBUG_APB1_PAUSE_TMR14_PAUSE_Pos) +#define DEBUG_APB1_PAUSE_TMR14_PAUSE DEBUG_APB1_PAUSE_TMR14_PAUSE_Msk /*!< TMR14 pause control bit */ +#define DEBUG_APB1_PAUSE_ERTC_PAUSE_Pos (10U) /*!< 0x00000400 */ +#define DEBUG_APB1_PAUSE_ERTC_PAUSE_Msk (0x1U << DEBUG_APB1_PAUSE_ERTC_PAUSE_Pos) +#define DEBUG_APB1_PAUSE_ERTC_PAUSE DEBUG_APB1_PAUSE_ERTC_PAUSE_Msk /*!< ERTC pause control bit */ +#define DEBUG_APB1_PAUSE_WWDT_PAUSE_Pos (11U) /*!< 0x00000800 */ +#define DEBUG_APB1_PAUSE_WWDT_PAUSE_Msk (0x1U << DEBUG_APB1_PAUSE_WWDT_PAUSE_Pos) +#define DEBUG_APB1_PAUSE_WWDT_PAUSE DEBUG_APB1_PAUSE_WWDT_PAUSE_Msk /*!< Window watchdog pause control bit */ +#define DEBUG_APB1_PAUSE_WDT_PAUSE_Pos (12U) /*!< 0x00001000 */ +#define DEBUG_APB1_PAUSE_WDT_PAUSE_Msk (0x1U << DEBUG_APB1_PAUSE_WDT_PAUSE_Pos) +#define DEBUG_APB1_PAUSE_WDT_PAUSE DEBUG_APB1_PAUSE_WDT_PAUSE_Msk /*!< Watchdog pause control bit */ +#define DEBUG_APB1_PAUSE_I2C1_SMBUS_TIMEOUT_Pos (24U) /*!< 0x01000000 */ +#define DEBUG_APB1_PAUSE_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DEBUG_APB1_PAUSE_I2C1_SMBUS_TIMEOUT_Pos) +#define DEBUG_APB1_PAUSE_I2C1_SMBUS_TIMEOUT DEBUG_APB1_PAUSE_I2C1_SMBUS_TIMEOUT_Msk /*!< I2C1 pause control bit */ +#define DEBUG_APB1_PAUSE_CAN1_PAUSE_Pos (25U) /*!< 0x02000000 */ +#define DEBUG_APB1_PAUSE_CAN1_PAUSE_Msk (0x1U << DEBUG_APB1_PAUSE_CAN1_PAUSE_Pos) +#define DEBUG_APB1_PAUSE_CAN1_PAUSE DEBUG_APB1_PAUSE_CAN1_PAUSE_Msk /*!< CAN1 pause control bit */ +#define DEBUG_APB1_PAUSE_I2C2_SMBUS_TIMEOUT_Pos (27U) /*!< 0x08000000 */ +#define DEBUG_APB1_PAUSE_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DEBUG_APB1_PAUSE_I2C2_SMBUS_TIMEOUT_Pos) +#define DEBUG_APB1_PAUSE_I2C2_SMBUS_TIMEOUT DEBUG_APB1_PAUSE_I2C2_SMBUS_TIMEOUT_Msk /*!< I2C2 pause control bit */ +#define DEBUG_APB1_PAUSE_I2C3_SMBUS_TIMEOUT_Pos (28U) /*!< 0x10000000 */ +#define DEBUG_APB1_PAUSE_I2C3_SMBUS_TIMEOUT_Msk (0x1U << DEBUG_APB1_PAUSE_I2C3_SMBUS_TIMEOUT_Pos) +#define DEBUG_APB1_PAUSE_I2C3_SMBUS_TIMEOUT DEBUG_APB1_PAUSE_I2C3_SMBUS_TIMEOUT_Msk /*!< I2C3 pause control bit */ + +/*************** Bit definition for DEBUG_APB2_PAUSE register ***************/ +#define DEBUG_APB2_PAUSE_TMR1_PAUSE_Pos (0U) /*!< 0x00000001 */ +#define DEBUG_APB2_PAUSE_TMR1_PAUSE_Msk (0x1U << DEBUG_APB2_PAUSE_TMR1_PAUSE_Pos) +#define DEBUG_APB2_PAUSE_TMR1_PAUSE DEBUG_APB2_PAUSE_TMR1_PAUSE_Msk /*!< TMR1 pause control bit */ +#define DEBUG_APB2_PAUSE_TMR9_PAUSE_Pos (16U) /*!< 0x00010000 */ +#define DEBUG_APB2_PAUSE_TMR9_PAUSE_Msk (0x1U << DEBUG_APB2_PAUSE_TMR9_PAUSE_Pos) +#define DEBUG_APB2_PAUSE_TMR9_PAUSE DEBUG_APB2_PAUSE_TMR9_PAUSE_Msk /*!< TMR9 pause control bit */ +#define DEBUG_APB2_PAUSE_TMR10_PAUSE_Pos (17U) /*!< 0x00020000 */ +#define DEBUG_APB2_PAUSE_TMR10_PAUSE_Msk (0x1U << DEBUG_APB2_PAUSE_TMR10_PAUSE_Pos) +#define DEBUG_APB2_PAUSE_TMR10_PAUSE DEBUG_APB2_PAUSE_TMR10_PAUSE_Msk /*!< TMR10 pause control bit */ +#define DEBUG_APB2_PAUSE_TMR11_PAUSE_Pos (18U) /*!< 0x00040000 */ +#define DEBUG_APB2_PAUSE_TMR11_PAUSE_Msk (0x1U << DEBUG_APB2_PAUSE_TMR11_PAUSE_Pos) +#define DEBUG_APB2_PAUSE_TMR11_PAUSE DEBUG_APB2_PAUSE_TMR11_PAUSE_Msk /*!< TMR11 pause control bit */ + +/***************** Bit definition for DEBUG_SER_ID register *****************/ +/*!< REV_ID congiguration */ +#define DEBUG_SER_ID_REV_ID_Pos (0U) +#define DEBUG_SER_ID_REV_ID_Msk (0x7U << DEBUG_SER_ID_REV_ID_Pos) /*!< 0x00000007 */ +#define DEBUG_SER_ID_REV_ID DEBUG_SER_ID_REV_ID_Msk /*!< REV_ID[2:0] bits (Revision ID) */ +#define DEBUG_SER_ID_REV_ID_0 (0x1U << DEBUG_SER_ID_REV_ID_Pos) /*!< 0x00000001 */ +#define DEBUG_SER_ID_REV_ID_1 (0x2U << DEBUG_SER_ID_REV_ID_Pos) /*!< 0x00000002 */ +#define DEBUG_SER_ID_REV_ID_2 (0x4U << DEBUG_SER_ID_REV_ID_Pos) /*!< 0x00000004 */ + +/*!< SER_ID congiguration */ +#define DEBUG_SER_ID_SER_ID_Pos (8U) +#define DEBUG_SER_ID_SER_ID_Msk (0xFFU << DEBUG_SER_ID_SER_ID_Pos) /*!< 0x0000FF00 */ +#define DEBUG_SER_ID_SER_ID DEBUG_SER_ID_SER_ID_Msk /*!< SER_ID[7:0] bits (Serial ID) */ +#define DEBUG_SER_ID_SER_ID_0 (0x01U << DEBUG_SER_ID_SER_ID_Pos) /*!< 0x00000100 */ +#define DEBUG_SER_ID_SER_ID_1 (0x02U << DEBUG_SER_ID_SER_ID_Pos) /*!< 0x00000200 */ +#define DEBUG_SER_ID_SER_ID_2 (0x04U << DEBUG_SER_ID_SER_ID_Pos) /*!< 0x00000400 */ +#define DEBUG_SER_ID_SER_ID_3 (0x08U << DEBUG_SER_ID_SER_ID_Pos) /*!< 0x00000800 */ +#define DEBUG_SER_ID_SER_ID_4 (0x10U << DEBUG_SER_ID_SER_ID_Pos) /*!< 0x00001000 */ +#define DEBUG_SER_ID_SER_ID_5 (0x20U << DEBUG_SER_ID_SER_ID_Pos) /*!< 0x00002000 */ +#define DEBUG_SER_ID_SER_ID_6 (0x40U << DEBUG_SER_ID_SER_ID_Pos) /*!< 0x00004000 */ +#define DEBUG_SER_ID_SER_ID_7 (0x80U << DEBUG_SER_ID_SER_ID_Pos) /*!< 0x00008000 */ + +/** + * @} +*/ + +/** + * @} +*/ + +/** @addtogroup Exported_macro + * @{ + */ + +#define CRM_HEXT_MIN 4000000U +#define CRM_HEXT_MAX 25000000U + +#define CRM_MAX_FREQUENCY 216000000U + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __AT32F402_405Kx_H */ + +/*********************** (C) COPYRIGHT Artery Technology *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ArteryTek/AT32F402_405/at32f402_405rx.h b/os/common/ext/CMSIS/ArteryTek/AT32F402_405/at32f402_405rx.h new file mode 100644 index 0000000000..b16731b7cc --- /dev/null +++ b/os/common/ext/CMSIS/ArteryTek/AT32F402_405/at32f402_405rx.h @@ -0,0 +1,11160 @@ +/** + ************************************************************************** + * @file at32f402_405rx.h + * @author Artery Technology & HorrorTroll & Zhaqian & Maxjta + * @version v2.1.2 + * @date 20-Jan-2025 + * @brief AT32F402_405Rx header file. + * + ************************************************************************** + * Copyright notice & Disclaimer + * + * The software Board Support Package (BSP) that is made available to + * download from Artery official website is the copyrighted work of Artery. + * Artery authorizes customers to use, copy, and distribute the BSP + * software and its related documentation for the purpose of design and + * development in conjunction with Artery microcontrollers. Use of the + * software is governed by this copyright notice and the following disclaimer. + * + * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES, + * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS, + * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR + * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS, + * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. + * + ************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup at32f402_405rx + * @{ + */ + +#ifndef __AT32F402_405Rx_H +#define __AT32F402_405Rx_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** + * @brief CMSIS Device version number V2.1.2 + */ +#define __AT32F402_405_LIBRARY_VERSION_MAJOR (0x02) /*!< [31:24] major version */ +#define __AT32F402_405_LIBRARY_VERSION_MIDDLE (0x01) /*!< [23:16] middle version */ +#define __AT32F402_405_LIBRARY_VERSION_MINOR (0x02) /*!< [15:8] minor version */ +#define __AT32F402_405_LIBRARY_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __AT32F402_405_LIBRARY_VERSION ((__AT32F402_405_LIBRARY_VERSION_MAJOR << 24)\ + |(__AT32F402_405_LIBRARY_VERSION_MIDDLE << 16)\ + |(__AT32F402_405_LIBRARY_VERSION_MINOR << 8 )\ + |(__AT32F402_405_LIBRARY_VERSION_RC)) + +/** + * @} + */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ +#define __CM4_REV 0x0001U /*!< Core Revision r0p1 */ +#define __MPU_PRESENT 1U /*!< AT32 devices provide an MPU */ +#define __NVIC_PRIO_BITS 4U /*!< AT32 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /*!< AT32 devices provide an FPU */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief AT32F402_405Rx Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ + + /*!< Interrupt Number Definition */ +typedef enum +{ +/****** Cortex-M4 Processor Exceptions Numbers ***************************************************/ + Reset_IRQn = -15, /*!< 1 Reset Vector Interrupt */ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + +/****** AT32 specific Interrupt Numbers **********************************************************/ + WWDT_IRQn = 0, /*!< Window WatchDog Timer Interrupt */ + PVM_IRQn = 1, /*!< PVM Interrupt linked to EXINT16 */ + TAMPER_IRQn = 2, /*!< Tamper Interrupt linked to EXINT21 */ + ERTC_WKUP_IRQn = 3, /*!< ERTC Wake Up Interrupt linked to EXINT22 */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + CRM_IRQn = 5, /*!< CRM global Interrupt */ + EXINT0_IRQn = 6, /*!< EXINT Line 0 Interrupt */ + EXINT1_IRQn = 7, /*!< EXINT Line 1 Interrupt */ + EXINT2_IRQn = 8, /*!< EXINT Line 2 Interrupt */ + EXINT3_IRQn = 9, /*!< EXINT Line 3 Interrupt */ + EXINT4_IRQn = 10, /*!< EXINT Line 4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ + ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ + CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ + CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SE_IRQn = 22, /*!< CAN1 SE Interrupt */ + EXINT9_5_IRQn = 23, /*!< EXINT Line[9:5] Interrupts */ + TMR1_BRK_TMR9_IRQn = 24, /*!< TMR1 Break Interrupt and TMR9 global Interrupt */ + TMR1_OVF_TMR10_IRQn = 25, /*!< TMR1 Overflow Interrupt and TMR10 global Interrupt */ + TMR1_TRG_HALL_TMR11_IRQn = 26, /*!< TMR1 Trigger and Hall Interrupt and TMR11 global IRQ */ + TMR1_CH_IRQn = 27, /*!< TMR1 Channel Interrupt */ + TMR2_GLOBAL_IRQn = 28, /*!< TMR2 global Interrupt */ + TMR3_GLOBAL_IRQn = 29, /*!< TMR3 global Interrupt */ + TMR4_GLOBAL_IRQn = 30, /*!< TMR4 global Interrupt */ + I2C1_EVT_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ERR_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EVT_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ERR_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXINT15_10_IRQn = 40, /*!< EXINT Line[15:10] Interrupts */ + ERTCAlarm_IRQn = 41, /*!< ERTC Alarm Interrupt linked to EXINT17 */ + OTGFS_WKUP_IRQn = 42, /*!< OTGFS Wake Up Interrupt linked to EXINT18 */ + TMR13_GLOBAL_IRQn = 44, /*!< TMR13 global Interrupt */ + TMR14_GLOBAL_IRQn = 45, /*!< TMR14 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + USART4_IRQn = 52, /*!< USART4 global Interrupt */ + USART5_IRQn = 53, /*!< USART5 global Interrupt */ + TMR6_GLOBAL_IRQn = 54, /*!< TMR6 global Interrupt */ + TMR7_GLOBAL_IRQn = 55, /*!< TMR7 global Interrupt */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ + DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ + OTGFS_IRQn = 67, /*!< OTGFS global Interrupt */ + DMA2_Channel6_IRQn = 68, /*!< DMA2 Channel 6 global Interrupt */ + DMA2_Channel7_IRQn = 69, /*!< DMA2 Channel 7 global Interrupt */ + USART6_IRQn = 71, /*!< USART6 global Interrupt */ + I2C3_EVT_IRQn = 72, /*!< I2C3 Event Interrupt */ + I2C3_ERR_IRQn = 73, /*!< I2C3 Error Interrupt */ + OTGHS_EP1_OUT_IRQn = 74, /*!< OTGHS Endpoint 1 OUT Interrupt (F405 only) */ + OTGHS_EP1_IN_IRQn = 75, /*!< OTGHS Endpoint 1 IN Interrupt (F405 only) */ + OTGHS_WKUP_IRQn = 76, /*!< OTGHS Wake Up IRQ linked to EXINT20 (F405 only) */ + OTGHS_IRQn = 77, /*!< OTGHS global Interrupt (F405 only) */ + FPU_IRQn = 81, /*!< FPU exception Interrupt */ + UART7_IRQn = 82, /*!< UART7 global Interrupt */ + UART8_IRQn = 83, /*!< UART8 global Interrupt */ + I2SF5_IRQn = 85, /*!< I2SF5 global Interrupt */ + QSPI1_IRQn = 92, /*!< QSPI1 global Interrupt */ + DMAMUX_IRQn = 94, /*!< DMAMUX overflow Interrupt */ + ACC_IRQn = 103, /*!< ACC global Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm4.h" +#include "system_at32f402_405.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief HICK Auto Clock Calibration + */ + +typedef struct +{ + __IO uint32_t STS; /*!< ACC Status register, Address offset: 0x00 */ + __IO uint32_t CTRL1; /*!< ACC Control register 1, Address offset: 0x04 */ + __IO uint32_t CTRL2; /*!< ACC Control register 2, Address offset: 0x08 */ + __IO uint32_t CP1; /*!< ACC Compare value 1, Address offset: 0x0C */ + __IO uint32_t CP2; /*!< ACC Compare value 2, Address offset: 0x10 */ + __IO uint32_t CP3; /*!< ACC Compare value 3, Address offset: 0x14 */ +} ACC_TypeDef; + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t STS; /*!< ADC status register, Address offset: 0x000 */ + __IO uint32_t CTRL1; /*!< ADC control register 1, Address offset: 0x004 */ + __IO uint32_t CTRL2; /*!< ADC control register 2, Address offset: 0x008 */ + __IO uint32_t SPT1; /*!< ADC sampling time register 1, Address offset: 0x00C */ + __IO uint32_t SPT2; /*!< ADC sampling time register 2, Address offset: 0x010 */ + __IO uint32_t PCDTO1; /*!< ADC preempted channel data offset reg 1, Address offset: 0x014 */ + __IO uint32_t PCDTO2; /*!< ADC preempted channel data offset reg 2, Address offset: 0x018 */ + __IO uint32_t PCDTO3; /*!< ADC preempted channel data offset reg 3, Address offset: 0x01C */ + __IO uint32_t PCDTO4; /*!< ADC preempted channel data offset reg 4, Address offset: 0x020 */ + __IO uint32_t VMHB; /*!< ADC voltage monitor high threshold register, Address offset: 0x024 */ + __IO uint32_t VMLB; /*!< ADC voltage monitor low threshold register, Address offset: 0x028 */ + __IO uint32_t OSQ1; /*!< ADC ordinary sequence register 1, Address offset: 0x02C */ + __IO uint32_t OSQ2; /*!< ADC ordinary sequence register 2, Address offset: 0x030 */ + __IO uint32_t OSQ3; /*!< ADC ordinary sequence register 3, Address offset: 0x034 */ + __IO uint32_t PSQ; /*!< ADC preempted sequence register, Address offset: 0x038 */ + __IO uint32_t PDT1; /*!< ADC preempted data register 1, Address offset: 0x03C */ + __IO uint32_t PDT2; /*!< ADC preempted data register 2, Address offset: 0x040 */ + __IO uint32_t PDT3; /*!< ADC preempted data register 3, Address offset: 0x044 */ + __IO uint32_t PDT4; /*!< ADC preempted data register 4, Address offset: 0x048 */ + __IO uint32_t ODT; /*!< ADC ordinary data register, Address offset: 0x04C */ + uint32_t RESERVED[12]; /*!< Reserved, Address offset: 0x050 ~ 0x07C */ + __IO uint32_t OVSP; /*!< ADC oversampling register, Address offset: 0x080 */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CCTRL; /*!< ADC common control register, Address offset: 0x304 */ +} ADC_Common_TypeDef; + +/** + * @brief Controller Area Network TX Mailbox Registers + */ + +typedef struct +{ + __IO uint32_t TMI; + __IO uint32_t TMC; + __IO uint32_t TMDTL; + __IO uint32_t TMDTH; +} CAN_TxMailBox_TypeDef; + +/** + * @brief Controller Area Network FIFO Mailbox Registers + */ + +typedef struct +{ + __IO uint32_t RFI; + __IO uint32_t RFC; + __IO uint32_t RFDTL; + __IO uint32_t RFDTH; +} CAN_FIFOMailBox_TypeDef; + +/** + * @brief Controller Area Network Filter Registers + */ + +typedef struct +{ + __IO uint32_t FFB1; + __IO uint32_t FFB2; +} CAN_FilterRegister_TypeDef; + +/** + * @brief Controller Area Network + */ + +typedef struct +{ + __IO uint32_t MCTRL; /*!< CAN master control register, Address offset: 0x000 */ + __IO uint32_t MSTS; /*!< CAN master status register, Address offset: 0x004 */ + __IO uint32_t TSTS; /*!< CAN transmit status register, Address offset: 0x008 */ + __IO uint32_t RF0; /*!< CAN receive FIFO 0 register, Address offset: 0x00C */ + __IO uint32_t RF1; /*!< CAN receive FIFO 1 register, Address offset: 0x010 */ + __IO uint32_t INTEN; /*!< CAN interrupt enable register, Address offset: 0x014 */ + __IO uint32_t ESTS; /*!< CAN error status register, Address offset: 0x018 */ + __IO uint32_t BTMG; /*!< CAN bit timing register, Address offset: 0x01C */ + uint32_t RESERVED0[88]; /*!< Reserved, Address offset: 0x020 ~ 0x17C */ + CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN TX Mailbox registers, Address offset: 0x180 ~ 0x1AC */ + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO Mailbox registers, Address offset: 0x1B0 ~ 0x1CC */ + uint32_t RESERVED1[12]; /*!< Reserved, Address offset: 0x1D0 ~ 0x1FC */ + __IO uint32_t FCTRL; /*!< CAN filter control register, Address offset: 0x200 */ + __IO uint32_t FMCFG; /*!< CAN filter mode configuration register, Address offset: 0x204 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x208 */ + __IO uint32_t FBWCFG; /*!< CAN filter bit width configuration register, Address offset: 0x20C */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x210 */ + __IO uint32_t FRF; /*!< CAN filter FIFO association register, Address offset: 0x214 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x218 */ + __IO uint32_t FACFG; /*!< CAN filter activation control register, Address offset: 0x21C */ + uint32_t RESERVED5[8]; /*!< Reserved, Address offset: 0x220 ~ 0x23C */ + CAN_FilterRegister_TypeDef sFilterRegister[14]; /*!< CAN filter registers, Address offset: 0x240 ~ 0x2AC */ +} CAN_TypeDef; + +/** + * @brief CRC Calculation Unit + */ + +typedef struct +{ + __IO uint32_t DT; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t CDT; /*!< CRC Common data register, Address offset: 0x04 */ + __IO uint32_t CTRL; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x0C */ + __IO uint32_t IDT; /*!< CRC Initialization register, Address offset: 0x10 */ + __IO uint32_t POLY; /*!< CRC Polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Clock and Reset Manage + */ + +typedef struct +{ + __IO uint32_t CTRL; /*!< CRM Clock control register, Address offset: 0x00 */ + __IO uint32_t PLLCFG; /*!< CRM PLL clock configuration register, Address offset: 0x04 */ + __IO uint32_t CFG; /*!< CRM Clock configuration register, Address offset: 0x08 */ + __IO uint32_t CLKINT; /*!< CRM Clock interrupt register, Address offset: 0x0C */ + __IO uint32_t AHBRST1; /*!< CRM AHB peripheral reset register 1, Address offset: 0x10 */ + __IO uint32_t AHBRST2; /*!< CRM AHB peripheral reset register 2, Address offset: 0x14 */ + __IO uint32_t AHBRST3; /*!< CRM AHB peripheral reset register 3, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t APB1RST; /*!< CRM APB1 peripheral reset register, Address offset: 0x20 */ + __IO uint32_t APB2RST; /*!< CRM APB2 peripheral reset register, Address offset: 0x24 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x28 ~ 0x2C */ + __IO uint32_t AHBEN1; /*!< CRM AHB peripheral clock enable register 1, Address offset: 0x30 */ + __IO uint32_t AHBEN2; /*!< CRM AHB peripheral clock enable register 2, Address offset: 0x34 */ + __IO uint32_t AHBEN3; /*!< CRM AHB peripheral clock enable register 3, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x3C */ + __IO uint32_t APB1EN; /*!< CRM APB1 peripheral clock enable register, Address offset: 0x40 */ + __IO uint32_t APB2EN; /*!< CRM APB2 peripheral clock enable register, Address offset: 0x44 */ + uint32_t RESERVED3[2]; /*!< Reserved, Address offset: 0x48 ~ 0x4C */ + __IO uint32_t AHBLPEN1; /*!< CRM AHB periph clk enable in LP mode reg 1, Address offset: 0x50 */ + __IO uint32_t AHBLPEN2; /*!< CRM AHB periph clk enable in LP mode reg 2, Address offset: 0x54 */ + __IO uint32_t AHBLPEN3; /*!< CRM AHB periph clk enable in LP mode reg 3, Address offset: 0x58 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x5C */ + __IO uint32_t APB1LPEN; /*!< CRM APB1 periph clk enable in LP mode reg, Address offset: 0x60 */ + __IO uint32_t APB2LPEN; /*!< CRM APB2 periph clk enable in LP mode reg, Address offset: 0x64 */ + uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x68 ~ 0x6C */ + __IO uint32_t BPDC; /*!< CRM Battery powered domain control register, Address offset: 0x70 */ + __IO uint32_t CTRLSTS; /*!< CRM Control/status register, Address offset: 0x74 */ + __IO uint32_t OTGHS; /*!< CRM OTGHS control register (F405 only), Address offset: 0x78 */ + uint32_t RESERVED6[9]; /*!< Reserved, Address offset: 0x7C ~ 0x9C */ + __IO uint32_t MISC1; /*!< CRM Additional register 1, Address offset: 0xA0 */ + __IO uint32_t MISC2; /*!< CRM Additional register 2, Address offset: 0xA4 */ +} CRM_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< DEBUG device ID, Address offset: 0xE004_2000 */ + __IO uint32_t CTRL; /*!< DEBUG control register, Address offset: 0xE004_2004 */ + __IO uint32_t APB1_PAUSE; /*!< DEBUG APB1 pause register, Address offset: 0xE004_2008 */ + __IO uint32_t APB2_PAUSE; /*!< DEBUG APB2 pause register, Address offset: 0xE004_200C */ + uint32_t RESERVED[4]; /*!< Reserved, Address offset: 0xE004_2010 ~ 0xE004_201C */ + __IO uint32_t SER_ID; /*!< DEBUG serial ID, Address offset: 0xE004_2020 */ +} DEBUG_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCTRL; /*!< DMA channel x configuration register, Address offset: 0x008 + 20 * (x - 1) (x = 1 ... 7) */ + __IO uint32_t CDTCNT; /*!< DMA channel x number of data register, Address offset: 0x00C + 20 * (x - 1) (x = 1 ... 7) */ + __IO uint32_t CPADDR; /*!< DMA channel x peripheral address register, Address offset: 0x010 + 20 * (x - 1) (x = 1 ... 7) */ + __IO uint32_t CMADDR; /*!< DMA channel x memory address register, Address offset: 0x014 + 20 * (x - 1) (x = 1 ... 7) */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t MUXCCTRL; /*!< DMA multiplexed channel x control register, Address offset: 0x104 + 4 * (x - 1) (x = 1 ... 7) */ +} DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t MUXSYNCSTS; /*!< DMA multiplexed channel sync status reg, Address offset: 0x130 */ + __IO uint32_t MUXSYNCCLR; /*!< DMA multiplexed channel irq flag clear reg, Address offset: 0x134 */ +} DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t MUXGCTRL; /*!< DMA multiplexed generator x control reg, Address offset: 0x120 + 4 * (x - 1) (x = 1 ... 4) */ +} DMAMUX_Generator_TypeDef; + +typedef struct +{ + __IO uint32_t MUXGSTS; /*!< DMA multiplexed generator irq status reg, Address offset: 0x138 */ + __IO uint32_t MUXGCLR; /*!< DMA mux generator irq flag clear register, Address offset: 0x13c */ +} DMAMUX_GeneratorStatus_TypeDef; + +typedef struct +{ + __IO uint32_t STS; /*!< DMA interrupt status register, Address offset: 0x000 */ + __IO uint32_t CLR; /*!< DMA interrupt flag clear register, Address offset: 0x004 */ + uint32_t RESERVED[62]; /*!< Reserved, Address offset: 0x008 ~ 0x0FC */ + __IO uint32_t MUXSEL; /*!< DMA multiplexed select register, Address offset: 0x100 */ +} DMA_TypeDef; + +/** + * @brief Enhanced Real-Time Clock + */ + +typedef struct +{ + __IO uint32_t TIME; /*!< ERTC time register, Address offset: 0x00 */ + __IO uint32_t DATE; /*!< ERTC date register, Address offset: 0x04 */ + __IO uint32_t CTRL; /*!< ERTC control register, Address offset: 0x08 */ + __IO uint32_t STS; /*!< ERTC initialization and status register, Address offset: 0x0C */ + __IO uint32_t DIV; /*!< ERTC divider register, Address offset: 0x10 */ + __IO uint32_t WAT; /*!< ERTC wakeup timer register, Address offset: 0x14 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x18 */ + __IO uint32_t ALA; /*!< ERTC alarm clock A register, Address offset: 0x1C */ + __IO uint32_t ALB; /*!< ERTC alarm clock B register, Address offset: 0x20 */ + __IO uint32_t WP; /*!< ERTC write protection register, Address offset: 0x24 */ + __IO uint32_t SBS; /*!< ERTC subsecond register, Address offset: 0x28 */ + __IO uint32_t TADJ; /*!< ERTC time adjustment register, Address offset: 0x2C */ + __IO uint32_t TSTM; /*!< ERTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDT; /*!< ERTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSBS; /*!< ERTC time stamp subsecond register, Address offset: 0x38 */ + __IO uint32_t SCAL; /*!< ERTC smooth calibration register, Address offset: 0x3C */ + __IO uint32_t TAMP; /*!< ERTC tamper configuration register, Address offset: 0x40 */ + __IO uint32_t ALASBS; /*!< ERTC alarm clock A subsecond register, Address offset: 0x44 */ + __IO uint32_t ALBSBS; /*!< ERTC alarm clock B subsecond register, Address offset: 0x48 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x4C */ + __IO uint32_t BPR1; /*!< ERTC battery powered domain data register 1, Address offset: 0x50 */ + __IO uint32_t BPR2; /*!< ERTC battery powered domain data register 2, Address offset: 0x54 */ + __IO uint32_t BPR3; /*!< ERTC battery powered domain data register 3, Address offset: 0x58 */ + __IO uint32_t BPR4; /*!< ERTC battery powered domain data register 4, Address offset: 0x5C */ + __IO uint32_t BPR5; /*!< ERTC battery powered domain data register 5, Address offset: 0x60 */ + __IO uint32_t BPR6; /*!< ERTC battery powered domain data register 6, Address offset: 0x64 */ + __IO uint32_t BPR7; /*!< ERTC battery powered domain data register 7, Address offset: 0x68 */ + __IO uint32_t BPR8; /*!< ERTC battery powered domain data register 8, Address offset: 0x6C */ + __IO uint32_t BPR9; /*!< ERTC battery powered domain data register 9, Address offset: 0x70 */ + __IO uint32_t BPR10; /*!< ERTC BAT powered domain data register 10, Address offset: 0x74 */ + __IO uint32_t BPR11; /*!< ERTC BAT powered domain data register 11, Address offset: 0x78 */ + __IO uint32_t BPR12; /*!< ERTC BAT powered domain data register 12, Address offset: 0x7C */ + __IO uint32_t BPR13; /*!< ERTC BAT powered domain data register 13, Address offset: 0x80 */ + __IO uint32_t BPR14; /*!< ERTC BAT powered domain data register 14, Address offset: 0x84 */ + __IO uint32_t BPR15; /*!< ERTC BAT powered domain data register 15, Address offset: 0x88 */ + __IO uint32_t BPR16; /*!< ERTC BAT powered domain data register 16, Address offset: 0x8C */ + __IO uint32_t BPR17; /*!< ERTC BAT powered domain data register 17, Address offset: 0x90 */ + __IO uint32_t BPR18; /*!< ERTC BAT powered domain data register 18, Address offset: 0x94 */ + __IO uint32_t BPR19; /*!< ERTC BAT powered domain data register 19, Address offset: 0x98 */ + __IO uint32_t BPR20; /*!< ERTC BAT powered domain data register 20, Address offset: 0x9C */ +} ERTC_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t INTEN; /*!< EXINT Interrupt enable register, Address offset: 0x00 */ + __IO uint32_t EVTEN; /*!< EXINT Event enable register, Address offset: 0x04 */ + __IO uint32_t POLCFG1; /*!< EXINT Polarity configuration register 1, Address offset: 0x08 */ + __IO uint32_t POLCFG2; /*!< EXINT Polarity configuration register 2, Address offset: 0x0C */ + __IO uint32_t SWTRG; /*!< EXINT Software trigger register, Address offset: 0x10 */ + __IO uint32_t INTSTS; /*!< EXINT Interrupt status register, Address offset: 0x14 */ +} EXINT_TypeDef; + +/** + * @brief Flash Memory Registers + */ + +typedef struct +{ + __IO uint32_t PSR; /*!< FLASH performance select register, Address offset: 0x00 */ + __IO uint32_t UNLOCK; /*!< FLASH unlock register, Address offset: 0x04 */ + __IO uint32_t USD_UNLOCK; /*!< FLASH user system data unlock register, Address offset: 0x08 */ + __IO uint32_t STS; /*!< FLASH status register, Address offset: 0x0C */ + __IO uint32_t CTRL; /*!< FLASH control register, Address offset: 0x10 */ + __IO uint32_t ADDR; /*!< FLASH address register, Address offset: 0x14 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x18 */ + __IO uint32_t USD; /*!< FLASH user system data register, Address offset: 0x1C */ + __IO uint32_t EPPS; /*!< FLASH erase/program protection status reg, Address offset: 0x20 */ + uint32_t RESERVED1[20]; /*!< Reserved, Address offset: 0x24 ~ 0x70 */ + __IO uint32_t SLIB_STS0; /*!< FLASH security library status register 0, Address offset: 0x74 */ + __IO uint32_t SLIB_STS1; /*!< FLASH security library status register 1, Address offset: 0x78 */ + __IO uint32_t SLIB_PWD_CLR; /*!< FLASH security library password clear reg, Address offset: 0x7C */ + __IO uint32_t SLIB_MISC_STS; /*!< FLASH security library additional stat reg, Address offset: 0x80 */ + __IO uint32_t CRC_ADDR; /*!< FLASH CRC address register, Address offset: 0x84 */ + __IO uint32_t CRC_CTRL; /*!< FLASH CRC control register, Address offset: 0x88 */ + __IO uint32_t CRC_CHKR; /*!< FLASH CRC check result register, Address offset: 0x8C */ + uint32_t RESERVED2[52]; /*!< Reserved, Address offset: 0x90 ~ 0x15C */ + __IO uint32_t SLIB_SET_PWD; /*!< FLASH security library password setting reg, Address offset: 0x160 */ + __IO uint32_t SLIB_SET_RANGE; /*!< FLASH security library address setting reg, Address offset: 0x164 */ + __IO uint32_t EM_SLIB_SET; /*!< FLASH extension mem security lib set reg, Address offset: 0x168 */ + __IO uint32_t BTM_MODE_SET; /*!< FLASH boot memory mode setting register, Address offset: 0x16C */ + __IO uint32_t SLIB_UNLOCK; /*!< FLASH security library unlock register, Address offset: 0x170 */ +} FLASH_TypeDef; + +/** + * @brief User System Data Registers + */ + +typedef struct +{ + __IO uint16_t FAP; /*!< USD memory access protection, Address offset: 0x1FFF_F800 */ + __IO uint16_t SSB; /*!< USD System configuration byte, Address offset: 0x1FFF_F802 */ + __IO uint16_t DATA0; /*!< USD User data 0, Address offset: 0x1FFF_F804 */ + __IO uint16_t DATA1; /*!< USD User data 1, Address offset: 0x1FFF_F806 */ + __IO uint16_t EPP0; /*!< USD erase/write protection byte 0, Address offset: 0x1FFF_F808 */ + __IO uint16_t EPP1; /*!< USD erase/write protection byte 1, Address offset: 0x1FFF_F80A */ + __IO uint16_t EPP2; /*!< USD erase/write protection byte 2, Address offset: 0x1FFF_F80C */ + __IO uint16_t EPP3; /*!< USD erase/write protection byte 3, Address offset: 0x1FFF_F80E */ + uint32_t RESERVED0[9]; /*!< Reserved, Address offset: 0x1FFF_F810 ~ 0x1FFF_F830 */ + __IO uint16_t QSPIKEY0; /*!< USD QSPI ciphertext access area + encryption key byte 0, Address offset: 0x1FFF_F834 */ + __IO uint16_t QSPIKEY1; /*!< USD QSPI ciphertext access area + encryption key byte 1, Address offset: 0x1FFF_F836 */ + __IO uint16_t QSPIKEY2; /*!< USD QSPI ciphertext access area + encryption key byte 2, Address offset: 0x1FFF_F838 */ + __IO uint16_t QSPIKEY3; /*!< USD QSPI ciphertext access area + encryption key byte 3, Address offset: 0x1FFF_F83A */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x1FFF_F83C ~ 0x1FFF_F848 */ + __IO uint16_t DATA[218]; /*!< USD User data 2 ~ 219, Address offset: 0x1FFF_F84C ~ 0x1FFF_F9FC */ +} USD_TypeDef; + +/** + * @brief General Purpose I/O or Multiplexed Function I/O + */ + +typedef struct +{ + __IO uint32_t CFGR; /*!< GPIO configuration register, Address offset: 0x00 */ + __IO uint32_t OMODE; /*!< GPIO output mode register, Address offset: 0x04 */ + __IO uint32_t ODRVR; /*!< GPIO drive capability register, Address offset: 0x08 */ + __IO uint32_t PULL; /*!< GPIO pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDT; /*!< GPIO input data register, Address offset: 0x10 */ + __IO uint32_t ODT; /*!< GPIO output data register, Address offset: 0x14 */ + __IO uint32_t SCR; /*!< GPIO set/clear register, Address offset: 0x18 */ + __IO uint32_t WPR; /*!< GPIO write protection register, Address offset: 0x1C */ + __IO uint32_t MUXL; /*!< GPIO multiplexed function low register, Address offset: 0x20 */ + __IO uint32_t MUXH; /*!< GPIO multiplexed function high register, Address offset: 0x24 */ + __IO uint32_t CLR; /*!< GPIO port bit clear register, Address offset: 0x28 */ + __IO uint32_t TOGR; /*!< GPIO port bit toggle register, Address offset: 0x2C */ + uint32_t RESERVED[3]; /*!< Reserved, Address offset: 0x30 ~ 0x38 */ + __IO uint32_t HDRV; /*!< GPIO huge current control register, Address offset: 0x3C */ + __IO uint32_t SRCTR; /*!< GPIO SRCTR register, Address offset: 0x40 */ +} GPIO_TypeDef; + +/** + * @brief Inter Integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CTRL1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CTRL2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OADDR1; /*!< I2C Own address register 1, Address offset: 0x08 */ + __IO uint32_t OADDR2; /*!< I2C Own address register 2, Address offset: 0x0C */ + __IO uint32_t CLKCTRL; /*!< I2C Clock control register, Address offset: 0x10 */ + __IO uint32_t TIMEOUT; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t STS; /*!< I2C Status register, Address offset: 0x18 */ + __IO uint32_t CLR; /*!< I2C Status clear flag register, Address offset: 0x1C */ + __IO uint32_t PEC; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDT; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDT; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CTRL; /*!< PWC Power control register, Address offset: 0x00 */ + __IO uint32_t CTRLSTS; /*!< PWC Power control/status register, Address offset: 0x04 */ + uint32_t RESERVED[2]; /*!< Reserved, Address offset: 0x08 ~ 0x0C */ + __IO uint32_t LDOOV; /*!< PWC LDO output voltage select register, Address offset: 0x10 */ +} PWC_TypeDef; + +/** + * @brief Quad-SPI Interface + */ + +typedef struct +{ + __IO uint32_t CMD_W0; /*!< QSPI Command word 0 register, Address offset: 0x00 */ + __IO uint32_t CMD_W1; /*!< QSPI Command word 1 register, Address offset: 0x04 */ + __IO uint32_t CMD_W2; /*!< QSPI Command word 2 register, Address offset: 0x08 */ + __IO uint32_t CMD_W3; /*!< QSPI Command word 3 register, Address offset: 0x0C */ + __IO uint32_t CTRL; /*!< QSPI Control register, Address offset: 0x10 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t FIFOSTS; /*!< QSPI FIFO status register, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t CTRL2; /*!< QSPI Control register 2, Address offset: 0x20 */ + __IO uint32_t CMDSTS; /*!< QSPI Command status register, Address offset: 0x24 */ + __IO uint32_t RSTS; /*!< QSPI Read status register, Address offset: 0x28 */ + __IO uint32_t FSIZE; /*!< QSPI Flash size register, Address offset: 0x2C */ + __IO uint32_t XIP_CMD_W0; /*!< QSPI XIP command word 0 register, Address offset: 0x30 */ + __IO uint32_t XIP_CMD_W1; /*!< QSPI XIP command word 1 register, Address offset: 0x34 */ + __IO uint32_t XIP_CMD_W2; /*!< QSPI XIP command word 2 register, Address offset: 0x38 */ + __IO uint32_t XIP_CMD_W3; /*!< QSPI XIP command word 3 register, Address offset: 0x3C */ + __IO uint32_t CTRL3; /*!< QSPI Control register 3, Address offset: 0x40 */ + uint32_t RESERVED2[3]; /*!< Reserved, Address offset: 0x44 ~ 0x4C */ + __IO uint32_t REV; /*!< QSPI Revision register, Address offset: 0x50 */ + uint32_t RESERVED3[43]; /*!< Reserved, Address offset: 0x54 ~ 0xFC */ + __IO uint8_t DT_U8; /*!< QSPI Data port (8-bit) register, Address offset: 0x100 */ + __IO uint16_t DT_U16; /*!< QSPI Data port (16-bit) register, Address offset: 0x100 */ + __IO uint32_t DT; /*!< QSPI Data port register, Address offset: 0x100 */ +} QSPI_TypeDef; + +/** + * @brief System Configuration Controller + */ + +typedef struct +{ + __IO uint32_t CFG1; /*!< SCFG configuration register 1, Address offset: 0x00 */ + __IO uint32_t CFG2; /*!< SCFG configuration register 2, Address offset: 0x04 */ + __IO uint32_t EXINTC[4]; /*!< SCFG external interrupt config register x, Address offset: 0x08 ~ 0x14 */ + uint32_t RESERVED[5]; /*!< Reserved, Address offset: 0x18 ~ 0x28 */ + __IO uint32_t UHDRV; /*!< SCFG ultra high source/sinking strength reg, Address offset: 0x2C */ +} SCFG_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CTRL1; /*!< SPI control register 1, Address offset: 0x00 */ + __IO uint32_t CTRL2; /*!< SPI control register 2, Address offset: 0x04 */ + __IO uint32_t STS; /*!< SPI status register, Address offset: 0x08 */ + __IO uint32_t DT; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CPOLY; /*!< SPI CRC register, Address offset: 0x10 */ + __IO uint32_t RCRC; /*!< SPI receive CRC register, Address offset: 0x14 */ + __IO uint32_t TCRC; /*!< SPI transmit CRC register, Address offset: 0x18 */ + __IO uint32_t I2SCTRL; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + __IO uint32_t I2SCLKP; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ + uint32_t RESERVED[3]; /*!< Reserved, Address offset: 0x24 ~ 0x2C */ + __IO uint32_t MISC1; /*!< SPI_I2SF5 additional register, Address offset: 0x30 */ +} SPI_TypeDef; + +/** + * @brief TMR Timers + */ + +typedef struct +{ + __IO uint32_t CTRL1; /*!< TMR control register 1, Address offset: 0x00 */ + __IO uint32_t CTRL2; /*!< TMR control register 2, Address offset: 0x04 */ + __IO uint32_t STCTRL; /*!< TMR slave timer control register, Address offset: 0x08 */ + __IO uint32_t IDEN; /*!< TMR DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t ISTS; /*!< TMR interrupt status register, Address offset: 0x10 */ + __IO uint32_t SWEVT; /*!< TMR software event register, Address offset: 0x14 */ + __IO uint32_t CM1; /*!< TMR channel mode register 1, Address offset: 0x18 */ + __IO uint32_t CM2; /*!< TMR channel mode register 2, Address offset: 0x1C */ + __IO uint32_t CCTRL; /*!< TMR channel control register, Address offset: 0x20 */ + __IO uint32_t CVAL; /*!< TMR counter value register, Address offset: 0x24 */ + __IO uint32_t DIV; /*!< TMR division value register, Address offset: 0x28 */ + __IO uint32_t PR; /*!< TMR period register, Address offset: 0x2C */ + __IO uint32_t RPR; /*!< TMR repetition period register, Address offset: 0x30 */ + __IO uint32_t C1DT; /*!< TMR channel 1 data register, Address offset: 0x34 */ + __IO uint32_t C2DT; /*!< TMR channel 2 data register, Address offset: 0x38 */ + __IO uint32_t C3DT; /*!< TMR channel 3 data register, Address offset: 0x3C */ + __IO uint32_t C4DT; /*!< TMR channel 4 data register, Address offset: 0x40 */ + __IO uint32_t BRK; /*!< TMR break register, Address offset: 0x44 */ + __IO uint32_t DMACTRL; /*!< TMR DMA control register, Address offset: 0x48 */ + __IO uint32_t DMADT; /*!< TMR DMA data register, Address offset: 0x4C */ + __IO uint32_t RMP; /*!< TMR channel input remap register, Address offset: 0x50 */ +} TMR_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint32_t STS; /*!< USART status register, Address offset: 0x00 */ + __IO uint32_t DT; /*!< USART data register, Address offset: 0x04 */ + __IO uint32_t BAUDR; /*!< USART baud rate register, Address offset: 0x08 */ + __IO uint32_t CTRL1; /*!< USART control register 1, Address offset: 0x0C */ + __IO uint32_t CTRL2; /*!< USART control register 2, Address offset: 0x10 */ + __IO uint32_t CTRL3; /*!< USART control register 3, Address offset: 0x14 */ + __IO uint32_t GDIV; /*!< USART guard time and divider register, Address offset: 0x18 */ + __IO uint32_t RTOV; /*!< USART receiver timeout detection register, Address offset: 0x1C */ + __IO uint32_t IFC; /*!< USART interrupt flag clear register, Address offset: 0x20 */ +} USART_TypeDef; + +/** + * @brief WATCHDOG Timer + */ + +typedef struct +{ + __IO uint32_t CMD; /*!< WDT Command register, Address offset: 0x00 */ + __IO uint32_t DIV; /*!< WDT Divider register, Address offset: 0x04 */ + __IO uint32_t RLD; /*!< WDT Reload register, Address offset: 0x08 */ + __IO uint32_t STS; /*!< WDT Status register, Address offset: 0x0C */ + __IO uint32_t WIN; /*!< WDT Window register, Address offset: 0x10 */ +} WDT_TypeDef; + +/** + * @brief Window WATCHDOG Timer + */ + +typedef struct +{ + __IO uint32_t CTRL; /*!< WWDT Control register, Address offset: 0x00 */ + __IO uint32_t CFG; /*!< WWDT Configuration register, Address offset: 0x04 */ + __IO uint32_t STS; /*!< WWDT Status register, Address offset: 0x08 */ +} WWDT_TypeDef; + +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ + +#define FLASH_BASE 0x08000000U /*!< FLASH base address in the alias region */ +#define FLASH_BANK1_END 0x0803FFFFU /*!< FLASH end address of bank 1 */ +#define QSPI1_BASE 0x90000000U /*!< QSPI1 base address */ +#define SRAM_BASE 0x20000000U /*!< SRAM base address in the alias region */ +#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */ + +#define SRAM_BB_BASE 0x22000000U /*!< SRAM base address in the bit-band region */ +#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE /*!< APB1 base address */ +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U) /*!< APB2 base address */ +#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000U) /*!< AHB base address */ + +#define TMR2_BASE (APB1PERIPH_BASE + 0x00000000U) /*!< TMR2 base address */ +#define TMR3_BASE (APB1PERIPH_BASE + 0x00000400U) /*!< TMR3 base address */ +#define TMR4_BASE (APB1PERIPH_BASE + 0x00000800U) /*!< TMR4 base address */ +#define TMR6_BASE (APB1PERIPH_BASE + 0x00001000U) /*!< TMR6 base address */ +#define TMR7_BASE (APB1PERIPH_BASE + 0x00001400U) /*!< TMR7 base address */ +#define TMR13_BASE (APB1PERIPH_BASE + 0x00001C00U) /*!< TMR13 base address */ +#define TMR14_BASE (APB1PERIPH_BASE + 0x00002000U) /*!< TMR14 base address */ +#define ERTC_BASE (APB1PERIPH_BASE + 0x00002800U) /*!< ERTC base address */ +#define WWDT_BASE (APB1PERIPH_BASE + 0x00002C00U) /*!< WWDT base address */ +#define WDT_BASE (APB1PERIPH_BASE + 0x00003000U) /*!< WDT base address */ +#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800U) /*!< SPI2 base address */ +#define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00U) /*!< SPI3 base address */ +#define USART2_BASE (APB1PERIPH_BASE + 0x00004400U) /*!< USART2 base address */ +#define USART3_BASE (APB1PERIPH_BASE + 0x00004800U) /*!< USART3 base address */ +#define USART4_BASE (APB1PERIPH_BASE + 0x00004C00U) /*!< USART4 base address */ +#define USART5_BASE (APB1PERIPH_BASE + 0x00005000U) /*!< USART5 base address */ +#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400U) /*!< I2C1 base address */ +#define I2C2_BASE (APB1PERIPH_BASE + 0x00005800U) /*!< I2C2 base address */ +#define I2C3_BASE (APB1PERIPH_BASE + 0x00005C00U) /*!< I2C3 base address */ +#define CAN1_BASE (APB1PERIPH_BASE + 0x00006400U) /*!< CAN1 base address */ +#define PWC_BASE (APB1PERIPH_BASE + 0x00007000U) /*!< PWC base address */ +#define UART7_BASE (APB1PERIPH_BASE + 0x00007800U) /*!< UART7 base address */ +#define UART8_BASE (APB1PERIPH_BASE + 0x00007C00U) /*!< UART8 base address */ + +#define TMR1_BASE (APB2PERIPH_BASE + 0x00000000U) /*!< TMR1 base address */ +#define USART1_BASE (APB2PERIPH_BASE + 0x00001000U) /*!< USART1 base address */ +#define USART6_BASE (APB2PERIPH_BASE + 0x00001400U) /*!< USART6 base address */ + +#define ADC1_BASE (APB2PERIPH_BASE + 0x00002000U) /*!< ADC1 base address */ +#define ADC_Common_BASE (APB2PERIPH_BASE + 0x00002300U) /*!< ADC Common base address */ + +#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000U) /*!< SPI1 base address */ +#define SCFG_BASE (APB2PERIPH_BASE + 0x00003800U) /*!< SCFG base address */ +#define EXINT_BASE (APB2PERIPH_BASE + 0x00003C00U) /*!< EXINT base address */ +#define TMR9_BASE (APB2PERIPH_BASE + 0x00004000U) /*!< TMR9 base address */ +#define TMR10_BASE (APB2PERIPH_BASE + 0x00004400U) /*!< TMR10 base address */ +#define TMR11_BASE (APB2PERIPH_BASE + 0x00004800U) /*!< TMR11 base address */ +#define I2SF5_BASE (APB2PERIPH_BASE + 0x00005000U) /*!< I2SF5 base address */ +#define ACC_BASE (APB2PERIPH_BASE + 0x00007400U) /*!< ACC base address */ + +#define GPIOA_BASE (AHBPERIPH_BASE + 0x00000000U) /*!< GPIOA base address */ +#define GPIOB_BASE (AHBPERIPH_BASE + 0x00000400U) /*!< GPIOB base address */ +#define GPIOC_BASE (AHBPERIPH_BASE + 0x00000800U) /*!< GPIOC base address */ +#define GPIOD_BASE (AHBPERIPH_BASE + 0x00000C00U) /*!< GPIOD base address */ +#define GPIOF_BASE (AHBPERIPH_BASE + 0x00001400U) /*!< GPIOF base address */ +#define CRC_BASE (AHBPERIPH_BASE + 0x00003000U) /*!< CRC base address */ +#define CRM_BASE (AHBPERIPH_BASE + 0x00003800U) /*!< CRM base address */ + +#define DMA1_BASE (AHBPERIPH_BASE + 0x00006000U) /*!< DMA1 base address */ +#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x00006008U) /*!< DMA1 Channel 1 base address */ +#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x0000601CU) /*!< DMA1 Channel 2 base address */ +#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x00006030U) /*!< DMA1 Channel 3 base address */ +#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x00006044U) /*!< DMA1 Channel 4 base address */ +#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x00006058U) /*!< DMA1 Channel 5 base address */ +#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x0000606CU) /*!< DMA1 Channel 6 base address */ +#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x00006080U) /*!< DMA1 Channel 7 base address */ + +#define DMA1MUX_BASE (AHBPERIPH_BASE + 0x00006104U) /*!< DMA1 Multiplexed base address */ +#define DMA1MUX_Channel1_BASE (DMA1MUX_BASE) /*!< DMA1 Multiplexed Channel 1 base address */ +#define DMA1MUX_Channel2_BASE (AHBPERIPH_BASE + 0x00006108U) /*!< DMA1 Multiplexed Channel 2 base address */ +#define DMA1MUX_Channel3_BASE (AHBPERIPH_BASE + 0x0000610CU) /*!< DMA1 Multiplexed Channel 3 base address */ +#define DMA1MUX_Channel4_BASE (AHBPERIPH_BASE + 0x00006110U) /*!< DMA1 Multiplexed Channel 4 base address */ +#define DMA1MUX_Channel5_BASE (AHBPERIPH_BASE + 0x00006114U) /*!< DMA1 Multiplexed Channel 5 base address */ +#define DMA1MUX_Channel6_BASE (AHBPERIPH_BASE + 0x00006118U) /*!< DMA1 Multiplexed Channel 6 base address */ +#define DMA1MUX_Channel7_BASE (AHBPERIPH_BASE + 0x0000611CU) /*!< DMA1 Multiplexed Channel 7 base address */ +#define DMA1MUX_Generator1_BASE (AHBPERIPH_BASE + 0x00006120U) /*!< DMA1 Multiplexed Generator 1 base address */ +#define DMA1MUX_Generator2_BASE (AHBPERIPH_BASE + 0x00006124U) /*!< DMA1 Multiplexed Generator 2 base address */ +#define DMA1MUX_Generator3_BASE (AHBPERIPH_BASE + 0x00006128U) /*!< DMA1 Multiplexed Generator 3 base address */ +#define DMA1MUX_Generator4_BASE (AHBPERIPH_BASE + 0x0000612CU) /*!< DMA1 Multiplexed Generator 4 base address */ +#define DMA1MUX_ChannelStatus_BASE (AHBPERIPH_BASE + 0x00006130U) /*!< DMA1 Multiplexed Channel status base address */ +#define DMA1MUX_GeneratorStatus_BASE (AHBPERIPH_BASE + 0x00006138U) /*!< DMA1 Multiplexed Generator status base address */ + +#define DMA2_BASE (AHBPERIPH_BASE + 0x00006400U) /*!< DMA2 base address */ +#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x00006408U) /*!< DMA2 Channel 1 base address */ +#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x0000641CU) /*!< DMA2 Channel 2 base address */ +#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x00006430U) /*!< DMA2 Channel 3 base address */ +#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x00006444U) /*!< DMA2 Channel 4 base address */ +#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x00006458U) /*!< DMA2 Channel 5 base address */ +#define DMA2_Channel6_BASE (AHBPERIPH_BASE + 0x0000646CU) /*!< DMA2 Channel 6 base address */ +#define DMA2_Channel7_BASE (AHBPERIPH_BASE + 0x00006480U) /*!< DMA2 Channel 7 base address */ + +#define DMA2MUX_BASE (AHBPERIPH_BASE + 0x00006504U) /*!< DMA2 Multiplexed base address */ +#define DMA2MUX_Channel1_BASE (DMA2MUX_BASE) /*!< DMA2 Multiplexed Channel 1 base address */ +#define DMA2MUX_Channel2_BASE (AHBPERIPH_BASE + 0x00006508U) /*!< DMA2 Multiplexed Channel 2 base address */ +#define DMA2MUX_Channel3_BASE (AHBPERIPH_BASE + 0x0000650CU) /*!< DMA2 Multiplexed Channel 3 base address */ +#define DMA2MUX_Channel4_BASE (AHBPERIPH_BASE + 0x00006510U) /*!< DMA2 Multiplexed Channel 4 base address */ +#define DMA2MUX_Channel5_BASE (AHBPERIPH_BASE + 0x00006514U) /*!< DMA2 Multiplexed Channel 5 base address */ +#define DMA2MUX_Channel6_BASE (AHBPERIPH_BASE + 0x00006518U) /*!< DMA2 Multiplexed Channel 6 base address */ +#define DMA2MUX_Channel7_BASE (AHBPERIPH_BASE + 0x0000651CU) /*!< DMA2 Multiplexed Channel 7 base address */ +#define DMA2MUX_Generator1_BASE (AHBPERIPH_BASE + 0x00006520U) /*!< DMA2 Multiplexed Generator 1 base address */ +#define DMA2MUX_Generator2_BASE (AHBPERIPH_BASE + 0x00006524U) /*!< DMA2 Multiplexed Generator 2 base address */ +#define DMA2MUX_Generator3_BASE (AHBPERIPH_BASE + 0x00006528U) /*!< DMA2 Multiplexed Generator 3 base address */ +#define DMA2MUX_Generator4_BASE (AHBPERIPH_BASE + 0x0000652CU) /*!< DMA2 Multiplexed Generator 4 base address */ +#define DMA2MUX_ChannelStatus_BASE (AHBPERIPH_BASE + 0x00006530U) /*!< DMA2 Multiplexed Channel status base address */ +#define DMA2MUX_GeneratorStatus_BASE (AHBPERIPH_BASE + 0x00006538U) /*!< DMA2 Multiplexed Generator status base address */ + +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00003C00U) /*!< FLASH registers base address */ +#define QSPI1_R_BASE 0xA0001000U /*!< QSPI1 registers base address */ +#define FLASHSIZE_BASE 0x1FFFF7E0U /*!< FLASH Size register base address */ +#define UID_BASE 0x1FFFF7E8U /*!< Unique device ID register base address */ +#define USD_BASE 0x1FFFF800U /*!< FLASH User System Data base address */ + +#define DEBUG_BASE 0xE0042000U /*!< Debug MCU registers base address */ + +/* USB OTG FS */ +#define USB_OTG_FS_PERIPH_BASE 0x50000000U /*!< USB OTG FS Peripheral Registers base address */ + +/* USB OTG HS (F405 only) */ +#define USB_OTG_HS_PERIPH_BASE 0x40040000U /*!< USB OTG HS Peripheral Registers base address */ + +#define USB_OTG_GLOBAL_BASE 0x00000000U /*!< USB OTG Global Registers base address */ +#define USB_OTG_DEVICE_BASE 0x00000800U /*!< USB OTG Device ModeRegisters base address */ +#define USB_OTG_IN_ENDPOINT_BASE 0x00000900U /*!< USB OTG IN Endpoint Registers base address */ +#define USB_OTG_OUT_ENDPOINT_BASE 0x00000B00U /*!< USB OTG OUT Endpoint Registers base address */ +#define USB_OTG_EP_REG_SIZE 0x00000020U /*!< USB OTG All Endpoint Registers size address */ +#define USB_OTG_HOST_BASE 0x00000400U /*!< USB OTG Host Mode Registers base address */ +#define USB_OTG_HOST_PORT_BASE 0x00000440U /*!< USB OTG Host Port Registers base address */ +#define USB_OTG_HOST_CHANNEL_BASE 0x00000500U /*!< USB OTG Host Channel Registers base address */ +#define USB_OTG_HOST_CHANNEL_SIZE 0x00000020U /*!< USB OTG Host Channel Registers size address */ +#define USB_OTG_PCGCCTL_BASE 0x00000E00U /*!< USB OTG Power and Ctrl Registers base address */ +#define USB_OTG_FIFO_BASE 0x00001000U /*!< USB OTG FIFO Registers base address */ +#define USB_OTG_FIFO_SIZE 0x00001000U /*!< USB OTG FIFO Registers size address */ + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ + +#define ACC ((ACC_TypeDef *)ACC_BASE) +#define ADC1 ((ADC_TypeDef *)ADC1_BASE) +#define ADC_COMMON ((ADC_Common_TypeDef *)ADC_Common_BASE) +#define CAN1 ((CAN_TypeDef *)CAN1_BASE) +#define CRC ((CRC_TypeDef *)CRC_BASE) +#define CRM ((CRM_TypeDef *)CRM_BASE) +#define DEBUG ((DEBUG_TypeDef *)DEBUG_BASE) +#define DMA1 ((DMA_TypeDef *)DMA1_BASE) +#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE) +#define DMA1MUX_Channel1 ((DMAMUX_Channel_TypeDef *) DMA1MUX_Channel1_BASE) +#define DMA1MUX_Channel2 ((DMAMUX_Channel_TypeDef *) DMA1MUX_Channel2_BASE) +#define DMA1MUX_Channel3 ((DMAMUX_Channel_TypeDef *) DMA1MUX_Channel3_BASE) +#define DMA1MUX_Channel4 ((DMAMUX_Channel_TypeDef *) DMA1MUX_Channel4_BASE) +#define DMA1MUX_Channel5 ((DMAMUX_Channel_TypeDef *) DMA1MUX_Channel5_BASE) +#define DMA1MUX_Channel6 ((DMAMUX_Channel_TypeDef *) DMA1MUX_Channel6_BASE) +#define DMA1MUX_Channel7 ((DMAMUX_Channel_TypeDef *) DMA1MUX_Channel7_BASE) +#define DMA1MUX_Generator1 ((DMAMUX_Generator_TypeDef *) DMA1MUX_Generator1_BASE) +#define DMA1MUX_Generator2 ((DMAMUX_Generator_TypeDef *) DMA1MUX_Generator2_BASE) +#define DMA1MUX_Generator3 ((DMAMUX_Generator_TypeDef *) DMA1MUX_Generator3_BASE) +#define DMA1MUX_Generator4 ((DMAMUX_Generator_TypeDef *) DMA1MUX_Generator4_BASE) +#define DMA1MUX_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMA1MUX_ChannelStatus_BASE) +#define DMA1MUX_GeneratorStatus ((DMAMUX_GeneratorStatus_TypeDef *) DMA1MUX_GeneratorStatus_BASE) +#define DMA2 ((DMA_TypeDef *)DMA2_BASE) +#define DMA2_Channel1 ((DMA_Channel_TypeDef *)DMA2_Channel1_BASE) +#define DMA2_Channel2 ((DMA_Channel_TypeDef *)DMA2_Channel2_BASE) +#define DMA2_Channel3 ((DMA_Channel_TypeDef *)DMA2_Channel3_BASE) +#define DMA2_Channel4 ((DMA_Channel_TypeDef *)DMA2_Channel4_BASE) +#define DMA2_Channel5 ((DMA_Channel_TypeDef *)DMA2_Channel5_BASE) +#define DMA2_Channel6 ((DMA_Channel_TypeDef *)DMA2_Channel6_BASE) +#define DMA2_Channel7 ((DMA_Channel_TypeDef *)DMA2_Channel7_BASE) +#define DMA2MUX_Channel1 ((DMAMUX_Channel_TypeDef *) DMA2MUX_Channel1_BASE) +#define DMA2MUX_Channel2 ((DMAMUX_Channel_TypeDef *) DMA2MUX_Channel2_BASE) +#define DMA2MUX_Channel3 ((DMAMUX_Channel_TypeDef *) DMA2MUX_Channel3_BASE) +#define DMA2MUX_Channel4 ((DMAMUX_Channel_TypeDef *) DMA2MUX_Channel4_BASE) +#define DMA2MUX_Channel5 ((DMAMUX_Channel_TypeDef *) DMA2MUX_Channel5_BASE) +#define DMA2MUX_Channel6 ((DMAMUX_Channel_TypeDef *) DMA2MUX_Channel6_BASE) +#define DMA2MUX_Channel7 ((DMAMUX_Channel_TypeDef *) DMA2MUX_Channel7_BASE) +#define DMA2MUX_Generator1 ((DMAMUX_Generator_TypeDef *) DMA2MUX_Generator1_BASE) +#define DMA2MUX_Generator2 ((DMAMUX_Generator_TypeDef *) DMA2MUX_Generator2_BASE) +#define DMA2MUX_Generator3 ((DMAMUX_Generator_TypeDef *) DMA2MUX_Generator3_BASE) +#define DMA2MUX_Generator4 ((DMAMUX_Generator_TypeDef *) DMA2MUX_Generator4_BASE) +#define DMA2MUX_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMA2MUX_ChannelStatus_BASE) +#define DMA2MUX_GeneratorStatus ((DMAMUX_GeneratorStatus_TypeDef *) DMA2MUX_GeneratorStatus_BASE) +#define ERTC ((ERTC_TypeDef *)ERTC_BASE) +#define EXINT ((EXINT_TypeDef *)EXINT_BASE) +#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE) +#define USD ((USD_TypeDef *)USD_BASE) +#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE) +#define GPIOF ((GPIO_TypeDef *)GPIOF_BASE) +#define I2C1 ((I2C_TypeDef *)I2C1_BASE) +#define I2C2 ((I2C_TypeDef *)I2C2_BASE) +#define I2C3 ((I2C_TypeDef *)I2C3_BASE) +#define PWC ((PWC_TypeDef *)PWC_BASE) +#define QSPI1 ((QSPI_TypeDef *)QSPI1_R_BASE) +#define SCFG ((SCFG_TypeDef *)SCFG_BASE) +#define SPI1 ((SPI_TypeDef *)SPI1_BASE) +#define SPI2 ((SPI_TypeDef *)SPI2_BASE) +#define SPI3 ((SPI_TypeDef *)SPI3_BASE) +#define I2SF5 ((SPI_TypeDef *)I2SF5_BASE) +#define TMR1 ((TMR_TypeDef *)TMR1_BASE) +#define TMR2 ((TMR_TypeDef *)TMR2_BASE) +#define TMR3 ((TMR_TypeDef *)TMR3_BASE) +#define TMR4 ((TMR_TypeDef *)TMR4_BASE) +#define TMR6 ((TMR_TypeDef *)TMR6_BASE) +#define TMR7 ((TMR_TypeDef *)TMR7_BASE) +#define TMR9 ((TMR_TypeDef *)TMR9_BASE) +#define TMR10 ((TMR_TypeDef *)TMR10_BASE) +#define TMR11 ((TMR_TypeDef *)TMR11_BASE) +#define TMR13 ((TMR_TypeDef *)TMR13_BASE) +#define TMR14 ((TMR_TypeDef *)TMR14_BASE) +#define USART1 ((USART_TypeDef *)USART1_BASE) +#define USART2 ((USART_TypeDef *)USART2_BASE) +#define USART3 ((USART_TypeDef *)USART3_BASE) +#define USART4 ((USART_TypeDef *)USART4_BASE) +#define USART5 ((USART_TypeDef *)USART5_BASE) +#define USART6 ((USART_TypeDef *)USART6_BASE) +#define UART7 ((USART_TypeDef *)UART7_BASE) +#define UART8 ((USART_TypeDef *)UART8_BASE) +#define WDT ((WDT_TypeDef *)WDT_BASE) +#define WWDT ((WWDT_TypeDef *)WWDT_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral registers bits definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Power Control (PWC) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for PWC_CTRL register *******************/ +#define PWC_CTRL_VRSEL_Pos (0U) +#define PWC_CTRL_VRSEL_Msk (0x1U << PWC_CTRL_VRSEL_Pos) /*!< 0x00000001 */ +#define PWC_CTRL_VRSEL PWC_CTRL_VRSEL_Msk /*!< LDO state select in deep sleep mode */ +#define PWC_CTRL_LPSEL_Pos (1U) +#define PWC_CTRL_LPSEL_Msk (0x1U << PWC_CTRL_LPSEL_Pos) /*!< 0x00000002 */ +#define PWC_CTRL_LPSEL PWC_CTRL_LPSEL_Msk /*!< Low power mode select in deep sleep mode */ +#define PWC_CTRL_CLSWEF_Pos (2U) +#define PWC_CTRL_CLSWEF_Msk (0x1U << PWC_CTRL_CLSWEF_Pos) /*!< 0x00000004 */ +#define PWC_CTRL_CLSWEF PWC_CTRL_CLSWEF_Msk /*!< Clear SWEF flag */ +#define PWC_CTRL_CLSEF_Pos (3U) +#define PWC_CTRL_CLSEF_Msk (0x1U << PWC_CTRL_CLSEF_Pos) /*!< 0x00000008 */ +#define PWC_CTRL_CLSEF PWC_CTRL_CLSEF_Msk /*!< Clear SEF flag */ +#define PWC_CTRL_PVMEN_Pos (4U) +#define PWC_CTRL_PVMEN_Msk (0x1U << PWC_CTRL_PVMEN_Pos) /*!< 0x00000010 */ +#define PWC_CTRL_PVMEN PWC_CTRL_PVMEN_Msk /*!< Power voltage monitoring enable */ + +/*!< PVM level configuration */ +#define PWC_CTRL_PVMSEL_Pos (5U) +#define PWC_CTRL_PVMSEL_Msk (0x7U << PWC_CTRL_PVMSEL_Pos) /*!< 0x000000E0 */ +#define PWC_CTRL_PVMSEL PWC_CTRL_PVMSEL_Msk /*!< PVMSEL[2:0] bits (Power voltage monitoring boundary select) */ +#define PWC_CTRL_PVMSEL_0 (0x1U << PWC_CTRL_PVMSEL_Pos) /*!< 0x00000020 */ +#define PWC_CTRL_PVMSEL_1 (0x2U << PWC_CTRL_PVMSEL_Pos) /*!< 0x00000040 */ +#define PWC_CTRL_PVMSEL_2 (0x4U << PWC_CTRL_PVMSEL_Pos) /*!< 0x00000080 */ + +#define PWC_CTRL_PVMSEL_LEV1 0x00000020U /*!< PVM level 2.3V */ +#define PWC_CTRL_PVMSEL_LEV2 0x00000040U /*!< PVM level 2.4V */ +#define PWC_CTRL_PVMSEL_LEV3 0x00000060U /*!< PVM level 2.5V */ +#define PWC_CTRL_PVMSEL_LEV4 0x00000080U /*!< PVM level 2.6V */ +#define PWC_CTRL_PVMSEL_LEV5 0x000000A0U /*!< PVM level 2.7V */ +#define PWC_CTRL_PVMSEL_LEV6 0x000000C0U /*!< PVM level 2.8V */ +#define PWC_CTRL_PVMSEL_LEV7 0x000000E0U /*!< PVM level 2.9V */ + +/* Legacy defines */ +#define PWC_CTRL_PVMSEL_2V3 PWC_CTRL_PVMSEL_LEV1 +#define PWC_CTRL_PVMSEL_2V4 PWC_CTRL_PVMSEL_LEV2 +#define PWC_CTRL_PVMSEL_2V5 PWC_CTRL_PVMSEL_LEV3 +#define PWC_CTRL_PVMSEL_2V6 PWC_CTRL_PVMSEL_LEV4 +#define PWC_CTRL_PVMSEL_2V7 PWC_CTRL_PVMSEL_LEV5 +#define PWC_CTRL_PVMSEL_2V8 PWC_CTRL_PVMSEL_LEV6 +#define PWC_CTRL_PVMSEL_2V9 PWC_CTRL_PVMSEL_LEV7 + +#define PWC_CTRL_BPWEN_Pos (8U) +#define PWC_CTRL_BPWEN_Msk (0x1U << PWC_CTRL_BPWEN_Pos) /*!< 0x00000100 */ +#define PWC_CTRL_BPWEN PWC_CTRL_BPWEN_Msk /*!< Battery powered domain write enable */ + +/***************** Bit definition for PWC_CTRLSTS register ******************/ +#define PWC_CTRLSTS_SWEF_Pos (0U) +#define PWC_CTRLSTS_SWEF_Msk (0x1U << PWC_CTRLSTS_SWEF_Pos) /*!< 0x00000001 */ +#define PWC_CTRLSTS_SWEF PWC_CTRLSTS_SWEF_Msk /*!< Standby wake-up event flag */ +#define PWC_CTRLSTS_SEF_Pos (1U) +#define PWC_CTRLSTS_SEF_Msk (0x1U << PWC_CTRLSTS_SEF_Pos) /*!< 0x00000002 */ +#define PWC_CTRLSTS_SEF PWC_CTRLSTS_SEF_Msk /*!< Standby mode entry flag */ +#define PWC_CTRLSTS_PVMOF_Pos (2U) +#define PWC_CTRLSTS_PVMOF_Msk (0x1U << PWC_CTRLSTS_PVMOF_Pos) /*!< 0x00000004 */ +#define PWC_CTRLSTS_PVMOF PWC_CTRLSTS_PVMOF_Msk /*!< Power voltage monitoring output flag */ +#define PWC_CTRLSTS_SWPEN1_Pos (8U) +#define PWC_CTRLSTS_SWPEN1_Msk (0x1U << PWC_CTRLSTS_SWPEN1_Pos) /*!< 0x00000100 */ +#define PWC_CTRLSTS_SWPEN1 PWC_CTRLSTS_SWPEN1_Msk /*!< Standby wake-up pin 1 enable */ +#define PWC_CTRLSTS_SWPEN2_Pos (9U) +#define PWC_CTRLSTS_SWPEN2_Msk (0x1U << PWC_CTRLSTS_SWPEN2_Pos) /*!< 0x00000200 */ +#define PWC_CTRLSTS_SWPEN2 PWC_CTRLSTS_SWPEN2_Msk /*!< Standby wake-up pin 2 enable */ +#define PWC_CTRLSTS_SWPEN6_Pos (13U) +#define PWC_CTRLSTS_SWPEN6_Msk (0x1U << PWC_CTRLSTS_SWPEN6_Pos) /*!< 0x00002000 */ +#define PWC_CTRLSTS_SWPEN6 PWC_CTRLSTS_SWPEN6_Msk /*!< Standby wake-up pin 6 enable */ + +/****************** Bit definition for PWC_LDOOV register *******************/ +/*!< LDOOVSEL congiguration */ +#define PWC_LDOOV_LDOOVSEL_Pos (0U) +#define PWC_LDOOV_LDOOVSEL_Msk (0x3U << PWC_LDOOV_LDOOVSEL_Pos) /*!< 0x00000003 */ +#define PWC_LDOOV_LDOOVSEL PWC_LDOOV_LDOOVSEL_Msk /*!< LDOOVSEL[1:0] bits (Voltage regulator output voltage select) */ +#define PWC_LDOOV_LDOOVSEL_0 (0x1U << PWC_LDOOV_LDOOVSEL_Pos) /*!< 0x00000001 */ +#define PWC_LDOOV_LDOOVSEL_1 (0x2U << PWC_LDOOV_LDOOVSEL_Pos) /*!< 0x00000002 */ + +#define PWC_LDOOV_LDOOVSEL_LEV0 0x00000000U /*!< Voltage output level 1.0V */ +#define PWC_LDOOV_LDOOVSEL_LEV2 0x00000002U /*!< Voltage output level 1.2V */ +#define PWC_LDOOV_LDOOVSEL_LEV3 0x00000003U /*!< Voltage output level 1.3V */ + +/* Legacy defines */ +#define PWC_LDOOV_LDOOVSEL_1V0 PWC_LDOOV_LDOOVSEL_LEV0 +#define PWC_LDOOV_LDOOVSEL_1V2 PWC_LDOOV_LDOOVSEL_LEV2 +#define PWC_LDOOV_LDOOVSEL_1V3 PWC_LDOOV_LDOOVSEL_LEV3 + +#define PWC_LDOOV_VREXLPEN_Pos (4U) +#define PWC_LDOOV_VREXLPEN_Msk (0x1U << PWC_LDOOV_VREXLPEN_Pos) /*!< 0x00000010 */ +#define PWC_LDOOV_VREXLPEN PWC_LDOOV_VREXLPEN_Msk /*!< Voltage regulator extra low power mode enable */ + +/******************************************************************************/ +/* */ +/* Clock and reset manage (CRM) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for CRM_CTRL register *******************/ +#define CRM_CTRL_HICKEN_Pos (0U) +#define CRM_CTRL_HICKEN_Msk (0x1U << CRM_CTRL_HICKEN_Pos) /*!< 0x00000001 */ +#define CRM_CTRL_HICKEN CRM_CTRL_HICKEN_Msk /*!< High speed internal clock enable */ +#define CRM_CTRL_HICKSTBL_Pos (1U) +#define CRM_CTRL_HICKSTBL_Msk (0x1U << CRM_CTRL_HICKSTBL_Pos) /*!< 0x00000002 */ +#define CRM_CTRL_HICKSTBL CRM_CTRL_HICKSTBL_Msk /*!< High speed internal clock stable */ +#define CRM_CTRL_HICKTRIM_Pos (2U) +#define CRM_CTRL_HICKTRIM_Msk (0x3FU << CRM_CTRL_HICKTRIM_Pos) /*!< 0x000000FC */ +#define CRM_CTRL_HICKTRIM CRM_CTRL_HICKTRIM_Msk /*!< High speed internal clock trimming */ +#define CRM_CTRL_HICKCAL_Pos (8U) +#define CRM_CTRL_HICKCAL_Msk (0xFFU << CRM_CTRL_HICKCAL_Pos) /*!< 0x0000FF00 */ +#define CRM_CTRL_HICKCAL CRM_CTRL_HICKCAL_Msk /*!< High speed internal clock calibration */ +#define CRM_CTRL_HEXTEN_Pos (16U) +#define CRM_CTRL_HEXTEN_Msk (0x1U << CRM_CTRL_HEXTEN_Pos) /*!< 0x00010000 */ +#define CRM_CTRL_HEXTEN CRM_CTRL_HEXTEN_Msk /*!< High speed external crystal enable */ +#define CRM_CTRL_HEXTSTBL_Pos (17U) +#define CRM_CTRL_HEXTSTBL_Msk (0x1U << CRM_CTRL_HEXTSTBL_Pos) /*!< 0x00020000 */ +#define CRM_CTRL_HEXTSTBL CRM_CTRL_HEXTSTBL_Msk /*!< High speed external crystal stable */ +#define CRM_CTRL_HEXTBYPS_Pos (18U) +#define CRM_CTRL_HEXTBYPS_Msk (0x1U << CRM_CTRL_HEXTBYPS_Pos) /*!< 0x00040000 */ +#define CRM_CTRL_HEXTBYPS CRM_CTRL_HEXTBYPS_Msk /*!< High speed external crystal bypass */ +#define CRM_CTRL_CFDEN_Pos (19U) +#define CRM_CTRL_CFDEN_Msk (0x1U << CRM_CTRL_CFDEN_Pos) /*!< 0x00080000 */ +#define CRM_CTRL_CFDEN CRM_CTRL_CFDEN_Msk /*!< Clock failure detector enable */ +#define CRM_CTRL_PLLEN_Pos (24U) +#define CRM_CTRL_PLLEN_Msk (0x1U << CRM_CTRL_PLLEN_Pos) /*!< 0x01000000 */ +#define CRM_CTRL_PLLEN CRM_CTRL_PLLEN_Msk /*!< PLL enable */ +#define CRM_CTRL_PLLSTBL_Pos (25U) +#define CRM_CTRL_PLLSTBL_Msk (0x1U << CRM_CTRL_PLLSTBL_Pos) /*!< 0x02000000 */ +#define CRM_CTRL_PLLSTBL CRM_CTRL_PLLSTBL_Msk /*!< PLL clock stable */ +#define CRM_CTRL_PLLUSTBL_Pos (26U) +#define CRM_CTRL_PLLUSTBL_Msk (0x1U << CRM_CTRL_PLLUSTBL_Pos) /*!< 0x04000000 */ +#define CRM_CTRL_PLLUSTBL CRM_CTRL_PLLUSTBL_Msk /*!< PLLU clock stable */ + +/****************** Bit definition for CRM_PLLCFG register ******************/ +/*!< PLL_MS congiguration */ +#define CRM_PLLCFG_PLL_MS_Pos (0U) +#define CRM_PLLCFG_PLL_MS_Msk (0xFU << CRM_PLLCFG_PLL_MS_Pos) /*!< 0x0000000F */ +#define CRM_PLLCFG_PLL_MS CRM_PLLCFG_PLL_MS_Msk /*!< PLL_MS[3:0] bits (PLL pre-division) */ +#define CRM_PLLCFG_PLL_MS_0 (0x1U << CRM_PLLCFG_PLL_MS_Pos) /*!< 0x00000001 */ +#define CRM_PLLCFG_PLL_MS_1 (0x2U << CRM_PLLCFG_PLL_MS_Pos) /*!< 0x00000002 */ +#define CRM_PLLCFG_PLL_MS_2 (0x4U << CRM_PLLCFG_PLL_MS_Pos) /*!< 0x00000004 */ +#define CRM_PLLCFG_PLL_MS_3 (0x8U << CRM_PLLCFG_PLL_MS_Pos) /*!< 0x00000008 */ + +/*!< PLL_NS congiguration */ +#define CRM_PLLCFG_PLL_NS_Pos (6U) +#define CRM_PLLCFG_PLL_NS_Msk (0x1FFU << CRM_PLLCFG_PLL_NS_Pos) /*!< 0x00007FC0 */ +#define CRM_PLLCFG_PLL_NS CRM_PLLCFG_PLL_NS_Msk /*!< PLL_NS[8:0] bits (PLL multiplication factor) */ +#define CRM_PLLCFG_PLL_NS_0 (0x001U << CRM_PLLCFG_PLL_NS_Pos) /*!< 0x00000040 */ +#define CRM_PLLCFG_PLL_NS_1 (0x002U << CRM_PLLCFG_PLL_NS_Pos) /*!< 0x00000080 */ +#define CRM_PLLCFG_PLL_NS_2 (0x004U << CRM_PLLCFG_PLL_NS_Pos) /*!< 0x00000100 */ +#define CRM_PLLCFG_PLL_NS_3 (0x008U << CRM_PLLCFG_PLL_NS_Pos) /*!< 0x00000200 */ +#define CRM_PLLCFG_PLL_NS_4 (0x010U << CRM_PLLCFG_PLL_NS_Pos) /*!< 0x00000400 */ +#define CRM_PLLCFG_PLL_NS_5 (0x020U << CRM_PLLCFG_PLL_NS_Pos) /*!< 0x00000800 */ +#define CRM_PLLCFG_PLL_NS_6 (0x040U << CRM_PLLCFG_PLL_NS_Pos) /*!< 0x00001000 */ +#define CRM_PLLCFG_PLL_NS_7 (0x080U << CRM_PLLCFG_PLL_NS_Pos) /*!< 0x00002000 */ +#define CRM_PLLCFG_PLL_NS_8 (0x100U << CRM_PLLCFG_PLL_NS_Pos) /*!< 0x00004000 */ + +/*!< PLL_FP congiguration */ +#define CRM_PLLCFG_PLL_FP_Pos (16U) +#define CRM_PLLCFG_PLL_FP_Msk (0xFU << CRM_PLLCFG_PLL_FP_Pos) /*!< 0x000F0000 */ +#define CRM_PLLCFG_PLL_FP CRM_PLLCFG_PLL_FP_Msk /*!< PLL_FP[3:0] bits (PLLP post-division) */ +#define CRM_PLLCFG_PLL_FP_0 (0x1U << CRM_PLLCFG_PLL_FP_Pos) /*!< 0x00010000 */ +#define CRM_PLLCFG_PLL_FP_1 (0x2U << CRM_PLLCFG_PLL_FP_Pos) /*!< 0x00020000 */ +#define CRM_PLLCFG_PLL_FP_2 (0x4U << CRM_PLLCFG_PLL_FP_Pos) /*!< 0x00040000 */ +#define CRM_PLLCFG_PLL_FP_3 (0x8U << CRM_PLLCFG_PLL_FP_Pos) /*!< 0x00080000 */ + +/*!< PLL_FU congiguration */ +#define CRM_PLLCFG_PLL_FU_Pos (20U) +#define CRM_PLLCFG_PLL_FU_Msk (0x7U << CRM_PLLCFG_PLL_FU_Pos) /*!< 0x00700000 */ +#define CRM_PLLCFG_PLL_FU CRM_PLLCFG_PLL_FU_Msk /*!< PLL_FU[2:0] bits (PLLU post-division) */ +#define CRM_PLLCFG_PLL_FU_0 (0x1U << CRM_PLLCFG_PLL_FU_Pos) /*!< 0x00100000 */ +#define CRM_PLLCFG_PLL_FU_1 (0x2U << CRM_PLLCFG_PLL_FU_Pos) /*!< 0x00200000 */ +#define CRM_PLLCFG_PLL_FU_2 (0x4U << CRM_PLLCFG_PLL_FU_Pos) /*!< 0x00400000 */ + +#define CRM_PLLCFG_PLLU_EN_Pos (29U) +#define CRM_PLLCFG_PLLU_EN_Msk (0x1U << CRM_PLLCFG_PLLU_EN_Pos) /*!< 0x20000000 */ +#define CRM_PLLCFG_PLLU_EN CRM_PLLCFG_PLLU_EN_Msk /*!< PLLU enable */ +#define CRM_PLLCFG_PLLRCS_Pos (30U) +#define CRM_PLLCFG_PLLRCS_Msk (0x1U << CRM_PLLCFG_PLLRCS_Pos) /*!< 0x40000000 */ +#define CRM_PLLCFG_PLLRCS CRM_PLLCFG_PLLRCS_Msk /*!< PLL reference clock select */ +#define CRM_PLLCFG_PLLRST_Pos (31U) +#define CRM_PLLCFG_PLLRST_Msk (0x1U << CRM_PLLCFG_PLLRST_Pos) /*!< 0x80000000 */ +#define CRM_PLLCFG_PLLRST CRM_PLLCFG_PLLRST_Msk /*!< PLLRST */ + +/******************* Bit definition for CRM_CFG register ********************/ +/*!< SCLKSEL configuration */ +#define CRM_CFG_SCLKSEL_Pos (0U) +#define CRM_CFG_SCLKSEL_Msk (0x3U << CRM_CFG_SCLKSEL_Pos) /*!< 0x00000003 */ +#define CRM_CFG_SCLKSEL CRM_CFG_SCLKSEL_Msk /*!< SCLKSEL[1:0] bits (System clock select) */ +#define CRM_CFG_SCLKSEL_0 (0x1U << CRM_CFG_SCLKSEL_Pos) /*!< 0x00000001 */ +#define CRM_CFG_SCLKSEL_1 (0x2U << CRM_CFG_SCLKSEL_Pos) /*!< 0x00000002 */ + +#define CRM_CFG_SCLKSEL_HICK 0x00000000U /*!< HICK */ +#define CRM_CFG_SCLKSEL_HEXT 0x00000001U /*!< HEXT */ +#define CRM_CFG_SCLKSEL_PLL 0x00000002U /*!< PLL */ + +/*!< SCLKSTS configuration */ +#define CRM_CFG_SCLKSTS_Pos (2U) +#define CRM_CFG_SCLKSTS_Msk (0x3U << CRM_CFG_SCLKSTS_Pos) /*!< 0x0000000C */ +#define CRM_CFG_SCLKSTS CRM_CFG_SCLKSTS_Msk /*!< SCLKSTS[1:0] bits (System clock select status) */ +#define CRM_CFG_SCLKSTS_0 (0x1U << CRM_CFG_SCLKSTS_Pos) /*!< 0x00000004 */ +#define CRM_CFG_SCLKSTS_1 (0x2U << CRM_CFG_SCLKSTS_Pos) /*!< 0x00000008 */ + +#define CRM_CFG_SCLKSTS_HICK 0x00000000U /*!< HICK */ +#define CRM_CFG_SCLKSTS_HEXT 0x00000004U /*!< HEXT */ +#define CRM_CFG_SCLKSTS_PLL 0x00000008U /*!< PLL */ + +/*!< AHBDIV configuration */ +#define CRM_CFG_AHBDIV_Pos (4U) +#define CRM_CFG_AHBDIV_Msk (0xFU << CRM_CFG_AHBDIV_Pos) /*!< 0x000000F0 */ +#define CRM_CFG_AHBDIV CRM_CFG_AHBDIV_Msk /*!< AHBDIV[3:0] bits (AHB division) */ +#define CRM_CFG_AHBDIV_0 (0x1U << CRM_CFG_AHBDIV_Pos) /*!< 0x00000010 */ +#define CRM_CFG_AHBDIV_1 (0x2U << CRM_CFG_AHBDIV_Pos) /*!< 0x00000020 */ +#define CRM_CFG_AHBDIV_2 (0x4U << CRM_CFG_AHBDIV_Pos) /*!< 0x00000040 */ +#define CRM_CFG_AHBDIV_3 (0x8U << CRM_CFG_AHBDIV_Pos) /*!< 0x00000080 */ + +#define CRM_CFG_AHBDIV_DIV1 0x00000000U /*!< SCLK is not divided */ +#define CRM_CFG_AHBDIV_DIV2 0x00000080U /*!< SCLK is divided by 2 */ +#define CRM_CFG_AHBDIV_DIV4 0x00000090U /*!< SCLK is divided by 4 */ +#define CRM_CFG_AHBDIV_DIV8 0x000000A0U /*!< SCLK is divided by 8 */ +#define CRM_CFG_AHBDIV_DIV16 0x000000B0U /*!< SCLK is divided by 16 */ +#define CRM_CFG_AHBDIV_DIV64 0x000000C0U /*!< SCLK is divided by 64 */ +#define CRM_CFG_AHBDIV_DIV128 0x000000D0U /*!< SCLK is divided by 128 */ +#define CRM_CFG_AHBDIV_DIV256 0x000000E0U /*!< SCLK is divided by 256 */ +#define CRM_CFG_AHBDIV_DIV512 0x000000F0U /*!< SCLK is divided by 512 */ + +/*!< APB1DIV configuration */ +#define CRM_CFG_APB1DIV_Pos (10U) +#define CRM_CFG_APB1DIV_Msk (0x7U << CRM_CFG_APB1DIV_Pos) /*!< 0x00001C00 */ +#define CRM_CFG_APB1DIV CRM_CFG_APB1DIV_Msk /*!< APB1DIV[2:0] bits (APB1 division) */ +#define CRM_CFG_APB1DIV_0 (0x1U << CRM_CFG_APB1DIV_Pos) /*!< 0x00000400 */ +#define CRM_CFG_APB1DIV_1 (0x2U << CRM_CFG_APB1DIV_Pos) /*!< 0x00000800 */ +#define CRM_CFG_APB1DIV_2 (0x4U << CRM_CFG_APB1DIV_Pos) /*!< 0x00001000 */ + +#define CRM_CFG_APB1DIV_DIV1 0x00000000U /*!< HCLK is not divided */ +#define CRM_CFG_APB1DIV_DIV2 0x00001000U /*!< HCLK is divided by 2 */ +#define CRM_CFG_APB1DIV_DIV4 0x00001400U /*!< HCLK is divided by 4 */ +#define CRM_CFG_APB1DIV_DIV8 0x00001800U /*!< HCLK is divided by 8 */ +#define CRM_CFG_APB1DIV_DIV16 0x00001C00U /*!< HCLK is divided by 16 */ + +/*!< APB2DIV configuration */ +#define CRM_CFG_APB2DIV_Pos (13U) +#define CRM_CFG_APB2DIV_Msk (0x7U << CRM_CFG_APB2DIV_Pos) /*!< 0x0000E000 */ +#define CRM_CFG_APB2DIV CRM_CFG_APB2DIV_Msk /*!< APB2DIV[2:0] bits (APB2 division) */ +#define CRM_CFG_APB2DIV_0 (0x1U << CRM_CFG_APB2DIV_Pos) /*!< 0x00002000 */ +#define CRM_CFG_APB2DIV_1 (0x2U << CRM_CFG_APB2DIV_Pos) /*!< 0x00004000 */ +#define CRM_CFG_APB2DIV_2 (0x4U << CRM_CFG_APB2DIV_Pos) /*!< 0x00008000 */ + +#define CRM_CFG_APB2DIV_DIV1 0x00000000U /*!< HCLK is not divided */ +#define CRM_CFG_APB2DIV_DIV2 0x00008000U /*!< HCLK is divided by 2 */ +#define CRM_CFG_APB2DIV_DIV4 0x0000A000U /*!< HCLK is divided by 4 */ +#define CRM_CFG_APB2DIV_DIV8 0x0000C000U /*!< HCLK is divided by 8 */ +#define CRM_CFG_APB2DIV_DIV16 0x0000E000U /*!< HCLK is divided by 16 */ + +/*!< ERTCDIV configuration */ +#define CRM_CFG_ERTCDIV_Pos (16U) +#define CRM_CFG_ERTCDIV_Msk (0x1FU << CRM_CFG_ERTCDIV_Pos) /*!< 0x001F0000 */ +#define CRM_CFG_ERTCDIV CRM_CFG_ERTCDIV_Msk /*!< ERTCDIV[4:0] bits (HEXT division for ERTC clock) */ +#define CRM_CFG_ERTCDIV_0 (0x01U << CRM_CFG_ERTCDIV_Pos) /*!< 0x00010000 */ +#define CRM_CFG_ERTCDIV_1 (0x02U << CRM_CFG_ERTCDIV_Pos) /*!< 0x00020000 */ +#define CRM_CFG_ERTCDIV_2 (0x04U << CRM_CFG_ERTCDIV_Pos) /*!< 0x00040000 */ +#define CRM_CFG_ERTCDIV_3 (0x08U << CRM_CFG_ERTCDIV_Pos) /*!< 0x00080000 */ +#define CRM_CFG_ERTCDIV_4 (0x10U << CRM_CFG_ERTCDIV_Pos) /*!< 0x00100000 */ + +#define CRM_CFG_ERTCDIV_DIV2 0x00020000U /*!< HEXT/2 */ +#define CRM_CFG_ERTCDIV_DIV3 0x00030000U /*!< HEXT/3 */ +#define CRM_CFG_ERTCDIV_DIV4 0x00040000U /*!< HEXT/4 */ +#define CRM_CFG_ERTCDIV_DIV5 0x00050000U /*!< HEXT/5 */ +#define CRM_CFG_ERTCDIV_DIV6 0x00060000U /*!< HEXT/6 */ +#define CRM_CFG_ERTCDIV_DIV7 0x00070000U /*!< HEXT/7 */ +#define CRM_CFG_ERTCDIV_DIV8 0x00080000U /*!< HEXT/8 */ +#define CRM_CFG_ERTCDIV_DIV9 0x00090000U /*!< HEXT/9 */ +#define CRM_CFG_ERTCDIV_DIV10 0x000A0000U /*!< HEXT/10 */ +#define CRM_CFG_ERTCDIV_DIV11 0x000B0000U /*!< HEXT/11 */ +#define CRM_CFG_ERTCDIV_DIV12 0x000C0000U /*!< HEXT/12 */ +#define CRM_CFG_ERTCDIV_DIV13 0x000D0000U /*!< HEXT/13 */ +#define CRM_CFG_ERTCDIV_DIV14 0x000E0000U /*!< HEXT/14 */ +#define CRM_CFG_ERTCDIV_DIV15 0x000F0000U /*!< HEXT/15 */ +#define CRM_CFG_ERTCDIV_DIV16 0x00100000U /*!< HEXT/16 */ +#define CRM_CFG_ERTCDIV_DIV17 0x00110000U /*!< HEXT/17 */ +#define CRM_CFG_ERTCDIV_DIV18 0x00120000U /*!< HEXT/18 */ +#define CRM_CFG_ERTCDIV_DIV19 0x00130000U /*!< HEXT/19 */ +#define CRM_CFG_ERTCDIV_DIV20 0x00140000U /*!< HEXT/20 */ +#define CRM_CFG_ERTCDIV_DIV21 0x00150000U /*!< HEXT/21 */ +#define CRM_CFG_ERTCDIV_DIV22 0x00160000U /*!< HEXT/22 */ +#define CRM_CFG_ERTCDIV_DIV23 0x00170000U /*!< HEXT/23 */ +#define CRM_CFG_ERTCDIV_DIV24 0x00180000U /*!< HEXT/24 */ +#define CRM_CFG_ERTCDIV_DIV25 0x00190000U /*!< HEXT/25 */ +#define CRM_CFG_ERTCDIV_DIV26 0x001A0000U /*!< HEXT/26 */ +#define CRM_CFG_ERTCDIV_DIV27 0x001B0000U /*!< HEXT/27 */ +#define CRM_CFG_ERTCDIV_DIV28 0x001C0000U /*!< HEXT/28 */ +#define CRM_CFG_ERTCDIV_DIV29 0x001D0000U /*!< HEXT/29 */ +#define CRM_CFG_ERTCDIV_DIV30 0x001E0000U /*!< HEXT/30 */ +#define CRM_CFG_ERTCDIV_DIV31 0x001F0000U /*!< HEXT/31 */ + +/*!< I2SF5CLKSEL configuration */ +#define CRM_CFG_I2SF5CLKSEL_Pos (22U) +#define CRM_CFG_I2SF5CLKSEL_Msk (0x3U << CRM_CFG_I2SF5CLKSEL_Pos) /*!< 0x00C00000 */ +#define CRM_CFG_I2SF5CLKSEL CRM_CFG_I2SF5CLKSEL_Msk /*!< I2SF5CLKSEL[1:0] bits (I2SF5 clock source selection) */ +#define CRM_CFG_I2SF5CLKSEL_0 (0x1U << CRM_CFG_I2SF5CLKSEL_Pos) /*!< 0x00400000 */ +#define CRM_CFG_I2SF5CLKSEL_1 (0x2U << CRM_CFG_I2SF5CLKSEL_Pos) /*!< 0x00800000 */ + +#define CRM_CFG_I2SF5CLKSEL_SCLK 0x00000000U /*!< System clock */ +#define CRM_CFG_I2SF5CLKSEL_PLL 0x00400000U /*!< PLL */ +#define CRM_CFG_I2SF5CLKSEL_HICK 0x00800000U /*!< HICK */ +#define CRM_CFG_I2SF5CLKSEL_EXTERNAL 0x00C00000U /*!< External input clock */ + +/*!< CLKOUTDIV1 configuration */ +#define CRM_CFG_CLKOUTDIV1_Pos (27U) +#define CRM_CFG_CLKOUTDIV1_Msk (0x7U << CRM_CFG_CLKOUTDIV1_Pos) /*!< 0x38000000 */ +#define CRM_CFG_CLKOUTDIV1 CRM_CFG_CLKOUTDIV1_Msk /*!< CLKOUTDIV1[2:0] bits (Clock output division 1) */ +#define CRM_CFG_CLKOUTDIV1_0 (0x1U << CRM_CFG_CLKOUTDIV1_Pos) /*!< 0x08000000 */ +#define CRM_CFG_CLKOUTDIV1_1 (0x2U << CRM_CFG_CLKOUTDIV1_Pos) /*!< 0x10000000 */ +#define CRM_CFG_CLKOUTDIV1_2 (0x4U << CRM_CFG_CLKOUTDIV1_Pos) /*!< 0x20000000 */ + +#define CRM_CFG_CLKOUTDIV1_DIV1 0x00000000U /*!< No clock output */ +#define CRM_CFG_CLKOUTDIV1_DIV2 0x20000000U /*!< Clock output divided by 2 */ +#define CRM_CFG_CLKOUTDIV1_DIV3 0x28000000U /*!< Clock output divided by 3 */ +#define CRM_CFG_CLKOUTDIV1_DIV4 0x30000000U /*!< Clock output divided by 4 */ +#define CRM_CFG_CLKOUTDIV1_DIV5 0x38000000U /*!< Clock output divided by 5 */ + +/*!< CLKOUT_SEL1 configuration */ +#define CRM_CFG_CLKOUT_SEL1_Pos (30U) +#define CRM_CFG_CLKOUT_SEL1_Msk (0x3U << CRM_CFG_CLKOUT_SEL1_Pos) /*!< 0xC0000000 */ +#define CRM_CFG_CLKOUT_SEL1 CRM_CFG_CLKOUT_SEL1_Msk /*!< CLKOUT_SEL1[1:0] bits (Clock output selection 1) */ +#define CRM_CFG_CLKOUT_SEL1_0 (0x1U << CRM_CFG_CLKOUT_SEL1_Pos) /*!< 0x40000000 */ +#define CRM_CFG_CLKOUT_SEL1_1 (0x2U << CRM_CFG_CLKOUT_SEL1_Pos) /*!< 0x80000000 */ + +#define CRM_CFG_CLKOUT_SEL1_SCLK 0x00000000U /*!< System clock */ +#define CRM_CFG_CLKOUT_SEL1_CLKOUT_SEL2 0x40000000U /*!< CLKOUT_SEL2 bit in the CRM_MISC1 register */ +#define CRM_CFG_CLKOUT_SEL1_HEXT 0x80000000U /*!< HEXT */ +#define CRM_CFG_CLKOUT_SEL1_PLL 0xC0000000U /*!< PLL */ + +/* Reference defines */ +#define CRM_CFG_CLKSEL1 CRM_CFG_CLKOUT_SEL1 +#define CRM_CFG_CLKSEL1_0 CRM_CFG_CLKOUT_SEL1_0 +#define CRM_CFG_CLKSEL1_1 CRM_CFG_CLKOUT_SEL1_1 +#define CRM_CFG_CLKSEL1_SCLK CRM_CFG_CLKOUT_SEL1_SCLK +#define CRM_CFG_CLKSEL1_CLKOUT_SEL2 CRM_CFG_CLKOUT_SEL1_CLKOUT_SEL2 +#define CRM_CFG_CLKSEL1_HEXT CRM_CFG_CLKOUT_SEL1_HEXT +#define CRM_CFG_CLKSEL1_PLL CRM_CFG_CLKOUT_SEL1_PLL + +/*!<*************** Bit definition for CRM_CLKINT register ******************/ +#define CRM_CLKINT_LICKSTBLF_Pos (0U) +#define CRM_CLKINT_LICKSTBLF_Msk (0x1U << CRM_CLKINT_LICKSTBLF_Pos) /*!< 0x00000001 */ +#define CRM_CLKINT_LICKSTBLF CRM_CLKINT_LICKSTBLF_Msk /*!< LICK stable interrupt flag */ +#define CRM_CLKINT_LEXTSTBLF_Pos (1U) +#define CRM_CLKINT_LEXTSTBLF_Msk (0x1U << CRM_CLKINT_LEXTSTBLF_Pos) /*!< 0x00000002 */ +#define CRM_CLKINT_LEXTSTBLF CRM_CLKINT_LEXTSTBLF_Msk /*!< LEXT stable flag */ +#define CRM_CLKINT_HICKSTBLF_Pos (2U) +#define CRM_CLKINT_HICKSTBLF_Msk (0x1U << CRM_CLKINT_HICKSTBLF_Pos) /*!< 0x00000004 */ +#define CRM_CLKINT_HICKSTBLF CRM_CLKINT_HICKSTBLF_Msk /*!< HICK stable flag */ +#define CRM_CLKINT_HEXTSTBLF_Pos (3U) +#define CRM_CLKINT_HEXTSTBLF_Msk (0x1U << CRM_CLKINT_HEXTSTBLF_Pos) /*!< 0x00000008 */ +#define CRM_CLKINT_HEXTSTBLF CRM_CLKINT_HEXTSTBLF_Msk /*!< HEXT stable flag */ +#define CRM_CLKINT_PLLSTBLF_Pos (4U) +#define CRM_CLKINT_PLLSTBLF_Msk (0x1U << CRM_CLKINT_PLLSTBLF_Pos) /*!< 0x00000010 */ +#define CRM_CLKINT_PLLSTBLF CRM_CLKINT_PLLSTBLF_Msk /*!< PLL stable flag */ +#define CRM_CLKINT_CFDF_Pos (7U) +#define CRM_CLKINT_CFDF_Msk (0x1U << CRM_CLKINT_CFDF_Pos) /*!< 0x00000080 */ +#define CRM_CLKINT_CFDF CRM_CLKINT_CFDF_Msk /*!< Clock failure detection flag */ +#define CRM_CLKINT_LICKSTBLIEN_Pos (8U) +#define CRM_CLKINT_LICKSTBLIEN_Msk (0x1U << CRM_CLKINT_LICKSTBLIEN_Pos) /*!< 0x00000100 */ +#define CRM_CLKINT_LICKSTBLIEN CRM_CLKINT_LICKSTBLIEN_Msk /*!< LICK stable interrupt enable */ +#define CRM_CLKINT_LEXTSTBLIEN_Pos (9U) +#define CRM_CLKINT_LEXTSTBLIEN_Msk (0x1U << CRM_CLKINT_LEXTSTBLIEN_Pos) /*!< 0x00000200 */ +#define CRM_CLKINT_LEXTSTBLIEN CRM_CLKINT_LEXTSTBLIEN_Msk /*!< LEXT stable interrupt enable */ +#define CRM_CLKINT_HICKSTBLIEN_Pos (10U) +#define CRM_CLKINT_HICKSTBLIEN_Msk (0x1U << CRM_CLKINT_HICKSTBLIEN_Pos) /*!< 0x00000400 */ +#define CRM_CLKINT_HICKSTBLIEN CRM_CLKINT_HICKSTBLIEN_Msk /*!< HICK stable interrupt enable */ +#define CRM_CLKINT_HEXTSTBLIEN_Pos (11U) +#define CRM_CLKINT_HEXTSTBLIEN_Msk (0x1U << CRM_CLKINT_HEXTSTBLIEN_Pos) /*!< 0x00000800 */ +#define CRM_CLKINT_HEXTSTBLIEN CRM_CLKINT_HEXTSTBLIEN_Msk /*!< HEXT stable interrupt enable */ +#define CRM_CLKINT_PLLSTBLIEN_Pos (12U) +#define CRM_CLKINT_PLLSTBLIEN_Msk (0x1U << CRM_CLKINT_PLLSTBLIEN_Pos) /*!< 0x00001000 */ +#define CRM_CLKINT_PLLSTBLIEN CRM_CLKINT_PLLSTBLIEN_Msk /*!< PLL stable interrupt enable */ +#define CRM_CLKINT_LICKSTBLFC_Pos (16U) +#define CRM_CLKINT_LICKSTBLFC_Msk (0x1U << CRM_CLKINT_LICKSTBLFC_Pos) /*!< 0x00010000 */ +#define CRM_CLKINT_LICKSTBLFC CRM_CLKINT_LICKSTBLFC_Msk /*!< LICK stable flag clear */ +#define CRM_CLKINT_LEXTSTBLFC_Pos (17U) +#define CRM_CLKINT_LEXTSTBLFC_Msk (0x1U << CRM_CLKINT_LEXTSTBLFC_Pos) /*!< 0x00020000 */ +#define CRM_CLKINT_LEXTSTBLFC CRM_CLKINT_LEXTSTBLFC_Msk /*!< LEXT stable flag clear */ +#define CRM_CLKINT_HICKSTBLFC_Pos (18U) +#define CRM_CLKINT_HICKSTBLFC_Msk (0x1U << CRM_CLKINT_HICKSTBLFC_Pos) /*!< 0x00040000 */ +#define CRM_CLKINT_HICKSTBLFC CRM_CLKINT_HICKSTBLFC_Msk /*!< HICK stable flag clear */ +#define CRM_CLKINT_HEXTSTBLFC_Pos (19U) +#define CRM_CLKINT_HEXTSTBLFC_Msk (0x1U << CRM_CLKINT_HEXTSTBLFC_Pos) /*!< 0x00080000 */ +#define CRM_CLKINT_HEXTSTBLFC CRM_CLKINT_HEXTSTBLFC_Msk /*!< HEXT stable flag clear */ +#define CRM_CLKINT_PLLSTBLFC_Pos (20U) +#define CRM_CLKINT_PLLSTBLFC_Msk (0x1U << CRM_CLKINT_PLLSTBLFC_Pos) /*!< 0x00100000 */ +#define CRM_CLKINT_PLLSTBLFC CRM_CLKINT_PLLSTBLFC_Msk /*!< PLL stable flag clear */ +#define CRM_CLKINT_CFDFC_Pos (23U) +#define CRM_CLKINT_CFDFC_Msk (0x1U << CRM_CLKINT_CFDFC_Pos) /*!< 0x00800000 */ +#define CRM_CLKINT_CFDFC CRM_CLKINT_CFDFC_Msk /*!< Clock failure detection flag clear */ + +/***************** Bit definition for CRM_AHBRST1 register ******************/ +#define CRM_AHBRST1_GPIOARST_Pos (0U) +#define CRM_AHBRST1_GPIOARST_Msk (0x1U << CRM_AHBRST1_GPIOARST_Pos) /*!< 0x00000001 */ +#define CRM_AHBRST1_GPIOARST CRM_AHBRST1_GPIOARST_Msk /*!< IO port A reset */ +#define CRM_AHBRST1_GPIOBRST_Pos (1U) +#define CRM_AHBRST1_GPIOBRST_Msk (0x1U << CRM_AHBRST1_GPIOBRST_Pos) /*!< 0x00000002 */ +#define CRM_AHBRST1_GPIOBRST CRM_AHBRST1_GPIOBRST_Msk /*!< IO port B reset */ +#define CRM_AHBRST1_GPIOCRST_Pos (2U) +#define CRM_AHBRST1_GPIOCRST_Msk (0x1U << CRM_AHBRST1_GPIOCRST_Pos) /*!< 0x00000004 */ +#define CRM_AHBRST1_GPIOCRST CRM_AHBRST1_GPIOCRST_Msk /*!< IO port C reset */ +#define CRM_AHBRST1_GPIODRST_Pos (3U) +#define CRM_AHBRST1_GPIODRST_Msk (0x1U << CRM_AHBRST1_GPIODRST_Pos) /*!< 0x00000008 */ +#define CRM_AHBRST1_GPIODRST CRM_AHBRST1_GPIODRST_Msk /*!< IO port D reset */ +#define CRM_AHBRST1_GPIOFRST_Pos (5U) +#define CRM_AHBRST1_GPIOFRST_Msk (0x1U << CRM_AHBRST1_GPIOFRST_Pos) /*!< 0x00000020 */ +#define CRM_AHBRST1_GPIOFRST CRM_AHBRST1_GPIOFRST_Msk /*!< IO port F reset */ +#define CRM_AHBRST1_CRCRST_Pos (12U) +#define CRM_AHBRST1_CRCRST_Msk (0x1U << CRM_AHBRST1_CRCRST_Pos) /*!< 0x00001000 */ +#define CRM_AHBRST1_CRCRST CRM_AHBRST1_CRCRST_Msk /*!< CRC reset */ +#define CRM_AHBRST1_DMA1RST_Pos (22U) +#define CRM_AHBRST1_DMA1RST_Msk (0x1U << CRM_AHBRST1_DMA1RST_Pos) /*!< 0x00400000 */ +#define CRM_AHBRST1_DMA1RST CRM_AHBRST1_DMA1RST_Msk /*!< DMA1 reset */ +#define CRM_AHBRST1_DMA2RST_Pos (24U) +#define CRM_AHBRST1_DMA2RST_Msk (0x1U << CRM_AHBRST1_DMA2RST_Pos) /*!< 0x01000000 */ +#define CRM_AHBRST1_DMA2RST CRM_AHBRST1_DMA2RST_Msk /*!< DMA2 reset */ +#define CRM_AHBRST1_OTGHSRST_Pos (29U) +#define CRM_AHBRST1_OTGHSRST_Msk (0x1U << CRM_AHBRST1_OTGHSRST_Pos) /*!< 0x20000000 */ +#define CRM_AHBRST1_OTGHSRST CRM_AHBRST1_OTGHSRST_Msk /*!< OTGHS reset (F405 only) */ + +/***************** Bit definition for CRM_AHBRST2 register ******************/ +#define CRM_AHBRST2_OTGFSRST_Pos (7U) +#define CRM_AHBRST2_OTGFSRST_Msk (0x1U << CRM_AHBRST2_OTGFSRST_Pos) /*!< 0x00000080 */ +#define CRM_AHBRST2_OTGFSRST CRM_AHBRST2_OTGFSRST_Msk /*!< OTGFS reset */ + +/***************** Bit definition for CRM_AHBRST3 register ******************/ +#define CRM_AHBRST3_QSPI1RST_Pos (1U) +#define CRM_AHBRST3_QSPI1RST_Msk (0x1U << CRM_AHBRST3_QSPI1RST_Pos) /*!< 0x00000002 */ +#define CRM_AHBRST3_QSPI1RST CRM_AHBRST3_QSPI1RST_Msk /*!< QSPI1 reset */ + +/***************** Bit definition for CRM_APB1RST register ******************/ +#define CRM_APB1RST_TMR2RST_Pos (0U) +#define CRM_APB1RST_TMR2RST_Msk (0x1U << CRM_APB1RST_TMR2RST_Pos) /*!< 0x00000001 */ +#define CRM_APB1RST_TMR2RST CRM_APB1RST_TMR2RST_Msk /*!< TMR2 reset */ +#define CRM_APB1RST_TMR3RST_Pos (1U) +#define CRM_APB1RST_TMR3RST_Msk (0x1U << CRM_APB1RST_TMR3RST_Pos) /*!< 0x00000002 */ +#define CRM_APB1RST_TMR3RST CRM_APB1RST_TMR3RST_Msk /*!< TMR3 reset */ +#define CRM_APB1RST_TMR4RST_Pos (2U) +#define CRM_APB1RST_TMR4RST_Msk (0x1U << CRM_APB1RST_TMR4RST_Pos) /*!< 0x00000004 */ +#define CRM_APB1RST_TMR4RST CRM_APB1RST_TMR4RST_Msk /*!< TMR4 reset */ +#define CRM_APB1RST_TMR6RST_Pos (4U) +#define CRM_APB1RST_TMR6RST_Msk (0x1U << CRM_APB1RST_TMR6RST_Pos) /*!< 0x00000010 */ +#define CRM_APB1RST_TMR6RST CRM_APB1RST_TMR6RST_Msk /*!< TMR6 reset */ +#define CRM_APB1RST_TMR7RST_Pos (5U) +#define CRM_APB1RST_TMR7RST_Msk (0x1U << CRM_APB1RST_TMR7RST_Pos) /*!< 0x00000020 */ +#define CRM_APB1RST_TMR7RST CRM_APB1RST_TMR7RST_Msk /*!< TMR7 reset */ +#define CRM_APB1RST_TMR13RST_Pos (7U) +#define CRM_APB1RST_TMR13RST_Msk (0x1U << CRM_APB1RST_TMR13RST_Pos) /*!< 0x00000080 */ +#define CRM_APB1RST_TMR13RST CRM_APB1RST_TMR13RST_Msk /*!< TMR13 reset */ +#define CRM_APB1RST_TMR14RST_Pos (8U) +#define CRM_APB1RST_TMR14RST_Msk (0x1U << CRM_APB1RST_TMR14RST_Pos) /*!< 0x00000100 */ +#define CRM_APB1RST_TMR14RST CRM_APB1RST_TMR14RST_Msk /*!< TMR14 reset */ +#define CRM_APB1RST_WWDTRST_Pos (11U) +#define CRM_APB1RST_WWDTRST_Msk (0x1U << CRM_APB1RST_WWDTRST_Pos) /*!< 0x00000800 */ +#define CRM_APB1RST_WWDTRST CRM_APB1RST_WWDTRST_Msk /*!< WWDT reset */ +#define CRM_APB1RST_SPI2RST_Pos (14U) +#define CRM_APB1RST_SPI2RST_Msk (0x1U << CRM_APB1RST_SPI2RST_Pos) /*!< 0x00004000 */ +#define CRM_APB1RST_SPI2RST CRM_APB1RST_SPI2RST_Msk /*!< SPI2 reset */ +#define CRM_APB1RST_SPI3RST_Pos (15U) +#define CRM_APB1RST_SPI3RST_Msk (0x1U << CRM_APB1RST_SPI3RST_Pos) /*!< 0x00008000 */ +#define CRM_APB1RST_SPI3RST CRM_APB1RST_SPI3RST_Msk /*!< SPI3 reset */ +#define CRM_APB1RST_USART2RST_Pos (17U) +#define CRM_APB1RST_USART2RST_Msk (0x1U << CRM_APB1RST_USART2RST_Pos) /*!< 0x00020000 */ +#define CRM_APB1RST_USART2RST CRM_APB1RST_USART2RST_Msk /*!< USART2 reset */ +#define CRM_APB1RST_USART3RST_Pos (18U) +#define CRM_APB1RST_USART3RST_Msk (0x1U << CRM_APB1RST_USART3RST_Pos) /*!< 0x00040000 */ +#define CRM_APB1RST_USART3RST CRM_APB1RST_USART3RST_Msk /*!< USART3 reset */ +#define CRM_APB1RST_USART4RST_Pos (19U) +#define CRM_APB1RST_USART4RST_Msk (0x1U << CRM_APB1RST_USART4RST_Pos) /*!< 0x00080000 */ +#define CRM_APB1RST_USART4RST CRM_APB1RST_USART4RST_Msk /*!< USART4 reset */ +#define CRM_APB1RST_USART5RST_Pos (20U) +#define CRM_APB1RST_USART5RST_Msk (0x1U << CRM_APB1RST_USART5RST_Pos) /*!< 0x00100000 */ +#define CRM_APB1RST_USART5RST CRM_APB1RST_USART5RST_Msk /*!< USART5 reset */ +#define CRM_APB1RST_I2C1RST_Pos (21U) +#define CRM_APB1RST_I2C1RST_Msk (0x1U << CRM_APB1RST_I2C1RST_Pos) /*!< 0x00200000 */ +#define CRM_APB1RST_I2C1RST CRM_APB1RST_I2C1RST_Msk /*!< I2C1 reset */ +#define CRM_APB1RST_I2C2RST_Pos (22U) +#define CRM_APB1RST_I2C2RST_Msk (0x1U << CRM_APB1RST_I2C2RST_Pos) /*!< 0x00400000 */ +#define CRM_APB1RST_I2C2RST CRM_APB1RST_I2C2RST_Msk /*!< I2C2 reset */ +#define CRM_APB1RST_I2C3RST_Pos (23U) +#define CRM_APB1RST_I2C3RST_Msk (0x1U << CRM_APB1RST_I2C3RST_Pos) /*!< 0x00800000 */ +#define CRM_APB1RST_I2C3RST CRM_APB1RST_I2C3RST_Msk /*!< I2C3 reset */ +#define CRM_APB1RST_CAN1RST_Pos (25U) +#define CRM_APB1RST_CAN1RST_Msk (0x1U << CRM_APB1RST_CAN1RST_Pos) /*!< 0x02000000 */ +#define CRM_APB1RST_CAN1RST CRM_APB1RST_CAN1RST_Msk /*!< CAN1 reset */ +#define CRM_APB1RST_PWCRST_Pos (28U) +#define CRM_APB1RST_PWCRST_Msk (0x1U << CRM_APB1RST_PWCRST_Pos) /*!< 0x10000000 */ +#define CRM_APB1RST_PWCRST CRM_APB1RST_PWCRST_Msk /*!< PWC reset */ +#define CRM_APB1RST_UART7RST_Pos (30U) +#define CRM_APB1RST_UART7RST_Msk (0x1U << CRM_APB1RST_UART7RST_Pos) /*!< 0x40000000 */ +#define CRM_APB1RST_UART7RST CRM_APB1RST_UART7RST_Msk /*!< UART7 reset */ +#define CRM_APB1RST_UART8RST_Pos (31U) +#define CRM_APB1RST_UART8RST_Msk (0x1U << CRM_APB1RST_UART8RST_Pos) /*!< 0x80000000 */ +#define CRM_APB1RST_UART8RST CRM_APB1RST_UART8RST_Msk /*!< UART8 reset */ + +/***************** Bit definition for CRM_APB2RST register ******************/ +#define CRM_APB2RST_TMR1RST_Pos (0U) +#define CRM_APB2RST_TMR1RST_Msk (0x1U << CRM_APB2RST_TMR1RST_Pos) /*!< 0x00000001 */ +#define CRM_APB2RST_TMR1RST CRM_APB2RST_TMR1RST_Msk /*!< TMR1 reset */ +#define CRM_APB2RST_USART1RST_Pos (4U) +#define CRM_APB2RST_USART1RST_Msk (0x1U << CRM_APB2RST_USART1RST_Pos) /*!< 0x00000010 */ +#define CRM_APB2RST_USART1RST CRM_APB2RST_USART1RST_Msk /*!< USART1 reset */ +#define CRM_APB2RST_USART6RST_Pos (5U) +#define CRM_APB2RST_USART6RST_Msk (0x1U << CRM_APB2RST_USART6RST_Pos) /*!< 0x00000020 */ +#define CRM_APB2RST_USART6RST CRM_APB2RST_USART6RST_Msk /*!< USART6 reset */ +#define CRM_APB2RST_ADCRST_Pos (8U) +#define CRM_APB2RST_ADCRST_Msk (0x1U << CRM_APB2RST_ADCRST_Pos) /*!< 0x00000100 */ +#define CRM_APB2RST_ADCRST CRM_APB2RST_ADCRST_Msk /*!< ADC reset */ +#define CRM_APB2RST_SPI1RST_Pos (12U) +#define CRM_APB2RST_SPI1RST_Msk (0x1U << CRM_APB2RST_SPI1RST_Pos) /*!< 0x00001000 */ +#define CRM_APB2RST_SPI1RST CRM_APB2RST_SPI1RST_Msk /*!< SPI1 reset */ +#define CRM_APB2RST_SCFGRST_Pos (14U) +#define CRM_APB2RST_SCFGRST_Msk (0x1U << CRM_APB2RST_SCFGRST_Pos) /*!< 0x00004000 */ +#define CRM_APB2RST_SCFGRST CRM_APB2RST_SCFGRST_Msk /*!< SCFG reset */ +#define CRM_APB2RST_EXINTRST_Pos (15U) +#define CRM_APB2RST_EXINTRST_Msk (0x1U << CRM_APB2RST_EXINTRST_Pos) /*!< 0x00008000 */ +#define CRM_APB2RST_EXINTRST CRM_APB2RST_EXINTRST_Msk /*!< EXINT reset */ +#define CRM_APB2RST_TMR9RST_Pos (16U) +#define CRM_APB2RST_TMR9RST_Msk (0x1U << CRM_APB2RST_TMR9RST_Pos) /*!< 0x00010000 */ +#define CRM_APB2RST_TMR9RST CRM_APB2RST_TMR9RST_Msk /*!< TMR9 reset */ +#define CRM_APB2RST_TMR10RST_Pos (17U) +#define CRM_APB2RST_TMR10RST_Msk (0x1U << CRM_APB2RST_TMR10RST_Pos) /*!< 0x00020000 */ +#define CRM_APB2RST_TMR10RST CRM_APB2RST_TMR10RST_Msk /*!< TMR10 reset */ +#define CRM_APB2RST_TMR11RST_Pos (18U) +#define CRM_APB2RST_TMR11RST_Msk (0x1U << CRM_APB2RST_TMR11RST_Pos) /*!< 0x00040000 */ +#define CRM_APB2RST_TMR11RST CRM_APB2RST_TMR11RST_Msk /*!< TMR11 reset */ +#define CRM_APB2RST_I2SF5RST_Pos (20U) +#define CRM_APB2RST_I2SF5RST_Msk (0x1U << CRM_APB2RST_I2SF5RST_Pos) /*!< 0x00100000 */ +#define CRM_APB2RST_I2SF5RST CRM_APB2RST_I2SF5RST_Msk /*!< I2SF5 reset */ +#define CRM_APB2RST_ACCRST_Pos (29U) +#define CRM_APB2RST_ACCRST_Msk (0x1U << CRM_APB2RST_ACCRST_Pos) /*!< 0x20000000 */ +#define CRM_APB2RST_ACCRST CRM_APB2RST_ACCRST_Msk /*!< ACC reset */ + +/****************** Bit definition for CRM_AHBEN1 register ******************/ +#define CRM_AHBEN1_GPIOAEN_Pos (0U) +#define CRM_AHBEN1_GPIOAEN_Msk (0x1U << CRM_AHBEN1_GPIOAEN_Pos) /*!< 0x00000001 */ +#define CRM_AHBEN1_GPIOAEN CRM_AHBEN1_GPIOAEN_Msk /*!< IO port A clock enable */ +#define CRM_AHBEN1_GPIOBEN_Pos (1U) +#define CRM_AHBEN1_GPIOBEN_Msk (0x1U << CRM_AHBEN1_GPIOBEN_Pos) /*!< 0x00000002 */ +#define CRM_AHBEN1_GPIOBEN CRM_AHBEN1_GPIOBEN_Msk /*!< IO port B clock enable */ +#define CRM_AHBEN1_GPIOCEN_Pos (2U) +#define CRM_AHBEN1_GPIOCEN_Msk (0x1U << CRM_AHBEN1_GPIOCEN_Pos) /*!< 0x00000004 */ +#define CRM_AHBEN1_GPIOCEN CRM_AHBEN1_GPIOCEN_Msk /*!< IO port C clock enable */ +#define CRM_AHBEN1_GPIODEN_Pos (3U) +#define CRM_AHBEN1_GPIODEN_Msk (0x1U << CRM_AHBEN1_GPIODEN_Pos) /*!< 0x00000008 */ +#define CRM_AHBEN1_GPIODEN CRM_AHBEN1_GPIODEN_Msk /*!< IO port D clock enable */ +#define CRM_AHBEN1_GPIOFEN_Pos (5U) +#define CRM_AHBEN1_GPIOFEN_Msk (0x1U << CRM_AHBEN1_GPIOFEN_Pos) /*!< 0x00000020 */ +#define CRM_AHBEN1_GPIOFEN CRM_AHBEN1_GPIOFEN_Msk /*!< IO port F clock enable */ +#define CRM_AHBEN1_CRCEN_Pos (12U) +#define CRM_AHBEN1_CRCEN_Msk (0x1U << CRM_AHBEN1_CRCEN_Pos) /*!< 0x00001000 */ +#define CRM_AHBEN1_CRCEN CRM_AHBEN1_CRCEN_Msk /*!< CRC clock enable */ +#define CRM_AHBEN1_DMA1EN_Pos (22U) +#define CRM_AHBEN1_DMA1EN_Msk (0x1U << CRM_AHBEN1_DMA1EN_Pos) /*!< 0x00400000 */ +#define CRM_AHBEN1_DMA1EN CRM_AHBEN1_DMA1EN_Msk /*!< DMA1 clock enable */ +#define CRM_AHBEN1_DMA2EN_Pos (24U) +#define CRM_AHBEN1_DMA2EN_Msk (0x1U << CRM_AHBEN1_DMA2EN_Pos) /*!< 0x01000000 */ +#define CRM_AHBEN1_DMA2EN CRM_AHBEN1_DMA2EN_Msk /*!< DMA2 clock enable */ +#define CRM_AHBEN1_OTGHSEN_Pos (29U) +#define CRM_AHBEN1_OTGHSEN_Msk (0x1U << CRM_AHBEN1_OTGHSEN_Pos) /*!< 0x20000000 */ +#define CRM_AHBEN1_OTGHSEN CRM_AHBEN1_OTGHSEN_Msk /*!< OTGHS clock enable (F405 only) */ + +/****************** Bit definition for CRM_AHBEN2 register ******************/ +#define CRM_AHBEN2_OTGFSEN_Pos (7U) +#define CRM_AHBEN2_OTGFSEN_Msk (0x1U << CRM_AHBEN2_OTGFSEN_Pos) /*!< 0x00000080 */ +#define CRM_AHBEN2_OTGFSEN CRM_AHBEN2_OTGFSEN_Msk /*!< OTGFS clock enable */ + +/****************** Bit definition for CRM_AHBEN3 register ******************/ +#define CRM_AHBEN3_QSPI1EN_Pos (1U) +#define CRM_AHBEN3_QSPI1EN_Msk (0x1U << CRM_AHBEN3_QSPI1EN_Pos) /*!< 0x00000002 */ +#define CRM_AHBEN3_QSPI1EN CRM_AHBEN3_QSPI1EN_Msk /*!< QSPI1 clock enable */ + +/****************** Bit definition for CRM_APB1EN register ******************/ +#define CRM_APB1EN_TMR2EN_Pos (0U) +#define CRM_APB1EN_TMR2EN_Msk (0x1U << CRM_APB1EN_TMR2EN_Pos) /*!< 0x00000001 */ +#define CRM_APB1EN_TMR2EN CRM_APB1EN_TMR2EN_Msk /*!< TMR2 clock enable */ +#define CRM_APB1EN_TMR3EN_Pos (1U) +#define CRM_APB1EN_TMR3EN_Msk (0x1U << CRM_APB1EN_TMR3EN_Pos) /*!< 0x00000002 */ +#define CRM_APB1EN_TMR3EN CRM_APB1EN_TMR3EN_Msk /*!< TMR3 clock enable */ +#define CRM_APB1EN_TMR4EN_Pos (2U) +#define CRM_APB1EN_TMR4EN_Msk (0x1U << CRM_APB1EN_TMR4EN_Pos) /*!< 0x00000004 */ +#define CRM_APB1EN_TMR4EN CRM_APB1EN_TMR4EN_Msk /*!< TMR4 clock enable */ +#define CRM_APB1EN_TMR6EN_Pos (4U) +#define CRM_APB1EN_TMR6EN_Msk (0x1U << CRM_APB1EN_TMR6EN_Pos) /*!< 0x00000010 */ +#define CRM_APB1EN_TMR6EN CRM_APB1EN_TMR6EN_Msk /*!< TMR6 clock enable */ +#define CRM_APB1EN_TMR7EN_Pos (5U) +#define CRM_APB1EN_TMR7EN_Msk (0x1U << CRM_APB1EN_TMR7EN_Pos) /*!< 0x00000020 */ +#define CRM_APB1EN_TMR7EN CRM_APB1EN_TMR7EN_Msk /*!< TMR7 clock enable */ +#define CRM_APB1EN_TMR13EN_Pos (7U) +#define CRM_APB1EN_TMR13EN_Msk (0x1U << CRM_APB1EN_TMR13EN_Pos) /*!< 0x00000080 */ +#define CRM_APB1EN_TMR13EN CRM_APB1EN_TMR13EN_Msk /*!< TMR13 clock enable */ +#define CRM_APB1EN_TMR14EN_Pos (8U) +#define CRM_APB1EN_TMR14EN_Msk (0x1U << CRM_APB1EN_TMR14EN_Pos) /*!< 0x00000100 */ +#define CRM_APB1EN_TMR14EN CRM_APB1EN_TMR14EN_Msk /*!< TMR14 clock enable */ +#define CRM_APB1EN_WWDTEN_Pos (11U) +#define CRM_APB1EN_WWDTEN_Msk (0x1U << CRM_APB1EN_WWDTEN_Pos) /*!< 0x00000800 */ +#define CRM_APB1EN_WWDTEN CRM_APB1EN_WWDTEN_Msk /*!< WWDT clock enable */ +#define CRM_APB1EN_SPI2EN_Pos (14U) +#define CRM_APB1EN_SPI2EN_Msk (0x1U << CRM_APB1EN_SPI2EN_Pos) /*!< 0x00004000 */ +#define CRM_APB1EN_SPI2EN CRM_APB1EN_SPI2EN_Msk /*!< SPI2 clock enable */ +#define CRM_APB1EN_SPI3EN_Pos (15U) +#define CRM_APB1EN_SPI3EN_Msk (0x1U << CRM_APB1EN_SPI3EN_Pos) /*!< 0x00008000 */ +#define CRM_APB1EN_SPI3EN CRM_APB1EN_SPI3EN_Msk /*!< SPI3 clock enable */ +#define CRM_APB1EN_USART2EN_Pos (17U) +#define CRM_APB1EN_USART2EN_Msk (0x1U << CRM_APB1EN_USART2EN_Pos) /*!< 0x00020000 */ +#define CRM_APB1EN_USART2EN CRM_APB1EN_USART2EN_Msk /*!< USART2 clock enable */ +#define CRM_APB1EN_USART3EN_Pos (18U) +#define CRM_APB1EN_USART3EN_Msk (0x1U << CRM_APB1EN_USART3EN_Pos) /*!< 0x00040000 */ +#define CRM_APB1EN_USART3EN CRM_APB1EN_USART3EN_Msk /*!< USART3 clock enable */ +#define CRM_APB1EN_USART4EN_Pos (19U) +#define CRM_APB1EN_USART4EN_Msk (0x1U << CRM_APB1EN_USART4EN_Pos) /*!< 0x00080000 */ +#define CRM_APB1EN_USART4EN CRM_APB1EN_USART4EN_Msk /*!< USART4 clock enable */ +#define CRM_APB1EN_USART5EN_Pos (20U) +#define CRM_APB1EN_USART5EN_Msk (0x1U << CRM_APB1EN_USART5EN_Pos) /*!< 0x00100000 */ +#define CRM_APB1EN_USART5EN CRM_APB1EN_USART5EN_Msk /*!< USART5 clock enable */ +#define CRM_APB1EN_I2C1EN_Pos (21U) +#define CRM_APB1EN_I2C1EN_Msk (0x1U << CRM_APB1EN_I2C1EN_Pos) /*!< 0x00200000 */ +#define CRM_APB1EN_I2C1EN CRM_APB1EN_I2C1EN_Msk /*!< I2C1 clock enable */ +#define CRM_APB1EN_I2C2EN_Pos (22U) +#define CRM_APB1EN_I2C2EN_Msk (0x1U << CRM_APB1EN_I2C2EN_Pos) /*!< 0x00400000 */ +#define CRM_APB1EN_I2C2EN CRM_APB1EN_I2C2EN_Msk /*!< I2C2 clock enable */ +#define CRM_APB1EN_I2C3EN_Pos (23U) +#define CRM_APB1EN_I2C3EN_Msk (0x1U << CRM_APB1EN_I2C3EN_Pos) /*!< 0x00800000 */ +#define CRM_APB1EN_I2C3EN CRM_APB1EN_I2C3EN_Msk /*!< I2C3 clock enable */ +#define CRM_APB1EN_CAN1EN_Pos (25U) +#define CRM_APB1EN_CAN1EN_Msk (0x1U << CRM_APB1EN_CAN1EN_Pos) /*!< 0x02000000 */ +#define CRM_APB1EN_CAN1EN CRM_APB1EN_CAN1EN_Msk /*!< CAN1 clock enable */ +#define CRM_APB1EN_PWCEN_Pos (28U) +#define CRM_APB1EN_PWCEN_Msk (0x1U << CRM_APB1EN_PWCEN_Pos) /*!< 0x10000000 */ +#define CRM_APB1EN_PWCEN CRM_APB1EN_PWCEN_Msk /*!< Power control clock enable */ +#define CRM_APB1EN_UART7EN_Pos (30U) +#define CRM_APB1EN_UART7EN_Msk (0x1U << CRM_APB1EN_UART7EN_Pos) /*!< 0x40000000 */ +#define CRM_APB1EN_UART7EN CRM_APB1EN_UART7EN_Msk /*!< UART7 clock enable */ +#define CRM_APB1EN_UART8EN_Pos (31U) +#define CRM_APB1EN_UART8EN_Msk (0x1U << CRM_APB1EN_UART8EN_Pos) /*!< 0x80000000 */ +#define CRM_APB1EN_UART8EN CRM_APB1EN_UART8EN_Msk /*!< UART8 clock enable */ + +/****************** Bit definition for CRM_APB2EN register ******************/ +#define CRM_APB2EN_TMR1EN_Pos (0U) +#define CRM_APB2EN_TMR1EN_Msk (0x1U << CRM_APB2EN_TMR1EN_Pos) /*!< 0x00000001 */ +#define CRM_APB2EN_TMR1EN CRM_APB2EN_TMR1EN_Msk /*!< TMR1 clock enable */ +#define CRM_APB2EN_USART1EN_Pos (4U) +#define CRM_APB2EN_USART1EN_Msk (0x1U << CRM_APB2EN_USART1EN_Pos) /*!< 0x00000010 */ +#define CRM_APB2EN_USART1EN CRM_APB2EN_USART1EN_Msk /*!< USART1 clock enable */ +#define CRM_APB2EN_USART6EN_Pos (5U) +#define CRM_APB2EN_USART6EN_Msk (0x1U << CRM_APB2EN_USART6EN_Pos) /*!< 0x00000020 */ +#define CRM_APB2EN_USART6EN CRM_APB2EN_USART6EN_Msk /*!< USART6 clock enable */ +#define CRM_APB2EN_ADC1EN_Pos (8U) +#define CRM_APB2EN_ADC1EN_Msk (0x1U << CRM_APB2EN_ADC1EN_Pos) /*!< 0x00000100 */ +#define CRM_APB2EN_ADC1EN CRM_APB2EN_ADC1EN_Msk /*!< ADC1 clock enable */ +#define CRM_APB2EN_SPI1EN_Pos (12U) +#define CRM_APB2EN_SPI1EN_Msk (0x1U << CRM_APB2EN_SPI1EN_Pos) /*!< 0x00001000 */ +#define CRM_APB2EN_SPI1EN CRM_APB2EN_SPI1EN_Msk /*!< SPI1 clock enable */ +#define CRM_APB2EN_SCFGEN_Pos (14U) +#define CRM_APB2EN_SCFGEN_Msk (0x1U << CRM_APB2EN_SCFGEN_Pos) /*!< 0x00004000 */ +#define CRM_APB2EN_SCFGEN CRM_APB2EN_SCFGEN_Msk /*!< SCFG clock enable */ +#define CRM_APB2EN_TMR9EN_Pos (16U) +#define CRM_APB2EN_TMR9EN_Msk (0x1U << CRM_APB2EN_TMR9EN_Pos) /*!< 0x00010000 */ +#define CRM_APB2EN_TMR9EN CRM_APB2EN_TMR9EN_Msk /*!< TMR9 clock enable */ +#define CRM_APB2EN_TMR10EN_Pos (17U) +#define CRM_APB2EN_TMR10EN_Msk (0x1U << CRM_APB2EN_TMR10EN_Pos) /*!< 0x00020000 */ +#define CRM_APB2EN_TMR10EN CRM_APB2EN_TMR10EN_Msk /*!< TMR10 clock enable */ +#define CRM_APB2EN_TMR11EN_Pos (18U) +#define CRM_APB2EN_TMR11EN_Msk (0x1U << CRM_APB2EN_TMR11EN_Pos) /*!< 0x00040000 */ +#define CRM_APB2EN_TMR11EN CRM_APB2EN_TMR11EN_Msk /*!< TMR11 clock enable */ +#define CRM_APB2EN_I2SF5EN_Pos (20U) +#define CRM_APB2EN_I2SF5EN_Msk (0x1U << CRM_APB2EN_I2SF5EN_Pos) /*!< 0x00100000 */ +#define CRM_APB2EN_I2SF5EN CRM_APB2EN_I2SF5EN_Msk /*!< I2SF5 clock enable */ +#define CRM_APB2EN_ACCEN_Pos (29U) +#define CRM_APB2EN_ACCEN_Msk (0x1U << CRM_APB2EN_ACCEN_Pos) /*!< 0x20000000 */ +#define CRM_APB2EN_ACCEN CRM_APB2EN_ACCEN_Msk /*!< ACC clock enable */ + +/***************** Bit definition for CRM_AHBLPEN1 register *****************/ +#define CRM_AHBLPEN1_GPIOALPEN_Pos (0U) +#define CRM_AHBLPEN1_GPIOALPEN_Msk (0x1U << CRM_AHBLPEN1_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define CRM_AHBLPEN1_GPIOALPEN CRM_AHBLPEN1_GPIOALPEN_Msk /*!< IO port A clock enable in sleep mode */ +#define CRM_AHBLPEN1_GPIOBLPEN_Pos (1U) +#define CRM_AHBLPEN1_GPIOBLPEN_Msk (0x1U << CRM_AHBLPEN1_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define CRM_AHBLPEN1_GPIOBLPEN CRM_AHBLPEN1_GPIOBLPEN_Msk /*!< IO port B clock enable in sleep mode */ +#define CRM_AHBLPEN1_GPIOCLPEN_Pos (2U) +#define CRM_AHBLPEN1_GPIOCLPEN_Msk (0x1U << CRM_AHBLPEN1_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define CRM_AHBLPEN1_GPIOCLPEN CRM_AHBLPEN1_GPIOCLPEN_Msk /*!< IO port C clock enable in sleep mode */ +#define CRM_AHBLPEN1_GPIODLPEN_Pos (3U) +#define CRM_AHBLPEN1_GPIODLPEN_Msk (0x1U << CRM_AHBLPEN1_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define CRM_AHBLPEN1_GPIODLPEN CRM_AHBLPEN1_GPIODLPEN_Msk /*!< IO port D clock enable in sleep mode */ +#define CRM_AHBLPEN1_GPIOFLPEN_Pos (5U) +#define CRM_AHBLPEN1_GPIOFLPEN_Msk (0x1U << CRM_AHBLPEN1_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define CRM_AHBLPEN1_GPIOFLPEN CRM_AHBLPEN1_GPIOFLPEN_Msk /*!< IO port F clock enable in sleep mode */ +#define CRM_AHBLPEN1_CRCLPEN_Pos (12U) +#define CRM_AHBLPEN1_CRCLPEN_Msk (0x1U << CRM_AHBLPEN1_CRCLPEN_Pos) /*!< 0x00001000 */ +#define CRM_AHBLPEN1_CRCLPEN CRM_AHBLPEN1_CRCLPEN_Msk /*!< CRC clock enable in sleep mode */ +#define CRM_AHBLPEN1_FLASHLPEN_Pos (15U) +#define CRM_AHBLPEN1_FLASHLPEN_Msk (0x1U << CRM_AHBLPEN1_FLASHLPEN_Pos) /*!< 0x00008000 */ +#define CRM_AHBLPEN1_FLASHLPEN CRM_AHBLPEN1_FLASHLPEN_Msk /*!< FLASH clock enable in sleep mode */ +#define CRM_AHBLPEN1_SRAMLPEN_Pos (16U) +#define CRM_AHBLPEN1_SRAMLPEN_Msk (0x1U << CRM_AHBLPEN1_SRAMLPEN_Pos) /*!< 0x00010000 */ +#define CRM_AHBLPEN1_SRAMLPEN CRM_AHBLPEN1_SRAMLPEN_Msk /*!< SRAM clock enable in sleep mode */ +#define CRM_AHBLPEN1_DMA1LPEN_Pos (22U) +#define CRM_AHBLPEN1_DMA1LPEN_Msk (0x1U << CRM_AHBLPEN1_DMA1LPEN_Pos) /*!< 0x00400000 */ +#define CRM_AHBLPEN1_DMA1LPEN CRM_AHBLPEN1_DMA1LPEN_Msk /*!< DMA1 clock enable in sleep mode */ +#define CRM_AHBLPEN1_DMA2LPEN_Pos (24U) +#define CRM_AHBLPEN1_DMA2LPEN_Msk (0x1U << CRM_AHBLPEN1_DMA2LPEN_Pos) /*!< 0x01000000 */ +#define CRM_AHBLPEN1_DMA2LPEN CRM_AHBLPEN1_DMA2LPEN_Msk /*!< DMA2 clock enable in sleep mode */ +#define CRM_AHBLPEN1_OTGHSLPEN_Pos (29U) +#define CRM_AHBLPEN1_OTGHSLPEN_Msk (0x1U << CRM_AHBLPEN1_OTGHSLPEN_Pos) /*!< 0x20000000 */ +#define CRM_AHBLPEN1_OTGHSLPEN CRM_AHBLPEN1_OTGHSLPEN_Msk /*!< OTGHS clock enable in sleep mode (F405 only) */ + +/***************** Bit definition for CRM_AHBLPEN2 register *****************/ +#define CRM_AHBLPEN2_OTGFSLPEN_Pos (7U) +#define CRM_AHBLPEN2_OTGFSLPEN_Msk (0x1U << CRM_AHBLPEN2_OTGFSLPEN_Pos) /*!< 0x00000080 */ +#define CRM_AHBLPEN2_OTGFSLPEN CRM_AHBLPEN2_OTGFSLPEN_Msk /*!< OTGFS clock enable in sleep mode */ + +/***************** Bit definition for CRM_AHBLPEN3 register *****************/ +#define CRM_AHBLPEN3_QSPI1LPEN_Pos (1U) +#define CRM_AHBLPEN3_QSPI1LPEN_Msk (0x1U << CRM_AHBLPEN3_QSPI1LPEN_Pos) /*!< 0x00000002 */ +#define CRM_AHBLPEN3_QSPI1LPEN CRM_AHBLPEN3_QSPI1LPEN_Msk /*!< QSPI1 clock enable in sleep mode */ + +/***************** Bit definition for CRM_APB1LPEN register *****************/ +#define CRM_APB1LPEN_TMR2LPEN_Pos (0U) +#define CRM_APB1LPEN_TMR2LPEN_Msk (0x1U << CRM_APB1LPEN_TMR2LPEN_Pos) /*!< 0x00000001 */ +#define CRM_APB1LPEN_TMR2LPEN CRM_APB1LPEN_TMR2LPEN_Msk /*!< TMR2 clock enable in sleep mode */ +#define CRM_APB1LPEN_TMR3LPEN_Pos (1U) +#define CRM_APB1LPEN_TMR3LPEN_Msk (0x1U << CRM_APB1LPEN_TMR3LPEN_Pos) /*!< 0x00000002 */ +#define CRM_APB1LPEN_TMR3LPEN CRM_APB1LPEN_TMR3LPEN_Msk /*!< TMR3 clock enable in sleep mode */ +#define CRM_APB1LPEN_TMR4LPEN_Pos (2U) +#define CRM_APB1LPEN_TMR4LPEN_Msk (0x1U << CRM_APB1LPEN_TMR4LPEN_Pos) /*!< 0x00000004 */ +#define CRM_APB1LPEN_TMR4LPEN CRM_APB1LPEN_TMR4LPEN_Msk /*!< TMR4 clock enable in sleep mode */ +#define CRM_APB1LPEN_TMR6LPEN_Pos (4U) +#define CRM_APB1LPEN_TMR6LPEN_Msk (0x1U << CRM_APB1LPEN_TMR6LPEN_Pos) /*!< 0x00000010 */ +#define CRM_APB1LPEN_TMR6LPEN CRM_APB1LPEN_TMR6LPEN_Msk /*!< TMR6 clock enable in sleep mode */ +#define CRM_APB1LPEN_TMR7LPEN_Pos (5U) +#define CRM_APB1LPEN_TMR7LPEN_Msk (0x1U << CRM_APB1LPEN_TMR7LPEN_Pos) /*!< 0x00000020 */ +#define CRM_APB1LPEN_TMR7LPEN CRM_APB1LPEN_TMR7LPEN_Msk /*!< TMR7 clock enable in sleep mode */ +#define CRM_APB1LPEN_TMR13LPEN_Pos (7U) +#define CRM_APB1LPEN_TMR13LPEN_Msk (0x1U << CRM_APB1LPEN_TMR13LPEN_Pos) /*!< 0x00000080 */ +#define CRM_APB1LPEN_TMR13LPEN CRM_APB1LPEN_TMR13LPEN_Msk /*!< TMR13 clock enable in sleep mode */ +#define CRM_APB1LPEN_TMR14LPEN_Pos (8U) +#define CRM_APB1LPEN_TMR14LPEN_Msk (0x1U << CRM_APB1LPEN_TMR14LPEN_Pos) /*!< 0x00000100 */ +#define CRM_APB1LPEN_TMR14LPEN CRM_APB1LPEN_TMR14LPEN_Msk /*!< TMR14 clock enable in sleep mode */ +#define CRM_APB1LPEN_WWDTLPEN_Pos (11U) +#define CRM_APB1LPEN_WWDTLPEN_Msk (0x1U << CRM_APB1LPEN_WWDTLPEN_Pos) /*!< 0x00000800 */ +#define CRM_APB1LPEN_WWDTLPEN CRM_APB1LPEN_WWDTLPEN_Msk /*!< WWDT clock enable in sleep mode */ +#define CRM_APB1LPEN_SPI2LPEN_Pos (14U) +#define CRM_APB1LPEN_SPI2LPEN_Msk (0x1U << CRM_APB1LPEN_SPI2LPEN_Pos) /*!< 0x00004000 */ +#define CRM_APB1LPEN_SPI2LPEN CRM_APB1LPEN_SPI2LPEN_Msk /*!< SPI2 clock enable in sleep mode */ +#define CRM_APB1LPEN_SPI3LPEN_Pos (15U) +#define CRM_APB1LPEN_SPI3LPEN_Msk (0x1U << CRM_APB1LPEN_SPI3LPEN_Pos) /*!< 0x00008000 */ +#define CRM_APB1LPEN_SPI3LPEN CRM_APB1LPEN_SPI3LPEN_Msk /*!< SPI3 clock enable in sleep mode */ +#define CRM_APB1LPEN_USART2LPEN_Pos (17U) +#define CRM_APB1LPEN_USART2LPEN_Msk (0x1U << CRM_APB1LPEN_USART2LPEN_Pos) /*!< 0x00020000 */ +#define CRM_APB1LPEN_USART2LPEN CRM_APB1LPEN_USART2LPEN_Msk /*!< USART2 clock enable in sleep mode */ +#define CRM_APB1LPEN_USART3LPEN_Pos (18U) +#define CRM_APB1LPEN_USART3LPEN_Msk (0x1U << CRM_APB1LPEN_USART3LPEN_Pos) /*!< 0x00040000 */ +#define CRM_APB1LPEN_USART3LPEN CRM_APB1LPEN_USART3LPEN_Msk /*!< USART3 clock enable in sleep mode */ +#define CRM_APB1LPEN_USART4LPEN_Pos (19U) +#define CRM_APB1LPEN_USART4LPEN_Msk (0x1U << CRM_APB1LPEN_USART4LPEN_Pos) /*!< 0x00080000 */ +#define CRM_APB1LPEN_USART4LPEN CRM_APB1LPEN_USART4LPEN_Msk /*!< USART4 clock enable in sleep mode */ +#define CRM_APB1LPEN_USART5LPEN_Pos (20U) +#define CRM_APB1LPEN_USART5LPEN_Msk (0x1U << CRM_APB1LPEN_USART5LPEN_Pos) /*!< 0x00100000 */ +#define CRM_APB1LPEN_USART5LPEN CRM_APB1LPEN_USART5LPEN_Msk /*!< USART5 clock enable in sleep mode */ +#define CRM_APB1LPEN_I2C1LPEN_Pos (21U) +#define CRM_APB1LPEN_I2C1LPEN_Msk (0x1U << CRM_APB1LPEN_I2C1LPEN_Pos) /*!< 0x00200000 */ +#define CRM_APB1LPEN_I2C1LPEN CRM_APB1LPEN_I2C1LPEN_Msk /*!< I2C1 clock enable in sleep mode */ +#define CRM_APB1LPEN_I2C2LPEN_Pos (22U) +#define CRM_APB1LPEN_I2C2LPEN_Msk (0x1U << CRM_APB1LPEN_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define CRM_APB1LPEN_I2C2LPEN CRM_APB1LPEN_I2C2LPEN_Msk /*!< I2C2 clock enable in sleep mode */ +#define CRM_APB1LPEN_I2C3LPEN_Pos (23U) +#define CRM_APB1LPEN_I2C3LPEN_Msk (0x1U << CRM_APB1LPEN_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define CRM_APB1LPEN_I2C3LPEN CRM_APB1LPEN_I2C3LPEN_Msk /*!< I2C3 clock enable in sleep mode */ +#define CRM_APB1LPEN_CAN1LPEN_Pos (25U) +#define CRM_APB1LPEN_CAN1LPEN_Msk (0x1U << CRM_APB1LPEN_CAN1LPEN_Pos) /*!< 0x02000000 */ +#define CRM_APB1LPEN_CAN1LPEN CRM_APB1LPEN_CAN1LPEN_Msk /*!< CAN1 clock enable in sleep mode */ +#define CRM_APB1LPEN_PWCLPEN_Pos (28U) +#define CRM_APB1LPEN_PWCLPEN_Msk (0x1U << CRM_APB1LPEN_PWCLPEN_Pos) /*!< 0x10000000 */ +#define CRM_APB1LPEN_PWCLPEN CRM_APB1LPEN_PWCLPEN_Msk /*!< Power control clock enable in sleep mode */ +#define CRM_APB1LPEN_UART7LPEN_Pos (30U) +#define CRM_APB1LPEN_UART7LPEN_Msk (0x1U << CRM_APB1LPEN_UART7LPEN_Pos) /*!< 0x40000000 */ +#define CRM_APB1LPEN_UART7LPEN CRM_APB1LPEN_UART7LPEN_Msk /*!< UART7 clock enable in sleep mode */ +#define CRM_APB1LPEN_UART8LPEN_Pos (31U) +#define CRM_APB1LPEN_UART8LPEN_Msk (0x1U << CRM_APB1LPEN_UART8LPEN_Pos) /*!< 0x80000000 */ +#define CRM_APB1LPEN_UART8LPEN CRM_APB1LPEN_UART8LPEN_Msk /*!< UART8 clock enable in sleep mode */ + +/***************** Bit definition for CRM_APB2LPEN register *****************/ +#define CRM_APB2LPEN_TMR1LPEN_Pos (0U) +#define CRM_APB2LPEN_TMR1LPEN_Msk (0x1U << CRM_APB2LPEN_TMR1LPEN_Pos) /*!< 0x00000001 */ +#define CRM_APB2LPEN_TMR1LPEN CRM_APB2LPEN_TMR1LPEN_Msk /*!< TMR1 clock enable in sleep mode */ +#define CRM_APB2LPEN_USART1LPEN_Pos (4U) +#define CRM_APB2LPEN_USART1LPEN_Msk (0x1U << CRM_APB2LPEN_USART1LPEN_Pos) /*!< 0x00000010 */ +#define CRM_APB2LPEN_USART1LPEN CRM_APB2LPEN_USART1LPEN_Msk /*!< USART1 clock enable in sleep mode */ +#define CRM_APB2LPEN_USART6LPEN_Pos (5U) +#define CRM_APB2LPEN_USART6LPEN_Msk (0x1U << CRM_APB2LPEN_USART6LPEN_Pos) /*!< 0x00000020 */ +#define CRM_APB2LPEN_USART6LPEN CRM_APB2LPEN_USART6LPEN_Msk /*!< USART6 clock enable in sleep mode */ +#define CRM_APB2LPEN_ADC1LPEN_Pos (8U) +#define CRM_APB2LPEN_ADC1LPEN_Msk (0x1U << CRM_APB2LPEN_ADC1LPEN_Pos) /*!< 0x00000100 */ +#define CRM_APB2LPEN_ADC1LPEN CRM_APB2LPEN_ADC1LPEN_Msk /*!< ADC1 clock enable in sleep mode */ +#define CRM_APB2LPEN_SPI1LPEN_Pos (12U) +#define CRM_APB2LPEN_SPI1LPEN_Msk (0x1U << CRM_APB2LPEN_SPI1LPEN_Pos) /*!< 0x00001000 */ +#define CRM_APB2LPEN_SPI1LPEN CRM_APB2LPEN_SPI1LPEN_Msk /*!< SPI1 clock enable in sleep mode */ +#define CRM_APB2LPEN_SCFGLPEN_Pos (14U) +#define CRM_APB2LPEN_SCFGLPEN_Msk (0x1U << CRM_APB2LPEN_SCFGLPEN_Pos) /*!< 0x00004000 */ +#define CRM_APB2LPEN_SCFGLPEN CRM_APB2LPEN_SCFGLPEN_Msk /*!< SCFG clock enable in sleep mode */ +#define CRM_APB2LPEN_TMR9LPEN_Pos (16U) +#define CRM_APB2LPEN_TMR9LPEN_Msk (0x1U << CRM_APB2LPEN_TMR9LPEN_Pos) /*!< 0x00010000 */ +#define CRM_APB2LPEN_TMR9LPEN CRM_APB2LPEN_TMR9LPEN_Msk /*!< TMR9 clock enable in sleep mode */ +#define CRM_APB2LPEN_TMR10LPEN_Pos (17U) +#define CRM_APB2LPEN_TMR10LPEN_Msk (0x1U << CRM_APB2LPEN_TMR10LPEN_Pos) /*!< 0x00020000 */ +#define CRM_APB2LPEN_TMR10LPEN CRM_APB2LPEN_TMR10LPEN_Msk /*!< TMR10 clock enable in sleep mode */ +#define CRM_APB2LPEN_TMR11LPEN_Pos (18U) +#define CRM_APB2LPEN_TMR11LPEN_Msk (0x1U << CRM_APB2LPEN_TMR11LPEN_Pos) /*!< 0x00040000 */ +#define CRM_APB2LPEN_TMR11LPEN CRM_APB2LPEN_TMR11LPEN_Msk /*!< TMR11 clock enable in sleep mode */ +#define CRM_APB2LPEN_I2SF5LPEN_Pos (20U) +#define CRM_APB2LPEN_I2SF5LPEN_Msk (0x1U << CRM_APB2LPEN_I2SF5LPEN_Pos) /*!< 0x00100000 */ +#define CRM_APB2LPEN_I2SF5LPEN CRM_APB2LPEN_I2SF5LPEN_Msk /*!< I2SF5 clock enable in sleep mode */ +#define CRM_APB2LPEN_ACCLPEN_Pos (29U) +#define CRM_APB2LPEN_ACCLPEN_Msk (0x1U << CRM_APB2LPEN_ACCLPEN_Pos) /*!< 0x20000000 */ +#define CRM_APB2LPEN_ACCLPEN CRM_APB2LPEN_ACCLPEN_Msk /*!< ACC clock enable in sleep mode */ + +/******************* Bit definition for CRM_BPDC register *******************/ +#define CRM_BPDC_LEXTEN_Pos (0U) +#define CRM_BPDC_LEXTEN_Msk (0x1U << CRM_BPDC_LEXTEN_Pos) /*!< 0x00000001 */ +#define CRM_BPDC_LEXTEN CRM_BPDC_LEXTEN_Msk /*!< External low-speed oscillator enable */ +#define CRM_BPDC_LEXTSTBL_Pos (1U) +#define CRM_BPDC_LEXTSTBL_Msk (0x1U << CRM_BPDC_LEXTSTBL_Pos) /*!< 0x00000002 */ +#define CRM_BPDC_LEXTSTBL CRM_BPDC_LEXTSTBL_Msk /*!< External low-speed oscillator stable */ +#define CRM_BPDC_LEXTBYPS_Pos (2U) +#define CRM_BPDC_LEXTBYPS_Msk (0x1U << CRM_BPDC_LEXTBYPS_Pos) /*!< 0x00000004 */ +#define CRM_BPDC_LEXTBYPS CRM_BPDC_LEXTBYPS_Msk /*!< External low-speed crystal bypass */ + +/*!< ERTCSEL congiguration */ +#define CRM_BPDC_ERTCSEL_Pos (8U) +#define CRM_BPDC_ERTCSEL_Msk (0x3U << CRM_BPDC_ERTCSEL_Pos) /*!< 0x00000300 */ +#define CRM_BPDC_ERTCSEL CRM_BPDC_ERTCSEL_Msk /*!< ERTCSEL[1:0] bits (ERTC clock selection) */ +#define CRM_BPDC_ERTCSEL_0 (0x1U << CRM_BPDC_ERTCSEL_Pos) /*!< 0x00000100 */ +#define CRM_BPDC_ERTCSEL_1 (0x2U << CRM_BPDC_ERTCSEL_Pos) /*!< 0x00000200 */ + +#define CRM_BPDC_ERTCSEL_NOCLOCK 0x00000000U /*!< No clock */ +#define CRM_BPDC_ERTCSEL_LEXT 0x00000100U /*!< LEXT */ +#define CRM_BPDC_ERTCSEL_LICK 0x00000200U /*!< LICK */ +#define CRM_BPDC_ERTCSEL_HEXT 0x00000300U /*!< Devided HEXT with ERTCDIV bit in CRM_CFG */ + +#define CRM_BPDC_ERTCEN_Pos (15U) +#define CRM_BPDC_ERTCEN_Msk (0x1U << CRM_BPDC_ERTCEN_Pos) /*!< 0x00008000 */ +#define CRM_BPDC_ERTCEN CRM_BPDC_ERTCEN_Msk /*!< ERTC clock enable */ +#define CRM_BPDC_BPDRST_Pos (16U) +#define CRM_BPDC_BPDRST_Msk (0x1U << CRM_BPDC_BPDRST_Pos) /*!< 0x00010000 */ +#define CRM_BPDC_BPDRST CRM_BPDC_BPDRST_Msk /*!< Battery powered domain software reset */ + +/***************** Bit definition for CRM_CTRLSTS register ******************/ +#define CRM_CTRLSTS_LICKEN_Pos (0U) +#define CRM_CTRLSTS_LICKEN_Msk (0x1U << CRM_CTRLSTS_LICKEN_Pos) /*!< 0x00000001 */ +#define CRM_CTRLSTS_LICKEN CRM_CTRLSTS_LICKEN_Msk /*!< LICK enable */ +#define CRM_CTRLSTS_LICKSTBL_Pos (1U) +#define CRM_CTRLSTS_LICKSTBL_Msk (0x1U << CRM_CTRLSTS_LICKSTBL_Pos) /*!< 0x00000002 */ +#define CRM_CTRLSTS_LICKSTBL CRM_CTRLSTS_LICKSTBL_Msk /*!< LICK stable */ +#define CRM_CTRLSTS_RSTFC_Pos (24U) +#define CRM_CTRLSTS_RSTFC_Msk (0x1U << CRM_CTRLSTS_RSTFC_Pos) /*!< 0x01000000 */ +#define CRM_CTRLSTS_RSTFC CRM_CTRLSTS_RSTFC_Msk /*!< Reset flag clear */ +#define CRM_CTRLSTS_NRSTF_Pos (26U) +#define CRM_CTRLSTS_NRSTF_Msk (0x1U << CRM_CTRLSTS_NRSTF_Pos) /*!< 0x04000000 */ +#define CRM_CTRLSTS_NRSTF CRM_CTRLSTS_NRSTF_Msk /*!< NRST pin reset flag */ +#define CRM_CTRLSTS_PORRSTF_Pos (27U) +#define CRM_CTRLSTS_PORRSTF_Msk (0x1U << CRM_CTRLSTS_PORRSTF_Pos) /*!< 0x08000000 */ +#define CRM_CTRLSTS_PORRSTF CRM_CTRLSTS_PORRSTF_Msk /*!< POR/LVR reset flag */ +#define CRM_CTRLSTS_SWRSTF_Pos (28U) +#define CRM_CTRLSTS_SWRSTF_Msk (0x1U << CRM_CTRLSTS_SWRSTF_Pos) /*!< 0x10000000 */ +#define CRM_CTRLSTS_SWRSTF CRM_CTRLSTS_SWRSTF_Msk /*!< Software reset flag */ +#define CRM_CTRLSTS_WDTRSTF_Pos (29U) +#define CRM_CTRLSTS_WDTRSTF_Msk (0x1U << CRM_CTRLSTS_WDTRSTF_Pos) /*!< 0x20000000 */ +#define CRM_CTRLSTS_WDTRSTF CRM_CTRLSTS_WDTRSTF_Msk /*!< Watchdog timer reset flag */ +#define CRM_CTRLSTS_WWDTRSTF_Pos (30U) +#define CRM_CTRLSTS_WWDTRSTF_Msk (0x1U << CRM_CTRLSTS_WWDTRSTF_Pos) /*!< 0x40000000 */ +#define CRM_CTRLSTS_WWDTRSTF CRM_CTRLSTS_WWDTRSTF_Msk /*!< Window watchdog timer reset flag */ +#define CRM_CTRLSTS_LPRSTF_Pos (31U) +#define CRM_CTRLSTS_LPRSTF_Msk (0x1U << CRM_CTRLSTS_LPRSTF_Pos) /*!< 0x80000000 */ +#define CRM_CTRLSTS_LPRSTF CRM_CTRLSTS_LPRSTF_Msk /*!< Low-power reset flag */ + +/****************** Bit definition for CRM_OTGHS register *******************/ +#define CRM_OTGHS_USBHS_PHY12_SEL_Pos (4U) +#define CRM_OTGHS_USBHS_PHY12_SEL_Msk (0x1U << CRM_OTGHS_USBHS_PHY12_SEL_Pos) /*!< 0x00000010 */ +#define CRM_OTGHS_USBHS_PHY12_SEL CRM_OTGHS_USBHS_PHY12_SEL_Msk /*!< USBHS PHY 12M clock source select (F405 only) */ + +/****************** Bit definition for CRM_MISC1 register *******************/ +#define CRM_MISC1_HICKCAL_KEY_Pos (0U) +#define CRM_MISC1_HICKCAL_KEY_Msk (0xFFU << CRM_MISC1_HICKCAL_KEY_Pos) /*!< 0x000000FF */ +#define CRM_MISC1_HICKCAL_KEY CRM_MISC1_HICKCAL_KEY_Msk /*!< HICK calibration key */ +#define CRM_MISC1_HICKDIV_Pos (12U) +#define CRM_MISC1_HICKDIV_Msk (0x1U << CRM_MISC1_HICKDIV_Pos) /*!< 0x00001000 */ +#define CRM_MISC1_HICKDIV CRM_MISC1_HICKDIV_Msk /*!< HICK 6 divider selection */ +#define CRM_MISC1_HICK_TO_SCLK_Pos (14U) +#define CRM_MISC1_HICK_TO_SCLK_Msk (0x1U << CRM_MISC1_HICK_TO_SCLK_Pos) /*!< 0x00004000 */ +#define CRM_MISC1_HICK_TO_SCLK CRM_MISC1_HICK_TO_SCLK_Msk /*!< HICK as system clock frequency select */ +#define CRM_MISC1_HICKRST_Pos (15U) +#define CRM_MISC1_HICKRST_Msk (0x1U << CRM_MISC1_HICKRST_Pos) /*!< 0x00008000 */ +#define CRM_MISC1_HICKRST CRM_MISC1_HICKRST_Msk /*!< HICKRST */ + +/*!< CLKOUT_SEL2 congiguration */ +#define CRM_MISC1_CLKOUT_SEL2_Pos (16U) +#define CRM_MISC1_CLKOUT_SEL2_Msk (0xFU << CRM_MISC1_CLKOUT_SEL2_Pos) /*!< 0x000F0000 */ +#define CRM_MISC1_CLKOUT_SEL2 CRM_MISC1_CLKOUT_SEL2_Msk /*!< CLKOUT_SEL2[3:0] bits (Clock output selection 2) */ +#define CRM_MISC1_CLKOUT_SEL2_0 (0x1U << CRM_MISC1_CLKOUT_SEL2_Pos) /*!< 0x00010000 */ +#define CRM_MISC1_CLKOUT_SEL2_1 (0x2U << CRM_MISC1_CLKOUT_SEL2_Pos) /*!< 0x00020000 */ +#define CRM_MISC1_CLKOUT_SEL2_2 (0x4U << CRM_MISC1_CLKOUT_SEL2_Pos) /*!< 0x00040000 */ +#define CRM_MISC1_CLKOUT_SEL2_3 (0x8U << CRM_MISC1_CLKOUT_SEL2_Pos) /*!< 0x00080000 */ + +#define CRM_MISC1_CLKOUT_SEL2_USBFS 0x00000000U /*!< USBFS 48M */ +#define CRM_MISC1_CLKOUT_SEL2_ADC 0x00010000U /*!< ADC */ +#define CRM_MISC1_CLKOUT_SEL2_HICK 0x00020000U /*!< HICK */ +#define CRM_MISC1_CLKOUT_SEL2_LICK 0x00030000U /*!< LICK */ +#define CRM_MISC1_CLKOUT_SEL2_LEXT 0x00040000U /*!< LEXT */ + +/* Reference defines */ +#define CRM_MISC1_CLKSEL2 CRM_MISC1_CLKOUT_SEL2 +#define CRM_MISC1_CLKSEL2_0 CRM_MISC1_CLKOUT_SEL2_0 +#define CRM_MISC1_CLKSEL2_1 CRM_MISC1_CLKOUT_SEL2_1 +#define CRM_MISC1_CLKSEL2_2 CRM_MISC1_CLKOUT_SEL2_2 +#define CRM_MISC1_CLKSEL2_3 CRM_MISC1_CLKOUT_SEL2_3 +#define CRM_MISC1_CLKSEL2_USBFS CRM_MISC1_CLKOUT_SEL2_USBFS +#define CRM_MISC1_CLKSEL2_ADC CRM_MISC1_CLKOUT_SEL2_ADC +#define CRM_MISC1_CLKSEL2_HICK CRM_MISC1_CLKOUT_SEL2_HICK +#define CRM_MISC1_CLKSEL2_LICK CRM_MISC1_CLKOUT_SEL2_LICK +#define CRM_MISC1_CLKSEL2_LEXT CRM_MISC1_CLKOUT_SEL2_LEXT + +/*!< CLKOUTDIV2 congiguration */ +#define CRM_MISC1_CLKOUTDIV2_Pos (28U) +#define CRM_MISC1_CLKOUTDIV2_Msk (0xFU << CRM_MISC1_CLKOUTDIV2_Pos) /*!< 0xF0000000 */ +#define CRM_MISC1_CLKOUTDIV2 CRM_MISC1_CLKOUTDIV2_Msk /*!< CLKOUTDIV2[3:0] bits (Clock output division 2) */ +#define CRM_MISC1_CLKOUTDIV2_0 (0x1U << CRM_MISC1_CLKOUTDIV2_Pos) /*!< 0x10000000 */ +#define CRM_MISC1_CLKOUTDIV2_1 (0x2U << CRM_MISC1_CLKOUTDIV2_Pos) /*!< 0x20000000 */ +#define CRM_MISC1_CLKOUTDIV2_2 (0x4U << CRM_MISC1_CLKOUTDIV2_Pos) /*!< 0x40000000 */ +#define CRM_MISC1_CLKOUTDIV2_3 (0x8U << CRM_MISC1_CLKOUTDIV2_Pos) /*!< 0x80000000 */ + +#define CRM_MISC1_CLKOUTDIV2_DIV1 0x00000000U /*!< No clock output */ +#define CRM_MISC1_CLKOUTDIV2_DIV2 0x80000000U /*!< Clock output divided by 2 */ +#define CRM_MISC1_CLKOUTDIV2_DIV4 0x90000000U /*!< Clock output divided by 4 */ +#define CRM_MISC1_CLKOUTDIV2_DIV8 0xA0000000U /*!< Clock output divided by 8 */ +#define CRM_MISC1_CLKOUTDIV2_DIV16 0xB0000000U /*!< Clock output divided by 16 */ +#define CRM_MISC1_CLKOUTDIV2_DIV64 0xC0000000U /*!< Clock output divided by 64 */ +#define CRM_MISC1_CLKOUTDIV2_DIV128 0xD0000000U /*!< Clock output divided by 128 */ +#define CRM_MISC1_CLKOUTDIV2_DIV256 0xE0000000U /*!< Clock output divided by 256 */ +#define CRM_MISC1_CLKOUTDIV2_DIV512 0xF0000000U /*!< Clock output divided by 512 */ + +/****************** Bit definition for CRM_MISC2 register *******************/ +/*!< AUTO_STEP_EN congiguration */ +#define CRM_MISC2_AUTO_STEP_EN_Pos (4U) +#define CRM_MISC2_AUTO_STEP_EN_Msk (0x3U << CRM_MISC2_AUTO_STEP_EN_Pos) /*!< 0x00000030 */ +#define CRM_MISC2_AUTO_STEP_EN CRM_MISC2_AUTO_STEP_EN_Msk /*!< AUTO_STEP_EN[1:0] bits (Auto step-by-step SCLK switch enable) */ +#define CRM_MISC2_AUTO_STEP_EN_0 (0x1U << CRM_MISC2_AUTO_STEP_EN_Pos) /*!< 0x00000010 */ +#define CRM_MISC2_AUTO_STEP_EN_1 (0x2U << CRM_MISC2_AUTO_STEP_EN_Pos) /*!< 0x00000020 */ + +#define CRM_MISC2_PLLU_USB48_SEL_Pos (10U) +#define CRM_MISC2_PLLU_USB48_SEL_Msk (0x1U << CRM_MISC2_PLLU_USB48_SEL_Pos) /*!< 0x00000400 */ +#define CRM_MISC2_PLLU_USB48_SEL CRM_MISC2_PLLU_USB48_SEL_Msk /*!< USBFS 48M clock source selection */ + +/*!< HICK_TO_SCLK_DIV congiguration */ +#define CRM_MISC2_HICK_TO_SCLK_DIV_Pos (16U) +#define CRM_MISC2_HICK_TO_SCLK_DIV_Msk (0x7U << CRM_MISC2_HICK_TO_SCLK_DIV_Pos) /*!< 0x00070000 */ +#define CRM_MISC2_HICK_TO_SCLK_DIV CRM_MISC2_HICK_TO_SCLK_DIV_Msk /*!< HICK_TO_SCLK_DIV[2:0] bits (HICK as SCLK frequency division) */ +#define CRM_MISC2_HICK_TO_SCLK_DIV_0 (0x1U << CRM_MISC2_HICK_TO_SCLK_DIV_Pos) /*!< 0x00010000 */ +#define CRM_MISC2_HICK_TO_SCLK_DIV_1 (0x2U << CRM_MISC2_HICK_TO_SCLK_DIV_Pos) /*!< 0x00020000 */ +#define CRM_MISC2_HICK_TO_SCLK_DIV_2 (0x4U << CRM_MISC2_HICK_TO_SCLK_DIV_Pos) /*!< 0x00040000 */ + +#define CRM_MISC2_HICK_TO_SCLK_DIV_DIV1 0x00000000U /*!< HICK */ +#define CRM_MISC2_HICK_TO_SCLK_DIV_DIV2 0x00010000U /*!< HICK/2 */ +#define CRM_MISC2_HICK_TO_SCLK_DIV_DIV4 0x00020000U /*!< HICK/4 */ +#define CRM_MISC2_HICK_TO_SCLK_DIV_DIV8 0x00030000U /*!< HICK/8 */ +#define CRM_MISC2_HICK_TO_SCLK_DIV_DIV16 0x00040000U /*!< HICK/16 */ + +/*!< HEXT_TO_SCLK_DIV congiguration */ +#define CRM_MISC2_HEXT_TO_SCLK_DIV_Pos (19U) +#define CRM_MISC2_HEXT_TO_SCLK_DIV_Msk (0x7U << CRM_MISC2_HEXT_TO_SCLK_DIV_Pos) /*!< 0x00380000 */ +#define CRM_MISC2_HEXT_TO_SCLK_DIV CRM_MISC2_HEXT_TO_SCLK_DIV_Msk /*!< HEXT_TO_SCLK_DIV[2:0] bits (HEXT as SCLK frequency division) */ +#define CRM_MISC2_HEXT_TO_SCLK_DIV_0 (0x1U << CRM_MISC2_HEXT_TO_SCLK_DIV_Pos) /*!< 0x00080000 */ +#define CRM_MISC2_HEXT_TO_SCLK_DIV_1 (0x2U << CRM_MISC2_HEXT_TO_SCLK_DIV_Pos) /*!< 0x00100000 */ +#define CRM_MISC2_HEXT_TO_SCLK_DIV_2 (0x4U << CRM_MISC2_HEXT_TO_SCLK_DIV_Pos) /*!< 0x00200000 */ + +#define CRM_MISC2_HEXT_TO_SCLK_DIV_DIV1 0x00000000U /*!< HEXT */ +#define CRM_MISC2_HEXT_TO_SCLK_DIV_DIV2 0x00080000U /*!< HEXT/2 */ +#define CRM_MISC2_HEXT_TO_SCLK_DIV_DIV4 0x00100000U /*!< HEXT/4 */ +#define CRM_MISC2_HEXT_TO_SCLK_DIV_DIV8 0x00180000U /*!< HEXT/8 */ +#define CRM_MISC2_HEXT_TO_SCLK_DIV_DIV16 0x00200000U /*!< HEXT/16 */ +#define CRM_MISC2_HEXT_TO_SCLK_DIV_DIV32 0x00280000U /*!< HEXT/32 */ + +/******************************************************************************/ +/* */ +/* Flash and User System Data Registers (FLASH) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for FLASH_PSR register ******************/ +/*!< WTCYC congiguration */ +#define FLASH_PSR_WTCYC_Pos (0U) +#define FLASH_PSR_WTCYC_Msk (0x7U << FLASH_PSR_WTCYC_Pos) /*!< 0x00000007 */ +#define FLASH_PSR_WTCYC FLASH_PSR_WTCYC_Msk /*!< WTCYC[2:0] bits (Wait cycle) */ +#define FLASH_PSR_WTCYC_0 (0x1U << FLASH_PSR_WTCYC_Pos) /*!< 0x00000001 */ +#define FLASH_PSR_WTCYC_1 (0x2U << FLASH_PSR_WTCYC_Pos) /*!< 0x00000002 */ +#define FLASH_PSR_WTCYC_2 (0x4U << FLASH_PSR_WTCYC_Pos) /*!< 0x00000004 */ + +#define FLASH_PSR_PFT_EN_Pos (4U) +#define FLASH_PSR_PFT_EN_Msk (0x1U << FLASH_PSR_PFT_EN_Pos) /*!< 0x00000010 */ +#define FLASH_PSR_PFT_EN FLASH_PSR_PFT_EN_Msk /*!< Prefetch enable */ +#define FLASH_PSR_PFT_ENF_Pos (5U) +#define FLASH_PSR_PFT_ENF_Msk (0x1U << FLASH_PSR_PFT_ENF_Pos) /*!< 0x00000020 */ +#define FLASH_PSR_PFT_ENF FLASH_PSR_PFT_ENF_Msk /*!< Prefetch enable flag */ +#define FLASH_PSR_PFT_EN2_Pos (6U) +#define FLASH_PSR_PFT_EN2_Msk (0x1U << FLASH_PSR_PFT_EN2_Pos) /*!< 0x00000040 */ +#define FLASH_PSR_PFT_EN2 FLASH_PSR_PFT_EN2_Msk /*!< Prefetch enable 2 */ +#define FLASH_PSR_PFT_ENF2_Pos (7U) +#define FLASH_PSR_PFT_ENF2_Msk (0x1U << FLASH_PSR_PFT_ENF2_Pos) /*!< 0x00000080 */ +#define FLASH_PSR_PFT_ENF2 FLASH_PSR_PFT_ENF2_Msk /*!< Prefetch enable flag 2 */ +#define FLASH_PSR_PFT_LAT_DIS_Pos (8U) +#define FLASH_PSR_PFT_LAT_DIS_Msk (0x1U << FLASH_PSR_PFT_LAT_DIS_Pos) /*!< 0x00000100 */ +#define FLASH_PSR_PFT_LAT_DIS FLASH_PSR_PFT_LAT_DIS_Msk /*!< Prefetch latency disable */ + +/***************** Bit definition for FLASH_UNLOCK register *****************/ +#define FLASH_UNLOCK_UKVAL_Pos (0U) +#define FLASH_UNLOCK_UKVAL_Msk (0xFFFFFFFFU << FLASH_UNLOCK_UKVAL_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_UNLOCK_UKVAL FLASH_UNLOCK_UKVAL_Msk /*!< Unlock key value */ + +#define FAP_KEY_Pos (0U) +#define FAP_KEY_Msk (0xA5U << FAP_KEY_Pos) /*!< 0x000000A5 */ +#define FAP_KEY FAP_KEY_Msk /*!< Flash access protection key */ +#define FLASH_KEY1_Pos (0U) +#define FLASH_KEY1_Msk (0x45670123U << FLASH_KEY1_Pos) /*!< 0x45670123 */ +#define FLASH_KEY1 FLASH_KEY1_Msk /*!< Flash key 1 */ +#define FLASH_KEY2_Pos (0U) +#define FLASH_KEY2_Msk (0xCDEF89ABU << FLASH_KEY2_Pos) /*!< 0xCDEF89AB */ +#define FLASH_KEY2 FLASH_KEY2_Msk /*!< Flash key 2 */ + +/*************** Bit definition for FLASH_USD_UNLOCK register ***************/ +#define FLASH_USD_UNLOCK_USD_UKVAL_Pos (0U) /*!< 0xFFFFFFFF */ +#define FLASH_USD_UNLOCK_USD_UKVAL_Msk (0xFFFFFFFFU << FLASH_USD_UNLOCK_USD_UKVAL_Pos) +#define FLASH_USD_UNLOCK_USD_UKVAL FLASH_USD_UNLOCK_USD_UKVAL_Msk /*!< User system data unlock key value */ + +#define FLASH_USDKEY1 FLASH_KEY1 /*!< User system data key 1 */ +#define FLASH_USDKEY2 FLASH_KEY2 /*!< User system data key 2 */ + +/****************** Bit definition for FLASH_STS register *******************/ +#define FLASH_STS_OBF_Pos (0U) +#define FLASH_STS_OBF_Msk (0x1U << FLASH_STS_OBF_Pos) /*!< 0x00000001 */ +#define FLASH_STS_OBF FLASH_STS_OBF_Msk /*!< Operation busy flag */ +#define FLASH_STS_PRGMERR_Pos (2U) +#define FLASH_STS_PRGMERR_Msk (0x1U << FLASH_STS_PRGMERR_Pos) /*!< 0x00000004 */ +#define FLASH_STS_PRGMERR FLASH_STS_PRGMERR_Msk /*!< Programming error */ +#define FLASH_STS_EPPERR_Pos (4U) +#define FLASH_STS_EPPERR_Msk (0x1U << FLASH_STS_EPPERR_Pos) /*!< 0x00000010 */ +#define FLASH_STS_EPPERR FLASH_STS_EPPERR_Msk /*!< Erase/program protection error */ +#define FLASH_STS_ODF_Pos (5U) +#define FLASH_STS_ODF_Msk (0x1U << FLASH_STS_ODF_Pos) /*!< 0x00000020 */ +#define FLASH_STS_ODF FLASH_STS_ODF_Msk /*!< Operation done flag */ + +/****************** Bit definition for FLASH_CTRL register ******************/ +#define FLASH_CTRL_FPRGM_Pos (0U) +#define FLASH_CTRL_FPRGM_Msk (0x1U << FLASH_CTRL_FPRGM_Pos) /*!< 0x00000001 */ +#define FLASH_CTRL_FPRGM FLASH_CTRL_FPRGM_Msk /*!< Flash program */ +#define FLASH_CTRL_SECERS_Pos (1U) +#define FLASH_CTRL_SECERS_Msk (0x1U << FLASH_CTRL_SECERS_Pos) /*!< 0x00000002 */ +#define FLASH_CTRL_SECERS FLASH_CTRL_SECERS_Msk /*!< Page erase */ +#define FLASH_CTRL_BANKERS_Pos (2U) +#define FLASH_CTRL_BANKERS_Msk (0x1U << FLASH_CTRL_BANKERS_Pos) /*!< 0x00000004 */ +#define FLASH_CTRL_BANKERS FLASH_CTRL_BANKERS_Msk /*!< Bank erase */ +#define FLASH_CTRL_USDPRGM_Pos (4U) +#define FLASH_CTRL_USDPRGM_Msk (0x1U << FLASH_CTRL_USDPRGM_Pos) /*!< 0x00000010 */ +#define FLASH_CTRL_USDPRGM FLASH_CTRL_USDPRGM_Msk /*!< User system data program */ +#define FLASH_CTRL_USDERS_Pos (5U) +#define FLASH_CTRL_USDERS_Msk (0x1U << FLASH_CTRL_USDERS_Pos) /*!< 0x00000020 */ +#define FLASH_CTRL_USDERS FLASH_CTRL_USDERS_Msk /*!< User system data erase */ +#define FLASH_CTRL_ERSTR_Pos (6U) +#define FLASH_CTRL_ERSTR_Msk (0x1U << FLASH_CTRL_ERSTR_Pos) /*!< 0x00000040 */ +#define FLASH_CTRL_ERSTR FLASH_CTRL_ERSTR_Msk /*!< Erase start */ +#define FLASH_CTRL_OPLK_Pos (7U) +#define FLASH_CTRL_OPLK_Msk (0x1U << FLASH_CTRL_OPLK_Pos) /*!< 0x00000080 */ +#define FLASH_CTRL_OPLK FLASH_CTRL_OPLK_Msk /*!< Operation lock */ +#define FLASH_CTRL_USDULKS_Pos (9U) +#define FLASH_CTRL_USDULKS_Msk (0x1U << FLASH_CTRL_USDULKS_Pos) /*!< 0x00000200 */ +#define FLASH_CTRL_USDULKS FLASH_CTRL_USDULKS_Msk /*!< User system data unlock success */ +#define FLASH_CTRL_ERRIE_Pos (10U) +#define FLASH_CTRL_ERRIE_Msk (0x1U << FLASH_CTRL_ERRIE_Pos) /*!< 0x00000400 */ +#define FLASH_CTRL_ERRIE FLASH_CTRL_ERRIE_Msk /*!< Error interrupt enable */ +#define FLASH_CTRL_ODFIE_Pos (12U) +#define FLASH_CTRL_ODFIE_Msk (0x1U << FLASH_CTRL_ODFIE_Pos) /*!< 0x00001000 */ +#define FLASH_CTRL_ODFIE FLASH_CTRL_ODFIE_Msk /*!< Operation done flag interrupt enable */ + +/****************** Bit definition for FLASH_ADDR register ******************/ +#define FLASH_ADDR_FA_Pos (0U) +#define FLASH_ADDR_FA_Msk (0xFFFFFFFFU << FLASH_ADDR_FA_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_ADDR_FA FLASH_ADDR_FA_Msk /*!< Flash address */ + +/****************** Bit definition for FLASH_USD register *******************/ +#define FLASH_USD_USDERR_Pos (0U) +#define FLASH_USD_USDERR_Msk (0x1U << FLASH_USD_USDERR_Pos) /*!< 0x00000001 */ +#define FLASH_USD_USDERR FLASH_USD_USDERR_Msk /*!< User system data error */ +#define FLASH_USD_FAP_Pos (1U) +#define FLASH_USD_FAP_Msk (0x1U << FLASH_USD_FAP_Pos) /*!< 0x00000002 */ +#define FLASH_USD_FAP FLASH_USD_FAP_Msk /*!< Flash access protection */ + +/*!< SSB congiguration */ +#define FLASH_USD_WDT_ATO_EN_Pos (2U) +#define FLASH_USD_WDT_ATO_EN_Msk (0x1U << FLASH_USD_WDT_ATO_EN_Pos) /*!< 0x00000004 */ +#define FLASH_USD_WDT_ATO_EN FLASH_USD_WDT_ATO_EN_Msk /*!< nWDT_ATO_EN */ +#define FLASH_USD_DEPSLP_RST_Pos (3U) +#define FLASH_USD_DEPSLP_RST_Msk (0x1U << FLASH_USD_DEPSLP_RST_Pos) /*!< 0x00000008 */ +#define FLASH_USD_DEPSLP_RST FLASH_USD_DEPSLP_RST_Msk /*!< nDEPSLP_RST */ +#define FLASH_USD_STDBY_RST_Pos (4U) +#define FLASH_USD_STDBY_RST_Msk (0x1U << FLASH_USD_STDBY_RST_Pos) /*!< 0x00000010 */ +#define FLASH_USD_STDBY_RST FLASH_USD_STDBY_RST_Msk /*!< nSTDBY_RST */ +#define FLASH_USD_BOOT1_Pos (6U) +#define FLASH_USD_BOOT1_Msk (0x1U << FLASH_USD_BOOT1_Pos) /*!< 0x00000040 */ +#define FLASH_USD_BOOT1 FLASH_USD_BOOT1_Msk /*!< nBOOT1 */ +#define FLASH_USD_DEPSLP_WDT_Pos (7U) +#define FLASH_USD_DEPSLP_WDT_Msk (0x1U << FLASH_USD_DEPSLP_WDT_Pos) /*!< 0x00000080 */ +#define FLASH_USD_DEPSLP_WDT FLASH_USD_DEPSLP_WDT_Msk /*!< nDEPSLP_WDT */ +#define FLASH_USD_STDBY_WDT_Pos (8U) +#define FLASH_USD_STDBY_WDT_Msk (0x1U << FLASH_USD_STDBY_WDT_Pos) /*!< 0x00000100 */ +#define FLASH_USD_STDBY_WDT FLASH_USD_STDBY_WDT_Msk /*!< nSTDBY_WDT */ +#define FLASH_USD_RAM_PRT_CHK_Pos (9U) +#define FLASH_USD_RAM_PRT_CHK_Msk (0x1U << FLASH_USD_RAM_PRT_CHK_Pos) /*!< 0x00000200 */ +#define FLASH_USD_RAM_PRT_CHK FLASH_USD_RAM_PRT_CHK_Msk /*!< nRAM_PRT_CHK */ +#define FLASH_USD_SSB_Pos (2U) +#define FLASH_USD_SSB_Msk (0xFFU << FLASH_USD_SSB_Pos) /*!< 0x000003FC */ +#define FLASH_USD_SSB FLASH_USD_SSB_Msk /*!< System setting byte */ + +#define FLASH_USD_USER_D0_Pos (10U) +#define FLASH_USD_USER_D0_Msk (0xFFU << FLASH_USD_USER_D0_Pos) /*!< 0x0003FC00 */ +#define FLASH_USD_USER_D0 FLASH_USD_USER_D0_Msk /*!< User data 0 */ +#define FLASH_USD_USER_D1_Pos (18U) +#define FLASH_USD_USER_D1_Msk (0xFFU << FLASH_USD_USER_D1_Pos) /*!< 0x03FC0000 */ +#define FLASH_USD_USER_D1 FLASH_USD_USER_D1_Msk /*!< User data 1 */ +#define FLASH_USD_FAP_HL_Pos (26U) +#define FLASH_USD_FAP_HL_Msk (0x1U << FLASH_USD_FAP_HL_Pos) /*!< 0x04000000 */ +#define FLASH_USD_FAP_HL FLASH_USD_FAP_HL_Msk /*!< Flash access protection high level */ + +/****************** Bit definition for FLASH_EPPS register ******************/ +#define FLASH_EPPS_EPPS_Pos (0U) +#define FLASH_EPPS_EPPS_Msk (0xFFFFFFFFU << FLASH_EPPS_EPPS_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_EPPS_EPPS FLASH_EPPS_EPPS_Msk /*!< Erase/Program protection status */ + +/******************* Bit definition for SLIB_STS0 register *******************/ +#define SLIB_STS0_BTM_AP_ENF_Pos (0U) +#define SLIB_STS0_BTM_AP_ENF_Msk (0x1U << SLIB_STS0_BTM_AP_ENF_Pos) /*!< 0x00000001 */ +#define SLIB_STS0_BTM_AP_ENF SLIB_STS0_BTM_AP_ENF_Msk /*!< Boot memory store application code enabled flag */ +#define SLIB_STS0_EM_SLIB_ENF_Pos (2U) +#define SLIB_STS0_EM_SLIB_ENF_Msk (0x1U << SLIB_STS0_EM_SLIB_ENF_Pos) /*!< 0x00000004 */ +#define SLIB_STS0_EM_SLIB_ENF SLIB_STS0_EM_SLIB_ENF_Msk /*!< Extension memory sLib enable flag */ +#define SLIB_STS0_SLIB_ENF_Pos (3U) +#define SLIB_STS0_SLIB_ENF_Msk (0x1U << SLIB_STS0_SLIB_ENF_Pos) /*!< 0x00000008 */ +#define SLIB_STS0_SLIB_ENF SLIB_STS0_SLIB_ENF_Msk /*!< Security library enable flag */ +#define SLIB_STS0_EM_SLIB_INST_SS_Pos (16U) /*!< 0x00FF0000 */ +#define SLIB_STS0_EM_SLIB_INST_SS_Msk (0xFFU << SLIB_STS0_EM_SLIB_INST_SS_Pos) +#define SLIB_STS0_EM_SLIB_INST_SS SLIB_STS0_EM_SLIB_INST_SS_Msk /*!< Extension memory sLib instruction start page */ + +/******************* Bit definition for SLIB_STS1 register *******************/ +#define SLIB_STS1_SLIB_SS_Pos (0U) +#define SLIB_STS1_SLIB_SS_Msk (0x7FFU << SLIB_STS1_SLIB_SS_Pos) /*!< 0x000007FF */ +#define SLIB_STS1_SLIB_SS SLIB_STS1_SLIB_SS_Msk /*!< Security library start page */ +#define SLIB_STS1_SLIB_INST_SS_Pos (11U) +#define SLIB_STS1_SLIB_INST_SS_Msk (0x7FFU << SLIB_STS1_SLIB_INST_SS_Pos) /*!< 0x003FF800 */ +#define SLIB_STS1_SLIB_INST_SS SLIB_STS1_SLIB_INST_SS_Msk /*!< Security library instruction start page */ +#define SLIB_STS1_SLIB_ES_Pos (22U) +#define SLIB_STS1_SLIB_ES_Msk (0x3FFU << SLIB_STS1_SLIB_ES_Pos) /*!< 0xFFC00000 */ +#define SLIB_STS1_SLIB_ES SLIB_STS1_SLIB_ES_Msk /*!< Security library end page */ + +/***************** Bit definition for SLIB_PWD_CLR register ******************/ +#define SLIB_PWD_CLR_SLIB_PCLR_VAL_Pos (0U) /*!< 0xFFFFFFFF */ +#define SLIB_PWD_CLR_SLIB_PCLR_VAL_Msk (0xFFFFFFFFU << SLIB_PWD_CLR_SLIB_PCLR_VAL_Pos) +#define SLIB_PWD_CLR_SLIB_PCLR_VAL SLIB_PWD_CLR_SLIB_PCLR_VAL_Msk /*!< Security library password clear value */ + +/***************** Bit definition for SLIB_MISC_STS register *****************/ +#define SLIB_MISC_STS_SLIB_PWD_ERR_Pos (0U) /*!< 0x00000001 */ +#define SLIB_MISC_STS_SLIB_PWD_ERR_Msk (0x1U << SLIB_MISC_STS_SLIB_PWD_ERR_Pos) +#define SLIB_MISC_STS_SLIB_PWD_ERR SLIB_MISC_STS_SLIB_PWD_ERR_Msk /*!< Security library password error */ +#define SLIB_MISC_STS_SLIB_PWD_OK_Pos (1U) +#define SLIB_MISC_STS_SLIB_PWD_OK_Msk (0x1U << SLIB_MISC_STS_SLIB_PWD_OK_Pos) /*!< 0x00000002 */ +#define SLIB_MISC_STS_SLIB_PWD_OK SLIB_MISC_STS_SLIB_PWD_OK_Msk /*!< Security library password ok */ +#define SLIB_MISC_STS_SLIB_ULKF_Pos (2U) +#define SLIB_MISC_STS_SLIB_ULKF_Msk (0x1U << SLIB_MISC_STS_SLIB_ULKF_Pos) /*!< 0x00000004 */ +#define SLIB_MISC_STS_SLIB_ULKF SLIB_MISC_STS_SLIB_ULKF_Msk /*!< Security library unlock flag */ + +/**************** Bit definition for FLASH_CRC_ADDR register *****************/ +#define FLASH_CRC_ADDR_CRC_ADDR_Pos (0U) /*!< 0xFFFFFFFF */ +#define FLASH_CRC_ADDR_CRC_ADDR_Msk (0xFFFFFFFFU << FLASH_CRC_ADDR_CRC_ADDR_Pos) +#define FLASH_CRC_ADDR_CRC_ADDR FLASH_CRC_ADDR_CRC_ADDR_Msk /*!< CRC address */ + +/**************** Bit definition for FLASH_CRC_CTRL register *****************/ +#define FLASH_CRC_CTRL_CRC_SN_Pos (0U) +#define FLASH_CRC_CTRL_CRC_SN_Msk (0xFFFFU << FLASH_CRC_CTRL_CRC_SN_Pos) /*!< 0x0000FFFF */ +#define FLASH_CRC_CTRL_CRC_SN FLASH_CRC_CTRL_CRC_SN_Msk /*!< CRC page number */ +#define FLASH_CRC_CTRL_CRC_STRT_Pos (16U) +#define FLASH_CRC_CTRL_CRC_STRT_Msk (0x1U << FLASH_CRC_CTRL_CRC_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_CRC_CTRL_CRC_STRT FLASH_CRC_CTRL_CRC_STRT_Msk /*!< CRC start */ + +/**************** Bit definition for FLASH_CRC_CHKR register *****************/ +#define FLASH_CRC_CHKR_CRC_CHKR_Pos (0U) /*!< 0xFFFFFFFF */ +#define FLASH_CRC_CHKR_CRC_CHKR_Msk (0xFFFFFFFFU << FLASH_CRC_CHKR_CRC_CHKR_Pos) +#define FLASH_CRC_CHKR_CRC_CHKR FLASH_CRC_CHKR_CRC_CHKR_Msk /*!< CRC check result */ + +/***************** Bit definition for SLIB_SET_PWD register ******************/ +#define SLIB_SET_PWD_SLIB_PSET_VAL_Pos (0U) /*!< 0xFFFFFFFF */ +#define SLIB_SET_PWD_SLIB_PSET_VAL_Msk (0xFFFFFFFFU << SLIB_SET_PWD_SLIB_PSET_VAL_Pos) +#define SLIB_SET_PWD_SLIB_PSET_VAL SLIB_SET_PWD_SLIB_PSET_VAL_Msk /*!< Security library password setting value */ + +/**************** Bit definition for SLIB_SET_RANGE register *****************/ +#define SLIB_SET_RANGE_SLIB_SS_SET_Pos (0U) /*!< 0x000007FF */ +#define SLIB_SET_RANGE_SLIB_SS_SET_Msk (0x7FFU << SLIB_SET_RANGE_SLIB_SS_SET_Pos) +#define SLIB_SET_RANGE_SLIB_SS_SET SLIB_SET_RANGE_SLIB_SS_SET_Msk /*!< Security library start page setting */ +#define SLIB_SET_RANGE_SLIB_ISS_SET_Pos (11U) /*!< 0x003FF800 */ +#define SLIB_SET_RANGE_SLIB_ISS_SET_Msk (0x7FFU << SLIB_SET_RANGE_SLIB_ISS_SET_Pos) +#define SLIB_SET_RANGE_SLIB_ISS_SET SLIB_SET_RANGE_SLIB_ISS_SET_Msk /*!< Security library instruction start page setting */ +#define SLIB_SET_RANGE_SLIB_ES_SET_Pos (22U) /*!< 0xFFC00000 */ +#define SLIB_SET_RANGE_SLIB_ES_SET_Msk (0x3FFU << SLIB_SET_RANGE_SLIB_ES_SET_Pos) +#define SLIB_SET_RANGE_SLIB_ES_SET SLIB_SET_RANGE_SLIB_ES_SET_Msk /*!< Security library end page setting */ + +/****************** Bit definition for EM_SLIB_SET register ******************/ +#define EM_SLIB_SET_EM_SLIB_SET_Pos (0U) /*!< 0x0000FFFF */ +#define EM_SLIB_SET_EM_SLIB_SET_Msk (0xFFFFU << EM_SLIB_SET_EM_SLIB_SET_Pos) +#define EM_SLIB_SET_EM_SLIB_SET EM_SLIB_SET_EM_SLIB_SET_Msk /*!< Extension memory sLib setting */ +#define EM_SLIB_SET_EM_SLIB_ISS_SET_Pos (16U) /*!< 0x00FF0000 */ +#define EM_SLIB_SET_EM_SLIB_ISS_SET_Msk (0xFFU << EM_SLIB_SET_EM_SLIB_ISS_SET_Pos) +#define EM_SLIB_SET_EM_SLIB_ISS_SET EM_SLIB_SET_EM_SLIB_ISS_SET_Msk /*!< Extension memory sLib instruction start page setting */ + +/***************** Bit definition for BTM_MODE_SET register ******************/ +#define BTM_MODE_SET_BTM_MODE_SET_Pos (0U) /*!< 0x000000FF */ +#define BTM_MODE_SET_BTM_MODE_SET_Msk (0xFFU << BTM_MODE_SET_BTM_MODE_SET_Pos) +#define BTM_MODE_SET_BTM_MODE_SET BTM_MODE_SET_BTM_MODE_SET_Msk /*!< Boot memory mode setting */ + +/***************** Bit definition for SLIB_UNLOCK register ******************/ +#define SLIB_UNLOCK_SLIB_UKVAL_Pos (0U) /*!< 0xFFFFFFFF */ +#define SLIB_UNLOCK_SLIB_UKVAL_Msk (0xFFFFFFFFU << SLIB_UNLOCK_SLIB_UKVAL_Pos) +#define SLIB_UNLOCK_SLIB_UKVAL SLIB_UNLOCK_SLIB_UKVAL_Msk /*!< Security library unlock key value */ + +#define SLIB_KEY_Pos (0U) +#define SLIB_KEY_Msk (0xA35F6D24U << SLIB_KEY_Pos) /*!< 0xA35F6D24 */ +#define SLIB_KEY SLIB_KEY_Msk /*!< Security library key */ + +/*----------------------------------------------------------------------------*/ + +/****************** Bit definition for FLASH_FAP register *******************/ +#define FLASH_FAP_FAP_Pos (0U) +#define FLASH_FAP_FAP_Msk (0xFFU << FLASH_FAP_FAP_Pos) /*!< 0x000000FF */ +#define FLASH_FAP_FAP FLASH_FAP_FAP_Msk /*!< Flash memory access protection */ +#define FLASH_FAP_nFAP_Pos (8U) +#define FLASH_FAP_nFAP_Msk (0xFFU << FLASH_FAP_nFAP_Pos) /*!< 0x0000FF00 */ +#define FLASH_FAP_nFAP FLASH_FAP_nFAP_Msk /*!< Inverse code of flash memory access protection */ + +/****************** Bit definition for FLASH_SSB register *******************/ +#define FLASH_SSB_SSB_Pos (16U) +#define FLASH_SSB_SSB_Msk (0xFFU << FLASH_SSB_SSB_Pos) /*!< 0x00FF0000 */ +#define FLASH_SSB_SSB FLASH_SSB_SSB_Msk /*!< System configuration byte */ +#define FLASH_SSB_nSSB_Pos (24U) +#define FLASH_SSB_nSSB_Msk (0xFFU << FLASH_SSB_nSSB_Pos) /*!< 0xFF000000 */ +#define FLASH_SSB_nSSB FLASH_SSB_nSSB_Msk /*!< Inverse code of system configuration byte */ + +/***************** Bit definition for FLASH_DATA0 register ******************/ +#define FLASH_DATA0_DATA0_Pos (0U) +#define FLASH_DATA0_DATA0_Msk (0xFFU << FLASH_DATA0_DATA0_Pos) /*!< 0x000000FF */ +#define FLASH_DATA0_DATA0 FLASH_DATA0_DATA0_Msk /*!< User data 0 */ +#define FLASH_DATA0_nDATA0_Pos (8U) +#define FLASH_DATA0_nDATA0_Msk (0xFFU << FLASH_DATA0_nDATA0_Pos) /*!< 0x0000FF00 */ +#define FLASH_DATA0_nDATA0 FLASH_DATA0_nDATA0_Msk /*!< Inverse code of user data 0 */ + +/***************** Bit definition for FLASH_DATA1 register ******************/ +#define FLASH_DATA1_DATA1_Pos (16U) +#define FLASH_DATA1_DATA1_Msk (0xFFU << FLASH_DATA1_DATA1_Pos) /*!< 0x00FF0000 */ +#define FLASH_DATA1_DATA1 FLASH_DATA1_DATA1_Msk /*!< User data 1 */ +#define FLASH_DATA1_nDATA1_Pos (24U) +#define FLASH_DATA1_nDATA1_Msk (0xFFU << FLASH_DATA1_nDATA1_Pos) /*!< 0xFF000000 */ +#define FLASH_DATA1_nDATA1 FLASH_DATA1_nDATA1_Msk /*!< Inverse code of user data 1 */ + +/****************** Bit definition for FLASH_EPP0 register ******************/ +#define FLASH_EPP0_EPP0_Pos (0U) +#define FLASH_EPP0_EPP0_Msk (0xFFU << FLASH_EPP0_EPP0_Pos) /*!< 0x000000FF */ +#define FLASH_EPP0_EPP0 FLASH_EPP0_EPP0_Msk /*!< Flash erase/write protection byte 0 */ +#define FLASH_EPP0_nEPP0_Pos (8U) +#define FLASH_EPP0_nEPP0_Msk (0xFFU << FLASH_EPP0_nEPP0_Pos) /*!< 0x0000FF00 */ +#define FLASH_EPP0_nEPP0 FLASH_EPP0_nEPP0_Msk /*!< Inverse code of flash erase/write protection byte 0 */ + +/****************** Bit definition for FLASH_EPP1 register ******************/ +#define FLASH_EPP1_EPP1_Pos (16U) +#define FLASH_EPP1_EPP1_Msk (0xFFU << FLASH_EPP1_EPP1_Pos) /*!< 0x00FF0000 */ +#define FLASH_EPP1_EPP1 FLASH_EPP1_EPP1_Msk /*!< Flash erase/write protection byte 1 */ +#define FLASH_EPP1_nEPP1_Pos (24U) +#define FLASH_EPP1_nEPP1_Msk (0xFFU << FLASH_EPP1_nEPP1_Pos) /*!< 0xFF000000 */ +#define FLASH_EPP1_nEPP1 FLASH_EPP1_nEPP1_Msk /*!< Inverse code of flash erase/write protection byte 1 */ + +/****************** Bit definition for FLASH_EPP2 register ******************/ +#define FLASH_EPP2_EPP2_Pos (0U) +#define FLASH_EPP2_EPP2_Msk (0xFFU << FLASH_EPP2_EPP2_Pos) /*!< 0x000000FF */ +#define FLASH_EPP2_EPP2 FLASH_EPP2_EPP2_Msk /*!< Flash erase/write protection byte 2 */ +#define FLASH_EPP2_nEPP2_Pos (8U) +#define FLASH_EPP2_nEPP2_Msk (0xFFU << FLASH_EPP2_nEPP2_Pos) /*!< 0x0000FF00 */ +#define FLASH_EPP2_nEPP2 FLASH_EPP2_nEPP2_Msk /*!< Inverse code of flash erase/write protection byte 2 */ + +/****************** Bit definition for FLASH_EPP3 register ******************/ +#define FLASH_EPP3_EPP3_Pos (16U) +#define FLASH_EPP3_EPP3_Msk (0xFFU << FLASH_EPP3_EPP3_Pos) /*!< 0x00FF0000 */ +#define FLASH_EPP3_EPP3 FLASH_EPP3_EPP3_Msk /*!< Flash erase/write protection byte 3 */ +#define FLASH_EPP3_nEPP3_Pos (24U) +#define FLASH_EPP3_nEPP3_Msk (0xFFU << FLASH_EPP3_nEPP3_Pos) /*!< 0xFF000000 */ +#define FLASH_EPP3_nEPP3 FLASH_EPP3_nEPP3_Msk /*!< Inverse code of flash erase/write protection byte 3 */ + +/**************** Bit definition for FLASH_QSPIKEY0 register ****************/ +#define FLASH_QSPIKEY0_QSPIKEY0_Pos (0U) +#define FLASH_QSPIKEY0_QSPIKEY0_Msk (0xFFU << FLASH_QSPIKEY0_QSPIKEY0_Pos) /*!< 0x000000FF */ +#define FLASH_QSPIKEY0_QSPIKEY0 FLASH_QSPIKEY0_QSPIKEY0_Msk /*!< QSPI ciphertext access area encryption key byte 0 */ +#define FLASH_QSPIKEY0_nQSPIKEY0_Pos (8U) +#define FLASH_QSPIKEY0_nQSPIKEY0_Msk (0xFFU << FLASH_QSPIKEY0_nQSPIKEY0_Pos) /*!< 0x0000FF00 */ +#define FLASH_QSPIKEY0_nQSPIKEY0 FLASH_QSPIKEY0_nQSPIKEY0_Msk /*!< Inverse code of QSPI ciphertext access area encryption key byte 0 */ + +/**************** Bit definition for FLASH_QSPIKEY1 register ****************/ +#define FLASH_QSPIKEY1_QSPIKEY1_Pos (16U) +#define FLASH_QSPIKEY1_QSPIKEY1_Msk (0xFFU << FLASH_QSPIKEY1_QSPIKEY1_Pos) /*!< 0x00FF0000 */ +#define FLASH_QSPIKEY1_QSPIKEY1 FLASH_QSPIKEY1_QSPIKEY1_Msk /*!< QSPI ciphertext access area encryption key byte 1 */ +#define FLASH_QSPIKEY1_nQSPIKEY1_Pos (23U) +#define FLASH_QSPIKEY1_nQSPIKEY1_Msk (0xFFU << FLASH_QSPIKEY1_nQSPIKEY1_Pos) /*!< 0xFF000000 */ +#define FLASH_QSPIKEY1_nQSPIKEY1 FLASH_QSPIKEY1_nQSPIKEY1_Msk /*!< Inverse code of QSPI ciphertext access area encryption key byte 1 */ + +/**************** Bit definition for FLASH_QSPIKEY2 register ****************/ +#define FLASH_QSPIKEY2_QSPIKEY2_Pos (0U) +#define FLASH_QSPIKEY2_QSPIKEY2_Msk (0xFFU << FLASH_QSPIKEY2_QSPIKEY2_Pos) /*!< 0x000000FF */ +#define FLASH_QSPIKEY2_QSPIKEY2 FLASH_QSPIKEY2_QSPIKEY2_Msk /*!< QSPI ciphertext access area encryption key byte 2 */ +#define FLASH_QSPIKEY2_nQSPIKEY2_Pos (8U) +#define FLASH_QSPIKEY2_nQSPIKEY2_Msk (0xFFU << FLASH_QSPIKEY2_nQSPIKEY2_Pos) /*!< 0x0000FF00 */ +#define FLASH_QSPIKEY2_nQSPIKEY2 FLASH_QSPIKEY2_nQSPIKEY2_Msk /*!< Inverse code of QSPI ciphertext access area encryption key byte 2 */ + +/**************** Bit definition for FLASH_QSPIKEY3 register ****************/ +#define FLASH_QSPIKEY3_QSPIKEY3_Pos (16U) +#define FLASH_QSPIKEY3_QSPIKEY3_Msk (0xFFU << FLASH_QSPIKEY3_QSPIKEY3_Pos) /*!< 0x00FF0000 */ +#define FLASH_QSPIKEY3_QSPIKEY3 FLASH_QSPIKEY3_QSPIKEY3_Msk /*!< QSPI ciphertext access area encryption key byte 3 */ +#define FLASH_QSPIKEY3_nQSPIKEY3_Pos (23U) +#define FLASH_QSPIKEY3_nQSPIKEY3_Msk (0xFFU << FLASH_QSPIKEY3_nQSPIKEY3_Pos) /*!< 0xFF000000 */ +#define FLASH_QSPIKEY3_nQSPIKEY3 FLASH_QSPIKEY3_nQSPIKEY3_Msk /*!< Inverse code of QSPI ciphertext access area encryption key byte 3 */ + +/***************** Bit definition for FLASH_DATA2 register ******************/ +#define FLASH_DATA2_DATA2_Pos (0U) +#define FLASH_DATA2_DATA2_Msk (0xFFU << FLASH_DATA2_DATA2_Pos) /*!< 0x000000FF */ +#define FLASH_DATA2_DATA2 FLASH_DATA2_DATA2_Msk /*!< User data 2 */ +#define FLASH_DATA2_nDATA2_Pos (8U) +#define FLASH_DATA2_nDATA2_Msk (0xFFU << FLASH_DATA2_nDATA2_Pos) /*!< 0x0000FF00 */ +#define FLASH_DATA2_nDATA2 FLASH_DATA2_nDATA2_Msk /*!< Inverse code of user data 2 */ + +/***************** Bit definition for FLASH_DATA3 register ******************/ +#define FLASH_DATA3_DATA3_Pos (16U) +#define FLASH_DATA3_DATA3_Msk (0xFFU << FLASH_DATA3_DATA3_Pos) /*!< 0x00FF0000 */ +#define FLASH_DATA3_DATA3 FLASH_DATA3_DATA3_Msk /*!< User data 3 */ +#define FLASH_DATA3_nDATA3_Pos (24U) +#define FLASH_DATA3_nDATA3_Msk (0xFFU << FLASH_DATA3_nDATA3_Pos) /*!< 0xFF000000 */ +#define FLASH_DATA3_nDATA3 FLASH_DATA3_nDATA3_Msk /*!< Inverse code of user data 3 */ + +/***************** Bit definition for FLASH_DATA4 register ******************/ +#define FLASH_DATA4_DATA4_Pos (0U) +#define FLASH_DATA4_DATA4_Msk (0xFFU << FLASH_DATA4_DATA4_Pos) /*!< 0x000000FF */ +#define FLASH_DATA4_DATA4 FLASH_DATA4_DATA4_Msk /*!< User data 4 */ +#define FLASH_DATA4_nDATA4_Pos (8U) +#define FLASH_DATA4_nDATA4_Msk (0xFFU << FLASH_DATA4_nDATA4_Pos) /*!< 0x0000FF00 */ +#define FLASH_DATA4_nDATA4 FLASH_DATA4_nDATA4_Msk /*!< Inverse code of user data 4 */ + +/***************** Bit definition for FLASH_DATA5 register ******************/ +#define FLASH_DATA5_DATA5_Pos (16U) +#define FLASH_DATA5_DATA5_Msk (0xFFU << FLASH_DATA5_DATA5_Pos) /*!< 0x00FF0000 */ +#define FLASH_DATA5_DATA5 FLASH_DATA5_DATA5_Msk /*!< User data 5 */ +#define FLASH_DATA5_nDATA5_Pos (24U) +#define FLASH_DATA5_nDATA5_Msk (0xFFU << FLASH_DATA5_nDATA5_Pos) /*!< 0xFF000000 */ +#define FLASH_DATA5_nDATA5 FLASH_DATA5_nDATA5_Msk /*!< Inverse code of user data 5 */ + +/***************** Bit definition for FLASH_DATA6 register ******************/ +#define FLASH_DATA6_DATA6_Pos (0U) +#define FLASH_DATA6_DATA6_Msk (0xFFU << FLASH_DATA6_DATA6_Pos) /*!< 0x000000FF */ +#define FLASH_DATA6_DATA6 FLASH_DATA6_DATA6_Msk /*!< User data 6 */ +#define FLASH_DATA6_nDATA6_Pos (8U) +#define FLASH_DATA6_nDATA6_Msk (0xFFU << FLASH_DATA6_nDATA6_Pos) /*!< 0x0000FF00 */ +#define FLASH_DATA6_nDATA6 FLASH_DATA6_nDATA6_Msk /*!< Inverse code of user data 6 */ + +/***************** Bit definition for FLASH_DATA7 register ******************/ +#define FLASH_DATA7_DATA7_Pos (16U) +#define FLASH_DATA7_DATA7_Msk (0xFFU << FLASH_DATA7_DATA7_Pos) /*!< 0x00FF0000 */ +#define FLASH_DATA7_DATA7 FLASH_DATA7_DATA7_Msk /*!< User data 7 */ +#define FLASH_DATA7_nDATA7_Pos (24U) +#define FLASH_DATA7_nDATA7_Msk (0xFFU << FLASH_DATA7_nDATA7_Pos) /*!< 0xFF000000 */ +#define FLASH_DATA7_nDATA7 FLASH_DATA7_nDATA7_Msk /*!< Inverse code of user data 7 */ + +/*!< Noted: The FLASH_DATA go up to 219, it too long for added in here */ + +/******************************************************************************/ +/* */ +/* General-purpose I/Os (GPIO) & Multiplex function I/Os (IOMUX) */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for GPIO_CFGR register *******************/ +#define GPIO_CFGR_IOMC_Pos (0U) +#define GPIO_CFGR_IOMC_Msk (0xFFFFFFFFU << GPIO_CFGR_IOMC_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_CFGR_IOMC GPIO_CFGR_IOMC_Msk /*!< GPIO x mode configuration */ + +/*!< IOMC0 configuration */ +#define GPIO_CFGR_IOMC0_Pos (0U) +#define GPIO_CFGR_IOMC0_Msk (0x3U << GPIO_CFGR_IOMC0_Pos) /*!< 0x00000003 */ +#define GPIO_CFGR_IOMC0 GPIO_CFGR_IOMC0_Msk /*!< IOMC0[1:0] bits (GPIO x mode configuration, pin 0) */ +#define GPIO_CFGR_IOMC0_0 (0x1U << GPIO_CFGR_IOMC0_Pos) /*!< 0x00000001 */ +#define GPIO_CFGR_IOMC0_1 (0x2U << GPIO_CFGR_IOMC0_Pos) /*!< 0x00000002 */ + +/*!< IOMC1 configuration */ +#define GPIO_CFGR_IOMC1_Pos (2U) +#define GPIO_CFGR_IOMC1_Msk (0x3U << GPIO_CFGR_IOMC1_Pos) /*!< 0x0000000C */ +#define GPIO_CFGR_IOMC1 GPIO_CFGR_IOMC1_Msk /*!< IOMC1[1:0] bits (GPIO x mode configuration, pin 1) */ +#define GPIO_CFGR_IOMC1_0 (0x1U << GPIO_CFGR_IOMC1_Pos) /*!< 0x00000004 */ +#define GPIO_CFGR_IOMC1_1 (0x2U << GPIO_CFGR_IOMC1_Pos) /*!< 0x00000008 */ + +/*!< IOMC2 configuration */ +#define GPIO_CFGR_IOMC2_Pos (4U) +#define GPIO_CFGR_IOMC2_Msk (0x3U << GPIO_CFGR_IOMC2_Pos) /*!< 0x00000030 */ +#define GPIO_CFGR_IOMC2 GPIO_CFGR_IOMC2_Msk /*!< IOMC2[1:0] bits (GPIO x mode configuration, pin 2) */ +#define GPIO_CFGR_IOMC2_0 (0x1U << GPIO_CFGR_IOMC2_Pos) /*!< 0x00000010 */ +#define GPIO_CFGR_IOMC2_1 (0x2U << GPIO_CFGR_IOMC2_Pos) /*!< 0x00000020 */ + +/*!< IOMC3 configuration */ +#define GPIO_CFGR_IOMC3_Pos (6U) +#define GPIO_CFGR_IOMC3_Msk (0x3U << GPIO_CFGR_IOMC3_Pos) /*!< 0x000000C0 */ +#define GPIO_CFGR_IOMC3 GPIO_CFGR_IOMC3_Msk /*!< IOMC3[1:0] bits (GPIO x mode configuration, pin 3) */ +#define GPIO_CFGR_IOMC3_0 (0x1U << GPIO_CFGR_IOMC3_Pos) /*!< 0x00000040 */ +#define GPIO_CFGR_IOMC3_1 (0x2U << GPIO_CFGR_IOMC3_Pos) /*!< 0x00000080 */ + +/*!< IOMC4 configuration */ +#define GPIO_CFGR_IOMC4_Pos (8U) +#define GPIO_CFGR_IOMC4_Msk (0x3U << GPIO_CFGR_IOMC4_Pos) /*!< 0x00000300 */ +#define GPIO_CFGR_IOMC4 GPIO_CFGR_IOMC4_Msk /*!< IOMC4[1:0] bits (GPIO x mode configuration, pin 4) */ +#define GPIO_CFGR_IOMC4_0 (0x1U << GPIO_CFGR_IOMC4_Pos) /*!< 0x00000100 */ +#define GPIO_CFGR_IOMC4_1 (0x2U << GPIO_CFGR_IOMC4_Pos) /*!< 0x00000200 */ + +/*!< IOMC5 configuration */ +#define GPIO_CFGR_IOMC5_Pos (10U) +#define GPIO_CFGR_IOMC5_Msk (0x3U << GPIO_CFGR_IOMC5_Pos) /*!< 0x00000C00 */ +#define GPIO_CFGR_IOMC5 GPIO_CFGR_IOMC5_Msk /*!< IOMC5[1:0] bits (GPIO x mode configuration, pin 5) */ +#define GPIO_CFGR_IOMC5_0 (0x1U << GPIO_CFGR_IOMC5_Pos) /*!< 0x00000400 */ +#define GPIO_CFGR_IOMC5_1 (0x2U << GPIO_CFGR_IOMC5_Pos) /*!< 0x00000800 */ + +/*!< IOMC6 configuration */ +#define GPIO_CFGR_IOMC6_Pos (12U) +#define GPIO_CFGR_IOMC6_Msk (0x3U << GPIO_CFGR_IOMC6_Pos) /*!< 0x00003000 */ +#define GPIO_CFGR_IOMC6 GPIO_CFGR_IOMC6_Msk /*!< IOMC6[1:0] bits (GPIO x mode configuration, pin 6) */ +#define GPIO_CFGR_IOMC6_0 (0x1U << GPIO_CFGR_IOMC6_Pos) /*!< 0x00001000 */ +#define GPIO_CFGR_IOMC6_1 (0x2U << GPIO_CFGR_IOMC6_Pos) /*!< 0x00002000 */ + +/*!< IOMC7 configuration */ +#define GPIO_CFGR_IOMC7_Pos (14U) +#define GPIO_CFGR_IOMC7_Msk (0x3U << GPIO_CFGR_IOMC7_Pos) /*!< 0x0000C000 */ +#define GPIO_CFGR_IOMC7 GPIO_CFGR_IOMC7_Msk /*!< IOMC7[1:0] bits (GPIO x mode configuration, pin 7) */ +#define GPIO_CFGR_IOMC7_0 (0x1U << GPIO_CFGR_IOMC7_Pos) /*!< 0x00004000 */ +#define GPIO_CFGR_IOMC7_1 (0x2U << GPIO_CFGR_IOMC7_Pos) /*!< 0x00008000 */ + +/*!< IOMC8 configuration */ +#define GPIO_CFGR_IOMC8_Pos (16U) +#define GPIO_CFGR_IOMC8_Msk (0x3U << GPIO_CFGR_IOMC8_Pos) /*!< 0x00030000 */ +#define GPIO_CFGR_IOMC8 GPIO_CFGR_IOMC8_Msk /*!< IOMC8[1:0] bits (GPIO x mode configuration, pin 8) */ +#define GPIO_CFGR_IOMC8_0 (0x1U << GPIO_CFGR_IOMC8_Pos) /*!< 0x00010000 */ +#define GPIO_CFGR_IOMC8_1 (0x2U << GPIO_CFGR_IOMC8_Pos) /*!< 0x00020000 */ + +/*!< IOMC9 configuration */ +#define GPIO_CFGR_IOMC9_Pos (18U) +#define GPIO_CFGR_IOMC9_Msk (0x3U << GPIO_CFGR_IOMC9_Pos) /*!< 0x000C0000 */ +#define GPIO_CFGR_IOMC9 GPIO_CFGR_IOMC9_Msk /*!< IOMC9[1:0] bits (GPIO x mode configuration, pin 9) */ +#define GPIO_CFGR_IOMC9_0 (0x1U << GPIO_CFGR_IOMC9_Pos) /*!< 0x00040000 */ +#define GPIO_CFGR_IOMC9_1 (0x2U << GPIO_CFGR_IOMC9_Pos) /*!< 0x00080000 */ + +/*!< IOMC10 configuration */ +#define GPIO_CFGR_IOMC10_Pos (20U) +#define GPIO_CFGR_IOMC10_Msk (0x3U << GPIO_CFGR_IOMC10_Pos) /*!< 0x00300000 */ +#define GPIO_CFGR_IOMC10 GPIO_CFGR_IOMC10_Msk /*!< IOMC10[1:0] bits (GPIO x mode configuration, pin 10) */ +#define GPIO_CFGR_IOMC10_0 (0x1U << GPIO_CFGR_IOMC10_Pos) /*!< 0x00100000 */ +#define GPIO_CFGR_IOMC10_1 (0x2U << GPIO_CFGR_IOMC10_Pos) /*!< 0x00200000 */ + +/*!< IOMC11 configuration */ +#define GPIO_CFGR_IOMC11_Pos (22U) +#define GPIO_CFGR_IOMC11_Msk (0x3U << GPIO_CFGR_IOMC11_Pos) /*!< 0x00C00000 */ +#define GPIO_CFGR_IOMC11 GPIO_CFGR_IOMC11_Msk /*!< IOMC11[1:0] bits (GPIO x mode configuration, pin 11) */ +#define GPIO_CFGR_IOMC11_0 (0x1U << GPIO_CFGR_IOMC11_Pos) /*!< 0x00400000 */ +#define GPIO_CFGR_IOMC11_1 (0x2U << GPIO_CFGR_IOMC11_Pos) /*!< 0x00800000 */ + +/*!< IOMC12 configuration */ +#define GPIO_CFGR_IOMC12_Pos (24U) +#define GPIO_CFGR_IOMC12_Msk (0x3U << GPIO_CFGR_IOMC12_Pos) /*!< 0x03000000 */ +#define GPIO_CFGR_IOMC12 GPIO_CFGR_IOMC12_Msk /*!< IOMC12[1:0] bits (GPIO x mode configuration, pin 12) */ +#define GPIO_CFGR_IOMC12_0 (0x1U << GPIO_CFGR_IOMC12_Pos) /*!< 0x01000000 */ +#define GPIO_CFGR_IOMC12_1 (0x2U << GPIO_CFGR_IOMC12_Pos) /*!< 0x02000000 */ + +/*!< IOMC13 configuration */ +#define GPIO_CFGR_IOMC13_Pos (26U) +#define GPIO_CFGR_IOMC13_Msk (0x3U << GPIO_CFGR_IOMC13_Pos) /*!< 0x0C000000 */ +#define GPIO_CFGR_IOMC13 GPIO_CFGR_IOMC13_Msk /*!< IOMC13[1:0] bits (GPIO x mode configuration, pin 13) */ +#define GPIO_CFGR_IOMC13_0 (0x1U << GPIO_CFGR_IOMC13_Pos) /*!< 0x04000000 */ +#define GPIO_CFGR_IOMC13_1 (0x2U << GPIO_CFGR_IOMC13_Pos) /*!< 0x08000000 */ + +/*!< IOMC14 configuration */ +#define GPIO_CFGR_IOMC14_Pos (28U) +#define GPIO_CFGR_IOMC14_Msk (0x3U << GPIO_CFGR_IOMC14_Pos) /*!< 0x30000000 */ +#define GPIO_CFGR_IOMC14 GPIO_CFGR_IOMC14_Msk /*!< IOMC14[1:0] bits (GPIO x mode configuration, pin 14) */ +#define GPIO_CFGR_IOMC14_0 (0x1U << GPIO_CFGR_IOMC14_Pos) /*!< 0x10000000 */ +#define GPIO_CFGR_IOMC14_1 (0x2U << GPIO_CFGR_IOMC14_Pos) /*!< 0x20000000 */ + +/*!< IOMC15 configuration */ +#define GPIO_CFGR_IOMC15_Pos (30U) +#define GPIO_CFGR_IOMC15_Msk (0x3U << GPIO_CFGR_IOMC15_Pos) /*!< 0xC0000000 */ +#define GPIO_CFGR_IOMC15 GPIO_CFGR_IOMC15_Msk /*!< IOMC15[1:0] bits (GPIO x mode configuration, pin 15) */ +#define GPIO_CFGR_IOMC15_0 (0x1U << GPIO_CFGR_IOMC15_Pos) /*!< 0x40000000 */ +#define GPIO_CFGR_IOMC15_1 (0x2U << GPIO_CFGR_IOMC15_Pos) /*!< 0x80000000 */ + +/****************** Bit definition for GPIO_OMODE register ******************/ +#define GPIO_OMODE_OM0_Pos (0U) +#define GPIO_OMODE_OM0_Msk (0x1U << GPIO_OMODE_OM0_Pos) /*!< 0x00000001 */ +#define GPIO_OMODE_OM0 GPIO_OMODE_OM0_Msk /*!< GPIO x output mode configuration, pin 0 */ +#define GPIO_OMODE_OM1_Pos (1U) +#define GPIO_OMODE_OM1_Msk (0x3U << GPIO_OMODE_OM1_Pos) /*!< 0x00000002 */ +#define GPIO_OMODE_OM1 GPIO_OMODE_OM1_Msk /*!< GPIO x output mode configuration, pin 1 */ +#define GPIO_OMODE_OM2_Pos (2U) +#define GPIO_OMODE_OM2_Msk (0x3U << GPIO_OMODE_OM2_Pos) /*!< 0x00000004 */ +#define GPIO_OMODE_OM2 GPIO_OMODE_OM2_Msk /*!< GPIO x output mode configuration, pin 2 */ +#define GPIO_OMODE_OM3_Pos (3U) +#define GPIO_OMODE_OM3_Msk (0x3U << GPIO_OMODE_OM3_Pos) /*!< 0x00000008 */ +#define GPIO_OMODE_OM3 GPIO_OMODE_OM3_Msk /*!< GPIO x output mode configuration, pin 3 */ +#define GPIO_OMODE_OM4_Pos (4U) +#define GPIO_OMODE_OM4_Msk (0x3U << GPIO_OMODE_OM4_Pos) /*!< 0x00000010 */ +#define GPIO_OMODE_OM4 GPIO_OMODE_OM4_Msk /*!< GPIO x output mode configuration, pin 4 */ +#define GPIO_OMODE_OM5_Pos (5U) +#define GPIO_OMODE_OM5_Msk (0x3U << GPIO_OMODE_OM5_Pos) /*!< 0x00000020 */ +#define GPIO_OMODE_OM5 GPIO_OMODE_OM5_Msk /*!< GPIO x output mode configuration, pin 5 */ +#define GPIO_OMODE_OM6_Pos (6U) +#define GPIO_OMODE_OM6_Msk (0x3U << GPIO_OMODE_OM6_Pos) /*!< 0x00000040 */ +#define GPIO_OMODE_OM6 GPIO_OMODE_OM6_Msk /*!< GPIO x output mode configuration, pin 6 */ +#define GPIO_OMODE_OM7_Pos (7U) +#define GPIO_OMODE_OM7_Msk (0x3U << GPIO_OMODE_OM7_Pos) /*!< 0x00000080 */ +#define GPIO_OMODE_OM7 GPIO_OMODE_OM7_Msk /*!< GPIO x output mode configuration, pin 7 */ +#define GPIO_OMODE_OM8_Pos (8U) +#define GPIO_OMODE_OM8_Msk (0x1U << GPIO_OMODE_OM8_Pos) /*!< 0x00000100 */ +#define GPIO_OMODE_OM8 GPIO_OMODE_OM8_Msk /*!< GPIO x output mode configuration, pin 8 */ +#define GPIO_OMODE_OM9_Pos (9U) +#define GPIO_OMODE_OM9_Msk (0x1U << GPIO_OMODE_OM9_Pos) /*!< 0x00000200 */ +#define GPIO_OMODE_OM9 GPIO_OMODE_OM9_Msk /*!< GPIO x output mode configuration, pin 9 */ +#define GPIO_OMODE_OM10_Pos (10U) +#define GPIO_OMODE_OM10_Msk (0x1U << GPIO_OMODE_OM10_Pos) /*!< 0x00000400 */ +#define GPIO_OMODE_OM10 GPIO_OMODE_OM10_Msk /*!< GPIO x output mode configuration, pin 10 */ +#define GPIO_OMODE_OM11_Pos (11U) +#define GPIO_OMODE_OM11_Msk (0x1U << GPIO_OMODE_OM11_Pos) /*!< 0x00000800 */ +#define GPIO_OMODE_OM11 GPIO_OMODE_OM11_Msk /*!< GPIO x output mode configuration, pin 11 */ +#define GPIO_OMODE_OM12_Pos (12U) +#define GPIO_OMODE_OM12_Msk (0x1U << GPIO_OMODE_OM12_Pos) /*!< 0x00001000 */ +#define GPIO_OMODE_OM12 GPIO_OMODE_OM12_Msk /*!< GPIO x output mode configuration, pin 12 */ +#define GPIO_OMODE_OM13_Pos (13U) +#define GPIO_OMODE_OM13_Msk (0x1U << GPIO_OMODE_OM13_Pos) /*!< 0x00002000 */ +#define GPIO_OMODE_OM13 GPIO_OMODE_OM13_Msk /*!< GPIO x output mode configuration, pin 13 */ +#define GPIO_OMODE_OM14_Pos (14U) +#define GPIO_OMODE_OM14_Msk (0x1U << GPIO_OMODE_OM14_Pos) /*!< 0x00004000 */ +#define GPIO_OMODE_OM14 GPIO_OMODE_OM14_Msk /*!< GPIO x output mode configuration, pin 14 */ +#define GPIO_OMODE_OM15_Pos (15U) +#define GPIO_OMODE_OM15_Msk (0x1U << GPIO_OMODE_OM15_Pos) /*!< 0x00008000 */ +#define GPIO_OMODE_OM15 GPIO_OMODE_OM15_Msk /*!< GPIO x output mode configuration, pin 15 */ + +/*!<*************** Bit definition for GPIO_ODRVR register ******************/ +#define GPIO_ODRVR_ODRV_Pos (0U) +#define GPIO_ODRVR_ODRV_Msk (0xFFFFFFFFU << GPIO_ODRVR_ODRV_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_ODRVR_ODRV GPIO_ODRVR_ODRV_Msk /*!< GPIO x drive capability */ + +/*!< ODRV0 configuration */ +#define GPIO_ODRVR_ODRV0_Pos (0U) +#define GPIO_ODRVR_ODRV0_Msk (0x3U << GPIO_ODRVR_ODRV0_Pos) /*!< 0x00000003 */ +#define GPIO_ODRVR_ODRV0 GPIO_ODRVR_ODRV0_Msk /*!< ODRV0[1:0] bits (GPIO x drive capability, pin 0) */ +#define GPIO_ODRVR_ODRV0_0 (0x1U << GPIO_ODRVR_ODRV0_Pos) /*!< 0x00000001 */ +#define GPIO_ODRVR_ODRV0_1 (0x2U << GPIO_ODRVR_ODRV0_Pos) /*!< 0x00000002 */ + +/*!< ODRV1 configuration */ +#define GPIO_ODRVR_ODRV1_Pos (2U) +#define GPIO_ODRVR_ODRV1_Msk (0x3U << GPIO_ODRVR_ODRV1_Pos) /*!< 0x0000000C */ +#define GPIO_ODRVR_ODRV1 GPIO_ODRVR_ODRV1_Msk /*!< ODRV1[1:0] bits (GPIO x drive capability, pin 1) */ +#define GPIO_ODRVR_ODRV1_0 (0x1U << GPIO_ODRVR_ODRV1_Pos) /*!< 0x00000004 */ +#define GPIO_ODRVR_ODRV1_1 (0x2U << GPIO_ODRVR_ODRV1_Pos) /*!< 0x00000008 */ + +/*!< ODRV2 configuration */ +#define GPIO_ODRVR_ODRV2_Pos (4U) +#define GPIO_ODRVR_ODRV2_Msk (0x3U << GPIO_ODRVR_ODRV2_Pos) /*!< 0x00000030 */ +#define GPIO_ODRVR_ODRV2 GPIO_ODRVR_ODRV2_Msk /*!< ODRV2[1:0] bits (GPIO x drive capability, pin 2) */ +#define GPIO_ODRVR_ODRV2_0 (0x1U << GPIO_ODRVR_ODRV2_Pos) /*!< 0x00000010 */ +#define GPIO_ODRVR_ODRV2_1 (0x2U << GPIO_ODRVR_ODRV2_Pos) /*!< 0x00000020 */ + +/*!< ODRV3 configuration */ +#define GPIO_ODRVR_ODRV3_Pos (6U) +#define GPIO_ODRVR_ODRV3_Msk (0x3U << GPIO_ODRVR_ODRV3_Pos) /*!< 0x000000C0 */ +#define GPIO_ODRVR_ODRV3 GPIO_ODRVR_ODRV3_Msk /*!< ODRV3[1:0] bits (GPIO x drive capability, pin 3) */ +#define GPIO_ODRVR_ODRV3_0 (0x1U << GPIO_ODRVR_ODRV3_Pos) /*!< 0x00000040 */ +#define GPIO_ODRVR_ODRV3_1 (0x2U << GPIO_ODRVR_ODRV3_Pos) /*!< 0x00000080 */ + +/*!< ODRV4 configuration */ +#define GPIO_ODRVR_ODRV4_Pos (8U) +#define GPIO_ODRVR_ODRV4_Msk (0x3U << GPIO_ODRVR_ODRV4_Pos) /*!< 0x00000300 */ +#define GPIO_ODRVR_ODRV4 GPIO_ODRVR_ODRV4_Msk /*!< ODRV4[1:0] bits (GPIO x drive capability, pin 4) */ +#define GPIO_ODRVR_ODRV4_0 (0x1U << GPIO_ODRVR_ODRV4_Pos) /*!< 0x00000100 */ +#define GPIO_ODRVR_ODRV4_1 (0x2U << GPIO_ODRVR_ODRV4_Pos) /*!< 0x00000200 */ + +/*!< ODRV5 configuration */ +#define GPIO_ODRVR_ODRV5_Pos (10U) +#define GPIO_ODRVR_ODRV5_Msk (0x3U << GPIO_ODRVR_ODRV5_Pos) /*!< 0x00000C00 */ +#define GPIO_ODRVR_ODRV5 GPIO_ODRVR_ODRV5_Msk /*!< ODRV5[1:0] bits (GPIO x drive capability, pin 5) */ +#define GPIO_ODRVR_ODRV5_0 (0x1U << GPIO_ODRVR_ODRV5_Pos) /*!< 0x00000400 */ +#define GPIO_ODRVR_ODRV5_1 (0x2U << GPIO_ODRVR_ODRV5_Pos) /*!< 0x00000800 */ + +/*!< ODRV6 configuration */ +#define GPIO_ODRVR_ODRV6_Pos (12U) +#define GPIO_ODRVR_ODRV6_Msk (0x3U << GPIO_ODRVR_ODRV6_Pos) /*!< 0x00003000 */ +#define GPIO_ODRVR_ODRV6 GPIO_ODRVR_ODRV6_Msk /*!< ODRV6[1:0] bits (GPIO x drive capability, pin 6) */ +#define GPIO_ODRVR_ODRV6_0 (0x1U << GPIO_ODRVR_ODRV6_Pos) /*!< 0x00001000 */ +#define GPIO_ODRVR_ODRV6_1 (0x2U << GPIO_ODRVR_ODRV6_Pos) /*!< 0x00002000 */ + +/*!< ODRV7 configuration */ +#define GPIO_ODRVR_ODRV7_Pos (14U) +#define GPIO_ODRVR_ODRV7_Msk (0x3U << GPIO_ODRVR_ODRV7_Pos) /*!< 0x0000C000 */ +#define GPIO_ODRVR_ODRV7 GPIO_ODRVR_ODRV7_Msk /*!< ODRV7[1:0] bits (GPIO x drive capability, pin 7) */ +#define GPIO_ODRVR_ODRV7_0 (0x1U << GPIO_ODRVR_ODRV7_Pos) /*!< 0x00004000 */ +#define GPIO_ODRVR_ODRV7_1 (0x2U << GPIO_ODRVR_ODRV7_Pos) /*!< 0x00008000 */ + +/*!< ODRV8 configuration */ +#define GPIO_ODRVR_ODRV8_Pos (16U) +#define GPIO_ODRVR_ODRV8_Msk (0x3U << GPIO_ODRVR_ODRV8_Pos) /*!< 0x00030000 */ +#define GPIO_ODRVR_ODRV8 GPIO_ODRVR_ODRV8_Msk /*!< ODRV8[1:0] bits (GPIO x drive capability, pin 8) */ +#define GPIO_ODRVR_ODRV8_0 (0x1U << GPIO_ODRVR_ODRV8_Pos) /*!< 0x00010000 */ +#define GPIO_ODRVR_ODRV8_1 (0x2U << GPIO_ODRVR_ODRV8_Pos) /*!< 0x00020000 */ + +/*!< ODRV9 configuration */ +#define GPIO_ODRVR_ODRV9_Pos (18U) +#define GPIO_ODRVR_ODRV9_Msk (0x3U << GPIO_ODRVR_ODRV9_Pos) /*!< 0x000C0000 */ +#define GPIO_ODRVR_ODRV9 GPIO_ODRVR_ODRV9_Msk /*!< ODRV9[1:0] bits (GPIO x drive capability, pin 9) */ +#define GPIO_ODRVR_ODRV9_0 (0x1U << GPIO_ODRVR_ODRV9_Pos) /*!< 0x00040000 */ +#define GPIO_ODRVR_ODRV9_1 (0x2U << GPIO_ODRVR_ODRV9_Pos) /*!< 0x00080000 */ + +/*!< ODRV10 configuration */ +#define GPIO_ODRVR_ODRV10_Pos (20U) +#define GPIO_ODRVR_ODRV10_Msk (0x3U << GPIO_ODRVR_ODRV10_Pos) /*!< 0x00300000 */ +#define GPIO_ODRVR_ODRV10 GPIO_ODRVR_ODRV10_Msk /*!< ODRV10[1:0] bits (GPIO x drive capability, pin 10) */ +#define GPIO_ODRVR_ODRV10_0 (0x1U << GPIO_ODRVR_ODRV10_Pos) /*!< 0x00100000 */ +#define GPIO_ODRVR_ODRV10_1 (0x2U << GPIO_ODRVR_ODRV10_Pos) /*!< 0x00200000 */ + +/*!< ODRV11 configuration */ +#define GPIO_ODRVR_ODRV11_Pos (22U) +#define GPIO_ODRVR_ODRV11_Msk (0x3U << GPIO_ODRVR_ODRV11_Pos) /*!< 0x00C00000 */ +#define GPIO_ODRVR_ODRV11 GPIO_ODRVR_ODRV11_Msk /*!< ODRV11[1:0] bits (GPIO x drive capability, pin 11) */ +#define GPIO_ODRVR_ODRV11_0 (0x1U << GPIO_ODRVR_ODRV11_Pos) /*!< 0x00400000 */ +#define GPIO_ODRVR_ODRV11_1 (0x2U << GPIO_ODRVR_ODRV11_Pos) /*!< 0x00800000 */ + +/*!< ODRV12 configuration */ +#define GPIO_ODRVR_ODRV12_Pos (24U) +#define GPIO_ODRVR_ODRV12_Msk (0x3U << GPIO_ODRVR_ODRV12_Pos) /*!< 0x03000000 */ +#define GPIO_ODRVR_ODRV12 GPIO_ODRVR_ODRV12_Msk /*!< ODRV12[1:0] bits (GPIO x drive capability, pin 12) */ +#define GPIO_ODRVR_ODRV12_0 (0x1U << GPIO_ODRVR_ODRV12_Pos) /*!< 0x01000000 */ +#define GPIO_ODRVR_ODRV12_1 (0x2U << GPIO_ODRVR_ODRV12_Pos) /*!< 0x02000000 */ + +/*!< ODRV13 configuration */ +#define GPIO_ODRVR_ODRV13_Pos (26U) +#define GPIO_ODRVR_ODRV13_Msk (0x3U << GPIO_ODRVR_ODRV13_Pos) /*!< 0x0C000000 */ +#define GPIO_ODRVR_ODRV13 GPIO_ODRVR_ODRV13_Msk /*!< ODRV13[1:0] bits (GPIO x drive capability, pin 13) */ +#define GPIO_ODRVR_ODRV13_0 (0x1U << GPIO_ODRVR_ODRV13_Pos) /*!< 0x04000000 */ +#define GPIO_ODRVR_ODRV13_1 (0x2U << GPIO_ODRVR_ODRV13_Pos) /*!< 0x08000000 */ + +/*!< ODRV14 configuration */ +#define GPIO_ODRVR_ODRV14_Pos (28U) +#define GPIO_ODRVR_ODRV14_Msk (0x3U << GPIO_ODRVR_ODRV14_Pos) /*!< 0x30000000 */ +#define GPIO_ODRVR_ODRV14 GPIO_ODRVR_ODRV14_Msk /*!< ODRV14[1:0] bits (GPIO x drive capability, pin 14) */ +#define GPIO_ODRVR_ODRV14_0 (0x1U << GPIO_ODRVR_ODRV14_Pos) /*!< 0x10000000 */ +#define GPIO_ODRVR_ODRV14_1 (0x2U << GPIO_ODRVR_ODRV14_Pos) /*!< 0x20000000 */ + +/*!< ODRV15 configuration */ +#define GPIO_ODRVR_ODRV15_Pos (30U) +#define GPIO_ODRVR_ODRV15_Msk (0x3U << GPIO_ODRVR_ODRV15_Pos) /*!< 0xC0000000 */ +#define GPIO_ODRVR_ODRV15 GPIO_ODRVR_ODRV15_Msk /*!< ODRV15[1:0] bits (GPIO x drive capability, pin 15) */ +#define GPIO_ODRVR_ODRV15_0 (0x1U << GPIO_ODRVR_ODRV15_Pos) /*!< 0x40000000 */ +#define GPIO_ODRVR_ODRV15_1 (0x2U << GPIO_ODRVR_ODRV15_Pos) /*!< 0x80000000 */ + +/*!<*************** Bit definition for GPIO_PULL register *******************/ +#define GPIO_PULL_PULL_Pos (0U) +#define GPIO_PULL_PULL_Msk (0xFFFFFFFFU << GPIO_PULL_PULL_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_PULL_PULL GPIO_PULL_PULL_Msk /*!< GPIO x pull-up/pull-down configuration */ + +/*!< PULL0 configuration */ +#define GPIO_PULL_PULL0_Pos (0U) +#define GPIO_PULL_PULL0_Msk (0x3U << GPIO_PULL_PULL0_Pos) /*!< 0x00000003 */ +#define GPIO_PULL_PULL0 GPIO_PULL_PULL0_Msk /*!< PULL0[1:0] bits (GPIO x pull-up/pull-down configuration, pin 0) */ +#define GPIO_PULL_PULL0_0 (0x1U << GPIO_PULL_PULL0_Pos) /*!< 0x00000001 */ +#define GPIO_PULL_PULL0_1 (0x2U << GPIO_PULL_PULL0_Pos) /*!< 0x00000002 */ + +/*!< PULL1 configuration */ +#define GPIO_PULL_PULL1_Pos (2U) +#define GPIO_PULL_PULL1_Msk (0x3U << GPIO_PULL_PULL1_Pos) /*!< 0x0000000C */ +#define GPIO_PULL_PULL1 GPIO_PULL_PULL1_Msk /*!< PULL1[1:0] bits (GPIO x pull-up/pull-down configuration, pin 1) */ +#define GPIO_PULL_PULL1_0 (0x1U << GPIO_PULL_PULL1_Pos) /*!< 0x00000004 */ +#define GPIO_PULL_PULL1_1 (0x2U << GPIO_PULL_PULL1_Pos) /*!< 0x00000008 */ + +/*!< PULL2 configuration */ +#define GPIO_PULL_PULL2_Pos (4U) +#define GPIO_PULL_PULL2_Msk (0x3U << GPIO_PULL_PULL2_Pos) /*!< 0x00000030 */ +#define GPIO_PULL_PULL2 GPIO_PULL_PULL2_Msk /*!< PULL2[1:0] bits (GPIO x pull-up/pull-down configuration, pin 2) */ +#define GPIO_PULL_PULL2_0 (0x1U << GPIO_PULL_PULL2_Pos) /*!< 0x00000010 */ +#define GPIO_PULL_PULL2_1 (0x2U << GPIO_PULL_PULL2_Pos) /*!< 0x00000020 */ + +/*!< PULL3 configuration */ +#define GPIO_PULL_PULL3_Pos (6U) +#define GPIO_PULL_PULL3_Msk (0x3U << GPIO_PULL_PULL3_Pos) /*!< 0x000000C0 */ +#define GPIO_PULL_PULL3 GPIO_PULL_PULL3_Msk /*!< PULL3[1:0] bits (GPIO x pull-up/pull-down configuration, pin 3) */ +#define GPIO_PULL_PULL3_0 (0x1U << GPIO_PULL_PULL3_Pos) /*!< 0x00000040 */ +#define GPIO_PULL_PULL3_1 (0x2U << GPIO_PULL_PULL3_Pos) /*!< 0x00000080 */ + +/*!< PULL4 configuration */ +#define GPIO_PULL_PULL4_Pos (8U) +#define GPIO_PULL_PULL4_Msk (0x3U << GPIO_PULL_PULL4_Pos) /*!< 0x00000300 */ +#define GPIO_PULL_PULL4 GPIO_PULL_PULL4_Msk /*!< PULL4[1:0] bits (GPIO x pull-up/pull-down configuration, pin 4) */ +#define GPIO_PULL_PULL4_0 (0x1U << GPIO_PULL_PULL4_Pos) /*!< 0x00000100 */ +#define GPIO_PULL_PULL4_1 (0x2U << GPIO_PULL_PULL4_Pos) /*!< 0x00000200 */ + +/*!< PULL5 configuration */ +#define GPIO_PULL_PULL5_Pos (10U) +#define GPIO_PULL_PULL5_Msk (0x3U << GPIO_PULL_PULL5_Pos) /*!< 0x00000C00 */ +#define GPIO_PULL_PULL5 GPIO_PULL_PULL5_Msk /*!< PULL5[1:0] bits (GPIO x pull-up/pull-down configuration, pin 5) */ +#define GPIO_PULL_PULL5_0 (0x1U << GPIO_PULL_PULL5_Pos) /*!< 0x00000400 */ +#define GPIO_PULL_PULL5_1 (0x2U << GPIO_PULL_PULL5_Pos) /*!< 0x00000800 */ + +/*!< PULL6 configuration */ +#define GPIO_PULL_PULL6_Pos (12U) +#define GPIO_PULL_PULL6_Msk (0x3U << GPIO_PULL_PULL6_Pos) /*!< 0x00003000 */ +#define GPIO_PULL_PULL6 GPIO_PULL_PULL6_Msk /*!< PULL6[1:0] bits (GPIO x pull-up/pull-down configuration, pin 6) */ +#define GPIO_PULL_PULL6_0 (0x1U << GPIO_PULL_PULL6_Pos) /*!< 0x00001000 */ +#define GPIO_PULL_PULL6_1 (0x2U << GPIO_PULL_PULL6_Pos) /*!< 0x00002000 */ + +/*!< PULL7 configuration */ +#define GPIO_PULL_PULL7_Pos (14U) +#define GPIO_PULL_PULL7_Msk (0x3U << GPIO_PULL_PULL7_Pos) /*!< 0x0000C000 */ +#define GPIO_PULL_PULL7 GPIO_PULL_PULL7_Msk /*!< PULL7[1:0] bits (GPIO x pull-up/pull-down configuration, pin 7) */ +#define GPIO_PULL_PULL7_0 (0x1U << GPIO_PULL_PULL7_Pos) /*!< 0x00004000 */ +#define GPIO_PULL_PULL7_1 (0x2U << GPIO_PULL_PULL7_Pos) /*!< 0x00008000 */ + +/*!< PULL8 configuration */ +#define GPIO_PULL_PULL8_Pos (16U) +#define GPIO_PULL_PULL8_Msk (0x3U << GPIO_PULL_PULL8_Pos) /*!< 0x00030000 */ +#define GPIO_PULL_PULL8 GPIO_PULL_PULL8_Msk /*!< PULL8[1:0] bits (GPIO x pull-up/pull-down configuration, pin 8) */ +#define GPIO_PULL_PULL8_0 (0x1U << GPIO_PULL_PULL8_Pos) /*!< 0x00010000 */ +#define GPIO_PULL_PULL8_1 (0x2U << GPIO_PULL_PULL8_Pos) /*!< 0x00020000 */ + +/*!< PULL9 configuration */ +#define GPIO_PULL_PULL9_Pos (18U) +#define GPIO_PULL_PULL9_Msk (0x3U << GPIO_PULL_PULL9_Pos) /*!< 0x000C0000 */ +#define GPIO_PULL_PULL9 GPIO_PULL_PULL9_Msk /*!< PULL9[1:0] bits (GPIO x pull-up/pull-down configuration, pin 9) */ +#define GPIO_PULL_PULL9_0 (0x1U << GPIO_PULL_PULL9_Pos) /*!< 0x00040000 */ +#define GPIO_PULL_PULL9_1 (0x2U << GPIO_PULL_PULL9_Pos) /*!< 0x00080000 */ + +/*!< PULL10 configuration */ +#define GPIO_PULL_PULL10_Pos (20U) +#define GPIO_PULL_PULL10_Msk (0x3U << GPIO_PULL_PULL10_Pos) /*!< 0x00300000 */ +#define GPIO_PULL_PULL10 GPIO_PULL_PULL10_Msk /*!< PULL10[1:0] bits (GPIO x pull-up/pull-down configuration, pin 10) */ +#define GPIO_PULL_PULL10_0 (0x1U << GPIO_PULL_PULL10_Pos) /*!< 0x00100000 */ +#define GPIO_PULL_PULL10_1 (0x2U << GPIO_PULL_PULL10_Pos) /*!< 0x00200000 */ + +/*!< PULL11 configuration */ +#define GPIO_PULL_PULL11_Pos (22U) +#define GPIO_PULL_PULL11_Msk (0x3U << GPIO_PULL_PULL11_Pos) /*!< 0x00C00000 */ +#define GPIO_PULL_PULL11 GPIO_PULL_PULL11_Msk /*!< PULL11[1:0] bits (GPIO x pull-up/pull-down configuration, pin 11) */ +#define GPIO_PULL_PULL11_0 (0x1U << GPIO_PULL_PULL11_Pos) /*!< 0x00400000 */ +#define GPIO_PULL_PULL11_1 (0x2U << GPIO_PULL_PULL11_Pos) /*!< 0x00800000 */ + +/*!< PULL12 configuration */ +#define GPIO_PULL_PULL12_Pos (24U) +#define GPIO_PULL_PULL12_Msk (0x3U << GPIO_PULL_PULL12_Pos) /*!< 0x03000000 */ +#define GPIO_PULL_PULL12 GPIO_PULL_PULL12_Msk /*!< PULL12[1:0] bits (GPIO x pull-up/pull-down configuration, pin 12) */ +#define GPIO_PULL_PULL12_0 (0x1U << GPIO_PULL_PULL12_Pos) /*!< 0x01000000 */ +#define GPIO_PULL_PULL12_1 (0x2U << GPIO_PULL_PULL12_Pos) /*!< 0x02000000 */ + +/*!< PULL13 configuration */ +#define GPIO_PULL_PULL13_Pos (26U) +#define GPIO_PULL_PULL13_Msk (0x3U << GPIO_PULL_PULL13_Pos) /*!< 0x0C000000 */ +#define GPIO_PULL_PULL13 GPIO_PULL_PULL13_Msk /*!< PULL13[1:0] bits (GPIO x pull-up/pull-down configuration, pin 13) */ +#define GPIO_PULL_PULL13_0 (0x1U << GPIO_PULL_PULL13_Pos) /*!< 0x04000000 */ +#define GPIO_PULL_PULL13_1 (0x2U << GPIO_PULL_PULL13_Pos) /*!< 0x08000000 */ + +/*!< PULL14 configuration */ +#define GPIO_PULL_PULL14_Pos (28U) +#define GPIO_PULL_PULL14_Msk (0x3U << GPIO_PULL_PULL14_Pos) /*!< 0x30000000 */ +#define GPIO_PULL_PULL14 GPIO_PULL_PULL14_Msk /*!< PULL14[1:0] bits (GPIO x pull-up/pull-down configuration, pin 14) */ +#define GPIO_PULL_PULL14_0 (0x1U << GPIO_PULL_PULL14_Pos) /*!< 0x10000000 */ +#define GPIO_PULL_PULL14_1 (0x2U << GPIO_PULL_PULL14_Pos) /*!< 0x20000000 */ + +/*!< PULL15 configuration */ +#define GPIO_PULL_PULL15_Pos (30U) +#define GPIO_PULL_PULL15_Msk (0x3U << GPIO_PULL_PULL15_Pos) /*!< 0xC0000000 */ +#define GPIO_PULL_PULL15 GPIO_PULL_PULL15_Msk /*!< PULL15[1:0] bits (GPIO x pull-up/pull-down configuration, pin 15) */ +#define GPIO_PULL_PULL15_0 (0x1U << GPIO_PULL_PULL15_Pos) /*!< 0x40000000 */ +#define GPIO_PULL_PULL15_1 (0x2U << GPIO_PULL_PULL15_Pos) /*!< 0x80000000 */ + +/*!<**************** Bit definition for GPIO_IDT register *******************/ +#define GPIO_IDT_IDT0_Pos (0U) +#define GPIO_IDT_IDT0_Msk (0x1U << GPIO_IDT_IDT0_Pos) /*!< 0x00000001 */ +#define GPIO_IDT_IDT0 GPIO_IDT_IDT0_Msk /*!< GPIO x input data, pin 0 */ +#define GPIO_IDT_IDT1_Pos (1U) +#define GPIO_IDT_IDT1_Msk (0x1U << GPIO_IDT_IDT1_Pos) /*!< 0x00000002 */ +#define GPIO_IDT_IDT1 GPIO_IDT_IDT1_Msk /*!< GPIO x input data, pin 1 */ +#define GPIO_IDT_IDT2_Pos (2U) +#define GPIO_IDT_IDT2_Msk (0x1U << GPIO_IDT_IDT2_Pos) /*!< 0x00000004 */ +#define GPIO_IDT_IDT2 GPIO_IDT_IDT2_Msk /*!< GPIO x input data, pin 2 */ +#define GPIO_IDT_IDT3_Pos (3U) +#define GPIO_IDT_IDT3_Msk (0x1U << GPIO_IDT_IDT3_Pos) /*!< 0x00000008 */ +#define GPIO_IDT_IDT3 GPIO_IDT_IDT3_Msk /*!< GPIO x input data, pin 3 */ +#define GPIO_IDT_IDT4_Pos (4U) +#define GPIO_IDT_IDT4_Msk (0x1U << GPIO_IDT_IDT4_Pos) /*!< 0x00000010 */ +#define GPIO_IDT_IDT4 GPIO_IDT_IDT4_Msk /*!< GPIO x input data, pin 4 */ +#define GPIO_IDT_IDT5_Pos (5U) +#define GPIO_IDT_IDT5_Msk (0x1U << GPIO_IDT_IDT5_Pos) /*!< 0x00000020 */ +#define GPIO_IDT_IDT5 GPIO_IDT_IDT5_Msk /*!< GPIO x input data, pin 5 */ +#define GPIO_IDT_IDT6_Pos (6U) +#define GPIO_IDT_IDT6_Msk (0x1U << GPIO_IDT_IDT6_Pos) /*!< 0x00000040 */ +#define GPIO_IDT_IDT6 GPIO_IDT_IDT6_Msk /*!< GPIO x input data, pin 6 */ +#define GPIO_IDT_IDT7_Pos (7U) +#define GPIO_IDT_IDT7_Msk (0x1U << GPIO_IDT_IDT7_Pos) /*!< 0x00000080 */ +#define GPIO_IDT_IDT7 GPIO_IDT_IDT7_Msk /*!< GPIO x input data, pin 7 */ +#define GPIO_IDT_IDT8_Pos (8U) +#define GPIO_IDT_IDT8_Msk (0x1U << GPIO_IDT_IDT8_Pos) /*!< 0x00000100 */ +#define GPIO_IDT_IDT8 GPIO_IDT_IDT8_Msk /*!< GPIO x input data, pin 8 */ +#define GPIO_IDT_IDT9_Pos (9U) +#define GPIO_IDT_IDT9_Msk (0x1U << GPIO_IDT_IDT9_Pos) /*!< 0x00000200 */ +#define GPIO_IDT_IDT9 GPIO_IDT_IDT9_Msk /*!< GPIO x input data, pin 9 */ +#define GPIO_IDT_IDT10_Pos (10U) +#define GPIO_IDT_IDT10_Msk (0x1U << GPIO_IDT_IDT10_Pos) /*!< 0x00000400 */ +#define GPIO_IDT_IDT10 GPIO_IDT_IDT10_Msk /*!< GPIO x input data, pin 10 */ +#define GPIO_IDT_IDT11_Pos (11U) +#define GPIO_IDT_IDT11_Msk (0x1U << GPIO_IDT_IDT11_Pos) /*!< 0x00000800 */ +#define GPIO_IDT_IDT11 GPIO_IDT_IDT11_Msk /*!< GPIO x input data, pin 11 */ +#define GPIO_IDT_IDT12_Pos (12U) +#define GPIO_IDT_IDT12_Msk (0x1U << GPIO_IDT_IDT12_Pos) /*!< 0x00001000 */ +#define GPIO_IDT_IDT12 GPIO_IDT_IDT12_Msk /*!< GPIO x input data, pin 12 */ +#define GPIO_IDT_IDT13_Pos (13U) +#define GPIO_IDT_IDT13_Msk (0x1U << GPIO_IDT_IDT13_Pos) /*!< 0x00002000 */ +#define GPIO_IDT_IDT13 GPIO_IDT_IDT13_Msk /*!< GPIO x input data, pin 13 */ +#define GPIO_IDT_IDT14_Pos (14U) +#define GPIO_IDT_IDT14_Msk (0x1U << GPIO_IDT_IDT14_Pos) /*!< 0x00004000 */ +#define GPIO_IDT_IDT14 GPIO_IDT_IDT14_Msk /*!< GPIO x input data, pin 14 */ +#define GPIO_IDT_IDT15_Pos (15U) +#define GPIO_IDT_IDT15_Msk (0x1U << GPIO_IDT_IDT15_Pos) /*!< 0x00008000 */ +#define GPIO_IDT_IDT15 GPIO_IDT_IDT15_Msk /*!< GPIO x input data, pin 15 */ + +/******************* Bit definition for GPIO_ODT register *******************/ +#define GPIO_ODT_ODT0_Pos (0U) +#define GPIO_ODT_ODT0_Msk (0x1U << GPIO_ODT_ODT0_Pos) /*!< 0x00000001 */ +#define GPIO_ODT_ODT0 GPIO_ODT_ODT0_Msk /*!< GPIO x output data, pin 0 */ +#define GPIO_ODT_ODT1_Pos (1U) +#define GPIO_ODT_ODT1_Msk (0x1U << GPIO_ODT_ODT1_Pos) /*!< 0x00000002 */ +#define GPIO_ODT_ODT1 GPIO_ODT_ODT1_Msk /*!< GPIO x output data, pin 1 */ +#define GPIO_ODT_ODT2_Pos (2U) +#define GPIO_ODT_ODT2_Msk (0x1U << GPIO_ODT_ODT2_Pos) /*!< 0x00000004 */ +#define GPIO_ODT_ODT2 GPIO_ODT_ODT2_Msk /*!< GPIO x output data, pin 2 */ +#define GPIO_ODT_ODT3_Pos (3U) +#define GPIO_ODT_ODT3_Msk (0x1U << GPIO_ODT_ODT3_Pos) /*!< 0x00000008 */ +#define GPIO_ODT_ODT3 GPIO_ODT_ODT3_Msk /*!< GPIO x output data, pin 3 */ +#define GPIO_ODT_ODT4_Pos (4U) +#define GPIO_ODT_ODT4_Msk (0x1U << GPIO_ODT_ODT4_Pos) /*!< 0x00000010 */ +#define GPIO_ODT_ODT4 GPIO_ODT_ODT4_Msk /*!< GPIO x output data, pin 4 */ +#define GPIO_ODT_ODT5_Pos (5U) +#define GPIO_ODT_ODT5_Msk (0x1U << GPIO_ODT_ODT5_Pos) /*!< 0x00000020 */ +#define GPIO_ODT_ODT5 GPIO_ODT_ODT5_Msk /*!< GPIO x output data, pin 5 */ +#define GPIO_ODT_ODT6_Pos (6U) +#define GPIO_ODT_ODT6_Msk (0x1U << GPIO_ODT_ODT6_Pos) /*!< 0x00000040 */ +#define GPIO_ODT_ODT6 GPIO_ODT_ODT6_Msk /*!< GPIO x output data, pin 6 */ +#define GPIO_ODT_ODT7_Pos (7U) +#define GPIO_ODT_ODT7_Msk (0x1U << GPIO_ODT_ODT7_Pos) /*!< 0x00000080 */ +#define GPIO_ODT_ODT7 GPIO_ODT_ODT7_Msk /*!< GPIO x output data, pin 7 */ +#define GPIO_ODT_ODT8_Pos (8U) +#define GPIO_ODT_ODT8_Msk (0x1U << GPIO_ODT_ODT8_Pos) /*!< 0x00000100 */ +#define GPIO_ODT_ODT8 GPIO_ODT_ODT8_Msk /*!< GPIO x output data, pin 8 */ +#define GPIO_ODT_ODT9_Pos (9U) +#define GPIO_ODT_ODT9_Msk (0x1U << GPIO_ODT_ODT9_Pos) /*!< 0x00000200 */ +#define GPIO_ODT_ODT9 GPIO_ODT_ODT9_Msk /*!< GPIO x output data, pin 9 */ +#define GPIO_ODT_ODT10_Pos (10U) +#define GPIO_ODT_ODT10_Msk (0x1U << GPIO_ODT_ODT10_Pos) /*!< 0x00000400 */ +#define GPIO_ODT_ODT10 GPIO_ODT_ODT10_Msk /*!< GPIO x output data, pin 10 */ +#define GPIO_ODT_ODT11_Pos (11U) +#define GPIO_ODT_ODT11_Msk (0x1U << GPIO_ODT_ODT11_Pos) /*!< 0x00000800 */ +#define GPIO_ODT_ODT11 GPIO_ODT_ODT11_Msk /*!< GPIO x output data, pin 11 */ +#define GPIO_ODT_ODT12_Pos (12U) +#define GPIO_ODT_ODT12_Msk (0x1U << GPIO_ODT_ODT12_Pos) /*!< 0x00001000 */ +#define GPIO_ODT_ODT12 GPIO_ODT_ODT12_Msk /*!< GPIO x output data, pin 12 */ +#define GPIO_ODT_ODT13_Pos (13U) +#define GPIO_ODT_ODT13_Msk (0x1U << GPIO_ODT_ODT13_Pos) /*!< 0x00002000 */ +#define GPIO_ODT_ODT13 GPIO_ODT_ODT13_Msk /*!< GPIO x output data, pin 13 */ +#define GPIO_ODT_ODT14_Pos (14U) +#define GPIO_ODT_ODT14_Msk (0x1U << GPIO_ODT_ODT14_Pos) /*!< 0x00004000 */ +#define GPIO_ODT_ODT14 GPIO_ODT_ODT14_Msk /*!< GPIO x output data, pin 14 */ +#define GPIO_ODT_ODT15_Pos (15U) +#define GPIO_ODT_ODT15_Msk (0x1U << GPIO_ODT_ODT15_Pos) /*!< 0x00008000 */ +#define GPIO_ODT_ODT15 GPIO_ODT_ODT15_Msk /*!< GPIO x output data, pin 15 */ + +/******************* Bit definition for GPIO_SCR register *******************/ +#define GPIO_SCR_IOSB0_Pos (0U) +#define GPIO_SCR_IOSB0_Msk (0x1U << GPIO_SCR_IOSB0_Pos) /*!< 0x00000001 */ +#define GPIO_SCR_IOSB0 GPIO_SCR_IOSB0_Msk /*!< GPIO x set bit, pin 0 */ +#define GPIO_SCR_IOSB1_Pos (1U) +#define GPIO_SCR_IOSB1_Msk (0x1U << GPIO_SCR_IOSB1_Pos) /*!< 0x00000002 */ +#define GPIO_SCR_IOSB1 GPIO_SCR_IOSB1_Msk /*!< GPIO x set bit, pin 1 */ +#define GPIO_SCR_IOSB2_Pos (2U) +#define GPIO_SCR_IOSB2_Msk (0x1U << GPIO_SCR_IOSB2_Pos) /*!< 0x00000004 */ +#define GPIO_SCR_IOSB2 GPIO_SCR_IOSB2_Msk /*!< GPIO x set bit, pin 2 */ +#define GPIO_SCR_IOSB3_Pos (3U) +#define GPIO_SCR_IOSB3_Msk (0x1U << GPIO_SCR_IOSB3_Pos) /*!< 0x00000008 */ +#define GPIO_SCR_IOSB3 GPIO_SCR_IOSB3_Msk /*!< GPIO x set bit, pin 3 */ +#define GPIO_SCR_IOSB4_Pos (4U) +#define GPIO_SCR_IOSB4_Msk (0x1U << GPIO_SCR_IOSB4_Pos) /*!< 0x00000010 */ +#define GPIO_SCR_IOSB4 GPIO_SCR_IOSB4_Msk /*!< GPIO x set bit, pin 4 */ +#define GPIO_SCR_IOSB5_Pos (5U) +#define GPIO_SCR_IOSB5_Msk (0x1U << GPIO_SCR_IOSB5_Pos) /*!< 0x00000020 */ +#define GPIO_SCR_IOSB5 GPIO_SCR_IOSB5_Msk /*!< GPIO x set bit, pin 5 */ +#define GPIO_SCR_IOSB6_Pos (6U) +#define GPIO_SCR_IOSB6_Msk (0x1U << GPIO_SCR_IOSB6_Pos) /*!< 0x00000040 */ +#define GPIO_SCR_IOSB6 GPIO_SCR_IOSB6_Msk /*!< GPIO x set bit, pin 6 */ +#define GPIO_SCR_IOSB7_Pos (7U) +#define GPIO_SCR_IOSB7_Msk (0x1U << GPIO_SCR_IOSB7_Pos) /*!< 0x00000080 */ +#define GPIO_SCR_IOSB7 GPIO_SCR_IOSB7_Msk /*!< GPIO x set bit, pin 7 */ +#define GPIO_SCR_IOSB8_Pos (8U) +#define GPIO_SCR_IOSB8_Msk (0x1U << GPIO_SCR_IOSB8_Pos) /*!< 0x00000100 */ +#define GPIO_SCR_IOSB8 GPIO_SCR_IOSB8_Msk /*!< GPIO x set bit, pin 8 */ +#define GPIO_SCR_IOSB9_Pos (9U) +#define GPIO_SCR_IOSB9_Msk (0x1U << GPIO_SCR_IOSB9_Pos) /*!< 0x00000200 */ +#define GPIO_SCR_IOSB9 GPIO_SCR_IOSB9_Msk /*!< GPIO x set bit, pin 9 */ +#define GPIO_SCR_IOSB10_Pos (10U) +#define GPIO_SCR_IOSB10_Msk (0x1U << GPIO_SCR_IOSB10_Pos) /*!< 0x00000400 */ +#define GPIO_SCR_IOSB10 GPIO_SCR_IOSB10_Msk /*!< GPIO x set bit, pin 10 */ +#define GPIO_SCR_IOSB11_Pos (11U) +#define GPIO_SCR_IOSB11_Msk (0x1U << GPIO_SCR_IOSB11_Pos) /*!< 0x00000800 */ +#define GPIO_SCR_IOSB11 GPIO_SCR_IOSB11_Msk /*!< GPIO x set bit, pin 11 */ +#define GPIO_SCR_IOSB12_Pos (12U) +#define GPIO_SCR_IOSB12_Msk (0x1U << GPIO_SCR_IOSB12_Pos) /*!< 0x00001000 */ +#define GPIO_SCR_IOSB12 GPIO_SCR_IOSB12_Msk /*!< GPIO x set bit, pin 12 */ +#define GPIO_SCR_IOSB13_Pos (13U) +#define GPIO_SCR_IOSB13_Msk (0x1U << GPIO_SCR_IOSB13_Pos) /*!< 0x00002000 */ +#define GPIO_SCR_IOSB13 GPIO_SCR_IOSB13_Msk /*!< GPIO x set bit, pin 13 */ +#define GPIO_SCR_IOSB14_Pos (14U) +#define GPIO_SCR_IOSB14_Msk (0x1U << GPIO_SCR_IOSB14_Pos) /*!< 0x00004000 */ +#define GPIO_SCR_IOSB14 GPIO_SCR_IOSB14_Msk /*!< GPIO x set bit, pin 14 */ +#define GPIO_SCR_IOSB15_Pos (15U) +#define GPIO_SCR_IOSB15_Msk (0x1U << GPIO_SCR_IOSB15_Pos) /*!< 0x00008000 */ +#define GPIO_SCR_IOSB15 GPIO_SCR_IOSB15_Msk /*!< GPIO x set bit, pin 15 */ +#define GPIO_SCR_IOCB0_Pos (16U) +#define GPIO_SCR_IOCB0_Msk (0x1U << GPIO_SCR_IOCB0_Pos) /*!< 0x00010000 */ +#define GPIO_SCR_IOCB0 GPIO_SCR_IOCB0_Msk /*!< GPIO x clear bit, pin 0 */ +#define GPIO_SCR_IOCB1_Pos (17U) +#define GPIO_SCR_IOCB1_Msk (0x1U << GPIO_SCR_IOCB1_Pos) /*!< 0x00020000 */ +#define GPIO_SCR_IOCB1 GPIO_SCR_IOCB1_Msk /*!< GPIO x clear bit, pin 1 */ +#define GPIO_SCR_IOCB2_Pos (18U) +#define GPIO_SCR_IOCB2_Msk (0x1U << GPIO_SCR_IOCB2_Pos) /*!< 0x00040000 */ +#define GPIO_SCR_IOCB2 GPIO_SCR_IOCB2_Msk /*!< GPIO x clear bit, pin 2 */ +#define GPIO_SCR_IOCB3_Pos (19U) +#define GPIO_SCR_IOCB3_Msk (0x1U << GPIO_SCR_IOCB3_Pos) /*!< 0x00080000 */ +#define GPIO_SCR_IOCB3 GPIO_SCR_IOCB3_Msk /*!< GPIO x clear bit, pin 3 */ +#define GPIO_SCR_IOCB4_Pos (20U) +#define GPIO_SCR_IOCB4_Msk (0x1U << GPIO_SCR_IOCB4_Pos) /*!< 0x00100000 */ +#define GPIO_SCR_IOCB4 GPIO_SCR_IOCB4_Msk /*!< GPIO x clear bit, pin 4 */ +#define GPIO_SCR_IOCB5_Pos (21U) +#define GPIO_SCR_IOCB5_Msk (0x1U << GPIO_SCR_IOCB5_Pos) /*!< 0x00200000 */ +#define GPIO_SCR_IOCB5 GPIO_SCR_IOCB5_Msk /*!< GPIO x clear bit, pin 5 */ +#define GPIO_SCR_IOCB6_Pos (22U) +#define GPIO_SCR_IOCB6_Msk (0x1U << GPIO_SCR_IOCB6_Pos) /*!< 0x00400000 */ +#define GPIO_SCR_IOCB6 GPIO_SCR_IOCB6_Msk /*!< GPIO x clear bit, pin 6 */ +#define GPIO_SCR_IOCB7_Pos (23U) +#define GPIO_SCR_IOCB7_Msk (0x1U << GPIO_SCR_IOCB7_Pos) /*!< 0x00800000 */ +#define GPIO_SCR_IOCB7 GPIO_SCR_IOCB7_Msk /*!< GPIO x clear bit, pin 7 */ +#define GPIO_SCR_IOCB8_Pos (24U) +#define GPIO_SCR_IOCB8_Msk (0x1U << GPIO_SCR_IOCB8_Pos) /*!< 0x01000000 */ +#define GPIO_SCR_IOCB8 GPIO_SCR_IOCB8_Msk /*!< GPIO x clear bit, pin 8 */ +#define GPIO_SCR_IOCB9_Pos (25U) +#define GPIO_SCR_IOCB9_Msk (0x1U << GPIO_SCR_IOCB9_Pos) /*!< 0x02000000 */ +#define GPIO_SCR_IOCB9 GPIO_SCR_IOCB9_Msk /*!< GPIO x clear bit, pin 9 */ +#define GPIO_SCR_IOCB10_Pos (26U) +#define GPIO_SCR_IOCB10_Msk (0x1U << GPIO_SCR_IOCB10_Pos) /*!< 0x04000000 */ +#define GPIO_SCR_IOCB10 GPIO_SCR_IOCB10_Msk /*!< GPIO x clear bit, pin 10 */ +#define GPIO_SCR_IOCB11_Pos (27U) +#define GPIO_SCR_IOCB11_Msk (0x1U << GPIO_SCR_IOCB11_Pos) /*!< 0x08000000 */ +#define GPIO_SCR_IOCB11 GPIO_SCR_IOCB11_Msk /*!< GPIO x clear bit, pin 11 */ +#define GPIO_SCR_IOCB12_Pos (28U) +#define GPIO_SCR_IOCB12_Msk (0x1U << GPIO_SCR_IOCB12_Pos) /*!< 0x10000000 */ +#define GPIO_SCR_IOCB12 GPIO_SCR_IOCB12_Msk /*!< GPIO x clear bit, pin 12 */ +#define GPIO_SCR_IOCB13_Pos (29U) +#define GPIO_SCR_IOCB13_Msk (0x1U << GPIO_SCR_IOCB13_Pos) /*!< 0x20000000 */ +#define GPIO_SCR_IOCB13 GPIO_SCR_IOCB13_Msk /*!< GPIO x clear bit, pin 13 */ +#define GPIO_SCR_IOCB14_Pos (30U) +#define GPIO_SCR_IOCB14_Msk (0x1U << GPIO_SCR_IOCB14_Pos) /*!< 0x40000000 */ +#define GPIO_SCR_IOCB14 GPIO_SCR_IOCB14_Msk /*!< GPIO x clear bit, pin 14 */ +#define GPIO_SCR_IOCB15_Pos (31U) +#define GPIO_SCR_IOCB15_Msk (0x1U << GPIO_SCR_IOCB15_Pos) /*!< 0x80000000 */ +#define GPIO_SCR_IOCB15 GPIO_SCR_IOCB15_Msk /*!< GPIO x clear bit, pin 15 */ + +/******************* Bit definition for GPIO_WPR register *******************/ +#define GPIO_WPR_WPEN0_Pos (0U) +#define GPIO_WPR_WPEN0_Msk (0x1U << GPIO_WPR_WPEN0_Pos) /*!< 0x00000001 */ +#define GPIO_WPR_WPEN0 GPIO_WPR_WPEN0_Msk /*!< Write protect enable, pin 0 */ +#define GPIO_WPR_WPEN1_Pos (1U) +#define GPIO_WPR_WPEN1_Msk (0x1U << GPIO_WPR_WPEN1_Pos) /*!< 0x00000002 */ +#define GPIO_WPR_WPEN1 GPIO_WPR_WPEN1_Msk /*!< Write protect enable, pin 1 */ +#define GPIO_WPR_WPEN2_Pos (2U) +#define GPIO_WPR_WPEN2_Msk (0x1U << GPIO_WPR_WPEN2_Pos) /*!< 0x00000004 */ +#define GPIO_WPR_WPEN2 GPIO_WPR_WPEN2_Msk /*!< Write protect enable, pin 2 */ +#define GPIO_WPR_WPEN3_Pos (3U) +#define GPIO_WPR_WPEN3_Msk (0x1U << GPIO_WPR_WPEN3_Pos) /*!< 0x00000008 */ +#define GPIO_WPR_WPEN3 GPIO_WPR_WPEN3_Msk /*!< Write protect enable, pin 3 */ +#define GPIO_WPR_WPEN4_Pos (4U) +#define GPIO_WPR_WPEN4_Msk (0x1U << GPIO_WPR_WPEN4_Pos) /*!< 0x00000010 */ +#define GPIO_WPR_WPEN4 GPIO_WPR_WPEN4_Msk /*!< Write protect enable, pin 4 */ +#define GPIO_WPR_WPEN5_Pos (5U) +#define GPIO_WPR_WPEN5_Msk (0x1U << GPIO_WPR_WPEN5_Pos) /*!< 0x00000020 */ +#define GPIO_WPR_WPEN5 GPIO_WPR_WPEN5_Msk /*!< Write protect enable, pin 5 */ +#define GPIO_WPR_WPEN6_Pos (6U) +#define GPIO_WPR_WPEN6_Msk (0x1U << GPIO_WPR_WPEN6_Pos) /*!< 0x00000040 */ +#define GPIO_WPR_WPEN6 GPIO_WPR_WPEN6_Msk /*!< Write protect enable, pin 6 */ +#define GPIO_WPR_WPEN7_Pos (7U) +#define GPIO_WPR_WPEN7_Msk (0x1U << GPIO_WPR_WPEN7_Pos) /*!< 0x00000080 */ +#define GPIO_WPR_WPEN7 GPIO_WPR_WPEN7_Msk /*!< Write protect enable, pin 7 */ +#define GPIO_WPR_WPEN8_Pos (8U) +#define GPIO_WPR_WPEN8_Msk (0x1U << GPIO_WPR_WPEN8_Pos) /*!< 0x00000100 */ +#define GPIO_WPR_WPEN8 GPIO_WPR_WPEN8_Msk /*!< Write protect enable, pin 8 */ +#define GPIO_WPR_WPEN9_Pos (9U) +#define GPIO_WPR_WPEN9_Msk (0x1U << GPIO_WPR_WPEN9_Pos) /*!< 0x00000200 */ +#define GPIO_WPR_WPEN9 GPIO_WPR_WPEN9_Msk /*!< Write protect enable, pin 9 */ +#define GPIO_WPR_WPEN10_Pos (10U) +#define GPIO_WPR_WPEN10_Msk (0x1U << GPIO_WPR_WPEN10_Pos) /*!< 0x00000400 */ +#define GPIO_WPR_WPEN10 GPIO_WPR_WPEN10_Msk /*!< Write protect enable, pin 10 */ +#define GPIO_WPR_WPEN11_Pos (11U) +#define GPIO_WPR_WPEN11_Msk (0x1U << GPIO_WPR_WPEN11_Pos) /*!< 0x00000800 */ +#define GPIO_WPR_WPEN11 GPIO_WPR_WPEN11_Msk /*!< Write protect enable, pin 11 */ +#define GPIO_WPR_WPEN12_Pos (12U) +#define GPIO_WPR_WPEN12_Msk (0x1U << GPIO_WPR_WPEN12_Pos) /*!< 0x00001000 */ +#define GPIO_WPR_WPEN12 GPIO_WPR_WPEN12_Msk /*!< Write protect enable, pin 12 */ +#define GPIO_WPR_WPEN13_Pos (13U) +#define GPIO_WPR_WPEN13_Msk (0x1U << GPIO_WPR_WPEN13_Pos) /*!< 0x00002000 */ +#define GPIO_WPR_WPEN13 GPIO_WPR_WPEN13_Msk /*!< Write protect enable, pin 13 */ +#define GPIO_WPR_WPEN14_Pos (14U) +#define GPIO_WPR_WPEN14_Msk (0x1U << GPIO_WPR_WPEN14_Pos) /*!< 0x00004000 */ +#define GPIO_WPR_WPEN14 GPIO_WPR_WPEN14_Msk /*!< Write protect enable, pin 14 */ +#define GPIO_WPR_WPEN15_Pos (15U) +#define GPIO_WPR_WPEN15_Msk (0x1U << GPIO_WPR_WPEN15_Pos) /*!< 0x00008000 */ +#define GPIO_WPR_WPEN15 GPIO_WPR_WPEN15_Msk /*!< Write protect enable, pin 15 */ +#define GPIO_WPR_WPSEQ_Pos (16U) +#define GPIO_WPR_WPSEQ_Msk (0x1U << GPIO_WPR_WPSEQ_Pos) /*!< 0x00010000 */ +#define GPIO_WPR_WPSEQ GPIO_WPR_WPSEQ_Msk /*!< Write protect sequence */ + +/****************** Bit definition for GPIO_MUXL register *******************/ +#define GPIO_MUXL_MUXL_Pos (0U) +#define GPIO_MUXL_MUXL_Msk (0xFFFFFFFFU << GPIO_MUXL_MUXL_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_MUXL_MUXL GPIO_MUXL_MUXL_Msk /*!< Multiplexed function select for GPIO x */ + +/*!< MUXL0 configuration */ +#define GPIO_MUXL_MUXL0_Pos (0U) +#define GPIO_MUXL_MUXL0_Msk (0xFU << GPIO_MUXL_MUXL0_Pos) /*!< 0x0000000F */ +#define GPIO_MUXL_MUXL0 GPIO_MUXL_MUXL0_Msk /*!< MUXL0[3:0] bits (Multiplexed function select for GPIO x, pin 0) */ +#define GPIO_MUXL_MUXL0_0 (0x1U << GPIO_MUXL_MUXL0_Pos) /*!< 0x00000001 */ +#define GPIO_MUXL_MUXL0_1 (0x2U << GPIO_MUXL_MUXL0_Pos) /*!< 0x00000002 */ +#define GPIO_MUXL_MUXL0_2 (0x4U << GPIO_MUXL_MUXL0_Pos) /*!< 0x00000004 */ +#define GPIO_MUXL_MUXL0_3 (0x8U << GPIO_MUXL_MUXL0_Pos) /*!< 0x00000008 */ + +/*!< MUXL1 configuration */ +#define GPIO_MUXL_MUXL1_Pos (4U) +#define GPIO_MUXL_MUXL1_Msk (0xFU << GPIO_MUXL_MUXL1_Pos) /*!< 0x000000F0 */ +#define GPIO_MUXL_MUXL1 GPIO_MUXL_MUXL1_Msk /*!< MUXL1[3:0] bits (Multiplexed function select for GPIO x, pin 1) */ +#define GPIO_MUXL_MUXL1_0 (0x1U << GPIO_MUXL_MUXL1_Pos) /*!< 0x00000010 */ +#define GPIO_MUXL_MUXL1_1 (0x2U << GPIO_MUXL_MUXL1_Pos) /*!< 0x00000020 */ +#define GPIO_MUXL_MUXL1_2 (0x4U << GPIO_MUXL_MUXL1_Pos) /*!< 0x00000040 */ +#define GPIO_MUXL_MUXL1_3 (0x8U << GPIO_MUXL_MUXL1_Pos) /*!< 0x00000080 */ + +/*!< MUXL2 configuration */ +#define GPIO_MUXL_MUXL2_Pos (8U) +#define GPIO_MUXL_MUXL2_Msk (0xFU << GPIO_MUXL_MUXL2_Pos) /*!< 0x00000F00 */ +#define GPIO_MUXL_MUXL2 GPIO_MUXL_MUXL2_Msk /*!< MUXL2[3:0] bits (Multiplexed function select for GPIO x, pin 2) */ +#define GPIO_MUXL_MUXL2_0 (0x1U << GPIO_MUXL_MUXL2_Pos) /*!< 0x00000100 */ +#define GPIO_MUXL_MUXL2_1 (0x2U << GPIO_MUXL_MUXL2_Pos) /*!< 0x00000200 */ +#define GPIO_MUXL_MUXL2_2 (0x4U << GPIO_MUXL_MUXL2_Pos) /*!< 0x00000400 */ +#define GPIO_MUXL_MUXL2_3 (0x8U << GPIO_MUXL_MUXL2_Pos) /*!< 0x00000800 */ + +/*!< MUXL3 configuration */ +#define GPIO_MUXL_MUXL3_Pos (12U) +#define GPIO_MUXL_MUXL3_Msk (0xFU << GPIO_MUXL_MUXL3_Pos) /*!< 0x0000F000 */ +#define GPIO_MUXL_MUXL3 GPIO_MUXL_MUXL3_Msk /*!< MUXL3[3:0] bits (Multiplexed function select for GPIO x, pin 3) */ +#define GPIO_MUXL_MUXL3_0 (0x1U << GPIO_MUXL_MUXL3_Pos) /*!< 0x00001000 */ +#define GPIO_MUXL_MUXL3_1 (0x2U << GPIO_MUXL_MUXL3_Pos) /*!< 0x00002000 */ +#define GPIO_MUXL_MUXL3_2 (0x4U << GPIO_MUXL_MUXL3_Pos) /*!< 0x00004000 */ +#define GPIO_MUXL_MUXL3_3 (0x8U << GPIO_MUXL_MUXL3_Pos) /*!< 0x00008000 */ + +/*!< MUXL4 configuration */ +#define GPIO_MUXL_MUXL4_Pos (16U) +#define GPIO_MUXL_MUXL4_Msk (0xFU << GPIO_MUXL_MUXL4_Pos) /*!< 0x000F0000 */ +#define GPIO_MUXL_MUXL4 GPIO_MUXL_MUXL4_Msk /*!< MUXL4[3:0] bits (Multiplexed function select for GPIO x, pin 4) */ +#define GPIO_MUXL_MUXL4_0 (0x1U << GPIO_MUXL_MUXL4_Pos) /*!< 0x00010000 */ +#define GPIO_MUXL_MUXL4_1 (0x2U << GPIO_MUXL_MUXL4_Pos) /*!< 0x00020000 */ +#define GPIO_MUXL_MUXL4_2 (0x4U << GPIO_MUXL_MUXL4_Pos) /*!< 0x00040000 */ +#define GPIO_MUXL_MUXL4_3 (0x8U << GPIO_MUXL_MUXL4_Pos) /*!< 0x00080000 */ + +/*!< MUXL5 configuration */ +#define GPIO_MUXL_MUXL5_Pos (20U) +#define GPIO_MUXL_MUXL5_Msk (0xFU << GPIO_MUXL_MUXL5_Pos) /*!< 0x00F00000 */ +#define GPIO_MUXL_MUXL5 GPIO_MUXL_MUXL5_Msk /*!< MUXL5[3:0] bits (Multiplexed function select for GPIO x, pin 5) */ +#define GPIO_MUXL_MUXL5_0 (0x1U << GPIO_MUXL_MUXL5_Pos) /*!< 0x00100000 */ +#define GPIO_MUXL_MUXL5_1 (0x2U << GPIO_MUXL_MUXL5_Pos) /*!< 0x00200000 */ +#define GPIO_MUXL_MUXL5_2 (0x4U << GPIO_MUXL_MUXL5_Pos) /*!< 0x00400000 */ +#define GPIO_MUXL_MUXL5_3 (0x8U << GPIO_MUXL_MUXL5_Pos) /*!< 0x00800000 */ + +/*!< MUXL6 configuration */ +#define GPIO_MUXL_MUXL6_Pos (24U) +#define GPIO_MUXL_MUXL6_Msk (0xFU << GPIO_MUXL_MUXL6_Pos) /*!< 0x0F000000 */ +#define GPIO_MUXL_MUXL6 GPIO_MUXL_MUXL6_Msk /*!< MUXL6[3:0] bits (Multiplexed function select for GPIO x, pin 6) */ +#define GPIO_MUXL_MUXL6_0 (0x1U << GPIO_MUXL_MUXL6_Pos) /*!< 0x01000000 */ +#define GPIO_MUXL_MUXL6_1 (0x2U << GPIO_MUXL_MUXL6_Pos) /*!< 0x02000000 */ +#define GPIO_MUXL_MUXL6_2 (0x4U << GPIO_MUXL_MUXL6_Pos) /*!< 0x04000000 */ +#define GPIO_MUXL_MUXL6_3 (0x8U << GPIO_MUXL_MUXL6_Pos) /*!< 0x08000000 */ + +/*!< MUXL7 configuration */ +#define GPIO_MUXL_MUXL7_Pos (28U) +#define GPIO_MUXL_MUXL7_Msk (0xFU << GPIO_MUXL_MUXL7_Pos) /*!< 0xF0000000 */ +#define GPIO_MUXL_MUXL7 GPIO_MUXL_MUXL7_Msk /*!< MUXL7[3:0] bits (Multiplexed function select for GPIO x, pin 7) */ +#define GPIO_MUXL_MUXL7_0 (0x1U << GPIO_MUXL_MUXL7_Pos) /*!< 0x10000000 */ +#define GPIO_MUXL_MUXL7_1 (0x2U << GPIO_MUXL_MUXL7_Pos) /*!< 0x20000000 */ +#define GPIO_MUXL_MUXL7_2 (0x4U << GPIO_MUXL_MUXL7_Pos) /*!< 0x40000000 */ +#define GPIO_MUXL_MUXL7_3 (0x8U << GPIO_MUXL_MUXL7_Pos) /*!< 0x80000000 */ + +/****************** Bit definition for GPIO_MUXH register *******************/ +#define GPIO_MUXH_MUXH_Pos (0U) +#define GPIO_MUXH_MUXH_Msk (0xFFFFFFFFU << GPIO_MUXH_MUXH_Pos) /*!< 0xFFFFFFFF */ +#define GPIO_MUXH_MUXH GPIO_MUXH_MUXH_Msk /*!< Multiplexed function select for GPIO x */ + +/*!< MUXH8 configuration */ +#define GPIO_MUXH_MUXH8_Pos (0U) +#define GPIO_MUXH_MUXH8_Msk (0xFU << GPIO_MUXH_MUXH8_Pos) /*!< 0x0000000F */ +#define GPIO_MUXH_MUXH8 GPIO_MUXH_MUXH8_Msk /*!< MUXH8[3:0] bits (Multiplexed function select for GPIO x, pin 8) */ +#define GPIO_MUXH_MUXH8_0 (0x1U << GPIO_MUXH_MUXH8_Pos) /*!< 0x00000001 */ +#define GPIO_MUXH_MUXH8_1 (0x2U << GPIO_MUXH_MUXH8_Pos) /*!< 0x00000002 */ +#define GPIO_MUXH_MUXH8_2 (0x4U << GPIO_MUXH_MUXH8_Pos) /*!< 0x00000004 */ +#define GPIO_MUXH_MUXH8_3 (0x8U << GPIO_MUXH_MUXH8_Pos) /*!< 0x00000008 */ + +/*!< MUXH9 configuration */ +#define GPIO_MUXH_MUXH9_Pos (4U) +#define GPIO_MUXH_MUXH9_Msk (0xFU << GPIO_MUXH_MUXH9_Pos) /*!< 0x000000F0 */ +#define GPIO_MUXH_MUXH9 GPIO_MUXH_MUXH9_Msk /*!< MUXH9[3:0] bits (Multiplexed function select for GPIO x, pin 9) */ +#define GPIO_MUXH_MUXH9_0 (0x1U << GPIO_MUXH_MUXH9_Pos) /*!< 0x00000010 */ +#define GPIO_MUXH_MUXH9_1 (0x2U << GPIO_MUXH_MUXH9_Pos) /*!< 0x00000020 */ +#define GPIO_MUXH_MUXH9_2 (0x4U << GPIO_MUXH_MUXH9_Pos) /*!< 0x00000040 */ +#define GPIO_MUXH_MUXH9_3 (0x8U << GPIO_MUXH_MUXH9_Pos) /*!< 0x00000080 */ + +/*!< MUXH10 configuration */ +#define GPIO_MUXH_MUXH10_Pos (8U) +#define GPIO_MUXH_MUXH10_Msk (0xFU << GPIO_MUXH_MUXH10_Pos) /*!< 0x00000F00 */ +#define GPIO_MUXH_MUXH10 GPIO_MUXH_MUXH10_Msk /*!< MUXH10[3:0] bits (Multiplexed function select for GPIO x, pin 10) */ +#define GPIO_MUXH_MUXH10_0 (0x1U << GPIO_MUXH_MUXH10_Pos) /*!< 0x00000100 */ +#define GPIO_MUXH_MUXH10_1 (0x2U << GPIO_MUXH_MUXH10_Pos) /*!< 0x00000200 */ +#define GPIO_MUXH_MUXH10_2 (0x4U << GPIO_MUXH_MUXH10_Pos) /*!< 0x00000400 */ +#define GPIO_MUXH_MUXH10_3 (0x8U << GPIO_MUXH_MUXH10_Pos) /*!< 0x00000800 */ + +/*!< MUXH11 configuration */ +#define GPIO_MUXH_MUXH11_Pos (12U) +#define GPIO_MUXH_MUXH11_Msk (0xFU << GPIO_MUXH_MUXH11_Pos) /*!< 0x0000F000 */ +#define GPIO_MUXH_MUXH11 GPIO_MUXH_MUXH11_Msk /*!< MUXH11[3:0] bits (Multiplexed function select for GPIO x, pin 11) */ +#define GPIO_MUXH_MUXH11_0 (0x1U << GPIO_MUXH_MUXH11_Pos) /*!< 0x00001000 */ +#define GPIO_MUXH_MUXH11_1 (0x2U << GPIO_MUXH_MUXH11_Pos) /*!< 0x00002000 */ +#define GPIO_MUXH_MUXH11_2 (0x4U << GPIO_MUXH_MUXH11_Pos) /*!< 0x00004000 */ +#define GPIO_MUXH_MUXH11_3 (0x8U << GPIO_MUXH_MUXH11_Pos) /*!< 0x00008000 */ + +/*!< MUXH12 configuration */ +#define GPIO_MUXH_MUXH12_Pos (16U) +#define GPIO_MUXH_MUXH12_Msk (0xFU << GPIO_MUXH_MUXH12_Pos) /*!< 0x000F0000 */ +#define GPIO_MUXH_MUXH12 GPIO_MUXH_MUXH12_Msk /*!< MUXH12[3:0] bits (Multiplexed function select for GPIO x, pin 12) */ +#define GPIO_MUXH_MUXH12_0 (0x1U << GPIO_MUXH_MUXH12_Pos) /*!< 0x00010000 */ +#define GPIO_MUXH_MUXH12_1 (0x2U << GPIO_MUXH_MUXH12_Pos) /*!< 0x00020000 */ +#define GPIO_MUXH_MUXH12_2 (0x4U << GPIO_MUXH_MUXH12_Pos) /*!< 0x00040000 */ +#define GPIO_MUXH_MUXH12_3 (0x8U << GPIO_MUXH_MUXH12_Pos) /*!< 0x00080000 */ + +/*!< MUXH13 configuration */ +#define GPIO_MUXH_MUXH13_Pos (20U) +#define GPIO_MUXH_MUXH13_Msk (0xFU << GPIO_MUXH_MUXH13_Pos) /*!< 0x00F00000 */ +#define GPIO_MUXH_MUXH13 GPIO_MUXH_MUXH13_Msk /*!< MUXH13[3:0] bits (Multiplexed function select for GPIO x, pin 13) */ +#define GPIO_MUXH_MUXH13_0 (0x1U << GPIO_MUXH_MUXH13_Pos) /*!< 0x00100000 */ +#define GPIO_MUXH_MUXH13_1 (0x2U << GPIO_MUXH_MUXH13_Pos) /*!< 0x00200000 */ +#define GPIO_MUXH_MUXH13_2 (0x4U << GPIO_MUXH_MUXH13_Pos) /*!< 0x00400000 */ +#define GPIO_MUXH_MUXH13_3 (0x8U << GPIO_MUXH_MUXH13_Pos) /*!< 0x00800000 */ + +/*!< MUXH14 configuration */ +#define GPIO_MUXH_MUXH14_Pos (24U) +#define GPIO_MUXH_MUXH14_Msk (0xFU << GPIO_MUXH_MUXH14_Pos) /*!< 0x0F000000 */ +#define GPIO_MUXH_MUXH14 GPIO_MUXH_MUXH14_Msk /*!< MUXH14[3:0] bits (Multiplexed function select for GPIO x, pin 14) */ +#define GPIO_MUXH_MUXH14_0 (0x1U << GPIO_MUXH_MUXH14_Pos) /*!< 0x01000000 */ +#define GPIO_MUXH_MUXH14_1 (0x2U << GPIO_MUXH_MUXH14_Pos) /*!< 0x02000000 */ +#define GPIO_MUXH_MUXH14_2 (0x4U << GPIO_MUXH_MUXH14_Pos) /*!< 0x04000000 */ +#define GPIO_MUXH_MUXH14_3 (0x8U << GPIO_MUXH_MUXH14_Pos) /*!< 0x08000000 */ + +/*!< MUXH15 configuration */ +#define GPIO_MUXH_MUXH15_Pos (28U) +#define GPIO_MUXH_MUXH15_Msk (0xFU << GPIO_MUXH_MUXH15_Pos) /*!< 0xF0000000 */ +#define GPIO_MUXH_MUXH15 GPIO_MUXH_MUXH15_Msk /*!< MUXH15[3:0] bits (Multiplexed function select for GPIO x, pin 15) */ +#define GPIO_MUXH_MUXH15_0 (0x1U << GPIO_MUXH_MUXH15_Pos) /*!< 0x10000000 */ +#define GPIO_MUXH_MUXH15_1 (0x2U << GPIO_MUXH_MUXH15_Pos) /*!< 0x20000000 */ +#define GPIO_MUXH_MUXH15_2 (0x4U << GPIO_MUXH_MUXH15_Pos) /*!< 0x40000000 */ +#define GPIO_MUXH_MUXH15_3 (0x8U << GPIO_MUXH_MUXH15_Pos) /*!< 0x80000000 */ + +/******************* Bit definition for GPIO_CLR register *******************/ +#define GPIO_CLR_IOCB0_Pos (0U) +#define GPIO_CLR_IOCB0_Msk (0x1U << GPIO_CLR_IOCB0_Pos) /*!< 0x00000001 */ +#define GPIO_CLR_IOCB0 GPIO_CLR_IOCB0_Msk /*!< GPIO x clear bit, pin 0 */ +#define GPIO_CLR_IOCB1_Pos (1U) +#define GPIO_CLR_IOCB1_Msk (0x1U << GPIO_CLR_IOCB1_Pos) /*!< 0x00000002 */ +#define GPIO_CLR_IOCB1 GPIO_CLR_IOCB1_Msk /*!< GPIO x clear bit, pin 1 */ +#define GPIO_CLR_IOCB2_Pos (2U) +#define GPIO_CLR_IOCB2_Msk (0x1U << GPIO_CLR_IOCB2_Pos) /*!< 0x00000004 */ +#define GPIO_CLR_IOCB2 GPIO_CLR_IOCB2_Msk /*!< GPIO x clear bit, pin 2 */ +#define GPIO_CLR_IOCB3_Pos (3U) +#define GPIO_CLR_IOCB3_Msk (0x1U << GPIO_CLR_IOCB3_Pos) /*!< 0x00000008 */ +#define GPIO_CLR_IOCB3 GPIO_CLR_IOCB3_Msk /*!< GPIO x clear bit, pin 3 */ +#define GPIO_CLR_IOCB4_Pos (4U) +#define GPIO_CLR_IOCB4_Msk (0x1U << GPIO_CLR_IOCB4_Pos) /*!< 0x00000010 */ +#define GPIO_CLR_IOCB4 GPIO_CLR_IOCB4_Msk /*!< GPIO x clear bit, pin 4 */ +#define GPIO_CLR_IOCB5_Pos (5U) +#define GPIO_CLR_IOCB5_Msk (0x1U << GPIO_CLR_IOCB5_Pos) /*!< 0x00000020 */ +#define GPIO_CLR_IOCB5 GPIO_CLR_IOCB5_Msk /*!< GPIO x clear bit, pin 5 */ +#define GPIO_CLR_IOCB6_Pos (6U) +#define GPIO_CLR_IOCB6_Msk (0x1U << GPIO_CLR_IOCB6_Pos) /*!< 0x00000040 */ +#define GPIO_CLR_IOCB6 GPIO_CLR_IOCB6_Msk /*!< GPIO x clear bit, pin 6 */ +#define GPIO_CLR_IOCB7_Pos (7U) +#define GPIO_CLR_IOCB7_Msk (0x1U << GPIO_CLR_IOCB7_Pos) /*!< 0x00000080 */ +#define GPIO_CLR_IOCB7 GPIO_CLR_IOCB7_Msk /*!< GPIO x clear bit, pin 7 */ +#define GPIO_CLR_IOCB8_Pos (8U) +#define GPIO_CLR_IOCB8_Msk (0x1U << GPIO_CLR_IOCB8_Pos) /*!< 0x00000100 */ +#define GPIO_CLR_IOCB8 GPIO_CLR_IOCB8_Msk /*!< GPIO x clear bit, pin 8 */ +#define GPIO_CLR_IOCB9_Pos (9U) +#define GPIO_CLR_IOCB9_Msk (0x1U << GPIO_CLR_IOCB9_Pos) /*!< 0x00000200 */ +#define GPIO_CLR_IOCB9 GPIO_CLR_IOCB9_Msk /*!< GPIO x clear bit, pin 9 */ +#define GPIO_CLR_IOCB10_Pos (10U) +#define GPIO_CLR_IOCB10_Msk (0x1U << GPIO_CLR_IOCB10_Pos) /*!< 0x00000400 */ +#define GPIO_CLR_IOCB10 GPIO_CLR_IOCB10_Msk /*!< GPIO x clear bit, pin 10 */ +#define GPIO_CLR_IOCB11_Pos (11U) +#define GPIO_CLR_IOCB11_Msk (0x1U << GPIO_CLR_IOCB11_Pos) /*!< 0x00000800 */ +#define GPIO_CLR_IOCB11 GPIO_CLR_IOCB11_Msk /*!< GPIO x clear bit, pin 11 */ +#define GPIO_CLR_IOCB12_Pos (12U) +#define GPIO_CLR_IOCB12_Msk (0x1U << GPIO_CLR_IOCB12_Pos) /*!< 0x00001000 */ +#define GPIO_CLR_IOCB12 GPIO_CLR_IOCB12_Msk /*!< GPIO x clear bit, pin 12 */ +#define GPIO_CLR_IOCB13_Pos (13U) +#define GPIO_CLR_IOCB13_Msk (0x1U << GPIO_CLR_IOCB13_Pos) /*!< 0x00002000 */ +#define GPIO_CLR_IOCB13 GPIO_CLR_IOCB13_Msk /*!< GPIO x clear bit, pin 13 */ +#define GPIO_CLR_IOCB14_Pos (14U) +#define GPIO_CLR_IOCB14_Msk (0x1U << GPIO_CLR_IOCB14_Pos) /*!< 0x00004000 */ +#define GPIO_CLR_IOCB14 GPIO_CLR_IOCB14_Msk /*!< GPIO x clear bit, pin 14 */ +#define GPIO_CLR_IOCB15_Pos (15U) +#define GPIO_CLR_IOCB15_Msk (0x1U << GPIO_CLR_IOCB15_Pos) /*!< 0x00008000 */ +#define GPIO_CLR_IOCB15 GPIO_CLR_IOCB15_Msk /*!< GPIO x clear bit, pin 15 */ + +/****************** Bit definition for GPIO_TOGR register *******************/ +#define GPIO_TOGR_IOTB0_Pos (0U) +#define GPIO_TOGR_IOTB0_Msk (0x1U << GPIO_TOGR_IOTB0_Pos) /*!< 0x00000001 */ +#define GPIO_TOGR_IOTB0 GPIO_TOGR_IOTB0_Msk /*!< GPIO x toggle bit, pin 0 */ +#define GPIO_TOGR_IOTB1_Pos (1U) +#define GPIO_TOGR_IOTB1_Msk (0x1U << GPIO_TOGR_IOTB1_Pos) /*!< 0x00000002 */ +#define GPIO_TOGR_IOTB1 GPIO_TOGR_IOTB1_Msk /*!< GPIO x toggle bit, pin 1 */ +#define GPIO_TOGR_IOTB2_Pos (2U) +#define GPIO_TOGR_IOTB2_Msk (0x1U << GPIO_TOGR_IOTB2_Pos) /*!< 0x00000004 */ +#define GPIO_TOGR_IOTB2 GPIO_TOGR_IOTB2_Msk /*!< GPIO x toggle bit, pin 2 */ +#define GPIO_TOGR_IOTB3_Pos (3U) +#define GPIO_TOGR_IOTB3_Msk (0x1U << GPIO_TOGR_IOTB3_Pos) /*!< 0x00000008 */ +#define GPIO_TOGR_IOTB3 GPIO_TOGR_IOTB3_Msk /*!< GPIO x toggle bit, pin 3 */ +#define GPIO_TOGR_IOTB4_Pos (4U) +#define GPIO_TOGR_IOTB4_Msk (0x1U << GPIO_TOGR_IOTB4_Pos) /*!< 0x00000010 */ +#define GPIO_TOGR_IOTB4 GPIO_TOGR_IOTB4_Msk /*!< GPIO x toggle bit, pin 4 */ +#define GPIO_TOGR_IOTB5_Pos (5U) +#define GPIO_TOGR_IOTB5_Msk (0x1U << GPIO_TOGR_IOTB5_Pos) /*!< 0x00000020 */ +#define GPIO_TOGR_IOTB5 GPIO_TOGR_IOTB5_Msk /*!< GPIO x toggle bit, pin 5 */ +#define GPIO_TOGR_IOTB6_Pos (6U) +#define GPIO_TOGR_IOTB6_Msk (0x1U << GPIO_TOGR_IOTB6_Pos) /*!< 0x00000040 */ +#define GPIO_TOGR_IOTB6 GPIO_TOGR_IOTB6_Msk /*!< GPIO x toggle bit, pin 6 */ +#define GPIO_TOGR_IOTB7_Pos (7U) +#define GPIO_TOGR_IOTB7_Msk (0x1U << GPIO_TOGR_IOTB7_Pos) /*!< 0x00000080 */ +#define GPIO_TOGR_IOTB7 GPIO_TOGR_IOTB7_Msk /*!< GPIO x toggle bit, pin 7 */ +#define GPIO_TOGR_IOTB8_Pos (8U) +#define GPIO_TOGR_IOTB8_Msk (0x1U << GPIO_TOGR_IOTB8_Pos) /*!< 0x00000100 */ +#define GPIO_TOGR_IOTB8 GPIO_TOGR_IOTB8_Msk /*!< GPIO x toggle bit, pin 8 */ +#define GPIO_TOGR_IOTB9_Pos (9U) +#define GPIO_TOGR_IOTB9_Msk (0x1U << GPIO_TOGR_IOTB9_Pos) /*!< 0x00000200 */ +#define GPIO_TOGR_IOTB9 GPIO_TOGR_IOTB9_Msk /*!< GPIO x toggle bit, pin 9 */ +#define GPIO_TOGR_IOTB10_Pos (10U) +#define GPIO_TOGR_IOTB10_Msk (0x1U << GPIO_TOGR_IOTB10_Pos) /*!< 0x00000400 */ +#define GPIO_TOGR_IOTB10 GPIO_TOGR_IOTB10_Msk /*!< GPIO x toggle bit, pin 10 */ +#define GPIO_TOGR_IOTB11_Pos (11U) +#define GPIO_TOGR_IOTB11_Msk (0x1U << GPIO_TOGR_IOTB11_Pos) /*!< 0x00000800 */ +#define GPIO_TOGR_IOTB11 GPIO_TOGR_IOTB11_Msk /*!< GPIO x toggle bit, pin 11 */ +#define GPIO_TOGR_IOTB12_Pos (12U) +#define GPIO_TOGR_IOTB12_Msk (0x1U << GPIO_TOGR_IOTB12_Pos) /*!< 0x00001000 */ +#define GPIO_TOGR_IOTB12 GPIO_TOGR_IOTB12_Msk /*!< GPIO x toggle bit, pin 12 */ +#define GPIO_TOGR_IOTB13_Pos (13U) +#define GPIO_TOGR_IOTB13_Msk (0x1U << GPIO_TOGR_IOTB13_Pos) /*!< 0x00002000 */ +#define GPIO_TOGR_IOTB13 GPIO_TOGR_IOTB13_Msk /*!< GPIO x toggle bit, pin 13 */ +#define GPIO_TOGR_IOTB14_Pos (14U) +#define GPIO_TOGR_IOTB14_Msk (0x1U << GPIO_TOGR_IOTB14_Pos) /*!< 0x00004000 */ +#define GPIO_TOGR_IOTB14 GPIO_TOGR_IOTB14_Msk /*!< GPIO x toggle bit, pin 14 */ +#define GPIO_TOGR_IOTB15_Pos (15U) +#define GPIO_TOGR_IOTB15_Msk (0x1U << GPIO_TOGR_IOTB15_Pos) /*!< 0x00008000 */ +#define GPIO_TOGR_IOTB15 GPIO_TOGR_IOTB15_Msk /*!< GPIO x toggle bit, pin 15 */ + +/****************** Bit definition for GPIO_HDRV register *******************/ +#define GPIO_HDRV_HDRV0_Pos (0U) +#define GPIO_HDRV_HDRV0_Msk (0x1U << GPIO_HDRV_HDRV0_Pos) /*!< 0x00000001 */ +#define GPIO_HDRV_HDRV0 GPIO_HDRV_HDRV0_Msk /*!< GPIO x huge sourcing/sinking strength control, pin 0 */ +#define GPIO_HDRV_HDRV1_Pos (1U) +#define GPIO_HDRV_HDRV1_Msk (0x1U << GPIO_HDRV_HDRV1_Pos) /*!< 0x00000002 */ +#define GPIO_HDRV_HDRV1 GPIO_HDRV_HDRV1_Msk /*!< GPIO x huge sourcing/sinking strength control, pin 1 */ +#define GPIO_HDRV_HDRV2_Pos (2U) +#define GPIO_HDRV_HDRV2_Msk (0x1U << GPIO_HDRV_HDRV2_Pos) /*!< 0x00000004 */ +#define GPIO_HDRV_HDRV2 GPIO_HDRV_HDRV2_Msk /*!< GPIO x huge sourcing/sinking strength control, pin 2 */ +#define GPIO_HDRV_HDRV3_Pos (3U) +#define GPIO_HDRV_HDRV3_Msk (0x1U << GPIO_HDRV_HDRV3_Pos) /*!< 0x00000008 */ +#define GPIO_HDRV_HDRV3 GPIO_HDRV_HDRV3_Msk /*!< GPIO x huge sourcing/sinking strength control, pin 3 */ +#define GPIO_HDRV_HDRV4_Pos (4U) +#define GPIO_HDRV_HDRV4_Msk (0x1U << GPIO_HDRV_HDRV4_Pos) /*!< 0x00000010 */ +#define GPIO_HDRV_HDRV4 GPIO_HDRV_HDRV4_Msk /*!< GPIO x huge sourcing/sinking strength control, pin 4 */ +#define GPIO_HDRV_HDRV5_Pos (5U) +#define GPIO_HDRV_HDRV5_Msk (0x1U << GPIO_HDRV_HDRV5_Pos) /*!< 0x00000020 */ +#define GPIO_HDRV_HDRV5 GPIO_HDRV_HDRV5_Msk /*!< GPIO x huge sourcing/sinking strength control, pin 5 */ +#define GPIO_HDRV_HDRV6_Pos (6U) +#define GPIO_HDRV_HDRV6_Msk (0x1U << GPIO_HDRV_HDRV6_Pos) /*!< 0x00000040 */ +#define GPIO_HDRV_HDRV6 GPIO_HDRV_HDRV6_Msk /*!< GPIO x huge sourcing/sinking strength control, pin 6 */ +#define GPIO_HDRV_HDRV7_Pos (7U) +#define GPIO_HDRV_HDRV7_Msk (0x1U << GPIO_HDRV_HDRV7_Pos) /*!< 0x00000080 */ +#define GPIO_HDRV_HDRV7 GPIO_HDRV_HDRV7_Msk /*!< GPIO x huge sourcing/sinking strength control, pin 7 */ +#define GPIO_HDRV_HDRV8_Pos (8U) +#define GPIO_HDRV_HDRV8_Msk (0x1U << GPIO_HDRV_HDRV8_Pos) /*!< 0x00000100 */ +#define GPIO_HDRV_HDRV8 GPIO_HDRV_HDRV8_Msk /*!< GPIO x huge sourcing/sinking strength control, pin 8 */ +#define GPIO_HDRV_HDRV9_Pos (9U) +#define GPIO_HDRV_HDRV9_Msk (0x1U << GPIO_HDRV_HDRV9_Pos) /*!< 0x00000200 */ +#define GPIO_HDRV_HDRV9 GPIO_HDRV_HDRV9_Msk /*!< GPIO x huge sourcing/sinking strength control, pin 9 */ +#define GPIO_HDRV_HDRV10_Pos (10U) +#define GPIO_HDRV_HDRV10_Msk (0x1U << GPIO_HDRV_HDRV10_Pos) /*!< 0x00000400 */ +#define GPIO_HDRV_HDRV10 GPIO_HDRV_HDRV10_Msk /*!< GPIO x huge sourcing/sinking strength control, pin 10 */ +#define GPIO_HDRV_HDRV11_Pos (11U) +#define GPIO_HDRV_HDRV11_Msk (0x1U << GPIO_HDRV_HDRV11_Pos) /*!< 0x00000800 */ +#define GPIO_HDRV_HDRV11 GPIO_HDRV_HDRV11_Msk /*!< GPIO x huge sourcing/sinking strength control, pin 11 */ +#define GPIO_HDRV_HDRV12_Pos (12U) +#define GPIO_HDRV_HDRV12_Msk (0x1U << GPIO_HDRV_HDRV12_Pos) /*!< 0x00001000 */ +#define GPIO_HDRV_HDRV12 GPIO_HDRV_HDRV12_Msk /*!< GPIO x huge sourcing/sinking strength control, pin 12 */ +#define GPIO_HDRV_HDRV13_Pos (13U) +#define GPIO_HDRV_HDRV13_Msk (0x1U << GPIO_HDRV_HDRV13_Pos) /*!< 0x00002000 */ +#define GPIO_HDRV_HDRV13 GPIO_HDRV_HDRV13_Msk /*!< GPIO x huge sourcing/sinking strength control, pin 13 */ +#define GPIO_HDRV_HDRV14_Pos (14U) +#define GPIO_HDRV_HDRV14_Msk (0x1U << GPIO_HDRV_HDRV14_Pos) /*!< 0x00004000 */ +#define GPIO_HDRV_HDRV14 GPIO_HDRV_HDRV14_Msk /*!< GPIO x huge sourcing/sinking strength control, pin 14 */ +#define GPIO_HDRV_HDRV15_Pos (15U) +#define GPIO_HDRV_HDRV15_Msk (0x1U << GPIO_HDRV_HDRV15_Pos) /*!< 0x00008000 */ +#define GPIO_HDRV_HDRV15 GPIO_HDRV_HDRV15_Msk /*!< GPIO x huge sourcing/sinking strength control, pin 15 */ + +/****************** Bit definition for GPIO_SRCTR register ******************/ +#define GPIO_SRCTR_SRCTR0_Pos (0U) +#define GPIO_SRCTR_SRCTR0_Msk (0x1U << GPIO_SRCTR_SRCTR0_Pos) /*!< 0x00000001 */ +#define GPIO_SRCTR_SRCTR0 GPIO_SRCTR_SRCTR0_Msk /*!< GPIO x SRCTR, pin 0 */ +#define GPIO_SRCTR_SRCTR1_Pos (1U) +#define GPIO_SRCTR_SRCTR1_Msk (0x1U << GPIO_SRCTR_SRCTR1_Pos) /*!< 0x00000002 */ +#define GPIO_SRCTR_SRCTR1 GPIO_SRCTR_SRCTR1_Msk /*!< GPIO x SRCTR, pin 1 */ +#define GPIO_SRCTR_SRCTR2_Pos (2U) +#define GPIO_SRCTR_SRCTR2_Msk (0x1U << GPIO_SRCTR_SRCTR2_Pos) /*!< 0x00000004 */ +#define GPIO_SRCTR_SRCTR2 GPIO_SRCTR_SRCTR2_Msk /*!< GPIO x SRCTR, pin 2 */ +#define GPIO_SRCTR_SRCTR3_Pos (3U) +#define GPIO_SRCTR_SRCTR3_Msk (0x1U << GPIO_SRCTR_SRCTR3_Pos) /*!< 0x00000008 */ +#define GPIO_SRCTR_SRCTR3 GPIO_SRCTR_SRCTR3_Msk /*!< GPIO x SRCTR, pin 3 */ +#define GPIO_SRCTR_SRCTR4_Pos (4U) +#define GPIO_SRCTR_SRCTR4_Msk (0x1U << GPIO_SRCTR_SRCTR4_Pos) /*!< 0x00000010 */ +#define GPIO_SRCTR_SRCTR4 GPIO_SRCTR_SRCTR4_Msk /*!< GPIO x SRCTR, pin 4 */ +#define GPIO_SRCTR_SRCTR5_Pos (5U) +#define GPIO_SRCTR_SRCTR5_Msk (0x1U << GPIO_SRCTR_SRCTR5_Pos) /*!< 0x00000020 */ +#define GPIO_SRCTR_SRCTR5 GPIO_SRCTR_SRCTR5_Msk /*!< GPIO x SRCTR, pin 5 */ +#define GPIO_SRCTR_SRCTR6_Pos (6U) +#define GPIO_SRCTR_SRCTR6_Msk (0x1U << GPIO_SRCTR_SRCTR6_Pos) /*!< 0x00000040 */ +#define GPIO_SRCTR_SRCTR6 GPIO_SRCTR_SRCTR6_Msk /*!< GPIO x SRCTR, pin 6 */ +#define GPIO_SRCTR_SRCTR7_Pos (7U) +#define GPIO_SRCTR_SRCTR7_Msk (0x1U << GPIO_SRCTR_SRCTR7_Pos) /*!< 0x00000080 */ +#define GPIO_SRCTR_SRCTR7 GPIO_SRCTR_SRCTR7_Msk /*!< GPIO x SRCTR, pin 7 */ +#define GPIO_SRCTR_SRCTR8_Pos (8U) +#define GPIO_SRCTR_SRCTR8_Msk (0x1U << GPIO_SRCTR_SRCTR8_Pos) /*!< 0x00000100 */ +#define GPIO_SRCTR_SRCTR8 GPIO_SRCTR_SRCTR8_Msk /*!< GPIO x SRCTR, pin 8 */ +#define GPIO_SRCTR_SRCTR9_Pos (9U) +#define GPIO_SRCTR_SRCTR9_Msk (0x1U << GPIO_SRCTR_SRCTR9_Pos) /*!< 0x00000200 */ +#define GPIO_SRCTR_SRCTR9 GPIO_SRCTR_SRCTR9_Msk /*!< GPIO x SRCTR, pin 9 */ +#define GPIO_SRCTR_SRCTR10_Pos (10U) +#define GPIO_SRCTR_SRCTR10_Msk (0x1U << GPIO_SRCTR_SRCTR10_Pos) /*!< 0x00000400 */ +#define GPIO_SRCTR_SRCTR10 GPIO_SRCTR_SRCTR10_Msk /*!< GPIO x SRCTR, pin 10 */ +#define GPIO_SRCTR_SRCTR11_Pos (11U) +#define GPIO_SRCTR_SRCTR11_Msk (0x1U << GPIO_SRCTR_SRCTR11_Pos) /*!< 0x00000800 */ +#define GPIO_SRCTR_SRCTR11 GPIO_SRCTR_SRCTR11_Msk /*!< GPIO x SRCTR, pin 11 */ +#define GPIO_SRCTR_SRCTR12_Pos (12U) +#define GPIO_SRCTR_SRCTR12_Msk (0x1U << GPIO_SRCTR_SRCTR12_Pos) /*!< 0x00001000 */ +#define GPIO_SRCTR_SRCTR12 GPIO_SRCTR_SRCTR12_Msk /*!< GPIO x SRCTR, pin 12 */ +#define GPIO_SRCTR_SRCTR13_Pos (13U) +#define GPIO_SRCTR_SRCTR13_Msk (0x1U << GPIO_SRCTR_SRCTR13_Pos) /*!< 0x00002000 */ +#define GPIO_SRCTR_SRCTR13 GPIO_SRCTR_SRCTR13_Msk /*!< GPIO x SRCTR, pin 13 */ +#define GPIO_SRCTR_SRCTR14_Pos (14U) +#define GPIO_SRCTR_SRCTR14_Msk (0x1U << GPIO_SRCTR_SRCTR14_Pos) /*!< 0x00004000 */ +#define GPIO_SRCTR_SRCTR14 GPIO_SRCTR_SRCTR14_Msk /*!< GPIO x SRCTR, pin 14 */ +#define GPIO_SRCTR_SRCTR15_Pos (15U) +#define GPIO_SRCTR_SRCTR15_Msk (0x1U << GPIO_SRCTR_SRCTR15_Pos) /*!< 0x00008000 */ +#define GPIO_SRCTR_SRCTR15 GPIO_SRCTR_SRCTR15_Msk /*!< GPIO x SRCTR, pin 15 */ + +/******************************************************************************/ +/* */ +/* System configuration controller (SCFG) */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for SCFG_CFG1 register *******************/ +/*!< MEM_MAP_SEL configuration */ +#define SCFG_CFG1_MEM_MAP_SEL_Pos (0U) +#define SCFG_CFG1_MEM_MAP_SEL_Msk (0x3U << SCFG_CFG1_MEM_MAP_SEL_Pos) /*!< 0x00000003 */ +#define SCFG_CFG1_MEM_MAP_SEL SCFG_CFG1_MEM_MAP_SEL_Msk /*!< MEM_MAP_SEL[1:0] bits (Boot mode status bit) */ +#define SCFG_CFG1_MEM_MAP_SEL_0 (0x1U << SCFG_CFG1_MEM_MAP_SEL_Pos) /*!< 0x00000001 */ +#define SCFG_CFG1_MEM_MAP_SEL_1 (0x2U << SCFG_CFG1_MEM_MAP_SEL_Pos) /*!< 0x00000002 */ + +#define SCFG_CFG1_MEM_MAP_SEL_FLASHMEM 0x00000000U /*!< Boot from main flash memory */ +#define SCFG_CFG1_MEM_MAP_SEL_SYSMEM 0x00000001U /*!< Boot from system memory */ +#define SCFG_CFG1_MEM_MAP_SEL_INTSRAM 0x00000003U /*!< Boot from internal SRAM */ + +#define SCFG_CFG1_IR_POL_Pos (5U) +#define SCFG_CFG1_IR_POL_Msk (0x1U << SCFG_CFG1_IR_POL_Pos) /*!< 0x00000020 */ +#define SCFG_CFG1_IR_POL SCFG_CFG1_IR_POL_Msk /*!< Infrared output polarity selection */ + +/*!< IR_SRC_SEL configuration */ +#define SCFG_CFG1_IR_SRC_SEL_Pos (6U) +#define SCFG_CFG1_IR_SRC_SEL_Msk (0x3U << SCFG_CFG1_IR_SRC_SEL_Pos) /*!< 0x000000C0 */ +#define SCFG_CFG1_IR_SRC_SEL SCFG_CFG1_IR_SRC_SEL_Msk /*!< IR_SRC_SEL[1:0] bits (IR modulation envelope signal source selection) */ +#define SCFG_CFG1_IR_SRC_SEL_0 (0x1U << SCFG_CFG1_IR_SRC_SEL_Pos) /*!< 0x00000040 */ +#define SCFG_CFG1_IR_SRC_SEL_1 (0x2U << SCFG_CFG1_IR_SRC_SEL_Pos) /*!< 0x00000080 */ + +#define SCFG_CFG1_IR_SRC_SEL_TMR10 0x00000000U /*!< TMR10 */ +#define SCFG_CFG1_IR_SRC_SEL_USART1 0x00000040U /*!< USART1 */ +#define SCFG_CFG1_IR_SRC_SEL_USART2 0x00000080U /*!< USART2 */ + +/****************** Bit definition for SCFG_CFG2 register *******************/ +#define SCFG_CFG2_LOCKUP_LK_Pos (0U) +#define SCFG_CFG2_LOCKUP_LK_Msk (0x1U << SCFG_CFG2_LOCKUP_LK_Pos) /*!< 0x00000001 */ +#define SCFG_CFG2_LOCKUP_LK SCFG_CFG2_LOCKUP_LK_Msk /*!< Cortex-M4F lockup bit enable */ +#define SCFG_CFG2_SRAM_OPERR_LK_Pos (1U) +#define SCFG_CFG2_SRAM_OPERR_LK_Msk (0x1U << SCFG_CFG2_SRAM_OPERR_LK_Pos) /*!< 0x00000002 */ +#define SCFG_CFG2_SRAM_OPERR_LK SCFG_CFG2_SRAM_OPERR_LK_Msk /*!< SRAM odd parity error lock enable */ +#define SCFG_CFG2_PVM_LK_Pos (2U) +#define SCFG_CFG2_PVM_LK_Msk (0x1U << SCFG_CFG2_PVM_LK_Pos) /*!< 0x00000004 */ +#define SCFG_CFG2_PVM_LK SCFG_CFG2_PVM_LK_Msk /*!< PVM lock enable */ +#define SCFG_CFG2_SRAM_OPERR_STS_Pos (8U) +#define SCFG_CFG2_SRAM_OPERR_STS_Msk (0x1U << SCFG_CFG2_SRAM_OPERR_STS_Pos) /*!< 0x00000100 */ +#define SCFG_CFG2_SRAM_OPERR_STS SCFG_CFG2_SRAM_OPERR_STS_Msk /*!< SRAM odd parity error status */ + +/*!< I2S_FD configuration */ +#define SCFG_CFG2_I2S_FD_Pos (30U) +#define SCFG_CFG2_I2S_FD_Msk (0x3U << SCFG_CFG2_I2S_FD_Pos) /*!< 0xC0000000 */ +#define SCFG_CFG2_I2S_FD SCFG_CFG2_I2S_FD_Msk /*!< I2S_FD[1:0] bits (I2S full duplex configuration bit) */ +#define SCFG_CFG2_I2S_FD_0 (0x1U << SCFG_CFG2_I2S_FD_Pos) /*!< 0x40000000 */ +#define SCFG_CFG2_I2S_FD_1 (0x2U << SCFG_CFG2_I2S_FD_Pos) /*!< 0x80000000 */ + +#define SCFG_CFG2_I2S_FD_SPI_I2S 0x00000000U /*!< SPI / I2S1 ~ 3 operates separately */ +#define SCFG_CFG2_I2S_FD_I2S1_3_FD 0x40000000U /*!< I2S1 and I2S3 are configured as full-duplex mode */ +#define SCFG_CFG2_I2S_FD_I2S2_3_FD 0x80000000U /*!< I2S2 and I2S3 are configured as full-duplex mode */ +#define SCFG_CFG2_I2S_FD_I2S1_2_FD 0xC0000000U /*!< I2S1 and I2S2 are configured as full-duplex mode */ + +/***************** Bit definition for SCFG_EXINTC1 register *****************/ +/*!< EXINT0 configuration */ +#define SCFG_EXINTC1_EXINT0_Pos (0U) +#define SCFG_EXINTC1_EXINT0_Msk (0xFU << SCFG_EXINTC1_EXINT0_Pos) /*!< 0x0000000F */ +#define SCFG_EXINTC1_EXINT0 SCFG_EXINTC1_EXINT0_Msk /*!< EXINT0[3:0] bits (EXINT0 input source configuration) */ + +#define SCFG_EXINTC1_EXINT0_GPA 0x00000000U /*!< GPIOA pin 0 */ +#define SCFG_EXINTC1_EXINT0_GPB_Pos (0U) +#define SCFG_EXINTC1_EXINT0_GPB_Msk (0x1U << SCFG_EXINTC1_EXINT0_GPB_Pos) /*!< 0x00000001 */ +#define SCFG_EXINTC1_EXINT0_GPB SCFG_EXINTC1_EXINT0_GPB_Msk /*!< GPIOB pin 0 */ +#define SCFG_EXINTC1_EXINT0_GPC_Pos (1U) +#define SCFG_EXINTC1_EXINT0_GPC_Msk (0x1U << SCFG_EXINTC1_EXINT0_GPC_Pos) /*!< 0x00000002 */ +#define SCFG_EXINTC1_EXINT0_GPC SCFG_EXINTC1_EXINT0_GPC_Msk /*!< GPIOC pin 0 */ +#define SCFG_EXINTC1_EXINT0_GPD_Pos (0U) +#define SCFG_EXINTC1_EXINT0_GPD_Msk (0x3U << SCFG_EXINTC1_EXINT0_GPD_Pos) /*!< 0x00000003 */ +#define SCFG_EXINTC1_EXINT0_GPD SCFG_EXINTC1_EXINT0_GPD_Msk /*!< GPIOD pin 0 */ +#define SCFG_EXINTC1_EXINT0_GPF_Pos (2U) +#define SCFG_EXINTC1_EXINT0_GPF_Msk (0x1U << SCFG_EXINTC1_EXINT0_GPF_Pos) /*!< 0x00000004 */ +#define SCFG_EXINTC1_EXINT0_GPF SCFG_EXINTC1_EXINT0_GPF_Msk /*!< GPIOF pin 0 */ + +/*!< EXINT1 configuration */ +#define SCFG_EXINTC1_EXINT1_Pos (4U) +#define SCFG_EXINTC1_EXINT1_Msk (0xFU << SCFG_EXINTC1_EXINT1_Pos) /*!< 0x000000F0 */ +#define SCFG_EXINTC1_EXINT1 SCFG_EXINTC1_EXINT1_Msk /*!< EXINT1[3:0] bits (EXINT1 input source configuration) */ + +#define SCFG_EXINTC1_EXINT1_GPA 0x00000000U /*!< GPIOA pin 1 */ +#define SCFG_EXINTC1_EXINT1_GPB_Pos (4U) +#define SCFG_EXINTC1_EXINT1_GPB_Msk (0x1U << SCFG_EXINTC1_EXINT1_GPB_Pos) /*!< 0x00000010 */ +#define SCFG_EXINTC1_EXINT1_GPB SCFG_EXINTC1_EXINT1_GPB_Msk /*!< GPIOB pin 1 */ +#define SCFG_EXINTC1_EXINT1_GPC_Pos (5U) +#define SCFG_EXINTC1_EXINT1_GPC_Msk (0x1U << SCFG_EXINTC1_EXINT1_GPC_Pos) /*!< 0x00000020 */ +#define SCFG_EXINTC1_EXINT1_GPC SCFG_EXINTC1_EXINT1_GPC_Msk /*!< GPIOC pin 1 */ +#define SCFG_EXINTC1_EXINT1_GPD_Pos (4U) +#define SCFG_EXINTC1_EXINT1_GPD_Msk (0x3U << SCFG_EXINTC1_EXINT1_GPD_Pos) /*!< 0x00000030 */ +#define SCFG_EXINTC1_EXINT1_GPD SCFG_EXINTC1_EXINT1_GPD_Msk /*!< GPIOD pin 1 */ +#define SCFG_EXINTC1_EXINT1_GPF_Pos (6U) +#define SCFG_EXINTC1_EXINT1_GPF_Msk (0x1U << SCFG_EXINTC1_EXINT1_GPF_Pos) /*!< 0x00000040 */ +#define SCFG_EXINTC1_EXINT1_GPF SCFG_EXINTC1_EXINT1_GPF_Msk /*!< GPIOF pin 1 */ + +/*!< EXINT2 configuration */ +#define SCFG_EXINTC1_EXINT2_Pos (8U) +#define SCFG_EXINTC1_EXINT2_Msk (0xFU << SCFG_EXINTC1_EXINT2_Pos) /*!< 0x00000F00 */ +#define SCFG_EXINTC1_EXINT2 SCFG_EXINTC1_EXINT2_Msk /*!< EXINT2[3:0] bits (EXINT2 input source configuration) */ + +#define SCFG_EXINTC1_EXINT2_GPA 0x00000000U /*!< GPIOA pin 2 */ +#define SCFG_EXINTC1_EXINT2_GPB_Pos (8U) +#define SCFG_EXINTC1_EXINT2_GPB_Msk (0x1U << SCFG_EXINTC1_EXINT2_GPB_Pos) /*!< 0x00000100 */ +#define SCFG_EXINTC1_EXINT2_GPB SCFG_EXINTC1_EXINT2_GPB_Msk /*!< GPIOB pin 2 */ +#define SCFG_EXINTC1_EXINT2_GPC_Pos (9U) +#define SCFG_EXINTC1_EXINT2_GPC_Msk (0x1U << SCFG_EXINTC1_EXINT2_GPC_Pos) /*!< 0x00000200 */ +#define SCFG_EXINTC1_EXINT2_GPC SCFG_EXINTC1_EXINT2_GPC_Msk /*!< GPIOC pin 2 */ +#define SCFG_EXINTC1_EXINT2_GPD_Pos (8U) +#define SCFG_EXINTC1_EXINT2_GPD_Msk (0x3U << SCFG_EXINTC1_EXINT2_GPD_Pos) /*!< 0x00000300 */ +#define SCFG_EXINTC1_EXINT2_GPD SCFG_EXINTC1_EXINT2_GPD_Msk /*!< GPIOD pin 2 */ +#define SCFG_EXINTC1_EXINT2_GPF_Pos (10U) +#define SCFG_EXINTC1_EXINT2_GPF_Msk (0x1U << SCFG_EXINTC1_EXINT2_GPF_Pos) /*!< 0x00000400 */ +#define SCFG_EXINTC1_EXINT2_GPF SCFG_EXINTC1_EXINT2_GPF_Msk /*!< GPIOF pin 2 */ + +/*!< EXINT3 configuration */ +#define SCFG_EXINTC1_EXINT3_Pos (12U) +#define SCFG_EXINTC1_EXINT3_Msk (0xFU << SCFG_EXINTC1_EXINT3_Pos) /*!< 0x0000F000 */ +#define SCFG_EXINTC1_EXINT3 SCFG_EXINTC1_EXINT3_Msk /*!< EXINT3[3:0] bits (EXINT3 input source configuration) */ + +#define SCFG_EXINTC1_EXINT3_GPA 0x00000000U /*!< GPIOA pin 3 */ +#define SCFG_EXINTC1_EXINT3_GPB_Pos (12U) +#define SCFG_EXINTC1_EXINT3_GPB_Msk (0x1U << SCFG_EXINTC1_EXINT3_GPB_Pos) /*!< 0x00001000 */ +#define SCFG_EXINTC1_EXINT3_GPB SCFG_EXINTC1_EXINT3_GPB_Msk /*!< GPIOB pin 3 */ +#define SCFG_EXINTC1_EXINT3_GPC_Pos (13U) +#define SCFG_EXINTC1_EXINT3_GPC_Msk (0x1U << SCFG_EXINTC1_EXINT3_GPC_Pos) /*!< 0x00002000 */ +#define SCFG_EXINTC1_EXINT3_GPC SCFG_EXINTC1_EXINT3_GPC_Msk /*!< GPIOC pin 3 */ +#define SCFG_EXINTC1_EXINT3_GPD_Pos (12U) +#define SCFG_EXINTC1_EXINT3_GPD_Msk (0x3U << SCFG_EXINTC1_EXINT3_GPD_Pos) /*!< 0x00003000 */ +#define SCFG_EXINTC1_EXINT3_GPD SCFG_EXINTC1_EXINT3_GPD_Msk /*!< GPIOD pin 3 */ +#define SCFG_EXINTC1_EXINT3_GPF_Pos (14U) +#define SCFG_EXINTC1_EXINT3_GPF_Msk (0x1U << SCFG_EXINTC1_EXINT3_GPF_Pos) /*!< 0x00004000 */ +#define SCFG_EXINTC1_EXINT3_GPF SCFG_EXINTC1_EXINT3_GPF_Msk /*!< GPIOF pin 3 */ + +/***************** Bit definition for SCFG_EXINTC2 register *****************/ +/*!< EXINT4 configuration */ +#define SCFG_EXINTC2_EXINT4_Pos (0U) +#define SCFG_EXINTC2_EXINT4_Msk (0xFU << SCFG_EXINTC2_EXINT4_Pos) /*!< 0x0000000F */ +#define SCFG_EXINTC2_EXINT4 SCFG_EXINTC2_EXINT4_Msk /*!< EXINT4[3:0] bits (EXINT4 input source configuration) */ + +#define SCFG_EXINTC2_EXINT4_GPA 0x00000000U /*!< GPIOA pin 4 */ +#define SCFG_EXINTC2_EXINT4_GPB_Pos (0U) +#define SCFG_EXINTC2_EXINT4_GPB_Msk (0x1U << SCFG_EXINTC2_EXINT4_GPB_Pos) /*!< 0x00000001 */ +#define SCFG_EXINTC2_EXINT4_GPB SCFG_EXINTC2_EXINT4_GPB_Msk /*!< GPIOB pin 4 */ +#define SCFG_EXINTC2_EXINT4_GPC_Pos (1U) +#define SCFG_EXINTC2_EXINT4_GPC_Msk (0x1U << SCFG_EXINTC2_EXINT4_GPC_Pos) /*!< 0x00000002 */ +#define SCFG_EXINTC2_EXINT4_GPC SCFG_EXINTC2_EXINT4_GPC_Msk /*!< GPIOC pin 4 */ +#define SCFG_EXINTC2_EXINT4_GPD_Pos (0U) +#define SCFG_EXINTC2_EXINT4_GPD_Msk (0x3U << SCFG_EXINTC2_EXINT4_GPD_Pos) /*!< 0x00000003 */ +#define SCFG_EXINTC2_EXINT4_GPD SCFG_EXINTC2_EXINT4_GPD_Msk /*!< GPIOD pin 4 */ +#define SCFG_EXINTC2_EXINT4_GPF_Pos (2U) +#define SCFG_EXINTC2_EXINT4_GPF_Msk (0x1U << SCFG_EXINTC2_EXINT4_GPF_Pos) /*!< 0x00000004 */ +#define SCFG_EXINTC2_EXINT4_GPF SCFG_EXINTC2_EXINT4_GPF_Msk /*!< GPIOF pin 4 */ + +/* EXINT5 configuration */ +#define SCFG_EXINTC2_EXINT5_Pos (4U) +#define SCFG_EXINTC2_EXINT5_Msk (0xFU << SCFG_EXINTC2_EXINT5_Pos) /*!< 0x000000F0 */ +#define SCFG_EXINTC2_EXINT5 SCFG_EXINTC2_EXINT5_Msk /*!< EXINT5[3:0] bits (EXINT5 input source configuration) */ + +#define SCFG_EXINTC2_EXINT5_GPA 0x00000000U /*!< GPIOA pin 5 */ +#define SCFG_EXINTC2_EXINT5_GPB_Pos (4U) +#define SCFG_EXINTC2_EXINT5_GPB_Msk (0x1U << SCFG_EXINTC2_EXINT5_GPB_Pos) /*!< 0x00000010 */ +#define SCFG_EXINTC2_EXINT5_GPB SCFG_EXINTC2_EXINT5_GPB_Msk /*!< GPIOB pin 5 */ +#define SCFG_EXINTC2_EXINT5_GPC_Pos (5U) +#define SCFG_EXINTC2_EXINT5_GPC_Msk (0x1U << SCFG_EXINTC2_EXINT5_GPC_Pos) /*!< 0x00000020 */ +#define SCFG_EXINTC2_EXINT5_GPC SCFG_EXINTC2_EXINT5_GPC_Msk /*!< GPIOC pin 5 */ +#define SCFG_EXINTC2_EXINT5_GPD_Pos (4U) +#define SCFG_EXINTC2_EXINT5_GPD_Msk (0x3U << SCFG_EXINTC2_EXINT5_GPD_Pos) /*!< 0x00000030 */ +#define SCFG_EXINTC2_EXINT5_GPD SCFG_EXINTC2_EXINT5_GPD_Msk /*!< GPIOD pin 5 */ +#define SCFG_EXINTC2_EXINT5_GPF_Pos (6U) +#define SCFG_EXINTC2_EXINT5_GPF_Msk (0x1U << SCFG_EXINTC2_EXINT5_GPF_Pos) /*!< 0x00000040 */ +#define SCFG_EXINTC2_EXINT5_GPF SCFG_EXINTC2_EXINT5_GPF_Msk /*!< GPIOF pin 5 */ + +/*!< EXINT6 configuration */ +#define SCFG_EXINTC2_EXINT6_Pos (8U) +#define SCFG_EXINTC2_EXINT6_Msk (0xFU << SCFG_EXINTC2_EXINT6_Pos) /*!< 0x00000F00 */ +#define SCFG_EXINTC2_EXINT6 SCFG_EXINTC2_EXINT6_Msk /*!< EXINT6[3:0] bits (EXINT6 input source configuration) */ + +#define SCFG_EXINTC2_EXINT6_GPA 0x00000000U /*!< GPIOA pin 6 */ +#define SCFG_EXINTC2_EXINT6_GPB_Pos (8U) +#define SCFG_EXINTC2_EXINT6_GPB_Msk (0x1U << SCFG_EXINTC2_EXINT6_GPB_Pos) /*!< 0x00000100 */ +#define SCFG_EXINTC2_EXINT6_GPB SCFG_EXINTC2_EXINT6_GPB_Msk /*!< GPIOB pin 6 */ +#define SCFG_EXINTC2_EXINT6_GPC_Pos (9U) +#define SCFG_EXINTC2_EXINT6_GPC_Msk (0x1U << SCFG_EXINTC2_EXINT6_GPC_Pos) /*!< 0x00000200 */ +#define SCFG_EXINTC2_EXINT6_GPC SCFG_EXINTC2_EXINT6_GPC_Msk /*!< GPIOC pin 6 */ +#define SCFG_EXINTC2_EXINT6_GPD_Pos (8U) +#define SCFG_EXINTC2_EXINT6_GPD_Msk (0x3U << SCFG_EXINTC2_EXINT6_GPD_Pos) /*!< 0x00000300 */ +#define SCFG_EXINTC2_EXINT6_GPD SCFG_EXINTC2_EXINT6_GPD_Msk /*!< GPIOD pin 6 */ +#define SCFG_EXINTC2_EXINT6_GPF_Pos (10U) +#define SCFG_EXINTC2_EXINT6_GPF_Msk (0x1U << SCFG_EXINTC2_EXINT6_GPF_Pos) /*!< 0x00000400 */ +#define SCFG_EXINTC2_EXINT6_GPF SCFG_EXINTC2_EXINT6_GPF_Msk /*!< GPIOF pin 6 */ + +/*!< EXINT7 configuration */ +#define SCFG_EXINTC2_EXINT7_Pos (12U) +#define SCFG_EXINTC2_EXINT7_Msk (0xFU << SCFG_EXINTC2_EXINT7_Pos) /*!< 0x0000F000 */ +#define SCFG_EXINTC2_EXINT7 SCFG_EXINTC2_EXINT7_Msk /*!< EXINT7[3:0] bits (EXINT7 input source configuration) */ + +#define SCFG_EXINTC2_EXINT7_GPA 0x00000000U /*!< GPIOA pin 7 */ +#define SCFG_EXINTC2_EXINT7_GPB_Pos (12U) +#define SCFG_EXINTC2_EXINT7_GPB_Msk (0x1U << SCFG_EXINTC2_EXINT7_GPB_Pos) /*!< 0x00001000 */ +#define SCFG_EXINTC2_EXINT7_GPB SCFG_EXINTC2_EXINT7_GPB_Msk /*!< GPIOB pin 7 */ +#define SCFG_EXINTC2_EXINT7_GPC_Pos (13U) +#define SCFG_EXINTC2_EXINT7_GPC_Msk (0x1U << SCFG_EXINTC2_EXINT7_GPC_Pos) /*!< 0x00002000 */ +#define SCFG_EXINTC2_EXINT7_GPC SCFG_EXINTC2_EXINT7_GPC_Msk /*!< GPIOC pin 7 */ +#define SCFG_EXINTC2_EXINT7_GPD_Pos (12U) +#define SCFG_EXINTC2_EXINT7_GPD_Msk (0x3U << SCFG_EXINTC2_EXINT7_GPD_Pos) /*!< 0x00003000 */ +#define SCFG_EXINTC2_EXINT7_GPD SCFG_EXINTC2_EXINT7_GPD_Msk /*!< GPIOD pin 7 */ +#define SCFG_EXINTC2_EXINT7_GPF_Pos (14U) +#define SCFG_EXINTC2_EXINT7_GPF_Msk (0x1U << SCFG_EXINTC2_EXINT7_GPF_Pos) /*!< 0x00004000 */ +#define SCFG_EXINTC2_EXINT7_GPF SCFG_EXINTC2_EXINT7_GPF_Msk /*!< GPIOF pin 7 */ + +/***************** Bit definition for SCFG_EXINTC3 register *****************/ +/*!< EXINT8 configuration */ +#define SCFG_EXINTC3_EXINT8_Pos (0U) +#define SCFG_EXINTC3_EXINT8_Msk (0xFU << SCFG_EXINTC3_EXINT8_Pos) /*!< 0x0000000F */ +#define SCFG_EXINTC3_EXINT8 SCFG_EXINTC3_EXINT8_Msk /*!< EXINT8[3:0] bits (EXINT8 input source configuration) */ + +#define SCFG_EXINTC3_EXINT8_GPA 0x00000000U /*!< GPIOA pin 8 */ +#define SCFG_EXINTC3_EXINT8_GPB_Pos (0U) +#define SCFG_EXINTC3_EXINT8_GPB_Msk (0x1U << SCFG_EXINTC3_EXINT8_GPB_Pos) /*!< 0x00000001 */ +#define SCFG_EXINTC3_EXINT8_GPB SCFG_EXINTC3_EXINT8_GPB_Msk /*!< GPIOB pin 8 */ +#define SCFG_EXINTC3_EXINT8_GPC_Pos (1U) +#define SCFG_EXINTC3_EXINT8_GPC_Msk (0x1U << SCFG_EXINTC3_EXINT8_GPC_Pos) /*!< 0x00000002 */ +#define SCFG_EXINTC3_EXINT8_GPC SCFG_EXINTC3_EXINT8_GPC_Msk /*!< GPIOC pin 8 */ +#define SCFG_EXINTC3_EXINT8_GPD_Pos (0U) +#define SCFG_EXINTC3_EXINT8_GPD_Msk (0x3U << SCFG_EXINTC3_EXINT8_GPD_Pos) /*!< 0x00000003 */ +#define SCFG_EXINTC3_EXINT8_GPD SCFG_EXINTC3_EXINT8_GPD_Msk /*!< GPIOD pin 8 */ +#define SCFG_EXINTC3_EXINT8_GPF_Pos (2U) +#define SCFG_EXINTC3_EXINT8_GPF_Msk (0x1U << SCFG_EXINTC3_EXINT8_GPF_Pos) /*!< 0x00000004 */ +#define SCFG_EXINTC3_EXINT8_GPF SCFG_EXINTC3_EXINT8_GPF_Msk /*!< GPIOF pin 8 */ + +/*!< EXINT9 configuration */ +#define SCFG_EXINTC3_EXINT9_Pos (4U) +#define SCFG_EXINTC3_EXINT9_Msk (0xFU << SCFG_EXINTC3_EXINT9_Pos) /*!< 0x000000F0 */ +#define SCFG_EXINTC3_EXINT9 SCFG_EXINTC3_EXINT9_Msk /*!< EXINT9[3:0] bits (EXINT9 input source configuration) */ + +#define SCFG_EXINTC3_EXINT9_GPA 0x00000000U /*!< GPIOA pin 9 */ +#define SCFG_EXINTC3_EXINT9_GPB_Pos (4U) +#define SCFG_EXINTC3_EXINT9_GPB_Msk (0x1U << SCFG_EXINTC3_EXINT9_GPB_Pos) /*!< 0x00000010 */ +#define SCFG_EXINTC3_EXINT9_GPB SCFG_EXINTC3_EXINT9_GPB_Msk /*!< GPIOB pin 9 */ +#define SCFG_EXINTC3_EXINT9_GPC_Pos (5U) +#define SCFG_EXINTC3_EXINT9_GPC_Msk (0x1U << SCFG_EXINTC3_EXINT9_GPC_Pos) /*!< 0x00000020 */ +#define SCFG_EXINTC3_EXINT9_GPC SCFG_EXINTC3_EXINT9_GPC_Msk /*!< GPIOC pin 9 */ +#define SCFG_EXINTC3_EXINT9_GPD_Pos (4U) +#define SCFG_EXINTC3_EXINT9_GPD_Msk (0x3U << SCFG_EXINTC3_EXINT9_GPD_Pos) /*!< 0x00000030 */ +#define SCFG_EXINTC3_EXINT9_GPD SCFG_EXINTC3_EXINT9_GPD_Msk /*!< GPIOD pin 9 */ +#define SCFG_EXINTC3_EXINT9_GPF_Pos (6U) +#define SCFG_EXINTC3_EXINT9_GPF_Msk (0x1U << SCFG_EXINTC3_EXINT9_GPF_Pos) /*!< 0x00000040 */ +#define SCFG_EXINTC3_EXINT9_GPF SCFG_EXINTC3_EXINT9_GPF_Msk /*!< GPIOF pin 9 */ + +/*!< EXINT10 configuration */ +#define SCFG_EXINTC3_EXINT10_Pos (8U) +#define SCFG_EXINTC3_EXINT10_Msk (0xFU << SCFG_EXINTC3_EXINT10_Pos) /*!< 0x00000F00 */ +#define SCFG_EXINTC3_EXINT10 SCFG_EXINTC3_EXINT10_Msk /*!< EXINT10[3:0] bits (EXINT10 input source configuration) */ + +#define SCFG_EXINTC3_EXINT10_GPA 0x00000000U /*!< GPIOA pin 10 */ +#define SCFG_EXINTC3_EXINT10_GPB_Pos (8U) +#define SCFG_EXINTC3_EXINT10_GPB_Msk (0x1U << SCFG_EXINTC3_EXINT10_GPB_Pos) /*!< 0x00000100 */ +#define SCFG_EXINTC3_EXINT10_GPB SCFG_EXINTC3_EXINT10_GPB_Msk /*!< GPIOB pin 10 */ +#define SCFG_EXINTC3_EXINT10_GPC_Pos (9U) +#define SCFG_EXINTC3_EXINT10_GPC_Msk (0x1U << SCFG_EXINTC3_EXINT10_GPC_Pos) /*!< 0x00000200 */ +#define SCFG_EXINTC3_EXINT10_GPC SCFG_EXINTC3_EXINT10_GPC_Msk /*!< GPIOC pin 10 */ +#define SCFG_EXINTC3_EXINT10_GPD_Pos (8U) +#define SCFG_EXINTC3_EXINT10_GPD_Msk (0x3U << SCFG_EXINTC3_EXINT10_GPD_Pos) /*!< 0x00000300 */ +#define SCFG_EXINTC3_EXINT10_GPD SCFG_EXINTC3_EXINT10_GPD_Msk /*!< GPIOD pin 10 */ +#define SCFG_EXINTC3_EXINT10_GPF_Pos (10U) +#define SCFG_EXINTC3_EXINT10_GPF_Msk (0x1U << SCFG_EXINTC3_EXINT10_GPF_Pos) /*!< 0x00000400 */ +#define SCFG_EXINTC3_EXINT10_GPF SCFG_EXINTC3_EXINT10_GPF_Msk /*!< GPIOF pin 10 */ + +/*!< EXINT11 configuration */ +#define SCFG_EXINTC3_EXINT11_Pos (12U) +#define SCFG_EXINTC3_EXINT11_Msk (0xFU << SCFG_EXINTC3_EXINT11_Pos) /*!< 0x0000F000 */ +#define SCFG_EXINTC3_EXINT11 SCFG_EXINTC3_EXINT11_Msk /*!< EXINT11[3:0] bits (EXINT11 input source configuration) */ + +#define SCFG_EXINTC3_EXINT11_GPA 0x00000000U /*!< GPIOA pin 11 */ +#define SCFG_EXINTC3_EXINT11_GPB_Pos (12U) +#define SCFG_EXINTC3_EXINT11_GPB_Msk (0x1U << SCFG_EXINTC3_EXINT11_GPB_Pos) /*!< 0x00001000 */ +#define SCFG_EXINTC3_EXINT11_GPB SCFG_EXINTC3_EXINT11_GPB_Msk /*!< GPIOB pin 11 */ +#define SCFG_EXINTC3_EXINT11_GPC_Pos (13U) +#define SCFG_EXINTC3_EXINT11_GPC_Msk (0x1U << SCFG_EXINTC3_EXINT11_GPC_Pos) /*!< 0x00002000 */ +#define SCFG_EXINTC3_EXINT11_GPC SCFG_EXINTC3_EXINT11_GPC_Msk /*!< GPIOC pin 11 */ +#define SCFG_EXINTC3_EXINT11_GPD_Pos (12U) +#define SCFG_EXINTC3_EXINT11_GPD_Msk (0x3U << SCFG_EXINTC3_EXINT11_GPD_Pos) /*!< 0x00003000 */ +#define SCFG_EXINTC3_EXINT11_GPD SCFG_EXINTC3_EXINT11_GPD_Msk /*!< GPIOD pin 11 */ +#define SCFG_EXINTC3_EXINT11_GPF_Pos (14U) +#define SCFG_EXINTC3_EXINT11_GPF_Msk (0x1U << SCFG_EXINTC3_EXINT11_GPF_Pos) /*!< 0x00004000 */ +#define SCFG_EXINTC3_EXINT11_GPF SCFG_EXINTC3_EXINT11_GPF_Msk /*!< GPIOF pin 11 */ + +/***************** Bit definition for SCFG_EXINTC4 register *****************/ +/* EXINT12 configuration */ +#define SCFG_EXINTC4_EXINT12_Pos (0U) +#define SCFG_EXINTC4_EXINT12_Msk (0xFU << SCFG_EXINTC4_EXINT12_Pos) /*!< 0x0000000F */ +#define SCFG_EXINTC4_EXINT12 SCFG_EXINTC4_EXINT12_Msk /*!< EXINT12[3:0] bits (EXINT12 input source configuration) */ + +#define SCFG_EXINTC4_EXINT12_GPA 0x00000000U /*!< GPIOA pin 12 */ +#define SCFG_EXINTC4_EXINT12_GPB_Pos (0U) +#define SCFG_EXINTC4_EXINT12_GPB_Msk (0x1U << SCFG_EXINTC4_EXINT12_GPB_Pos) /*!< 0x00000001 */ +#define SCFG_EXINTC4_EXINT12_GPB SCFG_EXINTC4_EXINT12_GPB_Msk /*!< GPIOB pin 12 */ +#define SCFG_EXINTC4_EXINT12_GPC_Pos (1U) +#define SCFG_EXINTC4_EXINT12_GPC_Msk (0x1U << SCFG_EXINTC4_EXINT12_GPC_Pos) /*!< 0x00000002 */ +#define SCFG_EXINTC4_EXINT12_GPC SCFG_EXINTC4_EXINT12_GPC_Msk /*!< GPIOC pin 12 */ +#define SCFG_EXINTC4_EXINT12_GPD_Pos (0U) +#define SCFG_EXINTC4_EXINT12_GPD_Msk (0x3U << SCFG_EXINTC4_EXINT12_GPD_Pos) /*!< 0x00000003 */ +#define SCFG_EXINTC4_EXINT12_GPD SCFG_EXINTC4_EXINT12_GPD_Msk /*!< GPIOD pin 12 */ +#define SCFG_EXINTC4_EXINT12_GPF_Pos (2U) +#define SCFG_EXINTC4_EXINT12_GPF_Msk (0x1U << SCFG_EXINTC4_EXINT12_GPF_Pos) /*!< 0x00000004 */ +#define SCFG_EXINTC4_EXINT12_GPF SCFG_EXINTC4_EXINT12_GPF_Msk /*!< GPIOF pin 12 */ + +/* EXINT13 configuration */ +#define SCFG_EXINTC4_EXINT13_Pos (4U) +#define SCFG_EXINTC4_EXINT13_Msk (0xFU << SCFG_EXINTC4_EXINT13_Pos) /*!< 0x000000F0 */ +#define SCFG_EXINTC4_EXINT13 SCFG_EXINTC4_EXINT13_Msk /*!< EXINT13[3:0] bits (EXINT13 input source configuration) */ + +#define SCFG_EXINTC4_EXINT13_GPA 0x00000000U /*!< GPIOA pin 13 */ +#define SCFG_EXINTC4_EXINT13_GPB_Pos (4U) +#define SCFG_EXINTC4_EXINT13_GPB_Msk (0x1U << SCFG_EXINTC4_EXINT13_GPB_Pos) /*!< 0x00000010 */ +#define SCFG_EXINTC4_EXINT13_GPB SCFG_EXINTC4_EXINT13_GPB_Msk /*!< GPIOB pin 13 */ +#define SCFG_EXINTC4_EXINT13_GPC_Pos (5U) +#define SCFG_EXINTC4_EXINT13_GPC_Msk (0x1U << SCFG_EXINTC4_EXINT13_GPC_Pos) /*!< 0x00000020 */ +#define SCFG_EXINTC4_EXINT13_GPC SCFG_EXINTC4_EXINT13_GPC_Msk /*!< GPIOC pin 13 */ +#define SCFG_EXINTC4_EXINT13_GPD_Pos (4U) +#define SCFG_EXINTC4_EXINT13_GPD_Msk (0x3U << SCFG_EXINTC4_EXINT13_GPD_Pos) /*!< 0x00000030 */ +#define SCFG_EXINTC4_EXINT13_GPD SCFG_EXINTC4_EXINT13_GPD_Msk /*!< GPIOD pin 13 */ +#define SCFG_EXINTC4_EXINT13_GPF_Pos (6U) +#define SCFG_EXINTC4_EXINT13_GPF_Msk (0x1U << SCFG_EXINTC4_EXINT13_GPF_Pos) /*!< 0x00000040 */ +#define SCFG_EXINTC4_EXINT13_GPF SCFG_EXINTC4_EXINT13_GPF_Msk /*!< GPIOF pin 13 */ + +/*!< EXINT14 configuration */ +#define SCFG_EXINTC4_EXINT14_Pos (8U) +#define SCFG_EXINTC4_EXINT14_Msk (0xFU << SCFG_EXINTC4_EXINT14_Pos) /*!< 0x00000F00 */ +#define SCFG_EXINTC4_EXINT14 SCFG_EXINTC4_EXINT14_Msk /*!< EXINT14[3:0] bits (EXINT14 input source configuration) */ + +#define SCFG_EXINTC4_EXINT14_GPA 0x00000000U /*!< GPIOA pin 14 */ +#define SCFG_EXINTC4_EXINT14_GPB_Pos (8U) +#define SCFG_EXINTC4_EXINT14_GPB_Msk (0x1U << SCFG_EXINTC4_EXINT14_GPB_Pos) /*!< 0x00000100 */ +#define SCFG_EXINTC4_EXINT14_GPB SCFG_EXINTC4_EXINT14_GPB_Msk /*!< GPIOB pin 14 */ +#define SCFG_EXINTC4_EXINT14_GPC_Pos (9U) +#define SCFG_EXINTC4_EXINT14_GPC_Msk (0x1U << SCFG_EXINTC4_EXINT14_GPC_Pos) /*!< 0x00000200 */ +#define SCFG_EXINTC4_EXINT14_GPC SCFG_EXINTC4_EXINT14_GPC_Msk /*!< GPIOC pin 14 */ +#define SCFG_EXINTC4_EXINT14_GPD_Pos (8U) +#define SCFG_EXINTC4_EXINT14_GPD_Msk (0x3U << SCFG_EXINTC4_EXINT14_GPD_Pos) /*!< 0x00000300 */ +#define SCFG_EXINTC4_EXINT14_GPD SCFG_EXINTC4_EXINT14_GPD_Msk /*!< GPIOD pin 14 */ +#define SCFG_EXINTC4_EXINT14_GPF_Pos (10U) +#define SCFG_EXINTC4_EXINT14_GPF_Msk (0x1U << SCFG_EXINTC4_EXINT14_GPF_Pos) /*!< 0x00000400 */ +#define SCFG_EXINTC4_EXINT14_GPF SCFG_EXINTC4_EXINT14_GPF_Msk /*!< GPIOF pin 14 */ + +/*!< EXINT15 configuration */ +#define SCFG_EXINTC4_EXINT15_Pos (12U) +#define SCFG_EXINTC4_EXINT15_Msk (0xFU << SCFG_EXINTC4_EXINT15_Pos) /*!< 0x0000F000 */ +#define SCFG_EXINTC4_EXINT15 SCFG_EXINTC4_EXINT15_Msk /*!< EXINT15[3:0] bits (EXINT15 input source configuration) */ + +#define SCFG_EXINTC4_EXINT15_GPA 0x00000000U /*!< GPIOA pin 15 */ +#define SCFG_EXINTC4_EXINT15_GPB_Pos (12U) +#define SCFG_EXINTC4_EXINT15_GPB_Msk (0x1U << SCFG_EXINTC4_EXINT15_GPB_Pos) /*!< 0x00001000 */ +#define SCFG_EXINTC4_EXINT15_GPB SCFG_EXINTC4_EXINT15_GPB_Msk /*!< GPIOB pin 15 */ +#define SCFG_EXINTC4_EXINT15_GPC_Pos (13U) +#define SCFG_EXINTC4_EXINT15_GPC_Msk (0x1U << SCFG_EXINTC4_EXINT15_GPC_Pos) /*!< 0x00002000 */ +#define SCFG_EXINTC4_EXINT15_GPC SCFG_EXINTC4_EXINT15_GPC_Msk /*!< GPIOC pin 15 */ +#define SCFG_EXINTC4_EXINT15_GPD_Pos (12U) +#define SCFG_EXINTC4_EXINT15_GPD_Msk (0x3U << SCFG_EXINTC4_EXINT15_GPD_Pos) /*!< 0x00003000 */ +#define SCFG_EXINTC4_EXINT15_GPD SCFG_EXINTC4_EXINT15_GPD_Msk /*!< GPIOD pin 15 */ +#define SCFG_EXINTC4_EXINT15_GPF_Pos (14U) +#define SCFG_EXINTC4_EXINT15_GPF_Msk (0x1U << SCFG_EXINTC4_EXINT15_GPF_Pos) /*!< 0x00004000 */ +#define SCFG_EXINTC4_EXINT15_GPF SCFG_EXINTC4_EXINT15_GPF_Msk /*!< GPIOF pin 15 */ + +/****************** Bit definition for SCFG_UHDRV register ******************/ +#define SCFG_UHDRV_PB3_UH_Pos (0U) +#define SCFG_UHDRV_PB3_UH_Msk (0x1U << SCFG_UHDRV_PB3_UH_Pos) /*!< 0x00000001 */ +#define SCFG_UHDRV_PB3_UH SCFG_UHDRV_PB3_UH_Msk /*!< PB3 Ultra high sourcing/sinking strength */ +#define SCFG_UHDRV_PB9_UH_Pos (1U) +#define SCFG_UHDRV_PB9_UH_Msk (0x1U << SCFG_UHDRV_PB9_UH_Pos) /*!< 0x00000002 */ +#define SCFG_UHDRV_PB9_UH SCFG_UHDRV_PB9_UH_Msk /*!< PB9 Ultra high sourcing/sinking strength */ +#define SCFG_UHDRV_PB10_UH_Pos (2U) +#define SCFG_UHDRV_PB10_UH_Msk (0x1U << SCFG_UHDRV_PB10_UH_Pos) /*!< 0x00000004 */ +#define SCFG_UHDRV_PB10_UH SCFG_UHDRV_PB10_UH_Msk /*!< PB10 Ultra high sourcing/sinking strength */ + +/******************************************************************************/ +/* */ +/* External interrupt/Event controller (EXINT) */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for EXINT_INTEN register ******************/ +#define EXINT_INTEN_INTEN0_Pos (0U) +#define EXINT_INTEN_INTEN0_Msk (0x1U << EXINT_INTEN_INTEN0_Pos) /*!< 0x00000001 */ +#define EXINT_INTEN_INTEN0 EXINT_INTEN_INTEN0_Msk /*!< Interrupt enable or disable on line 0 */ +#define EXINT_INTEN_INTEN1_Pos (1U) +#define EXINT_INTEN_INTEN1_Msk (0x1U << EXINT_INTEN_INTEN1_Pos) /*!< 0x00000002 */ +#define EXINT_INTEN_INTEN1 EXINT_INTEN_INTEN1_Msk /*!< Interrupt enable or disable on line 1 */ +#define EXINT_INTEN_INTEN2_Pos (2U) +#define EXINT_INTEN_INTEN2_Msk (0x1U << EXINT_INTEN_INTEN2_Pos) /*!< 0x00000004 */ +#define EXINT_INTEN_INTEN2 EXINT_INTEN_INTEN2_Msk /*!< Interrupt enable or disable on line 2 */ +#define EXINT_INTEN_INTEN3_Pos (3U) +#define EXINT_INTEN_INTEN3_Msk (0x1U << EXINT_INTEN_INTEN3_Pos) /*!< 0x00000008 */ +#define EXINT_INTEN_INTEN3 EXINT_INTEN_INTEN3_Msk /*!< Interrupt enable or disable on line 3 */ +#define EXINT_INTEN_INTEN4_Pos (4U) +#define EXINT_INTEN_INTEN4_Msk (0x1U << EXINT_INTEN_INTEN4_Pos) /*!< 0x00000010 */ +#define EXINT_INTEN_INTEN4 EXINT_INTEN_INTEN4_Msk /*!< Interrupt enable or disable on line 4 */ +#define EXINT_INTEN_INTEN5_Pos (5U) +#define EXINT_INTEN_INTEN5_Msk (0x1U << EXINT_INTEN_INTEN5_Pos) /*!< 0x00000020 */ +#define EXINT_INTEN_INTEN5 EXINT_INTEN_INTEN5_Msk /*!< Interrupt enable or disable on line 5 */ +#define EXINT_INTEN_INTEN6_Pos (6U) +#define EXINT_INTEN_INTEN6_Msk (0x1U << EXINT_INTEN_INTEN6_Pos) /*!< 0x00000040 */ +#define EXINT_INTEN_INTEN6 EXINT_INTEN_INTEN6_Msk /*!< Interrupt enable or disable on line 6 */ +#define EXINT_INTEN_INTEN7_Pos (7U) +#define EXINT_INTEN_INTEN7_Msk (0x1U << EXINT_INTEN_INTEN7_Pos) /*!< 0x00000080 */ +#define EXINT_INTEN_INTEN7 EXINT_INTEN_INTEN7_Msk /*!< Interrupt enable or disable on line 7 */ +#define EXINT_INTEN_INTEN8_Pos (8U) +#define EXINT_INTEN_INTEN8_Msk (0x1U << EXINT_INTEN_INTEN8_Pos) /*!< 0x00000100 */ +#define EXINT_INTEN_INTEN8 EXINT_INTEN_INTEN8_Msk /*!< Interrupt enable or disable on line 8 */ +#define EXINT_INTEN_INTEN9_Pos (9U) +#define EXINT_INTEN_INTEN9_Msk (0x1U << EXINT_INTEN_INTEN9_Pos) /*!< 0x00000200 */ +#define EXINT_INTEN_INTEN9 EXINT_INTEN_INTEN9_Msk /*!< Interrupt enable or disable on line 9 */ +#define EXINT_INTEN_INTEN10_Pos (10U) +#define EXINT_INTEN_INTEN10_Msk (0x1U << EXINT_INTEN_INTEN10_Pos) /*!< 0x00000400 */ +#define EXINT_INTEN_INTEN10 EXINT_INTEN_INTEN10_Msk /*!< Interrupt enable or disable on line 10 */ +#define EXINT_INTEN_INTEN11_Pos (11U) +#define EXINT_INTEN_INTEN11_Msk (0x1U << EXINT_INTEN_INTEN11_Pos) /*!< 0x00000800 */ +#define EXINT_INTEN_INTEN11 EXINT_INTEN_INTEN11_Msk /*!< Interrupt enable or disable on line 11 */ +#define EXINT_INTEN_INTEN12_Pos (12U) +#define EXINT_INTEN_INTEN12_Msk (0x1U << EXINT_INTEN_INTEN12_Pos) /*!< 0x00001000 */ +#define EXINT_INTEN_INTEN12 EXINT_INTEN_INTEN12_Msk /*!< Interrupt enable or disable on line 12 */ +#define EXINT_INTEN_INTEN13_Pos (13U) +#define EXINT_INTEN_INTEN13_Msk (0x1U << EXINT_INTEN_INTEN13_Pos) /*!< 0x00002000 */ +#define EXINT_INTEN_INTEN13 EXINT_INTEN_INTEN13_Msk /*!< Interrupt enable or disable on line 13 */ +#define EXINT_INTEN_INTEN14_Pos (14U) +#define EXINT_INTEN_INTEN14_Msk (0x1U << EXINT_INTEN_INTEN14_Pos) /*!< 0x00004000 */ +#define EXINT_INTEN_INTEN14 EXINT_INTEN_INTEN14_Msk /*!< Interrupt enable or disable on line 14 */ +#define EXINT_INTEN_INTEN15_Pos (15U) +#define EXINT_INTEN_INTEN15_Msk (0x1U << EXINT_INTEN_INTEN15_Pos) /*!< 0x00008000 */ +#define EXINT_INTEN_INTEN15 EXINT_INTEN_INTEN15_Msk /*!< Interrupt enable or disable on line 15 */ +#define EXINT_INTEN_INTEN16_Pos (16U) +#define EXINT_INTEN_INTEN16_Msk (0x1U << EXINT_INTEN_INTEN16_Pos) /*!< 0x00010000 */ +#define EXINT_INTEN_INTEN16 EXINT_INTEN_INTEN16_Msk /*!< Interrupt enable or disable on line 16 */ +#define EXINT_INTEN_INTEN17_Pos (17U) +#define EXINT_INTEN_INTEN17_Msk (0x1U << EXINT_INTEN_INTEN17_Pos) /*!< 0x00020000 */ +#define EXINT_INTEN_INTEN17 EXINT_INTEN_INTEN17_Msk /*!< Interrupt enable or disable on line 17 */ +#define EXINT_INTEN_INTEN18_Pos (18U) +#define EXINT_INTEN_INTEN18_Msk (0x1U << EXINT_INTEN_INTEN18_Pos) /*!< 0x00040000 */ +#define EXINT_INTEN_INTEN18 EXINT_INTEN_INTEN18_Msk /*!< Interrupt enable or disable on line 18 */ +#define EXINT_INTEN_INTEN20_Pos (20U) +#define EXINT_INTEN_INTEN20_Msk (0x1U << EXINT_INTEN_INTEN20_Pos) /*!< 0x00100000 */ +#define EXINT_INTEN_INTEN20 EXINT_INTEN_INTEN20_Msk /*!< Interrupt enable or disable on line 20 (F405 only) */ +#define EXINT_INTEN_INTEN21_Pos (21U) +#define EXINT_INTEN_INTEN21_Msk (0x1U << EXINT_INTEN_INTEN21_Pos) /*!< 0x00200000 */ +#define EXINT_INTEN_INTEN21 EXINT_INTEN_INTEN21_Msk /*!< Interrupt enable or disable on line 21 */ +#define EXINT_INTEN_INTEN22_Pos (22U) +#define EXINT_INTEN_INTEN22_Msk (0x1U << EXINT_INTEN_INTEN22_Pos) /*!< 0x00400000 */ +#define EXINT_INTEN_INTEN22 EXINT_INTEN_INTEN22_Msk /*!< Interrupt enable or disable on line 22 */ + +/* References Defines */ +#define EXINT_INTEN_INT0 EXINT_INTEN_INTEN0 +#define EXINT_INTEN_INT1 EXINT_INTEN_INTEN1 +#define EXINT_INTEN_INT2 EXINT_INTEN_INTEN2 +#define EXINT_INTEN_INT3 EXINT_INTEN_INTEN3 +#define EXINT_INTEN_INT4 EXINT_INTEN_INTEN4 +#define EXINT_INTEN_INT5 EXINT_INTEN_INTEN5 +#define EXINT_INTEN_INT6 EXINT_INTEN_INTEN6 +#define EXINT_INTEN_INT7 EXINT_INTEN_INTEN7 +#define EXINT_INTEN_INT8 EXINT_INTEN_INTEN8 +#define EXINT_INTEN_INT9 EXINT_INTEN_INTEN9 +#define EXINT_INTEN_INT10 EXINT_INTEN_INTEN10 +#define EXINT_INTEN_INT11 EXINT_INTEN_INTEN11 +#define EXINT_INTEN_INT12 EXINT_INTEN_INTEN12 +#define EXINT_INTEN_INT13 EXINT_INTEN_INTEN13 +#define EXINT_INTEN_INT14 EXINT_INTEN_INTEN14 +#define EXINT_INTEN_INT15 EXINT_INTEN_INTEN15 +#define EXINT_INTEN_INT16 EXINT_INTEN_INTEN16 +#define EXINT_INTEN_INT17 EXINT_INTEN_INTEN17 +#define EXINT_INTEN_INT18 EXINT_INTEN_INTEN18 +#define EXINT_INTEN_INT20 EXINT_INTEN_INTEN20 +#define EXINT_INTEN_INT21 EXINT_INTEN_INTEN21 +#define EXINT_INTEN_INT22 EXINT_INTEN_INTEN22 +#define EXINT_INTEN_INT 0x0077FFFFU /*!< Interrupt enable or disable all */ + +/***************** Bit definition for EXINT_EVTEN register ******************/ +#define EXINT_EVTEN_EVTEN0_Pos (0U) +#define EXINT_EVTEN_EVTEN0_Msk (0x1U << EXINT_EVTEN_EVTEN0_Pos) /*!< 0x00000001 */ +#define EXINT_EVTEN_EVTEN0 EXINT_EVTEN_EVTEN0_Msk /*!< Event enable or disable on line 0 */ +#define EXINT_EVTEN_EVTEN1_Pos (1U) +#define EXINT_EVTEN_EVTEN1_Msk (0x1U << EXINT_EVTEN_EVTEN1_Pos) /*!< 0x00000002 */ +#define EXINT_EVTEN_EVTEN1 EXINT_EVTEN_EVTEN1_Msk /*!< Event enable or disable on line 1 */ +#define EXINT_EVTEN_EVTEN2_Pos (2U) +#define EXINT_EVTEN_EVTEN2_Msk (0x1U << EXINT_EVTEN_EVTEN2_Pos) /*!< 0x00000004 */ +#define EXINT_EVTEN_EVTEN2 EXINT_EVTEN_EVTEN2_Msk /*!< Event enable or disable on line 2 */ +#define EXINT_EVTEN_EVTEN3_Pos (3U) +#define EXINT_EVTEN_EVTEN3_Msk (0x1U << EXINT_EVTEN_EVTEN3_Pos) /*!< 0x00000008 */ +#define EXINT_EVTEN_EVTEN3 EXINT_EVTEN_EVTEN3_Msk /*!< Event enable or disable on line 3 */ +#define EXINT_EVTEN_EVTEN4_Pos (4U) +#define EXINT_EVTEN_EVTEN4_Msk (0x1U << EXINT_EVTEN_EVTEN4_Pos) /*!< 0x00000010 */ +#define EXINT_EVTEN_EVTEN4 EXINT_EVTEN_EVTEN4_Msk /*!< Event enable or disable on line 4 */ +#define EXINT_EVTEN_EVTEN5_Pos (5U) +#define EXINT_EVTEN_EVTEN5_Msk (0x1U << EXINT_EVTEN_EVTEN5_Pos) /*!< 0x00000020 */ +#define EXINT_EVTEN_EVTEN5 EXINT_EVTEN_EVTEN5_Msk /*!< Event enable or disable on line 5 */ +#define EXINT_EVTEN_EVTEN6_Pos (6U) +#define EXINT_EVTEN_EVTEN6_Msk (0x1U << EXINT_EVTEN_EVTEN6_Pos) /*!< 0x00000040 */ +#define EXINT_EVTEN_EVTEN6 EXINT_EVTEN_EVTEN6_Msk /*!< Event enable or disable on line 6 */ +#define EXINT_EVTEN_EVTEN7_Pos (7U) +#define EXINT_EVTEN_EVTEN7_Msk (0x1U << EXINT_EVTEN_EVTEN7_Pos) /*!< 0x00000080 */ +#define EXINT_EVTEN_EVTEN7 EXINT_EVTEN_EVTEN7_Msk /*!< Event enable or disable on line 7 */ +#define EXINT_EVTEN_EVTEN8_Pos (8U) +#define EXINT_EVTEN_EVTEN8_Msk (0x1U << EXINT_EVTEN_EVTEN8_Pos) /*!< 0x00000100 */ +#define EXINT_EVTEN_EVTEN8 EXINT_EVTEN_EVTEN8_Msk /*!< Event enable or disable on line 8 */ +#define EXINT_EVTEN_EVTEN9_Pos (9U) +#define EXINT_EVTEN_EVTEN9_Msk (0x1U << EXINT_EVTEN_EVTEN9_Pos) /*!< 0x00000200 */ +#define EXINT_EVTEN_EVTEN9 EXINT_EVTEN_EVTEN9_Msk /*!< Event enable or disable on line 9 */ +#define EXINT_EVTEN_EVTEN10_Pos (10U) +#define EXINT_EVTEN_EVTEN10_Msk (0x1U << EXINT_EVTEN_EVTEN10_Pos) /*!< 0x00000400 */ +#define EXINT_EVTEN_EVTEN10 EXINT_EVTEN_EVTEN10_Msk /*!< Event enable or disable on line 10 */ +#define EXINT_EVTEN_EVTEN11_Pos (11U) +#define EXINT_EVTEN_EVTEN11_Msk (0x1U << EXINT_EVTEN_EVTEN11_Pos) /*!< 0x00000800 */ +#define EXINT_EVTEN_EVTEN11 EXINT_EVTEN_EVTEN11_Msk /*!< Event enable or disable on line 11 */ +#define EXINT_EVTEN_EVTEN12_Pos (12U) +#define EXINT_EVTEN_EVTEN12_Msk (0x1U << EXINT_EVTEN_EVTEN12_Pos) /*!< 0x00001000 */ +#define EXINT_EVTEN_EVTEN12 EXINT_EVTEN_EVTEN12_Msk /*!< Event enable or disable on line 12 */ +#define EXINT_EVTEN_EVTEN13_Pos (13U) +#define EXINT_EVTEN_EVTEN13_Msk (0x1U << EXINT_EVTEN_EVTEN13_Pos) /*!< 0x00002000 */ +#define EXINT_EVTEN_EVTEN13 EXINT_EVTEN_EVTEN13_Msk /*!< Event enable or disable on line 13 */ +#define EXINT_EVTEN_EVTEN14_Pos (14U) +#define EXINT_EVTEN_EVTEN14_Msk (0x1U << EXINT_EVTEN_EVTEN14_Pos) /*!< 0x00004000 */ +#define EXINT_EVTEN_EVTEN14 EXINT_EVTEN_EVTEN14_Msk /*!< Event enable or disable on line 14 */ +#define EXINT_EVTEN_EVTEN15_Pos (15U) +#define EXINT_EVTEN_EVTEN15_Msk (0x1U << EXINT_EVTEN_EVTEN15_Pos) /*!< 0x00008000 */ +#define EXINT_EVTEN_EVTEN15 EXINT_EVTEN_EVTEN15_Msk /*!< Event enable or disable on line 15 */ +#define EXINT_EVTEN_EVTEN16_Pos (16U) +#define EXINT_EVTEN_EVTEN16_Msk (0x1U << EXINT_EVTEN_EVTEN16_Pos) /*!< 0x00010000 */ +#define EXINT_EVTEN_EVTEN16 EXINT_EVTEN_EVTEN16_Msk /*!< Event enable or disable on line 16 */ +#define EXINT_EVTEN_EVTEN17_Pos (17U) +#define EXINT_EVTEN_EVTEN17_Msk (0x1U << EXINT_EVTEN_EVTEN17_Pos) /*!< 0x00020000 */ +#define EXINT_EVTEN_EVTEN17 EXINT_EVTEN_EVTEN17_Msk /*!< Event enable or disable on line 17 */ +#define EXINT_EVTEN_EVTEN18_Pos (18U) +#define EXINT_EVTEN_EVTEN18_Msk (0x1U << EXINT_EVTEN_EVTEN18_Pos) /*!< 0x00040000 */ +#define EXINT_EVTEN_EVTEN18 EXINT_EVTEN_EVTEN18_Msk /*!< Event enable or disable on line 18 */ +#define EXINT_EVTEN_EVTEN20_Pos (20U) +#define EXINT_EVTEN_EVTEN20_Msk (0x1U << EXINT_EVTEN_EVTEN20_Pos) /*!< 0x00100000 */ +#define EXINT_EVTEN_EVTEN20 EXINT_EVTEN_EVTEN20_Msk /*!< Event enable or disable on line 20 (F405 only) */ +#define EXINT_EVTEN_EVTEN21_Pos (21U) +#define EXINT_EVTEN_EVTEN21_Msk (0x1U << EXINT_EVTEN_EVTEN21_Pos) /*!< 0x00200000 */ +#define EXINT_EVTEN_EVTEN21 EXINT_EVTEN_EVTEN21_Msk /*!< Event enable or disable on line 21 */ +#define EXINT_EVTEN_EVTEN22_Pos (22U) +#define EXINT_EVTEN_EVTEN22_Msk (0x1U << EXINT_EVTEN_EVTEN22_Pos) /*!< 0x00400000 */ +#define EXINT_EVTEN_EVTEN22 EXINT_EVTEN_EVTEN22_Msk /*!< Event enable or disable on line 22 */ + +/* References Defines */ +#define EXINT_EVTEN_EVT0 EXINT_EVTEN_EVTEN0 +#define EXINT_EVTEN_EVT1 EXINT_EVTEN_EVTEN1 +#define EXINT_EVTEN_EVT2 EXINT_EVTEN_EVTEN2 +#define EXINT_EVTEN_EVT3 EXINT_EVTEN_EVTEN3 +#define EXINT_EVTEN_EVT4 EXINT_EVTEN_EVTEN4 +#define EXINT_EVTEN_EVT5 EXINT_EVTEN_EVTEN5 +#define EXINT_EVTEN_EVT6 EXINT_EVTEN_EVTEN6 +#define EXINT_EVTEN_EVT7 EXINT_EVTEN_EVTEN7 +#define EXINT_EVTEN_EVT8 EXINT_EVTEN_EVTEN8 +#define EXINT_EVTEN_EVT9 EXINT_EVTEN_EVTEN9 +#define EXINT_EVTEN_EVT10 EXINT_EVTEN_EVTEN10 +#define EXINT_EVTEN_EVT11 EXINT_EVTEN_EVTEN11 +#define EXINT_EVTEN_EVT12 EXINT_EVTEN_EVTEN12 +#define EXINT_EVTEN_EVT13 EXINT_EVTEN_EVTEN13 +#define EXINT_EVTEN_EVT14 EXINT_EVTEN_EVTEN14 +#define EXINT_EVTEN_EVT15 EXINT_EVTEN_EVTEN15 +#define EXINT_EVTEN_EVT16 EXINT_EVTEN_EVTEN16 +#define EXINT_EVTEN_EVT17 EXINT_EVTEN_EVTEN17 +#define EXINT_EVTEN_EVT18 EXINT_EVTEN_EVTEN18 +#define EXINT_EVTEN_EVT20 EXINT_EVTEN_EVTEN20 +#define EXINT_EVTEN_EVT21 EXINT_EVTEN_EVTEN21 +#define EXINT_EVTEN_EVT22 EXINT_EVTEN_EVTEN22 + +/**************** Bit definition for EXINT_POLCFG1 register *****************/ +#define EXINT_POLCFG1_RP0_Pos (0U) +#define EXINT_POLCFG1_RP0_Msk (0x1U << EXINT_POLCFG1_RP0_Pos) /*!< 0x00000001 */ +#define EXINT_POLCFG1_RP0 EXINT_POLCFG1_RP0_Msk /*!< Rising edge event configuration bit on line 0 */ +#define EXINT_POLCFG1_RP1_Pos (1U) +#define EXINT_POLCFG1_RP1_Msk (0x1U << EXINT_POLCFG1_RP1_Pos) /*!< 0x00000002 */ +#define EXINT_POLCFG1_RP1 EXINT_POLCFG1_RP1_Msk /*!< Rising edge event configuration bit on line 1 */ +#define EXINT_POLCFG1_RP2_Pos (2U) +#define EXINT_POLCFG1_RP2_Msk (0x1U << EXINT_POLCFG1_RP2_Pos) /*!< 0x00000004 */ +#define EXINT_POLCFG1_RP2 EXINT_POLCFG1_RP2_Msk /*!< Rising edge event configuration bit on line 2 */ +#define EXINT_POLCFG1_RP3_Pos (3U) +#define EXINT_POLCFG1_RP3_Msk (0x1U << EXINT_POLCFG1_RP3_Pos) /*!< 0x00000008 */ +#define EXINT_POLCFG1_RP3 EXINT_POLCFG1_RP3_Msk /*!< Rising edge event configuration bit on line 3 */ +#define EXINT_POLCFG1_RP4_Pos (4U) +#define EXINT_POLCFG1_RP4_Msk (0x1U << EXINT_POLCFG1_RP4_Pos) /*!< 0x00000010 */ +#define EXINT_POLCFG1_RP4 EXINT_POLCFG1_RP4_Msk /*!< Rising edge event configuration bit on line 4 */ +#define EXINT_POLCFG1_RP5_Pos (5U) +#define EXINT_POLCFG1_RP5_Msk (0x1U << EXINT_POLCFG1_RP5_Pos) /*!< 0x00000020 */ +#define EXINT_POLCFG1_RP5 EXINT_POLCFG1_RP5_Msk /*!< Rising edge event configuration bit on line 5 */ +#define EXINT_POLCFG1_RP6_Pos (6U) +#define EXINT_POLCFG1_RP6_Msk (0x1U << EXINT_POLCFG1_RP6_Pos) /*!< 0x00000040 */ +#define EXINT_POLCFG1_RP6 EXINT_POLCFG1_RP6_Msk /*!< Rising edge event configuration bit on line 6 */ +#define EXINT_POLCFG1_RP7_Pos (7U) +#define EXINT_POLCFG1_RP7_Msk (0x1U << EXINT_POLCFG1_RP7_Pos) /*!< 0x00000080 */ +#define EXINT_POLCFG1_RP7 EXINT_POLCFG1_RP7_Msk /*!< Rising edge event configuration bit on line 7 */ +#define EXINT_POLCFG1_RP8_Pos (8U) +#define EXINT_POLCFG1_RP8_Msk (0x1U << EXINT_POLCFG1_RP8_Pos) /*!< 0x00000100 */ +#define EXINT_POLCFG1_RP8 EXINT_POLCFG1_RP8_Msk /*!< Rising edge event configuration bit on line 8 */ +#define EXINT_POLCFG1_RP9_Pos (9U) +#define EXINT_POLCFG1_RP9_Msk (0x1U << EXINT_POLCFG1_RP9_Pos) /*!< 0x00000200 */ +#define EXINT_POLCFG1_RP9 EXINT_POLCFG1_RP9_Msk /*!< Rising edge event configuration bit on line 9 */ +#define EXINT_POLCFG1_RP10_Pos (10U) +#define EXINT_POLCFG1_RP10_Msk (0x1U << EXINT_POLCFG1_RP10_Pos) /*!< 0x00000400 */ +#define EXINT_POLCFG1_RP10 EXINT_POLCFG1_RP10_Msk /*!< Rising edge event configuration bit on line 10 */ +#define EXINT_POLCFG1_RP11_Pos (11U) +#define EXINT_POLCFG1_RP11_Msk (0x1U << EXINT_POLCFG1_RP11_Pos) /*!< 0x00000800 */ +#define EXINT_POLCFG1_RP11 EXINT_POLCFG1_RP11_Msk /*!< Rising edge event configuration bit on line 11 */ +#define EXINT_POLCFG1_RP12_Pos (12U) +#define EXINT_POLCFG1_RP12_Msk (0x1U << EXINT_POLCFG1_RP12_Pos) /*!< 0x00001000 */ +#define EXINT_POLCFG1_RP12 EXINT_POLCFG1_RP12_Msk /*!< Rising edge event configuration bit on line 12 */ +#define EXINT_POLCFG1_RP13_Pos (13U) +#define EXINT_POLCFG1_RP13_Msk (0x1U << EXINT_POLCFG1_RP13_Pos) /*!< 0x00002000 */ +#define EXINT_POLCFG1_RP13 EXINT_POLCFG1_RP13_Msk /*!< Rising edge event configuration bit on line 13 */ +#define EXINT_POLCFG1_RP14_Pos (14U) +#define EXINT_POLCFG1_RP14_Msk (0x1U << EXINT_POLCFG1_RP14_Pos) /*!< 0x00004000 */ +#define EXINT_POLCFG1_RP14 EXINT_POLCFG1_RP14_Msk /*!< Rising edge event configuration bit on line 14 */ +#define EXINT_POLCFG1_RP15_Pos (15U) +#define EXINT_POLCFG1_RP15_Msk (0x1U << EXINT_POLCFG1_RP15_Pos) /*!< 0x00008000 */ +#define EXINT_POLCFG1_RP15 EXINT_POLCFG1_RP15_Msk /*!< Rising edge event configuration bit on line 15 */ +#define EXINT_POLCFG1_RP16_Pos (16U) +#define EXINT_POLCFG1_RP16_Msk (0x1U << EXINT_POLCFG1_RP16_Pos) /*!< 0x00010000 */ +#define EXINT_POLCFG1_RP16 EXINT_POLCFG1_RP16_Msk /*!< Rising edge event configuration bit on line 16 */ +#define EXINT_POLCFG1_RP17_Pos (17U) +#define EXINT_POLCFG1_RP17_Msk (0x1U << EXINT_POLCFG1_RP17_Pos) /*!< 0x00020000 */ +#define EXINT_POLCFG1_RP17 EXINT_POLCFG1_RP17_Msk /*!< Rising edge event configuration bit on line 17 */ +#define EXINT_POLCFG1_RP18_Pos (18U) +#define EXINT_POLCFG1_RP18_Msk (0x1U << EXINT_POLCFG1_RP18_Pos) /*!< 0x00040000 */ +#define EXINT_POLCFG1_RP18 EXINT_POLCFG1_RP18_Msk /*!< Rising edge event configuration bit on line 18 */ +#define EXINT_POLCFG1_RP20_Pos (20U) +#define EXINT_POLCFG1_RP20_Msk (0x1U << EXINT_POLCFG1_RP20_Pos) /*!< 0x00100000 */ +#define EXINT_POLCFG1_RP20 EXINT_POLCFG1_RP20_Msk /*!< Rising edge event configuration bit on line 20 (F405 only) */ +#define EXINT_POLCFG1_RP21_Pos (21U) +#define EXINT_POLCFG1_RP21_Msk (0x1U << EXINT_POLCFG1_RP21_Pos) /*!< 0x00200000 */ +#define EXINT_POLCFG1_RP21 EXINT_POLCFG1_RP21_Msk /*!< Rising edge event configuration bit on line 21 */ +#define EXINT_POLCFG1_RP22_Pos (22U) +#define EXINT_POLCFG1_RP22_Msk (0x1U << EXINT_POLCFG1_RP22_Pos) /*!< 0x00400000 */ +#define EXINT_POLCFG1_RP22 EXINT_POLCFG1_RP22_Msk /*!< Rising edge event configuration bit on line 22 */ + +/* References Defines */ +#define EXINT_POLCFG1_POL0 EXINT_POLCFG1_RP0 +#define EXINT_POLCFG1_POL1 EXINT_POLCFG1_RP1 +#define EXINT_POLCFG1_POL2 EXINT_POLCFG1_RP2 +#define EXINT_POLCFG1_POL3 EXINT_POLCFG1_RP3 +#define EXINT_POLCFG1_POL4 EXINT_POLCFG1_RP4 +#define EXINT_POLCFG1_POL5 EXINT_POLCFG1_RP5 +#define EXINT_POLCFG1_POL6 EXINT_POLCFG1_RP6 +#define EXINT_POLCFG1_POL7 EXINT_POLCFG1_RP7 +#define EXINT_POLCFG1_POL8 EXINT_POLCFG1_RP8 +#define EXINT_POLCFG1_POL9 EXINT_POLCFG1_RP9 +#define EXINT_POLCFG1_POL10 EXINT_POLCFG1_RP10 +#define EXINT_POLCFG1_POL11 EXINT_POLCFG1_RP11 +#define EXINT_POLCFG1_POL12 EXINT_POLCFG1_RP12 +#define EXINT_POLCFG1_POL13 EXINT_POLCFG1_RP13 +#define EXINT_POLCFG1_POL14 EXINT_POLCFG1_RP14 +#define EXINT_POLCFG1_POL15 EXINT_POLCFG1_RP15 +#define EXINT_POLCFG1_POL16 EXINT_POLCFG1_RP16 +#define EXINT_POLCFG1_POL17 EXINT_POLCFG1_RP17 +#define EXINT_POLCFG1_POL18 EXINT_POLCFG1_RP18 +#define EXINT_POLCFG1_POL20 EXINT_POLCFG1_RP20 +#define EXINT_POLCFG1_POL21 EXINT_POLCFG1_RP21 +#define EXINT_POLCFG1_POL22 EXINT_POLCFG1_RP22 + +/**************** Bit definition for EXINT_POLCFG2 register *****************/ +#define EXINT_POLCFG2_FP0_Pos (0U) +#define EXINT_POLCFG2_FP0_Msk (0x1U << EXINT_POLCFG2_FP0_Pos) /*!< 0x00000001 */ +#define EXINT_POLCFG2_FP0 EXINT_POLCFG2_FP0_Msk /*!< Falling edge event configuration bit on line 0 */ +#define EXINT_POLCFG2_FP1_Pos (1U) +#define EXINT_POLCFG2_FP1_Msk (0x1U << EXINT_POLCFG2_FP1_Pos) /*!< 0x00000002 */ +#define EXINT_POLCFG2_FP1 EXINT_POLCFG2_FP1_Msk /*!< Falling edge event configuration bit on line 1 */ +#define EXINT_POLCFG2_FP2_Pos (2U) +#define EXINT_POLCFG2_FP2_Msk (0x1U << EXINT_POLCFG2_FP2_Pos) /*!< 0x00000004 */ +#define EXINT_POLCFG2_FP2 EXINT_POLCFG2_FP2_Msk /*!< Falling edge event configuration bit on line 2 */ +#define EXINT_POLCFG2_FP3_Pos (3U) +#define EXINT_POLCFG2_FP3_Msk (0x1U << EXINT_POLCFG2_FP3_Pos) /*!< 0x00000008 */ +#define EXINT_POLCFG2_FP3 EXINT_POLCFG2_FP3_Msk /*!< Falling edge event configuration bit on line 3 */ +#define EXINT_POLCFG2_FP4_Pos (4U) +#define EXINT_POLCFG2_FP4_Msk (0x1U << EXINT_POLCFG2_FP4_Pos) /*!< 0x00000010 */ +#define EXINT_POLCFG2_FP4 EXINT_POLCFG2_FP4_Msk /*!< Falling edge event configuration bit on line 4 */ +#define EXINT_POLCFG2_FP5_Pos (5U) +#define EXINT_POLCFG2_FP5_Msk (0x1U << EXINT_POLCFG2_FP5_Pos) /*!< 0x00000020 */ +#define EXINT_POLCFG2_FP5 EXINT_POLCFG2_FP5_Msk /*!< Falling edge event configuration bit on line 5 */ +#define EXINT_POLCFG2_FP6_Pos (6U) +#define EXINT_POLCFG2_FP6_Msk (0x1U << EXINT_POLCFG2_FP6_Pos) /*!< 0x00000040 */ +#define EXINT_POLCFG2_FP6 EXINT_POLCFG2_FP6_Msk /*!< Falling edge event configuration bit on line 6 */ +#define EXINT_POLCFG2_FP7_Pos (7U) +#define EXINT_POLCFG2_FP7_Msk (0x1U << EXINT_POLCFG2_FP7_Pos) /*!< 0x00000080 */ +#define EXINT_POLCFG2_FP7 EXINT_POLCFG2_FP7_Msk /*!< Falling edge event configuration bit on line 7 */ +#define EXINT_POLCFG2_FP8_Pos (8U) +#define EXINT_POLCFG2_FP8_Msk (0x1U << EXINT_POLCFG2_FP8_Pos) /*!< 0x00000100 */ +#define EXINT_POLCFG2_FP8 EXINT_POLCFG2_FP8_Msk /*!< Falling edge event configuration bit on line 8 */ +#define EXINT_POLCFG2_FP9_Pos (9U) +#define EXINT_POLCFG2_FP9_Msk (0x1U << EXINT_POLCFG2_FP9_Pos) /*!< 0x00000200 */ +#define EXINT_POLCFG2_FP9 EXINT_POLCFG2_FP9_Msk /*!< Falling edge event configuration bit on line 9 */ +#define EXINT_POLCFG2_FP10_Pos (10U) +#define EXINT_POLCFG2_FP10_Msk (0x1U << EXINT_POLCFG2_FP10_Pos) /*!< 0x00000400 */ +#define EXINT_POLCFG2_FP10 EXINT_POLCFG2_FP10_Msk /*!< Falling edge event configuration bit on line 10 */ +#define EXINT_POLCFG2_FP11_Pos (11U) +#define EXINT_POLCFG2_FP11_Msk (0x1U << EXINT_POLCFG2_FP11_Pos) /*!< 0x00000800 */ +#define EXINT_POLCFG2_FP11 EXINT_POLCFG2_FP11_Msk /*!< Falling edge event configuration bit on line 11 */ +#define EXINT_POLCFG2_FP12_Pos (12U) +#define EXINT_POLCFG2_FP12_Msk (0x1U << EXINT_POLCFG2_FP12_Pos) /*!< 0x00001000 */ +#define EXINT_POLCFG2_FP12 EXINT_POLCFG2_FP12_Msk /*!< Falling edge event configuration bit on line 12 */ +#define EXINT_POLCFG2_FP13_Pos (13U) +#define EXINT_POLCFG2_FP13_Msk (0x1U << EXINT_POLCFG2_FP13_Pos) /*!< 0x00002000 */ +#define EXINT_POLCFG2_FP13 EXINT_POLCFG2_FP13_Msk /*!< Falling edge event configuration bit on line 13 */ +#define EXINT_POLCFG2_FP14_Pos (14U) +#define EXINT_POLCFG2_FP14_Msk (0x1U << EXINT_POLCFG2_FP14_Pos) /*!< 0x00004000 */ +#define EXINT_POLCFG2_FP14 EXINT_POLCFG2_FP14_Msk /*!< Falling edge event configuration bit on line 14 */ +#define EXINT_POLCFG2_FP15_Pos (15U) +#define EXINT_POLCFG2_FP15_Msk (0x1U << EXINT_POLCFG2_FP15_Pos) /*!< 0x00008000 */ +#define EXINT_POLCFG2_FP15 EXINT_POLCFG2_FP15_Msk /*!< Falling edge event configuration bit on line 15 */ +#define EXINT_POLCFG2_FP16_Pos (16U) +#define EXINT_POLCFG2_FP16_Msk (0x1U << EXINT_POLCFG2_FP16_Pos) /*!< 0x00010000 */ +#define EXINT_POLCFG2_FP16 EXINT_POLCFG2_FP16_Msk /*!< Falling edge event configuration bit on line 16 */ +#define EXINT_POLCFG2_FP17_Pos (17U) +#define EXINT_POLCFG2_FP17_Msk (0x1U << EXINT_POLCFG2_FP17_Pos) /*!< 0x00020000 */ +#define EXINT_POLCFG2_FP17 EXINT_POLCFG2_FP17_Msk /*!< Falling edge event configuration bit on line 17 */ +#define EXINT_POLCFG2_FP18_Pos (18U) +#define EXINT_POLCFG2_FP18_Msk (0x1U << EXINT_POLCFG2_FP18_Pos) /*!< 0x00040000 */ +#define EXINT_POLCFG2_FP18 EXINT_POLCFG2_FP18_Msk /*!< Falling edge event configuration bit on line 18 */ +#define EXINT_POLCFG2_FP20_Pos (20U) +#define EXINT_POLCFG2_FP20_Msk (0x1U << EXINT_POLCFG2_FP20_Pos) /*!< 0x00100000 */ +#define EXINT_POLCFG2_FP20 EXINT_POLCFG2_FP20_Msk /*!< Falling edge event configuration bit on line 20 (F405 only) */ +#define EXINT_POLCFG2_FP21_Pos (21U) +#define EXINT_POLCFG2_FP21_Msk (0x1U << EXINT_POLCFG2_FP21_Pos) /*!< 0x00200000 */ +#define EXINT_POLCFG2_FP21 EXINT_POLCFG2_FP21_Msk /*!< Falling edge event configuration bit on line 21 */ +#define EXINT_POLCFG2_FP22_Pos (22U) +#define EXINT_POLCFG2_FP22_Msk (0x1U << EXINT_POLCFG2_FP22_Pos) /*!< 0x00400000 */ +#define EXINT_POLCFG2_FP22 EXINT_POLCFG2_FP22_Msk /*!< Falling edge event configuration bit on line 22 */ + +/* References Defines */ +#define EXINT_POLCFG2_POL0 EXINT_POLCFG2_FP0 +#define EXINT_POLCFG2_POL1 EXINT_POLCFG2_FP1 +#define EXINT_POLCFG2_POL2 EXINT_POLCFG2_FP2 +#define EXINT_POLCFG2_POL3 EXINT_POLCFG2_FP3 +#define EXINT_POLCFG2_POL4 EXINT_POLCFG2_FP4 +#define EXINT_POLCFG2_POL5 EXINT_POLCFG2_FP5 +#define EXINT_POLCFG2_POL6 EXINT_POLCFG2_FP6 +#define EXINT_POLCFG2_POL7 EXINT_POLCFG2_FP7 +#define EXINT_POLCFG2_POL8 EXINT_POLCFG2_FP8 +#define EXINT_POLCFG2_POL9 EXINT_POLCFG2_FP9 +#define EXINT_POLCFG2_POL10 EXINT_POLCFG2_FP10 +#define EXINT_POLCFG2_POL11 EXINT_POLCFG2_FP11 +#define EXINT_POLCFG2_POL12 EXINT_POLCFG2_FP12 +#define EXINT_POLCFG2_POL13 EXINT_POLCFG2_FP13 +#define EXINT_POLCFG2_POL14 EXINT_POLCFG2_FP14 +#define EXINT_POLCFG2_POL15 EXINT_POLCFG2_FP15 +#define EXINT_POLCFG2_POL16 EXINT_POLCFG2_FP16 +#define EXINT_POLCFG2_POL17 EXINT_POLCFG2_FP17 +#define EXINT_POLCFG2_POL18 EXINT_POLCFG2_FP18 +#define EXINT_POLCFG2_POL20 EXINT_POLCFG2_FP20 +#define EXINT_POLCFG2_POL21 EXINT_POLCFG2_FP21 +#define EXINT_POLCFG2_POL22 EXINT_POLCFG2_FP22 + +/***************** Bit definition for EXINT_SWTRG register ******************/ +#define EXINT_SWTRG_SWT0_Pos (0U) +#define EXINT_SWTRG_SWT0_Msk (0x1U << EXINT_SWTRG_SWT0_Pos) /*!< 0x00000001 */ +#define EXINT_SWTRG_SWT0 EXINT_SWTRG_SWT0_Msk /*!< Software trigger on line 0 */ +#define EXINT_SWTRG_SWT1_Pos (1U) +#define EXINT_SWTRG_SWT1_Msk (0x1U << EXINT_SWTRG_SWT1_Pos) /*!< 0x00000002 */ +#define EXINT_SWTRG_SWT1 EXINT_SWTRG_SWT1_Msk /*!< Software trigger on line 1 */ +#define EXINT_SWTRG_SWT2_Pos (2U) +#define EXINT_SWTRG_SWT2_Msk (0x1U << EXINT_SWTRG_SWT2_Pos) /*!< 0x00000004 */ +#define EXINT_SWTRG_SWT2 EXINT_SWTRG_SWT2_Msk /*!< Software trigger on line 2 */ +#define EXINT_SWTRG_SWT3_Pos (3U) +#define EXINT_SWTRG_SWT3_Msk (0x1U << EXINT_SWTRG_SWT3_Pos) /*!< 0x00000008 */ +#define EXINT_SWTRG_SWT3 EXINT_SWTRG_SWT3_Msk /*!< Software trigger on line 3 */ +#define EXINT_SWTRG_SWT4_Pos (4U) +#define EXINT_SWTRG_SWT4_Msk (0x1U << EXINT_SWTRG_SWT4_Pos) /*!< 0x00000010 */ +#define EXINT_SWTRG_SWT4 EXINT_SWTRG_SWT4_Msk /*!< Software trigger on line 4 */ +#define EXINT_SWTRG_SWT5_Pos (5U) +#define EXINT_SWTRG_SWT5_Msk (0x1U << EXINT_SWTRG_SWT5_Pos) /*!< 0x00000020 */ +#define EXINT_SWTRG_SWT5 EXINT_SWTRG_SWT5_Msk /*!< Software trigger on line 5 */ +#define EXINT_SWTRG_SWT6_Pos (6U) +#define EXINT_SWTRG_SWT6_Msk (0x1U << EXINT_SWTRG_SWT6_Pos) /*!< 0x00000040 */ +#define EXINT_SWTRG_SWT6 EXINT_SWTRG_SWT6_Msk /*!< Software trigger on line 6 */ +#define EXINT_SWTRG_SWT7_Pos (7U) +#define EXINT_SWTRG_SWT7_Msk (0x1U << EXINT_SWTRG_SWT7_Pos) /*!< 0x00000080 */ +#define EXINT_SWTRG_SWT7 EXINT_SWTRG_SWT7_Msk /*!< Software trigger on line 7 */ +#define EXINT_SWTRG_SWT8_Pos (8U) +#define EXINT_SWTRG_SWT8_Msk (0x1U << EXINT_SWTRG_SWT8_Pos) /*!< 0x00000100 */ +#define EXINT_SWTRG_SWT8 EXINT_SWTRG_SWT8_Msk /*!< Software trigger on line 8 */ +#define EXINT_SWTRG_SWT9_Pos (9U) +#define EXINT_SWTRG_SWT9_Msk (0x1U << EXINT_SWTRG_SWT9_Pos) /*!< 0x00000200 */ +#define EXINT_SWTRG_SWT9 EXINT_SWTRG_SWT9_Msk /*!< Software trigger on line 9 */ +#define EXINT_SWTRG_SWT10_Pos (10U) +#define EXINT_SWTRG_SWT10_Msk (0x1U << EXINT_SWTRG_SWT10_Pos) /*!< 0x00000400 */ +#define EXINT_SWTRG_SWT10 EXINT_SWTRG_SWT10_Msk /*!< Software trigger on line 10 */ +#define EXINT_SWTRG_SWT11_Pos (11U) +#define EXINT_SWTRG_SWT11_Msk (0x1U << EXINT_SWTRG_SWT11_Pos) /*!< 0x00000800 */ +#define EXINT_SWTRG_SWT11 EXINT_SWTRG_SWT11_Msk /*!< Software trigger on line 11 */ +#define EXINT_SWTRG_SWT12_Pos (12U) +#define EXINT_SWTRG_SWT12_Msk (0x1U << EXINT_SWTRG_SWT12_Pos) /*!< 0x00001000 */ +#define EXINT_SWTRG_SWT12 EXINT_SWTRG_SWT12_Msk /*!< Software trigger on line 12 */ +#define EXINT_SWTRG_SWT13_Pos (13U) +#define EXINT_SWTRG_SWT13_Msk (0x1U << EXINT_SWTRG_SWT13_Pos) /*!< 0x00002000 */ +#define EXINT_SWTRG_SWT13 EXINT_SWTRG_SWT13_Msk /*!< Software trigger on line 13 */ +#define EXINT_SWTRG_SWT14_Pos (14U) +#define EXINT_SWTRG_SWT14_Msk (0x1U << EXINT_SWTRG_SWT14_Pos) /*!< 0x00004000 */ +#define EXINT_SWTRG_SWT14 EXINT_SWTRG_SWT14_Msk /*!< Software trigger on line 14 */ +#define EXINT_SWTRG_SWT15_Pos (15U) +#define EXINT_SWTRG_SWT15_Msk (0x1U << EXINT_SWTRG_SWT15_Pos) /*!< 0x00008000 */ +#define EXINT_SWTRG_SWT15 EXINT_SWTRG_SWT15_Msk /*!< Software trigger on line 15 */ +#define EXINT_SWTRG_SWT16_Pos (16U) +#define EXINT_SWTRG_SWT16_Msk (0x1U << EXINT_SWTRG_SWT16_Pos) /*!< 0x00010000 */ +#define EXINT_SWTRG_SWT16 EXINT_SWTRG_SWT16_Msk /*!< Software trigger on line 16 */ +#define EXINT_SWTRG_SWT17_Pos (17U) +#define EXINT_SWTRG_SWT17_Msk (0x1U << EXINT_SWTRG_SWT17_Pos) /*!< 0x00020000 */ +#define EXINT_SWTRG_SWT17 EXINT_SWTRG_SWT17_Msk /*!< Software trigger on line 17 */ +#define EXINT_SWTRG_SWT18_Pos (18U) +#define EXINT_SWTRG_SWT18_Msk (0x1U << EXINT_SWTRG_SWT18_Pos) /*!< 0x00040000 */ +#define EXINT_SWTRG_SWT18 EXINT_SWTRG_SWT18_Msk /*!< Software trigger on line 18 */ +#define EXINT_SWTRG_SWT20_Pos (20U) +#define EXINT_SWTRG_SWT20_Msk (0x1U << EXINT_SWTRG_SWT20_Pos) /*!< 0x00100000 */ +#define EXINT_SWTRG_SWT20 EXINT_SWTRG_SWT20_Msk /*!< Software trigger on line 20 (F405 only) */ +#define EXINT_SWTRG_SWT21_Pos (21U) +#define EXINT_SWTRG_SWT21_Msk (0x1U << EXINT_SWTRG_SWT21_Pos) /*!< 0x00200000 */ +#define EXINT_SWTRG_SWT21 EXINT_SWTRG_SWT21_Msk /*!< Software trigger on line 21 */ +#define EXINT_SWTRG_SWT22_Pos (22U) +#define EXINT_SWTRG_SWT22_Msk (0x1U << EXINT_SWTRG_SWT22_Pos) /*!< 0x00400000 */ +#define EXINT_SWTRG_SWT22 EXINT_SWTRG_SWT22_Msk /*!< Software trigger on line 22 */ + +/* References Defines */ +#define EXINT_SWTRG_SW0 EXINT_SWTRG_SWT0 +#define EXINT_SWTRG_SW1 EXINT_SWTRG_SWT1 +#define EXINT_SWTRG_SW2 EXINT_SWTRG_SWT2 +#define EXINT_SWTRG_SW3 EXINT_SWTRG_SWT3 +#define EXINT_SWTRG_SW4 EXINT_SWTRG_SWT4 +#define EXINT_SWTRG_SW5 EXINT_SWTRG_SWT5 +#define EXINT_SWTRG_SW6 EXINT_SWTRG_SWT6 +#define EXINT_SWTRG_SW7 EXINT_SWTRG_SWT7 +#define EXINT_SWTRG_SW8 EXINT_SWTRG_SWT8 +#define EXINT_SWTRG_SW9 EXINT_SWTRG_SWT9 +#define EXINT_SWTRG_SW10 EXINT_SWTRG_SWT10 +#define EXINT_SWTRG_SW11 EXINT_SWTRG_SWT11 +#define EXINT_SWTRG_SW12 EXINT_SWTRG_SWT12 +#define EXINT_SWTRG_SW13 EXINT_SWTRG_SWT13 +#define EXINT_SWTRG_SW14 EXINT_SWTRG_SWT14 +#define EXINT_SWTRG_SW15 EXINT_SWTRG_SWT15 +#define EXINT_SWTRG_SW16 EXINT_SWTRG_SWT16 +#define EXINT_SWTRG_SW17 EXINT_SWTRG_SWT17 +#define EXINT_SWTRG_SW18 EXINT_SWTRG_SWT18 +#define EXINT_SWTRG_SW20 EXINT_SWTRG_SWT20 +#define EXINT_SWTRG_SW21 EXINT_SWTRG_SWT21 +#define EXINT_SWTRG_SW22 EXINT_SWTRG_SWT22 + +/***************** Bit definition for EXINT_INTSTS register *****************/ +#define EXINT_INTSTS_LINE0_Pos (0U) +#define EXINT_INTSTS_LINE0_Msk (0x1U << EXINT_INTSTS_LINE0_Pos) /*!< 0x00000001 */ +#define EXINT_INTSTS_LINE0 EXINT_INTSTS_LINE0_Msk /*!< Status bit for line 0 */ +#define EXINT_INTSTS_LINE1_Pos (1U) +#define EXINT_INTSTS_LINE1_Msk (0x1U << EXINT_INTSTS_LINE1_Pos) /*!< 0x00000002 */ +#define EXINT_INTSTS_LINE1 EXINT_INTSTS_LINE1_Msk /*!< Status bit for line 1 */ +#define EXINT_INTSTS_LINE2_Pos (2U) +#define EXINT_INTSTS_LINE2_Msk (0x1U << EXINT_INTSTS_LINE2_Pos) /*!< 0x00000004 */ +#define EXINT_INTSTS_LINE2 EXINT_INTSTS_LINE2_Msk /*!< Status bit for line 2 */ +#define EXINT_INTSTS_LINE3_Pos (3U) +#define EXINT_INTSTS_LINE3_Msk (0x1U << EXINT_INTSTS_LINE3_Pos) /*!< 0x00000008 */ +#define EXINT_INTSTS_LINE3 EXINT_INTSTS_LINE3_Msk /*!< Status bit for line 3 */ +#define EXINT_INTSTS_LINE4_Pos (4U) +#define EXINT_INTSTS_LINE4_Msk (0x1U << EXINT_INTSTS_LINE4_Pos) /*!< 0x00000010 */ +#define EXINT_INTSTS_LINE4 EXINT_INTSTS_LINE4_Msk /*!< Status bit for line 4 */ +#define EXINT_INTSTS_LINE5_Pos (5U) +#define EXINT_INTSTS_LINE5_Msk (0x1U << EXINT_INTSTS_LINE5_Pos) /*!< 0x00000020 */ +#define EXINT_INTSTS_LINE5 EXINT_INTSTS_LINE5_Msk /*!< Status bit for line 5 */ +#define EXINT_INTSTS_LINE6_Pos (6U) +#define EXINT_INTSTS_LINE6_Msk (0x1U << EXINT_INTSTS_LINE6_Pos) /*!< 0x00000040 */ +#define EXINT_INTSTS_LINE6 EXINT_INTSTS_LINE6_Msk /*!< Status bit for line 6 */ +#define EXINT_INTSTS_LINE7_Pos (7U) +#define EXINT_INTSTS_LINE7_Msk (0x1U << EXINT_INTSTS_LINE7_Pos) /*!< 0x00000080 */ +#define EXINT_INTSTS_LINE7 EXINT_INTSTS_LINE7_Msk /*!< Status bit for line 7 */ +#define EXINT_INTSTS_LINE8_Pos (8U) +#define EXINT_INTSTS_LINE8_Msk (0x1U << EXINT_INTSTS_LINE8_Pos) /*!< 0x00000100 */ +#define EXINT_INTSTS_LINE8 EXINT_INTSTS_LINE8_Msk /*!< Status bit for line 8 */ +#define EXINT_INTSTS_LINE9_Pos (9U) +#define EXINT_INTSTS_LINE9_Msk (0x1U << EXINT_INTSTS_LINE9_Pos) /*!< 0x00000200 */ +#define EXINT_INTSTS_LINE9 EXINT_INTSTS_LINE9_Msk /*!< Status bit for line 9 */ +#define EXINT_INTSTS_LINE10_Pos (10U) +#define EXINT_INTSTS_LINE10_Msk (0x1U << EXINT_INTSTS_LINE10_Pos) /*!< 0x00000400 */ +#define EXINT_INTSTS_LINE10 EXINT_INTSTS_LINE10_Msk /*!< Status bit for line 10 */ +#define EXINT_INTSTS_LINE11_Pos (11U) +#define EXINT_INTSTS_LINE11_Msk (0x1U << EXINT_INTSTS_LINE11_Pos) /*!< 0x00000800 */ +#define EXINT_INTSTS_LINE11 EXINT_INTSTS_LINE11_Msk /*!< Status bit for line 11 */ +#define EXINT_INTSTS_LINE12_Pos (12U) +#define EXINT_INTSTS_LINE12_Msk (0x1U << EXINT_INTSTS_LINE12_Pos) /*!< 0x00001000 */ +#define EXINT_INTSTS_LINE12 EXINT_INTSTS_LINE12_Msk /*!< Status bit for line 12 */ +#define EXINT_INTSTS_LINE13_Pos (13U) +#define EXINT_INTSTS_LINE13_Msk (0x1U << EXINT_INTSTS_LINE13_Pos) /*!< 0x00002000 */ +#define EXINT_INTSTS_LINE13 EXINT_INTSTS_LINE13_Msk /*!< Status bit for line 13 */ +#define EXINT_INTSTS_LINE14_Pos (14U) +#define EXINT_INTSTS_LINE14_Msk (0x1U << EXINT_INTSTS_LINE14_Pos) /*!< 0x00004000 */ +#define EXINT_INTSTS_LINE14 EXINT_INTSTS_LINE14_Msk /*!< Status bit for line 14 */ +#define EXINT_INTSTS_LINE15_Pos (15U) +#define EXINT_INTSTS_LINE15_Msk (0x1U << EXINT_INTSTS_LINE15_Pos) /*!< 0x00008000 */ +#define EXINT_INTSTS_LINE15 EXINT_INTSTS_LINE15_Msk /*!< Status bit for line 15 */ +#define EXINT_INTSTS_LINE16_Pos (16U) +#define EXINT_INTSTS_LINE16_Msk (0x1U << EXINT_INTSTS_LINE16_Pos) /*!< 0x00010000 */ +#define EXINT_INTSTS_LINE16 EXINT_INTSTS_LINE16_Msk /*!< Status bit for line 16 */ +#define EXINT_INTSTS_LINE17_Pos (17U) +#define EXINT_INTSTS_LINE17_Msk (0x1U << EXINT_INTSTS_LINE17_Pos) /*!< 0x00020000 */ +#define EXINT_INTSTS_LINE17 EXINT_INTSTS_LINE17_Msk /*!< Status bit for line 17 */ +#define EXINT_INTSTS_LINE18_Pos (18U) +#define EXINT_INTSTS_LINE18_Msk (0x1U << EXINT_INTSTS_LINE18_Pos) /*!< 0x00040000 */ +#define EXINT_INTSTS_LINE18 EXINT_INTSTS_LINE18_Msk /*!< Status bit for line 18 */ +#define EXINT_INTSTS_LINE20_Pos (20U) +#define EXINT_INTSTS_LINE20_Msk (0x1U << EXINT_INTSTS_LINE20_Pos) /*!< 0x00100000 */ +#define EXINT_INTSTS_LINE20 EXINT_INTSTS_LINE20_Msk /*!< Status bit for line 20 (F405 only) */ +#define EXINT_INTSTS_LINE21_Pos (21U) +#define EXINT_INTSTS_LINE21_Msk (0x1U << EXINT_INTSTS_LINE21_Pos) /*!< 0x00200000 */ +#define EXINT_INTSTS_LINE21 EXINT_INTSTS_LINE21_Msk /*!< Status bit for line 21 */ +#define EXINT_INTSTS_LINE22_Pos (22U) +#define EXINT_INTSTS_LINE22_Msk (0x1U << EXINT_INTSTS_LINE22_Pos) /*!< 0x00400000 */ +#define EXINT_INTSTS_LINE22 EXINT_INTSTS_LINE22_Msk /*!< Status bit for line 22 */ + +/* References Defines */ +#define EXINT_INTSTS_INT0 EXINT_INTSTS_LINE0 +#define EXINT_INTSTS_INT1 EXINT_INTSTS_LINE1 +#define EXINT_INTSTS_INT2 EXINT_INTSTS_LINE2 +#define EXINT_INTSTS_INT3 EXINT_INTSTS_LINE3 +#define EXINT_INTSTS_INT4 EXINT_INTSTS_LINE4 +#define EXINT_INTSTS_INT5 EXINT_INTSTS_LINE5 +#define EXINT_INTSTS_INT6 EXINT_INTSTS_LINE6 +#define EXINT_INTSTS_INT7 EXINT_INTSTS_LINE7 +#define EXINT_INTSTS_INT8 EXINT_INTSTS_LINE8 +#define EXINT_INTSTS_INT9 EXINT_INTSTS_LINE9 +#define EXINT_INTSTS_INT10 EXINT_INTSTS_LINE10 +#define EXINT_INTSTS_INT11 EXINT_INTSTS_LINE11 +#define EXINT_INTSTS_INT12 EXINT_INTSTS_LINE12 +#define EXINT_INTSTS_INT13 EXINT_INTSTS_LINE13 +#define EXINT_INTSTS_INT14 EXINT_INTSTS_LINE14 +#define EXINT_INTSTS_INT15 EXINT_INTSTS_LINE15 +#define EXINT_INTSTS_INT16 EXINT_INTSTS_LINE16 +#define EXINT_INTSTS_INT17 EXINT_INTSTS_LINE17 +#define EXINT_INTSTS_INT18 EXINT_INTSTS_LINE18 +#define EXINT_INTSTS_INT20 EXINT_INTSTS_LINE20 +#define EXINT_INTSTS_INT21 EXINT_INTSTS_LINE21 +#define EXINT_INTSTS_INT22 EXINT_INTSTS_LINE22 + +/******************************************************************************/ +/* */ +/* DMA controller (DMA) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for DMA_STS register ********************/ +#define DMA_STS_GF1_Pos (0U) +#define DMA_STS_GF1_Msk (0x1U << DMA_STS_GF1_Pos) /*!< 0x00000001 */ +#define DMA_STS_GF1 DMA_STS_GF1_Msk /*!< Channel 1 global event flag */ +#define DMA_STS_FDTF1_Pos (1U) +#define DMA_STS_FDTF1_Msk (0x1U << DMA_STS_FDTF1_Pos) /*!< 0x00000002 */ +#define DMA_STS_FDTF1 DMA_STS_FDTF1_Msk /*!< Channel 1 transfer complete event flag */ +#define DMA_STS_HDTF1_Pos (2U) +#define DMA_STS_HDTF1_Msk (0x1U << DMA_STS_HDTF1_Pos) /*!< 0x00000004 */ +#define DMA_STS_HDTF1 DMA_STS_HDTF1_Msk /*!< Channel 1 half transfer event flag */ +#define DMA_STS_DTERRF1_Pos (3U) +#define DMA_STS_DTERRF1_Msk (0x1U << DMA_STS_DTERRF1_Pos) /*!< 0x00000008 */ +#define DMA_STS_DTERRF1 DMA_STS_DTERRF1_Msk /*!< Channel 1 transfer error event flag */ +#define DMA_STS_GF2_Pos (4U) +#define DMA_STS_GF2_Msk (0x1U << DMA_STS_GF2_Pos) /*!< 0x00000010 */ +#define DMA_STS_GF2 DMA_STS_GF2_Msk /*!< Channel 2 global event flag */ +#define DMA_STS_FDTF2_Pos (5U) +#define DMA_STS_FDTF2_Msk (0x1U << DMA_STS_FDTF2_Pos) /*!< 0x00000020 */ +#define DMA_STS_FDTF2 DMA_STS_FDTF2_Msk /*!< Channel 2 transfer complete event flag */ +#define DMA_STS_HDTF2_Pos (6U) +#define DMA_STS_HDTF2_Msk (0x1U << DMA_STS_HDTF2_Pos) /*!< 0x00000040 */ +#define DMA_STS_HDTF2 DMA_STS_HDTF2_Msk /*!< Channel 2 half transfer event flag */ +#define DMA_STS_DTERRF2_Pos (7U) +#define DMA_STS_DTERRF2_Msk (0x1U << DMA_STS_DTERRF2_Pos) /*!< 0x00000080 */ +#define DMA_STS_DTERRF2 DMA_STS_DTERRF2_Msk /*!< Channel 2 transfer error event flag */ +#define DMA_STS_GF3_Pos (8U) +#define DMA_STS_GF3_Msk (0x1U << DMA_STS_GF3_Pos) /*!< 0x00000100 */ +#define DMA_STS_GF3 DMA_STS_GF3_Msk /*!< Channel 3 global event flag */ +#define DMA_STS_FDTF3_Pos (9U) +#define DMA_STS_FDTF3_Msk (0x1U << DMA_STS_FDTF3_Pos) /*!< 0x00000200 */ +#define DMA_STS_FDTF3 DMA_STS_FDTF3_Msk /*!< Channel 3 transfer complete event flag */ +#define DMA_STS_HDTF3_Pos (10U) +#define DMA_STS_HDTF3_Msk (0x1U << DMA_STS_HDTF3_Pos) /*!< 0x00000400 */ +#define DMA_STS_HDTF3 DMA_STS_HDTF3_Msk /*!< Channel 3 half transfer event flag */ +#define DMA_STS_DTERRF3_Pos (11U) +#define DMA_STS_DTERRF3_Msk (0x1U << DMA_STS_DTERRF3_Pos) /*!< 0x00000800 */ +#define DMA_STS_DTERRF3 DMA_STS_DTERRF3_Msk /*!< Channel 3 transfer error event flag */ +#define DMA_STS_GF4_Pos (12U) +#define DMA_STS_GF4_Msk (0x1U << DMA_STS_GF4_Pos) /*!< 0x00001000 */ +#define DMA_STS_GF4 DMA_STS_GF4_Msk /*!< Channel 4 global event flag */ +#define DMA_STS_FDTF4_Pos (13U) +#define DMA_STS_FDTF4_Msk (0x1U << DMA_STS_FDTF4_Pos) /*!< 0x00002000 */ +#define DMA_STS_FDTF4 DMA_STS_FDTF4_Msk /*!< Channel 4 transfer complete event flag */ +#define DMA_STS_HDTF4_Pos (14U) +#define DMA_STS_HDTF4_Msk (0x1U << DMA_STS_HDTF4_Pos) /*!< 0x00004000 */ +#define DMA_STS_HDTF4 DMA_STS_HDTF4_Msk /*!< Channel 4 half transfer event flag */ +#define DMA_STS_DTERRF4_Pos (15U) +#define DMA_STS_DTERRF4_Msk (0x1U << DMA_STS_DTERRF4_Pos) /*!< 0x00008000 */ +#define DMA_STS_DTERRF4 DMA_STS_DTERRF4_Msk /*!< Channel 4 transfer error event flag */ +#define DMA_STS_GF5_Pos (16U) +#define DMA_STS_GF5_Msk (0x1U << DMA_STS_GF5_Pos) /*!< 0x00010000 */ +#define DMA_STS_GF5 DMA_STS_GF5_Msk /*!< Channel 5 global event flag */ +#define DMA_STS_FDTF5_Pos (17U) +#define DMA_STS_FDTF5_Msk (0x1U << DMA_STS_FDTF5_Pos) /*!< 0x00020000 */ +#define DMA_STS_FDTF5 DMA_STS_FDTF5_Msk /*!< Channel 5 transfer complete event flag */ +#define DMA_STS_HDTF5_Pos (18U) +#define DMA_STS_HDTF5_Msk (0x1U << DMA_STS_HDTF5_Pos) /*!< 0x00040000 */ +#define DMA_STS_HDTF5 DMA_STS_HDTF5_Msk /*!< Channel 5 half transfer event flag */ +#define DMA_STS_DTERRF5_Pos (19U) +#define DMA_STS_DTERRF5_Msk (0x1U << DMA_STS_DTERRF5_Pos) /*!< 0x00080000 */ +#define DMA_STS_DTERRF5 DMA_STS_DTERRF5_Msk /*!< Channel 5 transfer error event flag */ +#define DMA_STS_GF6_Pos (20U) +#define DMA_STS_GF6_Msk (0x1U << DMA_STS_GF6_Pos) /*!< 0x00100000 */ +#define DMA_STS_GF6 DMA_STS_GF6_Msk /*!< Channel 6 global event flag */ +#define DMA_STS_FDTF6_Pos (21U) +#define DMA_STS_FDTF6_Msk (0x1U << DMA_STS_FDTF6_Pos) /*!< 0x00200000 */ +#define DMA_STS_FDTF6 DMA_STS_FDTF6_Msk /*!< Channel 6 transfer complete event flag */ +#define DMA_STS_HDTF6_Pos (22U) +#define DMA_STS_HDTF6_Msk (0x1U << DMA_STS_HDTF6_Pos) /*!< 0x00400000 */ +#define DMA_STS_HDTF6 DMA_STS_HDTF6_Msk /*!< Channel 6 half transfer event flag */ +#define DMA_STS_DTERRF6_Pos (23U) +#define DMA_STS_DTERRF6_Msk (0x1U << DMA_STS_DTERRF6_Pos) /*!< 0x00800000 */ +#define DMA_STS_DTERRF6 DMA_STS_DTERRF6_Msk /*!< Channel 6 transfer error event flag */ +#define DMA_STS_GF7_Pos (24U) +#define DMA_STS_GF7_Msk (0x1U << DMA_STS_GF7_Pos) /*!< 0x01000000 */ +#define DMA_STS_GF7 DMA_STS_GF7_Msk /*!< Channel 7 global event flag */ +#define DMA_STS_FDTF7_Pos (25U) +#define DMA_STS_FDTF7_Msk (0x1U << DMA_STS_FDTF7_Pos) /*!< 0x02000000 */ +#define DMA_STS_FDTF7 DMA_STS_FDTF7_Msk /*!< Channel 7 transfer complete event flag */ +#define DMA_STS_HDTF7_Pos (26U) +#define DMA_STS_HDTF7_Msk (0x1U << DMA_STS_HDTF7_Pos) /*!< 0x04000000 */ +#define DMA_STS_HDTF7 DMA_STS_HDTF7_Msk /*!< Channel 7 half transfer event flag */ +#define DMA_STS_DTERRF7_Pos (27U) +#define DMA_STS_DTERRF7_Msk (0x1U << DMA_STS_DTERRF7_Pos) /*!< 0x08000000 */ +#define DMA_STS_DTERRF7 DMA_STS_DTERRF7_Msk /*!< Channel 7 transfer error event flag */ + +/******************* Bit definition for DMA_CLR register ********************/ +#define DMA_CLR_GFC1_Pos (0U) +#define DMA_CLR_GFC1_Msk (0x1U << DMA_CLR_GFC1_Pos) /*!< 0x00000001 */ +#define DMA_CLR_GFC1 DMA_CLR_GFC1_Msk /*!< Channel 1 global interrupt flag clear */ +#define DMA_CLR_FDTFC1_Pos (1U) +#define DMA_CLR_FDTFC1_Msk (0x1U << DMA_CLR_FDTFC1_Pos) /*!< 0x00000002 */ +#define DMA_CLR_FDTFC1 DMA_CLR_FDTFC1_Msk /*!< Channel 1 transfer complete flag clear */ +#define DMA_CLR_HDTFC1_Pos (2U) +#define DMA_CLR_HDTFC1_Msk (0x1U << DMA_CLR_HDTFC1_Pos) /*!< 0x00000004 */ +#define DMA_CLR_HDTFC1 DMA_CLR_HDTFC1_Msk /*!< Channel 1 half transfer flag clear */ +#define DMA_CLR_DTERRFC1_Pos (3U) +#define DMA_CLR_DTERRFC1_Msk (0x1U << DMA_CLR_DTERRFC1_Pos) /*!< 0x00000008 */ +#define DMA_CLR_DTERRFC1 DMA_CLR_DTERRFC1_Msk /*!< Channel 1 data transfer error flag clear */ +#define DMA_CLR_GFC2_Pos (4U) +#define DMA_CLR_GFC2_Msk (0x1U << DMA_CLR_GFC2_Pos) /*!< 0x00000010 */ +#define DMA_CLR_GFC2 DMA_CLR_GFC2_Msk /*!< Channel 2 global interrupt flag clear */ +#define DMA_CLR_FDTFC2_Pos (5U) +#define DMA_CLR_FDTFC2_Msk (0x1U << DMA_CLR_FDTFC2_Pos) /*!< 0x00000020 */ +#define DMA_CLR_FDTFC2 DMA_CLR_FDTFC2_Msk /*!< Channel 2 transfer complete flag clear */ +#define DMA_CLR_HDTFC2_Pos (6U) +#define DMA_CLR_HDTFC2_Msk (0x1U << DMA_CLR_HDTFC2_Pos) /*!< 0x00000040 */ +#define DMA_CLR_HDTFC2 DMA_CLR_HDTFC2_Msk /*!< Channel 2 half transfer flag clear */ +#define DMA_CLR_DTERRFC2_Pos (7U) +#define DMA_CLR_DTERRFC2_Msk (0x1U << DMA_CLR_DTERRFC2_Pos) /*!< 0x00000080 */ +#define DMA_CLR_DTERRFC2 DMA_CLR_DTERRFC2_Msk /*!< Channel 2 data transfer error flag clear */ +#define DMA_CLR_GFC3_Pos (8U) +#define DMA_CLR_GFC3_Msk (0x1U << DMA_CLR_GFC3_Pos) /*!< 0x00000100 */ +#define DMA_CLR_GFC3 DMA_CLR_GFC3_Msk /*!< Channel 3 global interrupt flag clear */ +#define DMA_CLR_FDTFC3_Pos (9U) +#define DMA_CLR_FDTFC3_Msk (0x1U << DMA_CLR_FDTFC3_Pos) /*!< 0x00000200 */ +#define DMA_CLR_FDTFC3 DMA_CLR_FDTFC3_Msk /*!< Channel 3 transfer complete flag clear */ +#define DMA_CLR_HDTFC3_Pos (10U) +#define DMA_CLR_HDTFC3_Msk (0x1U << DMA_CLR_HDTFC3_Pos) /*!< 0x00000400 */ +#define DMA_CLR_HDTFC3 DMA_CLR_HDTFC3_Msk /*!< Channel 3 half transfer flag clear */ +#define DMA_CLR_DTERRFC3_Pos (11U) +#define DMA_CLR_DTERRFC3_Msk (0x1U << DMA_CLR_DTERRFC3_Pos) /*!< 0x00000800 */ +#define DMA_CLR_DTERRFC3 DMA_CLR_DTERRFC3_Msk /*!< Channel 3 data transfer error flag clear */ +#define DMA_CLR_GFC4_Pos (12U) +#define DMA_CLR_GFC4_Msk (0x1U << DMA_CLR_GFC4_Pos) /*!< 0x00001000 */ +#define DMA_CLR_GFC4 DMA_CLR_GFC4_Msk /*!< Channel 4 global interrupt flag clear */ +#define DMA_CLR_FDTFC4_Pos (13U) +#define DMA_CLR_FDTFC4_Msk (0x1U << DMA_CLR_FDTFC4_Pos) /*!< 0x00002000 */ +#define DMA_CLR_FDTFC4 DMA_CLR_FDTFC4_Msk /*!< Channel 4 transfer complete flag clear */ +#define DMA_CLR_HDTFC4_Pos (14U) +#define DMA_CLR_HDTFC4_Msk (0x1U << DMA_CLR_HDTFC4_Pos) /*!< 0x00004000 */ +#define DMA_CLR_HDTFC4 DMA_CLR_HDTFC4_Msk /*!< Channel 4 half transfer flag clear */ +#define DMA_CLR_DTERRFC4_Pos (15U) +#define DMA_CLR_DTERRFC4_Msk (0x1U << DMA_CLR_DTERRFC4_Pos) /*!< 0x00008000 */ +#define DMA_CLR_DTERRFC4 DMA_CLR_DTERRFC4_Msk /*!< Channel 4 data transfer error flag clear */ +#define DMA_CLR_GFC5_Pos (16U) +#define DMA_CLR_GFC5_Msk (0x1U << DMA_CLR_GFC5_Pos) /*!< 0x00010000 */ +#define DMA_CLR_GFC5 DMA_CLR_GFC5_Msk /*!< Channel 5 global interrupt flag clear */ +#define DMA_CLR_FDTFC5_Pos (17U) +#define DMA_CLR_FDTFC5_Msk (0x1U << DMA_CLR_FDTFC5_Pos) /*!< 0x00020000 */ +#define DMA_CLR_FDTFC5 DMA_CLR_FDTFC5_Msk /*!< Channel 5 transfer complete flag clear */ +#define DMA_CLR_HDTFC5_Pos (18U) +#define DMA_CLR_HDTFC5_Msk (0x1U << DMA_CLR_HDTFC5_Pos) /*!< 0x00040000 */ +#define DMA_CLR_HDTFC5 DMA_CLR_HDTFC5_Msk /*!< Channel 5 half transfer flag clear */ +#define DMA_CLR_DTERRFC5_Pos (19U) +#define DMA_CLR_DTERRFC5_Msk (0x1U << DMA_CLR_DTERRFC5_Pos) /*!< 0x00080000 */ +#define DMA_CLR_DTERRFC5 DMA_CLR_DTERRFC5_Msk /*!< Channel 5 data transfer error flag clear */ +#define DMA_CLR_GFC6_Pos (20U) +#define DMA_CLR_GFC6_Msk (0x1U << DMA_CLR_GFC6_Pos) /*!< 0x00100000 */ +#define DMA_CLR_GFC6 DMA_CLR_GFC6_Msk /*!< Channel 6 global interrupt flag clear */ +#define DMA_CLR_FDTFC6_Pos (21U) +#define DMA_CLR_FDTFC6_Msk (0x1U << DMA_CLR_FDTFC6_Pos) /*!< 0x00200000 */ +#define DMA_CLR_FDTFC6 DMA_CLR_FDTFC6_Msk /*!< Channel 6 transfer complete flag clear */ +#define DMA_CLR_HDTFC6_Pos (22U) +#define DMA_CLR_HDTFC6_Msk (0x1U << DMA_CLR_HDTFC6_Pos) /*!< 0x00400000 */ +#define DMA_CLR_HDTFC6 DMA_CLR_HDTFC6_Msk /*!< Channel 6 half transfer flag clear */ +#define DMA_CLR_DTERRFC6_Pos (23U) +#define DMA_CLR_DTERRFC6_Msk (0x1U << DMA_CLR_DTERRFC6_Pos) /*!< 0x00800000 */ +#define DMA_CLR_DTERRFC6 DMA_CLR_DTERRFC6_Msk /*!< Channel 6 data transfer error flag clear */ +#define DMA_CLR_GFC7_Pos (24U) +#define DMA_CLR_GFC7_Msk (0x1U << DMA_CLR_GFC7_Pos) /*!< 0x01000000 */ +#define DMA_CLR_GFC7 DMA_CLR_GFC7_Msk /*!< Channel 7 global interrupt flag clear */ +#define DMA_CLR_FDTFC7_Pos (25U) +#define DMA_CLR_FDTFC7_Msk (0x1U << DMA_CLR_FDTFC7_Pos) /*!< 0x02000000 */ +#define DMA_CLR_FDTFC7 DMA_CLR_FDTFC7_Msk /*!< Channel 7 transfer complete flag clear */ +#define DMA_CLR_HDTFC7_Pos (26U) +#define DMA_CLR_HDTFC7_Msk (0x1U << DMA_CLR_HDTFC7_Pos) /*!< 0x04000000 */ +#define DMA_CLR_HDTFC7 DMA_CLR_HDTFC7_Msk /*!< Channel 7 half transfer flag clear */ +#define DMA_CLR_DTERRFC7_Pos (27U) +#define DMA_CLR_DTERRFC7_Msk (0x1U << DMA_CLR_DTERRFC7_Pos) /*!< 0x08000000 */ +#define DMA_CLR_DTERRFC7 DMA_CLR_DTERRFC7_Msk /*!< Channel 7 data transfer error flag clear */ + +/****************** Bit definition for DMA_CCTRL register *******************/ +#define DMA_CCTRL_CHEN_Pos (0U) +#define DMA_CCTRL_CHEN_Msk (0x1U << DMA_CCTRL_CHEN_Pos) /*!< 0x00000001 */ +#define DMA_CCTRL_CHEN DMA_CCTRL_CHEN_Msk /*!< Channel enable */ +#define DMA_CCTRL_FDTIEN_Pos (1U) +#define DMA_CCTRL_FDTIEN_Msk (0x1U << DMA_CCTRL_FDTIEN_Pos) /*!< 0x00000002 */ +#define DMA_CCTRL_FDTIEN DMA_CCTRL_FDTIEN_Msk /*!< Transfer complete interrupt enable */ +#define DMA_CCTRL_HDTIEN_Pos (2U) +#define DMA_CCTRL_HDTIEN_Msk (0x1U << DMA_CCTRL_HDTIEN_Pos) /*!< 0x00000004 */ +#define DMA_CCTRL_HDTIEN DMA_CCTRL_HDTIEN_Msk /*!< Half-transfer interrupt enable */ +#define DMA_CCTRL_DTERRIEN_Pos (3U) +#define DMA_CCTRL_DTERRIEN_Msk (0x1U << DMA_CCTRL_DTERRIEN_Pos) /*!< 0x00000008 */ +#define DMA_CCTRL_DTERRIEN DMA_CCTRL_DTERRIEN_Msk /*!< Data transfer error interrupt enable */ +#define DMA_CCTRL_DTD_Pos (4U) +#define DMA_CCTRL_DTD_Msk (0x1U << DMA_CCTRL_DTD_Pos) /*!< 0x00000010 */ +#define DMA_CCTRL_DTD DMA_CCTRL_DTD_Msk /*!< Data transfer direction */ +#define DMA_CCTRL_LM_Pos (5U) +#define DMA_CCTRL_LM_Msk (0x1U << DMA_CCTRL_LM_Pos) /*!< 0x00000020 */ +#define DMA_CCTRL_LM DMA_CCTRL_LM_Msk /*!< Circular mode */ +#define DMA_CCTRL_PINCM_Pos (6U) +#define DMA_CCTRL_PINCM_Msk (0x1U << DMA_CCTRL_PINCM_Pos) /*!< 0x00000040 */ +#define DMA_CCTRL_PINCM DMA_CCTRL_PINCM_Msk /*!< Peripheral address increment mode */ +#define DMA_CCTRL_MINCM_Pos (7U) +#define DMA_CCTRL_MINCM_Msk (0x1U << DMA_CCTRL_MINCM_Pos) /*!< 0x00000080 */ +#define DMA_CCTRL_MINCM DMA_CCTRL_MINCM_Msk /*!< Memory address increment mode */ + +/*!< PWIDTH configuration */ +#define DMA_CCTRL_PWIDTH_Pos (8U) +#define DMA_CCTRL_PWIDTH_Msk (0x3U << DMA_CCTRL_PWIDTH_Pos) /*!< 0x00000300 */ +#define DMA_CCTRL_PWIDTH DMA_CCTRL_PWIDTH_Msk /*!< PWIDTH[1:0] bits (Peripheral data bit width) */ +#define DMA_CCTRL_PWIDTH_0 (0x1U << DMA_CCTRL_PWIDTH_Pos) /*!< 0x00000100 */ +#define DMA_CCTRL_PWIDTH_1 (0x2U << DMA_CCTRL_PWIDTH_Pos) /*!< 0x00000200 */ + +/*!< MWIDTH configuration */ +#define DMA_CCTRL_MWIDTH_Pos (10U) +#define DMA_CCTRL_MWIDTH_Msk (0x3U << DMA_CCTRL_MWIDTH_Pos) /*!< 0x00000C00 */ +#define DMA_CCTRL_MWIDTH DMA_CCTRL_MWIDTH_Msk /*!< MWIDTH[1:0] bits (Memory data bit width) */ +#define DMA_CCTRL_MWIDTH_0 (0x1U << DMA_CCTRL_MWIDTH_Pos) /*!< 0x00000400 */ +#define DMA_CCTRL_MWIDTH_1 (0x2U << DMA_CCTRL_MWIDTH_Pos) /*!< 0x00000800 */ + +/*!< CHPL configuration */ +#define DMA_CCTRL_CHPL_Pos (12U) +#define DMA_CCTRL_CHPL_Msk (0x3U << DMA_CCTRL_CHPL_Pos) /*!< 0x00003000 */ +#define DMA_CCTRL_CHPL DMA_CCTRL_CHPL_Msk /*!< CHPL[1:0] bits(Channel priority level) */ +#define DMA_CCTRL_CHPL_0 (0x1U << DMA_CCTRL_CHPL_Pos) /*!< 0x00001000 */ +#define DMA_CCTRL_CHPL_1 (0x2U << DMA_CCTRL_CHPL_Pos) /*!< 0x00002000 */ + +#define DMA_CCTRL_M2M_Pos (14U) +#define DMA_CCTRL_M2M_Msk (0x1U << DMA_CCTRL_M2M_Pos) /*!< 0x00004000 */ +#define DMA_CCTRL_M2M DMA_CCTRL_M2M_Msk /*!< Memory to memory mode */ + +/****************** Bit definition for DMA_CDTCNT register ******************/ +#define DMA_CDTCNT_CNT_Pos (0U) +#define DMA_CDTCNT_CNT_Msk (0xFFFFU << DMA_CDTCNT_CNT_Pos) /*!< 0x0000FFFF */ +#define DMA_CDTCNT_CNT DMA_CDTCNT_CNT_Msk /*!< Number of data to transfer */ + +/****************** Bit definition for DMA_CPADDR register ******************/ +#define DMA_CPADDR_PADDR_Pos (0U) +#define DMA_CPADDR_PADDR_Msk (0xFFFFFFFFU << DMA_CPADDR_PADDR_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CPADDR_PADDR DMA_CPADDR_PADDR_Msk /*!< Peripheral base address */ + +/****************** Bit definition for DMA_CMADDR register ******************/ +#define DMA_CMADDR_MADDR_Pos (0U) +#define DMA_CMADDR_MADDR_Msk (0xFFFFFFFFU << DMA_CMADDR_MADDR_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CMADDR_MADDR DMA_CMADDR_MADDR_Msk /*!< Memory base address */ + +/****************** Bit definition for DMA_MUXSEL register ******************/ +#define DMA_MUXSEL_TBL_SEL_Pos (0U) +#define DMA_MUXSEL_TBL_SEL_Msk (0x1U << DMA_MUXSEL_TBL_SEL_Pos) /*!< 0x00000001 */ +#define DMA_MUXSEL_TBL_SEL DMA_MUXSEL_TBL_SEL_Msk /*!< Multiplexer table select */ + +/***************** Bit definition for DMA_MUXCCTRL register *****************/ +#define DMA_MUXCCTRL_REQSEL_Pos (0U) +#define DMA_MUXCCTRL_REQSEL_Msk (0x7FU << DMA_MUXCCTRL_REQSEL_Pos) /*!< 0x0000007F */ +#define DMA_MUXCCTRL_REQSEL DMA_MUXCCTRL_REQSEL_Msk /*!< DMA request select */ +#define DMA_MUXCCTRL_SYNCOVIEN_Pos (8U) +#define DMA_MUXCCTRL_SYNCOVIEN_Msk (0x1U << DMA_MUXCCTRL_SYNCOVIEN_Pos) /*!< 0x00000100 */ +#define DMA_MUXCCTRL_SYNCOVIEN DMA_MUXCCTRL_SYNCOVIEN_Msk /*!< Synchronization overrun interrupt enable */ +#define DMA_MUXCCTRL_EVTGEN_Pos (9U) +#define DMA_MUXCCTRL_EVTGEN_Msk (0x1U << DMA_MUXCCTRL_EVTGEN_Pos) /*!< 0x00000200 */ +#define DMA_MUXCCTRL_EVTGEN DMA_MUXCCTRL_EVTGEN_Msk /*!< Event generate enable */ +#define DMA_MUXCCTRL_SYNCEN_Pos (16U) +#define DMA_MUXCCTRL_SYNCEN_Msk (0x1U << DMA_MUXCCTRL_SYNCEN_Pos) /*!< 0x00010000 */ +#define DMA_MUXCCTRL_SYNCEN DMA_MUXCCTRL_SYNCEN_Msk /*!< Synchronization enable */ + +/*!< SYNCPOL configuration */ +#define DMA_MUXCCTRL_SYNCPOL_Pos (17U) +#define DMA_MUXCCTRL_SYNCPOL_Msk (0x3U << DMA_MUXCCTRL_SYNCPOL_Pos) /*!< 0x00060000 */ +#define DMA_MUXCCTRL_SYNCPOL DMA_MUXCCTRL_SYNCPOL_Msk /*!< SYNCPOL[1:0] bits (Synchronization polarity) */ +#define DMA_MUXCCTRL_SYNCPOL_0 (0x1U << DMA_MUXCCTRL_SYNCPOL_Pos) /*!< 0x00020000 */ +#define DMA_MUXCCTRL_SYNCPOL_1 (0x2U << DMA_MUXCCTRL_SYNCPOL_Pos) /*!< 0x00040000 */ + +/*!< REQCNT configuration */ +#define DMA_MUXCCTRL_REQCNT_Pos (19U) +#define DMA_MUXCCTRL_REQCNT_Msk (0x1FU << DMA_MUXCCTRL_REQCNT_Pos) /*!< 0x00F80000 */ +#define DMA_MUXCCTRL_REQCNT DMA_MUXCCTRL_REQCNT_Msk /*!< REQCNT[4:0] bits (DMA request count) */ +#define DMA_MUXCCTRL_REQCNT_0 (0x1U << DMA_MUXCCTRL_REQCNT_Pos) /*!< 0x00080000 */ +#define DMA_MUXCCTRL_REQCNT_1 (0x2U << DMA_MUXCCTRL_REQCNT_Pos) /*!< 0x00100000 */ +#define DMA_MUXCCTRL_REQCNT_2 (0x4U << DMA_MUXCCTRL_REQCNT_Pos) /*!< 0x00200000 */ +#define DMA_MUXCCTRL_REQCNT_3 (0x8U << DMA_MUXCCTRL_REQCNT_Pos) /*!< 0x00400000 */ +#define DMA_MUXCCTRL_REQCNT_4 (0x10U << DMA_MUXCCTRL_REQCNT_Pos) /*!< 0x00800000 */ + +/*!< SYNCSEL configuration */ +#define DMA_MUXCCTRL_SYNCSEL_Pos (24U) +#define DMA_MUXCCTRL_SYNCSEL_Msk (0x1FU << DMA_MUXCCTRL_SYNCSEL_Pos) /*!< 0x1F000000 */ +#define DMA_MUXCCTRL_SYNCSEL DMA_MUXCCTRL_SYNCSEL_Msk /*!< SYNCSEL[4:0] bits (Synchronization select) */ +#define DMA_MUXCCTRL_SYNCSEL_0 (0x1U << DMA_MUXCCTRL_SYNCSEL_Pos) /*!< 0x01000000 */ +#define DMA_MUXCCTRL_SYNCSEL_1 (0x2U << DMA_MUXCCTRL_SYNCSEL_Pos) /*!< 0x02000000 */ +#define DMA_MUXCCTRL_SYNCSEL_2 (0x4U << DMA_MUXCCTRL_SYNCSEL_Pos) /*!< 0x04000000 */ +#define DMA_MUXCCTRL_SYNCSEL_3 (0x8U << DMA_MUXCCTRL_SYNCSEL_Pos) /*!< 0x08000000 */ +#define DMA_MUXCCTRL_SYNCSEL_4 (0x10U << DMA_MUXCCTRL_SYNCSEL_Pos) /*!< 0x10000000 */ + +/***************** Bit definition for DMA_MUXGCTRL register *****************/ +#define DMA_MUXGCTRL_SIGSEL_Pos (0U) +#define DMA_MUXGCTRL_SIGSEL_Msk (0x1FU << DMA_MUXGCTRL_SIGSEL_Pos) /*!< 0x0000001F */ +#define DMA_MUXGCTRL_SIGSEL DMA_MUXGCTRL_SIGSEL_Msk /*!< Signal select */ +#define DMA_MUXGCTRL_TRGOVIEN_Pos (8U) +#define DMA_MUXGCTRL_TRGOVIEN_Msk (0x1U << DMA_MUXGCTRL_TRGOVIEN_Pos) /*!< 0x00000100 */ +#define DMA_MUXGCTRL_TRGOVIEN DMA_MUXGCTRL_TRGOVIEN_Msk /*!< Trigger overrun interrupt enable */ +#define DMA_MUXGCTRL_GEN_Pos (16U) +#define DMA_MUXGCTRL_GEN_Msk (0x1U << DMA_MUXGCTRL_GEN_Pos) /*!< 0x00010000 */ +#define DMA_MUXGCTRL_GEN DMA_MUXGCTRL_GEN_Msk /*!< DMA request generation enable */ + +/*!< GPOL configuration */ +#define DMA_MUXGCTRL_GPOL_Pos (17U) +#define DMA_MUXGCTRL_GPOL_Msk (0x3U << DMA_MUXGCTRL_GPOL_Pos) /*!< 0x00060000 */ +#define DMA_MUXGCTRL_GPOL DMA_MUXGCTRL_GPOL_Msk /*!< GPOL[1:0] bits (DMA request generation polarity) */ +#define DMA_MUXGCTRL_GPOL_0 (0x1U << DMA_MUXGCTRL_GPOL_Pos) /*!< 0x00020000 */ +#define DMA_MUXGCTRL_GPOL_1 (0x2U << DMA_MUXGCTRL_GPOL_Pos) /*!< 0x00040000 */ + +/*!< GREQCNT configuration */ +#define DMA_MUXGCTRL_GREQCNT_Pos (19U) +#define DMA_MUXGCTRL_GREQCNT_Msk (0x1FU << DMA_MUXGCTRL_GREQCNT_Pos) /*!< 0x00F80000 */ +#define DMA_MUXGCTRL_GREQCNT DMA_MUXGCTRL_GREQCNT_Msk /*!< GREQCNT[4:0] bits (DMA request generation count) */ +#define DMA_MUXGCTRL_GREQCNT_0 (0x1U << DMA_MUXGCTRL_GREQCNT_Pos) /*!< 0x00080000 */ +#define DMA_MUXGCTRL_GREQCNT_1 (0x2U << DMA_MUXGCTRL_GREQCNT_Pos) /*!< 0x00100000 */ +#define DMA_MUXGCTRL_GREQCNT_2 (0x4U << DMA_MUXGCTRL_GREQCNT_Pos) /*!< 0x00200000 */ +#define DMA_MUXGCTRL_GREQCNT_3 (0x8U << DMA_MUXGCTRL_GREQCNT_Pos) /*!< 0x00400000 */ +#define DMA_MUXGCTRL_GREQCNT_4 (0x10U << DMA_MUXGCTRL_GREQCNT_Pos) /*!< 0x00800000 */ + +/**************** Bit definition for DMA_MUXSYNCSTS register ****************/ +#define DMA_MUXSYNCSTS_SYNCOVF_Pos (0U) +#define DMA_MUXSYNCSTS_SYNCOVF_Msk (0xFFU << DMA_MUXSYNCSTS_SYNCOVF_Pos) /*!< 0x000000FF */ +#define DMA_MUXSYNCSTS_SYNCOVF DMA_MUXSYNCSTS_SYNCOVF_Msk /*!< Synchronization overrun interrupt flag */ + +/**************** Bit definition for DMA_MUXSYNCCLR register ****************/ +#define DMA_MUXSYNCCLR_SYNCOVFC_Pos (0U) +#define DMA_MUXSYNCCLR_SYNCOVFC_Msk (0xFFU << DMA_MUXSYNCCLR_SYNCOVFC_Pos) /*!< 0x000000FF */ +#define DMA_MUXSYNCCLR_SYNCOVFC DMA_MUXSYNCCLR_SYNCOVFC_Msk /*!< Synchronization overrun interrupt flag clear */ + +/***************** Bit definition for DMA_MUXGSTS register ******************/ +#define DMA_MUXGSTS_TRGOVF_Pos (0U) +#define DMA_MUXGSTS_TRGOVF_Msk (0xFU << DMA_MUXGSTS_TRGOVF_Pos) /*!< 0x0000000F */ +#define DMA_MUXGSTS_TRGOVF DMA_MUXGSTS_TRGOVF_Msk /*!< Trigger overrun interrupt flag */ + +/***************** Bit definition for DMA_MUXGCLR register ******************/ +#define DMA_MUXGCLR_TRGOVFC_Pos (0U) +#define DMA_MUXGCLR_TRGOVFC_Msk (0xFU << DMA_MUXGCLR_TRGOVFC_Pos) /*!< 0x0000000F */ +#define DMA_MUXGCLR_TRGOVFC DMA_MUXGCLR_TRGOVFC_Msk /*!< Trigger overrun interrupt flag clear */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit (CRC) */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for CRC_DT register ********************/ +#define CRC_DT_DT_Pos (0U) +#define CRC_DT_DT_Msk (0xFFFFFFFFU << CRC_DT_DT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DT_DT CRC_DT_DT_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_CDT register ********************/ +#define CRC_CDT_CDT_Pos (0U) +#define CRC_CDT_CDT_Msk (0xFFU << CRC_CDT_CDT_Pos) /*!< 0x000000FF */ +#define CRC_CDT_CDT CRC_CDT_CDT_Msk /*!< General-purpose 8-bit data register bits */ + +/******************* Bit definition for CRC_CTRL register *******************/ +#define CRC_CTRL_RST_Pos (0U) +#define CRC_CTRL_RST_Msk (0x1U << CRC_CTRL_RST_Pos) /*!< 0x00000001 */ +#define CRC_CTRL_RST CRC_CTRL_RST_Msk /*!< Reset CRC calculation unit */ + +/*!< POLY_SIZE configuration */ +#define CRC_CTRL_POLY_SIZE_Pos (3U) +#define CRC_CTRL_POLY_SIZE_Msk (0x3U << CRC_CTRL_POLY_SIZE_Pos) /*!< 0x00000018 */ +#define CRC_CTRL_POLY_SIZE CRC_CTRL_POLY_SIZE_Msk /*!< POLY_SIZE[1:0] bits (Polynomial size) */ +#define CRC_CTRL_POLY_SIZE_0 (0x1U << CRC_CTRL_POLY_SIZE_Pos) /*!< 0x00000008 */ +#define CRC_CTRL_POLY_SIZE_1 (0x2U << CRC_CTRL_POLY_SIZE_Pos) /*!< 0x00000010 */ + +#define CRC_CTRL_POLY_SIZE_32BIT 0x00000000U /*!< 32-bit */ +#define CRC_CTRL_POLY_SIZE_16BIT_Pos (3U) +#define CRC_CTRL_POLY_SIZE_16BIT_Msk (0x1U << CRC_CTRL_POLY_SIZE_16BIT_Pos) /*!< 0x00000008 */ +#define CRC_CTRL_POLY_SIZE_16BIT CRC_CTRL_POLY_SIZE_16BIT_Msk /*!< 16-bit */ +#define CRC_CTRL_POLY_SIZE_8BIT_Pos (4U) +#define CRC_CTRL_POLY_SIZE_8BIT_Msk (0x1U << CRC_CTRL_POLY_SIZE_8BIT_Pos) /*!< 0x00000010 */ +#define CRC_CTRL_POLY_SIZE_8BIT CRC_CTRL_POLY_SIZE_8BIT_Msk /*!< 8-bit */ +#define CRC_CTRL_POLY_SIZE_7BIT_Pos (3U) +#define CRC_CTRL_POLY_SIZE_7BIT_Msk (0x3U << CRC_CTRL_POLY_SIZE_7BIT_Pos) /*!< 0x00000018 */ +#define CRC_CTRL_POLY_SIZE_7BIT CRC_CTRL_POLY_SIZE_7BIT_Msk /*!< 7-bit */ + +/*!< REVID configuration */ +#define CRC_CTRL_REVID_Pos (5U) +#define CRC_CTRL_REVID_Msk (0x3U << CRC_CTRL_REVID_Pos) /*!< 0x00000060 */ +#define CRC_CTRL_REVID CRC_CTRL_REVID_Msk /*!< REVID[1:0] bits (Reverse input data) */ +#define CRC_CTRL_REVID_0 (0x1U << CRC_CTRL_REVID_Pos) /*!< 0x00000020 */ +#define CRC_CTRL_REVID_1 (0x2U << CRC_CTRL_REVID_Pos) /*!< 0x00000040 */ + +#define CRC_CTRL_REVID_NOREV 0x00000000U /*!< No effect */ +#define CRC_CTRL_REVID_BYTEREV_Pos (5U) +#define CRC_CTRL_REVID_BYTEREV_Msk (0x1U << CRC_CTRL_REVID_BYTEREV_Pos) /*!< 0x00000020 */ +#define CRC_CTRL_REVID_BYTEREV CRC_CTRL_REVID_BYTEREV_Msk /*!< Byte reverse */ +#define CRC_CTRL_REVID_HALFREV_Pos (6U) +#define CRC_CTRL_REVID_HALFREV_Msk (0x1U << CRC_CTRL_REVID_HALFREV_Pos) /*!< 0x00000040 */ +#define CRC_CTRL_REVID_HALFREV CRC_CTRL_REVID_HALFREV_Msk /*!< Half-word reverse */ +#define CRC_CTRL_REVID_WORDREV_Pos (5U) +#define CRC_CTRL_REVID_WORDREV_Msk (0x3U << CRC_CTRL_REVID_WORDREV_Pos) /*!< 0x00000060 */ +#define CRC_CTRL_REVID_WORDREV CRC_CTRL_REVID_WORDREV_Msk /*!< Word reverse */ + +#define CRC_CTRL_REVOD_Pos (7U) +#define CRC_CTRL_REVOD_Msk (0x1U << CRC_CTRL_REVOD_Pos) /*!< 0x00000080 */ +#define CRC_CTRL_REVOD CRC_CTRL_REVOD_Msk /*!< Reverse output data */ + +/******************* Bit definition for CRC_IDT register ********************/ +#define CRC_IDT_IDT_Pos (0U) +#define CRC_IDT_IDT_Msk (0xFFFFFFFFU << CRC_IDT_IDT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDT_IDT CRC_IDT_IDT_Msk /*!< Initialization data register */ + +/******************* Bit definition for CRC_POLY register *******************/ +#define CRC_POLY_POLY_Pos (0U) +#define CRC_POLY_POLY_Msk (0xFFFFFFFFU << CRC_POLY_POLY_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POLY_POLY CRC_POLY_POLY_Msk /*!< Polynomial coefficient */ + +/******************************************************************************/ +/* */ +/* Inter-integrated circuit interface (I2C) */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for I2C_CTRL1 register *******************/ +#define I2C_CTRL1_I2CEN_Pos (0U) +#define I2C_CTRL1_I2CEN_Msk (0x1U << I2C_CTRL1_I2CEN_Pos) /*!< 0x00000001 */ +#define I2C_CTRL1_I2CEN I2C_CTRL1_I2CEN_Msk /*!< I2C peripheral enable */ +#define I2C_CTRL1_TDIEN_Pos (1U) +#define I2C_CTRL1_TDIEN_Msk (0x1U << I2C_CTRL1_TDIEN_Pos) /*!< 0x00000002 */ +#define I2C_CTRL1_TDIEN I2C_CTRL1_TDIEN_Msk /*!< Data transmit data interrupt enable */ +#define I2C_CTRL1_RDIEN_Pos (2U) +#define I2C_CTRL1_RDIEN_Msk (0x1U << I2C_CTRL1_RDIEN_Pos) /*!< 0x00000004 */ +#define I2C_CTRL1_RDIEN I2C_CTRL1_RDIEN_Msk /*!< Data receive interrupt enable */ +#define I2C_CTRL1_ADDRIEN_Pos (3U) +#define I2C_CTRL1_ADDRIEN_Msk (0x1U << I2C_CTRL1_ADDRIEN_Pos) /*!< 0x00000008 */ +#define I2C_CTRL1_ADDRIEN I2C_CTRL1_ADDRIEN_Msk /*!< Address match interrupt enable */ +#define I2C_CTRL1_ACKFAILIEN_Pos (4U) +#define I2C_CTRL1_ACKFAILIEN_Msk (0x1U << I2C_CTRL1_ACKFAILIEN_Pos) /*!< 0x00000010 */ +#define I2C_CTRL1_ACKFAILIEN I2C_CTRL1_ACKFAILIEN_Msk /*!< Acknowledge fail interrupt enable */ +#define I2C_CTRL1_STOPIEN_Pos (5U) +#define I2C_CTRL1_STOPIEN_Msk (0x1U << I2C_CTRL1_STOPIEN_Pos) /*!< 0x00000020 */ +#define I2C_CTRL1_STOPIEN I2C_CTRL1_STOPIEN_Msk /*!< Stop generation complete interrupt enable */ +#define I2C_CTRL1_TDCIEN_Pos (6U) +#define I2C_CTRL1_TDCIEN_Msk (0x1U << I2C_CTRL1_TDCIEN_Pos) /*!< 0x00000040 */ +#define I2C_CTRL1_TDCIEN I2C_CTRL1_TDCIEN_Msk /*!< Data transfer complete interrupt enable */ +#define I2C_CTRL1_ERRIEN_Pos (7U) +#define I2C_CTRL1_ERRIEN_Msk (0x1U << I2C_CTRL1_ERRIEN_Pos) /*!< 0x00000080 */ +#define I2C_CTRL1_ERRIEN I2C_CTRL1_ERRIEN_Msk /*!< Error interrupt enable */ +#define I2C_CTRL1_DFLT_Pos (8U) +#define I2C_CTRL1_DFLT_Msk (0xFU << I2C_CTRL1_DFLT_Pos) /*!< 0x00000F00 */ +#define I2C_CTRL1_DFLT I2C_CTRL1_DFLT_Msk /*!< Digital filter value */ +#define I2C_CTRL1_DMATEN_Pos (14U) +#define I2C_CTRL1_DMATEN_Msk (0x1U << I2C_CTRL1_DMATEN_Pos) /*!< 0x00004000 */ +#define I2C_CTRL1_DMATEN I2C_CTRL1_DMATEN_Msk /*!< DMA transmit data request enable */ +#define I2C_CTRL1_DMAREN_Pos (15U) +#define I2C_CTRL1_DMAREN_Msk (0x1U << I2C_CTRL1_DMAREN_Pos) /*!< 0x00008000 */ +#define I2C_CTRL1_DMAREN I2C_CTRL1_DMAREN_Msk /*!< DMA receive data request enable */ +#define I2C_CTRL1_SCTRL_Pos (16U) +#define I2C_CTRL1_SCTRL_Msk (0x1U << I2C_CTRL1_SCTRL_Pos) /*!< 0x00010000 */ +#define I2C_CTRL1_SCTRL I2C_CTRL1_SCTRL_Msk /*!< Slave receiving data control */ +#define I2C_CTRL1_STRETCH_Pos (17U) +#define I2C_CTRL1_STRETCH_Msk (0x1U << I2C_CTRL1_STRETCH_Pos) /*!< 0x00020000 */ +#define I2C_CTRL1_STRETCH I2C_CTRL1_STRETCH_Msk /*!< Clock stretching mode */ +#define I2C_CTRL1_GCAEN_Pos (19U) +#define I2C_CTRL1_GCAEN_Msk (0x1U << I2C_CTRL1_GCAEN_Pos) /*!< 0x00080000 */ +#define I2C_CTRL1_GCAEN I2C_CTRL1_GCAEN_Msk /*!< General call address enable */ +#define I2C_CTRL1_HADDREN_Pos (20U) +#define I2C_CTRL1_HADDREN_Msk (0x1U << I2C_CTRL1_HADDREN_Pos) /*!< 0x00100000 */ +#define I2C_CTRL1_HADDREN I2C_CTRL1_HADDREN_Msk /*!< SMBus host address enable */ +#define I2C_CTRL1_DEVADDREN_Pos (21U) +#define I2C_CTRL1_DEVADDREN_Msk (0x1U << I2C_CTRL1_DEVADDREN_Pos) /*!< 0x00200000 */ +#define I2C_CTRL1_DEVADDREN I2C_CTRL1_DEVADDREN_Msk /*!< SMBus device default address enable */ +#define I2C_CTRL1_SMBALERT_Pos (22U) +#define I2C_CTRL1_SMBALERT_Msk (0x1U << I2C_CTRL1_SMBALERT_Pos) /*!< 0x00400000 */ +#define I2C_CTRL1_SMBALERT I2C_CTRL1_SMBALERT_Msk /*!< SMBus alert enable / pin set */ +#define I2C_CTRL1_PECEN_Pos (23U) +#define I2C_CTRL1_PECEN_Msk (0x1U << I2C_CTRL1_PECEN_Pos) /*!< 0x00800000 */ +#define I2C_CTRL1_PECEN I2C_CTRL1_PECEN_Msk /*!< PEC calculation enable */ + +/****************** Bit definition for I2C_CTRL2 register *******************/ +/*!< SADDR configuration */ +#define I2C_CTRL2_SADDR_Pos (0U) +#define I2C_CTRL2_SADDR_Msk (0x3FFU << I2C_CTRL2_SADDR_Pos) /*!< 0x000003FF */ +#define I2C_CTRL2_SADDR I2C_CTRL2_SADDR_Msk /*!< SADDR[9:0] bits (Slave address sent by the master) */ +#define I2C_CTRL2_SADDR_0 (0x001U << I2C_CTRL2_SADDR_Pos) /*!< 0x00000001 */ +#define I2C_CTRL2_SADDR_1 (0x002U << I2C_CTRL2_SADDR_Pos) /*!< 0x00000002 */ +#define I2C_CTRL2_SADDR_2 (0x004U << I2C_CTRL2_SADDR_Pos) /*!< 0x00000004 */ +#define I2C_CTRL2_SADDR_3 (0x008U << I2C_CTRL2_SADDR_Pos) /*!< 0x00000008 */ +#define I2C_CTRL2_SADDR_4 (0x010U << I2C_CTRL2_SADDR_Pos) /*!< 0x00000010 */ +#define I2C_CTRL2_SADDR_5 (0x020U << I2C_CTRL2_SADDR_Pos) /*!< 0x00000020 */ +#define I2C_CTRL2_SADDR_6 (0x040U << I2C_CTRL2_SADDR_Pos) /*!< 0x00000040 */ +#define I2C_CTRL2_SADDR_7 (0x080U << I2C_CTRL2_SADDR_Pos) /*!< 0x00000080 */ +#define I2C_CTRL2_SADDR_8 (0x100U << I2C_CTRL2_SADDR_Pos) /*!< 0x00000100 */ +#define I2C_CTRL2_SADDR_9 (0x200U << I2C_CTRL2_SADDR_Pos) /*!< 0x00000200 */ + +#define I2C_CTRL2_DIR_Pos (10U) +#define I2C_CTRL2_DIR_Msk (0x1U << I2C_CTRL2_DIR_Pos) /*!< 0x00000400 */ +#define I2C_CTRL2_DIR I2C_CTRL2_DIR_Msk /*!< Master data transmission direction */ +#define I2C_CTRL2_ADDR10_Pos (11U) +#define I2C_CTRL2_ADDR10_Msk (0x1U << I2C_CTRL2_ADDR10_Pos) /*!< 0x00000800 */ +#define I2C_CTRL2_ADDR10 I2C_CTRL2_ADDR10_Msk /*!< Host sends 10-bit address mode enable */ +#define I2C_CTRL2_READH10_Pos (12U) +#define I2C_CTRL2_READH10_Msk (0x1U << I2C_CTRL2_READH10_Pos) /*!< 0x00001000 */ +#define I2C_CTRL2_READH10 I2C_CTRL2_READH10_Msk /*!< 10-bit address header read enable */ +#define I2C_CTRL2_GENSTART_Pos (13U) +#define I2C_CTRL2_GENSTART_Msk (0x1U << I2C_CTRL2_GENSTART_Pos) /*!< 0x00002000 */ +#define I2C_CTRL2_GENSTART I2C_CTRL2_GENSTART_Msk /*!< Generate start condition */ +#define I2C_CTRL2_GENSTOP_Pos (14U) +#define I2C_CTRL2_GENSTOP_Msk (0x1U << I2C_CTRL2_GENSTOP_Pos) /*!< 0x00004000 */ +#define I2C_CTRL2_GENSTOP I2C_CTRL2_GENSTOP_Msk /*!< Generate stop condition */ +#define I2C_CTRL2_NACKEN_Pos (15U) +#define I2C_CTRL2_NACKEN_Msk (0x1U << I2C_CTRL2_NACKEN_Pos) /*!< 0x00008000 */ +#define I2C_CTRL2_NACKEN I2C_CTRL2_NACKEN_Msk /*!< Not acknowledge enable */ + +/*!< CNT configuration */ +#define I2C_CTRL2_CNT_Pos (16U) +#define I2C_CTRL2_CNT_Msk (0xFFU << I2C_CTRL2_CNT_Pos) /*!< 0x00FF0000 */ +#define I2C_CTRL2_CNT I2C_CTRL2_CNT_Msk /*!< CNT[7:0] bits (CNT) */ +#define I2C_CTRL2_CNT_0 (0x01U << I2C_CTRL2_CNT_Pos) /*!< 0x00010000 */ +#define I2C_CTRL2_CNT_1 (0x02U << I2C_CTRL2_CNT_Pos) /*!< 0x00020000 */ +#define I2C_CTRL2_CNT_2 (0x04U << I2C_CTRL2_CNT_Pos) /*!< 0x00040000 */ +#define I2C_CTRL2_CNT_3 (0x08U << I2C_CTRL2_CNT_Pos) /*!< 0x00080000 */ +#define I2C_CTRL2_CNT_4 (0x10U << I2C_CTRL2_CNT_Pos) /*!< 0x00100000 */ +#define I2C_CTRL2_CNT_5 (0x20U << I2C_CTRL2_CNT_Pos) /*!< 0x00200000 */ +#define I2C_CTRL2_CNT_6 (0x40U << I2C_CTRL2_CNT_Pos) /*!< 0x00400000 */ +#define I2C_CTRL2_CNT_7 (0x80U << I2C_CTRL2_CNT_Pos) /*!< 0x00800000 */ + +#define I2C_CTRL2_RLDEN_Pos (24U) +#define I2C_CTRL2_RLDEN_Msk (0x1U << I2C_CTRL2_RLDEN_Pos) /*!< 0x01000000 */ +#define I2C_CTRL2_RLDEN I2C_CTRL2_RLDEN_Msk /*!< Send data reload mode enable */ +#define I2C_CTRL2_ASTOPEN_Pos (25U) +#define I2C_CTRL2_ASTOPEN_Msk (0x1U << I2C_CTRL2_ASTOPEN_Pos) /*!< 0x02000000 */ +#define I2C_CTRL2_ASTOPEN I2C_CTRL2_ASTOPEN_Msk /*!< Automatically send stop condition enable */ +#define I2C_CTRL2_PECTEN_Pos (26U) +#define I2C_CTRL2_PECTEN_Msk (0x1U << I2C_CTRL2_PECTEN_Pos) /*!< 0x04000000 */ +#define I2C_CTRL2_PECTEN I2C_CTRL2_PECTEN_Msk /*!< Request PEC transmission enable */ + +/****************** Bit definition for I2C_OADDR1 register ******************/ +/*!< ADDR1 configuration */ +#define I2C_OADDR1_ADDR1_1_7 0x000000FEU /*!< Interface Address */ +#define I2C_OADDR1_ADDR1_8_9 0x00000300U /*!< Interface Address */ + +#define I2C_OADDR1_ADDR1_0_Pos (0U) +#define I2C_OADDR1_ADDR1_0_Msk (0x1U << I2C_OADDR1_ADDR1_0_Pos) /*!< 0x00000001 */ +#define I2C_OADDR1_ADDR1_0 I2C_OADDR1_ADDR1_0_Msk /*!< Bit 0 */ +#define I2C_OADDR1_ADDR1_1_Pos (1U) +#define I2C_OADDR1_ADDR1_1_Msk (0x1U << I2C_OADDR1_ADDR1_1_Pos) /*!< 0x00000002 */ +#define I2C_OADDR1_ADDR1_1 I2C_OADDR1_ADDR1_1_Msk /*!< Bit 1 */ +#define I2C_OADDR1_ADDR1_2_Pos (2U) +#define I2C_OADDR1_ADDR1_2_Msk (0x1U << I2C_OADDR1_ADDR1_2_Pos) /*!< 0x00000004 */ +#define I2C_OADDR1_ADDR1_2 I2C_OADDR1_ADDR1_2_Msk /*!< Bit 2 */ +#define I2C_OADDR1_ADDR1_3_Pos (3U) +#define I2C_OADDR1_ADDR1_3_Msk (0x1U << I2C_OADDR1_ADDR1_3_Pos) /*!< 0x00000008 */ +#define I2C_OADDR1_ADDR1_3 I2C_OADDR1_ADDR1_3_Msk /*!< Bit 3 */ +#define I2C_OADDR1_ADDR1_4_Pos (4U) +#define I2C_OADDR1_ADDR1_4_Msk (0x1U << I2C_OADDR1_ADDR1_4_Pos) /*!< 0x00000010 */ +#define I2C_OADDR1_ADDR1_4 I2C_OADDR1_ADDR1_4_Msk /*!< Bit 4 */ +#define I2C_OADDR1_ADDR1_5_Pos (5U) +#define I2C_OADDR1_ADDR1_5_Msk (0x1U << I2C_OADDR1_ADDR1_5_Pos) /*!< 0x00000020 */ +#define I2C_OADDR1_ADDR1_5 I2C_OADDR1_ADDR1_5_Msk /*!< Bit 5 */ +#define I2C_OADDR1_ADDR1_6_Pos (6U) +#define I2C_OADDR1_ADDR1_6_Msk (0x1U << I2C_OADDR1_ADDR1_6_Pos) /*!< 0x00000040 */ +#define I2C_OADDR1_ADDR1_6 I2C_OADDR1_ADDR1_6_Msk /*!< Bit 6 */ +#define I2C_OADDR1_ADDR1_7_Pos (7U) +#define I2C_OADDR1_ADDR1_7_Msk (0x1U << I2C_OADDR1_ADDR1_7_Pos) /*!< 0x00000080 */ +#define I2C_OADDR1_ADDR1_7 I2C_OADDR1_ADDR1_7_Msk /*!< Bit 7 */ +#define I2C_OADDR1_ADDR1_8_Pos (8U) +#define I2C_OADDR1_ADDR1_8_Msk (0x1U << I2C_OADDR1_ADDR1_8_Pos) /*!< 0x00000100 */ +#define I2C_OADDR1_ADDR1_8 I2C_OADDR1_ADDR1_8_Msk /*!< Bit 8 */ +#define I2C_OADDR1_ADDR1_9_Pos (9U) +#define I2C_OADDR1_ADDR1_9_Msk (0x1U << I2C_OADDR1_ADDR1_9_Pos) /*!< 0x00000200 */ +#define I2C_OADDR1_ADDR1_9 I2C_OADDR1_ADDR1_9_Msk /*!< Bit 9 */ + +#define I2C_OADDR1_ADDR1MODE_Pos (10U) +#define I2C_OADDR1_ADDR1MODE_Msk (0x1U << I2C_OADDR1_ADDR1MODE_Pos) /*!< 0x00000400 */ +#define I2C_OADDR1_ADDR1MODE I2C_OADDR1_ADDR1MODE_Msk /*!< Own Address 1 mode */ +#define I2C_OADDR1_ADDR1EN_Pos (15U) +#define I2C_OADDR1_ADDR1EN_Msk (0x1U << I2C_OADDR1_ADDR1EN_Pos) /*!< 0x00008000 */ +#define I2C_OADDR1_ADDR1EN I2C_OADDR1_ADDR1EN_Msk /*!< Own Address 1 enable */ + +/****************** Bit definition for I2C_OADDR2 register ******************/ +#define I2C_OADDR2_ADDR2_Pos (1U) +#define I2C_OADDR2_ADDR2_Msk (0x7FU << I2C_OADDR2_ADDR2_Pos) /*!< 0x000000FE */ +#define I2C_OADDR2_ADDR2 I2C_OADDR2_ADDR2_Msk /*!< Own address 2 */ + +/*!< ADDR2MASK configuration */ +#define I2C_OADDR2_ADDR2MASK_Pos (8U) +#define I2C_OADDR2_ADDR2MASK_Msk (0x7U << I2C_OADDR2_ADDR2MASK_Pos) /*!< 0x00000700 */ +#define I2C_OADDR2_ADDR2MASK I2C_OADDR2_ADDR2MASK_Msk /*!< CNT[2:0] bits (Own address 2 bit mask) */ +#define I2C_OADDR2_ADDR2MASK_0 (0x01U << I2C_OADDR2_ADDR2MASK_Pos) /*!< 0x00000100 */ +#define I2C_OADDR2_ADDR2MASK_1 (0x02U << I2C_OADDR2_ADDR2MASK_Pos) /*!< 0x00000200 */ +#define I2C_OADDR2_ADDR2MASK_2 (0x04U << I2C_OADDR2_ADDR2MASK_Pos) /*!< 0x00000400 */ + +#define I2C_OADDR2_ADDR2EN_Pos (15U) +#define I2C_OADDR2_ADDR2EN_Msk (0x1U << I2C_OADDR2_ADDR2EN_Pos) /*!< 0x00008000 */ +#define I2C_OADDR2_ADDR2EN I2C_OADDR2_ADDR2EN_Msk /*!< Own Address 2 enable */ + +/***************** Bit definition for I2C_CLKCTRL register ******************/ +#define I2C_CLKCTRL_SCLL_Pos (0U) +#define I2C_CLKCTRL_SCLL_Msk (0xFFU << I2C_CLKCTRL_SCLL_Pos) /*!< 0x000000FF */ +#define I2C_CLKCTRL_SCLL I2C_CLKCTRL_SCLL_Msk /*!< SCL low level */ +#define I2C_CLKCTRL_SCLH_Pos (8U) +#define I2C_CLKCTRL_SCLH_Msk (0xFFU << I2C_CLKCTRL_SCLH_Pos) /*!< 0x0000FF00 */ +#define I2C_CLKCTRL_SCLH I2C_CLKCTRL_SCLH_Msk /*!< SCL high level */ +#define I2C_CLKCTRL_SDAD_Pos (16U) +#define I2C_CLKCTRL_SDAD_Msk (0xFU << I2C_CLKCTRL_SDAD_Pos) /*!< 0x000F0000 */ +#define I2C_CLKCTRL_SDAD I2C_CLKCTRL_SDAD_Msk /*!< SDA output delay */ +#define I2C_CLKCTRL_SCLD_Pos (20U) +#define I2C_CLKCTRL_SCLD_Msk (0xFU << I2C_CLKCTRL_SCLD_Pos) /*!< 0x00F00000 */ +#define I2C_CLKCTRL_SCLD I2C_CLKCTRL_SCLD_Msk /*!< SCL output delay */ +#define I2C_CLKCTRL_DIVH_Pos (24U) +#define I2C_CLKCTRL_DIVH_Msk (0xFU << I2C_CLKCTRL_DIVH_Pos) /*!< 0x0F000000 */ +#define I2C_CLKCTRL_DIVH I2C_CLKCTRL_DIVH_Msk /*!< High 4 bits of clock divider value */ +#define I2C_CLKCTRL_DIVL_Pos (28U) +#define I2C_CLKCTRL_DIVL_Msk (0xFU << I2C_CLKCTRL_DIVL_Pos) /*!< 0xF0000000 */ +#define I2C_CLKCTRL_DIVL I2C_CLKCTRL_DIVL_Msk /*!< Low 4 bits of clock divider value */ + +/***************** Bit definition for I2C_TIMEOUT register ******************/ +#define I2C_TIMEOUT_TOTIME_Pos (0U) +#define I2C_TIMEOUT_TOTIME_Msk (0xFFFU << I2C_TIMEOUT_TOTIME_Pos) /*!< 0x00000FFF */ +#define I2C_TIMEOUT_TOTIME I2C_TIMEOUT_TOTIME_Msk /*!< Clock timeout detection time */ +#define I2C_TIMEOUT_TOMODE_Pos (12U) +#define I2C_TIMEOUT_TOMODE_Msk (0x1U << I2C_TIMEOUT_TOMODE_Pos) /*!< 0x00001000 */ +#define I2C_TIMEOUT_TOMODE I2C_TIMEOUT_TOMODE_Msk /*!< Clock timeout detection mode */ +#define I2C_TIMEOUT_TOEN_Pos (15U) +#define I2C_TIMEOUT_TOEN_Msk (0x1U << I2C_TIMEOUT_TOEN_Pos) /*!< 0x00008000 */ +#define I2C_TIMEOUT_TOEN I2C_TIMEOUT_TOEN_Msk /*!< Detect clock low/high timeout enable */ +#define I2C_TIMEOUT_EXTTIME_Pos (16U) +#define I2C_TIMEOUT_EXTTIME_Msk (0xFFFU << I2C_TIMEOUT_EXTTIME_Pos) /*!< 0x0FFF0000 */ +#define I2C_TIMEOUT_EXTTIME I2C_TIMEOUT_EXTTIME_Msk /*!< Cumulative clock low extend timeout value */ +#define I2C_TIMEOUT_EXTEN_Pos (31U) +#define I2C_TIMEOUT_EXTEN_Msk (0x1U << I2C_TIMEOUT_EXTEN_Pos) /*!< 0x80000000 */ +#define I2C_TIMEOUT_EXTEN I2C_TIMEOUT_EXTEN_Msk /*!< Cumulative clock low extend timeout enable */ + +/******************* Bit definition for I2C_STS register ********************/ +#define I2C_STS_TDBE_Pos (0U) +#define I2C_STS_TDBE_Msk (0x1U << I2C_STS_TDBE_Pos) /*!< 0x00000001 */ +#define I2C_STS_TDBE I2C_STS_TDBE_Msk /*!< Transmit data buffer empty flag */ +#define I2C_STS_TDIS_Pos (1U) +#define I2C_STS_TDIS_Msk (0x1U << I2C_STS_TDIS_Pos) /*!< 0x00000002 */ +#define I2C_STS_TDIS I2C_STS_TDIS_Msk /*!< Transmit data interrupt status */ +#define I2C_STS_RDBF_Pos (2U) +#define I2C_STS_RDBF_Msk (0x1U << I2C_STS_RDBF_Pos) /*!< 0x00000004 */ +#define I2C_STS_RDBF I2C_STS_RDBF_Msk /*!< Receive data buffer full flag */ +#define I2C_STS_ADDRF_Pos (3U) +#define I2C_STS_ADDRF_Msk (0x1U << I2C_STS_ADDRF_Pos) /*!< 0x00000008 */ +#define I2C_STS_ADDRF I2C_STS_ADDRF_Msk /*!< 0 ~ 7 bit address match flag */ +#define I2C_STS_ACKFAILF_Pos (4U) +#define I2C_STS_ACKFAILF_Msk (0x1U << I2C_STS_ACKFAILF_Pos) /*!< 0x00000010 */ +#define I2C_STS_ACKFAILF I2C_STS_ACKFAILF_Msk /*!< Acknowledge failure flag */ +#define I2C_STS_STOPF_Pos (5U) +#define I2C_STS_STOPF_Msk (0x1U << I2C_STS_STOPF_Pos) /*!< 0x00000020 */ +#define I2C_STS_STOPF I2C_STS_STOPF_Msk /*!< Stop condition generation complete flag */ +#define I2C_STS_TDC_Pos (6U) +#define I2C_STS_TDC_Msk (0x1U << I2C_STS_TDC_Pos) /*!< 0x00000040 */ +#define I2C_STS_TDC I2C_STS_TDC_Msk /*!< Data transfer complete flag */ +#define I2C_STS_TCRLD_Pos (7U) +#define I2C_STS_TCRLD_Msk (0x1U << I2C_STS_TCRLD_Pos) /*!< 0x00000080 */ +#define I2C_STS_TCRLD I2C_STS_TCRLD_Msk /*!< Transmission is complete, waiting to load data */ +#define I2C_STS_BUSERR_Pos (8U) +#define I2C_STS_BUSERR_Msk (0x1U << I2C_STS_BUSERR_Pos) /*!< 0x00000100 */ +#define I2C_STS_BUSERR I2C_STS_BUSERR_Msk /*!< Bus error flag */ +#define I2C_STS_ARLOST_Pos (9U) +#define I2C_STS_ARLOST_Msk (0x1U << I2C_STS_ARLOST_Pos) /*!< 0x00000200 */ +#define I2C_STS_ARLOST I2C_STS_ARLOST_Msk /*!< Arbitration lost flag */ +#define I2C_STS_OUF_Pos (10U) +#define I2C_STS_OUF_Msk (0x1U << I2C_STS_OUF_Pos) /*!< 0x00000400 */ +#define I2C_STS_OUF I2C_STS_OUF_Msk /*!< Overflow or underflow flag */ +#define I2C_STS_PECERR_Pos (11U) +#define I2C_STS_PECERR_Msk (0x1U << I2C_STS_PECERR_Pos) /*!< 0x00000800 */ +#define I2C_STS_PECERR I2C_STS_PECERR_Msk /*!< PEC receive error flag */ +#define I2C_STS_TMOUT_Pos (12U) +#define I2C_STS_TMOUT_Msk (0x1U << I2C_STS_TMOUT_Pos) /*!< 0x00001000 */ +#define I2C_STS_TMOUT I2C_STS_TMOUT_Msk /*!< SMBus timeout flag */ +#define I2C_STS_ALERTF_Pos (13U) +#define I2C_STS_ALERTF_Msk (0x1U << I2C_STS_ALERTF_Pos) /*!< 0x00002000 */ +#define I2C_STS_ALERTF I2C_STS_ALERTF_Msk /*!< SMBus alert flag */ +#define I2C_STS_BUSYF_Pos (15U) +#define I2C_STS_BUSYF_Msk (0x1U << I2C_STS_BUSYF_Pos) /*!< 0x00008000 */ +#define I2C_STS_BUSYF I2C_STS_BUSYF_Msk /*!< Bus busy flag transmission mode */ +#define I2C_STS_SDIR_Pos (16U) +#define I2C_STS_SDIR_Msk (0x1U << I2C_STS_SDIR_Pos) /*!< 0x00010000 */ +#define I2C_STS_SDIR I2C_STS_SDIR_Msk /*!< Slave data transmit direction */ +#define I2C_STS_ADDR_Pos (17U) +#define I2C_STS_ADDR_Msk (0x7FU << I2C_STS_ADDR_Pos) /*!< 0x00FE0000 */ +#define I2C_STS_ADDR I2C_STS_ADDR_Msk /*!< Slave address matching value */ + +/******************* Bit definition for I2C_CLR register ********************/ +#define I2C_CLR_ADDRC_Pos (3U) +#define I2C_CLR_ADDRC_Msk (0x1U << I2C_CLR_ADDRC_Pos) /*!< 0x00000008 */ +#define I2C_CLR_ADDRC I2C_CLR_ADDRC_Msk /*!< Clear 0 ~ 7 bit address match flag */ +#define I2C_CLR_ACKFAILC_Pos (4U) +#define I2C_CLR_ACKFAILC_Msk (0x1U << I2C_CLR_ACKFAILC_Pos) /*!< 0x00000010 */ +#define I2C_CLR_ACKFAILC I2C_CLR_ACKFAILC_Msk /*!< Clear acknowledge failure flag */ +#define I2C_CLR_STOPC_Pos (5U) +#define I2C_CLR_STOPC_Msk (0x1U << I2C_CLR_STOPC_Pos) /*!< 0x00000020 */ +#define I2C_CLR_STOPC I2C_CLR_STOPC_Msk /*!< Clear stop condition generation complete flag */ +#define I2C_CLR_BUSERRC_Pos (8U) +#define I2C_CLR_BUSERRC_Msk (0x1U << I2C_CLR_BUSERRC_Pos) /*!< 0x00000100 */ +#define I2C_CLR_BUSERRC I2C_CLR_BUSERRC_Msk /*!< Clear bus error flag */ +#define I2C_CLR_ARLOSTC_Pos (9U) +#define I2C_CLR_ARLOSTC_Msk (0x1U << I2C_CLR_ARLOSTC_Pos) /*!< 0x00000200 */ +#define I2C_CLR_ARLOSTC I2C_CLR_ARLOSTC_Msk /*!< Clear arbitration lost flag */ +#define I2C_CLR_OUFC_Pos (10U) +#define I2C_CLR_OUFC_Msk (0x1U << I2C_CLR_OUFC_Pos) /*!< 0x00000400 */ +#define I2C_CLR_OUFC I2C_CLR_OUFC_Msk /*!< Clear overload / underload flag */ +#define I2C_CLR_PECERRC_Pos (11U) +#define I2C_CLR_PECERRC_Msk (0x1U << I2C_CLR_PECERRC_Pos) /*!< 0x00000800 */ +#define I2C_CLR_PECERRC I2C_CLR_PECERRC_Msk /*!< Clear PEC receive error flag */ +#define I2C_CLR_TMOUTC_Pos (12U) +#define I2C_CLR_TMOUTC_Msk (0x1U << I2C_CLR_TMOUTC_Pos) /*!< 0x00001000 */ +#define I2C_CLR_TMOUTC I2C_CLR_TMOUTC_Msk /*!< Clear SMBus timeout flag */ +#define I2C_CLR_ALERTC_Pos (13U) +#define I2C_CLR_ALERTC_Msk (0x1U << I2C_CLR_ALERTC_Pos) /*!< 0x00002000 */ +#define I2C_CLR_ALERTC I2C_CLR_ALERTC_Msk /*!< Clear SMBus alert flag */ + +/******************* Bit definition for I2C_PEC register ********************/ +#define I2C_PEC_PECVAL_Pos (0U) +#define I2C_PEC_PECVAL_Msk (0xFFU << I2C_PEC_PECVAL_Pos) /*!< 0x000000FF */ +#define I2C_PEC_PECVAL I2C_PEC_PECVAL_Msk /*!< PEC value */ + +/******************* Bit definition for I2C_RXDT register *******************/ +#define I2C_RXDT_DT_Pos (0U) +#define I2C_RXDT_DT_Msk (0xFFU << I2C_RXDT_DT_Pos) /*!< 0x000000FF */ +#define I2C_RXDT_DT I2C_RXDT_DT_Msk /*!< Receive data register */ + +/******************* Bit definition for I2C_TXDT register *******************/ +#define I2C_TXDT_DT_Pos (0U) +#define I2C_TXDT_DT_Msk (0xFFU << I2C_TXDT_DT_Pos) /*!< 0x000000FF */ +#define I2C_TXDT_DT I2C_TXDT_DT_Msk /*!< Transmit data register */ + +/******************************************************************************/ +/* */ +/* Universal synchronous/asynchronous receiver/transmitter (USART) */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for USART_STS register *******************/ +#define USART_STS_PERR_Pos (0U) +#define USART_STS_PERR_Msk (0x1U << USART_STS_PERR_Pos) /*!< 0x00000001 */ +#define USART_STS_PERR USART_STS_PERR_Msk /*!< Parity error */ +#define USART_STS_FERR_Pos (1U) +#define USART_STS_FERR_Msk (0x1U << USART_STS_FERR_Pos) /*!< 0x00000002 */ +#define USART_STS_FERR USART_STS_FERR_Msk /*!< Framing error */ +#define USART_STS_NERR_Pos (2U) +#define USART_STS_NERR_Msk (0x1U << USART_STS_NERR_Pos) /*!< 0x00000004 */ +#define USART_STS_NERR USART_STS_NERR_Msk /*!< Noise error */ +#define USART_STS_ROERR_Pos (3U) +#define USART_STS_ROERR_Msk (0x1U << USART_STS_ROERR_Pos) /*!< 0x00000008 */ +#define USART_STS_ROERR USART_STS_ROERR_Msk /*!< Receiver overflow error */ +#define USART_STS_IDLEF_Pos (4U) +#define USART_STS_IDLEF_Msk (0x1U << USART_STS_IDLEF_Pos) /*!< 0x00000010 */ +#define USART_STS_IDLEF USART_STS_IDLEF_Msk /*!< Idle flag */ +#define USART_STS_RDBF_Pos (5U) +#define USART_STS_RDBF_Msk (0x1U << USART_STS_RDBF_Pos) /*!< 0x00000020 */ +#define USART_STS_RDBF USART_STS_RDBF_Msk /*!< Receive data buffer full */ +#define USART_STS_TDC_Pos (6U) +#define USART_STS_TDC_Msk (0x1U << USART_STS_TDC_Pos) /*!< 0x00000040 */ +#define USART_STS_TDC USART_STS_TDC_Msk /*!< Transmit data complete */ +#define USART_STS_TDBE_Pos (7U) +#define USART_STS_TDBE_Msk (0x1U << USART_STS_TDBE_Pos) /*!< 0x00000080 */ +#define USART_STS_TDBE USART_STS_TDBE_Msk /*!< Transmit data buffer empty */ +#define USART_STS_BFF_Pos (8U) +#define USART_STS_BFF_Msk (0x1U << USART_STS_BFF_Pos) /*!< 0x00000100 */ +#define USART_STS_BFF USART_STS_BFF_Msk /*!< Break frame flag */ +#define USART_STS_CTSCF_Pos (9U) +#define USART_STS_CTSCF_Msk (0x1U << USART_STS_CTSCF_Pos) /*!< 0x00000200 */ +#define USART_STS_CTSCF USART_STS_CTSCF_Msk /*!< CTS change flag */ +#define USART_STS_RTODF_Pos (11U) +#define USART_STS_RTODF_Msk (0x1U << USART_STS_RTODF_Pos) /*!< 0x00000800 */ +#define USART_STS_RTODF USART_STS_RTODF_Msk /*!< Receiver timeout detection flag */ +#define USART_STS_CMDF_Pos (17U) +#define USART_STS_CMDF_Msk (0x1U << USART_STS_CMDF_Pos) /*!< 0x00020000 */ +#define USART_STS_CMDF USART_STS_CMDF_Msk /*!< Byte match detection flag */ + +/******************* Bit definition for USART_DT register *******************/ +#define USART_DT_DT_Pos (0U) +#define USART_DT_DT_Msk (0x1FFU << USART_DT_DT_Pos) /*!< 0x000001FF */ +#define USART_DT_DT USART_DT_DT_Msk /*!< Data value */ + +/***************** Bit definition for USART_BAUDR register ******************/ +#define USART_BAUDR_DIV_Pos (0U) +#define USART_BAUDR_DIV_Msk (0xFFFFU << USART_BAUDR_DIV_Pos) /*!< 0x0000FFFF */ +#define USART_BAUDR_DIV USART_BAUDR_DIV_Msk /*!< Divider */ + +/***************** Bit definition for USART_CTRL1 register ******************/ +#define USART_CTRL1_SBF_Pos (0U) +#define USART_CTRL1_SBF_Msk (0x1U << USART_CTRL1_SBF_Pos) /*!< 0x00000001 */ +#define USART_CTRL1_SBF USART_CTRL1_SBF_Msk /*!< Send break frame */ +#define USART_CTRL1_RM_Pos (1U) +#define USART_CTRL1_RM_Msk (0x1U << USART_CTRL1_RM_Pos) /*!< 0x00000002 */ +#define USART_CTRL1_RM USART_CTRL1_RM_Msk /*!< Receiver mute */ +#define USART_CTRL1_REN_Pos (2U) +#define USART_CTRL1_REN_Msk (0x1U << USART_CTRL1_REN_Pos) /*!< 0x00000004 */ +#define USART_CTRL1_REN USART_CTRL1_REN_Msk /*!< Receiver enable */ +#define USART_CTRL1_TEN_Pos (3U) +#define USART_CTRL1_TEN_Msk (0x1U << USART_CTRL1_TEN_Pos) /*!< 0x00000008 */ +#define USART_CTRL1_TEN USART_CTRL1_TEN_Msk /*!< Transmitter enable */ +#define USART_CTRL1_IDLEIEN_Pos (4U) +#define USART_CTRL1_IDLEIEN_Msk (0x1U << USART_CTRL1_IDLEIEN_Pos) /*!< 0x00000010 */ +#define USART_CTRL1_IDLEIEN USART_CTRL1_IDLEIEN_Msk /*!< IDLE interrupt enable */ +#define USART_CTRL1_RDBFIEN_Pos (5U) +#define USART_CTRL1_RDBFIEN_Msk (0x1U << USART_CTRL1_RDBFIEN_Pos) /*!< 0x00000020 */ +#define USART_CTRL1_RDBFIEN USART_CTRL1_RDBFIEN_Msk /*!< RDBF interrupt enable */ +#define USART_CTRL1_TDCIEN_Pos (6U) +#define USART_CTRL1_TDCIEN_Msk (0x1U << USART_CTRL1_TDCIEN_Pos) /*!< 0x00000040 */ +#define USART_CTRL1_TDCIEN USART_CTRL1_TDCIEN_Msk /*!< TDC interrupt enable */ +#define USART_CTRL1_TDBEIEN_Pos (7U) +#define USART_CTRL1_TDBEIEN_Msk (0x1U << USART_CTRL1_TDBEIEN_Pos) /*!< 0x00000080 */ +#define USART_CTRL1_TDBEIEN USART_CTRL1_TDBEIEN_Msk /*!< TDBE interrupt enable */ +#define USART_CTRL1_PERRIEN_Pos (8U) +#define USART_CTRL1_PERRIEN_Msk (0x1U << USART_CTRL1_PERRIEN_Pos) /*!< 0x00000100 */ +#define USART_CTRL1_PERRIEN USART_CTRL1_PERRIEN_Msk /*!< PERR interrupt enable */ +#define USART_CTRL1_PSEL_Pos (9U) +#define USART_CTRL1_PSEL_Msk (0x1U << USART_CTRL1_PSEL_Pos) /*!< 0x00000200 */ +#define USART_CTRL1_PSEL USART_CTRL1_PSEL_Msk /*!< Parity selection */ +#define USART_CTRL1_PEN_Pos (10U) +#define USART_CTRL1_PEN_Msk (0x1U << USART_CTRL1_PEN_Pos) /*!< 0x00000400 */ +#define USART_CTRL1_PEN USART_CTRL1_PEN_Msk /*!< Parity enable */ +#define USART_CTRL1_WUM_Pos (11U) +#define USART_CTRL1_WUM_Msk (0x1U << USART_CTRL1_WUM_Pos) /*!< 0x00000800 */ +#define USART_CTRL1_WUM USART_CTRL1_WUM_Msk /*!< Wakeup mode */ +#define USART_CTRL1_DBN0_Pos (12U) +#define USART_CTRL1_DBN0_Msk (0x1U << USART_CTRL1_DBN0_Pos) /*!< 0x00001000 */ +#define USART_CTRL1_DBN0 USART_CTRL1_DBN0_Msk /*!< Data bit num 0 */ +#define USART_CTRL1_UEN_Pos (13U) +#define USART_CTRL1_UEN_Msk (0x1U << USART_CTRL1_UEN_Pos) /*!< 0x00002000 */ +#define USART_CTRL1_UEN USART_CTRL1_UEN_Msk /*!< USART enable */ +#define USART_CTRL1_CMDIE_Pos (14U) +#define USART_CTRL1_CMDIE_Msk (0x1U << USART_CTRL1_CMDIE_Pos) /*!< 0x00004000 */ +#define USART_CTRL1_CMDIE USART_CTRL1_CMDIE_Msk /*!< Character match detection interrupt enable */ +#define USART_CTRL1_TCDT_Pos (16U) +#define USART_CTRL1_TCDT_Msk (0x1FU << USART_CTRL1_TCDT_Pos) /*!< 0x001F0000 */ +#define USART_CTRL1_TCDT USART_CTRL1_TCDT_Msk /*!< Transmit complete delay time */ +#define USART_CTRL1_TSDT_Pos (21U) +#define USART_CTRL1_TSDT_Msk (0x1FU << USART_CTRL1_TSDT_Pos) /*!< 0x03E00000 */ +#define USART_CTRL1_TSDT USART_CTRL1_TSDT_Msk /*!< Transmit start delay time */ +#define USART_CTRL1_RETODIE_Pos (26U) +#define USART_CTRL1_RETODIE_Msk (0x1U << USART_CTRL1_RETODIE_Pos) /*!< 0x04000000 */ +#define USART_CTRL1_RETODIE USART_CTRL1_RETODIE_Msk /*!< Receiver timeout detection interrupt enable */ +#define USART_CTRL1_RTODEN_Pos (27U) +#define USART_CTRL1_RTODEN_Msk (0x1U << USART_CTRL1_RTODEN_Pos) /*!< 0x08000000 */ +#define USART_CTRL1_RTODEN USART_CTRL1_RTODEN_Msk /*!< Receiver timeout detection enable */ +#define USART_CTRL1_DBN1_Pos (28U) +#define USART_CTRL1_DBN1_Msk (0x1U << USART_CTRL1_DBN1_Pos) /*!< 0x10000000 */ +#define USART_CTRL1_DBN1 USART_CTRL1_DBN1_Msk /*!< Data bit num 1 */ + +/***************** Bit definition for USART_CTRL2 register ******************/ +#define USART_CTRL2_IDL_Pos (0U) +#define USART_CTRL2_IDL_Msk (0xFU << USART_CTRL2_IDL_Pos) /*!< 0x0000000F */ +#define USART_CTRL2_IDL USART_CTRL2_IDL_Msk /*!< USART identification low */ +#define USART_CTRL2_IDBN_Pos (4U) +#define USART_CTRL2_IDBN_Msk (0x1U << USART_CTRL2_IDBN_Pos) /*!< 0x00000010 */ +#define USART_CTRL2_IDBN USART_CTRL2_IDBN_Msk /*!< Identification bit number */ +#define USART_CTRL2_BFBN_Pos (5U) +#define USART_CTRL2_BFBN_Msk (0x1U << USART_CTRL2_BFBN_Pos) /*!< 0x00000020 */ +#define USART_CTRL2_BFBN USART_CTRL2_BFBN_Msk /*!< Break frame bit num */ +#define USART_CTRL2_BFIEN_Pos (6U) +#define USART_CTRL2_BFIEN_Msk (0x1U << USART_CTRL2_BFIEN_Pos) /*!< 0x00000040 */ +#define USART_CTRL2_BFIEN USART_CTRL2_BFIEN_Msk /*!< Break frame interrupt enable */ +#define USART_CTRL2_LBCP_Pos (8U) +#define USART_CTRL2_LBCP_Msk (0x1U << USART_CTRL2_LBCP_Pos) /*!< 0x00000100 */ +#define USART_CTRL2_LBCP USART_CTRL2_LBCP_Msk /*!< Last bit clock pulse */ +#define USART_CTRL2_CLKPHA_Pos (9U) +#define USART_CTRL2_CLKPHA_Msk (0x1U << USART_CTRL2_CLKPHA_Pos) /*!< 0x00000200 */ +#define USART_CTRL2_CLKPHA USART_CTRL2_CLKPHA_Msk /*!< Clock phase */ +#define USART_CTRL2_CLKPOL_Pos (10U) +#define USART_CTRL2_CLKPOL_Msk (0x1U << USART_CTRL2_CLKPOL_Pos) /*!< 0x00000400 */ +#define USART_CTRL2_CLKPOL USART_CTRL2_CLKPOL_Msk /*!< Clock polarity */ +#define USART_CTRL2_CLKEN_Pos (11U) +#define USART_CTRL2_CLKEN_Msk (0x1U << USART_CTRL2_CLKEN_Pos) /*!< 0x00000800 */ +#define USART_CTRL2_CLKEN USART_CTRL2_CLKEN_Msk /*!< Clock enable */ + +/*!< STOPBN configuration */ +#define USART_CTRL2_STOPBN_Pos (12U) +#define USART_CTRL2_STOPBN_Msk (0x3U << USART_CTRL2_STOPBN_Pos) /*!< 0x00003000 */ +#define USART_CTRL2_STOPBN USART_CTRL2_STOPBN_Msk /*!< STOPBN[1:0] bits (STOP bit num) */ +#define USART_CTRL2_STOPBN_0 (0x1U << USART_CTRL2_STOPBN_Pos) /*!< 0x00001000 */ +#define USART_CTRL2_STOPBN_1 (0x2U << USART_CTRL2_STOPBN_Pos) /*!< 0x00002000 */ + +#define USART_CTRL2_LINEN_Pos (14U) +#define USART_CTRL2_LINEN_Msk (0x1U << USART_CTRL2_LINEN_Pos) /*!< 0x00004000 */ +#define USART_CTRL2_LINEN USART_CTRL2_LINEN_Msk /*!< LIN mode enable */ +#define USART_CTRL2_TRPSWAP_Pos (15U) +#define USART_CTRL2_TRPSWAP_Msk (0x1U << USART_CTRL2_TRPSWAP_Pos) /*!< 0x00008000 */ +#define USART_CTRL2_TRPSWAP USART_CTRL2_TRPSWAP_Msk /*!< Transmit/receive pin swap */ +#define USART_CTRL2_RXREV_Pos (16U) +#define USART_CTRL2_RXREV_Msk (0x1U << USART_CTRL2_RXREV_Pos) /*!< 0x00010000 */ +#define USART_CTRL2_RXREV USART_CTRL2_RXREV_Msk /*!< RX polarity reverse */ +#define USART_CTRL2_TXREV_Pos (17U) +#define USART_CTRL2_TXREV_Msk (0x1U << USART_CTRL2_TXREV_Pos) /*!< 0x00020000 */ +#define USART_CTRL2_TXREV USART_CTRL2_TXREV_Msk /*!< TX polarity reverse */ +#define USART_CTRL2_DTREV_Pos (18U) +#define USART_CTRL2_DTREV_Msk (0x1U << USART_CTRL2_DTREV_Pos) /*!< 0x00040000 */ +#define USART_CTRL2_DTREV USART_CTRL2_DTREV_Msk /*!< DT register polarity reverse */ +#define USART_CTRL2_MTF_Pos (19U) +#define USART_CTRL2_MTF_Msk (0x1U << USART_CTRL2_MTF_Pos) /*!< 0x00080000 */ +#define USART_CTRL2_MTF USART_CTRL2_MTF_Msk /*!< MSB transmit first */ +#define USART_CTRL2_IDH_Pos (28U) +#define USART_CTRL2_IDH_Msk (0xFU << USART_CTRL2_IDH_Pos) /*!< 0xF0000000 */ +#define USART_CTRL2_IDH USART_CTRL2_IDH_Msk /*!< USART identification high */ + +/***************** Bit definition for USART_CTRL3 register ******************/ +#define USART_CTRL3_ERRIEN_Pos (0U) +#define USART_CTRL3_ERRIEN_Msk (0x1U << USART_CTRL3_ERRIEN_Pos) /*!< 0x00000001 */ +#define USART_CTRL3_ERRIEN USART_CTRL3_ERRIEN_Msk /*!< Error interrupt enable */ +#define USART_CTRL3_IRDAEN_Pos (1U) +#define USART_CTRL3_IRDAEN_Msk (0x1U << USART_CTRL3_IRDAEN_Pos) /*!< 0x00000002 */ +#define USART_CTRL3_IRDAEN USART_CTRL3_IRDAEN_Msk /*!< IrDA enable */ +#define USART_CTRL3_IRDALP_Pos (2U) +#define USART_CTRL3_IRDALP_Msk (0x1U << USART_CTRL3_IRDALP_Pos) /*!< 0x00000004 */ +#define USART_CTRL3_IRDALP USART_CTRL3_IRDALP_Msk /*!< IrDA low-power mode */ +#define USART_CTRL3_SLBEN_Pos (3U) +#define USART_CTRL3_SLBEN_Msk (0x1U << USART_CTRL3_SLBEN_Pos) /*!< 0x00000008 */ +#define USART_CTRL3_SLBEN USART_CTRL3_SLBEN_Msk /*!< Single-wire bidirectional half-duplex enable */ +#define USART_CTRL3_SCNACKEN_Pos (4U) +#define USART_CTRL3_SCNACKEN_Msk (0x1U << USART_CTRL3_SCNACKEN_Pos) /*!< 0x00000010 */ +#define USART_CTRL3_SCNACKEN USART_CTRL3_SCNACKEN_Msk /*!< Smart Card NACK enable */ +#define USART_CTRL3_SCMEN_Pos (5U) +#define USART_CTRL3_SCMEN_Msk (0x1U << USART_CTRL3_SCMEN_Pos) /*!< 0x00000020 */ +#define USART_CTRL3_SCMEN USART_CTRL3_SCMEN_Msk /*!< Smart Card mode enable */ +#define USART_CTRL3_DMAREN_Pos (6U) +#define USART_CTRL3_DMAREN_Msk (0x1U << USART_CTRL3_DMAREN_Pos) /*!< 0x00000040 */ +#define USART_CTRL3_DMAREN USART_CTRL3_DMAREN_Msk /*!< DMA receiver enable */ +#define USART_CTRL3_DMATEN_Pos (7U) +#define USART_CTRL3_DMATEN_Msk (0x1U << USART_CTRL3_DMATEN_Pos) /*!< 0x00000080 */ +#define USART_CTRL3_DMATEN USART_CTRL3_DMATEN_Msk /*!< DMA transmitter enable */ +#define USART_CTRL3_RTSEN_Pos (8U) +#define USART_CTRL3_RTSEN_Msk (0x1U << USART_CTRL3_RTSEN_Pos) /*!< 0x00000100 */ +#define USART_CTRL3_RTSEN USART_CTRL3_RTSEN_Msk /*!< RTS enable */ +#define USART_CTRL3_CTSEN_Pos (9U) +#define USART_CTRL3_CTSEN_Msk (0x1U << USART_CTRL3_CTSEN_Pos) /*!< 0x00000200 */ +#define USART_CTRL3_CTSEN USART_CTRL3_CTSEN_Msk /*!< CTS enable */ +#define USART_CTRL3_CTSCFIEN_Pos (10U) +#define USART_CTRL3_CTSCFIEN_Msk (0x1U << USART_CTRL3_CTSCFIEN_Pos) /*!< 0x00000400 */ +#define USART_CTRL3_CTSCFIEN USART_CTRL3_CTSCFIEN_Msk /*!< CTSCF interrupt enable */ +#define USART_CTRL3_RS485EN_Pos (14U) +#define USART_CTRL3_RS485EN_Msk (0x1U << USART_CTRL3_RS485EN_Pos) /*!< 0x00004000 */ +#define USART_CTRL3_RS485EN USART_CTRL3_RS485EN_Msk /*!< RS485 enable */ +#define USART_CTRL3_DEP_Pos (15U) +#define USART_CTRL3_DEP_Msk (0x1U << USART_CTRL3_DEP_Pos) /*!< 0x00008000 */ +#define USART_CTRL3_DEP USART_CTRL3_DEP_Msk /*!< DE polarity selection */ + +/****************** Bit definition for USART_GDIV register ******************/ +/*!< ISDIV configuration */ +#define USART_GDIV_ISDIV_Pos (0U) +#define USART_GDIV_ISDIV_Msk (0xFFU << USART_GDIV_ISDIV_Pos) /*!< 0x000000FF */ +#define USART_GDIV_ISDIV USART_GDIV_ISDIV_Msk /*!< ISDIV[7:0] bits (IrDA/Smart Card division) */ +#define USART_GDIV_ISDIV_0 (0x01U << USART_GDIV_ISDIV_Pos) /*!< 0x00000001 */ +#define USART_GDIV_ISDIV_1 (0x02U << USART_GDIV_ISDIV_Pos) /*!< 0x00000002 */ +#define USART_GDIV_ISDIV_2 (0x04U << USART_GDIV_ISDIV_Pos) /*!< 0x00000004 */ +#define USART_GDIV_ISDIV_3 (0x08U << USART_GDIV_ISDIV_Pos) /*!< 0x00000008 */ +#define USART_GDIV_ISDIV_4 (0x10U << USART_GDIV_ISDIV_Pos) /*!< 0x00000010 */ +#define USART_GDIV_ISDIV_5 (0x20U << USART_GDIV_ISDIV_Pos) /*!< 0x00000020 */ +#define USART_GDIV_ISDIV_6 (0x40U << USART_GDIV_ISDIV_Pos) /*!< 0x00000040 */ +#define USART_GDIV_ISDIV_7 (0x80U << USART_GDIV_ISDIV_Pos) /*!< 0x00000080 */ + +#define USART_GDIV_SCGT_Pos (8U) +#define USART_GDIV_SCGT_Msk (0xFFU << USART_GDIV_SCGT_Pos) /*!< 0x0000FF00 */ +#define USART_GDIV_SCGT USART_GDIV_SCGT_Msk /*!< Smart Card guard time value */ + +/****************** Bit definition for USART_RTOV register ******************/ +#define USART_RTOV_RTOV_Pos (0U) +#define USART_RTOV_RTOV_Msk (0xFFFFFFU << USART_RTOV_RTOV_Pos) /*!< 0x00FFFFFF */ +#define USART_RTOV_RTOV USART_RTOV_RTOV_Msk /*!< Receiver timeout value */ + +/****************** Bit definition for USART_IFC register *******************/ +#define USART_IFC_RTODFC_Pos (11U) +#define USART_IFC_RTODFC_Msk (0x1U << USART_IFC_RTODFC_Pos) /*!< 0x00000800 */ +#define USART_IFC_RTODFC USART_IFC_RTODFC_Msk /*!< Receiver timeout detection flag clear */ +#define USART_IFC_CMDFC_Pos (17U) +#define USART_IFC_CMDFC_Msk (0x1U << USART_IFC_CMDFC_Pos) /*!< 0x00020000 */ +#define USART_IFC_CMDFC USART_IFC_CMDFC_Msk /*!< Character match detection flag clear */ + +/******************************************************************************/ +/* */ +/* Serial peripheral interface (SPI) */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for SPI_CTRL1 register *******************/ +#define SPI_CTRL1_CLKPHA_Pos (0U) +#define SPI_CTRL1_CLKPHA_Msk (0x1U << SPI_CTRL1_CLKPHA_Pos) /*!< 0x00000001 */ +#define SPI_CTRL1_CLKPHA SPI_CTRL1_CLKPHA_Msk /*!< Clock phase */ +#define SPI_CTRL1_CLKPOL_Pos (1U) +#define SPI_CTRL1_CLKPOL_Msk (0x1U << SPI_CTRL1_CLKPOL_Pos) /*!< 0x00000002 */ +#define SPI_CTRL1_CLKPOL SPI_CTRL1_CLKPOL_Msk /*!< Clock polarity */ +#define SPI_CTRL1_MSTEN_Pos (2U) +#define SPI_CTRL1_MSTEN_Msk (0x1U << SPI_CTRL1_MSTEN_Pos) /*!< 0x00000004 */ +#define SPI_CTRL1_MSTEN SPI_CTRL1_MSTEN_Msk /*!< Master enable */ + +/*!< MDIV configuration */ +#define SPI_CTRL1_MDIV_Msk ((SPI_CTRL2_MDIV) | (0x7U << 3) /*!< 0x00000138 */ +#define SPI_CTRL1_MDIV SPI_CTRL1_MDIV_Msk /*!< MDIV[3:0] bits (Master clock frequency division) */ +#define SPI_CTRL1_MDIV_0 (0x1U << 3) /*!< 0x00000008 */ +#define SPI_CTRL1_MDIV_1 (0x2U << 3) /*!< 0x00000010 */ +#define SPI_CTRL1_MDIV_2 (0x4U << 3) /*!< 0x00000020 */ +#define SPI_CTRL1_MDIV_3 SPI_CTRL2_MDIV /*!< 0x00000100 */ + +#define SPI_CTRL1_SPIEN_Pos (6U) +#define SPI_CTRL1_SPIEN_Msk (0x1U << SPI_CTRL1_SPIEN_Pos) /*!< 0x00000040 */ +#define SPI_CTRL1_SPIEN SPI_CTRL1_SPIEN_Msk /*!< SPI enable */ +#define SPI_CTRL1_LTF_Pos (7U) +#define SPI_CTRL1_LTF_Msk (0x1U << SPI_CTRL1_LTF_Pos) /*!< 0x00000080 */ +#define SPI_CTRL1_LTF SPI_CTRL1_LTF_Msk /*!< LSB transmit first */ +#define SPI_CTRL1_SWCSIL_Pos (8U) +#define SPI_CTRL1_SWCSIL_Msk (0x1U << SPI_CTRL1_SWCSIL_Pos) /*!< 0x00000100 */ +#define SPI_CTRL1_SWCSIL SPI_CTRL1_SWCSIL_Msk /*!< Software CS internal level */ +#define SPI_CTRL1_SWCSEN_Pos (9U) +#define SPI_CTRL1_SWCSEN_Msk (0x1U << SPI_CTRL1_SWCSEN_Pos) /*!< 0x00000200 */ +#define SPI_CTRL1_SWCSEN SPI_CTRL1_SWCSEN_Msk /*!< Software CS enable */ +#define SPI_CTRL1_ORA_Pos (10U) +#define SPI_CTRL1_ORA_Msk (0x1U << SPI_CTRL1_ORA_Pos) /*!< 0x00000400 */ +#define SPI_CTRL1_ORA SPI_CTRL1_ORA_Msk /*!< Receive-only active */ +#define SPI_CTRL1_FBN_Pos (11U) +#define SPI_CTRL1_FBN_Msk (0x1U << SPI_CTRL1_FBN_Pos) /*!< 0x00000800 */ +#define SPI_CTRL1_FBN SPI_CTRL1_FBN_Msk /*!< Frame bit num */ +#define SPI_CTRL1_NTC_Pos (12U) +#define SPI_CTRL1_NTC_Msk (0x1U << SPI_CTRL1_NTC_Pos) /*!< 0x00001000 */ +#define SPI_CTRL1_NTC SPI_CTRL1_NTC_Msk /*!< Transmit CRC next */ +#define SPI_CTRL1_CCEN_Pos (13U) +#define SPI_CTRL1_CCEN_Msk (0x1U << SPI_CTRL1_CCEN_Pos) /*!< 0x00002000 */ +#define SPI_CTRL1_CCEN SPI_CTRL1_CCEN_Msk /*!< RC calculation enable */ +#define SPI_CTRL1_SLBTD_Pos (14U) +#define SPI_CTRL1_SLBTD_Msk (0x1U << SPI_CTRL1_SLBTD_Pos) /*!< 0x00004000 */ +#define SPI_CTRL1_SLBTD SPI_CTRL1_SLBTD_Msk /*!< Single line bidirectional half-duplex transmission direction */ +#define SPI_CTRL1_SLBEN_Pos (15U) +#define SPI_CTRL1_SLBEN_Msk (0x1U << SPI_CTRL1_SLBEN_Pos) /*!< 0x00008000 */ +#define SPI_CTRL1_SLBEN SPI_CTRL1_SLBEN_Msk /*!< Single line bidirectional half-duplex enable */ + +/****************** Bit definition for SPI_CTRL2 register *******************/ +#define SPI_CTRL2_DMAREN_Pos (0U) +#define SPI_CTRL2_DMAREN_Msk (0x1U << SPI_CTRL2_DMAREN_Pos) /*!< 0x00000001 */ +#define SPI_CTRL2_DMAREN SPI_CTRL2_DMAREN_Msk /*!< DMA receive enable */ +#define SPI_CTRL2_DMATEN_Pos (1U) +#define SPI_CTRL2_DMATEN_Msk (0x1U << SPI_CTRL2_DMATEN_Pos) /*!< 0x00000002 */ +#define SPI_CTRL2_DMATEN SPI_CTRL2_DMATEN_Msk /*!< DMA transmit enable */ +#define SPI_CTRL2_HWCSOE_Pos (2U) +#define SPI_CTRL2_HWCSOE_Msk (0x1U << SPI_CTRL2_HWCSOE_Pos) /*!< 0x00000004 */ +#define SPI_CTRL2_HWCSOE SPI_CTRL2_HWCSOE_Msk /*!< Hardware CS output enable */ +#define SPI_CTRL2_TIEN_Pos (4U) +#define SPI_CTRL2_TIEN_Msk (0x1U << SPI_CTRL2_TIEN_Pos) /*!< 0x00000010 */ +#define SPI_CTRL2_TIEN SPI_CTRL2_TIEN_Msk /*!< TI mode enable */ +#define SPI_CTRL2_ERRIE_Pos (5U) +#define SPI_CTRL2_ERRIE_Msk (0x1U << SPI_CTRL2_ERRIE_Pos) /*!< 0x00000020 */ +#define SPI_CTRL2_ERRIE SPI_CTRL2_ERRIE_Msk /*!< Error interrupt enable */ +#define SPI_CTRL2_RDBFIE_Pos (6U) +#define SPI_CTRL2_RDBFIE_Msk (0x1U << SPI_CTRL2_RDBFIE_Pos) /*!< 0x00000040 */ +#define SPI_CTRL2_RDBFIE SPI_CTRL2_RDBFIE_Msk /*!< Receive data buffer full interrupt enable */ +#define SPI_CTRL2_TDBEIE_Pos (7U) +#define SPI_CTRL2_TDBEIE_Msk (0x1U << SPI_CTRL2_TDBEIE_Pos) /*!< 0x00000080 */ +#define SPI_CTRL2_TDBEIE SPI_CTRL2_TDBEIE_Msk /*!< Transmit data buffer empty interrupt enable */ +#define SPI_CTRL2_MDIV_Pos (8U) +#define SPI_CTRL2_MDIV_Msk (0x1U << SPI_CTRL2_MDIV_Pos) /*!< 0x00000100 */ +#define SPI_CTRL2_MDIV SPI_CTRL2_MDIV_Msk /*!< Master clock frequency division */ +#define SPI_CTRL2_MDIV3EN_Pos (9U) +#define SPI_CTRL2_MDIV3EN_Msk (0x1U << SPI_CTRL2_MDIV3EN_Pos) /*!< 0x00000200 */ +#define SPI_CTRL2_MDIV3EN SPI_CTRL2_MDIV3EN_Msk /*!< Master clock frequency divided by 3 enable */ + +/******************* Bit definition for SPI_STS register ********************/ +#define SPI_STS_RDBF_Pos (0U) +#define SPI_STS_RDBF_Msk (0x1U << SPI_STS_RDBF_Pos) /*!< 0x00000001 */ +#define SPI_STS_RDBF SPI_STS_RDBF_Msk /*!< Receive data buffer full */ +#define SPI_STS_TDBE_Pos (1U) +#define SPI_STS_TDBE_Msk (0x1U << SPI_STS_TDBE_Pos) /*!< 0x00000002 */ +#define SPI_STS_TDBE SPI_STS_TDBE_Msk /*!< Transmit data buffer empty */ +#define SPI_STS_ACS_Pos (2U) +#define SPI_STS_ACS_Msk (0x1U << SPI_STS_ACS_Pos) /*!< 0x00000004 */ +#define SPI_STS_ACS SPI_STS_ACS_Msk /*!< Audio channel state */ +#define SPI_STS_TUERR_Pos (3U) +#define SPI_STS_TUERR_Msk (0x1U << SPI_STS_TUERR_Pos) /*!< 0x00000008 */ +#define SPI_STS_TUERR SPI_STS_TUERR_Msk /*!< Transmitter underload error */ +#define SPI_STS_CCERR_Pos (4U) +#define SPI_STS_CCERR_Msk (0x1U << SPI_STS_CCERR_Pos) /*!< 0x00000010 */ +#define SPI_STS_CCERR SPI_STS_CCERR_Msk /*!< CRC error */ +#define SPI_STS_MMERR_Pos (5U) +#define SPI_STS_MMERR_Msk (0x1U << SPI_STS_MMERR_Pos) /*!< 0x00000020 */ +#define SPI_STS_MMERR SPI_STS_MMERR_Msk /*!< Master mode error */ +#define SPI_STS_ROERR_Pos (6U) +#define SPI_STS_ROERR_Msk (0x1U << SPI_STS_ROERR_Pos) /*!< 0x00000040 */ +#define SPI_STS_ROERR SPI_STS_ROERR_Msk /*!< Receiver overflow error */ +#define SPI_STS_BF_Pos (7U) +#define SPI_STS_BF_Msk (0x1U << SPI_STS_BF_Pos) /*!< 0x00000080 */ +#define SPI_STS_BF SPI_STS_BF_Msk /*!< Busy flag */ +#define SPI_STS_CSPAS_Pos (8U) +#define SPI_STS_CSPAS_Msk (0x1U << SPI_STS_CSPAS_Pos) /*!< 0x00000100 */ +#define SPI_STS_CSPAS SPI_STS_CSPAS_Msk /*!< CS pulse abnormal setting flag */ + +/******************** Bit definition for SPI_DT register ********************/ +#define SPI_DT_DT_Pos (0U) +#define SPI_DT_DT_Msk (0xFFFFU << SPI_DT_DT_Pos) /*!< 0x0000FFFF */ +#define SPI_DT_DT SPI_DT_DT_Msk /*!< Data value */ + +/******************* Bit definition for SPI_CPOLY register ******************/ +#define SPI_CPOLY_CPOLY_Pos (0U) +#define SPI_CPOLY_CPOLY_Msk (0xFFFFU << SPI_CPOLY_CPOLY_Pos) /*!< 0x0000FFFF */ +#define SPI_CPOLY_CPOLY SPI_CPOLY_CPOLY_Msk /*!< CRC polynomial */ + +/******************* Bit definition for SPI_RCRC register *******************/ +#define SPI_RCRC_RCRC_Pos (0U) +#define SPI_RCRC_RCRC_Msk (0xFFFFU << SPI_RCRC_RCRC_Pos) /*!< 0x0000FFFF */ +#define SPI_RCRC_RCRC SPI_RCRC_RCRC_Msk /*!< Receive CRC */ + +/******************* Bit definition for SPI_TCRC register *******************/ +#define SPI_TCRC_TCRC_Pos (0U) +#define SPI_TCRC_TCRC_Msk (0xFFFFU << SPI_TCRC_TCRC_Pos) /*!< 0x0000FFFF */ +#define SPI_TCRC_TCRC SPI_TCRC_TCRC_Msk /*!< Transmit CRC */ + +/***************** Bit definition for SPI_I2SCTRL register ******************/ +#define SPI_I2SCTRL_I2SCBN_Pos (0U) +#define SPI_I2SCTRL_I2SCBN_Msk (0x1U << SPI_I2SCTRL_I2SCBN_Pos) /*!< 0x00000001 */ +#define SPI_I2SCTRL_I2SCBN SPI_I2SCTRL_I2SCBN_Msk /*!< Channel length (I2S channel bit num) */ + +/*!< I2SDBN configuration */ +#define SPI_I2SCTRL_I2SDBN_Pos (1U) +#define SPI_I2SCTRL_I2SDBN_Msk (0x3U << SPI_I2SCTRL_I2SDBN_Pos) /*!< 0x00000006 */ +#define SPI_I2SCTRL_I2SDBN SPI_I2SCTRL_I2SDBN_Msk /*!< I2SDBN[1:0] bits (I2S data bit num) */ +#define SPI_I2SCTRL_I2SDBN_0 (0x1U << SPI_I2SCTRL_I2SDBN_Pos) /*!< 0x00000002 */ +#define SPI_I2SCTRL_I2SDBN_1 (0x2U << SPI_I2SCTRL_I2SDBN_Pos) /*!< 0x00000004 */ + +#define SPI_I2SCTRL_I2SCLKPOL_Pos (3U) +#define SPI_I2SCTRL_I2SCLKPOL_Msk (0x1U << SPI_I2SCTRL_I2SCLKPOL_Pos) /*!< 0x00000008 */ +#define SPI_I2SCTRL_I2SCLKPOL SPI_I2SCTRL_I2SCLKPOL_Msk /*!< I2S clock polarity */ + +/*!< STDSEL configuration */ +#define SPI_I2SCTRL_STDSEL_Pos (4U) +#define SPI_I2SCTRL_STDSEL_Msk (0x3U << SPI_I2SCTRL_STDSEL_Pos) /*!< 0x00000030 */ +#define SPI_I2SCTRL_STDSEL SPI_I2SCTRL_STDSEL_Msk /*!< STDSEL[1:0] bits (I2S standard select) */ +#define SPI_I2SCTRL_STDSEL_0 (0x1U << SPI_I2SCTRL_STDSEL_Pos) /*!< 0x00000010 */ +#define SPI_I2SCTRL_STDSEL_1 (0x2U << SPI_I2SCTRL_STDSEL_Pos) /*!< 0x00000020 */ + +#define SPI_I2SCTRL_PCMFSSEL_Pos (7U) +#define SPI_I2SCTRL_PCMFSSEL_Msk (0x1U << SPI_I2SCTRL_PCMFSSEL_Pos) /*!< 0x00000080 */ +#define SPI_I2SCTRL_PCMFSSEL SPI_I2SCTRL_PCMFSSEL_Msk /*!< PCM frame synchronization */ + +/*!< OPERSEL configuration */ +#define SPI_I2SCTRL_OPERSEL_Pos (8U) +#define SPI_I2SCTRL_OPERSEL_Msk (0x3U << SPI_I2SCTRL_OPERSEL_Pos) /*!< 0x00000300 */ +#define SPI_I2SCTRL_OPERSEL SPI_I2SCTRL_OPERSEL_Msk /*!< OPERSEL[1:0] bits (I2S operation mode select) */ +#define SPI_I2SCTRL_OPERSEL_0 (0x1U << SPI_I2SCTRL_OPERSEL_Pos) /*!< 0x00000100 */ +#define SPI_I2SCTRL_OPERSEL_1 (0x2U << SPI_I2SCTRL_OPERSEL_Pos) /*!< 0x00000200 */ + +#define SPI_I2SCTRL_I2SEN_Pos (10U) +#define SPI_I2SCTRL_I2SEN_Msk (0x1U << SPI_I2SCTRL_I2SEN_Pos) /*!< 0x00000400 */ +#define SPI_I2SCTRL_I2SEN SPI_I2SCTRL_I2SEN_Msk /*!< I2S enable */ +#define SPI_I2SCTRL_I2SMSEL_Pos (11U) +#define SPI_I2SCTRL_I2SMSEL_Msk (0x1U << SPI_I2SCTRL_I2SMSEL_Pos) /*!< 0x00000800 */ +#define SPI_I2SCTRL_I2SMSEL SPI_I2SCTRL_I2SMSEL_Msk /*!< I2S mode select */ +#define SPI_I2SCTRL_I2SFDUPEN_Pos (13U) +#define SPI_I2SCTRL_I2SFDUPEN_Msk (0x1U << SPI_I2SCTRL_I2SFDUPEN_Pos) /*!< 0x00002000 */ +#define SPI_I2SCTRL_I2SFDUPEN SPI_I2SCTRL_I2SFDUPEN_Msk /*!< I2S full duplex enable */ + +/***************** Bit definition for SPI_I2SCLKP register ******************/ +#define SPI_I2SCLKP_I2SDIV_Msk ((0xFFU << 0) | (0x3U << 10)) /*!< 0x00000CFF */ +#define SPI_I2SCLKP_I2SDIV SPI_I2SCLKP_I2SDIV_Msk /*!< I2SDIV[9:0] bits (I2S division) */ +#define SPI_I2SCLKP_I2SODD_Pos (8U) +#define SPI_I2SCLKP_I2SODD_Msk (0x1U << SPI_I2SCLKP_I2SODD_Pos) /*!< 0x00000100 */ +#define SPI_I2SCLKP_I2SODD SPI_I2SCLKP_I2SODD_Msk /*!< Odd factor for I2S division */ +#define SPI_I2SCLKP_I2SMCLKOE_Pos (9U) +#define SPI_I2SCLKP_I2SMCLKOE_Msk (0x1U << SPI_I2SCLKP_I2SMCLKOE_Pos) /*!< 0x00000200 */ +#define SPI_I2SCLKP_I2SMCLKOE SPI_I2SCLKP_I2SMCLKOE_Msk /*!< I2S Master clock output enable */ + +/****************** Bit definition for SPI_MISC1 register *******************/ +#define SPI_MISC1_I2SFPCMCKSEL_Pos (0U) +#define SPI_MISC1_I2SFPCMCKSEL_Msk (0x1U << SPI_MISC1_I2SFPCMCKSEL_Pos) /*!< 0x00000001 */ +#define SPI_MISC1_I2SFPCMCKSEL SPI_MISC1_I2SFPCMCKSEL_Msk /*!< I2S PCM clock edge select */ + +/******************************************************************************/ +/* */ +/* Window watchdog timer (WWDT) */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for WWDT_CTRL register *******************/ +/*!< CNT configuration */ +#define WWDT_CTRL_CNT_Pos (0U) +#define WWDT_CTRL_CNT_Msk (0x7FU << WWDT_CTRL_CNT_Pos) /*!< 0x0000007F */ +#define WWDT_CTRL_CNT WWDT_CTRL_CNT_Msk /*!< CNT[6:0] bits (Down counter) */ +#define WWDT_CTRL_CNT_0 (0x01U << WWDT_CTRL_CNT_Pos) /*!< 0x00000001 */ +#define WWDT_CTRL_CNT_1 (0x02U << WWDT_CTRL_CNT_Pos) /*!< 0x00000002 */ +#define WWDT_CTRL_CNT_2 (0x04U << WWDT_CTRL_CNT_Pos) /*!< 0x00000004 */ +#define WWDT_CTRL_CNT_3 (0x08U << WWDT_CTRL_CNT_Pos) /*!< 0x00000008 */ +#define WWDT_CTRL_CNT_4 (0x10U << WWDT_CTRL_CNT_Pos) /*!< 0x00000010 */ +#define WWDT_CTRL_CNT_5 (0x20U << WWDT_CTRL_CNT_Pos) /*!< 0x00000020 */ +#define WWDT_CTRL_CNT_6 (0x40U << WWDT_CTRL_CNT_Pos) /*!< 0x00000040 */ + +/* Legacy defines */ +#define WWDT_CTRL_CNT0 WWDT_CTRL_CNT_0 +#define WWDT_CTRL_CNT1 WWDT_CTRL_CNT_1 +#define WWDT_CTRL_CNT2 WWDT_CTRL_CNT_2 +#define WWDT_CTRL_CNT3 WWDT_CTRL_CNT_3 +#define WWDT_CTRL_CNT4 WWDT_CTRL_CNT_4 +#define WWDT_CTRL_CNT5 WWDT_CTRL_CNT_5 +#define WWDT_CTRL_CNT6 WWDT_CTRL_CNT_6 + +#define WWDT_CTRL_WWDTEN_Pos (7U) +#define WWDT_CTRL_WWDTEN_Msk (0x1U << WWDT_CTRL_WWDTEN_Pos) /*!< 0x00000080 */ +#define WWDT_CTRL_WWDTEN WWDT_CTRL_WWDTEN_Msk /*!< Window watchdog enable */ + +/******************* Bit definition for WWDT_CFG register *******************/ +/*!< WIN configuration */ +#define WWDT_CFG_WIN_Pos (0U) +#define WWDT_CFG_WIN_Msk (0x7FU << WWDT_CFG_WIN_Pos) /*!< 0x0000007F */ +#define WWDT_CFG_WIN WWDT_CFG_WIN_Msk /*!< WIN[6:0] bits (Window value) */ +#define WWDT_CFG_WIN_0 (0x01U << WWDT_CFG_WIN_Pos) /*!< 0x00000001 */ +#define WWDT_CFG_WIN_1 (0x02U << WWDT_CFG_WIN_Pos) /*!< 0x00000002 */ +#define WWDT_CFG_WIN_2 (0x04U << WWDT_CFG_WIN_Pos) /*!< 0x00000004 */ +#define WWDT_CFG_WIN_3 (0x08U << WWDT_CFG_WIN_Pos) /*!< 0x00000008 */ +#define WWDT_CFG_WIN_4 (0x10U << WWDT_CFG_WIN_Pos) /*!< 0x00000010 */ +#define WWDT_CFG_WIN_5 (0x20U << WWDT_CFG_WIN_Pos) /*!< 0x00000020 */ +#define WWDT_CFG_WIN_6 (0x40U << WWDT_CFG_WIN_Pos) /*!< 0x00000040 */ + +/* Legacy defines */ +#define WWDT_CFG_WIN0 WWDT_CFG_WIN_0 +#define WWDT_CFG_WIN1 WWDT_CFG_WIN_1 +#define WWDT_CFG_WIN2 WWDT_CFG_WIN_2 +#define WWDT_CFG_WIN3 WWDT_CFG_WIN_3 +#define WWDT_CFG_WIN4 WWDT_CFG_WIN_4 +#define WWDT_CFG_WIN5 WWDT_CFG_WIN_5 +#define WWDT_CFG_WIN6 WWDT_CFG_WIN_6 + +/*!< DIV configuration */ +#define WWDT_CFG_DIV_Pos (7U) +#define WWDT_CFG_DIV_Msk (0x3U << WWDT_CFG_DIV_Pos) /*!< 0x00000180 */ +#define WWDT_CFG_DIV WWDT_CFG_DIV_Msk /*!< DIV[1:0] bits (Clock division value) */ +#define WWDT_CFG_DIV_0 (0x1U << WWDT_CFG_DIV_Pos) /*!< 0x00000080 */ +#define WWDT_CFG_DIV_1 (0x2U << WWDT_CFG_DIV_Pos) /*!< 0x00000100 */ + +/* Legacy defines */ +#define WWDT_CFG_DIV0 WWDT_CFG_DIV_0 +#define WWDT_CFG_DIV1 WWDT_CFG_DIV_1 + +#define WWDT_CFG_RLDIEN_Pos (9U) +#define WWDT_CFG_RLDIEN_Msk (0x1U << WWDT_CFG_RLDIEN_Pos) /*!< 0x00000200 */ +#define WWDT_CFG_RLDIEN WWDT_CFG_RLDIEN_Msk /*!< Reload counter interrupt */ + +/******************* Bit definition for WWDT_STS register *******************/ +#define WWDT_STS_RLDF_Pos (0U) +#define WWDT_STS_RLDF_Msk (0x1U << WWDT_STS_RLDF_Pos) /*!< 0x00000001 */ +#define WWDT_STS_RLDF WWDT_STS_RLDF_Msk /*!< Reload counter interrupt flag */ + +/******************************************************************************/ +/* */ +/* Watchdog timer (WDT) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for WDT_CMD register ********************/ +#define WDT_CMD_CMD_Pos (0U) +#define WDT_CMD_CMD_Msk (0xFFFFU << WDT_CMD_CMD_Pos) /*!< 0x0000FFFF */ +#define WDT_CMD_CMD WDT_CMD_CMD_Msk /*!< Command register */ + +/******************* Bit definition for WDT_DIV register ********************/ +/*!< DIV configuration */ +#define WDT_DIV_DIV_Pos (0U) +#define WDT_DIV_DIV_Msk (0x7U << WDT_DIV_DIV_Pos) /*!< 0x00000007 */ +#define WDT_DIV_DIV WDT_DIV_DIV_Msk /*!< DIV[2:0] (Clock division value) */ +#define WDT_DIV_DIV_0 (0x1U << WDT_DIV_DIV_Pos) /*!< 0x00000001 */ +#define WDT_DIV_DIV_1 (0x2U << WDT_DIV_DIV_Pos) /*!< 0x00000002 */ +#define WDT_DIV_DIV_2 (0x4U << WDT_DIV_DIV_Pos) /*!< 0x00000004 */ + +/******************* Bit definition for WDT_RLD register ********************/ +#define WDT_RLD_RLD_Pos (0U) +#define WDT_RLD_RLD_Msk (0xFFFU << WDT_RLD_RLD_Pos) /*!< 0x00000FFF */ +#define WDT_RLD_RLD WDT_RLD_RLD_Msk /*!< Reload value */ + +/******************* Bit definition for WDT_STS register ********************/ +#define WDT_STS_DIVF_Pos (0U) +#define WDT_STS_DIVF_Msk (0x1U << WDT_STS_DIVF_Pos) /*!< 0x00000001 */ +#define WDT_STS_DIVF WDT_STS_DIVF_Msk /*!< Division value update complete flag */ +#define WDT_STS_RLDF_Pos (1U) +#define WDT_STS_RLDF_Msk (0x1U << WDT_STS_RLDF_Pos) /*!< 0x00000002 */ +#define WDT_STS_RLDF WDT_STS_RLDF_Msk /*!< Reload value update complete flag */ +#define WDT_STS_WINF_Pos (2U) +#define WDT_STS_WINF_Msk (0x1U << WDT_STS_WINF_Pos) /*!< 0x00000004 */ +#define WDT_STS_WINF WDT_STS_WINF_Msk /*!< Window value update complete flag */ + +/******************* Bit definition for WDT_WIN register ********************/ +#define WDT_WIN_WIN_Pos (0U) +#define WDT_WIN_WIN_Msk (0xFFFU << WDT_WIN_WIN_Pos) /*!< 0x00000FFF */ +#define WDT_WIN_WIN WDT_WIN_WIN_Msk /*!< Window value */ + +/******************************************************************************/ +/* */ +/* Enhanced real-time clock (ERTC) */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for ERTC_TIME register *******************/ +/*!< SU configuration */ +#define ERTC_TIME_SU_Pos (0U) +#define ERTC_TIME_SU_Msk (0xFU << ERTC_TIME_SU_Pos) /*!< 0x0000000F */ +#define ERTC_TIME_SU ERTC_TIME_SU_Msk /*!< SU[3:0] (Second units) */ +#define ERTC_TIME_SU_0 (0x1U << ERTC_TIME_SU_Pos) /*!< 0x00000001 */ +#define ERTC_TIME_SU_1 (0x2U << ERTC_TIME_SU_Pos) /*!< 0x00000002 */ +#define ERTC_TIME_SU_2 (0x4U << ERTC_TIME_SU_Pos) /*!< 0x00000004 */ +#define ERTC_TIME_SU_3 (0x8U << ERTC_TIME_SU_Pos) /*!< 0x00000008 */ + +/*!< ST configuration */ +#define ERTC_TIME_ST_Pos (4U) +#define ERTC_TIME_ST_Msk (0x7U << ERTC_TIME_ST_Pos) /*!< 0x00000070 */ +#define ERTC_TIME_ST ERTC_TIME_ST_Msk /*!< ST[2:0] (Second tens) */ +#define ERTC_TIME_ST_0 (0x1U << ERTC_TIME_ST_Pos) /*!< 0x00000010 */ +#define ERTC_TIME_ST_1 (0x2U << ERTC_TIME_ST_Pos) /*!< 0x00000020 */ +#define ERTC_TIME_ST_2 (0x4U << ERTC_TIME_ST_Pos) /*!< 0x00000040 */ + +/*!< MU configuration */ +#define ERTC_TIME_MU_Pos (8U) +#define ERTC_TIME_MU_Msk (0xFU << ERTC_TIME_MU_Pos) /*!< 0x00000F00 */ +#define ERTC_TIME_MU ERTC_TIME_MU_Msk /*!< MU[3:0] (Minute units) */ +#define ERTC_TIME_MU_0 (0x1U << ERTC_TIME_MU_Pos) /*!< 0x00000100 */ +#define ERTC_TIME_MU_1 (0x2U << ERTC_TIME_MU_Pos) /*!< 0x00000200 */ +#define ERTC_TIME_MU_2 (0x4U << ERTC_TIME_MU_Pos) /*!< 0x00000400 */ +#define ERTC_TIME_MU_3 (0x8U << ERTC_TIME_MU_Pos) /*!< 0x00000800 */ + +/*!< MT configuration */ +#define ERTC_TIME_MT_Pos (12U) +#define ERTC_TIME_MT_Msk (0x7U << ERTC_TIME_MT_Pos) /*!< 0x00007000 */ +#define ERTC_TIME_MT ERTC_TIME_MT_Msk /*!< MT[2:0] (Minute tens) */ +#define ERTC_TIME_MT_0 (0x1U << ERTC_TIME_MT_Pos) /*!< 0x00001000 */ +#define ERTC_TIME_MT_1 (0x2U << ERTC_TIME_MT_Pos) /*!< 0x00002000 */ +#define ERTC_TIME_MT_2 (0x4U << ERTC_TIME_MT_Pos) /*!< 0x00004000 */ + +/*!< HU configuration */ +#define ERTC_TIME_HU_Pos (16U) +#define ERTC_TIME_HU_Msk (0xFU << ERTC_TIME_HU_Pos) /*!< 0x000F0000 */ +#define ERTC_TIME_HU ERTC_TIME_HU_Msk /*!< HU[3:0] (Hour units) */ +#define ERTC_TIME_HU_0 (0x1U << ERTC_TIME_HU_Pos) /*!< 0x00010000 */ +#define ERTC_TIME_HU_1 (0x2U << ERTC_TIME_HU_Pos) /*!< 0x00020000 */ +#define ERTC_TIME_HU_2 (0x4U << ERTC_TIME_HU_Pos) /*!< 0x00040000 */ +#define ERTC_TIME_HU_3 (0x8U << ERTC_TIME_HU_Pos) /*!< 0x00080000 */ + +/*!< HT configuration */ +#define ERTC_TIME_HT_Pos (20U) +#define ERTC_TIME_HT_Msk (0x3U << ERTC_TIME_HT_Pos) /*!< 0x00300000 */ +#define ERTC_TIME_HT ERTC_TIME_HT_Msk /*!< HT[1:0] (Hour tens) */ +#define ERTC_TIME_HT_0 (0x1U << ERTC_TIME_HT_Pos) /*!< 0x00100000 */ +#define ERTC_TIME_HT_1 (0x2U << ERTC_TIME_HT_Pos) /*!< 0x00200000 */ + +#define ERTC_TIME_AMPM_Pos (22U) +#define ERTC_TIME_AMPM_Msk (0x1U << ERTC_TIME_AMPM_Pos) /*!< 0x00400000 */ +#define ERTC_TIME_AMPM ERTC_TIME_AMPM_Msk /*!< AM/PM */ + +/****************** Bit definition for ERTC_DATE register *******************/ +/*!< DU configuration */ +#define ERTC_DATE_DU_Pos (0U) +#define ERTC_DATE_DU_Msk (0xFU << ERTC_DATE_DU_Pos) /*!< 0x0000000F */ +#define ERTC_DATE_DU ERTC_DATE_DU_Msk /*!< DU[3:0] (Date units) */ +#define ERTC_DATE_DU_0 (0x1U << ERTC_DATE_DU_Pos) /*!< 0x00000001 */ +#define ERTC_DATE_DU_1 (0x2U << ERTC_DATE_DU_Pos) /*!< 0x00000002 */ +#define ERTC_DATE_DU_2 (0x4U << ERTC_DATE_DU_Pos) /*!< 0x00000004 */ +#define ERTC_DATE_DU_3 (0x8U << ERTC_DATE_DU_Pos) /*!< 0x00000008 */ + +/*!< DT configuration */ +#define ERTC_DATE_DT_Pos (4U) +#define ERTC_DATE_DT_Msk (0x3U << ERTC_DATE_DT_Pos) /*!< 0x00300000 */ +#define ERTC_DATE_DT ERTC_DATE_DT_Msk /*!< DT[1:0] (Date tens) */ +#define ERTC_DATE_DT_0 (0x1U << ERTC_DATE_DT_Pos) /*!< 0x00000010 */ +#define ERTC_DATE_DT_1 (0x2U << ERTC_DATE_DT_Pos) /*!< 0x00000020 */ + +/*!< MU configuration */ +#define ERTC_DATE_MU_Pos (8U) +#define ERTC_DATE_MU_Msk (0xFU << ERTC_DATE_MU_Pos) /*!< 0x00000F00 */ +#define ERTC_DATE_MU ERTC_DATE_MU_Msk /*!< MU[3:0] (Month units) */ +#define ERTC_DATE_MU_0 (0x1U << ERTC_DATE_MU_Pos) /*!< 0x00000100 */ +#define ERTC_DATE_MU_1 (0x2U << ERTC_DATE_MU_Pos) /*!< 0x00000200 */ +#define ERTC_DATE_MU_2 (0x4U << ERTC_DATE_MU_Pos) /*!< 0x00000400 */ +#define ERTC_DATE_MU_3 (0x8U << ERTC_DATE_MU_Pos) /*!< 0x00000800 */ + +#define ERTC_DATE_MT_Pos (12U) +#define ERTC_DATE_MT_Msk (0x1U << ERTC_DATE_MT_Pos) /*!< 0x00001000 */ +#define ERTC_DATE_MT ERTC_DATE_MT_Msk /*!< Month tens */ + +/*!< WK configuration */ +#define ERTC_DATE_WK_Pos (13U) +#define ERTC_DATE_WK_Msk (0x7U << ERTC_DATE_WK_Pos) /*!< 0x0000E000 */ +#define ERTC_DATE_WK ERTC_DATE_WK_Msk /*!< WK[2:0] (Week day) */ +#define ERTC_DATE_WK_0 (0x1U << ERTC_DATE_WK_Pos) /*!< 0x00002000 */ +#define ERTC_DATE_WK_1 (0x2U << ERTC_DATE_WK_Pos) /*!< 0x00004000 */ +#define ERTC_DATE_WK_2 (0x4U << ERTC_DATE_WK_Pos) /*!< 0x00008000 */ + +/*!< YU configuration */ +#define ERTC_DATE_YU_Pos (16U) +#define ERTC_DATE_YU_Msk (0xFU << ERTC_DATE_YU_Pos) /*!< 0x000F0000 */ +#define ERTC_DATE_YU ERTC_DATE_YU_Msk /*!< YU[3:0] (Year units) */ +#define ERTC_DATE_YU_0 (0x1U << ERTC_DATE_YU_Pos) /*!< 0x00010000 */ +#define ERTC_DATE_YU_1 (0x2U << ERTC_DATE_YU_Pos) /*!< 0x00020000 */ +#define ERTC_DATE_YU_2 (0x4U << ERTC_DATE_YU_Pos) /*!< 0x00040000 */ +#define ERTC_DATE_YU_3 (0x8U << ERTC_DATE_YU_Pos) /*!< 0x00080000 */ + +/*!< YT configuration */ +#define ERTC_DATE_YT_Pos (20U) +#define ERTC_DATE_YT_Msk (0xFU << ERTC_DATE_YT_Pos) /*!< 0x00F00000 */ +#define ERTC_DATE_YT ERTC_DATE_YT_Msk /*!< YT[3:0] (Year tens) */ +#define ERTC_DATE_YT_0 (0x1U << ERTC_DATE_YT_Pos) /*!< 0x00100000 */ +#define ERTC_DATE_YT_1 (0x2U << ERTC_DATE_YT_Pos) /*!< 0x00200000 */ +#define ERTC_DATE_YT_2 (0x4U << ERTC_DATE_YT_Pos) /*!< 0x00400000 */ +#define ERTC_DATE_YT_3 (0x8U << ERTC_DATE_YT_Pos) /*!< 0x00800000 */ + +/****************** Bit definition for ERTC_CTRL register *******************/ +/*!< WATCLK configuration */ +#define ERTC_CTRL_WATCLK_Pos (0U) +#define ERTC_CTRL_WATCLK_Msk (0x7U << ERTC_CTRL_WATCLK_Pos) /*!< 0x00000007 */ +#define ERTC_CTRL_WATCLK ERTC_CTRL_WATCLK_Msk /*!< WATCLK[2:0] (Wakeup timer clock selection) */ +#define ERTC_CTRL_WATCLK_0 (0x1U << ERTC_CTRL_WATCLK_Pos) /*!< 0x00000001 */ +#define ERTC_CTRL_WATCLK_1 (0x2U << ERTC_CTRL_WATCLK_Pos) /*!< 0x00000002 */ +#define ERTC_CTRL_WATCLK_2 (0x4U << ERTC_CTRL_WATCLK_Pos) /*!< 0x00000004 */ + +#define ERTC_CTRL_TSEDG_Pos (3U) +#define ERTC_CTRL_TSEDG_Msk (0x1U << ERTC_CTRL_TSEDG_Pos) /*!< 0x00000008 */ +#define ERTC_CTRL_TSEDG ERTC_CTRL_TSEDG_Msk /*!< Timestamp trigger edge */ +#define ERTC_CTRL_RCDEN_Pos (4U) +#define ERTC_CTRL_RCDEN_Msk (0x1U << ERTC_CTRL_RCDEN_Pos) /*!< 0x00000010 */ +#define ERTC_CTRL_RCDEN ERTC_CTRL_RCDEN_Msk /*!< Reference clock detection enable */ +#define ERTC_CTRL_DREN_Pos (5U) +#define ERTC_CTRL_DREN_Msk (0x1U << ERTC_CTRL_DREN_Pos) /*!< 0x00000020 */ +#define ERTC_CTRL_DREN ERTC_CTRL_DREN_Msk /*!< Date/time register direct read enable */ +#define ERTC_CTRL_HM_Pos (6U) +#define ERTC_CTRL_HM_Msk (0x1U << ERTC_CTRL_HM_Pos) /*!< 0x00000040 */ +#define ERTC_CTRL_HM ERTC_CTRL_HM_Msk /*!< Hour mode */ +#define ERTC_CTRL_ALAEN_Pos (8U) +#define ERTC_CTRL_ALAEN_Msk (0x1U << ERTC_CTRL_ALAEN_Pos) /*!< 0x00000100 */ +#define ERTC_CTRL_ALAEN ERTC_CTRL_ALAEN_Msk /*!< Alarm A enable */ +#define ERTC_CTRL_ALBEN_Pos (9U) +#define ERTC_CTRL_ALBEN_Msk (0x1U << ERTC_CTRL_ALBEN_Pos) /*!< 0x00000200 */ +#define ERTC_CTRL_ALBEN ERTC_CTRL_ALBEN_Msk /*!< Alarm B enable */ +#define ERTC_CTRL_WATEN_Pos (10U) +#define ERTC_CTRL_WATEN_Msk (0x1U << ERTC_CTRL_WATEN_Pos) /*!< 0x00000400 */ +#define ERTC_CTRL_WATEN ERTC_CTRL_WATEN_Msk /*!< Wakeup timer enable */ +#define ERTC_CTRL_TSEN_Pos (11U) +#define ERTC_CTRL_TSEN_Msk (0x1U << ERTC_CTRL_TSEN_Pos) /*!< 0x00000800 */ +#define ERTC_CTRL_TSEN ERTC_CTRL_TSEN_Msk /*!< Timestamp enable */ +#define ERTC_CTRL_ALAIEN_Pos (12U) +#define ERTC_CTRL_ALAIEN_Msk (0x1U << ERTC_CTRL_ALAIEN_Pos) /*!< 0x00001000 */ +#define ERTC_CTRL_ALAIEN ERTC_CTRL_ALAIEN_Msk /*!< Alarm A interrupt enable */ +#define ERTC_CTRL_ALBIEN_Pos (13U) +#define ERTC_CTRL_ALBIEN_Msk (0x1U << ERTC_CTRL_ALBIEN_Pos) /*!< 0x00002000 */ +#define ERTC_CTRL_ALBIEN ERTC_CTRL_ALBIEN_Msk /*!< Alarm B interrupt enable */ +#define ERTC_CTRL_WATIEN_Pos (14U) +#define ERTC_CTRL_WATIEN_Msk (0x1U << ERTC_CTRL_WATIEN_Pos) /*!< 0x00004000 */ +#define ERTC_CTRL_WATIEN ERTC_CTRL_WATIEN_Msk /*!< Wakeup timer interrupt enable */ +#define ERTC_CTRL_TSIEN_Pos (15U) +#define ERTC_CTRL_TSIEN_Msk (0x1U << ERTC_CTRL_TSIEN_Pos) /*!< 0x000008000 */ +#define ERTC_CTRL_TSIEN ERTC_CTRL_TSIEN_Msk /*!< Timestamp interrupt enable */ +#define ERTC_CTRL_ADD1H_Pos (16U) +#define ERTC_CTRL_ADD1H_Msk (0x1U << ERTC_CTRL_ADD1H_Pos) /*!< 0x00010000 */ +#define ERTC_CTRL_ADD1H ERTC_CTRL_ADD1H_Msk /*!< Add 1 hour */ +#define ERTC_CTRL_DEC1H_Pos (17U) +#define ERTC_CTRL_DEC1H_Msk (0x1U << ERTC_CTRL_DEC1H_Pos) /*!< 0x00020000 */ +#define ERTC_CTRL_DEC1H ERTC_CTRL_DEC1H_Msk /*!< Decrease 1 hour */ +#define ERTC_CTRL_BPR_Pos (18U) +#define ERTC_CTRL_BPR_Msk (0x1U << ERTC_CTRL_BPR_Pos) /*!< 0x00040000 */ +#define ERTC_CTRL_BPR ERTC_CTRL_BPR_Msk /*!< Battery powered domain data register */ +#define ERTC_CTRL_CALOSEL_Pos (19U) +#define ERTC_CTRL_CALOSEL_Msk (0x1U << ERTC_CTRL_CALOSEL_Pos) /*!< 0x00080000 */ +#define ERTC_CTRL_CALOSEL ERTC_CTRL_CALOSEL_Msk /*!< Calibration output selection */ +#define ERTC_CTRL_OUTP_Pos (20U) +#define ERTC_CTRL_OUTP_Msk (0x1U << ERTC_CTRL_OUTP_Pos) /*!< 0x00100000 */ +#define ERTC_CTRL_OUTP ERTC_CTRL_OUTP_Msk /*!< Output polarity */ + +/*!< OUTSEL configuration */ +#define ERTC_CTRL_OUTSEL_Pos (21U) +#define ERTC_CTRL_OUTSEL_Msk (0x3U << ERTC_CTRL_OUTSEL_Pos) /*!< 0x00600000 */ +#define ERTC_CTRL_OUTSEL ERTC_CTRL_OUTSEL_Msk /*!< OUTSEL[1:0] (Output source selection) */ +#define ERTC_CTRL_OUTSEL_0 (0x1U << ERTC_CTRL_OUTSEL_Pos) /*!< 0x00200000 */ +#define ERTC_CTRL_OUTSEL_1 (0x2U << ERTC_CTRL_OUTSEL_Pos) /*!< 0x00400000 */ + +#define ERTC_CTRL_CALOEN_Pos (23U) +#define ERTC_CTRL_CALOEN_Msk (0x1U << ERTC_CTRL_CALOEN_Pos) /*!< 0x00800000 */ +#define ERTC_CTRL_CALOEN ERTC_CTRL_CALOEN_Msk /*!< Calibration output enable */ + +/******************* Bit definition for ERTC_STS register *******************/ +#define ERTC_STS_ALAWF_Pos (0U) +#define ERTC_STS_ALAWF_Msk (0x1U << ERTC_STS_ALAWF_Pos) /*!< 0x00000001 */ +#define ERTC_STS_ALAWF ERTC_STS_ALAWF_Msk /*!< Alarm A register allows write flag */ +#define ERTC_STS_ALBWF_Pos (1U) +#define ERTC_STS_ALBWF_Msk (0x1U << ERTC_STS_ALBWF_Pos) /*!< 0x00000002 */ +#define ERTC_STS_ALBWF ERTC_STS_ALBWF_Msk /*!< Alarm B register allows write flag */ +#define ERTC_STS_WATWF_Pos (2U) +#define ERTC_STS_WATWF_Msk (0x1U << ERTC_STS_WATWF_Pos) /*!< 0x00000004 */ +#define ERTC_STS_WATWF ERTC_STS_WATWF_Msk /*!< Wakeup timer register allows write flag */ +#define ERTC_STS_TADJF_Pos (3U) +#define ERTC_STS_TADJF_Msk (0x1U << ERTC_STS_TADJF_Pos) /*!< 0x00000008 */ +#define ERTC_STS_TADJF ERTC_STS_TADJF_Msk /*!< Time adjustment flag */ +#define ERTC_STS_INITF_Pos (4U) +#define ERTC_STS_INITF_Msk (0x1U << ERTC_STS_INITF_Pos) /*!< 0x00000010 */ +#define ERTC_STS_INITF ERTC_STS_INITF_Msk /*!< Calendar initialization flag */ +#define ERTC_STS_UPDF_Pos (5U) +#define ERTC_STS_UPDF_Msk (0x1U << ERTC_STS_UPDF_Pos) /*!< 0x00000020 */ +#define ERTC_STS_UPDF ERTC_STS_UPDF_Msk /*!< Calendar update flag */ +#define ERTC_STS_IMF_Pos (6U) +#define ERTC_STS_IMF_Msk (0x1U << ERTC_STS_IMF_Pos) /*!< 0x00000040 */ +#define ERTC_STS_IMF ERTC_STS_IMF_Msk /*!< Enter initialization mode flag */ +#define ERTC_STS_IMEN_Pos (7U) +#define ERTC_STS_IMEN_Msk (0x1U << ERTC_STS_IMEN_Pos) /*!< 0x00000080 */ +#define ERTC_STS_IMEN ERTC_STS_IMEN_Msk /*!< Initialization mode enable */ +#define ERTC_STS_ALAF_Pos (8U) +#define ERTC_STS_ALAF_Msk (0x1U << ERTC_STS_ALAF_Pos) /*!< 0x00000100 */ +#define ERTC_STS_ALAF ERTC_STS_ALAF_Msk /*!< Alarm clock A flag */ +#define ERTC_STS_ALBF_Pos (9U) +#define ERTC_STS_ALBF_Msk (0x1U << ERTC_STS_ALBF_Pos) /*!< 0x00000200 */ +#define ERTC_STS_ALBF ERTC_STS_ALBF_Msk /*!< Alarm clock B flag */ +#define ERTC_STS_WATF_Pos (10U) +#define ERTC_STS_WATF_Msk (0x1U << ERTC_STS_WATF_Pos) /*!< 0x00000400 */ +#define ERTC_STS_WATF ERTC_STS_WATF_Msk /*!< Wakeup timer flag */ +#define ERTC_STS_TSF_Pos (11U) +#define ERTC_STS_TSF_Msk (0x1U << ERTC_STS_TSF_Pos) /*!< 0x00000800 */ +#define ERTC_STS_TSF ERTC_STS_TSF_Msk /*!< Timestamp flag */ +#define ERTC_STS_TSOF_Pos (12U) +#define ERTC_STS_TSOF_Msk (0x1U << ERTC_STS_TSOF_Pos) /*!< 0x00001000 */ +#define ERTC_STS_TSOF ERTC_STS_TSOF_Msk /*!< Timestamp overflow flag */ +#define ERTC_STS_TP1F_Pos (13U) +#define ERTC_STS_TP1F_Msk (0x1U << ERTC_STS_TP1F_Pos) /*!< 0x00002000 */ +#define ERTC_STS_TP1F ERTC_STS_TP1F_Msk /*!< Tamper detection 1 flag */ +#define ERTC_STS_TP2F_Pos (14U) +#define ERTC_STS_TP2F_Msk (0x1U << ERTC_STS_TP2F_Pos) /*!< 0x00004000 */ +#define ERTC_STS_TP2F ERTC_STS_TP2F_Msk /*!< Tamper detection 2 flag */ +#define ERTC_STS_CALUPDF_Pos (16U) +#define ERTC_STS_CALUPDF_Msk (0x1U << ERTC_STS_CALUPDF_Pos) /*!< 0x00010000 */ +#define ERTC_STS_CALUPDF ERTC_STS_CALUPDF_Msk /*!< Calibration value update complete flag */ + +/******************* Bit definition for ERTC_DIV register *******************/ +#define ERTC_DIV_DIVB_Pos (0U) +#define ERTC_DIV_DIVB_Msk (0x7FFFU << ERTC_DIV_DIVB_Pos) /*!< 0x00007FFF */ +#define ERTC_DIV_DIVB ERTC_DIV_DIVB_Msk /*!< Divider B */ +#define ERTC_DIV_DIVA_Pos (16U) +#define ERTC_DIV_DIVA_Msk (0x7FU << ERTC_DIV_DIVA_Pos) /*!< 0x007F0000 */ +#define ERTC_DIV_DIVA ERTC_DIV_DIVA_Msk /*!< Divider A */ + +/******************* Bit definition for ERTC_WAT register *******************/ +#define ERTC_WAT_VAL_Pos (0U) +#define ERTC_WAT_VAL_Msk (0xFFFFU << ERTC_WAT_VAL_Pos) /*!< 0x0000FFFF */ +#define ERTC_WAT_VAL ERTC_WAT_VAL_Msk /*!< Wakeup timer reload value */ + +/******************* Bit definition for ERTC_ALA register *******************/ +/*!< SU configuration */ +#define ERTC_ALA_SU_Pos (0U) +#define ERTC_ALA_SU_Msk (0xFU << ERTC_ALA_SU_Pos) /*!< 0x0000000F */ +#define ERTC_ALA_SU ERTC_ALA_SU_Msk /*!< SU[3:0] (Second units) */ +#define ERTC_ALA_SU_0 (0x1U << ERTC_ALA_SU_Pos) /*!< 0x00000001 */ +#define ERTC_ALA_SU_1 (0x2U << ERTC_ALA_SU_Pos) /*!< 0x00000002 */ +#define ERTC_ALA_SU_2 (0x4U << ERTC_ALA_SU_Pos) /*!< 0x00000004 */ +#define ERTC_ALA_SU_3 (0x8U << ERTC_ALA_SU_Pos) /*!< 0x00000008 */ + +/*!< ST configuration */ +#define ERTC_ALA_ST_Pos (4U) +#define ERTC_ALA_ST_Msk (0x7U << ERTC_ALA_ST_Pos) /*!< 0x00000070 */ +#define ERTC_ALA_ST ERTC_ALA_ST_Msk /*!< ST[2:0] (Second tens) */ +#define ERTC_ALA_ST_0 (0x1U << ERTC_ALA_ST_Pos) /*!< 0x00000010 */ +#define ERTC_ALA_ST_1 (0x2U << ERTC_ALA_ST_Pos) /*!< 0x00000020 */ +#define ERTC_ALA_ST_2 (0x4U << ERTC_ALA_ST_Pos) /*!< 0x00000040 */ + +#define ERTC_ALA_MASK1_Pos (7U) +#define ERTC_ALA_MASK1_Msk (0x1U << ERTC_ALA_MASK1_Pos) /*!< 0x00000080 */ +#define ERTC_ALA_MASK1 ERTC_ALA_MASK1_Msk /*!< Second mask */ + +/*!< MU configuration */ +#define ERTC_ALA_MU_Pos (8U) +#define ERTC_ALA_MU_Msk (0xFU << ERTC_ALA_MU_Pos) /*!< 0x00000F00 */ +#define ERTC_ALA_MU ERTC_ALA_MU_Msk /*!< MU[3:0] (Minute units) */ +#define ERTC_ALA_MU_0 (0x1U << ERTC_ALA_MU_Pos) /*!< 0x00000100 */ +#define ERTC_ALA_MU_1 (0x2U << ERTC_ALA_MU_Pos) /*!< 0x00000200 */ +#define ERTC_ALA_MU_2 (0x4U << ERTC_ALA_MU_Pos) /*!< 0x00000400 */ +#define ERTC_ALA_MU_3 (0x8U << ERTC_ALA_MU_Pos) /*!< 0x00000800 */ + +/*!< MT configuration */ +#define ERTC_ALA_MT_Pos (12U) +#define ERTC_ALA_MT_Msk (0x7U << ERTC_ALA_MT_Pos) /*!< 0x00007000 */ +#define ERTC_ALA_MT ERTC_ALA_MT_Msk /*!< MT[2:0] (Minute tens) */ +#define ERTC_ALA_MT_0 (0x1U << ERTC_ALA_MT_Pos) /*!< 0x00001000 */ +#define ERTC_ALA_MT_1 (0x2U << ERTC_ALA_MT_Pos) /*!< 0x00002000 */ +#define ERTC_ALA_MT_2 (0x4U << ERTC_ALA_MT_Pos) /*!< 0x00004000 */ + +#define ERTC_ALA_MASK2_Pos (15U) +#define ERTC_ALA_MASK2_Msk (0x1U << ERTC_ALA_MASK2_Pos) /*!< 0x00008000 */ +#define ERTC_ALA_MASK2 ERTC_ALA_MASK2_Msk /*!< Minute mask */ + +/*!< HU configuration */ +#define ERTC_ALA_HU_Pos (16U) +#define ERTC_ALA_HU_Msk (0xFU << ERTC_ALA_HU_Pos) /*!< 0x000F0000 */ +#define ERTC_ALA_HU ERTC_ALA_HU_Msk /*!< HU[3:0] (Hour units) */ +#define ERTC_ALA_HU_0 (0x1U << ERTC_ALA_HU_Pos) /*!< 0x00010000 */ +#define ERTC_ALA_HU_1 (0x2U << ERTC_ALA_HU_Pos) /*!< 0x00020000 */ +#define ERTC_ALA_HU_2 (0x4U << ERTC_ALA_HU_Pos) /*!< 0x00040000 */ +#define ERTC_ALA_HU_3 (0x8U << ERTC_ALA_HU_Pos) /*!< 0x00080000 */ + +/*!< HT configuration */ +#define ERTC_ALA_HT_Pos (20U) +#define ERTC_ALA_HT_Msk (0x3U << ERTC_ALA_HT_Pos) /*!< 0x00300000 */ +#define ERTC_ALA_HT ERTC_ALA_HT_Msk /*!< HT[1:0] (Hour tens) */ +#define ERTC_ALA_HT_0 (0x1U << ERTC_ALA_HT_Pos) /*!< 0x00100000 */ +#define ERTC_ALA_HT_1 (0x2U << ERTC_ALA_HT_Pos) /*!< 0x00200000 */ + +#define ERTC_ALA_AMPM_Pos (22U) +#define ERTC_ALA_AMPM_Msk (0x1U << ERTC_ALA_AMPM_Pos) /*!< 0x00400000 */ +#define ERTC_ALA_AMPM ERTC_ALA_AMPM_Msk /*!< AM/PM */ +#define ERTC_ALA_MASK3_Pos (23U) +#define ERTC_ALA_MASK3_Msk (0x1U << ERTC_ALA_MASK3_Pos) /*!< 0x00800000 */ +#define ERTC_ALA_MASK3 ERTC_ALA_MASK3_Msk /*!< Hour mask */ + +/*!< DU configuration */ +#define ERTC_ALA_DU_Pos (24U) +#define ERTC_ALA_DU_Msk (0xFU << ERTC_ALA_DU_Pos) /*!< 0x0F000000 */ +#define ERTC_ALA_DU ERTC_ALA_DU_Msk /*!< DU[3:0] (Date/week day units) */ +#define ERTC_ALA_DU_0 (0x1U << ERTC_ALA_DU_Pos) /*!< 0x01000000 */ +#define ERTC_ALA_DU_1 (0x2U << ERTC_ALA_DU_Pos) /*!< 0x02000000 */ +#define ERTC_ALA_DU_2 (0x4U << ERTC_ALA_DU_Pos) /*!< 0x04000000 */ +#define ERTC_ALA_DU_3 (0x8U << ERTC_ALA_DU_Pos) /*!< 0x08000000 */ + +/*!< DT configuration */ +#define ERTC_ALA_DT_Pos (28U) +#define ERTC_ALA_DT_Msk (0x3U << ERTC_ALA_DT_Pos) /*!< 0x30000000 */ +#define ERTC_ALA_DT ERTC_ALA_DT_Msk /*!< DT[1:0] (Date/week day tens) */ +#define ERTC_ALA_DT_0 (0x1U << ERTC_ALA_DT_Pos) /*!< 0x10000000 */ +#define ERTC_ALA_DT_1 (0x2U << ERTC_ALA_DT_Pos) /*!< 0x20000000 */ + +#define ERTC_ALA_WKSEL_Pos (30U) +#define ERTC_ALA_WKSEL_Msk (0x1U << ERTC_ALA_WKSEL_Pos) /*!< 0x40000000 */ +#define ERTC_ALA_WKSEL ERTC_ALA_WKSEL_Msk /*!< Date/week day select */ +#define ERTC_ALA_MASK4_Pos (31U) +#define ERTC_ALA_MASK4_Msk (0x1U << ERTC_ALA_MASK4_Pos) /*!< 0x80000000 */ +#define ERTC_ALA_MASK4 ERTC_ALA_MASK4_Msk /*!< Date/week day mask */ + +/******************* Bit definition for ERTC_ALB register *******************/ +/*!< SU configuration */ +#define ERTC_ALB_SU_Pos (0U) +#define ERTC_ALB_SU_Msk (0xFU << ERTC_ALB_SU_Pos) /*!< 0x0000000F */ +#define ERTC_ALB_SU ERTC_ALB_SU_Msk /*!< SU[3:0] (Second units) */ +#define ERTC_ALB_SU_0 (0x1U << ERTC_ALB_SU_Pos) /*!< 0x00000001 */ +#define ERTC_ALB_SU_1 (0x2U << ERTC_ALB_SU_Pos) /*!< 0x00000002 */ +#define ERTC_ALB_SU_2 (0x4U << ERTC_ALB_SU_Pos) /*!< 0x00000004 */ +#define ERTC_ALB_SU_3 (0x8U << ERTC_ALB_SU_Pos) /*!< 0x00000008 */ + +/*!< ST configuration */ +#define ERTC_ALB_ST_Pos (4U) +#define ERTC_ALB_ST_Msk (0x7U << ERTC_ALB_ST_Pos) /*!< 0x00000070 */ +#define ERTC_ALB_ST ERTC_ALB_ST_Msk /*!< ST[2:0] (Second tens) */ +#define ERTC_ALB_ST_0 (0x1U << ERTC_ALB_ST_Pos) /*!< 0x00000010 */ +#define ERTC_ALB_ST_1 (0x2U << ERTC_ALB_ST_Pos) /*!< 0x00000020 */ +#define ERTC_ALB_ST_2 (0x4U << ERTC_ALB_ST_Pos) /*!< 0x00000040 */ + +#define ERTC_ALB_MASK1_Pos (7U) +#define ERTC_ALB_MASK1_Msk (0x1U << ERTC_ALB_MASK1_Pos) /*!< 0x00000080 */ +#define ERTC_ALB_MASK1 ERTC_ALB_MASK1_Msk /*!< Second mask */ + +/*!< MU configuration */ +#define ERTC_ALB_MU_Pos (8U) +#define ERTC_ALB_MU_Msk (0xFU << ERTC_ALB_MU_Pos) /*!< 0x00000F00 */ +#define ERTC_ALB_MU ERTC_ALB_MU_Msk /*!< MU[3:0] (Minute units) */ +#define ERTC_ALB_MU_0 (0x1U << ERTC_ALB_MU_Pos) /*!< 0x00000100 */ +#define ERTC_ALB_MU_1 (0x2U << ERTC_ALB_MU_Pos) /*!< 0x00000200 */ +#define ERTC_ALB_MU_2 (0x4U << ERTC_ALB_MU_Pos) /*!< 0x00000400 */ +#define ERTC_ALB_MU_3 (0x8U << ERTC_ALB_MU_Pos) /*!< 0x00000800 */ + +/*!< MT configuration */ +#define ERTC_ALB_MT_Pos (12U) +#define ERTC_ALB_MT_Msk (0x7U << ERTC_ALB_MT_Pos) /*!< 0x00007000 */ +#define ERTC_ALB_MT ERTC_ALB_MT_Msk /*!< MT[2:0] (Minute tens) */ +#define ERTC_ALB_MT_0 (0x1U << ERTC_ALB_MT_Pos) /*!< 0x00001000 */ +#define ERTC_ALB_MT_1 (0x2U << ERTC_ALB_MT_Pos) /*!< 0x00002000 */ +#define ERTC_ALB_MT_2 (0x4U << ERTC_ALB_MT_Pos) /*!< 0x00004000 */ + +#define ERTC_ALB_MASK2_Pos (15U) +#define ERTC_ALB_MASK2_Msk (0x1U << ERTC_ALB_MASK2_Pos) /*!< 0x00008000 */ +#define ERTC_ALB_MASK2 ERTC_ALB_MASK2_Msk /*!< Minute mask */ + +/*!< HU configuration */ +#define ERTC_ALB_HU_Pos (16U) +#define ERTC_ALB_HU_Msk (0xFU << ERTC_ALB_HU_Pos) /*!< 0x000F0000 */ +#define ERTC_ALB_HU ERTC_ALB_HU_Msk /*!< HU[3:0] (Hour units) */ +#define ERTC_ALB_HU_0 (0x1U << ERTC_ALB_HU_Pos) /*!< 0x00010000 */ +#define ERTC_ALB_HU_1 (0x2U << ERTC_ALB_HU_Pos) /*!< 0x00020000 */ +#define ERTC_ALB_HU_2 (0x4U << ERTC_ALB_HU_Pos) /*!< 0x00040000 */ +#define ERTC_ALB_HU_3 (0x8U << ERTC_ALB_HU_Pos) /*!< 0x00080000 */ + +/*!< HT configuration */ +#define ERTC_ALB_HT_Pos (20U) +#define ERTC_ALB_HT_Msk (0x3U << ERTC_ALB_HT_Pos) /*!< 0x00300000 */ +#define ERTC_ALB_HT ERTC_ALB_HT_Msk /*!< HT[1:0] (Hour tens) */ +#define ERTC_ALB_HT_0 (0x1U << ERTC_ALB_HT_Pos) /*!< 0x00100000 */ +#define ERTC_ALB_HT_1 (0x2U << ERTC_ALB_HT_Pos) /*!< 0x00200000 */ + +#define ERTC_ALB_AMPM_Pos (22U) +#define ERTC_ALB_AMPM_Msk (0x1U << ERTC_ALB_AMPM_Pos) /*!< 0x00400000 */ +#define ERTC_ALB_AMPM ERTC_ALB_AMPM_Msk /*!< AM/PM */ +#define ERTC_ALB_MASK3_Pos (23U) +#define ERTC_ALB_MASK3_Msk (0x1U << ERTC_ALB_MASK3_Pos) /*!< 0x00800000 */ +#define ERTC_ALB_MASK3 ERTC_ALB_MASK3_Msk /*!< Hour mask */ + +/*!< DU configuration */ +#define ERTC_ALB_DU_Pos (24U) +#define ERTC_ALB_DU_Msk (0xFU << ERTC_ALB_DU_Pos) /*!< 0x0F000000 */ +#define ERTC_ALB_DU ERTC_ALB_DU_Msk /*!< DU[3:0] (Date/week day units) */ +#define ERTC_ALB_DU_0 (0x1U << ERTC_ALB_DU_Pos) /*!< 0x01000000 */ +#define ERTC_ALB_DU_1 (0x2U << ERTC_ALB_DU_Pos) /*!< 0x02000000 */ +#define ERTC_ALB_DU_2 (0x4U << ERTC_ALB_DU_Pos) /*!< 0x04000000 */ +#define ERTC_ALB_DU_3 (0x8U << ERTC_ALB_DU_Pos) /*!< 0x08000000 */ + +/*!< DT configuration */ +#define ERTC_ALB_DT_Pos (28U) +#define ERTC_ALB_DT_Msk (0x3U << ERTC_ALB_DT_Pos) /*!< 0x30000000 */ +#define ERTC_ALB_DT ERTC_ALB_DT_Msk /*!< DT[1:0] (Date/week day tens) */ +#define ERTC_ALB_DT_0 (0x1U << ERTC_ALB_DT_Pos) /*!< 0x10000000 */ +#define ERTC_ALB_DT_1 (0x2U << ERTC_ALB_DT_Pos) /*!< 0x20000000 */ + +#define ERTC_ALB_WKSEL_Pos (30U) +#define ERTC_ALB_WKSEL_Msk (0x1U << ERTC_ALB_WKSEL_Pos) /*!< 0x40000000 */ +#define ERTC_ALB_WKSEL ERTC_ALB_WKSEL_Msk /*!< Date/week day select */ +#define ERTC_ALB_MASK4_Pos (31U) +#define ERTC_ALB_MASK4_Msk (0x1U << ERTC_ALB_MASK4_Pos) /*!< 0x80000000 */ +#define ERTC_ALB_MASK4 ERTC_ALB_MASK4_Msk /*!< Date/week day mask */ + +/******************* Bit definition for ERTC_WP register ********************/ +#define ERTC_WP_CMD_Pos (0U) +#define ERTC_WP_CMD_Msk (0xFFU << ERTC_WP_CMD_Pos) /*!< 0x000000FF */ +#define ERTC_WP_CMD ERTC_WP_CMD_Msk /*!< Command register */ + +/******************* Bit definition for ERTC_SBS register *******************/ +#define ERTC_SBS_SBS_Pos (0U) +#define ERTC_SBS_SBS_Msk (0xFFFFU << ERTC_SBS_SBS_Pos) /*!< 0x0000FFFF */ +#define ERTC_SBS_SBS ERTC_SBS_SBS_Msk /*!< Sub-second value */ + +/****************** Bit definition for ERTC_TADJ register *******************/ +#define ERTC_TADJ_DECSBS_Pos (0U) +#define ERTC_TADJ_DECSBS_Msk (0x7FFFU << ERTC_TADJ_DECSBS_Pos) /*!< 0x00007FFF */ +#define ERTC_TADJ_DECSBS ERTC_TADJ_DECSBS_Msk /*!< Decrease sub-second value */ +#define ERTC_TADJ_ADD1S_Pos (31U) +#define ERTC_TADJ_ADD1S_Msk (0x1U << ERTC_TADJ_ADD1S_Pos) /*!< 0x80000000 */ +#define ERTC_TADJ_ADD1S ERTC_TADJ_ADD1S_Msk /*!< Add 1 second */ + +/****************** Bit definition for ERTC_TSTM register *******************/ +/*!< SU configuration */ +#define ERTC_TSTM_SU_Pos (0U) +#define ERTC_TSTM_SU_Msk (0xFU << ERTC_TSTM_SU_Pos) /*!< 0x0000000F */ +#define ERTC_TSTM_SU ERTC_TSTM_SU_Msk /*!< SU[3:0] (Second units) */ +#define ERTC_TSTM_SU_0 (0x1U << ERTC_TSTM_SU_Pos) /*!< 0x00000001 */ +#define ERTC_TSTM_SU_1 (0x2U << ERTC_TSTM_SU_Pos) /*!< 0x00000002 */ +#define ERTC_TSTM_SU_2 (0x4U << ERTC_TSTM_SU_Pos) /*!< 0x00000004 */ +#define ERTC_TSTM_SU_3 (0x8U << ERTC_TSTM_SU_Pos) /*!< 0x00000008 */ + +/*!< ST configuration */ +#define ERTC_TSTM_ST_Pos (4U) +#define ERTC_TSTM_ST_Msk (0x7U << ERTC_TSTM_ST_Pos) /*!< 0x00000070 */ +#define ERTC_TSTM_ST ERTC_TSTM_ST_Msk /*!< ST[2:0] (Second tens) */ +#define ERTC_TSTM_ST_0 (0x1U << ERTC_TSTM_ST_Pos) /*!< 0x00000010 */ +#define ERTC_TSTM_ST_1 (0x2U << ERTC_TSTM_ST_Pos) /*!< 0x00000020 */ +#define ERTC_TSTM_ST_2 (0x4U << ERTC_TSTM_ST_Pos) /*!< 0x00000040 */ + +/*!< MU configuration */ +#define ERTC_TSTM_MU_Pos (8U) +#define ERTC_TSTM_MU_Msk (0xFU << ERTC_TSTM_MU_Pos) /*!< 0x00000F00 */ +#define ERTC_TSTM_MU ERTC_TSTM_MU_Msk /*!< MU[3:0] (Minute units) */ +#define ERTC_TSTM_MU_0 (0x1U << ERTC_TSTM_MU_Pos) /*!< 0x00000100 */ +#define ERTC_TSTM_MU_1 (0x2U << ERTC_TSTM_MU_Pos) /*!< 0x00000200 */ +#define ERTC_TSTM_MU_2 (0x4U << ERTC_TSTM_MU_Pos) /*!< 0x00000400 */ +#define ERTC_TSTM_MU_3 (0x8U << ERTC_TSTM_MU_Pos) /*!< 0x00000800 */ + +/*!< MT configuration */ +#define ERTC_TSTM_MT_Pos (12U) +#define ERTC_TSTM_MT_Msk (0x7U << ERTC_TSTM_MT_Pos) /*!< 0x00007000 */ +#define ERTC_TSTM_MT ERTC_TSTM_MT_Msk /*!< MT[2:0] (Minute tens) */ +#define ERTC_TSTM_MT_0 (0x1U << ERTC_TSTM_MT_Pos) /*!< 0x00001000 */ +#define ERTC_TSTM_MT_1 (0x2U << ERTC_TSTM_MT_Pos) /*!< 0x00002000 */ +#define ERTC_TSTM_MT_2 (0x4U << ERTC_TSTM_MT_Pos) /*!< 0x00004000 */ + +/*!< HU configuration */ +#define ERTC_TSTM_HU_Pos (16U) +#define ERTC_TSTM_HU_Msk (0xFU << ERTC_TSTM_HU_Pos) /*!< 0x000F0000 */ +#define ERTC_TSTM_HU ERTC_TSTM_HU_Msk /*!< HU[3:0] (Hour units) */ +#define ERTC_TSTM_HU_0 (0x1U << ERTC_TSTM_HU_Pos) /*!< 0x00010000 */ +#define ERTC_TSTM_HU_1 (0x2U << ERTC_TSTM_HU_Pos) /*!< 0x00020000 */ +#define ERTC_TSTM_HU_2 (0x4U << ERTC_TSTM_HU_Pos) /*!< 0x00040000 */ +#define ERTC_TSTM_HU_3 (0x8U << ERTC_TSTM_HU_Pos) /*!< 0x00080000 */ + +/*!< HT configuration */ +#define ERTC_TSTM_HT_Pos (20U) +#define ERTC_TSTM_HT_Msk (0x3U << ERTC_TSTM_HT_Pos) /*!< 0x00300000 */ +#define ERTC_TSTM_HT ERTC_TSTM_HT_Msk /*!< HT[1:0] (Hour tens) */ +#define ERTC_TSTM_HT_0 (0x1U << ERTC_TSTM_HT_Pos) /*!< 0x00100000 */ +#define ERTC_TSTM_HT_1 (0x2U << ERTC_TSTM_HT_Pos) /*!< 0x00200000 */ + +#define ERTC_TSTM_AMPM_Pos (22U) +#define ERTC_TSTM_AMPM_Msk (0x1U << ERTC_TSTM_AMPM_Pos) /*!< 0x00400000 */ +#define ERTC_TSTM_AMPM ERTC_TSTM_AMPM_Msk /*!< AM/PM */ + +/****************** Bit definition for ERTC_TSDT register *******************/ +/*!< DU configuration */ +#define ERTC_TSDT_DU_Pos (0U) +#define ERTC_TSDT_DU_Msk (0xFU << ERTC_TSDT_DU_Pos) /*!< 0x0000000F */ +#define ERTC_TSDT_DU ERTC_TSDT_DU_Msk /*!< DU[3:0] (Date units) */ +#define ERTC_TSDT_DU_0 (0x1U << ERTC_TSDT_DU_Pos) /*!< 0x00000001 */ +#define ERTC_TSDT_DU_1 (0x2U << ERTC_TSDT_DU_Pos) /*!< 0x00000002 */ +#define ERTC_TSDT_DU_2 (0x4U << ERTC_TSDT_DU_Pos) /*!< 0x00000004 */ +#define ERTC_TSDT_DU_3 (0x8U << ERTC_TSDT_DU_Pos) /*!< 0x00000008 */ + +/*!< DT configuration */ +#define ERTC_TSDT_DT_Pos (4U) +#define ERTC_TSDT_DT_Msk (0x3U << ERTC_TSDT_DT_Pos) /*!< 0x00000030 */ +#define ERTC_TSDT_DT ERTC_TSDT_DT_Msk /*!< DT[1:0] (Date tens) */ +#define ERTC_TSDT_DT_0 (0x1U << ERTC_TSDT_DT_Pos) /*!< 0x00000010 */ +#define ERTC_TSDT_DT_1 (0x2U << ERTC_TSDT_DT_Pos) /*!< 0x00000020 */ + +/*!< MU configuration */ +#define ERTC_TSDT_MU_Pos (8U) +#define ERTC_TSDT_MU_Msk (0xFU << ERTC_TSDT_MU_Pos) /*!< 0x00000F00 */ +#define ERTC_TSDT_MU ERTC_TSDT_MU_Msk /*!< MU[3:0] (Month units) */ +#define ERTC_TSDT_MU_0 (0x1U << ERTC_TSDT_MU_Pos) /*!< 0x00000100 */ +#define ERTC_TSDT_MU_1 (0x2U << ERTC_TSDT_MU_Pos) /*!< 0x00000200 */ +#define ERTC_TSDT_MU_2 (0x4U << ERTC_TSDT_MU_Pos) /*!< 0x00000400 */ +#define ERTC_TSDT_MU_3 (0x8U << ERTC_TSDT_MU_Pos) /*!< 0x00000800 */ + +#define ERTC_TSDT_MT_Pos (12U) +#define ERTC_TSDT_MT_Msk (0x1U << ERTC_TSDT_MT_Pos) /*!< 0x00001000 */ +#define ERTC_TSDT_MT ERTC_TSDT_MT_Msk /*!< Month tens */ + +/*!< WK configuration */ +#define ERTC_TSDT_WK_Pos (13U) +#define ERTC_TSDT_WK_Msk (0x7U << ERTC_TSDT_WK_Pos) /*!< 0x0000E000 */ +#define ERTC_TSDT_WK ERTC_TSDT_WK_Msk /*!< WK[2:0] (Week day) */ +#define ERTC_TSDT_WK_0 (0x1U << ERTC_TSDT_WK_Pos) /*!< 0x00002000 */ +#define ERTC_TSDT_WK_1 (0x2U << ERTC_TSDT_WK_Pos) /*!< 0x00004000 */ +#define ERTC_TSDT_WK_2 (0x4U << ERTC_TSDT_WK_Pos) /*!< 0x00008000 */ + +/****************** Bit definition for ERTC_TSSBS register ******************/ +#define ERTC_TSSBS_SBS_Pos (0U) +#define ERTC_TSSBS_SBS_Msk (0xFFFFU << ERTC_TSSBS_SBS_Pos) /*!< 0x0000FFFF */ +#define ERTC_TSSBS_SBS ERTC_TSSBS_SBS_Msk /*!< Sub-second value */ + +/****************** Bit definition for ERTC_SCAL register *******************/ +#define ERTC_SCAL_DEC_Pos (0U) +#define ERTC_SCAL_DEC_Msk (0x1FFU << ERTC_SCAL_DEC_Pos) /*!< 0x000001FF */ +#define ERTC_SCAL_DEC ERTC_SCAL_DEC_Msk /*!< Decrease ERTC clock */ +#define ERTC_SCAL_CAL16_Pos (13U) +#define ERTC_SCAL_CAL16_Msk (0x1U << ERTC_SCAL_CAL16_Pos) /*!< 0x00002000 */ +#define ERTC_SCAL_CAL16 ERTC_SCAL_CAL16_Msk /*!< 16 second calibration period */ +#define ERTC_SCAL_CAL8_Pos (14U) +#define ERTC_SCAL_CAL8_Msk (0x1U << ERTC_SCAL_CAL8_Pos) /*!< 0x00004000 */ +#define ERTC_SCAL_CAL8 ERTC_SCAL_CAL8_Msk /*!< 8 second calibration period */ +#define ERTC_SCAL_ADD_Pos (15U) +#define ERTC_SCAL_ADD_Msk (0x1U << ERTC_SCAL_ADD_Pos) /*!< 0x00008000 */ +#define ERTC_SCAL_ADD ERTC_SCAL_ADD_Msk /*!< Add ERTC clock */ + +/****************** Bit definition for ERTC_TAMP register *******************/ +#define ERTC_TAMP_TP1EN_Pos (0U) +#define ERTC_TAMP_TP1EN_Msk (0x1U << ERTC_TAMP_TP1EN_Pos) /*!< 0x00000001 */ +#define ERTC_TAMP_TP1EN ERTC_TAMP_TP1EN_Msk /*!< Tamper detection 1 enable */ +#define ERTC_TAMP_TP1EDG_Pos (1U) +#define ERTC_TAMP_TP1EDG_Msk (0x1U << ERTC_TAMP_TP1EDG_Pos) /*!< 0x00000002 */ +#define ERTC_TAMP_TP1EDG ERTC_TAMP_TP1EDG_Msk /*!< Tamper detection 1 valid edge */ +#define ERTC_TAMP_TPIEN_Pos (2U) +#define ERTC_TAMP_TPIEN_Msk (0x1U << ERTC_TAMP_TPIEN_Pos) /*!< 0x00000004 */ +#define ERTC_TAMP_TPIEN ERTC_TAMP_TPIEN_Msk /*!< Tamper detection interrupt enable */ +#define ERTC_TAMP_TP2EN_Pos (3U) +#define ERTC_TAMP_TP2EN_Msk (0x1U << ERTC_TAMP_TP2EN_Pos) /*!< 0x00000008 */ +#define ERTC_TAMP_TP2EN ERTC_TAMP_TP2EN_Msk /*!< Tamper detection 2 enable */ +#define ERTC_TAMP_TP2EDG_Pos (4U) +#define ERTC_TAMP_TP2EDG_Msk (0x1U << ERTC_TAMP_TP2EDG_Pos) /*!< 0x00000010 */ +#define ERTC_TAMP_TP2EDG ERTC_TAMP_TP2EDG_Msk /*!< Tamper detection 2 valid edge */ +#define ERTC_TAMP_TPTSEN_Pos (7U) +#define ERTC_TAMP_TPTSEN_Msk (0x1U << ERTC_TAMP_TPTSEN_Pos) /*!< 0x00000080 */ +#define ERTC_TAMP_TPTSEN ERTC_TAMP_TPTSEN_Msk /*!< Tamper detection timestamp enable */ + +/*!< TPFREQ configuration */ +#define ERTC_TAMP_TPFREQ_Pos (8U) +#define ERTC_TAMP_TPFREQ_Msk (0x7U << ERTC_TAMP_TPFREQ_Pos) /*!< 0x00000700 */ +#define ERTC_TAMP_TPFREQ ERTC_TAMP_TPFREQ_Msk /*!< TPFREQ[2:0] (Tamper detection frequency) */ +#define ERTC_TAMP_TPFREQ_0 (0x1U << ERTC_TAMP_TPFREQ_Pos) /*!< 0x00000100 */ +#define ERTC_TAMP_TPFREQ_1 (0x2U << ERTC_TAMP_TPFREQ_Pos) /*!< 0x00000200 */ +#define ERTC_TAMP_TPFREQ_2 (0x4U << ERTC_TAMP_TPFREQ_Pos) /*!< 0x00000400 */ + +/*!< TPFLT configuration */ +#define ERTC_TAMP_TPFLT_Pos (11U) +#define ERTC_TAMP_TPFLT_Msk (0x3U << ERTC_TAMP_TPFLT_Pos) /*!< 0x00001800 */ +#define ERTC_TAMP_TPFLT ERTC_TAMP_TPFLT_Msk /*!< TPFLT[1:0] (Tamper detection filter time) */ +#define ERTC_TAMP_TPFLT_0 (0x1U << ERTC_TAMP_TPFLT_Pos) /*!< 0x00000800 */ +#define ERTC_TAMP_TPFLT_1 (0x2U << ERTC_TAMP_TPFLT_Pos) /*!< 0x00001000 */ + +/*!< TPPR configuration */ +#define ERTC_TAMP_TPPR_Pos (13U) +#define ERTC_TAMP_TPPR_Msk (0x3U << ERTC_TAMP_TPPR_Pos) /*!< 0x00006000 */ +#define ERTC_TAMP_TPPR ERTC_TAMP_TPPR_Msk /*!< TPPR[1:0] (Tamper detection pre-charge time) */ +#define ERTC_TAMP_TPPR_0 (0x1U << ERTC_TAMP_TPPR_Pos) /*!< 0x00002000 */ +#define ERTC_TAMP_TPPR_1 (0x2U << ERTC_TAMP_TPPR_Pos) /*!< 0x00004000 */ + +#define ERTC_TAMP_TPPU_Pos (15U) +#define ERTC_TAMP_TPPU_Msk (0x1U << ERTC_TAMP_TPPU_Pos) /*!< 0x00008000 */ +#define ERTC_TAMP_TPPU ERTC_TAMP_TPPU_Msk /*!< Tamper detection pull-up */ +#define ERTC_TAMP_TP1PIN_Pos (16U) +#define ERTC_TAMP_TP1PIN_Msk (0x1U << ERTC_TAMP_TP1PIN_Pos) /*!< 0x00010000 */ +#define ERTC_TAMP_TP1PIN ERTC_TAMP_TP1PIN_Msk /*!< Tamper detection pin selection */ +#define ERTC_TAMP_TSPIN_Pos (17U) +#define ERTC_TAMP_TSPIN_Msk (0x1U << ERTC_TAMP_TSPIN_Pos) /*!< 0x00020000 */ +#define ERTC_TAMP_TSPIN ERTC_TAMP_TSPIN_Msk /*!< Time stamp detection pin selection */ +#define ERTC_TAMP_OUTTYPE_Pos (18U) +#define ERTC_TAMP_OUTTYPE_Msk (0x1U << ERTC_TAMP_OUTTYPE_Pos) /*!< 0x00040000 */ +#define ERTC_TAMP_OUTTYPE ERTC_TAMP_OUTTYPE_Msk /*!< Output type */ + +/***************** Bit definition for ERTC_ALASBS register ******************/ +#define ERTC_ALASBS_SBS_Pos (0U) +#define ERTC_ALASBS_SBS_Msk (0x7FFFU << ERTC_ALASBS_SBS_Pos) /*!< 0x00007FFF */ +#define ERTC_ALASBS_SBS ERTC_ALASBS_SBS_Msk /*!< Sub-second value */ + +/*!< SBSMSK configuration */ +#define ERTC_ALASBS_SBSMSK_Pos (24U) +#define ERTC_ALASBS_SBSMSK_Msk (0xFU << ERTC_ALASBS_SBSMSK_Pos) /*!< 0x0F000000 */ +#define ERTC_ALASBS_SBSMSK ERTC_ALASBS_SBSMSK_Msk /*!< SBSMSK[3:0] (Sub-second mask) */ +#define ERTC_ALASBS_SBSMSK_0 (0x1U << ERTC_ALASBS_SBSMSK_Pos) /*!< 0x01000000 */ +#define ERTC_ALASBS_SBSMSK_1 (0x2U << ERTC_ALASBS_SBSMSK_Pos) /*!< 0x02000000 */ +#define ERTC_ALASBS_SBSMSK_2 (0x4U << ERTC_ALASBS_SBSMSK_Pos) /*!< 0x04000000 */ +#define ERTC_ALASBS_SBSMSK_3 (0x8U << ERTC_ALASBS_SBSMSK_Pos) /*!< 0x08000000 */ + +/***************** Bit definition for ERTC_ALBSBS register ******************/ +#define ERTC_ALBSBS_SBS_Pos (0U) +#define ERTC_ALBSBS_SBS_Msk (0x7FFFU << ERTC_ALBSBS_SBS_Pos) /*!< 0x00007FFF */ +#define ERTC_ALBSBS_SBS ERTC_ALBSBS_SBS_Msk /*!< Sub-second value */ + +/*!< SBSMSK configuration */ +#define ERTC_ALBSBS_SBSMSK_Pos (24U) +#define ERTC_ALBSBS_SBSMSK_Msk (0xFU << ERTC_ALBSBS_SBSMSK_Pos) /*!< 0x0F000000 */ +#define ERTC_ALBSBS_SBSMSK ERTC_ALBSBS_SBSMSK_Msk /*!< SBSMSK[3:0] (Sub-second mask) */ +#define ERTC_ALBSBS_SBSMSK_0 (0x1U << ERTC_ALBSBS_SBSMSK_Pos) /*!< 0x01000000 */ +#define ERTC_ALBSBS_SBSMSK_1 (0x2U << ERTC_ALBSBS_SBSMSK_Pos) /*!< 0x02000000 */ +#define ERTC_ALBSBS_SBSMSK_2 (0x4U << ERTC_ALBSBS_SBSMSK_Pos) /*!< 0x04000000 */ +#define ERTC_ALBSBS_SBSMSK_3 (0x8U << ERTC_ALBSBS_SBSMSK_Pos) /*!< 0x08000000 */ + +/****************** Bit definition for ERTC_BPR1 register *******************/ +#define ERTC_BPR1_DT_Pos (0U) +#define ERTC_BPR1_DT_Msk (0xFFFFFFFFU << ERTC_BPR1_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR1_DT ERTC_BPR1_DT_Msk /*!< Battery powered domain data 1 */ + +/****************** Bit definition for ERTC_BPR2 register *******************/ +#define ERTC_BPR2_DT_Pos (0U) +#define ERTC_BPR2_DT_Msk (0xFFFFFFFFU << ERTC_BPR2_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR2_DT ERTC_BPR2_DT_Msk /*!< Battery powered domain data 2 */ + +/****************** Bit definition for ERTC_BPR3 register *******************/ +#define ERTC_BPR3_DT_Pos (0U) +#define ERTC_BPR3_DT_Msk (0xFFFFFFFFU << ERTC_BPR3_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR3_DT ERTC_BPR3_DT_Msk /*!< Battery powered domain data 3 */ + +/****************** Bit definition for ERTC_BPR4 register *******************/ +#define ERTC_BPR4_DT_Pos (0U) +#define ERTC_BPR4_DT_Msk (0xFFFFFFFFU << ERTC_BPR4_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR4_DT ERTC_BPR4_DT_Msk /*!< Battery powered domain data 4 */ + +/****************** Bit definition for ERTC_BPR5 register *******************/ +#define ERTC_BPR5_DT_Pos (0U) +#define ERTC_BPR5_DT_Msk (0xFFFFFFFFU << ERTC_BPR5_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR5_DT ERTC_BPR5_DT_Msk /*!< Battery powered domain data 5 */ + +/****************** Bit definition for ERTC_BPR6 register *******************/ +#define ERTC_BPR6_DT_Pos (0U) +#define ERTC_BPR6_DT_Msk (0xFFFFFFFFU << ERTC_BPR6_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR6_DT ERTC_BPR6_DT_Msk /*!< Battery powered domain data 6 */ + +/****************** Bit definition for ERTC_BPR7 register *******************/ +#define ERTC_BPR7_DT_Pos (0U) +#define ERTC_BPR7_DT_Msk (0xFFFFFFFFU << ERTC_BPR7_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR7_DT ERTC_BPR7_DT_Msk /*!< Battery powered domain data 7 */ + +/****************** Bit definition for ERTC_BPR8 register *******************/ +#define ERTC_BPR8_DT_Pos (0U) +#define ERTC_BPR8_DT_Msk (0xFFFFFFFFU << ERTC_BPR8_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR8_DT ERTC_BPR8_DT_Msk /*!< Battery powered domain data 8 */ + +/****************** Bit definition for ERTC_BPR9 register *******************/ +#define ERTC_BPR9_DT_Pos (0U) +#define ERTC_BPR9_DT_Msk (0xFFFFFFFFU << ERTC_BPR9_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR9_DT ERTC_BPR9_DT_Msk /*!< Battery powered domain data 9 */ + +/****************** Bit definition for ERTC_BPR10 register ******************/ +#define ERTC_BPR10_DT_Pos (0U) +#define ERTC_BPR10_DT_Msk (0xFFFFFFFFU << ERTC_BPR10_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR10_DT ERTC_BPR10_DT_Msk /*!< Battery powered domain data 10 */ + +/****************** Bit definition for ERTC_BPR11 register ******************/ +#define ERTC_BPR11_DT_Pos (0U) +#define ERTC_BPR11_DT_Msk (0xFFFFFFFFU << ERTC_BPR11_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR11_DT ERTC_BPR11_DT_Msk /*!< Battery powered domain data 11 */ + +/****************** Bit definition for ERTC_BPR12 register ******************/ +#define ERTC_BPR12_DT_Pos (0U) +#define ERTC_BPR12_DT_Msk (0xFFFFFFFFU << ERTC_BPR12_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR12_DT ERTC_BPR12_DT_Msk /*!< Battery powered domain data 12 */ + +/****************** Bit definition for ERTC_BPR13 register ******************/ +#define ERTC_BPR13_DT_Pos (0U) +#define ERTC_BPR13_DT_Msk (0xFFFFFFFFU << ERTC_BPR13_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR13_DT ERTC_BPR13_DT_Msk /*!< Battery powered domain data 13 */ + +/****************** Bit definition for ERTC_BPR14 register ******************/ +#define ERTC_BPR14_DT_Pos (0U) +#define ERTC_BPR14_DT_Msk (0xFFFFFFFFU << ERTC_BPR14_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR14_DT ERTC_BPR14_DT_Msk /*!< Battery powered domain data 14 */ + +/****************** Bit definition for ERTC_BPR15 register ******************/ +#define ERTC_BPR15_DT_Pos (0U) +#define ERTC_BPR15_DT_Msk (0xFFFFFFFFU << ERTC_BPR15_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR15_DT ERTC_BPR15_DT_Msk /*!< Battery powered domain data 15 */ + +/****************** Bit definition for ERTC_BPR16 register ******************/ +#define ERTC_BPR16_DT_Pos (0U) +#define ERTC_BPR16_DT_Msk (0xFFFFFFFFU << ERTC_BPR16_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR16_DT ERTC_BPR16_DT_Msk /*!< Battery powered domain data 16 */ + +/****************** Bit definition for ERTC_BPR17 register ******************/ +#define ERTC_BPR17_DT_Pos (0U) +#define ERTC_BPR17_DT_Msk (0xFFFFFFFFU << ERTC_BPR17_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR17_DT ERTC_BPR17_DT_Msk /*!< Battery powered domain data 17 */ + +/****************** Bit definition for ERTC_BPR18 register ******************/ +#define ERTC_BPR18_DT_Pos (0U) +#define ERTC_BPR18_DT_Msk (0xFFFFFFFFU << ERTC_BPR18_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR18_DT ERTC_BPR18_DT_Msk /*!< Battery powered domain data 18 */ + +/****************** Bit definition for ERTC_BPR19 register ******************/ +#define ERTC_BPR19_DT_Pos (0U) +#define ERTC_BPR19_DT_Msk (0xFFFFFFFFU << ERTC_BPR19_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR19_DT ERTC_BPR19_DT_Msk /*!< Battery powered domain data 19 */ + +/****************** Bit definition for ERTC_BPR20 register ******************/ +#define ERTC_BPR20_DT_Pos (0U) +#define ERTC_BPR20_DT_Msk (0xFFFFFFFFU << ERTC_BPR20_DT_Pos) /*!< 0xFFFFFFFF */ +#define ERTC_BPR20_DT ERTC_BPR20_DT_Msk /*!< Battery powered domain data 20 */ + +/************************* Number of backup registers *************************/ +#define ERTC_BPR_NUMBER 0x000000014U + +/******************************************************************************/ +/* */ +/* Analog-to-digital converter (ADC) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for ADC_STS register ********************/ +#define ADC_STS_VMOR_Pos (0U) +#define ADC_STS_VMOR_Msk (0x1U << ADC_STS_VMOR_Pos) /*!< 0x00000001 */ +#define ADC_STS_VMOR ADC_STS_VMOR_Msk /*!< Voltage monitoring out of range flag */ +#define ADC_STS_OCCC_Pos (1U) +#define ADC_STS_OCCC_Msk (0x1U << ADC_STS_OCCC_Pos) /*!< 0x00000002 */ +#define ADC_STS_OCCC ADC_STS_OCCC_Msk /*!< End of conversion flag */ +#define ADC_STS_PCCC_Pos (2U) +#define ADC_STS_PCCC_Msk (0x1U << ADC_STS_PCCC_Pos) /*!< 0x00000004 */ +#define ADC_STS_PCCC ADC_STS_PCCC_Msk /*!< Preempted channel end of conversion flag */ +#define ADC_STS_PCCS_Pos (3U) +#define ADC_STS_PCCS_Msk (0x1U << ADC_STS_PCCS_Pos) /*!< 0x00000008 */ +#define ADC_STS_PCCS ADC_STS_PCCS_Msk /*!< Preempted channel conversion start flag */ +#define ADC_STS_OCCS_Pos (4U) +#define ADC_STS_OCCS_Msk (0x1U << ADC_STS_OCCS_Pos) /*!< 0x00000010 */ +#define ADC_STS_OCCS ADC_STS_OCCS_Msk /*!< Ordinary channel conversion start flag */ + +/* Legacy defines */ +#define ADC_STS_OCCE (ADC_STS_OCCC) +#define ADC_STS_PCCE (ADC_STS_PCCC) + +/****************** Bit definition for ADC_CTRL1 register *******************/ +/*!< VMCSEL configuration */ +#define ADC_CTRL1_VMCSEL_Pos (0U) +#define ADC_CTRL1_VMCSEL_Msk (0x1FU << ADC_CTRL1_VMCSEL_Pos) /*!< 0x0000001F */ +#define ADC_CTRL1_VMCSEL ADC_CTRL1_VMCSEL_Msk /*!< VMCSEL[4:0] bits (Voltage monitoring channel select) */ +#define ADC_CTRL1_VMCSEL_0 (0x01U << ADC_CTRL1_VMCSEL_Pos) /*!< 0x00000001 */ +#define ADC_CTRL1_VMCSEL_1 (0x02U << ADC_CTRL1_VMCSEL_Pos) /*!< 0x00000002 */ +#define ADC_CTRL1_VMCSEL_2 (0x04U << ADC_CTRL1_VMCSEL_Pos) /*!< 0x00000004 */ +#define ADC_CTRL1_VMCSEL_3 (0x08U << ADC_CTRL1_VMCSEL_Pos) /*!< 0x00000008 */ +#define ADC_CTRL1_VMCSEL_4 (0x10U << ADC_CTRL1_VMCSEL_Pos) /*!< 0x00000010 */ + +#define ADC_CTRL1_CCCIEN_Pos (5U) +#define ADC_CTRL1_CCCIEN_Msk (0x1U << ADC_CTRL1_CCCIEN_Pos) /*!< 0x00000020 */ +#define ADC_CTRL1_CCCIEN ADC_CTRL1_CCCIEN_Msk /*!< Channel conversion end interrupt enable */ +#define ADC_CTRL1_VMORIEN_Pos (6U) +#define ADC_CTRL1_VMORIEN_Msk (0x1U << ADC_CTRL1_VMORIEN_Pos) /*!< 0x00000040 */ +#define ADC_CTRL1_VMORIEN ADC_CTRL1_VMORIEN_Msk /*!< Voltage monitoring out of range interrupt enable */ +#define ADC_CTRL1_PCCCIEN_Pos (7U) +#define ADC_CTRL1_PCCCIEN_Msk (0x1U << ADC_CTRL1_PCCCIEN_Pos) /*!< 0x00000080 */ +#define ADC_CTRL1_PCCCIEN ADC_CTRL1_PCCCIEN_Msk /*!< Conversion end interrupt enable on Preempted channels */ +#define ADC_CTRL1_SQEN_Pos (8U) +#define ADC_CTRL1_SQEN_Msk (0x1U << ADC_CTRL1_SQEN_Pos) /*!< 0x00000100 */ +#define ADC_CTRL1_SQEN ADC_CTRL1_SQEN_Msk /*!< Sequence mode enable */ +#define ADC_CTRL1_VMSGEN_Pos (9U) +#define ADC_CTRL1_VMSGEN_Msk (0x1U << ADC_CTRL1_VMSGEN_Pos) /*!< 0x00000200 */ +#define ADC_CTRL1_VMSGEN ADC_CTRL1_VMSGEN_Msk /*!< Voltage monitoring enable on a single channel */ +#define ADC_CTRL1_PCAUTOEN_Pos (10U) +#define ADC_CTRL1_PCAUTOEN_Msk (0x1U << ADC_CTRL1_PCAUTOEN_Pos) /*!< 0x00000400 */ +#define ADC_CTRL1_PCAUTOEN ADC_CTRL1_PCAUTOEN_Msk /*!< Preempted group automatic conversion enable after ordinary group */ +#define ADC_CTRL1_OCPEN_Pos (11U) +#define ADC_CTRL1_OCPEN_Msk (0x1U << ADC_CTRL1_OCPEN_Pos) /*!< 0x00000800 */ +#define ADC_CTRL1_OCPEN ADC_CTRL1_OCPEN_Msk /*!< Partitioned mode enable on ordinary channels */ +#define ADC_CTRL1_PCPEN_Pos (12U) +#define ADC_CTRL1_PCPEN_Msk (0x1U << ADC_CTRL1_PCPEN_Pos) /*!< 0x00001000 */ +#define ADC_CTRL1_PCPEN ADC_CTRL1_PCPEN_Msk /*!< Partitioned mode enable on preempted channels */ + +/*!< OCPCNT configuration */ +#define ADC_CTRL1_OCPCNT_Pos (13U) +#define ADC_CTRL1_OCPCNT_Msk (0x7U << ADC_CTRL1_OCPCNT_Pos) /*!< 0x0000E000 */ +#define ADC_CTRL1_OCPCNT ADC_CTRL1_OCPCNT_Msk /*!< OCPCNT[2:0] bits (Partitioned mode conversion count of ordinary channels) */ +#define ADC_CTRL1_OCPCNT_0 (0x1U << ADC_CTRL1_OCPCNT_Pos) /*!< 0x00002000 */ +#define ADC_CTRL1_OCPCNT_1 (0x2U << ADC_CTRL1_OCPCNT_Pos) /*!< 0x00004000 */ +#define ADC_CTRL1_OCPCNT_2 (0x4U << ADC_CTRL1_OCPCNT_Pos) /*!< 0x00008000 */ + +#define ADC_CTRL1_PCVMEN_Pos (22U) +#define ADC_CTRL1_PCVMEN_Msk (0x1U << ADC_CTRL1_PCVMEN_Pos) /*!< 0x00400000 */ +#define ADC_CTRL1_PCVMEN ADC_CTRL1_PCVMEN_Msk /*!< Voltage monitoring enable on preempted channels */ +#define ADC_CTRL1_OCVMEN_Pos (23U) +#define ADC_CTRL1_OCVMEN_Msk (0x1U << ADC_CTRL1_OCVMEN_Pos) /*!< 0x00800000 */ +#define ADC_CTRL1_OCVMEN ADC_CTRL1_OCVMEN_Msk /*!< Voltage monitoring enable on ordinary channels */ + +/* Legacy defines */ +#define ADC_CTRL1_CCEIEN (ADC_CTRL1_CCCIEN) +#define ADC_CTRL1_PCCEIEN (ADC_CTRL1_PCCCIEN) + +/****************** Bit definition for ADC_CTRL2 register *******************/ +#define ADC_CTRL2_ADCEN_Pos (0U) +#define ADC_CTRL2_ADCEN_Msk (0x1U << ADC_CTRL2_ADCEN_Pos) /*!< 0x00000001 */ +#define ADC_CTRL2_ADCEN ADC_CTRL2_ADCEN_Msk /*!< A/D converter enable */ +#define ADC_CTRL2_RPEN_Pos (1U) +#define ADC_CTRL2_RPEN_Msk (0x1U << ADC_CTRL2_RPEN_Pos) /*!< 0x00000002 */ +#define ADC_CTRL2_RPEN ADC_CTRL2_RPEN_Msk /*!< Repetition mode enable */ +#define ADC_CTRL2_ADCAL_Pos (2U) +#define ADC_CTRL2_ADCAL_Msk (0x1U << ADC_CTRL2_ADCAL_Pos) /*!< 0x00000004 */ +#define ADC_CTRL2_ADCAL ADC_CTRL2_ADCAL_Msk /*!< A/D calibration */ +#define ADC_CTRL2_ADCALINIT_Pos (3U) +#define ADC_CTRL2_ADCALINIT_Msk (0x1U << ADC_CTRL2_ADCALINIT_Pos) /*!< 0x00000008 */ +#define ADC_CTRL2_ADCALINIT ADC_CTRL2_ADCALINIT_Msk /*!< Initialize A/D calibration */ +#define ADC_CTRL2_OCDMAEN_Pos (8U) +#define ADC_CTRL2_OCDMAEN_Msk (0x1U << ADC_CTRL2_OCDMAEN_Pos) /*!< 0x00000100 */ +#define ADC_CTRL2_OCDMAEN ADC_CTRL2_OCDMAEN_Msk /*!< DMA transfer enable of ordinary channels */ +#define ADC_CTRL2_DTALIGN_Pos (11U) +#define ADC_CTRL2_DTALIGN_Msk (0x1U << ADC_CTRL2_DTALIGN_Pos) /*!< 0x00000800 */ +#define ADC_CTRL2_DTALIGN ADC_CTRL2_DTALIGN_Msk /*!< Data alignment */ + +/*!< PCTESEL configuration */ +#define ADC_CTRL2_PCTESEL_Pos (12U) +#define ADC_CTRL2_PCTESEL_Msk (0x7U << ADC_CTRL2_PCTESEL_Pos) /*!< 0x00007000 */ +#define ADC_CTRL2_PCTESEL ADC_CTRL2_PCTESEL_Msk /*!< PCTESEL[2:0] bits (Trigger event select for preempted channels conversion) */ +#define ADC_CTRL2_PCTESEL_0 (0x1U << ADC_CTRL2_PCTESEL_Pos) /*!< 0x00001000 */ +#define ADC_CTRL2_PCTESEL_1 (0x2U << ADC_CTRL2_PCTESEL_Pos) /*!< 0x00002000 */ +#define ADC_CTRL2_PCTESEL_2 (0x4U << ADC_CTRL2_PCTESEL_Pos) /*!< 0x00004000 */ + +#define ADC_CTRL2_PCTEN_Pos (15U) +#define ADC_CTRL2_PCTEN_Msk (0x1U << ADC_CTRL2_PCTEN_Pos) /*!< 0x00008000 */ +#define ADC_CTRL2_PCTEN ADC_CTRL2_PCTEN_Msk /*!< Trigger mode enable for preempted channels conversion */ + +/*!< OCTESEL configuration */ +#define ADC_CTRL2_OCTESEL_Pos (17U) +#define ADC_CTRL2_OCTESEL_Msk (0x7U << ADC_CTRL2_OCTESEL_Pos) /*!< 0x000E0000 */ +#define ADC_CTRL2_OCTESEL ADC_CTRL2_OCTESEL_Msk /*!< OCTESEL[2:0] bits (Trigger event select for ordinary channels conversion) */ +#define ADC_CTRL2_OCTESEL_0 (0x1U << ADC_CTRL2_OCTESEL_Pos) /*!< 0x00020000 */ +#define ADC_CTRL2_OCTESEL_1 (0x2U << ADC_CTRL2_OCTESEL_Pos) /*!< 0x00040000 */ +#define ADC_CTRL2_OCTESEL_2 (0x4U << ADC_CTRL2_OCTESEL_Pos) /*!< 0x00080000 */ + +#define ADC_CTRL2_OCTEN_Pos (20U) +#define ADC_CTRL2_OCTEN_Msk (0x1U << ADC_CTRL2_OCTEN_Pos) /*!< 0x00100000 */ +#define ADC_CTRL2_OCTEN ADC_CTRL2_OCTEN_Msk /*!< Trigger mode enable for ordinary channels conversion */ +#define ADC_CTRL2_PCSWTRG_Pos (21U) +#define ADC_CTRL2_PCSWTRG_Msk (0x1U << ADC_CTRL2_PCSWTRG_Pos) /*!< 0x00200000 */ +#define ADC_CTRL2_PCSWTRG ADC_CTRL2_PCSWTRG_Msk /*!< Conversion of preempted channels triggered by software */ +#define ADC_CTRL2_OCSWTRG_Pos (22U) +#define ADC_CTRL2_OCSWTRG_Msk (0x1U << ADC_CTRL2_OCSWTRG_Pos) /*!< 0x00400000 */ +#define ADC_CTRL2_OCSWTRG ADC_CTRL2_OCSWTRG_Msk /*!< Conversion of ordinary channels triggered by software */ +#define ADC_CTRL2_ITSRVEN_Pos (23U) +#define ADC_CTRL2_ITSRVEN_Msk (0x1U << ADC_CTRL2_ITSRVEN_Pos) /*!< 0x00800000 */ +#define ADC_CTRL2_ITSRVEN ADC_CTRL2_ITSRVEN_Msk /*!< Internal temperature sensor and VINTRV enable */ + +/******************* Bit definition for ADC_SPT1 register *******************/ +/*!< CSPT10 configuration */ +#define ADC_SPT1_CSPT10_Pos (0U) +#define ADC_SPT1_CSPT10_Msk (0x7U << ADC_SPT1_CSPT10_Pos) /*!< 0x00000007 */ +#define ADC_SPT1_CSPT10 ADC_SPT1_CSPT10_Msk /*!< CSPT10[2:0] bits (Sample time selection of channel ADC_IN10) */ +#define ADC_SPT1_CSPT10_0 (0x1U << ADC_SPT1_CSPT10_Pos) /*!< 0x00000001 */ +#define ADC_SPT1_CSPT10_1 (0x2U << ADC_SPT1_CSPT10_Pos) /*!< 0x00000002 */ +#define ADC_SPT1_CSPT10_2 (0x4U << ADC_SPT1_CSPT10_Pos) /*!< 0x00000004 */ + +/*!< CSPT11 configuration */ +#define ADC_SPT1_CSPT11_Pos (3U) +#define ADC_SPT1_CSPT11_Msk (0x7U << ADC_SPT1_CSPT11_Pos) /*!< 0x00000038 */ +#define ADC_SPT1_CSPT11 ADC_SPT1_CSPT11_Msk /*!< CSPT11[2:0] bits (Sample time selection of channel ADC_IN11) */ +#define ADC_SPT1_CSPT11_0 (0x1U << ADC_SPT1_CSPT11_Pos) /*!< 0x00000008 */ +#define ADC_SPT1_CSPT11_1 (0x2U << ADC_SPT1_CSPT11_Pos) /*!< 0x00000010 */ +#define ADC_SPT1_CSPT11_2 (0x4U << ADC_SPT1_CSPT11_Pos) /*!< 0x00000020 */ + +/*!< CSPT12 configuration */ +#define ADC_SPT1_CSPT12_Pos (6U) +#define ADC_SPT1_CSPT12_Msk (0x7U << ADC_SPT1_CSPT12_Pos) /*!< 0x000001C0 */ +#define ADC_SPT1_CSPT12 ADC_SPT1_CSPT12_Msk /*!< CSPT12[2:0] bits (Sample time selection of channel ADC_IN12) */ +#define ADC_SPT1_CSPT12_0 (0x1U << ADC_SPT1_CSPT12_Pos) /*!< 0x00000040 */ +#define ADC_SPT1_CSPT12_1 (0x2U << ADC_SPT1_CSPT12_Pos) /*!< 0x00000080 */ +#define ADC_SPT1_CSPT12_2 (0x4U << ADC_SPT1_CSPT12_Pos) /*!< 0x00000100 */ + +/*!< CSPT13 configuration */ +#define ADC_SPT1_CSPT13_Pos (9U) +#define ADC_SPT1_CSPT13_Msk (0x7U << ADC_SPT1_CSPT13_Pos) /*!< 0x00000E00 */ +#define ADC_SPT1_CSPT13 ADC_SPT1_CSPT13_Msk /*!< CSPT13[2:0] bits (Sample time selection of channel ADC_IN13) */ +#define ADC_SPT1_CSPT13_0 (0x1U << ADC_SPT1_CSPT13_Pos) /*!< 0x00000200 */ +#define ADC_SPT1_CSPT13_1 (0x2U << ADC_SPT1_CSPT13_Pos) /*!< 0x00000400 */ +#define ADC_SPT1_CSPT13_2 (0x4U << ADC_SPT1_CSPT13_Pos) /*!< 0x00000800 */ + +/*!< CSPT14 configuration */ +#define ADC_SPT1_CSPT14_Pos (12U) +#define ADC_SPT1_CSPT14_Msk (0x7U << ADC_SPT1_CSPT14_Pos) /*!< 0x00007000 */ +#define ADC_SPT1_CSPT14 ADC_SPT1_CSPT14_Msk /*!< CSPT14[2:0] bits (Sample time selection of channel ADC_IN14) */ +#define ADC_SPT1_CSPT14_0 (0x1U << ADC_SPT1_CSPT14_Pos) /*!< 0x00001000 */ +#define ADC_SPT1_CSPT14_1 (0x2U << ADC_SPT1_CSPT14_Pos) /*!< 0x00002000 */ +#define ADC_SPT1_CSPT14_2 (0x4U << ADC_SPT1_CSPT14_Pos) /*!< 0x00004000 */ + +/*!< CSPT15 configuration */ +#define ADC_SPT1_CSPT15_Pos (15U) +#define ADC_SPT1_CSPT15_Msk (0x7U << ADC_SPT1_CSPT15_Pos) /*!< 0x00038000 */ +#define ADC_SPT1_CSPT15 ADC_SPT1_CSPT15_Msk /*!< CSPT15[2:0] bits (Sample time selection of channel ADC_IN15) */ +#define ADC_SPT1_CSPT15_0 (0x1U << ADC_SPT1_CSPT15_Pos) /*!< 0x00008000 */ +#define ADC_SPT1_CSPT15_1 (0x2U << ADC_SPT1_CSPT15_Pos) /*!< 0x00010000 */ +#define ADC_SPT1_CSPT15_2 (0x4U << ADC_SPT1_CSPT15_Pos) /*!< 0x00020000 */ + +/*!< CSPT16 configuration */ +#define ADC_SPT1_CSPT16_Pos (18U) +#define ADC_SPT1_CSPT16_Msk (0x7U << ADC_SPT1_CSPT16_Pos) /*!< 0x001C0000 */ +#define ADC_SPT1_CSPT16 ADC_SPT1_CSPT16_Msk /*!< CSPT16[2:0] bits (Sample time selection of channel ADC_IN16) */ +#define ADC_SPT1_CSPT16_0 (0x1U << ADC_SPT1_CSPT16_Pos) /*!< 0x00040000 */ +#define ADC_SPT1_CSPT16_1 (0x2U << ADC_SPT1_CSPT16_Pos) /*!< 0x00080000 */ +#define ADC_SPT1_CSPT16_2 (0x4U << ADC_SPT1_CSPT16_Pos) /*!< 0x00100000 */ + +/*!< CSPT17 configuration */ +#define ADC_SPT1_CSPT17_Pos (21U) +#define ADC_SPT1_CSPT17_Msk (0x7U << ADC_SPT1_CSPT17_Pos) /*!< 0x00E00000 */ +#define ADC_SPT1_CSPT17 ADC_SPT1_CSPT17_Msk /*!< CSPT17[2:0] bits (Sample time selection of channel ADC_IN17) */ +#define ADC_SPT1_CSPT17_0 (0x1U << ADC_SPT1_CSPT17_Pos) /*!< 0x00200000 */ +#define ADC_SPT1_CSPT17_1 (0x2U << ADC_SPT1_CSPT17_Pos) /*!< 0x00400000 */ +#define ADC_SPT1_CSPT17_2 (0x4U << ADC_SPT1_CSPT17_Pos) /*!< 0x00800000 */ + +/******************* Bit definition for ADC_SPT2 register *******************/ +/*!< CSPT0 configuration */ +#define ADC_SPT2_CSPT0_Pos (0U) +#define ADC_SPT2_CSPT0_Msk (0x7U << ADC_SPT2_CSPT0_Pos) /*!< 0x00000007 */ +#define ADC_SPT2_CSPT0 ADC_SPT2_CSPT0_Msk /*!< CSPT0[2:0] bits (Sample time selection of channel ADC_IN0) */ +#define ADC_SPT2_CSPT0_0 (0x1U << ADC_SPT2_CSPT0_Pos) /*!< 0x00000001 */ +#define ADC_SPT2_CSPT0_1 (0x2U << ADC_SPT2_CSPT0_Pos) /*!< 0x00000002 */ +#define ADC_SPT2_CSPT0_2 (0x4U << ADC_SPT2_CSPT0_Pos) /*!< 0x00000004 */ + +/*!< CSPT1 configuration */ +#define ADC_SPT2_CSPT1_Pos (3U) +#define ADC_SPT2_CSPT1_Msk (0x7U << ADC_SPT2_CSPT1_Pos) /*!< 0x00000038 */ +#define ADC_SPT2_CSPT1 ADC_SPT2_CSPT1_Msk /*!< CSPT1[2:0] bits (Sample time selection of channel ADC_IN1) */ +#define ADC_SPT2_CSPT1_0 (0x1U << ADC_SPT2_CSPT1_Pos) /*!< 0x00000008 */ +#define ADC_SPT2_CSPT1_1 (0x2U << ADC_SPT2_CSPT1_Pos) /*!< 0x00000010 */ +#define ADC_SPT2_CSPT1_2 (0x4U << ADC_SPT2_CSPT1_Pos) /*!< 0x00000020 */ + +/*!< CSPT2 configuration */ +#define ADC_SPT2_CSPT2_Pos (6U) +#define ADC_SPT2_CSPT2_Msk (0x7U << ADC_SPT2_CSPT2_Pos) /*!< 0x000001C0 */ +#define ADC_SPT2_CSPT2 ADC_SPT2_CSPT2_Msk /*!< CSPT2[2:0] bits (Sample time selection of channel ADC_IN2) */ +#define ADC_SPT2_CSPT2_0 (0x1U << ADC_SPT2_CSPT2_Pos) /*!< 0x00000040 */ +#define ADC_SPT2_CSPT2_1 (0x2U << ADC_SPT2_CSPT2_Pos) /*!< 0x00000080 */ +#define ADC_SPT2_CSPT2_2 (0x4U << ADC_SPT2_CSPT2_Pos) /*!< 0x00000100 */ + +/*!< CSPT3 configuration */ +#define ADC_SPT2_CSPT3_Pos (9U) +#define ADC_SPT2_CSPT3_Msk (0x7U << ADC_SPT2_CSPT3_Pos) /*!< 0x00000E00 */ +#define ADC_SPT2_CSPT3 ADC_SPT2_CSPT3_Msk /*!< CSPT3[2:0] bits (Sample time selection of channel ADC_IN3) */ +#define ADC_SPT2_CSPT3_0 (0x1U << ADC_SPT2_CSPT3_Pos) /*!< 0x00000200 */ +#define ADC_SPT2_CSPT3_1 (0x2U << ADC_SPT2_CSPT3_Pos) /*!< 0x00000400 */ +#define ADC_SPT2_CSPT3_2 (0x4U << ADC_SPT2_CSPT3_Pos) /*!< 0x00000800 */ + +/*!< CSPT4 configuration */ +#define ADC_SPT2_CSPT4_Pos (12U) +#define ADC_SPT2_CSPT4_Msk (0x7U << ADC_SPT2_CSPT4_Pos) /*!< 0x00007000 */ +#define ADC_SPT2_CSPT4 ADC_SPT2_CSPT4_Msk /*!< CSPT4[2:0] bits (Sample time selection of channel ADC_IN4) */ +#define ADC_SPT2_CSPT4_0 (0x1U << ADC_SPT2_CSPT4_Pos) /*!< 0x00001000 */ +#define ADC_SPT2_CSPT4_1 (0x2U << ADC_SPT2_CSPT4_Pos) /*!< 0x00002000 */ +#define ADC_SPT2_CSPT4_2 (0x4U << ADC_SPT2_CSPT4_Pos) /*!< 0x00004000 */ + +/*!< CSPT5 configuration */ +#define ADC_SPT2_CSPT5_Pos (15U) +#define ADC_SPT2_CSPT5_Msk (0x7U << ADC_SPT2_CSPT5_Pos) /*!< 0x00038000 */ +#define ADC_SPT2_CSPT5 ADC_SPT2_CSPT5_Msk /*!< CSPT5[2:0] bits (Sample time selection of channel ADC_IN5) */ +#define ADC_SPT2_CSPT5_0 (0x1U << ADC_SPT2_CSPT5_Pos) /*!< 0x00008000 */ +#define ADC_SPT2_CSPT5_1 (0x2U << ADC_SPT2_CSPT5_Pos) /*!< 0x00010000 */ +#define ADC_SPT2_CSPT5_2 (0x4U << ADC_SPT2_CSPT5_Pos) /*!< 0x00020000 */ + +/*!< CSPT6 configuration */ +#define ADC_SPT2_CSPT6_Pos (18U) +#define ADC_SPT2_CSPT6_Msk (0x7U << ADC_SPT2_CSPT6_Pos) /*!< 0x001C0000 */ +#define ADC_SPT2_CSPT6 ADC_SPT2_CSPT6_Msk /*!< CSPT6[2:0] bits (Sample time selection of channel ADC_IN6) */ +#define ADC_SPT2_CSPT6_0 (0x1U << ADC_SPT2_CSPT6_Pos) /*!< 0x00040000 */ +#define ADC_SPT2_CSPT6_1 (0x2U << ADC_SPT2_CSPT6_Pos) /*!< 0x00080000 */ +#define ADC_SPT2_CSPT6_2 (0x4U << ADC_SPT2_CSPT6_Pos) /*!< 0x00100000 */ + +/*!< CSPT7 configuration */ +#define ADC_SPT2_CSPT7_Pos (21U) +#define ADC_SPT2_CSPT7_Msk (0x7U << ADC_SPT2_CSPT7_Pos) /*!< 0x00E00000 */ +#define ADC_SPT2_CSPT7 ADC_SPT2_CSPT7_Msk /*!< CSPT7[2:0] bits (Sample time selection of channel ADC_IN7) */ +#define ADC_SPT2_CSPT7_0 (0x1U << ADC_SPT2_CSPT7_Pos) /*!< 0x00200000 */ +#define ADC_SPT2_CSPT7_1 (0x2U << ADC_SPT2_CSPT7_Pos) /*!< 0x00400000 */ +#define ADC_SPT2_CSPT7_2 (0x4U << ADC_SPT2_CSPT7_Pos) /*!< 0x00800000 */ + +/*!< CSPT8 configuration */ +#define ADC_SPT2_CSPT8_Pos (24U) +#define ADC_SPT2_CSPT8_Msk (0x7U << ADC_SPT2_CSPT8_Pos) /*!< 0x07000000 */ +#define ADC_SPT2_CSPT8 ADC_SPT2_CSPT8_Msk /*!< CSPT8[2:0] bits (Sample time selection of channel ADC_IN8) */ +#define ADC_SPT2_CSPT8_0 (0x1U << ADC_SPT2_CSPT8_Pos) /*!< 0x01000000 */ +#define ADC_SPT2_CSPT8_1 (0x2U << ADC_SPT2_CSPT8_Pos) /*!< 0x02000000 */ +#define ADC_SPT2_CSPT8_2 (0x4U << ADC_SPT2_CSPT8_Pos) /*!< 0x04000000 */ + +/*!< CSPT9 configuration */ +#define ADC_SPT2_CSPT9_Pos (27U) +#define ADC_SPT2_CSPT9_Msk (0x7U << ADC_SPT2_CSPT9_Pos) /*!< 0x38000000 */ +#define ADC_SPT2_CSPT9 ADC_SPT2_CSPT9_Msk /*!< CSPT9[2:0] bits (Sample time selection of channel ADC_IN9) */ +#define ADC_SPT2_CSPT9_0 (0x1U << ADC_SPT2_CSPT9_Pos) /*!< 0x08000000 */ +#define ADC_SPT2_CSPT9_1 (0x2U << ADC_SPT2_CSPT9_Pos) /*!< 0x10000000 */ +#define ADC_SPT2_CSPT9_2 (0x4U << ADC_SPT2_CSPT9_Pos) /*!< 0x20000000 */ + +/****************** Bit definition for ADC_PCDTO1 register ******************/ +#define ADC_PCDTO1_PCDTO1_Pos (0U) +#define ADC_PCDTO1_PCDTO1_Msk (0xFFFU << ADC_PCDTO1_PCDTO1_Pos) /*!< 0x00000FFF */ +#define ADC_PCDTO1_PCDTO1 ADC_PCDTO1_PCDTO1_Msk /*!< Data offset for Preempted channel 1 */ + +/****************** Bit definition for ADC_PCDTO2 register ******************/ +#define ADC_PCDTO2_PCDTO2_Pos (0U) +#define ADC_PCDTO2_PCDTO2_Msk (0xFFFU << ADC_PCDTO2_PCDTO2_Pos) /*!< 0x00000FFF */ +#define ADC_PCDTO2_PCDTO2 ADC_PCDTO2_PCDTO2_Msk /*!< Data offset for Preempted channel 2 */ + +/****************** Bit definition for ADC_PCDTO3 register ******************/ +#define ADC_PCDTO3_PCDTO3_Pos (0U) +#define ADC_PCDTO3_PCDTO3_Msk (0xFFFU << ADC_PCDTO3_PCDTO3_Pos) /*!< 0x00000FFF */ +#define ADC_PCDTO3_PCDTO3 ADC_PCDTO3_PCDTO3_Msk /*!< Data offset for Preempted channel 3 */ + +/****************** Bit definition for ADC_PCDTO4 register ******************/ +#define ADC_PCDTO4_PCDTO4_Pos (0U) +#define ADC_PCDTO4_PCDTO4_Msk (0xFFFU << ADC_PCDTO4_PCDTO4_Pos) /*!< 0x00000FFF */ +#define ADC_PCDTO4_PCDTO4 ADC_PCDTO4_PCDTO4_Msk /*!< Data offset for Preempted channel 4 */ + +/******************* Bit definition for ADC_VMHB register ********************/ +#define ADC_VMHB_VMHB_Pos (0U) +#define ADC_VMHB_VMHB_Msk (0xFFFFU << ADC_VMHB_VMHB_Pos) /*!< 0x0000FFFF */ +#define ADC_VMHB_VMHB ADC_VMHB_VMHB_Msk /*!< Voltage monitoring high boundary */ + +/******************* Bit definition for ADC_VMLB register ********************/ +#define ADC_VMLB_VMLB_Pos (0U) +#define ADC_VMLB_VMLB_Msk (0xFFFFU << ADC_VMLB_VMLB_Pos) /*!< 0x0000FFFF */ +#define ADC_VMLB_VMLB ADC_VMLB_VMLB_Msk /*!< Voltage monitoring low boundary */ + +/******************* Bit definition for ADC_OSQ1 register *******************/ +/*!< OSN13 configuration */ +#define ADC_OSQ1_OSN13_Pos (0U) +#define ADC_OSQ1_OSN13_Msk (0x1FU << ADC_OSQ1_OSN13_Pos) /*!< 0x0000001F */ +#define ADC_OSQ1_OSN13 ADC_OSQ1_OSN13_Msk /*!< OSN13[4:0] bits (Number of 13th conversion in ordinary sequence) */ +#define ADC_OSQ1_OSN13_0 (0x01U << ADC_OSQ1_OSN13_Pos) /*!< 0x00000001 */ +#define ADC_OSQ1_OSN13_1 (0x02U << ADC_OSQ1_OSN13_Pos) /*!< 0x00000002 */ +#define ADC_OSQ1_OSN13_2 (0x04U << ADC_OSQ1_OSN13_Pos) /*!< 0x00000004 */ +#define ADC_OSQ1_OSN13_3 (0x08U << ADC_OSQ1_OSN13_Pos) /*!< 0x00000008 */ +#define ADC_OSQ1_OSN13_4 (0x10U << ADC_OSQ1_OSN13_Pos) /*!< 0x00000010 */ + +/*!< OSN14 configuration */ +#define ADC_OSQ1_OSN14_Pos (5U) +#define ADC_OSQ1_OSN14_Msk (0x1FU << ADC_OSQ1_OSN14_Pos) /*!< 0x000003E0 */ +#define ADC_OSQ1_OSN14 ADC_OSQ1_OSN14_Msk /*!< OSN14[4:0] bits (Number of 14th conversion in ordinary sequence) */ +#define ADC_OSQ1_OSN14_0 (0x01U << ADC_OSQ1_OSN14_Pos) /*!< 0x00000020 */ +#define ADC_OSQ1_OSN14_1 (0x02U << ADC_OSQ1_OSN14_Pos) /*!< 0x00000040 */ +#define ADC_OSQ1_OSN14_2 (0x04U << ADC_OSQ1_OSN14_Pos) /*!< 0x00000080 */ +#define ADC_OSQ1_OSN14_3 (0x08U << ADC_OSQ1_OSN14_Pos) /*!< 0x00000100 */ +#define ADC_OSQ1_OSN14_4 (0x10U << ADC_OSQ1_OSN14_Pos) /*!< 0x00000200 */ + +/*!< OSN15 configuration */ +#define ADC_OSQ1_OSN15_Pos (10U) +#define ADC_OSQ1_OSN15_Msk (0x1FU << ADC_OSQ1_OSN15_Pos) /*!< 0x00007C00 */ +#define ADC_OSQ1_OSN15 ADC_OSQ1_OSN15_Msk /*!< OSN15[4:0] bits (Number of 15th conversion in ordinary sequence) */ +#define ADC_OSQ1_OSN15_0 (0x01U << ADC_OSQ1_OSN15_Pos) /*!< 0x00000400 */ +#define ADC_OSQ1_OSN15_1 (0x02U << ADC_OSQ1_OSN15_Pos) /*!< 0x00000800 */ +#define ADC_OSQ1_OSN15_2 (0x04U << ADC_OSQ1_OSN15_Pos) /*!< 0x00001000 */ +#define ADC_OSQ1_OSN15_3 (0x08U << ADC_OSQ1_OSN15_Pos) /*!< 0x00002000 */ +#define ADC_OSQ1_OSN15_4 (0x10U << ADC_OSQ1_OSN15_Pos) /*!< 0x00004000 */ + +/*!< OSN16 configuration */ +#define ADC_OSQ1_OSN16_Pos (15U) +#define ADC_OSQ1_OSN16_Msk (0x1FU << ADC_OSQ1_OSN16_Pos) /*!< 0x000F8000 */ +#define ADC_OSQ1_OSN16 ADC_OSQ1_OSN16_Msk /*!< OSN16[4:0] bits (Number of 16th conversion in ordinary sequence) */ +#define ADC_OSQ1_OSN16_0 (0x01U << ADC_OSQ1_OSN16_Pos) /*!< 0x00008000 */ +#define ADC_OSQ1_OSN16_1 (0x02U << ADC_OSQ1_OSN16_Pos) /*!< 0x00010000 */ +#define ADC_OSQ1_OSN16_2 (0x04U << ADC_OSQ1_OSN16_Pos) /*!< 0x00020000 */ +#define ADC_OSQ1_OSN16_3 (0x08U << ADC_OSQ1_OSN16_Pos) /*!< 0x00040000 */ +#define ADC_OSQ1_OSN16_4 (0x10U << ADC_OSQ1_OSN16_Pos) /*!< 0x00080000 */ + +/*!< OCLEN configuration */ +#define ADC_OSQ1_OCLEN_Pos (20U) +#define ADC_OSQ1_OCLEN_Msk (0xFU << ADC_OSQ1_OCLEN_Pos) /*!< 0x00F00000 */ +#define ADC_OSQ1_OCLEN ADC_OSQ1_OCLEN_Msk /*!< OCLEN[3:0] bits (Ordinary conversion sequence length) */ +#define ADC_OSQ1_OCLEN_0 (0x1U << ADC_OSQ1_OCLEN_Pos) /*!< 0x00100000 */ +#define ADC_OSQ1_OCLEN_1 (0x2U << ADC_OSQ1_OCLEN_Pos) /*!< 0x00200000 */ +#define ADC_OSQ1_OCLEN_2 (0x4U << ADC_OSQ1_OCLEN_Pos) /*!< 0x00400000 */ +#define ADC_OSQ1_OCLEN_3 (0x8U << ADC_OSQ1_OCLEN_Pos) /*!< 0x00800000 */ + +/******************* Bit definition for ADC_OSQ2 register *******************/ +/*!< OSN7 configuration */ +#define ADC_OSQ2_OSN7_Pos (0U) +#define ADC_OSQ2_OSN7_Msk (0x1FU << ADC_OSQ2_OSN7_Pos) /*!< 0x0000001F */ +#define ADC_OSQ2_OSN7 ADC_OSQ2_OSN7_Msk /*!< OSN7[4:0] bits (Number of 7th conversion in ordinary sequence) */ +#define ADC_OSQ2_OSN7_0 (0x01U << ADC_OSQ2_OSN7_Pos) /*!< 0x00000001 */ +#define ADC_OSQ2_OSN7_1 (0x02U << ADC_OSQ2_OSN7_Pos) /*!< 0x00000002 */ +#define ADC_OSQ2_OSN7_2 (0x04U << ADC_OSQ2_OSN7_Pos) /*!< 0x00000004 */ +#define ADC_OSQ2_OSN7_3 (0x08U << ADC_OSQ2_OSN7_Pos) /*!< 0x00000008 */ +#define ADC_OSQ2_OSN7_4 (0x10U << ADC_OSQ2_OSN7_Pos) /*!< 0x00000010 */ + +/*!< OSN8 configuration */ +#define ADC_OSQ2_OSN8_Pos (5U) +#define ADC_OSQ2_OSN8_Msk (0x1FU << ADC_OSQ2_OSN8_Pos) /*!< 0x000003E0 */ +#define ADC_OSQ2_OSN8 ADC_OSQ2_OSN8_Msk /*!< OSN8[4:0] bits (Number of 8th conversion in ordinary sequence) */ +#define ADC_OSQ2_OSN8_0 (0x01U << ADC_OSQ2_OSN8_Pos) /*!< 0x00000020 */ +#define ADC_OSQ2_OSN8_1 (0x02U << ADC_OSQ2_OSN8_Pos) /*!< 0x00000040 */ +#define ADC_OSQ2_OSN8_2 (0x04U << ADC_OSQ2_OSN8_Pos) /*!< 0x00000080 */ +#define ADC_OSQ2_OSN8_3 (0x08U << ADC_OSQ2_OSN8_Pos) /*!< 0x00000100 */ +#define ADC_OSQ2_OSN8_4 (0x10U << ADC_OSQ2_OSN8_Pos) /*!< 0x00000200 */ + +/*!< OSN9 configuration */ +#define ADC_OSQ2_OSN9_Pos (10U) +#define ADC_OSQ2_OSN9_Msk (0x1FU << ADC_OSQ2_OSN9_Pos) /*!< 0x00007C00 */ +#define ADC_OSQ2_OSN9 ADC_OSQ2_OSN9_Msk /*!< OSN9[4:0] bits (Number of 9th conversion in ordinary sequence) */ +#define ADC_OSQ2_OSN9_0 (0x01U << ADC_OSQ2_OSN9_Pos) /*!< 0x00000400 */ +#define ADC_OSQ2_OSN9_1 (0x02U << ADC_OSQ2_OSN9_Pos) /*!< 0x00000800 */ +#define ADC_OSQ2_OSN9_2 (0x04U << ADC_OSQ2_OSN9_Pos) /*!< 0x00001000 */ +#define ADC_OSQ2_OSN9_3 (0x08U << ADC_OSQ2_OSN9_Pos) /*!< 0x00002000 */ +#define ADC_OSQ2_OSN9_4 (0x10U << ADC_OSQ2_OSN9_Pos) /*!< 0x00004000 */ + +/*!< OSN10 configuration */ +#define ADC_OSQ2_OSN10_Pos (15U) +#define ADC_OSQ2_OSN10_Msk (0x1FU << ADC_OSQ2_OSN10_Pos) /*!< 0x000F8000 */ +#define ADC_OSQ2_OSN10 ADC_OSQ2_OSN10_Msk /*!< OSN10[4:0] bits (Number of 10th conversion in ordinary sequence) */ +#define ADC_OSQ2_OSN10_0 (0x01U << ADC_OSQ2_OSN10_Pos) /*!< 0x00008000 */ +#define ADC_OSQ2_OSN10_1 (0x02U << ADC_OSQ2_OSN10_Pos) /*!< 0x00010000 */ +#define ADC_OSQ2_OSN10_2 (0x04U << ADC_OSQ2_OSN10_Pos) /*!< 0x00020000 */ +#define ADC_OSQ2_OSN10_3 (0x08U << ADC_OSQ2_OSN10_Pos) /*!< 0x00040000 */ +#define ADC_OSQ2_OSN10_4 (0x10U << ADC_OSQ2_OSN10_Pos) /*!< 0x00080000 */ + +/*!< OSN11 configuration */ +#define ADC_OSQ2_OSN11_Pos (20U) +#define ADC_OSQ2_OSN11_Msk (0x1FU << ADC_OSQ2_OSN11_Pos) /*!< 0x01F00000 */ +#define ADC_OSQ2_OSN11 ADC_OSQ2_OSN11_Msk /*!< OSN11[4:0] bits (Number of 11th conversion in ordinary sequence) */ +#define ADC_OSQ2_OSN11_0 (0x01U << ADC_OSQ2_OSN11_Pos) /*!< 0x00100000 */ +#define ADC_OSQ2_OSN11_1 (0x02U << ADC_OSQ2_OSN11_Pos) /*!< 0x00200000 */ +#define ADC_OSQ2_OSN11_2 (0x04U << ADC_OSQ2_OSN11_Pos) /*!< 0x00400000 */ +#define ADC_OSQ2_OSN11_3 (0x08U << ADC_OSQ2_OSN11_Pos) /*!< 0x00800000 */ +#define ADC_OSQ2_OSN11_4 (0x10U << ADC_OSQ2_OSN11_Pos) /*!< 0x01000000 */ + +/*!< OSN12 configuration */ +#define ADC_OSQ2_OSN12_Pos (25U) +#define ADC_OSQ2_OSN12_Msk (0x1FU << ADC_OSQ2_OSN12_Pos) /*!< 0x3E000000 */ +#define ADC_OSQ2_OSN12 ADC_OSQ2_OSN12_Msk /*!< OSN12[4:0] bits (Number of 12th conversion in ordinary sequence) */ +#define ADC_OSQ2_OSN12_0 (0x01U << ADC_OSQ2_OSN12_Pos) /*!< 0x02000000 */ +#define ADC_OSQ2_OSN12_1 (0x02U << ADC_OSQ2_OSN12_Pos) /*!< 0x04000000 */ +#define ADC_OSQ2_OSN12_2 (0x04U << ADC_OSQ2_OSN12_Pos) /*!< 0x08000000 */ +#define ADC_OSQ2_OSN12_3 (0x08U << ADC_OSQ2_OSN12_Pos) /*!< 0x10000000 */ +#define ADC_OSQ2_OSN12_4 (0x10U << ADC_OSQ2_OSN12_Pos) /*!< 0x20000000 */ + +/******************* Bit definition for ADC_OSQ3 register *******************/ +/*!< OSN1 configuration */ +#define ADC_OSQ3_OSN1_Pos (0U) +#define ADC_OSQ3_OSN1_Msk (0x1FU << ADC_OSQ3_OSN1_Pos) /*!< 0x0000001F */ +#define ADC_OSQ3_OSN1 ADC_OSQ3_OSN1_Msk /*!< OSN1[4:0] bits (Number of 1st conversion in ordinary sequence) */ +#define ADC_OSQ3_OSN1_0 (0x01U << ADC_OSQ3_OSN1_Pos) /*!< 0x00000001 */ +#define ADC_OSQ3_OSN1_1 (0x02U << ADC_OSQ3_OSN1_Pos) /*!< 0x00000002 */ +#define ADC_OSQ3_OSN1_2 (0x04U << ADC_OSQ3_OSN1_Pos) /*!< 0x00000004 */ +#define ADC_OSQ3_OSN1_3 (0x08U << ADC_OSQ3_OSN1_Pos) /*!< 0x00000008 */ +#define ADC_OSQ3_OSN1_4 (0x10U << ADC_OSQ3_OSN1_Pos) /*!< 0x00000010 */ + +/*!< OSN2 configuration */ +#define ADC_OSQ3_OSN2_Pos (5U) +#define ADC_OSQ3_OSN2_Msk (0x1FU << ADC_OSQ3_OSN2_Pos) /*!< 0x000003E0 */ +#define ADC_OSQ3_OSN2 ADC_OSQ3_OSN2_Msk /*!< OSN2[4:0] bits (Number of 2nd conversion in ordinary sequence) */ +#define ADC_OSQ3_OSN2_0 (0x01U << ADC_OSQ3_OSN2_Pos) /*!< 0x00000020 */ +#define ADC_OSQ3_OSN2_1 (0x02U << ADC_OSQ3_OSN2_Pos) /*!< 0x00000040 */ +#define ADC_OSQ3_OSN2_2 (0x04U << ADC_OSQ3_OSN2_Pos) /*!< 0x00000080 */ +#define ADC_OSQ3_OSN2_3 (0x08U << ADC_OSQ3_OSN2_Pos) /*!< 0x00000100 */ +#define ADC_OSQ3_OSN2_4 (0x10U << ADC_OSQ3_OSN2_Pos) /*!< 0x00000200 */ + +/*!< OSN3 configuration */ +#define ADC_OSQ3_OSN3_Pos (10U) +#define ADC_OSQ3_OSN3_Msk (0x1FU << ADC_OSQ3_OSN3_Pos) /*!< 0x00007C00 */ +#define ADC_OSQ3_OSN3 ADC_OSQ3_OSN3_Msk /*!< OSN3[4:0] bits (Number of 3rd conversion in ordinary sequence) */ +#define ADC_OSQ3_OSN3_0 (0x01U << ADC_OSQ3_OSN3_Pos) /*!< 0x00000400 */ +#define ADC_OSQ3_OSN3_1 (0x02U << ADC_OSQ3_OSN3_Pos) /*!< 0x00000800 */ +#define ADC_OSQ3_OSN3_2 (0x04U << ADC_OSQ3_OSN3_Pos) /*!< 0x00001000 */ +#define ADC_OSQ3_OSN3_3 (0x08U << ADC_OSQ3_OSN3_Pos) /*!< 0x00002000 */ +#define ADC_OSQ3_OSN3_4 (0x10U << ADC_OSQ3_OSN3_Pos) /*!< 0x00004000 */ + +/*!< OSN4 configuration */ +#define ADC_OSQ3_OSN4_Pos (15U) +#define ADC_OSQ3_OSN4_Msk (0x1FU << ADC_OSQ3_OSN4_Pos) /*!< 0x000F8000 */ +#define ADC_OSQ3_OSN4 ADC_OSQ3_OSN4_Msk /*!< OSN4[4:0] bits (Number of 4th conversion in ordinary sequence) */ +#define ADC_OSQ3_OSN4_0 (0x01U << ADC_OSQ3_OSN4_Pos) /*!< 0x00008000 */ +#define ADC_OSQ3_OSN4_1 (0x02U << ADC_OSQ3_OSN4_Pos) /*!< 0x00010000 */ +#define ADC_OSQ3_OSN4_2 (0x04U << ADC_OSQ3_OSN4_Pos) /*!< 0x00020000 */ +#define ADC_OSQ3_OSN4_3 (0x08U << ADC_OSQ3_OSN4_Pos) /*!< 0x00040000 */ +#define ADC_OSQ3_OSN4_4 (0x10U << ADC_OSQ3_OSN4_Pos) /*!< 0x00080000 */ + +/*!< OSN5 configuration */ +#define ADC_OSQ3_OSN5_Pos (20U) +#define ADC_OSQ3_OSN5_Msk (0x1FU << ADC_OSQ3_OSN5_Pos) /*!< 0x01F00000 */ +#define ADC_OSQ3_OSN5 ADC_OSQ3_OSN5_Msk /*!< OSN5[4:0] bits (Number of 5th conversion in ordinary sequence) */ +#define ADC_OSQ3_OSN5_0 (0x01U << ADC_OSQ3_OSN5_Pos) /*!< 0x00100000 */ +#define ADC_OSQ3_OSN5_1 (0x02U << ADC_OSQ3_OSN5_Pos) /*!< 0x00200000 */ +#define ADC_OSQ3_OSN5_2 (0x04U << ADC_OSQ3_OSN5_Pos) /*!< 0x00400000 */ +#define ADC_OSQ3_OSN5_3 (0x08U << ADC_OSQ3_OSN5_Pos) /*!< 0x00800000 */ +#define ADC_OSQ3_OSN5_4 (0x10U << ADC_OSQ3_OSN5_Pos) /*!< 0x01000000 */ + +/*!< OSN6 configuration */ +#define ADC_OSQ3_OSN6_Pos (25U) +#define ADC_OSQ3_OSN6_Msk (0x1FU << ADC_OSQ3_OSN6_Pos) /*!< 0x3E000000 */ +#define ADC_OSQ3_OSN6 ADC_OSQ3_OSN6_Msk /*!< OSN6[4:0] bits (Number of 6th conversion in ordinary sequence) */ +#define ADC_OSQ3_OSN6_0 (0x01U << ADC_OSQ3_OSN6_Pos) /*!< 0x02000000 */ +#define ADC_OSQ3_OSN6_1 (0x02U << ADC_OSQ3_OSN6_Pos) /*!< 0x04000000 */ +#define ADC_OSQ3_OSN6_2 (0x04U << ADC_OSQ3_OSN6_Pos) /*!< 0x08000000 */ +#define ADC_OSQ3_OSN6_3 (0x08U << ADC_OSQ3_OSN6_Pos) /*!< 0x10000000 */ +#define ADC_OSQ3_OSN6_4 (0x10U << ADC_OSQ3_OSN6_Pos) /*!< 0x20000000 */ + +/******************* Bit definition for ADC_PSQ register ********************/ +/*!< PSN1 configuration */ +#define ADC_PSQ_PSN1_Pos (0U) +#define ADC_PSQ_PSN1_Msk (0x1FU << ADC_PSQ_PSN1_Pos) /*!< 0x0000001F */ +#define ADC_PSQ_PSN1 ADC_PSQ_PSN1_Msk /*!< PSN1[4:0] bits (Number of 1st conversion in preempted sequence) */ +#define ADC_PSQ_PSN1_0 (0x01U << ADC_PSQ_PSN1_Pos) /*!< 0x00000001 */ +#define ADC_PSQ_PSN1_1 (0x02U << ADC_PSQ_PSN1_Pos) /*!< 0x00000002 */ +#define ADC_PSQ_PSN1_2 (0x04U << ADC_PSQ_PSN1_Pos) /*!< 0x00000004 */ +#define ADC_PSQ_PSN1_3 (0x08U << ADC_PSQ_PSN1_Pos) /*!< 0x00000008 */ +#define ADC_PSQ_PSN1_4 (0x10U << ADC_PSQ_PSN1_Pos) /*!< 0x00000010 */ + +/*!< PSN2 configuration */ +#define ADC_PSQ_PSN2_Pos (5U) +#define ADC_PSQ_PSN2_Msk (0x1FU << ADC_PSQ_PSN2_Pos) /*!< 0x000003E0 */ +#define ADC_PSQ_PSN2 ADC_PSQ_PSN2_Msk /*!< PSN2[4:0] bits (Number of 2nd conversion in preempted sequence) */ +#define ADC_PSQ_PSN2_0 (0x01U << ADC_PSQ_PSN2_Pos) /*!< 0x00000020 */ +#define ADC_PSQ_PSN2_1 (0x02U << ADC_PSQ_PSN2_Pos) /*!< 0x00000040 */ +#define ADC_PSQ_PSN2_2 (0x04U << ADC_PSQ_PSN2_Pos) /*!< 0x00000080 */ +#define ADC_PSQ_PSN2_3 (0x08U << ADC_PSQ_PSN2_Pos) /*!< 0x00000100 */ +#define ADC_PSQ_PSN2_4 (0x10U << ADC_PSQ_PSN2_Pos) /*!< 0x00000200 */ + +/*!< PSN3 configuration */ +#define ADC_PSQ_PSN3_Pos (10U) +#define ADC_PSQ_PSN3_Msk (0x1FU << ADC_PSQ_PSN3_Pos) /*!< 0x00007C00 */ +#define ADC_PSQ_PSN3 ADC_PSQ_PSN3_Msk /*!< PSN3[4:0] bits (Number of 3rd conversion in preempted sequence) */ +#define ADC_PSQ_PSN3_0 (0x01U << ADC_PSQ_PSN3_Pos) /*!< 0x00000400 */ +#define ADC_PSQ_PSN3_1 (0x02U << ADC_PSQ_PSN3_Pos) /*!< 0x00000800 */ +#define ADC_PSQ_PSN3_2 (0x04U << ADC_PSQ_PSN3_Pos) /*!< 0x00001000 */ +#define ADC_PSQ_PSN3_3 (0x08U << ADC_PSQ_PSN3_Pos) /*!< 0x00002000 */ +#define ADC_PSQ_PSN3_4 (0x10U << ADC_PSQ_PSN3_Pos) /*!< 0x00004000 */ + +/*!< PSN4 configuration */ +#define ADC_PSQ_PSN4_Pos (15U) +#define ADC_PSQ_PSN4_Msk (0x1FU << ADC_PSQ_PSN4_Pos) /*!< 0x000F8000 */ +#define ADC_PSQ_PSN4 ADC_PSQ_PSN4_Msk /*!< PSN4[4:0] bits (Number of 4th conversion in preempted sequence) */ +#define ADC_PSQ_PSN4_0 (0x01U << ADC_PSQ_PSN4_Pos) /*!< 0x00008000 */ +#define ADC_PSQ_PSN4_1 (0x02U << ADC_PSQ_PSN4_Pos) /*!< 0x00010000 */ +#define ADC_PSQ_PSN4_2 (0x04U << ADC_PSQ_PSN4_Pos) /*!< 0x00020000 */ +#define ADC_PSQ_PSN4_3 (0x08U << ADC_PSQ_PSN4_Pos) /*!< 0x00040000 */ +#define ADC_PSQ_PSN4_4 (0x10U << ADC_PSQ_PSN4_Pos) /*!< 0x00080000 */ + +/*!< PCLEN configuration */ +#define ADC_PSQ_PCLEN_Pos (20U) +#define ADC_PSQ_PCLEN_Msk (0x3U << ADC_PSQ_PCLEN_Pos) /*!< 0x00300000 */ +#define ADC_PSQ_PCLEN ADC_PSQ_PCLEN_Msk /*!< PCLEN[1:0] bits (Preempted conversion sequence length) */ +#define ADC_PSQ_PCLEN_0 (0x1U << ADC_PSQ_PCLEN_Pos) /*!< 0x00100000 */ +#define ADC_PSQ_PCLEN_1 (0x2U << ADC_PSQ_PCLEN_Pos) /*!< 0x00200000 */ + +/******************* Bit definition for ADC_PDT1 register *******************/ +#define ADC_PDT1_PDT1_Pos (0U) +#define ADC_PDT1_PDT1_Msk (0xFFFFU << ADC_PDT1_PDT1_Pos) /*!< 0x0000FFFF */ +#define ADC_PDT1_PDT1 ADC_PDT1_PDT1_Msk /*!< Conversion data from preempted channel 1 */ + +/******************* Bit definition for ADC_PDT2 register *******************/ +#define ADC_PDT2_PDT2_Pos (0U) +#define ADC_PDT2_PDT2_Msk (0xFFFFU << ADC_PDT2_PDT2_Pos) /*!< 0x0000FFFF */ +#define ADC_PDT2_PDT2 ADC_PDT2_PDT2_Msk /*!< Conversion data from preempted channel 2 */ + +/******************* Bit definition for ADC_PDT3 register *******************/ +#define ADC_PDT3_PDT3_Pos (0U) +#define ADC_PDT3_PDT3_Msk (0xFFFFU << ADC_PDT3_PDT3_Pos) /*!< 0x0000FFFF */ +#define ADC_PDT3_PDT3 ADC_PDT3_PDT3_Msk /*!< Conversion data from preempted channel 3 */ + +/******************* Bit definition for ADC_PDT4 register *******************/ +#define ADC_PDT4_PDT4_Pos (0U) +#define ADC_PDT4_PDT4_Msk (0xFFFFU << ADC_PDT4_PDT4_Pos) /*!< 0x0000FFFF */ +#define ADC_PDT4_PDT4 ADC_PDT4_PDT4_Msk /*!< Conversion data from preempted channel 4 */ + +/******************* Bit definition for ADC_ODT register ********************/ +#define ADC_ODT_ODT_Pos (0U) +#define ADC_ODT_ODT_Msk (0xFFFFU << ADC_ODT_ODT_Pos) /*!< 0x0000FFFF */ +#define ADC_ODT_ODT ADC_ODT_ODT_Msk /*!< Conversion data of ordinary channel */ + +/******************* Bit definition for ADC_OVSP register *******************/ +#define ADC_OVSP_OOSEN_Pos (0U) +#define ADC_OVSP_OOSEN_Msk (0x1U << ADC_OVSP_OOSEN_Pos) /*!< 0x00000001 */ +#define ADC_OVSP_OOSEN ADC_OVSP_OOSEN_Msk /*!< Ordinary oversampling enable */ +#define ADC_OVSP_POSEN_Pos (1U) +#define ADC_OVSP_POSEN_Msk (0x1U << ADC_OVSP_POSEN_Pos) /*!< 0x00000002 */ +#define ADC_OVSP_POSEN ADC_OVSP_POSEN_Msk /*!< Preempted oversampling enable */ + +/*!< OSRSEL configuration */ +#define ADC_OVSP_OSRSEL_Pos (2U) +#define ADC_OVSP_OSRSEL_Msk (0x7U << ADC_OVSP_OSRSEL_Pos) /*!< 0x0000001C */ +#define ADC_OVSP_OSRSEL ADC_OVSP_OSRSEL_Msk /*!< OSRSEL[2:0] bits (Oversampling ratio select) */ +#define ADC_OVSP_OSRSEL_0 (0x1U << ADC_OVSP_OSRSEL_Pos) /*!< 0x00000004 */ +#define ADC_OVSP_OSRSEL_1 (0x2U << ADC_OVSP_OSRSEL_Pos) /*!< 0x00000008 */ +#define ADC_OVSP_OSRSEL_2 (0x4U << ADC_OVSP_OSRSEL_Pos) /*!< 0x00000010 */ + +#define ADC_OVSP_OSRSEL_MULTI2 0x00000000U /*!< 2x */ +#define ADC_OVSP_OSRSEL_MULTI4 0x00000004U /*!< 4x */ +#define ADC_OVSP_OSRSEL_MULTI8 0x00000008U /*!< 8x */ +#define ADC_OVSP_OSRSEL_MULTI16 0x0000000CU /*!< 16x */ +#define ADC_OVSP_OSRSEL_MULTI32 0x00000010U /*!< 32x */ +#define ADC_OVSP_OSRSEL_MULTI64 0x00000014U /*!< 64x */ +#define ADC_OVSP_OSRSEL_MULTI128 0x00000018U /*!< 128x */ +#define ADC_OVSP_OSRSEL_MULTI256 0x0000001CU /*!< 256x */ + +/*!< OSSSEL configuration */ +#define ADC_OVSP_OSSSEL_Pos (5U) +#define ADC_OVSP_OSSSEL_Msk (0xFU << ADC_OVSP_OSSSEL_Pos) /*!< 0x000001E0 */ +#define ADC_OVSP_OSSSEL ADC_OVSP_OSSSEL_Msk /*!< OSSSEL[3:0] bits (Oversampling shift select) */ +#define ADC_OVSP_OSSSEL_0 (0x1U << ADC_OVSP_OSSSEL_Pos) /*!< 0x00000020 */ +#define ADC_OVSP_OSSSEL_1 (0x2U << ADC_OVSP_OSSSEL_Pos) /*!< 0x00000040 */ +#define ADC_OVSP_OSSSEL_2 (0x4U << ADC_OVSP_OSSSEL_Pos) /*!< 0x00000080 */ +#define ADC_OVSP_OSSSEL_3 (0x8U << ADC_OVSP_OSSSEL_Pos) /*!< 0x00000100 */ + +#define ADC_OVSP_OSSSEL_NOSHIFT 0x00000000U /*!< No shift */ +#define ADC_OVSP_OSSSEL_SHIFT1 0x00000020U /*!< Shift 1 bit */ +#define ADC_OVSP_OSSSEL_SHIFT2 0x00000040U /*!< Shift 2 bit */ +#define ADC_OVSP_OSSSEL_SHIFT3 0x00000060U /*!< Shift 3 bit */ +#define ADC_OVSP_OSSSEL_SHIFT4 0x00000080U /*!< Shift 4 bit */ +#define ADC_OVSP_OSSSEL_SHIFT5 0x000000A0U /*!< Shift 5 bit */ +#define ADC_OVSP_OSSSEL_SHIFT6 0x000000C0U /*!< Shift 6 bit */ +#define ADC_OVSP_OSSSEL_SHIFT7 0x000000E0U /*!< Shift 7 bit */ +#define ADC_OVSP_OSSSEL_SHIFT8 0x00000100U /*!< Shift 8 bit */ + +#define ADC_OVSP_OOSTREN_Pos (9U) +#define ADC_OVSP_OOSTREN_Msk (0x1U << ADC_OVSP_OOSTREN_Pos) /*!< 0x00000200 */ +#define ADC_OVSP_OOSTREN ADC_OVSP_OOSTREN_Msk /*!< Ordinary oversampling trigger mode enable */ +#define ADC_OVSP_OOSRSEL_Pos (10U) +#define ADC_OVSP_OOSRSEL_Msk (0x1U << ADC_OVSP_OOSRSEL_Pos) /*!< 0x00000400 */ +#define ADC_OVSP_OOSRSEL ADC_OVSP_OOSRSEL_Msk /*!< Ordinary oversampling restart mode select */ + +/****************** Bit definition for ADC_CCTRL register *******************/ +/*!< ADCDIV configuration */ +#define ADC_CCTRL_ADCDIV_Pos (16U) +#define ADC_CCTRL_ADCDIV_Msk (0xFU << ADC_CCTRL_ADCDIV_Pos) /*!< 0x000F0000 */ +#define ADC_CCTRL_ADCDIV ADC_CCTRL_ADCDIV_Msk /*!< ADCDIV[3:0] bits (ADC division) */ +#define ADC_CCTRL_ADCDIV_0 (0x1U << ADC_CCTRL_ADCDIV_Pos) /*!< 0x00010000 */ +#define ADC_CCTRL_ADCDIV_1 (0x2U << ADC_CCTRL_ADCDIV_Pos) /*!< 0x00020000 */ +#define ADC_CCTRL_ADCDIV_2 (0x4U << ADC_CCTRL_ADCDIV_Pos) /*!< 0x00040000 */ +#define ADC_CCTRL_ADCDIV_3 (0x8U << ADC_CCTRL_ADCDIV_Pos) /*!< 0x00080000 */ + +#define ADC_CCTRL_ADCDIV_DIV2 0x00000000U /*!< HCLK/2 */ +#define ADC_CCTRL_ADCDIV_DIV3 0x00010000U /*!< HCLK/3 */ +#define ADC_CCTRL_ADCDIV_DIV4 0x00020000U /*!< HCLK/4 */ +#define ADC_CCTRL_ADCDIV_DIV5 0x00030000U /*!< HCLK/5 */ +#define ADC_CCTRL_ADCDIV_DIV6 0x00040000U /*!< HCLK/6 */ +#define ADC_CCTRL_ADCDIV_DIV7 0x00050000U /*!< HCLK/7 */ +#define ADC_CCTRL_ADCDIV_DIV8 0x00060000U /*!< HCLK/8 */ +#define ADC_CCTRL_ADCDIV_DIV9 0x00070000U /*!< HCLK/9 */ +#define ADC_CCTRL_ADCDIV_DIV10 0x00080000U /*!< HCLK/10 */ +#define ADC_CCTRL_ADCDIV_DIV11 0x00090000U /*!< HCLK/11 */ +#define ADC_CCTRL_ADCDIV_DIV12 0x000A0000U /*!< HCLK/12 */ +#define ADC_CCTRL_ADCDIV_DIV13 0x000B0000U /*!< HCLK/13 */ +#define ADC_CCTRL_ADCDIV_DIV14 0x000C0000U /*!< HCLK/14 */ +#define ADC_CCTRL_ADCDIV_DIV15 0x000D0000U /*!< HCLK/15 */ +#define ADC_CCTRL_ADCDIV_DIV16 0x000E0000U /*!< HCLK/16 */ +#define ADC_CCTRL_ADCDIV_DIV17 0x000F0000U /*!< HCLK/17 */ + +/******************************************************************************/ +/* */ +/* Controller Area Network (CAN) */ +/* */ +/******************************************************************************/ + +/*!< CAN control and status registers */ +/****************** Bit definition for CAN_MCTRL register *******************/ +#define CAN_MCTRL_FZEN_Pos (0U) +#define CAN_MCTRL_FZEN_Msk (0x1U << CAN_MCTRL_FZEN_Pos) /*!< 0x00000001 */ +#define CAN_MCTRL_FZEN CAN_MCTRL_FZEN_Msk /*!< Freeze mode enable */ +#define CAN_MCTRL_DZEN_Pos (1U) +#define CAN_MCTRL_DZEN_Msk (0x1U << CAN_MCTRL_DZEN_Pos) /*!< 0x00000002 */ +#define CAN_MCTRL_DZEN CAN_MCTRL_DZEN_Msk /*!< Doze mode enable */ +#define CAN_MCTRL_MMSSR_Pos (2U) +#define CAN_MCTRL_MMSSR_Msk (0x1U << CAN_MCTRL_MMSSR_Pos) /*!< 0x00000004 */ +#define CAN_MCTRL_MMSSR CAN_MCTRL_MMSSR_Msk /*!< Multiple message transmit sequence rule */ +#define CAN_MCTRL_MDRSEL_Pos (3U) +#define CAN_MCTRL_MDRSEL_Msk (0x1U << CAN_MCTRL_MDRSEL_Pos) /*!< 0x00000008 */ +#define CAN_MCTRL_MDRSEL CAN_MCTRL_MDRSEL_Msk /*!< Message discard rule select when overflow */ +#define CAN_MCTRL_PRSFEN_Pos (4U) +#define CAN_MCTRL_PRSFEN_Msk (0x1U << CAN_MCTRL_PRSFEN_Pos) /*!< 0x00000010 */ +#define CAN_MCTRL_PRSFEN CAN_MCTRL_PRSFEN_Msk /*!< Prohibit retransmission enable when sending fails enable */ +#define CAN_MCTRL_AEDEN_Pos (5U) +#define CAN_MCTRL_AEDEN_Msk (0x1U << CAN_MCTRL_AEDEN_Pos) /*!< 0x00000020 */ +#define CAN_MCTRL_AEDEN CAN_MCTRL_AEDEN_Msk /*!< Automatic exit doze mode enable */ +#define CAN_MCTRL_AEBOEN_Pos (6U) +#define CAN_MCTRL_AEBOEN_Msk (0x1U << CAN_MCTRL_AEBOEN_Pos) /*!< 0x00000040 */ +#define CAN_MCTRL_AEBOEN CAN_MCTRL_AEBOEN_Msk /*!< Automatic exit bus-off enable */ +#define CAN_MCTRL_TTCEN_Pos (7U) +#define CAN_MCTRL_TTCEN_Msk (0x1U << CAN_MCTRL_TTCEN_Pos) /*!< 0x00000080 */ +#define CAN_MCTRL_TTCEN CAN_MCTRL_TTCEN_Msk /*!< Time triggered communication mode enable */ +#define CAN_MCTRL_SPRST_Pos (15U) +#define CAN_MCTRL_SPRST_Msk (0x1U << CAN_MCTRL_SPRST_Pos) /*!< 0x00008000 */ +#define CAN_MCTRL_SPRST CAN_MCTRL_SPRST_Msk /*!< Software partial reset */ +#define CAN_MCTRL_PTD_Pos (16U) +#define CAN_MCTRL_PTD_Msk (0x1U << CAN_MCTRL_PTD_Pos) /*!< 0x00010000 */ +#define CAN_MCTRL_PTD CAN_MCTRL_PTD_Msk /*!< Prohibit trans when debug */ + +/******************* Bit definition for CAN_MSTS register *******************/ +#define CAN_MSTS_FZC_Pos (0U) +#define CAN_MSTS_FZC_Msk (0x1U << CAN_MSTS_FZC_Pos) /*!< 0x00000001 */ +#define CAN_MSTS_FZC CAN_MSTS_FZC_Msk /*!< Freeze mode confirm */ +#define CAN_MSTS_DZC_Pos (1U) +#define CAN_MSTS_DZC_Msk (0x1U << CAN_MSTS_DZC_Pos) /*!< 0x00000002 */ +#define CAN_MSTS_DZC CAN_MSTS_DZC_Msk /*!< Doze mode acknowledge */ +#define CAN_MSTS_EOIF_Pos (2U) +#define CAN_MSTS_EOIF_Msk (0x1U << CAN_MSTS_EOIF_Pos) /*!< 0x00000004 */ +#define CAN_MSTS_EOIF CAN_MSTS_EOIF_Msk /*!< Error occur interrupt flag */ +#define CAN_MSTS_QDZIF_Pos (3U) +#define CAN_MSTS_QDZIF_Msk (0x1U << CAN_MSTS_QDZIF_Pos) /*!< 0x00000008 */ +#define CAN_MSTS_QDZIF CAN_MSTS_QDZIF_Msk /*!< Exit doze mode interrupt flag */ +#define CAN_MSTS_EDZIF_Pos (4U) +#define CAN_MSTS_EDZIF_Msk (0x1U << CAN_MSTS_EDZIF_Pos) /*!< 0x00000010 */ +#define CAN_MSTS_EDZIF CAN_MSTS_EDZIF_Msk /*!< Enter doze mode interrupt flag */ +#define CAN_MSTS_CUSS_Pos (8U) +#define CAN_MSTS_CUSS_Msk (0x1U << CAN_MSTS_CUSS_Pos) /*!< 0x00000100 */ +#define CAN_MSTS_CUSS CAN_MSTS_CUSS_Msk /*!< Current transmit status */ +#define CAN_MSTS_CURS_Pos (9U) +#define CAN_MSTS_CURS_Msk (0x1U << CAN_MSTS_CURS_Pos) /*!< 0x00000200 */ +#define CAN_MSTS_CURS CAN_MSTS_CURS_Msk /*!< Current receive status */ +#define CAN_MSTS_LSAMPRX_Pos (10U) +#define CAN_MSTS_LSAMPRX_Msk (0x1U << CAN_MSTS_LSAMPRX_Pos) /*!< 0x00000400 */ +#define CAN_MSTS_LSAMPRX CAN_MSTS_LSAMPRX_Msk /*!< Last sample level on RX pin */ +#define CAN_MSTS_REALRX_Pos (11U) +#define CAN_MSTS_REALRX_Msk (0x1U << CAN_MSTS_REALRX_Pos) /*!< 0x00000800 */ +#define CAN_MSTS_REALRX CAN_MSTS_REALRX_Msk /*!< Real time level on RX pin */ + +/******************* Bit definition for CAN_TSTS register *******************/ +#define CAN_TSTS_TM0TCF_Pos (0U) +#define CAN_TSTS_TM0TCF_Msk (0x1U << CAN_TSTS_TM0TCF_Pos) /*!< 0x00000001 */ +#define CAN_TSTS_TM0TCF CAN_TSTS_TM0TCF_Msk /*!< Transmit mailbox 0 transmission completed flag */ +#define CAN_TSTS_TM0TSF_Pos (1U) +#define CAN_TSTS_TM0TSF_Msk (0x1U << CAN_TSTS_TM0TSF_Pos) /*!< 0x00000002 */ +#define CAN_TSTS_TM0TSF CAN_TSTS_TM0TSF_Msk /*!< Transmit mailbox 0 transmission success flag */ +#define CAN_TSTS_TM0ALF_Pos (2U) +#define CAN_TSTS_TM0ALF_Msk (0x1U << CAN_TSTS_TM0ALF_Pos) /*!< 0x00000004 */ +#define CAN_TSTS_TM0ALF CAN_TSTS_TM0ALF_Msk /*!< Transmit mailbox 0 arbitration lost flag */ +#define CAN_TSTS_TM0TEF_Pos (3U) +#define CAN_TSTS_TM0TEF_Msk (0x1U << CAN_TSTS_TM0TEF_Pos) /*!< 0x00000008 */ +#define CAN_TSTS_TM0TEF CAN_TSTS_TM0TEF_Msk /*!< Transmit mailbox 0 transmission error flag */ +#define CAN_TSTS_TM0CT_Pos (7U) +#define CAN_TSTS_TM0CT_Msk (0x1U << CAN_TSTS_TM0CT_Pos) /*!< 0x00000080 */ +#define CAN_TSTS_TM0CT CAN_TSTS_TM0CT_Msk /*!< Transmit mailbox 0 cancel transmit */ +#define CAN_TSTS_TM1TCF_Pos (8U) +#define CAN_TSTS_TM1TCF_Msk (0x1U << CAN_TSTS_TM1TCF_Pos) /*!< 0x00000100 */ +#define CAN_TSTS_TM1TCF CAN_TSTS_TM1TCF_Msk /*!< Transmit mailbox 1 transmission completed flag */ +#define CAN_TSTS_TM1TSF_Pos (9U) +#define CAN_TSTS_TM1TSF_Msk (0x1U << CAN_TSTS_TM1TSF_Pos) /*!< 0x00000200 */ +#define CAN_TSTS_TM1TSF CAN_TSTS_TM1TSF_Msk /*!< Transmit mailbox 1 transmission success flag */ +#define CAN_TSTS_TM1ALF_Pos (10U) +#define CAN_TSTS_TM1ALF_Msk (0x1U << CAN_TSTS_TM1ALF_Pos) /*!< 0x00000400 */ +#define CAN_TSTS_TM1ALF CAN_TSTS_TM1ALF_Msk /*!< Transmit mailbox 1 arbitration lost flag */ +#define CAN_TSTS_TM1TEF_Pos (11U) +#define CAN_TSTS_TM1TEF_Msk (0x1U << CAN_TSTS_TM1TEF_Pos) /*!< 0x00000800 */ +#define CAN_TSTS_TM1TEF CAN_TSTS_TM1TEF_Msk /*!< Transmit mailbox 1 transmission error flag */ +#define CAN_TSTS_TM1CT_Pos (15U) +#define CAN_TSTS_TM1CT_Msk (0x1U << CAN_TSTS_TM1CT_Pos) /*!< 0x00008000 */ +#define CAN_TSTS_TM1CT CAN_TSTS_TM1CT_Msk /*!< Transmit mailbox 1 cancel transmit */ +#define CAN_TSTS_TM2TCF_Pos (16U) +#define CAN_TSTS_TM2TCF_Msk (0x1U << CAN_TSTS_TM2TCF_Pos) /*!< 0x00010000 */ +#define CAN_TSTS_TM2TCF CAN_TSTS_TM2TCF_Msk /*!< Transmit mailbox 2 transmission completed flag */ +#define CAN_TSTS_TM2TSF_Pos (17U) +#define CAN_TSTS_TM2TSF_Msk (0x1U << CAN_TSTS_TM2TSF_Pos) /*!< 0x00020000 */ +#define CAN_TSTS_TM2TSF CAN_TSTS_TM2TSF_Msk /*!< Transmit mailbox 2 transmission success flag */ +#define CAN_TSTS_TM2ALF_Pos (18U) +#define CAN_TSTS_TM2ALF_Msk (0x1U << CAN_TSTS_TM2ALF_Pos) /*!< 0x00040000 */ +#define CAN_TSTS_TM2ALF CAN_TSTS_TM2ALF_Msk /*!< Transmit mailbox 2 arbitration lost flag */ +#define CAN_TSTS_TM2TEF_Pos (19U) +#define CAN_TSTS_TM2TEF_Msk (0x1U << CAN_TSTS_TM2TEF_Pos) /*!< 0x00080000 */ +#define CAN_TSTS_TM2TEF CAN_TSTS_TM2TEF_Msk /*!< Transmit mailbox 2 transmission error flag */ +#define CAN_TSTS_TM2CT_Pos (23U) +#define CAN_TSTS_TM2CT_Msk (0x1U << CAN_TSTS_TM2CT_Pos) /*!< 0x00800000 */ +#define CAN_TSTS_TM2CT CAN_TSTS_TM2CT_Msk /*!< Transmit mailbox 2 cancel transmit */ +#define CAN_TSTS_TMNR_Pos (24U) +#define CAN_TSTS_TMNR_Msk (0x3U << CAN_TSTS_TMNR_Pos) /*!< 0x03000000 */ +#define CAN_TSTS_TMNR CAN_TSTS_TMNR_Msk /*!< TMNR[1:0] bits (Transmit mailbox number record) */ + +/*!< TMEF congiguration */ +#define CAN_TSTS_TMEF_Pos (26U) +#define CAN_TSTS_TMEF_Msk (0x7U << CAN_TSTS_TMEF_Pos) /*!< 0x1C000000 */ +#define CAN_TSTS_TMEF CAN_TSTS_TMEF_Msk /*!< TMEF[2:0] bits (Transmit mailbox empty flag) */ +#define CAN_TSTS_TM0EF_Pos (26U) +#define CAN_TSTS_TM0EF_Msk (0x1U << CAN_TSTS_TM0EF_Pos) /*!< 0x04000000 */ +#define CAN_TSTS_TM0EF CAN_TSTS_TM0EF_Msk /*!< Transmit mailbox 0 empty flag */ +#define CAN_TSTS_TM1EF_Pos (27U) +#define CAN_TSTS_TM1EF_Msk (0x1U << CAN_TSTS_TM1EF_Pos) /*!< 0x08000000 */ +#define CAN_TSTS_TM1EF CAN_TSTS_TM1EF_Msk /*!< Transmit mailbox 1 empty flag */ +#define CAN_TSTS_TM2EF_Pos (28U) +#define CAN_TSTS_TM2EF_Msk (0x1U << CAN_TSTS_TM2EF_Pos) /*!< 0x10000000 */ +#define CAN_TSTS_TM2EF CAN_TSTS_TM2EF_Msk /*!< Transmit mailbox 2 empty flag */ + +/*!< TMLPF congiguration */ +#define CAN_TSTS_TMLPF_Pos (29U) +#define CAN_TSTS_TMLPF_Msk (0x7U << CAN_TSTS_TMLPF_Pos) /*!< 0xE0000000 */ +#define CAN_TSTS_TMLPF CAN_TSTS_TMLPF_Msk /*!< TMLPF[2:0] bits (Transmit mailbox lowest priority flag) */ +#define CAN_TSTS_TM0LPF_Pos (29U) +#define CAN_TSTS_TM0LPF_Msk (0x1U << CAN_TSTS_TM0LPF_Pos) /*!< 0x20000000 */ +#define CAN_TSTS_TM0LPF CAN_TSTS_TM0LPF_Msk /*!< Transmit mailbox 0 lowest priority flag */ +#define CAN_TSTS_TM1LPF_Pos (30U) +#define CAN_TSTS_TM1LPF_Msk (0x1U << CAN_TSTS_TM1LPF_Pos) /*!< 0x40000000 */ +#define CAN_TSTS_TM1LPF CAN_TSTS_TM1LPF_Msk /*!< Transmit mailbox 1 lowest priority flag */ +#define CAN_TSTS_TM2LPF_Pos (31U) +#define CAN_TSTS_TM2LPF_Msk (0x1U << CAN_TSTS_TM2LPF_Pos) /*!< 0x80000000 */ +#define CAN_TSTS_TM2LPF CAN_TSTS_TM2LPF_Msk /*!< Transmit mailbox 2 lowest priority flag */ + +/******************* Bit definition for CAN_RF0 register ********************/ +#define CAN_RF0_RF0MN_Pos (0U) +#define CAN_RF0_RF0MN_Msk (0x3U << CAN_RF0_RF0MN_Pos) /*!< 0x00000003 */ +#define CAN_RF0_RF0MN CAN_RF0_RF0MN_Msk /*!< Receive FIFO 0 message num */ +#define CAN_RF0_RF0FF_Pos (3U) +#define CAN_RF0_RF0FF_Msk (0x1U << CAN_RF0_RF0FF_Pos) /*!< 0x00000008 */ +#define CAN_RF0_RF0FF CAN_RF0_RF0FF_Msk /*!< Receive FIFO 0 full flag */ +#define CAN_RF0_RF0OF_Pos (4U) +#define CAN_RF0_RF0OF_Msk (0x1U << CAN_RF0_RF0OF_Pos) /*!< 0x00000010 */ +#define CAN_RF0_RF0OF CAN_RF0_RF0OF_Msk /*!< Receive FIFO 0 overflow flag */ +#define CAN_RF0_RF0R_Pos (5U) +#define CAN_RF0_RF0R_Msk (0x1U << CAN_RF0_RF0R_Pos) /*!< 0x00000020 */ +#define CAN_RF0_RF0R CAN_RF0_RF0R_Msk /*!< Receive FIFO 0 release */ + +/******************* Bit definition for CAN_RF1 register ********************/ +#define CAN_RF1_RF1MN_Pos (0U) +#define CAN_RF1_RF1MN_Msk (0x3U << CAN_RF1_RF1MN_Pos) /*!< 0x00000003 */ +#define CAN_RF1_RF1MN CAN_RF1_RF1MN_Msk /*!< Receive FIFO 1 message num */ +#define CAN_RF1_RF1FF_Pos (3U) +#define CAN_RF1_RF1FF_Msk (0x1U << CAN_RF1_RF1FF_Pos) /*!< 0x00000008 */ +#define CAN_RF1_RF1FF CAN_RF1_RF1FF_Msk /*!< Receive FIFO 1 full flag */ +#define CAN_RF1_RF1OF_Pos (4U) +#define CAN_RF1_RF1OF_Msk (0x1U << CAN_RF1_RF1OF_Pos) /*!< 0x00000010 */ +#define CAN_RF1_RF1OF CAN_RF1_RF1OF_Msk /*!< Receive FIFO 1 overflow flag */ +#define CAN_RF1_RF1R_Pos (5U) +#define CAN_RF1_RF1R_Msk (0x1U << CAN_RF1_RF1R_Pos) /*!< 0x00000020 */ +#define CAN_RF1_RF1R CAN_RF1_RF1R_Msk /*!< Receive FIFO 1 release */ + +/****************** Bit definition for CAN_INTEN register *******************/ +#define CAN_INTEN_TCIEN_Pos (0U) +#define CAN_INTEN_TCIEN_Msk (0x1U << CAN_INTEN_TCIEN_Pos) /*!< 0x00000001 */ +#define CAN_INTEN_TCIEN CAN_INTEN_TCIEN_Msk /*!< Transmit mailbox empty interrupt enable */ +#define CAN_INTEN_RF0MIEN_Pos (1U) +#define CAN_INTEN_RF0MIEN_Msk (0x1U << CAN_INTEN_RF0MIEN_Pos) /*!< 0x00000002 */ +#define CAN_INTEN_RF0MIEN CAN_INTEN_RF0MIEN_Msk /*!< FIFO 0 receive message interrupt enable */ +#define CAN_INTEN_RF0FIEN_Pos (2U) +#define CAN_INTEN_RF0FIEN_Msk (0x1U << CAN_INTEN_RF0FIEN_Pos) /*!< 0x00000004 */ +#define CAN_INTEN_RF0FIEN CAN_INTEN_RF0FIEN_Msk /*!< Receive FIFO 0 full interrupt enable */ +#define CAN_INTEN_RF0OIEN_Pos (3U) +#define CAN_INTEN_RF0OIEN_Msk (0x1U << CAN_INTEN_RF0OIEN_Pos) /*!< 0x00000008 */ +#define CAN_INTEN_RF0OIEN CAN_INTEN_RF0OIEN_Msk /*!< Receive FIFO 0 overflow interrupt enable */ +#define CAN_INTEN_RF1MIEN_Pos (4U) +#define CAN_INTEN_RF1MIEN_Msk (0x1U << CAN_INTEN_RF1MIEN_Pos) /*!< 0x00000010 */ +#define CAN_INTEN_RF1MIEN CAN_INTEN_RF1MIEN_Msk /*!< FIFO 1 receive message interrupt enable */ +#define CAN_INTEN_RF1FIEN_Pos (5U) +#define CAN_INTEN_RF1FIEN_Msk (0x1U << CAN_INTEN_RF1FIEN_Pos) /*!< 0x00000020 */ +#define CAN_INTEN_RF1FIEN CAN_INTEN_RF1FIEN_Msk /*!< Receive FIFO 1 full interrupt enable */ +#define CAN_INTEN_RF1OIEN_Pos (6U) +#define CAN_INTEN_RF1OIEN_Msk (0x1U << CAN_INTEN_RF1OIEN_Pos) /*!< 0x00000040 */ +#define CAN_INTEN_RF1OIEN CAN_INTEN_RF1OIEN_Msk /*!< Receive FIFO 1 overflow interrupt enable */ +#define CAN_INTEN_EAIEN_Pos (8U) +#define CAN_INTEN_EAIEN_Msk (0x1U << CAN_INTEN_EAIEN_Pos) /*!< 0x00000100 */ +#define CAN_INTEN_EAIEN CAN_INTEN_EAIEN_Msk /*!< Error active interrupt enable */ +#define CAN_INTEN_EPIEN_Pos (9U) +#define CAN_INTEN_EPIEN_Msk (0x1U << CAN_INTEN_EPIEN_Pos) /*!< 0x00000200 */ +#define CAN_INTEN_EPIEN CAN_INTEN_EPIEN_Msk /*!< Error passive interrupt enable */ +#define CAN_INTEN_BOIEN_Pos (10U) +#define CAN_INTEN_BOIEN_Msk (0x1U << CAN_INTEN_BOIEN_Pos) /*!< 0x00000400 */ +#define CAN_INTEN_BOIEN CAN_INTEN_BOIEN_Msk /*!< Bus-off interrupt enable */ +#define CAN_INTEN_ETRIEN_Pos (11U) +#define CAN_INTEN_ETRIEN_Msk (0x1U << CAN_INTEN_ETRIEN_Pos) /*!< 0x00000800 */ +#define CAN_INTEN_ETRIEN CAN_INTEN_ETRIEN_Msk /*!< Error type record interrupt enable */ +#define CAN_INTEN_EOIEN_Pos (15U) +#define CAN_INTEN_EOIEN_Msk (0x1U << CAN_INTEN_EOIEN_Pos) /*!< 0x00008000 */ +#define CAN_INTEN_EOIEN CAN_INTEN_EOIEN_Msk /*!< Error occur interrupt enable */ +#define CAN_INTEN_QDZIEN_Pos (16U) +#define CAN_INTEN_QDZIEN_Msk (0x1U << CAN_INTEN_QDZIEN_Pos) /*!< 0x00010000 */ +#define CAN_INTEN_QDZIEN CAN_INTEN_QDZIEN_Msk /*!< Quit doze mode interrupt enable */ +#define CAN_INTEN_EDZIEN_Pos (17U) +#define CAN_INTEN_EDZIEN_Msk (0x1U << CAN_INTEN_EDZIEN_Pos) /*!< 0x00020000 */ +#define CAN_INTEN_EDZIEN CAN_INTEN_EDZIEN_Msk /*!< Enter doze mode interrupt enable */ + +/******************* Bit definition for CAN_ESTS register *******************/ +#define CAN_ESTS_EAF_Pos (0U) +#define CAN_ESTS_EAF_Msk (0x1U << CAN_ESTS_EAF_Pos) /*!< 0x00000001 */ +#define CAN_ESTS_EAF CAN_ESTS_EAF_Msk /*!< Error active flag */ +#define CAN_ESTS_EPF_Pos (1U) +#define CAN_ESTS_EPF_Msk (0x1U << CAN_ESTS_EPF_Pos) /*!< 0x00000002 */ +#define CAN_ESTS_EPF CAN_ESTS_EPF_Msk /*!< Error passive flag */ +#define CAN_ESTS_BOF_Pos (2U) +#define CAN_ESTS_BOF_Msk (0x1U << CAN_ESTS_BOF_Pos) /*!< 0x00000004 */ +#define CAN_ESTS_BOF CAN_ESTS_BOF_Msk /*!< Bus-off flag */ + +/*!< ETR congiguration */ +#define CAN_ESTS_ETR_Pos (4U) +#define CAN_ESTS_ETR_Msk (0x7U << CAN_ESTS_ETR_Pos) /*!< 0x00000070 */ +#define CAN_ESTS_ETR CAN_ESTS_ETR_Msk /*!< ETR[2:0] bits (Error type record) */ +#define CAN_ESTS_ETR_0 (0x1U << CAN_ESTS_ETR_Pos) /*!< 0x00000010 */ +#define CAN_ESTS_ETR_1 (0x2U << CAN_ESTS_ETR_Pos) /*!< 0x00000020 */ +#define CAN_ESTS_ETR_2 (0x4U << CAN_ESTS_ETR_Pos) /*!< 0x00000040 */ + +#define CAN_ESTS_TEC_Pos (16U) +#define CAN_ESTS_TEC_Msk (0xFFU << CAN_ESTS_TEC_Pos) /*!< 0x00FF0000 */ +#define CAN_ESTS_TEC CAN_ESTS_TEC_Msk /*!< Transmit error counter */ +#define CAN_ESTS_REC_Pos (24U) +#define CAN_ESTS_REC_Msk (0xFFU << CAN_ESTS_REC_Pos) /*!< 0xFF000000 */ +#define CAN_ESTS_REC CAN_ESTS_REC_Msk /*!< Receive error counter */ + +/******************* Bit definition for CAN_BTMG register ********************/ +#define CAN_BTMG_BRDIV_Pos (0U) +#define CAN_BTMG_BRDIV_Msk (0xFFFU << CAN_BTMG_BRDIV_Pos) /*!< 0x00000FFF */ +#define CAN_BTMG_BRDIV CAN_BTMG_BRDIV_Msk /*!< Baud rate division */ + +/*!< BTS1 congiguration */ +#define CAN_BTMG_BTS1_Pos (16U) +#define CAN_BTMG_BTS1_Msk (0xFU << CAN_BTMG_BTS1_Pos) /*!< 0x000F0000 */ +#define CAN_BTMG_BTS1 CAN_BTMG_BTS1_Msk /*!< BTS1[3:0] bits (Bit time segment 1) */ +#define CAN_BTMG_BTS1_0 (0x1U << CAN_BTMG_BTS1_Pos) /*!< 0x00010000 */ +#define CAN_BTMG_BTS1_1 (0x2U << CAN_BTMG_BTS1_Pos) /*!< 0x00020000 */ +#define CAN_BTMG_BTS1_2 (0x4U << CAN_BTMG_BTS1_Pos) /*!< 0x00040000 */ +#define CAN_BTMG_BTS1_3 (0x8U << CAN_BTMG_BTS1_Pos) /*!< 0x00080000 */ + +/*!< BTS2 congiguration */ +#define CAN_BTMG_BTS2_Pos (20U) +#define CAN_BTMG_BTS2_Msk (0x7U << CAN_BTMG_BTS2_Pos) /*!< 0x00700000 */ +#define CAN_BTMG_BTS2 CAN_BTMG_BTS2_Msk /*!< BTS2[2:0] bits (Bit time segment 2) */ +#define CAN_BTMG_BTS2_0 (0x1U << CAN_BTMG_BTS2_Pos) /*!< 0x00100000 */ +#define CAN_BTMG_BTS2_1 (0x2U << CAN_BTMG_BTS2_Pos) /*!< 0x00200000 */ +#define CAN_BTMG_BTS2_2 (0x4U << CAN_BTMG_BTS2_Pos) /*!< 0x00400000 */ + +/*!< RSAW congiguration */ +#define CAN_BTMG_RSAW_Pos (24U) +#define CAN_BTMG_RSAW_Msk (0x3U << CAN_BTMG_RSAW_Pos) /*!< 0x03000000 */ +#define CAN_BTMG_RSAW CAN_BTMG_RSAW_Msk /*!< RSAW[1:0] bits (Resynchronization width) */ +#define CAN_BTMG_RSAW_0 (0x1U << CAN_BTMG_RSAW_Pos) /*!< 0x01000000 */ +#define CAN_BTMG_RSAW_1 (0x2U << CAN_BTMG_RSAW_Pos) /*!< 0x02000000 */ + +#define CAN_BTMG_LBEN_Pos (30U) +#define CAN_BTMG_LBEN_Msk (0x1U << CAN_BTMG_LBEN_Pos) /*!< 0x40000000 */ +#define CAN_BTMG_LBEN CAN_BTMG_LBEN_Msk /*!< Loop back mode */ +#define CAN_BTMG_LOEN_Pos (31U) +#define CAN_BTMG_LOEN_Msk (0x1U << CAN_BTMG_LOEN_Pos) /*!< 0x80000000 */ +#define CAN_BTMG_LOEN CAN_BTMG_LOEN_Msk /*!< Listen-Only mode */ + +/*!< Mailbox registers */ +/******************* Bit definition for CAN_TMI0 register *******************/ +#define CAN_TMI0_TMSR_Pos (0U) +#define CAN_TMI0_TMSR_Msk (0x1U << CAN_TMI0_TMSR_Pos) /*!< 0x00000001 */ +#define CAN_TMI0_TMSR CAN_TMI0_TMSR_Msk /*!< Transmit mailbox send request */ +#define CAN_TMI0_TMFRSEL_Pos (1U) +#define CAN_TMI0_TMFRSEL_Msk (0x1U << CAN_TMI0_TMFRSEL_Pos) /*!< 0x00000002 */ +#define CAN_TMI0_TMFRSEL CAN_TMI0_TMFRSEL_Msk /*!< Transmit mailbox frame type select */ +#define CAN_TMI0_TMIDSEL_Pos (2U) +#define CAN_TMI0_TMIDSEL_Msk (0x1U << CAN_TMI0_TMIDSEL_Pos) /*!< 0x00000004 */ +#define CAN_TMI0_TMIDSEL CAN_TMI0_TMIDSEL_Msk /*!< Transmit mailbox identifier type select */ +#define CAN_TMI0_TMEID_Pos (3U) +#define CAN_TMI0_TMEID_Msk (0x3FFFFU << CAN_TMI0_TMEID_Pos) /*!< 0x001FFFF8 */ +#define CAN_TMI0_TMEID CAN_TMI0_TMEID_Msk /*!< Transmit mailbox extended identifier */ +#define CAN_TMI0_TMSID_Pos (21U) +#define CAN_TMI0_TMSID_Msk (0x7FFU << CAN_TMI0_TMSID_Pos) /*!< 0xFFE00000 */ +#define CAN_TMI0_TMSID CAN_TMI0_TMSID_Msk /*!< Transmit mailbox standard identifier or extended identifier high bytes */ + +/******************* Bit definition for CAN_TMC0 register *******************/ +#define CAN_TMC0_TMDTBL_Pos (0U) +#define CAN_TMC0_TMDTBL_Msk (0xFU << CAN_TMC0_TMDTBL_Pos) /*!< 0x0000000F */ +#define CAN_TMC0_TMDTBL CAN_TMC0_TMDTBL_Msk /*!< Transmit mailbox data byte length */ +#define CAN_TMC0_TMTSTEN_Pos (8U) +#define CAN_TMC0_TMTSTEN_Msk (0x1U << CAN_TMC0_TMTSTEN_Pos) /*!< 0x00000100 */ +#define CAN_TMC0_TMTSTEN CAN_TMC0_TMTSTEN_Msk /*!< Transmit mailbox time stamp transmit enable */ +#define CAN_TMC0_TMTS_Pos (16U) +#define CAN_TMC0_TMTS_Msk (0xFFFFU << CAN_TMC0_TMTS_Pos) /*!< 0xFFFF0000 */ +#define CAN_TMC0_TMTS CAN_TMC0_TMTS_Msk /*!< Transmit mailbox time stamp */ + +/****************** Bit definition for CAN_TMDTL0 register ******************/ +#define CAN_TMDTL0_TMDT0_Pos (0U) +#define CAN_TMDTL0_TMDT0_Msk (0xFFU << CAN_TMDTL0_TMDT0_Pos) /*!< 0x000000FF */ +#define CAN_TMDTL0_TMDT0 CAN_TMDTL0_TMDT0_Msk /*!< Transmit mailbox data byte 0 */ +#define CAN_TMDTL0_TMDT1_Pos (8U) +#define CAN_TMDTL0_TMDT1_Msk (0xFFU << CAN_TMDTL0_TMDT1_Pos) /*!< 0x0000FF00 */ +#define CAN_TMDTL0_TMDT1 CAN_TMDTL0_TMDT1_Msk /*!< Transmit mailbox data byte 1 */ +#define CAN_TMDTL0_TMDT2_Pos (16U) +#define CAN_TMDTL0_TMDT2_Msk (0xFFU << CAN_TMDTL0_TMDT2_Pos) /*!< 0x00FF0000 */ +#define CAN_TMDTL0_TMDT2 CAN_TMDTL0_TMDT2_Msk /*!< Transmit mailbox data byte 2 */ +#define CAN_TMDTL0_TMDT3_Pos (24U) +#define CAN_TMDTL0_TMDT3_Msk (0xFFU << CAN_TMDTL0_TMDT3_Pos) /*!< 0xFF000000 */ +#define CAN_TMDTL0_TMDT3 CAN_TMDTL0_TMDT3_Msk /*!< Transmit mailbox data byte 3 */ + +/****************** Bit definition for CAN_TMDTH0 register ******************/ +#define CAN_TMDTH0_TMDT4_Pos (0U) +#define CAN_TMDTH0_TMDT4_Msk (0xFFU << CAN_TMDTH0_TMDT4_Pos) /*!< 0x000000FF */ +#define CAN_TMDTH0_TMDT4 CAN_TMDTH0_TMDT4_Msk /*!< Transmit mailbox data byte 4 */ +#define CAN_TMDTH0_TMDT5_Pos (8U) +#define CAN_TMDTH0_TMDT5_Msk (0xFFU << CAN_TMDTH0_TMDT5_Pos) /*!< 0x0000FF00 */ +#define CAN_TMDTH0_TMDT5 CAN_TMDTH0_TMDT5_Msk /*!< Transmit mailbox data byte 5 */ +#define CAN_TMDTH0_TMDT6_Pos (16U) +#define CAN_TMDTH0_TMDT6_Msk (0xFFU << CAN_TMDTH0_TMDT6_Pos) /*!< 0x00FF0000 */ +#define CAN_TMDTH0_TMDT6 CAN_TMDTH0_TMDT6_Msk /*!< Transmit mailbox data byte 6 */ +#define CAN_TMDTH0_TMDT7_Pos (24U) +#define CAN_TMDTH0_TMDT7_Msk (0xFFU << CAN_TMDTH0_TMDT7_Pos) /*!< 0xFF000000 */ +#define CAN_TMDTH0_TMDT7 CAN_TMDTH0_TMDT7_Msk /*!< Transmit mailbox data byte 7 */ + +/******************* Bit definition for CAN_TMI1 register *******************/ +#define CAN_TMI1_TMSR_Pos (0U) +#define CAN_TMI1_TMSR_Msk (0x1U << CAN_TMI1_TMSR_Pos) /*!< 0x00000001 */ +#define CAN_TMI1_TMSR CAN_TMI1_TMSR_Msk /*!< Transmit mailbox send request */ +#define CAN_TMI1_TMFRSEL_Pos (1U) +#define CAN_TMI1_TMFRSEL_Msk (0x1U << CAN_TMI1_TMFRSEL_Pos) /*!< 0x00000002 */ +#define CAN_TMI1_TMFRSEL CAN_TMI1_TMFRSEL_Msk /*!< Transmit mailbox frame type select */ +#define CAN_TMI1_TMIDSEL_Pos (2U) +#define CAN_TMI1_TMIDSEL_Msk (0x1U << CAN_TMI1_TMIDSEL_Pos) /*!< 0x00000004 */ +#define CAN_TMI1_TMIDSEL CAN_TMI1_TMIDSEL_Msk /*!< Transmit mailbox identifier type select */ +#define CAN_TMI1_TMEID_Pos (3U) +#define CAN_TMI1_TMEID_Msk (0x3FFFFU << CAN_TMI1_TMEID_Pos) /*!< 0x001FFFF8 */ +#define CAN_TMI1_TMEID CAN_TMI1_TMEID_Msk /*!< Transmit mailbox extended identifier */ +#define CAN_TMI1_TMSID_Pos (21U) +#define CAN_TMI1_TMSID_Msk (0x7FFU << CAN_TMI1_TMSID_Pos) /*!< 0xFFE00000 */ +#define CAN_TMI1_TMSID CAN_TMI1_TMSID_Msk /*!< Transmit mailbox standard identifier or extended identifier high bytes */ + +/******************* Bit definition for CAN_TMC1 register *******************/ +#define CAN_TMC1_TMDTBL_Pos (0U) +#define CAN_TMC1_TMDTBL_Msk (0xFU << CAN_TMC1_TMDTBL_Pos) /*!< 0x0000000F */ +#define CAN_TMC1_TMDTBL CAN_TMC1_TMDTBL_Msk /*!< Transmit mailbox data byte length */ +#define CAN_TMC1_TMTSTEN_Pos (8U) +#define CAN_TMC1_TMTSTEN_Msk (0x1U << CAN_TMC1_TMTSTEN_Pos) /*!< 0x00000100 */ +#define CAN_TMC1_TMTSTEN CAN_TMC1_TMTSTEN_Msk /*!< Transmit mailbox time stamp transmit enable */ +#define CAN_TMC1_TMTS_Pos (16U) +#define CAN_TMC1_TMTS_Msk (0xFFFFU << CAN_TMC1_TMTS_Pos) /*!< 0xFFFF0000 */ +#define CAN_TMC1_TMTS CAN_TMC1_TMTS_Msk /*!< Transmit mailbox time stamp */ + +/****************** Bit definition for CAN_TMDTL1 register ******************/ +#define CAN_TMDTL1_TMDT0_Pos (0U) +#define CAN_TMDTL1_TMDT0_Msk (0xFFU << CAN_TMDTL1_TMDT0_Pos) /*!< 0x000000FF */ +#define CAN_TMDTL1_TMDT0 CAN_TMDTL1_TMDT0_Msk /*!< Transmit mailbox data byte 0 */ +#define CAN_TMDTL1_TMDT1_Pos (8U) +#define CAN_TMDTL1_TMDT1_Msk (0xFFU << CAN_TMDTL1_TMDT1_Pos) /*!< 0x0000FF00 */ +#define CAN_TMDTL1_TMDT1 CAN_TMDTL1_TMDT1_Msk /*!< Transmit mailbox data byte 1 */ +#define CAN_TMDTL1_TMDT2_Pos (16U) +#define CAN_TMDTL1_TMDT2_Msk (0xFFU << CAN_TMDTL1_TMDT2_Pos) /*!< 0x00FF0000 */ +#define CAN_TMDTL1_TMDT2 CAN_TMDTL1_TMDT2_Msk /*!< Transmit mailbox data byte 2 */ +#define CAN_TMDTL1_TMDT3_Pos (24U) +#define CAN_TMDTL1_TMDT3_Msk (0xFFU << CAN_TMDTL1_TMDT3_Pos) /*!< 0xFF000000 */ +#define CAN_TMDTL1_TMDT3 CAN_TMDTL1_TMDT3_Msk /*!< Transmit mailbox data byte 3 */ + +/****************** Bit definition for CAN_TMDTH1 register ******************/ +#define CAN_TMDTH1_TMDT4_Pos (0U) +#define CAN_TMDTH1_TMDT4_Msk (0xFFU << CAN_TMDTH1_TMDT4_Pos) /*!< 0x000000FF */ +#define CAN_TMDTH1_TMDT4 CAN_TMDTH1_TMDT4_Msk /*!< Transmit mailbox data byte 4 */ +#define CAN_TMDTH1_TMDT5_Pos (8U) +#define CAN_TMDTH1_TMDT5_Msk (0xFFU << CAN_TMDTH1_TMDT5_Pos) /*!< 0x0000FF00 */ +#define CAN_TMDTH1_TMDT5 CAN_TMDTH1_TMDT5_Msk /*!< Transmit mailbox data byte 5 */ +#define CAN_TMDTH1_TMDT6_Pos (16U) +#define CAN_TMDTH1_TMDT6_Msk (0xFFU << CAN_TMDTH1_TMDT6_Pos) /*!< 0x00FF0000 */ +#define CAN_TMDTH1_TMDT6 CAN_TMDTH1_TMDT6_Msk /*!< Transmit mailbox data byte 6 */ +#define CAN_TMDTH1_TMDT7_Pos (24U) +#define CAN_TMDTH1_TMDT7_Msk (0xFFU << CAN_TMDTH1_TMDT7_Pos) /*!< 0xFF000000 */ +#define CAN_TMDTH1_TMDT7 CAN_TMDTH1_TMDT7_Msk /*!< Transmit mailbox data byte 7 */ + +/******************* Bit definition for CAN_TMI2 register *******************/ +#define CAN_TMI2_TMSR_Pos (0U) +#define CAN_TMI2_TMSR_Msk (0x1U << CAN_TMI2_TMSR_Pos) /*!< 0x00000001 */ +#define CAN_TMI2_TMSR CAN_TMI2_TMSR_Msk /*!< Transmit mailbox send request */ +#define CAN_TMI2_TMFRSEL_Pos (1U) +#define CAN_TMI2_TMFRSEL_Msk (0x1U << CAN_TMI2_TMFRSEL_Pos) /*!< 0x00000002 */ +#define CAN_TMI2_TMFRSEL CAN_TMI2_TMFRSEL_Msk /*!< Transmit mailbox frame type select */ +#define CAN_TMI2_TMIDSEL_Pos (2U) +#define CAN_TMI2_TMIDSEL_Msk (0x1U << CAN_TMI2_TMIDSEL_Pos) /*!< 0x00000004 */ +#define CAN_TMI2_TMIDSEL CAN_TMI2_TMIDSEL_Msk /*!< Transmit mailbox identifier type select */ +#define CAN_TMI2_TMEID_Pos (3U) +#define CAN_TMI2_TMEID_Msk (0x3FFFFU << CAN_TMI2_TMEID_Pos) /*!< 0x001FFFF8 */ +#define CAN_TMI2_TMEID CAN_TMI2_TMEID_Msk /*!< Transmit mailbox extended identifier */ +#define CAN_TMI2_TMSID_Pos (21U) +#define CAN_TMI2_TMSID_Msk (0x7FFU << CAN_TMI2_TMSID_Pos) /*!< 0xFFE00000 */ +#define CAN_TMI2_TMSID CAN_TMI2_TMSID_Msk /*!< Transmit mailbox standard identifier or extended identifier high bytes */ + +/******************* Bit definition for CAN_TMC2 register *******************/ +#define CAN_TMC2_TMDTBL_Pos (0U) +#define CAN_TMC2_TMDTBL_Msk (0xFU << CAN_TMC2_TMDTBL_Pos) /*!< 0x0000000F */ +#define CAN_TMC2_TMDTBL CAN_TMC2_TMDTBL_Msk /*!< Transmit mailbox data byte length */ +#define CAN_TMC2_TMTSTEN_Pos (8U) +#define CAN_TMC2_TMTSTEN_Msk (0x1U << CAN_TMC2_TMTSTEN_Pos) /*!< 0x00000100 */ +#define CAN_TMC2_TMTSTEN CAN_TMC2_TMTSTEN_Msk /*!< Transmit mailbox time stamp transmit enable */ +#define CAN_TMC2_TMTS_Pos (16U) +#define CAN_TMC2_TMTS_Msk (0xFFFFU << CAN_TMC2_TMTS_Pos) /*!< 0xFFFF0000 */ +#define CAN_TMC2_TMTS CAN_TMC2_TMTS_Msk /*!< Transmit mailbox time stamp */ + +/****************** Bit definition for CAN_TMDTL2 register ******************/ +#define CAN_TMDTL2_TMDT0_Pos (0U) +#define CAN_TMDTL2_TMDT0_Msk (0xFFU << CAN_TMDTL2_TMDT0_Pos) /*!< 0x000000FF */ +#define CAN_TMDTL2_TMDT0 CAN_TMDTL2_TMDT0_Msk /*!< Transmit mailbox data byte 0 */ +#define CAN_TMDTL2_TMDT1_Pos (8U) +#define CAN_TMDTL2_TMDT1_Msk (0xFFU << CAN_TMDTL2_TMDT1_Pos) /*!< 0x0000FF00 */ +#define CAN_TMDTL2_TMDT1 CAN_TMDTL2_TMDT1_Msk /*!< Transmit mailbox data byte 1 */ +#define CAN_TMDTL2_TMDT2_Pos (16U) +#define CAN_TMDTL2_TMDT2_Msk (0xFFU << CAN_TMDTL2_TMDT2_Pos) /*!< 0x00FF0000 */ +#define CAN_TMDTL2_TMDT2 CAN_TMDTL2_TMDT2_Msk /*!< Transmit mailbox data byte 2 */ +#define CAN_TMDTL2_TMDT3_Pos (24U) +#define CAN_TMDTL2_TMDT3_Msk (0xFFU << CAN_TMDTL2_TMDT3_Pos) /*!< 0xFF000000 */ +#define CAN_TMDTL2_TMDT3 CAN_TMDTL2_TMDT3_Msk /*!< Transmit mailbox data byte 3 */ + +/****************** Bit definition for CAN_TMDTH2 register ******************/ +#define CAN_TMDTH2_TMDT4_Pos (0U) +#define CAN_TMDTH2_TMDT4_Msk (0xFFU << CAN_TMDTH2_TMDT4_Pos) /*!< 0x000000FF */ +#define CAN_TMDTH2_TMDT4 CAN_TMDTH2_TMDT4_Msk /*!< Transmit mailbox data byte 4 */ +#define CAN_TMDTH2_TMDT5_Pos (8U) +#define CAN_TMDTH2_TMDT5_Msk (0xFFU << CAN_TMDTH2_TMDT5_Pos) /*!< 0x0000FF00 */ +#define CAN_TMDTH2_TMDT5 CAN_TMDTH2_TMDT5_Msk /*!< Transmit mailbox data byte 5 */ +#define CAN_TMDTH2_TMDT6_Pos (16U) +#define CAN_TMDTH2_TMDT6_Msk (0xFFU << CAN_TMDTH2_TMDT6_Pos) /*!< 0x00FF0000 */ +#define CAN_TMDTH2_TMDT6 CAN_TMDTH2_TMDT6_Msk /*!< Transmit mailbox data byte 6 */ +#define CAN_TMDTH2_TMDT7_Pos (24U) +#define CAN_TMDTH2_TMDT7_Msk (0xFFU << CAN_TMDTH2_TMDT7_Pos) /*!< 0xFF000000 */ +#define CAN_TMDTH2_TMDT7 CAN_TMDTH2_TMDT7_Msk /*!< Transmit mailbox data byte 7 */ + +/******************* Bit definition for CAN_RFI0 register *******************/ +#define CAN_RFI0_RFFRI_Pos (1U) +#define CAN_RFI0_RFFRI_Msk (0x1U << CAN_RFI0_RFFRI_Pos) /*!< 0x00000002 */ +#define CAN_RFI0_RFFRI CAN_RFI0_RFFRI_Msk /*!< Receive FIFO frame type indication */ +#define CAN_RFI0_RFIDI_Pos (2U) +#define CAN_RFI0_RFIDI_Msk (0x1U << CAN_RFI0_RFIDI_Pos) /*!< 0x00000004 */ +#define CAN_RFI0_RFIDI CAN_RFI0_RFIDI_Msk /*!< Receive FIFO identifier type indication */ +#define CAN_RFI0_RFEID_Pos (3U) +#define CAN_RFI0_RFEID_Msk (0x3FFFFU << CAN_RFI0_RFEID_Pos) /*!< 0x001FFFF8 */ +#define CAN_RFI0_RFEID CAN_RFI0_RFEID_Msk /*!< Receive FIFO extended identifier */ +#define CAN_RFI0_RFSID_Pos (21U) +#define CAN_RFI0_RFSID_Msk (0x7FFU << CAN_RFI0_RFSID_Pos) /*!< 0xFFE00000 */ +#define CAN_RFI0_RFSID CAN_RFI0_RFSID_Msk /*!< Receive FIFO standard identifier or receive FIFO extended identifier */ + +/******************* Bit definition for CAN_RFC0 register *******************/ +#define CAN_RFC0_RFDTL_Pos (0U) +#define CAN_RFC0_RFDTL_Msk (0xFU << CAN_RFC0_RFDTL_Pos) /*!< 0x0000000F */ +#define CAN_RFC0_RFDTL CAN_RFC0_RFDTL_Msk /*!< Receive FIFO data length */ +#define CAN_RFC0_RFFMN_Pos (8U) +#define CAN_RFC0_RFFMN_Msk (0xFFU << CAN_RFC0_RFFMN_Pos) /*!< 0x0000FF00 */ +#define CAN_RFC0_RFFMN CAN_RFC0_RFFMN_Msk /*!< Receive FIFO filter match number */ +#define CAN_RFC0_RFTS_Pos (16U) +#define CAN_RFC0_RFTS_Msk (0xFFFFU << CAN_RFC0_RFTS_Pos) /*!< 0xFFFF0000 */ +#define CAN_RFC0_RFTS CAN_RFC0_RFTS_Msk /*!< Receive FIFO time stamp */ + +/****************** Bit definition for CAN_RFDTL0 register ******************/ +#define CAN_RFDTL0_RFDT0_Pos (0U) +#define CAN_RFDTL0_RFDT0_Msk (0xFFU << CAN_RFDTL0_RFDT0_Pos) /*!< 0x000000FF */ +#define CAN_RFDTL0_RFDT0 CAN_RFDTL0_RFDT0_Msk /*!< Receive FIFO data byte 0 */ +#define CAN_RFDTL0_RFDT1_Pos (8U) +#define CAN_RFDTL0_RFDT1_Msk (0xFFU << CAN_RFDTL0_RFDT1_Pos) /*!< 0x0000FF00 */ +#define CAN_RFDTL0_RFDT1 CAN_RFDTL0_RFDT1_Msk /*!< Receive FIFO data byte 1 */ +#define CAN_RFDTL0_RFDT2_Pos (16U) +#define CAN_RFDTL0_RFDT2_Msk (0xFFU << CAN_RFDTL0_RFDT2_Pos) /*!< 0x00FF0000 */ +#define CAN_RFDTL0_RFDT2 CAN_RFDTL0_RFDT2_Msk /*!< Receive FIFO data byte 2 */ +#define CAN_RFDTL0_RFDT3_Pos (24U) +#define CAN_RFDTL0_RFDT3_Msk (0xFFU << CAN_RFDTL0_RFDT3_Pos) /*!< 0xFF000000 */ +#define CAN_RFDTL0_RFDT3 CAN_RFDTL0_RFDT3_Msk /*!< Receive FIFO data byte 3 */ + +/****************** Bit definition for CAN_RFDTH0 register ******************/ +#define CAN_RFDTH0_RFDT4_Pos (0U) +#define CAN_RFDTH0_RFDT4_Msk (0xFFU << CAN_RFDTH0_RFDT4_Pos) /*!< 0x000000FF */ +#define CAN_RFDTH0_RFDT4 CAN_RFDTH0_RFDT4_Msk /*!< Receive FIFO data byte 4 */ +#define CAN_RFDTH0_RFDT5_Pos (8U) +#define CAN_RFDTH0_RFDT5_Msk (0xFFU << CAN_RFDTH0_RFDT5_Pos) /*!< 0x0000FF00 */ +#define CAN_RFDTH0_RFDT5 CAN_RFDTH0_RFDT5_Msk /*!< Receive FIFO data byte 5 */ +#define CAN_RFDTH0_RFDT6_Pos (16U) +#define CAN_RFDTH0_RFDT6_Msk (0xFFU << CAN_RFDTH0_RFDT6_Pos) /*!< 0x00FF0000 */ +#define CAN_RFDTH0_RFDT6 CAN_RFDTH0_RFDT6_Msk /*!< Receive FIFO data byte 6 */ +#define CAN_RFDTH0_RFDT7_Pos (24U) +#define CAN_RFDTH0_RFDT7_Msk (0xFFU << CAN_RFDTH0_RFDT7_Pos) /*!< 0xFF000000 */ +#define CAN_RFDTH0_RFDT7 CAN_RFDTH0_RFDT7_Msk /*!< Receive FIFO data byte 7 */ + +/******************* Bit definition for CAN_RFI1 register *******************/ +#define CAN_RFI1_RFFRI_Pos (1U) +#define CAN_RFI1_RFFRI_Msk (0x1U << CAN_RFI1_RFFRI_Pos) /*!< 0x00000002 */ +#define CAN_RFI1_RFFRI CAN_RFI1_RFFRI_Msk /*!< Receive FIFO frame type indication */ +#define CAN_RFI1_RFIDI_Pos (2U) +#define CAN_RFI1_RFIDI_Msk (0x1U << CAN_RFI1_RFIDI_Pos) /*!< 0x00000004 */ +#define CAN_RFI1_RFIDI CAN_RFI1_RFIDI_Msk /*!< Receive FIFO identifier type indication */ +#define CAN_RFI1_RFEID_Pos (3U) +#define CAN_RFI1_RFEID_Msk (0x3FFFFU << CAN_RFI1_RFEID_Pos) /*!< 0x001FFFF8 */ +#define CAN_RFI1_RFEID CAN_RFI1_RFEID_Msk /*!< Receive FIFO extended identifier */ +#define CAN_RFI1_RFSID_Pos (21U) +#define CAN_RFI1_RFSID_Msk (0x7FFU << CAN_RFI1_RFSID_Pos) /*!< 0xFFE00000 */ +#define CAN_RFI1_RFSID CAN_RFI1_RFSID_Msk /*!< Receive FIFO standard identifier or receive FIFO extended identifier */ + +/******************* Bit definition for CAN_RFC1 register *******************/ +#define CAN_RFC1_RFDTL_Pos (0U) +#define CAN_RFC1_RFDTL_Msk (0xFU << CAN_RFC1_RFDTL_Pos) /*!< 0x0000000F */ +#define CAN_RFC1_RFDTL CAN_RFC1_RFDTL_Msk /*!< Receive FIFO data length */ +#define CAN_RFC1_RFFMN_Pos (8U) +#define CAN_RFC1_RFFMN_Msk (0xFFU << CAN_RFC1_RFFMN_Pos) /*!< 0x0000FF00 */ +#define CAN_RFC1_RFFMN CAN_RFC1_RFFMN_Msk /*!< Receive FIFO filter match number */ +#define CAN_RFC1_RFTS_Pos (16U) +#define CAN_RFC1_RFTS_Msk (0xFFFFU << CAN_RFC1_RFTS_Pos) /*!< 0xFFFF0000 */ +#define CAN_RFC1_RFTS CAN_RFC1_RFTS_Msk /*!< Receive FIFO time stamp */ + +/****************** Bit definition for CAN_RFDTL1 register ******************/ +#define CAN_RFDTL1_RFDT0_Pos (0U) +#define CAN_RFDTL1_RFDT0_Msk (0xFFU << CAN_RFDTL1_RFDT0_Pos) /*!< 0x000000FF */ +#define CAN_RFDTL1_RFDT0 CAN_RFDTL1_RFDT0_Msk /*!< Receive FIFO data byte 0 */ +#define CAN_RFDTL1_RFDT1_Pos (8U) +#define CAN_RFDTL1_RFDT1_Msk (0xFFU << CAN_RFDTL1_RFDT1_Pos) /*!< 0x0000FF00 */ +#define CAN_RFDTL1_RFDT1 CAN_RFDTL1_RFDT1_Msk /*!< Receive FIFO data byte 1 */ +#define CAN_RFDTL1_RFDT2_Pos (16U) +#define CAN_RFDTL1_RFDT2_Msk (0xFFU << CAN_RFDTL1_RFDT2_Pos) /*!< 0x00FF0000 */ +#define CAN_RFDTL1_RFDT2 CAN_RFDTL1_RFDT2_Msk /*!< Receive FIFO data byte 2 */ +#define CAN_RFDTL1_RFDT3_Pos (24U) +#define CAN_RFDTL1_RFDT3_Msk (0xFFU << CAN_RFDTL1_RFDT3_Pos) /*!< 0xFF000000 */ +#define CAN_RFDTL1_RFDT3 CAN_RFDTL1_RFDT3_Msk /*!< Receive FIFO data byte 3 */ + +/****************** Bit definition for CAN_RFDTH1 register ******************/ +#define CAN_RFDTH1_RFDT4_Pos (0U) +#define CAN_RFDTH1_RFDT4_Msk (0xFFU << CAN_RFDTH1_RFDT4_Pos) /*!< 0x000000FF */ +#define CAN_RFDTH1_RFDT4 CAN_RFDTH1_RFDT4_Msk /*!< Receive FIFO data byte 4 */ +#define CAN_RFDTH1_RFDT5_Pos (8U) +#define CAN_RFDTH1_RFDT5_Msk (0xFFU << CAN_RFDTH1_RFDT5_Pos) /*!< 0x0000FF00 */ +#define CAN_RFDTH1_RFDT5 CAN_RFDTH1_RFDT5_Msk /*!< Receive FIFO data byte 5 */ +#define CAN_RFDTH1_RFDT6_Pos (16U) +#define CAN_RFDTH1_RFDT6_Msk (0xFFU << CAN_RFDTH1_RFDT6_Pos) /*!< 0x00FF0000 */ +#define CAN_RFDTH1_RFDT6 CAN_RFDTH1_RFDT6_Msk /*!< Receive FIFO data byte 6 */ +#define CAN_RFDTH1_RFDT7_Pos (24U) +#define CAN_RFDTH1_RFDT7_Msk (0xFFU << CAN_RFDTH1_RFDT7_Pos) /*!< 0xFF000000 */ +#define CAN_RFDTH1_RFDT7 CAN_RFDTH1_RFDT7_Msk /*!< Receive FIFO data byte 7 */ + +/*!< CAN filter registers */ +/****************** Bit definition for CAN_FCTRL register *******************/ +#define CAN_FCTRL_FCS_Pos (0U) +#define CAN_FCTRL_FCS_Msk (0x1U << CAN_FCTRL_FCS_Pos) /*!< 0x00000001 */ +#define CAN_FCTRL_FCS CAN_FCTRL_FCS_Msk /*!< Filter configuration switch */ + +/****************** Bit definition for CAN_FMCFG register *******************/ +#define CAN_FMCFG_FMSEL_Pos (0U) +#define CAN_FMCFG_FMSEL_Msk (0xFFFFFFFU << CAN_FMCFG_FMSEL_Pos) /*!< 0x0FFFFFFF */ +#define CAN_FMCFG_FMSEL CAN_FMCFG_FMSEL_Msk /*!< Filter mode select */ +#define CAN_FMCFG_FMSEL0_Pos (0U) +#define CAN_FMCFG_FMSEL0_Msk (0x1U << CAN_FMCFG_FMSEL0_Pos) /*!< 0x00000001 */ +#define CAN_FMCFG_FMSEL0 CAN_FMCFG_FMSEL0_Msk /*!< Filter mode select for filter 0 */ +#define CAN_FMCFG_FMSEL1_Pos (1U) +#define CAN_FMCFG_FMSEL1_Msk (0x1U << CAN_FMCFG_FMSEL1_Pos) /*!< 0x00000002 */ +#define CAN_FMCFG_FMSEL1 CAN_FMCFG_FMSEL1_Msk /*!< Filter mode select for filter 1 */ +#define CAN_FMCFG_FMSEL2_Pos (2U) +#define CAN_FMCFG_FMSEL2_Msk (0x1U << CAN_FMCFG_FMSEL2_Pos) /*!< 0x00000004 */ +#define CAN_FMCFG_FMSEL2 CAN_FMCFG_FMSEL2_Msk /*!< Filter mode select for filter 2 */ +#define CAN_FMCFG_FMSEL3_Pos (3U) +#define CAN_FMCFG_FMSEL3_Msk (0x1U << CAN_FMCFG_FMSEL3_Pos) /*!< 0x00000008 */ +#define CAN_FMCFG_FMSEL3 CAN_FMCFG_FMSEL3_Msk /*!< Filter mode select for filter 3 */ +#define CAN_FMCFG_FMSEL4_Pos (4U) +#define CAN_FMCFG_FMSEL4_Msk (0x1U << CAN_FMCFG_FMSEL4_Pos) /*!< 0x00000010 */ +#define CAN_FMCFG_FMSEL4 CAN_FMCFG_FMSEL4_Msk /*!< Filter mode select for filter 4 */ +#define CAN_FMCFG_FMSEL5_Pos (5U) +#define CAN_FMCFG_FMSEL5_Msk (0x1U << CAN_FMCFG_FMSEL5_Pos) /*!< 0x00000020 */ +#define CAN_FMCFG_FMSEL5 CAN_FMCFG_FMSEL5_Msk /*!< Filter mode select for filter 5 */ +#define CAN_FMCFG_FMSEL6_Pos (6U) +#define CAN_FMCFG_FMSEL6_Msk (0x1U << CAN_FMCFG_FMSEL6_Pos) /*!< 0x00000040 */ +#define CAN_FMCFG_FMSEL6 CAN_FMCFG_FMSEL6_Msk /*!< Filter mode select for filter 6 */ +#define CAN_FMCFG_FMSEL7_Pos (7U) +#define CAN_FMCFG_FMSEL7_Msk (0x1U << CAN_FMCFG_FMSEL7_Pos) /*!< 0x00000080 */ +#define CAN_FMCFG_FMSEL7 CAN_FMCFG_FMSEL7_Msk /*!< Filter mode select for filter 7 */ +#define CAN_FMCFG_FMSEL8_Pos (8U) +#define CAN_FMCFG_FMSEL8_Msk (0x1U << CAN_FMCFG_FMSEL8_Pos) /*!< 0x00000100 */ +#define CAN_FMCFG_FMSEL8 CAN_FMCFG_FMSEL8_Msk /*!< Filter mode select for filter 8 */ +#define CAN_FMCFG_FMSEL9_Pos (9U) +#define CAN_FMCFG_FMSEL9_Msk (0x1U << CAN_FMCFG_FMSEL9_Pos) /*!< 0x00000200 */ +#define CAN_FMCFG_FMSEL9 CAN_FMCFG_FMSEL9_Msk /*!< Filter mode select for filter 9 */ +#define CAN_FMCFG_FMSEL10_Pos (10U) +#define CAN_FMCFG_FMSEL10_Msk (0x1U << CAN_FMCFG_FMSEL10_Pos) /*!< 0x00000400 */ +#define CAN_FMCFG_FMSEL10 CAN_FMCFG_FMSEL10_Msk /*!< Filter mode select for filter 10 */ +#define CAN_FMCFG_FMSEL11_Pos (11U) +#define CAN_FMCFG_FMSEL11_Msk (0x1U << CAN_FMCFG_FMSEL11_Pos) /*!< 0x00000800 */ +#define CAN_FMCFG_FMSEL11 CAN_FMCFG_FMSEL11_Msk /*!< Filter mode select for filter 11 */ +#define CAN_FMCFG_FMSEL12_Pos (12U) +#define CAN_FMCFG_FMSEL12_Msk (0x1U << CAN_FMCFG_FMSEL12_Pos) /*!< 0x00001000 */ +#define CAN_FMCFG_FMSEL12 CAN_FMCFG_FMSEL12_Msk /*!< Filter mode select for filter 12 */ +#define CAN_FMCFG_FMSEL13_Pos (13U) +#define CAN_FMCFG_FMSEL13_Msk (0x1U << CAN_FMCFG_FMSEL13_Pos) /*!< 0x00002000 */ +#define CAN_FMCFG_FMSEL13 CAN_FMCFG_FMSEL13_Msk /*!< Filter mode select for filter 13 */ +#define CAN_FMCFG_FMSEL14_Pos (14U) +#define CAN_FMCFG_FMSEL14_Msk (0x1U << CAN_FMCFG_FMSEL14_Pos) /*!< 0x00004000 */ +#define CAN_FMCFG_FMSEL14 CAN_FMCFG_FMSEL14_Msk /*!< Filter mode select for filter 14 */ +#define CAN_FMCFG_FMSEL15_Pos (15U) +#define CAN_FMCFG_FMSEL15_Msk (0x1U << CAN_FMCFG_FMSEL15_Pos) /*!< 0x00008000 */ +#define CAN_FMCFG_FMSEL15 CAN_FMCFG_FMSEL15_Msk /*!< Filter mode select for filter 15 */ +#define CAN_FMCFG_FMSEL16_Pos (16U) +#define CAN_FMCFG_FMSEL16_Msk (0x1U << CAN_FMCFG_FMSEL16_Pos) /*!< 0x00010000 */ +#define CAN_FMCFG_FMSEL16 CAN_FMCFG_FMSEL16_Msk /*!< Filter mode select for filter 16 */ +#define CAN_FMCFG_FMSEL17_Pos (17U) +#define CAN_FMCFG_FMSEL17_Msk (0x1U << CAN_FMCFG_FMSEL17_Pos) /*!< 0x00020000 */ +#define CAN_FMCFG_FMSEL17 CAN_FMCFG_FMSEL17_Msk /*!< Filter mode select for filter 17 */ +#define CAN_FMCFG_FMSEL18_Pos (18U) +#define CAN_FMCFG_FMSEL18_Msk (0x1U << CAN_FMCFG_FMSEL18_Pos) /*!< 0x00040000 */ +#define CAN_FMCFG_FMSEL18 CAN_FMCFG_FMSEL18_Msk /*!< Filter mode select for filter 18 */ +#define CAN_FMCFG_FMSEL19_Pos (19U) +#define CAN_FMCFG_FMSEL19_Msk (0x1U << CAN_FMCFG_FMSEL19_Pos) /*!< 0x00080000 */ +#define CAN_FMCFG_FMSEL19 CAN_FMCFG_FMSEL19_Msk /*!< Filter mode select for filter 19 */ +#define CAN_FMCFG_FMSEL20_Pos (20U) +#define CAN_FMCFG_FMSEL20_Msk (0x1U << CAN_FMCFG_FMSEL20_Pos) /*!< 0x00100000 */ +#define CAN_FMCFG_FMSEL20 CAN_FMCFG_FMSEL20_Msk /*!< Filter mode select for filter 20 */ +#define CAN_FMCFG_FMSEL21_Pos (21U) +#define CAN_FMCFG_FMSEL21_Msk (0x1U << CAN_FMCFG_FMSEL21_Pos) /*!< 0x00200000 */ +#define CAN_FMCFG_FMSEL21 CAN_FMCFG_FMSEL21_Msk /*!< Filter mode select for filter 21 */ +#define CAN_FMCFG_FMSEL22_Pos (22U) +#define CAN_FMCFG_FMSEL22_Msk (0x1U << CAN_FMCFG_FMSEL22_Pos) /*!< 0x00400000 */ +#define CAN_FMCFG_FMSEL22 CAN_FMCFG_FMSEL22_Msk /*!< Filter mode select for filter 22 */ +#define CAN_FMCFG_FMSEL23_Pos (23U) +#define CAN_FMCFG_FMSEL23_Msk (0x1U << CAN_FMCFG_FMSEL23_Pos) /*!< 0x00800000 */ +#define CAN_FMCFG_FMSEL23 CAN_FMCFG_FMSEL23_Msk /*!< Filter mode select for filter 23 */ +#define CAN_FMCFG_FMSEL24_Pos (24U) +#define CAN_FMCFG_FMSEL24_Msk (0x1U << CAN_FMCFG_FMSEL24_Pos) /*!< 0x01000000 */ +#define CAN_FMCFG_FMSEL24 CAN_FMCFG_FMSEL24_Msk /*!< Filter mode select for filter 24 */ +#define CAN_FMCFG_FMSEL25_Pos (25U) +#define CAN_FMCFG_FMSEL25_Msk (0x1U << CAN_FMCFG_FMSEL25_Pos) /*!< 0x02000000 */ +#define CAN_FMCFG_FMSEL25 CAN_FMCFG_FMSEL25_Msk /*!< Filter mode select for filter 25 */ +#define CAN_FMCFG_FMSEL26_Pos (26U) +#define CAN_FMCFG_FMSEL26_Msk (0x1U << CAN_FMCFG_FMSEL26_Pos) /*!< 0x04000000 */ +#define CAN_FMCFG_FMSEL26 CAN_FMCFG_FMSEL26_Msk /*!< Filter mode select for filter 26 */ +#define CAN_FMCFG_FMSEL27_Pos (27U) +#define CAN_FMCFG_FMSEL27_Msk (0x1U << CAN_FMCFG_FMSEL27_Pos) /*!< 0x08000000 */ +#define CAN_FMCFG_FMSEL27 CAN_FMCFG_FMSEL27_Msk /*!< Filter mode select for filter 27 */ + +/****************** Bit definition for CAN_FBWCFG register ******************/ +#define CAN_FBWCFG_FBWSEL_Pos (0U) +#define CAN_FBWCFG_FBWSEL_Msk (0xFFFFFFFU << CAN_FBWCFG_FBWSEL_Pos) /*!< 0x0FFFFFFF */ +#define CAN_FBWCFG_FBWSEL CAN_FBWCFG_FBWSEL_Msk /*!< Filter bit width select */ +#define CAN_FBWCFG_FBWSEL0_Pos (0U) +#define CAN_FBWCFG_FBWSEL0_Msk (0x1U << CAN_FBWCFG_FBWSEL0_Pos) /*!< 0x00000001 */ +#define CAN_FBWCFG_FBWSEL0 CAN_FBWCFG_FBWSEL0_Msk /*!< Filter bit width select for filter 0 */ +#define CAN_FBWCFG_FBWSEL1_Pos (1U) +#define CAN_FBWCFG_FBWSEL1_Msk (0x1U << CAN_FBWCFG_FBWSEL1_Pos) /*!< 0x00000002 */ +#define CAN_FBWCFG_FBWSEL1 CAN_FBWCFG_FBWSEL1_Msk /*!< Filter bit width select for filter 1 */ +#define CAN_FBWCFG_FBWSEL2_Pos (2U) +#define CAN_FBWCFG_FBWSEL2_Msk (0x1U << CAN_FBWCFG_FBWSEL2_Pos) /*!< 0x00000004 */ +#define CAN_FBWCFG_FBWSEL2 CAN_FBWCFG_FBWSEL2_Msk /*!< Filter bit width select for filter 2 */ +#define CAN_FBWCFG_FBWSEL3_Pos (3U) +#define CAN_FBWCFG_FBWSEL3_Msk (0x1U << CAN_FBWCFG_FBWSEL3_Pos) /*!< 0x00000008 */ +#define CAN_FBWCFG_FBWSEL3 CAN_FBWCFG_FBWSEL3_Msk /*!< Filter bit width select for filter 3 */ +#define CAN_FBWCFG_FBWSEL4_Pos (4U) +#define CAN_FBWCFG_FBWSEL4_Msk (0x1U << CAN_FBWCFG_FBWSEL4_Pos) /*!< 0x00000010 */ +#define CAN_FBWCFG_FBWSEL4 CAN_FBWCFG_FBWSEL4_Msk /*!< Filter bit width select for filter 4 */ +#define CAN_FBWCFG_FBWSEL5_Pos (5U) +#define CAN_FBWCFG_FBWSEL5_Msk (0x1U << CAN_FBWCFG_FBWSEL5_Pos) /*!< 0x00000020 */ +#define CAN_FBWCFG_FBWSEL5 CAN_FBWCFG_FBWSEL5_Msk /*!< Filter bit width select for filter 5 */ +#define CAN_FBWCFG_FBWSEL6_Pos (6U) +#define CAN_FBWCFG_FBWSEL6_Msk (0x1U << CAN_FBWCFG_FBWSEL6_Pos) /*!< 0x00000040 */ +#define CAN_FBWCFG_FBWSEL6 CAN_FBWCFG_FBWSEL6_Msk /*!< Filter bit width select for filter 6 */ +#define CAN_FBWCFG_FBWSEL7_Pos (7U) +#define CAN_FBWCFG_FBWSEL7_Msk (0x1U << CAN_FBWCFG_FBWSEL7_Pos) /*!< 0x00000080 */ +#define CAN_FBWCFG_FBWSEL7 CAN_FBWCFG_FBWSEL7_Msk /*!< Filter bit width select for filter 7 */ +#define CAN_FBWCFG_FBWSEL8_Pos (8U) +#define CAN_FBWCFG_FBWSEL8_Msk (0x1U << CAN_FBWCFG_FBWSEL8_Pos) /*!< 0x00000100 */ +#define CAN_FBWCFG_FBWSEL8 CAN_FBWCFG_FBWSEL8_Msk /*!< Filter bit width select for filter 8 */ +#define CAN_FBWCFG_FBWSEL9_Pos (9U) +#define CAN_FBWCFG_FBWSEL9_Msk (0x1U << CAN_FBWCFG_FBWSEL9_Pos) /*!< 0x00000200 */ +#define CAN_FBWCFG_FBWSEL9 CAN_FBWCFG_FBWSEL9_Msk /*!< Filter bit width select for filter 9 */ +#define CAN_FBWCFG_FBWSEL10_Pos (10U) +#define CAN_FBWCFG_FBWSEL10_Msk (0x1U << CAN_FBWCFG_FBWSEL10_Pos) /*!< 0x00000400 */ +#define CAN_FBWCFG_FBWSEL10 CAN_FBWCFG_FBWSEL10_Msk /*!< Filter bit width select for filter 10 */ +#define CAN_FBWCFG_FBWSEL11_Pos (11U) +#define CAN_FBWCFG_FBWSEL11_Msk (0x1U << CAN_FBWCFG_FBWSEL11_Pos) /*!< 0x00000800 */ +#define CAN_FBWCFG_FBWSEL11 CAN_FBWCFG_FBWSEL11_Msk /*!< Filter bit width select for filter 11 */ +#define CAN_FBWCFG_FBWSEL12_Pos (12U) +#define CAN_FBWCFG_FBWSEL12_Msk (0x1U << CAN_FBWCFG_FBWSEL12_Pos) /*!< 0x00001000 */ +#define CAN_FBWCFG_FBWSEL12 CAN_FBWCFG_FBWSEL12_Msk /*!< Filter bit width select for filter 12 */ +#define CAN_FBWCFG_FBWSEL13_Pos (13U) +#define CAN_FBWCFG_FBWSEL13_Msk (0x1U << CAN_FBWCFG_FBWSEL13_Pos) /*!< 0x00002000 */ +#define CAN_FBWCFG_FBWSEL13 CAN_FBWCFG_FBWSEL13_Msk /*!< Filter bit width select for filter 13 */ +#define CAN_FBWCFG_FBWSEL14_Pos (14U) +#define CAN_FBWCFG_FBWSEL14_Msk (0x1U << CAN_FBWCFG_FBWSEL14_Pos) /*!< 0x00004000 */ +#define CAN_FBWCFG_FBWSEL14 CAN_FBWCFG_FBWSEL14_Msk /*!< Filter bit width select for filter 14 */ +#define CAN_FBWCFG_FBWSEL15_Pos (15U) +#define CAN_FBWCFG_FBWSEL15_Msk (0x1U << CAN_FBWCFG_FBWSEL15_Pos) /*!< 0x00008000 */ +#define CAN_FBWCFG_FBWSEL15 CAN_FBWCFG_FBWSEL15_Msk /*!< Filter bit width select for filter 15 */ +#define CAN_FBWCFG_FBWSEL16_Pos (16U) +#define CAN_FBWCFG_FBWSEL16_Msk (0x1U << CAN_FBWCFG_FBWSEL16_Pos) /*!< 0x00010000 */ +#define CAN_FBWCFG_FBWSEL16 CAN_FBWCFG_FBWSEL16_Msk /*!< Filter bit width select for filter 16 */ +#define CAN_FBWCFG_FBWSEL17_Pos (17U) +#define CAN_FBWCFG_FBWSEL17_Msk (0x1U << CAN_FBWCFG_FBWSEL17_Pos) /*!< 0x00020000 */ +#define CAN_FBWCFG_FBWSEL17 CAN_FBWCFG_FBWSEL17_Msk /*!< Filter bit width select for filter 17 */ +#define CAN_FBWCFG_FBWSEL18_Pos (18U) +#define CAN_FBWCFG_FBWSEL18_Msk (0x1U << CAN_FBWCFG_FBWSEL18_Pos) /*!< 0x00040000 */ +#define CAN_FBWCFG_FBWSEL18 CAN_FBWCFG_FBWSEL18_Msk /*!< Filter bit width select for filter 18 */ +#define CAN_FBWCFG_FBWSEL19_Pos (19U) +#define CAN_FBWCFG_FBWSEL19_Msk (0x1U << CAN_FBWCFG_FBWSEL19_Pos) /*!< 0x00080000 */ +#define CAN_FBWCFG_FBWSEL19 CAN_FBWCFG_FBWSEL19_Msk /*!< Filter bit width select for filter 19 */ +#define CAN_FBWCFG_FBWSEL20_Pos (20U) +#define CAN_FBWCFG_FBWSEL20_Msk (0x1U << CAN_FBWCFG_FBWSEL20_Pos) /*!< 0x00100000 */ +#define CAN_FBWCFG_FBWSEL20 CAN_FBWCFG_FBWSEL20_Msk /*!< Filter bit width select for filter 20 */ +#define CAN_FBWCFG_FBWSEL21_Pos (21U) +#define CAN_FBWCFG_FBWSEL21_Msk (0x1U << CAN_FBWCFG_FBWSEL21_Pos) /*!< 0x00200000 */ +#define CAN_FBWCFG_FBWSEL21 CAN_FBWCFG_FBWSEL21_Msk /*!< Filter bit width select for filter 21 */ +#define CAN_FBWCFG_FBWSEL22_Pos (22U) +#define CAN_FBWCFG_FBWSEL22_Msk (0x1U << CAN_FBWCFG_FBWSEL22_Pos) /*!< 0x00400000 */ +#define CAN_FBWCFG_FBWSEL22 CAN_FBWCFG_FBWSEL22_Msk /*!< Filter bit width select for filter 22 */ +#define CAN_FBWCFG_FBWSEL23_Pos (23U) +#define CAN_FBWCFG_FBWSEL23_Msk (0x1U << CAN_FBWCFG_FBWSEL23_Pos) /*!< 0x00800000 */ +#define CAN_FBWCFG_FBWSEL23 CAN_FBWCFG_FBWSEL23_Msk /*!< Filter bit width select for filter 23 */ +#define CAN_FBWCFG_FBWSEL24_Pos (24U) +#define CAN_FBWCFG_FBWSEL24_Msk (0x1U << CAN_FBWCFG_FBWSEL24_Pos) /*!< 0x01000000 */ +#define CAN_FBWCFG_FBWSEL24 CAN_FBWCFG_FBWSEL24_Msk /*!< Filter bit width select for filter 24 */ +#define CAN_FBWCFG_FBWSEL25_Pos (25U) +#define CAN_FBWCFG_FBWSEL25_Msk (0x1U << CAN_FBWCFG_FBWSEL25_Pos) /*!< 0x02000000 */ +#define CAN_FBWCFG_FBWSEL25 CAN_FBWCFG_FBWSEL25_Msk /*!< Filter bit width select for filter 25 */ +#define CAN_FBWCFG_FBWSEL26_Pos (26U) +#define CAN_FBWCFG_FBWSEL26_Msk (0x1U << CAN_FBWCFG_FBWSEL26_Pos) /*!< 0x04000000 */ +#define CAN_FBWCFG_FBWSEL26 CAN_FBWCFG_FBWSEL26_Msk /*!< Filter bit width select for filter 26 */ +#define CAN_FBWCFG_FBWSEL27_Pos (27U) +#define CAN_FBWCFG_FBWSEL27_Msk (0x1U << CAN_FBWCFG_FBWSEL27_Pos) /*!< 0x08000000 */ +#define CAN_FBWCFG_FBWSEL27 CAN_FBWCFG_FBWSEL27_Msk /*!< Filter bit width select for filter 27 */ + +/******************* Bit definition for CAN_FRF register ********************/ +#define CAN_FRF_FRFSEL_Pos (0U) +#define CAN_FRF_FRFSEL_Msk (0xFFFFFFFU << CAN_FRF_FRFSEL_Pos) /*!< 0x0FFFFFFF */ +#define CAN_FRF_FRFSEL CAN_FRF_FRFSEL_Msk /*!< Filter relation FIFO select */ +#define CAN_FRF_FRFSEL0_Pos (0U) +#define CAN_FRF_FRFSEL0_Msk (0x1U << CAN_FRF_FRFSEL0_Pos) /*!< 0x00000001 */ +#define CAN_FRF_FRFSEL0 CAN_FRF_FRFSEL0_Msk /*!< Filter relation FIFO select for filter 0 */ +#define CAN_FRF_FRFSEL1_Pos (1U) +#define CAN_FRF_FRFSEL1_Msk (0x1U << CAN_FRF_FRFSEL1_Pos) /*!< 0x00000002 */ +#define CAN_FRF_FRFSEL1 CAN_FRF_FRFSEL1_Msk /*!< Filter relation FIFO select for filter 1 */ +#define CAN_FRF_FRFSEL2_Pos (2U) +#define CAN_FRF_FRFSEL2_Msk (0x1U << CAN_FRF_FRFSEL2_Pos) /*!< 0x00000004 */ +#define CAN_FRF_FRFSEL2 CAN_FRF_FRFSEL2_Msk /*!< Filter relation FIFO select for filter 2 */ +#define CAN_FRF_FRFSEL3_Pos (3U) +#define CAN_FRF_FRFSEL3_Msk (0x1U << CAN_FRF_FRFSEL3_Pos) /*!< 0x00000008 */ +#define CAN_FRF_FRFSEL3 CAN_FRF_FRFSEL3_Msk /*!< Filter relation FIFO select for filter 3 */ +#define CAN_FRF_FRFSEL4_Pos (4U) +#define CAN_FRF_FRFSEL4_Msk (0x1U << CAN_FRF_FRFSEL4_Pos) /*!< 0x00000010 */ +#define CAN_FRF_FRFSEL4 CAN_FRF_FRFSEL4_Msk /*!< Filter relation FIFO select for filter 4 */ +#define CAN_FRF_FRFSEL5_Pos (5U) +#define CAN_FRF_FRFSEL5_Msk (0x1U << CAN_FRF_FRFSEL5_Pos) /*!< 0x00000020 */ +#define CAN_FRF_FRFSEL5 CAN_FRF_FRFSEL5_Msk /*!< Filter relation FIFO select for filter 5 */ +#define CAN_FRF_FRFSEL6_Pos (6U) +#define CAN_FRF_FRFSEL6_Msk (0x1U << CAN_FRF_FRFSEL6_Pos) /*!< 0x00000040 */ +#define CAN_FRF_FRFSEL6 CAN_FRF_FRFSEL6_Msk /*!< Filter relation FIFO select for filter 6 */ +#define CAN_FRF_FRFSEL7_Pos (7U) +#define CAN_FRF_FRFSEL7_Msk (0x1U << CAN_FRF_FRFSEL7_Pos) /*!< 0x00000080 */ +#define CAN_FRF_FRFSEL7 CAN_FRF_FRFSEL7_Msk /*!< Filter relation FIFO select for filter 7 */ +#define CAN_FRF_FRFSEL8_Pos (8U) +#define CAN_FRF_FRFSEL8_Msk (0x1U << CAN_FRF_FRFSEL8_Pos) /*!< 0x00000100 */ +#define CAN_FRF_FRFSEL8 CAN_FRF_FRFSEL8_Msk /*!< Filter relation FIFO select for filter 8 */ +#define CAN_FRF_FRFSEL9_Pos (9U) +#define CAN_FRF_FRFSEL9_Msk (0x1U << CAN_FRF_FRFSEL9_Pos) /*!< 0x00000200 */ +#define CAN_FRF_FRFSEL9 CAN_FRF_FRFSEL9_Msk /*!< Filter relation FIFO select for filter 9 */ +#define CAN_FRF_FRFSEL10_Pos (10U) +#define CAN_FRF_FRFSEL10_Msk (0x1U << CAN_FRF_FRFSEL10_Pos) /*!< 0x00000400 */ +#define CAN_FRF_FRFSEL10 CAN_FRF_FRFSEL10_Msk /*!< Filter relation FIFO select for filter 10 */ +#define CAN_FRF_FRFSEL11_Pos (11U) +#define CAN_FRF_FRFSEL11_Msk (0x1U << CAN_FRF_FRFSEL11_Pos) /*!< 0x00000800 */ +#define CAN_FRF_FRFSEL11 CAN_FRF_FRFSEL11_Msk /*!< Filter relation FIFO select for filter 11 */ +#define CAN_FRF_FRFSEL12_Pos (12U) +#define CAN_FRF_FRFSEL12_Msk (0x1U << CAN_FRF_FRFSEL12_Pos) /*!< 0x00001000 */ +#define CAN_FRF_FRFSEL12 CAN_FRF_FRFSEL12_Msk /*!< Filter relation FIFO select for filter 12 */ +#define CAN_FRF_FRFSEL13_Pos (13U) +#define CAN_FRF_FRFSEL13_Msk (0x1U << CAN_FRF_FRFSEL13_Pos) /*!< 0x00002000 */ +#define CAN_FRF_FRFSEL13 CAN_FRF_FRFSEL13_Msk /*!< Filter relation FIFO select for filter 13 */ +#define CAN_FRF_FRFSEL14_Pos (14U) +#define CAN_FRF_FRFSEL14_Msk (0x1U << CAN_FRF_FRFSEL14_Pos) /*!< 0x00004000 */ +#define CAN_FRF_FRFSEL14 CAN_FRF_FRFSEL14_Msk /*!< Filter relation FIFO select for filter 14 */ +#define CAN_FRF_FRFSEL15_Pos (15U) +#define CAN_FRF_FRFSEL15_Msk (0x1U << CAN_FRF_FRFSEL15_Pos) /*!< 0x00008000 */ +#define CAN_FRF_FRFSEL15 CAN_FRF_FRFSEL15_Msk /*!< Filter relation FIFO select for filter 15 */ +#define CAN_FRF_FRFSEL16_Pos (16U) +#define CAN_FRF_FRFSEL16_Msk (0x1U << CAN_FRF_FRFSEL16_Pos) /*!< 0x00010000 */ +#define CAN_FRF_FRFSEL16 CAN_FRF_FRFSEL16_Msk /*!< Filter relation FIFO select for filter 16 */ +#define CAN_FRF_FRFSEL17_Pos (17U) +#define CAN_FRF_FRFSEL17_Msk (0x1U << CAN_FRF_FRFSEL17_Pos) /*!< 0x00020000 */ +#define CAN_FRF_FRFSEL17 CAN_FRF_FRFSEL17_Msk /*!< Filter relation FIFO select for filter 17 */ +#define CAN_FRF_FRFSEL18_Pos (18U) +#define CAN_FRF_FRFSEL18_Msk (0x1U << CAN_FRF_FRFSEL18_Pos) /*!< 0x00040000 */ +#define CAN_FRF_FRFSEL18 CAN_FRF_FRFSEL18_Msk /*!< Filter relation FIFO select for filter 18 */ +#define CAN_FRF_FRFSEL19_Pos (19U) +#define CAN_FRF_FRFSEL19_Msk (0x1U << CAN_FRF_FRFSEL19_Pos) /*!< 0x00080000 */ +#define CAN_FRF_FRFSEL19 CAN_FRF_FRFSEL19_Msk /*!< Filter relation FIFO select for filter 19 */ +#define CAN_FRF_FRFSEL20_Pos (20U) +#define CAN_FRF_FRFSEL20_Msk (0x1U << CAN_FRF_FRFSEL20_Pos) /*!< 0x00100000 */ +#define CAN_FRF_FRFSEL20 CAN_FRF_FRFSEL20_Msk /*!< Filter relation FIFO select for filter 20 */ +#define CAN_FRF_FRFSEL21_Pos (21U) +#define CAN_FRF_FRFSEL21_Msk (0x1U << CAN_FRF_FRFSEL21_Pos) /*!< 0x00200000 */ +#define CAN_FRF_FRFSEL21 CAN_FRF_FRFSEL21_Msk /*!< Filter relation FIFO select for filter 21 */ +#define CAN_FRF_FRFSEL22_Pos (22U) +#define CAN_FRF_FRFSEL22_Msk (0x1U << CAN_FRF_FRFSEL22_Pos) /*!< 0x00400000 */ +#define CAN_FRF_FRFSEL22 CAN_FRF_FRFSEL22_Msk /*!< Filter relation FIFO select for filter 22 */ +#define CAN_FRF_FRFSEL23_Pos (23U) +#define CAN_FRF_FRFSEL23_Msk (0x1U << CAN_FRF_FRFSEL23_Pos) /*!< 0x00800000 */ +#define CAN_FRF_FRFSEL23 CAN_FRF_FRFSEL23_Msk /*!< Filter relation FIFO select for filter 23 */ +#define CAN_FRF_FRFSEL24_Pos (24U) +#define CAN_FRF_FRFSEL24_Msk (0x1U << CAN_FRF_FRFSEL24_Pos) /*!< 0x01000000 */ +#define CAN_FRF_FRFSEL24 CAN_FRF_FRFSEL24_Msk /*!< Filter relation FIFO select for filter 24 */ +#define CAN_FRF_FRFSEL25_Pos (25U) +#define CAN_FRF_FRFSEL25_Msk (0x1U << CAN_FRF_FRFSEL25_Pos) /*!< 0x02000000 */ +#define CAN_FRF_FRFSEL25 CAN_FRF_FRFSEL25_Msk /*!< Filter relation FIFO select for filter 25 */ +#define CAN_FRF_FRFSEL26_Pos (26U) +#define CAN_FRF_FRFSEL26_Msk (0x1U << CAN_FRF_FRFSEL26_Pos) /*!< 0x04000000 */ +#define CAN_FRF_FRFSEL26 CAN_FRF_FRFSEL26_Msk /*!< Filter relation FIFO select for filter 26 */ +#define CAN_FRF_FRFSEL27_Pos (27U) +#define CAN_FRF_FRFSEL27_Msk (0x1U << CAN_FRF_FRFSEL27_Pos) /*!< 0x08000000 */ +#define CAN_FRF_FRFSEL27 CAN_FRF_FRFSEL27_Msk /*!< Filter relation FIFO select for filter 27 */ + +/****************** Bit definition for CAN_FACFG register *******************/ +#define CAN_FACFG_FAEN_Pos (0U) +#define CAN_FACFG_FAEN_Msk (0xFFFFFFFU << CAN_FACFG_FAEN_Pos) /*!< 0x0FFFFFFF */ +#define CAN_FACFG_FAEN CAN_FACFG_FAEN_Msk /*!< Filter active enable */ +#define CAN_FACFG_FAEN0_Pos (0U) +#define CAN_FACFG_FAEN0_Msk (0x1U << CAN_FACFG_FAEN0_Pos) /*!< 0x00000001 */ +#define CAN_FACFG_FAEN0 CAN_FACFG_FAEN0_Msk /*!< Filter 0 active enable */ +#define CAN_FACFG_FAEN1_Pos (1U) +#define CAN_FACFG_FAEN1_Msk (0x1U << CAN_FACFG_FAEN1_Pos) /*!< 0x00000002 */ +#define CAN_FACFG_FAEN1 CAN_FACFG_FAEN1_Msk /*!< Filter 1 active enable */ +#define CAN_FACFG_FAEN2_Pos (2U) +#define CAN_FACFG_FAEN2_Msk (0x1U << CAN_FACFG_FAEN2_Pos) /*!< 0x00000004 */ +#define CAN_FACFG_FAEN2 CAN_FACFG_FAEN2_Msk /*!< Filter 2 active enable */ +#define CAN_FACFG_FAEN3_Pos (3U) +#define CAN_FACFG_FAEN3_Msk (0x1U << CAN_FACFG_FAEN3_Pos) /*!< 0x00000008 */ +#define CAN_FACFG_FAEN3 CAN_FACFG_FAEN3_Msk /*!< Filter 3 active enable */ +#define CAN_FACFG_FAEN4_Pos (4U) +#define CAN_FACFG_FAEN4_Msk (0x1U << CAN_FACFG_FAEN4_Pos) /*!< 0x00000010 */ +#define CAN_FACFG_FAEN4 CAN_FACFG_FAEN4_Msk /*!< Filter 4 active enable */ +#define CAN_FACFG_FAEN5_Pos (5U) +#define CAN_FACFG_FAEN5_Msk (0x1U << CAN_FACFG_FAEN5_Pos) /*!< 0x00000020 */ +#define CAN_FACFG_FAEN5 CAN_FACFG_FAEN5_Msk /*!< Filter 5 active enable */ +#define CAN_FACFG_FAEN6_Pos (6U) +#define CAN_FACFG_FAEN6_Msk (0x1U << CAN_FACFG_FAEN6_Pos) /*!< 0x00000040 */ +#define CAN_FACFG_FAEN6 CAN_FACFG_FAEN6_Msk /*!< Filter 6 active enable */ +#define CAN_FACFG_FAEN7_Pos (7U) +#define CAN_FACFG_FAEN7_Msk (0x1U << CAN_FACFG_FAEN7_Pos) /*!< 0x00000080 */ +#define CAN_FACFG_FAEN7 CAN_FACFG_FAEN7_Msk /*!< Filter 7 active enable */ +#define CAN_FACFG_FAEN8_Pos (8U) +#define CAN_FACFG_FAEN8_Msk (0x1U << CAN_FACFG_FAEN8_Pos) /*!< 0x00000100 */ +#define CAN_FACFG_FAEN8 CAN_FACFG_FAEN8_Msk /*!< Filter 8 active enable */ +#define CAN_FACFG_FAEN9_Pos (9U) +#define CAN_FACFG_FAEN9_Msk (0x1U << CAN_FACFG_FAEN9_Pos) /*!< 0x00000200 */ +#define CAN_FACFG_FAEN9 CAN_FACFG_FAEN9_Msk /*!< Filter 9 active enable */ +#define CAN_FACFG_FAEN10_Pos (10U) +#define CAN_FACFG_FAEN10_Msk (0x1U << CAN_FACFG_FAEN10_Pos) /*!< 0x00000400 */ +#define CAN_FACFG_FAEN10 CAN_FACFG_FAEN10_Msk /*!< Filter 10 active enable */ +#define CAN_FACFG_FAEN11_Pos (11U) +#define CAN_FACFG_FAEN11_Msk (0x1U << CAN_FACFG_FAEN11_Pos) /*!< 0x00000800 */ +#define CAN_FACFG_FAEN11 CAN_FACFG_FAEN11_Msk /*!< Filter 11 active enable */ +#define CAN_FACFG_FAEN12_Pos (12U) +#define CAN_FACFG_FAEN12_Msk (0x1U << CAN_FACFG_FAEN12_Pos) /*!< 0x00001000 */ +#define CAN_FACFG_FAEN12 CAN_FACFG_FAEN12_Msk /*!< Filter 12 active enable */ +#define CAN_FACFG_FAEN13_Pos (13U) +#define CAN_FACFG_FAEN13_Msk (0x1U << CAN_FACFG_FAEN13_Pos) /*!< 0x00002000 */ +#define CAN_FACFG_FAEN13 CAN_FACFG_FAEN13_Msk /*!< Filter 13 active enable */ +#define CAN_FACFG_FAEN14_Pos (14U) +#define CAN_FACFG_FAEN14_Msk (0x1U << CAN_FACFG_FAEN14_Pos) /*!< 0x00004000 */ +#define CAN_FACFG_FAEN14 CAN_FACFG_FAEN14_Msk /*!< Filter 14 active enable */ +#define CAN_FACFG_FAEN15_Pos (15U) +#define CAN_FACFG_FAEN15_Msk (0x1U << CAN_FACFG_FAEN15_Pos) /*!< 0x00008000 */ +#define CAN_FACFG_FAEN15 CAN_FACFG_FAEN15_Msk /*!< Filter 15 active enable */ +#define CAN_FACFG_FAEN16_Pos (16U) +#define CAN_FACFG_FAEN16_Msk (0x1U << CAN_FACFG_FAEN16_Pos) /*!< 0x00010000 */ +#define CAN_FACFG_FAEN16 CAN_FACFG_FAEN16_Msk /*!< Filter 16 active enable */ +#define CAN_FACFG_FAEN17_Pos (17U) +#define CAN_FACFG_FAEN17_Msk (0x1U << CAN_FACFG_FAEN17_Pos) /*!< 0x00020000 */ +#define CAN_FACFG_FAEN17 CAN_FACFG_FAEN17_Msk /*!< Filter 17 active enable */ +#define CAN_FACFG_FAEN18_Pos (18U) +#define CAN_FACFG_FAEN18_Msk (0x1U << CAN_FACFG_FAEN18_Pos) /*!< 0x00040000 */ +#define CAN_FACFG_FAEN18 CAN_FACFG_FAEN18_Msk /*!< Filter 18 active enable */ +#define CAN_FACFG_FAEN19_Pos (19U) +#define CAN_FACFG_FAEN19_Msk (0x1U << CAN_FACFG_FAEN19_Pos) /*!< 0x00080000 */ +#define CAN_FACFG_FAEN19 CAN_FACFG_FAEN19_Msk /*!< Filter 19 active enable */ +#define CAN_FACFG_FAEN20_Pos (20U) +#define CAN_FACFG_FAEN20_Msk (0x1U << CAN_FACFG_FAEN20_Pos) /*!< 0x00100000 */ +#define CAN_FACFG_FAEN20 CAN_FACFG_FAEN20_Msk /*!< Filter 20 active enable */ +#define CAN_FACFG_FAEN21_Pos (21U) +#define CAN_FACFG_FAEN21_Msk (0x1U << CAN_FACFG_FAEN21_Pos) /*!< 0x00200000 */ +#define CAN_FACFG_FAEN21 CAN_FACFG_FAEN21_Msk /*!< Filter 21 active enable */ +#define CAN_FACFG_FAEN22_Pos (22U) +#define CAN_FACFG_FAEN22_Msk (0x1U << CAN_FACFG_FAEN22_Pos) /*!< 0x00400000 */ +#define CAN_FACFG_FAEN22 CAN_FACFG_FAEN22_Msk /*!< Filter 22 active enable */ +#define CAN_FACFG_FAEN23_Pos (23U) +#define CAN_FACFG_FAEN23_Msk (0x1U << CAN_FACFG_FAEN23_Pos) /*!< 0x00800000 */ +#define CAN_FACFG_FAEN23 CAN_FACFG_FAEN23_Msk /*!< Filter 23 active enable */ +#define CAN_FACFG_FAEN24_Pos (24U) +#define CAN_FACFG_FAEN24_Msk (0x1U << CAN_FACFG_FAEN24_Pos) /*!< 0x01000000 */ +#define CAN_FACFG_FAEN24 CAN_FACFG_FAEN24_Msk /*!< Filter 24 active enable */ +#define CAN_FACFG_FAEN25_Pos (25U) +#define CAN_FACFG_FAEN25_Msk (0x1U << CAN_FACFG_FAEN25_Pos) /*!< 0x02000000 */ +#define CAN_FACFG_FAEN25 CAN_FACFG_FAEN25_Msk /*!< Filter 25 active enable */ +#define CAN_FACFG_FAEN26_Pos (26U) +#define CAN_FACFG_FAEN26_Msk (0x1U << CAN_FACFG_FAEN26_Pos) /*!< 0x04000000 */ +#define CAN_FACFG_FAEN26 CAN_FACFG_FAEN26_Msk /*!< Filter 26 active enable */ +#define CAN_FACFG_FAEN27_Pos (27U) +#define CAN_FACFG_FAEN27_Msk (0x1U << CAN_FACFG_FAEN27_Pos) /*!< 0x08000000 */ +#define CAN_FACFG_FAEN27 CAN_FACFG_FAEN27_Msk /*!< Filter 27 active enable */ + +/****************** Bit definition for CAN_F0FB1 register *******************/ +#define CAN_F0FB1_FFDB0_Pos (0U) +#define CAN_F0FB1_FFDB0_Msk (0x1U << CAN_F0FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F0FB1_FFDB0 CAN_F0FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F0FB1_FFDB1_Pos (1U) +#define CAN_F0FB1_FFDB1_Msk (0x1U << CAN_F0FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F0FB1_FFDB1 CAN_F0FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F0FB1_FFDB2_Pos (2U) +#define CAN_F0FB1_FFDB2_Msk (0x1U << CAN_F0FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F0FB1_FFDB2 CAN_F0FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F0FB1_FFDB3_Pos (3U) +#define CAN_F0FB1_FFDB3_Msk (0x1U << CAN_F0FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F0FB1_FFDB3 CAN_F0FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F0FB1_FFDB4_Pos (4U) +#define CAN_F0FB1_FFDB4_Msk (0x1U << CAN_F0FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F0FB1_FFDB4 CAN_F0FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F0FB1_FFDB5_Pos (5U) +#define CAN_F0FB1_FFDB5_Msk (0x1U << CAN_F0FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F0FB1_FFDB5 CAN_F0FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F0FB1_FFDB6_Pos (6U) +#define CAN_F0FB1_FFDB6_Msk (0x1U << CAN_F0FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F0FB1_FFDB6 CAN_F0FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F0FB1_FFDB7_Pos (7U) +#define CAN_F0FB1_FFDB7_Msk (0x1U << CAN_F0FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F0FB1_FFDB7 CAN_F0FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F0FB1_FFDB8_Pos (8U) +#define CAN_F0FB1_FFDB8_Msk (0x1U << CAN_F0FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F0FB1_FFDB8 CAN_F0FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F0FB1_FFDB9_Pos (9U) +#define CAN_F0FB1_FFDB9_Msk (0x1U << CAN_F0FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F0FB1_FFDB9 CAN_F0FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F0FB1_FFDB10_Pos (10U) +#define CAN_F0FB1_FFDB10_Msk (0x1U << CAN_F0FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F0FB1_FFDB10 CAN_F0FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F0FB1_FFDB11_Pos (11U) +#define CAN_F0FB1_FFDB11_Msk (0x1U << CAN_F0FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F0FB1_FFDB11 CAN_F0FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F0FB1_FFDB12_Pos (12U) +#define CAN_F0FB1_FFDB12_Msk (0x1U << CAN_F0FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F0FB1_FFDB12 CAN_F0FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F0FB1_FFDB13_Pos (13U) +#define CAN_F0FB1_FFDB13_Msk (0x1U << CAN_F0FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F0FB1_FFDB13 CAN_F0FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F0FB1_FFDB14_Pos (14U) +#define CAN_F0FB1_FFDB14_Msk (0x1U << CAN_F0FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F0FB1_FFDB14 CAN_F0FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F0FB1_FFDB15_Pos (15U) +#define CAN_F0FB1_FFDB15_Msk (0x1U << CAN_F0FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F0FB1_FFDB15 CAN_F0FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F0FB1_FFDB16_Pos (16U) +#define CAN_F0FB1_FFDB16_Msk (0x1U << CAN_F0FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F0FB1_FFDB16 CAN_F0FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F0FB1_FFDB17_Pos (17U) +#define CAN_F0FB1_FFDB17_Msk (0x1U << CAN_F0FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F0FB1_FFDB17 CAN_F0FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F0FB1_FFDB18_Pos (18U) +#define CAN_F0FB1_FFDB18_Msk (0x1U << CAN_F0FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F0FB1_FFDB18 CAN_F0FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F0FB1_FFDB19_Pos (19U) +#define CAN_F0FB1_FFDB19_Msk (0x1U << CAN_F0FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F0FB1_FFDB19 CAN_F0FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F0FB1_FFDB20_Pos (20U) +#define CAN_F0FB1_FFDB20_Msk (0x1U << CAN_F0FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F0FB1_FFDB20 CAN_F0FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F0FB1_FFDB21_Pos (21U) +#define CAN_F0FB1_FFDB21_Msk (0x1U << CAN_F0FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F0FB1_FFDB21 CAN_F0FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F0FB1_FFDB22_Pos (22U) +#define CAN_F0FB1_FFDB22_Msk (0x1U << CAN_F0FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F0FB1_FFDB22 CAN_F0FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F0FB1_FFDB23_Pos (23U) +#define CAN_F0FB1_FFDB23_Msk (0x1U << CAN_F0FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F0FB1_FFDB23 CAN_F0FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F0FB1_FFDB24_Pos (24U) +#define CAN_F0FB1_FFDB24_Msk (0x1U << CAN_F0FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F0FB1_FFDB24 CAN_F0FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F0FB1_FFDB25_Pos (25U) +#define CAN_F0FB1_FFDB25_Msk (0x1U << CAN_F0FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F0FB1_FFDB25 CAN_F0FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F0FB1_FFDB26_Pos (26U) +#define CAN_F0FB1_FFDB26_Msk (0x1U << CAN_F0FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F0FB1_FFDB26 CAN_F0FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F0FB1_FFDB27_Pos (27U) +#define CAN_F0FB1_FFDB27_Msk (0x1U << CAN_F0FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F0FB1_FFDB27 CAN_F0FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F0FB1_FFDB28_Pos (28U) +#define CAN_F0FB1_FFDB28_Msk (0x1U << CAN_F0FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F0FB1_FFDB28 CAN_F0FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F0FB1_FFDB29_Pos (29U) +#define CAN_F0FB1_FFDB29_Msk (0x1U << CAN_F0FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F0FB1_FFDB29 CAN_F0FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F0FB1_FFDB30_Pos (30U) +#define CAN_F0FB1_FFDB30_Msk (0x1U << CAN_F0FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F0FB1_FFDB30 CAN_F0FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F0FB1_FFDB31_Pos (31U) +#define CAN_F0FB1_FFDB31_Msk (0x1U << CAN_F0FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F0FB1_FFDB31 CAN_F0FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F1FB1 register *******************/ +#define CAN_F1FB1_FFDB0_Pos (0U) +#define CAN_F1FB1_FFDB0_Msk (0x1U << CAN_F1FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F1FB1_FFDB0 CAN_F1FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F1FB1_FFDB1_Pos (1U) +#define CAN_F1FB1_FFDB1_Msk (0x1U << CAN_F1FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F1FB1_FFDB1 CAN_F1FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F1FB1_FFDB2_Pos (2U) +#define CAN_F1FB1_FFDB2_Msk (0x1U << CAN_F1FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F1FB1_FFDB2 CAN_F1FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F1FB1_FFDB3_Pos (3U) +#define CAN_F1FB1_FFDB3_Msk (0x1U << CAN_F1FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F1FB1_FFDB3 CAN_F1FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F1FB1_FFDB4_Pos (4U) +#define CAN_F1FB1_FFDB4_Msk (0x1U << CAN_F1FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F1FB1_FFDB4 CAN_F1FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F1FB1_FFDB5_Pos (5U) +#define CAN_F1FB1_FFDB5_Msk (0x1U << CAN_F1FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F1FB1_FFDB5 CAN_F1FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F1FB1_FFDB6_Pos (6U) +#define CAN_F1FB1_FFDB6_Msk (0x1U << CAN_F1FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F1FB1_FFDB6 CAN_F1FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F1FB1_FFDB7_Pos (7U) +#define CAN_F1FB1_FFDB7_Msk (0x1U << CAN_F1FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F1FB1_FFDB7 CAN_F1FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F1FB1_FFDB8_Pos (8U) +#define CAN_F1FB1_FFDB8_Msk (0x1U << CAN_F1FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F1FB1_FFDB8 CAN_F1FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F1FB1_FFDB9_Pos (9U) +#define CAN_F1FB1_FFDB9_Msk (0x1U << CAN_F1FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F1FB1_FFDB9 CAN_F1FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F1FB1_FFDB10_Pos (10U) +#define CAN_F1FB1_FFDB10_Msk (0x1U << CAN_F1FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F1FB1_FFDB10 CAN_F1FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F1FB1_FFDB11_Pos (11U) +#define CAN_F1FB1_FFDB11_Msk (0x1U << CAN_F1FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F1FB1_FFDB11 CAN_F1FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F1FB1_FFDB12_Pos (12U) +#define CAN_F1FB1_FFDB12_Msk (0x1U << CAN_F1FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F1FB1_FFDB12 CAN_F1FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F1FB1_FFDB13_Pos (13U) +#define CAN_F1FB1_FFDB13_Msk (0x1U << CAN_F1FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F1FB1_FFDB13 CAN_F1FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F1FB1_FFDB14_Pos (14U) +#define CAN_F1FB1_FFDB14_Msk (0x1U << CAN_F1FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F1FB1_FFDB14 CAN_F1FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F1FB1_FFDB15_Pos (15U) +#define CAN_F1FB1_FFDB15_Msk (0x1U << CAN_F1FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F1FB1_FFDB15 CAN_F1FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F1FB1_FFDB16_Pos (16U) +#define CAN_F1FB1_FFDB16_Msk (0x1U << CAN_F1FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F1FB1_FFDB16 CAN_F1FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F1FB1_FFDB17_Pos (17U) +#define CAN_F1FB1_FFDB17_Msk (0x1U << CAN_F1FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F1FB1_FFDB17 CAN_F1FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F1FB1_FFDB18_Pos (18U) +#define CAN_F1FB1_FFDB18_Msk (0x1U << CAN_F1FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F1FB1_FFDB18 CAN_F1FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F1FB1_FFDB19_Pos (19U) +#define CAN_F1FB1_FFDB19_Msk (0x1U << CAN_F1FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F1FB1_FFDB19 CAN_F1FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F1FB1_FFDB20_Pos (20U) +#define CAN_F1FB1_FFDB20_Msk (0x1U << CAN_F1FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F1FB1_FFDB20 CAN_F1FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F1FB1_FFDB21_Pos (21U) +#define CAN_F1FB1_FFDB21_Msk (0x1U << CAN_F1FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F1FB1_FFDB21 CAN_F1FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F1FB1_FFDB22_Pos (22U) +#define CAN_F1FB1_FFDB22_Msk (0x1U << CAN_F1FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F1FB1_FFDB22 CAN_F1FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F1FB1_FFDB23_Pos (23U) +#define CAN_F1FB1_FFDB23_Msk (0x1U << CAN_F1FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F1FB1_FFDB23 CAN_F1FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F1FB1_FFDB24_Pos (24U) +#define CAN_F1FB1_FFDB24_Msk (0x1U << CAN_F1FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F1FB1_FFDB24 CAN_F1FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F1FB1_FFDB25_Pos (25U) +#define CAN_F1FB1_FFDB25_Msk (0x1U << CAN_F1FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F1FB1_FFDB25 CAN_F1FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F1FB1_FFDB26_Pos (26U) +#define CAN_F1FB1_FFDB26_Msk (0x1U << CAN_F1FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F1FB1_FFDB26 CAN_F1FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F1FB1_FFDB27_Pos (27U) +#define CAN_F1FB1_FFDB27_Msk (0x1U << CAN_F1FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F1FB1_FFDB27 CAN_F1FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F1FB1_FFDB28_Pos (28U) +#define CAN_F1FB1_FFDB28_Msk (0x1U << CAN_F1FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F1FB1_FFDB28 CAN_F1FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F1FB1_FFDB29_Pos (29U) +#define CAN_F1FB1_FFDB29_Msk (0x1U << CAN_F1FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F1FB1_FFDB29 CAN_F1FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F1FB1_FFDB30_Pos (30U) +#define CAN_F1FB1_FFDB30_Msk (0x1U << CAN_F1FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F1FB1_FFDB30 CAN_F1FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F1FB1_FFDB31_Pos (31U) +#define CAN_F1FB1_FFDB31_Msk (0x1U << CAN_F1FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F1FB1_FFDB31 CAN_F1FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F2FB1 register *******************/ +#define CAN_F2FB1_FFDB0_Pos (0U) +#define CAN_F2FB1_FFDB0_Msk (0x1U << CAN_F2FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F2FB1_FFDB0 CAN_F2FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F2FB1_FFDB1_Pos (1U) +#define CAN_F2FB1_FFDB1_Msk (0x1U << CAN_F2FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F2FB1_FFDB1 CAN_F2FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F2FB1_FFDB2_Pos (2U) +#define CAN_F2FB1_FFDB2_Msk (0x1U << CAN_F2FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F2FB1_FFDB2 CAN_F2FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F2FB1_FFDB3_Pos (3U) +#define CAN_F2FB1_FFDB3_Msk (0x1U << CAN_F2FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F2FB1_FFDB3 CAN_F2FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F2FB1_FFDB4_Pos (4U) +#define CAN_F2FB1_FFDB4_Msk (0x1U << CAN_F2FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F2FB1_FFDB4 CAN_F2FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F2FB1_FFDB5_Pos (5U) +#define CAN_F2FB1_FFDB5_Msk (0x1U << CAN_F2FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F2FB1_FFDB5 CAN_F2FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F2FB1_FFDB6_Pos (6U) +#define CAN_F2FB1_FFDB6_Msk (0x1U << CAN_F2FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F2FB1_FFDB6 CAN_F2FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F2FB1_FFDB7_Pos (7U) +#define CAN_F2FB1_FFDB7_Msk (0x1U << CAN_F2FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F2FB1_FFDB7 CAN_F2FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F2FB1_FFDB8_Pos (8U) +#define CAN_F2FB1_FFDB8_Msk (0x1U << CAN_F2FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F2FB1_FFDB8 CAN_F2FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F2FB1_FFDB9_Pos (9U) +#define CAN_F2FB1_FFDB9_Msk (0x1U << CAN_F2FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F2FB1_FFDB9 CAN_F2FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F2FB1_FFDB10_Pos (10U) +#define CAN_F2FB1_FFDB10_Msk (0x1U << CAN_F2FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F2FB1_FFDB10 CAN_F2FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F2FB1_FFDB11_Pos (11U) +#define CAN_F2FB1_FFDB11_Msk (0x1U << CAN_F2FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F2FB1_FFDB11 CAN_F2FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F2FB1_FFDB12_Pos (12U) +#define CAN_F2FB1_FFDB12_Msk (0x1U << CAN_F2FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F2FB1_FFDB12 CAN_F2FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F2FB1_FFDB13_Pos (13U) +#define CAN_F2FB1_FFDB13_Msk (0x1U << CAN_F2FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F2FB1_FFDB13 CAN_F2FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F2FB1_FFDB14_Pos (14U) +#define CAN_F2FB1_FFDB14_Msk (0x1U << CAN_F2FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F2FB1_FFDB14 CAN_F2FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F2FB1_FFDB15_Pos (15U) +#define CAN_F2FB1_FFDB15_Msk (0x1U << CAN_F2FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F2FB1_FFDB15 CAN_F2FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F2FB1_FFDB16_Pos (16U) +#define CAN_F2FB1_FFDB16_Msk (0x1U << CAN_F2FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F2FB1_FFDB16 CAN_F2FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F2FB1_FFDB17_Pos (17U) +#define CAN_F2FB1_FFDB17_Msk (0x1U << CAN_F2FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F2FB1_FFDB17 CAN_F2FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F2FB1_FFDB18_Pos (18U) +#define CAN_F2FB1_FFDB18_Msk (0x1U << CAN_F2FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F2FB1_FFDB18 CAN_F2FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F2FB1_FFDB19_Pos (19U) +#define CAN_F2FB1_FFDB19_Msk (0x1U << CAN_F2FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F2FB1_FFDB19 CAN_F2FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F2FB1_FFDB20_Pos (20U) +#define CAN_F2FB1_FFDB20_Msk (0x1U << CAN_F2FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F2FB1_FFDB20 CAN_F2FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F2FB1_FFDB21_Pos (21U) +#define CAN_F2FB1_FFDB21_Msk (0x1U << CAN_F2FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F2FB1_FFDB21 CAN_F2FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F2FB1_FFDB22_Pos (22U) +#define CAN_F2FB1_FFDB22_Msk (0x1U << CAN_F2FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F2FB1_FFDB22 CAN_F2FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F2FB1_FFDB23_Pos (23U) +#define CAN_F2FB1_FFDB23_Msk (0x1U << CAN_F2FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F2FB1_FFDB23 CAN_F2FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F2FB1_FFDB24_Pos (24U) +#define CAN_F2FB1_FFDB24_Msk (0x1U << CAN_F2FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F2FB1_FFDB24 CAN_F2FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F2FB1_FFDB25_Pos (25U) +#define CAN_F2FB1_FFDB25_Msk (0x1U << CAN_F2FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F2FB1_FFDB25 CAN_F2FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F2FB1_FFDB26_Pos (26U) +#define CAN_F2FB1_FFDB26_Msk (0x1U << CAN_F2FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F2FB1_FFDB26 CAN_F2FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F2FB1_FFDB27_Pos (27U) +#define CAN_F2FB1_FFDB27_Msk (0x1U << CAN_F2FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F2FB1_FFDB27 CAN_F2FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F2FB1_FFDB28_Pos (28U) +#define CAN_F2FB1_FFDB28_Msk (0x1U << CAN_F2FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F2FB1_FFDB28 CAN_F2FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F2FB1_FFDB29_Pos (29U) +#define CAN_F2FB1_FFDB29_Msk (0x1U << CAN_F2FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F2FB1_FFDB29 CAN_F2FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F2FB1_FFDB30_Pos (30U) +#define CAN_F2FB1_FFDB30_Msk (0x1U << CAN_F2FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F2FB1_FFDB30 CAN_F2FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F2FB1_FFDB31_Pos (31U) +#define CAN_F2FB1_FFDB31_Msk (0x1U << CAN_F2FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F2FB1_FFDB31 CAN_F2FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F3FB1 register *******************/ +#define CAN_F3FB1_FFDB0_Pos (0U) +#define CAN_F3FB1_FFDB0_Msk (0x1U << CAN_F3FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F3FB1_FFDB0 CAN_F3FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F3FB1_FFDB1_Pos (1U) +#define CAN_F3FB1_FFDB1_Msk (0x1U << CAN_F3FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F3FB1_FFDB1 CAN_F3FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F3FB1_FFDB2_Pos (2U) +#define CAN_F3FB1_FFDB2_Msk (0x1U << CAN_F3FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F3FB1_FFDB2 CAN_F3FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F3FB1_FFDB3_Pos (3U) +#define CAN_F3FB1_FFDB3_Msk (0x1U << CAN_F3FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F3FB1_FFDB3 CAN_F3FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F3FB1_FFDB4_Pos (4U) +#define CAN_F3FB1_FFDB4_Msk (0x1U << CAN_F3FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F3FB1_FFDB4 CAN_F3FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F3FB1_FFDB5_Pos (5U) +#define CAN_F3FB1_FFDB5_Msk (0x1U << CAN_F3FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F3FB1_FFDB5 CAN_F3FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F3FB1_FFDB6_Pos (6U) +#define CAN_F3FB1_FFDB6_Msk (0x1U << CAN_F3FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F3FB1_FFDB6 CAN_F3FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F3FB1_FFDB7_Pos (7U) +#define CAN_F3FB1_FFDB7_Msk (0x1U << CAN_F3FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F3FB1_FFDB7 CAN_F3FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F3FB1_FFDB8_Pos (8U) +#define CAN_F3FB1_FFDB8_Msk (0x1U << CAN_F3FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F3FB1_FFDB8 CAN_F3FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F3FB1_FFDB9_Pos (9U) +#define CAN_F3FB1_FFDB9_Msk (0x1U << CAN_F3FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F3FB1_FFDB9 CAN_F3FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F3FB1_FFDB10_Pos (10U) +#define CAN_F3FB1_FFDB10_Msk (0x1U << CAN_F3FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F3FB1_FFDB10 CAN_F3FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F3FB1_FFDB11_Pos (11U) +#define CAN_F3FB1_FFDB11_Msk (0x1U << CAN_F3FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F3FB1_FFDB11 CAN_F3FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F3FB1_FFDB12_Pos (12U) +#define CAN_F3FB1_FFDB12_Msk (0x1U << CAN_F3FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F3FB1_FFDB12 CAN_F3FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F3FB1_FFDB13_Pos (13U) +#define CAN_F3FB1_FFDB13_Msk (0x1U << CAN_F3FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F3FB1_FFDB13 CAN_F3FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F3FB1_FFDB14_Pos (14U) +#define CAN_F3FB1_FFDB14_Msk (0x1U << CAN_F3FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F3FB1_FFDB14 CAN_F3FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F3FB1_FFDB15_Pos (15U) +#define CAN_F3FB1_FFDB15_Msk (0x1U << CAN_F3FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F3FB1_FFDB15 CAN_F3FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F3FB1_FFDB16_Pos (16U) +#define CAN_F3FB1_FFDB16_Msk (0x1U << CAN_F3FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F3FB1_FFDB16 CAN_F3FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F3FB1_FFDB17_Pos (17U) +#define CAN_F3FB1_FFDB17_Msk (0x1U << CAN_F3FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F3FB1_FFDB17 CAN_F3FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F3FB1_FFDB18_Pos (18U) +#define CAN_F3FB1_FFDB18_Msk (0x1U << CAN_F3FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F3FB1_FFDB18 CAN_F3FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F3FB1_FFDB19_Pos (19U) +#define CAN_F3FB1_FFDB19_Msk (0x1U << CAN_F3FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F3FB1_FFDB19 CAN_F3FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F3FB1_FFDB20_Pos (20U) +#define CAN_F3FB1_FFDB20_Msk (0x1U << CAN_F3FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F3FB1_FFDB20 CAN_F3FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F3FB1_FFDB21_Pos (21U) +#define CAN_F3FB1_FFDB21_Msk (0x1U << CAN_F3FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F3FB1_FFDB21 CAN_F3FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F3FB1_FFDB22_Pos (22U) +#define CAN_F3FB1_FFDB22_Msk (0x1U << CAN_F3FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F3FB1_FFDB22 CAN_F3FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F3FB1_FFDB23_Pos (23U) +#define CAN_F3FB1_FFDB23_Msk (0x1U << CAN_F3FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F3FB1_FFDB23 CAN_F3FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F3FB1_FFDB24_Pos (24U) +#define CAN_F3FB1_FFDB24_Msk (0x1U << CAN_F3FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F3FB1_FFDB24 CAN_F3FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F3FB1_FFDB25_Pos (25U) +#define CAN_F3FB1_FFDB25_Msk (0x1U << CAN_F3FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F3FB1_FFDB25 CAN_F3FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F3FB1_FFDB26_Pos (26U) +#define CAN_F3FB1_FFDB26_Msk (0x1U << CAN_F3FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F3FB1_FFDB26 CAN_F3FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F3FB1_FFDB27_Pos (27U) +#define CAN_F3FB1_FFDB27_Msk (0x1U << CAN_F3FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F3FB1_FFDB27 CAN_F3FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F3FB1_FFDB28_Pos (28U) +#define CAN_F3FB1_FFDB28_Msk (0x1U << CAN_F3FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F3FB1_FFDB28 CAN_F3FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F3FB1_FFDB29_Pos (29U) +#define CAN_F3FB1_FFDB29_Msk (0x1U << CAN_F3FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F3FB1_FFDB29 CAN_F3FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F3FB1_FFDB30_Pos (30U) +#define CAN_F3FB1_FFDB30_Msk (0x1U << CAN_F3FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F3FB1_FFDB30 CAN_F3FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F3FB1_FFDB31_Pos (31U) +#define CAN_F3FB1_FFDB31_Msk (0x1U << CAN_F3FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F3FB1_FFDB31 CAN_F3FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F4FB1 register *******************/ +#define CAN_F4FB1_FFDB0_Pos (0U) +#define CAN_F4FB1_FFDB0_Msk (0x1U << CAN_F4FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F4FB1_FFDB0 CAN_F4FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F4FB1_FFDB1_Pos (1U) +#define CAN_F4FB1_FFDB1_Msk (0x1U << CAN_F4FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F4FB1_FFDB1 CAN_F4FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F4FB1_FFDB2_Pos (2U) +#define CAN_F4FB1_FFDB2_Msk (0x1U << CAN_F4FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F4FB1_FFDB2 CAN_F4FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F4FB1_FFDB3_Pos (3U) +#define CAN_F4FB1_FFDB3_Msk (0x1U << CAN_F4FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F4FB1_FFDB3 CAN_F4FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F4FB1_FFDB4_Pos (4U) +#define CAN_F4FB1_FFDB4_Msk (0x1U << CAN_F4FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F4FB1_FFDB4 CAN_F4FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F4FB1_FFDB5_Pos (5U) +#define CAN_F4FB1_FFDB5_Msk (0x1U << CAN_F4FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F4FB1_FFDB5 CAN_F4FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F4FB1_FFDB6_Pos (6U) +#define CAN_F4FB1_FFDB6_Msk (0x1U << CAN_F4FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F4FB1_FFDB6 CAN_F4FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F4FB1_FFDB7_Pos (7U) +#define CAN_F4FB1_FFDB7_Msk (0x1U << CAN_F4FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F4FB1_FFDB7 CAN_F4FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F4FB1_FFDB8_Pos (8U) +#define CAN_F4FB1_FFDB8_Msk (0x1U << CAN_F4FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F4FB1_FFDB8 CAN_F4FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F4FB1_FFDB9_Pos (9U) +#define CAN_F4FB1_FFDB9_Msk (0x1U << CAN_F4FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F4FB1_FFDB9 CAN_F4FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F4FB1_FFDB10_Pos (10U) +#define CAN_F4FB1_FFDB10_Msk (0x1U << CAN_F4FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F4FB1_FFDB10 CAN_F4FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F4FB1_FFDB11_Pos (11U) +#define CAN_F4FB1_FFDB11_Msk (0x1U << CAN_F4FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F4FB1_FFDB11 CAN_F4FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F4FB1_FFDB12_Pos (12U) +#define CAN_F4FB1_FFDB12_Msk (0x1U << CAN_F4FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F4FB1_FFDB12 CAN_F4FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F4FB1_FFDB13_Pos (13U) +#define CAN_F4FB1_FFDB13_Msk (0x1U << CAN_F4FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F4FB1_FFDB13 CAN_F4FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F4FB1_FFDB14_Pos (14U) +#define CAN_F4FB1_FFDB14_Msk (0x1U << CAN_F4FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F4FB1_FFDB14 CAN_F4FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F4FB1_FFDB15_Pos (15U) +#define CAN_F4FB1_FFDB15_Msk (0x1U << CAN_F4FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F4FB1_FFDB15 CAN_F4FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F4FB1_FFDB16_Pos (16U) +#define CAN_F4FB1_FFDB16_Msk (0x1U << CAN_F4FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F4FB1_FFDB16 CAN_F4FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F4FB1_FFDB17_Pos (17U) +#define CAN_F4FB1_FFDB17_Msk (0x1U << CAN_F4FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F4FB1_FFDB17 CAN_F4FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F4FB1_FFDB18_Pos (18U) +#define CAN_F4FB1_FFDB18_Msk (0x1U << CAN_F4FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F4FB1_FFDB18 CAN_F4FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F4FB1_FFDB19_Pos (19U) +#define CAN_F4FB1_FFDB19_Msk (0x1U << CAN_F4FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F4FB1_FFDB19 CAN_F4FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F4FB1_FFDB20_Pos (20U) +#define CAN_F4FB1_FFDB20_Msk (0x1U << CAN_F4FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F4FB1_FFDB20 CAN_F4FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F4FB1_FFDB21_Pos (21U) +#define CAN_F4FB1_FFDB21_Msk (0x1U << CAN_F4FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F4FB1_FFDB21 CAN_F4FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F4FB1_FFDB22_Pos (22U) +#define CAN_F4FB1_FFDB22_Msk (0x1U << CAN_F4FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F4FB1_FFDB22 CAN_F4FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F4FB1_FFDB23_Pos (23U) +#define CAN_F4FB1_FFDB23_Msk (0x1U << CAN_F4FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F4FB1_FFDB23 CAN_F4FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F4FB1_FFDB24_Pos (24U) +#define CAN_F4FB1_FFDB24_Msk (0x1U << CAN_F4FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F4FB1_FFDB24 CAN_F4FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F4FB1_FFDB25_Pos (25U) +#define CAN_F4FB1_FFDB25_Msk (0x1U << CAN_F4FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F4FB1_FFDB25 CAN_F4FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F4FB1_FFDB26_Pos (26U) +#define CAN_F4FB1_FFDB26_Msk (0x1U << CAN_F4FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F4FB1_FFDB26 CAN_F4FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F4FB1_FFDB27_Pos (27U) +#define CAN_F4FB1_FFDB27_Msk (0x1U << CAN_F4FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F4FB1_FFDB27 CAN_F4FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F4FB1_FFDB28_Pos (28U) +#define CAN_F4FB1_FFDB28_Msk (0x1U << CAN_F4FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F4FB1_FFDB28 CAN_F4FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F4FB1_FFDB29_Pos (29U) +#define CAN_F4FB1_FFDB29_Msk (0x1U << CAN_F4FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F4FB1_FFDB29 CAN_F4FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F4FB1_FFDB30_Pos (30U) +#define CAN_F4FB1_FFDB30_Msk (0x1U << CAN_F4FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F4FB1_FFDB30 CAN_F4FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F4FB1_FFDB31_Pos (31U) +#define CAN_F4FB1_FFDB31_Msk (0x1U << CAN_F4FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F4FB1_FFDB31 CAN_F4FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F5FB1 register *******************/ +#define CAN_F5FB1_FFDB0_Pos (0U) +#define CAN_F5FB1_FFDB0_Msk (0x1U << CAN_F5FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F5FB1_FFDB0 CAN_F5FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F5FB1_FFDB1_Pos (1U) +#define CAN_F5FB1_FFDB1_Msk (0x1U << CAN_F5FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F5FB1_FFDB1 CAN_F5FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F5FB1_FFDB2_Pos (2U) +#define CAN_F5FB1_FFDB2_Msk (0x1U << CAN_F5FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F5FB1_FFDB2 CAN_F5FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F5FB1_FFDB3_Pos (3U) +#define CAN_F5FB1_FFDB3_Msk (0x1U << CAN_F5FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F5FB1_FFDB3 CAN_F5FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F5FB1_FFDB4_Pos (4U) +#define CAN_F5FB1_FFDB4_Msk (0x1U << CAN_F5FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F5FB1_FFDB4 CAN_F5FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F5FB1_FFDB5_Pos (5U) +#define CAN_F5FB1_FFDB5_Msk (0x1U << CAN_F5FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F5FB1_FFDB5 CAN_F5FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F5FB1_FFDB6_Pos (6U) +#define CAN_F5FB1_FFDB6_Msk (0x1U << CAN_F5FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F5FB1_FFDB6 CAN_F5FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F5FB1_FFDB7_Pos (7U) +#define CAN_F5FB1_FFDB7_Msk (0x1U << CAN_F5FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F5FB1_FFDB7 CAN_F5FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F5FB1_FFDB8_Pos (8U) +#define CAN_F5FB1_FFDB8_Msk (0x1U << CAN_F5FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F5FB1_FFDB8 CAN_F5FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F5FB1_FFDB9_Pos (9U) +#define CAN_F5FB1_FFDB9_Msk (0x1U << CAN_F5FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F5FB1_FFDB9 CAN_F5FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F5FB1_FFDB10_Pos (10U) +#define CAN_F5FB1_FFDB10_Msk (0x1U << CAN_F5FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F5FB1_FFDB10 CAN_F5FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F5FB1_FFDB11_Pos (11U) +#define CAN_F5FB1_FFDB11_Msk (0x1U << CAN_F5FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F5FB1_FFDB11 CAN_F5FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F5FB1_FFDB12_Pos (12U) +#define CAN_F5FB1_FFDB12_Msk (0x1U << CAN_F5FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F5FB1_FFDB12 CAN_F5FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F5FB1_FFDB13_Pos (13U) +#define CAN_F5FB1_FFDB13_Msk (0x1U << CAN_F5FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F5FB1_FFDB13 CAN_F5FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F5FB1_FFDB14_Pos (14U) +#define CAN_F5FB1_FFDB14_Msk (0x1U << CAN_F5FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F5FB1_FFDB14 CAN_F5FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F5FB1_FFDB15_Pos (15U) +#define CAN_F5FB1_FFDB15_Msk (0x1U << CAN_F5FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F5FB1_FFDB15 CAN_F5FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F5FB1_FFDB16_Pos (16U) +#define CAN_F5FB1_FFDB16_Msk (0x1U << CAN_F5FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F5FB1_FFDB16 CAN_F5FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F5FB1_FFDB17_Pos (17U) +#define CAN_F5FB1_FFDB17_Msk (0x1U << CAN_F5FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F5FB1_FFDB17 CAN_F5FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F5FB1_FFDB18_Pos (18U) +#define CAN_F5FB1_FFDB18_Msk (0x1U << CAN_F5FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F5FB1_FFDB18 CAN_F5FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F5FB1_FFDB19_Pos (19U) +#define CAN_F5FB1_FFDB19_Msk (0x1U << CAN_F5FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F5FB1_FFDB19 CAN_F5FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F5FB1_FFDB20_Pos (20U) +#define CAN_F5FB1_FFDB20_Msk (0x1U << CAN_F5FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F5FB1_FFDB20 CAN_F5FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F5FB1_FFDB21_Pos (21U) +#define CAN_F5FB1_FFDB21_Msk (0x1U << CAN_F5FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F5FB1_FFDB21 CAN_F5FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F5FB1_FFDB22_Pos (22U) +#define CAN_F5FB1_FFDB22_Msk (0x1U << CAN_F5FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F5FB1_FFDB22 CAN_F5FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F5FB1_FFDB23_Pos (23U) +#define CAN_F5FB1_FFDB23_Msk (0x1U << CAN_F5FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F5FB1_FFDB23 CAN_F5FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F5FB1_FFDB24_Pos (24U) +#define CAN_F5FB1_FFDB24_Msk (0x1U << CAN_F5FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F5FB1_FFDB24 CAN_F5FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F5FB1_FFDB25_Pos (25U) +#define CAN_F5FB1_FFDB25_Msk (0x1U << CAN_F5FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F5FB1_FFDB25 CAN_F5FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F5FB1_FFDB26_Pos (26U) +#define CAN_F5FB1_FFDB26_Msk (0x1U << CAN_F5FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F5FB1_FFDB26 CAN_F5FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F5FB1_FFDB27_Pos (27U) +#define CAN_F5FB1_FFDB27_Msk (0x1U << CAN_F5FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F5FB1_FFDB27 CAN_F5FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F5FB1_FFDB28_Pos (28U) +#define CAN_F5FB1_FFDB28_Msk (0x1U << CAN_F5FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F5FB1_FFDB28 CAN_F5FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F5FB1_FFDB29_Pos (29U) +#define CAN_F5FB1_FFDB29_Msk (0x1U << CAN_F5FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F5FB1_FFDB29 CAN_F5FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F5FB1_FFDB30_Pos (30U) +#define CAN_F5FB1_FFDB30_Msk (0x1U << CAN_F5FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F5FB1_FFDB30 CAN_F5FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F5FB1_FFDB31_Pos (31U) +#define CAN_F5FB1_FFDB31_Msk (0x1U << CAN_F5FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F5FB1_FFDB31 CAN_F5FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F6FB1 register *******************/ +#define CAN_F6FB1_FFDB0_Pos (0U) +#define CAN_F6FB1_FFDB0_Msk (0x1U << CAN_F6FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F6FB1_FFDB0 CAN_F6FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F6FB1_FFDB1_Pos (1U) +#define CAN_F6FB1_FFDB1_Msk (0x1U << CAN_F6FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F6FB1_FFDB1 CAN_F6FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F6FB1_FFDB2_Pos (2U) +#define CAN_F6FB1_FFDB2_Msk (0x1U << CAN_F6FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F6FB1_FFDB2 CAN_F6FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F6FB1_FFDB3_Pos (3U) +#define CAN_F6FB1_FFDB3_Msk (0x1U << CAN_F6FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F6FB1_FFDB3 CAN_F6FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F6FB1_FFDB4_Pos (4U) +#define CAN_F6FB1_FFDB4_Msk (0x1U << CAN_F6FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F6FB1_FFDB4 CAN_F6FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F6FB1_FFDB5_Pos (5U) +#define CAN_F6FB1_FFDB5_Msk (0x1U << CAN_F6FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F6FB1_FFDB5 CAN_F6FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F6FB1_FFDB6_Pos (6U) +#define CAN_F6FB1_FFDB6_Msk (0x1U << CAN_F6FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F6FB1_FFDB6 CAN_F6FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F6FB1_FFDB7_Pos (7U) +#define CAN_F6FB1_FFDB7_Msk (0x1U << CAN_F6FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F6FB1_FFDB7 CAN_F6FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F6FB1_FFDB8_Pos (8U) +#define CAN_F6FB1_FFDB8_Msk (0x1U << CAN_F6FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F6FB1_FFDB8 CAN_F6FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F6FB1_FFDB9_Pos (9U) +#define CAN_F6FB1_FFDB9_Msk (0x1U << CAN_F6FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F6FB1_FFDB9 CAN_F6FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F6FB1_FFDB10_Pos (10U) +#define CAN_F6FB1_FFDB10_Msk (0x1U << CAN_F6FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F6FB1_FFDB10 CAN_F6FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F6FB1_FFDB11_Pos (11U) +#define CAN_F6FB1_FFDB11_Msk (0x1U << CAN_F6FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F6FB1_FFDB11 CAN_F6FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F6FB1_FFDB12_Pos (12U) +#define CAN_F6FB1_FFDB12_Msk (0x1U << CAN_F6FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F6FB1_FFDB12 CAN_F6FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F6FB1_FFDB13_Pos (13U) +#define CAN_F6FB1_FFDB13_Msk (0x1U << CAN_F6FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F6FB1_FFDB13 CAN_F6FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F6FB1_FFDB14_Pos (14U) +#define CAN_F6FB1_FFDB14_Msk (0x1U << CAN_F6FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F6FB1_FFDB14 CAN_F6FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F6FB1_FFDB15_Pos (15U) +#define CAN_F6FB1_FFDB15_Msk (0x1U << CAN_F6FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F6FB1_FFDB15 CAN_F6FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F6FB1_FFDB16_Pos (16U) +#define CAN_F6FB1_FFDB16_Msk (0x1U << CAN_F6FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F6FB1_FFDB16 CAN_F6FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F6FB1_FFDB17_Pos (17U) +#define CAN_F6FB1_FFDB17_Msk (0x1U << CAN_F6FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F6FB1_FFDB17 CAN_F6FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F6FB1_FFDB18_Pos (18U) +#define CAN_F6FB1_FFDB18_Msk (0x1U << CAN_F6FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F6FB1_FFDB18 CAN_F6FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F6FB1_FFDB19_Pos (19U) +#define CAN_F6FB1_FFDB19_Msk (0x1U << CAN_F6FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F6FB1_FFDB19 CAN_F6FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F6FB1_FFDB20_Pos (20U) +#define CAN_F6FB1_FFDB20_Msk (0x1U << CAN_F6FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F6FB1_FFDB20 CAN_F6FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F6FB1_FFDB21_Pos (21U) +#define CAN_F6FB1_FFDB21_Msk (0x1U << CAN_F6FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F6FB1_FFDB21 CAN_F6FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F6FB1_FFDB22_Pos (22U) +#define CAN_F6FB1_FFDB22_Msk (0x1U << CAN_F6FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F6FB1_FFDB22 CAN_F6FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F6FB1_FFDB23_Pos (23U) +#define CAN_F6FB1_FFDB23_Msk (0x1U << CAN_F6FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F6FB1_FFDB23 CAN_F6FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F6FB1_FFDB24_Pos (24U) +#define CAN_F6FB1_FFDB24_Msk (0x1U << CAN_F6FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F6FB1_FFDB24 CAN_F6FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F6FB1_FFDB25_Pos (25U) +#define CAN_F6FB1_FFDB25_Msk (0x1U << CAN_F6FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F6FB1_FFDB25 CAN_F6FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F6FB1_FFDB26_Pos (26U) +#define CAN_F6FB1_FFDB26_Msk (0x1U << CAN_F6FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F6FB1_FFDB26 CAN_F6FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F6FB1_FFDB27_Pos (27U) +#define CAN_F6FB1_FFDB27_Msk (0x1U << CAN_F6FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F6FB1_FFDB27 CAN_F6FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F6FB1_FFDB28_Pos (28U) +#define CAN_F6FB1_FFDB28_Msk (0x1U << CAN_F6FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F6FB1_FFDB28 CAN_F6FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F6FB1_FFDB29_Pos (29U) +#define CAN_F6FB1_FFDB29_Msk (0x1U << CAN_F6FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F6FB1_FFDB29 CAN_F6FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F6FB1_FFDB30_Pos (30U) +#define CAN_F6FB1_FFDB30_Msk (0x1U << CAN_F6FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F6FB1_FFDB30 CAN_F6FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F6FB1_FFDB31_Pos (31U) +#define CAN_F6FB1_FFDB31_Msk (0x1U << CAN_F6FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F6FB1_FFDB31 CAN_F6FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F7FB1 register *******************/ +#define CAN_F7FB1_FFDB0_Pos (0U) +#define CAN_F7FB1_FFDB0_Msk (0x1U << CAN_F7FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F7FB1_FFDB0 CAN_F7FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F7FB1_FFDB1_Pos (1U) +#define CAN_F7FB1_FFDB1_Msk (0x1U << CAN_F7FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F7FB1_FFDB1 CAN_F7FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F7FB1_FFDB2_Pos (2U) +#define CAN_F7FB1_FFDB2_Msk (0x1U << CAN_F7FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F7FB1_FFDB2 CAN_F7FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F7FB1_FFDB3_Pos (3U) +#define CAN_F7FB1_FFDB3_Msk (0x1U << CAN_F7FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F7FB1_FFDB3 CAN_F7FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F7FB1_FFDB4_Pos (4U) +#define CAN_F7FB1_FFDB4_Msk (0x1U << CAN_F7FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F7FB1_FFDB4 CAN_F7FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F7FB1_FFDB5_Pos (5U) +#define CAN_F7FB1_FFDB5_Msk (0x1U << CAN_F7FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F7FB1_FFDB5 CAN_F7FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F7FB1_FFDB6_Pos (6U) +#define CAN_F7FB1_FFDB6_Msk (0x1U << CAN_F7FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F7FB1_FFDB6 CAN_F7FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F7FB1_FFDB7_Pos (7U) +#define CAN_F7FB1_FFDB7_Msk (0x1U << CAN_F7FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F7FB1_FFDB7 CAN_F7FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F7FB1_FFDB8_Pos (8U) +#define CAN_F7FB1_FFDB8_Msk (0x1U << CAN_F7FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F7FB1_FFDB8 CAN_F7FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F7FB1_FFDB9_Pos (9U) +#define CAN_F7FB1_FFDB9_Msk (0x1U << CAN_F7FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F7FB1_FFDB9 CAN_F7FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F7FB1_FFDB10_Pos (10U) +#define CAN_F7FB1_FFDB10_Msk (0x1U << CAN_F7FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F7FB1_FFDB10 CAN_F7FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F7FB1_FFDB11_Pos (11U) +#define CAN_F7FB1_FFDB11_Msk (0x1U << CAN_F7FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F7FB1_FFDB11 CAN_F7FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F7FB1_FFDB12_Pos (12U) +#define CAN_F7FB1_FFDB12_Msk (0x1U << CAN_F7FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F7FB1_FFDB12 CAN_F7FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F7FB1_FFDB13_Pos (13U) +#define CAN_F7FB1_FFDB13_Msk (0x1U << CAN_F7FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F7FB1_FFDB13 CAN_F7FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F7FB1_FFDB14_Pos (14U) +#define CAN_F7FB1_FFDB14_Msk (0x1U << CAN_F7FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F7FB1_FFDB14 CAN_F7FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F7FB1_FFDB15_Pos (15U) +#define CAN_F7FB1_FFDB15_Msk (0x1U << CAN_F7FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F7FB1_FFDB15 CAN_F7FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F7FB1_FFDB16_Pos (16U) +#define CAN_F7FB1_FFDB16_Msk (0x1U << CAN_F7FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F7FB1_FFDB16 CAN_F7FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F7FB1_FFDB17_Pos (17U) +#define CAN_F7FB1_FFDB17_Msk (0x1U << CAN_F7FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F7FB1_FFDB17 CAN_F7FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F7FB1_FFDB18_Pos (18U) +#define CAN_F7FB1_FFDB18_Msk (0x1U << CAN_F7FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F7FB1_FFDB18 CAN_F7FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F7FB1_FFDB19_Pos (19U) +#define CAN_F7FB1_FFDB19_Msk (0x1U << CAN_F7FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F7FB1_FFDB19 CAN_F7FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F7FB1_FFDB20_Pos (20U) +#define CAN_F7FB1_FFDB20_Msk (0x1U << CAN_F7FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F7FB1_FFDB20 CAN_F7FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F7FB1_FFDB21_Pos (21U) +#define CAN_F7FB1_FFDB21_Msk (0x1U << CAN_F7FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F7FB1_FFDB21 CAN_F7FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F7FB1_FFDB22_Pos (22U) +#define CAN_F7FB1_FFDB22_Msk (0x1U << CAN_F7FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F7FB1_FFDB22 CAN_F7FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F7FB1_FFDB23_Pos (23U) +#define CAN_F7FB1_FFDB23_Msk (0x1U << CAN_F7FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F7FB1_FFDB23 CAN_F7FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F7FB1_FFDB24_Pos (24U) +#define CAN_F7FB1_FFDB24_Msk (0x1U << CAN_F7FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F7FB1_FFDB24 CAN_F7FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F7FB1_FFDB25_Pos (25U) +#define CAN_F7FB1_FFDB25_Msk (0x1U << CAN_F7FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F7FB1_FFDB25 CAN_F7FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F7FB1_FFDB26_Pos (26U) +#define CAN_F7FB1_FFDB26_Msk (0x1U << CAN_F7FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F7FB1_FFDB26 CAN_F7FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F7FB1_FFDB27_Pos (27U) +#define CAN_F7FB1_FFDB27_Msk (0x1U << CAN_F7FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F7FB1_FFDB27 CAN_F7FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F7FB1_FFDB28_Pos (28U) +#define CAN_F7FB1_FFDB28_Msk (0x1U << CAN_F7FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F7FB1_FFDB28 CAN_F7FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F7FB1_FFDB29_Pos (29U) +#define CAN_F7FB1_FFDB29_Msk (0x1U << CAN_F7FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F7FB1_FFDB29 CAN_F7FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F7FB1_FFDB30_Pos (30U) +#define CAN_F7FB1_FFDB30_Msk (0x1U << CAN_F7FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F7FB1_FFDB30 CAN_F7FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F7FB1_FFDB31_Pos (31U) +#define CAN_F7FB1_FFDB31_Msk (0x1U << CAN_F7FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F7FB1_FFDB31 CAN_F7FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F8FB1 register *******************/ +#define CAN_F8FB1_FFDB0_Pos (0U) +#define CAN_F8FB1_FFDB0_Msk (0x1U << CAN_F8FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F8FB1_FFDB0 CAN_F8FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F8FB1_FFDB1_Pos (1U) +#define CAN_F8FB1_FFDB1_Msk (0x1U << CAN_F8FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F8FB1_FFDB1 CAN_F8FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F8FB1_FFDB2_Pos (2U) +#define CAN_F8FB1_FFDB2_Msk (0x1U << CAN_F8FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F8FB1_FFDB2 CAN_F8FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F8FB1_FFDB3_Pos (3U) +#define CAN_F8FB1_FFDB3_Msk (0x1U << CAN_F8FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F8FB1_FFDB3 CAN_F8FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F8FB1_FFDB4_Pos (4U) +#define CAN_F8FB1_FFDB4_Msk (0x1U << CAN_F8FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F8FB1_FFDB4 CAN_F8FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F8FB1_FFDB5_Pos (5U) +#define CAN_F8FB1_FFDB5_Msk (0x1U << CAN_F8FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F8FB1_FFDB5 CAN_F8FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F8FB1_FFDB6_Pos (6U) +#define CAN_F8FB1_FFDB6_Msk (0x1U << CAN_F8FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F8FB1_FFDB6 CAN_F8FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F8FB1_FFDB7_Pos (7U) +#define CAN_F8FB1_FFDB7_Msk (0x1U << CAN_F8FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F8FB1_FFDB7 CAN_F8FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F8FB1_FFDB8_Pos (8U) +#define CAN_F8FB1_FFDB8_Msk (0x1U << CAN_F8FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F8FB1_FFDB8 CAN_F8FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F8FB1_FFDB9_Pos (9U) +#define CAN_F8FB1_FFDB9_Msk (0x1U << CAN_F8FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F8FB1_FFDB9 CAN_F8FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F8FB1_FFDB10_Pos (10U) +#define CAN_F8FB1_FFDB10_Msk (0x1U << CAN_F8FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F8FB1_FFDB10 CAN_F8FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F8FB1_FFDB11_Pos (11U) +#define CAN_F8FB1_FFDB11_Msk (0x1U << CAN_F8FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F8FB1_FFDB11 CAN_F8FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F8FB1_FFDB12_Pos (12U) +#define CAN_F8FB1_FFDB12_Msk (0x1U << CAN_F8FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F8FB1_FFDB12 CAN_F8FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F8FB1_FFDB13_Pos (13U) +#define CAN_F8FB1_FFDB13_Msk (0x1U << CAN_F8FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F8FB1_FFDB13 CAN_F8FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F8FB1_FFDB14_Pos (14U) +#define CAN_F8FB1_FFDB14_Msk (0x1U << CAN_F8FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F8FB1_FFDB14 CAN_F8FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F8FB1_FFDB15_Pos (15U) +#define CAN_F8FB1_FFDB15_Msk (0x1U << CAN_F8FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F8FB1_FFDB15 CAN_F8FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F8FB1_FFDB16_Pos (16U) +#define CAN_F8FB1_FFDB16_Msk (0x1U << CAN_F8FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F8FB1_FFDB16 CAN_F8FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F8FB1_FFDB17_Pos (17U) +#define CAN_F8FB1_FFDB17_Msk (0x1U << CAN_F8FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F8FB1_FFDB17 CAN_F8FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F8FB1_FFDB18_Pos (18U) +#define CAN_F8FB1_FFDB18_Msk (0x1U << CAN_F8FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F8FB1_FFDB18 CAN_F8FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F8FB1_FFDB19_Pos (19U) +#define CAN_F8FB1_FFDB19_Msk (0x1U << CAN_F8FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F8FB1_FFDB19 CAN_F8FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F8FB1_FFDB20_Pos (20U) +#define CAN_F8FB1_FFDB20_Msk (0x1U << CAN_F8FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F8FB1_FFDB20 CAN_F8FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F8FB1_FFDB21_Pos (21U) +#define CAN_F8FB1_FFDB21_Msk (0x1U << CAN_F8FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F8FB1_FFDB21 CAN_F8FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F8FB1_FFDB22_Pos (22U) +#define CAN_F8FB1_FFDB22_Msk (0x1U << CAN_F8FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F8FB1_FFDB22 CAN_F8FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F8FB1_FFDB23_Pos (23U) +#define CAN_F8FB1_FFDB23_Msk (0x1U << CAN_F8FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F8FB1_FFDB23 CAN_F8FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F8FB1_FFDB24_Pos (24U) +#define CAN_F8FB1_FFDB24_Msk (0x1U << CAN_F8FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F8FB1_FFDB24 CAN_F8FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F8FB1_FFDB25_Pos (25U) +#define CAN_F8FB1_FFDB25_Msk (0x1U << CAN_F8FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F8FB1_FFDB25 CAN_F8FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F8FB1_FFDB26_Pos (26U) +#define CAN_F8FB1_FFDB26_Msk (0x1U << CAN_F8FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F8FB1_FFDB26 CAN_F8FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F8FB1_FFDB27_Pos (27U) +#define CAN_F8FB1_FFDB27_Msk (0x1U << CAN_F8FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F8FB1_FFDB27 CAN_F8FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F8FB1_FFDB28_Pos (28U) +#define CAN_F8FB1_FFDB28_Msk (0x1U << CAN_F8FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F8FB1_FFDB28 CAN_F8FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F8FB1_FFDB29_Pos (29U) +#define CAN_F8FB1_FFDB29_Msk (0x1U << CAN_F8FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F8FB1_FFDB29 CAN_F8FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F8FB1_FFDB30_Pos (30U) +#define CAN_F8FB1_FFDB30_Msk (0x1U << CAN_F8FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F8FB1_FFDB30 CAN_F8FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F8FB1_FFDB31_Pos (31U) +#define CAN_F8FB1_FFDB31_Msk (0x1U << CAN_F8FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F8FB1_FFDB31 CAN_F8FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F9FB1 register *******************/ +#define CAN_F9FB1_FFDB0_Pos (0U) +#define CAN_F9FB1_FFDB0_Msk (0x1U << CAN_F9FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F9FB1_FFDB0 CAN_F9FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F9FB1_FFDB1_Pos (1U) +#define CAN_F9FB1_FFDB1_Msk (0x1U << CAN_F9FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F9FB1_FFDB1 CAN_F9FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F9FB1_FFDB2_Pos (2U) +#define CAN_F9FB1_FFDB2_Msk (0x1U << CAN_F9FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F9FB1_FFDB2 CAN_F9FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F9FB1_FFDB3_Pos (3U) +#define CAN_F9FB1_FFDB3_Msk (0x1U << CAN_F9FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F9FB1_FFDB3 CAN_F9FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F9FB1_FFDB4_Pos (4U) +#define CAN_F9FB1_FFDB4_Msk (0x1U << CAN_F9FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F9FB1_FFDB4 CAN_F9FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F9FB1_FFDB5_Pos (5U) +#define CAN_F9FB1_FFDB5_Msk (0x1U << CAN_F9FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F9FB1_FFDB5 CAN_F9FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F9FB1_FFDB6_Pos (6U) +#define CAN_F9FB1_FFDB6_Msk (0x1U << CAN_F9FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F9FB1_FFDB6 CAN_F9FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F9FB1_FFDB7_Pos (7U) +#define CAN_F9FB1_FFDB7_Msk (0x1U << CAN_F9FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F9FB1_FFDB7 CAN_F9FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F9FB1_FFDB8_Pos (8U) +#define CAN_F9FB1_FFDB8_Msk (0x1U << CAN_F9FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F9FB1_FFDB8 CAN_F9FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F9FB1_FFDB9_Pos (9U) +#define CAN_F9FB1_FFDB9_Msk (0x1U << CAN_F9FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F9FB1_FFDB9 CAN_F9FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F9FB1_FFDB10_Pos (10U) +#define CAN_F9FB1_FFDB10_Msk (0x1U << CAN_F9FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F9FB1_FFDB10 CAN_F9FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F9FB1_FFDB11_Pos (11U) +#define CAN_F9FB1_FFDB11_Msk (0x1U << CAN_F9FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F9FB1_FFDB11 CAN_F9FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F9FB1_FFDB12_Pos (12U) +#define CAN_F9FB1_FFDB12_Msk (0x1U << CAN_F9FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F9FB1_FFDB12 CAN_F9FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F9FB1_FFDB13_Pos (13U) +#define CAN_F9FB1_FFDB13_Msk (0x1U << CAN_F9FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F9FB1_FFDB13 CAN_F9FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F9FB1_FFDB14_Pos (14U) +#define CAN_F9FB1_FFDB14_Msk (0x1U << CAN_F9FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F9FB1_FFDB14 CAN_F9FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F9FB1_FFDB15_Pos (15U) +#define CAN_F9FB1_FFDB15_Msk (0x1U << CAN_F9FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F9FB1_FFDB15 CAN_F9FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F9FB1_FFDB16_Pos (16U) +#define CAN_F9FB1_FFDB16_Msk (0x1U << CAN_F9FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F9FB1_FFDB16 CAN_F9FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F9FB1_FFDB17_Pos (17U) +#define CAN_F9FB1_FFDB17_Msk (0x1U << CAN_F9FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F9FB1_FFDB17 CAN_F9FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F9FB1_FFDB18_Pos (18U) +#define CAN_F9FB1_FFDB18_Msk (0x1U << CAN_F9FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F9FB1_FFDB18 CAN_F9FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F9FB1_FFDB19_Pos (19U) +#define CAN_F9FB1_FFDB19_Msk (0x1U << CAN_F9FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F9FB1_FFDB19 CAN_F9FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F9FB1_FFDB20_Pos (20U) +#define CAN_F9FB1_FFDB20_Msk (0x1U << CAN_F9FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F9FB1_FFDB20 CAN_F9FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F9FB1_FFDB21_Pos (21U) +#define CAN_F9FB1_FFDB21_Msk (0x1U << CAN_F9FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F9FB1_FFDB21 CAN_F9FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F9FB1_FFDB22_Pos (22U) +#define CAN_F9FB1_FFDB22_Msk (0x1U << CAN_F9FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F9FB1_FFDB22 CAN_F9FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F9FB1_FFDB23_Pos (23U) +#define CAN_F9FB1_FFDB23_Msk (0x1U << CAN_F9FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F9FB1_FFDB23 CAN_F9FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F9FB1_FFDB24_Pos (24U) +#define CAN_F9FB1_FFDB24_Msk (0x1U << CAN_F9FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F9FB1_FFDB24 CAN_F9FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F9FB1_FFDB25_Pos (25U) +#define CAN_F9FB1_FFDB25_Msk (0x1U << CAN_F9FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F9FB1_FFDB25 CAN_F9FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F9FB1_FFDB26_Pos (26U) +#define CAN_F9FB1_FFDB26_Msk (0x1U << CAN_F9FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F9FB1_FFDB26 CAN_F9FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F9FB1_FFDB27_Pos (27U) +#define CAN_F9FB1_FFDB27_Msk (0x1U << CAN_F9FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F9FB1_FFDB27 CAN_F9FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F9FB1_FFDB28_Pos (28U) +#define CAN_F9FB1_FFDB28_Msk (0x1U << CAN_F9FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F9FB1_FFDB28 CAN_F9FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F9FB1_FFDB29_Pos (29U) +#define CAN_F9FB1_FFDB29_Msk (0x1U << CAN_F9FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F9FB1_FFDB29 CAN_F9FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F9FB1_FFDB30_Pos (30U) +#define CAN_F9FB1_FFDB30_Msk (0x1U << CAN_F9FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F9FB1_FFDB30 CAN_F9FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F9FB1_FFDB31_Pos (31U) +#define CAN_F9FB1_FFDB31_Msk (0x1U << CAN_F9FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F9FB1_FFDB31 CAN_F9FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F10FB1 register ******************/ +#define CAN_F10FB1_FFDB0_Pos (0U) +#define CAN_F10FB1_FFDB0_Msk (0x1U << CAN_F10FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F10FB1_FFDB0 CAN_F10FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F10FB1_FFDB1_Pos (1U) +#define CAN_F10FB1_FFDB1_Msk (0x1U << CAN_F10FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F10FB1_FFDB1 CAN_F10FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F10FB1_FFDB2_Pos (2U) +#define CAN_F10FB1_FFDB2_Msk (0x1U << CAN_F10FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F10FB1_FFDB2 CAN_F10FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F10FB1_FFDB3_Pos (3U) +#define CAN_F10FB1_FFDB3_Msk (0x1U << CAN_F10FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F10FB1_FFDB3 CAN_F10FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F10FB1_FFDB4_Pos (4U) +#define CAN_F10FB1_FFDB4_Msk (0x1U << CAN_F10FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F10FB1_FFDB4 CAN_F10FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F10FB1_FFDB5_Pos (5U) +#define CAN_F10FB1_FFDB5_Msk (0x1U << CAN_F10FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F10FB1_FFDB5 CAN_F10FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F10FB1_FFDB6_Pos (6U) +#define CAN_F10FB1_FFDB6_Msk (0x1U << CAN_F10FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F10FB1_FFDB6 CAN_F10FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F10FB1_FFDB7_Pos (7U) +#define CAN_F10FB1_FFDB7_Msk (0x1U << CAN_F10FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F10FB1_FFDB7 CAN_F10FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F10FB1_FFDB8_Pos (8U) +#define CAN_F10FB1_FFDB8_Msk (0x1U << CAN_F10FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F10FB1_FFDB8 CAN_F10FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F10FB1_FFDB9_Pos (9U) +#define CAN_F10FB1_FFDB9_Msk (0x1U << CAN_F10FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F10FB1_FFDB9 CAN_F10FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F10FB1_FFDB10_Pos (10U) +#define CAN_F10FB1_FFDB10_Msk (0x1U << CAN_F10FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F10FB1_FFDB10 CAN_F10FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F10FB1_FFDB11_Pos (11U) +#define CAN_F10FB1_FFDB11_Msk (0x1U << CAN_F10FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F10FB1_FFDB11 CAN_F10FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F10FB1_FFDB12_Pos (12U) +#define CAN_F10FB1_FFDB12_Msk (0x1U << CAN_F10FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F10FB1_FFDB12 CAN_F10FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F10FB1_FFDB13_Pos (13U) +#define CAN_F10FB1_FFDB13_Msk (0x1U << CAN_F10FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F10FB1_FFDB13 CAN_F10FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F10FB1_FFDB14_Pos (14U) +#define CAN_F10FB1_FFDB14_Msk (0x1U << CAN_F10FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F10FB1_FFDB14 CAN_F10FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F10FB1_FFDB15_Pos (15U) +#define CAN_F10FB1_FFDB15_Msk (0x1U << CAN_F10FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F10FB1_FFDB15 CAN_F10FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F10FB1_FFDB16_Pos (16U) +#define CAN_F10FB1_FFDB16_Msk (0x1U << CAN_F10FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F10FB1_FFDB16 CAN_F10FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F10FB1_FFDB17_Pos (17U) +#define CAN_F10FB1_FFDB17_Msk (0x1U << CAN_F10FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F10FB1_FFDB17 CAN_F10FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F10FB1_FFDB18_Pos (18U) +#define CAN_F10FB1_FFDB18_Msk (0x1U << CAN_F10FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F10FB1_FFDB18 CAN_F10FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F10FB1_FFDB19_Pos (19U) +#define CAN_F10FB1_FFDB19_Msk (0x1U << CAN_F10FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F10FB1_FFDB19 CAN_F10FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F10FB1_FFDB20_Pos (20U) +#define CAN_F10FB1_FFDB20_Msk (0x1U << CAN_F10FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F10FB1_FFDB20 CAN_F10FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F10FB1_FFDB21_Pos (21U) +#define CAN_F10FB1_FFDB21_Msk (0x1U << CAN_F10FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F10FB1_FFDB21 CAN_F10FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F10FB1_FFDB22_Pos (22U) +#define CAN_F10FB1_FFDB22_Msk (0x1U << CAN_F10FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F10FB1_FFDB22 CAN_F10FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F10FB1_FFDB23_Pos (23U) +#define CAN_F10FB1_FFDB23_Msk (0x1U << CAN_F10FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F10FB1_FFDB23 CAN_F10FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F10FB1_FFDB24_Pos (24U) +#define CAN_F10FB1_FFDB24_Msk (0x1U << CAN_F10FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F10FB1_FFDB24 CAN_F10FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F10FB1_FFDB25_Pos (25U) +#define CAN_F10FB1_FFDB25_Msk (0x1U << CAN_F10FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F10FB1_FFDB25 CAN_F10FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F10FB1_FFDB26_Pos (26U) +#define CAN_F10FB1_FFDB26_Msk (0x1U << CAN_F10FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F10FB1_FFDB26 CAN_F10FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F10FB1_FFDB27_Pos (27U) +#define CAN_F10FB1_FFDB27_Msk (0x1U << CAN_F10FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F10FB1_FFDB27 CAN_F10FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F10FB1_FFDB28_Pos (28U) +#define CAN_F10FB1_FFDB28_Msk (0x1U << CAN_F10FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F10FB1_FFDB28 CAN_F10FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F10FB1_FFDB29_Pos (29U) +#define CAN_F10FB1_FFDB29_Msk (0x1U << CAN_F10FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F10FB1_FFDB29 CAN_F10FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F10FB1_FFDB30_Pos (30U) +#define CAN_F10FB1_FFDB30_Msk (0x1U << CAN_F10FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F10FB1_FFDB30 CAN_F10FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F10FB1_FFDB31_Pos (31U) +#define CAN_F10FB1_FFDB31_Msk (0x1U << CAN_F10FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F10FB1_FFDB31 CAN_F10FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F11FB1 register ******************/ +#define CAN_F11FB1_FFDB0_Pos (0U) +#define CAN_F11FB1_FFDB0_Msk (0x1U << CAN_F11FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F11FB1_FFDB0 CAN_F11FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F11FB1_FFDB1_Pos (1U) +#define CAN_F11FB1_FFDB1_Msk (0x1U << CAN_F11FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F11FB1_FFDB1 CAN_F11FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F11FB1_FFDB2_Pos (2U) +#define CAN_F11FB1_FFDB2_Msk (0x1U << CAN_F11FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F11FB1_FFDB2 CAN_F11FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F11FB1_FFDB3_Pos (3U) +#define CAN_F11FB1_FFDB3_Msk (0x1U << CAN_F11FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F11FB1_FFDB3 CAN_F11FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F11FB1_FFDB4_Pos (4U) +#define CAN_F11FB1_FFDB4_Msk (0x1U << CAN_F11FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F11FB1_FFDB4 CAN_F11FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F11FB1_FFDB5_Pos (5U) +#define CAN_F11FB1_FFDB5_Msk (0x1U << CAN_F11FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F11FB1_FFDB5 CAN_F11FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F11FB1_FFDB6_Pos (6U) +#define CAN_F11FB1_FFDB6_Msk (0x1U << CAN_F11FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F11FB1_FFDB6 CAN_F11FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F11FB1_FFDB7_Pos (7U) +#define CAN_F11FB1_FFDB7_Msk (0x1U << CAN_F11FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F11FB1_FFDB7 CAN_F11FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F11FB1_FFDB8_Pos (8U) +#define CAN_F11FB1_FFDB8_Msk (0x1U << CAN_F11FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F11FB1_FFDB8 CAN_F11FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F11FB1_FFDB9_Pos (9U) +#define CAN_F11FB1_FFDB9_Msk (0x1U << CAN_F11FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F11FB1_FFDB9 CAN_F11FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F11FB1_FFDB10_Pos (10U) +#define CAN_F11FB1_FFDB10_Msk (0x1U << CAN_F11FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F11FB1_FFDB10 CAN_F11FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F11FB1_FFDB11_Pos (11U) +#define CAN_F11FB1_FFDB11_Msk (0x1U << CAN_F11FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F11FB1_FFDB11 CAN_F11FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F11FB1_FFDB12_Pos (12U) +#define CAN_F11FB1_FFDB12_Msk (0x1U << CAN_F11FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F11FB1_FFDB12 CAN_F11FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F11FB1_FFDB13_Pos (13U) +#define CAN_F11FB1_FFDB13_Msk (0x1U << CAN_F11FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F11FB1_FFDB13 CAN_F11FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F11FB1_FFDB14_Pos (14U) +#define CAN_F11FB1_FFDB14_Msk (0x1U << CAN_F11FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F11FB1_FFDB14 CAN_F11FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F11FB1_FFDB15_Pos (15U) +#define CAN_F11FB1_FFDB15_Msk (0x1U << CAN_F11FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F11FB1_FFDB15 CAN_F11FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F11FB1_FFDB16_Pos (16U) +#define CAN_F11FB1_FFDB16_Msk (0x1U << CAN_F11FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F11FB1_FFDB16 CAN_F11FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F11FB1_FFDB17_Pos (17U) +#define CAN_F11FB1_FFDB17_Msk (0x1U << CAN_F11FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F11FB1_FFDB17 CAN_F11FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F11FB1_FFDB18_Pos (18U) +#define CAN_F11FB1_FFDB18_Msk (0x1U << CAN_F11FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F11FB1_FFDB18 CAN_F11FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F11FB1_FFDB19_Pos (19U) +#define CAN_F11FB1_FFDB19_Msk (0x1U << CAN_F11FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F11FB1_FFDB19 CAN_F11FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F11FB1_FFDB20_Pos (20U) +#define CAN_F11FB1_FFDB20_Msk (0x1U << CAN_F11FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F11FB1_FFDB20 CAN_F11FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F11FB1_FFDB21_Pos (21U) +#define CAN_F11FB1_FFDB21_Msk (0x1U << CAN_F11FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F11FB1_FFDB21 CAN_F11FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F11FB1_FFDB22_Pos (22U) +#define CAN_F11FB1_FFDB22_Msk (0x1U << CAN_F11FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F11FB1_FFDB22 CAN_F11FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F11FB1_FFDB23_Pos (23U) +#define CAN_F11FB1_FFDB23_Msk (0x1U << CAN_F11FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F11FB1_FFDB23 CAN_F11FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F11FB1_FFDB24_Pos (24U) +#define CAN_F11FB1_FFDB24_Msk (0x1U << CAN_F11FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F11FB1_FFDB24 CAN_F11FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F11FB1_FFDB25_Pos (25U) +#define CAN_F11FB1_FFDB25_Msk (0x1U << CAN_F11FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F11FB1_FFDB25 CAN_F11FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F11FB1_FFDB26_Pos (26U) +#define CAN_F11FB1_FFDB26_Msk (0x1U << CAN_F11FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F11FB1_FFDB26 CAN_F11FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F11FB1_FFDB27_Pos (27U) +#define CAN_F11FB1_FFDB27_Msk (0x1U << CAN_F11FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F11FB1_FFDB27 CAN_F11FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F11FB1_FFDB28_Pos (28U) +#define CAN_F11FB1_FFDB28_Msk (0x1U << CAN_F11FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F11FB1_FFDB28 CAN_F11FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F11FB1_FFDB29_Pos (29U) +#define CAN_F11FB1_FFDB29_Msk (0x1U << CAN_F11FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F11FB1_FFDB29 CAN_F11FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F11FB1_FFDB30_Pos (30U) +#define CAN_F11FB1_FFDB30_Msk (0x1U << CAN_F11FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F11FB1_FFDB30 CAN_F11FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F11FB1_FFDB31_Pos (31U) +#define CAN_F11FB1_FFDB31_Msk (0x1U << CAN_F11FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F11FB1_FFDB31 CAN_F11FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F12FB1 register ******************/ +#define CAN_F12FB1_FFDB0_Pos (0U) +#define CAN_F12FB1_FFDB0_Msk (0x1U << CAN_F12FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F12FB1_FFDB0 CAN_F12FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F12FB1_FFDB1_Pos (1U) +#define CAN_F12FB1_FFDB1_Msk (0x1U << CAN_F12FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F12FB1_FFDB1 CAN_F12FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F12FB1_FFDB2_Pos (2U) +#define CAN_F12FB1_FFDB2_Msk (0x1U << CAN_F12FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F12FB1_FFDB2 CAN_F12FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F12FB1_FFDB3_Pos (3U) +#define CAN_F12FB1_FFDB3_Msk (0x1U << CAN_F12FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F12FB1_FFDB3 CAN_F12FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F12FB1_FFDB4_Pos (4U) +#define CAN_F12FB1_FFDB4_Msk (0x1U << CAN_F12FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F12FB1_FFDB4 CAN_F12FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F12FB1_FFDB5_Pos (5U) +#define CAN_F12FB1_FFDB5_Msk (0x1U << CAN_F12FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F12FB1_FFDB5 CAN_F12FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F12FB1_FFDB6_Pos (6U) +#define CAN_F12FB1_FFDB6_Msk (0x1U << CAN_F12FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F12FB1_FFDB6 CAN_F12FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F12FB1_FFDB7_Pos (7U) +#define CAN_F12FB1_FFDB7_Msk (0x1U << CAN_F12FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F12FB1_FFDB7 CAN_F12FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F12FB1_FFDB8_Pos (8U) +#define CAN_F12FB1_FFDB8_Msk (0x1U << CAN_F12FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F12FB1_FFDB8 CAN_F12FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F12FB1_FFDB9_Pos (9U) +#define CAN_F12FB1_FFDB9_Msk (0x1U << CAN_F12FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F12FB1_FFDB9 CAN_F12FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F12FB1_FFDB10_Pos (10U) +#define CAN_F12FB1_FFDB10_Msk (0x1U << CAN_F12FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F12FB1_FFDB10 CAN_F12FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F12FB1_FFDB11_Pos (11U) +#define CAN_F12FB1_FFDB11_Msk (0x1U << CAN_F12FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F12FB1_FFDB11 CAN_F12FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F12FB1_FFDB12_Pos (12U) +#define CAN_F12FB1_FFDB12_Msk (0x1U << CAN_F12FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F12FB1_FFDB12 CAN_F12FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F12FB1_FFDB13_Pos (13U) +#define CAN_F12FB1_FFDB13_Msk (0x1U << CAN_F12FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F12FB1_FFDB13 CAN_F12FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F12FB1_FFDB14_Pos (14U) +#define CAN_F12FB1_FFDB14_Msk (0x1U << CAN_F12FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F12FB1_FFDB14 CAN_F12FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F12FB1_FFDB15_Pos (15U) +#define CAN_F12FB1_FFDB15_Msk (0x1U << CAN_F12FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F12FB1_FFDB15 CAN_F12FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F12FB1_FFDB16_Pos (16U) +#define CAN_F12FB1_FFDB16_Msk (0x1U << CAN_F12FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F12FB1_FFDB16 CAN_F12FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F12FB1_FFDB17_Pos (17U) +#define CAN_F12FB1_FFDB17_Msk (0x1U << CAN_F12FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F12FB1_FFDB17 CAN_F12FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F12FB1_FFDB18_Pos (18U) +#define CAN_F12FB1_FFDB18_Msk (0x1U << CAN_F12FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F12FB1_FFDB18 CAN_F12FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F12FB1_FFDB19_Pos (19U) +#define CAN_F12FB1_FFDB19_Msk (0x1U << CAN_F12FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F12FB1_FFDB19 CAN_F12FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F12FB1_FFDB20_Pos (20U) +#define CAN_F12FB1_FFDB20_Msk (0x1U << CAN_F12FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F12FB1_FFDB20 CAN_F12FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F12FB1_FFDB21_Pos (21U) +#define CAN_F12FB1_FFDB21_Msk (0x1U << CAN_F12FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F12FB1_FFDB21 CAN_F12FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F12FB1_FFDB22_Pos (22U) +#define CAN_F12FB1_FFDB22_Msk (0x1U << CAN_F12FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F12FB1_FFDB22 CAN_F12FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F12FB1_FFDB23_Pos (23U) +#define CAN_F12FB1_FFDB23_Msk (0x1U << CAN_F12FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F12FB1_FFDB23 CAN_F12FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F12FB1_FFDB24_Pos (24U) +#define CAN_F12FB1_FFDB24_Msk (0x1U << CAN_F12FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F12FB1_FFDB24 CAN_F12FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F12FB1_FFDB25_Pos (25U) +#define CAN_F12FB1_FFDB25_Msk (0x1U << CAN_F12FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F12FB1_FFDB25 CAN_F12FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F12FB1_FFDB26_Pos (26U) +#define CAN_F12FB1_FFDB26_Msk (0x1U << CAN_F12FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F12FB1_FFDB26 CAN_F12FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F12FB1_FFDB27_Pos (27U) +#define CAN_F12FB1_FFDB27_Msk (0x1U << CAN_F12FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F12FB1_FFDB27 CAN_F12FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F12FB1_FFDB28_Pos (28U) +#define CAN_F12FB1_FFDB28_Msk (0x1U << CAN_F12FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F12FB1_FFDB28 CAN_F12FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F12FB1_FFDB29_Pos (29U) +#define CAN_F12FB1_FFDB29_Msk (0x1U << CAN_F12FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F12FB1_FFDB29 CAN_F12FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F12FB1_FFDB30_Pos (30U) +#define CAN_F12FB1_FFDB30_Msk (0x1U << CAN_F12FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F12FB1_FFDB30 CAN_F12FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F12FB1_FFDB31_Pos (31U) +#define CAN_F12FB1_FFDB31_Msk (0x1U << CAN_F12FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F12FB1_FFDB31 CAN_F12FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F13FB1 register ******************/ +#define CAN_F13FB1_FFDB0_Pos (0U) +#define CAN_F13FB1_FFDB0_Msk (0x1U << CAN_F13FB1_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F13FB1_FFDB0 CAN_F13FB1_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F13FB1_FFDB1_Pos (1U) +#define CAN_F13FB1_FFDB1_Msk (0x1U << CAN_F13FB1_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F13FB1_FFDB1 CAN_F13FB1_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F13FB1_FFDB2_Pos (2U) +#define CAN_F13FB1_FFDB2_Msk (0x1U << CAN_F13FB1_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F13FB1_FFDB2 CAN_F13FB1_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F13FB1_FFDB3_Pos (3U) +#define CAN_F13FB1_FFDB3_Msk (0x1U << CAN_F13FB1_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F13FB1_FFDB3 CAN_F13FB1_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F13FB1_FFDB4_Pos (4U) +#define CAN_F13FB1_FFDB4_Msk (0x1U << CAN_F13FB1_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F13FB1_FFDB4 CAN_F13FB1_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F13FB1_FFDB5_Pos (5U) +#define CAN_F13FB1_FFDB5_Msk (0x1U << CAN_F13FB1_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F13FB1_FFDB5 CAN_F13FB1_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F13FB1_FFDB6_Pos (6U) +#define CAN_F13FB1_FFDB6_Msk (0x1U << CAN_F13FB1_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F13FB1_FFDB6 CAN_F13FB1_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F13FB1_FFDB7_Pos (7U) +#define CAN_F13FB1_FFDB7_Msk (0x1U << CAN_F13FB1_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F13FB1_FFDB7 CAN_F13FB1_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F13FB1_FFDB8_Pos (8U) +#define CAN_F13FB1_FFDB8_Msk (0x1U << CAN_F13FB1_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F13FB1_FFDB8 CAN_F13FB1_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F13FB1_FFDB9_Pos (9U) +#define CAN_F13FB1_FFDB9_Msk (0x1U << CAN_F13FB1_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F13FB1_FFDB9 CAN_F13FB1_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F13FB1_FFDB10_Pos (10U) +#define CAN_F13FB1_FFDB10_Msk (0x1U << CAN_F13FB1_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F13FB1_FFDB10 CAN_F13FB1_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F13FB1_FFDB11_Pos (11U) +#define CAN_F13FB1_FFDB11_Msk (0x1U << CAN_F13FB1_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F13FB1_FFDB11 CAN_F13FB1_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F13FB1_FFDB12_Pos (12U) +#define CAN_F13FB1_FFDB12_Msk (0x1U << CAN_F13FB1_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F13FB1_FFDB12 CAN_F13FB1_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F13FB1_FFDB13_Pos (13U) +#define CAN_F13FB1_FFDB13_Msk (0x1U << CAN_F13FB1_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F13FB1_FFDB13 CAN_F13FB1_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F13FB1_FFDB14_Pos (14U) +#define CAN_F13FB1_FFDB14_Msk (0x1U << CAN_F13FB1_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F13FB1_FFDB14 CAN_F13FB1_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F13FB1_FFDB15_Pos (15U) +#define CAN_F13FB1_FFDB15_Msk (0x1U << CAN_F13FB1_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F13FB1_FFDB15 CAN_F13FB1_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F13FB1_FFDB16_Pos (16U) +#define CAN_F13FB1_FFDB16_Msk (0x1U << CAN_F13FB1_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F13FB1_FFDB16 CAN_F13FB1_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F13FB1_FFDB17_Pos (17U) +#define CAN_F13FB1_FFDB17_Msk (0x1U << CAN_F13FB1_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F13FB1_FFDB17 CAN_F13FB1_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F13FB1_FFDB18_Pos (18U) +#define CAN_F13FB1_FFDB18_Msk (0x1U << CAN_F13FB1_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F13FB1_FFDB18 CAN_F13FB1_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F13FB1_FFDB19_Pos (19U) +#define CAN_F13FB1_FFDB19_Msk (0x1U << CAN_F13FB1_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F13FB1_FFDB19 CAN_F13FB1_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F13FB1_FFDB20_Pos (20U) +#define CAN_F13FB1_FFDB20_Msk (0x1U << CAN_F13FB1_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F13FB1_FFDB20 CAN_F13FB1_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F13FB1_FFDB21_Pos (21U) +#define CAN_F13FB1_FFDB21_Msk (0x1U << CAN_F13FB1_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F13FB1_FFDB21 CAN_F13FB1_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F13FB1_FFDB22_Pos (22U) +#define CAN_F13FB1_FFDB22_Msk (0x1U << CAN_F13FB1_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F13FB1_FFDB22 CAN_F13FB1_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F13FB1_FFDB23_Pos (23U) +#define CAN_F13FB1_FFDB23_Msk (0x1U << CAN_F13FB1_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F13FB1_FFDB23 CAN_F13FB1_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F13FB1_FFDB24_Pos (24U) +#define CAN_F13FB1_FFDB24_Msk (0x1U << CAN_F13FB1_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F13FB1_FFDB24 CAN_F13FB1_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F13FB1_FFDB25_Pos (25U) +#define CAN_F13FB1_FFDB25_Msk (0x1U << CAN_F13FB1_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F13FB1_FFDB25 CAN_F13FB1_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F13FB1_FFDB26_Pos (26U) +#define CAN_F13FB1_FFDB26_Msk (0x1U << CAN_F13FB1_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F13FB1_FFDB26 CAN_F13FB1_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F13FB1_FFDB27_Pos (27U) +#define CAN_F13FB1_FFDB27_Msk (0x1U << CAN_F13FB1_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F13FB1_FFDB27 CAN_F13FB1_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F13FB1_FFDB28_Pos (28U) +#define CAN_F13FB1_FFDB28_Msk (0x1U << CAN_F13FB1_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F13FB1_FFDB28 CAN_F13FB1_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F13FB1_FFDB29_Pos (29U) +#define CAN_F13FB1_FFDB29_Msk (0x1U << CAN_F13FB1_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F13FB1_FFDB29 CAN_F13FB1_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F13FB1_FFDB30_Pos (30U) +#define CAN_F13FB1_FFDB30_Msk (0x1U << CAN_F13FB1_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F13FB1_FFDB30 CAN_F13FB1_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F13FB1_FFDB31_Pos (31U) +#define CAN_F13FB1_FFDB31_Msk (0x1U << CAN_F13FB1_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F13FB1_FFDB31 CAN_F13FB1_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F0FB2 register *******************/ +#define CAN_F0FB2_FFDB0_Pos (0U) +#define CAN_F0FB2_FFDB0_Msk (0x1U << CAN_F0FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F0FB2_FFDB0 CAN_F0FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F0FB2_FFDB1_Pos (1U) +#define CAN_F0FB2_FFDB1_Msk (0x1U << CAN_F0FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F0FB2_FFDB1 CAN_F0FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F0FB2_FFDB2_Pos (2U) +#define CAN_F0FB2_FFDB2_Msk (0x1U << CAN_F0FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F0FB2_FFDB2 CAN_F0FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F0FB2_FFDB3_Pos (3U) +#define CAN_F0FB2_FFDB3_Msk (0x1U << CAN_F0FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F0FB2_FFDB3 CAN_F0FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F0FB2_FFDB4_Pos (4U) +#define CAN_F0FB2_FFDB4_Msk (0x1U << CAN_F0FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F0FB2_FFDB4 CAN_F0FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F0FB2_FFDB5_Pos (5U) +#define CAN_F0FB2_FFDB5_Msk (0x1U << CAN_F0FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F0FB2_FFDB5 CAN_F0FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F0FB2_FFDB6_Pos (6U) +#define CAN_F0FB2_FFDB6_Msk (0x1U << CAN_F0FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F0FB2_FFDB6 CAN_F0FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F0FB2_FFDB7_Pos (7U) +#define CAN_F0FB2_FFDB7_Msk (0x1U << CAN_F0FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F0FB2_FFDB7 CAN_F0FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F0FB2_FFDB8_Pos (8U) +#define CAN_F0FB2_FFDB8_Msk (0x1U << CAN_F0FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F0FB2_FFDB8 CAN_F0FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F0FB2_FFDB9_Pos (9U) +#define CAN_F0FB2_FFDB9_Msk (0x1U << CAN_F0FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F0FB2_FFDB9 CAN_F0FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F0FB2_FFDB10_Pos (10U) +#define CAN_F0FB2_FFDB10_Msk (0x1U << CAN_F0FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F0FB2_FFDB10 CAN_F0FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F0FB2_FFDB11_Pos (11U) +#define CAN_F0FB2_FFDB11_Msk (0x1U << CAN_F0FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F0FB2_FFDB11 CAN_F0FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F0FB2_FFDB12_Pos (12U) +#define CAN_F0FB2_FFDB12_Msk (0x1U << CAN_F0FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F0FB2_FFDB12 CAN_F0FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F0FB2_FFDB13_Pos (13U) +#define CAN_F0FB2_FFDB13_Msk (0x1U << CAN_F0FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F0FB2_FFDB13 CAN_F0FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F0FB2_FFDB14_Pos (14U) +#define CAN_F0FB2_FFDB14_Msk (0x1U << CAN_F0FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F0FB2_FFDB14 CAN_F0FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F0FB2_FFDB15_Pos (15U) +#define CAN_F0FB2_FFDB15_Msk (0x1U << CAN_F0FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F0FB2_FFDB15 CAN_F0FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F0FB2_FFDB16_Pos (16U) +#define CAN_F0FB2_FFDB16_Msk (0x1U << CAN_F0FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F0FB2_FFDB16 CAN_F0FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F0FB2_FFDB17_Pos (17U) +#define CAN_F0FB2_FFDB17_Msk (0x1U << CAN_F0FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F0FB2_FFDB17 CAN_F0FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F0FB2_FFDB18_Pos (18U) +#define CAN_F0FB2_FFDB18_Msk (0x1U << CAN_F0FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F0FB2_FFDB18 CAN_F0FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F0FB2_FFDB19_Pos (19U) +#define CAN_F0FB2_FFDB19_Msk (0x1U << CAN_F0FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F0FB2_FFDB19 CAN_F0FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F0FB2_FFDB20_Pos (20U) +#define CAN_F0FB2_FFDB20_Msk (0x1U << CAN_F0FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F0FB2_FFDB20 CAN_F0FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F0FB2_FFDB21_Pos (21U) +#define CAN_F0FB2_FFDB21_Msk (0x1U << CAN_F0FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F0FB2_FFDB21 CAN_F0FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F0FB2_FFDB22_Pos (22U) +#define CAN_F0FB2_FFDB22_Msk (0x1U << CAN_F0FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F0FB2_FFDB22 CAN_F0FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F0FB2_FFDB23_Pos (23U) +#define CAN_F0FB2_FFDB23_Msk (0x1U << CAN_F0FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F0FB2_FFDB23 CAN_F0FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F0FB2_FFDB24_Pos (24U) +#define CAN_F0FB2_FFDB24_Msk (0x1U << CAN_F0FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F0FB2_FFDB24 CAN_F0FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F0FB2_FFDB25_Pos (25U) +#define CAN_F0FB2_FFDB25_Msk (0x1U << CAN_F0FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F0FB2_FFDB25 CAN_F0FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F0FB2_FFDB26_Pos (26U) +#define CAN_F0FB2_FFDB26_Msk (0x1U << CAN_F0FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F0FB2_FFDB26 CAN_F0FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F0FB2_FFDB27_Pos (27U) +#define CAN_F0FB2_FFDB27_Msk (0x1U << CAN_F0FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F0FB2_FFDB27 CAN_F0FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F0FB2_FFDB28_Pos (28U) +#define CAN_F0FB2_FFDB28_Msk (0x1U << CAN_F0FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F0FB2_FFDB28 CAN_F0FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F0FB2_FFDB29_Pos (29U) +#define CAN_F0FB2_FFDB29_Msk (0x1U << CAN_F0FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F0FB2_FFDB29 CAN_F0FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F0FB2_FFDB30_Pos (30U) +#define CAN_F0FB2_FFDB30_Msk (0x1U << CAN_F0FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F0FB2_FFDB30 CAN_F0FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F0FB2_FFDB31_Pos (31U) +#define CAN_F0FB2_FFDB31_Msk (0x1U << CAN_F0FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F0FB2_FFDB31 CAN_F0FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F1FB2 register *******************/ +#define CAN_F1FB2_FFDB0_Pos (0U) +#define CAN_F1FB2_FFDB0_Msk (0x1U << CAN_F1FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F1FB2_FFDB0 CAN_F1FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F1FB2_FFDB1_Pos (1U) +#define CAN_F1FB2_FFDB1_Msk (0x1U << CAN_F1FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F1FB2_FFDB1 CAN_F1FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F1FB2_FFDB2_Pos (2U) +#define CAN_F1FB2_FFDB2_Msk (0x1U << CAN_F1FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F1FB2_FFDB2 CAN_F1FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F1FB2_FFDB3_Pos (3U) +#define CAN_F1FB2_FFDB3_Msk (0x1U << CAN_F1FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F1FB2_FFDB3 CAN_F1FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F1FB2_FFDB4_Pos (4U) +#define CAN_F1FB2_FFDB4_Msk (0x1U << CAN_F1FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F1FB2_FFDB4 CAN_F1FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F1FB2_FFDB5_Pos (5U) +#define CAN_F1FB2_FFDB5_Msk (0x1U << CAN_F1FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F1FB2_FFDB5 CAN_F1FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F1FB2_FFDB6_Pos (6U) +#define CAN_F1FB2_FFDB6_Msk (0x1U << CAN_F1FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F1FB2_FFDB6 CAN_F1FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F1FB2_FFDB7_Pos (7U) +#define CAN_F1FB2_FFDB7_Msk (0x1U << CAN_F1FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F1FB2_FFDB7 CAN_F1FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F1FB2_FFDB8_Pos (8U) +#define CAN_F1FB2_FFDB8_Msk (0x1U << CAN_F1FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F1FB2_FFDB8 CAN_F1FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F1FB2_FFDB9_Pos (9U) +#define CAN_F1FB2_FFDB9_Msk (0x1U << CAN_F1FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F1FB2_FFDB9 CAN_F1FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F1FB2_FFDB10_Pos (10U) +#define CAN_F1FB2_FFDB10_Msk (0x1U << CAN_F1FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F1FB2_FFDB10 CAN_F1FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F1FB2_FFDB11_Pos (11U) +#define CAN_F1FB2_FFDB11_Msk (0x1U << CAN_F1FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F1FB2_FFDB11 CAN_F1FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F1FB2_FFDB12_Pos (12U) +#define CAN_F1FB2_FFDB12_Msk (0x1U << CAN_F1FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F1FB2_FFDB12 CAN_F1FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F1FB2_FFDB13_Pos (13U) +#define CAN_F1FB2_FFDB13_Msk (0x1U << CAN_F1FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F1FB2_FFDB13 CAN_F1FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F1FB2_FFDB14_Pos (14U) +#define CAN_F1FB2_FFDB14_Msk (0x1U << CAN_F1FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F1FB2_FFDB14 CAN_F1FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F1FB2_FFDB15_Pos (15U) +#define CAN_F1FB2_FFDB15_Msk (0x1U << CAN_F1FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F1FB2_FFDB15 CAN_F1FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F1FB2_FFDB16_Pos (16U) +#define CAN_F1FB2_FFDB16_Msk (0x1U << CAN_F1FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F1FB2_FFDB16 CAN_F1FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F1FB2_FFDB17_Pos (17U) +#define CAN_F1FB2_FFDB17_Msk (0x1U << CAN_F1FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F1FB2_FFDB17 CAN_F1FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F1FB2_FFDB18_Pos (18U) +#define CAN_F1FB2_FFDB18_Msk (0x1U << CAN_F1FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F1FB2_FFDB18 CAN_F1FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F1FB2_FFDB19_Pos (19U) +#define CAN_F1FB2_FFDB19_Msk (0x1U << CAN_F1FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F1FB2_FFDB19 CAN_F1FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F1FB2_FFDB20_Pos (20U) +#define CAN_F1FB2_FFDB20_Msk (0x1U << CAN_F1FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F1FB2_FFDB20 CAN_F1FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F1FB2_FFDB21_Pos (21U) +#define CAN_F1FB2_FFDB21_Msk (0x1U << CAN_F1FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F1FB2_FFDB21 CAN_F1FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F1FB2_FFDB22_Pos (22U) +#define CAN_F1FB2_FFDB22_Msk (0x1U << CAN_F1FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F1FB2_FFDB22 CAN_F1FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F1FB2_FFDB23_Pos (23U) +#define CAN_F1FB2_FFDB23_Msk (0x1U << CAN_F1FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F1FB2_FFDB23 CAN_F1FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F1FB2_FFDB24_Pos (24U) +#define CAN_F1FB2_FFDB24_Msk (0x1U << CAN_F1FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F1FB2_FFDB24 CAN_F1FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F1FB2_FFDB25_Pos (25U) +#define CAN_F1FB2_FFDB25_Msk (0x1U << CAN_F1FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F1FB2_FFDB25 CAN_F1FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F1FB2_FFDB26_Pos (26U) +#define CAN_F1FB2_FFDB26_Msk (0x1U << CAN_F1FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F1FB2_FFDB26 CAN_F1FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F1FB2_FFDB27_Pos (27U) +#define CAN_F1FB2_FFDB27_Msk (0x1U << CAN_F1FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F1FB2_FFDB27 CAN_F1FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F1FB2_FFDB28_Pos (28U) +#define CAN_F1FB2_FFDB28_Msk (0x1U << CAN_F1FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F1FB2_FFDB28 CAN_F1FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F1FB2_FFDB29_Pos (29U) +#define CAN_F1FB2_FFDB29_Msk (0x1U << CAN_F1FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F1FB2_FFDB29 CAN_F1FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F1FB2_FFDB30_Pos (30U) +#define CAN_F1FB2_FFDB30_Msk (0x1U << CAN_F1FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F1FB2_FFDB30 CAN_F1FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F1FB2_FFDB31_Pos (31U) +#define CAN_F1FB2_FFDB31_Msk (0x1U << CAN_F1FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F1FB2_FFDB31 CAN_F1FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F2FB2 register *******************/ +#define CAN_F2FB2_FFDB0_Pos (0U) +#define CAN_F2FB2_FFDB0_Msk (0x1U << CAN_F2FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F2FB2_FFDB0 CAN_F2FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F2FB2_FFDB1_Pos (1U) +#define CAN_F2FB2_FFDB1_Msk (0x1U << CAN_F2FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F2FB2_FFDB1 CAN_F2FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F2FB2_FFDB2_Pos (2U) +#define CAN_F2FB2_FFDB2_Msk (0x1U << CAN_F2FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F2FB2_FFDB2 CAN_F2FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F2FB2_FFDB3_Pos (3U) +#define CAN_F2FB2_FFDB3_Msk (0x1U << CAN_F2FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F2FB2_FFDB3 CAN_F2FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F2FB2_FFDB4_Pos (4U) +#define CAN_F2FB2_FFDB4_Msk (0x1U << CAN_F2FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F2FB2_FFDB4 CAN_F2FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F2FB2_FFDB5_Pos (5U) +#define CAN_F2FB2_FFDB5_Msk (0x1U << CAN_F2FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F2FB2_FFDB5 CAN_F2FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F2FB2_FFDB6_Pos (6U) +#define CAN_F2FB2_FFDB6_Msk (0x1U << CAN_F2FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F2FB2_FFDB6 CAN_F2FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F2FB2_FFDB7_Pos (7U) +#define CAN_F2FB2_FFDB7_Msk (0x1U << CAN_F2FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F2FB2_FFDB7 CAN_F2FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F2FB2_FFDB8_Pos (8U) +#define CAN_F2FB2_FFDB8_Msk (0x1U << CAN_F2FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F2FB2_FFDB8 CAN_F2FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F2FB2_FFDB9_Pos (9U) +#define CAN_F2FB2_FFDB9_Msk (0x1U << CAN_F2FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F2FB2_FFDB9 CAN_F2FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F2FB2_FFDB10_Pos (10U) +#define CAN_F2FB2_FFDB10_Msk (0x1U << CAN_F2FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F2FB2_FFDB10 CAN_F2FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F2FB2_FFDB11_Pos (11U) +#define CAN_F2FB2_FFDB11_Msk (0x1U << CAN_F2FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F2FB2_FFDB11 CAN_F2FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F2FB2_FFDB12_Pos (12U) +#define CAN_F2FB2_FFDB12_Msk (0x1U << CAN_F2FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F2FB2_FFDB12 CAN_F2FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F2FB2_FFDB13_Pos (13U) +#define CAN_F2FB2_FFDB13_Msk (0x1U << CAN_F2FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F2FB2_FFDB13 CAN_F2FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F2FB2_FFDB14_Pos (14U) +#define CAN_F2FB2_FFDB14_Msk (0x1U << CAN_F2FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F2FB2_FFDB14 CAN_F2FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F2FB2_FFDB15_Pos (15U) +#define CAN_F2FB2_FFDB15_Msk (0x1U << CAN_F2FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F2FB2_FFDB15 CAN_F2FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F2FB2_FFDB16_Pos (16U) +#define CAN_F2FB2_FFDB16_Msk (0x1U << CAN_F2FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F2FB2_FFDB16 CAN_F2FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F2FB2_FFDB17_Pos (17U) +#define CAN_F2FB2_FFDB17_Msk (0x1U << CAN_F2FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F2FB2_FFDB17 CAN_F2FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F2FB2_FFDB18_Pos (18U) +#define CAN_F2FB2_FFDB18_Msk (0x1U << CAN_F2FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F2FB2_FFDB18 CAN_F2FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F2FB2_FFDB19_Pos (19U) +#define CAN_F2FB2_FFDB19_Msk (0x1U << CAN_F2FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F2FB2_FFDB19 CAN_F2FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F2FB2_FFDB20_Pos (20U) +#define CAN_F2FB2_FFDB20_Msk (0x1U << CAN_F2FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F2FB2_FFDB20 CAN_F2FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F2FB2_FFDB21_Pos (21U) +#define CAN_F2FB2_FFDB21_Msk (0x1U << CAN_F2FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F2FB2_FFDB21 CAN_F2FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F2FB2_FFDB22_Pos (22U) +#define CAN_F2FB2_FFDB22_Msk (0x1U << CAN_F2FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F2FB2_FFDB22 CAN_F2FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F2FB2_FFDB23_Pos (23U) +#define CAN_F2FB2_FFDB23_Msk (0x1U << CAN_F2FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F2FB2_FFDB23 CAN_F2FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F2FB2_FFDB24_Pos (24U) +#define CAN_F2FB2_FFDB24_Msk (0x1U << CAN_F2FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F2FB2_FFDB24 CAN_F2FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F2FB2_FFDB25_Pos (25U) +#define CAN_F2FB2_FFDB25_Msk (0x1U << CAN_F2FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F2FB2_FFDB25 CAN_F2FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F2FB2_FFDB26_Pos (26U) +#define CAN_F2FB2_FFDB26_Msk (0x1U << CAN_F2FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F2FB2_FFDB26 CAN_F2FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F2FB2_FFDB27_Pos (27U) +#define CAN_F2FB2_FFDB27_Msk (0x1U << CAN_F2FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F2FB2_FFDB27 CAN_F2FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F2FB2_FFDB28_Pos (28U) +#define CAN_F2FB2_FFDB28_Msk (0x1U << CAN_F2FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F2FB2_FFDB28 CAN_F2FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F2FB2_FFDB29_Pos (29U) +#define CAN_F2FB2_FFDB29_Msk (0x1U << CAN_F2FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F2FB2_FFDB29 CAN_F2FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F2FB2_FFDB30_Pos (30U) +#define CAN_F2FB2_FFDB30_Msk (0x1U << CAN_F2FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F2FB2_FFDB30 CAN_F2FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F2FB2_FFDB31_Pos (31U) +#define CAN_F2FB2_FFDB31_Msk (0x1U << CAN_F2FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F2FB2_FFDB31 CAN_F2FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F3FB2 register *******************/ +#define CAN_F3FB2_FFDB0_Pos (0U) +#define CAN_F3FB2_FFDB0_Msk (0x1U << CAN_F3FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F3FB2_FFDB0 CAN_F3FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F3FB2_FFDB1_Pos (1U) +#define CAN_F3FB2_FFDB1_Msk (0x1U << CAN_F3FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F3FB2_FFDB1 CAN_F3FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F3FB2_FFDB2_Pos (2U) +#define CAN_F3FB2_FFDB2_Msk (0x1U << CAN_F3FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F3FB2_FFDB2 CAN_F3FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F3FB2_FFDB3_Pos (3U) +#define CAN_F3FB2_FFDB3_Msk (0x1U << CAN_F3FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F3FB2_FFDB3 CAN_F3FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F3FB2_FFDB4_Pos (4U) +#define CAN_F3FB2_FFDB4_Msk (0x1U << CAN_F3FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F3FB2_FFDB4 CAN_F3FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F3FB2_FFDB5_Pos (5U) +#define CAN_F3FB2_FFDB5_Msk (0x1U << CAN_F3FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F3FB2_FFDB5 CAN_F3FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F3FB2_FFDB6_Pos (6U) +#define CAN_F3FB2_FFDB6_Msk (0x1U << CAN_F3FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F3FB2_FFDB6 CAN_F3FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F3FB2_FFDB7_Pos (7U) +#define CAN_F3FB2_FFDB7_Msk (0x1U << CAN_F3FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F3FB2_FFDB7 CAN_F3FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F3FB2_FFDB8_Pos (8U) +#define CAN_F3FB2_FFDB8_Msk (0x1U << CAN_F3FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F3FB2_FFDB8 CAN_F3FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F3FB2_FFDB9_Pos (9U) +#define CAN_F3FB2_FFDB9_Msk (0x1U << CAN_F3FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F3FB2_FFDB9 CAN_F3FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F3FB2_FFDB10_Pos (10U) +#define CAN_F3FB2_FFDB10_Msk (0x1U << CAN_F3FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F3FB2_FFDB10 CAN_F3FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F3FB2_FFDB11_Pos (11U) +#define CAN_F3FB2_FFDB11_Msk (0x1U << CAN_F3FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F3FB2_FFDB11 CAN_F3FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F3FB2_FFDB12_Pos (12U) +#define CAN_F3FB2_FFDB12_Msk (0x1U << CAN_F3FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F3FB2_FFDB12 CAN_F3FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F3FB2_FFDB13_Pos (13U) +#define CAN_F3FB2_FFDB13_Msk (0x1U << CAN_F3FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F3FB2_FFDB13 CAN_F3FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F3FB2_FFDB14_Pos (14U) +#define CAN_F3FB2_FFDB14_Msk (0x1U << CAN_F3FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F3FB2_FFDB14 CAN_F3FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F3FB2_FFDB15_Pos (15U) +#define CAN_F3FB2_FFDB15_Msk (0x1U << CAN_F3FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F3FB2_FFDB15 CAN_F3FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F3FB2_FFDB16_Pos (16U) +#define CAN_F3FB2_FFDB16_Msk (0x1U << CAN_F3FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F3FB2_FFDB16 CAN_F3FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F3FB2_FFDB17_Pos (17U) +#define CAN_F3FB2_FFDB17_Msk (0x1U << CAN_F3FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F3FB2_FFDB17 CAN_F3FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F3FB2_FFDB18_Pos (18U) +#define CAN_F3FB2_FFDB18_Msk (0x1U << CAN_F3FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F3FB2_FFDB18 CAN_F3FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F3FB2_FFDB19_Pos (19U) +#define CAN_F3FB2_FFDB19_Msk (0x1U << CAN_F3FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F3FB2_FFDB19 CAN_F3FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F3FB2_FFDB20_Pos (20U) +#define CAN_F3FB2_FFDB20_Msk (0x1U << CAN_F3FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F3FB2_FFDB20 CAN_F3FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F3FB2_FFDB21_Pos (21U) +#define CAN_F3FB2_FFDB21_Msk (0x1U << CAN_F3FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F3FB2_FFDB21 CAN_F3FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F3FB2_FFDB22_Pos (22U) +#define CAN_F3FB2_FFDB22_Msk (0x1U << CAN_F3FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F3FB2_FFDB22 CAN_F3FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F3FB2_FFDB23_Pos (23U) +#define CAN_F3FB2_FFDB23_Msk (0x1U << CAN_F3FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F3FB2_FFDB23 CAN_F3FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F3FB2_FFDB24_Pos (24U) +#define CAN_F3FB2_FFDB24_Msk (0x1U << CAN_F3FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F3FB2_FFDB24 CAN_F3FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F3FB2_FFDB25_Pos (25U) +#define CAN_F3FB2_FFDB25_Msk (0x1U << CAN_F3FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F3FB2_FFDB25 CAN_F3FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F3FB2_FFDB26_Pos (26U) +#define CAN_F3FB2_FFDB26_Msk (0x1U << CAN_F3FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F3FB2_FFDB26 CAN_F3FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F3FB2_FFDB27_Pos (27U) +#define CAN_F3FB2_FFDB27_Msk (0x1U << CAN_F3FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F3FB2_FFDB27 CAN_F3FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F3FB2_FFDB28_Pos (28U) +#define CAN_F3FB2_FFDB28_Msk (0x1U << CAN_F3FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F3FB2_FFDB28 CAN_F3FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F3FB2_FFDB29_Pos (29U) +#define CAN_F3FB2_FFDB29_Msk (0x1U << CAN_F3FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F3FB2_FFDB29 CAN_F3FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F3FB2_FFDB30_Pos (30U) +#define CAN_F3FB2_FFDB30_Msk (0x1U << CAN_F3FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F3FB2_FFDB30 CAN_F3FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F3FB2_FFDB31_Pos (31U) +#define CAN_F3FB2_FFDB31_Msk (0x1U << CAN_F3FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F3FB2_FFDB31 CAN_F3FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F4FB2 register *******************/ +#define CAN_F4FB2_FFDB0_Pos (0U) +#define CAN_F4FB2_FFDB0_Msk (0x1U << CAN_F4FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F4FB2_FFDB0 CAN_F4FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F4FB2_FFDB1_Pos (1U) +#define CAN_F4FB2_FFDB1_Msk (0x1U << CAN_F4FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F4FB2_FFDB1 CAN_F4FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F4FB2_FFDB2_Pos (2U) +#define CAN_F4FB2_FFDB2_Msk (0x1U << CAN_F4FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F4FB2_FFDB2 CAN_F4FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F4FB2_FFDB3_Pos (3U) +#define CAN_F4FB2_FFDB3_Msk (0x1U << CAN_F4FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F4FB2_FFDB3 CAN_F4FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F4FB2_FFDB4_Pos (4U) +#define CAN_F4FB2_FFDB4_Msk (0x1U << CAN_F4FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F4FB2_FFDB4 CAN_F4FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F4FB2_FFDB5_Pos (5U) +#define CAN_F4FB2_FFDB5_Msk (0x1U << CAN_F4FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F4FB2_FFDB5 CAN_F4FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F4FB2_FFDB6_Pos (6U) +#define CAN_F4FB2_FFDB6_Msk (0x1U << CAN_F4FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F4FB2_FFDB6 CAN_F4FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F4FB2_FFDB7_Pos (7U) +#define CAN_F4FB2_FFDB7_Msk (0x1U << CAN_F4FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F4FB2_FFDB7 CAN_F4FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F4FB2_FFDB8_Pos (8U) +#define CAN_F4FB2_FFDB8_Msk (0x1U << CAN_F4FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F4FB2_FFDB8 CAN_F4FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F4FB2_FFDB9_Pos (9U) +#define CAN_F4FB2_FFDB9_Msk (0x1U << CAN_F4FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F4FB2_FFDB9 CAN_F4FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F4FB2_FFDB10_Pos (10U) +#define CAN_F4FB2_FFDB10_Msk (0x1U << CAN_F4FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F4FB2_FFDB10 CAN_F4FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F4FB2_FFDB11_Pos (11U) +#define CAN_F4FB2_FFDB11_Msk (0x1U << CAN_F4FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F4FB2_FFDB11 CAN_F4FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F4FB2_FFDB12_Pos (12U) +#define CAN_F4FB2_FFDB12_Msk (0x1U << CAN_F4FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F4FB2_FFDB12 CAN_F4FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F4FB2_FFDB13_Pos (13U) +#define CAN_F4FB2_FFDB13_Msk (0x1U << CAN_F4FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F4FB2_FFDB13 CAN_F4FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F4FB2_FFDB14_Pos (14U) +#define CAN_F4FB2_FFDB14_Msk (0x1U << CAN_F4FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F4FB2_FFDB14 CAN_F4FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F4FB2_FFDB15_Pos (15U) +#define CAN_F4FB2_FFDB15_Msk (0x1U << CAN_F4FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F4FB2_FFDB15 CAN_F4FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F4FB2_FFDB16_Pos (16U) +#define CAN_F4FB2_FFDB16_Msk (0x1U << CAN_F4FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F4FB2_FFDB16 CAN_F4FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F4FB2_FFDB17_Pos (17U) +#define CAN_F4FB2_FFDB17_Msk (0x1U << CAN_F4FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F4FB2_FFDB17 CAN_F4FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F4FB2_FFDB18_Pos (18U) +#define CAN_F4FB2_FFDB18_Msk (0x1U << CAN_F4FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F4FB2_FFDB18 CAN_F4FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F4FB2_FFDB19_Pos (19U) +#define CAN_F4FB2_FFDB19_Msk (0x1U << CAN_F4FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F4FB2_FFDB19 CAN_F4FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F4FB2_FFDB20_Pos (20U) +#define CAN_F4FB2_FFDB20_Msk (0x1U << CAN_F4FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F4FB2_FFDB20 CAN_F4FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F4FB2_FFDB21_Pos (21U) +#define CAN_F4FB2_FFDB21_Msk (0x1U << CAN_F4FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F4FB2_FFDB21 CAN_F4FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F4FB2_FFDB22_Pos (22U) +#define CAN_F4FB2_FFDB22_Msk (0x1U << CAN_F4FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F4FB2_FFDB22 CAN_F4FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F4FB2_FFDB23_Pos (23U) +#define CAN_F4FB2_FFDB23_Msk (0x1U << CAN_F4FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F4FB2_FFDB23 CAN_F4FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F4FB2_FFDB24_Pos (24U) +#define CAN_F4FB2_FFDB24_Msk (0x1U << CAN_F4FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F4FB2_FFDB24 CAN_F4FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F4FB2_FFDB25_Pos (25U) +#define CAN_F4FB2_FFDB25_Msk (0x1U << CAN_F4FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F4FB2_FFDB25 CAN_F4FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F4FB2_FFDB26_Pos (26U) +#define CAN_F4FB2_FFDB26_Msk (0x1U << CAN_F4FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F4FB2_FFDB26 CAN_F4FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F4FB2_FFDB27_Pos (27U) +#define CAN_F4FB2_FFDB27_Msk (0x1U << CAN_F4FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F4FB2_FFDB27 CAN_F4FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F4FB2_FFDB28_Pos (28U) +#define CAN_F4FB2_FFDB28_Msk (0x1U << CAN_F4FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F4FB2_FFDB28 CAN_F4FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F4FB2_FFDB29_Pos (29U) +#define CAN_F4FB2_FFDB29_Msk (0x1U << CAN_F4FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F4FB2_FFDB29 CAN_F4FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F4FB2_FFDB30_Pos (30U) +#define CAN_F4FB2_FFDB30_Msk (0x1U << CAN_F4FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F4FB2_FFDB30 CAN_F4FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F4FB2_FFDB31_Pos (31U) +#define CAN_F4FB2_FFDB31_Msk (0x1U << CAN_F4FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F4FB2_FFDB31 CAN_F4FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F5FB2 register *******************/ +#define CAN_F5FB2_FFDB0_Pos (0U) +#define CAN_F5FB2_FFDB0_Msk (0x1U << CAN_F5FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F5FB2_FFDB0 CAN_F5FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F5FB2_FFDB1_Pos (1U) +#define CAN_F5FB2_FFDB1_Msk (0x1U << CAN_F5FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F5FB2_FFDB1 CAN_F5FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F5FB2_FFDB2_Pos (2U) +#define CAN_F5FB2_FFDB2_Msk (0x1U << CAN_F5FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F5FB2_FFDB2 CAN_F5FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F5FB2_FFDB3_Pos (3U) +#define CAN_F5FB2_FFDB3_Msk (0x1U << CAN_F5FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F5FB2_FFDB3 CAN_F5FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F5FB2_FFDB4_Pos (4U) +#define CAN_F5FB2_FFDB4_Msk (0x1U << CAN_F5FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F5FB2_FFDB4 CAN_F5FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F5FB2_FFDB5_Pos (5U) +#define CAN_F5FB2_FFDB5_Msk (0x1U << CAN_F5FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F5FB2_FFDB5 CAN_F5FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F5FB2_FFDB6_Pos (6U) +#define CAN_F5FB2_FFDB6_Msk (0x1U << CAN_F5FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F5FB2_FFDB6 CAN_F5FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F5FB2_FFDB7_Pos (7U) +#define CAN_F5FB2_FFDB7_Msk (0x1U << CAN_F5FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F5FB2_FFDB7 CAN_F5FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F5FB2_FFDB8_Pos (8U) +#define CAN_F5FB2_FFDB8_Msk (0x1U << CAN_F5FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F5FB2_FFDB8 CAN_F5FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F5FB2_FFDB9_Pos (9U) +#define CAN_F5FB2_FFDB9_Msk (0x1U << CAN_F5FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F5FB2_FFDB9 CAN_F5FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F5FB2_FFDB10_Pos (10U) +#define CAN_F5FB2_FFDB10_Msk (0x1U << CAN_F5FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F5FB2_FFDB10 CAN_F5FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F5FB2_FFDB11_Pos (11U) +#define CAN_F5FB2_FFDB11_Msk (0x1U << CAN_F5FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F5FB2_FFDB11 CAN_F5FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F5FB2_FFDB12_Pos (12U) +#define CAN_F5FB2_FFDB12_Msk (0x1U << CAN_F5FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F5FB2_FFDB12 CAN_F5FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F5FB2_FFDB13_Pos (13U) +#define CAN_F5FB2_FFDB13_Msk (0x1U << CAN_F5FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F5FB2_FFDB13 CAN_F5FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F5FB2_FFDB14_Pos (14U) +#define CAN_F5FB2_FFDB14_Msk (0x1U << CAN_F5FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F5FB2_FFDB14 CAN_F5FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F5FB2_FFDB15_Pos (15U) +#define CAN_F5FB2_FFDB15_Msk (0x1U << CAN_F5FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F5FB2_FFDB15 CAN_F5FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F5FB2_FFDB16_Pos (16U) +#define CAN_F5FB2_FFDB16_Msk (0x1U << CAN_F5FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F5FB2_FFDB16 CAN_F5FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F5FB2_FFDB17_Pos (17U) +#define CAN_F5FB2_FFDB17_Msk (0x1U << CAN_F5FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F5FB2_FFDB17 CAN_F5FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F5FB2_FFDB18_Pos (18U) +#define CAN_F5FB2_FFDB18_Msk (0x1U << CAN_F5FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F5FB2_FFDB18 CAN_F5FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F5FB2_FFDB19_Pos (19U) +#define CAN_F5FB2_FFDB19_Msk (0x1U << CAN_F5FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F5FB2_FFDB19 CAN_F5FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F5FB2_FFDB20_Pos (20U) +#define CAN_F5FB2_FFDB20_Msk (0x1U << CAN_F5FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F5FB2_FFDB20 CAN_F5FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F5FB2_FFDB21_Pos (21U) +#define CAN_F5FB2_FFDB21_Msk (0x1U << CAN_F5FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F5FB2_FFDB21 CAN_F5FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F5FB2_FFDB22_Pos (22U) +#define CAN_F5FB2_FFDB22_Msk (0x1U << CAN_F5FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F5FB2_FFDB22 CAN_F5FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F5FB2_FFDB23_Pos (23U) +#define CAN_F5FB2_FFDB23_Msk (0x1U << CAN_F5FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F5FB2_FFDB23 CAN_F5FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F5FB2_FFDB24_Pos (24U) +#define CAN_F5FB2_FFDB24_Msk (0x1U << CAN_F5FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F5FB2_FFDB24 CAN_F5FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F5FB2_FFDB25_Pos (25U) +#define CAN_F5FB2_FFDB25_Msk (0x1U << CAN_F5FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F5FB2_FFDB25 CAN_F5FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F5FB2_FFDB26_Pos (26U) +#define CAN_F5FB2_FFDB26_Msk (0x1U << CAN_F5FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F5FB2_FFDB26 CAN_F5FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F5FB2_FFDB27_Pos (27U) +#define CAN_F5FB2_FFDB27_Msk (0x1U << CAN_F5FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F5FB2_FFDB27 CAN_F5FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F5FB2_FFDB28_Pos (28U) +#define CAN_F5FB2_FFDB28_Msk (0x1U << CAN_F5FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F5FB2_FFDB28 CAN_F5FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F5FB2_FFDB29_Pos (29U) +#define CAN_F5FB2_FFDB29_Msk (0x1U << CAN_F5FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F5FB2_FFDB29 CAN_F5FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F5FB2_FFDB30_Pos (30U) +#define CAN_F5FB2_FFDB30_Msk (0x1U << CAN_F5FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F5FB2_FFDB30 CAN_F5FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F5FB2_FFDB31_Pos (31U) +#define CAN_F5FB2_FFDB31_Msk (0x1U << CAN_F5FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F5FB2_FFDB31 CAN_F5FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F6FB2 register *******************/ +#define CAN_F6FB2_FFDB0_Pos (0U) +#define CAN_F6FB2_FFDB0_Msk (0x1U << CAN_F6FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F6FB2_FFDB0 CAN_F6FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F6FB2_FFDB1_Pos (1U) +#define CAN_F6FB2_FFDB1_Msk (0x1U << CAN_F6FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F6FB2_FFDB1 CAN_F6FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F6FB2_FFDB2_Pos (2U) +#define CAN_F6FB2_FFDB2_Msk (0x1U << CAN_F6FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F6FB2_FFDB2 CAN_F6FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F6FB2_FFDB3_Pos (3U) +#define CAN_F6FB2_FFDB3_Msk (0x1U << CAN_F6FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F6FB2_FFDB3 CAN_F6FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F6FB2_FFDB4_Pos (4U) +#define CAN_F6FB2_FFDB4_Msk (0x1U << CAN_F6FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F6FB2_FFDB4 CAN_F6FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F6FB2_FFDB5_Pos (5U) +#define CAN_F6FB2_FFDB5_Msk (0x1U << CAN_F6FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F6FB2_FFDB5 CAN_F6FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F6FB2_FFDB6_Pos (6U) +#define CAN_F6FB2_FFDB6_Msk (0x1U << CAN_F6FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F6FB2_FFDB6 CAN_F6FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F6FB2_FFDB7_Pos (7U) +#define CAN_F6FB2_FFDB7_Msk (0x1U << CAN_F6FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F6FB2_FFDB7 CAN_F6FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F6FB2_FFDB8_Pos (8U) +#define CAN_F6FB2_FFDB8_Msk (0x1U << CAN_F6FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F6FB2_FFDB8 CAN_F6FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F6FB2_FFDB9_Pos (9U) +#define CAN_F6FB2_FFDB9_Msk (0x1U << CAN_F6FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F6FB2_FFDB9 CAN_F6FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F6FB2_FFDB10_Pos (10U) +#define CAN_F6FB2_FFDB10_Msk (0x1U << CAN_F6FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F6FB2_FFDB10 CAN_F6FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F6FB2_FFDB11_Pos (11U) +#define CAN_F6FB2_FFDB11_Msk (0x1U << CAN_F6FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F6FB2_FFDB11 CAN_F6FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F6FB2_FFDB12_Pos (12U) +#define CAN_F6FB2_FFDB12_Msk (0x1U << CAN_F6FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F6FB2_FFDB12 CAN_F6FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F6FB2_FFDB13_Pos (13U) +#define CAN_F6FB2_FFDB13_Msk (0x1U << CAN_F6FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F6FB2_FFDB13 CAN_F6FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F6FB2_FFDB14_Pos (14U) +#define CAN_F6FB2_FFDB14_Msk (0x1U << CAN_F6FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F6FB2_FFDB14 CAN_F6FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F6FB2_FFDB15_Pos (15U) +#define CAN_F6FB2_FFDB15_Msk (0x1U << CAN_F6FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F6FB2_FFDB15 CAN_F6FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F6FB2_FFDB16_Pos (16U) +#define CAN_F6FB2_FFDB16_Msk (0x1U << CAN_F6FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F6FB2_FFDB16 CAN_F6FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F6FB2_FFDB17_Pos (17U) +#define CAN_F6FB2_FFDB17_Msk (0x1U << CAN_F6FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F6FB2_FFDB17 CAN_F6FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F6FB2_FFDB18_Pos (18U) +#define CAN_F6FB2_FFDB18_Msk (0x1U << CAN_F6FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F6FB2_FFDB18 CAN_F6FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F6FB2_FFDB19_Pos (19U) +#define CAN_F6FB2_FFDB19_Msk (0x1U << CAN_F6FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F6FB2_FFDB19 CAN_F6FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F6FB2_FFDB20_Pos (20U) +#define CAN_F6FB2_FFDB20_Msk (0x1U << CAN_F6FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F6FB2_FFDB20 CAN_F6FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F6FB2_FFDB21_Pos (21U) +#define CAN_F6FB2_FFDB21_Msk (0x1U << CAN_F6FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F6FB2_FFDB21 CAN_F6FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F6FB2_FFDB22_Pos (22U) +#define CAN_F6FB2_FFDB22_Msk (0x1U << CAN_F6FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F6FB2_FFDB22 CAN_F6FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F6FB2_FFDB23_Pos (23U) +#define CAN_F6FB2_FFDB23_Msk (0x1U << CAN_F6FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F6FB2_FFDB23 CAN_F6FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F6FB2_FFDB24_Pos (24U) +#define CAN_F6FB2_FFDB24_Msk (0x1U << CAN_F6FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F6FB2_FFDB24 CAN_F6FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F6FB2_FFDB25_Pos (25U) +#define CAN_F6FB2_FFDB25_Msk (0x1U << CAN_F6FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F6FB2_FFDB25 CAN_F6FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F6FB2_FFDB26_Pos (26U) +#define CAN_F6FB2_FFDB26_Msk (0x1U << CAN_F6FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F6FB2_FFDB26 CAN_F6FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F6FB2_FFDB27_Pos (27U) +#define CAN_F6FB2_FFDB27_Msk (0x1U << CAN_F6FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F6FB2_FFDB27 CAN_F6FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F6FB2_FFDB28_Pos (28U) +#define CAN_F6FB2_FFDB28_Msk (0x1U << CAN_F6FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F6FB2_FFDB28 CAN_F6FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F6FB2_FFDB29_Pos (29U) +#define CAN_F6FB2_FFDB29_Msk (0x1U << CAN_F6FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F6FB2_FFDB29 CAN_F6FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F6FB2_FFDB30_Pos (30U) +#define CAN_F6FB2_FFDB30_Msk (0x1U << CAN_F6FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F6FB2_FFDB30 CAN_F6FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F6FB2_FFDB31_Pos (31U) +#define CAN_F6FB2_FFDB31_Msk (0x1U << CAN_F6FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F6FB2_FFDB31 CAN_F6FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F7FB2 register *******************/ +#define CAN_F7FB2_FFDB0_Pos (0U) +#define CAN_F7FB2_FFDB0_Msk (0x1U << CAN_F7FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F7FB2_FFDB0 CAN_F7FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F7FB2_FFDB1_Pos (1U) +#define CAN_F7FB2_FFDB1_Msk (0x1U << CAN_F7FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F7FB2_FFDB1 CAN_F7FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F7FB2_FFDB2_Pos (2U) +#define CAN_F7FB2_FFDB2_Msk (0x1U << CAN_F7FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F7FB2_FFDB2 CAN_F7FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F7FB2_FFDB3_Pos (3U) +#define CAN_F7FB2_FFDB3_Msk (0x1U << CAN_F7FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F7FB2_FFDB3 CAN_F7FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F7FB2_FFDB4_Pos (4U) +#define CAN_F7FB2_FFDB4_Msk (0x1U << CAN_F7FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F7FB2_FFDB4 CAN_F7FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F7FB2_FFDB5_Pos (5U) +#define CAN_F7FB2_FFDB5_Msk (0x1U << CAN_F7FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F7FB2_FFDB5 CAN_F7FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F7FB2_FFDB6_Pos (6U) +#define CAN_F7FB2_FFDB6_Msk (0x1U << CAN_F7FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F7FB2_FFDB6 CAN_F7FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F7FB2_FFDB7_Pos (7U) +#define CAN_F7FB2_FFDB7_Msk (0x1U << CAN_F7FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F7FB2_FFDB7 CAN_F7FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F7FB2_FFDB8_Pos (8U) +#define CAN_F7FB2_FFDB8_Msk (0x1U << CAN_F7FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F7FB2_FFDB8 CAN_F7FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F7FB2_FFDB9_Pos (9U) +#define CAN_F7FB2_FFDB9_Msk (0x1U << CAN_F7FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F7FB2_FFDB9 CAN_F7FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F7FB2_FFDB10_Pos (10U) +#define CAN_F7FB2_FFDB10_Msk (0x1U << CAN_F7FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F7FB2_FFDB10 CAN_F7FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F7FB2_FFDB11_Pos (11U) +#define CAN_F7FB2_FFDB11_Msk (0x1U << CAN_F7FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F7FB2_FFDB11 CAN_F7FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F7FB2_FFDB12_Pos (12U) +#define CAN_F7FB2_FFDB12_Msk (0x1U << CAN_F7FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F7FB2_FFDB12 CAN_F7FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F7FB2_FFDB13_Pos (13U) +#define CAN_F7FB2_FFDB13_Msk (0x1U << CAN_F7FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F7FB2_FFDB13 CAN_F7FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F7FB2_FFDB14_Pos (14U) +#define CAN_F7FB2_FFDB14_Msk (0x1U << CAN_F7FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F7FB2_FFDB14 CAN_F7FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F7FB2_FFDB15_Pos (15U) +#define CAN_F7FB2_FFDB15_Msk (0x1U << CAN_F7FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F7FB2_FFDB15 CAN_F7FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F7FB2_FFDB16_Pos (16U) +#define CAN_F7FB2_FFDB16_Msk (0x1U << CAN_F7FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F7FB2_FFDB16 CAN_F7FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F7FB2_FFDB17_Pos (17U) +#define CAN_F7FB2_FFDB17_Msk (0x1U << CAN_F7FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F7FB2_FFDB17 CAN_F7FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F7FB2_FFDB18_Pos (18U) +#define CAN_F7FB2_FFDB18_Msk (0x1U << CAN_F7FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F7FB2_FFDB18 CAN_F7FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F7FB2_FFDB19_Pos (19U) +#define CAN_F7FB2_FFDB19_Msk (0x1U << CAN_F7FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F7FB2_FFDB19 CAN_F7FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F7FB2_FFDB20_Pos (20U) +#define CAN_F7FB2_FFDB20_Msk (0x1U << CAN_F7FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F7FB2_FFDB20 CAN_F7FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F7FB2_FFDB21_Pos (21U) +#define CAN_F7FB2_FFDB21_Msk (0x1U << CAN_F7FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F7FB2_FFDB21 CAN_F7FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F7FB2_FFDB22_Pos (22U) +#define CAN_F7FB2_FFDB22_Msk (0x1U << CAN_F7FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F7FB2_FFDB22 CAN_F7FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F7FB2_FFDB23_Pos (23U) +#define CAN_F7FB2_FFDB23_Msk (0x1U << CAN_F7FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F7FB2_FFDB23 CAN_F7FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F7FB2_FFDB24_Pos (24U) +#define CAN_F7FB2_FFDB24_Msk (0x1U << CAN_F7FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F7FB2_FFDB24 CAN_F7FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F7FB2_FFDB25_Pos (25U) +#define CAN_F7FB2_FFDB25_Msk (0x1U << CAN_F7FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F7FB2_FFDB25 CAN_F7FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F7FB2_FFDB26_Pos (26U) +#define CAN_F7FB2_FFDB26_Msk (0x1U << CAN_F7FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F7FB2_FFDB26 CAN_F7FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F7FB2_FFDB27_Pos (27U) +#define CAN_F7FB2_FFDB27_Msk (0x1U << CAN_F7FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F7FB2_FFDB27 CAN_F7FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F7FB2_FFDB28_Pos (28U) +#define CAN_F7FB2_FFDB28_Msk (0x1U << CAN_F7FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F7FB2_FFDB28 CAN_F7FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F7FB2_FFDB29_Pos (29U) +#define CAN_F7FB2_FFDB29_Msk (0x1U << CAN_F7FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F7FB2_FFDB29 CAN_F7FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F7FB2_FFDB30_Pos (30U) +#define CAN_F7FB2_FFDB30_Msk (0x1U << CAN_F7FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F7FB2_FFDB30 CAN_F7FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F7FB2_FFDB31_Pos (31U) +#define CAN_F7FB2_FFDB31_Msk (0x1U << CAN_F7FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F7FB2_FFDB31 CAN_F7FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F8FB2 register *******************/ +#define CAN_F8FB2_FFDB0_Pos (0U) +#define CAN_F8FB2_FFDB0_Msk (0x1U << CAN_F8FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F8FB2_FFDB0 CAN_F8FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F8FB2_FFDB1_Pos (1U) +#define CAN_F8FB2_FFDB1_Msk (0x1U << CAN_F8FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F8FB2_FFDB1 CAN_F8FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F8FB2_FFDB2_Pos (2U) +#define CAN_F8FB2_FFDB2_Msk (0x1U << CAN_F8FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F8FB2_FFDB2 CAN_F8FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F8FB2_FFDB3_Pos (3U) +#define CAN_F8FB2_FFDB3_Msk (0x1U << CAN_F8FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F8FB2_FFDB3 CAN_F8FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F8FB2_FFDB4_Pos (4U) +#define CAN_F8FB2_FFDB4_Msk (0x1U << CAN_F8FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F8FB2_FFDB4 CAN_F8FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F8FB2_FFDB5_Pos (5U) +#define CAN_F8FB2_FFDB5_Msk (0x1U << CAN_F8FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F8FB2_FFDB5 CAN_F8FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F8FB2_FFDB6_Pos (6U) +#define CAN_F8FB2_FFDB6_Msk (0x1U << CAN_F8FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F8FB2_FFDB6 CAN_F8FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F8FB2_FFDB7_Pos (7U) +#define CAN_F8FB2_FFDB7_Msk (0x1U << CAN_F8FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F8FB2_FFDB7 CAN_F8FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F8FB2_FFDB8_Pos (8U) +#define CAN_F8FB2_FFDB8_Msk (0x1U << CAN_F8FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F8FB2_FFDB8 CAN_F8FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F8FB2_FFDB9_Pos (9U) +#define CAN_F8FB2_FFDB9_Msk (0x1U << CAN_F8FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F8FB2_FFDB9 CAN_F8FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F8FB2_FFDB10_Pos (10U) +#define CAN_F8FB2_FFDB10_Msk (0x1U << CAN_F8FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F8FB2_FFDB10 CAN_F8FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F8FB2_FFDB11_Pos (11U) +#define CAN_F8FB2_FFDB11_Msk (0x1U << CAN_F8FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F8FB2_FFDB11 CAN_F8FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F8FB2_FFDB12_Pos (12U) +#define CAN_F8FB2_FFDB12_Msk (0x1U << CAN_F8FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F8FB2_FFDB12 CAN_F8FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F8FB2_FFDB13_Pos (13U) +#define CAN_F8FB2_FFDB13_Msk (0x1U << CAN_F8FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F8FB2_FFDB13 CAN_F8FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F8FB2_FFDB14_Pos (14U) +#define CAN_F8FB2_FFDB14_Msk (0x1U << CAN_F8FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F8FB2_FFDB14 CAN_F8FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F8FB2_FFDB15_Pos (15U) +#define CAN_F8FB2_FFDB15_Msk (0x1U << CAN_F8FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F8FB2_FFDB15 CAN_F8FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F8FB2_FFDB16_Pos (16U) +#define CAN_F8FB2_FFDB16_Msk (0x1U << CAN_F8FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F8FB2_FFDB16 CAN_F8FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F8FB2_FFDB17_Pos (17U) +#define CAN_F8FB2_FFDB17_Msk (0x1U << CAN_F8FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F8FB2_FFDB17 CAN_F8FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F8FB2_FFDB18_Pos (18U) +#define CAN_F8FB2_FFDB18_Msk (0x1U << CAN_F8FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F8FB2_FFDB18 CAN_F8FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F8FB2_FFDB19_Pos (19U) +#define CAN_F8FB2_FFDB19_Msk (0x1U << CAN_F8FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F8FB2_FFDB19 CAN_F8FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F8FB2_FFDB20_Pos (20U) +#define CAN_F8FB2_FFDB20_Msk (0x1U << CAN_F8FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F8FB2_FFDB20 CAN_F8FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F8FB2_FFDB21_Pos (21U) +#define CAN_F8FB2_FFDB21_Msk (0x1U << CAN_F8FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F8FB2_FFDB21 CAN_F8FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F8FB2_FFDB22_Pos (22U) +#define CAN_F8FB2_FFDB22_Msk (0x1U << CAN_F8FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F8FB2_FFDB22 CAN_F8FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F8FB2_FFDB23_Pos (23U) +#define CAN_F8FB2_FFDB23_Msk (0x1U << CAN_F8FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F8FB2_FFDB23 CAN_F8FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F8FB2_FFDB24_Pos (24U) +#define CAN_F8FB2_FFDB24_Msk (0x1U << CAN_F8FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F8FB2_FFDB24 CAN_F8FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F8FB2_FFDB25_Pos (25U) +#define CAN_F8FB2_FFDB25_Msk (0x1U << CAN_F8FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F8FB2_FFDB25 CAN_F8FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F8FB2_FFDB26_Pos (26U) +#define CAN_F8FB2_FFDB26_Msk (0x1U << CAN_F8FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F8FB2_FFDB26 CAN_F8FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F8FB2_FFDB27_Pos (27U) +#define CAN_F8FB2_FFDB27_Msk (0x1U << CAN_F8FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F8FB2_FFDB27 CAN_F8FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F8FB2_FFDB28_Pos (28U) +#define CAN_F8FB2_FFDB28_Msk (0x1U << CAN_F8FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F8FB2_FFDB28 CAN_F8FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F8FB2_FFDB29_Pos (29U) +#define CAN_F8FB2_FFDB29_Msk (0x1U << CAN_F8FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F8FB2_FFDB29 CAN_F8FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F8FB2_FFDB30_Pos (30U) +#define CAN_F8FB2_FFDB30_Msk (0x1U << CAN_F8FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F8FB2_FFDB30 CAN_F8FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F8FB2_FFDB31_Pos (31U) +#define CAN_F8FB2_FFDB31_Msk (0x1U << CAN_F8FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F8FB2_FFDB31 CAN_F8FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F9FB2 register *******************/ +#define CAN_F9FB2_FFDB0_Pos (0U) +#define CAN_F9FB2_FFDB0_Msk (0x1U << CAN_F9FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F9FB2_FFDB0 CAN_F9FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F9FB2_FFDB1_Pos (1U) +#define CAN_F9FB2_FFDB1_Msk (0x1U << CAN_F9FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F9FB2_FFDB1 CAN_F9FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F9FB2_FFDB2_Pos (2U) +#define CAN_F9FB2_FFDB2_Msk (0x1U << CAN_F9FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F9FB2_FFDB2 CAN_F9FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F9FB2_FFDB3_Pos (3U) +#define CAN_F9FB2_FFDB3_Msk (0x1U << CAN_F9FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F9FB2_FFDB3 CAN_F9FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F9FB2_FFDB4_Pos (4U) +#define CAN_F9FB2_FFDB4_Msk (0x1U << CAN_F9FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F9FB2_FFDB4 CAN_F9FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F9FB2_FFDB5_Pos (5U) +#define CAN_F9FB2_FFDB5_Msk (0x1U << CAN_F9FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F9FB2_FFDB5 CAN_F9FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F9FB2_FFDB6_Pos (6U) +#define CAN_F9FB2_FFDB6_Msk (0x1U << CAN_F9FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F9FB2_FFDB6 CAN_F9FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F9FB2_FFDB7_Pos (7U) +#define CAN_F9FB2_FFDB7_Msk (0x1U << CAN_F9FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F9FB2_FFDB7 CAN_F9FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F9FB2_FFDB8_Pos (8U) +#define CAN_F9FB2_FFDB8_Msk (0x1U << CAN_F9FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F9FB2_FFDB8 CAN_F9FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F9FB2_FFDB9_Pos (9U) +#define CAN_F9FB2_FFDB9_Msk (0x1U << CAN_F9FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F9FB2_FFDB9 CAN_F9FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F9FB2_FFDB10_Pos (10U) +#define CAN_F9FB2_FFDB10_Msk (0x1U << CAN_F9FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F9FB2_FFDB10 CAN_F9FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F9FB2_FFDB11_Pos (11U) +#define CAN_F9FB2_FFDB11_Msk (0x1U << CAN_F9FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F9FB2_FFDB11 CAN_F9FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F9FB2_FFDB12_Pos (12U) +#define CAN_F9FB2_FFDB12_Msk (0x1U << CAN_F9FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F9FB2_FFDB12 CAN_F9FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F9FB2_FFDB13_Pos (13U) +#define CAN_F9FB2_FFDB13_Msk (0x1U << CAN_F9FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F9FB2_FFDB13 CAN_F9FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F9FB2_FFDB14_Pos (14U) +#define CAN_F9FB2_FFDB14_Msk (0x1U << CAN_F9FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F9FB2_FFDB14 CAN_F9FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F9FB2_FFDB15_Pos (15U) +#define CAN_F9FB2_FFDB15_Msk (0x1U << CAN_F9FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F9FB2_FFDB15 CAN_F9FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F9FB2_FFDB16_Pos (16U) +#define CAN_F9FB2_FFDB16_Msk (0x1U << CAN_F9FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F9FB2_FFDB16 CAN_F9FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F9FB2_FFDB17_Pos (17U) +#define CAN_F9FB2_FFDB17_Msk (0x1U << CAN_F9FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F9FB2_FFDB17 CAN_F9FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F9FB2_FFDB18_Pos (18U) +#define CAN_F9FB2_FFDB18_Msk (0x1U << CAN_F9FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F9FB2_FFDB18 CAN_F9FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F9FB2_FFDB19_Pos (19U) +#define CAN_F9FB2_FFDB19_Msk (0x1U << CAN_F9FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F9FB2_FFDB19 CAN_F9FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F9FB2_FFDB20_Pos (20U) +#define CAN_F9FB2_FFDB20_Msk (0x1U << CAN_F9FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F9FB2_FFDB20 CAN_F9FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F9FB2_FFDB21_Pos (21U) +#define CAN_F9FB2_FFDB21_Msk (0x1U << CAN_F9FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F9FB2_FFDB21 CAN_F9FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F9FB2_FFDB22_Pos (22U) +#define CAN_F9FB2_FFDB22_Msk (0x1U << CAN_F9FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F9FB2_FFDB22 CAN_F9FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F9FB2_FFDB23_Pos (23U) +#define CAN_F9FB2_FFDB23_Msk (0x1U << CAN_F9FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F9FB2_FFDB23 CAN_F9FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F9FB2_FFDB24_Pos (24U) +#define CAN_F9FB2_FFDB24_Msk (0x1U << CAN_F9FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F9FB2_FFDB24 CAN_F9FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F9FB2_FFDB25_Pos (25U) +#define CAN_F9FB2_FFDB25_Msk (0x1U << CAN_F9FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F9FB2_FFDB25 CAN_F9FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F9FB2_FFDB26_Pos (26U) +#define CAN_F9FB2_FFDB26_Msk (0x1U << CAN_F9FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F9FB2_FFDB26 CAN_F9FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F9FB2_FFDB27_Pos (27U) +#define CAN_F9FB2_FFDB27_Msk (0x1U << CAN_F9FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F9FB2_FFDB27 CAN_F9FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F9FB2_FFDB28_Pos (28U) +#define CAN_F9FB2_FFDB28_Msk (0x1U << CAN_F9FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F9FB2_FFDB28 CAN_F9FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F9FB2_FFDB29_Pos (29U) +#define CAN_F9FB2_FFDB29_Msk (0x1U << CAN_F9FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F9FB2_FFDB29 CAN_F9FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F9FB2_FFDB30_Pos (30U) +#define CAN_F9FB2_FFDB30_Msk (0x1U << CAN_F9FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F9FB2_FFDB30 CAN_F9FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F9FB2_FFDB31_Pos (31U) +#define CAN_F9FB2_FFDB31_Msk (0x1U << CAN_F9FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F9FB2_FFDB31 CAN_F9FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F10FB2 register ******************/ +#define CAN_F10FB2_FFDB0_Pos (0U) +#define CAN_F10FB2_FFDB0_Msk (0x1U << CAN_F10FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F10FB2_FFDB0 CAN_F10FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F10FB2_FFDB1_Pos (1U) +#define CAN_F10FB2_FFDB1_Msk (0x1U << CAN_F10FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F10FB2_FFDB1 CAN_F10FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F10FB2_FFDB2_Pos (2U) +#define CAN_F10FB2_FFDB2_Msk (0x1U << CAN_F10FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F10FB2_FFDB2 CAN_F10FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F10FB2_FFDB3_Pos (3U) +#define CAN_F10FB2_FFDB3_Msk (0x1U << CAN_F10FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F10FB2_FFDB3 CAN_F10FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F10FB2_FFDB4_Pos (4U) +#define CAN_F10FB2_FFDB4_Msk (0x1U << CAN_F10FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F10FB2_FFDB4 CAN_F10FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F10FB2_FFDB5_Pos (5U) +#define CAN_F10FB2_FFDB5_Msk (0x1U << CAN_F10FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F10FB2_FFDB5 CAN_F10FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F10FB2_FFDB6_Pos (6U) +#define CAN_F10FB2_FFDB6_Msk (0x1U << CAN_F10FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F10FB2_FFDB6 CAN_F10FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F10FB2_FFDB7_Pos (7U) +#define CAN_F10FB2_FFDB7_Msk (0x1U << CAN_F10FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F10FB2_FFDB7 CAN_F10FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F10FB2_FFDB8_Pos (8U) +#define CAN_F10FB2_FFDB8_Msk (0x1U << CAN_F10FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F10FB2_FFDB8 CAN_F10FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F10FB2_FFDB9_Pos (9U) +#define CAN_F10FB2_FFDB9_Msk (0x1U << CAN_F10FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F10FB2_FFDB9 CAN_F10FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F10FB2_FFDB10_Pos (10U) +#define CAN_F10FB2_FFDB10_Msk (0x1U << CAN_F10FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F10FB2_FFDB10 CAN_F10FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F10FB2_FFDB11_Pos (11U) +#define CAN_F10FB2_FFDB11_Msk (0x1U << CAN_F10FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F10FB2_FFDB11 CAN_F10FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F10FB2_FFDB12_Pos (12U) +#define CAN_F10FB2_FFDB12_Msk (0x1U << CAN_F10FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F10FB2_FFDB12 CAN_F10FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F10FB2_FFDB13_Pos (13U) +#define CAN_F10FB2_FFDB13_Msk (0x1U << CAN_F10FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F10FB2_FFDB13 CAN_F10FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F10FB2_FFDB14_Pos (14U) +#define CAN_F10FB2_FFDB14_Msk (0x1U << CAN_F10FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F10FB2_FFDB14 CAN_F10FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F10FB2_FFDB15_Pos (15U) +#define CAN_F10FB2_FFDB15_Msk (0x1U << CAN_F10FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F10FB2_FFDB15 CAN_F10FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F10FB2_FFDB16_Pos (16U) +#define CAN_F10FB2_FFDB16_Msk (0x1U << CAN_F10FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F10FB2_FFDB16 CAN_F10FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F10FB2_FFDB17_Pos (17U) +#define CAN_F10FB2_FFDB17_Msk (0x1U << CAN_F10FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F10FB2_FFDB17 CAN_F10FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F10FB2_FFDB18_Pos (18U) +#define CAN_F10FB2_FFDB18_Msk (0x1U << CAN_F10FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F10FB2_FFDB18 CAN_F10FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F10FB2_FFDB19_Pos (19U) +#define CAN_F10FB2_FFDB19_Msk (0x1U << CAN_F10FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F10FB2_FFDB19 CAN_F10FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F10FB2_FFDB20_Pos (20U) +#define CAN_F10FB2_FFDB20_Msk (0x1U << CAN_F10FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F10FB2_FFDB20 CAN_F10FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F10FB2_FFDB21_Pos (21U) +#define CAN_F10FB2_FFDB21_Msk (0x1U << CAN_F10FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F10FB2_FFDB21 CAN_F10FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F10FB2_FFDB22_Pos (22U) +#define CAN_F10FB2_FFDB22_Msk (0x1U << CAN_F10FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F10FB2_FFDB22 CAN_F10FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F10FB2_FFDB23_Pos (23U) +#define CAN_F10FB2_FFDB23_Msk (0x1U << CAN_F10FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F10FB2_FFDB23 CAN_F10FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F10FB2_FFDB24_Pos (24U) +#define CAN_F10FB2_FFDB24_Msk (0x1U << CAN_F10FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F10FB2_FFDB24 CAN_F10FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F10FB2_FFDB25_Pos (25U) +#define CAN_F10FB2_FFDB25_Msk (0x1U << CAN_F10FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F10FB2_FFDB25 CAN_F10FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F10FB2_FFDB26_Pos (26U) +#define CAN_F10FB2_FFDB26_Msk (0x1U << CAN_F10FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F10FB2_FFDB26 CAN_F10FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F10FB2_FFDB27_Pos (27U) +#define CAN_F10FB2_FFDB27_Msk (0x1U << CAN_F10FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F10FB2_FFDB27 CAN_F10FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F10FB2_FFDB28_Pos (28U) +#define CAN_F10FB2_FFDB28_Msk (0x1U << CAN_F10FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F10FB2_FFDB28 CAN_F10FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F10FB2_FFDB29_Pos (29U) +#define CAN_F10FB2_FFDB29_Msk (0x1U << CAN_F10FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F10FB2_FFDB29 CAN_F10FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F10FB2_FFDB30_Pos (30U) +#define CAN_F10FB2_FFDB30_Msk (0x1U << CAN_F10FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F10FB2_FFDB30 CAN_F10FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F10FB2_FFDB31_Pos (31U) +#define CAN_F10FB2_FFDB31_Msk (0x1U << CAN_F10FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F10FB2_FFDB31 CAN_F10FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F11FB2 register ******************/ +#define CAN_F11FB2_FFDB0_Pos (0U) +#define CAN_F11FB2_FFDB0_Msk (0x1U << CAN_F11FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F11FB2_FFDB0 CAN_F11FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F11FB2_FFDB1_Pos (1U) +#define CAN_F11FB2_FFDB1_Msk (0x1U << CAN_F11FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F11FB2_FFDB1 CAN_F11FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F11FB2_FFDB2_Pos (2U) +#define CAN_F11FB2_FFDB2_Msk (0x1U << CAN_F11FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F11FB2_FFDB2 CAN_F11FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F11FB2_FFDB3_Pos (3U) +#define CAN_F11FB2_FFDB3_Msk (0x1U << CAN_F11FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F11FB2_FFDB3 CAN_F11FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F11FB2_FFDB4_Pos (4U) +#define CAN_F11FB2_FFDB4_Msk (0x1U << CAN_F11FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F11FB2_FFDB4 CAN_F11FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F11FB2_FFDB5_Pos (5U) +#define CAN_F11FB2_FFDB5_Msk (0x1U << CAN_F11FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F11FB2_FFDB5 CAN_F11FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F11FB2_FFDB6_Pos (6U) +#define CAN_F11FB2_FFDB6_Msk (0x1U << CAN_F11FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F11FB2_FFDB6 CAN_F11FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F11FB2_FFDB7_Pos (7U) +#define CAN_F11FB2_FFDB7_Msk (0x1U << CAN_F11FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F11FB2_FFDB7 CAN_F11FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F11FB2_FFDB8_Pos (8U) +#define CAN_F11FB2_FFDB8_Msk (0x1U << CAN_F11FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F11FB2_FFDB8 CAN_F11FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F11FB2_FFDB9_Pos (9U) +#define CAN_F11FB2_FFDB9_Msk (0x1U << CAN_F11FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F11FB2_FFDB9 CAN_F11FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F11FB2_FFDB10_Pos (10U) +#define CAN_F11FB2_FFDB10_Msk (0x1U << CAN_F11FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F11FB2_FFDB10 CAN_F11FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F11FB2_FFDB11_Pos (11U) +#define CAN_F11FB2_FFDB11_Msk (0x1U << CAN_F11FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F11FB2_FFDB11 CAN_F11FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F11FB2_FFDB12_Pos (12U) +#define CAN_F11FB2_FFDB12_Msk (0x1U << CAN_F11FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F11FB2_FFDB12 CAN_F11FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F11FB2_FFDB13_Pos (13U) +#define CAN_F11FB2_FFDB13_Msk (0x1U << CAN_F11FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F11FB2_FFDB13 CAN_F11FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F11FB2_FFDB14_Pos (14U) +#define CAN_F11FB2_FFDB14_Msk (0x1U << CAN_F11FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F11FB2_FFDB14 CAN_F11FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F11FB2_FFDB15_Pos (15U) +#define CAN_F11FB2_FFDB15_Msk (0x1U << CAN_F11FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F11FB2_FFDB15 CAN_F11FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F11FB2_FFDB16_Pos (16U) +#define CAN_F11FB2_FFDB16_Msk (0x1U << CAN_F11FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F11FB2_FFDB16 CAN_F11FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F11FB2_FFDB17_Pos (17U) +#define CAN_F11FB2_FFDB17_Msk (0x1U << CAN_F11FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F11FB2_FFDB17 CAN_F11FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F11FB2_FFDB18_Pos (18U) +#define CAN_F11FB2_FFDB18_Msk (0x1U << CAN_F11FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F11FB2_FFDB18 CAN_F11FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F11FB2_FFDB19_Pos (19U) +#define CAN_F11FB2_FFDB19_Msk (0x1U << CAN_F11FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F11FB2_FFDB19 CAN_F11FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F11FB2_FFDB20_Pos (20U) +#define CAN_F11FB2_FFDB20_Msk (0x1U << CAN_F11FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F11FB2_FFDB20 CAN_F11FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F11FB2_FFDB21_Pos (21U) +#define CAN_F11FB2_FFDB21_Msk (0x1U << CAN_F11FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F11FB2_FFDB21 CAN_F11FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F11FB2_FFDB22_Pos (22U) +#define CAN_F11FB2_FFDB22_Msk (0x1U << CAN_F11FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F11FB2_FFDB22 CAN_F11FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F11FB2_FFDB23_Pos (23U) +#define CAN_F11FB2_FFDB23_Msk (0x1U << CAN_F11FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F11FB2_FFDB23 CAN_F11FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F11FB2_FFDB24_Pos (24U) +#define CAN_F11FB2_FFDB24_Msk (0x1U << CAN_F11FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F11FB2_FFDB24 CAN_F11FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F11FB2_FFDB25_Pos (25U) +#define CAN_F11FB2_FFDB25_Msk (0x1U << CAN_F11FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F11FB2_FFDB25 CAN_F11FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F11FB2_FFDB26_Pos (26U) +#define CAN_F11FB2_FFDB26_Msk (0x1U << CAN_F11FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F11FB2_FFDB26 CAN_F11FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F11FB2_FFDB27_Pos (27U) +#define CAN_F11FB2_FFDB27_Msk (0x1U << CAN_F11FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F11FB2_FFDB27 CAN_F11FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F11FB2_FFDB28_Pos (28U) +#define CAN_F11FB2_FFDB28_Msk (0x1U << CAN_F11FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F11FB2_FFDB28 CAN_F11FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F11FB2_FFDB29_Pos (29U) +#define CAN_F11FB2_FFDB29_Msk (0x1U << CAN_F11FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F11FB2_FFDB29 CAN_F11FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F11FB2_FFDB30_Pos (30U) +#define CAN_F11FB2_FFDB30_Msk (0x1U << CAN_F11FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F11FB2_FFDB30 CAN_F11FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F11FB2_FFDB31_Pos (31U) +#define CAN_F11FB2_FFDB31_Msk (0x1U << CAN_F11FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F11FB2_FFDB31 CAN_F11FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F12FB2 register ******************/ +#define CAN_F12FB2_FFDB0_Pos (0U) +#define CAN_F12FB2_FFDB0_Msk (0x1U << CAN_F12FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F12FB2_FFDB0 CAN_F12FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F12FB2_FFDB1_Pos (1U) +#define CAN_F12FB2_FFDB1_Msk (0x1U << CAN_F12FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F12FB2_FFDB1 CAN_F12FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F12FB2_FFDB2_Pos (2U) +#define CAN_F12FB2_FFDB2_Msk (0x1U << CAN_F12FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F12FB2_FFDB2 CAN_F12FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F12FB2_FFDB3_Pos (3U) +#define CAN_F12FB2_FFDB3_Msk (0x1U << CAN_F12FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F12FB2_FFDB3 CAN_F12FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F12FB2_FFDB4_Pos (4U) +#define CAN_F12FB2_FFDB4_Msk (0x1U << CAN_F12FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F12FB2_FFDB4 CAN_F12FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F12FB2_FFDB5_Pos (5U) +#define CAN_F12FB2_FFDB5_Msk (0x1U << CAN_F12FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F12FB2_FFDB5 CAN_F12FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F12FB2_FFDB6_Pos (6U) +#define CAN_F12FB2_FFDB6_Msk (0x1U << CAN_F12FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F12FB2_FFDB6 CAN_F12FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F12FB2_FFDB7_Pos (7U) +#define CAN_F12FB2_FFDB7_Msk (0x1U << CAN_F12FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F12FB2_FFDB7 CAN_F12FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F12FB2_FFDB8_Pos (8U) +#define CAN_F12FB2_FFDB8_Msk (0x1U << CAN_F12FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F12FB2_FFDB8 CAN_F12FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F12FB2_FFDB9_Pos (9U) +#define CAN_F12FB2_FFDB9_Msk (0x1U << CAN_F12FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F12FB2_FFDB9 CAN_F12FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F12FB2_FFDB10_Pos (10U) +#define CAN_F12FB2_FFDB10_Msk (0x1U << CAN_F12FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F12FB2_FFDB10 CAN_F12FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F12FB2_FFDB11_Pos (11U) +#define CAN_F12FB2_FFDB11_Msk (0x1U << CAN_F12FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F12FB2_FFDB11 CAN_F12FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F12FB2_FFDB12_Pos (12U) +#define CAN_F12FB2_FFDB12_Msk (0x1U << CAN_F12FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F12FB2_FFDB12 CAN_F12FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F12FB2_FFDB13_Pos (13U) +#define CAN_F12FB2_FFDB13_Msk (0x1U << CAN_F12FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F12FB2_FFDB13 CAN_F12FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F12FB2_FFDB14_Pos (14U) +#define CAN_F12FB2_FFDB14_Msk (0x1U << CAN_F12FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F12FB2_FFDB14 CAN_F12FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F12FB2_FFDB15_Pos (15U) +#define CAN_F12FB2_FFDB15_Msk (0x1U << CAN_F12FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F12FB2_FFDB15 CAN_F12FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F12FB2_FFDB16_Pos (16U) +#define CAN_F12FB2_FFDB16_Msk (0x1U << CAN_F12FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F12FB2_FFDB16 CAN_F12FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F12FB2_FFDB17_Pos (17U) +#define CAN_F12FB2_FFDB17_Msk (0x1U << CAN_F12FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F12FB2_FFDB17 CAN_F12FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F12FB2_FFDB18_Pos (18U) +#define CAN_F12FB2_FFDB18_Msk (0x1U << CAN_F12FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F12FB2_FFDB18 CAN_F12FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F12FB2_FFDB19_Pos (19U) +#define CAN_F12FB2_FFDB19_Msk (0x1U << CAN_F12FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F12FB2_FFDB19 CAN_F12FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F12FB2_FFDB20_Pos (20U) +#define CAN_F12FB2_FFDB20_Msk (0x1U << CAN_F12FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F12FB2_FFDB20 CAN_F12FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F12FB2_FFDB21_Pos (21U) +#define CAN_F12FB2_FFDB21_Msk (0x1U << CAN_F12FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F12FB2_FFDB21 CAN_F12FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F12FB2_FFDB22_Pos (22U) +#define CAN_F12FB2_FFDB22_Msk (0x1U << CAN_F12FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F12FB2_FFDB22 CAN_F12FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F12FB2_FFDB23_Pos (23U) +#define CAN_F12FB2_FFDB23_Msk (0x1U << CAN_F12FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F12FB2_FFDB23 CAN_F12FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F12FB2_FFDB24_Pos (24U) +#define CAN_F12FB2_FFDB24_Msk (0x1U << CAN_F12FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F12FB2_FFDB24 CAN_F12FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F12FB2_FFDB25_Pos (25U) +#define CAN_F12FB2_FFDB25_Msk (0x1U << CAN_F12FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F12FB2_FFDB25 CAN_F12FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F12FB2_FFDB26_Pos (26U) +#define CAN_F12FB2_FFDB26_Msk (0x1U << CAN_F12FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F12FB2_FFDB26 CAN_F12FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F12FB2_FFDB27_Pos (27U) +#define CAN_F12FB2_FFDB27_Msk (0x1U << CAN_F12FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F12FB2_FFDB27 CAN_F12FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F12FB2_FFDB28_Pos (28U) +#define CAN_F12FB2_FFDB28_Msk (0x1U << CAN_F12FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F12FB2_FFDB28 CAN_F12FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F12FB2_FFDB29_Pos (29U) +#define CAN_F12FB2_FFDB29_Msk (0x1U << CAN_F12FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F12FB2_FFDB29 CAN_F12FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F12FB2_FFDB30_Pos (30U) +#define CAN_F12FB2_FFDB30_Msk (0x1U << CAN_F12FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F12FB2_FFDB30 CAN_F12FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F12FB2_FFDB31_Pos (31U) +#define CAN_F12FB2_FFDB31_Msk (0x1U << CAN_F12FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F12FB2_FFDB31 CAN_F12FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/****************** Bit definition for CAN_F13FB2 register ******************/ +#define CAN_F13FB2_FFDB0_Pos (0U) +#define CAN_F13FB2_FFDB0_Msk (0x1U << CAN_F13FB2_FFDB0_Pos) /*!< 0x00000001 */ +#define CAN_F13FB2_FFDB0 CAN_F13FB2_FFDB0_Msk /*!< Filter data bit 0 */ +#define CAN_F13FB2_FFDB1_Pos (1U) +#define CAN_F13FB2_FFDB1_Msk (0x1U << CAN_F13FB2_FFDB1_Pos) /*!< 0x00000002 */ +#define CAN_F13FB2_FFDB1 CAN_F13FB2_FFDB1_Msk /*!< Filter data bit 1 */ +#define CAN_F13FB2_FFDB2_Pos (2U) +#define CAN_F13FB2_FFDB2_Msk (0x1U << CAN_F13FB2_FFDB2_Pos) /*!< 0x00000004 */ +#define CAN_F13FB2_FFDB2 CAN_F13FB2_FFDB2_Msk /*!< Filter data bit 2 */ +#define CAN_F13FB2_FFDB3_Pos (3U) +#define CAN_F13FB2_FFDB3_Msk (0x1U << CAN_F13FB2_FFDB3_Pos) /*!< 0x00000008 */ +#define CAN_F13FB2_FFDB3 CAN_F13FB2_FFDB3_Msk /*!< Filter data bit 3 */ +#define CAN_F13FB2_FFDB4_Pos (4U) +#define CAN_F13FB2_FFDB4_Msk (0x1U << CAN_F13FB2_FFDB4_Pos) /*!< 0x00000010 */ +#define CAN_F13FB2_FFDB4 CAN_F13FB2_FFDB4_Msk /*!< Filter data bit 4 */ +#define CAN_F13FB2_FFDB5_Pos (5U) +#define CAN_F13FB2_FFDB5_Msk (0x1U << CAN_F13FB2_FFDB5_Pos) /*!< 0x00000020 */ +#define CAN_F13FB2_FFDB5 CAN_F13FB2_FFDB5_Msk /*!< Filter data bit 5 */ +#define CAN_F13FB2_FFDB6_Pos (6U) +#define CAN_F13FB2_FFDB6_Msk (0x1U << CAN_F13FB2_FFDB6_Pos) /*!< 0x00000040 */ +#define CAN_F13FB2_FFDB6 CAN_F13FB2_FFDB6_Msk /*!< Filter data bit 6 */ +#define CAN_F13FB2_FFDB7_Pos (7U) +#define CAN_F13FB2_FFDB7_Msk (0x1U << CAN_F13FB2_FFDB7_Pos) /*!< 0x00000080 */ +#define CAN_F13FB2_FFDB7 CAN_F13FB2_FFDB7_Msk /*!< Filter data bit 7 */ +#define CAN_F13FB2_FFDB8_Pos (8U) +#define CAN_F13FB2_FFDB8_Msk (0x1U << CAN_F13FB2_FFDB8_Pos) /*!< 0x00000100 */ +#define CAN_F13FB2_FFDB8 CAN_F13FB2_FFDB8_Msk /*!< Filter data bit 8 */ +#define CAN_F13FB2_FFDB9_Pos (9U) +#define CAN_F13FB2_FFDB9_Msk (0x1U << CAN_F13FB2_FFDB9_Pos) /*!< 0x00000200 */ +#define CAN_F13FB2_FFDB9 CAN_F13FB2_FFDB9_Msk /*!< Filter data bit 9 */ +#define CAN_F13FB2_FFDB10_Pos (10U) +#define CAN_F13FB2_FFDB10_Msk (0x1U << CAN_F13FB2_FFDB10_Pos) /*!< 0x00000400 */ +#define CAN_F13FB2_FFDB10 CAN_F13FB2_FFDB10_Msk /*!< Filter data bit 10 */ +#define CAN_F13FB2_FFDB11_Pos (11U) +#define CAN_F13FB2_FFDB11_Msk (0x1U << CAN_F13FB2_FFDB11_Pos) /*!< 0x00000800 */ +#define CAN_F13FB2_FFDB11 CAN_F13FB2_FFDB11_Msk /*!< Filter data bit 11 */ +#define CAN_F13FB2_FFDB12_Pos (12U) +#define CAN_F13FB2_FFDB12_Msk (0x1U << CAN_F13FB2_FFDB12_Pos) /*!< 0x00001000 */ +#define CAN_F13FB2_FFDB12 CAN_F13FB2_FFDB12_Msk /*!< Filter data bit 12 */ +#define CAN_F13FB2_FFDB13_Pos (13U) +#define CAN_F13FB2_FFDB13_Msk (0x1U << CAN_F13FB2_FFDB13_Pos) /*!< 0x00002000 */ +#define CAN_F13FB2_FFDB13 CAN_F13FB2_FFDB13_Msk /*!< Filter data bit 13 */ +#define CAN_F13FB2_FFDB14_Pos (14U) +#define CAN_F13FB2_FFDB14_Msk (0x1U << CAN_F13FB2_FFDB14_Pos) /*!< 0x00004000 */ +#define CAN_F13FB2_FFDB14 CAN_F13FB2_FFDB14_Msk /*!< Filter data bit 14 */ +#define CAN_F13FB2_FFDB15_Pos (15U) +#define CAN_F13FB2_FFDB15_Msk (0x1U << CAN_F13FB2_FFDB15_Pos) /*!< 0x00008000 */ +#define CAN_F13FB2_FFDB15 CAN_F13FB2_FFDB15_Msk /*!< Filter data bit 15 */ +#define CAN_F13FB2_FFDB16_Pos (16U) +#define CAN_F13FB2_FFDB16_Msk (0x1U << CAN_F13FB2_FFDB16_Pos) /*!< 0x00010000 */ +#define CAN_F13FB2_FFDB16 CAN_F13FB2_FFDB16_Msk /*!< Filter data bit 16 */ +#define CAN_F13FB2_FFDB17_Pos (17U) +#define CAN_F13FB2_FFDB17_Msk (0x1U << CAN_F13FB2_FFDB17_Pos) /*!< 0x00020000 */ +#define CAN_F13FB2_FFDB17 CAN_F13FB2_FFDB17_Msk /*!< Filter data bit 17 */ +#define CAN_F13FB2_FFDB18_Pos (18U) +#define CAN_F13FB2_FFDB18_Msk (0x1U << CAN_F13FB2_FFDB18_Pos) /*!< 0x00040000 */ +#define CAN_F13FB2_FFDB18 CAN_F13FB2_FFDB18_Msk /*!< Filter data bit 18 */ +#define CAN_F13FB2_FFDB19_Pos (19U) +#define CAN_F13FB2_FFDB19_Msk (0x1U << CAN_F13FB2_FFDB19_Pos) /*!< 0x00080000 */ +#define CAN_F13FB2_FFDB19 CAN_F13FB2_FFDB19_Msk /*!< Filter data bit 19 */ +#define CAN_F13FB2_FFDB20_Pos (20U) +#define CAN_F13FB2_FFDB20_Msk (0x1U << CAN_F13FB2_FFDB20_Pos) /*!< 0x00100000 */ +#define CAN_F13FB2_FFDB20 CAN_F13FB2_FFDB20_Msk /*!< Filter data bit 20 */ +#define CAN_F13FB2_FFDB21_Pos (21U) +#define CAN_F13FB2_FFDB21_Msk (0x1U << CAN_F13FB2_FFDB21_Pos) /*!< 0x00200000 */ +#define CAN_F13FB2_FFDB21 CAN_F13FB2_FFDB21_Msk /*!< Filter data bit 21 */ +#define CAN_F13FB2_FFDB22_Pos (22U) +#define CAN_F13FB2_FFDB22_Msk (0x1U << CAN_F13FB2_FFDB22_Pos) /*!< 0x00400000 */ +#define CAN_F13FB2_FFDB22 CAN_F13FB2_FFDB22_Msk /*!< Filter data bit 22 */ +#define CAN_F13FB2_FFDB23_Pos (23U) +#define CAN_F13FB2_FFDB23_Msk (0x1U << CAN_F13FB2_FFDB23_Pos) /*!< 0x00800000 */ +#define CAN_F13FB2_FFDB23 CAN_F13FB2_FFDB23_Msk /*!< Filter data bit 23 */ +#define CAN_F13FB2_FFDB24_Pos (24U) +#define CAN_F13FB2_FFDB24_Msk (0x1U << CAN_F13FB2_FFDB24_Pos) /*!< 0x01000000 */ +#define CAN_F13FB2_FFDB24 CAN_F13FB2_FFDB24_Msk /*!< Filter data bit 24 */ +#define CAN_F13FB2_FFDB25_Pos (25U) +#define CAN_F13FB2_FFDB25_Msk (0x1U << CAN_F13FB2_FFDB25_Pos) /*!< 0x02000000 */ +#define CAN_F13FB2_FFDB25 CAN_F13FB2_FFDB25_Msk /*!< Filter data bit 25 */ +#define CAN_F13FB2_FFDB26_Pos (26U) +#define CAN_F13FB2_FFDB26_Msk (0x1U << CAN_F13FB2_FFDB26_Pos) /*!< 0x04000000 */ +#define CAN_F13FB2_FFDB26 CAN_F13FB2_FFDB26_Msk /*!< Filter data bit 26 */ +#define CAN_F13FB2_FFDB27_Pos (27U) +#define CAN_F13FB2_FFDB27_Msk (0x1U << CAN_F13FB2_FFDB27_Pos) /*!< 0x08000000 */ +#define CAN_F13FB2_FFDB27 CAN_F13FB2_FFDB27_Msk /*!< Filter data bit 27 */ +#define CAN_F13FB2_FFDB28_Pos (28U) +#define CAN_F13FB2_FFDB28_Msk (0x1U << CAN_F13FB2_FFDB28_Pos) /*!< 0x10000000 */ +#define CAN_F13FB2_FFDB28 CAN_F13FB2_FFDB28_Msk /*!< Filter data bit 28 */ +#define CAN_F13FB2_FFDB29_Pos (29U) +#define CAN_F13FB2_FFDB29_Msk (0x1U << CAN_F13FB2_FFDB29_Pos) /*!< 0x20000000 */ +#define CAN_F13FB2_FFDB29 CAN_F13FB2_FFDB29_Msk /*!< Filter data bit 29 */ +#define CAN_F13FB2_FFDB30_Pos (30U) +#define CAN_F13FB2_FFDB30_Msk (0x1U << CAN_F13FB2_FFDB30_Pos) /*!< 0x40000000 */ +#define CAN_F13FB2_FFDB30 CAN_F13FB2_FFDB30_Msk /*!< Filter data bit 30 */ +#define CAN_F13FB2_FFDB31_Pos (31U) +#define CAN_F13FB2_FFDB31_Msk (0x1U << CAN_F13FB2_FFDB31_Pos) /*!< 0x80000000 */ +#define CAN_F13FB2_FFDB31 CAN_F13FB2_FFDB31_Msk /*!< Filter data bit 31 */ + +/******************************************************************************/ +/* */ +/* HICK auto clock calibration (ACC) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for ACC_STS register ********************/ +#define ACC_STS_CALRDY_Pos (0U) +#define ACC_STS_CALRDY_Msk (0x1U << ACC_STS_CALRDY_Pos) /*!< 0x00000001 */ +#define ACC_STS_CALRDY ACC_STS_CALRDY_Msk /*!< Internal high-speed clock calibration ready */ +#define ACC_STS_RSLOST_Pos (1U) +#define ACC_STS_RSLOST_Msk (0x1U << ACC_STS_RSLOST_Pos) /*!< 0x00000002 */ +#define ACC_STS_RSLOST ACC_STS_RSLOST_Msk /*!< Reference signal lost */ + +/****************** Bit definition for ACC_CTRL1 register *******************/ +#define ACC_CTRL1_CALON_Pos (0U) +#define ACC_CTRL1_CALON_Msk (0x1U << ACC_CTRL1_CALON_Pos) /*!< 0x00000001 */ +#define ACC_CTRL1_CALON ACC_CTRL1_CALON_Msk /*!< Calibration on */ +#define ACC_CTRL1_ENTRIM_Pos (1U) +#define ACC_CTRL1_ENTRIM_Msk (0x1U << ACC_CTRL1_ENTRIM_Pos) /*!< 0x00000002 */ +#define ACC_CTRL1_ENTRIM ACC_CTRL1_ENTRIM_Msk /*!< Enable trim */ +#define ACC_CTRL1_EIEN_Pos (4U) +#define ACC_CTRL1_EIEN_Msk (0x1U << ACC_CTRL1_EIEN_Pos) /*!< 0x00000010 */ +#define ACC_CTRL1_EIEN ACC_CTRL1_EIEN_Msk /*!< RSLOST error interrupt enable */ +#define ACC_CTRL1_CALRDYIEN_Pos (5U) +#define ACC_CTRL1_CALRDYIEN_Msk (0x1U << ACC_CTRL1_CALRDYIEN_Pos) /*!< 0x00000020 */ +#define ACC_CTRL1_CALRDYIEN ACC_CTRL1_CALRDYIEN_Msk /*!< CALRDY interrupt enable */ +#define ACC_CTRL1_STEP_Pos (8U) +#define ACC_CTRL1_STEP_Msk (0xFU << ACC_CTRL1_STEP_Pos) /*!< 0x00000F00 */ +#define ACC_CTRL1_STEP ACC_CTRL1_STEP_Msk /*!< Calibrated step */ + +/****************** Bit definition for ACC_CTRL2 register *******************/ +#define ACC_CTRL2_HICKCAL_Pos (0U) +#define ACC_CTRL2_HICKCAL_Msk (0xFFU << ACC_CTRL2_HICKCAL_Pos) /*!< 0x000000FF */ +#define ACC_CTRL2_HICKCAL ACC_CTRL2_HICKCAL_Msk /*!< Internal high-speed auto clock calibration */ +#define ACC_CTRL2_HICKTRIM_Pos (8U) +#define ACC_CTRL2_HICKTRIM_Msk (0x3FU << ACC_CTRL2_HICKTRIM_Pos) /*!< 0x00003F00 */ +#define ACC_CTRL2_HICKTRIM ACC_CTRL2_HICKTRIM_Msk /*!< Internal high-speed auto clock trimming */ + +/******************* Bit definition for ACC_CP1 register ********************/ +#define ACC_CP1_C1_Pos (0U) +#define ACC_CP1_C1_Msk (0xFFFFU << ACC_CP1_C1_Pos) /*!< 0x0000FFFF */ +#define ACC_CP1_C1 ACC_CP1_C1_Msk /*!< Compare 1 */ + +/******************* Bit definition for ACC_CP2 register ********************/ +#define ACC_CP2_C2_Pos (0U) +#define ACC_CP2_C2_Msk (0xFFFFU << ACC_CP2_C2_Pos) /*!< 0x0000FFFF */ +#define ACC_CP2_C2 ACC_CP2_C2_Msk /*!< Compare 2 */ + +/******************* Bit definition for ACC_CP3 register ********************/ +#define ACC_CP3_C3_Pos (0U) +#define ACC_CP3_C3_Msk (0xFFFFU << ACC_CP3_C3_Pos) /*!< 0x0000FFFF */ +#define ACC_CP3_C3 ACC_CP3_C3_Msk /*!< Compare 3 */ + +/******************************************************************************/ +/* */ +/* Quad-SPI interface (QSPI) */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for QSPI_CMD_W0 register ******************/ +#define QSPI_CMD_W0_SPIADR_Pos (0U) +#define QSPI_CMD_W0_SPIADR_Msk (0xFFFFFFFFU << QSPI_CMD_W0_SPIADR_Pos) /*!< 0xFFFFFFFF */ +#define QSPI_CMD_W0_SPIADR QSPI_CMD_W0_SPIADR_Msk /*!< SPI Flash address */ + +/***************** Bit definition for QSPI_CMD_W1 register ******************/ +/*!< ADRLEN congiguration */ +#define QSPI_CMD_W1_ADRLEN_Pos (0U) +#define QSPI_CMD_W1_ADRLEN_Msk (0x7U << QSPI_CMD_W1_ADRLEN_Pos) /*!< 0x00000007 */ +#define QSPI_CMD_W1_ADRLEN QSPI_CMD_W1_ADRLEN_Msk /*!< ADRLEN[2:0] bits (SPI address length) */ +#define QSPI_CMD_W1_ADRLEN_0 (0x1U << QSPI_CMD_W1_ADRLEN_Pos) /*!< 0x00000001 */ +#define QSPI_CMD_W1_ADRLEN_1 (0x2U << QSPI_CMD_W1_ADRLEN_Pos) /*!< 0x00000002 */ +#define QSPI_CMD_W1_ADRLEN_2 (0x4U << QSPI_CMD_W1_ADRLEN_Pos) /*!< 0x00000004 */ + +#define QSPI_CMD_W1_ADRLEN_NOBYTE 0x00000000U /*!< No address state */ +#define QSPI_CMD_W1_ADRLEN_1BYTE 0x00000001U /*!< 1-byte address */ +#define QSPI_CMD_W1_ADRLEN_2BYTE 0x00000002U /*!< 2-byte address */ +#define QSPI_CMD_W1_ADRLEN_3BYTE 0x00000003U /*!< 3-byte address */ +#define QSPI_CMD_W1_ADRLEN_4BYTE 0x00000004U /*!< 4-byte address */ + +/*!< DUM2 congiguration */ +#define QSPI_CMD_W1_DUM2_Pos (16U) +#define QSPI_CMD_W1_DUM2_Msk (0xFFU << QSPI_CMD_W1_DUM2_Pos) /*!< 0x00FF0000 */ +#define QSPI_CMD_W1_DUM2 QSPI_CMD_W1_DUM2_Msk /*!< DUM2[7:0] bits (Second dummy state cycle) */ +#define QSPI_CMD_W1_DUM2_0 (0x01U << QSPI_CMD_W1_DUM2_Pos) /*!< 0x00010000 */ +#define QSPI_CMD_W1_DUM2_1 (0x02U << QSPI_CMD_W1_DUM2_Pos) /*!< 0x00020000 */ +#define QSPI_CMD_W1_DUM2_2 (0x04U << QSPI_CMD_W1_DUM2_Pos) /*!< 0x00040000 */ +#define QSPI_CMD_W1_DUM2_3 (0x08U << QSPI_CMD_W1_DUM2_Pos) /*!< 0x00080000 */ +#define QSPI_CMD_W1_DUM2_4 (0x10U << QSPI_CMD_W1_DUM2_Pos) /*!< 0x00100000 */ +#define QSPI_CMD_W1_DUM2_5 (0x20U << QSPI_CMD_W1_DUM2_Pos) /*!< 0x00200000 */ +#define QSPI_CMD_W1_DUM2_6 (0x40U << QSPI_CMD_W1_DUM2_Pos) /*!< 0x00400000 */ +#define QSPI_CMD_W1_DUM2_7 (0x80U << QSPI_CMD_W1_DUM2_Pos) /*!< 0x00800000 */ + +/*!< INSLEN congiguration */ +#define QSPI_CMD_W1_INSLEN_Pos (24U) +#define QSPI_CMD_W1_INSLEN_Msk (0x3U << QSPI_CMD_W1_INSLEN_Pos) /*!< 0x03000000 */ +#define QSPI_CMD_W1_INSLEN QSPI_CMD_W1_INSLEN_Msk /*!< INSLEN[1:0] bits (Instruction code length) */ +#define QSPI_CMD_W1_INSLEN_0 (0x1U << QSPI_CMD_W1_INSLEN_Pos) /*!< 0x01000000 */ +#define QSPI_CMD_W1_INSLEN_1 (0x2U << QSPI_CMD_W1_INSLEN_Pos) /*!< 0x02000000 */ + +#define QSPI_CMD_W1_INSLEN_NOINS 0x00000000U /*!< No instruction code */ +#define QSPI_CMD_W1_INSLEN_1INS 0x01000000U /*!< 1-byte instruction code */ +#define QSPI_CMD_W1_INSLEN_2INS 0x02000000U /*!< 2-byte instruction code (repeated instruction code) */ + +#define QSPI_CMD_W1_PEMEN_Pos (28U) +#define QSPI_CMD_W1_PEMEN_Msk (0x1U << QSPI_CMD_W1_PEMEN_Pos) /*!< 0x10000000 */ +#define QSPI_CMD_W1_PEMEN QSPI_CMD_W1_PEMEN_Msk /*!< Performance enhanced mode enable */ + +/***************** Bit definition for QSPI_CMD_W2 register ******************/ +#define QSPI_CMD_W2_DCNT_Pos (0U) +#define QSPI_CMD_W2_DCNT_Msk (0xFFFFFFFFU << QSPI_CMD_W2_DCNT_Pos) /*!< 0xFFFFFFFF */ +#define QSPI_CMD_W2_DCNT QSPI_CMD_W2_DCNT_Msk /*!< Read/Write data counter */ + +/***************** Bit definition for QSPI_CMD_W3 register ******************/ +#define QSPI_CMD_W3_WEN_Pos (1U) +#define QSPI_CMD_W3_WEN_Msk (0x1U << QSPI_CMD_W3_WEN_Pos) /*!< 0x00000002 */ +#define QSPI_CMD_W3_WEN QSPI_CMD_W3_WEN_Msk /*!< Write data enable */ +#define QSPI_CMD_W3_RSTSEN_Pos (2U) +#define QSPI_CMD_W3_RSTSEN_Msk (0x1U << QSPI_CMD_W3_RSTSEN_Pos) /*!< 0x00000004 */ +#define QSPI_CMD_W3_RSTSEN QSPI_CMD_W3_RSTSEN_Msk /*!< Read SPI status enable */ +#define QSPI_CMD_W3_RSTSC_Pos (3U) +#define QSPI_CMD_W3_RSTSC_Msk (0x1U << QSPI_CMD_W3_RSTSC_Pos) /*!< 0x00000008 */ +#define QSPI_CMD_W3_RSTSC QSPI_CMD_W3_RSTSC_Msk /*!< Read SPI status configuration */ + +/*!< OPMODE congiguration */ +#define QSPI_CMD_W3_OPMODE_Pos (5U) +#define QSPI_CMD_W3_OPMODE_Msk (0x7U << QSPI_CMD_W3_OPMODE_Pos) /*!< 0x000000E0 */ +#define QSPI_CMD_W3_OPMODE QSPI_CMD_W3_OPMODE_Msk /*!< OPMODE[2:0] bits (SPI Operation mode) */ +#define QSPI_CMD_W3_OPMODE_0 (0x1U << QSPI_CMD_W3_OPMODE_Pos) /*!< 0x00000020 */ +#define QSPI_CMD_W3_OPMODE_1 (0x2U << QSPI_CMD_W3_OPMODE_Pos) /*!< 0x00000040 */ +#define QSPI_CMD_W3_OPMODE_2 (0x4U << QSPI_CMD_W3_OPMODE_Pos) /*!< 0x00000080 */ + +#define QSPI_CMD_W3_OPMODE_SERIAL 0x00000000U /*!< Serial mode (1-1-1) */ +#define QSPI_CMD_W3_OPMODE_DUAL 0x00000020U /*!< Dual-wire mode (1-1-2) */ +#define QSPI_CMD_W3_OPMODE_QUAD 0x00000040U /*!< Quad mode (1-1-4) */ +#define QSPI_CMD_W3_OPMODE_DUALIO 0x00000060U /*!< Dual-wire I/O mode (1-2-2) */ +#define QSPI_CMD_W3_OPMODE_QUADIO 0x00000080U /*!< Quad I/O mode (1-4-4) */ +#define QSPI_CMD_W3_OPMODE_DPI 0x000000A0U /*!< DPI mode (2-2-2) */ +#define QSPI_CMD_W3_OPMODE_QPI 0x000000C0U /*!< QPI mode (4-4-4) */ + +#define QSPI_CMD_W3_PEMOPC_Pos (16U) +#define QSPI_CMD_W3_PEMOPC_Msk (0xFFU << QSPI_CMD_W3_PEMOPC_Pos) /*!< 0x00FF0000 */ +#define QSPI_CMD_W3_PEMOPC QSPI_CMD_W3_PEMOPC_Msk /*!< Performance enhanced mode operation code */ +#define QSPI_CMD_W3_INSC_Pos (24U) +#define QSPI_CMD_W3_INSC_Msk (0xFFU << QSPI_CMD_W3_INSC_Pos) /*!< 0xFF000000 */ +#define QSPI_CMD_W3_INSC QSPI_CMD_W3_INSC_Msk /*!< Instruction code */ + +/****************** Bit definition for QSPI_CTRL register *******************/ +/*!< CLKDIV congiguration */ +#define QSPI_CTRL_CLKDIV_Pos (0U) +#define QSPI_CTRL_CLKDIV_Msk (0x7U << QSPI_CTRL_CLKDIV_Pos) /*!< 0x00000007 */ +#define QSPI_CTRL_CLKDIV QSPI_CTRL_CLKDIV_Msk /*!< CLKDIV[2:0] bits (Clock divider) */ +#define QSPI_CTRL_CLKDIV_0 (0x1U << QSPI_CTRL_CLKDIV_Pos) /*!< 0x00000001 */ +#define QSPI_CTRL_CLKDIV_1 (0x2U << QSPI_CTRL_CLKDIV_Pos) /*!< 0x00000002 */ +#define QSPI_CTRL_CLKDIV_2 (0x4U << QSPI_CTRL_CLKDIV_Pos) /*!< 0x00000004 */ + +#define QSPI_CTRL_CLKDIV_DIV2 0x00000000U /*!< Clock is divided by 2 */ +#define QSPI_CTRL_CLKDIV_DIV4 0x00000001U /*!< Clock is divided by 4 */ +#define QSPI_CTRL_CLKDIV_DIV6 0x00000002U /*!< Clock is divided by 6 */ +#define QSPI_CTRL_CLKDIV_DIV8 0x00000003U /*!< Clock is divided by 8 */ +#define QSPI_CTRL_CLKDIV_DIV3 0x00000004U /*!< Clock is divided by 3 */ +#define QSPI_CTRL_CLKDIV_DIV5 0x00000005U /*!< Clock is divided by 5 */ +#define QSPI_CTRL_CLKDIV_DIV10 0x00000006U /*!< Clock is divided by 10 */ +#define QSPI_CTRL_CLKDIV_DIV12 0x00000007U /*!< Clock is divided by 12 */ + +#define QSPI_CTRL_SCKMODE_Pos (4U) +#define QSPI_CTRL_SCKMODE_Msk (0x1U << QSPI_CTRL_SCKMODE_Pos) /*!< 0x00000010 */ +#define QSPI_CTRL_SCKMODE QSPI_CTRL_SCKMODE_Msk /*!< SCK output mode */ +#define QSPI_CTRL_XIPIDLE_Pos (7U) +#define QSPI_CTRL_XIPIDLE_Msk (0x1U << QSPI_CTRL_XIPIDLE_Pos) /*!< 0x00000080 */ +#define QSPI_CTRL_XIPIDLE QSPI_CTRL_XIPIDLE_Msk /*!< XIP port idle status */ +#define QSPI_CTRL_ABORT_Pos (8U) +#define QSPI_CTRL_ABORT_Msk (0x1U << QSPI_CTRL_ABORT_Pos) /*!< 0x00000100 */ +#define QSPI_CTRL_ABORT QSPI_CTRL_ABORT_Msk /*!< Refresh all commands/FIFOs and reset state machine */ + +/*!< BUSY congiguration */ +#define QSPI_CTRL_BUSY_Pos (16U) +#define QSPI_CTRL_BUSY_Msk (0x7U << QSPI_CTRL_BUSY_Pos) /*!< 0x00070000 */ +#define QSPI_CTRL_BUSY QSPI_CTRL_BUSY_Msk /*!< BUSY[2:0] bits (Busy bit of SPI status) */ +#define QSPI_CTRL_BUSY_0 (0x1U << QSPI_CTRL_BUSY_Pos) /*!< 0x00010000 */ +#define QSPI_CTRL_BUSY_1 (0x2U << QSPI_CTRL_BUSY_Pos) /*!< 0x00020000 */ +#define QSPI_CTRL_BUSY_2 (0x4U << QSPI_CTRL_BUSY_Pos) /*!< 0x00040000 */ + +#define QSPI_CTRL_BUSY_BIT0 0x00000000U /*!< Bit 0 */ +#define QSPI_CTRL_BUSY_BIT1 0x00010000U /*!< Bit 1 */ +#define QSPI_CTRL_BUSY_BIT2 0x00020000U /*!< Bit 2 */ +#define QSPI_CTRL_BUSY_BIT3 0x00030000U /*!< Bit 3 */ +#define QSPI_CTRL_BUSY_BIT4 0x00040000U /*!< Bit 4 */ +#define QSPI_CTRL_BUSY_BIT5 0x00050000U /*!< Bit 5 */ +#define QSPI_CTRL_BUSY_BIT6 0x00060000U /*!< Bit 6 */ +#define QSPI_CTRL_BUSY_BIT7 0x00070000U /*!< Bit 7 */ + +#define QSPI_CTRL_XIPRCMDF_Pos (19U) +#define QSPI_CTRL_XIPRCMDF_Msk (0x1U << QSPI_CTRL_XIPRCMDF_Pos) /*!< 0x00080000 */ +#define QSPI_CTRL_XIPRCMDF QSPI_CTRL_XIPRCMDF_Msk /*!< XIP read command flush */ +#define QSPI_CTRL_XIPSEL_Pos (20U) +#define QSPI_CTRL_XIPSEL_Msk (0x1U << QSPI_CTRL_XIPSEL_Pos) /*!< 0x00100000 */ +#define QSPI_CTRL_XIPSEL QSPI_CTRL_XIPSEL_Msk /*!< XIP port selection */ +#define QSPI_CTRL_KEYEN_Pos (21U) +#define QSPI_CTRL_KEYEN_Msk (0x1U << QSPI_CTRL_KEYEN_Pos) /*!< 0x00200000 */ +#define QSPI_CTRL_KEYEN QSPI_CTRL_KEYEN_Msk /*!< SPI data encryption key enable */ + +/***************** Bit definition for QSPI_FIFOSTS register *****************/ +#define QSPI_FIFOSTS_TXFIFORDY_Pos (0U) +#define QSPI_FIFOSTS_TXFIFORDY_Msk (0x1U << QSPI_FIFOSTS_TXFIFORDY_Pos) /*!< 0x00000001 */ +#define QSPI_FIFOSTS_TXFIFORDY QSPI_FIFOSTS_TXFIFORDY_Msk /*!< TX FIFO ready status */ +#define QSPI_FIFOSTS_RXFIFORDY_Pos (1U) +#define QSPI_FIFOSTS_RXFIFORDY_Msk (0x1U << QSPI_FIFOSTS_RXFIFORDY_Pos) /*!< 0x00000002 */ +#define QSPI_FIFOSTS_RXFIFORDY QSPI_FIFOSTS_RXFIFORDY_Msk /*!< RX FIFO ready status */ + +/****************** Bit definition for QSPI_CTRL2 register ******************/ +#define QSPI_CTRL2_DMAEN_Pos (0U) +#define QSPI_CTRL2_DMAEN_Msk (0x1U << QSPI_CTRL2_DMAEN_Pos) /*!< 0x00000001 */ +#define QSPI_CTRL2_DMAEN QSPI_CTRL2_DMAEN_Msk /*!< DMA enable */ +#define QSPI_CTRL2_CMDIE_Pos (1U) +#define QSPI_CTRL2_CMDIE_Msk (0x1U << QSPI_CTRL2_CMDIE_Pos) /*!< 0x00000002 */ +#define QSPI_CTRL2_CMDIE QSPI_CTRL2_CMDIE_Msk /*!< Command complete Interrupt enable */ + +/*!< TXFIFO_THOD congiguration */ +#define QSPI_CTRL2_TXFIFO_THOD_Pos (8U) +#define QSPI_CTRL2_TXFIFO_THOD_Msk (0x3U << QSPI_CTRL2_TXFIFO_THOD_Pos) /*!< 0x00000300 */ +#define QSPI_CTRL2_TXFIFO_THOD QSPI_CTRL2_TXFIFO_THOD_Msk /*!< TXFIFO_THOD[1:0] bits (Program the level value to trigger TX FIFO threshold IRQ) */ +#define QSPI_CTRL2_TXFIFO_THOD_0 (0x1U << QSPI_CTRL2_TXFIFO_THOD_Pos) /*!< 0x00000100 */ +#define QSPI_CTRL2_TXFIFO_THOD_1 (0x2U << QSPI_CTRL2_TXFIFO_THOD_Pos) /*!< 0x00000200 */ + +#define QSPI_CTRL2_TXFIFO_THOD_8WORD 0x00000000U /*!< 8 WORD */ +#define QSPI_CTRL2_TXFIFO_THOD_16WORD 0x00000100U /*!< 16 WORD */ +#define QSPI_CTRL2_TXFIFO_THOD_24WORD 0x00000200U /*!< 24 WORD */ + +/*!< RXFIFO_THOD congiguration */ +#define QSPI_CTRL2_RXFIFO_THOD_Pos (12U) +#define QSPI_CTRL2_RXFIFO_THOD_Msk (0x3U << QSPI_CTRL2_RXFIFO_THOD_Pos) /*!< 0x00003000 */ +#define QSPI_CTRL2_RXFIFO_THOD QSPI_CTRL2_RXFIFO_THOD_Msk /*!< RXFIFO_THOD[1:0] bits (Program the level value to trigger RX FIFO threshold IRQ) */ +#define QSPI_CTRL2_RXFIFO_THOD_0 (0x1U << QSPI_CTRL2_RXFIFO_THOD_Pos) /*!< 0x00001000 */ +#define QSPI_CTRL2_RXFIFO_THOD_1 (0x2U << QSPI_CTRL2_RXFIFO_THOD_Pos) /*!< 0x00002000 */ + +#define QSPI_CTRL2_RXFIFO_THOD_8WORD 0x00000000U /*!< 8 WORD */ +#define QSPI_CTRL2_RXFIFO_THOD_16WORD 0x00001000U /*!< 16 WORD */ +#define QSPI_CTRL2_RXFIFO_THOD_24WORD 0x00002000U /*!< 24 WORD */ + +/***************** Bit definition for QSPI_CMDSTS register ******************/ +#define QSPI_CMDSTS_CMDSTS_Pos (0U) +#define QSPI_CMDSTS_CMDSTS_Msk (0x1U << QSPI_CMDSTS_CMDSTS_Pos) /*!< 0x00000001 */ +#define QSPI_CMDSTS_CMDSTS QSPI_CMDSTS_CMDSTS_Msk /*!< Command complete status */ + +/****************** Bit definition for QSPI_RSTS register *******************/ +#define QSPI_RSTS_SPISTS_Pos (0U) +#define QSPI_RSTS_SPISTS_Msk (0xFFU << QSPI_RSTS_SPISTS_Pos) /*!< 0x000000FF */ +#define QSPI_RSTS_SPISTS QSPI_RSTS_SPISTS_Msk /*!< SPI read status */ + +/****************** Bit definition for QSPI_FSIZE register ******************/ +#define QSPI_FSIZE_SPIFSIZE_Pos (0U) /*!< 0xFFFFFFFF */ +#define QSPI_FSIZE_SPIFSIZE_Msk (0xFFFFFFFFU << QSPI_FSIZE_SPIFSIZE_Pos) +#define QSPI_FSIZE_SPIFSIZE QSPI_FSIZE_SPIFSIZE_Msk /*!< SPI flash size */ + +/*************** Bit definition for QSPI_XIP_CMD_W0 register ****************/ +/*!< XIPR_DUM2 congiguration */ +#define QSPI_XIP_CMD_W0_XIPR_DUM2_Pos (0U) +#define QSPI_XIP_CMD_W0_XIPR_DUM2_Msk (0xFFU << QSPI_XIP_CMD_W0_XIPR_DUM2_Pos) /*!< 0x000000FF */ +#define QSPI_XIP_CMD_W0_XIPR_DUM2 QSPI_XIP_CMD_W0_XIPR_DUM2_Msk /*!< XIPR_DUM2[7:0] bits (XIP read second dummy cycle) */ +#define QSPI_XIP_CMD_W0_XIPR_DUM2_0 (0x01U << QSPI_XIP_CMD_W0_XIPR_DUM2_Pos) /*!< 0x00000001 */ +#define QSPI_XIP_CMD_W0_XIPR_DUM2_1 (0x02U << QSPI_XIP_CMD_W0_XIPR_DUM2_Pos) /*!< 0x00000002 */ +#define QSPI_XIP_CMD_W0_XIPR_DUM2_2 (0x04U << QSPI_XIP_CMD_W0_XIPR_DUM2_Pos) /*!< 0x00000004 */ +#define QSPI_XIP_CMD_W0_XIPR_DUM2_3 (0x08U << QSPI_XIP_CMD_W0_XIPR_DUM2_Pos) /*!< 0x00000008 */ +#define QSPI_XIP_CMD_W0_XIPR_DUM2_4 (0x10U << QSPI_XIP_CMD_W0_XIPR_DUM2_Pos) /*!< 0x00000010 */ +#define QSPI_XIP_CMD_W0_XIPR_DUM2_5 (0x20U << QSPI_XIP_CMD_W0_XIPR_DUM2_Pos) /*!< 0x00000020 */ +#define QSPI_XIP_CMD_W0_XIPR_DUM2_6 (0x40U << QSPI_XIP_CMD_W0_XIPR_DUM2_Pos) /*!< 0x00000040 */ +#define QSPI_XIP_CMD_W0_XIPR_DUM2_7 (0x80U << QSPI_XIP_CMD_W0_XIPR_DUM2_Pos) /*!< 0x00000080 */ + +/*!< XIPR_OPMODE congiguration */ +#define QSPI_XIP_CMD_W0_XIPR_OPMODE_Pos (8U) /*!< 0x00000700 */ +#define QSPI_XIP_CMD_W0_XIPR_OPMODE_Msk (0x7U << QSPI_XIP_CMD_W0_XIPR_OPMODE_Pos) +#define QSPI_XIP_CMD_W0_XIPR_OPMODE QSPI_XIP_CMD_W0_XIPR_OPMODE_Msk /*!< XIPR_OPMODE[2:0] bits (XIP read operation mode) */ +#define QSPI_XIP_CMD_W0_XIPR_OPMODE_0 (0x1U << QSPI_XIP_CMD_W0_XIPR_OPMODE_Pos) /*!< 0x00000100 */ +#define QSPI_XIP_CMD_W0_XIPR_OPMODE_1 (0x2U << QSPI_XIP_CMD_W0_XIPR_OPMODE_Pos) /*!< 0x00000200 */ +#define QSPI_XIP_CMD_W0_XIPR_OPMODE_2 (0x4U << QSPI_XIP_CMD_W0_XIPR_OPMODE_Pos) /*!< 0x00000400 */ + +#define QSPI_XIP_CMD_W0_XIPR_OPMODE_SERIAL 0x00000000U /*!< Serial mode (1-1-1) */ +#define QSPI_XIP_CMD_W0_XIPR_OPMODE_DUAL 0x00000100U /*!< Dual-wire mode (1-1-2) */ +#define QSPI_XIP_CMD_W0_XIPR_OPMODE_QUAD 0x00000200U /*!< Quad mode (1-1-4) */ +#define QSPI_XIP_CMD_W0_XIPR_OPMODE_DUALIO 0x00000300U /*!< Dual-wire I/O mode (1-2-2) */ +#define QSPI_XIP_CMD_W0_XIPR_OPMODE_QUADIO 0x00000400U /*!< Quad I/O mode (1-4-4) */ +#define QSPI_XIP_CMD_W0_XIPR_OPMODE_DPI 0x00000500U /*!< DPI mode (2-2-2) */ +#define QSPI_XIP_CMD_W0_XIPR_OPMODE_QPI 0x00000600U /*!< QPI mode (4-4-4) */ + +#define QSPI_XIP_CMD_W0_XIPR_ADRLEN_Pos (11U) /*!< 0x00000800 */ +#define QSPI_XIP_CMD_W0_XIPR_ADRLEN_Msk (0x1U << QSPI_XIP_CMD_W0_XIPR_ADRLEN_Pos) +#define QSPI_XIP_CMD_W0_XIPR_ADRLEN QSPI_XIP_CMD_W0_XIPR_ADRLEN_Msk /*!< XIP read address length */ +#define QSPI_XIP_CMD_W0_XIPR_INSC_Pos (12U) /*!< 0x000FF000 */ +#define QSPI_XIP_CMD_W0_XIPR_INSC_Msk (0xFFU << QSPI_XIP_CMD_W0_XIPR_INSC_Pos) +#define QSPI_XIP_CMD_W0_XIPR_INSC QSPI_XIP_CMD_W0_XIPR_INSC_Msk /*!< XIP read instruction code */ + +/*************** Bit definition for QSPI_XIP_CMD_W1 register ****************/ +/*!< XIPW_DUM2 congiguration */ +#define QSPI_XIP_CMD_W1_XIPW_DUM2_Pos (0U) +#define QSPI_XIP_CMD_W1_XIPW_DUM2_Msk (0xFFU << QSPI_XIP_CMD_W1_XIPW_DUM2_Pos) /*!< 0x000000FF */ +#define QSPI_XIP_CMD_W1_XIPW_DUM2 QSPI_XIP_CMD_W1_XIPW_DUM2_Msk /*!< XIPW_DUM2[7:0] bits (XIP write second dummy cycle) */ +#define QSPI_XIP_CMD_W1_XIPW_DUM2_0 (0x01U << QSPI_XIP_CMD_W1_XIPW_DUM2_Pos) /*!< 0x00000001 */ +#define QSPI_XIP_CMD_W1_XIPW_DUM2_1 (0x02U << QSPI_XIP_CMD_W1_XIPW_DUM2_Pos) /*!< 0x00000002 */ +#define QSPI_XIP_CMD_W1_XIPW_DUM2_2 (0x04U << QSPI_XIP_CMD_W1_XIPW_DUM2_Pos) /*!< 0x00000004 */ +#define QSPI_XIP_CMD_W1_XIPW_DUM2_3 (0x08U << QSPI_XIP_CMD_W1_XIPW_DUM2_Pos) /*!< 0x00000008 */ +#define QSPI_XIP_CMD_W1_XIPW_DUM2_4 (0x10U << QSPI_XIP_CMD_W1_XIPW_DUM2_Pos) /*!< 0x00000010 */ +#define QSPI_XIP_CMD_W1_XIPW_DUM2_5 (0x20U << QSPI_XIP_CMD_W1_XIPW_DUM2_Pos) /*!< 0x00000020 */ +#define QSPI_XIP_CMD_W1_XIPW_DUM2_6 (0x40U << QSPI_XIP_CMD_W1_XIPW_DUM2_Pos) /*!< 0x00000040 */ +#define QSPI_XIP_CMD_W1_XIPW_DUM2_7 (0x80U << QSPI_XIP_CMD_W1_XIPW_DUM2_Pos) /*!< 0x00000080 */ + +/*!< XIPW_OPMODE congiguration */ +#define QSPI_XIP_CMD_W1_XIPW_OPMODE_Pos (8U) /*!< 0x00000700 */ +#define QSPI_XIP_CMD_W1_XIPW_OPMODE_Msk (0x7U << QSPI_XIP_CMD_W1_XIPW_OPMODE_Pos) +#define QSPI_XIP_CMD_W1_XIPW_OPMODE QSPI_XIP_CMD_W1_XIPW_OPMODE_Msk /*!< XIPW_OPMODE[2:0] bits (XIP write operation mode) */ +#define QSPI_XIP_CMD_W1_XIPW_OPMODE_0 (0x1U << QSPI_XIP_CMD_W1_XIPW_OPMODE_Pos) /*!< 0x00000100 */ +#define QSPI_XIP_CMD_W1_XIPW_OPMODE_1 (0x2U << QSPI_XIP_CMD_W1_XIPW_OPMODE_Pos) /*!< 0x00000200 */ +#define QSPI_XIP_CMD_W1_XIPW_OPMODE_2 (0x4U << QSPI_XIP_CMD_W1_XIPW_OPMODE_Pos) /*!< 0x00000400 */ + +#define QSPI_XIP_CMD_W1_XIPW_OPMODE_SERIAL 0x00000000U /*!< Serial mode (1-1-1) */ +#define QSPI_XIP_CMD_W1_XIPW_OPMODE_DUAL 0x00000100U /*!< Dual-wire mode (1-1-2) */ +#define QSPI_XIP_CMD_W1_XIPW_OPMODE_QUAD 0x00000200U /*!< Quad mode (1-1-4) */ +#define QSPI_XIP_CMD_W1_XIPW_OPMODE_DUALIO 0x00000300U /*!< Dual-wire I/O mode (1-2-2) */ +#define QSPI_XIP_CMD_W1_XIPW_OPMODE_QUADIO 0x00000400U /*!< Quad I/O mode (1-4-4) */ +#define QSPI_XIP_CMD_W1_XIPW_OPMODE_DPI 0x00000500U /*!< DPI mode (2-2-2) */ +#define QSPI_XIP_CMD_W1_XIPW_OPMODE_QPI 0x00000600U /*!< QPI mode (4-4-4) */ + +#define QSPI_XIP_CMD_W1_XIPW_ADRLEN_Pos (11U) /*!< 0x00000800 */ +#define QSPI_XIP_CMD_W1_XIPW_ADRLEN_Msk (0x1U << QSPI_XIP_CMD_W1_XIPW_ADRLEN_Pos) +#define QSPI_XIP_CMD_W1_XIPW_ADRLEN QSPI_XIP_CMD_W1_XIPW_ADRLEN_Msk /*!< XIP write address length */ +#define QSPI_XIP_CMD_W1_XIPW_INSC_Pos (12U) /*!< 0x000FF000 */ +#define QSPI_XIP_CMD_W1_XIPW_INSC_Msk (0xFFU << QSPI_XIP_CMD_W1_XIPW_INSC_Pos) +#define QSPI_XIP_CMD_W1_XIPW_INSC QSPI_XIP_CMD_W1_XIPW_INSC_Msk /*!< XIP write instruction code */ + +/*************** Bit definition for QSPI_XIP_CMD_W2 register ****************/ +#define QSPI_XIP_CMD_W2_XIPR_DCNT_Pos (0U) /*!< 0x0000003F */ +#define QSPI_XIP_CMD_W2_XIPR_DCNT_Msk (0x3FU << QSPI_XIP_CMD_W2_XIPR_DCNT_Pos) +#define QSPI_XIP_CMD_W2_XIPR_DCNT QSPI_XIP_CMD_W2_XIPR_DCNT_Msk /*!< Indicates the time counter to judge maximum data count in mode D */ +#define QSPI_XIP_CMD_W2_XIPR_TCNT_Pos (8U) /*!< 0x00007F00 */ +#define QSPI_XIP_CMD_W2_XIPR_TCNT_Msk (0x7FU << QSPI_XIP_CMD_W2_XIPR_TCNT_Pos) +#define QSPI_XIP_CMD_W2_XIPR_TCNT QSPI_XIP_CMD_W2_XIPR_TCNT_Msk /*!< Indicates the time counter to judge time interval in mode T */ +#define QSPI_XIP_CMD_W2_XIPR_SEL_Pos (15U) +#define QSPI_XIP_CMD_W2_XIPR_SEL_Msk (0x1U << QSPI_XIP_CMD_W2_XIPR_SEL_Pos) /*!< 0x00008000 */ +#define QSPI_XIP_CMD_W2_XIPR_SEL QSPI_XIP_CMD_W2_XIPR_SEL_Msk /*!< XIP read mode select */ +#define QSPI_XIP_CMD_W2_XIPW_DCNT_Pos (16U) /*!< 0x003F0000 */ +#define QSPI_XIP_CMD_W2_XIPW_DCNT_Msk (0x3FU << QSPI_XIP_CMD_W2_XIPW_DCNT_Pos) +#define QSPI_XIP_CMD_W2_XIPW_DCNT QSPI_XIP_CMD_W2_XIPW_DCNT_Msk /*!< Indicates the time counter to judge maximum data count in mode D */ +#define QSPI_XIP_CMD_W2_XIPW_TCNT_Pos (24U) /*!< 0x7F000000 */ +#define QSPI_XIP_CMD_W2_XIPW_TCNT_Msk (0x7FU << QSPI_XIP_CMD_W2_XIPW_TCNT_Pos) +#define QSPI_XIP_CMD_W2_XIPW_TCNT QSPI_XIP_CMD_W2_XIPW_TCNT_Msk /*!< Indicates the time counter to judge time interval in mode T */ +#define QSPI_XIP_CMD_W2_XIPW_SEL_Pos (31U) +#define QSPI_XIP_CMD_W2_XIPW_SEL_Msk (0x1U << QSPI_XIP_CMD_W2_XIPW_SEL_Pos) /*!< 0x80000000 */ +#define QSPI_XIP_CMD_W2_XIPW_SEL QSPI_XIP_CMD_W2_XIPW_SEL_Msk /*!< XIP write mode select */ + +/*************** Bit definition for QSPI_XIP_CMD_W3 register ****************/ +#define QSPI_XIP_CMD_W3_BYPASSC_Pos (0U) +#define QSPI_XIP_CMD_W3_BYPASSC_Msk (0x1U << QSPI_XIP_CMD_W3_BYPASSC_Pos) /*!< 0x00000001 */ +#define QSPI_XIP_CMD_W3_BYPASSC QSPI_XIP_CMD_W3_BYPASSC_Msk /*!< Bypass cache function */ +#define QSPI_XIP_CMD_W3_CSTS_Pos (3U) +#define QSPI_XIP_CMD_W3_CSTS_Msk (0x1U << QSPI_XIP_CMD_W3_CSTS_Pos) /*!< 0x00000008 */ +#define QSPI_XIP_CMD_W3_CSTS QSPI_XIP_CMD_W3_CSTS_Msk /*!< Cache status */ + +/****************** Bit definition for QSPI_CTRL3 register ******************/ +#define QSPI_CTRL3_ISPC_Pos (8U) +#define QSPI_CTRL3_ISPC_Msk (0x1U << QSPI_CTRL3_ISPC_Pos) /*!< 0x00000100 */ +#define QSPI_CTRL3_ISPC QSPI_CTRL3_ISPC_Msk /*!< ISPC */ + +/******************* Bit definition for QSPI_REV register *******************/ +#define QSPI_REV_REV_Pos (0U) +#define QSPI_REV_REV_Msk (0xFFFFFFFFU << QSPI_REV_REV_Pos) /*!< 0xFFFFFFFF */ +#define QSPI_REV_REV QSPI_REV_REV_Msk /*!< Indicates IP version */ + +/******************* Bit definition for QSPI_DT register ********************/ +#define QSPI_DT_DT_Pos (0U) +#define QSPI_DT_DT_Msk (0xFFFFFFFFU << QSPI_DT_DT_Pos) /*!< 0xFFFFFFFF */ +#define QSPI_DT_DT QSPI_DT_DT_Msk /*!< Data port register */ + +/******************************************************************************/ +/* */ +/* Debug MCU (DEBUG) */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for DEBUG_IDCODE register *****************/ +/*!< PID congiguration */ +#define DEBUG_IDCODE_PID_Pos (0U) +#define DEBUG_IDCODE_PID_Msk (0xFFFFFFFFU << DEBUG_IDCODE_PID_Pos) /*!< 0xFFFFFFFF */ +#define DEBUG_IDCODE_PID DEBUG_IDCODE_PID_Msk /*!< PID[31:0] bits (PID information) */ +#define DEBUG_IDCODE_PID_0 (0x00000001U << DEBUG_IDCODE_PID_Pos) /*!< 0x00000001 */ +#define DEBUG_IDCODE_PID_1 (0x00000002U << DEBUG_IDCODE_PID_Pos) /*!< 0x00000002 */ +#define DEBUG_IDCODE_PID_2 (0x00000004U << DEBUG_IDCODE_PID_Pos) /*!< 0x00000004 */ +#define DEBUG_IDCODE_PID_3 (0x00000008U << DEBUG_IDCODE_PID_Pos) /*!< 0x00000008 */ +#define DEBUG_IDCODE_PID_4 (0x00000010U << DEBUG_IDCODE_PID_Pos) /*!< 0x00000010 */ +#define DEBUG_IDCODE_PID_5 (0x00000020U << DEBUG_IDCODE_PID_Pos) /*!< 0x00000020 */ +#define DEBUG_IDCODE_PID_6 (0x00000040U << DEBUG_IDCODE_PID_Pos) /*!< 0x00000040 */ +#define DEBUG_IDCODE_PID_7 (0x00000080U << DEBUG_IDCODE_PID_Pos) /*!< 0x00000080 */ +#define DEBUG_IDCODE_PID_8 (0x00000100U << DEBUG_IDCODE_PID_Pos) /*!< 0x00000100 */ +#define DEBUG_IDCODE_PID_9 (0x00000200U << DEBUG_IDCODE_PID_Pos) /*!< 0x00000200 */ +#define DEBUG_IDCODE_PID_10 (0x00000400U << DEBUG_IDCODE_PID_Pos) /*!< 0x00000400 */ +#define DEBUG_IDCODE_PID_11 (0x00000800U << DEBUG_IDCODE_PID_Pos) /*!< 0x00000800 */ +#define DEBUG_IDCODE_PID_12 (0x00001000U << DEBUG_IDCODE_PID_Pos) /*!< 0x00001000 */ +#define DEBUG_IDCODE_PID_13 (0x00002000U << DEBUG_IDCODE_PID_Pos) /*!< 0x00002000 */ +#define DEBUG_IDCODE_PID_14 (0x00004000U << DEBUG_IDCODE_PID_Pos) /*!< 0x00004000 */ +#define DEBUG_IDCODE_PID_15 (0x00008000U << DEBUG_IDCODE_PID_Pos) /*!< 0x00008000 */ +#define DEBUG_IDCODE_PID_16 (0x00010000U << DEBUG_IDCODE_PID_Pos) /*!< 0x00010000 */ +#define DEBUG_IDCODE_PID_17 (0x00020000U << DEBUG_IDCODE_PID_Pos) /*!< 0x00020000 */ +#define DEBUG_IDCODE_PID_18 (0x00040000U << DEBUG_IDCODE_PID_Pos) /*!< 0x00040000 */ +#define DEBUG_IDCODE_PID_19 (0x00080000U << DEBUG_IDCODE_PID_Pos) /*!< 0x00080000 */ +#define DEBUG_IDCODE_PID_20 (0x00100000U << DEBUG_IDCODE_PID_Pos) /*!< 0x00100000 */ +#define DEBUG_IDCODE_PID_21 (0x00200000U << DEBUG_IDCODE_PID_Pos) /*!< 0x00200000 */ +#define DEBUG_IDCODE_PID_22 (0x00400000U << DEBUG_IDCODE_PID_Pos) /*!< 0x00400000 */ +#define DEBUG_IDCODE_PID_23 (0x00800000U << DEBUG_IDCODE_PID_Pos) /*!< 0x00800000 */ +#define DEBUG_IDCODE_PID_24 (0x01000000U << DEBUG_IDCODE_PID_Pos) /*!< 0x01000000 */ +#define DEBUG_IDCODE_PID_25 (0x02000000U << DEBUG_IDCODE_PID_Pos) /*!< 0x02000000 */ +#define DEBUG_IDCODE_PID_26 (0x04000000U << DEBUG_IDCODE_PID_Pos) /*!< 0x04000000 */ +#define DEBUG_IDCODE_PID_27 (0x08000000U << DEBUG_IDCODE_PID_Pos) /*!< 0x08000000 */ +#define DEBUG_IDCODE_PID_28 (0x10000000U << DEBUG_IDCODE_PID_Pos) /*!< 0x10000000 */ +#define DEBUG_IDCODE_PID_29 (0x20000000U << DEBUG_IDCODE_PID_Pos) /*!< 0x20000000 */ +#define DEBUG_IDCODE_PID_30 (0x40000000U << DEBUG_IDCODE_PID_Pos) /*!< 0x40000000 */ +#define DEBUG_IDCODE_PID_31 (0x80000000U << DEBUG_IDCODE_PID_Pos) /*!< 0x80000000 */ + +/****************** Bit definition for DEBUG_CTRL register ******************/ +#define DEBUG_CTRL_SLEEP_DEBUG_Pos (0U) +#define DEBUG_CTRL_SLEEP_DEBUG_Msk (0x1U << DEBUG_CTRL_SLEEP_DEBUG_Pos) /*!< 0x00000001 */ +#define DEBUG_CTRL_SLEEP_DEBUG DEBUG_CTRL_SLEEP_DEBUG_Msk /*!< Debug Sleep mode control bit */ +#define DEBUG_CTRL_DEEPSLEEP_DEBUG_Pos (1U) /*!< 0x00000002 */ +#define DEBUG_CTRL_DEEPSLEEP_DEBUG_Msk (0x1U << DEBUG_CTRL_DEEPSLEEP_DEBUG_Pos) +#define DEBUG_CTRL_DEEPSLEEP_DEBUG DEBUG_CTRL_DEEPSLEEP_DEBUG_Msk /*!< Debug Deep sleep mode control bit */ +#define DEBUG_CTRL_STANDBY_DEBUG_Pos (2U) +#define DEBUG_CTRL_STANDBY_DEBUG_Msk (0x1U << DEBUG_CTRL_STANDBY_DEBUG_Pos) /*!< 0x00000004 */ +#define DEBUG_CTRL_STANDBY_DEBUG DEBUG_CTRL_STANDBY_DEBUG_Msk /*!< Debug Standby mode control bit */ + +/*************** Bit definition for DEBUG_APB1_PAUSE register ***************/ +#define DEBUG_APB1_PAUSE_TMR2_PAUSE_Pos (0U) /*!< 0x00000001 */ +#define DEBUG_APB1_PAUSE_TMR2_PAUSE_Msk (0x1U << DEBUG_APB1_PAUSE_TMR2_PAUSE_Pos) +#define DEBUG_APB1_PAUSE_TMR2_PAUSE DEBUG_APB1_PAUSE_TMR2_PAUSE_Msk /*!< TMR2 pause control bit */ +#define DEBUG_APB1_PAUSE_TMR3_PAUSE_Pos (1U) /*!< 0x00000002 */ +#define DEBUG_APB1_PAUSE_TMR3_PAUSE_Msk (0x1U << DEBUG_APB1_PAUSE_TMR3_PAUSE_Pos) +#define DEBUG_APB1_PAUSE_TMR3_PAUSE DEBUG_APB1_PAUSE_TMR3_PAUSE_Msk /*!< TMR3 pause control bit */ +#define DEBUG_APB1_PAUSE_TMR4_PAUSE_Pos (2U) /*!< 0x00000004 */ +#define DEBUG_APB1_PAUSE_TMR4_PAUSE_Msk (0x1U << DEBUG_APB1_PAUSE_TMR4_PAUSE_Pos) +#define DEBUG_APB1_PAUSE_TMR4_PAUSE DEBUG_APB1_PAUSE_TMR4_PAUSE_Msk /*!< TMR4 pause control bit */ +#define DEBUG_APB1_PAUSE_TMR6_PAUSE_Pos (4U) /*!< 0x00000010 */ +#define DEBUG_APB1_PAUSE_TMR6_PAUSE_Msk (0x1U << DEBUG_APB1_PAUSE_TMR6_PAUSE_Pos) +#define DEBUG_APB1_PAUSE_TMR6_PAUSE DEBUG_APB1_PAUSE_TMR6_PAUSE_Msk /*!< TMR6 pause control bit */ +#define DEBUG_APB1_PAUSE_TMR7_PAUSE_Pos (5U) /*!< 0x00000020 */ +#define DEBUG_APB1_PAUSE_TMR7_PAUSE_Msk (0x1U << DEBUG_APB1_PAUSE_TMR7_PAUSE_Pos) +#define DEBUG_APB1_PAUSE_TMR7_PAUSE DEBUG_APB1_PAUSE_TMR7_PAUSE_Msk /*!< TMR7 pause control bit */ +#define DEBUG_APB1_PAUSE_TMR13_PAUSE_Pos (7U) /*!< 0x00000080 */ +#define DEBUG_APB1_PAUSE_TMR13_PAUSE_Msk (0x1U << DEBUG_APB1_PAUSE_TMR13_PAUSE_Pos) +#define DEBUG_APB1_PAUSE_TMR13_PAUSE DEBUG_APB1_PAUSE_TMR13_PAUSE_Msk /*!< TMR13 pause control bit */ +#define DEBUG_APB1_PAUSE_TMR14_PAUSE_Pos (8U) /*!< 0x00000100 */ +#define DEBUG_APB1_PAUSE_TMR14_PAUSE_Msk (0x1U << DEBUG_APB1_PAUSE_TMR14_PAUSE_Pos) +#define DEBUG_APB1_PAUSE_TMR14_PAUSE DEBUG_APB1_PAUSE_TMR14_PAUSE_Msk /*!< TMR14 pause control bit */ +#define DEBUG_APB1_PAUSE_ERTC_PAUSE_Pos (10U) /*!< 0x00000400 */ +#define DEBUG_APB1_PAUSE_ERTC_PAUSE_Msk (0x1U << DEBUG_APB1_PAUSE_ERTC_PAUSE_Pos) +#define DEBUG_APB1_PAUSE_ERTC_PAUSE DEBUG_APB1_PAUSE_ERTC_PAUSE_Msk /*!< ERTC pause control bit */ +#define DEBUG_APB1_PAUSE_WWDT_PAUSE_Pos (11U) /*!< 0x00000800 */ +#define DEBUG_APB1_PAUSE_WWDT_PAUSE_Msk (0x1U << DEBUG_APB1_PAUSE_WWDT_PAUSE_Pos) +#define DEBUG_APB1_PAUSE_WWDT_PAUSE DEBUG_APB1_PAUSE_WWDT_PAUSE_Msk /*!< Window watchdog pause control bit */ +#define DEBUG_APB1_PAUSE_WDT_PAUSE_Pos (12U) /*!< 0x00001000 */ +#define DEBUG_APB1_PAUSE_WDT_PAUSE_Msk (0x1U << DEBUG_APB1_PAUSE_WDT_PAUSE_Pos) +#define DEBUG_APB1_PAUSE_WDT_PAUSE DEBUG_APB1_PAUSE_WDT_PAUSE_Msk /*!< Watchdog pause control bit */ +#define DEBUG_APB1_PAUSE_I2C1_SMBUS_TIMEOUT_Pos (24U) /*!< 0x01000000 */ +#define DEBUG_APB1_PAUSE_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DEBUG_APB1_PAUSE_I2C1_SMBUS_TIMEOUT_Pos) +#define DEBUG_APB1_PAUSE_I2C1_SMBUS_TIMEOUT DEBUG_APB1_PAUSE_I2C1_SMBUS_TIMEOUT_Msk /*!< I2C1 pause control bit */ +#define DEBUG_APB1_PAUSE_CAN1_PAUSE_Pos (25U) /*!< 0x02000000 */ +#define DEBUG_APB1_PAUSE_CAN1_PAUSE_Msk (0x1U << DEBUG_APB1_PAUSE_CAN1_PAUSE_Pos) +#define DEBUG_APB1_PAUSE_CAN1_PAUSE DEBUG_APB1_PAUSE_CAN1_PAUSE_Msk /*!< CAN1 pause control bit */ +#define DEBUG_APB1_PAUSE_I2C2_SMBUS_TIMEOUT_Pos (27U) /*!< 0x08000000 */ +#define DEBUG_APB1_PAUSE_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DEBUG_APB1_PAUSE_I2C2_SMBUS_TIMEOUT_Pos) +#define DEBUG_APB1_PAUSE_I2C2_SMBUS_TIMEOUT DEBUG_APB1_PAUSE_I2C2_SMBUS_TIMEOUT_Msk /*!< I2C2 pause control bit */ +#define DEBUG_APB1_PAUSE_I2C3_SMBUS_TIMEOUT_Pos (28U) /*!< 0x10000000 */ +#define DEBUG_APB1_PAUSE_I2C3_SMBUS_TIMEOUT_Msk (0x1U << DEBUG_APB1_PAUSE_I2C3_SMBUS_TIMEOUT_Pos) +#define DEBUG_APB1_PAUSE_I2C3_SMBUS_TIMEOUT DEBUG_APB1_PAUSE_I2C3_SMBUS_TIMEOUT_Msk /*!< I2C3 pause control bit */ + +/*************** Bit definition for DEBUG_APB2_PAUSE register ***************/ +#define DEBUG_APB2_PAUSE_TMR1_PAUSE_Pos (0U) /*!< 0x00000001 */ +#define DEBUG_APB2_PAUSE_TMR1_PAUSE_Msk (0x1U << DEBUG_APB2_PAUSE_TMR1_PAUSE_Pos) +#define DEBUG_APB2_PAUSE_TMR1_PAUSE DEBUG_APB2_PAUSE_TMR1_PAUSE_Msk /*!< TMR1 pause control bit */ +#define DEBUG_APB2_PAUSE_TMR9_PAUSE_Pos (16U) /*!< 0x00010000 */ +#define DEBUG_APB2_PAUSE_TMR9_PAUSE_Msk (0x1U << DEBUG_APB2_PAUSE_TMR9_PAUSE_Pos) +#define DEBUG_APB2_PAUSE_TMR9_PAUSE DEBUG_APB2_PAUSE_TMR9_PAUSE_Msk /*!< TMR9 pause control bit */ +#define DEBUG_APB2_PAUSE_TMR10_PAUSE_Pos (17U) /*!< 0x00020000 */ +#define DEBUG_APB2_PAUSE_TMR10_PAUSE_Msk (0x1U << DEBUG_APB2_PAUSE_TMR10_PAUSE_Pos) +#define DEBUG_APB2_PAUSE_TMR10_PAUSE DEBUG_APB2_PAUSE_TMR10_PAUSE_Msk /*!< TMR10 pause control bit */ +#define DEBUG_APB2_PAUSE_TMR11_PAUSE_Pos (18U) /*!< 0x00040000 */ +#define DEBUG_APB2_PAUSE_TMR11_PAUSE_Msk (0x1U << DEBUG_APB2_PAUSE_TMR11_PAUSE_Pos) +#define DEBUG_APB2_PAUSE_TMR11_PAUSE DEBUG_APB2_PAUSE_TMR11_PAUSE_Msk /*!< TMR11 pause control bit */ + +/***************** Bit definition for DEBUG_SER_ID register *****************/ +/*!< REV_ID congiguration */ +#define DEBUG_SER_ID_REV_ID_Pos (0U) +#define DEBUG_SER_ID_REV_ID_Msk (0x7U << DEBUG_SER_ID_REV_ID_Pos) /*!< 0x00000007 */ +#define DEBUG_SER_ID_REV_ID DEBUG_SER_ID_REV_ID_Msk /*!< REV_ID[2:0] bits (Revision ID) */ +#define DEBUG_SER_ID_REV_ID_0 (0x1U << DEBUG_SER_ID_REV_ID_Pos) /*!< 0x00000001 */ +#define DEBUG_SER_ID_REV_ID_1 (0x2U << DEBUG_SER_ID_REV_ID_Pos) /*!< 0x00000002 */ +#define DEBUG_SER_ID_REV_ID_2 (0x4U << DEBUG_SER_ID_REV_ID_Pos) /*!< 0x00000004 */ + +/*!< SER_ID congiguration */ +#define DEBUG_SER_ID_SER_ID_Pos (8U) +#define DEBUG_SER_ID_SER_ID_Msk (0xFFU << DEBUG_SER_ID_SER_ID_Pos) /*!< 0x0000FF00 */ +#define DEBUG_SER_ID_SER_ID DEBUG_SER_ID_SER_ID_Msk /*!< SER_ID[7:0] bits (Serial ID) */ +#define DEBUG_SER_ID_SER_ID_0 (0x01U << DEBUG_SER_ID_SER_ID_Pos) /*!< 0x00000100 */ +#define DEBUG_SER_ID_SER_ID_1 (0x02U << DEBUG_SER_ID_SER_ID_Pos) /*!< 0x00000200 */ +#define DEBUG_SER_ID_SER_ID_2 (0x04U << DEBUG_SER_ID_SER_ID_Pos) /*!< 0x00000400 */ +#define DEBUG_SER_ID_SER_ID_3 (0x08U << DEBUG_SER_ID_SER_ID_Pos) /*!< 0x00000800 */ +#define DEBUG_SER_ID_SER_ID_4 (0x10U << DEBUG_SER_ID_SER_ID_Pos) /*!< 0x00001000 */ +#define DEBUG_SER_ID_SER_ID_5 (0x20U << DEBUG_SER_ID_SER_ID_Pos) /*!< 0x00002000 */ +#define DEBUG_SER_ID_SER_ID_6 (0x40U << DEBUG_SER_ID_SER_ID_Pos) /*!< 0x00004000 */ +#define DEBUG_SER_ID_SER_ID_7 (0x80U << DEBUG_SER_ID_SER_ID_Pos) /*!< 0x00008000 */ + +/** + * @} +*/ + +/** + * @} +*/ + +/** @addtogroup Exported_macro + * @{ + */ + +#define CRM_HEXT_MIN 4000000U +#define CRM_HEXT_MAX 25000000U + +#define CRM_MAX_FREQUENCY 216000000U + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __AT32F402_405Rx_H */ + +/*********************** (C) COPYRIGHT Artery Technology *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ArteryTek/AT32F402_405/system_at32f402_405.h b/os/common/ext/CMSIS/ArteryTek/AT32F402_405/system_at32f402_405.h new file mode 100644 index 0000000000..e87780860a --- /dev/null +++ b/os/common/ext/CMSIS/ArteryTek/AT32F402_405/system_at32f402_405.h @@ -0,0 +1,105 @@ +/** + ************************************************************************** + * @file system_at32f402_405.h + * @author Artery Technology & HorrorTroll & Zhaqian & Maxjta + * @brief CMSIS AT32F402_405 system header file + * + ************************************************************************** + * Copyright notice & Disclaimer + * + * The software Board Support Package (BSP) that is made available to + * download from Artery official website is the copyrighted work of Artery. + * Artery authorizes customers to use, copy, and distribute the BSP + * software and its related documentation for the purpose of design and + * development in conjunction with Artery microcontrollers. Use of the + * software is governed by this copyright notice and the following disclaimer. + * + * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES, + * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS, + * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR + * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS, + * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. + * + ************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup AT32F402_405_system + * @{ + */ + +/** + * @brief Define to prevent recursive inclusion + */ + +#ifndef __SYSTEM_AT32F402_405_H +#define __SYSTEM_AT32F402_405_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup AT32F402_405_System_Includes + * @{ + */ + +/** + * @} + */ + +/** @defgroup AT32F402_405_System_Exported_Variables + * @{ + */ + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +/** + * @} + */ + +/** @addtogroup AT32F402_405_System_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @addtogroup AT32F402_405_System_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup AT32F402_405_System_Exported_Functions + * @{ + */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_AT32F402_405_H */ + +/** + * @} + */ + +/** + * @} + */ + +/*********************** (C) COPYRIGHT Artery Technology *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ArteryTek/AT32F402_405xx/at32f402_405xx.h b/os/common/ext/CMSIS/ArteryTek/AT32F402_405xx/at32f402_405xx.h deleted file mode 100644 index f359d99744..0000000000 --- a/os/common/ext/CMSIS/ArteryTek/AT32F402_405xx/at32f402_405xx.h +++ /dev/null @@ -1,2649 +0,0 @@ -/** - ************************************************************************** - * @file at32f402_405.h - * @brief at32f402_405 header file - ************************************************************************** - * Copyright notice & Disclaimer - * - * The software Board Support Package (BSP) that is made available to - * download from Artery official website is the copyrighted work of Artery. - * Artery authorizes customers to use, copy, and distribute the BSP - * software and its related documentation for the purpose of design and - * development in conjunction with Artery microcontrollers. Use of the - * software is governed by this copyright notice and the following disclaimer. - * - * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES, - * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS, - * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR - * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS, - * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. - * - ************************************************************************** - */ - -#ifndef __AT32F402_405_H -#define __AT32F402_405_H - -#ifdef __cplusplus -extern "C" { -#endif - -#if defined (__CC_ARM) - #pragma anon_unions -#endif - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup AT32F402_405 - * @{ - */ - -/** @addtogroup Library_configuration_section - * @{ - */ - -/** - * tip: to avoid modifying this file each time you need to switch between these - * devices, you can define the device in your toolchain compiler preprocessor. - */ - -#if !defined (AT32F405KBU7_4) && !defined (AT32F405KCU7_4) && !defined (AT32F405CBT7) && \ - !defined (AT32F405CCT7) && !defined (AT32F405CBU7) && !defined (AT32F405CCU7) && \ - !defined (AT32F405RBT7_7) && !defined (AT32F405RCT7_7) && !defined (AT32F405RBT7) && \ - !defined (AT32F405RCT7) && !defined (AT32F402KBU7_4) && !defined (AT32F402KCU7_4)&& \ - !defined (AT32F402CBT7) && !defined (AT32F402CCT7) && !defined (AT32F402CBU7) && \ - !defined (AT32F402CCU7) && !defined (AT32F402RBT7_7) && !defined (AT32F402RCT7_7)&& \ - !defined (AT32F402RBT7) && !defined (AT32F402RCT7) - - #error "Please select first the target device used in your application (in at32f402_405.h file)" -#endif - -#if defined (AT32F405KBU7_4) || defined (AT32F405KCU7_4) || defined (AT32F405CBT7) || \ - defined (AT32F405CCT7) || defined (AT32F405CBU7) || defined (AT32F405CCU7) || \ - defined (AT32F405RBT7_7) || defined (AT32F405RCT7_7) || defined (AT32F405RBT7) || \ - defined (AT32F405RCT7) - - #define AT32F405xx -#endif - -#if defined (AT32F402KBU7_4) || defined (AT32F402KCU7_4) || defined (AT32F402CBT7) || \ - defined (AT32F402CCT7) || defined (AT32F402CBU7) || defined (AT32F402CCU7) || \ - defined (AT32F402RBT7_7) || defined (AT32F402RCT7_7) || defined (AT32F402RBT7) || \ - defined (AT32F402RCT7) - - #define AT32F402xx -#endif - -/** - * define with package - */ -#if defined (AT32F405KBU7_4) || defined (AT32F405KCU7_4) - - #define AT32F405Kx -#endif -#if defined (AT32F405CBT7) || defined (AT32F405CCT7) || defined (AT32F405CBU7) || \ - defined (AT32F405CCU7) - - #define AT32F405Rx -#endif - -#if defined (AT32F405RBT7_7) || defined (AT32F405RCT7_7) || defined (AT32F405RBT7) || \ - defined (AT32F405RCT7) - - #define AT32F405Rx -#endif - -#if defined (AT32F402KBU7_4) || defined (AT32F402KCU7_4) - - #define AT32F402Kx -#endif -#if defined (AT32F402CBT7) || defined (AT32F402CCT7) || defined (AT32F402CBU7) || \ - defined (AT32F402CCU7) - - #define AT32F402Rx -#endif - -#if defined (AT32F402RBT7_7) || defined (AT32F402RCT7_7) || defined (AT32F402RBT7) || \ - defined (AT32F402RCT7) - - #define AT32F402Rx -#endif - - -/** - * define with memory density - */ -#if defined (AT32F405KBU7_4) || defined (AT32F405CBT7) || defined (AT32F405CBU7) || \ - defined (AT32F405RBT7_7) || defined (AT32F405RBT7) - - #define AT32F405xB -#endif - -#if defined (AT32F405KCU7_4) || defined (AT32F405CCT7) || defined (AT32F405CCU7) || \ - defined (AT32F405RCT7_7) || defined (AT32F405RCT7) - - #define AT32F405xC -#endif - -#if defined (AT32F402KBU7_4) || defined (AT32F402CBT7) || defined (AT32F402CBU7) || \ - defined (AT32F402RBT7_7) || defined (AT32F402RBT7) - - #define AT32F402xB -#endif - -#if defined (AT32F402KCU7_4) || defined (AT32F402CCT7) || defined (AT32F402CCU7) || \ - defined (AT32F402RCT7_7) || defined (AT32F402RCT7) - - #define AT32F402xC -#endif - -#ifndef USE_STDPERIPH_DRIVER -/** - * @brief comment the line below if you will not use the peripherals drivers. - * in this case, these drivers will not be included and the application code will - * be based on direct access to peripherals registers - */ - #ifdef _RTE_ - #include "RTE_Components.h" - #ifdef RTE_DEVICE_STDPERIPH_FRAMEWORK - #define USE_STDPERIPH_DRIVER - #endif - #endif -#endif - -/** - * @brief at32f402_405 standard peripheral library version number - */ -#define __AT32F402_405_LIBRARY_VERSION_MAJOR (0x02) /*!< [31:24] major version */ -#define __AT32F402_405_LIBRARY_VERSION_MIDDLE (0x00) /*!< [23:16] middle version */ -#define __AT32F402_405_LIBRARY_VERSION_MINOR (0x00) /*!< [15:8] minor version */ -#define __AT32F402_405_LIBRARY_VERSION_RC (0x00) /*!< [7:0] release candidate */ -#define __AT32F402_405_LIBRARY_VERSION ((__AT32F402_405_LIBRARY_VERSION_MAJOR << 24) | \ - (__AT32F402_405_LIBRARY_VERSION_MIDDLE << 16) | \ - (__AT32F402_405_LIBRARY_VERSION_MINOR << 8) | \ - (__AT32F402_405_LIBRARY_VERSION_RC)) - -/** - * @} - */ - -/** @addtogroup configuration_section_for_cmsis - * @{ - */ - -/** - * @brief configuration of the cortex-m4 processor and core peripherals - */ -#define __CM4_REV 0x0001U /*!< core revision r0p1 */ -#define __MPU_PRESENT 1 /*!< mpu present */ -#define __NVIC_PRIO_BITS 4 /*!< at32 uses 4 bits for the priority levels */ -#define __Vendor_SysTickConfig 0 /*!< set to 1 if different systick config is used */ -#define __FPU_PRESENT 1U /*!< fpu present */ - -/** - * @brief at32f402_405 interrupt number definition, according to the selected device - * in @ref library_configuration_section - */ -typedef enum IRQn -{ - /****** cortex-m4 processor exceptions numbers ***************************************************/ - Reset_IRQn = -15, /*!< 1 reset vector, invoked on power up and warm reset */ - NonMaskableInt_IRQn = -14, /*!< 2 non maskable interrupt */ - HardFault_IRQn = -13, /*!< 3 hard fault, all classes of fault */ - MemoryManagement_IRQn = -12, /*!< 4 cortex-m4 memory management interrupt */ - BusFault_IRQn = -11, /*!< 5 cortex-m4 bus fault interrupt */ - UsageFault_IRQn = -10, /*!< 6 cortex-m4 usage fault interrupt */ - SVCall_IRQn = -5, /*!< 11 cortex-m4 sv call interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 cortex-m4 debug monitor interrupt */ - PendSV_IRQn = -2, /*!< 14 cortex-m4 pend sv interrupt */ - SysTick_IRQn = -1, /*!< 15 cortex-m4 system tick interrupt */ - - /****** at32 specific interrupt numbers *********************************************************/ - WWDT_IRQn = 0, /*!< window watchdog timer interrupt */ - PVM_IRQn = 1, /*!< pvm through exint line detection interrupt */ - TAMP_STAMP_IRQn = 2, /*!< tamper and timestamp interrupts through the exint line */ - ERTC_WKUP_IRQn = 3, /*!< ertc wakeup through the exint line */ - FLASH_IRQn = 4, /*!< flash global interrupt */ - CRM_IRQn = 5, /*!< crm global interrupt */ - EXINT0_IRQn = 6, /*!< exint line0 interrupt */ - EXINT1_IRQn = 7, /*!< exint line1 interrupt */ - EXINT2_IRQn = 8, /*!< exint line2 interrupt */ - EXINT3_IRQn = 9, /*!< exint line3 interrupt */ - EXINT4_IRQn = 10, /*!< exint line4 interrupt */ - DMA1_Channel1_IRQn = 11, /*!< dma1 channel 1 global interrupt */ - DMA1_Channel2_IRQn = 12, /*!< dma1 channel 2 global interrupt */ - DMA1_Channel3_IRQn = 13, /*!< dma1 channel 3 global interrupt */ - DMA1_Channel4_IRQn = 14, /*!< dma1 channel 4 global interrupt */ - DMA1_Channel5_IRQn = 15, /*!< dma1 channel 5 global interrupt */ - DMA1_Channel6_IRQn = 16, /*!< dma1 channel 6 global interrupt */ - DMA1_Channel7_IRQn = 17, /*!< dma1 channel 7 global interrupt */ - - ADC1_IRQn = 18, /*!< adc1 global interrupt */ - CAN1_TX_IRQn = 19, /*!< can1 tx interrupts */ - CAN1_RX0_IRQn = 20, /*!< can1 rx0 interrupts */ - CAN1_RX1_IRQn = 21, /*!< can1 rx1 interrupt */ - CAN1_SE_IRQn = 22, /*!< can1 se interrupt */ - EXINT9_5_IRQn = 23, /*!< external line[9:5] interrupts */ - TMR1_BRK_TMR9_IRQn = 24, /*!< tmr1 brake interrupt */ - TMR1_OVF_TMR10_IRQn = 25, /*!< tmr1 overflow interrupt */ - TMR1_TRG_HALL_TMR11_IRQn = 26, /*!< tmr1 trigger and hall interrupt */ - TMR1_CH_IRQn = 27, /*!< tmr1 channel interrupt */ - TMR2_GLOBAL_IRQn = 28, /*!< tmr2 global interrupt */ - TMR3_GLOBAL_IRQn = 29, /*!< tmr3 global interrupt */ - TMR4_GLOBAL_IRQn = 30, /*!< tmr4 global interrupt */ - I2C1_EVT_IRQn = 31, /*!< i2c1 event interrupt */ - I2C1_ERR_IRQn = 32, /*!< i2c1 error interrupt */ - I2C2_EVT_IRQn = 33, /*!< i2c2 event interrupt */ - I2C2_ERR_IRQn = 34, /*!< i2c2 error interrupt */ - SPI1_IRQn = 35, /*!< spi1 global interrupt */ - SPI2_IRQn = 36, /*!< spi2 global interrupt */ - USART1_IRQn = 37, /*!< usart1 global interrupt */ - USART2_IRQn = 38, /*!< usart2 global interrupt */ - USART3_IRQn = 39, /*!< usart3 global interrupt */ - EXINT15_10_IRQn = 40, /*!< external line[15:10] interrupts */ - ERTCAlarm_IRQn = 41, /*!< ertc alarm through exint line interrupt */ - OTGFS1_WKUP_IRQn = 42, /*!< otgfs1 wakeup from suspend through exint line interrupt */ - TMR13_GLOBAL_IRQn = 44, /*!< tmr13 global interrupt */ - TMR14_GLOBAL_IRQn = 45, /*!< tmr14 global interrupt */ - SPI3_IRQn = 51, /*!< spi3 global interrupt */ - USART4_IRQn = 52, /*!< usart4 global interrupt */ - USART5_IRQn = 53, /*!< usart5 global interrupt */ - TMR6_GLOBAL_IRQn = 54, /*!< tmr6 global interrupt */ - TMR7_GLOBAL_IRQn = 55, /*!< tmr7 global interrupt */ - DMA2_Channel1_IRQn = 56, /*!< dma2 channel 1 global interrupt */ - DMA2_Channel2_IRQn = 57, /*!< dma2 channel 2 global interrupt */ - DMA2_Channel3_IRQn = 58, /*!< dma2 channel 3 global interrupt */ - DMA2_Channel4_IRQn = 59, /*!< dma2 channel 4 global interrupt */ - DMA2_Channel5_IRQn = 60, /*!< dma2 channel 5 global interrupt */ - OTGFS1_IRQn = 67, /*!< otgfs1 interrupt */ - DMA2_Channel6_IRQn = 68, /*!< dma2 channel 6 global interrupt */ - DMA2_Channel7_IRQn = 69, /*!< dma2 channel 7 global interrupt */ - USART6_IRQn = 71, /*!< usart6 interrupt */ - I2C3_EVT_IRQn = 72, /*!< i2c3 event interrupt */ - I2C3_ERR_IRQn = 73, /*!< i2c3 error interrupt */ - OTGHS_EP1_OUT_IRQn = 74, /*!< otghs wakeup from suspend through exint line interrupt */ - OTGHS_EP1_IN_IRQn = 75, /*!< otghs interrupt */ - OTGHS_WKUP_IRQn = 76, /*!< otghs wakeup from suspend through exint line interrupt */ - OTGHS_IRQn = 77, /*!< otghs interrupt */ - FPU_IRQn = 81, /*!< fpu interrupt */ - UART7_IRQn = 82, /*!< uart7 interrupt */ - UART8_IRQn = 83, /*!< uart8 interrupt */ - I2SF5_IRQn = 85, /*!< i2sf5 global interrupt */ - QSPI1_IRQn = 92, /*!< qspi1 global interrupt */ - DMAMUX_IRQn = 94, /*!< dmamux global interrupt */ - ACC_IRQn = 103, /*!< acc interrupt */ - -} IRQn_Type; - -/** - * @} - */ - -#include "core_cm4.h" -#include - -/** @addtogroup Exported_types - * @{ - */ - -typedef int32_t INT32; -typedef int16_t INT16; -typedef int8_t INT8; -typedef uint32_t UINT32; -typedef uint16_t UINT16; -typedef uint8_t UINT8; - -typedef int32_t s32; -typedef int16_t s16; -typedef int8_t s8; - -typedef const int32_t sc32; /*!< read only */ -typedef const int16_t sc16; /*!< read only */ -typedef const int8_t sc8; /*!< read only */ - -typedef __IO int32_t vs32; -typedef __IO int16_t vs16; -typedef __IO int8_t vs8; - -typedef __I int32_t vsc32; /*!< read only */ -typedef __I int16_t vsc16; /*!< read only */ -typedef __I int8_t vsc8; /*!< read only */ - -typedef uint32_t u32; -typedef uint16_t u16; -typedef uint8_t u8; - -typedef const uint32_t uc32; /*!< read only */ -typedef const uint16_t uc16; /*!< read only */ -typedef const uint8_t uc8; /*!< read only */ - -typedef __IO uint32_t vu32; -typedef __IO uint16_t vu16; -typedef __IO uint8_t vu8; - -typedef __I uint32_t vuc32; /*!< read only */ -typedef __I uint16_t vuc16; /*!< read only */ -typedef __I uint8_t vuc8; /*!< read only */ - -typedef enum {RESET = 0, SET = !RESET} flag_status; -typedef enum {ERROR = 0, SUCCESS = !ERROR} error_status; - -/** - * @} - */ - -/** @addtogroup Exported_macro - * @{ - */ - -#define REG8(addr) *(volatile uint8_t *)(addr) -#define REG16(addr) *(volatile uint16_t *)(addr) -#define REG32(addr) *(volatile uint32_t *)(addr) - -#define MAKE_VALUE(reg_offset, bit_num) (((reg_offset) << 16) | (bit_num & 0x1f)) - -#define PERIPH_REG(periph_base, value) REG32((periph_base + (value >> 16))) -#define PERIPH_REG_BIT(value) (0x1u << (value & 0x1f)) - -/** - * @} - */ - - - - - -/** @addtogroup Peripheral_registers_structures - * @{ - */ - -/* ================================================================================ */ -/* ================ ACC ================ */ -/* ================================================================================ */ - - -/** - * @brief HSI Auto Clock Calibration (ACC) - */ - -typedef struct -{ /*!< ACC Structure */ - __IO uint32_t STS; /*!< status register */ - __IO uint32_t CTRL1; /*!< control register 1 */ - __IO uint32_t CTRL2; /*!< control register 2 */ - __IO uint32_t CC1; /*!< compare value 1 */ - __IO uint32_t CC2; /*!< compare value 2 */ - __IO uint32_t CC3; /*!< compare value 3 */ -} ACC_TypeDef; - - -/* ================================================================================ */ -/* ================ ADC ================ */ -/* ================================================================================ */ - - -/** - * @brief Analog to digital converter (ADC) - */ - -typedef struct -{ /*!< ADC Structure */ - __IO uint32_t STS; /*!< status register */ - __IO uint32_t CTRL1; /*!< control register 1 */ - __IO uint32_t CTRL2; /*!< control register 2 */ - __IO uint32_t SPT1; /*!< sample time register 1 */ - __IO uint32_t SPT2; /*!< sample time register 2 */ - __IO uint32_t PCDTO1; /*!< Preempted channel 1 data offset register */ - __IO uint32_t PCDTO2; /*!< Preempted channel 2 data offset register */ - __IO uint32_t PCDTO3; /*!< Preempted channel 3 data offset register */ - __IO uint32_t PCDTO4; /*!< Preempted channel 4 data offset register */ - __IO uint32_t VMHB; /*!< Voltage monitoring high boundary register */ - __IO uint32_t VMLB; /*!< Voltage monitoring low boundary register */ - __IO uint32_t OSQ1; /*!< Ordinary sequence register 1 */ - __IO uint32_t OSQ2; /*!< Ordinary sequence register 2 */ - __IO uint32_t OSQ3; /*!< Ordinary sequence register 3 */ - __IO uint32_t PSQ; /*!< Preempted sequence register */ - __IO uint32_t PDT1; /*!< Preempted data register 1 */ - __IO uint32_t PDT2; /*!< Preempted data register 2 */ - __IO uint32_t PDT3; /*!< Preempted data register 3 */ - __IO uint32_t PDT4; /*!< Preempted data register 4 */ - __IO uint32_t ODT; /*!< Ordinary data register */ - __IO uint32_t RESERVED0[12]; - __IO uint32_t OVSP; /*!< oversampling register */ -} ADC_TypeDef; - - -/* ================================================================================ */ -/* ================ ADCCOM ================ */ -/* ================================================================================ */ - - -/** - * @brief ADC common area (ADCCOM) - */ - -typedef struct -{ /*!< ADCCOM Structure */ - __IO uint32_t RESERVED0; - __IO uint32_t CCTRL; /*!< Common control register */ -} ADCCOM_TypeDef; - - -/* ================================================================================ */ -/* ================ CAN ================ */ -/* ================================================================================ */ - - -/** - * @brief Controller Area Network (CAN) - */ -/** - * @brief Controller Area Network TX Mailbox Registers - */ - -typedef struct -{ - __IO uint32_t TMI; /*!< Transmit mailbox identifier register */ - __IO uint32_t TMC; /*!< Transmit mailbox data length and time stamp register */ - __IO uint32_t TMDTL; /*!< Transmit mailbox low byte data register */ - __IO uint32_t TMDTH; /*!< Transmit mailbox high byte data register */ -} CAN_TxMailBox_TypeDef; - -/** - * @brief Controller Area Network FIFO Mailbox Registers - */ - -typedef struct -{ - __IO uint32_t RFI; /*!< Receive FIFO register */ - __IO uint32_t RFC; /*!< Receive FIFO data length and time stamp register */ - __IO uint32_t RFDTL; /*!< Receive FIFO low byte data register */ - __IO uint32_t RFDTH; /*!< Receive FIFO high byte data register */ -} CAN_FIFOMailBox_TypeDef; - -/** - * @brief Controller Area Network Filter Registers - */ - -typedef struct -{ - __IO uint32_t FFB1; /*!< Filter bank filtrate bit register 1 */ - __IO uint32_t FFB2; /*!< Filter bank filtrate bit register 2 */ -} CAN_FilterRegister_TypeDef; - -/** - * @brief Controller Area Network - */ - -typedef struct -{ /*!< CAN Structure */ - __IO uint32_t MCTRL; /*!< Main control register */ - __IO uint32_t MSTS; /*!< Main status register */ - __IO uint32_t TSTS; /*!< Transmit status register */ - __IO uint32_t RF0; /*!< Receive FIFO 0 register */ - __IO uint32_t RF1; /*!< Receive FIFO 1 register */ - __IO uint32_t INTEN; /*!< Interrupt enable register */ - __IO uint32_t ESTS; /*!< Error status register */ - __IO uint32_t BTMG; /*!< Bit timing register */ - __IO uint32_t RESERVED0[88]; - CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< Transmit mailbox registers */ - CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< Receive FIFO registers */ - __IO uint32_t RESERVED1[12]; - __IO uint32_t FCTRL; /*!< Filter control register */ - __IO uint32_t FMCFG; /*!< Filter mode config register */ - __IO uint32_t RESERVED2; - __IO uint32_t FBWCFG; /*!< Filter bit width config register */ - __IO uint32_t RESERVED3; - __IO uint32_t FRF; /*!< Filter related FIFO register */ - __IO uint32_t RESERVED4; - __IO uint32_t FACFG; /*!< Filter activate configuration register */ - __IO uint32_t RESERVED5[8]; - CAN_FilterRegister_TypeDef sFilterRegister[14]; /*!< Filter registers */ -} CAN_TypeDef; - - -/* ================================================================================ */ -/* ================ CRC ================ */ -/* ================================================================================ */ - - -/** - * @brief CRC calculation unit (CRC) - */ - -typedef struct -{ /*!< CRC Structure */ - __IO uint32_t DT; /*!< Data register */ - __IO uint32_t CDT; /*!< Common data register */ - __IO uint32_t CTRL; /*!< Control register */ - __IO uint32_t RESERVED0; - __IO uint32_t IDT; /*!< Initial data register */ - __IO uint32_t POLY; /*!< Polynomial coefficient register */ -} CRC_TypeDef; - - -/* ================================================================================ */ -/* ================ CRM ================ */ -/* ================================================================================ */ - - -/** - * @brief Clock and reset management (CRM) - */ - -typedef struct -{ /*!< CRM Structure */ - __IO uint32_t CTRL; /*!< Clock control register */ - __IO uint32_t PLLCFG; /*!< PLL configuration register (CRM_PLLCFG) */ - __IO uint32_t CFG; /*!< Clock configuration register(CRM_CFG) */ - __IO uint32_t CLKINT; /*!< Clock interrupt register (CRM_CLKINT) */ - __IO uint32_t AHBRST1; /*!< AHB peripheral reset register1 (CRM_AHBRST1) */ - __IO uint32_t AHBRST2; /*!< AHB peripheral reset register 2 (CRM_AHBRST2) */ - __IO uint32_t AHBRST3; /*!< AHB peripheral reset register 3 (CRM_AHBRST3) */ - __IO uint32_t RESERVED0; - __IO uint32_t APB1RST; /*!< APB1 peripheral reset register (CRM_APB1RST) */ - __IO uint32_t APB2RST; /*!< APB2 peripheral reset register (CRM_APB2RST) */ - __IO uint32_t RESERVED1[2]; - __IO uint32_t AHBEN1; /*!< AHB Peripheral Clock enable register 1 (CRM_AHBEN1) */ - __IO uint32_t AHBEN2; /*!< AHB peripheral clock enable register 2 (CRM_AHBEN2) */ - __IO uint32_t AHBEN3; /*!< AHB peripheral clock enable register 3 (CRM_AHBEN3) */ - __IO uint32_t RESERVED2; - __IO uint32_t APB1EN; /*!< APB1 peripheral clock enable register (CRM_APB1EN) */ - __IO uint32_t APB2EN; /*!< APB2 peripheral clock enable register (CRM_APB2EN) */ - __IO uint32_t RESERVED3[2]; - __IO uint32_t AHBLPEN1; /*!< AHB Low-power Peripheral Clock enable register 1 (CRM_AHBLPEN1) */ - __IO uint32_t AHBLPEN2; /*!< AHB peripheral Low-power clock enable register 2 (CRM_AHBLPEN2) */ - __IO uint32_t AHBLPEN3; /*!< AHB peripheral Low-power clock enable register 3 (CRM_AHBLPEN3) */ - __IO uint32_t RESERVED4; - __IO uint32_t APB1LPEN; /*!< APB1 peripheral Low-power clock enable register (CRM_APB1LPEN) */ - __IO uint32_t APB2LPEN; /*!< APB2 peripheral Low-power clock enable register (CRM_APB2LPEN) */ - __IO uint32_t RESERVED5[2]; - __IO uint32_t BPDC; /*!< Battery powered domain control register (CRM_BPDC) */ - __IO uint32_t CTRLSTS; /*!< Control/status register (CRM_CTRLSTS) */ - __IO uint32_t OTGHS; /*!< OTGHS register */ - __IO uint32_t RESERVED6[9]; - __IO uint32_t MISC1; /*!< Miscellaneous register1 */ - __IO uint32_t MISC2; /*!< Miscellaneous register2 */ -} CRM_TypeDef; - - -/* ================================================================================ */ -/* ================ DEBUG ================ */ -/* ================================================================================ */ - - -/** - * @brief Debug support (DEBUG) - */ - -typedef struct -{ /*!< DEBUG Structure */ - __IO uint32_t IDCODE; /*!< DEBUG IDCODE */ - __IO uint32_t CTRL; /*!< DEBUG CTRL */ - __IO uint32_t APB1_PAUSE; /*!< DEBUG APB1 PAUSE */ - __IO uint32_t APB2_PAUSE; /*!< DEBUG APB2 PAUSE */ - __IO uint32_t RESERVED0[4]; - __IO uint32_t SER_ID; /*!< SERIES ID */ -} DEBUG_TypeDef; - - -/* ================================================================================ */ -/* ================ DMA ================ */ -/* ================================================================================ */ - - -/** - * @brief DMA controller (DMA) - */ - -typedef struct -{ /*!< DMA Structure */ - __IO uint32_t STS; /*!< DMA interrupt status register (DMA_STS) */ - __IO uint32_t CLR; /*!< DMA interrupt flag clear register (DMA_CLR) */ - __IO uint32_t RESERVED1[62]; - __IO uint32_t MUXSEL; /*!< DMAMUX Table Selection */ - __IO uint32_t RESERVED2[11]; - __IO uint32_t MUXSYNCSTS; /*!< Channel Interrupt Status Register */ - __IO uint32_t MUXSYNCCLR; /*!< Channel Interrupt Clear Flag Register */ - __IO uint32_t MUXGSTS; /*!< Generator Interrupt Status Register */ - __IO uint32_t MUXGCLR; /*!< Generator Interrupt Clear Flag Register */ -} DMA_TypeDef; - - -/* ================================================================================ */ -/* ================ DMA Channel ================ */ -/* ================================================================================ */ - - -/** - * @brief DMA controller Channel(DMA Channel) - */ -typedef struct -{ /*!< DMA Channel Structure */ - __IO uint32_t CTRL; /*!< DMA channel configuration register */ - __IO uint32_t DTCNT; /*!< DMA channel number of data to transfer register */ - __IO uint32_t PADDR; /*!< DMA channel peripheral base address register */ - __IO uint32_t MADDR; /*!< DMA channel memory base address register */ -} DMA_Channel_TypeDef; - - -/* ================================================================================ */ -/* ================ DMA MUX ================ */ -/* ================================================================================ */ - - -/** - * @brief DMA MUX controller - */ -typedef struct -{ - __IO uint32_t MUXCTRL; /*!< Channel Configuration Register */ - -} DMAMUX_Channel_TypeDef; - - -/* ================================================================================ */ -/* ================ DMA Generator ================ */ -/* ================================================================================ */ - - -/** - * @brief DMA MUX Generator Configuration - */ -typedef struct -{ - __IO uint32_t GCTRL; /*!< Generator Configuration Register */ - -} DMAMUX_Generator_TypeDef; - - -/* ================================================================================ */ -/* ================ ERTC ================ */ -/* ================================================================================ */ - - -/** - * @brief Real-time clock (ERTC) - */ - -typedef struct -{ /*!< ERTC Structure */ - __IO uint32_t TIME; /*!< time register */ - __IO uint32_t DATE; /*!< date register */ - __IO uint32_t CTRL; /*!< control register */ - __IO uint32_t STS; /*!< initialization and status register */ - __IO uint32_t DIV; /*!< Diveder register */ - __IO uint32_t WAT; /*!< Wakeup timer register */ - __IO uint32_t CCAL; /*!< Calibration register */ - __IO uint32_t ALA; /*!< Alarm A register */ - __IO uint32_t ALB; /*!< Alarm B register */ - __IO uint32_t WP; /*!< write protection register */ - __IO uint32_t SBS; /*!< sub second register */ - __IO uint32_t TADJ; /*!< time adjust register */ - __IO uint32_t TSTM; /*!< time stamp time register */ - __IO uint32_t TSDT; /*!< timestamp date register */ - __IO uint32_t TSSBS; /*!< timestamp sub second register */ - __IO uint32_t SCAL; /*!< calibration register */ - __IO uint32_t TAMP; /*!< tamper and alternate function configuration register */ - __IO uint32_t ALASBS; /*!< alarm A sub second register */ - __IO uint32_t ALBSBS; /*!< alarm B sub second register */ - __IO uint32_t RESERVED0; - __IO uint32_t BPR1; /*!< Battery powered domain register */ - __IO uint32_t BPR2; /*!< Battery powered domain register */ - __IO uint32_t BPR3; /*!< Battery powered domain register */ - __IO uint32_t BPR4; /*!< Battery powered domain register */ - __IO uint32_t BPR5; /*!< Battery powered domain register */ - __IO uint32_t BPR6; /*!< Battery powered domain register */ - __IO uint32_t BPR7; /*!< Battery powered domain register */ - __IO uint32_t BPR8; /*!< Battery powered domain register */ - __IO uint32_t BPR9; /*!< Battery powered domain register */ - __IO uint32_t BPR10; /*!< Battery powered domain register */ - __IO uint32_t BPR11; /*!< Battery powered domain register */ - __IO uint32_t BPR12; /*!< Battery powered domain register */ - __IO uint32_t BPR13; /*!< Battery powered domain register */ - __IO uint32_t BPR14; /*!< Battery powered domain register */ - __IO uint32_t BPR15; /*!< Battery powered domain register */ - __IO uint32_t BPR16; /*!< Battery powered domain register */ - __IO uint32_t BPR17; /*!< Battery powered domain register */ - __IO uint32_t BPR18; /*!< Battery powered domain register */ - __IO uint32_t BPR19; /*!< Battery powered domain register */ - __IO uint32_t BPR20; /*!< Battery powered domain register */ -} ERTC_TypeDef; - - -/* ================================================================================ */ -/* ================ EXINT ================ */ -/* ================================================================================ */ - - -/** - * @brief External Interrupt/Event Controller - */ - -typedef struct -{ /*!< EXINT Structure */ - __IO uint32_t INTEN; /*!< Interrupt enable register */ - __IO uint32_t EVTEN; /*!< Event enable register */ - __IO uint32_t POLCFG1; /*!< Rising polarity configuration register */ - __IO uint32_t POLCFG2; /*!< Falling polarity configuration register */ - __IO uint32_t SWTRG; /*!< Software triggle register */ - __IO uint32_t INTSTS; /*!< Interrupt status register */ -} EXINT_TypeDef; - - -/* ================================================================================ */ -/* ================ FLASH ================ */ -/* ================================================================================ */ - - -/** - * @brief Flash memory controler (FLASH) - */ - -typedef struct -{ /*!< FLASH Structure */ - __IO uint32_t PSR; /*!< Performance selection register */ - __IO uint32_t UNLOCK; /*!< Unlock register */ - __IO uint32_t USD_UNLOCK; /*!< USD unlock register */ - __IO uint32_t STS; /*!< Status register */ - __IO uint32_t CTRL; /*!< Control register */ - __IO uint32_t ADDR; /*!< Address register */ - __IO uint32_t RESERVED0; - __IO uint32_t USD; /*!< User system data register */ - __IO uint32_t EPPS; /*!< Erase/program protection status register */ - __IO uint32_t RESERVED1[20]; - __IO uint32_t SLIB_STS0; /*!< sLib status 0 register */ - __IO uint32_t SLIB_STS1; /*!< sLib status 1 register */ - __IO uint32_t SLIB_PWD_CLR; /*!< SLIB password clear register */ - __IO uint32_t SLIB_MISC_STS; /*!< sLib misc status register */ - __IO uint32_t CRC_ADDR; /*!< Flash CRC data start address register */ - __IO uint32_t CRC_CTRL; /*!< Flash CRC controll register */ - __IO uint32_t CRC_CHKR; /*!< FLASH CRC check result register */ - __IO uint32_t RESERVED2[52]; - __IO uint32_t SLIB_SET_PWD; /*!< sLib password setting register */ - __IO uint32_t SLIB_SET_RANGE; /*!< Configure sLib range register */ - __IO uint32_t EM_SLIB_SET; /*!< Extension momery slib set register */ - __IO uint32_t BTM_MODE_SET; /*!< Boot memory mode setting register */ - __IO uint32_t SLIB_UNLOCK; /*!< sLib unlock register */ -} FLASH_TypeDef; - - -/* ================================================================================ */ -/* ================ GPIO ================ */ -/* ================================================================================ */ - - -/** - * @brief General purpose I/Os (GPIO) - */ - -typedef struct -{ /*!< GPIO Structure */ - __IO uint32_t CFGR; /*!< GPIO configuration register */ - __IO uint32_t OMODE; /*!< GPIO output mode register */ - __IO uint32_t ODRVR; /*!< GPIO drive capability register */ - __IO uint32_t PULL; /*!< GPIO pull-up/pull-down register */ - __IO uint32_t IDT; /*!< GPIO input data register */ - __IO uint32_t ODT; /*!< GPIO output data register */ - __IO uint32_t SCR; /*!< Port bit set/clear register */ - __IO uint32_t WPR; /*!< Port write protect register */ - __IO uint32_t MUXL; /*!< GPIO muxing function low register */ - __IO uint32_t MUXH; /*!< GPIO muxing function high register */ - __IO uint32_t CLR; /*!< GPIO bit reset register */ - __IO uint32_t TOGR; /*!< GPIO bit toggle register */ - __IO uint32_t RESERVED0[3]; - __IO uint32_t HDRV; /*!< Huge current driver */ - __IO uint32_t SRCTR; -} GPIO_TypeDef; - - -/* ================================================================================ */ -/* ================ I2C ================ */ -/* ================================================================================ */ - - -/** - * @brief Inter-integrated circuit (I2C) - */ - -typedef struct -{ /*!< I2C Structure */ - __IO uint32_t CTRL1; /*!< Control register 1 */ - __IO uint32_t CTRL2; /*!< Control register 2 */ - __IO uint32_t OADDR1; /*!< Own address register 1 */ - __IO uint32_t OADDR2; /*!< Own address register 2 */ - __IO uint32_t CLKCTRL; /*!< Clock contorl register */ - __IO uint32_t TIMEOUT; /*!< Timeout register */ - __IO uint32_t STS; /*!< Interrupt and Status register */ - __IO uint32_t CLR; /*!< Interrupt clear register */ - __IO uint32_t PEC; /*!< PEC register */ - __IO uint32_t RXDT; /*!< Receive data register */ - __IO uint32_t TXDT; /*!< Transmit data register */ -} I2C_TypeDef; - - -/* ================================================================================ */ -/* ================ PWC ================ */ -/* ================================================================================ */ - - -/** - * @brief Power control (PWC) - */ - -typedef struct -{ /*!< PWC Structure */ - __IO uint32_t CTRL; /*!< Power control register (PWC_CTRL) */ - __IO uint32_t CTRLSTS; /*!< Power control and status register (PWC_CTRLSTS) */ - __IO uint32_t RESERVED0[2]; - __IO uint32_t LDOOV; /*!< LDO output voltage register */ -} PWC_TypeDef; - - -/* ================================================================================ */ -/* ================ QSPI ================ */ -/* ================================================================================ */ - - -/** - * @brief Quad SPI Controller (QSPI) - */ - -typedef struct -{ /*!< QSPI Structure */ - __IO uint32_t CMD_W0; /*!< Command word 0 */ - __IO uint32_t CMD_W1; /*!< Command word 1 */ - __IO uint32_t CMD_W2; /*!< Command word 2 */ - __IO uint32_t CMD_W3; /*!< Command word 3 */ - __IO uint32_t CTRL; /*!< Control register */ - __IO uint32_t RESERVED0; - __IO uint32_t FIFOSTS; /*!< FIFO Status register */ - __IO uint32_t RESERVED1; - __IO uint32_t CTRL2; /*!< control register 2 */ - __IO uint32_t CMDSTS; /*!< CMD status register */ - __IO uint32_t RSTS; /*!< SPI read status register */ - __IO uint32_t FSIZE; /*!< SPI flash size */ - __IO uint32_t XIP_CMD_W0; /*!< XIP command word 0 */ - __IO uint32_t XIP_CMD_W1; /*!< XIP command word 1 */ - __IO uint32_t XIP_CMD_W2; /*!< XIP command word 2 */ - __IO uint32_t XIP_CMD_W3; /*!< XIP command word 3 */ - __IO uint32_t CTRL3; /*!< control register 3 */ - __IO uint32_t RESERVED2[3]; - __IO uint32_t REV; /*!< Revision */ - __IO uint32_t RESERVED3[43]; - __IO uint32_t DT; /*!< 32/16/8 bit data port register */ -} QSPI1_TypeDef; - - -/* ================================================================================ */ -/* ================ SCFG ================ */ -/* ================================================================================ */ - - -/** - * @brief System configuration controller (SCFG) - */ - -typedef struct -{ /*!< SCFG Structure */ - __IO uint32_t CFG1; /*!< configuration register 1 */ - __IO uint32_t CFG2; /*!< configuration register 2 */ - __IO uint32_t EXINTC[4]; /*!< external interrupt configuration register 1,2,3,4 */ - __IO uint32_t RESERVED0[5]; - __IO uint32_t UHDRV; /*!< Ultra high drive register */ -} SCFG_TypeDef; - - -/* ================================================================================ */ -/* ================ SPI ================ */ -/* ================================================================================ */ - - -/** - * @brief Serial peripheral interface (SPI) - */ - -typedef struct -{ /*!< SPI Structure */ - __IO uint32_t CTRL1; /*!< control register 1 */ - __IO uint32_t CTRL2; /*!< control register 2 */ - __IO uint32_t STS; /*!< status register */ - __IO uint32_t DT; /*!< data register */ - __IO uint32_t CPOLY; /*!< CRC polynomial register */ - __IO uint32_t RCRC; /*!< Receive CRC register */ - __IO uint32_t TCRC; /*!< Transmit CRC register */ - __IO uint32_t I2SCTRL; /*!< I2S control register */ - __IO uint32_t I2SCLK; /*!< I2S clock register */ - __IO uint32_t RESERVED1[3]; - __IO uint32_t MISC1; /*!< I2S additional register */ -} SPI_TypeDef; - - -/* ================================================================================ */ -/* ================ TMR ================ */ -/* ================================================================================ */ - - -/** - * @brief timer (TMR) - */ - -typedef struct -{ /*!< TMR Structure */ - __IO uint32_t CTRL1; /*!< Control register 1 */ - __IO uint32_t CTRL2; /*!< Control register 2 */ - __IO uint32_t STCTRL; /*!< Subordinate TMR control register */ - __IO uint32_t IDEN; /*!< Interrupt/DMA enable register */ - __IO uint32_t ISTS; /*!< Interrupt status register */ - __IO uint32_t SWEVT; /*!< Software event register */ - __IO uint32_t CM1; /*!< Channel mode register 1 */ - __IO uint32_t CM2; /*!< Channel mode register 2 */ - __IO uint32_t CCTRL; /*!< Channel control register */ - __IO uint32_t CVAL; /*!< Counter value */ - __IO uint32_t DIV; /*!< Divider value */ - __IO uint32_t PR; /*!< Period value */ - __IO uint32_t RPR; /*!< Repetition of period value */ - __IO uint32_t C1DT; /*!< Channel 1 data register */ - __IO uint32_t C2DT; /*!< Channel 2 data register */ - __IO uint32_t C3DT; /*!< Channel 3 data register */ - __IO uint32_t C4DT; /*!< Channel 4 data register */ - __IO uint32_t BRK; /*!< Brake register */ - __IO uint32_t DMACTRL; /*!< DMA control register */ - __IO uint32_t DMADT; /*!< DMA data register */ - __IO uint32_t RMP; /*!< TMR input remap register */ - __IO uint32_t RESERVED0[7]; - __IO uint32_t CM3; /*!< Channel output mode register */ - __IO uint32_t C5DT; /*!< Channel 5 data register */ -} TMR_TypeDef; - - -/* ================================================================================ */ -/* ================ USART ================ */ -/* ================================================================================ */ - - -/** - * @brief Universal synchronous asynchronous receiver transmitter (USART) - */ - -typedef struct -{ /*!< USART Structure */ - __IO uint32_t STS; /*!< Status register */ - __IO uint32_t DT; /*!< Data register */ - __IO uint32_t BAUDR; /*!< Baud rate register */ - __IO uint32_t CTRL1; /*!< Control register 1 */ - __IO uint32_t CTRL2; /*!< Control register 2 */ - __IO uint32_t CTRL3; /*!< Control register 3 */ - __IO uint32_t GDIV; /*!< Guard time and division register */ - __IO uint32_t RTOV; /*!< Receiver time out value register */ - __IO uint32_t IFC; /*!< Interruption flag clear register */ -} USART_TypeDef; - - -/* ================================================================================ */ -/* ================ WDT ================ */ -/* ================================================================================ */ - - -/** - * @brief Watchdog (WDT) - */ - -typedef struct -{ /*!< WDT Structure */ - __IO uint32_t CMD; /*!< Command register */ - __IO uint32_t DIV; /*!< Division register */ - __IO uint32_t RLD; /*!< Reload register */ - __IO uint32_t STS; /*!< Status register */ - __IO uint32_t WIN; /*!< Window register */ -} WDT_TypeDef; - - - -/* ================================================================================ */ -/* ================ WWDT ================ */ -/* ================================================================================ */ - - -/** - * @brief Window watchdog (WWDT) - */ - -typedef struct -{ /*!< WWDT Structure */ - __IO uint32_t CTRL; /*!< Control register */ - __IO uint32_t CFG; /*!< Configuration register */ - __IO uint32_t STS; /*!< Status register */ -} WWDT_TypeDef; - - -/** - * @} - */ - -/** @addtogroup Peripheral_memory_map - * @{ - */ - -#define QSPI2_MEM_BASE ((uint32_t)0xB0000000) -#define QSPI2_REG_BASE ((uint32_t)0xA0002000) -#define QSPI1_REG_BASE ((uint32_t)0xA0001000) -#define QSPI1_MEM_BASE ((uint32_t)0x90000000) -#define PERIPH_BASE ((uint32_t)0x40000000) -#define SRAM_BB_BASE ((uint32_t)0x22000000) -#define PERIPH_BB_BASE ((uint32_t)0x42000000) -#define SRAM_BASE ((uint32_t)0x20000000) -#define USD_BASE ((uint32_t)0x1FFFF800) -#define FLASH_BASE ((uint32_t)0x08000000) - -#define DEBUG_BASE ((uint32_t)0xE0042000) - -#define APB1PERIPH_BASE (PERIPH_BASE) -#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) -#define AHBPERIPH1_BASE (PERIPH_BASE + 0x20000) -#define AHBPERIPH2_BASE (PERIPH_BASE + 0x10000000) - -/* apb1 bus base address */ -#define UART8_BASE (APB1PERIPH_BASE + 0x7C00) -#define UART7_BASE (APB1PERIPH_BASE + 0x7800) -#define PWC_BASE (APB1PERIPH_BASE + 0x7000) -#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) -#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00) -#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) -#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) -#define USART5_BASE (APB1PERIPH_BASE + 0x5000) -#define USART4_BASE (APB1PERIPH_BASE + 0x4C00) -#define USART3_BASE (APB1PERIPH_BASE + 0x4800) -#define USART2_BASE (APB1PERIPH_BASE + 0x4400) -#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) -#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) -#define WDT_BASE (APB1PERIPH_BASE + 0x3000) -#define WWDT_BASE (APB1PERIPH_BASE + 0x2C00) -#define ERTC_BASE (APB1PERIPH_BASE + 0x2800) -#define TMR14_BASE (APB1PERIPH_BASE + 0x2000) -#define TMR13_BASE (APB1PERIPH_BASE + 0x1C00) -#define TMR7_BASE (APB1PERIPH_BASE + 0x1400) -#define TMR6_BASE (APB1PERIPH_BASE + 0x1000) -#define TMR4_BASE (APB1PERIPH_BASE + 0x0800) -#define TMR3_BASE (APB1PERIPH_BASE + 0x0400) -#define TMR2_BASE (APB1PERIPH_BASE + 0x0000) -/* apb2 bus base address */ -#define OTGHS_PHY_BASE (APB2PERIPH_BASE + 0x7C00) -#define ACC_BASE (APB2PERIPH_BASE + 0x7400) -#define I2SF5_BASE (APB2PERIPH_BASE + 0x5000) -#define TMR11_BASE (APB2PERIPH_BASE + 0x4800) -#define TMR10_BASE (APB2PERIPH_BASE + 0x4400) -#define TMR9_BASE (APB2PERIPH_BASE + 0x4000) -#define EXINT_BASE (APB2PERIPH_BASE + 0x3C00) -#define SCFG_BASE (APB2PERIPH_BASE + 0x3800) -#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) -#define ADC1_BASE (APB2PERIPH_BASE + 0x2000) -#define ADCCOM_BASE (APB2PERIPH_BASE + 0x2300) -#define USART6_BASE (APB2PERIPH_BASE + 0x1400) -#define USART1_BASE (APB2PERIPH_BASE + 0x1000) -#define TMR1_BASE (APB2PERIPH_BASE + 0x0000) -/* ahb bus base address */ -#define GPIOF_BASE (AHBPERIPH1_BASE + 0x1400) -#define GPIOD_BASE (AHBPERIPH1_BASE + 0x0C00) -#define GPIOC_BASE (AHBPERIPH1_BASE + 0x0800) -#define GPIOB_BASE (AHBPERIPH1_BASE + 0x0400) -#define GPIOA_BASE (AHBPERIPH1_BASE + 0x0000) - -#define DMA1_BASE (AHBPERIPH1_BASE + 0x6000) -#define DMA1_CHANNEL1_BASE (DMA1_BASE + 0x0008) -#define DMA1_CHANNEL2_BASE (DMA1_BASE + 0x001C) -#define DMA1_CHANNEL3_BASE (DMA1_BASE + 0x0030) -#define DMA1_CHANNEL4_BASE (DMA1_BASE + 0x0044) -#define DMA1_CHANNEL5_BASE (DMA1_BASE + 0x0058) -#define DMA1_CHANNEL6_BASE (DMA1_BASE + 0x006C) -#define DMA1_CHANNEL7_BASE (DMA1_BASE + 0x0080) - -#define DMA1MUX_BASE (DMA1_BASE + 0x0104) -#define DMA1MUX_CHANNEL1_BASE (DMA1MUX_BASE) -#define DMA1MUX_CHANNEL2_BASE (DMA1MUX_BASE + 0x0004) -#define DMA1MUX_CHANNEL3_BASE (DMA1MUX_BASE + 0x0008) -#define DMA1MUX_CHANNEL4_BASE (DMA1MUX_BASE + 0x000C) -#define DMA1MUX_CHANNEL5_BASE (DMA1MUX_BASE + 0x0010) -#define DMA1MUX_CHANNEL6_BASE (DMA1MUX_BASE + 0x0014) -#define DMA1MUX_CHANNEL7_BASE (DMA1MUX_BASE + 0x0018) - -#define DMA1MUX_GENERATOR1_BASE (DMA1_BASE + 0x0120) -#define DMA1MUX_GENERATOR2_BASE (DMA1_BASE + 0x0124) -#define DMA1MUX_GENERATOR3_BASE (DMA1_BASE + 0x0128) -#define DMA1MUX_GENERATOR4_BASE (DMA1_BASE + 0x012C) - -#define DMA2_BASE (AHBPERIPH1_BASE + 0x6400) -#define DMA2_CHANNEL1_BASE (DMA2_BASE + 0x0008) -#define DMA2_CHANNEL2_BASE (DMA2_BASE + 0x001C) -#define DMA2_CHANNEL3_BASE (DMA2_BASE + 0x0030) -#define DMA2_CHANNEL4_BASE (DMA2_BASE + 0x0044) -#define DMA2_CHANNEL5_BASE (DMA2_BASE + 0x0058) -#define DMA2_CHANNEL6_BASE (DMA2_BASE + 0x006C) -#define DMA2_CHANNEL7_BASE (DMA2_BASE + 0x0080) - -#define DMA2MUX_BASE (DMA2_BASE + 0x0104) -#define DMA2MUX_CHANNEL1_BASE (DMA2MUX_BASE) -#define DMA2MUX_CHANNEL2_BASE (DMA2MUX_BASE + 0x0004) -#define DMA2MUX_CHANNEL3_BASE (DMA2MUX_BASE + 0x0008) -#define DMA2MUX_CHANNEL4_BASE (DMA2MUX_BASE + 0x000C) -#define DMA2MUX_CHANNEL5_BASE (DMA2MUX_BASE + 0x0010) -#define DMA2MUX_CHANNEL6_BASE (DMA2MUX_BASE + 0x0014) -#define DMA2MUX_CHANNEL7_BASE (DMA2MUX_BASE + 0x0018) - -#define DMA2MUX_GENERATOR1_BASE (DMA2_BASE + 0x0120) -#define DMA2MUX_GENERATOR2_BASE (DMA2_BASE + 0x0124) -#define DMA2MUX_GENERATOR3_BASE (DMA2_BASE + 0x0128) -#define DMA2MUX_GENERATOR4_BASE (DMA2_BASE + 0x012C) - -#define FLASH_REG_BASE (AHBPERIPH1_BASE + 0x3C00) -#define CRM_BASE (AHBPERIPH1_BASE + 0x3800) -#define CRC_BASE (AHBPERIPH1_BASE + 0x3000) -#define OTGHS_BASE (AHBPERIPH1_BASE + 0x20000) -#define OTGFS1_BASE (AHBPERIPH2_BASE + 0x00000) - -/** - * @} - */ - - -/** @addtogroup Peripheral_instance - * @{ - */ - -#define EXINT ((EXINT_TypeDef *) EXINT_BASE) -#define CRM ((CRM_TypeDef *) CRM_BASE) -#define PWC ((PWC_TypeDef *) PWC_BASE) -#define FLASH ((FLASH_TypeDef *) FLASH_REG_BASE) -#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) -#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) -#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) -#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) -#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) -#define SCFG ((SCFG_TypeDef *) SCFG_BASE) -#define TMR1 ((TMR_TypeDef *) TMR1_BASE) -#define TMR2 ((TMR_TypeDef *) TMR2_BASE) -#define TMR3 ((TMR_TypeDef *) TMR3_BASE) -#define TMR4 ((TMR_TypeDef *) TMR4_BASE) -#define TMR6 ((TMR_TypeDef *) TMR6_BASE) -#define TMR7 ((TMR_TypeDef *) TMR7_BASE) -#define TMR9 ((TMR_TypeDef *) TMR9_BASE) -#define TMR10 ((TMR_TypeDef *) TMR10_BASE) -#define TMR11 ((TMR_TypeDef *) TMR11_BASE) -#define TMR13 ((TMR_TypeDef *) TMR13_BASE) -#define TMR14 ((TMR_TypeDef *) TMR14_BASE) -#define DEBUGMCU ((DEBUG_TypeDef *) DEBUG_BASE) -#define DEBUG ((DEBUG_TypeDef *) DEBUG_BASE) -#define DMA1 ((DMA_TypeDef *) DMA1_BASE) -#define DMA2 ((DMA_TypeDef *) DMA2_BASE) -#define DMA1_CHANNEL1 ((DMA_Channel_TypeDef *) DMA1_CHANNEL1_BASE) -#define DMA1_CHANNEL2 ((DMA_Channel_TypeDef *) DMA1_CHANNEL2_BASE) -#define DMA1_CHANNEL3 ((DMA_Channel_TypeDef *) DMA1_CHANNEL3_BASE) -#define DMA1_CHANNEL4 ((DMA_Channel_TypeDef *) DMA1_CHANNEL4_BASE) -#define DMA1_CHANNEL5 ((DMA_Channel_TypeDef *) DMA1_CHANNEL5_BASE) -#define DMA1_CHANNEL6 ((DMA_Channel_TypeDef *) DMA1_CHANNEL6_BASE) -#define DMA1_CHANNEL7 ((DMA_Channel_TypeDef *) DMA1_CHANNEL7_BASE) -#define DMA2_CHANNEL1 ((DMA_Channel_TypeDef *) DMA2_CHANNEL1_BASE) -#define DMA2_CHANNEL2 ((DMA_Channel_TypeDef *) DMA2_CHANNEL2_BASE) -#define DMA2_CHANNEL3 ((DMA_Channel_TypeDef *) DMA2_CHANNEL3_BASE) -#define DMA2_CHANNEL4 ((DMA_Channel_TypeDef *) DMA2_CHANNEL4_BASE) -#define DMA2_CHANNEL5 ((DMA_Channel_TypeDef *) DMA2_CHANNEL5_BASE) -#define DMA2_CHANNEL6 ((DMA_Channel_TypeDef *) DMA2_CHANNEL6_BASE) -#define DMA2_CHANNEL7 ((DMA_Channel_TypeDef *) DMA2_CHANNEL7_BASE) -#define DMA1MUX_CHANNEL1 ((DMAMUX_Channel_TypeDef *) DMA1MUX_CHANNEL1_BASE) -#define DMA1MUX_CHANNEL2 ((DMAMUX_Channel_TypeDef *) DMA1MUX_CHANNEL2_BASE) -#define DMA1MUX_CHANNEL3 ((DMAMUX_Channel_TypeDef *) DMA1MUX_CHANNEL3_BASE) -#define DMA1MUX_CHANNEL4 ((DMAMUX_Channel_TypeDef *) DMA1MUX_CHANNEL4_BASE) -#define DMA1MUX_CHANNEL5 ((DMAMUX_Channel_TypeDef *) DMA1MUX_CHANNEL5_BASE) -#define DMA1MUX_CHANNEL6 ((DMAMUX_Channel_TypeDef *) DMA1MUX_CHANNEL6_BASE) -#define DMA1MUX_CHANNEL7 ((DMAMUX_Channel_TypeDef *) DMA1MUX_CHANNEL7_BASE) -#define DMA2MUX_CHANNEL1 ((DMAMUX_Channel_TypeDef *) DMA2MUX_CHANNEL1_BASE) -#define DMA2MUX_CHANNEL2 ((DMAMUX_Channel_TypeDef *) DMA2MUX_CHANNEL2_BASE) -#define DMA2MUX_CHANNEL3 ((DMAMUX_Channel_TypeDef *) DMA2MUX_CHANNEL3_BASE) -#define DMA2MUX_CHANNEL4 ((DMAMUX_Channel_TypeDef *) DMA2MUX_CHANNEL4_BASE) -#define DMA2MUX_CHANNEL5 ((DMAMUX_Channel_TypeDef *) DMA2MUX_CHANNEL5_BASE) -#define DMA2MUX_CHANNEL6 ((DMAMUX_Channel_TypeDef *) DMA2MUX_CHANNEL6_BASE) -#define DMA2MUX_CHANNEL7 ((DMAMUX_Channel_TypeDef *) DMA2MUX_CHANNEL7_BASE) -#define DMA1MUX_GENERATOR1 ((DMAMUX_Generator_TypeDef *) DMA1MUX_GENERATOR1_BASE) -#define DMA1MUX_GENERATOR2 ((DMAMUX_Generator_TypeDef *) DMA1MUX_GENERATOR2_BASE) -#define DMA1MUX_GENERATOR3 ((DMAMUX_Generator_TypeDef *) DMA1MUX_GENERATOR3_BASE) -#define DMA1MUX_GENERATOR4 ((DMAMUX_Generator_TypeDef *) DMA1MUX_GENERATOR4_BASE) -#define DMA2MUX_GENERATOR1 ((DMAMUX_Generator_TypeDef *) DMA2MUX_GENERATOR1_BASE) -#define DMA2MUX_GENERATOR2 ((DMAMUX_Generator_TypeDef *) DMA2MUX_GENERATOR2_BASE) -#define DMA2MUX_GENERATOR3 ((DMAMUX_Generator_TypeDef *) DMA2MUX_GENERATOR3_BASE) -#define DMA2MUX_GENERATOR4 ((DMAMUX_Generator_TypeDef *) DMA2MUX_GENERATOR4_BASE) -#define ADC1 ((ADC_TypeDef *) ADC1_BASE) -#define ADCCOM ((ADCCOM_TypeDef *) ADCCOM_BASE) -#define I2C1 ((I2C_TypeDef *) I2C1_BASE) -#define I2C2 ((I2C_TypeDef *) I2C2_BASE) -#define I2C3 ((I2C_TypeDef *) I2C3_BASE) -#define USART1 ((USART_TypeDef *) USART1_BASE) -#define USART2 ((USART_TypeDef *) USART2_BASE) -#define USART3 ((USART_TypeDef *) USART3_BASE) -#define UART4 ((USART_TypeDef *) USART4_BASE) -#define UART5 ((USART_TypeDef *) USART5_BASE) -#define USART6 ((USART_TypeDef *) USART6_BASE) -#define UART7 ((USART_TypeDef *) UART7_BASE) -#define UART8 ((USART_TypeDef *) UART8_BASE) -#define SPI1 ((SPI_TypeDef *) SPI1_BASE) -#define SPI2 ((SPI_TypeDef *) SPI2_BASE) -#define SPI3 ((SPI_TypeDef *) SPI3_BASE) -#define I2SF5 ((SPI_TypeDef *) I2SF5_BASE) -#define ERTC ((ERTC_TypeDef *)ERTC_BASE) - -/** - * @} - */ - -/** @defgroup FLASH_unlock_keys - * @brief flash unlock keys - * @{ - */ - -#define FLASH_UNLOCK_KEY1 ((uint32_t)0x45670123) /*!< flash operation unlock order key1 */ -#define FLASH_UNLOCK_KEY2 ((uint32_t)0xCDEF89AB) /*!< flash operation unlock order key2 */ -#define FAP_RELIEVE_KEY ((uint16_t)0x00A5) /*!< flash fap relieve key val */ -#define FAP_HIGH_LEVEL_KEY ((uint16_t)0x00CC) /*!< flash fap high level enable key val */ -#define SLIB_UNLOCK_KEY ((uint32_t)0xA35F6D24) /*!< flash slib operation unlock order key */ - -#define FLASHSIZE_BASE ((uint32_t)0x1FFFF7E0U) /*!< FLASH Size register base address */ -#define UID_BASE ((uint32_t)0x1FFFF7E8U) /*!< Unique device ID register base address */ - -/** - * @} - */ - - -/** @addtogroup Peripheral_Registers_Bits_Definition - * @{ - */ - - -/* =========================================================================================================================== */ -/* ================ ADC ================ */ -/* =========================================================================================================================== */ - -/****************** Bit definition for ADC_STS register ***************/ -#define ADC_STS_VMOR (0x1U << 0) -#define ADC_STS_OCCC (0x1U << 1) -#define ADC_STS_CCE (0x1U << 1) -#define ADC_STS_PCCE (0x1U << 2) -#define ADC_STS_PCCS (0x1U << 3) -#define ADC_STS_OCCS (0x1U << 4) - -/****************** Bit definition for ADC_CTRL1 register ***************/ -#define ADC_CTRL1_CCEIEN (0x1U << 5) -#define ADC_CTRL1_VMORIEN (0x1U << 6) -#define ADC_CTRL1_PCCEIEN (0x1U << 7) -#define ADC_CTRL1_SQEN (0x1U << 8) -#define ADC_CTRL1_VMSGEN (0x1U << 9) -#define ADC_CTRL1_PCAUTOEN (0x1U << 10) -#define ADC_CTRL1_OCPEN (0x1U << 11) -#define ADC_CTRL1_PCPEN (0x1U << 12) -#define ADC_CTRL1_PCVMEN (0x1U << 22) -#define ADC_CTRL1_OCVMEN (0x1U << 23) -#define ADC_CTRL1_OCCOIE (0x1U << 26) - -/****************** Bit definition for ADC_CTRL2 register *******************/ -#define ADC_CTRL2_ADCEN (0x1U << 0) -#define ADC_CTRL2_RPEN (0x1U << 1) -#define ADC_CTRL2_ADCAL (0x1U << 2) -#define ADC_CTRL2_ADCALINIT (0x1U << 3) -#define ADC_CTRL2_OCDMAEN (0x1U << 8) -#define ADC_CTRL2_DTALIGN (0x1U << 11) -#define ADC_CTRL2_DTALIGN_R (0x0U << 11) -#define ADC_CTRL2_DTALIGN_L (0x1U << 11) -#define ADC_CTRL2_PCTEN (0x1U << 15) -#define ADC_CTRL2_OCTEN (0x1U << 20) -#define ADC_CTRL2_PCSWTRG (0x1U << 21) -#define ADC_CTRL2_OCSWTRG (0x1U << 22) -#define ADC_CTRL2_ITSRVEN (0x1U << 23) - -/****************** Bit definition for ADC_VMHB register ***************/ -#define ADC_VMHB_HB (0xFFFFU << 0) - -/****************** Bit definition for ADC_VMLB register ***************/ -#define ADC_VMLB_LB (0x0000U << 0) - - -/* =========================================================================================================================== */ -/* ================ CRM ================ */ -/* =========================================================================================================================== */ -/****************** Bit definition for CRM_CTRL register *****************/ -#define CRM_CTRL_HICKEN (0x1U << 0) -#define CRM_CTRL_HICKSTBL (0x1U << 1) -#define CRM_CTRL_HICKTRIM (0x3FU << 2) -#define CRM_CTRL_HEXTEN (0x1U << 16) -#define CRM_CTRL_HEXTSTBL (0x1U << 17) -#define CRM_CTRL_HEXTBYPS (0x1U << 18) -#define CRM_CTRL_CFDEN (0x1U << 19) -#define CRM_CTRL_PLLEN (0x1U << 24) -#define CRM_CTRL_PLLSTBL (0x1U << 25) -#define CRM_CTRL_PLLUSTBL (0x1U << 26) - -/****************** Bit definition for CRM_PLLCFG register *****************/ -#define CRM_PLLCFG_PLLUEN (0x1U << 29) -#define CRM_PLLCFG_PLLRCS (0x1U << 30) - -/****************** Bit definition for CRM_CFG register ******************/ -#define CRM_CFG_SCLKSEL (0x3U << 0) -#define CRM_CFG_SCLK_HICK (0x0U << 0) -#define CRM_CFG_SCLK_HEXT (0x1U << 0) -#define CRM_CFG_SCLK_PLL (0x2U << 0) -#define CRM_CFG_SCLKSTS (0x3U << 2) -#define CRM_CFG_SCLKSTS_HICK (0x0U << 2) -#define CRM_CFG_SCLKSTS_HEXT (0x1U << 2) -#define CRM_CFG_SCLKSTS_PLL (0x2U << 2) - -/***************** Bit definition for CRM_AHBRST1 register ***************/ -#define CRM_AHBRST1_GPIOARST (0x1U << 0) -#define CRM_AHBRST1_GPIOBRST (0x1U << 1) -#define CRM_AHBRST1_GPIOCRST (0x1U << 2) -#define CRM_AHBRST1_GPIODRST (0x1U << 3) -#define CRM_AHBRST1_GPIOFRST (0x1U << 5) -#define CRM_AHBRST1_CRCRST (0x1U << 12) -#define CRM_AHBRST1_DMA1RST (0x1U << 22) -#define CRM_AHBRST1_DMA2RST (0x1U << 24) -#define CRM_AHBRST1_OTGHSRST (0x1U << 29) - -/***************** Bit definition for CRM_AHBRST2 register ***************/ -#define CRM_AHBRST2_OTGFS1RST (0x1U << 7) - -/***************** Bit definition for CRM_AHBRST3 register ***************/ -#define CRM_AHBRST3_QSPI1RST (0x1U << 1) - -/***************** Bit definition for CRM_APB1RST register ***************/ -#define CRM_APB1RST_TMR2RST (0x1U << 0) -#define CRM_APB1RST_TMR3RST (0x1U << 1) -#define CRM_APB1RST_TMR4RST (0x1U << 2) -#define CRM_APB1RST_TMR6RST (0x1U << 4) -#define CRM_APB1RST_TMR7RST (0x1U << 5) -#define CRM_APB1RST_TMR13RST (0x1U << 7) -#define CRM_APB1RST_TMR14RST (0x1U << 8) -#define CRM_APB1RST_WWDTRST (0x1U << 11) -#define CRM_APB1RST_SPI2RST (0x1U << 14) -#define CRM_APB1RST_SPI3RST (0x1U << 15) -#define CRM_APB1RST_USART2RST (0x1U << 17) -#define CRM_APB1RST_USART3RST (0x1U << 18) -#define CRM_APB1RST_USART4RST (0x1U << 19) -#define CRM_APB1RST_USART5RST (0x1U << 20) -#define CRM_APB1RST_I2C1RST (0x1U << 21) -#define CRM_APB1RST_I2C2RST (0x1U << 22) -#define CRM_APB1RST_I2C3RST (0x1U << 23) -#define CRM_APB1RST_CAN1RST (0x1U << 25) -#define CRM_APB1RST_PWCRST (0x1U << 28) -#define CRM_APB1RST_UART7RST (0x1U << 30) -#define CRM_APB1RST_UART8RST (0x1U << 31) - -/***************** Bit definition for CRM_APB2RST register ***************/ -#define CRM_APB2RST_TMR1RST (0x1U << 0) -#define CRM_APB2RST_USART1RST (0x1U << 4) -#define CRM_APB2RST_USART6RST (0x1U << 5) -#define CRM_APB2RST_ADC1RST (0x1U << 8) -#define CRM_APB2RST_SPI1RST (0x1U << 12) -#define CRM_APB2RST_SCFGRST (0x1U << 14) -#define CRM_APB2RST_TMR9RST (0x1U << 16) -#define CRM_APB2RST_TMR10RST (0x1U << 17) -#define CRM_APB2RST_TMR11RST (0x1U << 18) -#define CRM_APB2RST_I2SF5RST (0x1U << 20) -#define CRM_APB2RST_ACCRST (0x1U << 29) - -/***************** Bit definition for CRM_AHBEN1 register ***************/ -#define CRM_AHBEN1_GPIOAEN (0x1U << 0) -#define CRM_AHBEN1_GPIOBEN (0x1U << 1) -#define CRM_AHBEN1_GPIOCEN (0x1U << 2) -#define CRM_AHBEN1_GPIODEN (0x1U << 3) -#define CRM_AHBEN1_GPIOFEN (0x1U << 5) -#define CRM_AHBEN1_CRCEN (0x1U << 12) -#define CRM_AHBEN1_DMA1EN (0x1U << 22) -#define CRM_AHBEN1_DMA2EN (0x1U << 24) -#define CRM_AHBEN1_OTGHSEN (0x1U << 29) - -/***************** Bit definition for CRM_AHBEN2 register ***************/ -#define CRM_AHBEN2_OTGFS1EN (0x1U << 7) - -/***************** Bit definition for CRM_AHBEN3 register ***************/ -#define CRM_AHBEN3_QSPI1EN (0x1U << 1) - -/***************** Bit definition for CRM_APB1EN register ***************/ -#define CRM_APB1EN_TMR2EN (0x1U << 0) -#define CRM_APB1EN_TMR3EN (0x1U << 1) -#define CRM_APB1EN_TMR4EN (0x1U << 2) -#define CRM_APB1EN_TMR6EN (0x1U << 4) -#define CRM_APB1EN_TMR7EN (0x1U << 5) -#define CRM_APB1EN_TMR13EN (0x1U << 7) -#define CRM_APB1EN_TMR14EN (0x1U << 8) -#define CRM_APB1EN_WWDTEN (0x1U << 11) -#define CRM_APB1EN_SPI2EN (0x1U << 14) -#define CRM_APB1EN_SPI3EN (0x1U << 15) -#define CRM_APB1EN_USART2EN (0x1U << 17) -#define CRM_APB1EN_USART3EN (0x1U << 18) -#define CRM_APB1EN_USART4EN (0x1U << 19) -#define CRM_APB1EN_USART5EN (0x1U << 20) -#define CRM_APB1EN_I2C1EN (0x1U << 21) -#define CRM_APB1EN_I2C2EN (0x1U << 22) -#define CRM_APB1EN_I2C3EN (0x1U << 23) -#define CRM_APB1EN_CAN1EN (0x1U << 25) -#define CRM_APB1EN_PWCEN (0x1U << 28) -#define CRM_APB1EN_UART7EN (0x1U << 30) -#define CRM_APB1EN_UART8EN (0x1U << 31) - -/***************** Bit definition for CRM_APB2EN register ***************/ -#define CRM_APB2EN_TMR1EN (0x1U << 0) -#define CRM_APB2EN_USART1EN (0x1U << 4) -#define CRM_APB2EN_USART6EN (0x1U << 5) -#define CRM_APB2EN_ADC1EN (0x1U << 8) -#define CRM_APB2EN_SPI1EN (0x1U << 12) -#define CRM_APB2EN_SCFGEN (0x1U << 14) -#define CRM_APB2EN_TMR9EN (0x1U << 16) -#define CRM_APB2EN_TMR10EN (0x1U << 17) -#define CRM_APB2EN_TMR11EN (0x1U << 18) -#define CRM_APB2EN_I2SF5EN (0x1U << 20) -#define CRM_APB2EN_ACCEN (0x1U << 29) - -/***************** Bit definition for CRM_AHBLPEN1 register ***************/ -#define CRM_AHBLPEN1_GPIOALPEN (0x1U << 0) -#define CRM_AHBLPEN1_GPIOBLPEN (0x1U << 1) -#define CRM_AHBLPEN1_GPIOCLPEN (0x1U << 2) -#define CRM_AHBLPEN1_GPIODLPEN (0x1U << 3) -#define CRM_AHBLPEN1_GPIOFLPEN (0x1U << 5) -#define CRM_AHBLPEN1_CRCLPEN (0x1U << 12) -#define CRM_AHBLPEN1_DMA1LPEN (0x1U << 22) -#define CRM_AHBLPEN1_DMA2LPEN (0x1U << 24) -#define CRM_AHBLPEN1_OTGHSLPEN (0x1U << 29) - -/***************** Bit definition for CRM_AHBLPEN2 register ***************/ -#define CRM_AHBLPEN2_OTGFS1LPEN (0x1U << 7) - -/***************** Bit definition for CRM_AHBLPEN3 register ***************/ -#define CRM_AHBLPEN3_QSPI1LPEN (0x1U << 1) - -/***************** Bit definition for CRM_APB1LPEN register ***************/ -#define CRM_APB1LPEN_TMR2LPEN (0x1U << 0) -#define CRM_APB1LPEN_TMR3LPEN (0x1U << 1) -#define CRM_APB1LPEN_TMR4LPEN (0x1U << 2) -#define CRM_APB1LPEN_TMR6LPEN (0x1U << 4) -#define CRM_APB1LPEN_TMR7LPEN (0x1U << 5) -#define CRM_APB1LPEN_TMR13LPEN (0x1U << 7) -#define CRM_APB1LPEN_TMR14LPEN (0x1U << 8) -#define CRM_APB1LPEN_WWDTLPEN (0x1U << 11) -#define CRM_APB1LPEN_SPI2LPEN (0x1U << 14) -#define CRM_APB1LPEN_SPI3LPEN (0x1U << 15) -#define CRM_APB1LPEN_USART2LPEN (0x1U << 17) -#define CRM_APB1LPEN_USART3LPEN (0x1U << 18) -#define CRM_APB1LPEN_USART4LPEN (0x1U << 19) -#define CRM_APB1LPEN_USART5LPEN (0x1U << 20) -#define CRM_APB1LPEN_I2C1LPEN (0x1U << 21) -#define CRM_APB1LPEN_I2C2LPEN (0x1U << 22) -#define CRM_APB1LPEN_I2C3LPEN (0x1U << 23) -#define CRM_APB1LPEN_CAN1LPEN (0x1U << 25) -#define CRM_APB1LPEN_PWCLPEN (0x1U << 28) -#define CRM_APB1LPEN_UART7LPEN (0x1U << 30) -#define CRM_APB1LPEN_UART8LPEN (0x1U << 31) - -/***************** Bit definition for CRM_APB2LPEN register ***************/ -#define CRM_APB2LPEN_TMR1LPEN (0x1U << 0) -#define CRM_APB2LPEN_USART1LPEN (0x1U << 4) -#define CRM_APB2LPEN_USART6LPEN (0x1U << 5) -#define CRM_APB2LPEN_ADC1LPEN (0x1U << 8) -#define CRM_APB2LPEN_SPI1LPEN (0x1U << 12) -#define CRM_APB2LPEN_SCFGLPEN (0x1U << 14) -#define CRM_APB2LPEN_TMR9LPEN (0x1U << 16) -#define CRM_APB2LPEN_TMR10LPEN (0x1U << 17) -#define CRM_APB2LPEN_TMR11LPEN (0x1U << 18) -#define CRM_APB2LPEN_I2SF5LPEN (0x1U << 20) -#define CRM_APB2LPEN_ACCLPEN (0x1U << 29) - -/****************** Bit definition for CRM_BPDC register *****************/ -#define CRM_BPDC_LEXTEN (0x1U << 0) -#define CRM_BPDC_LEXTSTBL (0x1U << 1) -#define CRM_BPDC_LEXTBYPS (0x1U << 2) -#define CRM_BPDC_ERTCSEL (0x3U << 8) -#define CRM_BPDC_ERTCSEL_LEXT (0x1U << 8) -#define CRM_BPDC_ERTCSEL_LICK (0x2U << 8) -#define CRM_BPDC_ERTCSEL_HEXTDIV (0x3U << 8) -#define CRM_BPDC_ERTCEN (0x1U << 15) -#define CRM_BPDC_BPDRST (0x1U << 16) - -/****************** Bit definition for CRM_CTRLSTS register **************/ -#define CRM_CTRLSTS_LICKEN (0x1U << 0) -#define CRM_CTRLSTS_LICKSTBL (0x1U << 1) -#define CRM_CTRLSTS_RSTFC (0x1U << 24) -#define CRM_CTRLSTS_NRSTF (0x1U << 26) -#define CRM_CTRLSTS_PORRSTF (0x1U << 27) -#define CRM_CTRLSTS_SWRSTF (0x1U << 28) -#define CRM_CTRLSTS_WDTRSTF (0x1U << 29) -#define CRM_CTRLSTS_WWDTRSTF (0x1U << 30) -#define CRM_CTRLSTS_LPRSTF (0x1U << 31) - -/****************** Bit definition for CRM_OTGHS register ****************/ -#define CRM_OTGHS_USBHS_PHY12_SEL (0x1U << 4) -#define CRM_OTGHS_USBHS_PHY12_SEL_HEXT (0x0U << 4) - -/****************** Bit definition for CRM_MISC1 register ****************/ -#define CRM_MISC1_HICKDIV (0x1U << 12) -#define CRM_MISC1_HICK_TO_SCLK (0x1U << 14) - -/****************** Bit definition for CRM_MISC2 register ****************/ -#define CRM_MISC2_AUTO_STEP_EN (0x3U << 4) -#define CRM_MISC2_PLLU_USB48_SEL (0x1U << 10) -#define CRM_MISC2_PLLU_USB48_SEL_PLLU (0x0U << 10) -#define CRM_MISC2_PLLU_USB48_SEL_HICK (0x1U << 10) - - -/* =========================================================================================================================== */ -/* ================ ERTC ================ */ -/* =========================================================================================================================== */ - -/****************** Bit definition for ERTC_TIME register *******************/ -/*!< SU configuration */ -#define ERTC_TIME_SU_Pos (0U) -#define ERTC_TIME_SU_Msk (0xFU << ERTC_TIME_SU_Pos) /*!< 0x0000000F */ -#define ERTC_TIME_SU ERTC_TIME_SU_Msk /*!< SU[3:0] (Second units) */ -#define ERTC_TIME_SU_0 (0x1U << ERTC_TIME_SU_Pos) /*!< 0x00000001 */ -#define ERTC_TIME_SU_1 (0x2U << ERTC_TIME_SU_Pos) /*!< 0x00000002 */ -#define ERTC_TIME_SU_2 (0x4U << ERTC_TIME_SU_Pos) /*!< 0x00000004 */ -#define ERTC_TIME_SU_3 (0x8U << ERTC_TIME_SU_Pos) /*!< 0x00000008 */ - -/*!< ST configuration */ -#define ERTC_TIME_ST_Pos (4U) -#define ERTC_TIME_ST_Msk (0x7U << ERTC_TIME_ST_Pos) /*!< 0x00000070 */ -#define ERTC_TIME_ST ERTC_TIME_ST_Msk /*!< ST[2:0] (Second tens) */ -#define ERTC_TIME_ST_0 (0x1U << ERTC_TIME_ST_Pos) /*!< 0x00000010 */ -#define ERTC_TIME_ST_1 (0x2U << ERTC_TIME_ST_Pos) /*!< 0x00000020 */ -#define ERTC_TIME_ST_2 (0x4U << ERTC_TIME_ST_Pos) /*!< 0x00000040 */ - -/*!< MU configuration */ -#define ERTC_TIME_MU_Pos (8U) -#define ERTC_TIME_MU_Msk (0xFU << ERTC_TIME_MU_Pos) /*!< 0x00000F00 */ -#define ERTC_TIME_MU ERTC_TIME_MU_Msk /*!< MU[3:0] (Minute units) */ -#define ERTC_TIME_MU_0 (0x1U << ERTC_TIME_MU_Pos) /*!< 0x00000100 */ -#define ERTC_TIME_MU_1 (0x2U << ERTC_TIME_MU_Pos) /*!< 0x00000200 */ -#define ERTC_TIME_MU_2 (0x4U << ERTC_TIME_MU_Pos) /*!< 0x00000400 */ -#define ERTC_TIME_MU_3 (0x8U << ERTC_TIME_MU_Pos) /*!< 0x00000800 */ - -/*!< MT configuration */ -#define ERTC_TIME_MT_Pos (12U) -#define ERTC_TIME_MT_Msk (0x7U << ERTC_TIME_MT_Pos) /*!< 0x00007000 */ -#define ERTC_TIME_MT ERTC_TIME_MT_Msk /*!< MT[2:0] (Minute tens) */ -#define ERTC_TIME_MT_0 (0x1U << ERTC_TIME_MT_Pos) /*!< 0x00001000 */ -#define ERTC_TIME_MT_1 (0x2U << ERTC_TIME_MT_Pos) /*!< 0x00002000 */ -#define ERTC_TIME_MT_2 (0x4U << ERTC_TIME_MT_Pos) /*!< 0x00004000 */ - -/*!< HU configuration */ -#define ERTC_TIME_HU_Pos (16U) -#define ERTC_TIME_HU_Msk (0xFU << ERTC_TIME_HU_Pos) /*!< 0x000F0000 */ -#define ERTC_TIME_HU ERTC_TIME_HU_Msk /*!< HU[3:0] (Hour units) */ -#define ERTC_TIME_HU_0 (0x1U << ERTC_TIME_HU_Pos) /*!< 0x00010000 */ -#define ERTC_TIME_HU_1 (0x2U << ERTC_TIME_HU_Pos) /*!< 0x00020000 */ -#define ERTC_TIME_HU_2 (0x4U << ERTC_TIME_HU_Pos) /*!< 0x00040000 */ -#define ERTC_TIME_HU_3 (0x8U << ERTC_TIME_HU_Pos) /*!< 0x00080000 */ - -/*!< HT configuration */ -#define ERTC_TIME_HT_Pos (20U) -#define ERTC_TIME_HT_Msk (0x3U << ERTC_TIME_HT_Pos) /*!< 0x00300000 */ -#define ERTC_TIME_HT ERTC_TIME_HT_Msk /*!< HT[1:0] (Hour tens) */ -#define ERTC_TIME_HT_0 (0x1U << ERTC_TIME_HT_Pos) /*!< 0x00100000 */ -#define ERTC_TIME_HT_1 (0x2U << ERTC_TIME_HT_Pos) /*!< 0x00200000 */ - -#define ERTC_TIME_AMPM_Pos (22U) -#define ERTC_TIME_AMPM_Msk (0x1U << ERTC_TIME_AMPM_Pos) /*!< 0x00400000 */ -#define ERTC_TIME_AMPM ERTC_TIME_AMPM_Msk /*!< AM/PM */ - -/****************** Bit definition for ERTC_DATE register *******************/ -/*!< DU configuration */ -#define ERTC_DATE_DU_Pos (0U) -#define ERTC_DATE_DU_Msk (0xFU << ERTC_DATE_DU_Pos) /*!< 0x0000000F */ -#define ERTC_DATE_DU ERTC_DATE_DU_Msk /*!< DU[3:0] (Date units) */ -#define ERTC_DATE_DU_0 (0x1U << ERTC_DATE_DU_Pos) /*!< 0x00000001 */ -#define ERTC_DATE_DU_1 (0x2U << ERTC_DATE_DU_Pos) /*!< 0x00000002 */ -#define ERTC_DATE_DU_2 (0x4U << ERTC_DATE_DU_Pos) /*!< 0x00000004 */ -#define ERTC_DATE_DU_3 (0x8U << ERTC_DATE_DU_Pos) /*!< 0x00000008 */ - -/*!< DT configuration */ -#define ERTC_DATE_DT_Pos (4U) -#define ERTC_DATE_DT_Msk (0x3U << ERTC_DATE_DT_Pos) /*!< 0x00300000 */ -#define ERTC_DATE_DT ERTC_DATE_DT_Msk /*!< DT[1:0] (Date tens) */ -#define ERTC_DATE_DT_0 (0x1U << ERTC_DATE_DT_Pos) /*!< 0x00000010 */ -#define ERTC_DATE_DT_1 (0x2U << ERTC_DATE_DT_Pos) /*!< 0x00000020 */ - -/*!< MU configuration */ -#define ERTC_DATE_MU_Pos (8U) -#define ERTC_DATE_MU_Msk (0xFU << ERTC_DATE_MU_Pos) /*!< 0x00000F00 */ -#define ERTC_DATE_MU ERTC_DATE_MU_Msk /*!< MU[3:0] (Month units) */ -#define ERTC_DATE_MU_0 (0x1U << ERTC_DATE_MU_Pos) /*!< 0x00000100 */ -#define ERTC_DATE_MU_1 (0x2U << ERTC_DATE_MU_Pos) /*!< 0x00000200 */ -#define ERTC_DATE_MU_2 (0x4U << ERTC_DATE_MU_Pos) /*!< 0x00000400 */ -#define ERTC_DATE_MU_3 (0x8U << ERTC_DATE_MU_Pos) /*!< 0x00000800 */ - -#define ERTC_DATE_MT_Pos (12U) -#define ERTC_DATE_MT_Msk (0x1U << ERTC_DATE_MT_Pos) /*!< 0x00001000 */ -#define ERTC_DATE_MT ERTC_DATE_MT_Msk /*!< Month tens */ - -/*!< WK configuration */ -#define ERTC_DATE_WK_Pos (13U) -#define ERTC_DATE_WK_Msk (0x7U << ERTC_DATE_WK_Pos) /*!< 0x0000E000 */ -#define ERTC_DATE_WK ERTC_DATE_WK_Msk /*!< WK[2:0] (Week day) */ -#define ERTC_DATE_WK_0 (0x1U << ERTC_DATE_WK_Pos) /*!< 0x00002000 */ -#define ERTC_DATE_WK_1 (0x2U << ERTC_DATE_WK_Pos) /*!< 0x00004000 */ -#define ERTC_DATE_WK_2 (0x4U << ERTC_DATE_WK_Pos) /*!< 0x00008000 */ - -/*!< YU configuration */ -#define ERTC_DATE_YU_Pos (16U) -#define ERTC_DATE_YU_Msk (0xFU << ERTC_DATE_YU_Pos) /*!< 0x000F0000 */ -#define ERTC_DATE_YU ERTC_DATE_YU_Msk /*!< YU[3:0] (Year units) */ -#define ERTC_DATE_YU_0 (0x1U << ERTC_DATE_YU_Pos) /*!< 0x00010000 */ -#define ERTC_DATE_YU_1 (0x2U << ERTC_DATE_YU_Pos) /*!< 0x00020000 */ -#define ERTC_DATE_YU_2 (0x4U << ERTC_DATE_YU_Pos) /*!< 0x00040000 */ -#define ERTC_DATE_YU_3 (0x8U << ERTC_DATE_YU_Pos) /*!< 0x00080000 */ - -/*!< YT configuration */ -#define ERTC_DATE_YT_Pos (20U) -#define ERTC_DATE_YT_Msk (0xFU << ERTC_DATE_YT_Pos) /*!< 0x00F00000 */ -#define ERTC_DATE_YT ERTC_DATE_YT_Msk /*!< YT[3:0] (Year tens) */ -#define ERTC_DATE_YT_0 (0x1U << ERTC_DATE_YT_Pos) /*!< 0x00100000 */ -#define ERTC_DATE_YT_1 (0x2U << ERTC_DATE_YT_Pos) /*!< 0x00200000 */ -#define ERTC_DATE_YT_2 (0x4U << ERTC_DATE_YT_Pos) /*!< 0x00400000 */ -#define ERTC_DATE_YT_3 (0x8U << ERTC_DATE_YT_Pos) /*!< 0x00800000 */ - -/****************** Bit definition for ERTC_CTRL register *******************/ -/*!< WATCLK configuration */ -#define ERTC_CTRL_WATCLK_Pos (0U) -#define ERTC_CTRL_WATCLK_Msk (0x7U << ERTC_CTRL_WATCLK_Pos) /*!< 0x00000007 */ -#define ERTC_CTRL_WATCLK ERTC_CTRL_WATCLK_Msk /*!< WATCLK[2:0] (Wakeup timer clock selection) */ -#define ERTC_CTRL_WATCLK_0 (0x1U << ERTC_CTRL_WATCLK_Pos) /*!< 0x00000001 */ -#define ERTC_CTRL_WATCLK_1 (0x2U << ERTC_CTRL_WATCLK_Pos) /*!< 0x00000002 */ -#define ERTC_CTRL_WATCLK_2 (0x4U << ERTC_CTRL_WATCLK_Pos) /*!< 0x00000004 */ - -#define ERTC_CTRL_TSEDG_Pos (3U) -#define ERTC_CTRL_TSEDG_Msk (0x1U << ERTC_CTRL_TSEDG_Pos) /*!< 0x00000008 */ -#define ERTC_CTRL_TSEDG ERTC_CTRL_TSEDG_Msk /*!< Timestamp trigger edge */ -#define ERTC_CTRL_RCDEN_Pos (4U) -#define ERTC_CTRL_RCDEN_Msk (0x1U << ERTC_CTRL_RCDEN_Pos) /*!< 0x00000010 */ -#define ERTC_CTRL_RCDEN ERTC_CTRL_RCDEN_Msk /*!< Reference clock detection enable */ -#define ERTC_CTRL_DREN_Pos (5U) -#define ERTC_CTRL_DREN_Msk (0x1U << ERTC_CTRL_DREN_Pos) /*!< 0x00000020 */ -#define ERTC_CTRL_DREN ERTC_CTRL_DREN_Msk /*!< Date/time register direct read enable */ -#define ERTC_CTRL_HM_Pos (6U) -#define ERTC_CTRL_HM_Msk (0x1U << ERTC_CTRL_HM_Pos) /*!< 0x00000040 */ -#define ERTC_CTRL_HM ERTC_CTRL_HM_Msk /*!< Hour mode */ -#define ERTC_CTRL_CCALEN_Pos (7U) -#define ERTC_CTRL_CCALEN_Msk (0x1U << ERTC_CTRL_CCALEN_Pos) /*!< 0x00000080 */ -#define ERTC_CTRL_CCALEN ERTC_CTRL_CCALEN_Msk /*!< Coarse calibration enable */ -#define ERTC_CTRL_ALAEN_Pos (8U) -#define ERTC_CTRL_ALAEN_Msk (0x1U << ERTC_CTRL_ALAEN_Pos) /*!< 0x00000100 */ -#define ERTC_CTRL_ALAEN ERTC_CTRL_ALAEN_Msk /*!< Alarm A enable */ -#define ERTC_CTRL_ALBEN_Pos (9U) -#define ERTC_CTRL_ALBEN_Msk (0x1U << ERTC_CTRL_ALBEN_Pos) /*!< 0x00000200 */ -#define ERTC_CTRL_ALBEN ERTC_CTRL_ALBEN_Msk /*!< Alarm B enable */ -#define ERTC_CTRL_WATEN_Pos (10U) -#define ERTC_CTRL_WATEN_Msk (0x1U << ERTC_CTRL_WATEN_Pos) /*!< 0x00000400 */ -#define ERTC_CTRL_WATEN ERTC_CTRL_WATEN_Msk /*!< Wakeup timer enable */ -#define ERTC_CTRL_TSEN_Pos (11U) -#define ERTC_CTRL_TSEN_Msk (0x1U << ERTC_CTRL_TSEN_Pos) /*!< 0x00000800 */ -#define ERTC_CTRL_TSEN ERTC_CTRL_TSEN_Msk /*!< Timestamp enable */ -#define ERTC_CTRL_ALAIEN_Pos (12U) -#define ERTC_CTRL_ALAIEN_Msk (0x1U << ERTC_CTRL_ALAIEN_Pos) /*!< 0x00001000 */ -#define ERTC_CTRL_ALAIEN ERTC_CTRL_ALAIEN_Msk /*!< Alarm A interrupt enable */ -#define ERTC_CTRL_ALBIEN_Pos (13U) -#define ERTC_CTRL_ALBIEN_Msk (0x1U << ERTC_CTRL_ALBIEN_Pos) /*!< 0x00002000 */ -#define ERTC_CTRL_ALBIEN ERTC_CTRL_ALBIEN_Msk /*!< Alarm B interrupt enable */ -#define ERTC_CTRL_WATIEN_Pos (14U) -#define ERTC_CTRL_WATIEN_Msk (0x1U << ERTC_CTRL_WATIEN_Pos) /*!< 0x00004000 */ -#define ERTC_CTRL_WATIEN ERTC_CTRL_WATIEN_Msk /*!< Wakeup timer interrupt enable */ -#define ERTC_CTRL_TSIEN_Pos (15U) -#define ERTC_CTRL_TSIEN_Msk (0x1U << ERTC_CTRL_TSIEN_Pos) /*!< 0x000008000 */ -#define ERTC_CTRL_TSIEN ERTC_CTRL_TSIEN_Msk /*!< Timestamp interrupt enable */ -#define ERTC_CTRL_ADD1H_Pos (16U) -#define ERTC_CTRL_ADD1H_Msk (0x1U << ERTC_CTRL_ADD1H_Pos) /*!< 0x00010000 */ -#define ERTC_CTRL_ADD1H ERTC_CTRL_ADD1H_Msk /*!< Add 1 hour */ -#define ERTC_CTRL_DEC1H_Pos (17U) -#define ERTC_CTRL_DEC1H_Msk (0x1U << ERTC_CTRL_DEC1H_Pos) /*!< 0x00020000 */ -#define ERTC_CTRL_DEC1H ERTC_CTRL_DEC1H_Msk /*!< Decrease 1 hour */ -#define ERTC_CTRL_BPR_Pos (18U) -#define ERTC_CTRL_BPR_Msk (0x1U << ERTC_CTRL_BPR_Pos) /*!< 0x00040000 */ -#define ERTC_CTRL_BPR ERTC_CTRL_BPR_Msk /*!< Battery powered domain data register */ -#define ERTC_CTRL_CALOSEL_Pos (19U) -#define ERTC_CTRL_CALOSEL_Msk (0x1U << ERTC_CTRL_CALOSEL_Pos) /*!< 0x00080000 */ -#define ERTC_CTRL_CALOSEL ERTC_CTRL_CALOSEL_Msk /*!< Calibration output selection */ -#define ERTC_CTRL_OUTP_Pos (20U) -#define ERTC_CTRL_OUTP_Msk (0x1U << ERTC_CTRL_OUTP_Pos) /*!< 0x00100000 */ -#define ERTC_CTRL_OUTP ERTC_CTRL_OUTP_Msk /*!< Output polarity */ - -/*!< OUTSEL configuration */ -#define ERTC_CTRL_OUTSEL_Pos (21U) -#define ERTC_CTRL_OUTSEL_Msk (0x3U << ERTC_CTRL_OUTSEL_Pos) /*!< 0x00600000 */ -#define ERTC_CTRL_OUTSEL ERTC_CTRL_OUTSEL_Msk /*!< OUTSEL[1:0] (Output source selection) */ -#define ERTC_CTRL_OUTSEL_0 (0x1U << ERTC_CTRL_OUTSEL_Pos) /*!< 0x00200000 */ -#define ERTC_CTRL_OUTSEL_1 (0x2U << ERTC_CTRL_OUTSEL_Pos) /*!< 0x00400000 */ - -#define ERTC_CTRL_CALOEN_Pos (23U) -#define ERTC_CTRL_CALOEN_Msk (0x1U << ERTC_CTRL_CALOEN_Pos) /*!< 0x00800000 */ -#define ERTC_CTRL_CALOEN ERTC_CTRL_CALOEN_Msk /*!< Calibration output enable */ - -/******************* Bit definition for ERTC_STS register *******************/ -#define ERTC_STS_ALAWF_Pos (0U) -#define ERTC_STS_ALAWF_Msk (0x1U << ERTC_STS_ALAWF_Pos) /*!< 0x00000001 */ -#define ERTC_STS_ALAWF ERTC_STS_ALAWF_Msk /*!< Alarm A register allows write flag */ -#define ERTC_STS_ALBWF_Pos (1U) -#define ERTC_STS_ALBWF_Msk (0x1U << ERTC_STS_ALBWF_Pos) /*!< 0x00000002 */ -#define ERTC_STS_ALBWF ERTC_STS_ALBWF_Msk /*!< Alarm B register allows write flag */ -#define ERTC_STS_WATWF_Pos (2U) -#define ERTC_STS_WATWF_Msk (0x1U << ERTC_STS_WATWF_Pos) /*!< 0x00000004 */ -#define ERTC_STS_WATWF ERTC_STS_WATWF_Msk /*!< Wakeup timer register allows write flag */ -#define ERTC_STS_TADJF_Pos (3U) -#define ERTC_STS_TADJF_Msk (0x1U << ERTC_STS_TADJF_Pos) /*!< 0x00000008 */ -#define ERTC_STS_TADJF ERTC_STS_TADJF_Msk /*!< Time adjustment flag */ -#define ERTC_STS_INITF_Pos (4U) -#define ERTC_STS_INITF_Msk (0x1U << ERTC_STS_INITF_Pos) /*!< 0x00000010 */ -#define ERTC_STS_INITF ERTC_STS_INITF_Msk /*!< Calendar initialization flag */ -#define ERTC_STS_UPDF_Pos (5U) -#define ERTC_STS_UPDF_Msk (0x1U << ERTC_STS_UPDF_Pos) /*!< 0x00000020 */ -#define ERTC_STS_UPDF ERTC_STS_UPDF_Msk /*!< Calendar update flag */ -#define ERTC_STS_IMF_Pos (6U) -#define ERTC_STS_IMF_Msk (0x1U << ERTC_STS_IMF_Pos) /*!< 0x00000040 */ -#define ERTC_STS_IMF ERTC_STS_IMF_Msk /*!< Enter initialization mode flag */ -#define ERTC_STS_IMEN_Pos (7U) -#define ERTC_STS_IMEN_Msk (0x1U << ERTC_STS_IMEN_Pos) /*!< 0x00000080 */ -#define ERTC_STS_IMEN ERTC_STS_IMEN_Msk /*!< Initialization mode enable */ -#define ERTC_STS_ALAF_Pos (8U) -#define ERTC_STS_ALAF_Msk (0x1U << ERTC_STS_ALAF_Pos) /*!< 0x00000100 */ -#define ERTC_STS_ALAF ERTC_STS_ALAF_Msk /*!< Alarm clock A flag */ -#define ERTC_STS_ALBF_Pos (9U) -#define ERTC_STS_ALBF_Msk (0x1U << ERTC_STS_ALBF_Pos) /*!< 0x00000200 */ -#define ERTC_STS_ALBF ERTC_STS_ALBF_Msk /*!< Alarm clock B flag */ -#define ERTC_STS_WATF_Pos (10U) -#define ERTC_STS_WATF_Msk (0x1U << ERTC_STS_WATF_Pos) /*!< 0x00000400 */ -#define ERTC_STS_WATF ERTC_STS_WATF_Msk /*!< Wakeup timer flag */ -#define ERTC_STS_TSF_Pos (11U) -#define ERTC_STS_TSF_Msk (0x1U << ERTC_STS_TSF_Pos) /*!< 0x00000800 */ -#define ERTC_STS_TSF ERTC_STS_TSF_Msk /*!< Timestamp flag */ -#define ERTC_STS_TSOF_Pos (12U) -#define ERTC_STS_TSOF_Msk (0x1U << ERTC_STS_TSOF_Pos) /*!< 0x00001000 */ -#define ERTC_STS_TSOF ERTC_STS_TSOF_Msk /*!< Timestamp overflow flag */ -#define ERTC_STS_TP1F_Pos (13U) -#define ERTC_STS_TP1F_Msk (0x1U << ERTC_STS_TP1F_Pos) /*!< 0x00002000 */ -#define ERTC_STS_TP1F ERTC_STS_TP1F_Msk /*!< Tamper detection 1 flag */ -#define ERTC_STS_CALUPDF_Pos (16U) -#define ERTC_STS_CALUPDF_Msk (0x1U << ERTC_STS_CALUPDF_Pos) /*!< 0x00010000 */ -#define ERTC_STS_CALUPDF ERTC_STS_CALUPDF_Msk /*!< Calibration value update complete flag */ - -/******************* Bit definition for ERTC_DIV register *******************/ -#define ERTC_DIV_DIVB_Pos (0U) -#define ERTC_DIV_DIVB_Msk (0x7FFFU << ERTC_DIV_DIVB_Pos) /*!< 0x00007FFF */ -#define ERTC_DIV_DIVB ERTC_DIV_DIVB_Msk /*!< Divider B */ -#define ERTC_DIV_DIVA_Pos (16U) -#define ERTC_DIV_DIVA_Msk (0x7FU << ERTC_DIV_DIVA_Pos) /*!< 0x007F0000 */ -#define ERTC_DIV_DIVA ERTC_DIV_DIVA_Msk /*!< Divider A */ - -/******************* Bit definition for ERTC_WAT register *******************/ -#define ERTC_WAT_VAL_Pos (0U) -#define ERTC_WAT_VAL_Msk (0xFFFFU << ERTC_WAT_VAL_Pos) /*!< 0x0000FFFF */ -#define ERTC_WAT_VAL ERTC_WAT_VAL_Msk /*!< Wakeup timer reload value */ - -/****************** Bit definition for ERTC_CCAL register *******************/ -/*!< CALVAL configuration */ -#define ERTC_CCAL_CALVAL_Pos (0U) -#define ERTC_CCAL_CALVAL_Msk (0x1FU << ERTC_CCAL_CALVAL_Pos) /*!< 0x0000001F */ -#define ERTC_CCAL_CALVAL ERTC_CCAL_CALVAL_Msk /*!< CALVAL[4:0] (Calibration value) */ -#define ERTC_CCAL_CALVAL_0 (0x1U << ERTC_CCAL_CALVAL_Pos) /*!< 0x00000001 */ -#define ERTC_CCAL_CALVAL_1 (0x2U << ERTC_CCAL_CALVAL_Pos) /*!< 0x00000002 */ -#define ERTC_CCAL_CALVAL_2 (0x4U << ERTC_CCAL_CALVAL_Pos) /*!< 0x00000004 */ -#define ERTC_CCAL_CALVAL_3 (0x8U << ERTC_CCAL_CALVAL_Pos) /*!< 0x00000008 */ -#define ERTC_CCAL_CALVAL_4 (0x10U << ERTC_CCAL_CALVAL_Pos) /*!< 0x00000010 */ - -#define ERTC_CCAL_CALDIR_Pos (7U) -#define ERTC_CCAL_CALDIR_Msk (0x1U << ERTC_CCAL_CALDIR_Pos) /*!< 0x00000080 */ -#define ERTC_CCAL_CALDIR ERTC_CCAL_CALDIR_Msk /*!< Calibration direction */ - -/******************* Bit definition for ERTC_ALA register *******************/ -/*!< SU configuration */ -#define ERTC_ALA_SU_Pos (0U) -#define ERTC_ALA_SU_Msk (0xFU << ERTC_ALA_SU_Pos) /*!< 0x0000000F */ -#define ERTC_ALA_SU ERTC_ALA_SU_Msk /*!< SU[3:0] (Second units) */ -#define ERTC_ALA_SU_0 (0x1U << ERTC_ALA_SU_Pos) /*!< 0x00000001 */ -#define ERTC_ALA_SU_1 (0x2U << ERTC_ALA_SU_Pos) /*!< 0x00000002 */ -#define ERTC_ALA_SU_2 (0x4U << ERTC_ALA_SU_Pos) /*!< 0x00000004 */ -#define ERTC_ALA_SU_3 (0x8U << ERTC_ALA_SU_Pos) /*!< 0x00000008 */ - -/*!< ST configuration */ -#define ERTC_ALA_ST_Pos (4U) -#define ERTC_ALA_ST_Msk (0x7U << ERTC_ALA_ST_Pos) /*!< 0x00000070 */ -#define ERTC_ALA_ST ERTC_ALA_ST_Msk /*!< ST[2:0] (Second tens) */ -#define ERTC_ALA_ST_0 (0x1U << ERTC_ALA_ST_Pos) /*!< 0x00000010 */ -#define ERTC_ALA_ST_1 (0x2U << ERTC_ALA_ST_Pos) /*!< 0x00000020 */ -#define ERTC_ALA_ST_2 (0x4U << ERTC_ALA_ST_Pos) /*!< 0x00000040 */ - -#define ERTC_ALA_MASK1_Pos (7U) -#define ERTC_ALA_MASK1_Msk (0x1U << ERTC_ALA_MASK1_Pos) /*!< 0x00000080 */ -#define ERTC_ALA_MASK1 ERTC_ALA_MASK1_Msk /*!< Second mask */ - -/*!< MU configuration */ -#define ERTC_ALA_MU_Pos (8U) -#define ERTC_ALA_MU_Msk (0xFU << ERTC_ALA_MU_Pos) /*!< 0x00000F00 */ -#define ERTC_ALA_MU ERTC_ALA_MU_Msk /*!< MU[3:0] (Minute units) */ -#define ERTC_ALA_MU_0 (0x1U << ERTC_ALA_MU_Pos) /*!< 0x00000100 */ -#define ERTC_ALA_MU_1 (0x2U << ERTC_ALA_MU_Pos) /*!< 0x00000200 */ -#define ERTC_ALA_MU_2 (0x4U << ERTC_ALA_MU_Pos) /*!< 0x00000400 */ -#define ERTC_ALA_MU_3 (0x8U << ERTC_ALA_MU_Pos) /*!< 0x00000800 */ - -/*!< MT configuration */ -#define ERTC_ALA_MT_Pos (12U) -#define ERTC_ALA_MT_Msk (0x7U << ERTC_ALA_MT_Pos) /*!< 0x00007000 */ -#define ERTC_ALA_MT ERTC_ALA_MT_Msk /*!< MT[2:0] (Minute tens) */ -#define ERTC_ALA_MT_0 (0x1U << ERTC_ALA_MT_Pos) /*!< 0x00001000 */ -#define ERTC_ALA_MT_1 (0x2U << ERTC_ALA_MT_Pos) /*!< 0x00002000 */ -#define ERTC_ALA_MT_2 (0x4U << ERTC_ALA_MT_Pos) /*!< 0x00004000 */ - -#define ERTC_ALA_MASK2_Pos (15U) -#define ERTC_ALA_MASK2_Msk (0x1U << ERTC_ALA_MASK2_Pos) /*!< 0x00008000 */ -#define ERTC_ALA_MASK2 ERTC_ALA_MASK2_Msk /*!< Minute mask */ - -/*!< HU configuration */ -#define ERTC_ALA_HU_Pos (16U) -#define ERTC_ALA_HU_Msk (0xFU << ERTC_ALA_HU_Pos) /*!< 0x000F0000 */ -#define ERTC_ALA_HU ERTC_ALA_HU_Msk /*!< HU[3:0] (Hour units) */ -#define ERTC_ALA_HU_0 (0x1U << ERTC_ALA_HU_Pos) /*!< 0x00010000 */ -#define ERTC_ALA_HU_1 (0x2U << ERTC_ALA_HU_Pos) /*!< 0x00020000 */ -#define ERTC_ALA_HU_2 (0x4U << ERTC_ALA_HU_Pos) /*!< 0x00040000 */ -#define ERTC_ALA_HU_3 (0x8U << ERTC_ALA_HU_Pos) /*!< 0x00080000 */ - -/*!< HT configuration */ -#define ERTC_ALA_HT_Pos (20U) -#define ERTC_ALA_HT_Msk (0x3U << ERTC_ALA_HT_Pos) /*!< 0x00300000 */ -#define ERTC_ALA_HT ERTC_ALA_HT_Msk /*!< HT[1:0] (Hour tens) */ -#define ERTC_ALA_HT_0 (0x1U << ERTC_ALA_HT_Pos) /*!< 0x00100000 */ -#define ERTC_ALA_HT_1 (0x2U << ERTC_ALA_HT_Pos) /*!< 0x00200000 */ - -#define ERTC_ALA_AMPM_Pos (22U) -#define ERTC_ALA_AMPM_Msk (0x1U << ERTC_ALA_AMPM_Pos) /*!< 0x00400000 */ -#define ERTC_ALA_AMPM ERTC_ALA_AMPM_Msk /*!< AM/PM */ -#define ERTC_ALA_MASK3_Pos (23U) -#define ERTC_ALA_MASK3_Msk (0x1U << ERTC_ALA_MASK3_Pos) /*!< 0x00800000 */ -#define ERTC_ALA_MASK3 ERTC_ALA_MASK3_Msk /*!< Hour mask */ - -/*!< DU configuration */ -#define ERTC_ALA_DU_Pos (24U) -#define ERTC_ALA_DU_Msk (0xFU << ERTC_ALA_DU_Pos) /*!< 0x0F000000 */ -#define ERTC_ALA_DU ERTC_ALA_DU_Msk /*!< DU[3:0] (Date/week day units) */ -#define ERTC_ALA_DU_0 (0x1U << ERTC_ALA_DU_Pos) /*!< 0x01000000 */ -#define ERTC_ALA_DU_1 (0x2U << ERTC_ALA_DU_Pos) /*!< 0x02000000 */ -#define ERTC_ALA_DU_2 (0x4U << ERTC_ALA_DU_Pos) /*!< 0x04000000 */ -#define ERTC_ALA_DU_3 (0x8U << ERTC_ALA_DU_Pos) /*!< 0x08000000 */ - -/*!< DT configuration */ -#define ERTC_ALA_DT_Pos (28U) -#define ERTC_ALA_DT_Msk (0x3U << ERTC_ALA_DT_Pos) /*!< 0x30000000 */ -#define ERTC_ALA_DT ERTC_ALA_DT_Msk /*!< DT[1:0] (Date/week day tens) */ -#define ERTC_ALA_DT_0 (0x1U << ERTC_ALA_DT_Pos) /*!< 0x10000000 */ -#define ERTC_ALA_DT_1 (0x2U << ERTC_ALA_DT_Pos) /*!< 0x20000000 */ - -#define ERTC_ALA_WKSEL_Pos (30U) -#define ERTC_ALA_WKSEL_Msk (0x1U << ERTC_ALA_WKSEL_Pos) /*!< 0x40000000 */ -#define ERTC_ALA_WKSEL ERTC_ALA_WKSEL_Msk /*!< Date/week day select */ -#define ERTC_ALA_MASK4_Pos (31U) -#define ERTC_ALA_MASK4_Msk (0x1U << ERTC_ALA_MASK4_Pos) /*!< 0x80000000 */ -#define ERTC_ALA_MASK4 ERTC_ALA_MASK4_Msk /*!< Date/week day mask */ - -/******************* Bit definition for ERTC_ALB register *******************/ -/*!< SU configuration */ -#define ERTC_ALB_SU_Pos (0U) -#define ERTC_ALB_SU_Msk (0xFU << ERTC_ALB_SU_Pos) /*!< 0x0000000F */ -#define ERTC_ALB_SU ERTC_ALB_SU_Msk /*!< SU[3:0] (Second units) */ -#define ERTC_ALB_SU_0 (0x1U << ERTC_ALB_SU_Pos) /*!< 0x00000001 */ -#define ERTC_ALB_SU_1 (0x2U << ERTC_ALB_SU_Pos) /*!< 0x00000002 */ -#define ERTC_ALB_SU_2 (0x4U << ERTC_ALB_SU_Pos) /*!< 0x00000004 */ -#define ERTC_ALB_SU_3 (0x8U << ERTC_ALB_SU_Pos) /*!< 0x00000008 */ - -/*!< ST configuration */ -#define ERTC_ALB_ST_Pos (4U) -#define ERTC_ALB_ST_Msk (0x7U << ERTC_ALB_ST_Pos) /*!< 0x00000070 */ -#define ERTC_ALB_ST ERTC_ALB_ST_Msk /*!< ST[2:0] (Second tens) */ -#define ERTC_ALB_ST_0 (0x1U << ERTC_ALB_ST_Pos) /*!< 0x00000010 */ -#define ERTC_ALB_ST_1 (0x2U << ERTC_ALB_ST_Pos) /*!< 0x00000020 */ -#define ERTC_ALB_ST_2 (0x4U << ERTC_ALB_ST_Pos) /*!< 0x00000040 */ - -#define ERTC_ALB_MASK1_Pos (7U) -#define ERTC_ALB_MASK1_Msk (0x1U << ERTC_ALB_MASK1_Pos) /*!< 0x00000080 */ -#define ERTC_ALB_MASK1 ERTC_ALB_MASK1_Msk /*!< Second mask */ - -/*!< MU configuration */ -#define ERTC_ALB_MU_Pos (8U) -#define ERTC_ALB_MU_Msk (0xFU << ERTC_ALB_MU_Pos) /*!< 0x00000F00 */ -#define ERTC_ALB_MU ERTC_ALB_MU_Msk /*!< MU[3:0] (Minute units) */ -#define ERTC_ALB_MU_0 (0x1U << ERTC_ALB_MU_Pos) /*!< 0x00000100 */ -#define ERTC_ALB_MU_1 (0x2U << ERTC_ALB_MU_Pos) /*!< 0x00000200 */ -#define ERTC_ALB_MU_2 (0x4U << ERTC_ALB_MU_Pos) /*!< 0x00000400 */ -#define ERTC_ALB_MU_3 (0x8U << ERTC_ALB_MU_Pos) /*!< 0x00000800 */ - -/*!< MT configuration */ -#define ERTC_ALB_MT_Pos (12U) -#define ERTC_ALB_MT_Msk (0x7U << ERTC_ALB_MT_Pos) /*!< 0x00007000 */ -#define ERTC_ALB_MT ERTC_ALB_MT_Msk /*!< MT[2:0] (Minute tens) */ -#define ERTC_ALB_MT_0 (0x1U << ERTC_ALB_MT_Pos) /*!< 0x00001000 */ -#define ERTC_ALB_MT_1 (0x2U << ERTC_ALB_MT_Pos) /*!< 0x00002000 */ -#define ERTC_ALB_MT_2 (0x4U << ERTC_ALB_MT_Pos) /*!< 0x00004000 */ - -#define ERTC_ALB_MASK2_Pos (15U) -#define ERTC_ALB_MASK2_Msk (0x1U << ERTC_ALB_MASK2_Pos) /*!< 0x00008000 */ -#define ERTC_ALB_MASK2 ERTC_ALB_MASK2_Msk /*!< Minute mask */ - -/*!< HU configuration */ -#define ERTC_ALB_HU_Pos (16U) -#define ERTC_ALB_HU_Msk (0xFU << ERTC_ALB_HU_Pos) /*!< 0x000F0000 */ -#define ERTC_ALB_HU ERTC_ALB_HU_Msk /*!< HU[3:0] (Hour units) */ -#define ERTC_ALB_HU_0 (0x1U << ERTC_ALB_HU_Pos) /*!< 0x00010000 */ -#define ERTC_ALB_HU_1 (0x2U << ERTC_ALB_HU_Pos) /*!< 0x00020000 */ -#define ERTC_ALB_HU_2 (0x4U << ERTC_ALB_HU_Pos) /*!< 0x00040000 */ -#define ERTC_ALB_HU_3 (0x8U << ERTC_ALB_HU_Pos) /*!< 0x00080000 */ - -/*!< HT configuration */ -#define ERTC_ALB_HT_Pos (20U) -#define ERTC_ALB_HT_Msk (0x3U << ERTC_ALB_HT_Pos) /*!< 0x00300000 */ -#define ERTC_ALB_HT ERTC_ALB_HT_Msk /*!< HT[1:0] (Hour tens) */ -#define ERTC_ALB_HT_0 (0x1U << ERTC_ALB_HT_Pos) /*!< 0x00100000 */ -#define ERTC_ALB_HT_1 (0x2U << ERTC_ALB_HT_Pos) /*!< 0x00200000 */ - -#define ERTC_ALB_AMPM_Pos (22U) -#define ERTC_ALB_AMPM_Msk (0x1U << ERTC_ALB_AMPM_Pos) /*!< 0x00400000 */ -#define ERTC_ALB_AMPM ERTC_ALB_AMPM_Msk /*!< AM/PM */ -#define ERTC_ALB_MASK3_Pos (23U) -#define ERTC_ALB_MASK3_Msk (0x1U << ERTC_ALB_MASK3_Pos) /*!< 0x00800000 */ -#define ERTC_ALB_MASK3 ERTC_ALB_MASK3_Msk /*!< Hour mask */ - -/*!< DU configuration */ -#define ERTC_ALB_DU_Pos (24U) -#define ERTC_ALB_DU_Msk (0xFU << ERTC_ALB_DU_Pos) /*!< 0x0F000000 */ -#define ERTC_ALB_DU ERTC_ALB_DU_Msk /*!< DU[3:0] (Date/week day units) */ -#define ERTC_ALB_DU_0 (0x1U << ERTC_ALB_DU_Pos) /*!< 0x01000000 */ -#define ERTC_ALB_DU_1 (0x2U << ERTC_ALB_DU_Pos) /*!< 0x02000000 */ -#define ERTC_ALB_DU_2 (0x4U << ERTC_ALB_DU_Pos) /*!< 0x04000000 */ -#define ERTC_ALB_DU_3 (0x8U << ERTC_ALB_DU_Pos) /*!< 0x08000000 */ - -/*!< DT configuration */ -#define ERTC_ALB_DT_Pos (28U) -#define ERTC_ALB_DT_Msk (0x3U << ERTC_ALB_DT_Pos) /*!< 0x30000000 */ -#define ERTC_ALB_DT ERTC_ALB_DT_Msk /*!< DT[1:0] (Date/week day tens) */ -#define ERTC_ALB_DT_0 (0x1U << ERTC_ALB_DT_Pos) /*!< 0x10000000 */ -#define ERTC_ALB_DT_1 (0x2U << ERTC_ALB_DT_Pos) /*!< 0x20000000 */ - -#define ERTC_ALB_WKSEL_Pos (30U) -#define ERTC_ALB_WKSEL_Msk (0x1U << ERTC_ALB_WKSEL_Pos) /*!< 0x40000000 */ -#define ERTC_ALB_WKSEL ERTC_ALB_WKSEL_Msk /*!< Date/week day select */ -#define ERTC_ALB_MASK4_Pos (31U) -#define ERTC_ALB_MASK4_Msk (0x1U << ERTC_ALB_MASK4_Pos) /*!< 0x80000000 */ -#define ERTC_ALB_MASK4 ERTC_ALB_MASK4_Msk /*!< Date/week day mask */ - -/******************* Bit definition for ERTC_WP register ********************/ -#define ERTC_WP_CMD_Pos (0U) -#define ERTC_WP_CMD_Msk (0xFFU << ERTC_WP_CMD_Pos) /*!< 0x000000FF */ -#define ERTC_WP_CMD ERTC_WP_CMD_Msk /*!< Command register */ - -/******************* Bit definition for ERTC_SBS register *******************/ -#define ERTC_SBS_SBS_Pos (0U) -#define ERTC_SBS_SBS_Msk (0xFFFFU << ERTC_SBS_SBS_Pos) /*!< 0x0000FFFF */ -#define ERTC_SBS_SBS ERTC_SBS_SBS_Msk /*!< Sub-second value */ - -/****************** Bit definition for ERTC_TADJ register *******************/ -#define ERTC_TADJ_DECSBS_Pos (0U) -#define ERTC_TADJ_DECSBS_Msk (0x7FFFU << ERTC_TADJ_DECSBS_Pos) /*!< 0x00007FFF */ -#define ERTC_TADJ_DECSBS ERTC_TADJ_DECSBS_Msk /*!< Decrease sub-second value */ -#define ERTC_TADJ_ADD1S_Pos (31U) -#define ERTC_TADJ_ADD1S_Msk (0x1U << ERTC_TADJ_ADD1S_Pos) /*!< 0x80000000 */ -#define ERTC_TADJ_ADD1S ERTC_TADJ_ADD1S_Msk /*!< Add 1 second */ - -/****************** Bit definition for ERTC_TSTM register *******************/ -/*!< SU configuration */ -#define ERTC_TSTM_SU_Pos (0U) -#define ERTC_TSTM_SU_Msk (0xFU << ERTC_TSTM_SU_Pos) /*!< 0x0000000F */ -#define ERTC_TSTM_SU ERTC_TSTM_SU_Msk /*!< SU[3:0] (Second units) */ -#define ERTC_TSTM_SU_0 (0x1U << ERTC_TSTM_SU_Pos) /*!< 0x00000001 */ -#define ERTC_TSTM_SU_1 (0x2U << ERTC_TSTM_SU_Pos) /*!< 0x00000002 */ -#define ERTC_TSTM_SU_2 (0x4U << ERTC_TSTM_SU_Pos) /*!< 0x00000004 */ -#define ERTC_TSTM_SU_3 (0x8U << ERTC_TSTM_SU_Pos) /*!< 0x00000008 */ - -/*!< ST configuration */ -#define ERTC_TSTM_ST_Pos (4U) -#define ERTC_TSTM_ST_Msk (0x7U << ERTC_TSTM_ST_Pos) /*!< 0x00000070 */ -#define ERTC_TSTM_ST ERTC_TSTM_ST_Msk /*!< ST[2:0] (Second tens) */ -#define ERTC_TSTM_ST_0 (0x1U << ERTC_TSTM_ST_Pos) /*!< 0x00000010 */ -#define ERTC_TSTM_ST_1 (0x2U << ERTC_TSTM_ST_Pos) /*!< 0x00000020 */ -#define ERTC_TSTM_ST_2 (0x4U << ERTC_TSTM_ST_Pos) /*!< 0x00000040 */ - -/*!< MU configuration */ -#define ERTC_TSTM_MU_Pos (8U) -#define ERTC_TSTM_MU_Msk (0xFU << ERTC_TSTM_MU_Pos) /*!< 0x00000F00 */ -#define ERTC_TSTM_MU ERTC_TSTM_MU_Msk /*!< MU[3:0] (Minute units) */ -#define ERTC_TSTM_MU_0 (0x1U << ERTC_TSTM_MU_Pos) /*!< 0x00000100 */ -#define ERTC_TSTM_MU_1 (0x2U << ERTC_TSTM_MU_Pos) /*!< 0x00000200 */ -#define ERTC_TSTM_MU_2 (0x4U << ERTC_TSTM_MU_Pos) /*!< 0x00000400 */ -#define ERTC_TSTM_MU_3 (0x8U << ERTC_TSTM_MU_Pos) /*!< 0x00000800 */ - -/*!< MT configuration */ -#define ERTC_TSTM_MT_Pos (12U) -#define ERTC_TSTM_MT_Msk (0x7U << ERTC_TSTM_MT_Pos) /*!< 0x00007000 */ -#define ERTC_TSTM_MT ERTC_TSTM_MT_Msk /*!< MT[2:0] (Minute tens) */ -#define ERTC_TSTM_MT_0 (0x1U << ERTC_TSTM_MT_Pos) /*!< 0x00001000 */ -#define ERTC_TSTM_MT_1 (0x2U << ERTC_TSTM_MT_Pos) /*!< 0x00002000 */ -#define ERTC_TSTM_MT_2 (0x4U << ERTC_TSTM_MT_Pos) /*!< 0x00004000 */ - -/*!< HU configuration */ -#define ERTC_TSTM_HU_Pos (16U) -#define ERTC_TSTM_HU_Msk (0xFU << ERTC_TSTM_HU_Pos) /*!< 0x000F0000 */ -#define ERTC_TSTM_HU ERTC_TSTM_HU_Msk /*!< HU[3:0] (Hour units) */ -#define ERTC_TSTM_HU_0 (0x1U << ERTC_TSTM_HU_Pos) /*!< 0x00010000 */ -#define ERTC_TSTM_HU_1 (0x2U << ERTC_TSTM_HU_Pos) /*!< 0x00020000 */ -#define ERTC_TSTM_HU_2 (0x4U << ERTC_TSTM_HU_Pos) /*!< 0x00040000 */ -#define ERTC_TSTM_HU_3 (0x8U << ERTC_TSTM_HU_Pos) /*!< 0x00080000 */ - -/*!< HT configuration */ -#define ERTC_TSTM_HT_Pos (20U) -#define ERTC_TSTM_HT_Msk (0x3U << ERTC_TSTM_HT_Pos) /*!< 0x00300000 */ -#define ERTC_TSTM_HT ERTC_TSTM_HT_Msk /*!< HT[1:0] (Hour tens) */ -#define ERTC_TSTM_HT_0 (0x1U << ERTC_TSTM_HT_Pos) /*!< 0x00100000 */ -#define ERTC_TSTM_HT_1 (0x2U << ERTC_TSTM_HT_Pos) /*!< 0x00200000 */ - -#define ERTC_TSTM_AMPM_Pos (22U) -#define ERTC_TSTM_AMPM_Msk (0x1U << ERTC_TSTM_AMPM_Pos) /*!< 0x00400000 */ -#define ERTC_TSTM_AMPM ERTC_TSTM_AMPM_Msk /*!< AM/PM */ - -/****************** Bit definition for ERTC_TSDT register *******************/ -/*!< DU configuration */ -#define ERTC_TSDT_DU_Pos (0U) -#define ERTC_TSDT_DU_Msk (0xFU << ERTC_TSDT_DU_Pos) /*!< 0x0000000F */ -#define ERTC_TSDT_DU ERTC_TSDT_DU_Msk /*!< DU[3:0] (Date units) */ -#define ERTC_TSDT_DU_0 (0x1U << ERTC_TSDT_DU_Pos) /*!< 0x00000001 */ -#define ERTC_TSDT_DU_1 (0x2U << ERTC_TSDT_DU_Pos) /*!< 0x00000002 */ -#define ERTC_TSDT_DU_2 (0x4U << ERTC_TSDT_DU_Pos) /*!< 0x00000004 */ -#define ERTC_TSDT_DU_3 (0x8U << ERTC_TSDT_DU_Pos) /*!< 0x00000008 */ - -/*!< DT configuration */ -#define ERTC_TSDT_DT_Pos (4U) -#define ERTC_TSDT_DT_Msk (0x3U << ERTC_TSDT_DT_Pos) /*!< 0x00000030 */ -#define ERTC_TSDT_DT ERTC_TSDT_DT_Msk /*!< DT[1:0] (Date tens) */ -#define ERTC_TSDT_DT_0 (0x1U << ERTC_TSDT_DT_Pos) /*!< 0x00000010 */ -#define ERTC_TSDT_DT_1 (0x2U << ERTC_TSDT_DT_Pos) /*!< 0x00000020 */ - -/*!< MU configuration */ -#define ERTC_TSDT_MU_Pos (8U) -#define ERTC_TSDT_MU_Msk (0xFU << ERTC_TSDT_MU_Pos) /*!< 0x00000F00 */ -#define ERTC_TSDT_MU ERTC_TSDT_MU_Msk /*!< MU[3:0] (Month units) */ -#define ERTC_TSDT_MU_0 (0x1U << ERTC_TSDT_MU_Pos) /*!< 0x00000100 */ -#define ERTC_TSDT_MU_1 (0x2U << ERTC_TSDT_MU_Pos) /*!< 0x00000200 */ -#define ERTC_TSDT_MU_2 (0x4U << ERTC_TSDT_MU_Pos) /*!< 0x00000400 */ -#define ERTC_TSDT_MU_3 (0x8U << ERTC_TSDT_MU_Pos) /*!< 0x00000800 */ - -#define ERTC_TSDT_MT_Pos (12U) -#define ERTC_TSDT_MT_Msk (0x1U << ERTC_TSDT_MT_Pos) /*!< 0x00001000 */ -#define ERTC_TSDT_MT ERTC_TSDT_MT_Msk /*!< Month tens */ - -/*!< WK configuration */ -#define ERTC_TSDT_WK_Pos (13U) -#define ERTC_TSDT_WK_Msk (0x7U << ERTC_TSDT_WK_Pos) /*!< 0x0000E000 */ -#define ERTC_TSDT_WK ERTC_TSDT_WK_Msk /*!< WK[2:0] (Week day) */ -#define ERTC_TSDT_WK_0 (0x1U << ERTC_TSDT_WK_Pos) /*!< 0x00002000 */ -#define ERTC_TSDT_WK_1 (0x2U << ERTC_TSDT_WK_Pos) /*!< 0x00004000 */ -#define ERTC_TSDT_WK_2 (0x4U << ERTC_TSDT_WK_Pos) /*!< 0x00008000 */ - -/****************** Bit definition for ERTC_TSSBS register ******************/ -#define ERTC_TSSBS_SBS_Pos (0U) -#define ERTC_TSSBS_SBS_Msk (0xFFFFU << ERTC_TSSBS_SBS_Pos) /*!< 0x0000FFFF */ -#define ERTC_TSSBS_SBS ERTC_TSSBS_SBS_Msk /*!< Sub-second value */ - -/****************** Bit definition for ERTC_SCAL register *******************/ -#define ERTC_SCAL_DEC_Pos (0U) -#define ERTC_SCAL_DEC_Msk (0x1FFU << ERTC_SCAL_DEC_Pos) /*!< 0x000001FF */ -#define ERTC_SCAL_DEC ERTC_SCAL_DEC_Msk /*!< Decrease ERTC clock */ -#define ERTC_SCAL_CAL16_Pos (13U) -#define ERTC_SCAL_CAL16_Msk (0x1U << ERTC_SCAL_CAL16_Pos) /*!< 0x00002000 */ -#define ERTC_SCAL_CAL16 ERTC_SCAL_CAL16_Msk /*!< 16 second calibration period */ -#define ERTC_SCAL_CAL8_Pos (14U) -#define ERTC_SCAL_CAL8_Msk (0x1U << ERTC_SCAL_CAL8_Pos) /*!< 0x00004000 */ -#define ERTC_SCAL_CAL8 ERTC_SCAL_CAL8_Msk /*!< 8 second calibration period */ -#define ERTC_SCAL_ADD_Pos (15U) -#define ERTC_SCAL_ADD_Msk (0x1U << ERTC_SCAL_ADD_Pos) /*!< 0x00008000 */ -#define ERTC_SCAL_ADD ERTC_SCAL_ADD_Msk /*!< Add ERTC clock */ - -/****************** Bit definition for ERTC_TAMP register *******************/ -#define ERTC_TAMP_TP1EN_Pos (0U) -#define ERTC_TAMP_TP1EN_Msk (0x1U << ERTC_TAMP_TP1EN_Pos) /*!< 0x00000001 */ -#define ERTC_TAMP_TP1EN ERTC_TAMP_TP1EN_Msk /*!< Tamper detection 1 enable */ -#define ERTC_TAMP_TP1EDG_Pos (1U) -#define ERTC_TAMP_TP1EDG_Msk (0x1U << ERTC_TAMP_TP1EDG_Pos) /*!< 0x00000002 */ -#define ERTC_TAMP_TP1EDG ERTC_TAMP_TP1EDG_Msk /*!< Tamper detection 1 valid edge */ -#define ERTC_TAMP_TPIEN_Pos (2U) -#define ERTC_TAMP_TPIEN_Msk (0x1U << ERTC_TAMP_TPIEN_Pos) /*!< 0x00000004 */ -#define ERTC_TAMP_TPIEN ERTC_TAMP_TPIEN_Msk /*!< Tamper detection interrupt enable */ -#define ERTC_TAMP_TPTSEN_Pos (7U) -#define ERTC_TAMP_TPTSEN_Msk (0x1U << ERTC_TAMP_TPTSEN_Pos) /*!< 0x00000080 */ -#define ERTC_TAMP_TPTSEN ERTC_TAMP_TPTSEN_Msk /*!< Tamper detection timestamp enable */ - -/*!< TPFREQ configuration */ -#define ERTC_TAMP_TPFREQ_Pos (8U) -#define ERTC_TAMP_TPFREQ_Msk (0x7U << ERTC_TAMP_TPFREQ_Pos) /*!< 0x00000700 */ -#define ERTC_TAMP_TPFREQ ERTC_TAMP_TPFREQ_Msk /*!< TPFREQ[2:0] (Tamper detection frequency) */ -#define ERTC_TAMP_TPFREQ_0 (0x1U << ERTC_TAMP_TPFREQ_Pos) /*!< 0x00000100 */ -#define ERTC_TAMP_TPFREQ_1 (0x2U << ERTC_TAMP_TPFREQ_Pos) /*!< 0x00000200 */ -#define ERTC_TAMP_TPFREQ_2 (0x4U << ERTC_TAMP_TPFREQ_Pos) /*!< 0x00000400 */ - -/*!< TPFLT configuration */ -#define ERTC_TAMP_TPFLT_Pos (11U) -#define ERTC_TAMP_TPFLT_Msk (0x3U << ERTC_TAMP_TPFLT_Pos) /*!< 0x00001800 */ -#define ERTC_TAMP_TPFLT ERTC_TAMP_TPFLT_Msk /*!< TPFLT[1:0] (Tamper detection filter time) */ -#define ERTC_TAMP_TPFLT_0 (0x1U << ERTC_TAMP_TPFLT_Pos) /*!< 0x00000800 */ -#define ERTC_TAMP_TPFLT_1 (0x2U << ERTC_TAMP_TPFLT_Pos) /*!< 0x00001000 */ - -/*!< TPPR configuration */ -#define ERTC_TAMP_TPPR_Pos (13U) -#define ERTC_TAMP_TPPR_Msk (0x3U << ERTC_TAMP_TPPR_Pos) /*!< 0x00006000 */ -#define ERTC_TAMP_TPPR ERTC_TAMP_TPPR_Msk /*!< TPPR[1:0] (Tamper detection pre-charge time) */ -#define ERTC_TAMP_TPPR_0 (0x1U << ERTC_TAMP_TPPR_Pos) /*!< 0x00002000 */ -#define ERTC_TAMP_TPPR_1 (0x2U << ERTC_TAMP_TPPR_Pos) /*!< 0x00004000 */ - -#define ERTC_TAMP_TPPU_Pos (15U) -#define ERTC_TAMP_TPPU_Msk (0x1U << ERTC_TAMP_TPPU_Pos) /*!< 0x00008000 */ -#define ERTC_TAMP_TPPU ERTC_TAMP_TPPU_Msk /*!< Tamper detection pull-up */ -#define ERTC_TAMP_OUTTYPE_Pos (18U) -#define ERTC_TAMP_OUTTYPE_Msk (0x1U << ERTC_TAMP_OUTTYPE_Pos) /*!< 0x00040000 */ -#define ERTC_TAMP_OUTTYPE ERTC_TAMP_OUTTYPE_Msk /*!< Output type */ - -/***************** Bit definition for ERTC_ALASBS register ******************/ -#define ERTC_ALASBS_SBS_Pos (0U) -#define ERTC_ALASBS_SBS_Msk (0x7FFFU << ERTC_ALASBS_SBS_Pos) /*!< 0x00007FFF */ -#define ERTC_ALASBS_SBS ERTC_ALASBS_SBS_Msk /*!< Sub-second value */ - -/*!< SBSMSK configuration */ -#define ERTC_ALASBS_SBSMSK_Pos (24U) -#define ERTC_ALASBS_SBSMSK_Msk (0xFU << ERTC_ALASBS_SBSMSK_Pos) /*!< 0x0F000000 */ -#define ERTC_ALASBS_SBSMSK ERTC_ALASBS_SBSMSK_Msk /*!< SBSMSK[3:0] (Sub-second mask) */ -#define ERTC_ALASBS_SBSMSK_0 (0x1U << ERTC_ALASBS_SBSMSK_Pos) /*!< 0x01000000 */ -#define ERTC_ALASBS_SBSMSK_1 (0x2U << ERTC_ALASBS_SBSMSK_Pos) /*!< 0x02000000 */ -#define ERTC_ALASBS_SBSMSK_2 (0x4U << ERTC_ALASBS_SBSMSK_Pos) /*!< 0x04000000 */ -#define ERTC_ALASBS_SBSMSK_3 (0x8U << ERTC_ALASBS_SBSMSK_Pos) /*!< 0x08000000 */ - -/***************** Bit definition for ERTC_ALBSBS register ******************/ -#define ERTC_ALBSBS_SBS_Pos (0U) -#define ERTC_ALBSBS_SBS_Msk (0x7FFFU << ERTC_ALBSBS_SBS_Pos) /*!< 0x00007FFF */ -#define ERTC_ALBSBS_SBS ERTC_ALBSBS_SBS_Msk /*!< Sub-second value */ - -/*!< SBSMSK configuration */ -#define ERTC_ALBSBS_SBSMSK_Pos (24U) -#define ERTC_ALBSBS_SBSMSK_Msk (0xFU << ERTC_ALBSBS_SBSMSK_Pos) /*!< 0x0F000000 */ -#define ERTC_ALBSBS_SBSMSK ERTC_ALBSBS_SBSMSK_Msk /*!< SBSMSK[3:0] (Sub-second mask) */ -#define ERTC_ALBSBS_SBSMSK_0 (0x1U << ERTC_ALBSBS_SBSMSK_Pos) /*!< 0x01000000 */ -#define ERTC_ALBSBS_SBSMSK_1 (0x2U << ERTC_ALBSBS_SBSMSK_Pos) /*!< 0x02000000 */ -#define ERTC_ALBSBS_SBSMSK_2 (0x4U << ERTC_ALBSBS_SBSMSK_Pos) /*!< 0x04000000 */ -#define ERTC_ALBSBS_SBSMSK_3 (0x8U << ERTC_ALBSBS_SBSMSK_Pos) /*!< 0x08000000 */ - -/****************** Bit definition for ERTC_BPR1 register *******************/ -#define ERTC_BPR1_DT_Pos (0U) -#define ERTC_BPR1_DT_Msk (0xFFFFFFFFU << ERTC_BPR1_DT_Pos) /*!< 0xFFFFFFFF */ -#define ERTC_BPR1_DT ERTC_BPR1_DT_Msk /*!< Battery powered domain data 1 */ - -/****************** Bit definition for ERTC_BPR2 register *******************/ -#define ERTC_BPR2_DT_Pos (0U) -#define ERTC_BPR2_DT_Msk (0xFFFFFFFFU << ERTC_BPR2_DT_Pos) /*!< 0xFFFFFFFF */ -#define ERTC_BPR2_DT ERTC_BPR2_DT_Msk /*!< Battery powered domain data 2 */ - -/****************** Bit definition for ERTC_BPR3 register *******************/ -#define ERTC_BPR3_DT_Pos (0U) -#define ERTC_BPR3_DT_Msk (0xFFFFFFFFU << ERTC_BPR3_DT_Pos) /*!< 0xFFFFFFFF */ -#define ERTC_BPR3_DT ERTC_BPR3_DT_Msk /*!< Battery powered domain data 3 */ - -/****************** Bit definition for ERTC_BPR4 register *******************/ -#define ERTC_BPR4_DT_Pos (0U) -#define ERTC_BPR4_DT_Msk (0xFFFFFFFFU << ERTC_BPR4_DT_Pos) /*!< 0xFFFFFFFF */ -#define ERTC_BPR4_DT ERTC_BPR4_DT_Msk /*!< Battery powered domain data 4 */ - -/****************** Bit definition for ERTC_BPR5 register *******************/ -#define ERTC_BPR5_DT_Pos (0U) -#define ERTC_BPR5_DT_Msk (0xFFFFFFFFU << ERTC_BPR5_DT_Pos) /*!< 0xFFFFFFFF */ -#define ERTC_BPR5_DT ERTC_BPR5_DT_Msk /*!< Battery powered domain data 5 */ - -/****************** Bit definition for ERTC_BPR6 register *******************/ -#define ERTC_BPR6_DT_Pos (0U) -#define ERTC_BPR6_DT_Msk (0xFFFFFFFFU << ERTC_BPR6_DT_Pos) /*!< 0xFFFFFFFF */ -#define ERTC_BPR6_DT ERTC_BPR6_DT_Msk /*!< Battery powered domain data 6 */ - -/****************** Bit definition for ERTC_BPR7 register *******************/ -#define ERTC_BPR7_DT_Pos (0U) -#define ERTC_BPR7_DT_Msk (0xFFFFFFFFU << ERTC_BPR7_DT_Pos) /*!< 0xFFFFFFFF */ -#define ERTC_BPR7_DT ERTC_BPR7_DT_Msk /*!< Battery powered domain data 7 */ - -/****************** Bit definition for ERTC_BPR8 register *******************/ -#define ERTC_BPR8_DT_Pos (0U) -#define ERTC_BPR8_DT_Msk (0xFFFFFFFFU << ERTC_BPR8_DT_Pos) /*!< 0xFFFFFFFF */ -#define ERTC_BPR8_DT ERTC_BPR8_DT_Msk /*!< Battery powered domain data 8 */ - -/****************** Bit definition for ERTC_BPR9 register *******************/ -#define ERTC_BPR9_DT_Pos (0U) -#define ERTC_BPR9_DT_Msk (0xFFFFFFFFU << ERTC_BPR9_DT_Pos) /*!< 0xFFFFFFFF */ -#define ERTC_BPR9_DT ERTC_BPR9_DT_Msk /*!< Battery powered domain data 9 */ - -/****************** Bit definition for ERTC_BPR10 register ******************/ -#define ERTC_BPR10_DT_Pos (0U) -#define ERTC_BPR10_DT_Msk (0xFFFFFFFFU << ERTC_BPR10_DT_Pos) /*!< 0xFFFFFFFF */ -#define ERTC_BPR10_DT ERTC_BPR10_DT_Msk /*!< Battery powered domain data 10 */ - -/****************** Bit definition for ERTC_BPR11 register ******************/ -#define ERTC_BPR11_DT_Pos (0U) -#define ERTC_BPR11_DT_Msk (0xFFFFFFFFU << ERTC_BPR11_DT_Pos) /*!< 0xFFFFFFFF */ -#define ERTC_BPR11_DT ERTC_BPR11_DT_Msk /*!< Battery powered domain data 11 */ - -/****************** Bit definition for ERTC_BPR12 register ******************/ -#define ERTC_BPR12_DT_Pos (0U) -#define ERTC_BPR12_DT_Msk (0xFFFFFFFFU << ERTC_BPR12_DT_Pos) /*!< 0xFFFFFFFF */ -#define ERTC_BPR12_DT ERTC_BPR12_DT_Msk /*!< Battery powered domain data 12 */ - -/****************** Bit definition for ERTC_BPR13 register ******************/ -#define ERTC_BPR13_DT_Pos (0U) -#define ERTC_BPR13_DT_Msk (0xFFFFFFFFU << ERTC_BPR13_DT_Pos) /*!< 0xFFFFFFFF */ -#define ERTC_BPR13_DT ERTC_BPR13_DT_Msk /*!< Battery powered domain data 13 */ - -/****************** Bit definition for ERTC_BPR14 register ******************/ -#define ERTC_BPR14_DT_Pos (0U) -#define ERTC_BPR14_DT_Msk (0xFFFFFFFFU << ERTC_BPR14_DT_Pos) /*!< 0xFFFFFFFF */ -#define ERTC_BPR14_DT ERTC_BPR14_DT_Msk /*!< Battery powered domain data 14 */ - -/****************** Bit definition for ERTC_BPR15 register ******************/ -#define ERTC_BPR15_DT_Pos (0U) -#define ERTC_BPR15_DT_Msk (0xFFFFFFFFU << ERTC_BPR15_DT_Pos) /*!< 0xFFFFFFFF */ -#define ERTC_BPR15_DT ERTC_BPR15_DT_Msk /*!< Battery powered domain data 15 */ - -/****************** Bit definition for ERTC_BPR16 register ******************/ -#define ERTC_BPR16_DT_Pos (0U) -#define ERTC_BPR16_DT_Msk (0xFFFFFFFFU << ERTC_BPR16_DT_Pos) /*!< 0xFFFFFFFF */ -#define ERTC_BPR16_DT ERTC_BPR16_DT_Msk /*!< Battery powered domain data 16 */ - -/****************** Bit definition for ERTC_BPR17 register ******************/ -#define ERTC_BPR17_DT_Pos (0U) -#define ERTC_BPR17_DT_Msk (0xFFFFFFFFU << ERTC_BPR17_DT_Pos) /*!< 0xFFFFFFFF */ -#define ERTC_BPR17_DT ERTC_BPR17_DT_Msk /*!< Battery powered domain data 17 */ - -/****************** Bit definition for ERTC_BPR18 register ******************/ -#define ERTC_BPR18_DT_Pos (0U) -#define ERTC_BPR18_DT_Msk (0xFFFFFFFFU << ERTC_BPR18_DT_Pos) /*!< 0xFFFFFFFF */ -#define ERTC_BPR18_DT ERTC_BPR18_DT_Msk /*!< Battery powered domain data 18 */ - -/****************** Bit definition for ERTC_BPR19 register ******************/ -#define ERTC_BPR19_DT_Pos (0U) -#define ERTC_BPR19_DT_Msk (0xFFFFFFFFU << ERTC_BPR19_DT_Pos) /*!< 0xFFFFFFFF */ -#define ERTC_BPR19_DT ERTC_BPR19_DT_Msk /*!< Battery powered domain data 19 */ - -/****************** Bit definition for ERTC_BPR20 register ******************/ -#define ERTC_BPR20_DT_Pos (0U) -#define ERTC_BPR20_DT_Msk (0xFFFFFFFFU << ERTC_BPR20_DT_Pos) /*!< 0xFFFFFFFF */ -#define ERTC_BPR20_DT ERTC_BPR20_DT_Msk /*!< Battery powered domain data 20 */ - -/************************* Number of backup registers *************************/ -#define ERTC_BPR_NUMBER 0x000000014U - -/* =========================================================================================================================== */ -/* ================ PWC ================ */ -/* =========================================================================================================================== */ -/****************** Bit definition for PWC_CTRL register *****************/ -#define PWC_CTRL_PVMEN (0x1U << 4) -#define PWC_CTRL_BPWEN (0x1U << 8) - - -/* =========================================================================================================================== */ -/* ================ FLASH ================ */ -/* =========================================================================================================================== */ -/****************** Bit definition for FLASH_STS register ****************/ -#define FLASH_STS_OBF (0x1U << 0) -#define FLASH_STS_PRGMERR (0x1U << 2) -#define FLASH_STS_EPPERR (0x1U << 4) -#define FLASH_STS_ODF (0x1U << 5) - -/****************** Bit definition for FLASH_CTRL register ***************/ -#define FLASH_CTRL_FPRGM (0x1U << 0) -#define FLASH_CTRL_SECERS (0x1U << 1) -#define FLASH_CTRL_BANKERS (0x1U << 2) -#define FLASH_CTRL_USDPRGM (0x1U << 4) -#define FLASH_CTRL_USDERS (0x1U << 5) -#define FLASH_CTRL_ERSTR (0x1U << 6) -#define FLASH_CTRL_OPLK (0x1U << 7) - - -/* =========================================================================================================================== */ -/* ================ TMR ================ */ -/* =========================================================================================================================== */ -/****************** Bit definition for TMR_IDEN register ****************/ -#define TMR_IDEN_OVFIEN (0x1U << 0) -#define TMR_IDEN_C1IEN (0x1U << 1) -#define TMR_IDEN_C2IEN (0x1U << 2) -#define TMR_IDEN_C3IEN (0x1U << 3) -#define TMR_IDEN_C4IEN (0x1U << 4) -#define TMR_IDEN_HALLIEN (0x1U << 5) -#define TMR_IDEN_TIEN (0x1U << 6) -#define TMR_IDEN_BRKIEN (0x1U << 7) -#define TMR_IDEN_OVFDEN (0x1U << 8) -#define TMR_IDEN_C1DEN (0x1U << 9) -#define TMR_IDEN_C2DEN (0x1U << 10) -#define TMR_IDEN_C3DEN (0x1U << 11) -#define TMR_IDEN_C4DEN (0x1U << 12) -#define TMR_IDEN_HALLDEN (0x1U << 13) -#define TMR_IDEN_TDEN (0x1U << 14) - - -/* =========================================================================================================================== */ -/* ================ DMA ================ */ -/* =========================================================================================================================== */ -/****************** Bit definition for DMA_CxCTRL register **************/ -#define DMA_CTRL_CHEN (0x1U << 0) -#define DMA_CTRL_FDTIEN (0x1U << 1) -#define DMA_CTRL_HDTIEN (0x1U << 2) -#define DMA_CTRL_DTERRIEN (0x1U << 3) -#define DMA_CTRL_DTD (0x1U << 4) -#define DMA_CTRL_LM (0x1U << 5) -#define DMA_CTRL_PINCM (0x1U << 6) -#define DMA_CTRL_MINCM (0x1U << 7) -#define DMA_CTRL_PWIDTH (0x3U << 8) -#define DMA_CTRL_PWIDTH_8BITS (0x0U << 8) -#define DMA_CTRL_PWIDTH_16BITS (0x1U << 8) -#define DMA_CTRL_PWIDTH_32BITS (0x2U << 8) -#define DMA_CTRL_MWIDTH (0x3U << 10) -#define DMA_CTRL_MWIDTH_8BITS (0x0U << 10) -#define DMA_CTRL_MWIDTH_16BITS (0x1U << 10) -#define DMA_CTRL_MWIDTH_32BITS (0x2U << 10) -#define DMA_CTRL_CHPL (0x3U << 12) -#define DMA_CTRL_CHPL_LOW (0x0U << 12) -#define DMA_CTRL_CHPL_MID (0x1U << 12) -#define DMA_CTRL_CHPL_HIGH (0x2U << 12) -#define DMA_CTRL_CHPL_HIGHEST (0x3U << 12) -#define DMA_CTRL_M2M (0x1U << 14) - -/****************** Bit definition for DMA_MUXSEL register *************/ -#define DMA_MUXSEL_TBL_SEL (0x1U << 0) - -/****************** Bit definition for DMA_MUXCxCTRL register *************/ -#define DMA_MUXCTRL_SYNCOVIEN (0x1U << 8) -#define DMA_MUXCTRL_EVTGEN (0x1U << 9) -#define DMA_MUXCTRL_SYNCEN (0x1U << 16) -#define DMA_MUXCTRL_SYNCPOL (0x3U << 17) -#define DMA_MUXCTRL_SYNCPOL_NONE (0x0U << 17) -#define DMA_MUXCTRL_SYNCPOL_RISING (0x1U << 17) -#define DMA_MUXCTRL_SYNCPOL_FALLING (0x2U << 17) -#define DMA_MUXCTRL_SYNCPOL_BOTH (0x3U << 17) - -/****************** Bit definition for DMA_MUXGxCTRL register *************/ -#define DMA_MUXGCTRL_TRGOVIEN (0x1U << 8) -#define DMA_MUXGCTRL_GEN (0x1U << 16) -#define DMA_MUXGCTRL_GPOL (0x3U << 17) -#define DMA_MUXGCTRL_GPOL_NONE (0x0U << 17) -#define DMA_MUXGCTRL_GPOL_RISING (0x1U << 17) -#define DMA_MUXGCTRL_GPOL_FALLING (0x2U << 17) -#define DMA_MUXGCTRL_GPOL_BOTH (0x3U << 17) - - -/* =========================================================================================================================== */ -/* ================ I2C ================ */ -/* =========================================================================================================================== */ -/****************** Bit definition for I2C_CTRL1 register ***************/ -#define I2C_CTRL1_I2CEN (0x1U << 0) -#define I2C_CTRL1_TDIEN (0x1U << 1) -#define I2C_CTRL1_RDIEN (0x1U << 2) -#define I2C_CTRL1_ADDRIEN (0x1U << 3) -#define I2C_CTRL1_ACKFAILIEN (0x1U << 4) -#define I2C_CTRL1_STOPIEN (0x1U << 5) -#define I2C_CTRL1_TDCIEN (0x1U << 6) -#define I2C_CTRL1_ERRIEN (0x1U << 7) -#define I2C_CTRL1_DMATEN (0x1U << 14) -#define I2C_CTRL1_DMAREN (0x1U << 15) -#define I2C_CTRL1_SCTRL (0x1U << 16) -#define I2C_CTRL1_STRETCH (0x1U << 17) -#define I2C_CTRL1_GCAEN (0x1U << 19) -#define I2C_CTRL1_HADDREN (0x1U << 20) -#define I2C_CTRL1_DEVADDREN (0x1U << 21) -#define I2C_CTRL1_SMBALERT (0x1U << 22) -#define I2C_CTRL1_PECEN (0x1U << 23) - -/****************** Bit definition for I2C_CTRL2 register ***************/ -#define I2C_CTRL2_DIR (0x1U << 10) -#define I2C_CTRL2_ADDR10 (0x1U << 11) -#define I2C_CTRL2_READH10 (0x1U << 12) -#define I2C_CTRL2_GENSTART (0x1U << 13) -#define I2C_CTRL2_GENSTOP (0x1U << 14) -#define I2C_CTRL2_NACKEN (0x1U << 15) -#define I2C_CTRL2_RLDEN (0x1U << 24) -#define I2C_CTRL2_ASTOPEN (0x1U << 25) -#define I2C_CTRL2_PECTEN (0x1U << 26) -#define I2C_CTRL2_CNT_MASK (0xFF << 16) - -/****************** Bit definition for I2C_TIMEOUT register ***************/ -#define I2C_TIMEOUT_TOMODE (0x1U << 12) -#define I2C_TIMEOUT_TOMODE_LOW (0x0U << 12) -#define I2C_TIMEOUT_TOMODE_HIGH (0x1U << 12) -#define I2C_TIMEOUT_TOEN (0x1U << 15) -#define I2C_TIMEOUT_EXTEN (0x1U << 31) - -/****************** Bit definition for I2C_STS register ***************/ -#define I2C_STS_TDBE (0x1U << 0) -#define I2C_STS_TDIS (0x1U << 1) -#define I2C_STS_RDBF (0x1U << 2) -#define I2C_STS_ADDRF (0x1U << 3) -#define I2C_STS_ACKFAILF (0x1U << 4) -#define I2C_STS_STOPF (0x1U << 5) -#define I2C_STS_TDC (0x1U << 6) -#define I2C_STS_TCRLD (0x1U << 7) -#define I2C_STS_BUSERR (0x1U << 8) -#define I2C_STS_ARLOST (0x1U << 9) -#define I2C_STS_OUF (0x1U << 10) -#define I2C_STS_PECERR (0x1U << 11) -#define I2C_STS_TMOUT (0x1U << 12) -#define I2C_STS_ALERTF (0x1U << 13) -#define I2C_STS_BUSYF (0x1U << 15) -#define I2C_STS_SDIR (0x1U << 16) - - -/* =========================================================================================================================== */ -/* ================ USART ================ */ -/* =========================================================================================================================== */ - - -/******************* Bit definition for USART_STS register **************/ -#define USART_STS_PERR (0x1U << 0) -#define USART_STS_FERR (0x1U << 1) -#define USART_STS_NERR (0x1U << 2) -#define USART_STS_ROERR (0x1U << 3) -#define USART_STS_IDLEF (0x1U << 4) -#define USART_STS_RDBF (0x1U << 5) -#define USART_STS_TDC (0x1U << 6) -#define USART_STS_TDBE (0x1U << 7) -#define USART_STS_BFF (0x1U << 8) -#define USART_STS_CTSCF (0x1U << 9) -#define USART_STS_RTODF (0x1U << 11) -#define USART_STS_CMDF (0x1U << 17) - -/******************* Bit definition for USART_DT register ***************/ -#define USART_DT_DT (0x1FFU << 0) - -/****************** Bit definition for USART_CTRL1 register *************/ -#define USART_CTRL1_SBF (0x1U << 0) -#define USART_CTRL1_RM (0x1U << 1) -#define USART_CTRL1_REN (0x1U << 2) -#define USART_CTRL1_TEN (0x1U << 3) -#define USART_CTRL1_IDLEIEN (0x1U << 4) -#define USART_CTRL1_RDBFIEN (0x1U << 5) -#define USART_CTRL1_TDCIEN (0x1U << 6) -#define USART_CTRL1_TDBEIEN (0x1U << 7) -#define USART_CTRL1_PERRIEN (0x1U << 8) -#define USART_CTRL1_PSEL (0x1U << 9) -#define USART_CTRL1_PEN (0x1U << 10) -#define USART_CTRL1_WUM (0x1U << 11) -#define USART_CTRL1_DBN0 (0x1U << 12) -#define USART_CTRL1_UEN (0x1U << 13) -#define USART_CTRL1_CMDIE (0x1U << 14) -#define USART_CTRL1_RETODIE (0x1U << 26) -#define USART_CTRL1_RTODEN (0x1U << 27) -#define USART_CTRL1_DBN1 (0x1U << 28) -#define USART_CTRL1_DBN_7BITS (0x1U << 28) -#define USART_CTRL1_DBN_8BITS (0x0U << 28) -#define USART_CTRL1_DBN_9BITS (0x1U << 12) -#define USART_CTRL1_DBN (0x1U << 12) - -/****************** Bit definition for USART_CTRL2 register *************/ -#define USART_CTRL2_IDL (0xFU << 0) -#define USART_CTRL2_IDBN (0x1U << 4) -#define USART_CTRL2_BFBN (0x1U << 5) -#define USART_CTRL2_BFIEN (0x1U << 6) -#define USART_CTRL2_LBCP (0x1U << 8) -#define USART_CTRL2_CLKPHA (0x1U << 9) -#define USART_CTRL2_CLKPOL (0x1U << 10) -#define USART_CTRL2_CLKEN (0x1U << 11) -#define USART_CTRL2_STOPBN (0x3U << 12) -#define USART_CTRL2_STOP_0 (0x1U << 12) -#define USART_CTRL2_STOP_1 (0x1U << 13) -#define USART_CTRL2_STOPBN_1_BITS (0x0U << 12) -#define USART_CTRL2_STOPBN_0P5_BITS (0x1U << 12) -#define USART_CTRL2_STOPBN_2_BITS (0x2U << 12) -#define USART_CTRL2_STOPBN_1P5_BITS (0x3U << 12) -#define USART_CTRL2_LINEN (0x1U << 14) -#define USART_CTRL2_TRPSWAP (0x1U << 15) -#define USART_CTRL2_RXREV (0x1U << 16) -#define USART_CTRL2_TXREV (0x1U << 17) -#define USART_CTRL2_DTREV (0x1U << 18) -#define USART_CTRL2_MTF (0x1U << 19) -#define USART_CTRL2_IDH (0xFU << 28) - -/****************** Bit definition for USART_CTRL3 register *************/ -#define USART_CTRL3_ERRIEN (0x1U << 0) -#define USART_CTRL3_IRDAEN (0x1U << 1) -#define USART_CTRL3_IRDALP (0x1U << 2) -#define USART_CTRL3_SLBEN (0x1U << 3) -#define USART_CTRL3_SCNACKEN (0x1U << 4) -#define USART_CTRL3_SCMEN (0x1U << 5) -#define USART_CTRL3_DMAREN (0x1U << 6) -#define USART_CTRL3_DMATEN (0x1U << 7) -#define USART_CTRL3_RTSEN (0x1U << 8) -#define USART_CTRL3_CTSEN (0x1U << 9) -#define USART_CTRL3_CTSCFIEN (0x1U << 10) -#define USART_CTRL3_RS485EN (0x1U << 14) -#define USART_CTRL3_DEP (0x1U << 15) - -/******************* Bit definition for USART_IFC register ***************/ -#define USART_IFC_RTODFC (0x1U << 11) -#define USART_IFC_CMDFC (0x1U << 17) - - -/* =========================================================================================================================== */ -/* ================ SPI ================ */ -/* =========================================================================================================================== */ - -/******************* Bit definition for SPI_CTRL1 register **************/ -#define SPI_CTRL1_CLKPHA (0x1U << 0) -#define SPI_CTRL1_CLKPOL (0x1U << 1) -#define SPI_CTRL1_MSTEN (0x1U << 2) -#define SPI_CTRL1_MDIV (0x7U << 3) -#define SPI_CTRL1_MDIV_2 (0x0U << 3) -#define SPI_CTRL1_MDIV_4 (0x1U << 3) -#define SPI_CTRL1_MDIV_8 (0x2U << 3) -#define SPI_CTRL1_MDIV_16 (0x3U << 3) -#define SPI_CTRL1_MDIV_32 (0x4U << 3) -#define SPI_CTRL1_MDIV_64 (0x5U << 3) -#define SPI_CTRL1_MDIV_128 (0x6U << 3) -#define SPI_CTRL1_MDIV_256 (0x7U << 3) -#define SPI_CTRL1_MDIV_512 (0x0U << 3) -#define SPI_CTRL1_MDIV_1024 (0x1U << 3) -#define SPI_CTRL1_SPIEN (0x1U << 6) -#define SPI_CTRL1_LTF (0x1U << 7) -#define SPI_CTRL1_SWCSIL (0x1U << 8) -#define SPI_CTRL1_SWCSEN (0x1U << 9) -#define SPI_CTRL1_ORA (0x1U << 10) -#define SPI_CTRL1_FBN (0x1U << 11) -#define SPI_CTRL1_NTC (0x1U << 12) -#define SPI_CTRL1_CCEN (0x1U << 13) -#define SPI_CTRL1_SLBTD (0x1U << 14) -#define SPI_CTRL1_SLBEN (0x1U << 15) - -/******************* Bit definition for SPI_CTRL2 register **************/ -#define SPI_CTRL2_DMAREN (0x1U << 0) -#define SPI_CTRL2_DMATEN (0x1U << 1) -#define SPI_CTRL2_HWCSOE (0x1U << 2) -#define SPI_CTRL2_TIEN (0x1U << 4) -#define SPI_CTRL2_ERRIE (0x1U << 5) -#define SPI_CTRL2_RDBFIE (0x1U << 6) -#define SPI_CTRL2_TDBEIE (0x1U << 7) -#define SPI_CTRL2_MDIV (0x1U << 8) -#define SPI_CTRL2_MDIV_512_1024 (0x1U << 8) -#define SPI_CTRL2_MDIV3EN (0x1U << 9) - -/******************* Bit definition for SPI_STS register ********************/ -#define SPI_STS_RDBF (0x1U << 0) -#define SPI_STS_TDBE (0x1U << 1) -#define SPI_STS_ACS (0x1U << 2) -#define SPI_STS_TUERR (0x1U << 3) -#define SPI_STS_CCERR (0x1U << 4) -#define SPI_STS_MMERR (0x1U << 5) -#define SPI_STS_ROERR (0x1U << 6) -#define SPI_STS_BF (0x1U << 7) -#define SPI_STS_CSPAS (0x1U << 8) - -/******************* Bit definition for SPI_I2SCTRL register *****************/ -#define SPI_I2SCTRL_I2SCBN (0x1U << 0) -#define SPI_I2SCTRL_I2SDBN (0x3U << 1) -#define SPI_I2SCTRL_I2SDBN_16BITS (0x0U << 1) -#define SPI_I2SCTRL_I2SDBN_24BITS (0x1U << 1) -#define SPI_I2SCTRL_I2SDBN_32BITS (0x2U << 1) -#define SPI_I2SCTRL_I2SDBN_NONE (0x3U << 1) -#define SPI_I2SCTRL_I2SCLKPOL (0x1U << 3) -#define SPI_I2SCTRL_STDSEL (0x3U << 4) -#define SPI_I2SCTRL_STDSEL_PHILIPS (0x0U << 4) -#define SPI_I2SCTRL_STDSEL_MSB (0x1U << 4) -#define SPI_I2SCTRL_STDSEL_LSB (0x2U << 4) -#define SPI_I2SCTRL_STDSEL_PCM (0x3U << 4) -#define SPI_I2SCTRL_PCMFSSEL (0x1U << 7) -#define SPI_I2SCTRL_OPERSEL (0x3U << 8) -#define SPI_I2SCTRL_OPERSEL_ST (0x0U << 8) -#define SPI_I2SCTRL_OPERSEL_SR (0x1U << 8) -#define SPI_I2SCTRL_OPERSEL_HT (0x2U << 8) -#define SPI_I2SCTRL_OPERSEL_HR (0x3U << 8) -#define SPI_I2SCTRL_I2SEN (0x1U << 10) -#define SPI_I2SCTRL_I2SMSEL (0x1U << 11) - -/******************* Bit definition for SPI_I2SCLKP register ************/ -#define SPI_I2SCLKP_I2SDIV_1 (0xFFU << 0) -#define SPI_I2SCLKP_I2SODD (0x1U << 8) -#define SPI_I2SCLKP_I2SMCLKOE (0x1U << 9) -#define SPI_I2SCLKP_I2SDIV_2 (0x3U << 10) - - -/* =========================================================================================================================== */ -/* ================ DEBUG ================ */ -/* =========================================================================================================================== */ - -/****************** Bit definition for DEBUG_APB1_PAUSE register **************/ -#define DEBUG_APB1_PAUSE_TMR2_PAUSE (0x1U << 0) -#define DEBUG_APB1_PAUSE_TMR3_PAUSE (0x1U << 1) -#define DEBUG_APB1_PAUSE_TMR4_PAUSE (0x1U << 2) -#define DEBUG_APB1_PAUSE_TMR6_PAUSE (0x1U << 4) -#define DEBUG_APB1_PAUSE_TMR7_PAUSE (0x1U << 5) -#define DEBUG_APB1_PAUSE_TMR13_PAUSE (0x1U << 7) -#define DEBUG_APB1_PAUSE_TMR14_PAUSE (0x1U << 8) -#define DEBUG_APB1_PAUSE_ERTC_PAUSE (0x1U << 10) -#define DEBUG_APB1_PAUSE_WWDT_PAUSE (0x1U << 11) -#define DEBUG_APB1_PAUSE_WDT_PAUSE (0x1U << 12) -#define DEBUG_APB1_PAUSE_I2C1_SMBUS_TIMEOUT (0x1U << 24) -#define DEBUG_APB1_PAUSE_CAN1_PAUSE (0x1U << 25) -#define DEBUG_APB1_PAUSE_I2C2_SMBUS_TIMEOUT (0x1U << 27) -#define DEBUG_APB1_PAUSE_I2C3_SMBUS_TIMEOUT (0x1U << 28) - -/****************** Bit definition for DEBUG_APB2_PAUSE register **************/ -#define DEBUG_APB2_PAUSE_TMR1_PAUSE (0x1U << 0) -#define DEBUG_APB2_PAUSE_TMR9_PAUSE (0x1U << 16) -#define DEBUG_APB2_PAUSE_TMR10_PAUSE (0x1U << 17) -#define DEBUG_APB2_PAUSE_TMR11_PAUSE (0x1U << 18) - -/** - * @} - */ - - - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415.h b/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415.h index ce0861468d..645864bcd6 100644 --- a/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415.h +++ b/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415.h @@ -90,17 +90,11 @@ * @{ */ -#if defined(AT32F415KB) +#if defined(AT32F415KB) || defined(AT32F415KC) #include "at32f415kx.h" -#elif defined(AT32F415KC) - #include "at32f415kx.h" -#elif defined(AT32F415CB) - #include "at32f415cx.h" -#elif defined(AT32F415CC) +#elif defined(AT32F415CB) || defined(AT32F415CC) #include "at32f415cx.h" -#elif defined(AT32F415RB) - #include "at32f415rx.h" -#elif defined(AT32F415RC) +#elif defined(AT32F415RB) || defined(AT32F415RC) #include "at32f415rx.h" #else #error "Please select first the target AT32F415 device used in your application (in at32f415.h file)" diff --git a/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415cx.h b/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415cx.h index acb83d0a07..39ea659757 100644 --- a/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415cx.h +++ b/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415cx.h @@ -3,7 +3,7 @@ * @file at32f415cx.h * @author Artery Technology & HorrorTroll & Zhaqian * @version v2.1.6 - * @date 13-December-2024 + * @date 13-Dec-2024 * @brief AT32F415Cx header file. * ************************************************************************** diff --git a/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415kx.h b/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415kx.h index 7b02735fa1..b74817ecdb 100644 --- a/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415kx.h +++ b/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415kx.h @@ -3,7 +3,7 @@ * @file at32f415kx.h * @author Artery Technology & HorrorTroll & Zhaqian * @version v2.1.6 - * @date 13-December-2024 + * @date 13-Dec-2024 * @brief AT32F415Kx header file. * ************************************************************************** diff --git a/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415rx.h b/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415rx.h index 9e8cee8114..bf6e685394 100644 --- a/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415rx.h +++ b/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415rx.h @@ -3,7 +3,7 @@ * @file at32f415rx.h * @author Artery Technology & HorrorTroll & Zhaqian * @version v2.1.6 - * @date 13-December-2024 + * @date 13-Dec-2024 * @brief AT32F415Rx header file. * ************************************************************************** diff --git a/os/common/startup/ARMCMx/compilers/GCC/ld/AT32F402xB.ld b/os/common/startup/ARMCMx/compilers/GCC/ld/AT32F402xB.ld new file mode 100644 index 0000000000..bf5bad6ee7 --- /dev/null +++ b/os/common/startup/ARMCMx/compilers/GCC/ld/AT32F402xB.ld @@ -0,0 +1,87 @@ +/* + Copyright (C) 2023..2025 Artery Technology + Copyright (C) 2023..2025 HorrorTroll (https://github.com/HorrorTroll) + Copyright (C) 2023..2025 Zhaqian (https://github.com/zhaqian12) + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * AT32F402xB memory setup. + */ +MEMORY +{ + flash0 (rx) : org = 0x08000000, len = 128k + flash1 (rx) : org = 0x00000000, len = 0 + flash2 (rx) : org = 0x00000000, len = 0 + flash3 (rx) : org = 0x00000000, len = 0 + flash4 (rx) : org = 0x00000000, len = 0 + flash5 (rx) : org = 0x00000000, len = 0 + flash6 (rx) : org = 0x00000000, len = 0 + flash7 (rx) : org = 0x00000000, len = 0 + ram0 (wx) : org = 0x20000000, len = 70k + ram1 (wx) : org = 0x00000000, len = 0 + ram2 (wx) : org = 0x00000000, len = 0 + ram3 (wx) : org = 0x00000000, len = 0 + ram4 (wx) : org = 0x00000000, len = 0 + ram5 (wx) : org = 0x00000000, len = 0 + ram6 (wx) : org = 0x00000000, len = 0 + ram7 (wx) : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash0); +REGION_ALIAS("VECTORS_FLASH_LMA", flash0); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash0); +REGION_ALIAS("XTORS_FLASH_LMA", flash0); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash0); +REGION_ALIAS("TEXT_FLASH_LMA", flash0); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash0); +REGION_ALIAS("RODATA_FLASH_LMA", flash0); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash0); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash0); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash0); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* Generic rules inclusion.*/ +INCLUDE rules.ld diff --git a/os/common/startup/ARMCMx/compilers/GCC/ld/AT32F402xC.ld b/os/common/startup/ARMCMx/compilers/GCC/ld/AT32F402xC.ld new file mode 100644 index 0000000000..af75b8c705 --- /dev/null +++ b/os/common/startup/ARMCMx/compilers/GCC/ld/AT32F402xC.ld @@ -0,0 +1,87 @@ +/* + Copyright (C) 2023..2025 Artery Technology + Copyright (C) 2023..2025 HorrorTroll (https://github.com/HorrorTroll) + Copyright (C) 2023..2025 Zhaqian (https://github.com/zhaqian12) + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * AT32F402xC memory setup. + */ +MEMORY +{ + flash0 (rx) : org = 0x08000000, len = 256k + flash1 (rx) : org = 0x00000000, len = 0 + flash2 (rx) : org = 0x00000000, len = 0 + flash3 (rx) : org = 0x00000000, len = 0 + flash4 (rx) : org = 0x00000000, len = 0 + flash5 (rx) : org = 0x00000000, len = 0 + flash6 (rx) : org = 0x00000000, len = 0 + flash7 (rx) : org = 0x00000000, len = 0 + ram0 (wx) : org = 0x20000000, len = 102k + ram1 (wx) : org = 0x00000000, len = 0 + ram2 (wx) : org = 0x00000000, len = 0 + ram3 (wx) : org = 0x00000000, len = 0 + ram4 (wx) : org = 0x00000000, len = 0 + ram5 (wx) : org = 0x00000000, len = 0 + ram6 (wx) : org = 0x00000000, len = 0 + ram7 (wx) : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash0); +REGION_ALIAS("VECTORS_FLASH_LMA", flash0); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash0); +REGION_ALIAS("XTORS_FLASH_LMA", flash0); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash0); +REGION_ALIAS("TEXT_FLASH_LMA", flash0); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash0); +REGION_ALIAS("RODATA_FLASH_LMA", flash0); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash0); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash0); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash0); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* Generic rules inclusion.*/ +INCLUDE rules.ld diff --git a/os/common/startup/ARMCMx/compilers/GCC/ld/AT32F405xB.ld b/os/common/startup/ARMCMx/compilers/GCC/ld/AT32F405xB.ld index bc182b3840..e8a41790a3 100644 --- a/os/common/startup/ARMCMx/compilers/GCC/ld/AT32F405xB.ld +++ b/os/common/startup/ARMCMx/compilers/GCC/ld/AT32F405xB.ld @@ -1,5 +1,8 @@ /* - COPYRIGHT(C) 2023, Artery + Copyright (C) 2023..2025 Artery Technology + Copyright (C) 2023..2025 HorrorTroll (https://github.com/HorrorTroll) + Copyright (C) 2023..2025 Zhaqian (https://github.com/zhaqian12) + Copyright (C) 2024..2025 Maxjta (https://github.com/Maxjta) Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -15,7 +18,7 @@ */ /* - * AT32F402_405xB memory setup. + * AT32F405xB memory setup. */ MEMORY { @@ -27,7 +30,7 @@ MEMORY flash5 (rx) : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0 - ram0 (wx) : org = 0x20000000, len = 64k + ram0 (wx) : org = 0x20000000, len = 70k ram1 (wx) : org = 0x00000000, len = 0 ram2 (wx) : org = 0x00000000, len = 0 ram3 (wx) : org = 0x00000000, len = 0 diff --git a/os/common/startup/ARMCMx/compilers/GCC/ld/AT32F405xC.ld b/os/common/startup/ARMCMx/compilers/GCC/ld/AT32F405xC.ld index 758f2285e4..602a3db0f0 100644 --- a/os/common/startup/ARMCMx/compilers/GCC/ld/AT32F405xC.ld +++ b/os/common/startup/ARMCMx/compilers/GCC/ld/AT32F405xC.ld @@ -1,5 +1,8 @@ /* - COPYRIGHT(C) 2023, Artery + Copyright (C) 2023..2025 Artery Technology + Copyright (C) 2023..2025 HorrorTroll (https://github.com/HorrorTroll) + Copyright (C) 2023..2025 Zhaqian (https://github.com/zhaqian12) + Copyright (C) 2024..2025 Maxjta (https://github.com/Maxjta) Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -15,7 +18,7 @@ */ /* - * AT32F402_405xC memory setup. + * AT32F405xC memory setup. */ MEMORY { @@ -27,7 +30,7 @@ MEMORY flash5 (rx) : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0 - ram0 (wx) : org = 0x20000000, len = 96k + ram0 (wx) : org = 0x20000000, len = 102k ram1 (wx) : org = 0x00000000, len = 0 ram2 (wx) : org = 0x00000000, len = 0 ram3 (wx) : org = 0x00000000, len = 0 diff --git a/os/common/startup/ARMCMx/compilers/GCC/ld/AT32F415x8.ld b/os/common/startup/ARMCMx/compilers/GCC/ld/AT32F415x8.ld index f42f326a33..7e91888f83 100644 --- a/os/common/startup/ARMCMx/compilers/GCC/ld/AT32F415x8.ld +++ b/os/common/startup/ARMCMx/compilers/GCC/ld/AT32F415x8.ld @@ -1,7 +1,7 @@ /* - Copyright (C) 2023..2024 Artery Technology - Copyright (C) 2023..2024 HorrorTroll (https://github.com/HorrorTroll) - Copyright (C) 2023..2024 Zhaqian (https://github.com/zhaqian12) + Copyright (C) 2023..2025 Artery Technology + Copyright (C) 2023..2025 HorrorTroll (https://github.com/HorrorTroll) + Copyright (C) 2023..2025 Zhaqian (https://github.com/zhaqian12) Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/common/startup/ARMCMx/compilers/GCC/ld/AT32F415xB.ld b/os/common/startup/ARMCMx/compilers/GCC/ld/AT32F415xB.ld index 5ddf72c8f7..d30d2b5578 100644 --- a/os/common/startup/ARMCMx/compilers/GCC/ld/AT32F415xB.ld +++ b/os/common/startup/ARMCMx/compilers/GCC/ld/AT32F415xB.ld @@ -1,7 +1,7 @@ /* - Copyright (C) 2023..2024 Artery Technology - Copyright (C) 2023..2024 HorrorTroll (https://github.com/HorrorTroll) - Copyright (C) 2023..2024 Zhaqian (https://github.com/zhaqian12) + Copyright (C) 2023..2025 Artery Technology + Copyright (C) 2023..2025 HorrorTroll (https://github.com/HorrorTroll) + Copyright (C) 2023..2025 Zhaqian (https://github.com/zhaqian12) Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/common/startup/ARMCMx/compilers/GCC/ld/AT32F415xC.ld b/os/common/startup/ARMCMx/compilers/GCC/ld/AT32F415xC.ld index 4625d97aa9..d676bf724d 100644 --- a/os/common/startup/ARMCMx/compilers/GCC/ld/AT32F415xC.ld +++ b/os/common/startup/ARMCMx/compilers/GCC/ld/AT32F415xC.ld @@ -1,7 +1,7 @@ /* - Copyright (C) 2023..2024 Artery Technology - Copyright (C) 2023..2024 HorrorTroll (https://github.com/HorrorTroll) - Copyright (C) 2023..2024 Zhaqian (https://github.com/zhaqian12) + Copyright (C) 2023..2025 Artery Technology + Copyright (C) 2023..2025 HorrorTroll (https://github.com/HorrorTroll) + Copyright (C) 2023..2025 Zhaqian (https://github.com/zhaqian12) Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_at32f405xx.mk b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_at32f402.mk similarity index 77% rename from os/common/startup/ARMCMx/compilers/GCC/mk/startup_at32f405xx.mk rename to os/common/startup/ARMCMx/compilers/GCC/mk/startup_at32f402.mk index ac07851b44..eb7941c8ef 100644 --- a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_at32f405xx.mk +++ b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_at32f402.mk @@ -1,14 +1,14 @@ -# List of the ChibiOS generic AT32F402_405 startup and CMSIS files. -STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c +# List of the ChibiOS generic AT32F402x startup and CMSIS files. +STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S \ - $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.S \ + $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.S STARTUPINC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \ $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld \ - $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/devices/AT32F402_405xx \ + $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/devices/AT32F402 \ $(CHIBIOS)/os/common/ext/ARM/CMSIS/Core/Include \ - $(CHIBIOS_CONTRIB)/os/common/ext/CMSIS/ArteryTek/AT32F402_405xx + $(CHIBIOS_CONTRIB)/os/common/ext/CMSIS/ArteryTek/AT32F402_405 STARTUPLD = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld STARTUPLD_CONTRIB = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/ld @@ -16,4 +16,4 @@ STARTUPLD_CONTRIB = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/l # Shared variables ALLXASMSRC += $(STARTUPASM) ALLCSRC += $(STARTUPSRC) -ALLINC += $(STARTUPINC) \ No newline at end of file +ALLINC += $(STARTUPINC) diff --git a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_at32f405.mk b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_at32f405.mk new file mode 100644 index 0000000000..60126d9269 --- /dev/null +++ b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_at32f405.mk @@ -0,0 +1,19 @@ +# List of the ChibiOS generic AT32F405x startup and CMSIS files. +STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c + +STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S \ + $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.S + +STARTUPINC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \ + $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld \ + $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/devices/AT32F405 \ + $(CHIBIOS)/os/common/ext/ARM/CMSIS/Core/Include \ + $(CHIBIOS_CONTRIB)/os/common/ext/CMSIS/ArteryTek/AT32F402_405 + +STARTUPLD = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld +STARTUPLD_CONTRIB = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/ld + +# Shared variables +ALLXASMSRC += $(STARTUPASM) +ALLCSRC += $(STARTUPSRC) +ALLINC += $(STARTUPINC) diff --git a/os/common/startup/ARMCMx/devices/AT32F402_405xx/cmparams.h b/os/common/startup/ARMCMx/devices/AT32F402/cmparams.h similarity index 59% rename from os/common/startup/ARMCMx/devices/AT32F402_405xx/cmparams.h rename to os/common/startup/ARMCMx/devices/AT32F402/cmparams.h index 3b4ed7770d..7c37f465f7 100644 --- a/os/common/startup/ARMCMx/devices/AT32F402_405xx/cmparams.h +++ b/os/common/startup/ARMCMx/devices/AT32F402/cmparams.h @@ -1,7 +1,8 @@ /* ChibiOS/RT - Copyright (C) 2006-2014 Giovanni Di Sirio. - ChibiOS/RT - Copyright (C) 2023..2024 Zhaqian - ChibiOS/RT - Copyright (C) 2023..2024 Maxjta + (C) 2015 RedoX (https://github.com/RedoXyde) + (C) 2023-2025 HorrorTroll (https://github.com/HorrorTroll) + (C) 2023-2025 Zhaqian (https://github.com/zhaqian12) This file is part of ChibiOS/RT. @@ -12,21 +13,21 @@ ChibiOS/RT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License - along with this program. If not, see . + along with this program. If not, see . */ /** - * @file AT32F402_405xx/cmparams.h - * @brief ARM Cortex-M4 parameters for the ArteryTek AT32F402_405 + * @file AT32F402/cmparams.h + * @brief ARM Cortex-M4F parameters for the Artery AT32F402 * - * @defgroup ARMCMx_AT32F402_405 ArteryTek AT32F402_405 Specific Parameters + * @defgroup ARMCMx_AT32F402 Artery AT32F402 Specific Parameters * @ingroup ARMCMx_SPECIFIC - * @details This file contains the Cortex-M4 specific parameters for the - * ArteryTek AT32F402_405 platform. + * @details This file contains the Cortex-M4F specific parameters for the + * Artery AT32F402 platform. * @{ */ @@ -53,26 +54,32 @@ */ #define CORTEX_PRIORITY_BITS 4 +/* If the device type is not externally defined, for example from the Makefile, + then a file named board.h is included. This file must contain a device + definition compatible with the include file.*/ +#if !defined(AT32F402KB) && !defined(AT32F402KC) && !defined(AT32F402CB) && \ + !defined(AT32F402CC) && !defined(AT32F402RB) && !defined(AT32F402RC) +#include "board.h" +#endif + /** * @brief Number of interrupt vectors. * @note This number does not include the 16 system vectors and must be * rounded to a multiple of 8. */ -#define CORTEX_NUM_VECTORS 112 +#define CORTEX_NUM_VECTORS 104 /* The following code is not processed when the file is included from an asm module.*/ #if !defined(_FROM_ASM_) -#if !defined (AT32F405xx) && !defined (AT32F402xx) - #include "board.h" -#endif - /* Including the device CMSIS header. Note, we are not using the definitions from this header because we need this file to be usable also from assembler source files. We verify that the info matches instead.*/ -#include "at32f402_405xx.h" +#include "at32f402_405.h" +/*lint -save -e9029 [10.4] Signedness comes from external files, it is + unpredictable but gives no problems.*/ #if CORTEX_MODEL != __CORTEX_M #error "CMSIS __CORTEX_M mismatch" #endif @@ -80,6 +87,7 @@ #if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS #error "CMSIS __NVIC_PRIO_BITS mismatch" #endif +/*lint -restore*/ #endif /* !defined(_FROM_ASM_) */ diff --git a/os/common/startup/ARMCMx/devices/AT32F405/cmparams.h b/os/common/startup/ARMCMx/devices/AT32F405/cmparams.h new file mode 100644 index 0000000000..a39f91d252 --- /dev/null +++ b/os/common/startup/ARMCMx/devices/AT32F405/cmparams.h @@ -0,0 +1,97 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2014 Giovanni Di Sirio. + (C) 2015 RedoX (https://github.com/RedoXyde) + (C) 2023-2025 HorrorTroll (https://github.com/HorrorTroll) + (C) 2023-2025 Zhaqian (https://github.com/zhaqian12) + (C) 2024-2025 Maxjta (https://github.com/Maxjta) + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file AT32F405/cmparams.h + * @brief ARM Cortex-M4F parameters for the Artery AT32F405 + * + * @defgroup ARMCMx_AT32F405 Artery AT32F405 Specific Parameters + * @ingroup ARMCMx_SPECIFIC + * @details This file contains the Cortex-M4F specific parameters for the + * Artery AT32F405 platform. + * @{ + */ + +#ifndef _CMPARAMS_H_ +#define _CMPARAMS_H_ + +/** + * @brief Cortex core model. + */ +#define CORTEX_MODEL 4 + +/** + * @brief Systick unit presence. + */ +#define CORTEX_HAS_ST TRUE + +/** + * @brief Floating Point unit presence. + */ +#define CORTEX_HAS_FPU TRUE + +/** + * @brief Number of bits in priority masks. + */ +#define CORTEX_PRIORITY_BITS 4 + +/* If the device type is not externally defined, for example from the Makefile, + then a file named board.h is included. This file must contain a device + definition compatible with the include file.*/ +#if !defined(AT32F405KB) && !defined(AT32F405KC) && !defined(AT32F405CB) && \ + !defined(AT32F405CC) && !defined(AT32F405RB) && !defined(AT32F405RC) +#include "board.h" +#endif + +/** + * @brief Number of interrupt vectors. + * @note This number does not include the 16 system vectors and must be + * rounded to a multiple of 8. + */ +#define CORTEX_NUM_VECTORS 104 + +/* The following code is not processed when the file is included from an + asm module.*/ +#if !defined(_FROM_ASM_) + +/* Including the device CMSIS header. Note, we are not using the definitions + from this header because we need this file to be usable also from + assembler source files. We verify that the info matches instead.*/ +#include "at32f402_405.h" + +/*lint -save -e9029 [10.4] Signedness comes from external files, it is + unpredictable but gives no problems.*/ +#if CORTEX_MODEL != __CORTEX_M +#error "CMSIS __CORTEX_M mismatch" +#endif + +#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS +#error "CMSIS __NVIC_PRIO_BITS mismatch" +#endif +/*lint -restore*/ + +#endif /* !defined(_FROM_ASM_) */ + +#endif /* _CMPARAMS_H_ */ + +/** @} */ diff --git a/os/common/startup/ARMCMx/devices/AT32F415/cmparams.h b/os/common/startup/ARMCMx/devices/AT32F415/cmparams.h index 5a37704e76..5a2164936c 100644 --- a/os/common/startup/ARMCMx/devices/AT32F415/cmparams.h +++ b/os/common/startup/ARMCMx/devices/AT32F415/cmparams.h @@ -1,8 +1,8 @@ /* ChibiOS/RT - Copyright (C) 2006-2014 Giovanni Di Sirio. (C) 2015 RedoX (https://github.com/RedoXyde) - (C) 2023-2024 HorrorTroll (https://github.com/HorrorTroll) - (C) 2023-2024 Zhaqian (https://github.com/zhaqian12) + (C) 2023-2025 HorrorTroll (https://github.com/HorrorTroll) + (C) 2023-2025 Zhaqian (https://github.com/zhaqian12) This file is part of ChibiOS/RT. diff --git a/os/hal/boards/AT_START_F402/board.c b/os/hal/boards/AT_START_F402/board.c new file mode 100644 index 0000000000..bce33e714d --- /dev/null +++ b/os/hal/boards/AT_START_F402/board.c @@ -0,0 +1,158 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "hal.h" +#include "at32_gpio.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** + * @brief Type of AT32 GPIO port setup. + */ +typedef struct { + uint32_t cfgr; + uint32_t omode; + uint32_t odrvr; + uint32_t pull; + uint32_t odt; + uint32_t muxl; + uint32_t muxh; + uint32_t hdrv; +} gpio_setup_t; + +/** + * @brief Type of AT32 GPIO initialization data. + */ +typedef struct { +#if AT32_HAS_GPIOA || defined(__DOXYGEN__) + gpio_setup_t PAData; +#endif +#if AT32_HAS_GPIOB || defined(__DOXYGEN__) + gpio_setup_t PBData; +#endif +#if AT32_HAS_GPIOC || defined(__DOXYGEN__) + gpio_setup_t PCData; +#endif +#if AT32_HAS_GPIOD || defined(__DOXYGEN__) + gpio_setup_t PDData; +#endif +#if AT32_HAS_GPIOF || defined(__DOXYGEN__) + gpio_setup_t PFData; +#endif +} gpio_config_t; + +/** + * @brief AT32 GPIO static initialization data. + */ +static const gpio_config_t gpio_default_config = { +#if AT32_HAS_GPIOA + {VAL_GPIOA_CFGR, VAL_GPIOA_OMODE, VAL_GPIOA_ODRVR, VAL_GPIOA_PULL, + VAL_GPIOA_ODT, VAL_GPIOA_MUXL, VAL_GPIOA_MUXH, VAL_GPIOA_HDRV}, +#endif +#if AT32_HAS_GPIOB + {VAL_GPIOB_CFGR, VAL_GPIOB_OMODE, VAL_GPIOB_ODRVR, VAL_GPIOB_PULL, + VAL_GPIOB_ODT, VAL_GPIOB_MUXL, VAL_GPIOB_MUXH, VAL_GPIOB_HDRV}, +#endif +#if AT32_HAS_GPIOC + {VAL_GPIOC_CFGR, VAL_GPIOC_OMODE, VAL_GPIOC_ODRVR, VAL_GPIOC_PULL, + VAL_GPIOC_ODT, VAL_GPIOC_MUXL, VAL_GPIOC_MUXH, VAL_GPIOC_HDRV}, +#endif +#if AT32_HAS_GPIOD + {VAL_GPIOD_CFGR, VAL_GPIOD_OMODE, VAL_GPIOD_ODRVR, VAL_GPIOD_PULL, + VAL_GPIOD_ODT, VAL_GPIOD_MUXL, VAL_GPIOD_MUXH, VAL_GPIOD_HDRV}, +#endif +#if AT32_HAS_GPIOF + {VAL_GPIOF_CFGR, VAL_GPIOF_OMODE, VAL_GPIOF_ODRVR, VAL_GPIOF_PULL, + VAL_GPIOF_ODT, VAL_GPIOF_MUXL, VAL_GPIOF_MUXH, VAL_GPIOF_HDRV}, +#endif +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static void gpio_init(at32_gpio_t *gpiop, const gpio_setup_t *config) { + gpiop->OMODE = config->omode; + gpiop->ODRVR = config->odrvr; + gpiop->PULL = config->pull; + gpiop->ODT = config->odt; + gpiop->MUXL = config->muxl; + gpiop->MUXH = config->muxh; + gpiop->HDRV = config->hdrv; + gpiop->CFGR = config->cfgr; +} + +static void at32_gpio_init(void) { + /* Enabling GPIO-related clocks, the mask comes from the + registry header file.*/ + crmResetAHB1(AT32_GPIO_EN_MASK); + crmEnableAHB1(AT32_GPIO_EN_MASK, true); + + /* Initializing all the defined GPIO ports.*/ +#if AT32_HAS_GPIOA + gpio_init(GPIOA, &gpio_default_config.PAData); +#endif +#if AT32_HAS_GPIOB + gpio_init(GPIOB, &gpio_default_config.PBData); +#endif +#if AT32_HAS_GPIOC + gpio_init(GPIOC, &gpio_default_config.PCData); +#endif +#if AT32_HAS_GPIOD + gpio_init(GPIOD, &gpio_default_config.PDData); +#endif +#if AT32_HAS_GPIOF + gpio_init(GPIOF, &gpio_default_config.PFData); +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Early initialization code. + * @details GPIO ports and system clocks are initialized before everything + * else. + */ +void __early_init(void) { + at32_gpio_init(); + at32_clock_init(); +} + +/** + * @brief Board-specific initialization code. + * @note You can add your board-specific code here. + */ +void boardInit(void) { + +} diff --git a/os/hal/boards/AT_START_F402/board.h b/os/hal/boards/AT_START_F402/board.h new file mode 100644 index 0000000000..6268475ee4 --- /dev/null +++ b/os/hal/boards/AT_START_F402/board.h @@ -0,0 +1,685 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/* + * Setup for a AT-START-F402 board. + */ + +/* + * Board identifier. + */ +#define BOARD_AT_START_F402 +#define BOARD_NAME "Artery AT-START-F402" + +/* + * Board oscillators-related settings. + */ +#if !defined(AT32_LEXTCLK) +#define AT32_LEXTCLK 32768 +#endif + +#if !defined(AT32_HEXTCLK) +#define AT32_HEXTCLK 12000000 +#endif + +/* + * MCU type, supported types are defined in ./os/hal/platforms/hal_lld.h. + */ +#define AT32F402RC + +/* + * IO pins assignments. + */ +#define GPIOA_BUTTON 0U +#define GPIOA_ARD_A1 1U +#define GPIOA_ARD_D1 2U +#define GPIOA_ARD_D0 3U +#define GPIOA_ARD_A2 4U +#define GPIOA_ARD_D13 5U +#define GPIOA_ARD_D12 6U +#define GPIOA_ARD_D11 7U +#define GPIOA_ARD_D7 8U +#define GPIOA_ARD_D8 9U +#define GPIOA_ARD_D2 10U +#define GPIOA_PIN11 11U +#define GPIOA_PIN12 12U +#define GPIOA_SWDIO 13U +#define GPIOA_SWCLK 14U +#define GPIOA_ARD_D10 15U + +#define GPIOB_ARD_A3 0U +#define GPIOB_PIN1 1U +#define GPIOB_PIN2 2U +#define GPIOB_SWO 3U +#define GPIOB_ARD_D5 4U +#define GPIOB_ARD_D4 5U +#define GPIOB_PIN6 6U +#define GPIOB_PIN7 7U +#define GPIOB_ARD_SCL 8U +#define GPIOB_ARD_SDA 9U +#define GPIOB_ARD_D6 10U +#define GPIOB_PIN11 11U +#define GPIOB_ARD_NSS 12U +#define GPIOB_ARD_SCK 13U +#define GPIOB_PIN14 14U +#define GPIOB_PIN15 15U + +#define GPIOC_ARD_A5 0U +#define GPIOC_ARD_A4 1U +#define GPIOC_ARD_MISO 2U +#define GPIOC_ARD_MOSI 3U +#define GPIOC_ARD_PC4 4U +#define GPIOC_PIN5 5U +#define GPIOC_PIN6 6U +#define GPIOC_ARD_D9 7U +#define GPIOC_PIN8 8U +#define GPIOC_PIN9 9U +#define GPIOC_PIN10 10U +#define GPIOC_PIN11 11U +#define GPIOC_PIN12 12U +#define GPIOC_BUTTON 13U +#define GPIOC_LEXT_IN 14U +#define GPIOC_LEXT_OUT 15U + +#define GPIOD_PIN2 2U + +#define GPIOF_HEXT_IN 0U +#define GPIOF_HEXT_OUT 1U +#define GPIOF_LED_RED 4U +#define GPIOF_LED_YELLOW 5U +#define GPIOF_LED_GREEN 6U +#define GPIOF_PIN7 7U +#define GPIOF_PIN11 11U + +/* + * IO lines assignments. + */ +#define LINE_BUTTON PAL_LINE(GPIOA, 0U) +#define LINE_ARD_A1 PAL_LINE(GPIOA, 1U) +#define LINE_ARD_D1 PAL_LINE(GPIOA, 2U) +#define LINE_ARD_D0 PAL_LINE(GPIOA, 3U) +#define LINE_ARD_A2 PAL_LINE(GPIOA, 4U) +#define LINE_ARD_D13 PAL_LINE(GPIOA, 5U) +#define LINE_ARD_D12 PAL_LINE(GPIOA, 6U) +#define LINE_ARD_D11 PAL_LINE(GPIOA, 7U) +#define LINE_ARD_D7 PAL_LINE(GPIOA, 8U) +#define LINE_ARD_D8 PAL_LINE(GPIOA, 9U) +#define LINE_ARD_D2 PAL_LINE(GPIOA, 10U) +#define LINE_SWDIO PAL_LINE(GPIOA, 13U) +#define LINE_SWCLK PAL_LINE(GPIOA, 14U) +#define LINE_ARD_D10 PAL_LINE(GPIOA, 15U) +#define LINE_ARD_A3 PAL_LINE(GPIOB, 0U) +#define LINE_SWO PAL_LINE(GPIOB, 3U) +#define LINE_ARD_D5 PAL_LINE(GPIOB, 4U) +#define LINE_ARD_D4 PAL_LINE(GPIOB, 5U) +#define LINE_ARD_SCL PAL_LINE(GPIOB, 8U) +#define LINE_ARD_SDA PAL_LINE(GPIOB, 9U) +#define LINE_ARD_D6 PAL_LINE(GPIOB, 10U) +#define LINE_ARD_NSS PAL_LINE(GPIOB, 12U) +#define LINE_ARD_SCK PAL_LINE(GPIOB, 13U) +#define LINE_ARD_A5 PAL_LINE(GPIOC, 0U) +#define LINE_ARD_A4 PAL_LINE(GPIOC, 1U) +#define LINE_ARD_MISO PAL_LINE(GPIOC, 2U) +#define LINE_ARD_MOSI PAL_LINE(GPIOC, 3U) +#define LINE_ARD_PC4 PAL_LINE(GPIOC, 4U) +#define LINE_ARD_D9 PAL_LINE(GPIOC, 7U) +#define LINE_BUTTON_ALT PAL_LINE(GPIOC, 13U) +#define LINE_LEXT_IN PAL_LINE(GPIOC, 14U) +#define LINE_LEXT_OUT PAL_LINE(GPIOC, 15U) +#define LINE_HEXT_IN PAL_LINE(GPIOF, 0U) +#define LINE_HEXT_OUT PAL_LINE(GPIOF, 1U) +#define LINE_LED_RED PAL_LINE(GPIOF, 4U) +#define LINE_LED_YELLOW PAL_LINE(GPIOF, 5U) +#define LINE_LED_GREEN PAL_LINE(GPIOF, 6U) + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * Please refer to the AT32 Reference Manual for details. + */ +#define PIN_MODE_INPUT(n) (0U << ((n) * 2U)) +#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U)) +#define PIN_MODE_MUX(n) (2U << ((n) * 2U)) +#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U)) +#define PIN_ODT_LOW(n) (0U << (n)) +#define PIN_ODT_HIGH(n) (1U << (n)) +#define PIN_OMODE_PUSHPULL(n) (0U << (n)) +#define PIN_OMODE_OPENDRAIN(n) (1U << (n)) +#define PIN_ODRVR_STRONGER(n) (1U << ((n) * 2U)) +#define PIN_ODRVR_MODERATE(n) (3U << ((n) * 2U)) +#define PIN_PULL_FLOATING(n) (0U << ((n) * 2U)) +#define PIN_PULL_PULLUP(n) (1U << ((n) * 2U)) +#define PIN_PULL_PULLDOWN(n) (2U << ((n) * 2U)) +#define PIN_IOMUX_MUX(n, v) ((v) << (((n) % 8U) * 4U)) +#define PIN_WPR_DISABLED(n) (0U << (n)) +#define PIN_WPR_ENABLED(n) (1U << (n)) +#define PIN_HDRV_DISABLED(n) (0U << (n)) +#define PIN_HDRV_ENABLED(n) (1U << (n)) + +/* + * Port A setup. + * + * PA0 - BUTTON (input floating). + * PA1 - ARD_A1 (input pullup). + * PA2 - ARD_D1 (input pullup). + * PA3 - ARD_D0 (input pullup). + * PA4 - ARD_A2 (input pullup). + * PA5 - ARD_D13 (input pullup). + * PA6 - ARD_D12 (input pullup). + * PA7 - ARD_D11 (input pullup). + * PA8 - ARD_D7 (input pullup). + * PA9 - ARD_D8 USART1_TX (multiplexing 7). + * PA10 - ARD_D2 USART1_RX (multiplexing 7). + * PA11 - PIN11 (input floating). + * PA12 - PIN12 (input floating). + * PA13 - SWDIO (multiplexing 0). + * PA14 - SWCLK (multiplexing 0). + * PA15 - ARD_D10 (input pullup). + */ +#define VAL_GPIOA_CFGR (PIN_MODE_INPUT(GPIOA_BUTTON) | \ + PIN_MODE_INPUT(GPIOA_ARD_A1) | \ + PIN_MODE_INPUT(GPIOA_ARD_D1) | \ + PIN_MODE_INPUT(GPIOA_ARD_D0) | \ + PIN_MODE_INPUT(GPIOA_ARD_A2) | \ + PIN_MODE_INPUT(GPIOA_ARD_D13) | \ + PIN_MODE_INPUT(GPIOA_ARD_D12) | \ + PIN_MODE_INPUT(GPIOA_ARD_D11) | \ + PIN_MODE_INPUT(GPIOA_ARD_D7) | \ + PIN_MODE_MUX(GPIOA_ARD_D8) | \ + PIN_MODE_MUX(GPIOA_ARD_D2) | \ + PIN_MODE_INPUT(GPIOA_PIN11) | \ + PIN_MODE_INPUT(GPIOA_PIN12) | \ + PIN_MODE_MUX(GPIOA_SWDIO) | \ + PIN_MODE_MUX(GPIOA_SWCLK) | \ + PIN_MODE_INPUT(GPIOA_ARD_D10)) +#define VAL_GPIOA_OMODE (PIN_OMODE_PUSHPULL(GPIOA_BUTTON) | \ + PIN_OMODE_PUSHPULL(GPIOA_ARD_A1) | \ + PIN_OMODE_PUSHPULL(GPIOA_ARD_D1) | \ + PIN_OMODE_PUSHPULL(GPIOA_ARD_D0) | \ + PIN_OMODE_PUSHPULL(GPIOA_ARD_A2) | \ + PIN_OMODE_PUSHPULL(GPIOA_ARD_D13) | \ + PIN_OMODE_PUSHPULL(GPIOA_ARD_D12) | \ + PIN_OMODE_PUSHPULL(GPIOA_ARD_D11) | \ + PIN_OMODE_PUSHPULL(GPIOA_ARD_D7) | \ + PIN_OMODE_PUSHPULL(GPIOA_ARD_D8) | \ + PIN_OMODE_PUSHPULL(GPIOA_ARD_D2) | \ + PIN_OMODE_PUSHPULL(GPIOA_PIN11) | \ + PIN_OMODE_PUSHPULL(GPIOA_PIN12) | \ + PIN_OMODE_PUSHPULL(GPIOA_SWDIO) | \ + PIN_OMODE_PUSHPULL(GPIOA_SWCLK) | \ + PIN_OMODE_PUSHPULL(GPIOA_ARD_D10)) +#define VAL_GPIOA_ODRVR (PIN_ODRVR_STRONGER(GPIOA_BUTTON) | \ + PIN_ODRVR_STRONGER(GPIOA_ARD_A1) | \ + PIN_ODRVR_STRONGER(GPIOA_ARD_D1) | \ + PIN_ODRVR_STRONGER(GPIOA_ARD_D0) | \ + PIN_ODRVR_STRONGER(GPIOA_ARD_A2) | \ + PIN_ODRVR_STRONGER(GPIOA_ARD_D13) | \ + PIN_ODRVR_STRONGER(GPIOA_ARD_D12) | \ + PIN_ODRVR_STRONGER(GPIOA_ARD_D11) | \ + PIN_ODRVR_STRONGER(GPIOA_ARD_D7) | \ + PIN_ODRVR_STRONGER(GPIOA_ARD_D8) | \ + PIN_ODRVR_STRONGER(GPIOA_ARD_D2) | \ + PIN_ODRVR_STRONGER(GPIOA_PIN11) | \ + PIN_ODRVR_STRONGER(GPIOA_PIN12) | \ + PIN_ODRVR_STRONGER(GPIOA_SWDIO) | \ + PIN_ODRVR_STRONGER(GPIOA_SWCLK) | \ + PIN_ODRVR_STRONGER(GPIOA_ARD_D10)) +#define VAL_GPIOA_PULL (PIN_PULL_FLOATING(GPIOA_BUTTON) | \ + PIN_PULL_PULLUP(GPIOA_ARD_A1) | \ + PIN_PULL_PULLUP(GPIOA_ARD_D1) | \ + PIN_PULL_PULLUP(GPIOA_ARD_D0) | \ + PIN_PULL_PULLUP(GPIOA_ARD_A2) | \ + PIN_PULL_PULLUP(GPIOA_ARD_D13) | \ + PIN_PULL_PULLUP(GPIOA_ARD_D12) | \ + PIN_PULL_PULLUP(GPIOA_ARD_D11) | \ + PIN_PULL_PULLUP(GPIOA_ARD_D7) | \ + PIN_PULL_FLOATING(GPIOA_ARD_D8) | \ + PIN_PULL_FLOATING(GPIOA_ARD_D2) | \ + PIN_PULL_FLOATING(GPIOA_PIN11) | \ + PIN_PULL_FLOATING(GPIOA_PIN12) | \ + PIN_PULL_PULLUP(GPIOA_SWDIO) | \ + PIN_PULL_PULLDOWN(GPIOA_SWCLK) | \ + PIN_PULL_PULLUP(GPIOA_ARD_D10)) +#define VAL_GPIOA_ODT (PIN_ODT_HIGH(GPIOA_BUTTON) | \ + PIN_ODT_HIGH(GPIOA_ARD_A1) | \ + PIN_ODT_HIGH(GPIOA_ARD_D1) | \ + PIN_ODT_HIGH(GPIOA_ARD_D0) | \ + PIN_ODT_HIGH(GPIOA_ARD_A2) | \ + PIN_ODT_HIGH(GPIOA_ARD_D13) | \ + PIN_ODT_HIGH(GPIOA_ARD_D12) | \ + PIN_ODT_HIGH(GPIOA_ARD_D11) | \ + PIN_ODT_HIGH(GPIOA_ARD_D7) | \ + PIN_ODT_HIGH(GPIOA_ARD_D8) | \ + PIN_ODT_HIGH(GPIOA_ARD_D2) | \ + PIN_ODT_HIGH(GPIOA_PIN11) | \ + PIN_ODT_HIGH(GPIOA_PIN12) | \ + PIN_ODT_HIGH(GPIOA_SWDIO) | \ + PIN_ODT_HIGH(GPIOA_SWCLK) | \ + PIN_ODT_HIGH(GPIOA_ARD_D10)) +#define VAL_GPIOA_MUXL (PIN_IOMUX_MUX(GPIOA_BUTTON, 0U) | \ + PIN_IOMUX_MUX(GPIOA_ARD_A1, 0U) | \ + PIN_IOMUX_MUX(GPIOA_ARD_D1, 0U) | \ + PIN_IOMUX_MUX(GPIOA_ARD_D0, 0U) | \ + PIN_IOMUX_MUX(GPIOA_ARD_A2, 0U) | \ + PIN_IOMUX_MUX(GPIOA_ARD_D13, 0U) | \ + PIN_IOMUX_MUX(GPIOA_ARD_D12, 0U) | \ + PIN_IOMUX_MUX(GPIOA_ARD_D11, 0U)) +#define VAL_GPIOA_MUXH (PIN_IOMUX_MUX(GPIOA_ARD_D7, 0U) | \ + PIN_IOMUX_MUX(GPIOA_ARD_D8, 7U) | \ + PIN_IOMUX_MUX(GPIOA_ARD_D2, 7U) | \ + PIN_IOMUX_MUX(GPIOA_PIN11, 0U) | \ + PIN_IOMUX_MUX(GPIOA_PIN12, 0U) | \ + PIN_IOMUX_MUX(GPIOA_SWDIO, 0U) | \ + PIN_IOMUX_MUX(GPIOA_SWCLK, 0U) | \ + PIN_IOMUX_MUX(GPIOA_ARD_D10, 0U)) +#define VAL_GPIOA_HDRV (PIN_HDRV_DISABLED(GPIOA_BUTTON) | \ + PIN_HDRV_DISABLED(GPIOA_ARD_A1) | \ + PIN_HDRV_DISABLED(GPIOA_ARD_D1) | \ + PIN_HDRV_DISABLED(GPIOA_ARD_D0) | \ + PIN_HDRV_DISABLED(GPIOA_ARD_A2) | \ + PIN_HDRV_DISABLED(GPIOA_ARD_D13) | \ + PIN_HDRV_DISABLED(GPIOA_ARD_D12) | \ + PIN_HDRV_DISABLED(GPIOA_ARD_D11) | \ + PIN_HDRV_DISABLED(GPIOA_ARD_D7) | \ + PIN_HDRV_DISABLED(GPIOA_ARD_D8) | \ + PIN_HDRV_DISABLED(GPIOA_ARD_D2) | \ + PIN_HDRV_DISABLED(GPIOA_PIN11) | \ + PIN_HDRV_DISABLED(GPIOA_PIN12) | \ + PIN_HDRV_DISABLED(GPIOA_SWDIO) | \ + PIN_HDRV_DISABLED(GPIOA_SWCLK) | \ + PIN_HDRV_DISABLED(GPIOA_ARD_D10)) + +/* + * Port B setup. + * + * PB0 - ARD_A3 (input pullup). + * PB1 - PIN1 (input pullup). + * PB2 - PIN2 (input pullup). + * PB3 - SWO (multiplexing 0). + * PB4 - ARD_D5 (input pullup). + * PB5 - ARD_D4 (input pullup). + * PB6 - PIN6 (input pullup). + * PB7 - PIN7 (input pullup). + * PB8 - ARD_SCL (input pullup). + * PB9 - ARD_SDA (input pullup). + * PB10 - ARD_D6 (input pullup). + * PB11 - PIN11 (input pullup). + * PB12 - ARD_NSS (input pullup). + * PB13 - ARD_SCK (input pullup). + * PB14 - PIN14 (input pullup). + * PB15 - PIN15 (input pullup). + */ +#define VAL_GPIOB_CFGR (PIN_MODE_INPUT(GPIOB_ARD_A3) | \ + PIN_MODE_INPUT(GPIOB_PIN1) | \ + PIN_MODE_INPUT(GPIOB_PIN2) | \ + PIN_MODE_MUX(GPIOB_SWO) | \ + PIN_MODE_INPUT(GPIOB_ARD_D5) | \ + PIN_MODE_INPUT(GPIOB_ARD_D4) | \ + PIN_MODE_INPUT(GPIOB_PIN6) | \ + PIN_MODE_INPUT(GPIOB_PIN7) | \ + PIN_MODE_INPUT(GPIOB_ARD_SCL) | \ + PIN_MODE_INPUT(GPIOB_ARD_SDA) | \ + PIN_MODE_INPUT(GPIOB_ARD_D6) | \ + PIN_MODE_INPUT(GPIOB_PIN11) | \ + PIN_MODE_INPUT(GPIOB_ARD_NSS) | \ + PIN_MODE_INPUT(GPIOB_ARD_SCK) | \ + PIN_MODE_INPUT(GPIOB_PIN14) | \ + PIN_MODE_INPUT(GPIOB_PIN15)) +#define VAL_GPIOB_OMODE (PIN_OMODE_PUSHPULL(GPIOB_ARD_A3) | \ + PIN_OMODE_PUSHPULL(GPIOB_PIN1) | \ + PIN_OMODE_PUSHPULL(GPIOB_PIN2) | \ + PIN_OMODE_PUSHPULL(GPIOB_SWO) | \ + PIN_OMODE_PUSHPULL(GPIOB_ARD_D5) | \ + PIN_OMODE_PUSHPULL(GPIOB_ARD_D4) | \ + PIN_OMODE_PUSHPULL(GPIOB_PIN6) | \ + PIN_OMODE_PUSHPULL(GPIOB_PIN7) | \ + PIN_OMODE_PUSHPULL(GPIOB_ARD_SCL) | \ + PIN_OMODE_PUSHPULL(GPIOB_ARD_SDA) | \ + PIN_OMODE_PUSHPULL(GPIOB_ARD_D6) | \ + PIN_OMODE_PUSHPULL(GPIOB_PIN11) | \ + PIN_OMODE_PUSHPULL(GPIOB_ARD_NSS) | \ + PIN_OMODE_PUSHPULL(GPIOB_ARD_SCK) | \ + PIN_OMODE_PUSHPULL(GPIOB_PIN14) | \ + PIN_OMODE_PUSHPULL(GPIOB_PIN15)) +#define VAL_GPIOB_ODRVR (PIN_ODRVR_STRONGER(GPIOB_ARD_A3) | \ + PIN_ODRVR_STRONGER(GPIOB_PIN1) | \ + PIN_ODRVR_STRONGER(GPIOB_PIN2) | \ + PIN_ODRVR_STRONGER(GPIOB_SWO) | \ + PIN_ODRVR_STRONGER(GPIOB_ARD_D5) | \ + PIN_ODRVR_STRONGER(GPIOB_ARD_D4) | \ + PIN_ODRVR_STRONGER(GPIOB_PIN6) | \ + PIN_ODRVR_STRONGER(GPIOB_PIN7) | \ + PIN_ODRVR_STRONGER(GPIOB_ARD_SCL) | \ + PIN_ODRVR_STRONGER(GPIOB_ARD_SDA) | \ + PIN_ODRVR_STRONGER(GPIOB_ARD_D6) | \ + PIN_ODRVR_STRONGER(GPIOB_PIN11) | \ + PIN_ODRVR_STRONGER(GPIOB_ARD_NSS) | \ + PIN_ODRVR_STRONGER(GPIOB_ARD_SCK) | \ + PIN_ODRVR_STRONGER(GPIOB_PIN14) | \ + PIN_ODRVR_STRONGER(GPIOB_PIN15)) +#define VAL_GPIOB_PULL (PIN_PULL_PULLUP(GPIOB_ARD_A3) | \ + PIN_PULL_PULLUP(GPIOB_PIN1) | \ + PIN_PULL_PULLUP(GPIOB_PIN2) | \ + PIN_PULL_FLOATING(GPIOB_SWO) | \ + PIN_PULL_PULLUP(GPIOB_ARD_D5) | \ + PIN_PULL_PULLUP(GPIOB_ARD_D4) | \ + PIN_PULL_PULLUP(GPIOB_PIN6) | \ + PIN_PULL_PULLUP(GPIOB_PIN7) | \ + PIN_PULL_PULLUP(GPIOB_ARD_SCL) | \ + PIN_PULL_PULLUP(GPIOB_ARD_SDA) | \ + PIN_PULL_PULLUP(GPIOB_ARD_D6) | \ + PIN_PULL_PULLUP(GPIOB_PIN11) | \ + PIN_PULL_PULLUP(GPIOB_ARD_NSS) | \ + PIN_PULL_PULLUP(GPIOB_ARD_SCK) | \ + PIN_PULL_PULLUP(GPIOB_PIN14) | \ + PIN_PULL_PULLUP(GPIOB_PIN15)) +#define VAL_GPIOB_ODT (PIN_ODT_HIGH(GPIOB_ARD_A3) | \ + PIN_ODT_HIGH(GPIOB_PIN1) | \ + PIN_ODT_HIGH(GPIOB_PIN2) | \ + PIN_ODT_HIGH(GPIOB_SWO) | \ + PIN_ODT_HIGH(GPIOB_ARD_D5) | \ + PIN_ODT_HIGH(GPIOB_ARD_D4) | \ + PIN_ODT_HIGH(GPIOB_PIN6) | \ + PIN_ODT_HIGH(GPIOB_PIN7) | \ + PIN_ODT_HIGH(GPIOB_ARD_SCL) | \ + PIN_ODT_HIGH(GPIOB_ARD_SDA) | \ + PIN_ODT_HIGH(GPIOB_ARD_D6) | \ + PIN_ODT_HIGH(GPIOB_PIN11) | \ + PIN_ODT_HIGH(GPIOB_ARD_NSS) | \ + PIN_ODT_HIGH(GPIOB_ARD_SCK) | \ + PIN_ODT_HIGH(GPIOB_PIN14) | \ + PIN_ODT_HIGH(GPIOB_PIN15)) +#define VAL_GPIOB_MUXL (PIN_IOMUX_MUX(GPIOB_ARD_A3, 0U) | \ + PIN_IOMUX_MUX(GPIOB_PIN1, 0U) | \ + PIN_IOMUX_MUX(GPIOB_PIN2, 0U) | \ + PIN_IOMUX_MUX(GPIOB_SWO, 0U) | \ + PIN_IOMUX_MUX(GPIOB_ARD_D5, 0U) | \ + PIN_IOMUX_MUX(GPIOB_ARD_D4, 0U) | \ + PIN_IOMUX_MUX(GPIOB_PIN6, 0U) | \ + PIN_IOMUX_MUX(GPIOB_PIN7, 0U)) +#define VAL_GPIOB_MUXH (PIN_IOMUX_MUX(GPIOB_ARD_SCL, 0U) | \ + PIN_IOMUX_MUX(GPIOB_ARD_SDA, 0U) | \ + PIN_IOMUX_MUX(GPIOB_ARD_D6, 0U) | \ + PIN_IOMUX_MUX(GPIOB_PIN11, 0U) | \ + PIN_IOMUX_MUX(GPIOB_ARD_NSS, 0U) | \ + PIN_IOMUX_MUX(GPIOB_ARD_SCK, 0U) | \ + PIN_IOMUX_MUX(GPIOB_PIN14, 0U) | \ + PIN_IOMUX_MUX(GPIOB_PIN15, 0U)) +#define VAL_GPIOB_HDRV (PIN_HDRV_DISABLED(GPIOB_ARD_A3) | \ + PIN_HDRV_DISABLED(GPIOB_PIN1) | \ + PIN_HDRV_DISABLED(GPIOB_PIN2) | \ + PIN_HDRV_DISABLED(GPIOB_SWO) | \ + PIN_HDRV_DISABLED(GPIOB_ARD_D5) | \ + PIN_HDRV_DISABLED(GPIOB_ARD_D4) | \ + PIN_HDRV_DISABLED(GPIOB_PIN6) | \ + PIN_HDRV_DISABLED(GPIOB_PIN7) | \ + PIN_HDRV_DISABLED(GPIOB_ARD_SCL) | \ + PIN_HDRV_DISABLED(GPIOB_ARD_SDA) | \ + PIN_HDRV_DISABLED(GPIOB_ARD_D6) | \ + PIN_HDRV_DISABLED(GPIOB_PIN11) | \ + PIN_HDRV_DISABLED(GPIOB_ARD_NSS) | \ + PIN_HDRV_DISABLED(GPIOB_ARD_SCK) | \ + PIN_HDRV_DISABLED(GPIOB_PIN14) | \ + PIN_HDRV_DISABLED(GPIOB_PIN15)) + +/* + * Port C setup. + * + * PC0 - ARD_A5 (input pullup). + * PC1 - ARD_A4 (input pullup). + * PC2 - ARD_MISO (input pullup). + * PC3 - ARD_MOSI (input pullup). + * PC4 - ARD_PC4 (input pullup). + * PC5 - PIN5 (input pullup). + * PC6 - PIN6 (input pullup). + * PC7 - ARD_D9 (input pullup). + * PC8 - PIN8 (input pullup). + * PC9 - PIN9 (input pullup). + * PC10 - PIN10 (input pullup). + * PC11 - PIN11 (input pullup). + * PC12 - PIN12 (input pullup). + * PC13 - BUTTON (input floating). + * PC14 - LEXT_IN (input floating). + * PC15 - LEXT_OUT (input floating). + */ +#define VAL_GPIOC_CFGR (PIN_MODE_INPUT(GPIOC_ARD_A5) | \ + PIN_MODE_INPUT(GPIOC_ARD_A4) | \ + PIN_MODE_INPUT(GPIOC_ARD_MISO) | \ + PIN_MODE_INPUT(GPIOC_ARD_MOSI) | \ + PIN_MODE_INPUT(GPIOC_ARD_PC4) | \ + PIN_MODE_INPUT(GPIOC_PIN5) | \ + PIN_MODE_INPUT(GPIOC_PIN6) | \ + PIN_MODE_INPUT(GPIOC_ARD_D9) | \ + PIN_MODE_INPUT(GPIOC_PIN8) | \ + PIN_MODE_INPUT(GPIOC_PIN9) | \ + PIN_MODE_INPUT(GPIOC_PIN10) | \ + PIN_MODE_INPUT(GPIOC_PIN11) | \ + PIN_MODE_INPUT(GPIOC_PIN12) | \ + PIN_MODE_INPUT(GPIOC_BUTTON) | \ + PIN_MODE_INPUT(GPIOC_LEXT_IN) | \ + PIN_MODE_INPUT(GPIOC_LEXT_OUT)) +#define VAL_GPIOC_OMODE (PIN_OMODE_PUSHPULL(GPIOC_ARD_A5) | \ + PIN_OMODE_PUSHPULL(GPIOC_ARD_A4) | \ + PIN_OMODE_PUSHPULL(GPIOC_ARD_MISO) | \ + PIN_OMODE_PUSHPULL(GPIOC_ARD_MOSI) | \ + PIN_OMODE_PUSHPULL(GPIOC_ARD_PC4) | \ + PIN_OMODE_PUSHPULL(GPIOC_PIN5) | \ + PIN_OMODE_PUSHPULL(GPIOC_PIN6) | \ + PIN_OMODE_PUSHPULL(GPIOC_ARD_D9) | \ + PIN_OMODE_PUSHPULL(GPIOC_PIN8) | \ + PIN_OMODE_PUSHPULL(GPIOC_PIN9) | \ + PIN_OMODE_PUSHPULL(GPIOC_PIN10) | \ + PIN_OMODE_PUSHPULL(GPIOC_PIN11) | \ + PIN_OMODE_PUSHPULL(GPIOC_PIN12) | \ + PIN_OMODE_PUSHPULL(GPIOC_BUTTON) | \ + PIN_OMODE_PUSHPULL(GPIOC_LEXT_IN) | \ + PIN_OMODE_PUSHPULL(GPIOC_LEXT_OUT)) +#define VAL_GPIOC_ODRVR (PIN_ODRVR_STRONGER(GPIOC_ARD_A5) | \ + PIN_ODRVR_STRONGER(GPIOC_ARD_A4) | \ + PIN_ODRVR_STRONGER(GPIOC_ARD_MISO) | \ + PIN_ODRVR_STRONGER(GPIOC_ARD_MOSI) | \ + PIN_ODRVR_STRONGER(GPIOC_ARD_PC4) | \ + PIN_ODRVR_STRONGER(GPIOC_PIN5) | \ + PIN_ODRVR_STRONGER(GPIOC_PIN6) | \ + PIN_ODRVR_STRONGER(GPIOC_ARD_D9) | \ + PIN_ODRVR_STRONGER(GPIOC_PIN8) | \ + PIN_ODRVR_STRONGER(GPIOC_PIN9) | \ + PIN_ODRVR_STRONGER(GPIOC_PIN10) | \ + PIN_ODRVR_STRONGER(GPIOC_PIN11) | \ + PIN_ODRVR_STRONGER(GPIOC_PIN12) | \ + PIN_ODRVR_STRONGER(GPIOC_BUTTON) | \ + PIN_ODRVR_STRONGER(GPIOC_LEXT_IN) | \ + PIN_ODRVR_STRONGER(GPIOC_LEXT_OUT)) +#define VAL_GPIOC_PULL (PIN_PULL_PULLUP(GPIOC_ARD_A5) | \ + PIN_PULL_PULLUP(GPIOC_ARD_A4) | \ + PIN_PULL_PULLUP(GPIOC_ARD_MISO) | \ + PIN_PULL_PULLUP(GPIOC_ARD_MOSI) | \ + PIN_PULL_PULLUP(GPIOC_ARD_PC4) | \ + PIN_PULL_PULLUP(GPIOC_PIN5) | \ + PIN_PULL_PULLUP(GPIOC_PIN6) | \ + PIN_PULL_PULLUP(GPIOC_ARD_D9) | \ + PIN_PULL_PULLUP(GPIOC_PIN8) | \ + PIN_PULL_PULLUP(GPIOC_PIN9) | \ + PIN_PULL_PULLUP(GPIOC_PIN10) | \ + PIN_PULL_PULLUP(GPIOC_PIN11) | \ + PIN_PULL_PULLUP(GPIOC_PIN12) | \ + PIN_PULL_FLOATING(GPIOC_BUTTON) | \ + PIN_PULL_FLOATING(GPIOC_LEXT_IN) | \ + PIN_PULL_FLOATING(GPIOC_LEXT_OUT)) +#define VAL_GPIOC_ODT (PIN_ODT_HIGH(GPIOC_ARD_A5) | \ + PIN_ODT_HIGH(GPIOC_ARD_A4) | \ + PIN_ODT_HIGH(GPIOC_ARD_MISO) | \ + PIN_ODT_HIGH(GPIOC_ARD_MOSI) | \ + PIN_ODT_HIGH(GPIOC_ARD_PC4) | \ + PIN_ODT_HIGH(GPIOC_PIN5) | \ + PIN_ODT_HIGH(GPIOC_PIN6) | \ + PIN_ODT_HIGH(GPIOC_ARD_D9) | \ + PIN_ODT_HIGH(GPIOC_PIN8) | \ + PIN_ODT_HIGH(GPIOC_PIN9) | \ + PIN_ODT_HIGH(GPIOC_PIN10) | \ + PIN_ODT_HIGH(GPIOC_PIN11) | \ + PIN_ODT_HIGH(GPIOC_PIN12) | \ + PIN_ODT_HIGH(GPIOC_BUTTON) | \ + PIN_ODT_HIGH(GPIOC_LEXT_IN) | \ + PIN_ODT_HIGH(GPIOC_LEXT_OUT)) +#define VAL_GPIOC_MUXL (PIN_IOMUX_MUX(GPIOC_ARD_A5, 0U) | \ + PIN_IOMUX_MUX(GPIOC_ARD_A4, 0U) | \ + PIN_IOMUX_MUX(GPIOC_ARD_MISO, 0U) | \ + PIN_IOMUX_MUX(GPIOC_ARD_MOSI, 0U) | \ + PIN_IOMUX_MUX(GPIOC_ARD_PC4, 0U) | \ + PIN_IOMUX_MUX(GPIOC_PIN5, 0U) | \ + PIN_IOMUX_MUX(GPIOC_PIN6, 0U) | \ + PIN_IOMUX_MUX(GPIOC_ARD_D9, 0U)) +#define VAL_GPIOC_MUXH (PIN_IOMUX_MUX(GPIOC_PIN8, 0U) | \ + PIN_IOMUX_MUX(GPIOC_PIN9, 0U) | \ + PIN_IOMUX_MUX(GPIOC_PIN10, 0U) | \ + PIN_IOMUX_MUX(GPIOC_PIN11, 0U) | \ + PIN_IOMUX_MUX(GPIOC_PIN12, 0U) | \ + PIN_IOMUX_MUX(GPIOC_BUTTON, 0U) | \ + PIN_IOMUX_MUX(GPIOC_LEXT_IN, 0U) | \ + PIN_IOMUX_MUX(GPIOC_LEXT_OUT, 0U)) +#define VAL_GPIOC_HDRV (PIN_HDRV_DISABLED(GPIOC_ARD_A5) | \ + PIN_HDRV_DISABLED(GPIOC_ARD_A4) | \ + PIN_HDRV_DISABLED(GPIOC_ARD_MISO) | \ + PIN_HDRV_DISABLED(GPIOC_ARD_MOSI) | \ + PIN_HDRV_DISABLED(GPIOC_ARD_PC4) | \ + PIN_HDRV_DISABLED(GPIOC_PIN5) | \ + PIN_HDRV_DISABLED(GPIOC_PIN6) | \ + PIN_HDRV_DISABLED(GPIOC_ARD_D9) | \ + PIN_HDRV_DISABLED(GPIOC_PIN8) | \ + PIN_HDRV_DISABLED(GPIOC_PIN9) | \ + PIN_HDRV_DISABLED(GPIOC_PIN10) | \ + PIN_HDRV_DISABLED(GPIOC_PIN11) | \ + PIN_HDRV_DISABLED(GPIOC_PIN12) | \ + PIN_HDRV_DISABLED(GPIOC_BUTTON) | \ + PIN_HDRV_DISABLED(GPIOC_LEXT_IN) | \ + PIN_HDRV_DISABLED(GPIOC_LEXT_OUT)) + +/* + * Port D setup. + * + * PD2 - PIN2 (input pullup). + */ +#define VAL_GPIOD_CFGR (PIN_MODE_INPUT(GPIOD_PIN2)) +#define VAL_GPIOD_OMODE (PIN_OMODE_PUSHPULL(GPIOD_PIN2)) +#define VAL_GPIOD_ODRVR (PIN_ODRVR_STRONGER(GPIOD_PIN2)) +#define VAL_GPIOD_PULL (PIN_PULL_PULLUP(GPIOD_PIN2)) +#define VAL_GPIOD_ODT (PIN_ODT_HIGH(GPIOD_PIN2)) +#define VAL_GPIOD_MUXL (PIN_IOMUX_MUX(GPIOD_PIN2, 0U)) +#define VAL_GPIOD_MUXH 0U +#define VAL_GPIOD_HDRV (PIN_HDRV_DISABLED(GPIOD_PIN2)) + +/* + * Port F setup. + * + * PF0 - HEXT_IN (input floating). + * PF1 - HEXT_OUT (input floating). + * PF4 - LED_RED (output pushpull). + * PF5 - LED_YELLOW (output pushpull). + * PF6 - LED_GREEN (output pushpull). + * PF7 - PIN7 (input pullup). + * PF11 - PIN11 (input pullup). + */ +#define VAL_GPIOF_CFGR (PIN_MODE_INPUT(GPIOF_HEXT_IN) | \ + PIN_MODE_INPUT(GPIOF_HEXT_OUT) | \ + PIN_MODE_OUTPUT(GPIOF_LED_RED) | \ + PIN_MODE_OUTPUT(GPIOF_LED_YELLOW) | \ + PIN_MODE_OUTPUT(GPIOF_LED_GREEN) | \ + PIN_MODE_INPUT(GPIOF_PIN7) | \ + PIN_MODE_INPUT(GPIOF_PIN11)) +#define VAL_GPIOF_OMODE (PIN_OMODE_PUSHPULL(GPIOF_HEXT_IN) | \ + PIN_OMODE_PUSHPULL(GPIOF_HEXT_OUT) | \ + PIN_OMODE_PUSHPULL(GPIOF_LED_RED) | \ + PIN_OMODE_PUSHPULL(GPIOF_LED_YELLOW) | \ + PIN_OMODE_PUSHPULL(GPIOF_LED_GREEN) | \ + PIN_OMODE_PUSHPULL(GPIOF_PIN7) | \ + PIN_OMODE_PUSHPULL(GPIOF_PIN11)) +#define VAL_GPIOF_ODRVR (PIN_ODRVR_STRONGER(GPIOF_HEXT_IN) | \ + PIN_ODRVR_STRONGER(GPIOF_HEXT_OUT) | \ + PIN_ODRVR_STRONGER(GPIOF_LED_RED) | \ + PIN_ODRVR_STRONGER(GPIOF_LED_YELLOW) | \ + PIN_ODRVR_STRONGER(GPIOF_LED_GREEN) | \ + PIN_ODRVR_STRONGER(GPIOF_PIN7) | \ + PIN_ODRVR_STRONGER(GPIOF_PIN11)) +#define VAL_GPIOF_PULL (PIN_PULL_FLOATING(GPIOF_HEXT_IN) | \ + PIN_PULL_FLOATING(GPIOF_HEXT_OUT) | \ + PIN_PULL_FLOATING(GPIOF_LED_RED) | \ + PIN_PULL_FLOATING(GPIOF_LED_YELLOW) | \ + PIN_PULL_FLOATING(GPIOF_LED_GREEN) | \ + PIN_PULL_PULLUP(GPIOF_PIN7) | \ + PIN_PULL_PULLUP(GPIOF_PIN11)) +#define VAL_GPIOF_ODT (PIN_ODT_HIGH(GPIOF_HEXT_IN) | \ + PIN_ODT_HIGH(GPIOF_HEXT_OUT) | \ + PIN_ODT_HIGH(GPIOF_LED_RED) | \ + PIN_ODT_HIGH(GPIOF_LED_YELLOW) | \ + PIN_ODT_HIGH(GPIOF_LED_GREEN) | \ + PIN_ODT_HIGH(GPIOF_PIN7) | \ + PIN_ODT_HIGH(GPIOF_PIN11)) +#define VAL_GPIOF_MUXL (PIN_IOMUX_MUX(GPIOF_HEXT_IN, 0U) | \ + PIN_IOMUX_MUX(GPIOF_HEXT_OUT, 0U) | \ + PIN_IOMUX_MUX(GPIOF_LED_RED, 0U) | \ + PIN_IOMUX_MUX(GPIOF_LED_YELLOW, 0U) | \ + PIN_IOMUX_MUX(GPIOF_LED_GREEN, 0U) | \ + PIN_IOMUX_MUX(GPIOF_PIN7, 0U)) +#define VAL_GPIOF_MUXH (PIN_IOMUX_MUX(GPIOF_PIN11, 0U)) +#define VAL_GPIOF_HDRV (PIN_HDRV_DISABLED(GPIOF_HEXT_IN) | \ + PIN_HDRV_DISABLED(GPIOF_HEXT_OUT) | \ + PIN_HDRV_DISABLED(GPIOF_LED_RED) | \ + PIN_HDRV_DISABLED(GPIOF_LED_YELLOW) | \ + PIN_HDRV_DISABLED(GPIOF_LED_GREEN) | \ + PIN_HDRV_DISABLED(GPIOF_PIN7) | \ + PIN_HDRV_DISABLED(GPIOF_PIN11)) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/os/hal/boards/AT_START_F402/board.mk b/os/hal/boards/AT_START_F402/board.mk new file mode 100644 index 0000000000..be4fdf90e6 --- /dev/null +++ b/os/hal/boards/AT_START_F402/board.mk @@ -0,0 +1,9 @@ +# List of all the board related files. +BOARDSRC = $(CHIBIOS_CONTRIB)/os/hal/boards/AT_START_F402/board.c + +# Required include directories +BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/AT_START_F402 + +# Shared variables +ALLCSRC += $(BOARDSRC) +ALLINC += $(BOARDINC) diff --git a/os/hal/boards/AT_START_F405/board.c b/os/hal/boards/AT_START_F405/board.c index 346e5194fb..d413e74f47 100644 --- a/os/hal/boards/AT_START_F405/board.c +++ b/os/hal/boards/AT_START_F405/board.c @@ -1,8 +1,8 @@ /* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian - ChibiOS - Copyright (C) 2003..2024 Maxjta + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + ChibiOS - Copyright (C) 2024..2025 Maxjta Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -18,6 +18,7 @@ */ #include "hal.h" +#include "at32_gpio.h" /*===========================================================================*/ /* Driver local definitions. */ @@ -30,6 +31,7 @@ /*===========================================================================*/ /* Driver local variables and types. */ /*===========================================================================*/ + /** * @brief Type of AT32 GPIO port setup. */ @@ -44,7 +46,6 @@ typedef struct { uint32_t hdrv; } gpio_setup_t; - /** * @brief Type of AT32 GPIO initialization data. */ @@ -71,73 +72,66 @@ typedef struct { */ static const gpio_config_t gpio_default_config = { #if AT32_HAS_GPIOA - {VAL_GPIOA_MODE, VAL_GPIOA_OUTPUT, VAL_GPIOA_ODRVR, VAL_GPIOA_PULL, - VAL_GPIOA_ODT, VAL_GPIOA_MUXL, VAL_GPIOA_MUXH, VAL_GPIOA_HDRV}, + {VAL_GPIOA_CFGR, VAL_GPIOA_OMODE, VAL_GPIOA_ODRVR, VAL_GPIOA_PULL, + VAL_GPIOA_ODT, VAL_GPIOA_MUXL, VAL_GPIOA_MUXH, VAL_GPIOA_HDRV}, #endif #if AT32_HAS_GPIOB - {VAL_GPIOB_MODE, VAL_GPIOB_OUTPUT, VAL_GPIOB_ODRVR, VAL_GPIOB_PULL, - VAL_GPIOB_ODT, VAL_GPIOB_MUXL, VAL_GPIOB_MUXH, VAL_GPIOB_HDRV}, + {VAL_GPIOB_CFGR, VAL_GPIOB_OMODE, VAL_GPIOB_ODRVR, VAL_GPIOB_PULL, + VAL_GPIOB_ODT, VAL_GPIOB_MUXL, VAL_GPIOB_MUXH, VAL_GPIOB_HDRV}, #endif #if AT32_HAS_GPIOC - {VAL_GPIOC_MODE, VAL_GPIOC_OUTPUT, VAL_GPIOC_ODRVR, VAL_GPIOC_PULL, - VAL_GPIOC_ODT, VAL_GPIOC_MUXL, VAL_GPIOC_MUXH, VAL_GPIOC_HDRV}, + {VAL_GPIOC_CFGR, VAL_GPIOC_OMODE, VAL_GPIOC_ODRVR, VAL_GPIOC_PULL, + VAL_GPIOC_ODT, VAL_GPIOC_MUXL, VAL_GPIOC_MUXH, VAL_GPIOC_HDRV}, #endif #if AT32_HAS_GPIOD - {VAL_GPIOD_MODE, VAL_GPIOD_OUTPUT, VAL_GPIOD_ODRVR, VAL_GPIOD_PULL, - VAL_GPIOD_ODT, VAL_GPIOD_MUXL, VAL_GPIOD_MUXH, VAL_GPIOD_HDRV}, + {VAL_GPIOD_CFGR, VAL_GPIOD_OMODE, VAL_GPIOD_ODRVR, VAL_GPIOD_PULL, + VAL_GPIOD_ODT, VAL_GPIOD_MUXL, VAL_GPIOD_MUXH, VAL_GPIOD_HDRV}, #endif #if AT32_HAS_GPIOF - {VAL_GPIOF_MODE, VAL_GPIOF_OUTPUT, VAL_GPIOF_ODRVR, VAL_GPIOF_PULL, - VAL_GPIOF_ODT, VAL_GPIOF_MUXL, VAL_GPIOF_MUXH, VAL_GPIOF_HDRV}, + {VAL_GPIOF_CFGR, VAL_GPIOF_OMODE, VAL_GPIOF_ODRVR, VAL_GPIOF_PULL, + VAL_GPIOF_ODT, VAL_GPIOF_MUXL, VAL_GPIOF_MUXH, VAL_GPIOF_HDRV}, #endif }; -/** - * @brief PAL setup. - * @details Digital I/O ports static configuration as defined in @p board.h. - * This variable is used by the HAL when initializing the PAL driver. - */ - /*===========================================================================*/ /* Driver local functions. */ /*===========================================================================*/ -static void gpio_init_lld(at32_gpio_t *gpiop, const gpio_setup_t *config) { - gpiop->OMODE = config->omode; +static void gpio_init(at32_gpio_t *gpiop, const gpio_setup_t *config) { + gpiop->OMODE = config->omode; gpiop->ODRVR = config->odrvr; - gpiop->PULL = config->pull; - gpiop->ODT = config->odt; - gpiop->MUXL = config->muxl; - gpiop->MUXH = config->muxh; - gpiop->CFGR = config->cfgr; - gpiop->HDRV = config->hdrv; - + gpiop->PULL = config->pull; + gpiop->ODT = config->odt; + gpiop->MUXL = config->muxl; + gpiop->MUXH = config->muxh; + gpiop->HDRV = config->hdrv; + gpiop->CFGR = config->cfgr; } static void at32_gpio_init(void) { - /* Enabling GPIO-related clocks, the mask comes from the registry header file.*/ - crmEnableAHB1(AT32_GPIO_EN_MASK, false); crmResetAHB1(AT32_GPIO_EN_MASK); + crmEnableAHB1(AT32_GPIO_EN_MASK, true); /* Initializing all the defined GPIO ports.*/ #if AT32_HAS_GPIOA - gpio_init_lld(GPIOA, &gpio_default_config.PAData); + gpio_init(GPIOA, &gpio_default_config.PAData); #endif #if AT32_HAS_GPIOB - gpio_init_lld(GPIOB, &gpio_default_config.PBData); + gpio_init(GPIOB, &gpio_default_config.PBData); #endif #if AT32_HAS_GPIOC - gpio_init_lld(GPIOC, &gpio_default_config.PCData); + gpio_init(GPIOC, &gpio_default_config.PCData); #endif #if AT32_HAS_GPIOD - gpio_init_lld(GPIOD, &gpio_default_config.PDData); + gpio_init(GPIOD, &gpio_default_config.PDData); #endif #if AT32_HAS_GPIOF - gpio_init_lld(GPIOF, &gpio_default_config.PFData); + gpio_init(GPIOF, &gpio_default_config.PFData); #endif } + /*===========================================================================*/ /* Driver interrupt handlers. */ /*===========================================================================*/ @@ -148,35 +142,14 @@ static void at32_gpio_init(void) { /** * @brief Early initialization code. - * @details System clocks are initialized before everything else. + * @details GPIO ports and system clocks are initialized before everything + * else. */ void __early_init(void) { - at32_clock_init(); at32_gpio_init(); + at32_clock_init(); } -#if HAL_USE_SDC || defined(__DOXYGEN__) -/** - * @brief SDC card detection. - */ -bool sdc_lld_is_card_inserted(SDCDriver *sdcp) { - static bool last_status = false; - - if (blkIsTransferring(sdcp)) - return last_status; - return last_status = (bool)palReadPad(GPIOA, GPIOA_ARD_A2); -} - -/** - * @brief SDC card write protection detection. - */ -bool sdc_lld_is_write_protected(SDCDriver *sdcp) { - - (void)sdcp; - return false; -} -#endif /* HAL_USE_SDC */ - /** * @brief Board-specific initialization code. * @note You can add your board-specific code here. diff --git a/os/hal/boards/AT_START_F405/board.h b/os/hal/boards/AT_START_F405/board.h index c38edc6ff7..f950a475f9 100644 --- a/os/hal/boards/AT_START_F405/board.h +++ b/os/hal/boards/AT_START_F405/board.h @@ -1,8 +1,8 @@ /* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian - ChibiOS - Copyright (C) 2023..2024 Maxjta + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + ChibiOS - Copyright (C) 2024..2025 Maxjta Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -34,6 +34,11 @@ #define BOARD_AT_START_F405 #define BOARD_NAME "Artery AT-START-F405" +/* + * The board has an ULPI USB PHY. + */ +#define BOARD_OTG2_USES_ULPI + /* * Board oscillators-related settings. */ @@ -48,77 +53,106 @@ /* * MCU type, supported types are defined in ./os/hal/platforms/hal_lld.h. */ -#define AT32F405RCT7 +#define AT32F405RC /* * IO pins assignments. */ #define GPIOA_BUTTON 0U -#define GPIOA_PIN1 1U -#define GPIOA_PIN2 2U -#define GPIOA_PIN3 3U -#define GPIOA_PIN4 4U -#define GPIOA_PIN5 5U -#define GPIOA_PIN6 6U -#define GPIOA_PIN7 7U -#define GPIOA_PIN8 8U -#define GPIOA_PIN9 9U -#define GPIOA_PIN10 10U +#define GPIOA_ARD_A1 1U +#define GPIOA_ARD_D1 2U +#define GPIOA_ARD_D0 3U +#define GPIOA_ARD_A2 4U +#define GPIOA_ARD_D13 5U +#define GPIOA_ARD_D12 6U +#define GPIOA_ARD_D11 7U +#define GPIOA_ARD_D7 8U +#define GPIOA_ARD_D8 9U +#define GPIOA_ARD_D2 10U #define GPIOA_PIN11 11U #define GPIOA_PIN12 12U #define GPIOA_SWDIO 13U #define GPIOA_SWCLK 14U -#define GPIOA_PIN15 15U +#define GPIOA_ARD_D10 15U -#define GPIOB_PIN0 0U +#define GPIOB_ARD_A3 0U #define GPIOB_PIN1 1U #define GPIOB_PIN2 2U -#define GPIOB_PIN3 3U -#define GPIOB_PIN4 4U -#define GPIOB_PIN5 5U +#define GPIOB_SWO 3U +#define GPIOB_ARD_D5 4U +#define GPIOB_ARD_D4 5U #define GPIOB_PIN6 6U #define GPIOB_PIN7 7U -#define GPIOB_PIN8 8U -#define GPIOB_PIN9 9U -#define GPIOB_PIN10 10U -#define GPIOB_PIN11 11U -#define GPIOB_PIN12 12U -#define GPIOB_PIN13 13U -#define GPIOB_PIN14 14U -#define GPIOB_PIN15 15U - -#define GPIOC_PIN0 0U -#define GPIOC_PIN1 1U -#define GPIOC_PIN2 2U -#define GPIOC_PIN3 3U -#define GPIOC_PIN4 4U +#define GPIOB_ARD_SCL 8U +#define GPIOB_ARD_SDA 9U +#define GPIOB_ARD_D6 10U +#define GPIOB_ARD_NSS 12U +#define GPIOB_ARD_SCK 13U + +#define GPIOC_ARD_A5 0U +#define GPIOC_ARD_A4 1U +#define GPIOC_ARD_MISO 2U +#define GPIOC_ARD_MOSI 3U +#define GPIOC_ARD_PC4 4U #define GPIOC_PIN5 5U #define GPIOC_PIN6 6U -#define GPIOC_PIN7 7U +#define GPIOC_ARD_D9 7U #define GPIOC_PIN8 8U #define GPIOC_PIN9 9U #define GPIOC_PIN10 10U #define GPIOC_PIN11 11U #define GPIOC_PIN12 12U -#define GPIOC_PIN13 13U -#define GPIOC_PIN14 14U -#define GPIOC_PIN15 15U +#define GPIOC_BUTTON 13U +#define GPIOC_LEXT_IN 14U +#define GPIOC_LEXT_OUT 15U -#define GPIOD_PIN2 15U +#define GPIOD_PIN2 2U #define GPIOF_HEXT_IN 0U #define GPIOF_HEXT_OUT 1U -#define GPIOF_PIN4 4U -#define GPIOF_PIN5 5U -#define GPIOF_PIN6 6U +#define GPIOF_LED_RED 4U +#define GPIOF_LED_YELLOW 5U +#define GPIOF_LED_GREEN 6U #define GPIOF_PIN7 7U #define GPIOF_PIN11 11U - /* * IO lines assignments. */ #define LINE_BUTTON PAL_LINE(GPIOA, 0U) +#define LINE_ARD_A1 PAL_LINE(GPIOA, 1U) +#define LINE_ARD_D1 PAL_LINE(GPIOA, 2U) +#define LINE_ARD_D0 PAL_LINE(GPIOA, 3U) +#define LINE_ARD_A2 PAL_LINE(GPIOA, 4U) +#define LINE_ARD_D13 PAL_LINE(GPIOA, 5U) +#define LINE_ARD_D12 PAL_LINE(GPIOA, 6U) +#define LINE_ARD_D11 PAL_LINE(GPIOA, 7U) +#define LINE_ARD_D7 PAL_LINE(GPIOA, 8U) +#define LINE_ARD_D8 PAL_LINE(GPIOA, 9U) +#define LINE_ARD_D2 PAL_LINE(GPIOA, 10U) +#define LINE_SWDIO PAL_LINE(GPIOA, 13U) +#define LINE_SWCLK PAL_LINE(GPIOA, 14U) +#define LINE_ARD_D10 PAL_LINE(GPIOA, 15U) +#define LINE_ARD_A3 PAL_LINE(GPIOB, 0U) +#define LINE_SWO PAL_LINE(GPIOB, 3U) +#define LINE_ARD_D5 PAL_LINE(GPIOB, 4U) +#define LINE_ARD_D4 PAL_LINE(GPIOB, 5U) +#define LINE_ARD_SCL PAL_LINE(GPIOB, 8U) +#define LINE_ARD_SDA PAL_LINE(GPIOB, 9U) +#define LINE_ARD_D6 PAL_LINE(GPIOB, 10U) +#define LINE_ARD_NSS PAL_LINE(GPIOB, 12U) +#define LINE_ARD_SCK PAL_LINE(GPIOB, 13U) +#define LINE_ARD_A5 PAL_LINE(GPIOC, 0U) +#define LINE_ARD_A4 PAL_LINE(GPIOC, 1U) +#define LINE_ARD_MISO PAL_LINE(GPIOC, 2U) +#define LINE_ARD_MOSI PAL_LINE(GPIOC, 3U) +#define LINE_ARD_PC4 PAL_LINE(GPIOC, 4U) +#define LINE_ARD_D9 PAL_LINE(GPIOC, 7U) +#define LINE_BUTTON_ALT PAL_LINE(GPIOC, 13U) +#define LINE_LEXT_IN PAL_LINE(GPIOC, 14U) +#define LINE_LEXT_OUT PAL_LINE(GPIOC, 15U) +#define LINE_HEXT_IN PAL_LINE(GPIOF, 0U) +#define LINE_HEXT_OUT PAL_LINE(GPIOF, 1U) #define LINE_LED_RED PAL_LINE(GPIOF, 4U) #define LINE_LED_YELLOW PAL_LINE(GPIOF, 5U) #define LINE_LED_GREEN PAL_LINE(GPIOF, 6U) @@ -139,7 +173,6 @@ /* Driver macros. */ /*===========================================================================*/ - /* * I/O ports initial setup, this configuration is established soon after reset * in the initialization code. @@ -151,519 +184,468 @@ #define PIN_MODE_ANALOG(n) (3U << ((n) * 2U)) #define PIN_ODT_LOW(n) (0U << (n)) #define PIN_ODT_HIGH(n) (1U << (n)) -#define PIN_OUTPUT_PUSHPULL(n) (0U << (n)) -#define PIN_OUTPUT_OPENDRAIN(n) (1U << (n)) +#define PIN_OMODE_PUSHPULL(n) (0U << (n)) +#define PIN_OMODE_OPENDRAIN(n) (1U << (n)) #define PIN_ODRVR_STRONGER(n) (1U << ((n) * 2U)) -#define PIN_ODRVR_MODERATE(n) (2U << ((n) * 2U)) -#define PIN_PULL_NONE(n) (0U << ((n) * 2U)) -#define PIN_PULL_UP(n) (1U << ((n) * 2U)) -#define PIN_PULL_DOWN(n) (2U << ((n) * 2U)) -#define PIN_MUX(n, v) ((v) << (((n) % 8U) * 4U)) -#define PIN_HDRV_NOTACTIVE(n) (0U << (n)) -#define PIN_HDRV_ACTIVE(n) (1U << (n)) - +#define PIN_ODRVR_MODERATE(n) (3U << ((n) * 2U)) +#define PIN_PULL_FLOATING(n) (0U << ((n) * 2U)) +#define PIN_PULL_PULLUP(n) (1U << ((n) * 2U)) +#define PIN_PULL_PULLDOWN(n) (2U << ((n) * 2U)) +#define PIN_IOMUX_MUX(n, v) ((v) << (((n) % 8U) * 4U)) +#define PIN_WPR_DISABLED(n) (0U << (n)) +#define PIN_WPR_ENABLED(n) (1U << (n)) +#define PIN_HDRV_DISABLED(n) (0U << (n)) +#define PIN_HDRV_ENABLED(n) (1U << (n)) /* - * GPIOA setup: + * Port A setup. * - * PA0 - PIN0 (output none pull). - * PA1 - PIN1 (input none pull). - * PA2 - PIN2 (input none pull). - * PA3 - PIN3 (input none pull). - * PA4 - PIN4 (input none pull). - * PA5 - PIN5 (input none pull). - * PA6 - PIN6 (input none pull). - * PA7 - PIN7 (input none pull). - * PA8 - PIN8 (input none pull). - * PA9 - PIN9 (mux 7). - * PA10 - PIN10 (mux 7). - * PA11 - PIN11 (input none pull). - * PA12 - PIN12 (input none pull). - * PA13 - SWDIO (mux 0). - * PA14 - SWCLK (mux 0). - * PA15 - PIN15 (input none pull). + * PA0 - BUTTON (input floating). + * PA1 - ARD_A1 (input pullup). + * PA2 - ARD_D1 (input pullup). + * PA3 - ARD_D0 (input pullup). + * PA4 - ARD_A2 (input pullup). + * PA5 - ARD_D13 (input pullup). + * PA6 - ARD_D12 (input pullup). + * PA7 - ARD_D11 (input pullup). + * PA8 - ARD_D7 (input pullup). + * PA9 - ARD_D8 USART1_TX (multiplexing 7). + * PA10 - ARD_D2 USART1_RX (multiplexing 7). + * PA11 - PIN11 (input floating). + * PA12 - PIN12 (input floating). + * PA13 - SWDIO (multiplexing 0). + * PA14 - SWCLK (multiplexing 0). + * PA15 - ARD_D10 (input pullup). */ -#define VAL_GPIOA_MODE (PIN_MODE_INPUT(GPIOA_BUTTON) | \ - PIN_MODE_INPUT(GPIOA_PIN1) | \ - PIN_MODE_INPUT(GPIOA_PIN2) | \ - PIN_MODE_INPUT(GPIOA_PIN3) | \ - PIN_MODE_INPUT(GPIOA_PIN4) | \ - PIN_MODE_INPUT(GPIOA_PIN5) | \ - PIN_MODE_INPUT(GPIOA_PIN6) | \ - PIN_MODE_INPUT(GPIOA_PIN7) | \ - PIN_MODE_INPUT(GPIOA_PIN8) | \ - PIN_MODE_MUX(GPIOA_PIN9) | \ - PIN_MODE_MUX(GPIOA_PIN10) | \ - PIN_MODE_INPUT(GPIOA_PIN11) | \ - PIN_MODE_INPUT(GPIOA_PIN12) | \ - PIN_MODE_MUX(GPIOA_SWDIO) | \ - PIN_MODE_MUX(GPIOA_SWCLK) | \ - PIN_MODE_INPUT(GPIOA_PIN15)) - -#define VAL_GPIOA_ODT (PIN_ODT_HIGH(GPIOA_BUTTON) | \ - PIN_ODT_HIGH(GPIOA_PIN1) | \ - PIN_ODT_HIGH(GPIOA_PIN2) | \ - PIN_ODT_HIGH(GPIOA_PIN3) | \ - PIN_ODT_HIGH(GPIOA_PIN4) | \ - PIN_ODT_HIGH(GPIOA_PIN5) | \ - PIN_ODT_HIGH(GPIOA_PIN6) | \ - PIN_ODT_HIGH(GPIOA_PIN7) | \ - PIN_ODT_HIGH(GPIOA_PIN8) | \ - PIN_ODT_HIGH(GPIOA_PIN9) | \ - PIN_ODT_HIGH(GPIOA_PIN10) | \ - PIN_ODT_HIGH(GPIOA_PIN11) | \ - PIN_ODT_HIGH(GPIOA_PIN12) | \ - PIN_ODT_HIGH(GPIOA_SWDIO) | \ - PIN_ODT_HIGH(GPIOA_SWCLK) | \ - PIN_ODT_HIGH(GPIOA_PIN15)) - -#define VAL_GPIOA_OUTPUT (PIN_OUTPUT_PUSHPULL(GPIOA_BUTTON) | \ - PIN_OUTPUT_PUSHPULL(GPIOA_PIN1) | \ - PIN_OUTPUT_PUSHPULL(GPIOA_PIN2) | \ - PIN_OUTPUT_PUSHPULL(GPIOA_PIN3) | \ - PIN_OUTPUT_PUSHPULL(GPIOA_PIN4) | \ - PIN_OUTPUT_PUSHPULL(GPIOA_PIN5) | \ - PIN_OUTPUT_PUSHPULL(GPIOA_PIN6) | \ - PIN_OUTPUT_PUSHPULL(GPIOA_PIN7) | \ - PIN_OUTPUT_PUSHPULL(GPIOA_PIN8) | \ - PIN_OUTPUT_PUSHPULL(GPIOA_PIN9) | \ - PIN_OUTPUT_PUSHPULL(GPIOA_PIN10) | \ - PIN_OUTPUT_PUSHPULL(GPIOA_PIN11) | \ - PIN_OUTPUT_PUSHPULL(GPIOA_PIN12) | \ - PIN_OUTPUT_PUSHPULL(GPIOA_SWDIO) | \ - PIN_OUTPUT_PUSHPULL(GPIOA_SWCLK) | \ - PIN_OUTPUT_PUSHPULL(GPIOA_PIN15)) - -#define VAL_GPIOA_ODRVR (PIN_ODRVR_STRONGER(GPIOA_BUTTON) | \ - PIN_ODRVR_STRONGER(GPIOA_PIN1) | \ - PIN_ODRVR_STRONGER(GPIOA_PIN2) | \ - PIN_ODRVR_STRONGER(GPIOA_PIN3) | \ - PIN_ODRVR_STRONGER(GPIOA_PIN4) | \ - PIN_ODRVR_STRONGER(GPIOA_PIN5) | \ - PIN_ODRVR_STRONGER(GPIOA_PIN6) | \ - PIN_ODRVR_STRONGER(GPIOA_PIN7) | \ - PIN_ODRVR_STRONGER(GPIOA_PIN8) | \ - PIN_ODRVR_STRONGER(GPIOA_PIN9) | \ - PIN_ODRVR_STRONGER(GPIOA_PIN10) | \ - PIN_ODRVR_STRONGER(GPIOA_PIN11) | \ - PIN_ODRVR_STRONGER(GPIOA_PIN12) | \ - PIN_ODRVR_STRONGER(GPIOA_SWDIO) | \ - PIN_ODRVR_STRONGER(GPIOA_SWCLK) | \ - PIN_ODRVR_STRONGER(GPIOA_PIN15)) +#define VAL_GPIOA_CFGR (PIN_MODE_INPUT(GPIOA_BUTTON) | \ + PIN_MODE_INPUT(GPIOA_ARD_A1) | \ + PIN_MODE_INPUT(GPIOA_ARD_D1) | \ + PIN_MODE_INPUT(GPIOA_ARD_D0) | \ + PIN_MODE_INPUT(GPIOA_ARD_A2) | \ + PIN_MODE_INPUT(GPIOA_ARD_D13) | \ + PIN_MODE_INPUT(GPIOA_ARD_D12) | \ + PIN_MODE_INPUT(GPIOA_ARD_D11) | \ + PIN_MODE_INPUT(GPIOA_ARD_D7) | \ + PIN_MODE_MUX(GPIOA_ARD_D8) | \ + PIN_MODE_MUX(GPIOA_ARD_D2) | \ + PIN_MODE_INPUT(GPIOA_PIN11) | \ + PIN_MODE_INPUT(GPIOA_PIN12) | \ + PIN_MODE_MUX(GPIOA_SWDIO) | \ + PIN_MODE_MUX(GPIOA_SWCLK) | \ + PIN_MODE_INPUT(GPIOA_ARD_D10)) +#define VAL_GPIOA_OMODE (PIN_OMODE_PUSHPULL(GPIOA_BUTTON) | \ + PIN_OMODE_PUSHPULL(GPIOA_ARD_A1) | \ + PIN_OMODE_PUSHPULL(GPIOA_ARD_D1) | \ + PIN_OMODE_PUSHPULL(GPIOA_ARD_D0) | \ + PIN_OMODE_PUSHPULL(GPIOA_ARD_A2) | \ + PIN_OMODE_PUSHPULL(GPIOA_ARD_D13) | \ + PIN_OMODE_PUSHPULL(GPIOA_ARD_D12) | \ + PIN_OMODE_PUSHPULL(GPIOA_ARD_D11) | \ + PIN_OMODE_PUSHPULL(GPIOA_ARD_D7) | \ + PIN_OMODE_PUSHPULL(GPIOA_ARD_D8) | \ + PIN_OMODE_PUSHPULL(GPIOA_ARD_D2) | \ + PIN_OMODE_PUSHPULL(GPIOA_PIN11) | \ + PIN_OMODE_PUSHPULL(GPIOA_PIN12) | \ + PIN_OMODE_PUSHPULL(GPIOA_SWDIO) | \ + PIN_OMODE_PUSHPULL(GPIOA_SWCLK) | \ + PIN_OMODE_PUSHPULL(GPIOA_ARD_D10)) +#define VAL_GPIOA_ODRVR (PIN_ODRVR_STRONGER(GPIOA_BUTTON) | \ + PIN_ODRVR_STRONGER(GPIOA_ARD_A1) | \ + PIN_ODRVR_STRONGER(GPIOA_ARD_D1) | \ + PIN_ODRVR_STRONGER(GPIOA_ARD_D0) | \ + PIN_ODRVR_STRONGER(GPIOA_ARD_A2) | \ + PIN_ODRVR_STRONGER(GPIOA_ARD_D13) | \ + PIN_ODRVR_STRONGER(GPIOA_ARD_D12) | \ + PIN_ODRVR_STRONGER(GPIOA_ARD_D11) | \ + PIN_ODRVR_STRONGER(GPIOA_ARD_D7) | \ + PIN_ODRVR_STRONGER(GPIOA_ARD_D8) | \ + PIN_ODRVR_STRONGER(GPIOA_ARD_D2) | \ + PIN_ODRVR_STRONGER(GPIOA_PIN11) | \ + PIN_ODRVR_STRONGER(GPIOA_PIN12) | \ + PIN_ODRVR_STRONGER(GPIOA_SWDIO) | \ + PIN_ODRVR_STRONGER(GPIOA_SWCLK) | \ + PIN_ODRVR_STRONGER(GPIOA_ARD_D10)) +#define VAL_GPIOA_PULL (PIN_PULL_FLOATING(GPIOA_BUTTON) | \ + PIN_PULL_PULLUP(GPIOA_ARD_A1) | \ + PIN_PULL_PULLUP(GPIOA_ARD_D1) | \ + PIN_PULL_PULLUP(GPIOA_ARD_D0) | \ + PIN_PULL_PULLUP(GPIOA_ARD_A2) | \ + PIN_PULL_PULLUP(GPIOA_ARD_D13) | \ + PIN_PULL_PULLUP(GPIOA_ARD_D12) | \ + PIN_PULL_PULLUP(GPIOA_ARD_D11) | \ + PIN_PULL_PULLUP(GPIOA_ARD_D7) | \ + PIN_PULL_FLOATING(GPIOA_ARD_D8) | \ + PIN_PULL_FLOATING(GPIOA_ARD_D2) | \ + PIN_PULL_FLOATING(GPIOA_PIN11) | \ + PIN_PULL_FLOATING(GPIOA_PIN12) | \ + PIN_PULL_PULLUP(GPIOA_SWDIO) | \ + PIN_PULL_PULLDOWN(GPIOA_SWCLK) | \ + PIN_PULL_PULLUP(GPIOA_ARD_D10)) +#define VAL_GPIOA_ODT (PIN_ODT_HIGH(GPIOA_BUTTON) | \ + PIN_ODT_HIGH(GPIOA_ARD_A1) | \ + PIN_ODT_HIGH(GPIOA_ARD_D1) | \ + PIN_ODT_HIGH(GPIOA_ARD_D0) | \ + PIN_ODT_HIGH(GPIOA_ARD_A2) | \ + PIN_ODT_HIGH(GPIOA_ARD_D13) | \ + PIN_ODT_HIGH(GPIOA_ARD_D12) | \ + PIN_ODT_HIGH(GPIOA_ARD_D11) | \ + PIN_ODT_HIGH(GPIOA_ARD_D7) | \ + PIN_ODT_HIGH(GPIOA_ARD_D8) | \ + PIN_ODT_HIGH(GPIOA_ARD_D2) | \ + PIN_ODT_HIGH(GPIOA_PIN11) | \ + PIN_ODT_HIGH(GPIOA_PIN12) | \ + PIN_ODT_HIGH(GPIOA_SWDIO) | \ + PIN_ODT_HIGH(GPIOA_SWCLK) | \ + PIN_ODT_HIGH(GPIOA_ARD_D10)) +#define VAL_GPIOA_MUXL (PIN_IOMUX_MUX(GPIOA_BUTTON, 0U) | \ + PIN_IOMUX_MUX(GPIOA_ARD_A1, 0U) | \ + PIN_IOMUX_MUX(GPIOA_ARD_D1, 0U) | \ + PIN_IOMUX_MUX(GPIOA_ARD_D0, 0U) | \ + PIN_IOMUX_MUX(GPIOA_ARD_A2, 0U) | \ + PIN_IOMUX_MUX(GPIOA_ARD_D13, 0U) | \ + PIN_IOMUX_MUX(GPIOA_ARD_D12, 0U) | \ + PIN_IOMUX_MUX(GPIOA_ARD_D11, 0U)) +#define VAL_GPIOA_MUXH (PIN_IOMUX_MUX(GPIOA_ARD_D7, 0U) | \ + PIN_IOMUX_MUX(GPIOA_ARD_D8, 7U) | \ + PIN_IOMUX_MUX(GPIOA_ARD_D2, 7U) | \ + PIN_IOMUX_MUX(GPIOA_PIN11, 0U) | \ + PIN_IOMUX_MUX(GPIOA_PIN12, 0U) | \ + PIN_IOMUX_MUX(GPIOA_SWDIO, 0U) | \ + PIN_IOMUX_MUX(GPIOA_SWCLK, 0U) | \ + PIN_IOMUX_MUX(GPIOA_ARD_D10, 0U)) +#define VAL_GPIOA_HDRV (PIN_HDRV_DISABLED(GPIOA_BUTTON) | \ + PIN_HDRV_DISABLED(GPIOA_ARD_A1) | \ + PIN_HDRV_DISABLED(GPIOA_ARD_D1) | \ + PIN_HDRV_DISABLED(GPIOA_ARD_D0) | \ + PIN_HDRV_DISABLED(GPIOA_ARD_A2) | \ + PIN_HDRV_DISABLED(GPIOA_ARD_D13) | \ + PIN_HDRV_DISABLED(GPIOA_ARD_D12) | \ + PIN_HDRV_DISABLED(GPIOA_ARD_D11) | \ + PIN_HDRV_DISABLED(GPIOA_ARD_D7) | \ + PIN_HDRV_DISABLED(GPIOA_ARD_D8) | \ + PIN_HDRV_DISABLED(GPIOA_ARD_D2) | \ + PIN_HDRV_DISABLED(GPIOA_PIN11) | \ + PIN_HDRV_DISABLED(GPIOA_PIN12) | \ + PIN_HDRV_DISABLED(GPIOA_SWDIO) | \ + PIN_HDRV_DISABLED(GPIOA_SWCLK) | \ + PIN_HDRV_DISABLED(GPIOA_ARD_D10)) -#define VAL_GPIOA_PULL (PIN_PULL_NONE(GPIOA_BUTTON) | \ - PIN_PULL_NONE(GPIOA_PIN1) | \ - PIN_PULL_NONE(GPIOA_PIN2) | \ - PIN_PULL_NONE(GPIOA_PIN3) | \ - PIN_PULL_NONE(GPIOA_PIN4) | \ - PIN_PULL_NONE(GPIOA_PIN5) | \ - PIN_PULL_NONE(GPIOA_PIN6) | \ - PIN_PULL_NONE(GPIOA_PIN7) | \ - PIN_PULL_NONE(GPIOA_PIN8) | \ - PIN_PULL_NONE(GPIOA_PIN9) | \ - PIN_PULL_NONE(GPIOA_PIN10) | \ - PIN_PULL_NONE(GPIOA_PIN11) | \ - PIN_PULL_NONE(GPIOA_PIN12) | \ - PIN_PULL_NONE(GPIOA_SWDIO) | \ - PIN_PULL_NONE(GPIOA_SWCLK) | \ - PIN_PULL_NONE(GPIOA_PIN15)) - -#define VAL_GPIOA_MUXL (PIN_MUX(GPIOA_BUTTON, 0U) | \ - PIN_MUX(GPIOA_PIN1, 0U) | \ - PIN_MUX(GPIOA_PIN2, 0U) | \ - PIN_MUX(GPIOA_PIN3, 0U) | \ - PIN_MUX(GPIOA_PIN4, 5U) | \ - PIN_MUX(GPIOA_PIN5, 5U) | \ - PIN_MUX(GPIOA_PIN6, 5U) | \ - PIN_MUX(GPIOA_PIN7, 5U)) - -#define VAL_GPIOA_MUXH (PIN_MUX(GPIOA_PIN8, 0U) | \ - PIN_MUX(GPIOA_PIN9, 7U) | \ - PIN_MUX(GPIOA_PIN10, 7U) | \ - PIN_MUX(GPIOA_PIN11, 0U) | \ - PIN_MUX(GPIOA_PIN12, 0U) | \ - PIN_MUX(GPIOA_SWDIO, 0U) | \ - PIN_MUX(GPIOA_SWCLK, 0U) | \ - PIN_MUX(GPIOA_PIN15, 0U)) - -#define VAL_GPIOA_HDRV (PIN_HDRV_NOTACTIVE(GPIOA_BUTTON) | \ - PIN_HDRV_NOTACTIVE(GPIOA_PIN1) | \ - PIN_HDRV_NOTACTIVE(GPIOA_PIN2) | \ - PIN_HDRV_NOTACTIVE(GPIOA_PIN3) | \ - PIN_HDRV_NOTACTIVE(GPIOA_PIN4) | \ - PIN_HDRV_NOTACTIVE(GPIOA_PIN5) | \ - PIN_HDRV_NOTACTIVE(GPIOA_PIN6) | \ - PIN_HDRV_NOTACTIVE(GPIOA_PIN7) | \ - PIN_HDRV_NOTACTIVE(GPIOA_PIN8) | \ - PIN_HDRV_NOTACTIVE(GPIOA_PIN9) | \ - PIN_HDRV_NOTACTIVE(GPIOA_PIN10) | \ - PIN_HDRV_NOTACTIVE(GPIOA_PIN11) | \ - PIN_HDRV_NOTACTIVE(GPIOA_PIN12) | \ - PIN_HDRV_NOTACTIVE(GPIOA_SWDIO) | \ - PIN_HDRV_NOTACTIVE(GPIOA_SWCLK) | \ - PIN_HDRV_NOTACTIVE(GPIOA_PIN15)) /* - * GPIOB setup: + * Port B setup. * - * PB0 - PIN0 (input none pull). - * PB1 - PIN1 (input none pull). - * PB2 - PIN2 (input none pull). - * PB3 - PIN3 (input none pull). - * PB4 - PIN4 (input none pull). - * PB5 - PIN5 (input none pull). - * PB6 - PIN6 (input none pull). - * PB7 - PIN7 (input none pull). - * PB8 - PIN8 (input none pull). - * PB9 - PIN9 (input none pull). - * PB10 - PIN10 (input none pull). - * PB11 - PIN11 (input none pull). - * PB12 - PIN12 (input none pull). - * PB13 - PIN13 (input none pull). - * PB14 - PIN14 (input none pull). - * PB15 - PIN15 (input none pull). + * PB0 - ARD_A3 (input pullup). + * PB1 - PIN1 (input pullup). + * PB2 - PIN2 (input pullup). + * PB3 - SWO (multiplexing 0). + * PB4 - ARD_D5 (input pullup). + * PB5 - ARD_D4 (input pullup). + * PB6 - PIN6 (input pullup). + * PB7 - PIN7 (input pullup). + * PB8 - ARD_SCL (input pullup). + * PB9 - ARD_SDA (input pullup). + * PB10 - ARD_D6 (input pullup). + * PB12 - ARD_NSS (input pullup). + * PB13 - ARD_SCK (input pullup). */ -#define VAL_GPIOB_MODE (PIN_MODE_INPUT(GPIOB_PIN0) | \ - PIN_MODE_INPUT(GPIOB_PIN1) | \ - PIN_MODE_INPUT(GPIOB_PIN2) | \ - PIN_MODE_INPUT(GPIOB_PIN3) | \ - PIN_MODE_INPUT(GPIOB_PIN4) | \ - PIN_MODE_INPUT(GPIOB_PIN5) | \ - PIN_MODE_INPUT(GPIOB_PIN6) | \ - PIN_MODE_INPUT(GPIOB_PIN7) | \ - PIN_MODE_INPUT(GPIOB_PIN8) | \ - PIN_MODE_INPUT(GPIOB_PIN9) | \ - PIN_MODE_INPUT(GPIOB_PIN10) | \ - PIN_MODE_INPUT(GPIOB_PIN11) | \ - PIN_MODE_INPUT(GPIOB_PIN12) | \ - PIN_MODE_INPUT(GPIOB_PIN13) | \ - PIN_MODE_INPUT(GPIOB_PIN14) | \ - PIN_MODE_INPUT(GPIOB_PIN15)) - -#define VAL_GPIOB_ODT (PIN_ODT_HIGH(GPIOB_PIN0) | \ - PIN_ODT_HIGH(GPIOB_PIN1) | \ - PIN_ODT_HIGH(GPIOB_PIN2) | \ - PIN_ODT_HIGH(GPIOB_PIN3) | \ - PIN_ODT_HIGH(GPIOB_PIN4) | \ - PIN_ODT_HIGH(GPIOB_PIN5) | \ - PIN_ODT_HIGH(GPIOB_PIN6) | \ - PIN_ODT_HIGH(GPIOB_PIN7) | \ - PIN_ODT_HIGH(GPIOB_PIN8) | \ - PIN_ODT_HIGH(GPIOB_PIN9) | \ - PIN_ODT_HIGH(GPIOB_PIN10) | \ - PIN_ODT_HIGH(GPIOB_PIN11) | \ - PIN_ODT_HIGH(GPIOB_PIN12) | \ - PIN_ODT_HIGH(GPIOB_PIN13) | \ - PIN_ODT_HIGH(GPIOB_PIN14) | \ - PIN_ODT_HIGH(GPIOB_PIN15)) - -#define VAL_GPIOB_OUTPUT (PIN_OUTPUT_PUSHPULL(GPIOB_PIN0) | \ - PIN_OUTPUT_PUSHPULL(GPIOB_PIN1) | \ - PIN_OUTPUT_PUSHPULL(GPIOB_PIN2) | \ - PIN_OUTPUT_PUSHPULL(GPIOB_PIN3) | \ - PIN_OUTPUT_PUSHPULL(GPIOB_PIN4) | \ - PIN_OUTPUT_PUSHPULL(GPIOB_PIN5) | \ - PIN_OUTPUT_PUSHPULL(GPIOB_PIN6) | \ - PIN_OUTPUT_PUSHPULL(GPIOB_PIN7) | \ - PIN_OUTPUT_PUSHPULL(GPIOB_PIN8) | \ - PIN_OUTPUT_PUSHPULL(GPIOB_PIN9) | \ - PIN_OUTPUT_PUSHPULL(GPIOB_PIN10) | \ - PIN_OUTPUT_PUSHPULL(GPIOB_PIN11) | \ - PIN_OUTPUT_PUSHPULL(GPIOB_PIN12) | \ - PIN_OUTPUT_PUSHPULL(GPIOB_PIN13) | \ - PIN_OUTPUT_PUSHPULL(GPIOB_PIN14) | \ - PIN_OUTPUT_PUSHPULL(GPIOB_PIN15)) - -#define VAL_GPIOB_ODRVR (PIN_ODRVR_STRONGER(GPIOB_PIN0) | \ - PIN_ODRVR_STRONGER(GPIOB_PIN1) | \ - PIN_ODRVR_STRONGER(GPIOB_PIN2) | \ - PIN_ODRVR_STRONGER(GPIOB_PIN3) | \ - PIN_ODRVR_STRONGER(GPIOB_PIN4) | \ - PIN_ODRVR_STRONGER(GPIOB_PIN5) | \ - PIN_ODRVR_STRONGER(GPIOB_PIN6) | \ - PIN_ODRVR_STRONGER(GPIOB_PIN7) | \ - PIN_ODRVR_STRONGER(GPIOB_PIN8) | \ - PIN_ODRVR_STRONGER(GPIOB_PIN9) | \ - PIN_ODRVR_STRONGER(GPIOB_PIN10) | \ - PIN_ODRVR_STRONGER(GPIOB_PIN11) | \ - PIN_ODRVR_STRONGER(GPIOB_PIN12) | \ - PIN_ODRVR_STRONGER(GPIOB_PIN13) | \ - PIN_ODRVR_STRONGER(GPIOB_PIN14) | \ - PIN_ODRVR_STRONGER(GPIOB_PIN15)) - -#define VAL_GPIOB_PULL (PIN_PULL_NONE(GPIOB_PIN0) | \ - PIN_PULL_NONE(GPIOB_PIN1) | \ - PIN_PULL_NONE(GPIOB_PIN2) | \ - PIN_PULL_NONE(GPIOB_PIN3) | \ - PIN_PULL_NONE(GPIOB_PIN4) | \ - PIN_PULL_NONE(GPIOB_PIN5) | \ - PIN_PULL_NONE(GPIOB_PIN6) | \ - PIN_PULL_NONE(GPIOB_PIN7) | \ - PIN_PULL_NONE(GPIOB_PIN8) | \ - PIN_PULL_NONE(GPIOB_PIN9) | \ - PIN_PULL_NONE(GPIOB_PIN10) | \ - PIN_PULL_NONE(GPIOB_PIN11) | \ - PIN_PULL_NONE(GPIOB_PIN12) | \ - PIN_PULL_NONE(GPIOB_PIN13) | \ - PIN_PULL_NONE(GPIOB_PIN14) | \ - PIN_PULL_NONE(GPIOB_PIN15)) - -#define VAL_GPIOB_MUXL (PIN_MUX(GPIOB_PIN0, 0U) | \ - PIN_MUX(GPIOB_PIN1, 0U) | \ - PIN_MUX(GPIOB_PIN2, 0U) | \ - PIN_MUX(GPIOB_PIN3, 0U) | \ - PIN_MUX(GPIOB_PIN4, 0U) | \ - PIN_MUX(GPIOB_PIN5, 0U) | \ - PIN_MUX(GPIOB_PIN6, 0U) | \ - PIN_MUX(GPIOB_PIN7, 0U)) - -#define VAL_GPIOB_MUXH (PIN_MUX(GPIOB_PIN8, 0U) | \ - PIN_MUX(GPIOB_PIN9, 0U) | \ - PIN_MUX(GPIOB_PIN10, 0U) | \ - PIN_MUX(GPIOB_PIN11, 0U) | \ - PIN_MUX(GPIOB_PIN12, 0U) | \ - PIN_MUX(GPIOB_PIN13, 0U) | \ - PIN_MUX(GPIOB_PIN14, 0U) | \ - PIN_MUX(GPIOB_PIN15, 0U)) - -#define VAL_GPIOB_HDRV (PIN_HDRV_NOTACTIVE(GPIOB_PIN0) | \ - PIN_HDRV_NOTACTIVE(GPIOB_PIN1) | \ - PIN_HDRV_NOTACTIVE(GPIOB_PIN2) | \ - PIN_HDRV_NOTACTIVE(GPIOB_PIN3) | \ - PIN_HDRV_NOTACTIVE(GPIOB_PIN4) | \ - PIN_HDRV_NOTACTIVE(GPIOB_PIN5) | \ - PIN_HDRV_NOTACTIVE(GPIOB_PIN6) | \ - PIN_HDRV_NOTACTIVE(GPIOB_PIN7) | \ - PIN_HDRV_NOTACTIVE(GPIOB_PIN8) | \ - PIN_HDRV_NOTACTIVE(GPIOB_PIN9) | \ - PIN_HDRV_NOTACTIVE(GPIOB_PIN10) | \ - PIN_HDRV_NOTACTIVE(GPIOB_PIN11) | \ - PIN_HDRV_NOTACTIVE(GPIOB_PIN12) | \ - PIN_HDRV_NOTACTIVE(GPIOB_PIN13) | \ - PIN_HDRV_NOTACTIVE(GPIOB_PIN14) | \ - PIN_HDRV_NOTACTIVE(GPIOB_PIN15)) +#define VAL_GPIOB_CFGR (PIN_MODE_INPUT(GPIOB_ARD_A3) | \ + PIN_MODE_INPUT(GPIOB_PIN1) | \ + PIN_MODE_INPUT(GPIOB_PIN2) | \ + PIN_MODE_MUX(GPIOB_SWO) | \ + PIN_MODE_INPUT(GPIOB_ARD_D5) | \ + PIN_MODE_INPUT(GPIOB_ARD_D4) | \ + PIN_MODE_INPUT(GPIOB_PIN6) | \ + PIN_MODE_INPUT(GPIOB_PIN7) | \ + PIN_MODE_INPUT(GPIOB_ARD_SCL) | \ + PIN_MODE_INPUT(GPIOB_ARD_SDA) | \ + PIN_MODE_INPUT(GPIOB_ARD_D6) | \ + PIN_MODE_INPUT(GPIOB_ARD_NSS) | \ + PIN_MODE_INPUT(GPIOB_ARD_SCK)) +#define VAL_GPIOB_OMODE (PIN_OMODE_PUSHPULL(GPIOB_ARD_A3) | \ + PIN_OMODE_PUSHPULL(GPIOB_PIN1) | \ + PIN_OMODE_PUSHPULL(GPIOB_PIN2) | \ + PIN_OMODE_PUSHPULL(GPIOB_SWO) | \ + PIN_OMODE_PUSHPULL(GPIOB_ARD_D5) | \ + PIN_OMODE_PUSHPULL(GPIOB_ARD_D4) | \ + PIN_OMODE_PUSHPULL(GPIOB_PIN6) | \ + PIN_OMODE_PUSHPULL(GPIOB_PIN7) | \ + PIN_OMODE_PUSHPULL(GPIOB_ARD_SCL) | \ + PIN_OMODE_PUSHPULL(GPIOB_ARD_SDA) | \ + PIN_OMODE_PUSHPULL(GPIOB_ARD_D6) | \ + PIN_OMODE_PUSHPULL(GPIOB_ARD_NSS) | \ + PIN_OMODE_PUSHPULL(GPIOB_ARD_SCK)) +#define VAL_GPIOB_ODRVR (PIN_ODRVR_STRONGER(GPIOB_ARD_A3) | \ + PIN_ODRVR_STRONGER(GPIOB_PIN1) | \ + PIN_ODRVR_STRONGER(GPIOB_PIN2) | \ + PIN_ODRVR_STRONGER(GPIOB_SWO) | \ + PIN_ODRVR_STRONGER(GPIOB_ARD_D5) | \ + PIN_ODRVR_STRONGER(GPIOB_ARD_D4) | \ + PIN_ODRVR_STRONGER(GPIOB_PIN6) | \ + PIN_ODRVR_STRONGER(GPIOB_PIN7) | \ + PIN_ODRVR_STRONGER(GPIOB_ARD_SCL) | \ + PIN_ODRVR_STRONGER(GPIOB_ARD_SDA) | \ + PIN_ODRVR_STRONGER(GPIOB_ARD_D6) | \ + PIN_ODRVR_STRONGER(GPIOB_ARD_NSS) | \ + PIN_ODRVR_STRONGER(GPIOB_ARD_SCK)) +#define VAL_GPIOB_PULL (PIN_PULL_PULLUP(GPIOB_ARD_A3) | \ + PIN_PULL_PULLUP(GPIOB_PIN1) | \ + PIN_PULL_PULLUP(GPIOB_PIN2) | \ + PIN_PULL_FLOATING(GPIOB_SWO) | \ + PIN_PULL_PULLUP(GPIOB_ARD_D5) | \ + PIN_PULL_PULLUP(GPIOB_ARD_D4) | \ + PIN_PULL_PULLUP(GPIOB_PIN6) | \ + PIN_PULL_PULLUP(GPIOB_PIN7) | \ + PIN_PULL_PULLUP(GPIOB_ARD_SCL) | \ + PIN_PULL_PULLUP(GPIOB_ARD_SDA) | \ + PIN_PULL_PULLUP(GPIOB_ARD_D6) | \ + PIN_PULL_PULLUP(GPIOB_ARD_NSS) | \ + PIN_PULL_PULLUP(GPIOB_ARD_SCK)) +#define VAL_GPIOB_ODT (PIN_ODT_HIGH(GPIOB_ARD_A3) | \ + PIN_ODT_HIGH(GPIOB_PIN1) | \ + PIN_ODT_HIGH(GPIOB_PIN2) | \ + PIN_ODT_HIGH(GPIOB_SWO) | \ + PIN_ODT_HIGH(GPIOB_ARD_D5) | \ + PIN_ODT_HIGH(GPIOB_ARD_D4) | \ + PIN_ODT_HIGH(GPIOB_PIN6) | \ + PIN_ODT_HIGH(GPIOB_PIN7) | \ + PIN_ODT_HIGH(GPIOB_ARD_SCL) | \ + PIN_ODT_HIGH(GPIOB_ARD_SDA) | \ + PIN_ODT_HIGH(GPIOB_ARD_D6) | \ + PIN_ODT_HIGH(GPIOB_ARD_NSS) | \ + PIN_ODT_HIGH(GPIOB_ARD_SCK)) +#define VAL_GPIOB_MUXL (PIN_IOMUX_MUX(GPIOB_ARD_A3, 0U) | \ + PIN_IOMUX_MUX(GPIOB_PIN1, 0U) | \ + PIN_IOMUX_MUX(GPIOB_PIN2, 0U) | \ + PIN_IOMUX_MUX(GPIOB_SWO, 0U) | \ + PIN_IOMUX_MUX(GPIOB_ARD_D5, 0U) | \ + PIN_IOMUX_MUX(GPIOB_ARD_D4, 0U) | \ + PIN_IOMUX_MUX(GPIOB_PIN6, 0U) | \ + PIN_IOMUX_MUX(GPIOB_PIN7, 0U)) +#define VAL_GPIOB_MUXH (PIN_IOMUX_MUX(GPIOB_ARD_SCL, 0U) | \ + PIN_IOMUX_MUX(GPIOB_ARD_SDA, 0U) | \ + PIN_IOMUX_MUX(GPIOB_ARD_D6, 0U) | \ + PIN_IOMUX_MUX(GPIOB_ARD_NSS, 0U) | \ + PIN_IOMUX_MUX(GPIOB_ARD_SCK, 0U)) +#define VAL_GPIOB_HDRV (PIN_HDRV_DISABLED(GPIOB_ARD_A3) | \ + PIN_HDRV_DISABLED(GPIOB_PIN1) | \ + PIN_HDRV_DISABLED(GPIOB_PIN2) | \ + PIN_HDRV_DISABLED(GPIOB_SWO) | \ + PIN_HDRV_DISABLED(GPIOB_ARD_D5) | \ + PIN_HDRV_DISABLED(GPIOB_ARD_D4) | \ + PIN_HDRV_DISABLED(GPIOB_PIN6) | \ + PIN_HDRV_DISABLED(GPIOB_PIN7) | \ + PIN_HDRV_DISABLED(GPIOB_ARD_SCL) | \ + PIN_HDRV_DISABLED(GPIOB_ARD_SDA) | \ + PIN_HDRV_DISABLED(GPIOB_ARD_D6) | \ + PIN_HDRV_DISABLED(GPIOB_ARD_NSS) | \ + PIN_HDRV_DISABLED(GPIOB_ARD_SCK)) /* - * GPIOC setup: + * Port C setup. * - * PC0 - PIN0 (input none pull). - * PC1 - PIN1 (input none pull). - * PC2 - PIN2 (input none pull). - * PC3 - PIN3 (input none pull). - * PC4 - PIN4 (input none pull). - * PC5 - PIN5 (input none pull). - * PC6 - PIN6 (input none pull). - * PC7 - PIN7 (input none pull). - * PC8 - PIN8 (input none pull). - * PC9 - PIN9 (input none pull). - * PC10 - PIN10 (input none pull). - * PC11 - PIN11 (input none pull). - * PC12 - PIN12 (input none pull). - * PC13 - PIN13 (input none pull). - * PC14 - PIN14 (input none pull). - * PC15 - PIN15 (input none pull). + * PC0 - ARD_A5 (input pullup). + * PC1 - ARD_A4 (input pullup). + * PC2 - ARD_MISO (input pullup). + * PC3 - ARD_MOSI (input pullup). + * PC4 - ARD_PC4 (input pullup). + * PC5 - PIN5 (input pullup). + * PC6 - PIN6 (input pullup). + * PC7 - ARD_D9 (input pullup). + * PC8 - PIN8 (input pullup). + * PC9 - PIN9 (input pullup). + * PC10 - PIN10 (input pullup). + * PC11 - PIN11 (input pullup). + * PC12 - PIN12 (input pullup). + * PC13 - BUTTON (input floating). + * PC14 - LEXT_IN (input floating). + * PC15 - LEXT_OUT (input floating). */ -#define VAL_GPIOC_MODE (PIN_MODE_INPUT(GPIOC_PIN0) | \ - PIN_MODE_INPUT(GPIOC_PIN1) | \ - PIN_MODE_INPUT(GPIOC_PIN2) | \ - PIN_MODE_INPUT(GPIOC_PIN3) | \ - PIN_MODE_INPUT(GPIOC_PIN4) | \ - PIN_MODE_INPUT(GPIOC_PIN5) | \ - PIN_MODE_INPUT(GPIOC_PIN6) | \ - PIN_MODE_INPUT(GPIOC_PIN7) | \ - PIN_MODE_INPUT(GPIOC_PIN8) | \ - PIN_MODE_INPUT(GPIOC_PIN9) | \ - PIN_MODE_INPUT(GPIOC_PIN10) | \ - PIN_MODE_INPUT(GPIOC_PIN11) | \ - PIN_MODE_INPUT(GPIOC_PIN12) | \ - PIN_MODE_INPUT(GPIOC_PIN13) | \ - PIN_MODE_INPUT(GPIOC_PIN14) | \ - PIN_MODE_INPUT(GPIOC_PIN15)) - -#define VAL_GPIOC_ODT (PIN_ODT_HIGH(GPIOC_PIN0) | \ - PIN_ODT_HIGH(GPIOC_PIN1) | \ - PIN_ODT_HIGH(GPIOC_PIN2) | \ - PIN_ODT_HIGH(GPIOC_PIN3) | \ - PIN_ODT_HIGH(GPIOC_PIN4) | \ - PIN_ODT_HIGH(GPIOC_PIN5) | \ - PIN_ODT_HIGH(GPIOC_PIN6) | \ - PIN_ODT_HIGH(GPIOC_PIN7) | \ - PIN_ODT_HIGH(GPIOC_PIN8) | \ - PIN_ODT_HIGH(GPIOC_PIN9) | \ - PIN_ODT_HIGH(GPIOC_PIN10) | \ - PIN_ODT_HIGH(GPIOC_PIN11) | \ - PIN_ODT_HIGH(GPIOC_PIN12) | \ - PIN_ODT_HIGH(GPIOC_PIN13) | \ - PIN_ODT_HIGH(GPIOC_PIN14) | \ - PIN_ODT_HIGH(GPIOC_PIN15)) - -#define VAL_GPIOC_OUTPUT (PIN_OUTPUT_PUSHPULL(GPIOC_PIN0) | \ - PIN_OUTPUT_PUSHPULL(GPIOC_PIN1) | \ - PIN_OUTPUT_PUSHPULL(GPIOC_PIN2) | \ - PIN_OUTPUT_PUSHPULL(GPIOC_PIN3) | \ - PIN_OUTPUT_PUSHPULL(GPIOC_PIN4) | \ - PIN_OUTPUT_PUSHPULL(GPIOC_PIN5) | \ - PIN_OUTPUT_PUSHPULL(GPIOC_PIN6) | \ - PIN_OUTPUT_PUSHPULL(GPIOC_PIN7) | \ - PIN_OUTPUT_PUSHPULL(GPIOC_PIN8) | \ - PIN_OUTPUT_PUSHPULL(GPIOC_PIN9) | \ - PIN_OUTPUT_PUSHPULL(GPIOC_PIN10) | \ - PIN_OUTPUT_PUSHPULL(GPIOC_PIN11) | \ - PIN_OUTPUT_PUSHPULL(GPIOC_PIN12) | \ - PIN_OUTPUT_PUSHPULL(GPIOC_PIN13) | \ - PIN_OUTPUT_PUSHPULL(GPIOC_PIN14) | \ - PIN_OUTPUT_PUSHPULL(GPIOC_PIN15)) - -#define VAL_GPIOC_ODRVR (PIN_ODRVR_STRONGER(GPIOC_PIN0) | \ - PIN_ODRVR_STRONGER(GPIOC_PIN1) | \ - PIN_ODRVR_STRONGER(GPIOC_PIN2) | \ - PIN_ODRVR_STRONGER(GPIOC_PIN3) | \ - PIN_ODRVR_STRONGER(GPIOC_PIN4) | \ - PIN_ODRVR_STRONGER(GPIOC_PIN5) | \ - PIN_ODRVR_STRONGER(GPIOC_PIN6) | \ - PIN_ODRVR_STRONGER(GPIOC_PIN7) | \ - PIN_ODRVR_STRONGER(GPIOC_PIN8) | \ - PIN_ODRVR_STRONGER(GPIOC_PIN9) | \ - PIN_ODRVR_STRONGER(GPIOC_PIN10) | \ - PIN_ODRVR_STRONGER(GPIOC_PIN11) | \ - PIN_ODRVR_STRONGER(GPIOC_PIN12) | \ - PIN_ODRVR_STRONGER(GPIOC_PIN13) | \ - PIN_ODRVR_STRONGER(GPIOC_PIN14) | \ - PIN_ODRVR_STRONGER(GPIOC_PIN15)) - -#define VAL_GPIOC_PULL (PIN_PULL_NONE(GPIOC_PIN0) | \ - PIN_PULL_NONE(GPIOC_PIN1) | \ - PIN_PULL_NONE(GPIOC_PIN2) | \ - PIN_PULL_NONE(GPIOC_PIN3) | \ - PIN_PULL_NONE(GPIOC_PIN4) | \ - PIN_PULL_NONE(GPIOC_PIN5) | \ - PIN_PULL_NONE(GPIOC_PIN6) | \ - PIN_PULL_NONE(GPIOC_PIN7) | \ - PIN_PULL_NONE(GPIOC_PIN8) | \ - PIN_PULL_NONE(GPIOC_PIN9) | \ - PIN_PULL_NONE(GPIOC_PIN10) | \ - PIN_PULL_NONE(GPIOC_PIN11) | \ - PIN_PULL_NONE(GPIOC_PIN12) | \ - PIN_PULL_NONE(GPIOC_PIN13) | \ - PIN_PULL_NONE(GPIOC_PIN14) | \ - PIN_PULL_NONE(GPIOC_PIN15)) - -#define VAL_GPIOC_MUXL (PIN_MUX(GPIOC_PIN0, 0U) | \ - PIN_MUX(GPIOC_PIN1, 0U) | \ - PIN_MUX(GPIOC_PIN2, 0U) | \ - PIN_MUX(GPIOC_PIN3, 0U) | \ - PIN_MUX(GPIOC_PIN4, 0U) | \ - PIN_MUX(GPIOC_PIN5, 0U) | \ - PIN_MUX(GPIOC_PIN6, 0U) | \ - PIN_MUX(GPIOC_PIN7, 0U)) - -#define VAL_GPIOC_MUXH (PIN_MUX(GPIOC_PIN8, 0U) | \ - PIN_MUX(GPIOC_PIN9, 0U) | \ - PIN_MUX(GPIOC_PIN10, 0U) | \ - PIN_MUX(GPIOC_PIN11, 0U) | \ - PIN_MUX(GPIOC_PIN12, 0U) | \ - PIN_MUX(GPIOC_PIN13, 0U) | \ - PIN_MUX(GPIOC_PIN14, 0U) | \ - PIN_MUX(GPIOC_PIN15, 0U)) - -#define VAL_GPIOC_HDRV (PIN_HDRV_NOTACTIVE(GPIOC_PIN0) | \ - PIN_HDRV_NOTACTIVE(GPIOC_PIN1) | \ - PIN_HDRV_NOTACTIVE(GPIOC_PIN2) | \ - PIN_HDRV_NOTACTIVE(GPIOC_PIN3) | \ - PIN_HDRV_NOTACTIVE(GPIOC_PIN4) | \ - PIN_HDRV_NOTACTIVE(GPIOC_PIN5) | \ - PIN_HDRV_NOTACTIVE(GPIOC_PIN6) | \ - PIN_HDRV_NOTACTIVE(GPIOC_PIN7) | \ - PIN_HDRV_NOTACTIVE(GPIOC_PIN8) | \ - PIN_HDRV_NOTACTIVE(GPIOC_PIN9) | \ - PIN_HDRV_NOTACTIVE(GPIOC_PIN10) | \ - PIN_HDRV_NOTACTIVE(GPIOC_PIN11) | \ - PIN_HDRV_NOTACTIVE(GPIOC_PIN12) | \ - PIN_HDRV_NOTACTIVE(GPIOC_PIN13) | \ - PIN_HDRV_NOTACTIVE(GPIOC_PIN14) | \ - PIN_HDRV_NOTACTIVE(GPIOC_PIN15)) +#define VAL_GPIOC_CFGR (PIN_MODE_INPUT(GPIOC_ARD_A5) | \ + PIN_MODE_INPUT(GPIOC_ARD_A4) | \ + PIN_MODE_INPUT(GPIOC_ARD_MISO) | \ + PIN_MODE_INPUT(GPIOC_ARD_MOSI) | \ + PIN_MODE_INPUT(GPIOC_ARD_PC4) | \ + PIN_MODE_INPUT(GPIOC_PIN5) | \ + PIN_MODE_INPUT(GPIOC_PIN6) | \ + PIN_MODE_INPUT(GPIOC_ARD_D9) | \ + PIN_MODE_INPUT(GPIOC_PIN8) | \ + PIN_MODE_INPUT(GPIOC_PIN9) | \ + PIN_MODE_INPUT(GPIOC_PIN10) | \ + PIN_MODE_INPUT(GPIOC_PIN11) | \ + PIN_MODE_INPUT(GPIOC_PIN12) | \ + PIN_MODE_INPUT(GPIOC_BUTTON) | \ + PIN_MODE_INPUT(GPIOC_LEXT_IN) | \ + PIN_MODE_INPUT(GPIOC_LEXT_OUT)) +#define VAL_GPIOC_OMODE (PIN_OMODE_PUSHPULL(GPIOC_ARD_A5) | \ + PIN_OMODE_PUSHPULL(GPIOC_ARD_A4) | \ + PIN_OMODE_PUSHPULL(GPIOC_ARD_MISO) | \ + PIN_OMODE_PUSHPULL(GPIOC_ARD_MOSI) | \ + PIN_OMODE_PUSHPULL(GPIOC_ARD_PC4) | \ + PIN_OMODE_PUSHPULL(GPIOC_PIN5) | \ + PIN_OMODE_PUSHPULL(GPIOC_PIN6) | \ + PIN_OMODE_PUSHPULL(GPIOC_ARD_D9) | \ + PIN_OMODE_PUSHPULL(GPIOC_PIN8) | \ + PIN_OMODE_PUSHPULL(GPIOC_PIN9) | \ + PIN_OMODE_PUSHPULL(GPIOC_PIN10) | \ + PIN_OMODE_PUSHPULL(GPIOC_PIN11) | \ + PIN_OMODE_PUSHPULL(GPIOC_PIN12) | \ + PIN_OMODE_PUSHPULL(GPIOC_BUTTON) | \ + PIN_OMODE_PUSHPULL(GPIOC_LEXT_IN) | \ + PIN_OMODE_PUSHPULL(GPIOC_LEXT_OUT)) +#define VAL_GPIOC_ODRVR (PIN_ODRVR_STRONGER(GPIOC_ARD_A5) | \ + PIN_ODRVR_STRONGER(GPIOC_ARD_A4) | \ + PIN_ODRVR_STRONGER(GPIOC_ARD_MISO) | \ + PIN_ODRVR_STRONGER(GPIOC_ARD_MOSI) | \ + PIN_ODRVR_STRONGER(GPIOC_ARD_PC4) | \ + PIN_ODRVR_STRONGER(GPIOC_PIN5) | \ + PIN_ODRVR_STRONGER(GPIOC_PIN6) | \ + PIN_ODRVR_STRONGER(GPIOC_ARD_D9) | \ + PIN_ODRVR_STRONGER(GPIOC_PIN8) | \ + PIN_ODRVR_STRONGER(GPIOC_PIN9) | \ + PIN_ODRVR_STRONGER(GPIOC_PIN10) | \ + PIN_ODRVR_STRONGER(GPIOC_PIN11) | \ + PIN_ODRVR_STRONGER(GPIOC_PIN12) | \ + PIN_ODRVR_STRONGER(GPIOC_BUTTON) | \ + PIN_ODRVR_STRONGER(GPIOC_LEXT_IN) | \ + PIN_ODRVR_STRONGER(GPIOC_LEXT_OUT)) +#define VAL_GPIOC_PULL (PIN_PULL_PULLUP(GPIOC_ARD_A5) | \ + PIN_PULL_PULLUP(GPIOC_ARD_A4) | \ + PIN_PULL_PULLUP(GPIOC_ARD_MISO) | \ + PIN_PULL_PULLUP(GPIOC_ARD_MOSI) | \ + PIN_PULL_PULLUP(GPIOC_ARD_PC4) | \ + PIN_PULL_PULLUP(GPIOC_PIN5) | \ + PIN_PULL_PULLUP(GPIOC_PIN6) | \ + PIN_PULL_PULLUP(GPIOC_ARD_D9) | \ + PIN_PULL_PULLUP(GPIOC_PIN8) | \ + PIN_PULL_PULLUP(GPIOC_PIN9) | \ + PIN_PULL_PULLUP(GPIOC_PIN10) | \ + PIN_PULL_PULLUP(GPIOC_PIN11) | \ + PIN_PULL_PULLUP(GPIOC_PIN12) | \ + PIN_PULL_FLOATING(GPIOC_BUTTON) | \ + PIN_PULL_FLOATING(GPIOC_LEXT_IN) | \ + PIN_PULL_FLOATING(GPIOC_LEXT_OUT)) +#define VAL_GPIOC_ODT (PIN_ODT_HIGH(GPIOC_ARD_A5) | \ + PIN_ODT_HIGH(GPIOC_ARD_A4) | \ + PIN_ODT_HIGH(GPIOC_ARD_MISO) | \ + PIN_ODT_HIGH(GPIOC_ARD_MOSI) | \ + PIN_ODT_HIGH(GPIOC_ARD_PC4) | \ + PIN_ODT_HIGH(GPIOC_PIN5) | \ + PIN_ODT_HIGH(GPIOC_PIN6) | \ + PIN_ODT_HIGH(GPIOC_ARD_D9) | \ + PIN_ODT_HIGH(GPIOC_PIN8) | \ + PIN_ODT_HIGH(GPIOC_PIN9) | \ + PIN_ODT_HIGH(GPIOC_PIN10) | \ + PIN_ODT_HIGH(GPIOC_PIN11) | \ + PIN_ODT_HIGH(GPIOC_PIN12) | \ + PIN_ODT_HIGH(GPIOC_BUTTON) | \ + PIN_ODT_HIGH(GPIOC_LEXT_IN) | \ + PIN_ODT_HIGH(GPIOC_LEXT_OUT)) +#define VAL_GPIOC_MUXL (PIN_IOMUX_MUX(GPIOC_ARD_A5, 0U) | \ + PIN_IOMUX_MUX(GPIOC_ARD_A4, 0U) | \ + PIN_IOMUX_MUX(GPIOC_ARD_MISO, 0U) | \ + PIN_IOMUX_MUX(GPIOC_ARD_MOSI, 0U) | \ + PIN_IOMUX_MUX(GPIOC_ARD_PC4, 0U) | \ + PIN_IOMUX_MUX(GPIOC_PIN5, 0U) | \ + PIN_IOMUX_MUX(GPIOC_PIN6, 0U) | \ + PIN_IOMUX_MUX(GPIOC_ARD_D9, 0U)) +#define VAL_GPIOC_MUXH (PIN_IOMUX_MUX(GPIOC_PIN8, 0U) | \ + PIN_IOMUX_MUX(GPIOC_PIN9, 0U) | \ + PIN_IOMUX_MUX(GPIOC_PIN10, 0U) | \ + PIN_IOMUX_MUX(GPIOC_PIN11, 0U) | \ + PIN_IOMUX_MUX(GPIOC_PIN12, 0U) | \ + PIN_IOMUX_MUX(GPIOC_BUTTON, 0U) | \ + PIN_IOMUX_MUX(GPIOC_LEXT_IN, 0U) | \ + PIN_IOMUX_MUX(GPIOC_LEXT_OUT, 0U)) +#define VAL_GPIOC_HDRV (PIN_HDRV_DISABLED(GPIOC_ARD_A5) | \ + PIN_HDRV_DISABLED(GPIOC_ARD_A4) | \ + PIN_HDRV_DISABLED(GPIOC_ARD_MISO) | \ + PIN_HDRV_DISABLED(GPIOC_ARD_MOSI) | \ + PIN_HDRV_DISABLED(GPIOC_ARD_PC4) | \ + PIN_HDRV_DISABLED(GPIOC_PIN5) | \ + PIN_HDRV_DISABLED(GPIOC_PIN6) | \ + PIN_HDRV_DISABLED(GPIOC_ARD_D9) | \ + PIN_HDRV_DISABLED(GPIOC_PIN8) | \ + PIN_HDRV_DISABLED(GPIOC_PIN9) | \ + PIN_HDRV_DISABLED(GPIOC_PIN10) | \ + PIN_HDRV_DISABLED(GPIOC_PIN11) | \ + PIN_HDRV_DISABLED(GPIOC_PIN12) | \ + PIN_HDRV_DISABLED(GPIOC_BUTTON) | \ + PIN_HDRV_DISABLED(GPIOC_LEXT_IN) | \ + PIN_HDRV_DISABLED(GPIOC_LEXT_OUT)) /* - * GPIOD setup: - * PD2 - PIN2 (input none pull). + * Port D setup. + * + * PD2 - PIN2 (input pullup). */ -#define VAL_GPIOD_MODE (PIN_MODE_INPUT(GPIOD_PIN2)) -#define VAL_GPIOD_ODT (PIN_ODT_HIGH(GPIOD_PIN2)) -#define VAL_GPIOD_OUTPUT (PIN_OUTPUT_PUSHPULL(GPIOD_PIN2)) +#define VAL_GPIOD_CFGR (PIN_MODE_INPUT(GPIOD_PIN2)) +#define VAL_GPIOD_OMODE (PIN_OMODE_PUSHPULL(GPIOD_PIN2)) #define VAL_GPIOD_ODRVR (PIN_ODRVR_STRONGER(GPIOD_PIN2)) -#define VAL_GPIOD_PULL (PIN_PULL_NONE(GPIOD_PIN2)) -#define VAL_GPIOD_MUXL (PIN_MUX(GPIOD_PIN2, 0U)) +#define VAL_GPIOD_PULL (PIN_PULL_PULLUP(GPIOD_PIN2)) +#define VAL_GPIOD_ODT (PIN_ODT_HIGH(GPIOD_PIN2)) +#define VAL_GPIOD_MUXL (PIN_IOMUX_MUX(GPIOD_PIN2, 0U)) #define VAL_GPIOD_MUXH 0U -#define VAL_GPIOD_HDRV (PIN_HDRV_NOTACTIVE(GPIOD_PIN2)) +#define VAL_GPIOD_HDRV (PIN_HDRV_DISABLED(GPIOD_PIN2)) /* - * GPIOF setup: + * Port F setup. * - * PF0 - PIN0 (input none pull). - * PF1 - PIN1 (input none pull). - * PF4 - PIN4 (output none pull). - * PF5 - PIN5 (output none pull). - * PF6 - PIN6 (output none pull). - * PF7 - PIN7 (input none pull). - * PF11 - PIN11 (input none pull). + * PF0 - HEXT_IN (input floating). + * PF1 - HEXT_OUT (input floating). + * PF4 - LED_RED (output pushpull). + * PF5 - LED_YELLOW (output pushpull). + * PF6 - LED_GREEN (output pushpull). + * PF7 - PIN7 (input pullup). + * PF11 - PIN11 (input pullup). */ -#define VAL_GPIOF_MODE (PIN_MODE_INPUT(GPIOF_HEXT_IN) | \ - PIN_MODE_INPUT(GPIOF_HEXT_OUT) | \ - PIN_MODE_OUTPUT(GPIOF_PIN4) | \ - PIN_MODE_OUTPUT(GPIOF_PIN5) | \ - PIN_MODE_OUTPUT(GPIOF_PIN6) | \ - PIN_MODE_INPUT(GPIOF_PIN7) | \ - PIN_MODE_INPUT(GPIOF_PIN11)) - -#define VAL_GPIOF_ODT (PIN_ODT_HIGH(GPIOF_HEXT_IN) | \ - PIN_ODT_HIGH(GPIOF_HEXT_OUT) | \ - PIN_ODT_HIGH(GPIOF_PIN4) | \ - PIN_ODT_HIGH(GPIOF_PIN5) | \ - PIN_ODT_HIGH(GPIOF_PIN6) | \ - PIN_ODT_HIGH(GPIOF_PIN7) | \ - PIN_ODT_HIGH(GPIOF_PIN11)) - - -#define VAL_GPIOF_OUTPUT (PIN_OUTPUT_PUSHPULL(GPIOF_HEXT_IN) | \ - PIN_OUTPUT_PUSHPULL(GPIOF_HEXT_OUT) | \ - PIN_OUTPUT_PUSHPULL(GPIOF_PIN4) | \ - PIN_OUTPUT_PUSHPULL(GPIOF_PIN5) | \ - PIN_OUTPUT_PUSHPULL(GPIOF_PIN6) | \ - PIN_OUTPUT_PUSHPULL(GPIOF_PIN7) | \ - PIN_OUTPUT_PUSHPULL(GPIOF_PIN11)) - - -#define VAL_GPIOF_ODRVR (PIN_ODRVR_STRONGER(GPIOF_HEXT_IN) | \ - PIN_ODRVR_STRONGER(GPIOF_HEXT_OUT) | \ - PIN_ODRVR_STRONGER(GPIOF_PIN4) | \ - PIN_ODRVR_STRONGER(GPIOF_PIN5) | \ - PIN_ODRVR_STRONGER(GPIOF_PIN6) | \ - PIN_ODRVR_STRONGER(GPIOF_PIN7) | \ +#define VAL_GPIOF_CFGR (PIN_MODE_INPUT(GPIOF_HEXT_IN) | \ + PIN_MODE_INPUT(GPIOF_HEXT_OUT) | \ + PIN_MODE_OUTPUT(GPIOF_LED_RED) | \ + PIN_MODE_OUTPUT(GPIOF_LED_YELLOW) | \ + PIN_MODE_OUTPUT(GPIOF_LED_GREEN) | \ + PIN_MODE_INPUT(GPIOF_PIN7) | \ + PIN_MODE_INPUT(GPIOF_PIN11)) +#define VAL_GPIOF_OMODE (PIN_OMODE_PUSHPULL(GPIOF_HEXT_IN) | \ + PIN_OMODE_PUSHPULL(GPIOF_HEXT_OUT) | \ + PIN_OMODE_PUSHPULL(GPIOF_LED_RED) | \ + PIN_OMODE_PUSHPULL(GPIOF_LED_YELLOW) | \ + PIN_OMODE_PUSHPULL(GPIOF_LED_GREEN) | \ + PIN_OMODE_PUSHPULL(GPIOF_PIN7) | \ + PIN_OMODE_PUSHPULL(GPIOF_PIN11)) +#define VAL_GPIOF_ODRVR (PIN_ODRVR_STRONGER(GPIOF_HEXT_IN) | \ + PIN_ODRVR_STRONGER(GPIOF_HEXT_OUT) | \ + PIN_ODRVR_STRONGER(GPIOF_LED_RED) | \ + PIN_ODRVR_STRONGER(GPIOF_LED_YELLOW) | \ + PIN_ODRVR_STRONGER(GPIOF_LED_GREEN) | \ + PIN_ODRVR_STRONGER(GPIOF_PIN7) | \ PIN_ODRVR_STRONGER(GPIOF_PIN11)) - -#define VAL_GPIOF_PULL (PIN_PULL_NONE(GPIOF_HEXT_IN) | \ - PIN_PULL_NONE(GPIOF_HEXT_OUT) | \ - PIN_PULL_NONE(GPIOF_PIN4) | \ - PIN_PULL_NONE(GPIOF_PIN5) | \ - PIN_PULL_NONE(GPIOF_PIN6) | \ - PIN_PULL_NONE(GPIOF_PIN7) | \ - PIN_PULL_NONE(GPIOF_PIN11)) - -#define VAL_GPIOF_MUXL (PIN_MUX(GPIOF_HEXT_IN, 0U) | \ - PIN_MUX(GPIOF_HEXT_OUT, 0U) | \ - PIN_MUX(GPIOF_PIN4, 0U) | \ - PIN_MUX(GPIOF_PIN5, 0U) | \ - PIN_MUX(GPIOF_PIN6, 0U) | \ - PIN_MUX(GPIOF_PIN7, 0U) | \ - PIN_MUX(GPIOF_PIN11, 0U)) -#define VAL_GPIOF_MUXH 0U - -#define VAL_GPIOF_HDRV (PIN_HDRV_NOTACTIVE(GPIOF_HEXT_IN) | \ - PIN_HDRV_NOTACTIVE(GPIOF_HEXT_OUT) | \ - PIN_HDRV_NOTACTIVE(GPIOF_PIN4) | \ - PIN_HDRV_NOTACTIVE(GPIOF_PIN5) | \ - PIN_HDRV_NOTACTIVE(GPIOF_PIN6) | \ - PIN_HDRV_NOTACTIVE(GPIOF_PIN7) | \ - PIN_HDRV_NOTACTIVE(GPIOF_PIN11)) +#define VAL_GPIOF_PULL (PIN_PULL_FLOATING(GPIOF_HEXT_IN) | \ + PIN_PULL_FLOATING(GPIOF_HEXT_OUT) | \ + PIN_PULL_FLOATING(GPIOF_LED_RED) | \ + PIN_PULL_FLOATING(GPIOF_LED_YELLOW) | \ + PIN_PULL_FLOATING(GPIOF_LED_GREEN) | \ + PIN_PULL_PULLUP(GPIOF_PIN7) | \ + PIN_PULL_PULLUP(GPIOF_PIN11)) +#define VAL_GPIOF_ODT (PIN_ODT_HIGH(GPIOF_HEXT_IN) | \ + PIN_ODT_HIGH(GPIOF_HEXT_OUT) | \ + PIN_ODT_HIGH(GPIOF_LED_RED) | \ + PIN_ODT_HIGH(GPIOF_LED_YELLOW) | \ + PIN_ODT_HIGH(GPIOF_LED_GREEN) | \ + PIN_ODT_HIGH(GPIOF_PIN7) | \ + PIN_ODT_HIGH(GPIOF_PIN11)) +#define VAL_GPIOF_MUXL (PIN_IOMUX_MUX(GPIOF_HEXT_IN, 0U) | \ + PIN_IOMUX_MUX(GPIOF_HEXT_OUT, 0U) | \ + PIN_IOMUX_MUX(GPIOF_LED_RED, 0U) | \ + PIN_IOMUX_MUX(GPIOF_LED_YELLOW, 0U) | \ + PIN_IOMUX_MUX(GPIOF_LED_GREEN, 0U) | \ + PIN_IOMUX_MUX(GPIOF_PIN7, 0U)) +#define VAL_GPIOF_MUXH (PIN_IOMUX_MUX(GPIOF_PIN11, 0U)) +#define VAL_GPIOF_HDRV (PIN_HDRV_DISABLED(GPIOF_HEXT_IN) | \ + PIN_HDRV_DISABLED(GPIOF_HEXT_OUT) | \ + PIN_HDRV_DISABLED(GPIOF_LED_RED) | \ + PIN_HDRV_DISABLED(GPIOF_LED_YELLOW) | \ + PIN_HDRV_DISABLED(GPIOF_LED_GREEN) | \ + PIN_HDRV_DISABLED(GPIOF_PIN7) | \ + PIN_HDRV_DISABLED(GPIOF_PIN11)) /*===========================================================================*/ /* External declarations. */ diff --git a/os/hal/boards/AT_START_F415/board.c b/os/hal/boards/AT_START_F415/board.c index 8d8e33825d..bd4ec0b998 100644 --- a/os/hal/boards/AT_START_F415/board.c +++ b/os/hal/boards/AT_START_F415/board.c @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/boards/AT_START_F415/board.h b/os/hal/boards/AT_START_F415/board.h index dc5739838e..8cf613893a 100644 --- a/os/hal/boards/AT_START_F415/board.h +++ b/os/hal/boards/AT_START_F415/board.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/AT32F405xx/at32_crm.h b/os/hal/ports/AT32/AT32F402_405/at32_crm.h similarity index 84% rename from os/hal/ports/AT32/AT32F405xx/at32_crm.h rename to os/hal/ports/AT32/AT32F402_405/at32_crm.h index fb5a4274cc..fc0763dc29 100644 --- a/os/hal/ports/AT32/AT32F405xx/at32_crm.h +++ b/os/hal/ports/AT32/AT32F402_405/at32_crm.h @@ -1,6 +1,8 @@ /* - ChibiOS - Copyright (C) 2023..2024 Zhaqian - ChibiOS - Copyright (C) 2024 Maxjta + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + ChibiOS - Copyright (C) 2024..2025 Maxjta Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -16,12 +18,12 @@ */ /** - * @file AT32F405xx/at32_crm.h + * @file AT32F402_405/at32_crm.h * @brief CRM helper driver header. * @note This file requires definitions from the AT header file - * @p at32f402_405xx.h. + * @p at32f402_405.h. * - * @addtogroup AT32F405xx_CRM + * @addtogroup AT32F402_405_CRM * @{ */ @@ -33,7 +35,7 @@ /*===========================================================================*/ /*===========================================================================*/ -/* Driver pre-compile TMRe settings. */ +/* Driver pre-compile time settings. */ /*===========================================================================*/ /*===========================================================================*/ @@ -54,34 +56,32 @@ */ /** * @brief Enables the clock of one or more peripheral on the APB1 bus. - * @note The @p lp parameter is ignored in this family. * * @param[in] mask APB1 peripherals mask * @param[in] lp low power enable flag * * @api */ -#define crmEnableAPB1(mask, lp) { \ - CRM->APB1EN |= (mask); \ - if (lp) \ - CRM->APB1LPEN |= (mask); \ - else \ - CRM->APB1LPEN &= ~(mask); \ - (void)CRM->APB1LPEN; \ +#define crmEnableAPB1(mask, lp) { \ + CRM->APB1EN |= (mask); \ + if (lp) \ + CRM->APB1LPEN |= (mask); \ + else \ + CRM->APB1LPEN &= ~(mask); \ + (void)CRM->APB1LPEN; \ } /** * @brief Disables the clock of one or more peripheral on the APB1 bus. - * @note The @p lp parameter is ignored in this family. * * @param[in] mask APB1 peripherals mask * * @api */ -#define crmDisableAPB1(mask) { \ - CRM->APB1EN &= ~(mask); \ - CRM->APB1LPEN &= ~(mask); \ - (void)CRM->APB1LPEN; \ +#define crmDisableAPB1(mask) { \ + CRM->APB1EN &= ~(mask); \ + CRM->APB1LPEN &= ~(mask); \ + (void)CRM->APB1LPEN; \ } /** @@ -91,42 +91,40 @@ * * @api */ -#define crmResetAPB1(mask) { \ - CRM->APB1RST |= (mask); \ - CRM->APB1RST &= ~(mask); \ - (void)CRM->APB1RST; \ +#define crmResetAPB1(mask) { \ + CRM->APB1RST |= (mask); \ + CRM->APB1RST &= ~(mask); \ + (void)CRM->APB1RST; \ } /** * @brief Enables the clock of one or more peripheral on the APB2 bus. - * @note The @p lp parameter is ignored in this family. * * @param[in] mask APB2 peripherals mask * @param[in] lp low power enable flag * * @api */ -#define crmEnableAPB2(mask, lp) { \ - CRM->APB2EN |= (mask); \ - if (lp) \ - CRM->APB2LPEN |= (mask); \ - else \ - CRM->APB2LPEN &= ~(mask); \ - (void)CRM->APB2LPEN; \ +#define crmEnableAPB2(mask, lp) { \ + CRM->APB2EN |= (mask); \ + if (lp) \ + CRM->APB2LPEN |= (mask); \ + else \ + CRM->APB2LPEN &= ~(mask); \ + (void)CRM->APB2LPEN; \ } /** * @brief Disables the clock of one or more peripheral on the APB2 bus. - * @note The @p lp parameter is ignored in this family. * * @param[in] mask APB2 peripherals mask * * @api */ -#define crmDisableAPB2(mask) { \ - CRM->APB2EN &= ~(mask); \ - CRM->APB2LPEN &= ~(mask); \ - (void)CRM->APB2LPEN; \ +#define crmDisableAPB2(mask) { \ + CRM->APB2EN &= ~(mask); \ + CRM->APB2LPEN &= ~(mask); \ + (void)CRM->APB2LPEN; \ } /** @@ -136,10 +134,10 @@ * * @api */ -#define crmResetAPB2(mask) { \ - CRM->APB2RST |= (mask); \ - CRM->APB2RST &= ~(mask); \ - (void)CRM->APB2RST; \ +#define crmResetAPB2(mask) { \ + CRM->APB2RST |= (mask); \ + CRM->APB2RST &= ~(mask); \ + (void)CRM->APB2RST; \ } /** @@ -150,13 +148,13 @@ * * @api */ -#define crmEnableAHB1(mask, lp) { \ - CRM->AHBEN1 |= (mask); \ - if (lp) \ - CRM->AHBLPEN1 |= (mask); \ - else \ - CRM->AHBLPEN1 &= ~(mask); \ - (void)CRM->AHBLPEN1; \ +#define crmEnableAHB1(mask, lp) { \ + CRM->AHBEN1 |= (mask); \ + if (lp) \ + CRM->AHBLPEN1 |= (mask); \ + else \ + CRM->AHBLPEN1 &= ~(mask); \ + (void)CRM->AHBLPEN1; \ } /** @@ -166,10 +164,10 @@ * * @api */ -#define crmDisableAHB1(mask) { \ - CRM->AHBEN1 &= ~(mask); \ - CRM->AHBLPEN1 &= ~(mask); \ - (void)CRM->AHBLPEN1; \ +#define crmDisableAHB1(mask) { \ + CRM->AHBEN1 &= ~(mask); \ + CRM->AHBLPEN1 &= ~(mask); \ + (void)CRM->AHBLPEN1; \ } /** @@ -179,10 +177,10 @@ * * @api */ -#define crmResetAHB1(mask) { \ - CRM->AHBRST1 |= (mask); \ - CRM->AHBRST1 &= ~(mask); \ - (void)CRM->AHBRST1; \ +#define crmResetAHB1(mask) { \ + CRM->AHBRST1 |= (mask); \ + CRM->AHBRST1 &= ~(mask); \ + (void)CRM->AHBRST1; \ } /** @@ -193,13 +191,13 @@ * * @api */ -#define crmEnableAHB2(mask, lp) { \ - CRM->AHBEN2 |= (mask); \ - if (lp) \ - CRM->AHBLPEN2 |= (mask); \ - else \ - CRM->AHBLPEN2 &= ~(mask); \ - (void)CRM->AHBLPEN2; \ +#define crmEnableAHB2(mask, lp) { \ + CRM->AHBEN2 |= (mask); \ + if (lp) \ + CRM->AHBLPEN2 |= (mask); \ + else \ + CRM->AHBLPEN2 &= ~(mask); \ + (void)CRM->AHBLPEN2; \ } /** @@ -209,10 +207,10 @@ * * @api */ -#define crmDisableAHB2(mask) { \ - CRM->AHBEN2 &= ~(mask); \ - CRM->AHBLPEN2 &= ~(mask); \ - (void)CRM->AHBLPEN2; \ +#define crmDisableAHB2(mask) { \ + CRM->AHBEN2 &= ~(mask); \ + CRM->AHBLPEN2 &= ~(mask); \ + (void)CRM->AHBLPEN2; \ } /** @@ -222,53 +220,53 @@ * * @api */ -#define crmResetAHB2(mask) { \ - CRM->AHBRST2 |= (mask); \ - CRM->AHBRST2 &= ~(mask); \ - (void)CRM->AHBRST2; \ +#define crmResetAHB2(mask) { \ + CRM->AHBRST2 |= (mask); \ + CRM->AHBRST2 &= ~(mask); \ + (void)CRM->AHBRST2; \ } /** - * @brief Enables the clock of one or more peripheral on the AHB3 (FSMC) bus. + * @brief Enables the clock of one or more peripheral on the AHB3 bus. * * @param[in] mask AHB3 peripherals mask * @param[in] lp low power enable flag * * @api */ -#define crmEnableAHB3(mask, lp) { \ - CRM->AHBEN3 |= (mask); \ - if (lp) \ - CRM->AHBLPEN3 |= (mask); \ - else \ - CRM->AHBLPEN3 &= ~(mask); \ - (void)CRM->AHBLPEN3; \ +#define crmEnableAHB3(mask, lp) { \ + CRM->AHBEN3 |= (mask); \ + if (lp) \ + CRM->AHBLPEN3 |= (mask); \ + else \ + CRM->AHBLPEN3 &= ~(mask); \ + (void)CRM->AHBLPEN3; \ } /** - * @brief Disables the clock of one or more peripheral on the AHB3 (FSMC) bus. + * @brief Disables the clock of one or more peripheral on the AHB3 bus. * * @param[in] mask AHB3 peripherals mask * * @api */ -#define crmDisableAHB3(mask) { \ - CRM->AHBEN3 &= ~(mask); \ - CRM->AHBLPEN3 &= ~(mask); \ - (void)CRM->AHBLPEN3; \ +#define crmDisableAHB3(mask) { \ + CRM->AHBEN3 &= ~(mask); \ + CRM->AHBLPEN3 &= ~(mask); \ + (void)CRM->AHBLPEN3; \ } /** - * @brief Resets one or more peripheral on the AHB3 (FSMC) bus. + * @brief Resets one or more peripheral on the AHB3 bus. * * @param[in] mask AHB3 peripherals mask * * @api */ -#define crmResetAHB3(mask) { \ - CRM->AHBRST3 |= (mask); \ - CRM->AHBRST3 &= ~(mask); \ - (void)CRM->AHBRST3; \ +#define crmResetAHB3(mask) { \ + CRM->AHBRST3 |= (mask); \ + CRM->AHBRST3 &= ~(mask); \ + (void)CRM->AHBRST3; \ } /** @} */ @@ -276,9 +274,15 @@ * @name ADC peripherals specific CRM operations * @{ */ +/** + * @brief Resets ADC peripherals. + * + * @api + */ +#define crmResetADC() crmResetAPB2(CRM_APB2RST_ADCRST) + /** * @brief Enables the ADC1 peripheral clock. - * @note The @p lp parameter is ignored in this family. * * @param[in] lp low power enable flag * @@ -292,13 +296,6 @@ * @api */ #define crmDisableADC1() crmDisableAPB2(CRM_APB2EN_ADC1EN) - -/** - * @brief Resets the ADC1 peripheral. - * - * @api - */ -#define crmResetADC1() crmResetAPB2(CRM_APB2RST_ADC1RST) /** @} */ /** @@ -307,7 +304,6 @@ */ /** * @brief Enables the PWC interface clock. - * @note The @p lp parameter is ignored in this family. * * @param[in] lp low power enable flag * @@ -336,7 +332,6 @@ */ /** * @brief Enables the CAN1 peripheral clock. - * @note The @p lp parameter is ignored in this family. * * @param[in] lp low power enable flag * @@ -357,6 +352,7 @@ * @api */ #define crmResetCAN1() crmResetAPB1(CRM_APB1RST_CAN1RST) +/** @} */ /** * @name DMA peripherals specific CRM operations @@ -364,7 +360,6 @@ */ /** * @brief Enables the DMA1 peripheral clock. - * @note The @p lp parameter is ignored in this family. * * @param[in] lp low power enable flag * @@ -381,7 +376,6 @@ /** * @brief Resets the DMA1 peripheral. - * @note Not supported in this family, does nothing. * * @api */ @@ -389,7 +383,6 @@ /** * @brief Enables the DMA2 peripheral clock. - * @note The @p lp parameter is ignored in this family. * * @param[in] lp low power enable flag * @@ -406,7 +399,6 @@ /** * @brief Resets the DMA2 peripheral. - * @note Not supported in this family, does nothing. * * @api */ @@ -419,7 +411,6 @@ */ /** * @brief Enables the I2C1 peripheral clock. - * @note The @p lp parameter is ignored in this family. * * @param[in] lp low power enable flag * @@ -443,7 +434,6 @@ /** * @brief Enables the I2C2 peripheral clock. - * @note The @p lp parameter is ignored in this family. * * @param[in] lp low power enable flag * @@ -467,7 +457,6 @@ /** * @brief Enables the I2C3 peripheral clock. - * @note The @p lp parameter is ignored in this family. * * @param[in] lp low power enable flag * @@ -501,26 +490,24 @@ * * @api */ -#define crmEnableOTG_FS1(lp) crmEnableAHB2(CRM_AHBEN2_OTGFS1EN, lp) -#define crmEnableOTG_FS(lp) crmEnableOTG_FS1(lp) +#define crmEnableOTG_FS(lp) crmEnableAHB2(CRM_AHBEN2_OTGFSEN, lp) /** * @brief Disables the OTG_FS peripheral clock. * * @api */ -#define crmDisableOTG_FS1() crmDisableAHB2(CRM_AHBEN2_OTGFS1EN) -#define crmDisableOTG_FS() crmDisableOTG_FS1() +#define crmDisableOTG_FS() crmDisableAHB2(CRM_AHBEN2_OTGFSEN) /** * @brief Resets the OTG_FS peripheral. * * @api */ -#define crmResetOTG_FS1() crmResetAHB2(CRM_AHBRST2_OTGFS1RST) -#define crmResetOTG_FS() crmResetOTG_FS1() +#define crmResetOTG_FS() crmResetAHB2(CRM_AHBRST2_OTGFSRST) + /** - * @brief Enables the OTG_HS peripheral clock. + * @brief Enables the OTG_HS peripheral clock (F405 only). * * @param[in] lp low power enable flag * @@ -529,14 +516,14 @@ #define crmEnableOTG_HS(lp) crmEnableAHB1(CRM_AHBEN1_OTGHSEN, lp) /** - * @brief Disables the OTG_HS peripheral clock. + * @brief Disables the OTG_HS peripheral clock (F405 only). * * @api */ #define crmDisableOTG_HS() crmDisableAHB1(CRM_AHBEN1_OTGHSEN) /** - * @brief Resets the OTG_HS peripheral. + * @brief Resets the OTG_HS peripheral (F405 only). * * @api */ @@ -577,7 +564,6 @@ */ /** * @brief Enables the SPI1 peripheral clock. - * @note The @p lp parameter is ignored in this family. * * @param[in] lp low power enable flag * @@ -601,7 +587,6 @@ /** * @brief Enables the SPI2 peripheral clock. - * @note The @p lp parameter is ignored in this family. * * @param[in] lp low power enable flag * @@ -625,7 +610,6 @@ /** * @brief Enables the SPI3 peripheral clock. - * @note The @p lp parameter is ignored in this family. * * @param[in] lp low power enable flag * @@ -654,7 +638,6 @@ */ /** * @brief Enables the TMR1 peripheral clock. - * @note The @p lp parameter is ignored in this family. * * @param[in] lp low power enable flag * @@ -678,7 +661,6 @@ /** * @brief Enables the TMR2 peripheral clock. - * @note The @p lp parameter is ignored in this family. * * @param[in] lp low power enable flag * @@ -702,7 +684,6 @@ /** * @brief Enables the TMR3 peripheral clock. - * @note The @p lp parameter is ignored in this family. * * @param[in] lp low power enable flag * @@ -726,7 +707,6 @@ /** * @brief Enables the TMR4 peripheral clock. - * @note The @p lp parameter is ignored in this family. * * @param[in] lp low power enable flag * @@ -750,7 +730,6 @@ /** * @brief Enables the TMR6 peripheral clock. - * @note The @p lp parameter is ignored in this family. * * @param[in] lp low power enable flag * @@ -774,7 +753,6 @@ /** * @brief Enables the TMR7 peripheral clock. - * @note The @p lp parameter is ignored in this family. * * @param[in] lp low power enable flag * @@ -797,11 +775,7 @@ #define crmResetTMR7() crmResetAPB1(CRM_APB1RST_TMR7RST) /** - * @brief Enables the TMR9 peripheral clock. - - * @note The @p lp parameter is ignored in this family. - * * @param[in] lp low power enable flag * @@ -825,7 +799,6 @@ /** * @brief Enables the TMR10 peripheral clock. - * @note The @p lp parameter is ignored in this family. * * @param[in] lp low power enable flag * @@ -849,7 +822,6 @@ /** * @brief Enables the TMR11 peripheral clock. - * @note The @p lp parameter is ignored in this family. * * @param[in] lp low power enable flag * @@ -873,7 +845,6 @@ /** * @brief Enables the TMR13 peripheral clock. - * @note The @p lp parameter is ignored in this family. * * @param[in] lp low power enable flag * @@ -897,7 +868,6 @@ /** * @brief Enables the TMR14 peripheral clock. - * @note The @p lp parameter is ignored in this family. * * @param[in] lp low power enable flag * @@ -926,7 +896,6 @@ */ /** * @brief Enables the USART1 peripheral clock. - * @note The @p lp parameter is ignored in this family. * * @param[in] lp low power enable flag * @@ -950,7 +919,6 @@ /** * @brief Enables the USART2 peripheral clock. - * @note The @p lp parameter is ignored in this family. * * @param[in] lp low power enable flag * @@ -974,7 +942,6 @@ /** * @brief Enables the USART3 peripheral clock. - * @note The @p lp parameter is ignored in this family. * * @param[in] lp low power enable flag * @@ -995,11 +962,9 @@ * @api */ #define crmResetUSART3() crmResetAPB1(CRM_APB1RST_USART3RST) -/** @} */ /** * @brief Enables the UART4 peripheral clock. - * @note The @p lp parameter is ignored in this family. * * @param[in] lp low power enable flag * @@ -1023,7 +988,6 @@ /** * @brief Enables the UART5 peripheral clock. - * @note The @p lp parameter is ignored in this family. * * @param[in] lp low power enable flag * @@ -1047,7 +1011,6 @@ /** * @brief Enables the USART6 peripheral clock. - * @note The @p lp parameter is ignored in this family. * * @param[in] lp low power enable flag * @@ -1071,7 +1034,6 @@ /** * @brief Enables the UART7 peripheral clock. - * @note The @p lp parameter is ignored in this family. * * @param[in] lp low power enable flag * @@ -1095,7 +1057,6 @@ /** * @brief Enables the UART8 peripheral clock. - * @note The @p lp parameter is ignored in this family. * * @param[in] lp low power enable flag * @@ -1124,7 +1085,6 @@ */ /** * @brief Enables the ACC peripheral clock. - * @note The @p lp parameter is ignored in this family. * * @param[in] lp low power enable flag * @@ -1148,32 +1108,31 @@ /** @} */ /** - * @name SCFG peripherals specific CRM operations + * @name CRC peripherals specific CRM operations * @{ */ /** - * @brief Enables the SCFG peripheral clock. - * @note The @p lp parameter is ignored in this family. + * @brief Enables the CRC peripheral clock. * * @param[in] lp low power enable flag * * @api */ -#define crmEnableSCFG(lp) crmEnableAPB2(CRM_APB2EN_SCFGEN, lp) +#define crmEnableCRC(lp) crmEnableAHB1(CRM_AHBEN1_CRCEN, lp) /** - * @brief Disables the SCFG peripheral clock. + * @brief Disables the CRC peripheral clock. * * @api */ -#define crmDisableSCFG() crmDisableAPB2(CRM_APB2EN_SCFGEN) +#define crmDisableCRC() crmDisableAHB1(CRM_AHBEN1_CRCEN) /** - * @brief Resets the SCFG peripheral. + * @brief Resets the CRC peripheral. * * @api */ -#define crmResetSCFG() crmResetAPB2(CRM_APB2RST_SCFGRST) +#define crmResetCRC() crmResetAHB1(CRM_AHBRST1_CRCRST) /** @} */ /*===========================================================================*/ diff --git a/os/hal/ports/AT32/AT32F405xx/at32_dmamux.h b/os/hal/ports/AT32/AT32F402_405/at32_dmamux.h similarity index 92% rename from os/hal/ports/AT32/AT32F405xx/at32_dmamux.h rename to os/hal/ports/AT32/AT32F402_405/at32_dmamux.h index d6d4e4847f..ce133cd47b 100644 --- a/os/hal/ports/AT32/AT32F405xx/at32_dmamux.h +++ b/os/hal/ports/AT32/AT32F402_405/at32_dmamux.h @@ -1,6 +1,8 @@ /* - ChibiOS - Copyright (C) 2023..2024 Zhaqian - ChibiOS - Copyright (C) 2024 Maxjta + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + ChibiOS - Copyright (C) 2024..2025 Maxjta Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -16,10 +18,10 @@ */ /** - * @file AT32F405xx/at32_dmamux.h - * @brief AT32F405xx DMAMUX handler header. + * @file AT32F402_405/at32_dmamux.h + * @brief AT32F402_405 DMAMUX handler header. * - * @addtogroup AT32F405xx_DMAMUX + * @addtogroup AT32F402_405_DMAMUX * @{ */ @@ -35,10 +37,12 @@ * @{ */ #define AT32_DMAMUX_MUXREQG1 1 -#define AT32_DMAMUX_MUXREQG2 2 +#define AT32_DMAMUX_MUXREQG2 2 #define AT32_DMAMUX_MUXREQG3 3 #define AT32_DMAMUX_MUXREQG4 4 #define AT32_DMAMUX_ADC1 5 +#define AT32_DMAMUX_TMR6_OVERFLOW 8 +#define AT32_DMAMUX_TMR7_OVERFLOW 9 #define AT32_DMAMUX_SPI1_RX 10 #define AT32_DMAMUX_SPI1_TX 11 #define AT32_DMAMUX_SPI2_RX 12 diff --git a/os/hal/ports/AT32/AT32F405xx/at32_isr.c b/os/hal/ports/AT32/AT32F402_405/at32_isr.c similarity index 89% rename from os/hal/ports/AT32/AT32F405xx/at32_isr.c rename to os/hal/ports/AT32/AT32F402_405/at32_isr.c index 0678e5685d..1ffafa7103 100644 --- a/os/hal/ports/AT32/AT32F405xx/at32_isr.c +++ b/os/hal/ports/AT32/AT32F402_405/at32_isr.c @@ -1,6 +1,8 @@ /* - ChibiOS - Copyright (C) 2023..2024 Zhaqian - ChibiOS - Copyright (C) 2024 Maxjta + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + ChibiOS - Copyright (C) 2024..2025 Maxjta Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -16,10 +18,10 @@ */ /** - * @file AT32F405xx/at32_isr.c - * @brief AT32F405xx ISR handler code. + * @file AT32F402_405/at32_isr.c + * @brief AT32F402_405 ISR handler code. * - * @addtogroup AT32F405xx_ISR + * @addtogroup AT32F402_405_ISR * @{ */ @@ -41,9 +43,9 @@ /* Driver local functions. */ /*===========================================================================*/ -#define exint_serve_irq(intsts, channel) { \ +#define exint_serve_irq(intsts, channel) { \ \ - if ((intsts) & (1U << (channel))) { \ + if ((intsts) & (1U << (channel))) { \ _pal_isr_code(channel); \ } \ } @@ -51,6 +53,7 @@ /*===========================================================================*/ /* Driver interrupt handlers. */ /*===========================================================================*/ + #include "at32_exint0.inc" #include "at32_exint1.inc" #include "at32_exint2.inc" @@ -61,8 +64,7 @@ #include "at32_exint16.inc" #include "at32_exint17.inc" #include "at32_exint18.inc" -#include "at32_exint19.inc" -#include "at32_exint20.inc" +#include "at32_exint20.inc" /* Note: F405 only */ #include "at32_exint21.inc" #include "at32_exint22.inc" @@ -105,8 +107,7 @@ void irqInit(void) { exint16_irq_init(); exint17_irq_init(); exint18_irq_init(); - exint19_irq_init(); - exint20_irq_init(); + exint20_irq_init(); /* Note: F405 only */ exint21_irq_init(); exint22_irq_init(); @@ -146,8 +147,7 @@ void irqDeinit(void) { exint16_irq_deinit(); exint17_irq_deinit(); exint18_irq_deinit(); - exint19_irq_deinit(); - exint20_irq_deinit(); + exint20_irq_deinit(); /* Note: F405 only */ exint21_irq_deinit(); exint22_irq_deinit(); diff --git a/os/hal/ports/AT32/AT32F402_405/at32_isr.h b/os/hal/ports/AT32/AT32F402_405/at32_isr.h new file mode 100644 index 0000000000..b33eba07ca --- /dev/null +++ b/os/hal/ports/AT32/AT32F402_405/at32_isr.h @@ -0,0 +1,301 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + ChibiOS - Copyright (C) 2024..2025 Maxjta + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file AT32F402_405/at32_isr.h + * @brief AT32F402_405 ISR handler header. + * + * @addtogroup AT32F402_405_ISR + * @{ + */ + +#ifndef AT32_ISR_H +#define AT32_ISR_H + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name ISRs suppressed in standard drivers + * @{ + */ +#define AT32_TMR1_SUPPRESS_ISR +#define AT32_TMR2_SUPPRESS_ISR +#define AT32_TMR3_SUPPRESS_ISR +#define AT32_TMR4_SUPPRESS_ISR +#define AT32_TMR6_SUPPRESS_ISR +#define AT32_TMR7_SUPPRESS_ISR +#define AT32_TMR9_SUPPRESS_ISR +#define AT32_TMR10_SUPPRESS_ISR +#define AT32_TMR11_SUPPRESS_ISR +#define AT32_TMR13_SUPPRESS_ISR +#define AT32_TMR14_SUPPRESS_ISR + +#define AT32_USART1_SUPPRESS_ISR +#define AT32_USART2_SUPPRESS_ISR +#define AT32_USART3_SUPPRESS_ISR +#define AT32_UART4_SUPPRESS_ISR +#define AT32_UART5_SUPPRESS_ISR +#define AT32_USART6_SUPPRESS_ISR +#define AT32_UART7_SUPPRESS_ISR +#define AT32_UART8_SUPPRESS_ISR +/** @} */ + +/** + * @name ISR names and numbers + * @{ + */ +/* + * ADC unit. + */ +#define AT32_ADC_HANDLER Vector88 + +#define AT32_ADC_NUMBER 18 + +/* + * CAN unit. + */ +#define AT32_CAN1_TX_HANDLER Vector8C +#define AT32_CAN1_RX0_HANDLER Vector90 +#define AT32_CAN1_RX1_HANDLER Vector94 +#define AT32_CAN1_SE_HANDLER Vector98 + +#define AT32_CAN1_TX_NUMBER 19 +#define AT32_CAN1_RX0_NUMBER 20 +#define AT32_CAN1_RX1_NUMBER 21 +#define AT32_CAN1_SE_NUMBER 22 + +/* + * DMA units. + */ +#define AT32_DMA1_CH1_HANDLER Vector6C +#define AT32_DMA1_CH2_HANDLER Vector70 +#define AT32_DMA1_CH3_HANDLER Vector74 +#define AT32_DMA1_CH4_HANDLER Vector78 +#define AT32_DMA1_CH5_HANDLER Vector7C +#define AT32_DMA1_CH6_HANDLER Vector80 +#define AT32_DMA1_CH7_HANDLER Vector84 + +#define AT32_DMA1_CH1_NUMBER 11 +#define AT32_DMA1_CH2_NUMBER 12 +#define AT32_DMA1_CH3_NUMBER 13 +#define AT32_DMA1_CH4_NUMBER 14 +#define AT32_DMA1_CH5_NUMBER 15 +#define AT32_DMA1_CH6_NUMBER 16 +#define AT32_DMA1_CH7_NUMBER 17 + +#define AT32_DMA2_CH1_HANDLER Vector120 +#define AT32_DMA2_CH2_HANDLER Vector124 +#define AT32_DMA2_CH3_HANDLER Vector128 +#define AT32_DMA2_CH4_HANDLER Vector12C +#define AT32_DMA2_CH5_HANDLER Vector130 +#define AT32_DMA2_CH6_HANDLER Vector150 +#define AT32_DMA2_CH7_HANDLER Vector154 + +#define AT32_DMA2_CH1_NUMBER 56 +#define AT32_DMA2_CH2_NUMBER 57 +#define AT32_DMA2_CH3_NUMBER 58 +#define AT32_DMA2_CH4_NUMBER 59 +#define AT32_DMA2_CH5_NUMBER 60 +#define AT32_DMA2_CH6_NUMBER 68 +#define AT32_DMA2_CH7_NUMBER 69 + +#define AT32_DMAMUX_HANDLER Vector1B8 + +#define AT32_DMAMUX_NUMBER 94 + +/* + * ERTC unit. + */ +#define AT32_ERTC_TAMP_STAMP_HANDLER Vector48 +#define AT32_ERTC_WKUP_HANDLER Vector4C +#define AT32_ERTC_ALARM_HANDLER VectorE4 + +#define AT32_ERTC_TAMP_STAMP_NUMBER 2 +#define AT32_ERTC_WKUP_NUMBER 3 +#define AT32_ERTC_ALARM_NUMBER 41 + +#define AT32_ERTC_ALARM_EXINT 17 +#define AT32_ERTC_TAMP_STAMP_EXINT 21 +#define AT32_ERTC_WKUP_EXINT 22 +#define AT32_ERTC_IRQ_ENABLE() do { \ + nvicEnableVector(AT32_ERTC_TAMP_STAMP_NUMBER, AT32_IRQ_EXINT21_PRIORITY); \ + nvicEnableVector(AT32_ERTC_WKUP_NUMBER, AT32_IRQ_EXINT22_PRIORITY); \ + nvicEnableVector(AT32_ERTC_ALARM_NUMBER, AT32_IRQ_EXINT17_PRIORITY); \ +} while (false) + +/* + * EXINT units. + */ +#define AT32_EXINT0_HANDLER Vector58 +#define AT32_EXINT1_HANDLER Vector5C +#define AT32_EXINT2_HANDLER Vector60 +#define AT32_EXINT3_HANDLER Vector64 +#define AT32_EXINT4_HANDLER Vector68 +#define AT32_EXINT5_9_HANDLER Vector9C +#define AT32_EXINT10_15_HANDLER VectorE0 +#define AT32_EXINT16_HANDLER Vector44 /* Note: same as PVM_IRQn */ +#define AT32_EXINT17_HANDLER VectorE4 /* Note: same as ERTCAlarm_IRQn */ +#define AT32_EXINT18_HANDLER VectorE8 /* Note: same as OTGFS_WKUP_IRQn */ +#define AT32_EXINT20_HANDLER Vector170 /* Note: same as OTGHS_WKUP_IRQn + (F405 only) */ +#define AT32_EXINT21_HANDLER Vector48 /* Note: same as TAMPER_IRQn */ +#define AT32_EXINT22_HANDLER Vector4C /* Note: same as ERTC_WKUP_IRQn */ + +#define AT32_EXINT0_NUMBER 6 +#define AT32_EXINT1_NUMBER 7 +#define AT32_EXINT2_NUMBER 8 +#define AT32_EXINT3_NUMBER 9 +#define AT32_EXINT4_NUMBER 10 +#define AT32_EXINT5_9_NUMBER 23 +#define AT32_EXINT10_15_NUMBER 40 +#define AT32_EXINT16_NUMBER 1 /* Note: same as PVM_IRQn */ +#define AT32_EXINT17_NUMBER 41 /* Note: same as ERTCAlarm_IRQn */ +#define AT32_EXINT18_NUMBER 42 /* Note: same as OTGFS_WKUP_IRQn */ +#define AT32_EXINT20_NUMBER 76 /* Note: same as OTGHS_WKUP_IRQn + (F405 only) */ +#define AT32_EXINT21_NUMBER 2 /* Note: same as TAMPER_IRQn */ +#define AT32_EXINT22_NUMBER 3 /* Note: same as ERTC_WKUP_IRQn */ + +/* + * I2C units. + */ +#define AT32_I2C1_EVENT_HANDLER VectorBC +#define AT32_I2C1_ERROR_HANDLER VectorC0 +#define AT32_I2C2_EVENT_HANDLER VectorC4 +#define AT32_I2C2_ERROR_HANDLER VectorC8 +#define AT32_I2C3_EVENT_HANDLER Vector160 +#define AT32_I2C3_ERROR_HANDLER Vector164 + +#define AT32_I2C1_EVENT_NUMBER 31 +#define AT32_I2C1_ERROR_NUMBER 32 +#define AT32_I2C2_EVENT_NUMBER 33 +#define AT32_I2C2_ERROR_NUMBER 34 +#define AT32_I2C3_EVENT_NUMBER 72 +#define AT32_I2C3_ERROR_NUMBER 73 + +/* + * OTG units. + */ +#define AT32_OTG1_HANDLER Vector14C +#define AT32_OTG2_HANDLER Vector174 /* Note: F405 only */ +#define AT32_OTG2_EP1_OUT_HANDLER Vector168 /* Note: F405 only */ +#define AT32_OTG2_EP1_IN_HANDLER Vector16C /* Note: F405 only */ + +#define AT32_OTG1_NUMBER 67 +#define AT32_OTG2_NUMBER 77 /* Note: F405 only */ +#define AT32_OTG2_EP1_OUT_NUMBER 74 /* Note: F405 only */ +#define AT32_OTG2_EP1_IN_NUMBER 75 /* Note: F405 only */ + +/* + * QUADSPI unit. + */ +#define AT32_QUADSPI1_HANDLER Vector1B0 + +#define AT32_QUADSPI1_NUMBER 92 + +/* + * TMR units. + */ +#define AT32_TMR1_BRK_TMR9_HANDLER VectorA0 +#define AT32_TMR1_OVF_TMR10_HANDLER VectorA4 +#define AT32_TMR1_HALL_TMR11_HANDLER VectorA8 +#define AT32_TMR1_CH_HANDLER VectorAC +#define AT32_TMR2_HANDLER VectorB0 +#define AT32_TMR3_HANDLER VectorB4 +#define AT32_TMR4_HANDLER VectorB8 +#define AT32_TMR6_HANDLER Vector118 +#define AT32_TMR7_HANDLER Vector11C +#define AT32_TMR13_HANDLER VectorF0 +#define AT32_TMR14_HANDLER VectorF4 + +#define AT32_TMR1_BRK_TMR9_NUMBER 24 +#define AT32_TMR1_OVF_TMR10_NUMBER 25 +#define AT32_TMR1_HALL_TMR11_NUMBER 26 +#define AT32_TMR1_CH_NUMBER 27 +#define AT32_TMR2_NUMBER 28 +#define AT32_TMR3_NUMBER 29 +#define AT32_TMR4_NUMBER 30 +#define AT32_TMR6_NUMBER 54 +#define AT32_TMR7_NUMBER 55 +#define AT32_TMR13_NUMBER 44 +#define AT32_TMR14_NUMBER 45 + +/* + * USART units. + */ +#define AT32_USART1_HANDLER VectorD4 +#define AT32_USART2_HANDLER VectorD8 +#define AT32_USART3_HANDLER VectorDC +#define AT32_UART4_HANDLER Vector110 +#define AT32_UART5_HANDLER Vector114 +#define AT32_USART6_HANDLER Vector15C +#define AT32_UART7_HANDLER Vector188 +#define AT32_UART8_HANDLER Vector18C + +#define AT32_USART1_NUMBER 37 +#define AT32_USART2_NUMBER 38 +#define AT32_USART3_NUMBER 39 +#define AT32_UART4_NUMBER 52 +#define AT32_UART5_NUMBER 53 +#define AT32_USART6_NUMBER 71 +#define AT32_UART7_NUMBER 82 +#define AT32_UART8_NUMBER 83 + +/* + * ACC unit. + */ +#define AT32_ACC_HANDLER Vector1DC + +#define AT32_ACC_NUMBER 103 +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void irqInit(void); + void irqDeinit(void); +#ifdef __cplusplus +} +#endif + +#endif /* AT32_ISR_H */ + +/** @} */ diff --git a/os/hal/ports/AT32/AT32F402_405/at32_registry.h b/os/hal/ports/AT32/AT32F402_405/at32_registry.h new file mode 100644 index 0000000000..84d5ba53da --- /dev/null +++ b/os/hal/ports/AT32/AT32F402_405/at32_registry.h @@ -0,0 +1,703 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + ChibiOS - Copyright (C) 2024..2025 Maxjta + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file AT32F402_405/at32_registry.h + * @brief AT32F402_405 capabilities registry. + * + * @addtogroup HAL + * @{ + */ + +#ifndef AT32_REGISTRY_H +#define AT32_REGISTRY_H + +#if defined(AT32F402KB) || defined(AT32F402KC) || \ + defined(AT32F405KB) || defined(AT32F405KC) +#define AT32F402_405K + +#elif defined(AT32F402CB) || defined(AT32F402CC) || \ + defined(AT32F405CB) || defined(AT32F405CC) +#define AT32F402_405C + +#elif defined(AT32F402RB) || defined(AT32F402RC) || \ + defined(AT32F405RB) || defined(AT32F405RC) +#define AT32F402_405R + +#else +#error "unsupported or unrecognized AT32F402 or AT32F405 member" +#endif + +/*===========================================================================*/ +/* Platform capabilities. */ +/*===========================================================================*/ + +/** + * @name Common capabilities + * @{ + */ +/* GPIO attributes.*/ +#if defined(AT32_HAS_GPIOD) +#define AT32_GPIO_EN_MASK (CRM_AHBEN1_GPIOAEN | \ + CRM_AHBEN1_GPIOBEN | \ + CRM_AHBEN1_GPIOCEN | \ + CRM_AHBEN1_GPIODEN | \ + CRM_AHBEN1_GPIOFEN) +#elif defined(AT32_HAS_GPIOC) +#define AT32_GPIO_EN_MASK (CRM_AHBEN1_GPIOAEN | \ + CRM_AHBEN1_GPIOBEN | \ + CRM_AHBEN1_GPIOCEN | \ + CRM_AHBEN1_GPIOFEN) +#else +#define AT32_GPIO_EN_MASK (CRM_AHBEN1_GPIOAEN | \ + CRM_AHBEN1_GPIOBEN | \ + CRM_AHBEN1_GPIOFEN) +#endif +/** @} */ + +#if defined(AT32F402_405K) || defined(__DOXYGEN__) +/** + * @name AT32F402_405K capabilities + * @{ + */ +/* ADC attributes.*/ +#define AT32_HAS_ADC1 TRUE +#define AT32_ADC_SUPPORTS_PRESCALER TRUE +#define AT32_ADC_SUPPORTS_OVERSAMPLING TRUE +#define AT32_ADC_ADC1_DMA_STREAM AT32_DMA_STREAM_ID_ANY + +/* CAN attributes.*/ +#define AT32_HAS_CAN1 TRUE +#define AT32_CAN_MAX_FILTERS 14 + +/* DMA attributes.*/ +#define AT32_ADVANCED_DMA TRUE +#define AT32_DMA_SUPPORTS_DMAMUX TRUE + +#define AT32_DMA1_NUM_CHANNELS 7 +#define AT32_DMA2_NUM_CHANNELS 7 + +/* EXINT attributes.*/ +#if defined(AT32F402KB) || defined(AT32F402KC) || defined(__DOXYGEN__) +#define AT32_EXINT_NUM_LINES 21 +#elif defined(AT32F405KB) || defined(AT32F405KC) +#define AT32_EXINT_NUM_LINES 22 +#endif +#define AT32_EXINT_INTEN_MASK 0x00000000U + +/* FLASH attributes.*/ +#define AT32_FLASH_NUMBER_OF_BANKS 1 +#if defined(AT32F402KB) || defined(AT32F405KB) || defined(__DOXYGEN__) +#define AT32_FLASH_SECTOR_SIZE 1024U +#elif defined(AT32F402KC) || defined(AT32F405KC) +#define AT32_FLASH_SECTOR_SIZE 2048U +#endif + +#if !defined(AT32_FLASH_SECTORS_PER_BANK) || defined(__DOXYGEN__) +#define AT32_FLASH_SECTORS_PER_BANK 128 /* Maximum, can be redefined.*/ +#endif + +/* GPIO attributes.*/ +#define AT32_HAS_GPIOA TRUE +#define AT32_HAS_GPIOB TRUE +#define AT32_HAS_GPIOF TRUE + +#if !defined(AT32_HAS_GPIOC) || defined(__DOXYGEN__) +#define AT32_HAS_GPIOC FALSE +#elif !defined(AT32_HAS_GPIOD) +#define AT32_HAS_GPIOD FALSE +#endif +#define AT32_HAS_GPIOE FALSE +#define AT32_HAS_GPIOG FALSE +#define AT32_HAS_GPIOH FALSE + +/* I2C attributes.*/ +#define AT32_HAS_I2C1 TRUE +#define AT32_I2C_I2C1_RX_DMA_STREAM AT32_DMA_STREAM_ID_ANY +#define AT32_I2C_I2C1_TX_DMA_STREAM AT32_DMA_STREAM_ID_ANY + +#define AT32_HAS_I2C2 TRUE +#define AT32_I2C_I2C2_RX_DMA_STREAM AT32_DMA_STREAM_ID_ANY +#define AT32_I2C_I2C2_TX_DMA_STREAM AT32_DMA_STREAM_ID_ANY + +#define AT32_HAS_I2C3 TRUE +#define AT32_I2C_I2C3_RX_DMA_STREAM AT32_DMA_STREAM_ID_ANY +#define AT32_I2C_I2C3_TX_DMA_STREAM AT32_DMA_STREAM_ID_ANY + +/* ERTC attributes.*/ +#define AT32_HAS_ERTC TRUE +#define AT32_ERTC_HAS_SUBSECONDS TRUE +#define AT32_ERTC_HAS_PERIODIC_WAKEUPS TRUE +#define AT32_ERTC_NUM_ALARMS 2 +#define AT32_ERTC_STORAGE_SIZE 80 + +/* QUADSPI attributes.*/ +#define AT32_HAS_QUADSPI1 TRUE +#define AT32_WSPI_QUADSPI1_DMA_STREAM AT32_DMA_STREAM_ID_ANY + +/* SDIO attributes.*/ +#define AT32_HAS_SDIO FALSE + +/* SPI attributes.*/ +#define AT32_HAS_SPI1 TRUE +#define AT32_SPI1_SUPPORTS_I2S TRUE +#define AT32_SPI1_I2S_FULLDUPLEX TRUE +#define AT32_SPI_SPI1_RX_DMA_STREAM AT32_DMA_STREAM_ID_ANY +#define AT32_SPI_SPI1_TX_DMA_STREAM AT32_DMA_STREAM_ID_ANY + +#define AT32_HAS_SPI3 TRUE +#define AT32_SPI3_SUPPORTS_I2S TRUE +#define AT32_SPI3_I2S_FULLDUPLEX TRUE +#define AT32_SPI_SPI3_RX_DMA_STREAM AT32_DMA_STREAM_ID_ANY +#define AT32_SPI_SPI3_TX_DMA_STREAM AT32_DMA_STREAM_ID_ANY + +#define AT32_HAS_SPI2 FALSE + +/* TMR attributes.*/ +#define AT32_TMR_MAX_CHANNELS 4 + +#define AT32_HAS_TMR1 TRUE +#define AT32_TMR1_IS_32BITS FALSE +#define AT32_TMR1_CHANNELS 4 + +#define AT32_HAS_TMR2 TRUE +#define AT32_TMR2_IS_32BITS TRUE +#define AT32_TMR2_CHANNELS 4 + +#define AT32_HAS_TMR3 TRUE +#define AT32_TMR3_IS_32BITS FALSE +#define AT32_TMR3_CHANNELS 4 + +#define AT32_HAS_TMR4 TRUE +#define AT32_TMR4_IS_32BITS FALSE +#define AT32_TMR4_CHANNELS 4 + +#define AT32_HAS_TMR6 TRUE +#define AT32_TMR6_IS_32BITS FALSE +#define AT32_TMR6_CHANNELS 0 + +#define AT32_HAS_TMR7 TRUE +#define AT32_TMR7_IS_32BITS FALSE +#define AT32_TMR7_CHANNELS 0 + +#define AT32_HAS_TMR9 TRUE +#define AT32_TMR9_IS_32BITS FALSE +#define AT32_TMR9_CHANNELS 2 + +#define AT32_HAS_TMR10 TRUE +#define AT32_TMR10_IS_32BITS FALSE +#define AT32_TMR10_CHANNELS 1 + +#define AT32_HAS_TMR11 TRUE +#define AT32_TMR11_IS_32BITS FALSE +#define AT32_TMR11_CHANNELS 1 + +#define AT32_HAS_TMR13 TRUE +#define AT32_TMR13_IS_32BITS FALSE +#define AT32_TMR13_CHANNELS 1 + +#define AT32_HAS_TMR14 TRUE +#define AT32_TMR14_IS_32BITS FALSE +#define AT32_TMR14_CHANNELS 1 + +#define AT32_HAS_TMR5 FALSE + +/* USART attributes.*/ +#define AT32_HAS_USART1 TRUE +#define AT32_UART_USART1_RX_DMA_STREAM AT32_DMA_STREAM_ID_ANY +#define AT32_UART_USART1_TX_DMA_STREAM AT32_DMA_STREAM_ID_ANY + +#define AT32_HAS_USART2 TRUE +#define AT32_UART_USART2_RX_DMA_STREAM AT32_DMA_STREAM_ID_ANY +#define AT32_UART_USART2_TX_DMA_STREAM AT32_DMA_STREAM_ID_ANY + +#define AT32_HAS_USART3 TRUE +#define AT32_UART_USART3_RX_DMA_STREAM AT32_DMA_STREAM_ID_ANY +#define AT32_UART_USART3_TX_DMA_STREAM AT32_DMA_STREAM_ID_ANY + +#define AT32_HAS_UART4 TRUE +#define AT32_UART_UART4_RX_DMA_STREAM AT32_DMA_STREAM_ID_ANY +#define AT32_UART_UART4_TX_DMA_STREAM AT32_DMA_STREAM_ID_ANY + +#define AT32_HAS_UART5 TRUE +#define AT32_UART_UART5_RX_DMA_STREAM AT32_DMA_STREAM_ID_ANY +#define AT32_UART_UART5_TX_DMA_STREAM AT32_DMA_STREAM_ID_ANY + +#define AT32_HAS_USART6 TRUE +#define AT32_UART_USART6_RX_DMA_STREAM AT32_DMA_STREAM_ID_ANY +#define AT32_UART_USART6_TX_DMA_STREAM AT32_DMA_STREAM_ID_ANY + +#define AT32_HAS_UART7 TRUE +#define AT32_UART_UART7_RX_DMA_STREAM AT32_DMA_STREAM_ID_ANY +#define AT32_UART_UART7_TX_DMA_STREAM AT32_DMA_STREAM_ID_ANY + +#define AT32_HAS_UART8 FALSE + +/* USB attributes.*/ +#define AT32_OTG_STEPPING 2 + +#define AT32_HAS_OTG1 TRUE +#define AT32_OTG1_ENDPOINTS 8 + +#if defined(AT32F402KB) || defined(AT32F402KC) || defined(__DOXYGEN__) +#define AT32_HAS_OTG2 FALSE +#elif defined(AT32F405KB) || defined(AT32F405KC) +#define AT32_HAS_OTG2 TRUE +#define AT32_OTG2_ENDPOINTS 8 +#endif + +/* WDT attributes.*/ +#define AT32_HAS_WDT TRUE +#define AT32_WDT_IS_WINDOWED TRUE + +/* CRC attributes.*/ +#define AT32_HAS_CRC TRUE + +/* STM32 compatibility define. */ +#if AT32_CRC_USE_CRC1 == TRUE +#define STM32_CRC_USE_CRC1 TRUE +#else +#define STM32_CRC_USE_CRC1 FALSE +#endif +/** @} */ +#endif /* defined(AT32F402_405K) */ + +#if defined(AT32F402_405C) || defined(__DOXYGEN__) +/** + * @name AT32F402_405C capabilities + * @{ + */ +/* ADC attributes.*/ +#define AT32_HAS_ADC1 TRUE +#define AT32_ADC_SUPPORTS_PRESCALER TRUE +#define AT32_ADC_SUPPORTS_OVERSAMPLING TRUE +#define AT32_ADC_ADC1_DMA_STREAM AT32_DMA_STREAM_ID_ANY + +/* CAN attributes.*/ +#define AT32_HAS_CAN1 TRUE +#define AT32_CAN_MAX_FILTERS 14 + +/* DMA attributes.*/ +#define AT32_ADVANCED_DMA TRUE +#define AT32_DMA_SUPPORTS_DMAMUX TRUE + +#define AT32_DMA1_NUM_CHANNELS 7 +#define AT32_DMA2_NUM_CHANNELS 7 + +/* EXINT attributes.*/ +#if defined(AT32F402CB) || defined(AT32F402CC) || defined(__DOXYGEN__) +#define AT32_EXINT_NUM_LINES 21 +#elif defined(AT32F405CB) || defined(AT32F405CC) +#define AT32_EXINT_NUM_LINES 22 +#endif +#define AT32_EXINT_INTEN_MASK 0x00000000U + +/* FLASH attributes.*/ +#define AT32_FLASH_NUMBER_OF_BANKS 1 +#if defined(AT32F402CB) || defined(AT32F405CB) || defined(__DOXYGEN__) +#define AT32_FLASH_SECTOR_SIZE 1024U +#elif defined(AT32F402CC) || defined(AT32F405CC) +#define AT32_FLASH_SECTOR_SIZE 2048U +#endif + +#if !defined(AT32_FLASH_SECTORS_PER_BANK) || defined(__DOXYGEN__) +#define AT32_FLASH_SECTORS_PER_BANK 128 /* Maximum, can be redefined.*/ +#endif + +/* GPIO attributes.*/ +#define AT32_HAS_GPIOA TRUE +#define AT32_HAS_GPIOB TRUE +#define AT32_HAS_GPIOC TRUE +#define AT32_HAS_GPIOF TRUE + +#if !defined(AT32_HAS_GPIOD) || defined(__DOXYGEN__) +#define AT32_HAS_GPIOD FALSE +#endif +#define AT32_HAS_GPIOE FALSE +#define AT32_HAS_GPIOG FALSE +#define AT32_HAS_GPIOH FALSE + +/* I2C attributes.*/ +#define AT32_HAS_I2C1 TRUE +#define AT32_I2C_I2C1_RX_DMA_STREAM AT32_DMA_STREAM_ID_ANY +#define AT32_I2C_I2C1_TX_DMA_STREAM AT32_DMA_STREAM_ID_ANY + +#define AT32_HAS_I2C2 TRUE +#define AT32_I2C_I2C2_RX_DMA_STREAM AT32_DMA_STREAM_ID_ANY +#define AT32_I2C_I2C2_TX_DMA_STREAM AT32_DMA_STREAM_ID_ANY + +#define AT32_HAS_I2C3 TRUE +#define AT32_I2C_I2C3_RX_DMA_STREAM AT32_DMA_STREAM_ID_ANY +#define AT32_I2C_I2C3_TX_DMA_STREAM AT32_DMA_STREAM_ID_ANY + +/* ERTC attributes.*/ +#define AT32_HAS_ERTC TRUE +#define AT32_ERTC_HAS_SUBSECONDS TRUE +#define AT32_ERTC_HAS_PERIODIC_WAKEUPS TRUE +#define AT32_ERTC_NUM_ALARMS 2 +#define AT32_ERTC_STORAGE_SIZE 80 + +/* QUADSPI attributes.*/ +#define AT32_HAS_QUADSPI1 TRUE +#define AT32_WSPI_QUADSPI1_DMA_STREAM AT32_DMA_STREAM_ID_ANY + +/* SDIO attributes.*/ +#define AT32_HAS_SDIO FALSE + +/* SPI attributes.*/ +#define AT32_HAS_SPI1 TRUE +#define AT32_SPI1_SUPPORTS_I2S TRUE +#define AT32_SPI1_I2S_FULLDUPLEX TRUE +#define AT32_SPI_SPI1_RX_DMA_STREAM AT32_DMA_STREAM_ID_ANY +#define AT32_SPI_SPI1_TX_DMA_STREAM AT32_DMA_STREAM_ID_ANY + +#define AT32_HAS_SPI2 TRUE +#define AT32_SPI2_SUPPORTS_I2S TRUE +#define AT32_SPI2_I2S_FULLDUPLEX TRUE +#define AT32_SPI_SPI2_RX_DMA_STREAM AT32_DMA_STREAM_ID_ANY +#define AT32_SPI_SPI2_TX_DMA_STREAM AT32_DMA_STREAM_ID_ANY + +#define AT32_HAS_SPI3 TRUE +#define AT32_SPI3_SUPPORTS_I2S TRUE +#define AT32_SPI3_I2S_FULLDUPLEX TRUE +#define AT32_SPI_SPI3_RX_DMA_STREAM AT32_DMA_STREAM_ID_ANY +#define AT32_SPI_SPI3_TX_DMA_STREAM AT32_DMA_STREAM_ID_ANY + +/* TMR attributes.*/ +#define AT32_TMR_MAX_CHANNELS 4 + +#define AT32_HAS_TMR1 TRUE +#define AT32_TMR1_IS_32BITS FALSE +#define AT32_TMR1_CHANNELS 4 + +#define AT32_HAS_TMR2 TRUE +#define AT32_TMR2_IS_32BITS TRUE +#define AT32_TMR2_CHANNELS 4 + +#define AT32_HAS_TMR3 TRUE +#define AT32_TMR3_IS_32BITS FALSE +#define AT32_TMR3_CHANNELS 4 + +#define AT32_HAS_TMR4 TRUE +#define AT32_TMR4_IS_32BITS FALSE +#define AT32_TMR4_CHANNELS 4 + +#define AT32_HAS_TMR6 TRUE +#define AT32_TMR6_IS_32BITS FALSE +#define AT32_TMR6_CHANNELS 0 + +#define AT32_HAS_TMR7 TRUE +#define AT32_TMR7_IS_32BITS FALSE +#define AT32_TMR7_CHANNELS 0 + +#define AT32_HAS_TMR9 TRUE +#define AT32_TMR9_IS_32BITS FALSE +#define AT32_TMR9_CHANNELS 2 + +#define AT32_HAS_TMR10 TRUE +#define AT32_TMR10_IS_32BITS FALSE +#define AT32_TMR10_CHANNELS 1 + +#define AT32_HAS_TMR11 TRUE +#define AT32_TMR11_IS_32BITS FALSE +#define AT32_TMR11_CHANNELS 1 + +#define AT32_HAS_TMR13 TRUE +#define AT32_TMR13_IS_32BITS FALSE +#define AT32_TMR13_CHANNELS 1 + +#define AT32_HAS_TMR14 TRUE +#define AT32_TMR14_IS_32BITS FALSE +#define AT32_TMR14_CHANNELS 1 + +#define AT32_HAS_TMR5 FALSE + +/* USART attributes.*/ +#define AT32_HAS_USART1 TRUE +#define AT32_UART_USART1_RX_DMA_STREAM AT32_DMA_STREAM_ID_ANY +#define AT32_UART_USART1_TX_DMA_STREAM AT32_DMA_STREAM_ID_ANY + +#define AT32_HAS_USART2 TRUE +#define AT32_UART_USART2_RX_DMA_STREAM AT32_DMA_STREAM_ID_ANY +#define AT32_UART_USART2_TX_DMA_STREAM AT32_DMA_STREAM_ID_ANY + +#define AT32_HAS_USART3 TRUE +#define AT32_UART_USART3_RX_DMA_STREAM AT32_DMA_STREAM_ID_ANY +#define AT32_UART_USART3_TX_DMA_STREAM AT32_DMA_STREAM_ID_ANY + +#define AT32_HAS_UART4 TRUE +#define AT32_UART_UART4_RX_DMA_STREAM AT32_DMA_STREAM_ID_ANY +#define AT32_UART_UART4_TX_DMA_STREAM AT32_DMA_STREAM_ID_ANY + +#define AT32_HAS_UART5 TRUE +#define AT32_UART_UART5_RX_DMA_STREAM AT32_DMA_STREAM_ID_ANY +#define AT32_UART_UART5_TX_DMA_STREAM AT32_DMA_STREAM_ID_ANY + +#define AT32_HAS_USART6 TRUE +#define AT32_UART_USART6_RX_DMA_STREAM AT32_DMA_STREAM_ID_ANY +#define AT32_UART_USART6_TX_DMA_STREAM AT32_DMA_STREAM_ID_ANY + +#define AT32_HAS_UART7 TRUE +#define AT32_UART_UART7_RX_DMA_STREAM AT32_DMA_STREAM_ID_ANY +#define AT32_UART_UART7_TX_DMA_STREAM AT32_DMA_STREAM_ID_ANY + +#define AT32_HAS_UART8 FALSE + +/* USB attributes.*/ +#define AT32_OTG_STEPPING 2 + +#define AT32_HAS_OTG1 TRUE +#define AT32_OTG1_ENDPOINTS 8 + +#if defined(AT32F402CB) || defined(AT32F402CC) || defined(__DOXYGEN__) +#define AT32_HAS_OTG2 FALSE +#elif defined(AT32F405CB) || defined(AT32F405CC) +#define AT32_HAS_OTG2 TRUE +#define AT32_OTG2_ENDPOINTS 8 +#endif + +/* WDT attributes.*/ +#define AT32_HAS_WDT TRUE +#define AT32_WDT_IS_WINDOWED TRUE + +/* CRC attributes.*/ +#define AT32_HAS_CRC TRUE + +/* STM32 compatibility define. */ +#if AT32_CRC_USE_CRC1 == TRUE +#define STM32_CRC_USE_CRC1 TRUE +#else +#define STM32_CRC_USE_CRC1 FALSE +#endif +/** @} */ +#endif /* defined(AT32F402_405C) */ + +#if defined(AT32F402_405R) || defined(__DOXYGEN__) +/** + * @name AT32F402_405R capabilities + * @{ + */ +/* ADC attributes.*/ +#define AT32_HAS_ADC1 TRUE +#define AT32_ADC_SUPPORTS_PRESCALER TRUE +#define AT32_ADC_SUPPORTS_OVERSAMPLING TRUE +#define AT32_ADC_ADC1_DMA_STREAM AT32_DMA_STREAM_ID_ANY + +/* CAN attributes.*/ +#define AT32_HAS_CAN1 TRUE +#define AT32_CAN_MAX_FILTERS 14 + +/* DMA attributes.*/ +#define AT32_ADVANCED_DMA TRUE +#define AT32_DMA_SUPPORTS_DMAMUX TRUE + +#define AT32_DMA1_NUM_CHANNELS 7 +#define AT32_DMA2_NUM_CHANNELS 7 + +/* EXINT attributes.*/ +#if defined(AT32F402RB) || defined(AT32F402RC) || defined(__DOXYGEN__) +#define AT32_EXINT_NUM_LINES 21 +#elif defined(AT32F405RB) || defined(AT32F405RC) +#define AT32_EXINT_NUM_LINES 22 +#endif +#define AT32_EXINT_INTEN_MASK 0x00000000U + +/* FLASH attributes.*/ +#define AT32_FLASH_NUMBER_OF_BANKS 1 +#if defined(AT32F402RB) || defined(AT32F405RB) || defined(__DOXYGEN__) +#define AT32_FLASH_SECTOR_SIZE 1024U +#elif defined(AT32F402RC) || defined(AT32F405RC) +#define AT32_FLASH_SECTOR_SIZE 2048U +#endif + +#if !defined(AT32_FLASH_SECTORS_PER_BANK) || defined(__DOXYGEN__) +#define AT32_FLASH_SECTORS_PER_BANK 128 /* Maximum, can be redefined.*/ +#endif + +/* GPIO attributes.*/ +#define AT32_HAS_GPIOA TRUE +#define AT32_HAS_GPIOB TRUE +#define AT32_HAS_GPIOC TRUE +#define AT32_HAS_GPIOD TRUE +#define AT32_HAS_GPIOF TRUE + +#define AT32_HAS_GPIOE FALSE +#define AT32_HAS_GPIOG FALSE +#define AT32_HAS_GPIOH FALSE + +/* I2C attributes.*/ +#define AT32_HAS_I2C1 TRUE +#define AT32_I2C_I2C1_RX_DMA_STREAM AT32_DMA_STREAM_ID_ANY +#define AT32_I2C_I2C1_TX_DMA_STREAM AT32_DMA_STREAM_ID_ANY + +#define AT32_HAS_I2C2 TRUE +#define AT32_I2C_I2C2_RX_DMA_STREAM AT32_DMA_STREAM_ID_ANY +#define AT32_I2C_I2C2_TX_DMA_STREAM AT32_DMA_STREAM_ID_ANY + +#define AT32_HAS_I2C3 TRUE +#define AT32_I2C_I2C3_RX_DMA_STREAM AT32_DMA_STREAM_ID_ANY +#define AT32_I2C_I2C3_TX_DMA_STREAM AT32_DMA_STREAM_ID_ANY + +/* ERTC attributes.*/ +#define AT32_HAS_ERTC TRUE +#define AT32_ERTC_HAS_SUBSECONDS TRUE +#define AT32_ERTC_HAS_PERIODIC_WAKEUPS TRUE +#define AT32_ERTC_NUM_ALARMS 2 +#define AT32_ERTC_STORAGE_SIZE 80 + +/* QUADSPI attributes.*/ +#define AT32_HAS_QUADSPI1 TRUE +#define AT32_WSPI_QUADSPI1_DMA_STREAM AT32_DMA_STREAM_ID_ANY + +/* SDIO attributes.*/ +#define AT32_HAS_SDIO FALSE + +/* SPI attributes.*/ +#define AT32_HAS_SPI1 TRUE +#define AT32_SPI1_SUPPORTS_I2S TRUE +#define AT32_SPI1_I2S_FULLDUPLEX TRUE +#define AT32_SPI_SPI1_RX_DMA_STREAM AT32_DMA_STREAM_ID_ANY +#define AT32_SPI_SPI1_TX_DMA_STREAM AT32_DMA_STREAM_ID_ANY + +#define AT32_HAS_SPI2 TRUE +#define AT32_SPI2_SUPPORTS_I2S TRUE +#define AT32_SPI2_I2S_FULLDUPLEX TRUE +#define AT32_SPI_SPI2_RX_DMA_STREAM AT32_DMA_STREAM_ID_ANY +#define AT32_SPI_SPI2_TX_DMA_STREAM AT32_DMA_STREAM_ID_ANY + +#define AT32_HAS_SPI3 TRUE +#define AT32_SPI3_SUPPORTS_I2S TRUE +#define AT32_SPI3_I2S_FULLDUPLEX TRUE +#define AT32_SPI_SPI3_RX_DMA_STREAM AT32_DMA_STREAM_ID_ANY +#define AT32_SPI_SPI3_TX_DMA_STREAM AT32_DMA_STREAM_ID_ANY + +/* TMR attributes.*/ +#define AT32_TMR_MAX_CHANNELS 4 + +#define AT32_HAS_TMR1 TRUE +#define AT32_TMR1_IS_32BITS FALSE +#define AT32_TMR1_CHANNELS 4 + +#define AT32_HAS_TMR2 TRUE +#define AT32_TMR2_IS_32BITS TRUE +#define AT32_TMR2_CHANNELS 4 + +#define AT32_HAS_TMR3 TRUE +#define AT32_TMR3_IS_32BITS FALSE +#define AT32_TMR3_CHANNELS 4 + +#define AT32_HAS_TMR4 TRUE +#define AT32_TMR4_IS_32BITS FALSE +#define AT32_TMR4_CHANNELS 4 + +#define AT32_HAS_TMR6 TRUE +#define AT32_TMR6_IS_32BITS FALSE +#define AT32_TMR6_CHANNELS 0 + +#define AT32_HAS_TMR7 TRUE +#define AT32_TMR7_IS_32BITS FALSE +#define AT32_TMR7_CHANNELS 0 + +#define AT32_HAS_TMR9 TRUE +#define AT32_TMR9_IS_32BITS FALSE +#define AT32_TMR9_CHANNELS 2 + +#define AT32_HAS_TMR10 TRUE +#define AT32_TMR10_IS_32BITS FALSE +#define AT32_TMR10_CHANNELS 1 + +#define AT32_HAS_TMR11 TRUE +#define AT32_TMR11_IS_32BITS FALSE +#define AT32_TMR11_CHANNELS 1 + +#define AT32_HAS_TMR13 TRUE +#define AT32_TMR13_IS_32BITS FALSE +#define AT32_TMR13_CHANNELS 1 + +#define AT32_HAS_TMR14 TRUE +#define AT32_TMR14_IS_32BITS FALSE +#define AT32_TMR14_CHANNELS 1 + +#define AT32_HAS_TMR5 FALSE + +/* USART attributes.*/ +#define AT32_HAS_USART1 TRUE +#define AT32_UART_USART1_RX_DMA_STREAM AT32_DMA_STREAM_ID_ANY +#define AT32_UART_USART1_TX_DMA_STREAM AT32_DMA_STREAM_ID_ANY + +#define AT32_HAS_USART2 TRUE +#define AT32_UART_USART2_RX_DMA_STREAM AT32_DMA_STREAM_ID_ANY +#define AT32_UART_USART2_TX_DMA_STREAM AT32_DMA_STREAM_ID_ANY + +#define AT32_HAS_USART3 TRUE +#define AT32_UART_USART3_RX_DMA_STREAM AT32_DMA_STREAM_ID_ANY +#define AT32_UART_USART3_TX_DMA_STREAM AT32_DMA_STREAM_ID_ANY + +#define AT32_HAS_UART4 TRUE +#define AT32_UART_UART4_RX_DMA_STREAM AT32_DMA_STREAM_ID_ANY +#define AT32_UART_UART4_TX_DMA_STREAM AT32_DMA_STREAM_ID_ANY + +#define AT32_HAS_UART5 TRUE +#define AT32_UART_UART5_RX_DMA_STREAM AT32_DMA_STREAM_ID_ANY +#define AT32_UART_UART5_TX_DMA_STREAM AT32_DMA_STREAM_ID_ANY + +#define AT32_HAS_USART6 TRUE +#define AT32_UART_USART6_RX_DMA_STREAM AT32_DMA_STREAM_ID_ANY +#define AT32_UART_USART6_TX_DMA_STREAM AT32_DMA_STREAM_ID_ANY + +#define AT32_HAS_UART7 TRUE +#define AT32_UART_UART7_RX_DMA_STREAM AT32_DMA_STREAM_ID_ANY +#define AT32_UART_UART7_TX_DMA_STREAM AT32_DMA_STREAM_ID_ANY + +#define AT32_HAS_UART8 TRUE +#define AT32_UART_UART8_RX_DMA_STREAM AT32_DMA_STREAM_ID_ANY +#define AT32_UART_UART8_TX_DMA_STREAM AT32_DMA_STREAM_ID_ANY + +/* USB attributes.*/ +#define AT32_OTG_STEPPING 2 + +#define AT32_HAS_OTG1 TRUE +#define AT32_OTG1_ENDPOINTS 8 + +#if defined(AT32F402RB) || defined(AT32F402RC) || defined(__DOXYGEN__) +#define AT32_HAS_OTG2 FALSE +#elif defined(AT32F405RB) || defined(AT32F405RC) +#define AT32_HAS_OTG2 TRUE +#define AT32_OTG2_ENDPOINTS 8 +#endif + +/* WDT attributes.*/ +#define AT32_HAS_WDT TRUE +#define AT32_WDT_IS_WINDOWED TRUE + +/* CRC attributes.*/ +#define AT32_HAS_CRC TRUE + +/* STM32 compatibility define. */ +#if AT32_CRC_USE_CRC1 == TRUE +#define STM32_CRC_USE_CRC1 TRUE +#else +#define STM32_CRC_USE_CRC1 FALSE +#endif +/** @} */ +#endif /* defined(AT32F402_405R) */ + +#endif /* AT32_REGISTRY_H */ + +/** @} */ diff --git a/os/hal/ports/AT32/AT32F405xx/hal_efl_lld.c b/os/hal/ports/AT32/AT32F402_405/hal_efl_lld.c similarity index 92% rename from os/hal/ports/AT32/AT32F405xx/hal_efl_lld.c rename to os/hal/ports/AT32/AT32F402_405/hal_efl_lld.c index 8020eb3707..d96352c2f8 100644 --- a/os/hal/ports/AT32/AT32F405xx/hal_efl_lld.c +++ b/os/hal/ports/AT32/AT32F402_405/hal_efl_lld.c @@ -1,6 +1,8 @@ /* - ChibiOS - Copyright (C) 2023..2024 Zhaqian - ChibiOS - Copyright (C) 2024 Maxjta + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + ChibiOS - Copyright (C) 2024..2025 Maxjta Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -16,8 +18,8 @@ */ /** - * @file AT32F405xx/hal_efl_lld.c - * @brief AT32F405xx Embedded Flash subsystem low level driver source. + * @file hal_efl_lld.c + * @brief AT32F402_405 Embedded Flash subsystem low level driver source. * * @addtogroup HAL_EFL * @{ @@ -73,9 +75,9 @@ static inline void at32_flash_lock(EFlashDriver *eflp) { } static inline void at32_flash_unlock(EFlashDriver *eflp) { - - eflp->flash->UNLOCK = FLASH_UNLOCK_KEY1; - eflp->flash->UNLOCK = FLASH_UNLOCK_KEY2; + + eflp->flash->UNLOCK = FLASH_KEY1; + eflp->flash->UNLOCK = FLASH_KEY2; } static inline void at32_flash_enable_pgm(EFlashDriver *eflp) { @@ -89,8 +91,8 @@ static inline void at32_flash_disable_pgm(EFlashDriver *eflp) { } static inline void at32_flash_clear_status(EFlashDriver *eflp) { - - eflp->flash->STS = FLASH_STS_PRGMERR | FLASH_STS_EPPERR; + + eflp->flash->STS = 0x0000001FU; } static inline uint32_t at32_flash_is_busy(EFlashDriver *eflp) { @@ -105,6 +107,24 @@ static inline void at32_flash_wait_busy(EFlashDriver *eflp) { } } +static inline flash_error_t at32_flash_check_errors(EFlashDriver *eflp) { + uint32_t sts = eflp->flash->STS; + + /* Clearing error conditions.*/ + eflp->flash->STS = sts & 0x0000001FU; + + /* Decoding relevant errors.*/ + if ((sts & FLASH_STS_EPPERR) != 0U) { + return FLASH_ERROR_HW_FAILURE; + } + + if ((sts & FLASH_STS_PRGMERR) != 0U) { + return FLASH_ERROR_PROGRAM; /* There is no error on erase.*/ + } + + return FLASH_NO_ERROR; +} + /*===========================================================================*/ /* Driver interrupt handlers. */ /*===========================================================================*/ @@ -135,7 +155,7 @@ void efl_lld_init(void) { void efl_lld_start(EFlashDriver *eflp) { at32_flash_unlock(eflp); - eflp->flash->CTRL = 0x00000000U; + FLASH->CTRL = 0x00000000U; } /** @@ -202,7 +222,7 @@ flash_error_t efl_lld_read(void *instance, flash_offset_t offset, at32_flash_clear_status(devp); /* Actual read implementation.*/ - memcpy((void *)rp, (const void *)(efl_lld_descriptor.address + offset), n); + memcpy((void *)rp, (const void *)efl_lld_descriptor.address + offset, n); /* Ready state again.*/ devp->state = FLASH_READY; @@ -276,26 +296,13 @@ flash_error_t efl_lld_program(void *instance, flash_offset_t offset, pp++; } while ((n > 0U) & ((offset & AT32_FLASH_LINE_MASK) != 0U)); + /* Programming line.*/ address[0] = line.hw[0]; at32_flash_wait_busy(devp); - uint32_t sts = devp->flash->STS; - - /* Clearing error status bits.*/ - at32_flash_clear_status(devp); - - /* Decoding relevant errors.*/ - if ((sts & FLASH_STS_EPPERR) != 0U) { - err = FLASH_ERROR_HW_FAILURE; - break; - } - else if ((sts & FLASH_STS_PRGMERR) != 0U) { - err = FLASH_ERROR_PROGRAM; - break; - } - else if ((sts & FLASH_STS_ODF) == 0U) { - err = FLASH_ERROR_PROGRAM; + err = at32_flash_check_errors(devp); + if (err != FLASH_NO_ERROR) { break; } @@ -371,7 +378,7 @@ flash_error_t efl_lld_start_erase_sector(void *instance, /* Set the page.*/ devp->flash->ADDR = (uint32_t)(efl_lld_descriptor.address + - flashGetSectorOffset(getBaseFlash(devp), sector)); + flashGetSectorOffset(getBaseFlash(devp), sector)); /* Start the erase.*/ devp->flash->CTRL |= FLASH_CTRL_ERSTR; diff --git a/os/hal/ports/AT32/AT32F405xx/hal_efl_lld.h b/os/hal/ports/AT32/AT32F402_405/hal_efl_lld.h similarity index 91% rename from os/hal/ports/AT32/AT32F405xx/hal_efl_lld.h rename to os/hal/ports/AT32/AT32F402_405/hal_efl_lld.h index 40cd178c6e..d48d4656b7 100644 --- a/os/hal/ports/AT32/AT32F405xx/hal_efl_lld.h +++ b/os/hal/ports/AT32/AT32F402_405/hal_efl_lld.h @@ -1,6 +1,8 @@ /* - ChibiOS - Copyright (C) 2023..2024 Zhaqian - ChibiOS - Copyright (C) 2024 Maxjta + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + ChibiOS - Copyright (C) 2024..2025 Maxjta Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -16,8 +18,8 @@ */ /** - * @file AT32F405xx/hal_efl_lld.h - * @brief AT32F405xx Embedded Flash subsystem low level driver header. + * @file hal_efl_lld.h + * @brief AT32F402_405 Embedded Flash subsystem low level driver header. * * @addtogroup HAL_EFL * @{ @@ -37,14 +39,14 @@ /*===========================================================================*/ /** - * @name AT32F402_5xx configuration options + * @name AT32F402_405 configuration options * @{ */ /** * @brief Suggested wait time during erase operations polling. */ #if !defined(AT32_FLASH_WAIT_TIME_MS) || defined(__DOXYGEN__) -#define AT32_FLASH_WAIT_TIME_MS 10 +#define AT32_FLASH_WAIT_TIME_MS 1 #endif /** @} */ diff --git a/os/hal/ports/AT32/AT32F405xx/hal_lld.c b/os/hal/ports/AT32/AT32F402_405/hal_lld.c similarity index 59% rename from os/hal/ports/AT32/AT32F405xx/hal_lld.c rename to os/hal/ports/AT32/AT32F402_405/hal_lld.c index 5fae394718..3644cbae57 100644 --- a/os/hal/ports/AT32/AT32F405xx/hal_lld.c +++ b/os/hal/ports/AT32/AT32F402_405/hal_lld.c @@ -1,6 +1,8 @@ /* - ChibiOS - Copyright (C) 2023..2024 Zhaqian - ChibiOS - Copyright (C) 2024 Maxjta + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + ChibiOS - Copyright (C) 2024..2025 Maxjta Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -16,8 +18,8 @@ */ /** - * @file AT32F405xx/hal_lld.c - * @brief AT32F405xx HAL subsystem low level driver source. + * @file AT32F402_405/hal_lld.c + * @brief AT32F402_405 HAL subsystem low level driver source. * * @addtogroup HAL * @{ @@ -35,7 +37,7 @@ /** * @brief CMSIS system core clock variable. - * @note It is declared in system_at32f405xx.h. + * @note It is declared in system_at32f402_405.h. */ uint32_t SystemCoreClock = AT32_HCLK; @@ -48,23 +50,29 @@ uint32_t SystemCoreClock = AT32_HCLK; /*===========================================================================*/ /** - * @brief Initializes the backup domain. + * @brief Initializes the battery powered domain. * @note WARNING! Changing clock source impossible without resetting - * of the whole BKP domain. + * of the whole BPR domain. */ -static void hal_lld_backup_domain_init(void) { +static void hal_lld_battery_powered_domain_init(void) { - /* Backup domain access enabled and left open.*/ + /* Battery powered domain access enabled and left open.*/ PWC->CTRL |= PWC_CTRL_BPWEN; - - /* Reset BKP domain if different clock source selected.*/ + + /* Reset BPR domain if different clock source selected.*/ if ((CRM->BPDC & AT32_ERTCSEL_MASK) != AT32_ERTCSEL) { - /* Backup domain reset.*/ + /* Battery powered domain reset.*/ CRM->BPDC = CRM_BPDC_BPDRST; + + /* Errata 1.2.1: Read/write ERTC occupies APB1 for 15 ERTC clock cycles.*/ + { + __NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP(); + __NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP(); + } + CRM->BPDC = 0; } - /* If enabled then the LEXT is started.*/ #if AT32_LEXT_ENABLED #if defined(AT32_LEXT_BYPASS) /* LEXT Bypass.*/ @@ -73,12 +81,13 @@ static void hal_lld_backup_domain_init(void) { /* No LEXT Bypass.*/ CRM->BPDC |= CRM_BPDC_LEXTEN; #endif - while ((CRM->BPDC & CRM_BPDC_LEXTSTBL) == 0); /* Waits until LEXT is stable. */ -#endif /* AT32_LEXT_ENABLED */ + while ((CRM->BPDC & CRM_BPDC_LEXTSTBL) == 0) + ; /* Waits until LEXT is stable. */ +#endif -#if AT32_ERTCSEL != AT32_ERTCSEL_NOCLOCK - /* If the backup domain hasn't been initialized yet then proceed with - initialization.*/ +#if HAL_USE_RTC + /* If the battery powered domain hasn't been initialized yet then proceed + with initialization.*/ if ((CRM->BPDC & CRM_BPDC_ERTCEN) == 0) { /* Selects clock source.*/ CRM->BPDC |= AT32_ERTCSEL; @@ -86,7 +95,7 @@ static void hal_lld_backup_domain_init(void) { /* ERTC clock enabled.*/ CRM->BPDC |= CRM_BPDC_ERTCEN; } -#endif /* AT32_ERTCSEL != AT32_ERTCSEL_NOCLOCK */ +#endif /* HAL_USE_RTC */ } /*===========================================================================*/ @@ -114,7 +123,7 @@ void hal_lld_init(void) { crmResetAPB2(~0); /* Initializes the backup domain.*/ - hal_lld_backup_domain_init(); + hal_lld_battery_powered_domain_init(); /* DMA subsystems initialization.*/ #if defined(AT32_DMA_REQUIRED) @@ -124,23 +133,24 @@ void hal_lld_init(void) { /* IRQ subsystem initialization.*/ irqInit(); - /* Programmable voltage detector enable.*/ + /* Power voltage monitoring enable.*/ #if AT32_PVM_ENABLE - PWC->CTRL |= PWC_CTRL_PVMEN | (AT32_PVM & AT32_PVMSEL_MASK); + PWC->CTRL |= PWC_CTRL_PVMEN | (AT32_PVMSEL & AT32_PVMSEL_MASK); #endif /* AT32_PVM_ENABLE */ } /* - * hick divider selection for all sub-families. + * HICK divider selection for all sub-families. */ -static void at32_hick_divider_select(uint32_t div) +static void at32_hick_divider(uint32_t div) { volatile uint32_t misc1 = CRM->MISC1; volatile uint32_t misc2 = CRM->MISC2; CRM->MISC2 &= ~AT32_HICK_TO_SCLK_DIV_MASK; CRM->MISC2 |= AT32_HICK_TO_SCLK_DIV_DIV16; - /* delay */ + + /* Delay.*/ { __NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP(); __NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP(); @@ -148,33 +158,34 @@ static void at32_hick_divider_select(uint32_t div) __NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP(); } - CRM->MISC1 = (AT32_HICK_TO_SCLK_HICKOUT | div); + CRM->MISC1 = (AT32_HICK_TO_SCLK_48M | div); CRM->MISC1 &= ~AT32_HICK_TO_SCLK_MASK; CRM->MISC1 |= (misc1 & AT32_HICK_TO_SCLK_MASK); - + CRM->MISC2 &= ~AT32_HICK_TO_SCLK_DIV_MASK; CRM->MISC2 |= (misc2 & AT32_HICK_TO_SCLK_DIV_MASK); } -/* - * hick as system clock frequency selection for all sub-families. +/* + * HICK to SCLK selection for all sub-families. */ -static void at32_hick_frequency_select(uint32_t value) +static void at32_hick_to_sclk(uint32_t value) { volatile uint32_t misc1 = CRM->MISC1; volatile uint32_t misc2 = CRM->MISC2; CRM->MISC2 &= ~AT32_HICK_TO_SCLK_DIV_MASK; CRM->MISC2 |= AT32_HICK_TO_SCLK_DIV_DIV16; - /* delay */ + + /* Delay.*/ { __NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP(); __NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP(); __NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP(); __NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP(); } - - CRM->MISC1 = (AT32_HICK_TO_SCLK_HICKOUT | (misc1 & AT32_HICKDIV_MASK)); + + CRM->MISC1 = (AT32_HICK_TO_SCLK_48M | (misc1 & AT32_HICKDIV_MASK)); CRM->MISC1 &= ~AT32_HICK_TO_SCLK_MASK; CRM->MISC1 |= value; @@ -182,103 +193,101 @@ static void at32_hick_frequency_select(uint32_t value) CRM->MISC2 |= (misc2 & AT32_HICK_TO_SCLK_DIV_MASK); } -/* - * Clocks deinitialization for all sub-families. +/** + * @brief AT32 clocks and PLL initialization. + * @note All the involved constants come from the file @p board.h. + * @note This function should be invoked just after the system reset. + * + * @special */ -void at32_clock_reset(void) -{ - /* reset cfg register, include sclk switch, ahbdiv, apb1div, apb2div, adcdiv, clkout bits */ - CRM->CFG = (0x40000000U); - - /* reset hexten, hextbyps, cfden and pllen bits */ - CRM->CTRL &= ~(0x010D0000U); - - /* reset pllms pllns pllfr pllrcs bits */ - CRM->PLLCFG = 0x000007C1U; - - /* reset clkout_sel, clkoutdiv, pllclk_to_adc, hick_to_usb */ - CRM->MISC1 &= 0x00005000U; - CRM->MISC1 |= 0x000F0000U; - - /* disable all interrupts enable and clear pending bits */ - CRM->CLKINT = 0x009F0000; -} /* - * Clocks initialization for all sub-families. + * Clocks initialization for all series. */ void at32_clock_init(void) { -#if !AT32_NO_INIT - /* HICK setup, it enforces the reset situation in order to handle possible - problems with JTAG probes and re-initializations.*/ - - /* clock reset. */ - at32_clock_reset(); - CRM->MISC2 |= CRM_MISC2_AUTO_STEP_EN; - - CRM->CTRL |= CRM_CTRL_HICKEN; /* Make sure HICK is ON. */ - while((CRM->CTRL & CRM_CTRL_HICKSTBL) == 0); /* Wait until HICK is stable. */ - - CRM->CTRL &= CRM_CTRL_HICKTRIM | CRM_CTRL_HICKEN; /* CTRL Reset value. */ +#if !AT32_NO_INIT + /* PWC activation.*/ + CRM->APB1EN |= CRM_APB1EN_PWCEN; - at32_hick_divider_select(AT32_HICKDIV); - at32_hick_frequency_select(AT32_HICK_TO_SCLK); - CRM->MISC2 |= AT32_HICK_TO_SCLK_DIV; - CRM->CFG |= CRM_CFG_SCLK_HICK; /* CFG reset value. */ - while ((CRM->CFG & CRM_CFG_SCLKSTS) != CRM_CFG_SCLKSTS_HICK); /* Waits until HICK is selected.*/ + /* PWC initialization.*/ + PWC->LDOOV = AT32_LDOOVSEL; - CRM->MISC2 &= ~CRM_MISC2_AUTO_STEP_EN; + /* HICK setup, it enforces the reset situation in order to handle possible + problems with JTAG probes and re-initializations.*/ + CRM->CTRL |= CRM_CTRL_HICKEN; /* Make sure HICK is ON. */ + while (!(CRM->CTRL & CRM_CTRL_HICKSTBL)) + ; /* Wait until HICK is stable. */ + at32_hick_divider(AT32_HICKDIV); /* HICK divider. */ + at32_hick_to_sclk(AT32_HICK_TO_SCLK); /* HICK sending to SCLK. */ + CRM->MISC2 |= AT32_HICK_TO_SCLK_DIV; /* Divider when sending to SCLK. */ + + /* HICK is selected as new source without touching the other fields in + CFGR. Clearing the register has to be postponed after HICK is the + new source. */ + CRM->CFG &= ~CRM_CFG_SCLKSEL; /* Reset SCLKSEL, selecting HICK. */ + while ((CRM->CFG & CRM_CFG_SCLKSTS) != CRM_CFG_SCLKSTS_HICK) + ; /* Waits until HICK is selected. */ + + /* Registers finally cleared to reset values. */ + CRM->CTRL &= ~(0x010D0000); /* CTRL reset value. */ + CRM->CFG = (0x40000000); /* CFG reset value. */ + CRM->PLLCFG = 0x000007C1; /* PLLCFG reset value. */ + CRM->MISC1 &= 0x00005000; /* MISC1 reset value. */ + CRM->MISC1 |= 0x000F0000; + CRM->CLKINT = 0x009F0000; /* CLKINT reset value. */ /* Flash setup and final clock selection.*/ - FLASH->PSR = AT32_FLASHBITS; - CRM->APB1EN |= CRM_APB1EN_PWCEN; - - /* PWR initialization.*/ - PWC->LDOOV = AT32_LDOOVSEL; + FLASH->PSR = AT32_FLASHBITS; /* Flash wait states depending on clock.*/ + while ((FLASH->PSR & FLASH_PSR_WTCYC_Msk) != + (AT32_FLASHBITS & FLASH_PSR_WTCYC_Msk)) { + } #if AT32_HEXT_ENABLED - /* HEXT activation.*/ #if defined(AT32_HEXT_BYPASS) /* HEXT Bypass.*/ CRM->CTRL |= CRM_CTRL_HEXTEN | CRM_CTRL_HEXTBYPS; -#else - /* No HEXT Bypass.*/ - CRM->CTRL |= CRM_CTRL_HEXTEN; #endif - while (!(CRM->CTRL & CRM_CTRL_HEXTSTBL)); /* Waits until HEXT is stable. */ + /* HEXT activation. */ + CRM->CTRL |= CRM_CTRL_HEXTEN; + while (!(CRM->CTRL & CRM_CTRL_HEXTSTBL)) + ; /* Waits until HEXT is stable. */ #endif #if AT32_LICK_ENABLED /* LICK activation.*/ CRM->CTRLSTS |= CRM_CTRLSTS_LICKEN; - while ((CRM->CTRLSTS & CRM_CTRLSTS_LICKSTBL) == 0); /* Waits until LICK is stable. */ + while ((CRM->CTRLSTS & CRM_CTRLSTS_LICKSTBL) == 0) + ; /* Waits until LICK is stable. */ #endif #if AT32_ACTIVATE_PLL /* PLL activation.*/ #if AT32_PLLRCS == AT32_PLLRCS_HICK - at32_hick_divider_select(AT32_HICKDIV_DIV1); + at32_hick_divider(AT32_HICKDIV_DIV1); #endif CRM->PLLCFG = AT32_PLL_MS | AT32_PLL_NS | AT32_PLL_FP | AT32_PLL_FU | AT32_PLLRCS; CRM->CTRL |= CRM_CTRL_PLLEN; - while (!(CRM->CTRL & CRM_CTRL_PLLSTBL)); /* Waits until PLL is stable. */ + while (!(CRM->CTRL & CRM_CTRL_PLLSTBL)) + ; /* Waits until PLL is stable. */ #if AT32_PLLU_ENABLED - CRM->PLLCFG |= CRM_PLLCFG_PLLUEN; - while (!(CRM->CTRL & CRM_CTRL_PLLUSTBL)); /* Waits until PLLU is stable. */ + CRM->PLLCFG |= CRM_PLLCFG_PLLU_EN; + while (!(CRM->CTRL & CRM_CTRL_PLLUSTBL)) + ; /* Waits until PLLU is stable. */ #endif #endif /* Clock settings.*/ - CRM->CFG |= (AT32_CLKOUT_SEL & AT32_CLKOUT_SEL_CFG_MASK) | AT32_APB2DIV | - AT32_APB1DIV | AT32_AHBDIV | AT32_ETRCDIV | AT32_I2SF5CLKSEL | + CRM->CFG |= (AT32_CLKOUT_SEL & AT32_CLKOUT_SEL_CFG_MASK) | AT32_APB2DIV | + AT32_APB1DIV | AT32_AHBDIV | + AT32_ERTCDIV | AT32_I2SF5CLKSEL | AT32_CLKOUTDIV1; CRM->MISC1 |= (AT32_CLKOUT_SEL & AT32_CLKOUT_SEL_MISC1_MASK) | AT32_CLKOUTDIV2; - /* PLL Auto Step activation.*/ + /* PLL auto step activation.*/ CRM->MISC2 |= CRM_MISC2_AUTO_STEP_EN; - + /* Switching to the configured clock source if it is different from HICK.*/ #if AT32_SCLKSEL != AT32_SCLKSEL_HICK #if AT32_SCLKSEL == AT32_SCLKSEL_HEXT @@ -286,35 +295,28 @@ void at32_clock_init(void) { #endif /* Switches clock source.*/ CRM->CFG |= AT32_SCLKSEL; - while ((CRM->CFG & CRM_CFG_SCLKSTS) != (AT32_SCLKSEL << 2)); /* Waits selection complete. */ + while ((CRM->CFG & CRM_CFG_SCLKSTS) != (AT32_SCLKSEL << 2)) + ; /* Waits selection complete. */ #endif - /* PLL Auto Step inactivation.*/ + /* PLL auto step inactivation.*/ CRM->MISC2 &= ~CRM_MISC2_AUTO_STEP_EN; - + #if !AT32_HICK_ENABLED CRM->CTRL &= ~CRM_CTRL_HICKEN; #endif #if AT32_PLLU_USB48_SEL == AT32_PLLU_USB48_SEL_HICK - at32_hick_divider_select(AT32_HICKDIV_DIV1); - at32_hick_frequency_select(AT32_HICK_TO_SCLK_HICKOUT); + at32_hick_divider(AT32_HICKDIV_DIV1); + at32_hick_to_sclk(AT32_HICK_TO_SCLK_48M); #endif CRM->MISC2 &= ~AT32_PLLU_USB48_SEL_MASK; CRM->MISC2 |= AT32_PLLU_USB48_SEL; -#if AT32_SYSTICK_CLKSRC == AT32_SYSTICK_CLKSRC_HCLKDIV1 - SysTick->CTRL |= AT32_SYSTICK_CLKSRC_HCLKDIV1; -#else - SysTick->CTRL &= ~AT32_SYSTICK_CLKSRC_HCLKDIV1; -#endif - #endif /* !AT32_NO_INIT */ /* SYSCFG clock enabled here because it is a multi-functional unit shared among multiple drivers.*/ - CRM->APB2EN |= CRM_APB2EN_SCFGEN; - CRM->APB2LPEN |= CRM_APB2LPEN_SCFGLPEN; + crmEnableAPB2(CRM_APB2EN_SCFGEN, true); } - /** @} */ diff --git a/os/hal/ports/AT32/AT32F402_405/hal_lld.h b/os/hal/ports/AT32/AT32F402_405/hal_lld.h new file mode 100644 index 0000000000..03e6a26c5f --- /dev/null +++ b/os/hal/ports/AT32/AT32F402_405/hal_lld.h @@ -0,0 +1,1202 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + ChibiOS - Copyright (C) 2024..2025 Maxjta + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file AT32F402_405/hal_lld.h + * @brief AT32F402_405 HAL subsystem low level driver header. + * @pre This module requires the following macros to be defined in the + * @p board.h file: + * - AT32_LEXTCLK. + * - AT32_LEXT_BYPASS (optionally). + * - AT32_HEXTCLK. + * - AT32_HEXT_BYPASS (optionally). + * . + * One of the following macros must also be defined: + * - AT32F402KB, AT32F405KB for 32 pin Mainstream + Medium Density devices. + * - AT32F402KC, AT32F405KC for 32 pin Mainstream + High Density devices. + * - AT32F402CB, AT32F405CB for 48 pin Mainstream + Medium Density devices. + * - AT32F402CC, AT32F405CC for 48 pin Mainstream + High Density devices. + * - AT32F402RB, AT32F405RB for 64 pin Mainstream + Medium Density devices. + * - AT32F402RC, AT32F405RC for 64 pin Mainstream + High Density devices. + * . + * + * @addtogroup HAL + * @{ + */ + +#ifndef _HAL_LLD_H_ +#define _HAL_LLD_H_ + +#include "at32_registry.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Requires use of SPIv2 driver model. + */ +#define HAL_LLD_SELECT_SPI_V2 TRUE + +/** + * @name Platform identification + * @{ + */ +#if defined(__DOXYGEN__) +#define PLATFORM_NAME "AT32F402_405" + +#elif defined(AT32F402KB) || defined(AT32F405KB) +#define PLATFORM_NAME "AT32F402_405K Mainstream Line Medium Density" + +#elif defined(AT32F402KC) || defined(AT32F405KC) +#define PLATFORM_NAME "AT32F402_405K Mainstream Line High Density" + +#elif defined(AT32F402CB) || defined(AT32F405CB) +#define PLATFORM_NAME "AT32F402_405C Mainstream Line Medium Density" + +#elif defined(AT32F402CC) || defined(AT32F405CC) +#define PLATFORM_NAME "AT32F402_405C Mainstream Line High Density" + +#elif defined(AT32F402RB) || defined(AT32F405RB) +#define PLATFORM_NAME "AT32F402_405R Mainstream Line Medium Density" + +#elif defined(AT32F402RC) || defined(AT32F405RC) +#define PLATFORM_NAME "AT32F402_405R Mainstream Line High Density" + +#else +#error "unsupported or unrecognized AT32F402 or AT32F405 member" +#endif + +/** + * @brief Sub-family identifier. + */ +#if !defined(AT32F402_405) || defined(__DOXYGEN__) +#define AT32F402_405 +#endif +/** @} */ + +/** + * @name Absolute Maximum Ratings + * @{ + */ + +/** + * @brief Maximum system clock frequency. + */ +#define AT32_SYSCLK_MAX 216000000 + +/** + * @brief Maximum HEXT clock frequency. + */ +#define AT32_HEXTCLK_MAX 25000000 + +/** + * @brief Minimum HEXT clock frequency. + */ +#define AT32_HEXTCLK_MIN 4000000 + +/** + * @brief Maximum LEXT clock frequency. + */ +#define AT32_LEXTCLK_MAX 32768 + +/** + * @brief Minimum LEXT clock frequency. + */ +#define AT32_LEXTCLK_MIN 32768 + +/** + * @brief Maximum PLLs input clock frequency. + */ +#define AT32_PLLIN_MAX 16000000 + +/** + * @brief Minimum PLLs input clock frequency. + */ +#define AT32_PLLIN_MIN 2000000 + +/** + * @brief Maximum PLL output clock frequency. + */ +#define AT32_PLLOUT_MAX 216000000 + +/** + * @brief Minimum PLL output clock frequency. + */ +#define AT32_PLLOUT_MIN 4000000 + +/** + * @brief Maximum PLL VCO clock frequency. + */ +#define AT32_PLLVCO_MAX 1000000000 + +/** + * @brief Minimum PLL VCO clock frequency. + */ +#define AT32_PLLVCO_MIN 500000000 + +/** + * @brief Maximum APB1 clock frequency. + */ +#define AT32_PCLK1_MAX 120000000 + +/** + * @brief Maximum APB2 clock frequency. + */ +#define AT32_PCLK2_MAX 216000000 +/** @} */ + +/** + * @name Internal clock sources + * @{ + */ +#define AT32_HICKCLK 48000000 /**< High speed internal clock. */ +#define AT32_LICKCLK 40000 /**< Low speed internal clock. */ +/** @} */ + +/** + * @name PWC_CTRL register bits definitions + * @{ + */ +#define AT32_PVMSEL_MASK (7 << 5) /**< PVMSEL bits mask. */ +#define AT32_PVMSEL_LEV1 (1 << 5) /**< PVM level 1. */ +#define AT32_PVMSEL_LEV2 (2 << 5) /**< PVM level 2. */ +#define AT32_PVMSEL_LEV3 (3 << 5) /**< PVM level 3. */ +#define AT32_PVMSEL_LEV4 (4 << 5) /**< PVM level 4. */ +#define AT32_PVMSEL_LEV5 (5 << 5) /**< PVM level 5. */ +#define AT32_PVMSEL_LEV6 (6 << 5) /**< PVM level 6. */ +#define AT32_PVMSEL_LEV7 (7 << 5) /**< PVM level 7. */ +/** @} */ + +/** + * @name PWC_LDOOV register bits definitions + * @{ + */ +#define AT32_LDOOVSEL_LEV0 (0 << 0) /**< LDOOVSEL level 0. */ +#define AT32_LDOOVSEL_LEV2 (2 << 0) /**< LDOOVSEL level 2. */ +#define AT32_LDOOVSEL_LEV3 (3 << 0) /**< LDOOVSEL level 3. */ +/** @} */ + +/** + * @name CRM_PLLCFG register bits definitions + * @{ + */ +#define AT32_PLL_FP_DIV1 (0 << 16) /**< PLL clock divided by 1. */ +#define AT32_PLL_FP_DIV2 (1 << 16) /**< PLL clock divided by 2. */ +#define AT32_PLL_FP_DIV4 (2 << 16) /**< PLL clock divided by 4. */ +#define AT32_PLL_FP_DIV6 (3 << 16) /**< PLL clock divided by 6. */ +#define AT32_PLL_FP_DIV8 (4 << 16) /**< PLL clock divided by 8. */ +#define AT32_PLL_FP_DIV10 (5 << 16) /**< PLL clock divided by 10. */ +#define AT32_PLL_FP_DIV12 (6 << 16) /**< PLL clock divided by 12. */ +#define AT32_PLL_FP_DIV14 (7 << 16) /**< PLL clock divided by 14. */ +#define AT32_PLL_FP_DIV16 (8 << 16) /**< PLL clock divided by 16. */ +#define AT32_PLL_FP_DIV18 (9 << 16) /**< PLL clock divided by 18. */ +#define AT32_PLL_FP_DIV20 (10 << 16) /**< PLL clock divided by 20. */ +#define AT32_PLL_FP_DIV22 (11 << 16) /**< PLL clock divided by 22. */ +#define AT32_PLL_FP_DIV24 (12 << 16) /**< PLL clock divided by 24. */ +#define AT32_PLL_FP_DIV26 (13 << 16) /**< PLL clock divided by 26. */ +#define AT32_PLL_FP_DIV28 (14 << 16) /**< PLL clock divided by 28. */ +#define AT32_PLL_FP_DIV30 (15 << 16) /**< PLL clock divided by 30. */ + +#define AT32_PLL_FU_DIV11 (0 << 20) /**< PLLU clock divided by 11. */ +#define AT32_PLL_FU_DIV13 (1 << 20) /**< PLLU clock divided by 13. */ +#define AT32_PLL_FU_DIV12 (2 << 20) /**< PLLU clock divided by 12. */ +#define AT32_PLL_FU_DIV14 (3 << 20) /**< PLLU clock divided by 14. */ +#define AT32_PLL_FU_DIV16 (4 << 20) /**< PLLU clock divided by 16. */ +#define AT32_PLL_FU_DIV18 (5 << 20) /**< PLLU clock divided by 18. */ +#define AT32_PLL_FU_DIV20 (6 << 20) /**< PLLU clock divided by 20. */ + +#define AT32_PLLRCS_HICK (0 << 30) /**< PLL clock source is HICK. */ +#define AT32_PLLRCS_HEXT (1 << 30) /**< PLL clock source is HEXT. */ +/** @} */ + +/** + * @name CRM_CFG register bits definitions + * @{ + */ +#define AT32_SCLKSEL_HICK (0 << 0) /**< SCLK source is HICK. */ +#define AT32_SCLKSEL_HEXT (1 << 0) /**< SCLK source is HEXT. */ +#define AT32_SCLKSEL_PLL (2 << 0) /**< SCLK source is PLL. */ + +#define AT32_SCLKSTS_HICK (0 << 2) /**< SCLK use HICK. */ +#define AT32_SCLKSTS_HEXT (1 << 2) /**< SCLK use HEXT. */ +#define AT32_SCLKSTS_PLL (2 << 2) /**< SCLK use PLL. */ + +#define AT32_AHBDIV_DIV1 (0 << 4) /**< SCLK divided by 1. */ +#define AT32_AHBDIV_DIV2 (8 << 4) /**< SCLK divided by 2. */ +#define AT32_AHBDIV_DIV4 (9 << 4) /**< SCLK divided by 4. */ +#define AT32_AHBDIV_DIV8 (10 << 4) /**< SCLK divided by 8. */ +#define AT32_AHBDIV_DIV16 (11 << 4) /**< SCLK divided by 16. */ +#define AT32_AHBDIV_DIV64 (12 << 4) /**< SCLK divided by 64. */ +#define AT32_AHBDIV_DIV128 (13 << 4) /**< SCLK divided by 128. */ +#define AT32_AHBDIV_DIV256 (14 << 4) /**< SCLK divided by 256. */ +#define AT32_AHBDIV_DIV512 (15 << 4) /**< SCLK divided by 512. */ + +#define AT32_APB1DIV_DIV1 (0 << 10) /**< HCLK divided by 1. */ +#define AT32_APB1DIV_DIV2 (4 << 10) /**< HCLK divided by 2. */ +#define AT32_APB1DIV_DIV4 (5 << 10) /**< HCLK divided by 4. */ +#define AT32_APB1DIV_DIV8 (6 << 10) /**< HCLK divided by 8. */ +#define AT32_APB1DIV_DIV16 (7 << 10) /**< HCLK divided by 16. */ + +#define AT32_APB2DIV_DIV1 (0 << 13) /**< HCLK divided by 1. */ +#define AT32_APB2DIV_DIV2 (4 << 13) /**< HCLK divided by 2. */ +#define AT32_APB2DIV_DIV4 (5 << 13) /**< HCLK divided by 4. */ +#define AT32_APB2DIV_DIV8 (6 << 13) /**< HCLK divided by 8. */ +#define AT32_APB2DIV_DIV16 (7 << 13) /**< HCLK divided by 16. */ + +#define AT32_I2SF5CLKSEL_SCLK (0 << 22) /**< I2SF5CLKSEL is SCLK. */ +#define AT32_I2SF5CLKSEL_PLL (1 << 22) /**< I2SF5CLKSEL is PLL. */ +#define AT32_I2SF5CLKSEL_HICK (2 << 22) /**< I2SF5CLKSEL is HICK. */ +#define AT32_I2SF5CLKSEL_EXTERNAL (3 << 22) /**< I2SF5CLKSEL is External input CLK. */ + +#define AT32_CLKOUTDIV1_DIV1 (0 << 27) /**< CLKOUT_SEL1 divided by 1. */ +#define AT32_CLKOUTDIV1_DIV2 (4 << 27) /**< CLKOUT_SEL1 divided by 2. */ +#define AT32_CLKOUTDIV1_DIV3 (5 << 27) /**< CLKOUT_SEL1 divided by 3. */ +#define AT32_CLKOUTDIV1_DIV4 (6 << 27) /**< CLKOUT_SEL1 divided by 4. */ +#define AT32_CLKOUTDIV1_DIV5 (7 << 27) /**< CLKOUT_SEL1 divided by 5. */ + +#define AT32_CLKOUT_SEL_CFG_MASK (3 << 30) /**< CLKOUT_SEL1 pin on CRM_CFG mask. */ +#define AT32_CLKOUT_SEL_SCLK (0 << 30) /**< SCLK on CLKOUT_SEL1 pin. */ +#define AT32_CLKOUT_SEL_HEXT (2 << 30) /**< HEXT clock on CLKOUT_SEL1 pin. */ +#define AT32_CLKOUT_SEL_PLL (3 << 30) /**< PLL clock on CLKOUT_SEL1 pin. */ +/** @} */ + +/** + * @name CRM_BPDC register bits definitions + * @{ + */ +#define AT32_ERTCSEL_MASK (3 << 8) /**< ERTC clock source mask. */ +#define AT32_ERTCSEL_NOCLOCK (0 << 8) /**< No clock. */ +#define AT32_ERTCSEL_LEXT (1 << 8) /**< LEXT used as ERTC clock. */ +#define AT32_ERTCSEL_LICK (2 << 8) /**< LICK used as ERTC clock. */ +#define AT32_ERTCSEL_HEXTDIV (3 << 8) /**< HEXT divided used as ERTC clock. */ +/** @} */ + +/** + * @name CRM_MISC1 register bits definitions + * @{ + */ +#define AT32_HICKDIV_MASK (1 << 12) /**< HICKDIV mask. */ +#define AT32_HICKDIV_DIV6 (0 << 12) /**< HICK divided by 6. */ +#define AT32_HICKDIV_DIV1 (1 << 12) /**< HICK divided by 1. */ + +#define AT32_HICK_TO_SCLK_MASK (1 << 14) /**< HICK_TO_SCLK mask. */ +#define AT32_HICK_TO_SCLK_8M (0 << 14) /**< SCLK is 8 MHz if SCLK is HICK. */ +#define AT32_HICK_TO_SCLK_48M (1 << 14) /**< SCLK is 48 MHz if SCLK is HICK. */ + +#define AT32_CLKOUT_SEL_MISC1_MASK (15 << 16) /**< CLKOUT_SEL2 pin on CRM_MISC1 mask. */ +#define AT32_CLKOUT_SEL_USBFS ((1 << 30) | (0 << 16)) + /**< USBFS clock on CLKOUT_SEL2 pin. */ +#define AT32_CLKOUT_SEL_ADC ((1 << 30) | (1 << 16)) + /**< ADC clock on CLKOUT_SEL2 pin. */ +#define AT32_CLKOUT_SEL_HICK ((1 << 30) | (2 << 16)) + /**< HICK clock on CLKOUT_SEL2 pin. */ +#define AT32_CLKOUT_SEL_LICK ((1 << 30) | (3 << 16)) + /**< LICK clock on CLKOUT_SEL2 pin. */ +#define AT32_CLKOUT_SEL_LEXT ((1 << 30) | (4 << 16)) + /**< LEXT clock on CLKOUT_SEL2 pin. */ +#define AT32_CLKOUT_SEL_USBHS ((1 << 30) | (5 << 16)) + /**< USBHS clock on CLKOUT_SEL2 pin. */ + +#define AT32_CLKOUTDIV2_DIV1 (0 << 28) /**< CLKOUT_SEL2 divided by 1. */ +#define AT32_CLKOUTDIV2_DIV2 (8 << 28) /**< CLKOUT_SEL2 divided by 2. */ +#define AT32_CLKOUTDIV2_DIV4 (9 << 28) /**< CLKOUT_SEL2 divided by 4. */ +#define AT32_CLKOUTDIV2_DIV8 (10 << 28) /**< CLKOUT_SEL2 divided by 8. */ +#define AT32_CLKOUTDIV2_DIV16 (11 << 28) /**< CLKOUT_SEL2 divided by 16. */ +#define AT32_CLKOUTDIV2_DIV64 (12 << 28) /**< CLKOUT_SEL2 divided by 64. */ +#define AT32_CLKOUTDIV2_DIV128 (13 << 28) /**< CLKOUT_SEL2 divided by 128. */ +#define AT32_CLKOUTDIV2_DIV256 (14 << 28) /**< CLKOUT_SEL2 divided by 256. */ +#define AT32_CLKOUTDIV2_DIV512 (15 << 28) /**< CLKOUT_SEL2 divided by 512. */ +/** @} */ + +/** + * @name CRM_MISC2 register bits definitions + * @{ + */ +#define AT32_PLLU_USB48_SEL_MASK (1 << 10) /**< PLLU_USB48_SEL mask. */ +#define AT32_PLLU_USB48_SEL_PLLU (0 << 10) /**< PLLU_USB48_SEL source is PLLU. */ +#define AT32_PLLU_USB48_SEL_HICK (1 << 10) /**< PLLU_USB48_SEL source is HICK. */ + +#define AT32_HICK_TO_SCLK_DIV_MASK (7 << 16) /**< HICK_TO_SCLK divided mask. */ +#define AT32_HICK_TO_SCLK_DIV_DIV1 (0 << 16) /**< HICK divided by 1. */ +#define AT32_HICK_TO_SCLK_DIV_DIV2 (1 << 16) /**< HICK divided by 2. */ +#define AT32_HICK_TO_SCLK_DIV_DIV4 (2 << 16) /**< HICK divided by 4. */ +#define AT32_HICK_TO_SCLK_DIV_DIV8 (3 << 16) /**< HICK divided by 8. */ +#define AT32_HICK_TO_SCLK_DIV_DIV16 (4 << 16) /**< HICK divided by 16. */ + +#define AT32_HEXT_TO_SCLK_DIV_MASK (7 << 19) /**< HEXT_TO_SCLK divided mask. */ +#define AT32_HEXT_TO_SCLK_DIV_DIV1 (0 << 19) /**< HEXT divided by 1. */ +#define AT32_HEXT_TO_SCLK_DIV_DIV2 (1 << 19) /**< HEXT divided by 2. */ +#define AT32_HEXT_TO_SCLK_DIV_DIV4 (2 << 19) /**< HEXT divided by 4. */ +#define AT32_HEXT_TO_SCLK_DIV_DIV8 (3 << 19) /**< HEXT divided by 8. */ +#define AT32_HEXT_TO_SCLK_DIV_DIV16 (4 << 19) /**< HEXT divided by 16. */ +#define AT32_HEXT_TO_SCLK_DIV_DIV32 (5 << 19) /**< HEXT divided by 32. */ +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief Disables the PWC/CRM initialization in the HAL. + */ +#if !defined(AT32_NO_INIT) || defined(__DOXYGEN__) +#define AT32_NO_INIT FALSE +#endif + +/** + * @brief Enables or disables the power voltage monitoring. + */ +#if !defined(AT32_PVM_ENABLE) || defined(__DOXYGEN__) +#define AT32_PVM_ENABLE FALSE +#endif + +/** + * @brief Sets voltage level for power voltage monitoring. + */ +#if !defined(AT32_PVMSEL) || defined(__DOXYGEN__) +#define AT32_PVMSEL AT32_PVMSEL_LEV1 +#endif + +/** + * @brief Sets voltage level for voltage regulator output. + */ +#if !defined(AT32_LDOOVSEL) || defined(__DOXYGEN__) +#define AT32_LDOOVSEL AT32_LDOOVSEL_LEV3 +#endif + +/** + * @brief Enables or disables the HICK clock source. + */ +#if !defined(AT32_HICK_ENABLED) || defined(__DOXYGEN__) +#define AT32_HICK_ENABLED TRUE +#endif + +/** + * @brief Enables or disables the LICK clock source. + */ +#if !defined(AT32_LICK_ENABLED) || defined(__DOXYGEN__) +#define AT32_LICK_ENABLED FALSE +#endif + +/** + * @brief Enables or disables the HEXT clock source. + */ +#if !defined(AT32_HEXT_ENABLED) || defined(__DOXYGEN__) +#define AT32_HEXT_ENABLED TRUE +#endif + +/** + * @brief Enables or disables the LEXT clock source. + */ +#if !defined(AT32_LEXT_ENABLED) || defined(__DOXYGEN__) +#define AT32_LEXT_ENABLED FALSE +#endif + +/** + * @brief Enables or disables the PLLU clock source. + */ +#if !defined(AT32_PLLU_ENABLED) || defined(__DOXYGEN__) +#define AT32_PLLU_ENABLED TRUE +#endif + +/** + * @brief Main clock source selection. + * @note If the selected clock source is not the PLL then the PLL is not + * initialized and started. + * @note The default value is calculated for a 216MHz system clock from + * a 12MHz crystal using the PLL. + */ +#if !defined(AT32_SCLKSEL) || defined(__DOXYGEN__) +#define AT32_SCLKSEL AT32_SCLKSEL_PLL +#endif + +/** + * @brief Clock source for the PLL. + * @note This setting has only effect if the PLL is selected as the + * system clock source. + * @note The default value is calculated for a 216MHz system clock from + * a 12MHz crystal using the PLL. + */ +#if !defined(AT32_PLLRCS) || defined(__DOXYGEN__) +#define AT32_PLLRCS AT32_PLLRCS_HEXT +#endif + +/** + * @brief PLL MS divider value. + * @note The allowed values are 1..15. + * @note The default value is calculated for a 216MHz system clock from + * a 12MHz crystal using the PLL. + */ +#if !defined(AT32_PLL_MS_VALUE) || defined(__DOXYGEN__) +#define AT32_PLL_MS_VALUE 1 +#endif + +/** + * @brief PLL NS multiplier value. + * @note The allowed values are 31..500. + * @note The default value is calculated for a 216MHz system clock from + * a 12MHz crystal using the PLL. + */ +#if !defined(AT32_PLL_NS_VALUE) || defined(__DOXYGEN__) +#define AT32_PLL_NS_VALUE 72 +#endif + +/** + * @brief PLL FP divider value. + * @note The allowed values are 1, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, + * 22, 24, 26, 28, 30. + * @note The default value is calculated for a 216MHz system clock from + * a 12MHz crystal using the PLL. + */ +#if !defined(AT32_PLL_FP_VALUE) || defined(__DOXYGEN__) +#define AT32_PLL_FP_VALUE 4 +#endif + +/** + * @brief PLL FU divider value. + * @note The allowed values are 11, 12, 13, 14, 16, 18, 20. + * @note The default value is calculated for a 216MHz system clock from + * a 12MHz crystal using the PLL. + */ +#if !defined(AT32_PLL_FU_VALUE) || defined(__DOXYGEN__) +#define AT32_PLL_FU_VALUE 18 +#endif + +/** + * @brief AHB prescaler value. + * @note The default value is calculated for a 216MHz system clock from + * a 12MHz crystal using the PLL. + */ +#if !defined(AT32_AHBDIV) || defined(__DOXYGEN__) +#define AT32_AHBDIV AT32_AHBDIV_DIV1 +#endif + +/** + * @brief APB1 prescaler value. + */ +#if !defined(AT32_APB1DIV) || defined(__DOXYGEN__) +#define AT32_APB1DIV AT32_APB1DIV_DIV2 +#endif + +/** + * @brief APB2 prescaler value. + */ +#if !defined(AT32_APB2DIV) || defined(__DOXYGEN__) +#define AT32_APB2DIV AT32_APB2DIV_DIV1 +#endif + +/** + * @brief HICK source selection if SCLK is HICK. + */ +#if !defined(AT32_HICK_TO_SCLK) || defined(__DOXYGEN__) +#define AT32_HICK_TO_SCLK AT32_HICK_TO_SCLK_48M +#endif + +/** + * @brief HICK prescaler selection. + */ +#if !defined(AT32_HICKDIV) || defined(__DOXYGEN__) +#define AT32_HICKDIV AT32_HICKDIV_DIV1 +#endif + +/** + * @brief HICK prescaler value when SCLK is HICK. + */ +#if !defined(AT32_HICK_TO_SCLK_DIV) || defined(__DOXYGEN__) +#define AT32_HICK_TO_SCLK_DIV AT32_HICK_TO_SCLK_DIV_DIV1 +#endif + +/** + * @brief HEXT prescaler value when SCLK is HEXT. + */ +#if !defined(AT32_HEXT_TO_SCLK_DIV) || defined(__DOXYGEN__) +#define AT32_HEXT_TO_SCLK_DIV AT32_HEXT_TO_SCLK_DIV_DIV1 +#endif + +/** + * @brief USB clock setting. + */ +#if !defined(AT32_USB_CLOCK48_REQUIRED) || defined(__DOXYGEN__) +#define AT32_USB_CLOCK48_REQUIRED TRUE +#endif + +/** + * @brief USB clock source selection. + */ +#if !defined(AT32_PLLU_USB48_SEL) || defined(__DOXYGEN__) +#define AT32_PLLU_USB48_SEL AT32_PLLU_USB48_SEL_PLLU +#endif + +/** + * @brief CLKOUT_SEL pin setting. + */ +#if !defined(AT32_CLKOUT_SEL) || defined(__DOXYGEN__) +#define AT32_CLKOUT_SEL AT32_CLKOUT_SEL_HICK +#endif + +/** + * @brief CLKOUT_SEL1 prescaler value. + */ +#if !defined(AT32_CLKOUTDIV1) || defined(__DOXYGEN__) +#define AT32_CLKOUTDIV1 AT32_CLKOUTDIV1_DIV1 +#endif + +/** + * @brief CLKOUT_SEL2 prescaler value. + */ +#if !defined(AT32_CLKOUTDIV2) || defined(__DOXYGEN__) +#define AT32_CLKOUTDIV2 AT32_CLKOUTDIV2_DIV1 +#endif + +/** + * @brief ERTC clock source. + */ +#if !defined(AT32_ERTCSEL) || defined(__DOXYGEN__) +#define AT32_ERTCSEL AT32_ERTCSEL_NOCLOCK +#endif + +/** + * @brief ERTC HEXT prescaler value. + * @note The allowed values are 2..31. + */ +#if !defined(AT32_ERTCDIV_VALUE) || defined(__DOXYGEN__) +#define AT32_ERTCDIV_VALUE 12 +#endif + +/** + * @brief I2SF5 clock source. + */ +#if !defined(AT32_I2SF5CLKSEL) || defined(__DOXYGEN__) +#define AT32_I2SF5CLKSEL AT32_I2SF5CLKSEL_SCLK +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* + * Configuration-related checks. + */ +#if defined(AT32F402KB) || defined(AT32F402KC) || defined(AT32F402CB) || \ + defined(AT32F402CC) || defined(AT32F402RB) || defined(AT32F402RC) +#if !defined(AT32F402_MCUCONF) +#error "Using a wrong mcuconf.h file, AT32F402_MCUCONF not defined" +#endif +#elif defined(AT32F405KB) || defined(AT32F405KC) || defined(AT32F405CB) || \ + defined(AT32F405CC) || defined(AT32F405RB) || defined(AT32F405RC) +#if !defined(AT32F405_MCUCONF) +#error "Using a wrong mcuconf.h file, AT32F405_MCUCONF not defined" +#endif +#endif + +/* + * Board files sanity checks. + */ +#if !defined(AT32_LEXTCLK) +#error "AT32_LEXTCLK not defined in board.h" +#endif + +#if !defined(AT32_HEXTCLK) +#error "AT32_HEXTCLK not defined in board.h" +#endif + +/* + * HICK related checks. + */ +#if AT32_HICK_ENABLED +#else /* !AT32_HICK_ENABLED */ + +#if AT32_SCLKSEL == AT32_SCLKSEL_HICK +#error "HICK not enabled, required by AT32_SCLKSEL" +#endif + +#if ((AT32_SCLKSEL == AT32_SCLKSEL_HICK) && \ + (AT32_PLLRCS == AT32_PLLRCS_HICK)) +#error "HICK not enabled, required by AT32_SCLKSEL and AT32_PLLRCS" +#endif + +#if (AT32_CLKOUT_SEL == AT32_CLKOUT_SEL_HICK) || \ + ((AT32_CLKOUT_SEL == AT32_CLKOUT_SEL_PLL) && \ + (AT32_PLLRCS == AT32_PLLRCS_HICK)) +#error "HICK not enabled, required by AT32_CLKOUT_SEL" +#endif + +#if (AT32_PLLU_USB48_SEL == AT32_PLLU_USB48_SEL_HICK) || \ + ((AT32_PLLU_USB48_SEL == AT32_PLLU_USB48_SEL_PLLU) && \ + (AT32_PLLRCS == AT32_PLLRCS_HICK)) +#error "HICK not enabled, required by AT32_PLLU_USB48_SEL" +#endif + +#if (AT32_I2SF5CLKSEL == AT32_I2SF5CLKSEL_HICK) || \ + ((AT32_I2SF5CLKSEL == AT32_I2SF5CLKSEL_PLL) && \ + (AT32_PLLRCS == AT32_PLLRCS_HICK)) || \ + ((AT32_I2SF5CLKSEL == AT32_I2SF5CLKSEL_SCLK) && \ + (AT32_SCLKSEL == AT32_SCLKSEL_HICK)) || \ + ((AT32_I2SF5CLKSEL == AT32_I2SF5CLKSEL_SCLK) && \ + (AT32_SCLKSEL == AT32_SCLKSEL_PLL) && \ + (AT32_PLLRCS == AT32_PLLRCS_HICK)) +#error "HICK not enabled, required by AT32_I2SF5CLKSEL" +#endif + +#endif /* !AT32_HICK_ENABLED */ + +/* + * HEXT related checks. + */ +#if AT32_HEXT_ENABLED + +#if AT32_HEXTCLK == 0 +#error "HEXT frequency not defined" +#elif (AT32_HEXTCLK < AT32_HEXTCLK_MIN) || (AT32_HEXTCLK > AT32_HEXTCLK_MAX) +#error "AT32_HEXTCLK outside acceptable range (AT32_HEXTCLK_MIN...AT32_HEXTCLK_MAX)" +#endif + +#else /* !AT32_HEXT_ENABLED */ + +#if AT32_SCLKSEL == AT32_SCLKSEL_HEXT +#error "HEXT not enabled, required by AT32_SCLKSEL" +#endif + +#if ((AT32_SCLKSEL == AT32_SCLKSEL_PLL) && (AT32_PLLRCS == AT32_PLLRCS_HEXT)) +#error "HEXT not enabled, required by AT32_SCLKSEL and AT32_PLLRCS" +#endif + +#if (AT32_CLKOUT_SEL == AT32_CLKOUT_SEL_HEXT) || \ + ((AT32_CLKOUT_SEL == AT32_CLKOUT_SEL_PLL) && \ + (AT32_PLLRCS == AT32_PLLRCS_HEXT)) +#error "HEXT not enabled, required by AT32_CLKOUT_SEL" +#endif + +#if AT32_ERTCSEL == AT32_ERTCSEL_HEXTDIV +#error "HEXT not enabled, required by AT32_ERTCSEL" +#endif + +#if ((AT32_I2SF5CLKSEL == AT32_I2SF5CLKSEL_PLL) && \ + (AT32_PLLRCS == AT32_PLLRCS_HEXT)) || \ + ((AT32_I2SF5CLKSEL == AT32_I2SF5CLKSEL_SCLK) && \ + (AT32_SCLKSEL == AT32_SCLKSEL_HEXT)) || \ + ((AT32_I2SF5CLKSEL == AT32_I2SF5CLKSEL_SCLK) && \ + (AT32_SCLKSEL == AT32_SCLKSEL_PLL) && \ + (AT32_PLLRCS == AT32_PLLRCS_HEXT)) +#error "HEXT not enabled, required by AT32_I2SF5CLKSEL" +#endif + +#endif /* !AT32_HEXT_ENABLED */ + +/* + * LICK related checks. + */ +#if AT32_LICK_ENABLED +#else /* !AT32_LICK_ENABLED */ + +#if AT32_CLKOUT_SEL == AT32_CLKOUT_SEL_LICK +#error "LICK not enabled, required by AT32_CLKOUT_SEL" +#endif + +#if HAL_USE_RTC && (AT32_ERTCSEL == AT32_ERTCSEL_LICK) +#error "LICK not enabled, required by AT32_ERTCSEL" +#endif +#endif /* !AT32_LICK_ENABLED */ + +/* + * LEXT related checks. + */ +#if AT32_LEXT_ENABLED + +#if (AT32_LEXTCLK == 0) +#error "LEXT frequency not defined" +#elif (AT32_LEXTCLK < AT32_LEXTCLK_MIN) || (AT32_LEXTCLK > AT32_LEXTCLK_MAX) +#error "AT32_LEXTCLK outside acceptable range (AT32_LEXTCLK_MIN...AT32_LEXTCLK_MAX)" +#endif + +#else /* !AT32_LEXT_ENABLED */ + +#if AT32_CLKOUT_SEL == AT32_CLKOUT_SEL_LEXT +#error "LEXT not enabled, required by AT32_CLKOUT_SEL" +#endif + +#if AT32_ERTCSEL == AT32_ERTCSEL_LEXT +#error "LEXT not enabled, required by AT32_ERTCSEL" +#endif + +#endif /* !AT32_LEXT_ENABLED */ + +/* + * PLLU related checks. + */ +#if AT32_PLLU_ENABLED +#else /* !AT32_PLLU_ENABLED */ + +#if AT32_PLLU_USB48_SEL == AT32_PLLU_USB48_SEL_PLLU +#error "PLLU not enabled, required by AT32_PLLU_USB48_SEL" +#endif +#endif /* !AT32_PLLU_ENABLED */ + +/* + * PLL enable check. + */ +#if (AT32_USB_CLOCK48_REQUIRED && \ + (AT32_PLLU_USB48_SEL == AT32_PLLU_USB48_SEL_PLLU)) || \ + (AT32_SCLKSEL == AT32_SCLKSEL_PLL) || \ + (AT32_I2SF5CLKSEL == AT32_I2SF5CLKSEL_PLL) || \ + (AT32_CLKOUT_SEL == AT32_CLKOUT_SEL_PLL) || \ + (AT32_PLLU_ENABLED) || defined(__DOXYGEN__) + +/** + * @brief PLL activation flag. + */ +#define AT32_ACTIVATE_PLL TRUE +#else +#define AT32_ACTIVATE_PLL FALSE +#endif + +/** + * @brief PLL input clock frequency. + */ +#if (AT32_PLLRCS == AT32_PLLRCS_HEXT) || defined(__DOXYGEN__) +#define AT32_PLLCLKIN (AT32_HEXTCLK / AT32_PLL_MS_VALUE) +#elif AT32_PLLRCS == AT32_PLLRCS_HICK +#define AT32_PLLCLKIN ((AT32_HICKCLK / 6) / AT32_PLL_MS_VALUE) +#else +#error "invalid AT32_PLLRCS value specified" +#endif + +/* PLL input frequency range check.*/ +#if (AT32_PLLCLKIN < AT32_PLLIN_MIN) || (AT32_PLLCLKIN > AT32_PLLIN_MAX) +#error "AT32_PLLCLKIN outside acceptable range (AT32_PLLIN_MIN...AT32_PLLIN_MAX)" +#endif + +/** + * @brief AT32_PLL_MS field. + */ +#if ((AT32_PLL_MS_VALUE >= 1) && (AT32_PLL_MS_VALUE <= 15)) || \ + defined(__DOXYGEN__) +#define AT32_PLL_MS (AT32_PLL_MS_VALUE << 0) +#else +#error "invalid AT32_PLL_MS_VALUE value specified" +#endif + +/** + * @brief AT32_PLL_NS field. + */ +#if ((AT32_PLL_NS_VALUE >= 31) && (AT32_PLL_NS_VALUE <= 500)) || \ + defined(__DOXYGEN__) +#define AT32_PLL_NS (AT32_PLL_NS_VALUE << 6) +#else +#error "invalid AT32_PLL_NS_VALUE value specified" +#endif + +/** + * @brief AT32_PLL_FP field. + */ +#if (AT32_PLL_FP_VALUE == 1) || defined(__DOXYGEN__) +#define AT32_PLL_FP AT32_PLL_FP_DIV1 +#elif AT32_PLL_FP_VALUE == 2 +#define AT32_PLL_FP AT32_PLL_FP_DIV2 +#elif AT32_PLL_FP_VALUE == 4 +#define AT32_PLL_FP AT32_PLL_FP_DIV4 +#elif AT32_PLL_FP_VALUE == 6 +#define AT32_PLL_FP AT32_PLL_FP_DIV6 +#elif AT32_PLL_FP_VALUE == 8 +#define AT32_PLL_FP AT32_PLL_FP_DIV8 +#elif AT32_PLL_FP_VALUE == 10 +#define AT32_PLL_FP AT32_PLL_FP_DIV10 +#elif AT32_PLL_FP_VALUE == 12 +#define AT32_PLL_FP AT32_PLL_FP_DIV12 +#elif AT32_PLL_FP_VALUE == 14 +#define AT32_PLL_FP AT32_PLL_FP_DIV14 +#elif AT32_PLL_FP_VALUE == 16 +#define AT32_PLL_FP AT32_PLL_FP_DIV16 +#elif AT32_PLL_FP_VALUE == 18 +#define AT32_PLL_FP AT32_PLL_FP_DIV18 +#elif AT32_PLL_FP_VALUE == 20 +#define AT32_PLL_FP AT32_PLL_FP_DIV20 +#elif AT32_PLL_FP_VALUE == 22 +#define AT32_PLL_FP AT32_PLL_FP_DIV22 +#elif AT32_PLL_FP_VALUE == 24 +#define AT32_PLL_FP AT32_PLL_FP_DIV24 +#elif AT32_PLL_FP_VALUE == 26 +#define AT32_PLL_FP AT32_PLL_FP_DIV26 +#elif AT32_PLL_FP_VALUE == 28 +#define AT32_PLL_FP AT32_PLL_FP_DIV28 +#elif AT32_PLL_FP_VALUE == 30 +#define AT32_PLL_FP AT32_PLL_FP_DIV30 +#else +#error "invalid AT32_PLL_FP_VALUE value specified" +#endif + +/** + * @brief AT32_PLL_FU field. + */ +#if (AT32_PLL_FU_VALUE == 11) || defined(__DOXYGEN__) +#define AT32_PLL_FU AT32_PLL_FU_DIV11 +#elif AT32_PLL_FU_VALUE == 12 +#define AT32_PLL_FU AT32_PLL_FU_DIV12 +#elif AT32_PLL_FU_VALUE == 13 +#define AT32_PLL_FU AT32_PLL_FU_DIV13 +#elif AT32_PLL_FU_VALUE == 14 +#define AT32_PLL_FU AT32_PLL_FU_DIV14 +#elif AT32_PLL_FU_VALUE == 16 +#define AT32_PLL_FU AT32_PLL_FU_DIV16 +#elif AT32_PLL_FU_VALUE == 18 +#define AT32_PLL_FU AT32_PLL_FU_DIV18 +#elif AT32_PLL_FU_VALUE == 20 +#define AT32_PLL_FU AT32_PLL_FU_DIV20 +#else +#error "invalid AT32_PLL_FU_VALUE value specified" +#endif + +/** + * @brief PLL VCO frequency. + */ +#define AT32_PLLVCO (AT32_PLLCLKIN * AT32_PLL_NS_VALUE) + +/* PLL VCO frequency range check.*/ +#if (AT32_PLLVCO < AT32_PLLVCO_MIN) || (AT32_PLLVCO > AT32_PLLVCO_MAX) +#error "AT32_PLLVCO outside acceptable range (AT32_PLLVCO_MIN...AT32_PLLVCO_MAX)" +#endif + +/** + * @brief PLL PCLK output clock frequency. + */ +#define AT32_PLLPCLK (AT32_PLLVCO / AT32_PLL_FP_VALUE) + +/* PLL PCLK frequency range check.*/ +#if (AT32_PLLPCLK < AT32_PLLOUT_MIN) || (AT32_PLLPCLK > AT32_PLLOUT_MAX) +#error "AT32_PLLPCLK outside acceptable range (AT32_PLLOUT_MIN...AT32_PLLOUT_MAX)" +#endif + +/** + * @brief PLL UCLK output clock frequency. + */ +#define AT32_PLLUCLK (AT32_PLLVCO / AT32_PLL_FU_VALUE) + +/* PLL UCLK frequency range check.*/ +#if (AT32_PLLUCLK < AT32_PLLOUT_MIN) || (AT32_PLLUCLK > AT32_PLLOUT_MAX) +#error "AT32_PLLUCLK outside acceptable range (AT32_PLLOUT_MIN...AT32_PLLOUT_MAX)" +#endif + +/** + * @brief HICK output clock frequency. + */ +#if (AT32_HICKDIV == AT32_HICKDIV_DIV1) || defined(__DOXYGEN__) +#define AT32_HICKCLKOUT (AT32_HICKCLK / 1) +#elif AT32_HICKDIV == AT32_HICKDIV_DIV6 +#define AT32_HICKCLKOUT (AT32_HICKCLK / 6) +#else +#error "invalid AT32_HICKDIV value specified" +#endif + +/** + * @brief System clock source. + */ +#if AT32_SCLKSEL == AT32_SCLKSEL_HICK + +#if (AT32_HICK_TO_SCLK == AT32_HICK_TO_SCLK_8M) || defined(__DOXYGEN__) +#define AT32_SYSCLKIN 8000000 +#elif AT32_HICK_TO_SCLK == AT32_HICK_TO_SCLK_48M +#define AT32_SYSCLKIN AT32_HICKCLKOUT +#else +#error "invalid AT32_HICK_TO_SCLK value specified" +#endif + +#if (AT32_HICK_TO_SCLK_DIV == AT32_HICK_TO_SCLK_DIV_DIV1) || \ + defined(__DOXYGEN__) +#define AT32_SYSCLK (AT32_SYSCLKIN / 1) +#elif AT32_HICK_TO_SCLK_DIV == AT32_HICK_TO_SCLK_DIV_DIV2 +#define AT32_SYSCLK (AT32_SYSCLKIN / 2) +#elif AT32_HICK_TO_SCLK_DIV == AT32_HICK_TO_SCLK_DIV_DIV4 +#define AT32_SYSCLK (AT32_SYSCLKIN / 4) +#elif AT32_HICK_TO_SCLK_DIV == AT32_HICK_TO_SCLK_DIV_DIV8 +#define AT32_SYSCLK (AT32_SYSCLKIN / 8) +#elif AT32_HICK_TO_SCLK_DIV == AT32_HICK_TO_SCLK_DIV_DIV16 +#define AT32_SYSCLK (AT32_SYSCLKIN / 16) +#else +#error "invalid AT32_HICK_TO_SCLK_DIV value specified" +#endif + +#elif AT32_SCLKSEL == AT32_SCLKSEL_HEXT + +#if (AT32_HEXT_TO_SCLK_DIV == AT32_HEXT_TO_SCLK_DIV_DIV1) || \ + defined(__DOXYGEN__) +#define AT32_SYSCLK (AT32_HEXTCLK / 1) +#elif AT32_HEXT_TO_SCLK_DIV == AT32_HEXT_TO_SCLK_DIV_DIV2 +#define AT32_SYSCLK (AT32_HEXTCLK / 2) +#elif AT32_HEXT_TO_SCLK_DIV == AT32_HEXT_TO_SCLK_DIV_DIV4 +#define AT32_SYSCLK (AT32_HEXTCLK / 4) +#elif AT32_HEXT_TO_SCLK_DIV == AT32_HEXT_TO_SCLK_DIV_DIV8 +#define AT32_SYSCLK (AT32_HEXTCLK / 8) +#elif AT32_HEXT_TO_SCLK_DIV == AT32_HEXT_TO_SCLK_DIV_DIV16 +#define AT32_SYSCLK (AT32_HEXTCLK / 16) +#elif AT32_HEXT_TO_SCLK_DIV == AT32_HEXT_TO_SCLK_DIV_DIV32 +#define AT32_SYSCLK (AT32_HEXTCLK / 32) +#else +#error "invalid AT32_HEXT_TO_SCLK_DIV value specified" +#endif + +#elif AT32_SCLKSEL == AT32_SCLKSEL_PLL +#define AT32_SYSCLK AT32_PLLPCLK +#else +#error "invalid AT32_SCLKSEL value specified" +#endif + +/* Check on the system clock.*/ +#if AT32_SYSCLK > AT32_SYSCLK_MAX +#error "AT32_SYSCLK exceeding maximum frequency (AT32_SYSCLK_MAX)" +#endif + +/** + * @brief AHB frequency. + */ +#if (AT32_AHBDIV == AT32_AHBDIV_DIV1) || defined(__DOXYGEN__) +#define AT32_HCLK (AT32_SYSCLK / 1) +#elif AT32_AHBDIV == AT32_AHBDIV_DIV2 +#define AT32_HCLK (AT32_SYSCLK / 2) +#elif AT32_AHBDIV == AT32_AHBDIV_DIV4 +#define AT32_HCLK (AT32_SYSCLK / 4) +#elif AT32_AHBDIV == AT32_AHBDIV_DIV8 +#define AT32_HCLK (AT32_SYSCLK / 8) +#elif AT32_AHBDIV == AT32_AHBDIV_DIV16 +#define AT32_HCLK (AT32_SYSCLK / 16) +#elif AT32_AHBDIV == AT32_AHBDIV_DIV64 +#define AT32_HCLK (AT32_SYSCLK / 64) +#elif AT32_AHBDIV == AT32_AHBDIV_DIV128 +#define AT32_HCLK (AT32_SYSCLK / 128) +#elif AT32_AHBDIV == AT32_AHBDIV_DIV256 +#define AT32_HCLK (AT32_SYSCLK / 256) +#elif AT32_AHBDIV == AT32_AHBDIV_DIV512 +#define AT32_HCLK (AT32_SYSCLK / 512) +#else +#error "invalid AT32_AHBDIV value specified" +#endif + +/* AHB frequency check.*/ +#if AT32_HCLK > AT32_SYSCLK_MAX +#error "AT32_HCLK exceeding maximum frequency (AT32_SYSCLK_MAX)" +#endif + +/** + * @brief APB1 frequency. + */ +#if (AT32_APB1DIV == AT32_APB1DIV_DIV1) || defined(__DOXYGEN__) +#define AT32_PCLK1 (AT32_HCLK / 1) +#elif AT32_APB1DIV == AT32_APB1DIV_DIV2 +#define AT32_PCLK1 (AT32_HCLK / 2) +#elif AT32_APB1DIV == AT32_APB1DIV_DIV4 +#define AT32_PCLK1 (AT32_HCLK / 4) +#elif AT32_APB1DIV == AT32_APB1DIV_DIV8 +#define AT32_PCLK1 (AT32_HCLK / 8) +#elif AT32_APB1DIV == AT32_APB1DIV_DIV16 +#define AT32_PCLK1 (AT32_HCLK / 16) +#else +#error "invalid AT32_APB1DIV value specified" +#endif + +/* APB1 frequency check.*/ +#if AT32_PCLK1 > AT32_PCLK1_MAX +#error "AT32_PCLK1 exceeding maximum frequency (AT32_PCLK1_MAX)" +#endif + +/** + * @brief APB2 frequency. + */ +#if (AT32_APB2DIV == AT32_APB2DIV_DIV1) || defined(__DOXYGEN__) +#define AT32_PCLK2 (AT32_HCLK / 1) +#elif AT32_APB2DIV == AT32_APB2DIV_DIV2 +#define AT32_PCLK2 (AT32_HCLK / 2) +#elif AT32_APB2DIV == AT32_APB2DIV_DIV4 +#define AT32_PCLK2 (AT32_HCLK / 4) +#elif AT32_APB2DIV == AT32_APB2DIV_DIV8 +#define AT32_PCLK2 (AT32_HCLK / 8) +#elif AT32_APB2DIV == AT32_APB2DIV_DIV16 +#define AT32_PCLK2 (AT32_HCLK / 16) +#else +#error "invalid AT32_APB2DIV value specified" +#endif + +/* APB2 frequency check.*/ +#if AT32_PCLK2 > AT32_PCLK2_MAX +#error "AT32_PCLK2 exceeding maximum frequency (AT32_PCLK2_MAX)" +#endif + +/* Check on LDOOVSEL value.*/ +#if AT32_LDOOVSEL == AT32_LDOOVSEL_LEV3 + +#if (AT32_HCLK > 216000000) || \ + (AT32_PCLK1 > 120000000) || \ + (AT32_PCLK2 > AT32_HCLK) +#error "AT32 bus clock exceeding maximum frequency when LDO is 1.3V" +#endif + +#elif AT32_LDOOVSEL == AT32_LDOOVSEL_LEV2 + +#if (AT32_HCLK > 168000000) || \ + (AT32_PCLK1 > 120000000) || \ + (AT32_PCLK2 > AT32_HCLK) +#error "AT32 bus clock exceeding maximum frequency when LDO is 1.2V" +#endif + +#elif AT32_LDOOVSEL == AT32_LDOOVSEL_LEV0 + +#if (AT32_HCLK > 108000000) || \ + (AT32_PCLK1 > AT32_HCLK) || \ + (AT32_PCLK2 > AT32_HCLK) +#error "AT32 bus clock exceeding maximum frequency when LDO is 1.0V" +#endif + +#else +#error "invalid AT32_LDOOVSEL value specified" +#endif + +/** + * @brief ERTC clock. + */ +#if (AT32_ERTCSEL == AT32_ERTCSEL_LEXT) || defined(__DOXYGEN__) +#define AT32_ERTCCLK AT32_LEXTCLK +#elif AT32_ERTCSEL == AT32_ERTCSEL_LICK +#define AT32_ERTCCLK AT32_LICKCLK +#elif AT32_ERTCSEL == AT32_ERTCSEL_HEXTDIV +#define AT32_ERTCCLK AT32_HEXTDIVCLK +#elif AT32_ERTCSEL == AT32_ERTCSEL_NOCLOCK +#define AT32_ERTCCLK 0 +#else +#error "invalid source selected for ERTC clock" +#endif + +/** + * @brief HEXT divider toward ERTC clock. + */ +#if ((AT32_ERTCDIV_VALUE >= 2) && (AT32_ERTCDIV_VALUE <= 31)) || \ + defined(__DOXYGEN__) +#define AT32_HEXTDIVCLK (AT32_HEXTCLK / AT32_ERTCDIV_VALUE) +#define AT32_ERTCDIV (AT32_ERTCDIV_VALUE << 16) +#else +#error "invalid AT32_ERTCDIV value specified" +#endif + +/** + * @brief I2SF5 clock. + */ +#if (AT32_I2SF5CLKSEL == AT32_I2SF5CLKSEL_SCLK) || defined(__DOXYGEN__) +#define AT32_I2SF5CLK AT32_SYSCLK +#elif AT32_I2SF5CLKSEL == AT32_I2SF5CLKSEL_PLL +#define AT32_I2SF5CLK AT32_PLLPCLK +#elif AT32_I2SF5CLKSEL == AT32_I2SF5CLKSEL_HICK +#define AT32_I2SF5CLK AT32_HICKCLKOUT +#elif AT32_I2SF5CLKSEL == AT32_I2SF5CLKSEL_EXTERNAL +#define AT32_I2SF5CLK 0 +#else +#error "invalid AT32_I2SF5CLKSEL value specified" +#endif + +/** + * @brief USB clock. + */ +#if (AT32_PLLU_USB48_SEL == AT32_PLLU_USB48_SEL_PLLU) || \ + defined(__DOXYGEN__) +#define AT32_USBCLK AT32_PLLUCLK +#elif AT32_PLLU_USB48_SEL == AT32_PLLU_USB48_SEL_HICK +#define AT32_USBCLK AT32_HICKCLKOUT +#else +#error "invalid AT32_PLLU_USB48_SEL value specified" +#endif + +/** + * @brief Timers 2, 3, 4, 6, 7, 13, 14 clock. + */ +#if (AT32_APB1DIV == AT32_APB1DIV_DIV1) || defined(__DOXYGEN__) +#define AT32_TMRCLK1 (AT32_PCLK1 * 1) +#else +#define AT32_TMRCLK1 (AT32_PCLK1 * 2) +#endif + +/** + * @brief Timers 1, 9, 10, 11 clock. + */ +#if (AT32_APB2DIV == AT32_APB2DIV_DIV1) || defined(__DOXYGEN__) +#define AT32_TMRCLK2 (AT32_PCLK2 * 1) +#else +#define AT32_TMRCLK2 (AT32_PCLK2 * 2) +#endif + +/** + * @brief Flash settings. + */ +#if (AT32_HCLK <= 32000000) || defined(__DOXYGEN__) +#define AT32_FLASHBITS 0x00000150 +#elif (AT32_HCLK <= 64000000) +#define AT32_FLASHBITS 0x00000151 +#elif (AT32_HCLK <= 96000000) +#define AT32_FLASHBITS 0x00000152 +#elif (AT32_HCLK <= 128000000) +#define AT32_FLASHBITS 0x00000153 +#elif (AT32_HCLK <= 160000000) +#define AT32_FLASHBITS 0x00000154 +#elif (AT32_HCLK <= 192000000) +#define AT32_FLASHBITS 0x00000155 +#elif (AT32_HCLK <= 216000000) +#define AT32_FLASHBITS 0x00000156 +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +/* Various helpers.*/ +#include "nvic.h" +#include "cache.h" +#include "mpu_v7m.h" +#include "at32_crm.h" +#include "at32_dma.h" +#include "at32_exint.h" +#include "at32_isr.h" +#include "at32_tmr.h" + +#ifdef __cplusplus +extern "C" { +#endif + void hal_lld_init(void); + void at32_clock_init(void); +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/ports/AT32/AT32F405xx/platform.mk b/os/hal/ports/AT32/AT32F402_405/platform.mk similarity index 63% rename from os/hal/ports/AT32/AT32F405xx/platform.mk rename to os/hal/ports/AT32/AT32F402_405/platform.mk index c1d78a6be9..7c87c78418 100644 --- a/os/hal/ports/AT32/AT32F405xx/platform.mk +++ b/os/hal/ports/AT32/AT32F402_405/platform.mk @@ -1,14 +1,14 @@ # Required platform files. -PLATFORMSRC_CONTRIB += $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \ - $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/AT32F405xx/hal_lld.c \ - $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/AT32F405xx/at32_isr.c \ - $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/AT32F405xx/hal_efl_lld.c +PLATFORMSRC_CONTRIB := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \ + $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/AT32F402_405/at32_isr.c \ + $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/AT32F402_405/hal_lld.c \ + $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/AT32F402_405/hal_efl_lld.c # Required include directories. -PLATFORMINC_CONTRIB += $(CHIBIOS)/os/hal/ports/common/ARMCMx \ - $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/AT32F405xx - +PLATFORMINC_CONTRIB := $(CHIBIOS)/os/hal/ports/common/ARMCMx \ + $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/AT32F402_405 +# Optional platform files. ifeq ($(USE_SMART_BUILD),yes) # Configuration files directory @@ -20,22 +20,23 @@ ifeq ($(HALCONFDIR),) endif endif -HALCONF := $(strip $(shell cat $(HALCONFDIR)/halconf.h | egrep -e "\#define")) -endif #ifeq ($(USE_SMART_BUILD), yes) +HALCONF := $(strip $(shell cat $(HALCONFDIR)/halconf.h $(HALCONFDIR)/halconf_community.h | egrep -e "\#define")) +endif # Drivers compatible with the platform. -include $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/EXINTv1/driver.mk -include ${CHIBIOS_CONTRIB}/os/hal/ports/AT32/LLD/GPIOv2/driver.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/ADCv2/driver.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/CRCv1/driver.mk include $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/DMAv2/driver.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/EXINTv1/driver.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/GPIOv2/driver.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/I2Cv2/driver.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/OTGv1/driver.mk include $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/RTCv2/driver.mk -include $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/TMRv1/driver.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/SPIv2/driver.mk include $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/SYSTICKv1/driver.mk -include $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/OTGv1/driver.mk -include $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/ADCv2/driver.mk -include $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/I2Cv2/driver.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/TMRv1/driver.mk include $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/USARTv2/driver.mk -include $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/SPIv2/driver.mk - +include $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/xWDGv1/driver.mk # Shared variables ALLCSRC += $(PLATFORMSRC_CONTRIB) diff --git a/os/hal/ports/AT32/AT32F405xx/at32_isr.h b/os/hal/ports/AT32/AT32F405xx/at32_isr.h deleted file mode 100644 index 92a8c614ff..0000000000 --- a/os/hal/ports/AT32/AT32F405xx/at32_isr.h +++ /dev/null @@ -1,285 +0,0 @@ -/* - ChibiOS - Copyright (C) 2023..2024 Zhaqian - ChibiOS - Copyright (C) 2024 Maxjta - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file AT32F405xx/at32_isr.h - * @brief AT32F405xx ISR handler header. - * - * @addtogroup AT32F405xx_ISR - * @{ - */ - -#ifndef AT32_ISR_H -#define AT32_ISR_H - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name ISRs suppressed in standard drivers - * @{ - */ -#define AT32_TMR1_SUPPRESS_ISR -#define AT32_TMR2_SUPPRESS_ISR -#define AT32_TMR3_SUPPRESS_ISR -#define AT32_TMR4_SUPPRESS_ISR -#define AT32_TMR6_SUPPRESS_ISR -#define AT32_TMR7_SUPPRESS_ISR -#define AT32_TMR9_SUPPRESS_ISR -#define AT32_TMR10_SUPPRESS_ISR -#define AT32_TMR11_SUPPRESS_ISR -#define AT32_TMR13_SUPPRESS_ISR -#define AT32_TMR14_SUPPRESS_ISR - -#define AT32_USART1_SUPPRESS_ISR -#define AT32_USART2_SUPPRESS_ISR -#define AT32_USART3_SUPPRESS_ISR -#define AT32_UART4_SUPPRESS_ISR -#define AT32_UART5_SUPPRESS_ISR -#define AT32_USART6_SUPPRESS_ISR -#define AT32_UART7_SUPPRESS_ISR -#define AT32_UART8_SUPPRESS_ISR -/** @} */ - -/** - * @name ISR names and numbers - * @{ - */ -/* - * ADC units. - */ -#define AT32_ADC_HANDLER Vector88 -#define AT32_ADC_NUMBER 18 - -/* - * CAN units. - */ -#define AT32_CAN1_TX_HANDLER Vector8C -#define AT32_CAN1_RX0_HANDLER Vector90 -#define AT32_CAN1_RX1_HANDLER Vector94 -#define AT32_CAN1_SCE_HANDLER Vector98 - -#define AT32_CAN1_TX_NUMBER 19 -#define AT32_CAN1_RX0_NUMBER 20 -#define AT32_CAN1_RX1_NUMBER 21 -#define AT32_CAN1_SCE_NUMBER 22 - -/* - * DMA units. - */ -#define AT32_DMA1_CH1_HANDLER Vector6C -#define AT32_DMA1_CH2_HANDLER Vector70 -#define AT32_DMA1_CH3_HANDLER Vector74 -#define AT32_DMA1_CH4_HANDLER Vector78 -#define AT32_DMA1_CH5_HANDLER Vector7C -#define AT32_DMA1_CH6_HANDLER Vector80 -#define AT32_DMA1_CH7_HANDLER Vector84 -#define AT32_DMA2_CH1_HANDLER Vector120 -#define AT32_DMA2_CH2_HANDLER Vector124 -#define AT32_DMA2_CH3_HANDLER Vector128 -#define AT32_DMA2_CH4_HANDLER Vector12C -#define AT32_DMA2_CH5_HANDLER Vector130 -#define AT32_DMA2_CH6_HANDLER Vector150 -#define AT32_DMA2_CH7_HANDLER Vector154 -#define AT32_DMAMUX_HANDLER Vector1B8 - -#define AT32_DMA1_CH1_NUMBER 11 -#define AT32_DMA1_CH2_NUMBER 12 -#define AT32_DMA1_CH3_NUMBER 13 -#define AT32_DMA1_CH4_NUMBER 14 -#define AT32_DMA1_CH5_NUMBER 15 -#define AT32_DMA1_CH6_NUMBER 16 -#define AT32_DMA1_CH7_NUMBER 17 -#define AT32_DMA2_CH1_NUMBER 56 -#define AT32_DMA2_CH2_NUMBER 57 -#define AT32_DMA2_CH3_NUMBER 58 -#define AT32_DMA2_CH4_NUMBER 59 -#define AT32_DMA2_CH5_NUMBER 60 -#define AT32_DMA2_CH6_NUMBER 68 -#define AT32_DMA2_CH7_NUMBER 69 -#define AT32_DMAMUX_NUMBER 94 - -/* - * ERTC unit. - */ -#define AT32_ERTC_TAMP_STAMP_HANDLER Vector48 -#define AT32_ERTC_WKUP_HANDLER Vector4C -#define AT32_ERTC_ALARM_HANDLER VectorE4 - -#define AT32_ERTC_TAMP_STAMP_NUMBER 2 -#define AT32_ERTC_WKUP_NUMBER 3 -#define AT32_ERTC_ALARM_NUMBER 41 - -#define AT32_ERTC_ALARM_EXINT 17 -#define AT32_ERTC_TAMP_STAMP_EXINT 21 -#define AT32_ERTC_WKUP_EXINT 22 -#define AT32_ERTC_IRQ_ENABLE() do { \ - nvicEnableVector(AT32_ERTC_TAMP_STAMP_NUMBER, AT32_IRQ_EXINT21_PRIORITY); \ - nvicEnableVector(AT32_ERTC_WKUP_NUMBER, AT32_IRQ_EXINT22_PRIORITY); \ - nvicEnableVector(AT32_ERTC_ALARM_NUMBER, AT32_IRQ_EXINT17_PRIORITY); \ -} while (false) - -/* - * EXINT unit. - */ -#define AT32_EXINT0_HANDLER Vector58 -#define AT32_EXINT1_HANDLER Vector5C -#define AT32_EXINT2_HANDLER Vector60 -#define AT32_EXINT3_HANDLER Vector64 -#define AT32_EXINT4_HANDLER Vector68 -#define AT32_EXINT5_9_HANDLER Vector9C -#define AT32_EXINT10_15_HANDLER VectorE0 -#define AT32_EXINT16_HANDLER Vector44 /* PVM */ -#define AT32_EXINT17_HANDLER VectorE4 /* ERTC ALARM */ -#define AT32_EXINT18_HANDLER VectorE8 /* OTGFS1 WAKEUP */ -#define AT32_EXINT20_HANDLER Vector170 /* OTGHS WAKEUP */ -#define AT32_EXINT21_HANDLER Vector48 /* ERTC TAMP */ -#define AT32_EXINT22_HANDLER Vector4C /* ERTC WAKEUP */ - -#define AT32_EXINT0_NUMBER 6 -#define AT32_EXINT1_NUMBER 7 -#define AT32_EXINT2_NUMBER 8 -#define AT32_EXINT3_NUMBER 9 -#define AT32_EXINT4_NUMBER 10 -#define AT32_EXINT5_9_NUMBER 23 -#define AT32_EXINT10_15_NUMBER 40 -#define AT32_EXINT16_NUMBER 1 -#define AT32_EXINT17_NUMBER 41 -#define AT32_EXINT18_NUMBER 42 -#define AT32_EXINT20_NUMBER 76 -#define AT32_EXINT21_NUMBER 2 -#define AT32_EXINT22_NUMBER 3 - -/* - * I2C units. - */ -#define AT32_I2C1_EVENT_HANDLER VectorBC -#define AT32_I2C1_ERROR_HANDLER VectorC0 -#define AT32_I2C2_EVENT_HANDLER VectorC4 -#define AT32_I2C2_ERROR_HANDLER VectorC8 -#define AT32_I2C3_EVENT_HANDLER Vector160 -#define AT32_I2C3_ERROR_HANDLER Vector164 - -#define AT32_I2C1_EVENT_NUMBER 31 -#define AT32_I2C1_ERROR_NUMBER 32 -#define AT32_I2C2_EVENT_NUMBER 33 -#define AT32_I2C2_ERROR_NUMBER 34 -#define AT32_I2C3_EVENT_NUMBER 72 -#define AT32_I2C3_ERROR_NUMBER 73 - -/* - * USB units. - */ -#define AT32_OTG1_HANDLER Vector14C -#define AT32_OTG2_HANDLER Vector174 -#define AT32_OTG2_EP1OUT_HANDLER Vector168 -#define AT32_OTG2_EP1IN_HANDLER Vector16C - -#define AT32_OTG1_NUMBER 67 -#define AT32_OTG2_NUMBER 77 -#define AT32_OTG2_EP1OUT_NUMBER 74 -#define AT32_OTG2_EP1IN_NUMBER 75 - -/* - * TMR units. - */ -#define AT32_TMR1_BRK_TMR9_HANDLER VectorA0 -#define AT32_TMR1_OVF_TMR10_HANDLER VectorA4 -#define AT32_TMR1_HALL_TMR11_HANDLER VectorA8 -#define AT32_TMR1_CH_HANDLER VectorAC -#define AT32_TMR2_HANDLER VectorB0 -#define AT32_TMR3_HANDLER VectorB4 -#define AT32_TMR4_HANDLER VectorB8 -#define AT32_TMR6_HANDLER Vector118 -#define AT32_TMR7_HANDLER Vector11C -#define AT32_TMR13_HANDLER VectorF0 -#define AT32_TMR14_HANDLER VectorF4 - -#define AT32_TMR1_BRK_TMR9_NUMBER 24 -#define AT32_TMR1_OVF_TMR10_NUMBER 25 -#define AT32_TMR1_HALL_TMR11_NUMBER 26 -#define AT32_TMR1_CH_NUMBER 27 -#define AT32_TMR2_NUMBER 28 -#define AT32_TMR3_NUMBER 29 -#define AT32_TMR4_NUMBER 30 -#define AT32_TMR6_NUMBER 54 -#define AT32_TMR7_NUMBER 55 -#define AT32_TMR13_NUMBER 44 -#define AT32_TMR14_NUMBER 45 - -/* - * USART units. - */ -#define AT32_USART1_HANDLER VectorD4 -#define AT32_USART2_HANDLER VectorD8 -#define AT32_USART3_HANDLER VectorDC -#define AT32_UART4_HANDLER Vector110 -#define AT32_UART5_HANDLER Vector114 -#define AT32_USART6_HANDLER Vector15C -#define AT32_UART7_HANDLER Vector188 -#define AT32_UART8_HANDLER Vector18C - -#define AT32_USART1_NUMBER 37 -#define AT32_USART2_NUMBER 38 -#define AT32_USART3_NUMBER 39 -#define AT32_UART4_NUMBER 52 -#define AT32_UART5_NUMBER 53 -#define AT32_USART6_NUMBER 71 -#define AT32_UART7_NUMBER 82 -#define AT32_UART8_NUMBER 83 - -/* - * ACC units. - */ -#define AT32_ACC_HANDLER Vector1DC -#define AT32_ACC_NUMBER 103 - -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void irqInit(void); - void irqDeinit(void); -#ifdef __cplusplus -} -#endif - -#endif /* AT32_ISR_H */ - -/** @} */ diff --git a/os/hal/ports/AT32/AT32F405xx/at32_registry.h b/os/hal/ports/AT32/AT32F405xx/at32_registry.h deleted file mode 100644 index 6235b66030..0000000000 --- a/os/hal/ports/AT32/AT32F405xx/at32_registry.h +++ /dev/null @@ -1,579 +0,0 @@ -/* - ChibiOS - Copyright (C) 2023..2024 Zhaqian - ChibiOS - Copyright (C) 2024 Maxjta - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file AT32F405xx/at32_registry.h - * @brief AT32F405xx capabilities registry. - * - * @addtogroup HAL - * @{ - */ - -#ifndef AT32_REGISTRY_H -#define AT32_REGISTRY_H - -/*===========================================================================*/ -/* Platform capabilities. */ -/*===========================================================================*/ -#if defined(AT32F402Kx) || defined(AT32F405Kx) || defined(__DOXYGEN__) -/** - * @name AT32F402_5Kx capabilities - * @{ - */ -/* ADC attributes.*/ -#define AT32_HAS_ADC1 TRUE -#define AT32_HAS_ADC2 FALSE -#define AT32_HAS_ADC3 FALSE - -/* CAN attributes.*/ -#define AT32_HAS_CAN1 TRUE -#define AT32_HAS_CAN2 FALSE -#define AT32_CAN_MAX_FILTERS 14 - -/* DAC attributes.*/ -#define AT32_HAS_DAC1_CH1 FALSE -#define AT32_HAS_DAC1_CH2 FALSE - -/* DMA attributes.*/ -#define AT32_ADVANCED_DMA TRUE -#define AT32_DMA_SUPPORTS_DMAMUX TRUE -#define AT32_DMA_SUPPORTS_CSELR FALSE - -#define AT32_DMA1_NUM_CHANNELS 7 -#define AT32_DMA2_NUM_CHANNELS 7 - -/* ETH attributes.*/ -#define AT32_HAS_ETH FALSE - -/* EXINT attributes.*/ -#define AT32_EXINT_NUM_LINES 22 -#define AT32_EXINT_INTEN_MASK 0x00000000U - -/* Flash attributes.*/ -#define AT32_FLASH_NUMBER_OF_BANKS 1 -#if defined(AT32F402xB) || defined(AT32F405xB) -#define AT32_FLASH_SECTOR_SIZE 1024U -#elif defined(AT32F402xC) || defined(AT32F405xC) -#define AT32_FLASH_SECTOR_SIZE 2048U -#endif -#if !defined(AT32_FLASH_SECTORS_PER_BANK) || defined(__DOXYGEN__) -#define AT32_FLASH_SECTORS_PER_BANK 128 /* Maximum, can be redefined.*/ -#endif - -/* GPIO attributes.*/ -#define AT32_HAS_GPIOA TRUE -#define AT32_HAS_GPIOB TRUE -#define AT32_HAS_GPIOC FALSE -#define AT32_HAS_GPIOD FALSE -#define AT32_HAS_GPIOE FALSE -#define AT32_HAS_GPIOF TRUE -#define AT32_HAS_GPIOG FALSE -#define AT32_HAS_GPIOH FALSE -#define AT32_HAS_GPIOI FALSE -#define AT32_HAS_GPIOJ FALSE -#define AT32_HAS_GPIOK FALSE - -#define AT32_GPIO_EN_MASK (CRM_AHBEN1_GPIOAEN | \ - CRM_AHBEN1_GPIOBEN | \ - CRM_AHBEN1_GPIOFEN) - -/* I2C attributes.*/ -#define AT32_HAS_I2C1 TRUE -#define AT32_HAS_I2C2 TRUE -#define AT32_HAS_I2C3 TRUE - -/* RTC attributes.*/ -#define AT32_HAS_ERTC TRUE -#define AT32_ERTC_HAS_SUBSECONDS TRUE -#define AT32_ERTC_IS_CALENDAR TRUE -#define AT32_ERTC_HAS_PERIODIC_WAKEUPS TRUE -#define AT32_ERTC_NUM_ALARMS 2 -#define AT32_ERTC_STORAGE_SIZE 80 - -/* SDIO attributes.*/ -#define AT32_HAS_SDIO FALSE - -/* SPI attributes.*/ -#define AT32_HAS_SPI1 TRUE -#define AT32_SPI1_SUPPORTS_I2S TRUE -#define AT32_SPI1_I2S_FULLDUPLEX FALSE - -#define AT32_HAS_SPI2 FALSE - -#define AT32_HAS_SPI3 TRUE -#define AT32_SPI3_SUPPORTS_I2S TRUE -#define AT32_SPI3_I2S_FULLDUPLEX FALSE - -/* TMR attributes.*/ -#define AT32_TMR_MAX_CHANNELS 4 - -#define AT32_HAS_TMR1 TRUE -#define AT32_TMR1_IS_32BITS FALSE -#define AT32_TMR1_CHANNELS 4 - -#define AT32_HAS_TMR2 TRUE -#define AT32_TMR2_IS_32BITS TRUE -#define AT32_TMR2_CHANNELS 4 - -#define AT32_HAS_TMR3 TRUE -#define AT32_TMR3_IS_32BITS FALSE -#define AT32_TMR3_CHANNELS 4 - -#define AT32_HAS_TMR4 TRUE -#define AT32_TMR4_IS_32BITS FALSE -#define AT32_TMR4_CHANNELS 4 - -#define AT32_HAS_TMR5 FALSE - -#define AT32_HAS_TMR6 TRUE -#define AT32_TMR6_IS_32BITS FALSE -#define AT32_TMR6_CHANNELS 0 - -#define AT32_HAS_TMR7 TRUE -#define AT32_TMR7_IS_32BITS FALSE -#define AT32_TMR7_CHANNELS 0 - -#define AT32_HAS_TMR8 FALSE - -#define AT32_HAS_TMR9 TRUE -#define AT32_TMR9_IS_32BITS FALSE -#define AT32_TMR9_CHANNELS 2 - -#define AT32_HAS_TMR10 TRUE -#define AT32_TMR10_IS_32BITS FALSE -#define AT32_TMR10_CHANNELS 1 - -#define AT32_HAS_TMR11 TRUE -#define AT32_TMR11_IS_32BITS FALSE -#define AT32_TMR11_CHANNELS 1 - -#define AT32_HAS_TMR12 FALSE - -#define AT32_HAS_TMR13 TRUE -#define AT32_TMR13_IS_32BITS FALSE -#define AT32_TMR13_CHANNELS 1 - -#define AT32_HAS_TMR14 TRUE -#define AT32_TMR14_IS_32BITS FALSE -#define AT32_TMR14_CHANNELS 1 - -/* USART attributes.*/ -#define AT32_HAS_USART1 TRUE -#define AT32_HAS_USART2 TRUE -#define AT32_HAS_USART3 TRUE -#define AT32_HAS_UART4 TRUE -#define AT32_HAS_UART5 TRUE -#define AT32_HAS_USART6 TRUE -#define AT32_HAS_UART7 TRUE -#define AT32_HAS_UART8 FALSE - -/* USB attributes.*/ -#define AT32_OTG_STEPPING 2 -#define AT32_HAS_OTG1 TRUE -#define AT32_OTG1_ENDPOINTS 8 - -#if defined(AT32F405xx) -#define AT32_HAS_OTG2 TRUE -#define AT32_OTG2_ENDPOINTS 8 -#define AT32_OTG2_SUPPORTS_HS TRUE -#else -#define AT32_HAS_OTG2 FALSE -#endif - -#define AT32_HAS_USB FALSE - -/* IWDG attributes.*/ -#define AT32_HAS_IWDG TRUE -#define AT32_IWDG_IS_WINDOWED TRUE - -/* FSMC attributes.*/ -#define AT32_HAS_FSMC FALSE - -/* CRC attributes.*/ -#define AT32_HAS_CRC TRUE -#define AT32_CRC_PROGRAMMABLE FALSE - -#endif /* defined(AT32F402Kx) || defined(AT32F405Kx) */ - -#if defined(AT32F402Cx) || defined(AT32F405Cx) -/** - * @name AT32F402_5Cx capabilities - * @{ - */ -/* ADC attributes.*/ -#define AT32_HAS_ADC1 TRUE -#define AT32_HAS_ADC2 FALSE -#define AT32_HAS_ADC3 FALSE - -/* CAN attributes.*/ -#define AT32_HAS_CAN1 TRUE -#define AT32_HAS_CAN2 FALSE -#define AT32_CAN_MAX_FILTERS 14 - -/* DAC attributes.*/ -#define AT32_HAS_DAC1_CH1 FALSE -#define AT32_HAS_DAC1_CH2 FALSE - -/* DMA attributes.*/ -#define AT32_ADVANCED_DMA TRUE -#define AT32_DMA_SUPPORTS_DMAMUX TRUE -#define AT32_DMA_SUPPORTS_CSELR FALSE - -#define AT32_DMA1_NUM_CHANNELS 7 -#define AT32_DMA2_NUM_CHANNELS 7 - -/* ETH attributes.*/ -#define AT32_HAS_ETH FALSE - -/* EXINT attributes.*/ -#define AT32_EXINT_NUM_LINES 22 -#define AT32_EXINT_INTEN_MASK 0x00000000U - -/* Flash attributes.*/ -#define AT32_FLASH_NUMBER_OF_BANKS 1 -#if defined(AT32F402xB) || defined(AT32F405xB) -#define AT32_FLASH_SECTOR_SIZE 1024U -#elif defined(AT32F402xC) || defined(AT32F405xC) -#define AT32_FLASH_SECTOR_SIZE 2048U -#endif -#if !defined(AT32_FLASH_SECTORS_PER_BANK) || defined(__DOXYGEN__) -#define AT32_FLASH_SECTORS_PER_BANK 128 /* Maximum, can be redefined.*/ -#endif - -/* GPIO attributes.*/ -#define AT32_HAS_GPIOA TRUE -#define AT32_HAS_GPIOB TRUE -#define AT32_HAS_GPIOC TRUE -#define AT32_HAS_GPIOD FALSE -#define AT32_HAS_GPIOE FALSE -#define AT32_HAS_GPIOF TRUE -#define AT32_HAS_GPIOG FALSE -#define AT32_HAS_GPIOH FALSE -#define AT32_HAS_GPIOI FALSE -#define AT32_HAS_GPIOJ FALSE -#define AT32_HAS_GPIOK FALSE - -#define AT32_GPIO_EN_MASK (CRM_AHBEN1_GPIOAEN | \ - CRM_AHBEN1_GPIOBEN | \ - CRM_AHBEN1_GPIOCEN | \ - CRM_AHBEN1_GPIOFEN) - -/* I2C attributes.*/ -#define AT32_HAS_I2C1 TRUE -#define AT32_HAS_I2C2 TRUE -#define AT32_HAS_I2C3 TRUE - -/* RTC attributes.*/ -#define AT32_HAS_ERTC TRUE -#define AT32_ERTC_HAS_SUBSECONDS TRUE -#define AT32_ERTC_IS_CALENDAR TRUE -#define AT32_ERTC_HAS_PERIODIC_WAKEUPS TRUE -#define AT32_ERTC_NUM_ALARMS 2 -#define AT32_ERTC_STORAGE_SIZE 80 - -/* SDIO attributes.*/ -#define AT32_HAS_SDIO FALSE - -/* SPI attributes.*/ -#define AT32_HAS_SPI1 TRUE -#define AT32_SPI1_SUPPORTS_I2S TRUE -#define AT32_SPI1_I2S_FULLDUPLEX FALSE - -#define AT32_HAS_SPI2 TRUE -#define AT32_SPI2_SUPPORTS_I2S TRUE -#define AT32_SPI2_I2S_FULLDUPLEX FALSE - -#define AT32_HAS_SPI3 TRUE -#define AT32_SPI3_SUPPORTS_I2S TRUE -#define AT32_SPI3_I2S_FULLDUPLEX FALSE - -/* TMR attributes.*/ -#define AT32_TMR_MAX_CHANNELS 4 - -#define AT32_HAS_TMR1 TRUE -#define AT32_TMR1_IS_32BITS FALSE -#define AT32_TMR1_CHANNELS 4 - -#define AT32_HAS_TMR2 TRUE -#define AT32_TMR2_IS_32BITS TRUE -#define AT32_TMR2_CHANNELS 4 - -#define AT32_HAS_TMR3 TRUE -#define AT32_TMR3_IS_32BITS FALSE -#define AT32_TMR3_CHANNELS 4 - -#define AT32_HAS_TMR4 TRUE -#define AT32_TMR4_IS_32BITS FALSE -#define AT32_TMR4_CHANNELS 4 - -#define AT32_HAS_TMR5 FALSE - -#define AT32_HAS_TMR6 TRUE -#define AT32_TMR6_IS_32BITS FALSE -#define AT32_TMR6_CHANNELS 0 - -#define AT32_HAS_TMR7 TRUE -#define AT32_TMR7_IS_32BITS FALSE -#define AT32_TMR7_CHANNELS 0 - -#define AT32_HAS_TMR8 FALSE - -#define AT32_HAS_TMR9 TRUE -#define AT32_TMR9_IS_32BITS FALSE -#define AT32_TMR9_CHANNELS 2 - -#define AT32_HAS_TMR10 TRUE -#define AT32_TMR10_IS_32BITS FALSE -#define AT32_TMR10_CHANNELS 1 - -#define AT32_HAS_TMR11 TRUE -#define AT32_TMR11_IS_32BITS FALSE -#define AT32_TMR11_CHANNELS 1 - -#define AT32_HAS_TMR12 FALSE - -#define AT32_HAS_TMR13 TRUE -#define AT32_TMR13_IS_32BITS FALSE -#define AT32_TMR13_CHANNELS 1 - -#define AT32_HAS_TMR14 TRUE -#define AT32_TMR14_IS_32BITS FALSE -#define AT32_TMR14_CHANNELS 1 - -/* USART attributes.*/ -#define AT32_HAS_USART1 TRUE -#define AT32_HAS_USART2 TRUE -#define AT32_HAS_USART3 TRUE -#define AT32_HAS_UART4 TRUE -#define AT32_HAS_UART5 TRUE -#define AT32_HAS_USART6 TRUE -#define AT32_HAS_UART7 TRUE -#define AT32_HAS_UART8 FALSE - -/* USB attributes.*/ -#define AT32_OTG_STEPPING 2 -#define AT32_HAS_OTG1 TRUE -#define AT32_OTG1_ENDPOINTS 8 - -#if defined(AT32F405xx) -#define AT32_HAS_OTG2 TRUE -#define AT32_OTG2_ENDPOINTS 8 -#else -#define AT32_HAS_OTG2 FALSE -#endif - -#define AT32_HAS_USB FALSE - -/* IWDG attributes.*/ -#define AT32_HAS_IWDG TRUE -#define AT32_IWDG_IS_WINDOWED TRUE - -/* FSMC attributes.*/ -#define AT32_HAS_FSMC FALSE - -/* CRC attributes.*/ -#define AT32_HAS_CRC TRUE -#define AT32_CRC_PROGRAMMABLE FALSE - -#endif /* defined(AT32F402Cx) || defined(AT32F405Cx) */ - -#if defined(AT32F402Rx) || defined(AT32F405Rx) -/** - * @name AT32F402_405Rx capabilities - * @{ - */ -/* ADC attributes.*/ -#define AT32_HAS_ADC1 TRUE -#define AT32_HAS_ADC2 FALSE -#define AT32_HAS_ADC3 FALSE - -/* CAN attributes.*/ -#define AT32_HAS_CAN1 TRUE -#define AT32_HAS_CAN2 FALSE -#define AT32_CAN_MAX_FILTERS 14 - -/* DAC attributes.*/ -#define AT32_HAS_DAC1_CH1 FALSE -#define AT32_HAS_DAC1_CH2 FALSE - -/* DMA attributes.*/ -#define AT32_ADVANCED_DMA TRUE -#define AT32_DMA_SUPPORTS_DMAMUX TRUE -#define AT32_DMA_SUPPORTS_CSELR FALSE - -#define AT32_DMA1_NUM_CHANNELS 7 -#define AT32_DMA2_NUM_CHANNELS 7 - -/* ETH attributes.*/ -#define AT32_HAS_ETH FALSE - -/* EXINT attributes.*/ -#define AT32_EXINT_NUM_LINES 22 -#define AT32_EXINT_INTEN_MASK 0x00000000U - -/* Flash attributes.*/ -#define AT32_FLASH_NUMBER_OF_BANKS 1 -#if defined(AT32F402xB) || defined(AT32F405xB) -#define AT32_FLASH_SECTOR_SIZE 1024U -#elif defined(AT32F402xC) || defined(AT32F405xC) -#define AT32_FLASH_SECTOR_SIZE 2048U -#endif -#if !defined(AT32_FLASH_SECTORS_PER_BANK) || defined(__DOXYGEN__) -#define AT32_FLASH_SECTORS_PER_BANK 128 /* Maximum, can be redefined.*/ -#endif - -/* GPIO attributes.*/ -#define AT32_HAS_GPIOA TRUE -#define AT32_HAS_GPIOB TRUE -#define AT32_HAS_GPIOC TRUE -#define AT32_HAS_GPIOD TRUE -#define AT32_HAS_GPIOE FALSE -#define AT32_HAS_GPIOF TRUE -#define AT32_HAS_GPIOG FALSE -#define AT32_HAS_GPIOH FALSE -#define AT32_HAS_GPIOI FALSE -#define AT32_HAS_GPIOJ FALSE -#define AT32_HAS_GPIOK FALSE - -#define AT32_GPIO_EN_MASK (CRM_AHBEN1_GPIOAEN | \ - CRM_AHBEN1_GPIOBEN | \ - CRM_AHBEN1_GPIOCEN | \ - CRM_AHBEN1_GPIODEN | \ - CRM_AHBEN1_GPIOFEN) - -/* I2C attributes.*/ -#define AT32_HAS_I2C1 TRUE -#define AT32_HAS_I2C2 TRUE -#define AT32_HAS_I2C3 TRUE - -/* RTC attributes.*/ -#define AT32_HAS_ERTC TRUE -#define AT32_ERTC_HAS_SUBSECONDS TRUE -#define AT32_ERTC_IS_CALENDAR TRUE -#define AT32_ERTC_HAS_PERIODIC_WAKEUPS TRUE -#define AT32_ERTC_NUM_ALARMS 2 -#define AT32_ERTC_STORAGE_SIZE 80 - -/* SDIO attributes.*/ -#define AT32_HAS_SDIO FALSE - -/* SPI attributes.*/ -#define AT32_HAS_SPI1 TRUE -#define AT32_SPI1_SUPPORTS_I2S TRUE -#define AT32_SPI1_I2S_FULLDUPLEX FALSE - -#define AT32_HAS_SPI2 TRUE -#define AT32_SPI2_SUPPORTS_I2S TRUE -#define AT32_SPI2_I2S_FULLDUPLEX FALSE - -#define AT32_HAS_SPI3 TRUE -#define AT32_SPI3_SUPPORTS_I2S TRUE -#define AT32_SPI3_I2S_FULLDUPLEX FALSE - -/* TMR attributes.*/ -#define AT32_TMR_MAX_CHANNELS 4 - -#define AT32_HAS_TMR1 TRUE -#define AT32_TMR1_IS_32BITS FALSE -#define AT32_TMR1_CHANNELS 4 - -#define AT32_HAS_TMR2 TRUE -#define AT32_TMR2_IS_32BITS TRUE -#define AT32_TMR2_CHANNELS 4 - -#define AT32_HAS_TMR3 TRUE -#define AT32_TMR3_IS_32BITS FALSE -#define AT32_TMR3_CHANNELS 4 - -#define AT32_HAS_TMR4 TRUE -#define AT32_TMR4_IS_32BITS FALSE -#define AT32_TMR4_CHANNELS 4 - -#define AT32_HAS_TMR5 FALSE - -#define AT32_HAS_TMR6 TRUE -#define AT32_TMR6_IS_32BITS FALSE -#define AT32_TMR6_CHANNELS 0 - -#define AT32_HAS_TMR7 TRUE -#define AT32_TMR7_IS_32BITS FALSE -#define AT32_TMR7_CHANNELS 0 - -#define AT32_HAS_TMR8 FALSE - -#define AT32_HAS_TMR9 TRUE -#define AT32_TMR9_IS_32BITS FALSE -#define AT32_TMR9_CHANNELS 2 - -#define AT32_HAS_TMR10 TRUE -#define AT32_TMR10_IS_32BITS FALSE -#define AT32_TMR10_CHANNELS 1 - -#define AT32_HAS_TMR11 TRUE -#define AT32_TMR11_IS_32BITS FALSE -#define AT32_TMR11_CHANNELS 1 - -#define AT32_HAS_TMR12 FALSE - -#define AT32_HAS_TMR13 TRUE -#define AT32_TMR13_IS_32BITS FALSE -#define AT32_TMR13_CHANNELS 1 - -#define AT32_HAS_TMR14 TRUE -#define AT32_TMR14_IS_32BITS FALSE -#define AT32_TMR14_CHANNELS 1 - -/* USART attributes.*/ -#define AT32_HAS_USART1 TRUE -#define AT32_HAS_USART2 TRUE -#define AT32_HAS_USART3 TRUE -#define AT32_HAS_UART4 TRUE -#define AT32_HAS_UART5 TRUE -#define AT32_HAS_USART6 TRUE -#define AT32_HAS_UART7 TRUE -#define AT32_HAS_UART8 TRUE - -/* USB attributes.*/ -#define AT32_OTG_STEPPING 2 -#define AT32_HAS_OTG1 TRUE -#define AT32_OTG1_ENDPOINTS 8 - -#if defined(AT32F405xx) -#define AT32_HAS_OTG2 TRUE -#define AT32_OTG2_ENDPOINTS 8 -#else -#define AT32_HAS_OTG2 FALSE -#endif - -#define AT32_HAS_USB FALSE - -/* IWDG attributes.*/ -#define AT32_HAS_IWDG TRUE -#define AT32_IWDG_IS_WINDOWED TRUE - -/* FSMC attributes.*/ -#define AT32_HAS_FSMC FALSE - -/* CRC attributes.*/ -#define AT32_HAS_CRC TRUE -#define AT32_CRC_PROGRAMMABLE FALSE - -#endif /* defined(AT32F402Rx) || defined(AT32F405Rx) */ - -#endif /* AT32_REGISTRY_H */ - -/** @} */ diff --git a/os/hal/ports/AT32/AT32F405xx/hal_lld.h b/os/hal/ports/AT32/AT32F405xx/hal_lld.h deleted file mode 100644 index de7eebd51c..0000000000 --- a/os/hal/ports/AT32/AT32F405xx/hal_lld.h +++ /dev/null @@ -1,1203 +0,0 @@ -/* - ChibiOS - Copyright (C) 2023..2024 Zhaqian - ChibiOS - Copyright (C) 2024 Maxjta - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file AT32F405xx/hal_lld.h - * @brief AT32F405xx HAL subsystem low level driver header. - * @pre This module requires the following macros to be defined in the - * @p board.h file: - * - AT32_LEXTCLK. - * - AT32_LEXT_BYPASS (optionally). - * - AT32_HEXTCLK. - * - AT32_HEXT_BYPASS (optionally). - * . - * - * @addtogroup HAL - * @{ - */ - -#ifndef HAL_LLD_H -#define HAL_LLD_H - -#include "at32_registry.h" - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief Requires use of SPIv2 driver model. - */ -#define HAL_LLD_SELECT_SPI_V2 TRUE - -/** - * @name Platform identification - * @{ - */ -#define PLATFORM_NAME "AT32F405xx" - -/** - * @brief Sub-family identifier. - */ -#if !defined(AT32F405xx) || defined(__DOXYGEN__) -#define AT32F405xx -#endif -/** @} */ - -/** - * @name Absolute Maximum Ratings - * @{ - */ -/** - * @brief Maximum system clock frequency. - */ -#define AT32_SYSCLK_MAX 216000000 - -/** - * @brief Maximum HEXT clock frequency. - */ -#define AT32_HEXTCLK_MAX 25000000 - -/** - * @brief Maximum HEXT clock frequency using an external source. - */ -#define AT32_HEXTCLK_BYP_MAX 25000000 - -/** - * @brief Minimum HEXT clock frequency. - */ -#define AT32_HEXTCLK_MIN 4000000 - -/** - * @brief Minimum HEXT clock frequency. - */ -#define AT32_HEXTCLK_BYP_MIN 4000000 - -/** - * @brief Maximum LSE clock frequency. - */ -#define AT32_LEXTCLK_MAX 32768 - -/** - * @brief Maximum LSE clock frequency. - */ -#define AT32_LEXTCLK_BYP_MAX 1000000 - -/** - * @brief Minimum LEXT clock frequency. - */ -#define AT32_LEXTCLK_MIN 32768 - -/** - * @brief Maximum PLLs input clock frequency. - */ -#define AT32_PLLIN_MAX 16000000 - -/** - * @brief Minimum PLLs input clock frequency. - */ -#define AT32_PLLIN_MIN 2000000 - -/** - * @brief Maximum PLLs VCO clock frequency. - */ -#define AT32_PLLVCO_MAX 1000000000 - -/** - * @brief Minimum PLLs VCO clock frequency. - */ -#define AT32_PLLVCO_MIN 500000000 - -/** - * @brief Maximum PLL output clock frequency. - */ -#define AT32_PLLOUT_MAX 216000000 - -/** - * @brief Minimum PLL output clock frequency. - */ -#define AT32_PLLOUT_MIN 4000000 - -/** - * @brief Maximum APB1 clock frequency. - */ -#define AT32_PCLK1_MAX 120000000 - -/** - * @brief Maximum APB2 clock frequency. - */ -#define AT32_PCLK2_MAX 216000000 - -/** - * @brief Maximum ADC clock frequency. - */ -#define AT32_ADCCLK_MAX 28000000 -/** @} */ - -/** - * @name Internal clock sources - * @{ - */ -#define AT32_HICKCLK 48000000 /**< High speed internal clock. */ -#define AT32_LICKCLK 40000 /**< Low speed internal clock. */ -/** @} */ - -/** - * @name PWC_CTRL register bits definitions - * @{ - */ -#define AT32_PVMSEL_MASK (7 << 5) /**< PVMSEL bits mask. */ -#define AT32_PVMSEL_LEV0 (0 << 5) /**< PVM level 0. */ -#define AT32_PVMSEL_LEV1 (1 << 5) /**< PVM level 1. */ -#define AT32_PVMSEL_LEV2 (2 << 5) /**< PVM level 2. */ -#define AT32_PVMSEL_LEV3 (3 << 5) /**< PVM level 3. */ -#define AT32_PVMSEL_LEV4 (4 << 5) /**< PVM level 4. */ -#define AT32_PVMSEL_LEV5 (5 << 5) /**< PVM level 5. */ -#define AT32_PVMSEL_LEV6 (6 << 5) /**< PVM level 6. */ -#define AT32_PVMSEL_LEV7 (7 << 5) /**< PVM level 7. */ -/** @} */ - -/** - * @name PWC_LDOOV register bits definitions - * @{ - */ -#define AT32_LDOOVSEL_MASK (3 << 0) /**< LDOOVSEL bits mask. */ -#define AT32_LDOOVSEL_1P0V (0 << 0) /**< LDOOVSEL 1.0V. */ -#define AT32_LDOOVSEL_1P1V (1 << 0) /**< LDOOVSEL 1.1V. */ -#define AT32_LDOOVSEL_1P2V (2 << 0) /**< LDOOVSEL 1.2V. */ -#define AT32_LDOOVSEL_1P3V (3 << 0) /**< LDOOVSEL 1.3V. */ -/** @} */ - -/** - * @name CRM_PLLCFG register bits definitions - * @{ - */ -#define AT32_PLL_FP_MASK (15 << 16) /**< PLL_FP mask. */ -#define AT32_PLL_FP_DIV1 (0 << 16) /**< PLL clock divided by 1. */ -#define AT32_PLL_FP_DIV2 (1 << 16) /**< PLL clock divided by 2. */ -#define AT32_PLL_FP_DIV4 (2 << 16) /**< PLL clock divided by 4. */ -#define AT32_PLL_FP_DIV6 (3 << 16) /**< PLL clock divided by 6. */ -#define AT32_PLL_FP_DIV8 (4 << 16) /**< PLL clock divided by 8. */ -#define AT32_PLL_FP_DIV10 (5 << 16) /**< PLL clock divided by 10. */ -#define AT32_PLL_FP_DIV12 (6 << 16) /**< PLL clock divided by 12. */ -#define AT32_PLL_FP_DIV14 (7 << 16) /**< PLL clock divided by 14. */ -#define AT32_PLL_FP_DIV16 (8 << 16) /**< PLL clock divided by 16. */ -#define AT32_PLL_FP_DIV18 (9 << 16) /**< PLL clock divided by 18. */ -#define AT32_PLL_FP_DIV20 (10 << 16) /**< PLL clock divided by 20. */ -#define AT32_PLL_FP_DIV22 (11 << 16) /**< PLL clock divided by 22. */ -#define AT32_PLL_FP_DIV24 (12 << 16) /**< PLL clock divided by 24. */ -#define AT32_PLL_FP_DIV26 (13 << 16) /**< PLL clock divided by 26. */ -#define AT32_PLL_FP_DIV28 (14 << 16) /**< PLL clock divided by 28. */ -#define AT32_PLL_FP_DIV30 (15 << 16) /**< PLL clock divided by 30. */ - -#define AT32_PLL_FU_MASK (7 << 20) /**< PLL_FU mask. */ -#define AT32_PLL_FU_DIV11 (0 << 20) /**< PLLU clock divided by 11. */ -#define AT32_PLL_FU_DIV13 (1 << 20) /**< PLLU clock divided by 13. */ -#define AT32_PLL_FU_DIV12 (2 << 20) /**< PLLU clock divided by 12. */ -#define AT32_PLL_FU_DIV14 (3 << 20) /**< PLLU clock divided by 14. */ -#define AT32_PLL_FU_DIV16 (4 << 20) /**< PLLU clock divided by 16. */ -#define AT32_PLL_FU_DIV18 (5 << 20) /**< PLLU clock divided by 18. */ -#define AT32_PLL_FU_DIV20 (6 << 20) /**< PLLU clock divided by 20. */ - -#define AT32_PLLRCS_HICK (0 << 30) /**< PLL clock source is HICK. */ -#define AT32_PLLRCS_HEXT (1 << 30) /**< PLL clock source is HEXT. */ -/** @} */ - -/** - * @name CRM_CFG register bits definitions - * @{ - */ -#define AT32_SCLKSEL_MASK (3 << 0) /**< SCLKSEL mask. */ -#define AT32_SCLKSEL_HICK (0 << 0) /**< SYSCLK source is HICK. */ -#define AT32_SCLKSEL_HEXT (1 << 0) /**< SYSCLK source is HEXT. */ -#define AT32_SCLKSEL_PLL (2 << 0) /**< SYSCLK source is PLL. */ - -#define AT32_SCLKSTS_MASK (3 << 2) /**< SCLKSTS mask. */ -#define AT32_SCLKSTS_HICK (0 << 2) /**< SYSCLK use HICK. */ -#define AT32_SCLKSTS_HEXT (1 << 2) /**< SYSCLK use HEXT. */ -#define AT32_SCLKSTS_PLL (2 << 2) /**< SYSCLK use PLL. */ - -#define AT32_AHBDIV_MASK (15 << 4) /**< AHBDIV mask. */ -#define AT32_AHBDIV_DIV1 (0 << 4) /**< SYSCLK divided by 1. */ -#define AT32_AHBDIV_DIV2 (8 << 4) /**< SYSCLK divided by 2. */ -#define AT32_AHBDIV_DIV4 (9 << 4) /**< SYSCLK divided by 4. */ -#define AT32_AHBDIV_DIV8 (10 << 4) /**< SYSCLK divided by 8. */ -#define AT32_AHBDIV_DIV16 (11 << 4) /**< SYSCLK divided by 16. */ -#define AT32_AHBDIV_DIV64 (12 << 4) /**< SYSCLK divided by 64. */ -#define AT32_AHBDIV_DIV128 (13 << 4) /**< SYSCLK divided by 128. */ -#define AT32_AHBDIV_DIV256 (14 << 4) /**< SYSCLK divided by 256. */ -#define AT32_AHBDIV_DIV512 (15 << 4) /**< SYSCLK divided by 512. */ - -#define AT32_APB1DIV_MASK (7 << 10) /**< APB1DIV mask. */ -#define AT32_APB1DIV_DIV1 (0 << 10) /**< HCLK divided by 1. */ -#define AT32_APB1DIV_DIV2 (4 << 10) /**< HCLK divided by 2. */ -#define AT32_APB1DIV_DIV4 (5 << 10) /**< HCLK divided by 4. */ -#define AT32_APB1DIV_DIV8 (6 << 10) /**< HCLK divided by 8. */ -#define AT32_APB1DIV_DIV16 (7 << 10) /**< HCLK divided by 16. */ - -#define AT32_APB2DIV_MASK (7 << 13) /**< APB2DIV mask. */ -#define AT32_APB2DIV_DIV1 (0 << 13) /**< HCLK divided by 1. */ -#define AT32_APB2DIV_DIV2 (4 << 13) /**< HCLK divided by 2. */ -#define AT32_APB2DIV_DIV4 (5 << 13) /**< HCLK divided by 4. */ -#define AT32_APB2DIV_DIV8 (6 << 13) /**< HCLK divided by 8. */ -#define AT32_APB2DIV_DIV16 (7 << 13) /**< HCLK divided by 16. */ - -#define AT32_ERTCDIV_MASK (31 << 16) /**< ERTCDIV mask. */ - -#define AT32_I2SF5CLKSEL_MASK (3 << 22) /**< I2SF5CLKSEL mask. */ -#define AT32_I2SF5CLKSEL_SCLK (0 << 22) /**< I2SF5CLKSEL is SYSCLK. */ -#define AT32_I2SF5CLKSEL_PLL (1 << 22) /**< I2SF5CLKSEL is PLL. */ -#define AT32_I2SF5CLKSEL_HICK (2 << 22) /**< I2SF5CLKSEL is HICK. */ -#define AT32_I2SF5CLKSEL_EXCLK (3 << 22) /**< I2SF5CLKSEL is EXCLK. */ - -#define AT32_CLKOUTDIV1_MASK (7 << 27) /**< CLKOUTDIV1 mask. */ -#define AT32_CLKOUTDIV1_DIV1 (0 << 27) /**< CLKOUT divided by 1. */ -#define AT32_CLKOUTDIV1_DIV2 (4 << 27) /**< CLKOUT divided by 2. */ -#define AT32_CLKOUTDIV1_DIV3 (5 << 27) /**< CLKOUT divided by 3. */ -#define AT32_CLKOUTDIV1_DIV4 (6 << 27) /**< CLKOUT divided by 4. */ -#define AT32_CLKOUTDIV1_DIV5 (7 << 27) /**< CLKOUT divided by 5. */ - -#define AT32_CLKOUT_SEL_CFG_MASK (3 << 30) /**< CLKOUT_SEL CFG mask. */ -#define AT32_CLKOUT_SEL_MISC1_MASK (15 << 16) /**< CLKOUT_SEL MISC1 mask. */ -#define AT32_CLKOUT_SEL_SCLK (0 << 30) /**< CLKOUT_SEL SYSCLK. */ -#define AT32_CLKOUT_SEL_HEXT (2 << 30) /**< CLKOUT_SEL HEXT. */ -#define AT32_CLKOUT_SEL_PLL (3 << 30) /**< CLKOUT_SEL PLL. */ -#define AT32_CLKOUT_SEL_USBFS ((1 << 30) | \ - (0 << 16)) /**< CLKOUT_SEL USBFS. */ -#define AT32_CLKOUT_SEL_ADC ((1 << 30) | \ - (1 << 16)) /**< CLKOUT_SEL ADC. */ -#define AT32_CLKOUT_SEL_HICK ((1 << 30) | \ - (2 << 16)) /**< CLKOUT_SEL HICK. */ -#define AT32_CLKOUT_SEL_LICK ((1 << 30) | \ - (3 << 16)) /**< CLKOUT_SEL LICK. */ -#define AT32_CLKOUT_SEL_LEXT ((1 << 30) | \ - (4 << 16)) /**< CLKOUT_SEL LEXT. */ -#define AT32_CLKOUT_SEL_USBHS ((1 << 30) | \ - (5 << 16)) /**< CLKOUT_SEL USBHS. */ -/** @} */ - -/** - * @name CRM_BPDC register bits definitions - * @{ - */ -#define AT32_ERTCSEL_MASK (3 << 8) /**< RTC clock source mask. */ -#define AT32_ERTCSEL_NOCLOCK (0 << 8) /**< No clock. */ -#define AT32_ERTCSEL_LEXT (1 << 8) /**< LEXT used as RTC clock. */ -#define AT32_ERTCSEL_LICK (2 << 8) /**< LICK used as RTC clock. */ -#define AT32_ERTCSEL_HEXTDIV (3 << 8) /**< HEXT divided used as - RTC clock. */ -/** @} */ - -/** - * @name CRM_MISC1 register bits definitions - * @{ - */ -#define AT32_HICKDIV_MASK (1 << 12) /**< HICKDIV mask. */ -#define AT32_HICKDIV_DIV6 (0 << 12) /**< HICK divided by 6. */ -#define AT32_HICKDIV_DIV1 (1 << 12) /**< HICK divided by 1. */ - -#define AT32_HICK_TO_SCLK_MASK (1 << 14) /**< HICK_TO_SCLK mask. */ -#define AT32_HICK_TO_SCLK_8M (0 << 14) /**< SCLK is 8MHz if SCLK - is HICK. */ -#define AT32_HICK_TO_SCLK_HICKOUT (1 << 14) /**< SCLK is HICKOUT if SCLK - is HICK. */ - -#define AT32_CLKOUTDIV2_MASK (15 << 28) /**< CLKOUTDIV2 mask. */ -#define AT32_CLKOUTDIV2_DIV1 (0 << 28) /**< CLKOUT divided by 1. */ -#define AT32_CLKOUTDIV2_DIV2 (8 << 28) /**< CLKOUT divided by 2. */ -#define AT32_CLKOUTDIV2_DIV4 (9 << 28) /**< CLKOUT divided by 4. */ -#define AT32_CLKOUTDIV2_DIV8 (10 << 28) /**< CLKOUT divided by 8. */ -#define AT32_CLKOUTDIV2_DIV16 (11 << 28) /**< CLKOUT divided by 16. */ -#define AT32_CLKOUTDIV2_DIV64 (12 << 28) /**< CLKOUT divided by 64. */ -#define AT32_CLKOUTDIV2_DIV128 (13 << 28) /**< CLKOUT divided by 128. */ -#define AT32_CLKOUTDIV2_DIV256 (14 << 28) /**< CLKOUT divided by 256. */ -#define AT32_CLKOUTDIV2_DIV512 (15 << 28) /**< CLKOUT divided by 512. */ -/** @} */ - -/** - * @name CRM_MISC2 register bits definitions - * @{ - */ -#define AT32_PLLU_USB48_SEL_MASK (1 << 10) /**< PLLU_USB48_SEL mask. */ -#define AT32_PLLU_USB48_SEL_PLLU (0 << 10) /**< PLLU_USB48_SEL PLLU. */ -#define AT32_PLLU_USB48_SEL_HICK (1 << 10) /**< PLLU_USB48_SEL HICK. */ - -#define AT32_HICK_TO_SCLK_DIV_MASK (7 << 16) /**< HICK_TO_SCLK_DIV mask. */ -#define AT32_HICK_TO_SCLK_DIV_DIV1 (0 << 16) /**< HICK divided by 1. */ -#define AT32_HICK_TO_SCLK_DIV_DIV2 (1 << 16) /**< HICK divided by 2. */ -#define AT32_HICK_TO_SCLK_DIV_DIV4 (2 << 16) /**< HICK divided by 4. */ -#define AT32_HICK_TO_SCLK_DIV_DIV8 (3 << 16) /**< HICK divided by 8. */ -#define AT32_HICK_TO_SCLK_DIV_DIV16 (4 << 16) /**< HICK divided by 16. */ - -#define AT32_HEXT_TO_SCLK_DIV_MASK (7 << 19) /**< HEXT_TO_SCLK_DIV mask. */ -#define AT32_HEXT_TO_SCLK_DIV_DIV1 (0 << 19) /**< HEXT divided by 1. */ -#define AT32_HEXT_TO_SCLK_DIV_DIV2 (1 << 19) /**< HEXT divided by 2. */ -#define AT32_HEXT_TO_SCLK_DIV_DIV4 (2 << 19) /**< HEXT divided by 4. */ -#define AT32_HEXT_TO_SCLK_DIV_DIV8 (3 << 19) /**< HEXT divided by 8. */ -#define AT32_HEXT_TO_SCLK_DIV_DIV16 (4 << 19) /**< HEXT divided by 16. */ -#define AT32_HEXT_TO_SCLK_DIV_DIV32 (5 << 19) /**< HEXT divided by 32. */ -/** @} */ - -/** - * @name SYSTICK_CTRL register bits definitions - * @{ - */ -#define AT32_SYSTICK_CLKSRC_HCLKDIV8 (0 << 0) /**< Systick clk is hclk/8 */ -#define AT32_SYSTICK_CLKSRC_HCLKDIV1 (4 << 0) /**< Systick clk is hclk. */ -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief Disables the PWR/CRM initialization in the HAL. - */ -#if !defined(AT32_NO_INIT) || defined(__DOXYGEN__) -#define AT32_NO_INIT FALSE -#endif - -/** - * @brief Enables or disables the programmable voltage detector. - */ -#if !defined(AT32_PVM_ENABLE) || defined(__DOXYGEN__) -#define AT32_PVM_ENABLE FALSE -#endif - -/** - * @brief Sets voltage level for programmable voltage detector. - */ -#if !defined(AT32_PVM) || defined(__DOXYGEN__) -#define AT32_PVM AT32_PVMSEL_LEV0 -#endif - -/** - * @brief Enables or disables the HICK clock source. - */ -#if !defined(AT32_HICK_ENABLED) || defined(__DOXYGEN__) -#define AT32_HICK_ENABLED TRUE -#endif - -/** - * @brief Enables or disables the LICK clock source. - */ -#if !defined(AT32_LICK_ENABLED) || defined(__DOXYGEN__) -#define AT32_LICK_ENABLED FALSE -#endif - -/** - * @brief Enables or disables the HEXT clock source. - */ -#if !defined(AT32_HEXT_ENABLED) || defined(__DOXYGEN__) -#define AT32_HEXT_ENABLED TRUE -#endif - -/** - * @brief Enables or disables the LEXT clock source. - */ -#if !defined(AT32_LEXT_ENABLED) || defined(__DOXYGEN__) -#define AT32_LEXT_ENABLED FALSE -#endif - -/** - * @brief Enables or disables the PLLU clock source. - */ -#if !defined(AT32_PLLU_ENABLED) || defined(__DOXYGEN__) -#define AT32_PLLU_ENABLED TRUE -#endif - -/** - * @brief USB clock setting. - */ -#if !defined(AT32_CLOCK48_REQUIRED) || defined(__DOXYGEN__) -#define AT32_CLOCK48_REQUIRED TRUE -#endif - -/** - * @brief USB clock source selection. - */ -#if !defined(AT32_PLLU_USB48_SEL) || defined(__DOXYGEN__) -#define AT32_PLLU_USB48_SEL AT32_PLLU_USB48_SEL_PLLU -#endif - -/** - * @brief Main clock source selection. - * @note If the selected clock source is not the PLL then the PLL is not - * initialized and started. - * @note The default value is calculated for a 216MHz system clock from - * a 12MHz crystal using the PLL. - */ -#if !defined(AT32_SCLKSEL) || defined(__DOXYGEN__) -#define AT32_SCLKSEL AT32_SCLKSEL_PLL -#endif - -/** - * @brief Clock source for the PLL. - * @note This setting has only effect if the PLL is selected as the - * system clock source. - * @note The default value is calculated for a 216MHz system clock from - * a 12MHz crystal using the PLL. - */ -#if !defined(AT32_PLLRCS) || defined(__DOXYGEN__) -#define AT32_PLLRCS AT32_PLLRCS_HEXT -#endif - -/** - * @brief PLL_MS divider value. - * @note The allowed values are 1..15. - * @note The default value is calculated for a 216MHz system clock from - * a 12MHz crystal using the PLL. - */ -#if !defined(AT32_PLL_MS_VALUE) || defined(__DOXYGEN__) -#define AT32_PLL_MS_VALUE 1 -#endif - -/** - * @brief PLL_NS multiplier value. - * @note The allowed values are 31..500. - * @note The default value is calculated for a 216MHz system clock from - * a 12MHz crystal using the PLL. - */ -#if !defined(AT32_PLL_NS_VALUE) || defined(__DOXYGEN__) -#define AT32_PLL_NS_VALUE 72 -#endif - -/** - * @brief PLL_FP divider value. - * @note The allowed values are 1, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, - * 22, 24, 26, 28, 30. - * @note The default value is calculated for a 216MHz system clock from - * a 12MHz crystal using the PLL. - */ -#if !defined(AT32_PLL_FP_VALUE) || defined(__DOXYGEN__) -#define AT32_PLL_FP_VALUE 4 -#endif - -/** - * @brief PLL_FU divider value. - * @note The allowed values are 11, 12, 13, 14, 16, 18, 20. - * @note The default value is calculated for a 216MHz system clock from - * a 12MHz crystal using the PLL. - */ -#if !defined(AT32_PLL_FU_VALUE) || defined(__DOXYGEN__) -#define AT32_PLL_FU_VALUE 18 -#endif - -/** - * @brief AHB prescaler value. - * @note The default value is calculated for a 216MHz system clock from - * a 12MHz crystal using the PLL. - */ -#if !defined(AT32_AHBDIV) || defined(__DOXYGEN__) -#define AT32_AHBDIV AT32_AHBDIV_DIV1 -#endif - -/** - * @brief APB1 prescaler value. - */ -#if !defined(AT32_APB1DIV) || defined(__DOXYGEN__) -#define AT32_APB1DIV AT32_APB1DIV_DIV2 -#endif - -/** - * @brief APB2 prescaler value. - */ -#if !defined(AT32_APB2DIV) || defined(__DOXYGEN__) -#define AT32_APB2DIV AT32_APB2DIV_DIV1 -#endif - -/** - * @brief HICK source selection if SCLK is HICK. - */ -#if !defined(AT32_HICK_TO_SCLK) || defined(__DOXYGEN__) -#define AT32_HICK_TO_SCLK AT32_HICK_TO_SCLK_HICKOUT -#endif - -/** - * @brief HICK prescaler selection. - */ -#if !defined(AT32_HICKDIV) || defined(__DOXYGEN__) -#define AT32_HICKDIV AT32_HICKDIV_DIV1 -#endif - -/** - * @brief HICK prescaler value when SCLK is HICK. - */ -#if !defined(AT32_HICK_TO_SCLK_DIV) || defined(__DOXYGEN__) -#define AT32_HICK_TO_SCLK_DIV AT32_HICK_TO_SCLK_DIV_DIV1 -#endif - -/** - * @brief HEXT prescaler value when SCLK is HEXT. - */ -#if !defined(AT32_HEXT_TO_SCLK_DIV) || defined(__DOXYGEN__) -#define AT32_HEXT_TO_SCLK_DIV AT32_HEXT_TO_SCLK_DIV_DIV1 -#endif - -/** - * @brief ERTC clock source. - */ -#if !defined(AT32_ERTCSEL) || defined(__DOXYGEN__) -#define AT32_ERTCSEL AT32_ERTCSEL_NOCLOCK -#endif - -/** - * @brief ERTC HEXT prescaler value. - * @note The allowed values are 2..31. - */ -#if !defined(AT32_ERTCDIV_VALUE) || defined(__DOXYGEN__) -#define AT32_ERTCDIV_VALUE 12 -#endif - -/** - * @brief I2SF5 clock source. - */ -#if !defined(AT32_I2SF5CLKSEL) || defined(__DOXYGEN__) -#define AT32_I2SF5CLKSEL AT32_I2SF5CLKSEL_SCLK -#endif - -/** - * @brief CLKOUT pin setting. - */ -#if !defined(AT32_CLKOUT_SEL) || defined(__DOXYGEN__) -#define AT32_CLKOUT_SEL AT32_CLKOUT_SEL_HICK -#endif - -/** - * @brief CLKOUT prescaler value 1. - */ -#if !defined(AT32_CLKOUTDIV1) || defined(__DOXYGEN__) -#define AT32_CLKOUTDIV1 AT32_CLKOUTDIV1_DIV1 -#endif - -/** - * @brief CLKOUT prescaler value 2. - */ -#if !defined(AT32_CLKOUTDIV2) || defined(__DOXYGEN__) -#define AT32_CLKOUTDIV2 AT32_CLKOUTDIV2_DIV1 -#endif - -/** - * @brief LDOOVSEL setting. - */ -#if !defined(AT32_LDOOVSEL) || defined(__DOXYGEN__) -#define AT32_LDOOVSEL AT32_LDOOVSEL_1P3V -#endif - -/** - * @brief Systick clock source setting. - */ -#if !defined(AT32_SYSTICK_CLKSRC) || defined(__DOXYGEN__) -#define AT32_SYSTICK_CLKSRC AT32_SYSTICK_CLKSRC_HCLKDIV1 -#endif - -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/* - * Configuration-related checks. - */ -#if !defined(AT32F405xx_MCUCONF) -#error "Using a wrong mcuconf.h file, AT32F405xx_MCUCONF not defined" -#endif - -/* - * Board files sanity checks. - */ -#if !defined(AT32_LEXTCLK) -#error "AT32_LEXTCLK not defined in board.h" -#endif - -#if !defined(AT32_HEXTCLK) -#error "AT32_HEXTCLK not defined in board.h" -#endif - -/* - * HICK related checks. - */ -#if AT32_HICK_ENABLED -#else /* !AT32_HICK_ENABLED */ - -#if AT32_SCLKSEL == AT32_SCLKSEL_HICK -#error "HICK not enabled, required by AT32_SCLKSEL" -#endif - -#if ((AT32_SCLKSEL == AT32_SCLKSEL_HICK) && \ - (AT32_PLLRCS == AT32_PLLRCS_HICK)) -#error "HICK not enabled, required by AT32_SCLKSEL and AT32_PLLRCS" -#endif - -#if (AT32_CLKOUT_SEL == AT32_CLKOUT_SEL_HICK) || \ - ((AT32_CLKOUT_SEL == AT32_CLKOUT_SEL_PLL) && \ - (AT32_PLLRCS == AT32_PLLRCS_HICK)) -#error "HICK not enabled, required by AT32_CLKOUT_SEL" -#endif - -#if (AT32_PLLU_USB48_SEL == AT32_PLLU_USB48_SEL_HICK) || \ - ((AT32_PLLU_USB48_SEL == AT32_PLLU_USB48_SEL_PLLU) && \ - (AT32_PLLRCS == AT32_PLLRCS_HICK)) -#error "HICK not enabled, required by AT32_PLLU_USB48_SEL" -#endif - -#if (AT32_I2SF5CLKSEL == AT32_I2SF5CLKSEL_HICK) || \ - ((AT32_I2SF5CLKSEL == AT32_I2SF5CLKSEL_PLL) && \ - (AT32_PLLRCS == AT32_PLLRCS_HICK)) || \ - ((AT32_I2SF5CLKSEL == AT32_I2SF5CLKSEL_SCLK) && \ - (AT32_SCLKSEL == AT32_SCLKSEL_HICK)) || \ - ((AT32_I2SF5CLKSEL == AT32_I2SF5CLKSEL_SCLK) && \ - (AT32_SCLKSEL == AT32_SCLKSEL_PLL) && \ - (AT32_PLLRCS == AT32_PLLRCS_HICK)) -#error "HICK not enabled, required by AT32_I2SF5CLKSEL" -#endif - -#endif /* !AT32_HICK_ENABLED */ - -/* - * HEXT related checks. - */ -#if AT32_HEXT_ENABLED - -#if AT32_HEXTCLK == 0 -#error "HEXT frequency not defined" -#else /* AT32_HEXTCLK != 0 */ -#if defined(AT32_HEXT_BYPASS) -#if (AT32_HEXTCLK < AT32_HEXTCLK_BYP_MIN) || (AT32_HEXTCLK > AT32_HEXTCLK_BYP_MAX) -#error "AT32_HEXTCLK outside acceptable range (AT32_HEXTCLK_MIN...AT32_HEXTCLK_BYP_MAX)" -#endif -#else /* !defined(AT32_HEXT_BYPASS) */ -#if (AT32_HEXTCLK < AT32_HEXTCLK_MIN) || (AT32_HEXTCLK > AT32_HEXTCLK_MAX) -#error "AT32_HEXTCLK outside acceptable range (AT32_HEXTCLK_MIN...AT32_HEXTCLK_MAX)" -#endif -#endif /* !defined(AT32_HEXT_BYPASS) */ -#endif /* AT32_HEXTCLK != 0 */ - -#else /* !AT32_HEXT_ENABLED */ - -#if AT32_SCLKSEL == AT32_SCLKSEL_HEXT -#error "HEXT not enabled, required by AT32_SCLKSEL" -#endif - -#if (AT32_SCLKSEL == AT32_SCLKSEL_PLL) && (AT32_PLLRCS == AT32_PLLRCS_HEXT) -#error "HEXT not enabled, required by AT32_SCLKSEL and AT32_PLLRCS" -#endif - -#if (AT32_CLKOUT_SEL == AT32_CLKOUT_SEL_HEXT) || \ - ((AT32_CLKOUT_SEL == AT32_CLKOUT_SEL_PLL) && \ - (AT32_PLLRCS == AT32_PLLRCS_HEXT)) -#error "HEXT not enabled, required by AT32_CLKOUT_SEL" -#endif - -#if AT32_ERTCSEL == AT32_ERTCSEL_HEXTDIV -#error "HEXT not enabled, required by AT32_ERTCSEL" -#endif - -#if ((AT32_I2SF5CLKSEL == AT32_I2SF5CLKSEL_PLL) && \ - (AT32_PLLRCS == AT32_PLLRCS_HEXT)) || \ - ((AT32_I2SF5CLKSEL == AT32_I2SF5CLKSEL_SCLK) && \ - (AT32_SCLKSEL == AT32_SCLKSEL_HEXT)) || \ - ((AT32_I2SF5CLKSEL == AT32_I2SF5CLKSEL_SCLK) && \ - (AT32_SCLKSEL == AT32_SCLKSEL_PLL) && \ - (AT32_PLLRCS == AT32_PLLRCS_HEXT)) -#error "HICK not enabled, required by AT32_I2SF5CLKSEL" -#endif - -#endif /* !AT32_HEXT_ENABLED */ - -#if AT32_LICK_ENABLED -#else /* !AT32_LICK_ENABLED */ - -#if AT32_CLKOUT_SEL == AT32_CLKOUT_SEL_LICK -#error "LICK not enabled, required by AT32_CLKOUT_SEL" -#endif -#if HAL_USE_RTC && (AT32_ERTCSEL == AT32_ERTCSEL_LICK) -#error "LICK not enabled, required by AT32_ERTCSEL" -#endif -#endif /* !AT32_LICK_ENABLED */ - -/* LEXT related checks.*/ -#if AT32_LEXT_ENABLED -#if (AT32_LEXTCLK == 0) -#error "impossible to activate LEXT, frequency is zero" -#endif - -#if (AT32_LEXTCLK < AT32_LEXTCLK_MIN) || (AT32_LEXTCLK > AT32_LEXTCLK_MAX) -#error "AT32_LEXTCLK outside acceptable range (AT32_LEXTCLK_MIN...AT32_LEXTCLK_MAX)" -#endif - -#else /* !AT32_LEXT_ENABLED */ - -#if AT32_CLKOUT_SEL == AT32_CLKOUT_SEL_LEXT -#error "LEXT not enabled, required by AT32_CLKOUT_SEL" -#endif -#if AT32_ERTCSEL == AT32_ERTCSEL_LEXT -#error "LEXT not enabled, required by AT32_ERTCSEL" -#endif -#endif /* !AT32_LEXT_ENABLED */ - -#if AT32_PLLU_ENABLED -#else /* !AT32_PLLU_ENABLED */ - -#if AT32_PLLU_USB48_SEL == AT32_PLLU_USB48_SEL_PLLU -#error "PLLU not enabled, required by AT32_PLLU_USB48_SEL" -#endif -#endif /* !AT32_PLLU_ENABLED */ - -/** - * @brief AT32_PLL_MS field. - */ -#if ((AT32_PLL_MS_VALUE >= 1) && (AT32_PLL_MS_VALUE <= 15)) || \ - defined(__DOXYGEN__) -#define AT32_PLL_MS (AT32_PLL_MS_VALUE << 0) -#else -#error "invalid AT32_PLL_MS_VALUE value specified" -#endif - -/** - * @brief HICK output clock frequency. - */ -#if (AT32_HICKDIV == AT32_HICKDIV_DIV1) || defined(__DOXYGEN__) -#define AT32_HICKCLKOUT (AT32_HICKCLK / 1) -#elif (AT32_HICKDIV == AT32_HICKDIV_DIV6) -#define AT32_HICKCLKOUT (AT32_HICKCLK / 6) -#else -#error "invalid AT32_HICKDIV value specified" -#endif - -/** - * @brief PLLs input clock frequency. - */ -#if (AT32_PLLRCS == AT32_PLLRCS_HEXT) || defined(__DOXYGEN__) -#define AT32_PLLCLKIN (AT32_HEXTCLK / AT32_PLL_MS_VALUE) -#elif AT32_PLLRCS == AT32_PLLRCS_HICK -#define AT32_PLLCLKIN ((AT32_HICKCLK / 6) / AT32_PLL_MS_VALUE) -#else -#error "invalid AT32_PLLRCS value specified" -#endif - -/* - * PLLs input frequency range check. - */ -#if (AT32_PLLCLKIN < AT32_PLLIN_MIN) || (AT32_PLLCLKIN > AT32_PLLIN_MAX) -#error "AT32_PLLCLKIN outside acceptable range (AT32_PLLIN_MIN...AT32_PLLIN_MAX)" -#endif - -/* - * PLL enable check. - */ -#if (AT32_CLOCK48_REQUIRED && (AT32_PLLU_USB48_SEL == AT32_PLLU_USB48_SEL_PLLU)) || \ - (AT32_SCLKSEL == AT32_SCLKSEL_PLL) || \ - (AT32_I2SF5CLKSEL == AT32_I2SF5CLKSEL_PLL) || \ - (AT32_CLKOUT_SEL == AT32_CLKOUT_SEL_PLL) || \ - (AT32_PLLU_ENABLED) || defined(__DOXYGEN__) -/** - * @brief PLL activation flag. - */ -#define AT32_ACTIVATE_PLL TRUE -#else -#define AT32_ACTIVATE_PLL FALSE -#endif - -/** - * @brief AT32_PLL_NS field. - */ -#if ((AT32_PLL_NS_VALUE >= 31) && (AT32_PLL_NS_VALUE <= 500)) || \ - defined(__DOXYGEN__) -#define AT32_PLL_NS (AT32_PLL_NS_VALUE << 6) -#else -#error "invalid AT32_PLL_NS_VALUE value specified" -#endif - -/** - * @brief AT32_PLL_FP field. - */ -#if (AT32_PLL_FP_VALUE == 1) || defined(__DOXYGEN__) -#define AT32_PLL_FP AT32_PLL_FP_DIV1 -#elif AT32_PLL_FP_VALUE == 2 -#define AT32_PLL_FP AT32_PLL_FP_DIV2 -#elif AT32_PLL_FP_VALUE == 4 -#define AT32_PLL_FP AT32_PLL_FP_DIV4 -#elif AT32_PLL_FP_VALUE == 6 -#define AT32_PLL_FP AT32_PLL_FP_DIV6 -#elif AT32_PLL_FP_VALUE == 8 -#define AT32_PLL_FP AT32_PLL_FP_DIV8 -#elif AT32_PLL_FP_VALUE == 10 -#define AT32_PLL_FP AT32_PLL_FP_DIV10 -#elif AT32_PLL_FP_VALUE == 12 -#define AT32_PLL_FP AT32_PLL_FP_DIV12 -#elif AT32_PLL_FP_VALUE == 14 -#define AT32_PLL_FP AT32_PLL_FP_DIV14 -#elif AT32_PLL_FP_VALUE == 16 -#define AT32_PLL_FP AT32_PLL_FP_DIV16 -#elif AT32_PLL_FP_VALUE == 18 -#define AT32_PLL_FP AT32_PLL_FP_DIV18 -#elif AT32_PLL_FP_VALUE == 20 -#define AT32_PLL_FP AT32_PLL_FP_DIV20 -#else -#error "invalid AT32_PLL_FP_VALUE value specified" -#endif - -/** - * @brief AT32_PLL_FU field. - */ -#if (AT32_PLL_FU_VALUE == 11) || defined(__DOXYGEN__) -#define AT32_PLL_FU AT32_PLL_FU_DIV11 -#elif AT32_PLL_FU_VALUE == 12 -#define AT32_PLL_FU AT32_PLL_FU_DIV12 -#elif AT32_PLL_FU_VALUE == 13 -#define AT32_PLL_FU AT32_PLL_FU_DIV13 -#elif AT32_PLL_FU_VALUE == 14 -#define AT32_PLL_FU AT32_PLL_FU_DIV14 -#elif AT32_PLL_FU_VALUE == 16 -#define AT32_PLL_FU AT32_PLL_FU_DIV16 -#elif AT32_PLL_FU_VALUE == 18 -#define AT32_PLL_FU AT32_PLL_FU_DIV18 -#elif AT32_PLL_FU_VALUE == 20 -#define AT32_PLL_FU AT32_PLL_FU_DIV20 -#else -#error "invalid AT32_PLL_FU_VALUE value specified" -#endif - -/** - * @brief PLL VCO frequency. - */ -#define AT32_PLLVCO (AT32_PLLCLKIN * AT32_PLL_NS_VALUE) - -/* - * PLL VCO frequency range check. - */ -#if (AT32_PLLVCO < AT32_PLLVCO_MIN) || (AT32_PLLVCO > AT32_PLLVCO_MAX) -#error "AT32_PLLVCO outside acceptable range (AT32_PLLVCO_MIN...AT32_PLLVCO_MAX)" -#endif - -/** - * @brief PLL PCLK output clock frequency. - */ -#define AT32_PLLPCLK (AT32_PLLVCO / AT32_PLL_FP_VALUE) - -/* - * PLL PCLK frequency range check. - */ -#if (AT32_PLLPCLK < AT32_PLLOUT_MIN) || (AT32_PLLPCLK > AT32_PLLOUT_MAX) -#error "AT32_PLLPCLK outside acceptable range (AT32_PLLOUT_MIN...AT32_PLLOUT_MAX)" -#endif - -/** - * @brief PLL UCLK output clock frequency. - */ -#define AT32_PLLUCLK (AT32_PLLVCO / AT32_PLL_FU_VALUE) - -/* - * PLL UCLK frequency range check. - */ -#if (AT32_PLLUCLK < AT32_PLLOUT_MIN) || (AT32_PLLUCLK > AT32_PLLOUT_MAX) -#error "AT32_PLLUCLK outside acceptable range (AT32_PLLOUT_MIN...AT32_PLLOUT_MAX)" -#endif - -/** - * @brief System clock source. - */ -#if AT32_NO_INIT || (AT32_SCLKSEL == AT32_SCLKSEL_HICK) || \ - defined(__DOXYGEN__) - -#if (AT32_HICK_TO_SCLK == AT32_HICK_TO_SCLK_8M) || defined(__DOXYGEN__) -#define AT32_SYSCLKIN (8000000) -#elif (AT32_HICK_TO_SCLK == AT32_HICK_TO_SCLK_HICKOUT) -#define AT32_SYSCLKIN (AT32_HICKCLKOUT) -#else -#error "invalid AT32_HICK_TO_SCLK value specified" -#endif - -#if (AT32_HICK_TO_SCLK_DIV == AT32_HICK_TO_SCLK_DIV_DIV1) || defined(__DOXYGEN__) -#define AT32_SYSCLK (AT32_SYSCLKIN / 1) -#elif (AT32_HICK_TO_SCLK_DIV == AT32_HICK_TO_SCLK_DIV_DIV2) -#define AT32_SYSCLK (AT32_SYSCLKIN / 2) -#elif (AT32_HICK_TO_SCLK_DIV == AT32_HICK_TO_SCLK_DIV_DIV4) -#define AT32_SYSCLK (AT32_SYSCLKIN / 4) -#elif (AT32_HICK_TO_SCLK_DIV == AT32_HICK_TO_SCLK_DIV_DIV8) -#define AT32_SYSCLK (AT32_SYSCLKIN / 8) -#elif (AT32_HICK_TO_SCLK_DIV == AT32_HICK_TO_SCLK_DIV_DIV16) -#define AT32_SYSCLK (AT32_SYSCLKIN / 16) -#else -#error "invalid AT32_HICK_TO_SCLK_DIV value specified" -#endif - -#elif AT32_SCLKSEL == AT32_SCLKSEL_HEXT - -#if (AT32_HEXT_TO_SCLK_DIV == AT32_HEXT_TO_SCLK_DIV_DIV1) -#define AT32_SYSCLK (AT32_HEXTCLK / 1) -#elif (AT32_HEXT_TO_SCLK_DIV == AT32_HEXT_TO_SCLK_DIV_DIV2) -#define AT32_SYSCLK (AT32_HEXTCLK / 2) -#elif (AT32_HEXT_TO_SCLK_DIV == AT32_HEXT_TO_SCLK_DIV_DIV4) -#define AT32_SYSCLK (AT32_HEXTCLK / 4) -#elif (AT32_HEXT_TO_SCLK_DIV == AT32_HEXT_TO_SCLK_DIV_DIV8) -#define AT32_SYSCLK (AT32_HEXTCLK / 8) -#elif (AT32_HEXT_TO_SCLK_DIV == AT32_HEXT_TO_SCLK_DIV_DIV16) -#define AT32_SYSCLK (AT32_HEXTCLK / 16) -#elif (AT32_HEXT_TO_SCLK_DIV == AT32_HEXT_TO_SCLK_DIV_DIV32) -#define AT32_SYSCLK (AT32_HEXTCLK / 32) -#else -#error "invalid AT32_HEXT_TO_SCLK_DIV value specified" -#endif - -#elif AT32_SCLKSEL == AT32_SCLKSEL_PLL - -#define AT32_SYSCLK AT32_PLLPCLK - -#else -#error "invalid AT32_SCLKSEL value specified" -#endif - -/* Check on the system clock.*/ -#if AT32_SYSCLK > AT32_SYSCLK_MAX -#error "AT32_SYSCLK above maximum rated frequency (AT32_SYSCLK_MAX)" -#endif - -/** - * @brief AHB frequency. - */ -#if (AT32_AHBDIV == AT32_AHBDIV_DIV1) || defined(__DOXYGEN__) -#define AT32_HCLK (AT32_SYSCLK / 1) -#elif AT32_AHBDIV == AT32_AHBDIV_DIV2 -#define AT32_HCLK (AT32_SYSCLK / 2) -#elif AT32_AHBDIV == AT32_AHBDIV_DIV4 -#define AT32_HCLK (AT32_SYSCLK / 4) -#elif AT32_AHBDIV == AT32_AHBDIV_DIV8 -#define AT32_HCLK (AT32_SYSCLK / 8) -#elif AT32_AHBDIV == AT32_AHBDIV_DIV16 -#define AT32_HCLK (AT32_SYSCLK / 16) -#elif AT32_AHBDIV == AT32_AHBDIV_DIV64 -#define AT32_HCLK (AT32_SYSCLK / 64) -#elif AT32_AHBDIV == AT32_AHBDIV_DIV128 -#define AT32_HCLK (AT32_SYSCLK / 128) -#elif AT32_AHBDIV == AT32_AHBDIV_DIV256 -#define AT32_HCLK (AT32_SYSCLK / 256) -#elif AT32_AHBDIV == AT32_AHBDIV_DIV512 -#define AT32_HCLK (AT32_SYSCLK / 512) -#else -#error "invalid AT32_AHBDIV value specified" -#endif - -/* AHB frequency check.*/ -#if AT32_HCLK > AT32_SYSCLK_MAX -#error "AT32_HCLK exceeding maximum frequency (AT32_SYSCLK_MAX)" -#endif - -/** - * @brief APB1 frequency. - */ -#if (AT32_APB1DIV == AT32_APB1DIV_DIV1) || defined(__DOXYGEN__) -#define AT32_PCLK1 (AT32_HCLK / 1) -#elif AT32_APB1DIV == AT32_APB1DIV_DIV2 -#define AT32_PCLK1 (AT32_HCLK / 2) -#elif AT32_APB1DIV == AT32_APB1DIV_DIV4 -#define AT32_PCLK1 (AT32_HCLK / 4) -#elif AT32_APB1DIV == AT32_APB1DIV_DIV8 -#define AT32_PCLK1 (AT32_HCLK / 8) -#elif AT32_APB1DIV == AT32_APB1DIV_DIV16 -#define AT32_PCLK1 (AT32_HCLK / 16) -#else -#error "invalid AT32_APB1DIV value specified" -#endif - -/* APB1 frequency check.*/ -#if AT32_PCLK1 > AT32_PCLK1_MAX -#error "AT32_PCLK1 exceeding maximum frequency (AT32_PCLK1_MAX)" -#endif - -/** - * @brief APB2 frequency. - */ -#if (AT32_APB2DIV == AT32_APB2DIV_DIV1) || defined(__DOXYGEN__) -#define AT32_PCLK2 (AT32_HCLK / 1) -#elif AT32_APB2DIV == AT32_APB2DIV_DIV2 -#define AT32_PCLK2 (AT32_HCLK / 2) -#elif AT32_APB2DIV == AT32_APB2DIV_DIV4 -#define AT32_PCLK2 (AT32_HCLK / 4) -#elif AT32_APB2DIV == AT32_APB2DIV_DIV8 -#define AT32_PCLK2 (AT32_HCLK / 8) -#elif AT32_APB2DIV == AT32_APB2DIV_DIV16 -#define AT32_PCLK2 (AT32_HCLK / 16) -#else -#error "invalid AT32_APB2DIV value specified" -#endif - -/* APB2 frequency check.*/ -#if AT32_PCLK2 > AT32_PCLK2_MAX -#error "AT32_PCLK2 exceeding maximum frequency (AT32_PCLK2_MAX)" -#endif - -/* Check on LDOOVSEL value.*/ -#if AT32_LDOOVSEL == AT32_LDOOVSEL_1P3V - -#if (AT32_HCLK > 216000000) || \ - (AT32_PCLK1 > 120000000) || \ - (AT32_PCLK2 > AT32_HCLK) -#error "AT32 bus clock exceeding maximum frequency when LDO is 1.3V" -#endif - -#elif AT32_LDOOVSEL == AT32_LDOOVSEL_1P2V - -#if (AT32_HCLK > 168000000) || \ - (AT32_PCLK1 > 120000000) || \ - (AT32_PCLK2 > AT32_HCLK) -#error "AT32 bus clock exceeding maximum frequency when LDO is 1.2V" -#endif - -#elif ((AT32_LDOOVSEL == AT32_LDOOVSEL_1P1V) || \ - (AT32_LDOOVSEL == AT32_LDOOVSEL_1P0V)) - -#if (AT32_HCLK > 108000000) || \ - (AT32_PCLK1 > AT32_HCLK) || \ - (AT32_PCLK2 > AT32_HCLK) -#error "AT32 bus clock exceeding maximum frequency when LDO is 1.0V" -#endif - -#else -#error "invalid AT32_LDOOVSEL value specified" -#endif - -/** - * @brief USB clock. - */ -#if AT32_PLLU_USB48_SEL == AT32_PLLU_USB48_SEL_PLLU -#define AT32_USBCLK AT32_PLLUCLK -#elif AT32_PLLU_USB48_SEL == AT32_PLLU_USB48_SEL_HICK -#define AT32_USBCLK AT32_HICKCLKOUT -#else -#error "invalid AT32_PLLU_USB48_SEL value specified" -#endif - -/** - * @brief HEXT divider toward ERTC clock. - */ -#if ((AT32_ERTCDIV_VALUE >= 2) && (AT32_ERTCDIV_VALUE <= 31)) || \ - defined(__DOXYGEN__) -#define AT32_HEXTDIVCLK (AT32_HEXTCLK / AT32_ERTCDIV_VALUE) -#define AT32_ETRCDIV (AT32_ERTCDIV_VALUE << 16) -#else -#error "invalid AT32_ERTCDIV value specified" -#endif - -/** - * @brief ERTC clock. - */ -#if (AT32_ERTCSEL == AT32_ERTCSEL_NOCLOCK) || defined(__DOXYGEN__) -#define AT32_ERTCCLK 0 -#elif AT32_ERTCSEL == AT32_ERTCSEL_LEXT -#define AT32_ERTCCLK AT32_LEXTCLK -#elif AT32_ERTCSEL == AT32_ERTCSEL_LICK -#define AT32_ERTCCLK AT32_LICKCLK -#elif AT32_ERTCSEL == AT32_ERTCSEL_HEXTDIV -#define AT32_ERTCCLK AT32_HEXTDIVCLK -#else -#error "invalid AT32_ERTCSEL value specified" -#endif - -/** - * @brief I2SF5 clock. - */ -#if (AT32_I2SF5CLKSEL == AT32_I2SF5CLKSEL_SCLK) || defined(__DOXYGEN__) -#define AT32_I2SF5CLK AT32_SYSCLK -#elif AT32_I2SF5CLKSEL == AT32_I2SF5CLKSEL_PLL -#define AT32_I2SF5CLK AT32_PLLPCLK -#elif AT32_I2SF5CLKSEL == AT32_I2SF5CLKSEL_HICK -#define AT32_I2SF5CLK AT32_HICKCLKOUT -#elif AT32_I2SF5CLKSEL == AT32_I2SF5CLKSEL_EXCLK -#define AT32_I2SF5CLK 0 -#else -#error "invalid AT32_I2SF5CLKSEL value specified" -#endif - - -/** - * @brief Systick clock. - */ -#if (AT32_SYSTICK_CLKSRC == AT32_SYSTICK_CLKSRC_HCLKDIV1) || defined(__DOXYGEN__) -#define AT32_SYSTICK_CLK AT32_HCLK -#elif AT32_SYSTICK_CLKSRC == AT32_SYSTICK_CLKSRC_HCLKDIV8 -#define AT32_SYSTICK_CLK (AT32_HCLK / 8) -#else -#error "invalid AT32_SYSTICK_CLKSRC value specified" -#endif - -/** - * @brief Timers 2, 3, 4, 6, 7, 13, 14 clock. - */ -#if (AT32_APB1DIV == AT32_APB1DIV_DIV1) || defined(__DOXYGEN__) -#define AT32_TMRCLK1 (AT32_PCLK1 * 1) -#else -#define AT32_TMRCLK1 (AT32_PCLK1 * 2) -#endif - -/** - * @brief Timers 1, 9, 10, 11 clock. - */ -#if (AT32_APB2DIV == AT32_APB2DIV_DIV1) || defined(__DOXYGEN__) -#define AT32_TMRCLK2 (AT32_PCLK2 * 1) -#else -#define AT32_TMRCLK2 (AT32_PCLK2 * 2) -#endif - -/** - * @brief Flash settings. - */ -#if (AT32_HCLK <= 32000000) || defined(__DOXYGEN__) -#define AT32_FLASHBITS 0x00000150 -#elif (AT32_HCLK <= 64000000) -#define AT32_FLASHBITS 0x00000151 -#elif (AT32_HCLK <= 96000000) -#define AT32_FLASHBITS 0x00000152 -#elif (AT32_HCLK <= 128000000) -#define AT32_FLASHBITS 0x00000153 -#elif (AT32_HCLK <= 160000000) -#define AT32_FLASHBITS 0x00000154 -#elif (AT32_HCLK <= 192000000) -#define AT32_FLASHBITS 0x00000155 -#elif (AT32_HCLK <= 216000000) -#define AT32_FLASHBITS 0x00000156 -#endif - -#define DEBUG_CTRL_TMR2_PAUSE DEBUG_APB1_PAUSE_TMR2_PAUSE -/* Various helpers.*/ -#include "nvic.h" -#include "cache.h" -#include "mpu_v7m.h" -#include "at32_crm.h" -#include "at32_dma.h" -#include "at32_exint.h" -#include "at32_isr.h" -#include "at32_tmr.h" - -#ifdef __cplusplus -extern "C" { -#endif - void hal_lld_init(void); - void at32_clock_init(void); - void at32_clock_reset(void); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_LLD_H */ -/** @} */ diff --git a/os/hal/ports/AT32/AT32F415/at32_crm.h b/os/hal/ports/AT32/AT32F415/at32_crm.h index a0c2ecf34d..715e38c285 100644 --- a/os/hal/ports/AT32/AT32F415/at32_crm.h +++ b/os/hal/ports/AT32/AT32F415/at32_crm.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/AT32F415/at32_dmamux.h b/os/hal/ports/AT32/AT32F415/at32_dmamux.h index e48c61ae2a..b2b0387138 100644 --- a/os/hal/ports/AT32/AT32F415/at32_dmamux.h +++ b/os/hal/ports/AT32/AT32F415/at32_dmamux.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/AT32F415/at32_isr.c b/os/hal/ports/AT32/AT32F415/at32_isr.c index 0ffb999140..4c4ef9a26b 100644 --- a/os/hal/ports/AT32/AT32F415/at32_isr.c +++ b/os/hal/ports/AT32/AT32F415/at32_isr.c @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/AT32F415/at32_isr.h b/os/hal/ports/AT32/AT32F415/at32_isr.h index 277b402f45..da168bec30 100644 --- a/os/hal/ports/AT32/AT32F415/at32_isr.h +++ b/os/hal/ports/AT32/AT32F415/at32_isr.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -52,9 +52,16 @@ /** @} */ /** - * @name ISR names and numbers remapping + * @name ISR names and numbers * @{ */ +/* + * ADC unit. + */ +#define AT32_ADC1_HANDLER Vector88 + +#define AT32_ADC1_NUMBER 18 + /* * CAN unit. */ diff --git a/os/hal/ports/AT32/AT32F415/at32_registry.h b/os/hal/ports/AT32/AT32F415/at32_registry.h index 21888706b9..bc38bdc7c3 100644 --- a/os/hal/ports/AT32/AT32F415/at32_registry.h +++ b/os/hal/ports/AT32/AT32F415/at32_registry.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -27,23 +27,14 @@ #ifndef AT32_REGISTRY_H #define AT32_REGISTRY_H -#if defined(AT32F415KB) -#define AT32F415K_MD +#if defined(AT32F415KB) || defined(AT32F415KC) +#define AT32F415K -#elif defined(AT32F415KC) -#define AT32F415K_HD - -#elif defined(AT32F415CB) -#define AT32F415C_MD - -#elif defined(AT32F415CC) -#define AT32F415C_HD +#elif defined(AT32F415CB) || defined(AT32F415CC) +#define AT32F415C -#elif defined(AT32F415RB) -#define AT32F415R_MD - -#elif defined(AT32F415RC) -#define AT32F415R_HD +#elif defined(AT32F415RB) || defined(AT32F415RC) +#define AT32F415R #else #error "unsupported or unrecognized AT32F415 member" @@ -53,13 +44,15 @@ /* Platform capabilities. */ /*===========================================================================*/ -#if defined(AT32F415K_MD) || defined(__DOXYGEN__) +#if defined(AT32F415K) || defined(__DOXYGEN__) /** - * @name AT32F415K MD capabilities + * @name AT32F415K capabilities * @{ */ /* ADC attributes.*/ #define AT32_HAS_ADC1 TRUE +#define AT32_ADC_SUPPORTS_PRESCALER FALSE +#define AT32_ADC_SUPPORTS_OVERSAMPLING FALSE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) #define AT32_ADC_ADC1_DMA_STREAM AT32_DMA_STREAM_ID(1, 2) @@ -90,235 +83,11 @@ /* FLASH attributes.*/ #define AT32_FLASH_NUMBER_OF_BANKS 1 +#if defined(AT32F415KB) || defined(__DOXYGEN__) #define AT32_FLASH_SECTOR_SIZE 1024U - -#if !defined(AT32_FLASH_SECTORS_PER_BANK) || defined(__DOXYGEN__) -#define AT32_FLASH_SECTORS_PER_BANK 128 /* Maximum, can be redefined.*/ -#endif - -/* GPIO attributes.*/ -#define AT32_HAS_GPIOA TRUE -#define AT32_HAS_GPIOB TRUE -#define AT32_HAS_GPIOD TRUE - -#if !defined(AT32_HAS_GPIOC) || defined(__DOXYGEN__) -#define AT32_HAS_GPIOC FALSE -#elif !defined(AT32_HAS_GPIOF) -#define AT32_HAS_GPIOF FALSE -#endif - -/* I2C attributes.*/ -#define AT32_HAS_I2C1 TRUE - -#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_I2C_I2C1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 3) -#define AT32_I2C_I2C1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) -#define AT32_I2C_I2C1_RX_DMAMUX_CHANNEL 3 -#define AT32_I2C_I2C1_TX_DMAMUX_CHANNEL 4 -#else -#define AT32_I2C_I2C1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) -#define AT32_I2C_I2C1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 6) -#endif - -#define AT32_HAS_I2C2 TRUE - -#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_I2C_I2C2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 3) -#define AT32_I2C_I2C2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) -#define AT32_I2C_I2C2_RX_DMAMUX_CHANNEL 3 -#define AT32_I2C_I2C2_TX_DMAMUX_CHANNEL 4 -#else -#define AT32_I2C_I2C2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) -#define AT32_I2C_I2C2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) -#endif - -#define AT32_HAS_I2C3 FALSE - -/* ERTC attributes.*/ -#define AT32_HAS_ERTC TRUE -#define AT32_ERTC_HAS_SUBSECONDS TRUE -#define AT32_ERTC_HAS_PERIODIC_WAKEUPS TRUE -#define AT32_ERTC_NUM_ALARMS 2 -#define AT32_ERTC_STORAGE_SIZE 80 - -/* QUADSPI attributes.*/ -#define AT32_HAS_QUADSPI1 FALSE - -/* SDIO attributes.*/ -#define AT32_HAS_SDIO TRUE - -#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_SDC_SDIO_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) -#define AT32_SDC_SDIO_DMAMUX_CHANNEL 5 -#else -#define AT32_SDC_SDIO_DMA_STREAM AT32_DMA_STREAM_ID(2, 4) -#endif - -/* SPI attributes.*/ -#define AT32_HAS_SPI1 TRUE -#define AT32_SPI1_SUPPORTS_I2S TRUE -#define AT32_SPI1_I2S_FULLDUPLEX FALSE - -#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_SPI_SPI1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 6) -#define AT32_SPI_SPI1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) -#define AT32_SPI_SPI1_RX_DMAMUX_CHANNEL 6 -#define AT32_SPI_SPI1_TX_DMAMUX_CHANNEL 7 -#else -#define AT32_SPI_SPI1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 2) -#define AT32_SPI_SPI1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 3) -#endif - -#define AT32_HAS_SPI2 TRUE -#define AT32_SPI2_SUPPORTS_I2S TRUE -#define AT32_SPI2_I2S_FULLDUPLEX FALSE - -#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_SPI_SPI2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 6) -#define AT32_SPI_SPI2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) -#define AT32_SPI_SPI2_RX_DMAMUX_CHANNEL 6 -#define AT32_SPI_SPI2_TX_DMAMUX_CHANNEL 7 -#else -#define AT32_SPI_SPI2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) -#define AT32_SPI_SPI2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) -#endif - -#define AT32_HAS_SPI3 FALSE - -/* TMR attributes.*/ -#define AT32_TMR_MAX_CHANNELS 4 - -#define AT32_HAS_TMR1 TRUE -#define AT32_TMR1_IS_32BITS FALSE -#define AT32_TMR1_CHANNELS 4 - -#define AT32_HAS_TMR2 TRUE -#define AT32_TMR2_IS_32BITS TRUE -#define AT32_TMR2_CHANNELS 4 - -#define AT32_HAS_TMR3 TRUE -#define AT32_TMR3_IS_32BITS FALSE -#define AT32_TMR3_CHANNELS 4 - -#define AT32_HAS_TMR4 TRUE -#define AT32_TMR4_IS_32BITS FALSE -#define AT32_TMR4_CHANNELS 4 - -#define AT32_HAS_TMR5 TRUE -#define AT32_TMR5_IS_32BITS TRUE -#define AT32_TMR5_CHANNELS 4 - -#define AT32_HAS_TMR9 TRUE -#define AT32_TMR9_IS_32BITS FALSE -#define AT32_TMR9_CHANNELS 2 - -#define AT32_HAS_TMR10 TRUE -#define AT32_TMR10_IS_32BITS FALSE -#define AT32_TMR10_CHANNELS 1 - -#define AT32_HAS_TMR11 TRUE -#define AT32_TMR11_IS_32BITS FALSE -#define AT32_TMR11_CHANNELS 1 - -#define AT32_HAS_TMR6 FALSE -#define AT32_HAS_TMR7 FALSE -#define AT32_HAS_TMR13 FALSE -#define AT32_HAS_TMR14 FALSE - -/* USART attributes.*/ -#define AT32_HAS_USART1 TRUE - -#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_UART_USART1_RX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) -#define AT32_UART_USART1_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 2) -#define AT32_UART_USART1_RX_DMAMUX_CHANNEL 1 -#define AT32_UART_USART1_TX_DMAMUX_CHANNEL 2 -#else -#define AT32_UART_USART1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) -#define AT32_UART_USART1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) -#endif - -#define AT32_HAS_USART2 TRUE - -#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_UART_USART2_RX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) -#define AT32_UART_USART2_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 2) -#define AT32_UART_USART2_RX_DMAMUX_CHANNEL 1 -#define AT32_UART_USART2_TX_DMAMUX_CHANNEL 2 -#else -#define AT32_UART_USART2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 6) -#define AT32_UART_USART2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) -#endif - -#define AT32_HAS_USART3 FALSE -#define AT32_HAS_UART4 FALSE -#define AT32_HAS_UART5 FALSE -#define AT32_HAS_USART6 FALSE -#define AT32_HAS_UART7 FALSE -#define AT32_HAS_UART8 FALSE - -/* USB attributes.*/ -#define AT32_OTG_STEPPING 1 - -#define AT32_HAS_OTG1 TRUE -#define AT32_OTG1_ENDPOINTS 3 - -#define AT32_HAS_OTG2 FALSE - -/* WDT attributes.*/ -#define AT32_HAS_WDT TRUE -#define AT32_WDT_IS_WINDOWED FALSE - -/* CRC attributes.*/ -#define AT32_HAS_CRC TRUE - -/* STM32 compatibility define. */ -#if AT32_CRC_USE_CRC1 == TRUE -#define STM32_CRC_USE_CRC1 TRUE -#else -#define STM32_CRC_USE_CRC1 FALSE -#endif -/** @} */ -#endif /* defined(AT32F415K_MD) */ - -#if defined(AT32F415K_HD) || defined(__DOXYGEN__) -/** - * @name AT32F415K HD capabilities - * @{ - */ -/* ADC attributes.*/ -#define AT32_HAS_ADC1 TRUE - -#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_ADC_ADC1_DMA_STREAM AT32_DMA_STREAM_ID(1, 2) -#define AT32_ADC_ADC1_DMAMUX_CHANNEL 2 -#else -#define AT32_ADC_ADC1_DMA_STREAM AT32_DMA_STREAM_ID(1, 1) -#endif - -/* CAN attributes.*/ -#define AT32_HAS_CAN1 TRUE -#define AT32_CAN_MAX_FILTERS 14 - -/* DMA attributes.*/ -#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_ADVANCED_DMA TRUE -#define AT32_DMA_SUPPORTS_DMAMUX TRUE -#else -#define AT32_ADVANCED_DMA FALSE -#define AT32_DMA_SUPPORTS_DMAMUX FALSE -#endif - -#define AT32_DMA1_NUM_CHANNELS 7 -#define AT32_DMA2_NUM_CHANNELS 7 - -/* EXINT attributes.*/ -#define AT32_EXINT_NUM_LINES 23 -#define AT32_EXINT_INTEN_MASK 0x00000000U - -/* FLASH attributes.*/ -#define AT32_FLASH_NUMBER_OF_BANKS 1 +#elif defined(AT32F415KC) #define AT32_FLASH_SECTOR_SIZE 2048U +#endif #if !defined(AT32_FLASH_SECTORS_PER_BANK) || defined(__DOXYGEN__) #define AT32_FLASH_SECTORS_PER_BANK 128 /* Maximum, can be redefined.*/ @@ -334,6 +103,9 @@ #elif !defined(AT32_HAS_GPIOF) #define AT32_HAS_GPIOF FALSE #endif +#define AT32_HAS_GPIOE FALSE +#define AT32_HAS_GPIOG FALSE +#define AT32_HAS_GPIOH FALSE /* I2C attributes.*/ #define AT32_HAS_I2C1 TRUE @@ -502,20 +274,22 @@ /* STM32 compatibility define. */ #if AT32_CRC_USE_CRC1 == TRUE -#define STM32_CRC_USE_CRC1 TRUE +#define STM32_CRC_USE_CRC1 TRUE #else -#define STM32_CRC_USE_CRC1 FALSE +#define STM32_CRC_USE_CRC1 FALSE #endif /** @} */ -#endif /* defined(AT32F415K_HD) */ +#endif /* defined(AT32F415K) */ -#if defined(AT32F415C_MD) || defined(__DOXYGEN__) +#if defined(AT32F415C) || defined(__DOXYGEN__) /** - * @name AT32F415C MD capabilities + * @name AT32F415C capabilities * @{ */ /* ADC attributes.*/ #define AT32_HAS_ADC1 TRUE +#define AT32_ADC_SUPPORTS_PRESCALER FALSE +#define AT32_ADC_SUPPORTS_OVERSAMPLING FALSE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) #define AT32_ADC_ADC1_DMA_STREAM AT32_DMA_STREAM_ID(1, 2) @@ -546,7 +320,11 @@ /* FLASH attributes.*/ #define AT32_FLASH_NUMBER_OF_BANKS 1 +#if defined(AT32F415CB) || defined(__DOXYGEN__) #define AT32_FLASH_SECTOR_SIZE 1024U +#elif defined(AT32F415CC) +#define AT32_FLASH_SECTOR_SIZE 2048U +#endif #if !defined(AT32_FLASH_SECTORS_PER_BANK) || defined(__DOXYGEN__) #define AT32_FLASH_SECTORS_PER_BANK 128 /* Maximum, can be redefined.*/ @@ -559,6 +337,10 @@ #define AT32_HAS_GPIOD TRUE #define AT32_HAS_GPIOF TRUE +#define AT32_HAS_GPIOE FALSE +#define AT32_HAS_GPIOG FALSE +#define AT32_HAS_GPIOH FALSE + /* I2C attributes.*/ #define AT32_HAS_I2C1 TRUE @@ -737,20 +519,22 @@ /* STM32 compatibility define. */ #if AT32_CRC_USE_CRC1 == TRUE -#define STM32_CRC_USE_CRC1 TRUE +#define STM32_CRC_USE_CRC1 TRUE #else -#define STM32_CRC_USE_CRC1 FALSE +#define STM32_CRC_USE_CRC1 FALSE #endif /** @} */ -#endif /* defined(AT32F415C_MD) */ +#endif /* defined(AT32F415C) */ -#if defined(AT32F415C_HD) || defined(__DOXYGEN__) +#if defined(AT32F415R) || defined(__DOXYGEN__) /** - * @name AT32F415C HD capabilities + * @name AT32F415R capabilities * @{ */ /* ADC attributes.*/ #define AT32_HAS_ADC1 TRUE +#define AT32_ADC_SUPPORTS_PRESCALER FALSE +#define AT32_ADC_SUPPORTS_OVERSAMPLING FALSE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) #define AT32_ADC_ADC1_DMA_STREAM AT32_DMA_STREAM_ID(1, 2) @@ -781,7 +565,11 @@ /* FLASH attributes.*/ #define AT32_FLASH_NUMBER_OF_BANKS 1 +#if defined(AT32F415RB) || defined(__DOXYGEN__) +#define AT32_FLASH_SECTOR_SIZE 1024U +#elif defined(AT32F415RC) #define AT32_FLASH_SECTOR_SIZE 2048U +#endif #if !defined(AT32_FLASH_SECTORS_PER_BANK) || defined(__DOXYGEN__) #define AT32_FLASH_SECTORS_PER_BANK 128 /* Maximum, can be redefined.*/ @@ -794,494 +582,9 @@ #define AT32_HAS_GPIOD TRUE #define AT32_HAS_GPIOF TRUE -/* I2C attributes.*/ -#define AT32_HAS_I2C1 TRUE - -#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_I2C_I2C1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 3) -#define AT32_I2C_I2C1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) -#define AT32_I2C_I2C1_RX_DMAMUX_CHANNEL 3 -#define AT32_I2C_I2C1_TX_DMAMUX_CHANNEL 4 -#else -#define AT32_I2C_I2C1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) -#define AT32_I2C_I2C1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 6) -#endif - -#define AT32_HAS_I2C2 TRUE - -#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_I2C_I2C2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 3) -#define AT32_I2C_I2C2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) -#define AT32_I2C_I2C2_RX_DMAMUX_CHANNEL 3 -#define AT32_I2C_I2C2_TX_DMAMUX_CHANNEL 4 -#else -#define AT32_I2C_I2C2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) -#define AT32_I2C_I2C2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) -#endif - -#define AT32_HAS_I2C3 FALSE - -/* ERTC attributes.*/ -#define AT32_HAS_ERTC TRUE -#define AT32_ERTC_HAS_SUBSECONDS TRUE -#define AT32_ERTC_HAS_PERIODIC_WAKEUPS TRUE -#define AT32_ERTC_NUM_ALARMS 2 -#define AT32_ERTC_STORAGE_SIZE 80 - -/* QUADSPI attributes.*/ -#define AT32_HAS_QUADSPI1 FALSE - -/* SDIO attributes.*/ -#define AT32_HAS_SDIO TRUE - -#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_SDC_SDIO_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) -#define AT32_SDC_SDIO_DMAMUX_CHANNEL 5 -#else -#define AT32_SDC_SDIO_DMA_STREAM AT32_DMA_STREAM_ID(2, 4) -#endif - -/* SPI attributes.*/ -#define AT32_HAS_SPI1 TRUE -#define AT32_SPI1_SUPPORTS_I2S TRUE -#define AT32_SPI1_I2S_FULLDUPLEX FALSE - -#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_SPI_SPI1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 6) -#define AT32_SPI_SPI1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) -#define AT32_SPI_SPI1_RX_DMAMUX_CHANNEL 6 -#define AT32_SPI_SPI1_TX_DMAMUX_CHANNEL 7 -#else -#define AT32_SPI_SPI1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 2) -#define AT32_SPI_SPI1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 3) -#endif - -#define AT32_HAS_SPI2 TRUE -#define AT32_SPI2_SUPPORTS_I2S TRUE -#define AT32_SPI2_I2S_FULLDUPLEX FALSE - -#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_SPI_SPI2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 6) -#define AT32_SPI_SPI2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) -#define AT32_SPI_SPI2_RX_DMAMUX_CHANNEL 6 -#define AT32_SPI_SPI2_TX_DMAMUX_CHANNEL 7 -#else -#define AT32_SPI_SPI2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) -#define AT32_SPI_SPI2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) -#endif - -#define AT32_HAS_SPI3 FALSE - -/* TMR attributes.*/ -#define AT32_TMR_MAX_CHANNELS 4 - -#define AT32_HAS_TMR1 TRUE -#define AT32_TMR1_IS_32BITS FALSE -#define AT32_TMR1_CHANNELS 4 - -#define AT32_HAS_TMR2 TRUE -#define AT32_TMR2_IS_32BITS TRUE -#define AT32_TMR2_CHANNELS 4 - -#define AT32_HAS_TMR3 TRUE -#define AT32_TMR3_IS_32BITS FALSE -#define AT32_TMR3_CHANNELS 4 - -#define AT32_HAS_TMR4 TRUE -#define AT32_TMR4_IS_32BITS FALSE -#define AT32_TMR4_CHANNELS 4 - -#define AT32_HAS_TMR5 TRUE -#define AT32_TMR5_IS_32BITS TRUE -#define AT32_TMR5_CHANNELS 4 - -#define AT32_HAS_TMR9 TRUE -#define AT32_TMR9_IS_32BITS FALSE -#define AT32_TMR9_CHANNELS 2 - -#define AT32_HAS_TMR10 TRUE -#define AT32_TMR10_IS_32BITS FALSE -#define AT32_TMR10_CHANNELS 1 - -#define AT32_HAS_TMR11 TRUE -#define AT32_TMR11_IS_32BITS FALSE -#define AT32_TMR11_CHANNELS 1 - -#define AT32_HAS_TMR6 FALSE -#define AT32_HAS_TMR7 FALSE -#define AT32_HAS_TMR13 FALSE -#define AT32_HAS_TMR14 FALSE - -/* USART attributes.*/ -#define AT32_HAS_USART1 TRUE - -#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_UART_USART1_RX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) -#define AT32_UART_USART1_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 2) -#define AT32_UART_USART1_RX_DMAMUX_CHANNEL 1 -#define AT32_UART_USART1_TX_DMAMUX_CHANNEL 2 -#else -#define AT32_UART_USART1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) -#define AT32_UART_USART1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) -#endif - -#define AT32_HAS_USART2 TRUE - -#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_UART_USART2_RX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) -#define AT32_UART_USART2_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 2) -#define AT32_UART_USART2_RX_DMAMUX_CHANNEL 1 -#define AT32_UART_USART2_TX_DMAMUX_CHANNEL 2 -#else -#define AT32_UART_USART2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 6) -#define AT32_UART_USART2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) -#endif - -#define AT32_HAS_USART3 TRUE - -#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_UART_USART3_RX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) -#define AT32_UART_USART3_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 2) -#define AT32_UART_USART3_RX_DMAMUX_CHANNEL 1 -#define AT32_UART_USART3_TX_DMAMUX_CHANNEL 2 -#else -#define AT32_UART_USART3_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 3) -#define AT32_UART_USART3_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 2) -#endif - -#define AT32_HAS_UART4 FALSE -#define AT32_HAS_UART5 FALSE -#define AT32_HAS_USART6 FALSE -#define AT32_HAS_UART7 FALSE -#define AT32_HAS_UART8 FALSE - -/* USB attributes.*/ -#define AT32_OTG_STEPPING 1 - -#define AT32_HAS_OTG1 TRUE -#define AT32_OTG1_ENDPOINTS 3 - -#define AT32_HAS_OTG2 FALSE - -/* WDT attributes.*/ -#define AT32_HAS_WDT TRUE -#define AT32_WDT_IS_WINDOWED FALSE - -/* CRC attributes.*/ -#define AT32_HAS_CRC TRUE - -/* STM32 compatibility define. */ -#if AT32_CRC_USE_CRC1 == TRUE -#define STM32_CRC_USE_CRC1 TRUE -#else -#define STM32_CRC_USE_CRC1 FALSE -#endif -/** @} */ -#endif /* defined(AT32F415C_HD) */ - -#if defined(AT32F415R_MD) || defined(__DOXYGEN__) -/** - * @name AT32F415R MD capabilities - * @{ - */ -/* ADC attributes.*/ -#define AT32_HAS_ADC1 TRUE - -#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_ADC_ADC1_DMA_STREAM AT32_DMA_STREAM_ID(1, 2) -#define AT32_ADC_ADC1_DMAMUX_CHANNEL 2 -#else -#define AT32_ADC_ADC1_DMA_STREAM AT32_DMA_STREAM_ID(1, 1) -#endif - -/* CAN attributes.*/ -#define AT32_HAS_CAN1 TRUE -#define AT32_CAN_MAX_FILTERS 14 - -/* DMA attributes.*/ -#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_ADVANCED_DMA TRUE -#define AT32_DMA_SUPPORTS_DMAMUX TRUE -#else -#define AT32_ADVANCED_DMA FALSE -#define AT32_DMA_SUPPORTS_DMAMUX FALSE -#endif - -#define AT32_DMA1_NUM_CHANNELS 7 -#define AT32_DMA2_NUM_CHANNELS 7 - -/* EXINT attributes.*/ -#define AT32_EXINT_NUM_LINES 23 -#define AT32_EXINT_INTEN_MASK 0x00000000U - -/* FLASH attributes.*/ -#define AT32_FLASH_NUMBER_OF_BANKS 1 -#define AT32_FLASH_SECTOR_SIZE 1024U - -#if !defined(AT32_FLASH_SECTORS_PER_BANK) || defined(__DOXYGEN__) -#define AT32_FLASH_SECTORS_PER_BANK 128 /* Maximum, can be redefined.*/ -#endif - -/* GPIO attributes.*/ -#define AT32_HAS_GPIOA TRUE -#define AT32_HAS_GPIOB TRUE -#define AT32_HAS_GPIOC TRUE -#define AT32_HAS_GPIOD TRUE -#define AT32_HAS_GPIOF TRUE - -/* I2C attributes.*/ -#define AT32_HAS_I2C1 TRUE - -#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_I2C_I2C1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 3) -#define AT32_I2C_I2C1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) -#define AT32_I2C_I2C1_RX_DMAMUX_CHANNEL 3 -#define AT32_I2C_I2C1_TX_DMAMUX_CHANNEL 4 -#else -#define AT32_I2C_I2C1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) -#define AT32_I2C_I2C1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 6) -#endif - -#define AT32_HAS_I2C2 TRUE - -#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_I2C_I2C2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 3) -#define AT32_I2C_I2C2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) -#define AT32_I2C_I2C2_RX_DMAMUX_CHANNEL 3 -#define AT32_I2C_I2C2_TX_DMAMUX_CHANNEL 4 -#else -#define AT32_I2C_I2C2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) -#define AT32_I2C_I2C2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) -#endif - -#define AT32_HAS_I2C3 FALSE - -/* ERTC attributes.*/ -#define AT32_HAS_ERTC TRUE -#define AT32_ERTC_HAS_SUBSECONDS TRUE -#define AT32_ERTC_HAS_PERIODIC_WAKEUPS TRUE -#define AT32_ERTC_NUM_ALARMS 2 -#define AT32_ERTC_STORAGE_SIZE 80 - -/* QUADSPI attributes.*/ -#define AT32_HAS_QUADSPI1 FALSE - -/* SDIO attributes.*/ -#define AT32_HAS_SDIO TRUE - -#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_SDC_SDIO_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) -#define AT32_SDC_SDIO_DMAMUX_CHANNEL 5 -#else -#define AT32_SDC_SDIO_DMA_STREAM AT32_DMA_STREAM_ID(2, 4) -#endif - -/* SPI attributes.*/ -#define AT32_HAS_SPI1 TRUE -#define AT32_SPI1_SUPPORTS_I2S TRUE -#define AT32_SPI1_I2S_FULLDUPLEX FALSE - -#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_SPI_SPI1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 6) -#define AT32_SPI_SPI1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) -#define AT32_SPI_SPI1_RX_DMAMUX_CHANNEL 6 -#define AT32_SPI_SPI1_TX_DMAMUX_CHANNEL 7 -#else -#define AT32_SPI_SPI1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 2) -#define AT32_SPI_SPI1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 3) -#endif - -#define AT32_HAS_SPI2 TRUE -#define AT32_SPI2_SUPPORTS_I2S TRUE -#define AT32_SPI2_I2S_FULLDUPLEX FALSE - -#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_SPI_SPI2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 6) -#define AT32_SPI_SPI2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) -#define AT32_SPI_SPI2_RX_DMAMUX_CHANNEL 6 -#define AT32_SPI_SPI2_TX_DMAMUX_CHANNEL 7 -#else -#define AT32_SPI_SPI2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) -#define AT32_SPI_SPI2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) -#endif - -#define AT32_HAS_SPI3 FALSE - -/* TMR attributes.*/ -#define AT32_TMR_MAX_CHANNELS 4 - -#define AT32_HAS_TMR1 TRUE -#define AT32_TMR1_IS_32BITS FALSE -#define AT32_TMR1_CHANNELS 4 - -#define AT32_HAS_TMR2 TRUE -#define AT32_TMR2_IS_32BITS TRUE -#define AT32_TMR2_CHANNELS 4 - -#define AT32_HAS_TMR3 TRUE -#define AT32_TMR3_IS_32BITS FALSE -#define AT32_TMR3_CHANNELS 4 - -#define AT32_HAS_TMR4 TRUE -#define AT32_TMR4_IS_32BITS FALSE -#define AT32_TMR4_CHANNELS 4 - -#define AT32_HAS_TMR5 TRUE -#define AT32_TMR5_IS_32BITS TRUE -#define AT32_TMR5_CHANNELS 4 - -#define AT32_HAS_TMR9 TRUE -#define AT32_TMR9_IS_32BITS FALSE -#define AT32_TMR9_CHANNELS 2 - -#define AT32_HAS_TMR10 TRUE -#define AT32_TMR10_IS_32BITS FALSE -#define AT32_TMR10_CHANNELS 1 - -#define AT32_HAS_TMR11 TRUE -#define AT32_TMR11_IS_32BITS FALSE -#define AT32_TMR11_CHANNELS 1 - -#define AT32_HAS_TMR6 FALSE -#define AT32_HAS_TMR7 FALSE -#define AT32_HAS_TMR13 FALSE -#define AT32_HAS_TMR14 FALSE - -/* USART attributes.*/ -#define AT32_HAS_USART1 TRUE - -#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_UART_USART1_RX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) -#define AT32_UART_USART1_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 2) -#define AT32_UART_USART1_RX_DMAMUX_CHANNEL 1 -#define AT32_UART_USART1_TX_DMAMUX_CHANNEL 2 -#else -#define AT32_UART_USART1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) -#define AT32_UART_USART1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) -#endif - -#define AT32_HAS_USART2 TRUE - -#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_UART_USART2_RX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) -#define AT32_UART_USART2_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 2) -#define AT32_UART_USART2_RX_DMAMUX_CHANNEL 1 -#define AT32_UART_USART2_TX_DMAMUX_CHANNEL 2 -#else -#define AT32_UART_USART2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 6) -#define AT32_UART_USART2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) -#endif - -#define AT32_HAS_USART3 TRUE - -#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_UART_USART3_RX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) -#define AT32_UART_USART3_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 2) -#define AT32_UART_USART3_RX_DMAMUX_CHANNEL 1 -#define AT32_UART_USART3_TX_DMAMUX_CHANNEL 2 -#else -#define AT32_UART_USART3_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 3) -#define AT32_UART_USART3_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 2) -#endif - -#define AT32_HAS_UART4 TRUE - -#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_UART_UART4_RX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) -#define AT32_UART_UART4_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 2) -#define AT32_UART_UART4_RX_DMAMUX_CHANNEL 1 -#define AT32_UART_UART4_TX_DMAMUX_CHANNEL 2 -#else -#define AT32_UART_UART4_RX_DMA_STREAM AT32_DMA_STREAM_ID(2, 3) -#define AT32_UART_UART4_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 5) -#endif - -#define AT32_HAS_UART5 TRUE - -#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_UART_UART5_RX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) -#define AT32_UART_UART5_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 2) -#define AT32_UART_UART5_RX_DMAMUX_CHANNEL 1 -#define AT32_UART_UART5_TX_DMAMUX_CHANNEL 2 -#endif - -#define AT32_HAS_USART6 FALSE -#define AT32_HAS_UART7 FALSE -#define AT32_HAS_UART8 FALSE - -/* USB attributes.*/ -#define AT32_OTG_STEPPING 1 - -#define AT32_HAS_OTG1 TRUE -#define AT32_OTG1_ENDPOINTS 3 - -#define AT32_HAS_OTG2 FALSE - -/* WDT attributes.*/ -#define AT32_HAS_WDT TRUE -#define AT32_WDT_IS_WINDOWED FALSE - -/* CRC attributes.*/ -#define AT32_HAS_CRC TRUE - -/* STM32 compatibility define. */ -#if AT32_CRC_USE_CRC1 == TRUE -#define STM32_CRC_USE_CRC1 TRUE -#else -#define STM32_CRC_USE_CRC1 FALSE -#endif -/** @} */ -#endif /* defined(AT32F415R_MD) */ - -#if defined(AT32F415R_HD) || defined(__DOXYGEN__) -/** - * @name AT32F415R HD capabilities - * @{ - */ -/* ADC attributes.*/ -#define AT32_HAS_ADC1 TRUE - -#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_ADC_ADC1_DMA_STREAM AT32_DMA_STREAM_ID(1, 2) -#define AT32_ADC_ADC1_DMAMUX_CHANNEL 2 -#else -#define AT32_ADC_ADC1_DMA_STREAM AT32_DMA_STREAM_ID(1, 1) -#endif - -/* CAN attributes.*/ -#define AT32_HAS_CAN1 TRUE -#define AT32_CAN_MAX_FILTERS 14 - -/* DMA attributes.*/ -#if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_ADVANCED_DMA TRUE -#define AT32_DMA_SUPPORTS_DMAMUX TRUE -#else -#define AT32_ADVANCED_DMA FALSE -#define AT32_DMA_SUPPORTS_DMAMUX FALSE -#endif - -#define AT32_DMA1_NUM_CHANNELS 7 -#define AT32_DMA2_NUM_CHANNELS 7 - -/* EXINT attributes.*/ -#define AT32_EXINT_NUM_LINES 23 -#define AT32_EXINT_INTEN_MASK 0x00000000U - -/* FLASH attributes.*/ -#define AT32_FLASH_NUMBER_OF_BANKS 1 -#define AT32_FLASH_SECTOR_SIZE 2048U - -#if !defined(AT32_FLASH_SECTORS_PER_BANK) || defined(__DOXYGEN__) -#define AT32_FLASH_SECTORS_PER_BANK 128 /* Maximum, can be redefined.*/ -#endif - -/* GPIO attributes.*/ -#define AT32_HAS_GPIOA TRUE -#define AT32_HAS_GPIOB TRUE -#define AT32_HAS_GPIOC TRUE -#define AT32_HAS_GPIOD TRUE -#define AT32_HAS_GPIOF TRUE +#define AT32_HAS_GPIOE FALSE +#define AT32_HAS_GPIOG FALSE +#define AT32_HAS_GPIOH FALSE /* I2C attributes.*/ #define AT32_HAS_I2C1 TRUE @@ -1480,12 +783,12 @@ /* STM32 compatibility define. */ #if AT32_CRC_USE_CRC1 == TRUE -#define STM32_CRC_USE_CRC1 TRUE +#define STM32_CRC_USE_CRC1 TRUE #else -#define STM32_CRC_USE_CRC1 FALSE +#define STM32_CRC_USE_CRC1 FALSE #endif /** @} */ -#endif /* defined(AT32F415R_HD) */ +#endif /* defined(AT32F415R) */ #endif /* AT32_REGISTRY_H */ diff --git a/os/hal/ports/AT32/AT32F415/hal_efl_lld.c b/os/hal/ports/AT32/AT32F415/hal_efl_lld.c index 86471681dc..5871b166f0 100644 --- a/os/hal/ports/AT32/AT32F415/hal_efl_lld.c +++ b/os/hal/ports/AT32/AT32F415/hal_efl_lld.c @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/AT32F415/hal_efl_lld.h b/os/hal/ports/AT32/AT32F415/hal_efl_lld.h index 327d3cfb37..1f358ac507 100644 --- a/os/hal/ports/AT32/AT32F415/hal_efl_lld.h +++ b/os/hal/ports/AT32/AT32F415/hal_efl_lld.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/AT32F415/hal_lld.c b/os/hal/ports/AT32/AT32F415/hal_lld.c index fbeb6bb9dd..f6d87db80b 100644 --- a/os/hal/ports/AT32/AT32F415/hal_lld.c +++ b/os/hal/ports/AT32/AT32F415/hal_lld.c @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/AT32F415/hal_lld.h b/os/hal/ports/AT32/AT32F415/hal_lld.h index 6eb43f528e..05a7012a6f 100644 --- a/os/hal/ports/AT32/AT32F415/hal_lld.h +++ b/os/hal/ports/AT32/AT32F415/hal_lld.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -27,12 +27,15 @@ * - AT32_HEXT_BYPASS (optionally). * . * One of the following macros must also be defined: - * - AT32F415KB for K Value Medium Density devices. - * - AT32F415CB for C Value Medium Density devices. - * - AT32F415RB for R Value Medium Density devices. - * - AT32F415KC for K Value High Density devices. - * - AT32F415CC for C Value High Density devices. - * - AT32F415RC for R Value High Density devices. + * - AT32F415K8, AT32F415KB for 32 pin Value Line + Medium Density devices. + * - AT32F415KC for 32 pin Value Line High Density devices. + * - AT32F415C8, AT32F415CB for 48 pin Value Line + Medium Density devices. + * - AT32F415CC for 48 pin Value Line High Density devices. + * - AT32F415R8, AT32F415RB for 64 pin Value Line + Medium Density devices. + * - AT32F415RC for 64 pin Value Line High Density devices. * . * * @addtogroup HAL @@ -60,22 +63,22 @@ #if defined(__DOXYGEN__) #define PLATFORM_NAME "AT32F415" -#elif defined(AT32F415K_MD) +#elif defined(AT32F415KB) #define PLATFORM_NAME "AT32F415K Value Line Medium Density" -#elif defined(AT32F415K_HD) +#elif defined(AT32F415KC) #define PLATFORM_NAME "AT32F415K Value Line High Density" -#elif defined(AT32F415C_MD) +#elif defined(AT32F415CB) #define PLATFORM_NAME "AT32F415C Value Line Medium Density" -#elif defined(AT32F415C_HD) +#elif defined(AT32F415CC) #define PLATFORM_NAME "AT32F415C Value Line High Density" -#elif defined(AT32F415R_MD) +#elif defined(AT32F415RB) #define PLATFORM_NAME "AT32F415R Value Line Medium Density" -#elif defined(AT32F415R_HD) +#elif defined(AT32F415RC) #define PLATFORM_NAME "AT32F415R Value Line High Density" #else diff --git a/os/hal/ports/AT32/LLD/ADCv1/hal_adc_lld.c b/os/hal/ports/AT32/LLD/ADCv1/hal_adc_lld.c index 0f42b0a5ed..668c6b7cbc 100644 --- a/os/hal/ports/AT32/LLD/ADCv1/hal_adc_lld.c +++ b/os/hal/ports/AT32/LLD/ADCv1/hal_adc_lld.c @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -64,13 +64,41 @@ static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) { _adc_isr_error_code(adcp, ADC_ERR_DMAFAILURE); } else { - if ((flags & AT32_DMA_STS_FDTF) != 0) { - /* Transfer complete processing.*/ - _adc_isr_full_code(adcp); + /* It is possible that the conversion group has already be reset by the + ADC error handler, in this case this interrupt is spurious.*/ + if (adcp->grpp != NULL) { + + if ((flags & AT32_DMA_STS_FDTF) != 0) { + /* Transfer complete processing.*/ + _adc_isr_full_code(adcp); + } + else if ((flags & AT32_DMA_STS_HDTF) != 0) { + /* Half transfer processing.*/ + _adc_isr_half_code(adcp); + } } - else if ((flags & AT32_DMA_STS_HDTF) != 0) { - /* Half transfer processing.*/ - _adc_isr_half_code(adcp); + } +} + +/** + * @brief ADC IRQ service routine. + * + * @param[in] adcp pointer to the @p ADCDriver object + * @param[in] sts content of the STS register + */ +static void adc_lld_serve_interrupt(ADCDriver *adcp, uint32_t sts) { + + /* It could be a spurious interrupt caused by overflows after DMA disabling, + just ignore it in this case.*/ + if (adcp->grpp != NULL) { + adcerror_t emask = 0U; + + if (sts & ADC_STS_VMOR) { + /* Analog voltage monitoring error.*/ + emask |= ADC_ERR_VM; + } + if (emask != 0U) { + _adc_isr_error_code(adcp, emask); } } } @@ -79,6 +107,30 @@ static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) { /* Driver interrupt handlers. */ /*===========================================================================*/ +#if AT32_ADC_USE_ADC1 || defined(__DOXYGEN__) +/** + * @brief ADC1 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_ADC1_HANDLER) { + uint32_t sts; + + OSAL_IRQ_PROLOGUE(); + +#if AT32_ADC_USE_ADC1 + sts = ADC1->STS; + ADC1->STS = 0; +#if defined(AT32_ADC_ADC1_IRQ_HOOK) + AT32_ADC_ADC1_IRQ_HOOK +#endif + adc_lld_serve_interrupt(&ADCD1, sts); +#endif /* AT32_ADC_USE_ADC1 */ + + OSAL_IRQ_EPILOGUE(); +} +#endif + /*===========================================================================*/ /* Driver exported functions. */ /*===========================================================================*/ @@ -93,9 +145,10 @@ void adc_lld_init(void) { #if AT32_ADC_USE_ADC1 /* Driver initialization.*/ adcObjectInit(&ADCD1); - ADCD1.adc = ADC1; + ADCD1.adc = ADC1; ADCD1.dmastp = NULL; ADCD1.dmamode = AT32_DMA_CCTRL_CHPL(AT32_ADC_ADC1_DMA_PRIORITY) | + AT32_DMA_CCTRL_DTD_P2M | AT32_DMA_CCTRL_MWIDTH_HWORD | AT32_DMA_CCTRL_PWIDTH_HWORD | AT32_DMA_CCTRL_MINCM | AT32_DMA_CCTRL_FDTIEN | AT32_DMA_CCTRL_DTERRIEN; @@ -119,6 +172,10 @@ void adc_lld_init(void) { ADC1->CTRL2 = 0; crmDisableADC1(); #endif + + /* The shared vector is initialized on driver initialization and never + disabled because sharing.*/ + nvicEnableVector(AT32_ADC1_NUMBER, AT32_ADC_ADC1_IRQ_PRIORITY); } /** @@ -135,24 +192,30 @@ void adc_lld_start(ADCDriver *adcp) { #if AT32_ADC_USE_ADC1 if (&ADCD1 == adcp) { adcp->dmastp = dmaStreamAllocI(AT32_ADC_ADC1_DMA_STREAM, - AT32_ADC_ADC1_IRQ_PRIORITY, + AT32_ADC_ADC1_DMA_IRQ_PRIORITY, (at32_dmasts_t)adc_lld_serve_rx_interrupt, (void *)adcp); osalDbgAssert(adcp->dmastp != NULL, "unable to allocate stream"); - + dmaStreamSetPeripheral(adcp->dmastp, &ADC1->ODT); #if AT32_DMA_SUPPORTS_DMAMUX dmaSetRequestSource(adcp->dmastp, AT32_ADC_ADC1_DMAMUX_CHANNEL, AT32_DMAMUX_ADC1); #endif - - dmaStreamSetPeripheral(adcp->dmastp, &ADC1->ODT); +#if defined(crmResetADC1) + crmResetADC1(); +#endif crmEnableADC1(true); } -#endif +#endif /* AT32_ADC_USE_ADC1 */ - /* ADC setup, the calibration procedure has already been performed - during initialization.*/ + /* This is a common register but apparently it requires that at least one + of the ADCs is clocked in order to allow writing, see bug 3575297.*/ + adcp->adc->CTRL2 = ADC_CTRL2_ITSRVEN; + + /* ADC initial setup, starting the analog part here in order to reduce + the latency when starting a conversion.*/ adcp->adc->CTRL1 = 0; adcp->adc->CTRL2 = 0; + adcp->adc->CTRL2 = ADC_CTRL2_ADCEN; } } @@ -167,16 +230,16 @@ void adc_lld_stop(ADCDriver *adcp) { /* If in ready state then disables the ADC clock.*/ if (adcp->state == ADC_READY) { -#if AT32_ADC_USE_ADC1 - if (&ADCD1 == adcp) { - ADC1->CTRL1 = 0; - ADC1->CTRL2 = 0; - dmaStreamFreeI(adcp->dmastp); - adcp->dmastp = NULL; + dmaStreamFreeI(adcp->dmastp); + adcp->dmastp = NULL; + adcp->adc->CTRL1 = 0; + adcp->adc->CTRL2 = 0; + +#if AT32_ADC_USE_ADC1 + if (&ADCD1 == adcp) crmDisableADC1(); - } #endif } } @@ -189,7 +252,8 @@ void adc_lld_stop(ADCDriver *adcp) { * @notapi */ void adc_lld_start_conversion(ADCDriver *adcp) { - uint32_t mode, ctrl2; + uint32_t mode; + uint32_t ctrl2; const ADCConversionGroup *grpp = adcp->grpp; /* DMA setup.*/ @@ -209,16 +273,24 @@ void adc_lld_start_conversion(ADCDriver *adcp) { dmaStreamEnable(adcp->dmastp); /* ADC setup.*/ + adcp->adc->STS = 0; + adcp->adc->SPT1 = grpp->spt1; + adcp->adc->SPT2 = grpp->spt2; + adcp->adc->VMHB = grpp->vmhb; + adcp->adc->VMLB = grpp->vmlb; + adcp->adc->OSQ1 = grpp->osq1 | ADC_OSQ1_NUM_CH(grpp->num_channels); + adcp->adc->OSQ2 = grpp->osq2; + adcp->adc->OSQ3 = grpp->osq3; + + /* ADC configuration and start.*/ adcp->adc->CTRL1 = grpp->ctrl1 | ADC_CTRL1_SQEN; + + /* Enforcing the mandatory bits in CTRL2.*/ ctrl2 = grpp->ctrl2 | ADC_CTRL2_OCDMAEN | ADC_CTRL2_ADCEN; + if ((ctrl2 & (ADC_CTRL2_OCTEN | ADC_CTRL2_PCTEN)) == 0) ctrl2 |= ADC_CTRL2_RPEN; adcp->adc->CTRL2 = grpp->ctrl2 | ctrl2; - adcp->adc->SPT1 = grpp->spt1; - adcp->adc->SPT2 = grpp->spt2; - adcp->adc->OSQ1 = grpp->osq1; - adcp->adc->OSQ2 = grpp->osq2; - adcp->adc->OSQ3 = grpp->osq3; /* ADC start by writing ADC_CTRL2_ADCEN a second time.*/ adcp->adc->CTRL2 = ctrl2; @@ -234,7 +306,33 @@ void adc_lld_start_conversion(ADCDriver *adcp) { void adc_lld_stop_conversion(ADCDriver *adcp) { dmaStreamDisable(adcp->dmastp); - adcp->adc->CTRL2 = 0; + adcp->adc->CTRL1 = 0U; + if ((adcp->adc->CTRL2 & ADC_CTRL2_RPEN) != 0U) { + adcp->adc->CTRL2 = 0U; + } + adcp->adc->CTRL2 = ADC_CTRL2_ADCEN; +} + +/** + * @brief Enables the ITSRVEN bit. + * @details The ITSRVEN bit is required in order to sample the internal + * temperature sensor and internal reference voltage. + * @note This is an AT32-only functionality. + */ +void adcAT32EnableITSRVEN(void) { + + ADC1->CTRL2 |= ADC_CTRL2_ITSRVEN; +} + +/** + * @brief Disables the ITSRVEN bit. + * @details The ITSRVEN bit is required in order to sample the internal + * temperature sensor and internal reference voltage. + * @note This is an AT32-only functionality. + */ +void adcAT32DisableITSRVEN(void) { + + ADC1->CTRL2 &= ~ADC_CTRL2_ITSRVEN; } #endif /* HAL_USE_ADC */ diff --git a/os/hal/ports/AT32/LLD/ADCv1/hal_adc_lld.h b/os/hal/ports/AT32/LLD/ADCv1/hal_adc_lld.h index a54d9b8988..db406bf938 100644 --- a/os/hal/ports/AT32/LLD/ADCv1/hal_adc_lld.h +++ b/os/hal/ports/AT32/LLD/ADCv1/hal_adc_lld.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -33,50 +33,61 @@ /* Driver constants. */ /*===========================================================================*/ +/** + * @name Possible ADC errors mask bits. + * @{ + */ +#define ADC_ERR_DMAFAILURE 1U /**< DMA operations failure. */ +#define ADC_ERR_VM 4U /**< Voltage monitoring triggered. */ +/** @} */ + /** * @name Triggers selection * @{ */ -#define ADC_CTRL2_OCTESEL_SRC(n) ((n) << 17) /**< @brief Trigger source. */ -#define ADC_CTRL2_OCTESEL_OCSWTRG (7 << 17) /**< @brief Software trigger. */ +#define ADC_CTRL2_OCTESEL_MASK ((7U << 17U) | (1U << 25)) +#define ADC_CTRL2_OCTESEL_SRC(n) (((n) << 17U) | \ + (((n) >> 3) << 25)) /** @} */ /** * @name Available analog channels * @{ */ -#define ADC_CHANNEL_IN0 0 /**< @brief External analog input 0. */ -#define ADC_CHANNEL_IN1 1 /**< @brief External analog input 1. */ -#define ADC_CHANNEL_IN2 2 /**< @brief External analog input 2. */ -#define ADC_CHANNEL_IN3 3 /**< @brief External analog input 3. */ -#define ADC_CHANNEL_IN4 4 /**< @brief External analog input 4. */ -#define ADC_CHANNEL_IN5 5 /**< @brief External analog input 5. */ -#define ADC_CHANNEL_IN6 6 /**< @brief External analog input 6. */ -#define ADC_CHANNEL_IN7 7 /**< @brief External analog input 7. */ -#define ADC_CHANNEL_IN8 8 /**< @brief External analog input 8. */ -#define ADC_CHANNEL_IN9 9 /**< @brief External analog input 9. */ -#define ADC_CHANNEL_IN10 10 /**< @brief External analog input 10. */ -#define ADC_CHANNEL_IN11 11 /**< @brief External analog input 11. */ -#define ADC_CHANNEL_IN12 12 /**< @brief External analog input 12. */ -#define ADC_CHANNEL_IN13 13 /**< @brief External analog input 13. */ -#define ADC_CHANNEL_IN14 14 /**< @brief External analog input 14. */ -#define ADC_CHANNEL_IN15 15 /**< @brief External analog input 15. */ -#define ADC_CHANNEL_SENSOR 16 /**< @brief Internal temperature sensor.*/ -#define ADC_CHANNEL_VREF 17 /**< @brief Internal reference. */ +#define ADC_CHANNEL_IN0 0 /**< @brief External analog input 0. */ +#define ADC_CHANNEL_IN1 1 /**< @brief External analog input 1. */ +#define ADC_CHANNEL_IN2 2 /**< @brief External analog input 2. */ +#define ADC_CHANNEL_IN3 3 /**< @brief External analog input 3. */ +#define ADC_CHANNEL_IN4 4 /**< @brief External analog input 4. */ +#define ADC_CHANNEL_IN5 5 /**< @brief External analog input 5. */ +#define ADC_CHANNEL_IN6 6 /**< @brief External analog input 6. */ +#define ADC_CHANNEL_IN7 7 /**< @brief External analog input 7. */ +#define ADC_CHANNEL_IN8 8 /**< @brief External analog input 8. */ +#define ADC_CHANNEL_IN9 9 /**< @brief External analog input 9. */ +#define ADC_CHANNEL_IN10 10 /**< @brief External analog input 10. */ +#define ADC_CHANNEL_IN11 11 /**< @brief External analog input 11. */ +#define ADC_CHANNEL_IN12 12 /**< @brief External analog input 12. */ +#define ADC_CHANNEL_IN13 13 /**< @brief External analog input 13. */ +#define ADC_CHANNEL_IN14 14 /**< @brief External analog input 14. */ +#define ADC_CHANNEL_IN15 15 /**< @brief External analog input 15. */ +#define ADC_CHANNEL_SENSOR 16 /**< @brief Internal temperature sensor. + @note Available on ADC1 only. */ +#define ADC_CHANNEL_VREF 17 /**< @brief Internal reference. + @note Available on ADC1 only. */ /** @} */ /** * @name Sampling rates * @{ */ -#define ADC_SAMPLE_1P5 0 /**< @brief 1.5 cycles sampling time. */ -#define ADC_SAMPLE_7P5 1 /**< @brief 7.5 cycles sampling time. */ -#define ADC_SAMPLE_13P5 2 /**< @brief 13.5 cycles sampling time. */ -#define ADC_SAMPLE_28P5 3 /**< @brief 28.5 cycles sampling time. */ -#define ADC_SAMPLE_41P5 4 /**< @brief 41.5 cycles sampling time. */ -#define ADC_SAMPLE_55P5 5 /**< @brief 55.5 cycles sampling time. */ -#define ADC_SAMPLE_71P5 6 /**< @brief 71.5 cycles sampling time. */ -#define ADC_SAMPLE_239P5 7 /**< @brief 239.5 cycles sampling time. */ +#define ADC_SAMPLE_1P5 0 /**< @brief 1.5 cycles sampling time. */ +#define ADC_SAMPLE_7P5 1 /**< @brief 7.5 cycles sampling time. */ +#define ADC_SAMPLE_13P5 2 /**< @brief 13.5 cycles sampling time. */ +#define ADC_SAMPLE_28P5 3 /**< @brief 28.5 cycles sampling time. */ +#define ADC_SAMPLE_41P5 4 /**< @brief 41.5 cycles sampling time. */ +#define ADC_SAMPLE_55P5 5 /**< @brief 55.5 cycles sampling time. */ +#define ADC_SAMPLE_71P5 6 /**< @brief 71.5 cycles sampling time. */ +#define ADC_SAMPLE_239P5 7 /**< @brief 239.5 cycles sampling time. */ /** @} */ /*===========================================================================*/ @@ -96,6 +107,13 @@ #define AT32_ADC_USE_ADC1 FALSE #endif +/** + * @brief DMA stream used for ADC1 operations. + */ +#if !defined(AT32_ADC_ADC1_DMA_STREAM) || defined(__DOXYGEN__) +#define AT32_ADC_ADC1_DMA_STREAM AT32_DMA_STREAM_ID(1, 1) +#endif + /** * @brief ADC1 DMA priority (0..3|lowest..highest). */ @@ -109,6 +127,14 @@ #if !defined(AT32_ADC_ADC1_IRQ_PRIORITY) || defined(__DOXYGEN__) #define AT32_ADC_ADC1_IRQ_PRIORITY 5 #endif + +/** + * @brief ADC1 DMA interrupt priority level setting. + */ +#if !defined(AT32_ADC_ADC1_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define AT32_ADC_ADC1_DMA_IRQ_PRIORITY 5 +#endif + /** @} */ /*===========================================================================*/ @@ -142,13 +168,9 @@ typedef uint16_t adcsample_t; typedef uint16_t adc_channels_num_t; /** - * @brief Possible ADC failure causes. - * @note Error codes are architecture dependent and should not relied - * upon. + * @brief Type of an ADC error mask. */ -typedef enum { - ADC_ERR_DMAFAILURE = 0 /**< DMA operations failure. */ -} adcerror_t; +typedef uint32_t adcerror_t; /*===========================================================================*/ /* Driver macros. */ @@ -157,50 +179,58 @@ typedef enum { /** * @brief Low level fields of the ADC driver structure. */ -#define adc_lld_driver_fields \ - /* Pointer to the ADCx registers block.*/ \ - ADC_TypeDef *adc; \ - /* Pointer to associated DMA channel.*/ \ - const at32_dma_stream_t *dmastp; \ - /* DMA mode bit mask.*/ \ +#define adc_lld_driver_fields \ + /* Pointer to the ADCx registers block.*/ \ + ADC_TypeDef *adc; \ + /* Pointer to associated DMA channel.*/ \ + const at32_dma_stream_t *dmastp; \ + /* DMA mode bit mask.*/ \ uint32_t dmamode /** * @brief Low level fields of the ADC configuration structure. */ -#define adc_lld_config_fields \ - /* Dummy configuration, it is not needed.*/ \ +#define adc_lld_config_fields \ + /* Dummy configuration, it is not needed.*/ \ uint32_t dummy /** * @brief Low level fields of the ADC configuration structure. */ -#define adc_lld_configuration_group_fields \ - /* ADC CTRL1 register initialization data. \ - NOTE: All the required bits must be defined into this field except \ - @p ADC_CTRL1_SQEN that is enforced inside the driver.*/ \ - uint32_t ctrl1; \ - /* ADC CTRL2 register initialization data. \ - NOTE: All the required bits must be defined into this field except \ - @p ADC_CTRL2_OCDMAEN, @p ADC_CTRL2_RPEN and @p ADC_CTRL2_ADCEN \ - that are enforced inside the driver.*/ \ - uint32_t ctrl2; \ - /* ADC SPT1 register initialization data. \ - NOTE: In this field must be specified the sample times for channels \ - 10...17.*/ \ - uint32_t spt1; \ - /* ADC SPT2 register initialization data. \ - NOTE: In this field must be specified the sample times for channels \ - 0...9.*/ \ - uint32_t spt2; \ - /* ADC OSQ1 register initialization data. \ - NOTE: Conversion group sequence 13...16 + sequence length.*/ \ - uint32_t osq1; \ - /* ADC OSQ2 register initialization data. \ - NOTE: Conversion group sequence 7...12.*/ \ - uint32_t osq2; \ - /* ADC OSQ3 register initialization data. \ - NOTE: Conversion group sequence 1...6.*/ \ +#define adc_lld_configuration_group_fields \ + /* ADC CTRL1 register initialization data. \ + NOTE: All the required bits must be defined into this field except \ + @p ADC_CTRL1_SQEN that is enforced inside the driver.*/ \ + uint32_t ctrl1; \ + /* ADC CTRL2 register initialization data. \ + NOTE: All the required bits must be defined into this field except \ + @p ADC_CTRL2_OCDMAEN, @p ADC_CTRL2_RPEN and @p ADC_CTRL2_ADCEN \ + that are enforced inside the driver.*/ \ + uint32_t ctrl2; \ + /* ADC SPT1 register initialization data. \ + NOTE: In this field must be specified the sample times for channels \ + 10...17.*/ \ + uint32_t spt1; \ + /* ADC SPT2 register initialization data. \ + NOTE: In this field must be specified the sample times for channels \ + 0...9.*/ \ + uint32_t spt2; \ + /* ADC voltage monitoring high boundary register. \ + NOTE: This field defines the high boundary of the analog \ + voltage monitoring.*/ \ + uint16_t vmhb; \ + /* ADC voltage monitoring low boundary register. \ + NOTE: This field defines the low boundary of the analog \ + voltage monitoring.*/ \ + uint16_t vmlb; \ + /* ADC OSQ1 register initialization data. \ + NOTE: Conversion group sequence 13...16 + sequence length.*/ \ + uint32_t osq1; \ + /* ADC OSQ2 register initialization data. \ + NOTE: Conversion group sequence 7...12.*/ \ + uint32_t osq2; \ + /* ADC OSQ3 register initialization data. \ + NOTE: Conversion group sequence 1...6.*/ \ uint32_t osq3 /** @@ -212,51 +242,65 @@ typedef enum { */ #define ADC_OSQ1_NUM_CH(n) (((n) - 1) << 20) -#define ADC_OSQ3_OSN1_N(n) ((n) << 0) /**< @brief 1st channel in seq. */ -#define ADC_OSQ3_OSN2_N(n) ((n) << 5) /**< @brief 2nd channel in seq. */ -#define ADC_OSQ3_OSN3_N(n) ((n) << 10) /**< @brief 3rd channel in seq. */ -#define ADC_OSQ3_OSN4_N(n) ((n) << 15) /**< @brief 4th channel in seq. */ -#define ADC_OSQ3_OSN5_N(n) ((n) << 20) /**< @brief 5th channel in seq. */ -#define ADC_OSQ3_OSN6_N(n) ((n) << 25) /**< @brief 6th channel in seq. */ - -#define ADC_OSQ2_OSN7_N(n) ((n) << 0) /**< @brief 7th channel in seq. */ -#define ADC_OSQ2_OSN8_N(n) ((n) << 5) /**< @brief 8th channel in seq. */ -#define ADC_OSQ2_OSN9_N(n) ((n) << 10) /**< @brief 9th channel in seq. */ -#define ADC_OSQ2_OSN10_N(n) ((n) << 15) /**< @brief 10th channel in seq. */ -#define ADC_OSQ2_OSN11_N(n) ((n) << 20) /**< @brief 11th channel in seq. */ -#define ADC_OSQ2_OSN12_N(n) ((n) << 25) /**< @brief 12th channel in seq. */ - -#define ADC_OSQ1_OSN13_N(n) ((n) << 0) /**< @brief 13th channel in seq. */ -#define ADC_OSQ1_OSN14_N(n) ((n) << 5) /**< @brief 14th channel in seq. */ -#define ADC_OSQ1_OSN15_N(n) ((n) << 10) /**< @brief 15th channel in seq. */ -#define ADC_OSQ1_OSN16_N(n) ((n) << 15) /**< @brief 16th channel in seq. */ +#define ADC_OSQ3_OSN1_N(n) ((n) << 0) /**< @brief 1st channel in seq. */ +#define ADC_OSQ3_OSN2_N(n) ((n) << 5) /**< @brief 2nd channel in seq. */ +#define ADC_OSQ3_OSN3_N(n) ((n) << 10) /**< @brief 3rd channel in seq. */ +#define ADC_OSQ3_OSN4_N(n) ((n) << 15) /**< @brief 4th channel in seq. */ +#define ADC_OSQ3_OSN5_N(n) ((n) << 20) /**< @brief 5th channel in seq. */ +#define ADC_OSQ3_OSN6_N(n) ((n) << 25) /**< @brief 6th channel in seq. */ + +#define ADC_OSQ2_OSN7_N(n) ((n) << 0) /**< @brief 7th channel in seq. */ +#define ADC_OSQ2_OSN8_N(n) ((n) << 5) /**< @brief 8th channel in seq. */ +#define ADC_OSQ2_OSN9_N(n) ((n) << 10) /**< @brief 9th channel in seq. */ +#define ADC_OSQ2_OSN10_N(n) ((n) << 15) /**< @brief 10th channel in seq.*/ +#define ADC_OSQ2_OSN11_N(n) ((n) << 20) /**< @brief 11th channel in seq.*/ +#define ADC_OSQ2_OSN12_N(n) ((n) << 25) /**< @brief 12th channel in seq.*/ + +#define ADC_OSQ1_OSN13_N(n) ((n) << 0) /**< @brief 13th channel in seq.*/ +#define ADC_OSQ1_OSN14_N(n) ((n) << 5) /**< @brief 14th channel in seq.*/ +#define ADC_OSQ1_OSN15_N(n) ((n) << 10) /**< @brief 15th channel in seq.*/ +#define ADC_OSQ1_OSN16_N(n) ((n) << 15) /**< @brief 16th channel in seq.*/ /** @} */ /** * @name Sampling rate settings helper macros * @{ */ -#define ADC_SPT2_CSPT_AN0(n) ((n) << 0) /**< @brief AN0 sampling time. */ -#define ADC_SPT2_CSPT_AN1(n) ((n) << 3) /**< @brief AN1 sampling time. */ -#define ADC_SPT2_CSPT_AN2(n) ((n) << 6) /**< @brief AN2 sampling time. */ -#define ADC_SPT2_CSPT_AN3(n) ((n) << 9) /**< @brief AN3 sampling time. */ -#define ADC_SPT2_CSPT_AN4(n) ((n) << 12) /**< @brief AN4 sampling time. */ -#define ADC_SPT2_CSPT_AN5(n) ((n) << 15) /**< @brief AN5 sampling time. */ -#define ADC_SPT2_CSPT_AN6(n) ((n) << 18) /**< @brief AN6 sampling time. */ -#define ADC_SPT2_CSPT_AN7(n) ((n) << 21) /**< @brief AN7 sampling time. */ -#define ADC_SPT2_CSPT_AN8(n) ((n) << 24) /**< @brief AN8 sampling time. */ -#define ADC_SPT2_CSPT_AN9(n) ((n) << 27) /**< @brief AN9 sampling time. */ - -#define ADC_SPT1_CSPT_AN10(n) ((n) << 0) /**< @brief AN10 sampling time. */ -#define ADC_SPT1_CSPT_AN11(n) ((n) << 3) /**< @brief AN11 sampling time. */ -#define ADC_SPT1_CSPT_AN12(n) ((n) << 6) /**< @brief AN12 sampling time. */ -#define ADC_SPT1_CSPT_AN13(n) ((n) << 9) /**< @brief AN13 sampling time. */ -#define ADC_SPT1_CSPT_AN14(n) ((n) << 12) /**< @brief AN14 sampling time. */ -#define ADC_SPT1_CSPT_AN15(n) ((n) << 15) /**< @brief AN15 sampling time. */ +#define ADC_SPT2_CSPT_AN0(n) ((n) << 0) /**< @brief AN0 sampling time. */ +#define ADC_SPT2_CSPT_AN1(n) ((n) << 3) /**< @brief AN1 sampling time. */ +#define ADC_SPT2_CSPT_AN2(n) ((n) << 6) /**< @brief AN2 sampling time. */ +#define ADC_SPT2_CSPT_AN3(n) ((n) << 9) /**< @brief AN3 sampling time. */ +#define ADC_SPT2_CSPT_AN4(n) ((n) << 12) /**< @brief AN4 sampling time. */ +#define ADC_SPT2_CSPT_AN5(n) ((n) << 15) /**< @brief AN5 sampling time. */ +#define ADC_SPT2_CSPT_AN6(n) ((n) << 18) /**< @brief AN6 sampling time. */ +#define ADC_SPT2_CSPT_AN7(n) ((n) << 21) /**< @brief AN7 sampling time. */ +#define ADC_SPT2_CSPT_AN8(n) ((n) << 24) /**< @brief AN8 sampling time. */ +#define ADC_SPT2_CSPT_AN9(n) ((n) << 27) /**< @brief AN9 sampling time. */ + +#define ADC_SPT1_CSPT_AN10(n) ((n) << 0) /**< @brief AN10 sampling time. */ +#define ADC_SPT1_CSPT_AN11(n) ((n) << 3) /**< @brief AN11 sampling time. */ +#define ADC_SPT1_CSPT_AN12(n) ((n) << 6) /**< @brief AN12 sampling time. */ +#define ADC_SPT1_CSPT_AN13(n) ((n) << 9) /**< @brief AN13 sampling time. */ +#define ADC_SPT1_CSPT_AN14(n) ((n) << 12) /**< @brief AN14 sampling time. */ +#define ADC_SPT1_CSPT_AN15(n) ((n) << 15) /**< @brief AN15 sampling time. */ #define ADC_SPT1_CSPT_SENSOR(n) ((n) << 18) /**< @brief Temperature Sensor - sampling time. */ + sampling time. */ #define ADC_SPT1_CSPT_VREF(n) ((n) << 21) /**< @brief Voltage Reference - sampling time. */ + sampling time. */ +/** @} */ + +/** + * @name Threshold settings helper macros + * @{ + */ +/** + * @brief High voltage monitoring boundary. + */ +#define ADC_VMHB(n) ((n > ADC_VMHB_HB) ? ADC_VMHB_HB : n) +/** + * @brief Low voltage monitoring boundary. + */ +#define ADC_VMLB(n) ((n > ADC_VMLB_LB) ? ADC_VMLB_LB : n) /** @} */ /*===========================================================================*/ @@ -275,6 +319,8 @@ extern "C" { void adc_lld_stop(ADCDriver *adcp); void adc_lld_start_conversion(ADCDriver *adcp); void adc_lld_stop_conversion(ADCDriver *adcp); + void adcAT32EnableITSRVEN(void); + void adcAT32DisableITSRVEN(void); #ifdef __cplusplus } #endif diff --git a/os/hal/ports/AT32/LLD/ADCv2/hal_adc_lld.c b/os/hal/ports/AT32/LLD/ADCv2/hal_adc_lld.c index 7f5568e9f6..a2cd5afb07 100644 --- a/os/hal/ports/AT32/LLD/ADCv2/hal_adc_lld.c +++ b/os/hal/ports/AT32/LLD/ADCv2/hal_adc_lld.c @@ -1,6 +1,8 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 Maxjta + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + ChibiOS - Copyright (C) 2024..2025 Maxjta Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -31,15 +33,6 @@ /* Driver local definitions. */ /*===========================================================================*/ -#define ADC1_DMA_CHANNEL \ - AT32_DMA_GETCHANNEL(AT32_ADC_ADC1_DMA_STREAM, AT32_ADC1_DMA_CHN) - -#define ADC2_DMA_CHANNEL \ - AT32_DMA_GETCHANNEL(AT32_ADC_ADC2_DMA_STREAM, AT32_ADC2_DMA_CHN) - -#define ADC3_DMA_CHANNEL \ - AT32_DMA_GETCHANNEL(AT32_ADC_ADC3_DMA_STREAM, AT32_ADC3_DMA_CHN) - /*===========================================================================*/ /* Driver exported variables. */ /*===========================================================================*/ @@ -49,16 +42,6 @@ ADCDriver ADCD1; #endif -/** @brief ADC2 driver identifier.*/ -#if AT32_ADC_USE_ADC2 || defined(__DOXYGEN__) -ADCDriver ADCD2; -#endif - -/** @brief ADC3 driver identifier.*/ -#if AT32_ADC_USE_ADC3 || defined(__DOXYGEN__) -ADCDriver ADCD3; -#endif - /*===========================================================================*/ /* Driver local variables and types. */ /*===========================================================================*/ @@ -71,12 +54,12 @@ ADCDriver ADCD3; * @brief ADC DMA service routine. * * @param[in] adcp pointer to the @p ADCDriver object - * @param[in] flags pre-shifted content of the ISR register + * @param[in] flags pre-shifted content of the STS register */ static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) { /* DMA errors handling.*/ - if ((flags & (AT32_DMA_STS_DTERRF | AT32_DMA_STS_DMERRF)) != 0) { + if ((flags & AT32_DMA_STS_DTERRF) != 0) { /* DMA, this could help only if the DMA tries to access an unmapped address space or violates alignment rules.*/ _adc_isr_error_code(adcp, ADC_ERR_DMAFAILURE); @@ -111,15 +94,8 @@ static void adc_lld_serve_interrupt(ADCDriver *adcp, uint32_t sts) { if (adcp->grpp != NULL) { adcerror_t emask = 0U; - /* Note, an overflow may occur after the conversion ended before the driver - is able to stop the ADC, this is why the state is checked too.*/ - if ((sts & ADC_STS_OCCS) && (adcp->state == ADC_ACTIVE)) { - /* ADC overflow condition, this could happen only if the DMA is unable - to read data fast enough.*/ - emask |= ADC_ERR_OVERFLOW; - } if (sts & ADC_STS_VMOR) { - /* Analog watchdog 1 error.*/ + /* Analog voltage monitoring error.*/ emask |= ADC_ERR_VM; } if (emask != 0U) { @@ -132,8 +108,7 @@ static void adc_lld_serve_interrupt(ADCDriver *adcp, uint32_t sts) { /* Driver interrupt handlers. */ /*===========================================================================*/ -#if AT32_ADC_USE_ADC1 || AT32_ADC_USE_ADC2 || AT32_ADC_USE_ADC3 || \ - defined(__DOXYGEN__) +#if AT32_ADC_USE_ADC1 || defined(__DOXYGEN__) /** * @brief ADC interrupt handler. * @@ -153,24 +128,6 @@ OSAL_IRQ_HANDLER(AT32_ADC_HANDLER) { adc_lld_serve_interrupt(&ADCD1, sts); #endif /* AT32_ADC_USE_ADC1 */ -#if AT32_ADC_USE_ADC2 - sts = ADC2->STS; - ADC2->STS = 0; -#if defined(AT32_ADC_ADC2_IRQ_HOOK) - AT32_ADC_ADC2_IRQ_HOOK -#endif - adc_lld_serve_interrupt(&ADCD2, sts); -#endif /* AT32_ADC_USE_ADC2 */ - -#if AT32_ADC_USE_ADC3 - sts = ADC3->STS; - ADC3->STS = 0; -#if defined(AT32_ADC_ADC3_IRQ_HOOK) - AT32_ADC_ADC3_IRQ_HOOK -#endif - adc_lld_serve_interrupt(&ADCD3, sts); -#endif /* AT32_ADC_USE_ADC3 */ - OSAL_IRQ_EPILOGUE(); } #endif @@ -191,83 +148,35 @@ void adc_lld_init(void) { adcObjectInit(&ADCD1); ADCD1.adc = ADC1; ADCD1.dmastp = NULL; - ADCD1.dmamode = AT32_DMA_CTRL_CHSEL(ADC1_DMA_CHANNEL) | - AT32_DMA_CTRL_CHPL(AT32_ADC_ADC1_DMA_PRIORITY) | - AT32_DMA_CTRL_DTD_P2M | - AT32_DMA_CTRL_MWIDTH_HWORD | AT32_DMA_CTRL_PWIDTH_HWORD | - AT32_DMA_CTRL_MINCM | AT32_DMA_CTRL_FDTIEN | - AT32_DMA_CTRL_DMERRIEN | AT32_DMA_CTRL_DTERRIEN; + ADCD1.dmamode = AT32_DMA_CCTRL_CHPL(AT32_ADC_ADC1_DMA_PRIORITY) | + AT32_DMA_CCTRL_DTD_P2M | + AT32_DMA_CCTRL_MWIDTH_HWORD | AT32_DMA_CCTRL_PWIDTH_HWORD | + AT32_DMA_CCTRL_MINCM | AT32_DMA_CCTRL_FDTIEN | + AT32_DMA_CCTRL_DTERRIEN; + + /* Temporary activation.*/ crmEnableADC1(true); ADC1->CTRL1 = 0; ADC1->CTRL2 = ADC_CTRL2_ADCEN; /* Reset calibration just to be safe.*/ ADC1->CTRL2 = ADC_CTRL2_ADCEN | ADC_CTRL2_ADCALINIT; - while ((ADC1->CTRL2 & ADC_CTRL2_ADCALINIT) != 0); + while ((ADC1->CTRL2 & ADC_CTRL2_ADCALINIT) != 0) + ; /* Calibration.*/ ADC1->CTRL2 = ADC_CTRL2_ADCEN | ADC_CTRL2_ADCAL; - while ((ADC1->CTRL2 & ADC_CTRL2_ADCAL) != 0); + while ((ADC1->CTRL2 & ADC_CTRL2_ADCAL) != 0) + ; /* Return the ADC in low power mode.*/ ADC1->CTRL2 = 0; crmDisableADC1(); #endif -#if AT32_ADC_USE_ADC2 - /* Driver initialization.*/ - adcObjectInit(&ADCD2); - ADCD2.adc = ADC2; - ADCD2.dmastp = NULL; - ADCD2.dmamode = AT32_DMA_CTRL_CHSEL(ADC2_DMA_CHANNEL) | - AT32_DMA_CTRL_CHPL(AT32_ADC_ADC2_DMA_PRIORITY) | - AT32_DMA_CTRL_DTD_P2M | - AT32_DMA_CTRL_MWIDTH_HWORD | AT32_DMA_CTRL_PWIDTH_HWORD | - AT32_DMA_CTRL_MINCM | AT32_DMA_CTRL_FDTIEN | - AT32_DMA_CTRL_DMERRIEN | AT32_DMA_CTRL_DTERRIEN; - crmEnableADC2(true); - ADC2->CTRL1 = 0; - ADC2->CTRL2 = ADC_CTRL2_ADCEN; - - /* Reset calibration just to be safe.*/ - ADC2->CTRL2 = ADC_CTRL2_ADCEN | ADC_CTRL2_ADCALINIT; - while ((ADC2->CTRL2 & ADC_CTRL2_ADCALINIT) != 0); - - /* Calibration.*/ - ADC2->CTRL2 = ADC_CTRL2_ADCEN | ADC_CTRL2_ADCAL; - while ((ADC2->CTRL2 & ADC_CTRL2_ADCAL) != 0); - - /* Return the ADC in low power mode.*/ - ADC2->CTRL2 = 0; - crmDisableADC2(); -#endif - -#if AT32_ADC_USE_ADC3 - /* Driver initialization.*/ - adcObjectInit(&ADCD3); - ADCD3.adc = ADC3; - ADCD3.dmastp = NULL; - ADCD3.dmamode = AT32_DMA_CTRL_CHSEL(ADC3_DMA_CHANNEL) | - AT32_DMA_CTRL_CHPL(AT32_ADC_ADC3_DMA_PRIORITY) | - AT32_DMA_CTRL_DTD_P2M | - AT32_DMA_CTRL_MWIDTH_HWORD | AT32_DMA_CTRL_PWIDTH_HWORD | - AT32_DMA_CTRL_MINCM | AT32_DMA_CTRL_FDTIEN | - AT32_DMA_CTRL_DMERRIEN | AT32_DMA_CTRL_DTERRIEN; - crmEnableADC3(true); - ADC3->CTRL1 = 0; - ADC3->CTRL2 = ADC_CTRL2_ADCEN; - - /* Reset calibration just to be safe.*/ - ADC3->CTRL2 = ADC_CTRL2_ADCEN | ADC_CTRL2_ADCALINIT; - while ((ADC3->CTRL2 & ADC_CTRL2_ADCALINIT) != 0); - - /* Calibration.*/ - ADC3->CTRL2 = ADC_CTRL2_ADCEN | ADC_CTRL2_ADCAL; - while ((ADC3->CTRL2 & ADC_CTRL2_ADCAL) != 0); - - /* Return the ADC in low power mode.*/ - ADC3->CTRL2 = 0; - crmDisableADC3(); +#if defined(crmResetADC) + /* Shared reset case.*/ + crmResetADC(); #endif /* The shared vector is initialized on driver initialization and never @@ -294,68 +203,22 @@ void adc_lld_start(ADCDriver *adcp) { (void *)adcp); osalDbgAssert(adcp->dmastp != NULL, "unable to allocate stream"); dmaStreamSetPeripheral(adcp->dmastp, &ADC1->ODT); -#if AT32_USE_DMA_V1 && AT32_DMA_USE_DMAMUX - dmaSetRequestSource(adcp->dmastp, AT32_ADC_ADC1_DMAMUX_CHANNEL, AT32_DMAMUX_ADC1); -#elif AT32_USE_DMA_V2 || AT32_USE_DMA_V3 +#if AT32_DMA_SUPPORTS_DMAMUX dmaSetRequestSource(adcp->dmastp, AT32_DMAMUX_ADC1); #endif crmEnableADC1(true); } #endif /* AT32_ADC_USE_ADC1 */ -#if AT32_ADC_USE_ADC2 - if (&ADCD2 == adcp) { - adcp->dmastp = dmaStreamAllocI(AT32_ADC_ADC2_DMA_STREAM, - AT32_ADC_ADC2_DMA_IRQ_PRIORITY, - (at32_dmasts_t)adc_lld_serve_rx_interrupt, - (void *)adcp); - osalDbgAssert(adcp->dmastp != NULL, "unable to allocate stream"); - dmaStreamSetPeripheral(adcp->dmastp, &ADC2->ODT); -#if AT32_USE_DMA_V1 && AT32_DMA_USE_DMAMUX - dmaSetRequestSource(adcp->dmastp, AT32_ADC_ADC2_DMAMUX_CHANNEL, AT32_DMAMUX_ADC2); -#elif AT32_USE_DMA_V2 || AT32_USE_DMA_V3 - dmaSetRequestSource(adcp->dmastp, AT32_DMAMUX_ADC2); -#endif - crmEnableADC2(true); - } -#endif /* AT32_ADC_USE_ADC2 */ - -#if AT32_ADC_USE_ADC3 - if (&ADCD3 == adcp) { - adcp->dmastp = dmaStreamAllocI(AT32_ADC_ADC3_DMA_STREAM, - AT32_ADC_ADC3_DMA_IRQ_PRIORITY, - (at32_dmasts_t)adc_lld_serve_rx_interrupt, - (void *)adcp); - osalDbgAssert(adcp->dmastp != NULL, "unable to allocate stream"); - dmaStreamSetPeripheral(adcp->dmastp, &ADC3->ODT); -#if AT32_USE_DMA_V1 && AT32_DMA_USE_DMAMUX - dmaSetRequestSource(adcp->dmastp, AT32_ADC_ADC3_DMAMUX_CHANNEL, AT32_DMAMUX_ADC3); -#elif AT32_USE_DMA_V2 || AT32_USE_DMA_V3 - dmaSetRequestSource(adcp->dmastp, AT32_DMAMUX_ADC3); -#endif - crmEnableADC3(true); - } -#endif /* AT32_ADC_USE_ADC3 */ - /* This is a common register but apparently it requires that at least one of the ADCs is clocked in order to allow writing, see bug 3575297.*/ -#if defined(AT32F435_437xx) - ADCCOM->CCTRL = (ADCCOM->CCTRL & (ADC_CCTRL_ITSRVEN | ADC_CCTRL_VBATEN)) | - ((AT32_ADC_ADCDIV - 2) << 16); -#elif defined(AT32F423xx) - ADCCOM->CCTRL = (ADCCOM->CCTRL & ADC_CCTRL_ITSRVEN) | - ((AT32_ADC_ADCDIV - 2) << 16); -#else adcp->adc->CTRL2 = ADC_CTRL2_ITSRVEN; - ADCCOM->CCTRL = ((AT32_ADC_ADCDIV - 2) << 16); -#endif - + ADC_COMMON->CCTRL = ((AT32_ADC_ADCDIV - 2) << 16); + /* ADC initial setup, starting the analog part here in order to reduce the latency when starting a conversion.*/ adcp->adc->CTRL1 = 0; -#if defined(AT32F435_437xx) || defined(AT32F423xx) adcp->adc->CTRL2 = 0; -#endif adcp->adc->CTRL2 = ADC_CTRL2_ADCEN; } } @@ -382,16 +245,6 @@ void adc_lld_stop(ADCDriver *adcp) { if (&ADCD1 == adcp) crmDisableADC1(); #endif - -#if AT32_ADC_USE_ADC2 - if (&ADCD2 == adcp) - crmDisableADC2(); -#endif - -#if AT32_ADC_USE_ADC3 - if (&ADCD3 == adcp) - crmDisableADC3(); -#endif } } @@ -410,11 +263,11 @@ void adc_lld_start_conversion(ADCDriver *adcp) { /* DMA setup.*/ mode = adcp->dmamode; if (grpp->circular) { - mode |= AT32_DMA_CTRL_LM; + mode |= AT32_DMA_CCTRL_LM; if (adcp->depth > 1) { /* If circular buffer depth > 1, then the half transfer interrupt is enabled in order to allow streaming processing.*/ - mode |= AT32_DMA_CTRL_HDTIEN; + mode |= AT32_DMA_CCTRL_HDTIEN; } } dmaStreamSetMemory0(adcp->dmastp, adcp->samples); @@ -432,33 +285,19 @@ void adc_lld_start_conversion(ADCDriver *adcp) { adcp->adc->OSQ1 = grpp->osq1 | ADC_OSQ1_NUM_CH(grpp->num_channels); adcp->adc->OSQ2 = grpp->osq2; adcp->adc->OSQ3 = grpp->osq3; -#if AT32_ADC_MAX_CHANNELS >= 20 - adcp->adc->SPT3 = grpp->spt3; - adcp->adc->OSQ4 = grpp->osq4; - adcp->adc->OSQ4 = grpp->osq5; - adcp->adc->OSQ4 = grpp->osq6; -#endif /* ADC configuration and start.*/ -#if defined(AT32F435_437xx) || defined(AT32F423xx) - adcp->adc->CTRL1 = grpp->ctrl1 | ADC_CTRL1_OCCOIE | ADC_CTRL1_SQEN; - ctrl2 = grpp->ctrl2 | ADC_CTRL2_OCDMAEN | ADC_CTRL2_OCDRCEN | ADC_CTRL2_ADCEN; -#else - adcp->adc->CTRL1 = grpp->ctrl1 | ADC_CTRL1_OCCOIE | ADC_CTRL1_SQEN; + adcp->adc->CTRL1 = grpp->ctrl1 | ADC_CTRL1_SQEN; + + /* Enforcing the mandatory bits in CTRL2.*/ ctrl2 = grpp->ctrl2 | ADC_CTRL2_OCDMAEN | ADC_CTRL2_ADCEN; -#endif - /* The start method is different dependign if HW or SW triggered, the - start is performed using the method specified in the CTRL2 configuration.*/ - if ((ctrl2 & ADC_CTRL2_OCSWTRG) != 0) { - /* Initializing CTRL2 while keeping ADC_CTRL2_OCSWTRG at zero.*/ - adcp->adc->CTRL2 = (ctrl2 | ADC_CTRL2_RPEN) & ~ADC_CTRL2_OCSWTRG; + if ((ctrl2 & (ADC_CTRL2_OCTEN | ADC_CTRL2_PCTEN)) == 0) + ctrl2 |= ADC_CTRL2_RPEN; + adcp->adc->CTRL2 = grpp->ctrl2 | ctrl2; - /* Finally enabling ADC_CTRL2_OCSWTRG.*/ - adcp->adc->CTRL2 = (ctrl2 | ADC_CTRL2_RPEN); - } - else - adcp->adc->CTRL2 = ctrl2; + /* ADC start by writing ADC_CTRL2_ADCEN a second time.*/ + adcp->adc->CTRL2 = ctrl2; } /** @@ -471,66 +310,33 @@ void adc_lld_start_conversion(ADCDriver *adcp) { void adc_lld_stop_conversion(ADCDriver *adcp) { dmaStreamDisable(adcp->dmastp); - adcp->adc->CTRL1 = 0; - /* Because ticket #822, preserving injected conversions.*/ - adcp->adc->CTRL2 &= ~(ADC_CTRL2_OCSWTRG); + adcp->adc->CTRL1 = 0U; + if ((adcp->adc->CTRL2 & ADC_CTRL2_RPEN) != 0U) { + adcp->adc->CTRL2 = 0U; + } adcp->adc->CTRL2 = ADC_CTRL2_ADCEN; } /** - * @brief Enables the TSVREFE bit. - * @details The TSVREFE bit is required in order to sample the internal + * @brief Enables the ITSRVEN bit. + * @details The ITSRVEN bit is required in order to sample the internal * temperature sensor and internal reference voltage. * @note This is an AT32-only functionality. */ void adcAT32EnableITSRVEN(void) { -#if defined(AT32F435_437xx) || defined(AT32F423xx) - ADCCOM->CCTRL |= ADC_CCTRL_ITSRVEN; -#else ADC1->CTRL2 |= ADC_CTRL2_ITSRVEN; -#endif } /** - * @brief Disables the TSVREFE bit. - * @details The TSVREFE bit is required in order to sample the internal + * @brief Disables the ITSRVEN bit. + * @details The ITSRVEN bit is required in order to sample the internal * temperature sensor and internal reference voltage. * @note This is an AT32-only functionality. */ void adcAT32DisableITSRVEN(void) { -#if defined(AT32F435_437xx) || defined(AT32F423xx) - ADCCOM->CCTRL &= ~ADC_CCTRL_ITSRVEN; -#else ADC1->CTRL2 &= ~ADC_CTRL2_ITSRVEN; -#endif -} - -/** - * @brief Enables the VBATE bit. - * @details The VBATE bit is required in order to sample the VBAT channel. - * @note This is an AT32-only functionality. - * @note This function is meant to be called after @p adcStart(). - */ -void adcAT32EnableVBATEN(void) { - -#if defined(AT32F435_437xx) - ADCCOM->CCTRL |= ADC_CCTRL_VBATEN; -#endif -} - -/** - * @brief Disables the VBATE bit. - * @details The VBATE bit is required in order to sample the VBAT channel. - * @note This is an AT32-only functionality. - * @note This function is meant to be called after @p adcStart(). - */ -void adcAT32DisableVBATEN(void) { - -#if defined(AT32F435_437xx) - ADCCOM->CCTRL &= ~ADC_CCTRL_VBATEN; -#endif } #endif /* HAL_USE_ADC */ diff --git a/os/hal/ports/AT32/LLD/ADCv2/hal_adc_lld.h b/os/hal/ports/AT32/LLD/ADCv2/hal_adc_lld.h index 1143ce59a2..da313d611e 100644 --- a/os/hal/ports/AT32/LLD/ADCv2/hal_adc_lld.h +++ b/os/hal/ports/AT32/LLD/ADCv2/hal_adc_lld.h @@ -1,6 +1,8 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 Maxjta + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + ChibiOS - Copyright (C) 2024..2025 Maxjta Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -36,9 +38,8 @@ * @name Possible ADC errors mask bits. * @{ */ -#define ADC_ERR_DMAFAILURE 1U /**< DMA operations failure. */ -#define ADC_ERR_OVERFLOW 2U /**< ADC overflow condition. */ -#define ADC_ERR_VM 4U /**< Watchdog triggered. */ +#define ADC_ERR_DMAFAILURE 1U /**< DMA operations failure. */ +#define ADC_ERR_VM 4U /**< Voltage monitoring triggered. */ /** @} */ /** @@ -53,37 +54,15 @@ /** * @brief Maximum ADC clock frequency. */ -#if !defined(AT32_ADCCLK_MAX) -#if defined(AT32F435_7xx) || defined(AT32F423xx) -#define AT32_ADCCLK_MAX 80000000 -#else #define AT32_ADCCLK_MAX 28000000 -#endif -#endif /** @} */ /** * @name Triggers selection * @{ */ -#define ADC_CTRL2_OCETE_MASK (3U << 28U) -#define ADC_CTRL2_OCETE_DISABLED (0U << 28U) -#define ADC_CTRL2_OCETE_RISING (1U << 28U) -#define ADC_CTRL2_OCETE_FALLING (2U << 28U) -#define ADC_CTRL2_OCETE_BOTH (3U << 28U) - -#define ADC_CTRL2_OCTESEL_MASK ((15U << 24U) | (1U << 31)) -#define ADC_CTRL2_OCTESEL_SRC(n) (((n) << 24U) | \ - (((n) >> 4) << 31)) -/** @} */ - -/** - * @name Available analog channels nums - * @{ - */ -#if !defined(AT32_ADC_MAX_CHANNELS) -#define AT32_ADC_MAX_CHANNELS 18 -#endif +#define ADC_CTRL2_OCTESEL_MASK (7U << 17U) +#define ADC_CTRL2_OCTESEL_SRC(n) ((n) << 17U) /** @} */ /** @@ -107,43 +86,42 @@ #define ADC_CHANNEL_IN14 14 /**< @brief External analog input 14. */ #define ADC_CHANNEL_IN15 15 /**< @brief External analog input 15. */ #define ADC_CHANNEL_SENSOR 16 /**< @brief Internal temperature sensor. - @note Available onADC1 only. */ -#define ADC_CHANNEL_VINTRV 17 /**< @brief Internal reference. - @note Available onADC1 only. */ -#define ADC_CHANNEL_VBAT 18 /**< @brief VBAT. - @note Available onADC1 only. */ -#define ADC_CHANNEL_IN20 20 /**< @brief External analog input 20. */ -#define ADC_CHANNEL_IN21 21 /**< @brief External analog input 21. */ -#define ADC_CHANNEL_IN22 22 /**< @brief External analog input 22. */ -#define ADC_CHANNEL_IN23 23 /**< @brief External analog input 23. */ -#define ADC_CHANNEL_IN24 24 /**< @brief External analog input 24. */ -#define ADC_CHANNEL_IN25 25 /**< @brief External analog input 25. */ -#define ADC_CHANNEL_IN26 26 /**< @brief External analog input 26. */ -#define ADC_CHANNEL_IN27 27 /**< @brief External analog input 27. */ + @note Available on ADC1 only. */ +#define ADC_CHANNEL_VREF 17 /**< @brief Internal reference. + @note Available on ADC1 only. */ /** @} */ /** * @name Sampling rates * @{ */ -#if defined(AT32F435_437xx) || defined(AT32F423xx) || defined(__DOXYGEN__) -#define ADC_SAMPLE_2P5 0 /**< @brief 2.5 cycles sampling time. */ -#define ADC_SAMPLE_6P5 1 /**< @brief 6.5 cycles sampling time. */ -#define ADC_SAMPLE_12P5 2 /**< @brief 12.5 cycles sampling time. */ -#define ADC_SAMPLE_24P5 3 /**< @brief 24.5 cycles sampling time. */ -#define ADC_SAMPLE_47P5 4 /**< @brief 47.5 cycles sampling time. */ -#define ADC_SAMPLE_92P5 5 /**< @brief 92.5 cycles sampling time. */ -#define ADC_SAMPLE_247P5 6 /**< @brief 247.5 cycles sampling time. */ -#define ADC_SAMPLE_640P5 7 /**< @brief 640.5 cycles sampling time. */ -#else -#define ADC_SAMPLE_1P5 0 /**< @brief 1.5 cycles sampling time. */ -#define ADC_SAMPLE_7P5 1 /**< @brief 7.5 cycles sampling time. */ -#define ADC_SAMPLE_13P5 2 /**< @brief 13.5 cycles sampling time. */ -#define ADC_SAMPLE_28P5 3 /**< @brief 28.5 cycles sampling time. */ -#define ADC_SAMPLE_41P5 4 /**< @brief 41.5 cycles sampling time. */ -#define ADC_SAMPLE_55P5 5 /**< @brief 55.5 cycles sampling time. */ -#define ADC_SAMPLE_71P5 6 /**< @brief 71.5 cycles sampling time. */ -#define ADC_SAMPLE_239P5 7 /**< @brief 239.5 cycles sampling time. */ +#define ADC_SAMPLE_1P5 0 /**< @brief 1.5 cycles sampling time. */ +#define ADC_SAMPLE_7P5 1 /**< @brief 7.5 cycles sampling time. */ +#define ADC_SAMPLE_13P5 2 /**< @brief 13.5 cycles sampling time. */ +#define ADC_SAMPLE_28P5 3 /**< @brief 28.5 cycles sampling time. */ +#define ADC_SAMPLE_41P5 4 /**< @brief 41.5 cycles sampling time. */ +#define ADC_SAMPLE_55P5 5 /**< @brief 55.5 cycles sampling time. */ +#define ADC_SAMPLE_71P5 6 /**< @brief 71.5 cycles sampling time. */ +#define ADC_SAMPLE_239P5 7 /**< @brief 239.5 cycles sampling time. */ +/** @} */ + +/** + * @name OVSP register configuration helpers + * @{ + */ +#if (AT32_ADC_SUPPORTS_OVERSAMPLING == TRUE) || defined(__DOXYGEN__) +#define ADC_OVSP_OSRSEL_MASK (7U << 2U) +#define ADC_OVSP_OSRSEL_2X (0U << 2U) +#define ADC_OVSP_OSRSEL_4X (1U << 2U) +#define ADC_OVSP_OSRSEL_8X (2U << 2U) +#define ADC_OVSP_OSRSEL_16X (3U << 2U) +#define ADC_OVSP_OSRSEL_32X (4U << 2U) +#define ADC_OVSP_OSRSEL_64X (5U << 2U) +#define ADC_OVSP_OSRSEL_128X (6U << 2U) +#define ADC_OVSP_OSRSEL_256X (7U << 2U) + +#define ADC_OVSP_OSSSEL_MASK (15 << 5U) +#define ADC_OVSP_OSSSEL_SHIFT(n) ((n) << 5U) #endif /** @} */ @@ -162,7 +140,7 @@ * info. */ #if !defined(AT32_ADC_ADCDIV) || defined(__DOXYGEN__) -#define AT32_ADC_ADCDIV 16 +#define AT32_ADC_ADCDIV 8 #endif /** @@ -171,97 +149,35 @@ * @note The default is @p TRUE. */ #if !defined(AT32_ADC_USE_ADC1) || defined(__DOXYGEN__) -#define AT32_ADC_USE_ADC1 FALSE -#endif - -/** - * @brief ADC2 driver enable switch. - * @details If set to @p TRUE the support for ADC2 is included. - * @note The default is @p TRUE. - */ -#if !defined(AT32_ADC_USE_ADC2) || defined(__DOXYGEN__) -#define AT32_ADC_USE_ADC2 FALSE -#endif - -/** - * @brief ADC3 driver enable switch. - * @details If set to @p TRUE the support for ADC3 is included. - * @note The default is @p TRUE. - */ -#if !defined(AT32_ADC_USE_ADC3) || defined(__DOXYGEN__) -#define AT32_ADC_USE_ADC3 FALSE +#define AT32_ADC_USE_ADC1 FALSE #endif /** * @brief DMA stream used for ADC1 operations. */ #if !defined(AT32_ADC_ADC1_DMA_STREAM) || defined(__DOXYGEN__) -#define AT32_ADC_ADC1_DMA_STREAM AT32_DMA_STREAM_ID_ANY -#endif - -/** - * @brief DMA stream used for ADC2 operations. - */ -#if !defined(AT32_ADC_ADC2_DMA_STREAM) || defined(__DOXYGEN__) -#define AT32_ADC_ADC2_DMA_STREAM AT32_DMA_STREAM_ID_ANY -#endif - -/** - * @brief DMA stream used for ADC3 operations. - */ -#if !defined(AT32_ADC_ADC3_DMA_STREAM) || defined(__DOXYGEN__) -#define AT32_ADC_ADC3_DMA_STREAM AT32_DMA_STREAM_ID_ANY +#define AT32_ADC_ADC1_DMA_STREAM AT32_DMA_STREAM_ID_ANY #endif /** * @brief ADC1 DMA priority (0..3|lowest..highest). */ #if !defined(AT32_ADC_ADC1_DMA_PRIORITY) || defined(__DOXYGEN__) -#define AT32_ADC_ADC1_DMA_PRIORITY 2 -#endif - -/** - * @brief ADC2 DMA priority (0..3|lowest..highest). - */ -#if !defined(AT32_ADC_ADC2_DMA_PRIORITY) || defined(__DOXYGEN__) -#define AT32_ADC_ADC2_DMA_PRIORITY 2 -#endif - -/** - * @brief ADC3 DMA priority (0..3|lowest..highest). - */ -#if !defined(AT32_ADC_ADC3_DMA_PRIORITY) || defined(__DOXYGEN__) -#define AT32_ADC_ADC3_DMA_PRIORITY 2 +#define AT32_ADC_ADC1_DMA_PRIORITY 2 #endif /** * @brief ADC interrupt priority level setting. - * @note This setting is shared among ADC1, ADC2 and ADC3 because - * all ADCs share the same vector. */ #if !defined(AT32_ADC_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define AT32_ADC_IRQ_PRIORITY 5 +#define AT32_ADC_IRQ_PRIORITY 5 #endif /** * @brief ADC1 DMA interrupt priority level setting. */ #if !defined(AT32_ADC_ADC1_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define AT32_ADC_ADC1_DMA_IRQ_PRIORITY 5 -#endif - -/** - * @brief ADC2 DMA interrupt priority level setting. - */ -#if !defined(AT32_ADC_ADC2_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define AT32_ADC_ADC2_DMA_IRQ_PRIORITY 5 -#endif - -/** - * @brief ADC3 DMA interrupt priority level setting. - */ -#if !defined(AT32_ADC_ADC3_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define AT32_ADC_ADC3_DMA_IRQ_PRIORITY 5 +#define AT32_ADC_ADC1_DMA_IRQ_PRIORITY 5 #endif /** @} */ @@ -270,62 +186,14 @@ /* Derived constants and error checks. */ /*===========================================================================*/ -/* Registry checks.*/ -#if !defined(AT32_HAS_ADC1) || !defined(AT32_HAS_ADC2) || \ - !defined(AT32_HAS_ADC3) -#error "AT32_HAS_ADCx not defined in registry" -#endif - -#if !AT32_DMA_SUPPORTS_DMAMUX -#if (AT32_ADC_USE_ADC1 && !defined(AT32_ADC1_DMA_MSK)) || \ - (AT32_ADC_USE_ADC2 && !defined(AT32_ADC2_DMA_MSK)) || \ - (AT32_ADC_USE_ADC3 && !defined(AT32_ADC3_DMA_MSK)) -#error "AT32_ADCx_DMA_MSK not defined in registry" -#endif - -#if (AT32_ADC_USE_ADC1 && !defined(AT32_ADC1_DMA_CHN)) || \ - (AT32_ADC_USE_ADC2 && !defined(AT32_ADC2_DMA_CHN)) || \ - (AT32_ADC_USE_ADC3 && !defined(AT32_ADC3_DMA_CHN)) -#error "AT32_ADCx_DMA_CHN not defined in registry" -#endif -#endif /* !AT32_DMA_SUPPORTS_DMAMUX */ - #if AT32_ADC_USE_ADC1 && !AT32_HAS_ADC1 #error "ADC1 not present in the selected device" #endif -#if AT32_ADC_USE_ADC2 && !AT32_HAS_ADC2 -#error "ADC2 not present in the selected device" -#endif - -#if AT32_ADC_USE_ADC3 && !AT32_HAS_ADC3 -#error "ADC3 not present in the selected device" -#endif - -#if !AT32_ADC_USE_ADC1 && !AT32_ADC_USE_ADC2 && !AT32_ADC_USE_ADC3 +#if !AT32_ADC_USE_ADC1 #error "ADC driver activated but no ADC peripheral assigned" #endif -#if !AT32_DMA_SUPPORTS_DMAMUX - -/* Check on the validity of the assigned DMA channels.*/ -#if AT32_ADC_USE_ADC1 && \ - !AT32_DMA_IS_VALID_ID(AT32_ADC_ADC1_DMA_STREAM, AT32_ADC1_DMA_MSK) -#error "invalid DMA stream associated to ADC1" -#endif - -#if AT32_ADC_USE_ADC2 && \ - !AT32_DMA_IS_VALID_ID(AT32_ADC_ADC2_DMA_STREAM, AT32_ADC2_DMA_MSK) -#error "invalid DMA stream associated to ADC2" -#endif - -#if AT32_ADC_USE_ADC3 && \ - !AT32_DMA_IS_VALID_ID(AT32_ADC_ADC3_DMA_STREAM, AT32_ADC3_DMA_MSK) -#error "invalid DMA stream associated to ADC3" -#endif - -#endif /* !AT32_DMA_SUPPORTS_DMAMUX */ - #if !defined(AT32_ADCCLKIN) #define AT32_ADCCLKIN AT32_HCLK #endif @@ -372,9 +240,9 @@ typedef uint32_t adcerror_t; */ #define adc_lld_driver_fields \ /* Pointer to the ADCx registers block.*/ \ - ADC_TypeDef *adc; \ + ADC_TypeDef *adc; \ /* Pointer to associated DMA channel.*/ \ - const at32_dma_stream_t *dmastp; \ + const at32_dma_stream_t *dmastp; \ /* DMA mode bit mask.*/ \ uint32_t dmamode @@ -388,55 +256,41 @@ typedef uint32_t adcerror_t; /** * @brief Low level fields of the ADC configuration structure. */ -#if AT32_ADC_MAX_CHANNELS < 20 #define adc_lld_configuration_group_fields \ - /* ADC CTRL1 register initialization data.*/ \ + /* ADC CTRL1 register initialization data. \ + NOTE: All the required bits must be defined into this field except \ + @p ADC_CTRL1_SQEN that is enforced inside the driver.*/ \ uint32_t ctrl1; \ - /* ADC CTRL2 register initialization data.*/ \ + /* ADC CTRL2 register initialization data. \ + NOTE: All the required bits must be defined into this field except \ + @p ADC_CTRL2_OCDMAEN, @p ADC_CTRL2_RPEN and @p ADC_CTRL2_ADCEN \ + that are enforced inside the driver.*/ \ uint32_t ctrl2; \ - /* ADC SPT1 register initialization data.*/ \ + /* ADC SPT1 register initialization data. \ + NOTE: In this field must be specified the sample times for channels \ + 10...17.*/ \ uint32_t spt1; \ - /* ADC SPT2 register initialization data.*/ \ + /* ADC SPT2 register initialization data. \ + NOTE: In this field must be specified the sample times for channels \ + 0...9.*/ \ uint32_t spt2; \ - /* ADC voltage monitoring high boundary.*/ \ + /* ADC voltage monitoring high boundary register. \ + NOTE: This field defines the high boundary of the analog \ + voltage monitoring.*/ \ uint16_t vmhb; \ - /* ADC voltage monitoring low boundary.*/ \ + /* ADC voltage monitoring low boundary register. \ + NOTE: This field defines the low boundary of the analog \ + voltage monitoring.*/ \ uint16_t vmlb; \ - /* ADC OSQ1 register initialization data.*/ \ + /* ADC OSQ1 register initialization data. \ + NOTE: Conversion group sequence 13...16 + sequence length.*/ \ uint32_t osq1; \ - /* ADC OSQ2 register initialization data.*/ \ + /* ADC OSQ2 register initialization data. \ + NOTE: Conversion group sequence 7...12.*/ \ uint32_t osq2; \ - /* ADC OSQ3 register initialization data.*/ \ + /* ADC OSQ3 register initialization data. \ + NOTE: Conversion group sequence 1...6.*/ \ uint32_t osq3 -#else -#define adc_lld_configuration_group_fields \ - /* ADC CTRL1 register initialization data.*/ \ - uint32_t ctrl1; \ - /* ADC CTRL2 register initialization data.*/ \ - uint32_t ctrl2; \ - /* ADC SPT1 register initialization data.*/ \ - uint32_t spt1; \ - /* ADC SPT2 register initialization data.*/ \ - uint32_t spt2; \ - /* ADC voltage monitoring high boundary.*/ \ - uint16_t vmhb; \ - /* ADC voltage monitoring low boundary.*/ \ - uint16_t vmlb; \ - /* ADC OSQ1 register initialization data.*/ \ - uint32_t osq1; \ - /* ADC OSQ2 register initialization data.*/ \ - uint32_t osq2; \ - /* ADC OSQ3 register initialization data.*/ \ - uint32_t osq3; \ - /* ADC SPT3 register initialization data.*/ \ - uint32_t spt3; \ - /* ADC OSQ4 register initialization data.*/ \ - uint32_t osq4; \ - /* ADC OSQ5 register initialization data.*/ \ - uint32_t osq5; \ - /* ADC OSQ6 register initialization data.*/ \ - uint32_t osq6 -#endif /** * @name Sequences building helper macros @@ -465,62 +319,33 @@ typedef uint32_t adcerror_t; #define ADC_OSQ1_OSN14_N(n) ((n) << 5) /**< @brief 14th channel in seq.*/ #define ADC_OSQ1_OSN15_N(n) ((n) << 10) /**< @brief 15th channel in seq.*/ #define ADC_OSQ1_OSN16_N(n) ((n) << 15) /**< @brief 16th channel in seq.*/ - -#define ADC_OSQ4_OSN17_N(n) ((n) << 0) /**< @brief 17th channel in seq.*/ -#define ADC_OSQ4_OSN18_N(n) ((n) << 5) /**< @brief 18th channel in seq.*/ -#define ADC_OSQ4_OSN19_N(n) ((n) << 10) /**< @brief 19th channel in seq.*/ -#define ADC_OSQ4_OSN20_N(n) ((n) << 15) /**< @brief 20th channel in seq.*/ -#define ADC_OSQ4_OSN21_N(n) ((n) << 20) /**< @brief 21th channel in seq.*/ -#define ADC_OSQ4_OSN22_N(n) ((n) << 25) /**< @brief 22th channel in seq.*/ - -#define ADC_OSQ5_OSN23_N(n) ((n) << 0) /**< @brief 23th channel in seq.*/ -#define ADC_OSQ5_OSN24_N(n) ((n) << 5) /**< @brief 24th channel in seq.*/ -#define ADC_OSQ5_OSN25_N(n) ((n) << 10) /**< @brief 25th channel in seq.*/ -#define ADC_OSQ5_OSN26_N(n) ((n) << 15) /**< @brief 26th channel in seq.*/ -#define ADC_OSQ5_OSN27_N(n) ((n) << 20) /**< @brief 27th channel in seq.*/ -#define ADC_OSQ5_OSN28_N(n) ((n) << 25) /**< @brief 28th channel in seq.*/ - -#define ADC_OSQ6_OSN29_N(n) ((n) << 0) /**< @brief 29th channel in seq.*/ -#define ADC_OSQ6_OSN30_N(n) ((n) << 5) /**< @brief 30th channel in seq.*/ -#define ADC_OSQ6_OSN31_N(n) ((n) << 10) /**< @brief 31th channel in seq.*/ -#define ADC_OSQ6_OSN32_N(n) ((n) << 15) /**< @brief 32th channel in seq.*/ /** @} */ /** * @name Sampling rate settings helper macros * @{ */ -#define ADC_SPT2_CSPT0(n) ((n) << 0) /**< @brief AN0 sampling time. */ -#define ADC_SPT2_CSPT1(n) ((n) << 3) /**< @brief AN1 sampling time. */ -#define ADC_SPT2_CSPT2(n) ((n) << 6) /**< @brief AN2 sampling time. */ -#define ADC_SPT2_CSPT3(n) ((n) << 9) /**< @brief AN3 sampling time. */ -#define ADC_SPT2_CSPT4(n) ((n) << 12) /**< @brief AN4 sampling time. */ -#define ADC_SPT2_CSPT5(n) ((n) << 15) /**< @brief AN5 sampling time. */ -#define ADC_SPT2_CSPT6(n) ((n) << 18) /**< @brief AN6 sampling time. */ -#define ADC_SPT2_CSPT7(n) ((n) << 21) /**< @brief AN7 sampling time. */ -#define ADC_SPT2_CSPT8(n) ((n) << 24) /**< @brief AN8 sampling time. */ -#define ADC_SPT2_CSPT9(n) ((n) << 27) /**< @brief AN9 sampling time. */ - -#define ADC_SPT1_CSPT10(n) ((n) << 0) /**< @brief AN10 sampling time. */ -#define ADC_SPT1_CSPT11(n) ((n) << 3) /**< @brief AN11 sampling time. */ -#define ADC_SPT1_CSPT12(n) ((n) << 6) /**< @brief AN12 sampling time. */ -#define ADC_SPT1_CSPT13(n) ((n) << 9) /**< @brief AN13 sampling time. */ -#define ADC_SPT1_CSPT14(n) ((n) << 12) /**< @brief AN14 sampling time. */ -#define ADC_SPT1_CSPT15(n) ((n) << 15) /**< @brief AN15 sampling time. */ -#define ADC_SPT1_CSPT16(n) ((n) << 18) /**< @brief Temperature Sensor +#define ADC_SPT2_CSPT_AN0(n) ((n) << 0) /**< @brief AN0 sampling time. */ +#define ADC_SPT2_CSPT_AN1(n) ((n) << 3) /**< @brief AN1 sampling time. */ +#define ADC_SPT2_CSPT_AN2(n) ((n) << 6) /**< @brief AN2 sampling time. */ +#define ADC_SPT2_CSPT_AN3(n) ((n) << 9) /**< @brief AN3 sampling time. */ +#define ADC_SPT2_CSPT_AN4(n) ((n) << 12) /**< @brief AN4 sampling time. */ +#define ADC_SPT2_CSPT_AN5(n) ((n) << 15) /**< @brief AN5 sampling time. */ +#define ADC_SPT2_CSPT_AN6(n) ((n) << 18) /**< @brief AN6 sampling time. */ +#define ADC_SPT2_CSPT_AN7(n) ((n) << 21) /**< @brief AN7 sampling time. */ +#define ADC_SPT2_CSPT_AN8(n) ((n) << 24) /**< @brief AN8 sampling time. */ +#define ADC_SPT2_CSPT_AN9(n) ((n) << 27) /**< @brief AN9 sampling time. */ + +#define ADC_SPT1_CSPT_AN10(n) ((n) << 0) /**< @brief AN10 sampling time. */ +#define ADC_SPT1_CSPT_AN11(n) ((n) << 3) /**< @brief AN11 sampling time. */ +#define ADC_SPT1_CSPT_AN12(n) ((n) << 6) /**< @brief AN12 sampling time. */ +#define ADC_SPT1_CSPT_AN13(n) ((n) << 9) /**< @brief AN13 sampling time. */ +#define ADC_SPT1_CSPT_AN14(n) ((n) << 12) /**< @brief AN14 sampling time. */ +#define ADC_SPT1_CSPT_AN15(n) ((n) << 15) /**< @brief AN15 sampling time. */ +#define ADC_SPT1_CSPT_SENSOR(n) ((n) << 18) /**< @brief Temperature Sensor sampling time. */ -#define ADC_SPT1_CSPT17(n) ((n) << 21) /**< @brief Voltage Reference +#define ADC_SPT1_CSPT_VREF(n) ((n) << 21) /**< @brief Voltage Reference sampling time. */ -#define ADC_SPT1_CSPT18(n) ((n) << 24) /**< @brief VBAT sampling time. */ - -#define ADC_SPT3_CSPT20(n) ((n) << 0) /**< @brief AN20 sampling time. */ -#define ADC_SPT3_CSPT21(n) ((n) << 3) /**< @brief AN21 sampling time. */ -#define ADC_SPT3_CSPT22(n) ((n) << 6) /**< @brief AN22 sampling time. */ -#define ADC_SPT3_CSPT23(n) ((n) << 9) /**< @brief AN23 sampling time. */ -#define ADC_SPT3_CSPT24(n) ((n) << 12) /**< @brief AN24 sampling time. */ -#define ADC_SPT3_CSPT25(n) ((n) << 15) /**< @brief AN25 sampling time. */ -#define ADC_SPT3_CSPT26(n) ((n) << 18) /**< @brief AN26 sampling time. */ -#define ADC_SPT3_CSPT27(n) ((n) << 21) /**< @brief AN27 sampling time. */ /** @} */ /** @@ -530,11 +355,11 @@ typedef uint32_t adcerror_t; /** * @brief High voltage monitoring boundary. */ -#define ADC_VMHB(n) ((n > ADC_VMHB_HB) ? ADC_VMHB_HB : n) +#define ADC_VMHB(n) ((n > ADC_VMHB_HB) ? ADC_VMHB_HB : n) /** * @brief Low voltage monitoring boundary. */ -#define ADC_VMHL(n) ((n > ADC_VMHL_LB) ? ADC_VMHL_LB : n) +#define ADC_VMLB(n) ((n > ADC_VMLB_LB) ? ADC_VMLB_LB : n) /** @} */ /*===========================================================================*/ @@ -545,14 +370,6 @@ typedef uint32_t adcerror_t; extern ADCDriver ADCD1; #endif -#if AT32_ADC_USE_ADC2 && !defined(__DOXYGEN__) -extern ADCDriver ADCD2; -#endif - -#if AT32_ADC_USE_ADC3 && !defined(__DOXYGEN__) -extern ADCDriver ADCD3; -#endif - #ifdef __cplusplus extern "C" { #endif @@ -563,8 +380,6 @@ extern "C" { void adc_lld_stop_conversion(ADCDriver *adcp); void adcAT32EnableITSRVEN(void); void adcAT32DisableITSRVEN(void); - void adcAT32EnableVBATEN(void); - void adcAT32DisableVBATEN(void); #ifdef __cplusplus } #endif diff --git a/os/hal/ports/AT32/LLD/CRCv1/hal_crc_lld.c b/os/hal/ports/AT32/LLD/CRCv1/hal_crc_lld.c index 09c065cb7a..5bac9f273a 100644 --- a/os/hal/ports/AT32/LLD/CRCv1/hal_crc_lld.c +++ b/os/hal/ports/AT32/LLD/CRCv1/hal_crc_lld.c @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2015 Michael D. Spradling - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/CRCv1/hal_crc_lld.h b/os/hal/ports/AT32/LLD/CRCv1/hal_crc_lld.h index f443c0a911..1211d61024 100644 --- a/os/hal/ports/AT32/LLD/CRCv1/hal_crc_lld.h +++ b/os/hal/ports/AT32/LLD/CRCv1/hal_crc_lld.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2015 Michael D. Spradling - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -62,7 +62,7 @@ * @brief CRC1 DMA interrupt priority level setting. */ #if !defined(AT32_CRC_CRC1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define AT32_CRC_CRC1_IRQ_PRIORITY 1 +#define AT32_CRC_CRC1_IRQ_PRIORITY 5 #endif /** diff --git a/os/hal/ports/AT32/LLD/DMAv1/at32_dma.c b/os/hal/ports/AT32/LLD/DMAv1/at32_dma.c index be862b066b..dfd0d9a9f8 100644 --- a/os/hal/ports/AT32/LLD/DMAv1/at32_dma.c +++ b/os/hal/ports/AT32/LLD/DMAv1/at32_dma.c @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -205,7 +205,7 @@ static struct { /** * @brief DMA callback function. */ - at32_dmasts_t func; + at32_dmasts_t func; /** * @brief DMA callback parameter. */ diff --git a/os/hal/ports/AT32/LLD/DMAv1/at32_dma.h b/os/hal/ports/AT32/LLD/DMAv1/at32_dma.h index c09aecee36..a51d80920c 100644 --- a/os/hal/ports/AT32/LLD/DMAv1/at32_dma.h +++ b/os/hal/ports/AT32/LLD/DMAv1/at32_dma.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -65,6 +65,27 @@ */ #define AT32_DMA_IS_VALID_PRIORITY(prio) (((prio) >= 0U) && ((prio) <= 3U)) +#if (AT32_DMA_SUPPORTS_DMAMUX == FALSE) || defined(_DOXYGEN__) +/** + * @brief Checks if a DMA stream id is within the valid range. + * + * @param[in] id DMA stream id + * @retval The check result. + * @retval false invalid DMA channel. + * @retval true correct DMA channel. + */ +#define AT32_DMA_IS_VALID_STREAM(id) (((id) >= 0U) && \ + ((id) < AT32_DMA_STREAMS)) +#else /* AT32_DMA_SUPPORTS_DMAMUX == FALSE */ +#if AT32_DMA2_NUM_CHANNELS > 0 +#define AT32_DMA_IS_VALID_STREAM(id) (((id) >= 0U) && \ + ((id) <= (AT32_DMA_STREAMS + 2))) +#else +#define AT32_DMA_IS_VALID_STREAM(id) (((id) >= 0U) && \ + ((id) <= (AT32_DMA_STREAMS + 1))) +#endif +#endif /* AT32_DMA_SUPPORTS_DMAMUX == FALSE */ + /** * @brief Returns an unique numeric identifier for a DMA stream. * @@ -72,7 +93,7 @@ * @param[in] stream the stream number * @return An unique numeric stream identifier. */ -#define AT32_DMA_STREAM_ID(dma, stream) \ +#define AT32_DMA_STREAM_ID(dma, stream) \ ((((dma) - 1) * AT32_DMA1_NUM_CHANNELS) + ((stream) - 1)) /** diff --git a/os/hal/ports/AT32/LLD/DMAv2/at32_dma.c b/os/hal/ports/AT32/LLD/DMAv2/at32_dma.c index 99fbb52a3a..12177729b0 100644 --- a/os/hal/ports/AT32/LLD/DMAv2/at32_dma.c +++ b/os/hal/ports/AT32/LLD/DMAv2/at32_dma.c @@ -1,6 +1,8 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 Maxjta + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + ChibiOS - Copyright (C) 2024..2025 Maxjta Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -16,7 +18,7 @@ */ /** - * @file DMAv1/at32_dma.c + * @file DMAv2/at32_dma.c * @brief DMA helper driver code. * * @addtogroup AT32_DMA @@ -24,9 +26,9 @@ * shared resource, this driver allows to allocate and free DMA * streams at runtime in order to allow all the other device * drivers to coordinate the access to the resource. - * @note The DMA ISR handlers are all declared into this module because + * @note The DMA STS handlers are all declared into this module because * sharing, the various device drivers can associate a callback to - * ISRs when allocating streams. + * STSs when allocating streams. * @{ */ @@ -43,46 +45,15 @@ /** * @brief Mask of the DMA1 streams in @p dma_streams_mask. */ -#define AT32_DMA1_STREAMS_MASK ((1U << AT32_DMA1_NUM_CHANNELS) - 1U) +#define AT32_DMA1_STREAMS_MASK ((1U << AT32_DMA1_NUM_CHANNELS) - 1U) /** * @brief Mask of the DMA2 streams in @p dma_streams_mask. */ -#define AT32_DMA2_STREAMS_MASK (((1U << AT32_DMA2_NUM_CHANNELS) - \ +#define AT32_DMA2_STREAMS_MASK (((1U << AT32_DMA2_NUM_CHANNELS) - \ 1U) << AT32_DMA1_NUM_CHANNELS) -#if AT32_DMA_SUPPORTS_CSELR == TRUE - -#if defined(DMA1_CSELR) -#define __DMA1_CSELR &DMA1_CSELR->CSELR -#else -#define __DMA1_CSELR &DMA1->CSELR -#endif - -#if defined(DMA2_CSELR) -#define __DMA2_CSELR &DMA2_CSELR->CSELR -#else -#define __DMA2_CSELR &DMA2->CSELR -#endif - -#define DMA1_CH1_VARIANT __DMA1_CSELR -#define DMA1_CH2_VARIANT __DMA1_CSELR -#define DMA1_CH3_VARIANT __DMA1_CSELR -#define DMA1_CH4_VARIANT __DMA1_CSELR -#define DMA1_CH5_VARIANT __DMA1_CSELR -#define DMA1_CH6_VARIANT __DMA1_CSELR -#define DMA1_CH7_VARIANT __DMA1_CSELR -#define DMA1_CH8_VARIANT __DMA1_CSELR -#define DMA2_CH1_VARIANT __DMA2_CSELR -#define DMA2_CH2_VARIANT __DMA2_CSELR -#define DMA2_CH3_VARIANT __DMA2_CSELR -#define DMA2_CH4_VARIANT __DMA2_CSELR -#define DMA2_CH5_VARIANT __DMA2_CSELR -#define DMA2_CH6_VARIANT __DMA2_CSELR -#define DMA2_CH7_VARIANT __DMA2_CSELR -#define DMA2_CH8_VARIANT __DMA2_CSELR - -#elif AT32_DMA_SUPPORTS_DMAMUX == TRUE +#if AT32_DMA_SUPPORTS_DMAMUX == TRUE #define DMA1MUX_CHANNEL(id) (DMA1MUX_BASE + ((id) * 4U)) #define DMA2MUX_CHANNEL(id) (DMA2MUX_BASE + ((id) * 4U)) @@ -94,7 +65,6 @@ #define DMA1_CH5_VARIANT ((DMAMUX_Channel_TypeDef *)DMA1MUX_CHANNEL(4)) #define DMA1_CH6_VARIANT ((DMAMUX_Channel_TypeDef *)DMA1MUX_CHANNEL(5)) #define DMA1_CH7_VARIANT ((DMAMUX_Channel_TypeDef *)DMA1MUX_CHANNEL(6)) -#define DMA1_CH8_VARIANT ((DMAMUX_Channel_TypeDef *)DMA1MUX_CHANNEL(7)) #define DMA2_CH1_VARIANT ((DMAMUX_Channel_TypeDef *)DMA2MUX_CHANNEL(0)) #define DMA2_CH2_VARIANT ((DMAMUX_Channel_TypeDef *)DMA2MUX_CHANNEL(1)) #define DMA2_CH3_VARIANT ((DMAMUX_Channel_TypeDef *)DMA2MUX_CHANNEL(2)) @@ -102,7 +72,6 @@ #define DMA2_CH5_VARIANT ((DMAMUX_Channel_TypeDef *)DMA2MUX_CHANNEL(4)) #define DMA2_CH6_VARIANT ((DMAMUX_Channel_TypeDef *)DMA2MUX_CHANNEL(5)) #define DMA2_CH7_VARIANT ((DMAMUX_Channel_TypeDef *)DMA2MUX_CHANNEL(6)) -#define DMA2_CH8_VARIANT ((DMAMUX_Channel_TypeDef *)DMA2MUX_CHANNEL(7)) #else /* !(AT32_DMA_SUPPORTS_DMAMUX == TRUE) */ @@ -121,10 +90,10 @@ #define DMA2_CH6_VARIANT 0 #define DMA2_CH7_VARIANT 0 -#endif +#endif /* !(AT32_DMA_SUPPORTS_DMAMUX == TRUE) */ /* - * Default ISR collision masks. + * Default STS collision masks. */ #if !defined(AT32_DMA1_CH1_CMASK) #define AT32_DMA1_CH1_CMASK (1U << 0U) @@ -154,10 +123,6 @@ #define AT32_DMA1_CH7_CMASK (1U << 6U) #endif -#if !defined(AT32_DMA1_CH8_CMASK) -#define AT32_DMA1_CH8_CMASK (1U << 7U) -#endif - #if !defined(AT32_DMA2_CH1_CMASK) #define AT32_DMA2_CH1_CMASK (1U << (AT32_DMA1_NUM_CHANNELS + 0U)) #endif @@ -186,10 +151,6 @@ #define AT32_DMA2_CH7_CMASK (1U << (AT32_DMA1_NUM_CHANNELS + 6U)) #endif -#if !defined(AT32_DMA2_CH8_CMASK) -#define AT32_DMA2_CH8_CMASK (1U << (AT32_DMA1_NUM_CHANNELS + 7U)) -#endif - /*===========================================================================*/ /* Driver exported variables. */ /*===========================================================================*/ @@ -203,52 +164,46 @@ */ const at32_dma_stream_t _at32_dma_streams[AT32_DMA_STREAMS] = { #if AT32_DMA1_NUM_CHANNELS > 0 - {DMA1, DMA1_CHANNEL1, AT32_DMA1_CH1_CMASK, DMA1_CH1_VARIANT, 0, 0, AT32_DMA1_CH1_NUMBER}, + {DMA1, DMA1_Channel1, AT32_DMA1_CH1_CMASK, DMA1_CH1_VARIANT, 0, 0, AT32_DMA1_CH1_NUMBER}, #endif #if AT32_DMA1_NUM_CHANNELS > 1 - {DMA1, DMA1_CHANNEL2, AT32_DMA1_CH2_CMASK, DMA1_CH2_VARIANT, 4, 1, AT32_DMA1_CH2_NUMBER}, + {DMA1, DMA1_Channel2, AT32_DMA1_CH2_CMASK, DMA1_CH2_VARIANT, 4, 1, AT32_DMA1_CH2_NUMBER}, #endif #if AT32_DMA1_NUM_CHANNELS > 2 - {DMA1, DMA1_CHANNEL3, AT32_DMA1_CH3_CMASK, DMA1_CH3_VARIANT, 8, 2, AT32_DMA1_CH3_NUMBER}, + {DMA1, DMA1_Channel3, AT32_DMA1_CH3_CMASK, DMA1_CH3_VARIANT, 8, 2, AT32_DMA1_CH3_NUMBER}, #endif #if AT32_DMA1_NUM_CHANNELS > 3 - {DMA1, DMA1_CHANNEL4, AT32_DMA1_CH4_CMASK, DMA1_CH4_VARIANT, 12, 3, AT32_DMA1_CH4_NUMBER}, + {DMA1, DMA1_Channel4, AT32_DMA1_CH4_CMASK, DMA1_CH4_VARIANT, 12, 3, AT32_DMA1_CH4_NUMBER}, #endif #if AT32_DMA1_NUM_CHANNELS > 4 - {DMA1, DMA1_CHANNEL5, AT32_DMA1_CH5_CMASK, DMA1_CH5_VARIANT, 16, 4, AT32_DMA1_CH5_NUMBER}, + {DMA1, DMA1_Channel5, AT32_DMA1_CH5_CMASK, DMA1_CH5_VARIANT, 16, 4, AT32_DMA1_CH5_NUMBER}, #endif #if AT32_DMA1_NUM_CHANNELS > 5 - {DMA1, DMA1_CHANNEL6, AT32_DMA1_CH6_CMASK, DMA1_CH6_VARIANT, 20, 5, AT32_DMA1_CH6_NUMBER}, + {DMA1, DMA1_Channel6, AT32_DMA1_CH6_CMASK, DMA1_CH6_VARIANT, 20, 5, AT32_DMA1_CH6_NUMBER}, #endif #if AT32_DMA1_NUM_CHANNELS > 6 - {DMA1, DMA1_CHANNEL7, AT32_DMA1_CH7_CMASK, DMA1_CH7_VARIANT, 24, 6, AT32_DMA1_CH7_NUMBER}, -#endif -#if AT32_DMA1_NUM_CHANNELS > 7 - {DMA1, DMA1_CHANNEL8, AT32_DMA1_CH8_CMASK, DMA1_CH8_VARIANT, 28, 7, AT32_DMA1_CH8_NUMBER}, + {DMA1, DMA1_Channel7, AT32_DMA1_CH7_CMASK, DMA1_CH7_VARIANT, 24, 6, AT32_DMA1_CH7_NUMBER}, #endif #if AT32_DMA2_NUM_CHANNELS > 0 - {DMA2, DMA2_CHANNEL1, AT32_DMA2_CH1_CMASK, DMA2_CH1_VARIANT, 0, 0 + AT32_DMA1_NUM_CHANNELS, AT32_DMA2_CH1_NUMBER}, + {DMA2, DMA2_Channel1, AT32_DMA2_CH1_CMASK, DMA2_CH1_VARIANT, 0, 0 + AT32_DMA1_NUM_CHANNELS, AT32_DMA2_CH1_NUMBER}, #endif #if AT32_DMA2_NUM_CHANNELS > 1 - {DMA2, DMA2_CHANNEL2, AT32_DMA2_CH2_CMASK, DMA2_CH2_VARIANT, 4, 1 + AT32_DMA1_NUM_CHANNELS, AT32_DMA2_CH2_NUMBER}, + {DMA2, DMA2_Channel2, AT32_DMA2_CH2_CMASK, DMA2_CH2_VARIANT, 4, 1 + AT32_DMA1_NUM_CHANNELS, AT32_DMA2_CH2_NUMBER}, #endif #if AT32_DMA2_NUM_CHANNELS > 2 - {DMA2, DMA2_CHANNEL3, AT32_DMA2_CH3_CMASK, DMA2_CH3_VARIANT, 8, 2 + AT32_DMA1_NUM_CHANNELS, AT32_DMA2_CH3_NUMBER}, + {DMA2, DMA2_Channel3, AT32_DMA2_CH3_CMASK, DMA2_CH3_VARIANT, 8, 2 + AT32_DMA1_NUM_CHANNELS, AT32_DMA2_CH3_NUMBER}, #endif #if AT32_DMA2_NUM_CHANNELS > 3 - {DMA2, DMA2_CHANNEL4, AT32_DMA2_CH4_CMASK, DMA2_CH4_VARIANT, 12, 3 + AT32_DMA1_NUM_CHANNELS, AT32_DMA2_CH4_NUMBER}, + {DMA2, DMA2_Channel4, AT32_DMA2_CH4_CMASK, DMA2_CH4_VARIANT, 12, 3 + AT32_DMA1_NUM_CHANNELS, AT32_DMA2_CH4_NUMBER}, #endif #if AT32_DMA2_NUM_CHANNELS > 4 - {DMA2, DMA2_CHANNEL5, AT32_DMA2_CH5_CMASK, DMA2_CH5_VARIANT, 16, 4 + AT32_DMA1_NUM_CHANNELS, AT32_DMA2_CH5_NUMBER}, + {DMA2, DMA2_Channel5, AT32_DMA2_CH5_CMASK, DMA2_CH5_VARIANT, 16, 4 + AT32_DMA1_NUM_CHANNELS, AT32_DMA2_CH5_NUMBER}, #endif #if AT32_DMA2_NUM_CHANNELS > 5 - {DMA2, DMA2_CHANNEL6, AT32_DMA2_CH6_CMASK, DMA2_CH6_VARIANT, 20, 5 + AT32_DMA1_NUM_CHANNELS, AT32_DMA2_CH6_NUMBER}, + {DMA2, DMA2_Channel6, AT32_DMA2_CH6_CMASK, DMA2_CH6_VARIANT, 20, 5 + AT32_DMA1_NUM_CHANNELS, AT32_DMA2_CH6_NUMBER}, #endif #if AT32_DMA2_NUM_CHANNELS > 6 - {DMA2, DMA2_CHANNEL7, AT32_DMA2_CH7_CMASK, DMA2_CH7_VARIANT, 24, 6 + AT32_DMA1_NUM_CHANNELS, AT32_DMA2_CH7_NUMBER}, -#endif -#if AT32_DMA2_NUM_CHANNELS > 7 - {DMA2, DMA2_CHANNEL8, AT32_DMA2_CH8_CMASK, DMA2_CH8_VARIANT, 28, 7 + AT32_DMA1_NUM_CHANNELS, AT32_DMA2_CH8_NUMBER}, + {DMA2, DMA2_Channel7, AT32_DMA2_CH7_CMASK, DMA2_CH7_VARIANT, 24, 6 + AT32_DMA1_NUM_CHANNELS, AT32_DMA2_CH7_NUMBER}, #endif }; @@ -263,11 +218,11 @@ static struct { /** * @brief Mask of the allocated streams. */ - uint32_t allocated_mask; + uint32_t allocated_mask; /** - * @brief Mask of the enabled streams ISRs. + * @brief Mask of the enabled streams STSs. */ - uint32_t sts_mask; + uint32_t sts_mask; /** * @brief DMA IRQ redirectors. */ @@ -275,11 +230,11 @@ static struct { /** * @brief DMA callback function. */ - at32_dmasts_t func; + at32_dmasts_t func; /** * @brief DMA callback parameter. */ - void *param; + void *param; } streams[AT32_DMA_STREAMS]; } dma; @@ -293,7 +248,7 @@ static struct { #if defined(AT32_DMA1_CH1_HANDLER) || defined(__DOXYGEN__) /** - * @brief DMA1 stream 1 shared ISR. + * @brief DMA1 stream 1 shared interrupt handler. * * @isr */ @@ -309,7 +264,7 @@ OSAL_IRQ_HANDLER(AT32_DMA1_CH1_HANDLER) { #if defined(AT32_DMA1_CH2_HANDLER) || defined(__DOXYGEN__) /** - * @brief DMA1 stream 2 shared ISR. + * @brief DMA1 stream 2 shared interrupt handler. * * @isr */ @@ -325,7 +280,7 @@ OSAL_IRQ_HANDLER(AT32_DMA1_CH2_HANDLER) { #if defined(AT32_DMA1_CH3_HANDLER) || defined(__DOXYGEN__) /** - * @brief DMA1 stream 3 shared ISR. + * @brief DMA1 stream 3 shared interrupt handler. * * @isr */ @@ -341,7 +296,7 @@ OSAL_IRQ_HANDLER(AT32_DMA1_CH3_HANDLER) { #if defined(AT32_DMA1_CH4_HANDLER) || defined(__DOXYGEN__) /** - * @brief DMA1 stream 4 shared ISR. + * @brief DMA1 stream 4 shared interrupt handler. * * @isr */ @@ -357,7 +312,7 @@ OSAL_IRQ_HANDLER(AT32_DMA1_CH4_HANDLER) { #if defined(AT32_DMA1_CH5_HANDLER) || defined(__DOXYGEN__) /** - * @brief DMA1 stream 5 shared ISR. + * @brief DMA1 stream 5 shared interrupt handler. * * @isr */ @@ -373,7 +328,7 @@ OSAL_IRQ_HANDLER(AT32_DMA1_CH5_HANDLER) { #if defined(AT32_DMA1_CH6_HANDLER) || defined(__DOXYGEN__) /** - * @brief DMA1 stream 6 shared ISR. + * @brief DMA1 stream 6 shared interrupt handler. * * @isr */ @@ -389,7 +344,7 @@ OSAL_IRQ_HANDLER(AT32_DMA1_CH6_HANDLER) { #if defined(AT32_DMA1_CH7_HANDLER) || defined(__DOXYGEN__) /** - * @brief DMA1 stream 7 shared ISR. + * @brief DMA1 stream 7 shared interrupt handler. * * @isr */ @@ -403,25 +358,9 @@ OSAL_IRQ_HANDLER(AT32_DMA1_CH7_HANDLER) { } #endif -#if defined(AT32_DMA1_CH8_HANDLER) || defined(__DOXYGEN__) -/** - * @brief DMA1 stream 8 shared ISR. - * - * @isr - */ -OSAL_IRQ_HANDLER(AT32_DMA1_CH8_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - dmaServeInterrupt(AT32_DMA1_STREAM8); - - OSAL_IRQ_EPILOGUE(); -} -#endif - #if defined(AT32_DMA2_CH1_HANDLER) || defined(__DOXYGEN__) /** - * @brief DMA2 stream 1 shared ISR. + * @brief DMA2 stream 1 shared interrupt handler. * * @isr */ @@ -437,7 +376,7 @@ OSAL_IRQ_HANDLER(AT32_DMA2_CH1_HANDLER) { #if defined(AT32_DMA2_CH2_HANDLER) || defined(__DOXYGEN__) /** - * @brief DMA2 stream 2 shared ISR. + * @brief DMA2 stream 2 shared interrupt handler. * * @isr */ @@ -453,7 +392,7 @@ OSAL_IRQ_HANDLER(AT32_DMA2_CH2_HANDLER) { #if defined(AT32_DMA2_CH3_HANDLER) || defined(__DOXYGEN__) /** - * @brief DMA2 stream 3 shared ISR. + * @brief DMA2 stream 3 shared interrupt handler. * * @isr */ @@ -469,7 +408,7 @@ OSAL_IRQ_HANDLER(AT32_DMA2_CH3_HANDLER) { #if defined(AT32_DMA2_CH4_HANDLER) || defined(__DOXYGEN__) /** - * @brief DMA2 stream 4 shared ISR. + * @brief DMA2 stream 4 shared interrupt handler. * * @isr */ @@ -485,7 +424,7 @@ OSAL_IRQ_HANDLER(AT32_DMA2_CH4_HANDLER) { #if defined(AT32_DMA2_CH5_HANDLER) || defined(__DOXYGEN__) /** - * @brief DMA2 stream 5 shared ISR. + * @brief DMA2 stream 5 shared interrupt handler. * * @isr */ @@ -501,7 +440,7 @@ OSAL_IRQ_HANDLER(AT32_DMA2_CH5_HANDLER) { #if defined(AT32_DMA2_CH6_HANDLER) || defined(__DOXYGEN__) /** - * @brief DMA2 stream 6 shared ISR. + * @brief DMA2 stream 6 shared interrupt handler. * * @isr */ @@ -517,7 +456,7 @@ OSAL_IRQ_HANDLER(AT32_DMA2_CH6_HANDLER) { #if defined(AT32_DMA2_CH7_HANDLER) || defined(__DOXYGEN__) /** - * @brief DMA2 stream 7 shared ISR. + * @brief DMA2 stream 7 shared interrupt handler. * * @isr */ @@ -531,22 +470,6 @@ OSAL_IRQ_HANDLER(AT32_DMA2_CH7_HANDLER) { } #endif -#if defined(AT32_DMA2_CH8_HANDLER) || defined(__DOXYGEN__) -/** - * @brief DMA2 stream 8 shared ISR. - * - * @isr - */ -OSAL_IRQ_HANDLER(AT32_DMA2_CH8_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - - dmaServeInterrupt(AT32_DMA2_STREAM8); - - OSAL_IRQ_EPILOGUE(); -} -#endif - /*===========================================================================*/ /* Driver exported functions. */ /*===========================================================================*/ @@ -562,7 +485,7 @@ void dmaInit(void) { dma.allocated_mask = 0U; dma.sts_mask = 0U; for (i = 0; i < AT32_DMA_STREAMS; i++) { - _at32_dma_streams[i].channel->CTRL = AT32_DMA_CCTRL_RESET_VALUE; + _at32_dma_streams[i].channel->CCTRL = AT32_DMA_CCTRL_RESET_VALUE; dma.streams[i].func = NULL; } DMA1->CLR = 0xFFFFFFFFU; @@ -594,9 +517,9 @@ void dmaInit(void) { * @iclass */ const at32_dma_stream_t *dmaStreamAllocI(uint32_t id, - uint32_t priority, - at32_dmasts_t func, - void *param) { + uint32_t priority, + at32_dmasts_t func, + void *param) { uint32_t i, startid, endid; osalDbgCheckClassI(); @@ -619,8 +542,8 @@ const at32_dma_stream_t *dmaStreamAllocI(uint32_t id, startid = AT32_DMA1_NUM_CHANNELS; endid = AT32_DMA_STREAMS - 1U; } -#endif -#endif +#endif /* AT32_DMA2_NUM_CHANNELS > 0 */ +#endif /* AT32_DMA_SUPPORTS_DMAMUX == TRUE */ else { osalDbgCheck(false); return NULL; @@ -646,18 +569,13 @@ const at32_dma_stream_t *dmaStreamAllocI(uint32_t id, } #endif -#if (AT32_DMA_SUPPORTS_DMAMUX == TRUE) && defined(crmEnableDMAMUX) - /* Enabling DMAMUX if present.*/ - if (dma.allocated_mask != 0U) { - crmEnableDMAMUX(true); - } -#endif #if AT32_DMA_SUPPORTS_DMAMUX == TRUE DMA1->MUXSEL = DMA_MUXSEL_TBL_SEL; #if AT32_DMA2_NUM_CHANNELS > 0 DMA2->MUXSEL = DMA_MUXSEL_TBL_SEL; -#endif -#endif +#endif /* AT32_DMA2_NUM_CHANNELS > 0 */ +#endif /* AT32_DMA_SUPPORTS_DMAMUX == TRUE */ + /* Enables the associated IRQ vector if not already enabled and if a callback is defined.*/ if (func != NULL) { @@ -669,7 +587,7 @@ const at32_dma_stream_t *dmaStreamAllocI(uint32_t id, /* Putting the stream in a known state.*/ dmaStreamDisable(dmastp); - dmastp->channel->CTRL = AT32_DMA_CCTRL_RESET_VALUE; + dmastp->channel->CCTRL = AT32_DMA_CCTRL_RESET_VALUE; return dmastp; } @@ -701,9 +619,9 @@ const at32_dma_stream_t *dmaStreamAllocI(uint32_t id, * @api */ const at32_dma_stream_t *dmaStreamAlloc(uint32_t id, - uint32_t priority, - at32_dmasts_t func, - void *param) { + uint32_t priority, + at32_dmasts_t func, + void *param) { const at32_dma_stream_t *dmastp; osalSysLock(); @@ -754,13 +672,6 @@ void dmaStreamFreeI(const at32_dma_stream_t *dmastp) { crmDisableDMA2(); } #endif - -#if (AT32_DMA_SUPPORTS_DMAMUX == TRUE) && defined(crmDisableDMAMUX) - /* Shutting down DMAMUX if present.*/ - if (dma.allocated_mask == 0U) { - crmDisableDMAMUX(); - } -#endif } /** @@ -792,7 +703,7 @@ void dmaServeInterrupt(const at32_dma_stream_t *dmastp) { uint32_t selfindex = (uint32_t)dmastp->selfindex; flags = (dmastp->dma->STS >> dmastp->shift) & AT32_DMA_STS_MASK; - if (flags & dmastp->channel->CTRL) { + if (flags & dmastp->channel->CCTRL) { dmastp->dma->CLR = flags << dmastp->shift; if (dma.streams[selfindex].func) { dma.streams[selfindex].func(dma.streams[selfindex].param, flags); @@ -803,7 +714,7 @@ void dmaServeInterrupt(const at32_dma_stream_t *dmastp) { #if (AT32_DMA_SUPPORTS_DMAMUX == TRUE) || defined(__DOXYGEN__) /** * @brief Associates a peripheral request to a DMA stream. - * @note This function can be invoked in both ISR or thread context. + * @note This function can be invoked in both STS or thread context. * * @param[in] dmastp pointer to a @p at32_dma_stream_t structure * @param[in] per peripheral identifier @@ -812,9 +723,9 @@ void dmaServeInterrupt(const at32_dma_stream_t *dmastp) { */ void dmaSetRequestSource(const at32_dma_stream_t *dmastp, uint32_t per) { - osalDbgCheck(per < 128U); + osalDbgCheck(per < 256U); - dmastp->mux->MUXCTRL = per; + dmastp->mux->MUXCCTRL = per; } #endif diff --git a/os/hal/ports/AT32/LLD/DMAv2/at32_dma.h b/os/hal/ports/AT32/LLD/DMAv2/at32_dma.h index a695edf645..50636b8d7b 100644 --- a/os/hal/ports/AT32/LLD/DMAv2/at32_dma.h +++ b/os/hal/ports/AT32/LLD/DMAv2/at32_dma.h @@ -1,6 +1,8 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 Maxjta + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + ChibiOS - Copyright (C) 2024..2025 Maxjta Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -18,8 +20,6 @@ /** * @file DMAv2/at32_dma.h * @brief DMA helper driver header. - * @note This driver uses the new naming convention used for the AT32F4xx - * so the "DMA channels" are referred as "DMA streams". * * @addtogroup AT32_DMA * @{ @@ -32,42 +32,29 @@ /* Driver constants. */ /*===========================================================================*/ -/** - * @brief Requires use of DMAv2 driver model. - */ -#define AT32_USE_DMA_V2 TRUE - /** * @brief DMA capability. * @details if @p TRUE then the DMA is able of burst transfers, FIFOs, * scatter gather and other advanced features. */ -#define AT32_DMA_ADVANCED FALSE +#define AT32_DMA_ADVANCED FALSE /** - * @brief Total number of DMA streams. - * @details This is the total number of streams among all the DMA units. + * @brief Maximum number of transfers in a single operation. */ -#define AT32_DMA_STREAMS (AT32_DMA1_NUM_CHANNELS + \ - AT32_DMA2_NUM_CHANNELS) +#define AT32_DMA_MAX_TRANSFER 65535 /** - * @brief Mask of the ISR bits passed to the DMA callback functions. + * @brief Total number of DMA streams. + * @details This is the total number of streams among all the DMA units. */ -#define AT32_DMA_STS_MASK 0x0E +#define AT32_DMA_STREAMS (AT32_DMA1_NUM_CHANNELS + \ + AT32_DMA2_NUM_CHANNELS) /** - * @brief Returns the request line associated to the specified stream. - * @note In some AT32 manuals the request line is named confusingly - * channel. - * - * @param[in] id the unique numeric stream identifier - * @param[in] c a stream/request association word, one request per - * nibble - * @return Returns the request associated to the stream. + * @brief Mask of the STS bits passed to the DMA callback functions. */ -#define AT32_DMA_GETCHANNEL(id, c) \ - (((uint32_t)(c) >> (((uint32_t)(id) % (uint32_t)AT32_DMA1_NUM_CHANNELS) * 4U)) & 15U) +#define AT32_DMA_STS_MASK 0x0E /** * @brief Checks if a DMA priority is within the valid range. @@ -88,14 +75,14 @@ * @retval false invalid DMA channel. * @retval true correct DMA channel. */ -#define AT32_DMA_IS_VALID_STREAM(id) (((id) >= 0U) && \ +#define AT32_DMA_IS_VALID_STREAM(id) (((id) >= 0U) && \ ((id) < AT32_DMA_STREAMS)) #else /* AT32_DMA_SUPPORTS_DMAMUX == FALSE */ #if AT32_DMA2_NUM_CHANNELS > 0 -#define AT32_DMA_IS_VALID_STREAM(id) (((id) >= 0U) && \ +#define AT32_DMA_IS_VALID_STREAM(id) (((id) >= 0U) && \ ((id) <= (AT32_DMA_STREAMS + 2))) #else -#define AT32_DMA_IS_VALID_STREAM(id) (((id) >= 0U) && \ +#define AT32_DMA_IS_VALID_STREAM(id) (((id) >= 0U) && \ ((id) <= (AT32_DMA_STREAMS + 1))) #endif #endif /* AT32_DMA_SUPPORTS_DMAMUX == FALSE */ @@ -107,32 +94,9 @@ * @param[in] stream the stream number * @return An unique numeric stream identifier. */ -#define AT32_DMA_STREAM_ID(dma, stream) \ +#define AT32_DMA_STREAM_ID(dma, stream) \ ((((dma) - 1) * AT32_DMA1_NUM_CHANNELS) + ((stream) - 1)) -/** - * @brief Returns a DMA stream identifier mask. - * - * - * @param[in] dma the DMA unit number - * @param[in] stream the stream number - * @return A DMA stream identifier mask. - */ -#define AT32_DMA_STREAM_ID_MSK(dma, stream) \ - (1U << AT32_DMA_STREAM_ID(dma, stream)) - -/** - * @brief Checks if a DMA stream unique identifier belongs to a mask. - * - * @param[in] id the stream numeric identifier - * @param[in] mask the stream numeric identifiers mask - * - * @retval The check result. - * @retval false id does not belong to the mask. - * @retval true id belongs to the mask. - */ -#define AT32_DMA_IS_VALID_ID(id, mask) (((1U << (id)) & (mask))) - #if (AT32_DMA_SUPPORTS_DMAMUX == TRUE) || defined(_DOXYGEN__) /** * @name Special stream identifiers @@ -180,9 +144,6 @@ #if AT32_DMA1_NUM_CHANNELS > 6 #define AT32_DMA1_STREAM7 AT32_DMA_STREAM(6) #endif -#if AT32_DMA1_NUM_CHANNELS > 7 -#define AT32_DMA1_STREAM8 AT32_DMA_STREAM(7) -#endif #if AT32_DMA2_NUM_CHANNELS > 0 #define AT32_DMA2_STREAM1 AT32_DMA_STREAM(AT32_DMA1_NUM_CHANNELS + 0) #endif @@ -204,95 +165,45 @@ #if AT32_DMA2_NUM_CHANNELS > 6 #define AT32_DMA2_STREAM7 AT32_DMA_STREAM(AT32_DMA1_NUM_CHANNELS + 6) #endif -#if AT32_DMA2_NUM_CHANNELS > 7 -#define AT32_DMA2_STREAM8 AT32_DMA_STREAM(AT32_DMA1_NUM_CHANNELS + 7) -#endif /** @} */ /** - * @name CTRL register constants common to all DMA types + * @name CCTRL register constants common to all DMA types * @{ */ -#define AT32_DMA_CCTRL_RESET_VALUE 0x00000000U -#define AT32_DMA_CTRL_CHEN DMA_CTRL_CHEN -#define AT32_DMA_CTRL_DTERRIEN DMA_CTRL_DTERRIEN -#define AT32_DMA_CTRL_HDTIEN DMA_CTRL_HDTIEN -#define AT32_DMA_CTRL_FDTIEN DMA_CTRL_FDTIEN -#define AT32_DMA_CTRL_DTD_MASK (DMA_CTRL_DTD | DMA_CTRL_M2M) -#define AT32_DMA_CTRL_DTD_P2M 0U -#define AT32_DMA_CTRL_DTD_M2P DMA_CTRL_DTD -#define AT32_DMA_CTRL_DTD_M2M DMA_CTRL_M2M -#define AT32_DMA_CTRL_LM DMA_CTRL_LM -#define AT32_DMA_CTRL_PINCM DMA_CTRL_PINCM -#define AT32_DMA_CTRL_MINCM DMA_CTRL_MINCM -#define AT32_DMA_CTRL_PWIDTH_MASK DMA_CTRL_PWIDTH -#define AT32_DMA_CTRL_PWIDTH_BYTE 0U -#define AT32_DMA_CTRL_PWIDTH_HWORD DMA_CTRL_PWIDTH_16BITS -#define AT32_DMA_CTRL_PWIDTH_WORD DMA_CTRL_PWIDTH_32BITS -#define AT32_DMA_CTRL_MWIDTH_MASK DMA_CTRL_MWIDTH -#define AT32_DMA_CTRL_MWIDTH_BYTE 0U -#define AT32_DMA_CTRL_MWIDTH_HWORD DMA_CTRL_MWIDTH_16BITS -#define AT32_DMA_CTRL_MWIDTH_WORD DMA_CTRL_MWIDTH_32BITS -#define AT32_DMA_CTRL_WIDTH_MASK (AT32_DMA_CTRL_PWIDTH_MASK | \ - AT32_DMA_CTRL_MWIDTH_MASK) -#define AT32_DMA_CTRL_CHPL_MASK DMA_CTRL_CHPL -#define AT32_DMA_CTRL_CHPL(n) ((n) << 12U) - #define AT32_DMA_CCTRL_RESET_VALUE 0x00000000U -#define AT32_DMA_CCTRL_CHEN DMA_CTRL_CHEN -#define AT32_DMA_CCTRL_DTERRIEN DMA_CTRL_DTERRIEN -#define AT32_DMA_CCTRL_HDTIEN DMA_CTRL_HDTIEN -#define AT32_DMA_CCTRL_FDTIEN DMA_CTRL_FDTIEN -#define AT32_DMA_CCTRL_DTD_MASK (DMA_CTRL_DTD | DMA_CCTRL_M2M) +#define AT32_DMA_CCTRL_CHEN DMA_CCTRL_CHEN +#define AT32_DMA_CCTRL_DTERRIEN DMA_CCTRL_DTERRIEN +#define AT32_DMA_CCTRL_HDTIEN DMA_CCTRL_HDTIEN +#define AT32_DMA_CCTRL_FDTIEN DMA_CCTRL_FDTIEN +#define AT32_DMA_CCTRL_DTD_MASK (DMA_CCTRL_DTD | DMA_CCTRL_M2M) #define AT32_DMA_CCTRL_DTD_P2M 0U -#define AT32_DMA_CCTRL_DTD_M2P DMA_CTRL_DTD -#define AT32_DMA_CCTRL_DTD_M2M DMA_CTRL_M2M -#define AT32_DMA_CCTRL_LM DMA_CTRL_LM -#define AT32_DMA_CCTRL_PINCM DMA_CTRL_PINCM -#define AT32_DMA_CCTRL_MINCM DMA_CTRL_MINCM -#define AT32_DMA_CCTRL_PWIDTH_MASK DMA_CTRL_PWIDTH +#define AT32_DMA_CCTRL_DTD_M2P DMA_CCTRL_DTD +#define AT32_DMA_CCTRL_DTD_M2M DMA_CCTRL_M2M +#define AT32_DMA_CCTRL_LM DMA_CCTRL_LM +#define AT32_DMA_CCTRL_PINCM DMA_CCTRL_PINCM +#define AT32_DMA_CCTRL_MINCM DMA_CCTRL_MINCM +#define AT32_DMA_CCTRL_PWIDTH_MASK DMA_CCTRL_PWIDTH #define AT32_DMA_CCTRL_PWIDTH_BYTE 0U -#define AT32_DMA_CCTRL_PWIDTH_HWORD DMA_CTRL_PWIDTH_16BITS -#define AT32_DMA_CCTRL_PWIDTH_WORD DMA_CTRL_PWIDTH_32BITS +#define AT32_DMA_CCTRL_PWIDTH_HWORD DMA_CCTRL_PWIDTH_0 +#define AT32_DMA_CCTRL_PWIDTH_WORD DMA_CCTRL_PWIDTH_1 #define AT32_DMA_CCTRL_MWIDTH_MASK DMA_CCTRL_MWIDTH #define AT32_DMA_CCTRL_MWIDTH_BYTE 0U -#define AT32_DMA_CCTRL_MWIDTH_HWORD DMA_CTRL_MWIDTH_16BITS -#define AT32_DMA_CCTRL_MWIDTH_WORD DMA_CTRL_MWIDTH_32BITS -#define AT32_DMA_CCTRL_SIZE_MASK (AT32_DMA_CTRL_PWIDTH_MASK | \ - AT32_DMA_CTRL_MWIDTH_MASK) -#define AT32_DMA_CCTRL_CHPL_MASK DMA_CTRL_CHPL +#define AT32_DMA_CCTRL_MWIDTH_HWORD DMA_CCTRL_MWIDTH_0 +#define AT32_DMA_CCTRL_MWIDTH_WORD DMA_CCTRL_MWIDTH_1 +#define AT32_DMA_CCTRL_SIZE_MASK (AT32_DMA_CCTRL_PWIDTH_MASK | \ + AT32_DMA_CCTRL_MWIDTH_MASK) +#define AT32_DMA_CCTRL_CHPL_MASK DMA_CCTRL_CHPL #define AT32_DMA_CCTRL_CHPL(n) ((n) << 12U) /** @} */ /** - * @name Request line selector macro + * @name Status flags passed to the STS callbacks * @{ */ -#if AT32_DMA_SUPPORTS_CSELR || defined(__DOXYGEN__) -#define AT32_DMA_CTRL_CHSEL_MASK (15U << 16U) -#define AT32_DMA_CTRL_CHSEL(n) ((n) << 16U) -#else -#define AT32_DMA_CTRL_CHSEL_MASK 0U -#define AT32_DMA_CTRL_CHSEL(n) 0U -#endif -/** @} */ - -/** - * @name CTRL register constants only found in enhanced DMA - * @{ - */ -#define AT32_DMA_CTRL_DMERRIEN 0U /**< @brief Ignored by normal DMA. */ -/** @} */ - -/** - * @name Status flags passed to the ISR callbacks - * @{ - */ -#define AT32_DMA_STS_FERRF 0U -#define AT32_DMA_STS_DMERRF 0U -#define AT32_DMA_STS_DTERRF (0x1U << 3) -#define AT32_DMA_STS_HDTF (0x1U << 2) -#define AT32_DMA_STS_FDTF (0x1U << 1) +#define AT32_DMA_STS_DTERRF DMA_STS_DTERRF1 +#define AT32_DMA_STS_HDTF DMA_STS_HDTF1 +#define AT32_DMA_STS_FDTF DMA_STS_FDTF1 /** @} */ /*===========================================================================*/ @@ -307,14 +218,6 @@ #error "AT32_DMA_SUPPORTS_DMAMUX not defined in registry" #endif -#if !defined(AT32_DMA_SUPPORTS_CSELR) -#error "AT32_DMA_SUPPORTS_CSELR not defined in registry" -#endif - -#if AT32_DMA_SUPPORTS_DMAMUX && AT32_DMA_SUPPORTS_CSELR -#error "AT32_DMA_SUPPORTS_DMAMUX and AT32_DMA_SUPPORTS_CSELR both TRUE" -#endif - #if !defined(AT32_DMA1_NUM_CHANNELS) #error "AT32_DMA1_NUM_CHANNELS not defined in registry" #endif @@ -323,11 +226,11 @@ #error "AT32_DMA2_NUM_CHANNELS not defined in registry" #endif -#if (AT32_DMA1_NUM_CHANNELS < 0) || (AT32_DMA1_NUM_CHANNELS > 8) +#if (AT32_DMA1_NUM_CHANNELS < 0) || (AT32_DMA1_NUM_CHANNELS > 7) #error "unsupported channels configuration" #endif -#if (AT32_DMA2_NUM_CHANNELS < 0) || (AT32_DMA2_NUM_CHANNELS > 8) +#if (AT32_DMA2_NUM_CHANNELS < 0) || (AT32_DMA2_NUM_CHANNELS > 7) #error "unsupported channels configuration" #endif @@ -352,21 +255,18 @@ typedef void (*at32_dmasts_t)(void *p, uint32_t flags); * @brief AT32 DMA stream descriptor structure. */ typedef struct { - DMA_TypeDef *dma; /**< @brief Associated DMA. */ - DMA_Channel_TypeDef *channel; /**< @brief Associated DMA channel. */ - uint32_t cmask; /**< @brief Mask of streams sharing - the same ISR. */ -#if (AT32_DMA_SUPPORTS_CSELR == TRUE) || defined(__DOXYGEN__) - volatile uint32_t *cselr; /**< @brief Associated CSELR reg. */ -#elif AT32_DMA_SUPPORTS_DMAMUX == TRUE - DMAMUX_Channel_TypeDef *mux; /**< @brief Associated DMA mux. */ + DMA_TypeDef *dma; /**< @brief Associated DMA. */ + DMA_Channel_TypeDef *channel; /**< @brief Associated DMA channel. */ + uint32_t cmask; /**< @brief Mask of streams sharing + the same STS. */ +#if (AT32_DMA_SUPPORTS_DMAMUX == TRUE) || defined(__DOXYGEN__) + DMAMUX_Channel_TypeDef *mux; /**< @brief Associated DMA mux. */ #else - uint8_t dummy; /**< @brief Filler. */ + uint8_t dummy; /**< @brief Filler. */ #endif - uint8_t shift; /**< @brief Bit offset in STS, CLR - and CSELR registers. */ - uint8_t selfindex; /**< @brief Index to self in array. */ - uint8_t vector; /**< @brief Associated IRQ vector. */ + uint8_t shift; /**< @brief Bit offset in STS, CLR */ + uint8_t selfindex; /**< @brief Index to self in array. */ + uint8_t vector; /**< @brief Associated IRQ vector. */ } at32_dma_stream_t; /*===========================================================================*/ @@ -384,12 +284,12 @@ typedef struct { * @post After use the stream can be released using @p dmaStreamRelease(). * * @param[in] dmastp pointer to a at32_dma_stream_t structure - * @param[in] addr value to be written in the PADDR register + * @param[in] addr value to be written in the CPADDR register * * @special */ #define dmaStreamSetPeripheral(dmastp, addr) { \ - (dmastp)->channel->PADDR = (uint32_t)(addr); \ + (dmastp)->channel->CPADDR = (uint32_t)(addr); \ } /** @@ -399,12 +299,12 @@ typedef struct { * @post After use the stream can be released using @p dmaStreamRelease(). * * @param[in] dmastp pointer to a at32_dma_stream_t structure - * @param[in] addr value to be written in the MADDR register + * @param[in] addr value to be written in the CMADDR register * * @special */ #define dmaStreamSetMemory0(dmastp, addr) { \ - (dmastp)->channel->MADDR = (uint32_t)(addr); \ + (dmastp)->channel->CMADDR = (uint32_t)(addr); \ } /** @@ -414,12 +314,12 @@ typedef struct { * @post After use the stream can be released using @p dmaStreamRelease(). * * @param[in] dmastp pointer to a at32_dma_stream_t structure - * @param[in] size value to be written in the DTCNT register + * @param[in] size value to be written in the CDTCNT register * * @special */ #define dmaStreamSetTransactionSize(dmastp, size) { \ - (dmastp)->channel->DTCNT = (uint32_t)(size); \ + (dmastp)->channel->CDTCNT = (uint32_t)(size); \ } /** @@ -433,7 +333,7 @@ typedef struct { * * @special */ -#define dmaStreamGetTransactionSize(dmastp) ((size_t)((dmastp)->channel->DTCNT)) +#define dmaStreamGetTransactionSize(dmastp) ((size_t)((dmastp)->channel->CDTCNT)) /** * @brief Programs the stream mode settings. @@ -442,23 +342,13 @@ typedef struct { * @post After use the stream can be released using @p dmaStreamRelease(). * * @param[in] dmastp pointer to a at32_dma_stream_t structure - * @param[in] mode value to be written in the CCR register + * @param[in] mode value to be written in the CCTRL register * * @special */ -#if AT32_DMA_SUPPORTS_CSELR || defined(__DOXYGEN__) #define dmaStreamSetMode(dmastp, mode) { \ - uint32_t cselr = *(dmastp)->cselr; \ - cselr &= ~(0x0000000FU << (dmastp)->shift); \ - cselr |= (((uint32_t)(mode) >> 16U) << (dmastp)->shift); \ - *(dmastp)->cselr = cselr; \ - (dmastp)->channel->CTRL = (uint32_t)(mode); \ + (dmastp)->channel->CCTRL = (uint32_t)(mode); \ } -#else -#define dmaStreamSetMode(dmastp, mode) { \ - (dmastp)->channel->CTRL = (uint32_t)(mode); \ -} -#endif /** * @brief DMA stream enable. @@ -471,7 +361,7 @@ typedef struct { * @special */ #define dmaStreamEnable(dmastp) { \ - (dmastp)->channel->CTRL |= AT32_DMA_CTRL_CHEN; \ + (dmastp)->channel->CCTRL |= AT32_DMA_CCTRL_CHEN; \ } /** @@ -488,10 +378,12 @@ typedef struct { * * @special */ -#define dmaStreamDisable(dmastp) { \ - (dmastp)->channel->CTRL &= ~(AT32_DMA_CTRL_FDTIEN | AT32_DMA_CTRL_HDTIEN | \ - AT32_DMA_CTRL_DTERRIEN | AT32_DMA_CTRL_CHEN); \ - dmaStreamClearInterrupt(dmastp); \ +#define dmaStreamDisable(dmastp) { \ + (dmastp)->channel->CCTRL &= ~(AT32_DMA_CCTRL_FDTIEN | \ + AT32_DMA_CCTRL_HDTIEN | \ + AT32_DMA_CCTRL_DTERRIEN | \ + AT32_DMA_CCTRL_CHEN); \ + dmaStreamClearInterrupt(dmastp); \ } /** @@ -504,8 +396,8 @@ typedef struct { * * @special */ -#define dmaStreamClearInterrupt(dmastp) { \ - (dmastp)->dma->CLR = AT32_DMA_STS_MASK << (dmastp)->shift; \ +#define dmaStreamClearInterrupt(dmastp) { \ + (dmastp)->dma->CLR = AT32_DMA_STS_MASK << (dmastp)->shift; \ } /** @@ -516,12 +408,12 @@ typedef struct { * @post After use the stream can be released using @p dmaStreamRelease(). * * @param[in] dmastp pointer to a at32_dma_stream_t structure - * @param[in] mode value to be written in the CCR register, this value + * @param[in] mode value to be written in the CCTRL register, this value * is implicitly ORed with: - * - @p AT32_DMA_CTRL_MINCM - * - @p AT32_DMA_CTRL_PINCM - * - @p AT32_DMA_CTRL_DTD_M2M - * - @p AT32_DMA_CTRL_CHEN + * - @p AT32_DMA_CCTRL_MINCM + * - @p AT32_DMA_CCTRL_PINCM + * - @p AT32_DMA_CCTRL_DTD_M2M + * - @p AT32_DMA_CCTRL_CHEN * . * @param[in] src source address * @param[in] dst destination address @@ -532,8 +424,8 @@ typedef struct { dmaStreamSetMemory0(dmastp, dst); \ dmaStreamSetTransactionSize(dmastp, n); \ dmaStreamSetMode(dmastp, (mode) | \ - AT32_DMA_CTRL_MINCM | AT32_DMA_CTRL_PINCM | \ - AT32_DMA_CTRL_DTD_M2M | AT32_DMA_CTRL_CHEN); \ + AT32_DMA_CCTRL_MINCM | AT32_DMA_CCTRL_PINCM | \ + AT32_DMA_CCTRL_DTD_M2M | AT32_DMA_CCTRL_CHEN); \ } /** @@ -544,7 +436,7 @@ typedef struct { * @param[in] dmastp pointer to a at32_dma_stream_t structure */ #define dmaWaitCompletion(dmastp) { \ - while ((dmastp)->channel->DTCNT > 0U) \ + while ((dmastp)->channel->CDTCNT > 0U) \ ; \ dmaStreamDisable(dmastp); \ } @@ -563,13 +455,13 @@ extern "C" { #endif void dmaInit(void); const at32_dma_stream_t *dmaStreamAllocI(uint32_t id, + uint32_t priority, + at32_dmasts_t func, + void *param); + const at32_dma_stream_t *dmaStreamAlloc(uint32_t id, uint32_t priority, at32_dmasts_t func, void *param); - const at32_dma_stream_t *dmaStreamAlloc(uint32_t id, - uint32_t priority, - at32_dmasts_t func, - void *param); void dmaStreamFreeI(const at32_dma_stream_t *dmastp); void dmaStreamFree(const at32_dma_stream_t *dmastp); void dmaServeInterrupt(const at32_dma_stream_t *dmastp); diff --git a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint.c b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint.c index 562d860d33..581599704e 100644 --- a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint.c +++ b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint.c @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint.h b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint.h index 95c2e2037d..5d1d63740b 100644 --- a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint.h +++ b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint.h @@ -1,7 +1,8 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + ChibiOS - Copyright (C) 2024..2025 Maxjta Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -112,11 +113,11 @@ typedef uint32_t exintmode_t; * @special */ #define exintGetAndClearGroup1(mask, out) do { \ - uint32_t intsts1; \ + uint32_t intsts1; \ \ - intsts1 = EXINT->INTSTS & (mask); \ - (out) = intsts1; \ - EXINT->INTSTS = intsts1; \ + intsts1 = EXINT->INTSTS & (mask); \ + (out) = intsts1; \ + EXINT->INTSTS = intsts1; \ } while (false) /*===========================================================================*/ diff --git a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint0.inc b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint0.inc index 8b66e3fa46..8509e2bc4d 100644 --- a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint0.inc +++ b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint0.inc @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint1.inc b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint1.inc index cad5ad33b9..55db776410 100644 --- a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint1.inc +++ b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint1.inc @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint10_15.inc b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint10_15.inc index 222415d510..187575e32e 100644 --- a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint10_15.inc +++ b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint10_15.inc @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint16.inc b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint16.inc index 9c0b7db12f..d70fc0930b 100644 --- a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint16.inc +++ b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint16.inc @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint17.inc b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint17.inc index 9d6d39e6bb..3db10d47d2 100644 --- a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint17.inc +++ b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint17.inc @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint18.inc b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint18.inc index 644488de5b..2958493188 100644 --- a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint18.inc +++ b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint18.inc @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint19.inc b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint19.inc index f6ccd70063..410d23a19e 100644 --- a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint19.inc +++ b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint19.inc @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint2.inc b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint2.inc index 43caec1e48..910b811a77 100644 --- a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint2.inc +++ b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint2.inc @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint20.inc b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint20.inc index 6eaef17174..9bb9836c74 100644 --- a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint20.inc +++ b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint20.inc @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint21.inc b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint21.inc index 2f3e1ee21b..1ebe7cc30c 100644 --- a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint21.inc +++ b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint21.inc @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint22.inc b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint22.inc index b202b57e57..50a0ab2667 100644 --- a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint22.inc +++ b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint22.inc @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint3.inc b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint3.inc index 883d82bc7b..ff94c82ec5 100644 --- a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint3.inc +++ b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint3.inc @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint4.inc b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint4.inc index 3388a97493..c85f6d11d4 100644 --- a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint4.inc +++ b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint4.inc @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint5_9.inc b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint5_9.inc index 56cc2b499b..e3d41d79e3 100644 --- a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint5_9.inc +++ b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint5_9.inc @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/GPIOv1/hal_pal_lld.c b/os/hal/ports/AT32/LLD/GPIOv1/hal_pal_lld.c index 6a70cb35f4..0cc258742b 100644 --- a/os/hal/ports/AT32/LLD/GPIOv1/hal_pal_lld.c +++ b/os/hal/ports/AT32/LLD/GPIOv1/hal_pal_lld.c @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/GPIOv1/hal_pal_lld.h b/os/hal/ports/AT32/LLD/GPIOv1/hal_pal_lld.h index 5b4965c0cd..125d3551d1 100644 --- a/os/hal/ports/AT32/LLD/GPIOv1/hal_pal_lld.h +++ b/os/hal/ports/AT32/LLD/GPIOv1/hal_pal_lld.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/GPIOv2/at32_gpio.h b/os/hal/ports/AT32/LLD/GPIOv2/at32_gpio.h index 99f905c661..fa4ddac1a6 100644 --- a/os/hal/ports/AT32/LLD/GPIOv2/at32_gpio.h +++ b/os/hal/ports/AT32/LLD/GPIOv2/at32_gpio.h @@ -1,6 +1,8 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2024 Maxjta + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + ChibiOS - Copyright (C) 2024..2025 Maxjta Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -18,7 +20,7 @@ /** * @file GPIOv2/at32_gpio.h * @brief AT32 GPIO units common header. - * @note This file requires definitions from the AT32 header file. + * @note This file requires definitions from the Artery AT32 header file. * * @addtogroup AT32_GPIOv2 * @{ @@ -43,9 +45,6 @@ #undef GPIOF #undef GPIOG #undef GPIOH -#undef GPIOI -#undef GPIOJ -#undef GPIOK /** * @name GPIO ports definitions @@ -57,21 +56,8 @@ #define GPIOD ((at32_gpio_t *)GPIOD_BASE) #define GPIOE ((at32_gpio_t *)GPIOE_BASE) #define GPIOF ((at32_gpio_t *)GPIOF_BASE) -#if AT32_HAS_GPIOG #define GPIOG ((at32_gpio_t *)GPIOG_BASE) -#endif -#if AT32_HAS_GPIOH #define GPIOH ((at32_gpio_t *)GPIOH_BASE) -#endif -#if AT32_HAS_GPIOI -#define GPIOI ((at32_gpio_t *)GPIOI_BASE) -#endif -#if AT32_HAS_GPIOJ -#define GPIOJ ((at32_gpio_t *)GPIOJ_BASE) -#endif -#if AT32_HAS_GPIOK -#define GPIOK ((at32_gpio_t *)GPIOK_BASE) -#endif /** @} */ /*===========================================================================*/ @@ -91,26 +77,26 @@ */ typedef struct { - volatile uint32_t CFGR; - volatile uint32_t OMODE; - volatile uint32_t ODRVR; - volatile uint32_t PULL; - volatile uint32_t IDT; - volatile uint32_t ODT; + volatile uint32_t CFGR; + volatile uint32_t OMODE; + volatile uint32_t ODRVR; + volatile uint32_t PULL; + volatile uint32_t IDT; + volatile uint32_t ODT; volatile union { - uint32_t W; + uint32_t W; struct { - uint16_t set; - uint16_t clear; + uint16_t set; + uint16_t clear; } H; } SCR; - volatile uint32_t WPR; - volatile uint32_t MUXL; - volatile uint32_t MUXH; - volatile uint32_t CLR; - volatile uint32_t TOGR; - volatile uint32_t resvd30[3]; - volatile uint32_t HDRV; + volatile uint32_t WPR; + volatile uint32_t MUXL; + volatile uint32_t MUXH; + volatile uint32_t CLR; + volatile uint32_t TOGR; + volatile uint32_t RESERVED[3]; + volatile uint32_t HDRV; } at32_gpio_t; /*===========================================================================*/ diff --git a/os/hal/ports/AT32/LLD/GPIOv2/hal_pal_lld.c b/os/hal/ports/AT32/LLD/GPIOv2/hal_pal_lld.c index 7415a5376a..20d20535ea 100644 --- a/os/hal/ports/AT32/LLD/GPIOv2/hal_pal_lld.c +++ b/os/hal/ports/AT32/LLD/GPIOv2/hal_pal_lld.c @@ -1,6 +1,8 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2024 Maxjta + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + ChibiOS - Copyright (C) 2024..2025 Maxjta Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -72,7 +74,6 @@ void _pal_lld_init(void) { _pal_init_event(i); } #endif - crmEnableAHB1(AT32_GPIO_EN_MASK, false); } /** @@ -92,43 +93,43 @@ void _pal_lld_setgroupmode(ioportid_t port, ioportmask_t mask, iomode_t mode) { - uint32_t cfgr = (mode & PAL_AT32_MODE_MASK) >> 0; - uint32_t omode = (mode & PAL_AT32_OMODE_MASK) >> 2; - uint32_t odrvr = (mode & PAL_AT32_ODRV_MASK) >> 3; - uint32_t pull = (mode & PAL_AT32_PULL_MASK) >> 5; - uint32_t muxr = (mode & PAL_AT32_ALTERNATE_MASK) >> 7; - uint32_t hdrv = (mode & PAL_AT32_HDRV_MASK) >> 11; - uint32_t bit = 0; + uint32_t cfgr = (mode & PAL_AT32_MODE_MASK) >> 0; + uint32_t omode = (mode & PAL_AT32_OMODE_MASK) >> 2; + uint32_t odrvr = (mode & PAL_AT32_ODRVR_MASK) >> 3; + uint32_t pull = (mode & PAL_AT32_PULL_MASK) >> 5; + uint32_t mux = (mode & PAL_AT32_MUX_MASK) >> 7; + uint32_t hdrv = (mode & PAL_AT32_HDRV_MASK) >> 11; + uint32_t bit = 0; while (true) { if ((mask & 1) != 0) { - uint32_t muxrmask, m1, m2, m4; + uint32_t muxmask, m1, m2, m4; - muxrmask = muxr << ((bit & 7) * 4); + muxmask = mux << ((bit & 7) * 4); m1 = 1 << bit; m2 = 3 << (bit * 2); m4 = 15 << ((bit & 7) * 4); - port->OMODE = (port->OMODE & ~m1) | omode; - port->ODRVR = (port->ODRVR & ~m2) | odrvr; - port->PULL = (port->PULL & ~m2) | pull; - port->HDRV = (port->HDRV & ~m1) | hdrv; - if ((mode & PAL_AT32_MODE_MASK) == PAL_AT32_MODE_ALTERNATE) { - /* If going in alternate mode then the alternate number is set + port->OMODE = (port->OMODE & ~m1) | omode; + port->ODRVR = (port->ODRVR & ~m2) | odrvr; + port->PULL = (port->PULL & ~m2) | pull; + port->HDRV = (port->HDRV & ~m1) | hdrv; + if ((mode & PAL_AT32_MODE_MASK) == PAL_AT32_MODE_MUX) { + /* If going in multiplexing mode then the multiplexing number is set before switching mode in order to avoid glitches.*/ if (bit < 8) - port->MUXL = (port->MUXL & ~m4) | muxrmask; + port->MUXL = (port->MUXL & ~m4) | muxmask; else - port->MUXH = (port->MUXH & ~m4) | muxrmask; + port->MUXH = (port->MUXH & ~m4) | muxmask; port->CFGR = (port->CFGR & ~m2) | cfgr; } else { - /* If going into a non-alternate mode then the mode is switched - before setting the alternate mode in order to avoid glitches.*/ + /* If going into a non-multiplexing mode then the mode is switched + before setting the multiplexing mode in order to avoid glitches.*/ port->CFGR = (port->CFGR & ~m2) | cfgr; if (bit < 8) - port->MUXL = (port->MUXL & ~m4) | muxrmask; + port->MUXL = (port->MUXL & ~m4) | muxmask; else - port->MUXH = (port->MUXH & ~m4) | muxrmask; + port->MUXH = (port->MUXH & ~m4) | muxmask; } } mask >>= 1; @@ -157,10 +158,7 @@ void _pal_lld_enablepadevent(ioportid_t port, iopadid_t pad, ioeventmode_t mode) { - uint32_t padmask, cidx, coff, cmask, portidx; - - /* Enable SCFG clock. */ - crmEnableSCFG(false); + uint32_t padmask, cridx, croff, crmask, portidx; /* Mask of the pad.*/ padmask = 1U << (uint32_t)pad; @@ -176,10 +174,10 @@ void _pal_lld_enablepadevent(ioportid_t port, portidx = (((uint32_t)port - (uint32_t)GPIOA) >> 10U) & 0xFU; /* Index and mask of the EXINTC register to be used.*/ - cidx = (uint32_t)pad >> 2U; - coff = ((uint32_t)pad & 3U) * 4U; - cmask = ~(0xFU << coff); - SCFG->EXINTC[cidx] = (SCFG->EXINTC[cidx] & cmask) | (portidx << coff); + cridx = (uint32_t)pad >> 2U; + croff = ((uint32_t)pad & 3U) * 4U; + crmask = ~(0xFU << croff); + SCFG->EXINTC[cridx] = (SCFG->EXINTC[cridx] & crmask) | (portidx << croff); /* Programming edge registers.*/ if (mode & PAL_EVENT_MODE_RISING_EDGE) @@ -214,20 +212,20 @@ void _pal_lld_disablepadevent(ioportid_t port, iopadid_t pad) { /* Mask of the pad.*/ padmask = 1U << (uint32_t)pad; - /* If either RTRS1 or POLCFG2 is enabled then the channel is in use.*/ + /* If either POLCFG1 or POLCFG2 is enabled then the channel is in use.*/ if (((polcfg1 | polcfg2) & padmask) != 0U) { - uint32_t cidx, coff, cport, portidx; + uint32_t cridx, croff, crport, portidx; /* Port index is obtained assuming that GPIO ports are placed at regular 0x400 intervals in memory space. So far this is true for all devices.*/ portidx = (((uint32_t)port - (uint32_t)GPIOA) >> 10U) & 0xFU; /* Index and mask of the EXINTC register to be used.*/ - cidx = (uint32_t)pad >> 2U; - coff = ((uint32_t)pad & 3U) * 4U; - cport = (SCFG->EXINTC[cidx] >> coff) & 0xFU; + cridx = (uint32_t)pad >> 2U; + croff = ((uint32_t)pad & 3U) * 4U; + crport = (SCFG->EXINTC[cridx] >> croff) & 0xFU; - osalDbgAssert(cport == portidx, "channel mapped on different port"); + osalDbgAssert(crport == portidx, "channel mapped on different port"); /* Disabling channel.*/ EXINT->INTEN &= ~padmask; diff --git a/os/hal/ports/AT32/LLD/GPIOv2/hal_pal_lld.h b/os/hal/ports/AT32/LLD/GPIOv2/hal_pal_lld.h index 2194f7cf4f..b9727814e7 100644 --- a/os/hal/ports/AT32/LLD/GPIOv2/hal_pal_lld.h +++ b/os/hal/ports/AT32/LLD/GPIOv2/hal_pal_lld.h @@ -1,6 +1,8 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2024 Maxjta + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + ChibiOS - Copyright (C) 2024..2025 Maxjta Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -51,39 +53,39 @@ * @name AT32-specific I/O mode flags * @{ */ -#define PAL_AT32_MODE_MASK (3U << 0U) -#define PAL_AT32_MODE_INPUT (0U << 0U) -#define PAL_AT32_MODE_OUTPUT (1U << 0U) -#define PAL_AT32_MODE_ALTERNATE (2U << 0U) -#define PAL_AT32_MODE_ANALOG (3U << 0U) +#define PAL_AT32_MODE_MASK (3U << 0U) +#define PAL_AT32_MODE_INPUT (0U << 0U) +#define PAL_AT32_MODE_OUTPUT (1U << 0U) +#define PAL_AT32_MODE_MUX (2U << 0U) +#define PAL_AT32_MODE_ANALOG (3U << 0U) -#define PAL_AT32_OMODE_MASK (1U << 2U) -#define PAL_AT32_OMODE_PUSHPULL (0U << 2U) -#define PAL_AT32_OMODE_OPENDRAIN (1U << 2U) +#define PAL_AT32_OMODE_MASK (1U << 2U) +#define PAL_AT32_OMODE_PUSHPULL (0U << 2U) +#define PAL_AT32_OMODE_OPENDRAIN (1U << 2U) -#define PAL_AT32_ODRV_MASK (3U << 3U) -#define PAL_AT32_ODRV_STRONGER (1U << 3U) -#define PAL_AT32_ODRV_MODERATE (2U << 3U) +#define PAL_AT32_ODRVR_MASK (3U << 3U) +#define PAL_AT32_ODRVR_STRONGER (1U << 3U) +#define PAL_AT32_ODRVR_MODERATE (2U << 3U) -#define PAL_AT32_PULL_MASK (3U << 5U) -#define PAL_AT32_PULL_FLOATING (0U << 5U) -#define PAL_AT32_PULL_PULLUP (1U << 5U) -#define PAL_AT32_PULL_PULLDOWN (2U << 5U) +#define PAL_AT32_PULL_MASK (3U << 5U) +#define PAL_AT32_PULL_FLOATING (0U << 5U) +#define PAL_AT32_PULL_PULLUP (1U << 5U) +#define PAL_AT32_PULL_PULLDOWN (2U << 5U) -#define PAL_AT32_ALTERNATE_MASK (15U << 7U) -#define PAL_AT32_ALTERNATE(n) ((n) << 7U) +#define PAL_AT32_MUX_MASK (15U << 7U) +#define PAL_AT32_MUX(n) ((n) << 7U) -#define PAL_AT32_HDRV_MASK (1U << 11U) -#define PAL_AT32_HDRV_NORMAL (0U << 11U) -#define PAL_AT32_HDRV_HUGE (1U << 11U) +#define PAL_AT32_HDRV_MASK (1U << 11U) +#define PAL_AT32_HDRV_DISABLED (0U << 11U) +#define PAL_AT32_HDRV_ENABLED (1U << 11U) /** - * @brief Alternate function. + * @brief Multiplexing function. * - * @param[in] n alternate function selector + * @param[in] n multiplexing function selector */ -#define PAL_MODE_ALTERNATE(n) (PAL_AT32_MODE_ALTERNATE | \ - PAL_AT32_ALTERNATE(n)) +#define PAL_MODE_MUX(n) (PAL_AT32_MODE_MUX | \ + PAL_AT32_MUX(n)) /** @} */ /** @@ -108,13 +110,13 @@ /** * @brief Input pad with weak pull up resistor. */ -#define PAL_MODE_INPUT_PULLUP (PAL_AT32_MODE_INPUT | \ +#define PAL_MODE_INPUT_PULLUP (PAL_AT32_MODE_INPUT | \ PAL_AT32_PULL_PULLUP) /** * @brief Input pad with weak pull down resistor. */ -#define PAL_MODE_INPUT_PULLDOWN (PAL_AT32_MODE_INPUT | \ +#define PAL_MODE_INPUT_PULLDOWN (PAL_AT32_MODE_INPUT | \ PAL_AT32_PULL_PULLDOWN) /** @@ -125,13 +127,13 @@ /** * @brief Push-pull output pad. */ -#define PAL_MODE_OUTPUT_PUSHPULL (PAL_AT32_MODE_OUTPUT | \ +#define PAL_MODE_OUTPUT_PUSHPULL (PAL_AT32_MODE_OUTPUT | \ PAL_AT32_OMODE_PUSHPULL) /** * @brief Open-drain output pad. */ -#define PAL_MODE_OUTPUT_OPENDRAIN (PAL_AT32_MODE_OUTPUT | \ +#define PAL_MODE_OUTPUT_OPENDRAIN (PAL_AT32_MODE_OUTPUT | \ PAL_AT32_OMODE_OPENDRAIN) /** @} */ @@ -208,7 +210,7 @@ typedef uint32_t ioline_t; typedef uint32_t ioeventmode_t; /** - * @brief Type of a port Identifier. + * @brief Type of a port identifier. * @details This type can be a scalar or some kind of pointer, do not make * any assumption about it, use the provided macros when populating * variables of this type. @@ -222,7 +224,7 @@ typedef uint32_t iopadid_t; /*===========================================================================*/ /* I/O Ports Identifiers. */ -/* The low level driver wraps the definitions already present in the AT32 */ +/* The low level driver wraps the definitions already present in the AT32 */ /* firmware library. */ /*===========================================================================*/ @@ -282,27 +284,6 @@ typedef uint32_t iopadid_t; #define IOPORT8 GPIOH #endif -/** - * @brief GPIO port I identifier. - */ -#if AT32_HAS_GPIOI || defined(__DOXYGEN__) -#define IOPORT9 GPIOI -#endif - -/** - * @brief GPIO port J identifier. - */ -#if AT32_HAS_GPIOJ || defined(__DOXYGEN__) -#define IOPORT10 GPIOJ -#endif - -/** - * @brief GPIO port K identifier. - */ -#if AT32_HAS_GPIOK || defined(__DOXYGEN__) -#define IOPORT11 GPIOK -#endif - /*===========================================================================*/ /* Implementation, some of the following macros could be implemented as */ /* functions, if so please put them in pal_lld.c. */ @@ -407,7 +388,7 @@ typedef uint32_t iopadid_t; #define pal_lld_writegroup(port, mask, offset, bits) { \ uint32_t w = ((~(uint32_t)(bits) & (uint32_t)(mask)) << (16U + (offset))) | \ ((uint32_t)(bits) & (uint32_t)(mask)) << (offset); \ - (port)->SCR.W = w; \ + (port)->SCR.W = w; \ } /** diff --git a/os/hal/ports/AT32/LLD/I2Cv1/driver.mk b/os/hal/ports/AT32/LLD/I2Cv1/driver.mk index 1a0b930c1c..66381ef851 100644 --- a/os/hal/ports/AT32/LLD/I2Cv1/driver.mk +++ b/os/hal/ports/AT32/LLD/I2Cv1/driver.mk @@ -9,6 +9,7 @@ ifeq ($(USE_HAL_I2C_FALLBACK),yes) endif PLATFORMINC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/lib/fallback/I2C else + # Default HW driver. ifeq ($(USE_SMART_BUILD),yes) ifneq ($(findstring HAL_USE_I2C TRUE,$(HALCONF)),) PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/I2Cv1/hal_i2c_lld.c @@ -16,6 +17,5 @@ else else PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/I2Cv1/hal_i2c_lld.c endif - PLATFORMINC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/I2Cv1 endif diff --git a/os/hal/ports/AT32/LLD/I2Cv1/hal_i2c_lld.c b/os/hal/ports/AT32/LLD/I2Cv1/hal_i2c_lld.c index e634185f52..3f3f6b6b91 100644 --- a/os/hal/ports/AT32/LLD/I2Cv1/hal_i2c_lld.c +++ b/os/hal/ports/AT32/LLD/I2Cv1/hal_i2c_lld.c @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/I2Cv1/hal_i2c_lld.h b/os/hal/ports/AT32/LLD/I2Cv1/hal_i2c_lld.h index 02cf1c9c8a..cd306f0053 100644 --- a/os/hal/ports/AT32/LLD/I2Cv1/hal_i2c_lld.h +++ b/os/hal/ports/AT32/LLD/I2Cv1/hal_i2c_lld.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/I2Cv2/driver.mk b/os/hal/ports/AT32/LLD/I2Cv2/driver.mk index ea3344b51c..d2614214ee 100644 --- a/os/hal/ports/AT32/LLD/I2Cv2/driver.mk +++ b/os/hal/ports/AT32/LLD/I2Cv2/driver.mk @@ -2,12 +2,12 @@ ifeq ($(USE_HAL_I2C_FALLBACK),yes) # Fallback SW driver. ifeq ($(USE_SMART_BUILD),yes) ifneq ($(findstring HAL_USE_I2C TRUE,$(HALCONF)),) - PLATFORMSRC_CONTRIB += $(CHIBIOS)/os/hal/lib/fallback/I2C/hal_i2c_lld.c + PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/lib/fallback/I2C/hal_i2c_lld.c endif else - PLATFORMSRC_CONTRIB += $(CHIBIOS)/os/hal/lib/fallback/I2C/hal_i2c_lld.c + PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/lib/fallback/I2C/hal_i2c_lld.c endif - PLATFORMINC_CONTRIB += $(CHIBIOS)/os/hal/lib/fallback/I2C + PLATFORMINC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/lib/fallback/I2C else # Default HW driver. ifeq ($(USE_SMART_BUILD),yes) diff --git a/os/hal/ports/AT32/LLD/I2Cv2/hal_i2c_lld.c b/os/hal/ports/AT32/LLD/I2Cv2/hal_i2c_lld.c index 501f9b7d1a..520a895e5e 100644 --- a/os/hal/ports/AT32/LLD/I2Cv2/hal_i2c_lld.c +++ b/os/hal/ports/AT32/LLD/I2Cv2/hal_i2c_lld.c @@ -1,6 +1,8 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 Maxjta + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + ChibiOS - Copyright (C) 2024..2025 Maxjta Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -33,41 +35,9 @@ #if AT32_I2C_USE_DMA == TRUE #define DMAMODE_COMMON \ - (AT32_DMA_CTRL_PWIDTH_BYTE | AT32_DMA_CTRL_MWIDTH_BYTE | \ - AT32_DMA_CTRL_MINCM | AT32_DMA_CTRL_DMERRIEN | \ - AT32_DMA_CTRL_DTERRIEN | AT32_DMA_CTRL_FDTIEN) - -#define I2C1_RX_DMA_CHANNEL \ - AT32_DMA_GETCHANNEL(AT32_I2C_I2C1_RX_DMA_STREAM, \ - AT32_I2C1_RX_DMA_CHN) - -#define I2C1_TX_DMA_CHANNEL \ - AT32_DMA_GETCHANNEL(AT32_I2C_I2C1_TX_DMA_STREAM, \ - AT32_I2C1_TX_DMA_CHN) - -#define I2C2_RX_DMA_CHANNEL \ - AT32_DMA_GETCHANNEL(AT32_I2C_I2C2_RX_DMA_STREAM, \ - AT32_I2C2_RX_DMA_CHN) - -#define I2C2_TX_DMA_CHANNEL \ - AT32_DMA_GETCHANNEL(AT32_I2C_I2C2_TX_DMA_STREAM, \ - AT32_I2C2_TX_DMA_CHN) - -#define I2C3_RX_DMA_CHANNEL \ - AT32_DMA_GETCHANNEL(AT32_I2C_I2C3_RX_DMA_STREAM, \ - AT32_I2C3_RX_DMA_CHN) - -#define I2C3_TX_DMA_CHANNEL \ - AT32_DMA_GETCHANNEL(AT32_I2C_I2C3_TX_DMA_STREAM, \ - AT32_I2C3_TX_DMA_CHN) - -#define I2C4_RX_DMA_CHANNEL \ - AT32_DMA_GETCHANNEL(AT32_I2C_I2C4_RX_DMA_STREAM, \ - AT32_I2C4_RX_DMA_CHN) - -#define I2C4_TX_DMA_CHANNEL \ - AT32_DMA_GETCHANNEL(AT32_I2C_I2C4_TX_DMA_STREAM, \ - AT32_I2C4_TX_DMA_CHN) + (AT32_DMA_CCTRL_PWIDTH_BYTE | AT32_DMA_CCTRL_MWIDTH_BYTE | \ + AT32_DMA_CCTRL_MINCM | AT32_DMA_CCTRL_DTERRIEN | \ + AT32_DMA_CCTRL_FDTIEN) #endif /* AT32_I2C_USE_DMA == TRUE */ #if AT32_I2C_USE_DMA == TRUE @@ -82,13 +52,14 @@ /* Driver constants. */ /*===========================================================================*/ -#define I2C_ERROR_MASK \ - ((uint32_t)(I2C_STS_BUSERR | I2C_STS_ARLOST | I2C_STS_OUF | I2C_STS_PECERR | \ - I2C_STS_TMOUT | I2C_STS_ALERTF)) +#define I2C_ERROR_MASK \ + ((uint32_t)(I2C_STS_BUSERR | I2C_STS_ARLOST | I2C_STS_OUF | \ + I2C_STS_PECERR | I2C_STS_TMOUT | I2C_STS_ALERTF)) -#define I2C_INT_MASK \ - ((uint32_t)(I2C_STS_TCRLD | I2C_STS_TDC | I2C_STS_STOPF | I2C_STS_ACKFAILF | \ - I2C_STS_ADDRF | I2C_STS_RDBF | I2C_STS_TDIS)) +#define I2C_INT_MASK \ + ((uint32_t)(I2C_STS_TCRLD | I2C_STS_TDC | I2C_STS_STOPF | \ + I2C_STS_ACKFAILF | I2C_STS_ADDRF | I2C_STS_RDBF | \ + I2C_STS_TDIS)) /*===========================================================================*/ /* Driver exported variables. */ @@ -109,11 +80,6 @@ I2CDriver I2CD2; I2CDriver I2CD3; #endif -/** @brief I2C4 driver identifier.*/ -#if AT32_I2C_USE_I2C4 || defined(__DOXYGEN__) -I2CDriver I2CD4; -#endif - /*===========================================================================*/ /* Driver local variables and types. */ /*===========================================================================*/ @@ -165,8 +131,8 @@ static void i2c_lld_setup_rx_transfer(I2CDriver *i2cp) { /* Configures the CTRL2 registers with both the calculated and static settings.*/ - dp->CTRL2 = (dp->CTRL2 & ~(I2C_CTRL2_CNT_MASK | I2C_CTRL2_RLDEN)) | i2cp->config->ctrl2 | - I2C_CTRL2_DIR | (n << 16U) | rlden; + dp->CTRL2 = (dp->CTRL2 & ~(I2C_CTRL2_CNT | I2C_CTRL2_RLDEN)) | i2cp->config->ctrl2 | + I2C_CTRL2_DIR | (n << 16U) | rlden; } /** @@ -186,14 +152,15 @@ static void i2c_lld_setup_tx_transfer(I2CDriver *i2cp) { if (n > 255U) { n = 255U; rlden = I2C_CTRL2_RLDEN; - } else { + } + else { rlden = 0U; } /* Configures the CTRL2 registers with both the calculated and static settings.*/ - dp->CTRL2 = (dp->CTRL2 & ~(I2C_CTRL2_CNT_MASK | I2C_CTRL2_RLDEN)) | i2cp->config->ctrl2 | - (n << 16U) | rlden; + dp->CTRL2 = (dp->CTRL2 & ~(I2C_CTRL2_CNT | I2C_CTRL2_RLDEN)) | i2cp->config->ctrl2 | + (n << 16U) | rlden; } /** @@ -224,7 +191,7 @@ static void i2c_lld_abort_operation(I2CDriver *i2cp) { } /** - * @brief I2C shared ISR code. + * @brief I2C shared STS code. * * @param[in] i2cp pointer to the @p I2CDriver object * @param[in] sts content of the STS register to be decoded @@ -234,7 +201,7 @@ static void i2c_lld_abort_operation(I2CDriver *i2cp) { static void i2c_lld_serve_interrupt(I2CDriver *i2cp, uint32_t sts) { I2C_TypeDef *dp = i2cp->i2c; - /* Special case of a received NACK, the transfer is aborted.*/ + /* Special case of a received ACKFAIL, the transfer is aborted.*/ if ((sts & I2C_STS_ACKFAILF) != 0U) { #if AT32_I2C_USE_DMA == TRUE /* Stops the associated DMA streams.*/ @@ -245,7 +212,7 @@ static void i2c_lld_serve_interrupt(I2CDriver *i2cp, uint32_t sts) { /* Error flag.*/ i2cp->errors |= I2C_ACK_FAILURE; - /* Transaction finished sending the STOP.*/ + /* Transaction finished sending the GENSTOP.*/ dp->CTRL2 |= I2C_CTRL2_GENSTOP; /* Make sure no more interrupts.*/ @@ -339,7 +306,7 @@ static void i2c_lld_serve_interrupt(I2CDriver *i2cp, uint32_t sts) { #endif } - /* Transaction finished sending the STOP.*/ + /* Transaction finished sending the GENSTOP.*/ dp->CTRL2 |= I2C_CTRL2_GENSTOP; /* Make sure no more 'Transfer Complete' interrupts.*/ @@ -555,61 +522,6 @@ OSAL_IRQ_HANDLER(AT32_I2C3_ERROR_HANDLER) { #endif #endif /* AT32_I2C_USE_I2C3 */ -#if AT32_I2C_USE_I2C4 || defined(__DOXYGEN__) -#if defined(AT32_I2C4_GLOBAL_HANDLER) || defined(__DOXYGEN__) -/** - * @brief I2C4 event interrupt handler. - * - * @notapi - */ -OSAL_IRQ_HANDLER(AT32_I2C4_GLOBAL_HANDLER) { - uint32_t sts = I2CD4.i2c->STS; - - OSAL_IRQ_PROLOGUE(); - - /* Clearing IRQ bits.*/ - I2CD4.i2c->CLR = sts; - - if (sts & I2C_ERROR_MASK) - i2c_lld_serve_error_interrupt(&I2CD4, sts); - else if (sts & I2C_INT_MASK) - i2c_lld_serve_interrupt(&I2CD4, sts); - - OSAL_IRQ_EPILOGUE(); -} - -#elif defined(AT32_I2C4_EVENT_HANDLER) && defined(AT32_I2C4_ERROR_HANDLER) -OSAL_IRQ_HANDLER(AT32_I2C4_EVENT_HANDLER) { - uint32_t sts = I2CD4.i2c->STS; - - OSAL_IRQ_PROLOGUE(); - - /* Clearing IRQ bits.*/ - I2CD4.i2c->CLR = sts & I2C_INT_MASK; - - i2c_lld_serve_interrupt(&I2CD4, sts); - - OSAL_IRQ_EPILOGUE(); -} - -OSAL_IRQ_HANDLER(AT32_I2C4_ERROR_HANDLER) { - uint32_t sts = I2CD4.i2c->STS; - - OSAL_IRQ_PROLOGUE(); - - /* Clearing IRQ bits.*/ - I2CD4.i2c->CLR = sts & I2C_ERROR_MASK; - - i2c_lld_serve_error_interrupt(&I2CD4, sts); - - OSAL_IRQ_EPILOGUE(); -} - -#else -#error "I2C4 interrupt handlers not defined" -#endif -#endif /* AT32_I2C_USE_I2C4 */ - /*===========================================================================*/ /* Driver exported functions. */ /*===========================================================================*/ @@ -650,16 +562,6 @@ void i2c_lld_init(void) { I2CD3.dmatx = NULL; #endif #endif /* AT32_I2C_USE_I2C3 */ - -#if AT32_I2C_USE_I2C4 - i2cObjectInit(&I2CD4); - I2CD4.thread = NULL; - I2CD4.i2c = I2C4; -#if AT32_I2C_USE_DMA == TRUE - I2CD4.dmarx = NULL; - I2CD4.dmatx = NULL; -#endif -#endif /* AT32_I2C_USE_I2C4 */ } /** @@ -680,8 +582,8 @@ void i2c_lld_start(I2CDriver *i2cp) { #if AT32_I2C_USE_DMA == TRUE /* Common DMA modes.*/ - i2cp->txdmamode = DMAMODE_COMMON | AT32_DMA_CTRL_DTD_M2P; - i2cp->rxdmamode = DMAMODE_COMMON | AT32_DMA_CTRL_DTD_P2M; + i2cp->txdmamode = DMAMODE_COMMON | AT32_DMA_CCTRL_DTD_M2P; + i2cp->rxdmamode = DMAMODE_COMMON | AT32_DMA_CCTRL_DTD_P2M; #endif #if AT32_I2C_USE_I2C1 @@ -702,18 +604,11 @@ void i2c_lld_start(I2CDriver *i2cp) { (void *)i2cp); osalDbgAssert(i2cp->dmatx != NULL, "unable to allocate stream"); - i2cp->rxdmamode |= AT32_DMA_CTRL_CHSEL(I2C1_RX_DMA_CHANNEL) | - AT32_DMA_CTRL_CHPL(AT32_I2C_I2C1_DMA_PRIORITY); - i2cp->txdmamode |= AT32_DMA_CTRL_CHSEL(I2C1_TX_DMA_CHANNEL) | - AT32_DMA_CTRL_CHPL(AT32_I2C_I2C1_DMA_PRIORITY); + i2cp->rxdmamode |= AT32_DMA_CCTRL_CHPL(AT32_I2C_I2C1_DMA_PRIORITY); + i2cp->txdmamode |= AT32_DMA_CCTRL_CHPL(AT32_I2C_I2C1_DMA_PRIORITY); #if AT32_DMA_SUPPORTS_DMAMUX -#if AT32_USE_DMA_V1 && AT32_DMA_USE_DMAMUX - dmaSetRequestSource(i2cp->dmarx, AT32_I2C_I2C1_RX_DMAMUX_CHANNEL, AT32_DMAMUX_I2C1_RX); - dmaSetRequestSource(i2cp->dmatx, AT32_I2C_I2C1_TX_DMAMUX_CHANNEL, AT32_DMAMUX_I2C1_TX); -#elif AT32_USE_DMA_V2 || AT32_USE_DMA_V3 dmaSetRequestSource(i2cp->dmarx, AT32_DMAMUX_I2C1_RX); dmaSetRequestSource(i2cp->dmatx, AT32_DMAMUX_I2C1_TX); -#endif #endif } #endif /* AT32_I2C_USE_DMA == TRUE */ @@ -747,18 +642,11 @@ void i2c_lld_start(I2CDriver *i2cp) { (void *)i2cp); osalDbgAssert(i2cp->dmatx != NULL, "unable to allocate stream"); - i2cp->rxdmamode |= AT32_DMA_CTRL_CHSEL(I2C2_RX_DMA_CHANNEL) | - AT32_DMA_CTRL_CHPL(AT32_I2C_I2C2_DMA_PRIORITY); - i2cp->txdmamode |= AT32_DMA_CTRL_CHSEL(I2C2_TX_DMA_CHANNEL) | - AT32_DMA_CTRL_CHPL(AT32_I2C_I2C2_DMA_PRIORITY); + i2cp->rxdmamode |= AT32_DMA_CCTRL_CHPL(AT32_I2C_I2C2_DMA_PRIORITY); + i2cp->txdmamode |= AT32_DMA_CCTRL_CHPL(AT32_I2C_I2C2_DMA_PRIORITY); #if AT32_DMA_SUPPORTS_DMAMUX -#if AT32_USE_DMA_V1 && AT32_DMA_USE_DMAMUX - dmaSetRequestSource(i2cp->dmarx, AT32_I2C_I2C2_RX_DMAMUX_CHANNEL, AT32_DMAMUX_I2C2_RX); - dmaSetRequestSource(i2cp->dmatx, AT32_I2C_I2C2_TX_DMAMUX_CHANNEL, AT32_DMAMUX_I2C2_TX); -#elif AT32_USE_DMA_V2 || AT32_USE_DMA_V3 dmaSetRequestSource(i2cp->dmarx, AT32_DMAMUX_I2C2_RX); dmaSetRequestSource(i2cp->dmatx, AT32_DMAMUX_I2C2_TX); -#endif #endif } #endif /* AT32_I2C_USE_DMA == TRUE */ @@ -792,18 +680,11 @@ void i2c_lld_start(I2CDriver *i2cp) { (void *)i2cp); osalDbgAssert(i2cp->dmatx != NULL, "unable to allocate stream"); - i2cp->rxdmamode |= AT32_DMA_CTRL_CHSEL(I2C3_RX_DMA_CHANNEL) | - AT32_DMA_CTRL_CHPL(AT32_I2C_I2C3_DMA_PRIORITY); - i2cp->txdmamode |= AT32_DMA_CTRL_CHSEL(I2C3_TX_DMA_CHANNEL) | - AT32_DMA_CTRL_CHPL(AT32_I2C_I2C3_DMA_PRIORITY); + i2cp->rxdmamode |= AT32_DMA_CCTRL_CHPL(AT32_I2C_I2C3_DMA_PRIORITY); + i2cp->txdmamode |= AT32_DMA_CCTRL_CHPL(AT32_I2C_I2C3_DMA_PRIORITY); #if AT32_DMA_SUPPORTS_DMAMUX -#if AT32_USE_DMA_V1 && AT32_DMA_USE_DMAMUX - dmaSetRequestSource(i2cp->dmarx, AT32_I2C_I2C3_RX_DMAMUX_CHANNEL, AT32_DMAMUX_I2C3_RX); - dmaSetRequestSource(i2cp->dmatx, AT32_I2C_I2C3_TX_DMAMUX_CHANNEL, AT32_DMAMUX_I2C3_TX); -#elif AT32_USE_DMA_V2 || AT32_USE_DMA_V3 dmaSetRequestSource(i2cp->dmarx, AT32_DMAMUX_I2C3_RX); dmaSetRequestSource(i2cp->dmatx, AT32_DMAMUX_I2C3_TX); -#endif #endif } #endif /* AT32_I2C_USE_DMA == TRUE */ @@ -818,51 +699,6 @@ void i2c_lld_start(I2CDriver *i2cp) { #endif } #endif /* AT32_I2C_USE_I2C3 */ - -#if AT32_I2C_USE_I2C4 - if (&I2CD4 == i2cp) { - - crmResetI2C4(); - crmEnableI2C4(true); -#if AT32_I2C_USE_DMA == TRUE - { - i2cp->dmarx = dmaStreamAllocI(AT32_I2C_I2C4_RX_DMA_STREAM, - AT32_I2C_I2C4_IRQ_PRIORITY, - NULL, - (void *)i2cp); - osalDbgAssert(i2cp->dmarx != NULL, "unable to allocate stream"); - i2cp->dmatx = dmaStreamAllocI(AT32_I2C_I2C4_TX_DMA_STREAM, - AT32_I2C_I2C4_IRQ_PRIORITY, - NULL, - (void *)i2cp); - osalDbgAssert(i2cp->dmatx != NULL, "unable to allocate stream"); - - i2cp->rxdmamode |= AT32_DMA_CTRL_CHSEL(I2C4_RX_DMA_CHANNEL) | - AT32_DMA_CTRL_CHPL(AT32_I2C_I2C4_DMA_PRIORITY); - i2cp->txdmamode |= AT32_DMA_CTRL_CHSEL(I2C4_TX_DMA_CHANNEL) | - AT32_DMA_CTRL_CHPL(AT32_I2C_I2C4_DMA_PRIORITY); -#if AT32_DMA_SUPPORTS_DMAMUX -#if AT32_USE_DMA_V1 && AT32_DMA_USE_DMAMUX - dmaSetRequestSource(i2cp->dmarx, AT32_I2C_I2C4_RX_DMAMUX_CHANNEL, AT32_DMAMUX_I2C4_RX); - dmaSetRequestSource(i2cp->dmatx, AT32_I2C_I2C4_TX_DMAMUX_CHANNEL, AT32_DMAMUX_I2C4_TX); -#elif AT32_USE_DMA_V2 || AT32_USE_DMA_V3 - dmaSetRequestSource(i2cp->dmarx, AT32_DMAMUX_I2C4_RX); - dmaSetRequestSource(i2cp->dmatx, AT32_DMAMUX_I2C4_TX); -#endif -#endif - } -#endif /* AT32_I2C_USE_DMA == TRUE */ - -#if defined(AT32_I2C4_GLOBAL_NUMBER) || defined(__DOXYGEN__) - nvicEnableVector(AT32_I2C4_GLOBAL_NUMBER, AT32_I2C_I2C4_IRQ_PRIORITY); -#elif defined(AT32_I2C4_EVENT_NUMBER) && defined(AT32_I2C4_ERROR_NUMBER) - nvicEnableVector(AT32_I2C4_EVENT_NUMBER, AT32_I2C_I2C4_IRQ_PRIORITY); - nvicEnableVector(AT32_I2C4_ERROR_NUMBER, AT32_I2C_I2C4_IRQ_PRIORITY); -#else -#error "I2C4 interrupt numbers not defined" -#endif - } -#endif /* AT32_I2C_USE_I2C4 */ } #if AT32_I2C_USE_DMA == TRUE @@ -871,7 +707,7 @@ void i2c_lld_start(I2CDriver *i2cp) { dmaStreamSetPeripheral(i2cp->dmatx, &dp->TXDT); #endif - /* Reset i2c peripheral, the TCIE bit will be handled separately.*/ + /* Reset i2c peripheral, the TDCIEN bit will be handled separately.*/ dp->CTRL1 = i2cp->config->ctrl1 | #if AT32_I2C_USE_DMA == TRUE I2C_CTRL1_DMATEN | I2C_CTRL1_DMAREN | /* Enable only if using DMA */ @@ -950,21 +786,6 @@ void i2c_lld_stop(I2CDriver *i2cp) { crmDisableI2C3(); } #endif - -#if AT32_I2C_USE_I2C4 - if (&I2CD4 == i2cp) { -#if defined(AT32_I2C4_GLOBAL_NUMBER) || defined(__DOXYGEN__) - nvicDisableVector(AT32_I2C4_GLOBAL_NUMBER); -#elif defined(AT32_I2C4_EVENT_NUMBER) && defined(AT32_I2C4_ERROR_NUMBER) - nvicDisableVector(AT32_I2C4_EVENT_NUMBER); - nvicDisableVector(AT32_I2C4_ERROR_NUMBER); -#else -#error "I2C4 interrupt numbers not defined" -#endif - - crmDisableI2C4(); - } -#endif } } @@ -1016,7 +837,7 @@ msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr, start = osalOsGetSystemTimeX(); end = osalTimeAddX(start, OSAL_MS2I(AT32_I2C_BUSY_TIMEOUT)); - /* Waits until BUSY flag is reset or, alternatively, for a timeout + /* Waits until BUSYF flag is reset or, alternatively, for a timeout condition.*/ while (true) { osalSysLock(); @@ -1059,7 +880,7 @@ msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr, /* Waits for the operation completion or a timeout.*/ msg = osalThreadSuspendTimeoutS(&i2cp->thread, timeout); - /* In case of a software timeout a STOP is sent as an extreme attempt + /* In case of a software timeout a GENSTOP is sent as an extreme attempt to release the bus and DMA is forcibly disabled.*/ if (msg == MSG_TIMEOUT) { dp->CTRL2 |= I2C_CTRL2_GENSTOP; @@ -1171,7 +992,7 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr, /* Waits for the operation completion or a timeout.*/ msg = osalThreadSuspendTimeoutS(&i2cp->thread, timeout); - /* In case of a software timeout a STOP is sent as an extreme attempt + /* In case of a software timeout a GENSTOP is sent as an extreme attempt to release the bus and DMA is forcibly disabled.*/ if (msg == MSG_TIMEOUT) { dp->CTRL2 |= I2C_CTRL2_GENSTOP; diff --git a/os/hal/ports/AT32/LLD/I2Cv2/hal_i2c_lld.h b/os/hal/ports/AT32/LLD/I2Cv2/hal_i2c_lld.h index f6d22314fc..619bf3b819 100644 --- a/os/hal/ports/AT32/LLD/I2Cv2/hal_i2c_lld.h +++ b/os/hal/ports/AT32/LLD/I2Cv2/hal_i2c_lld.h @@ -1,6 +1,8 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 Maxjta + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + ChibiOS - Copyright (C) 2024..2025 Maxjta Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -44,6 +46,9 @@ #define AT32_CLKCTRL_DIVL(n) ((n) << 28) #define AT32_CLKCTRL_DIVH_MASK (15U << 24) #define AT32_CLKCTRL_DIVH(n) ((n) << 24) +#define AT32_CLKCTRL_DIV_MASK (AT32_CLKCTRL_DIVL_MASK | AT32_CLKCTRL_DIVH_MASK) +#define AT32_CLKCTRL_DIV(n) (AT32_CLKCTRL_DIVL(n & 0xF) | AT32_CLKCTRL_DIVH((n >> 4) & 0xF)) + #define AT32_CLKCTRL_SCLD_MASK (15U << 20) #define AT32_CLKCTRL_SCLD(n) ((n) << 20) #define AT32_CLKCTRL_SDAD_MASK (15U << 16) @@ -52,20 +57,6 @@ #define AT32_CLKCTRL_SCLH(n) ((n) << 8) #define AT32_CLKCTRL_SCLL_MASK (255U << 0) #define AT32_CLKCTRL_SCLL(n) ((n) << 0) - - -/* Same as stm32 */ -#define STM32_TIMINGR_PRESC_MASK (AT32_CLKCTRL_DIVH_MASK | AT32_CLKCTRL_DIVL_MASK) -#define STM32_TIMINGR_PRESC(n) (AT32_CLKCTRL_DIVL(n&0xF) | AT32_CLKCTRL_DIVH((n>>4)&0xF)) -#define STM32_TIMINGR_SCLDEL_MASK AT32_CLKCTRL_SCLD_MASK -#define STM32_TIMINGR_SCLDEL(n) AT32_CLKCTRL_SCLD(n) -#define STM32_TIMINGR_SDADEL_MASK AT32_CLKCTRL_SDAD_MASK -#define STM32_TIMINGR_SDADEL(n) AT32_CLKCTRL_SDAD(n) -#define STM32_TIMINGR_SCLH_MASK AT32_CLKCTRL_SCLH_MASK -#define STM32_TIMINGR_SCLH(n) AT32_CLKCTRL_SCLH(n) -#define STM32_TIMINGR_SCLL_MASK AT32_CLKCTRL_SCLL_MASK -#define STM32_TIMINGR_SCLL(n) AT32_CLKCTRL_SCLL(n) - /** @} */ /*===========================================================================*/ @@ -103,15 +94,6 @@ #define AT32_I2C_USE_I2C3 FALSE #endif -/** - * @brief I2C4 driver enable switch. - * @details If set to @p TRUE the support for I2C4 is included. - * @note The default is @p FALSE. - */ -#if !defined(AT32_I2C_USE_I2C4) || defined(__DOXYGEN__) -#define AT32_I2C_USE_I2C4 FALSE -#endif - /** * @brief I2C timeout on busy condition in milliseconds. */ @@ -140,13 +122,6 @@ #define AT32_I2C_I2C3_IRQ_PRIORITY 10 #endif -/** - * @brief I2C4 interrupt priority level setting. - */ -#if !defined(AT32_I2C_I2C4_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define AT32_I2C_I2C4_IRQ_PRIORITY 10 -#endif - /** * @brief DMA use switch. */ @@ -184,16 +159,6 @@ #define AT32_I2C_I2C3_DMA_PRIORITY 1 #endif -/** - * @brief I2C4 DMA priority (0..3|lowest..highest). - * @note The priority level is used for both the TX and RX DMA streams but - * because of the streams ordering the RX stream has always priority - * over the TX stream. - */ -#if !defined(AT32_I2C_I2C4_DMA_PRIORITY) || defined(__DOXYGEN__) -#define AT32_I2C_I2C4_DMA_PRIORITY 1 -#endif - /** * @brief I2C DMA error hook. * @note The default action for DMA errors is a system halt because DMA @@ -221,130 +186,62 @@ #error "I2C3 not present in the selected device" #endif -#if AT32_I2C_USE_I2C4 && !AT32_HAS_I2C4 -#error "I2C4 not present in the selected device" -#endif - -#if !AT32_I2C_USE_I2C1 && !AT32_I2C_USE_I2C2 && !AT32_I2C_USE_I2C3 && \ - !AT32_I2C_USE_I2C4 +#if !AT32_I2C_USE_I2C1 && !AT32_I2C_USE_I2C2 && !AT32_I2C_USE_I2C3 #error "I2C driver activated but no I2C peripheral assigned" #endif -#if AT32_I2C_USE_I2C1 && \ +#if AT32_I2C_USE_I2C1 && \ !OSAL_IRQ_IS_VALID_PRIORITY(AT32_I2C_I2C1_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to I2C1" #endif -#if AT32_I2C_USE_I2C2 && \ +#if AT32_I2C_USE_I2C2 && \ !OSAL_IRQ_IS_VALID_PRIORITY(AT32_I2C_I2C2_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to I2C2" #endif -#if AT32_I2C_USE_I2C3 && \ +#if AT32_I2C_USE_I2C3 && \ !OSAL_IRQ_IS_VALID_PRIORITY(AT32_I2C_I2C3_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to I2C3" #endif -#if AT32_I2C_USE_I2C4 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(AT32_I2C_I2C4_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to I2C4" -#endif - #if AT32_I2C_USE_DMA == TRUE -#if AT32_I2C_USE_I2C1 && \ +#if AT32_I2C_USE_I2C1 && \ !AT32_DMA_IS_VALID_PRIORITY(AT32_I2C_I2C1_DMA_PRIORITY) #error "Invalid DMA priority assigned to I2C1" #endif -#if AT32_I2C_USE_I2C2 && \ +#if AT32_I2C_USE_I2C2 && \ !AT32_DMA_IS_VALID_PRIORITY(AT32_I2C_I2C2_DMA_PRIORITY) #error "Invalid DMA priority assigned to I2C2" #endif -#if AT32_I2C_USE_I2C3 && \ +#if AT32_I2C_USE_I2C3 && \ !AT32_DMA_IS_VALID_PRIORITY(AT32_I2C_I2C3_DMA_PRIORITY) #error "Invalid DMA priority assigned to I2C3" #endif -#if AT32_I2C_USE_I2C4 && \ - !AT32_DMA_IS_VALID_PRIORITY(AT32_I2C_I2C4_DMA_PRIORITY) -#error "Invalid DMA priority assigned to I2C4" -#endif -#if 0 +/* The following checks are only required when there is a DMA able to + reassign streams to different channels.*/ +#if AT32_ADVANCED_DMA + /* Check on the presence of the DMA streams settings in mcuconf.h.*/ -#if AT32_I2C_USE_I2C1 && (!defined(AT32_I2C_I2C1_RX_DMA_STREAM) || \ +#if AT32_I2C_USE_I2C1 && (!defined(AT32_I2C_I2C1_RX_DMA_STREAM) || \ !defined(AT32_I2C_I2C1_TX_DMA_STREAM)) #error "I2C1 DMA streams not defined" #endif - -#if AT32_I2C_USE_I2C2 && (!defined(AT32_I2C_I2C2_RX_DMA_STREAM) || \ + +#if AT32_I2C_USE_I2C2 && (!defined(AT32_I2C_I2C2_RX_DMA_STREAM) || \ !defined(AT32_I2C_I2C2_TX_DMA_STREAM)) #error "I2C2 DMA streams not defined" #endif -#if AT32_I2C_USE_I2C3 && (!defined(AT32_I2C_I2C3_RX_DMA_STREAM) || \ +#if AT32_I2C_USE_I2C3 && (!defined(AT32_I2C_I2C3_RX_DMA_STREAM) || \ !defined(AT32_I2C_I2C3_TX_DMA_STREAM)) #error "I2C3 DMA streams not defined" #endif -#if AT32_I2C_USE_I2C4 && (!defined(AT32_I2C_I2C4_RX_DMA_STREAM) || \ - !defined(AT32_I2C_I2C4_TX_DMA_STREAM)) -#error "I2C4 DMA streams not defined" -#endif -#endif -/* Devices without DMAMUX require an additional check.*/ -#if !AT32_DMA_SUPPORTS_DMAMUX - -/* Check on the validity of the assigned DMA channels.*/ -#if AT32_I2C_USE_I2C1 && \ - !AT32_DMA_IS_VALID_ID(AT32_I2C_I2C1_RX_DMA_STREAM, \ - AT32_I2C1_RX_DMA_MSK) -#error "invalid DMA stream associated to I2C1 RX" -#endif - -#if AT32_I2C_USE_I2C1 && \ - !AT32_DMA_IS_VALID_ID(AT32_I2C_I2C1_TX_DMA_STREAM, \ - AT32_I2C1_TX_DMA_MSK) -#error "invalid DMA stream associated to I2C1 TX" -#endif - -#if AT32_I2C_USE_I2C2 && \ - !AT32_DMA_IS_VALID_ID(AT32_I2C_I2C2_RX_DMA_STREAM, \ - AT32_I2C2_RX_DMA_MSK) -#error "invalid DMA stream associated to I2C2 RX" -#endif - -#if AT32_I2C_USE_I2C2 && \ - !AT32_DMA_IS_VALID_ID(AT32_I2C_I2C2_TX_DMA_STREAM, \ - AT32_I2C2_TX_DMA_MSK) -#error "invalid DMA stream associated to I2C2 TX" -#endif - -#if AT32_I2C_USE_I2C3 && \ - !AT32_DMA_IS_VALID_ID(AT32_I2C_I2C3_RX_DMA_STREAM, \ - AT32_I2C3_RX_DMA_MSK) -#error "invalid DMA stream associated to I2C3 RX" -#endif - -#if AT32_I2C_USE_I2C3 && \ - !AT32_DMA_IS_VALID_ID(AT32_I2C_I2C3_TX_DMA_STREAM, \ - AT32_I2C3_TX_DMA_MSK) -#error "invalid DMA stream associated to I2C3 TX" -#endif - -#if AT32_I2C_USE_I2C4 && \ - !AT32_DMA_IS_VALID_ID(AT32_I2C_I2C4_RX_DMA_STREAM, \ - AT32_I2C4_RX_DMA_MSK) -#error "invalid DMA stream associated to I2C4 RX" -#endif - -#if AT32_I2C_USE_I2C4 && \ - !AT32_DMA_IS_VALID_ID(AT32_I2C_I2C4_TX_DMA_STREAM, \ - AT32_I2C4_TX_DMA_MSK) -#error "invalid DMA stream associated to I2C4 TX" -#endif - -#endif /* !AT32_DMA_SUPPORTS_DMAMUX */ +#endif /* AT32_ADVANCED_DMA */ #if !defined(AT32_DMA_REQUIRED) #define AT32_DMA_REQUIRED @@ -495,10 +392,6 @@ extern I2CDriver I2CD2; extern I2CDriver I2CD3; #endif -#if AT32_I2C_USE_I2C4 -extern I2CDriver I2CD4; -#endif - #endif /* !defined(__DOXYGEN__) */ #ifdef __cplusplus diff --git a/os/hal/ports/AT32/LLD/OTGv1/at32_otg.h b/os/hal/ports/AT32/LLD/OTGv1/at32_otg.h index ba9c2fd97d..cb749d1720 100644 --- a/os/hal/ports/AT32/LLD/OTGv1/at32_otg.h +++ b/os/hal/ports/AT32/LLD/OTGv1/at32_otg.h @@ -1,7 +1,8 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + ChibiOS - Copyright (C) 2024..2025 Maxjta Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -777,6 +778,8 @@ typedef struct { #define DIEPINT_INTKNTXFEMP (1U << 4) /**< IN Token received when TxFIFO is empty. */ #define DIEPINT_TIMEOUT (1U << 3) /**< Timeout condition. */ +#define DIEPINT_AHBERR (1U << 2) /**< AHB error interrupt + (HS only). */ #define DIEPINT_EPTDISD (1U << 1) /**< Endpoint disabled interrupt. */ #define DIEPINT_XFERC (1U << 0) /**< Transfer completed @@ -834,11 +837,15 @@ typedef struct { * @name DOEPINT register bit definitions * @{ */ +#define DOEPINT_STPPKRX (1U << 15) /**< Setup packet received + (HS only). */ #define DOEPINT_B2BSTUP (1U << 6) /**< Back-to-back SETUP packets received. */ #define DOEPINT_OUTTEPD (1U << 4) /**< OUT token received when endpoint disabled. */ #define DOEPINT_SETUP (1U << 3) /**< SETUP phase done. */ +#define DOEPINT_AHBERR (1U << 2) /**< AHB error interrupt + (HS only). */ #define DOEPINT_EPTDISD (1U << 1) /**< Endpoint disabled interrupt. */ #define DOEPINT_XFERC (1U << 0) /**< Transfer completed diff --git a/os/hal/ports/AT32/LLD/OTGv1/hal_usb_lld.c b/os/hal/ports/AT32/LLD/OTGv1/hal_usb_lld.c index 0bf7051782..50f2e90232 100644 --- a/os/hal/ports/AT32/LLD/OTGv1/hal_usb_lld.c +++ b/os/hal/ports/AT32/LLD/OTGv1/hal_usb_lld.c @@ -1,8 +1,8 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian - ChibiOS - Copyright (C) 2023..2024 Maxjta + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + ChibiOS - Copyright (C) 2024..2025 Maxjta Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -119,7 +119,8 @@ static const USBEndpointConfig ep0config = { static const at32_otg_params_t fsparams = { AT32_USB_OTG1_RX_FIFO_SIZE / 4, AT32_OTG1_FIFO_MEM_SIZE, - AT32_OTG1_ENDPOINTS + AT32_OTG1_ENDPOINTS, + 0 }; #endif @@ -127,7 +128,12 @@ static const at32_otg_params_t fsparams = { static const at32_otg_params_t hsparams = { AT32_USB_OTG2_RX_FIFO_SIZE / 4, AT32_OTG2_FIFO_MEM_SIZE, - AT32_OTG2_ENDPOINTS + AT32_OTG2_ENDPOINTS, +#if AT32_USE_USB_OTG2_HS_DMA + 1 +#else + 0 +#endif }; #endif @@ -376,9 +382,17 @@ static bool otg_txfifo_handler(USBDriver *usbp, usbep_t ep) { #if AT32_USB_OTGFIFO_FILL_BASEPRI __set_BASEPRI(CORTEX_PRIO_MASK(AT32_USB_OTGFIFO_FILL_BASEPRI)); #endif +#if AT32_USE_USB_OTG2_HS_DMA + if (usbp->otgparams->dma_en) { + usbp->otg->ie[ep].DIEPDMA = (uint32_t)(usbp->epc[ep]->in_state->txbuf); + } + else +#endif + { otg_fifo_write_from_buffer(usbp->otg->FIFO[ep], usbp->epc[ep]->in_state->txbuf, n); + } usbp->epc[ep]->in_state->txbuf += n; usbp->epc[ep]->in_state->txcnt += n; #if AT32_USB_OTGFIFO_FILL_BASEPRI @@ -412,6 +426,11 @@ static void otg_epin_handler(USBDriver *usbp, usbep_t ep) { /* In case the transaction covered only part of the total transfer then another transaction is immediately started in order to cover the remaining.*/ +#if AT32_USE_USB_OTG2_HS_DMA + if (usbp->otgparams->dma_en) { + isp->txbuf += isp->txsize; + } +#endif isp->txsize = isp->totsize - isp->txsize; isp->txcnt = 0; osalSysLockFromISR(); @@ -422,11 +441,25 @@ static void otg_epin_handler(USBDriver *usbp, usbep_t ep) { /* End on IN transfer.*/ _usb_isr_invoke_in_cb(usbp, ep); } +#if AT32_USE_USB_OTG2_HS_DMA + if (usbp->otgparams->dma_en) { + if (ep == 0 && 0 == isp->totsize) { + usbp->otg->oe[0].DOEPTSIZ = DOEPTSIZ_SETUPCNT(3); + usbp->otg->oe[0].DOEPDMA = (uint32_t)(usbp->epc[0]->setup_buf); + usbp->otg->oe[0].DOEPCTL |= DOEPCTL_EPTENA | DOEPCTL_USBACEPT | + DOEPCTL_CNAK; + } + } +#endif } - if ((epint & DIEPINT_TXFEMP) && - (otgp->DIEPEMPMSK & DIEPEMPMSK_INEPTXFEMSK(ep))) { - /* TX FIFO empty or emptying.*/ - otg_txfifo_handler(usbp, ep); + if (usbp->otgparams->dma_en) { + } + else { + if ((epint & DIEPINT_TXFEMP) && + (otgp->DIEPEMPMSK & DIEPEMPMSK_INEPTXFEMSK(ep))) { + /* TX FIFO empty or emptying.*/ + otg_txfifo_handler(usbp, ep); + } } } @@ -449,6 +482,11 @@ static void otg_epout_handler(USBDriver *usbp, usbep_t ep) { /* Setup packets handling, setup packets are handled using a specific callback.*/ _usb_isr_invoke_setup_cb(usbp, ep); +#if AT32_USE_USB_OTG2_HS_DMA + if (usbp->otgparams->dma_en) { + return; + } +#endif } if ((epint & DOEPINT_XFERC) && (otgp->DOEPMSK & DOEPMSK_XFERCMSK)) { @@ -456,6 +494,28 @@ static void otg_epout_handler(USBDriver *usbp, usbep_t ep) { /* OUT state structure pointer for this endpoint.*/ osp = usbp->epc[ep]->out_state; +#if AT32_USE_USB_OTG2_HS_DMA + if (usbp->otgparams->dma_en) { + if (epint & DOEPINT_STPPKRX) { + if (epint & DOEPINT_SETUP) { + } + else { + return; + } + } + if (osp->totsize) { + uint32_t sz = osp->rxsize - (usbp->otg->oe[ep].DOEPTSIZ & DOEPTSIZ_XFERSIZE_MASK); + osp->rxcnt += sz; + osp->rxbuf += sz; + } + else { + usbp->otg->oe[0].DOEPTSIZ = DOEPTSIZ_SETUPCNT(3); + usbp->otg->oe[0].DOEPDMA = (uint32_t)(usbp->epc[0]->setup_buf); + usbp->otg->oe[0].DOEPCTL |= DOEPCTL_EPTENA | DOEPCTL_USBACEPT | + DOEPCTL_CNAK; + } + } +#endif /* EP0 requires special handling.*/ if (ep == 0) { @@ -814,18 +874,30 @@ void usb_lld_start(USBDriver *usbp) { #if AT32_USB_USE_OTG2 if (&USBD2 == usbp) { - -#if AT32_OTG2_SUPPORTS_HS +#if defined(BOARD_OTG2_USES_ULPI) /* OTG HS clock enable and reset.*/ crmEnableOTG_HS(true); crmResetOTG_HS(); +#else + /* OTG FS clock enable and reset.*/ + crmEnableOTG_FS2(true); + crmResetOTG_FS2(); +#endif /* Enables IRQ vector.*/ nvicEnableVector(AT32_OTG2_NUMBER, AT32_USB_OTG2_IRQ_PRIORITY); /* - Forced device mode. - - USB turn-around time = USBTRDTIM_VALUE_HS or USBTRDTIM_VALUE_FS.*/ + - USB turn-around time = USBTRDTIM_VALUE_HS or USBTRDTIM_VALUE_FS.*/ +#if defined(BOARD_OTG2_USES_ULPI) + /* High speed ULPI PHY.*/ otgp->GUSBCFG = GUSBCFG_FDEVMODE | GUSBCFG_USBTRDTIM(USBTRDTIM_VALUE_HS); +#else + otgp->GUSBCFG = GUSBCFG_FDEVMODE | GUSBCFG_USBTRDTIM(USBTRDTIM_VALUE_FS) | + GUSBCFG_PHYSEL; +#endif + +#if defined(BOARD_OTG2_USES_ULPI) #if AT32_USE_USB_OTG2_HS /* USB 2.0 High Speed PHY in HS mode.*/ otgp->DCFG = 0x02200000 | DCFG_DEVSPD_HS; @@ -833,20 +905,7 @@ void usb_lld_start(USBDriver *usbp) { /* USB 2.0 High Speed PHY in FS mode.*/ otgp->DCFG = 0x02200000 | DCFG_DEVSPD_HS_FS; #endif - #else - /* OTG FS clock enable and reset.*/ - crmEnableOTG_FS2(true); - crmResetOTG_FS2(); - - /* Enables IRQ vector.*/ - nvicEnableVector(AT32_OTG2_NUMBER, AT32_USB_OTG2_IRQ_PRIORITY); - - /* - Forced device mode. - - USB turn-around time = USBTRDTIM_VALUE_HS or USBTRDTIM_VALUE_FS.*/ - otgp->GUSBCFG = GUSBCFG_FDEVMODE | GUSBCFG_USBTRDTIM(USBTRDTIM_VALUE_FS) | - GUSBCFG_PHYSEL; - /* 48MHz 1.1 PHY.*/ otgp->DCFG = 0x02200000 | DCFG_DEVSPD_FS11; #endif @@ -861,8 +920,16 @@ void usb_lld_start(USBDriver *usbp) { /* Soft core reset.*/ otg_core_reset(usbp); - /* Interrupts on TXFIFOs half empty.*/ - otgp->GAHBCFG = 0; +#if AT32_USE_USB_OTG2_HS_DMA + if (usbp->otgparams->dma_en) { + otgp->GAHBCFG = GAHBCFG_DMAEN | GAHBCFG_HBSTLEN(1); + } + else +#endif + { + /* Interrupts on TXFIFOs half empty.*/ + otgp->GAHBCFG = 0; + } /* Endpoints re-initialization.*/ otg_disable_ep(usbp); @@ -964,15 +1031,31 @@ void usb_lld_reset(USBDriver *usbp) { otgp->DCFG = (otgp->DCFG & ~DCFG_DEVADDR_MASK) | DCFG_DEVADDR(0); /* Enables also EP-related interrupt sources.*/ - otgp->GINTMSK |= GINTMSK_RXFLVLMSK | GINTMSK_OEPTINTMSK | GINTMSK_IEPTINTMSK; - otgp->DIEPMSK = DIEPMSK_TIMEOUTMSK | DIEPMSK_XFERCMSK; - otgp->DOEPMSK = DOEPMSK_SETUPMSK | DOEPMSK_XFERCMSK; + otgp->GINTMSK |= GINTMSK_RXFLVLMSK | GINTMSK_OEPTINTMSK | GINTMSK_IEPTINTMSK; +#if AT32_USE_USB_OTG2_HS_DMA + if (usbp->otgparams->dma_en) { + otgp->GINTMSK &= ~GINTMSK_RXFLVLMSK; + } +#endif + otgp->DIEPMSK = DIEPMSK_TIMEOUTMSK | DIEPMSK_XFERCMSK; + otgp->DOEPMSK = DOEPMSK_SETUPMSK | DOEPMSK_XFERCMSK; /* EP0 initialization, it is a special case.*/ usbp->epc[0] = &ep0config; otgp->oe[0].DOEPTSIZ = DOEPTSIZ_SETUPCNT(3); - otgp->oe[0].DOEPCTL = DOEPCTL_SETD0PID | DOEPCTL_USBACEPT | DOEPCTL_EPTYPE_CTRL | - DOEPCTL_MPS(ep0config.out_maxsize); +#if AT32_USE_USB_OTG2_HS_DMA + if (usbp->otgparams->dma_en) { + otgp->oe[0].DOEPDMA = (uint32_t)(usbp->epc[0]->setup_buf); + otgp->oe[0].DOEPCTL = DOEPCTL_SETD0PID | DOEPCTL_USBACEPT | DOEPCTL_EPTYPE_CTRL | DOEPCTL_EPTENA | + DOEPCTL_MPS(ep0config.out_maxsize); + } + else +#endif + { + otgp->oe[0].DOEPCTL = DOEPCTL_SETD0PID | DOEPCTL_USBACEPT | DOEPCTL_EPTYPE_CTRL | + DOEPCTL_MPS(ep0config.out_maxsize); + } + otgp->ie[0].DIEPTSIZ = 0; otgp->ie[0].DIEPCTL = DIEPCTL_SETD0PID | DIEPCTL_USBACEPT | DIEPCTL_EPTYPE_CTRL | DIEPCTL_TXFNUM(0) | DIEPCTL_MPS(ep0config.in_maxsize); @@ -1166,14 +1249,37 @@ void usb_lld_start_out(USBDriver *usbp, usbep_t ep) { "For OUT transfers, the transfer size field in the endpoint's transfer size register must be a multiple of the maximum packet size of the endpoint, adjusted to the Word boundary".*/ +#if AT32_USE_USB_OTG2_HS_DMA + if (usbp->otgparams->dma_en && ep == 0) { + pcnt = 1; + } + else { + pcnt = (osp->rxsize + usbp->epc[ep]->out_maxsize - 1U) / + usbp->epc[ep]->out_maxsize; + } +#else pcnt = (osp->rxsize + usbp->epc[ep]->out_maxsize - 1U) / usbp->epc[ep]->out_maxsize; +#endif rxsize = (pcnt * usbp->epc[ep]->out_maxsize + 3U) & 0xFFFFFFFCU; /* Setting up transaction parameters in DOEPTSIZ.*/ usbp->otg->oe[ep].DOEPTSIZ = DOEPTSIZ_SETUPCNT(3) | DOEPTSIZ_PKTCNT(pcnt) | DOEPTSIZ_XFERSIZE(rxsize); +#if AT32_USE_USB_OTG2_HS_DMA + if (usbp->otgparams->dma_en) { + if (osp->rxbuf) { + usbp->otg->oe[ep].DOEPDMA = (uint32_t)(osp->rxbuf); + } + else { + if (ep == 0) { + usbp->otg->oe[ep].DOEPDMA = (uint32_t)(usbp->epc[0]->setup_buf); + } + } + } +#endif + /* Special case of isochronous endpoint.*/ if ((usbp->epc[ep]->ep_mode & USB_EP_MODE_TYPE) == USB_EP_MODE_TYPE_ISOC) { /* Odd/even bit toggling for isochronous endpoint.*/ @@ -1203,6 +1309,11 @@ void usb_lld_start_in(USBDriver *usbp, usbep_t ep) { if (isp->txsize == 0) { /* Special case, sending zero size packet.*/ usbp->otg->ie[ep].DIEPTSIZ = DIEPTSIZ_PKTCNT(1) | DIEPTSIZ_XFERSIZE(0); +#if AT32_USE_USB_OTG2_HS_DMA + if (usbp->otgparams->dma_en) { + usbp->otg->ie[ep].DIEPDMA = 0; + } +#endif } else { if ((ep == 0) && (isp->txsize > EP0_MAX_INSIZE)) @@ -1214,6 +1325,11 @@ void usb_lld_start_in(USBDriver *usbp, usbep_t ep) { /* CHTODO: Support more than one packet per frame for isochronous transfers.*/ usbp->otg->ie[ep].DIEPTSIZ = DIEPTSIZ_MC(1) | DIEPTSIZ_PKTCNT(pcnt) | DIEPTSIZ_XFERSIZE(isp->txsize); +#if AT32_USE_USB_OTG2_HS_DMA + if (usbp->otgparams->dma_en) { + usbp->otg->ie[ep].DIEPDMA = (uint32_t)(isp->txbuf); + } +#endif } /* Special case of isochronous endpoint.*/ @@ -1227,7 +1343,13 @@ void usb_lld_start_in(USBDriver *usbp, usbep_t ep) { /* Starting operation.*/ usbp->otg->ie[ep].DIEPCTL |= DIEPCTL_EPTENA | DIEPCTL_CNAK; +#if AT32_USE_USB_OTG2_HS_DMA + if (usbp->otgparams->dma_en == 0) { + usbp->otg->DIEPEMPMSK |= DIEPEMPMSK_INEPTXFEMSK(ep); + } +#else usbp->otg->DIEPEMPMSK |= DIEPEMPMSK_INEPTXFEMSK(ep); +#endif } /** diff --git a/os/hal/ports/AT32/LLD/OTGv1/hal_usb_lld.h b/os/hal/ports/AT32/LLD/OTGv1/hal_usb_lld.h index 67d6dd1f76..1221fa8bcb 100644 --- a/os/hal/ports/AT32/LLD/OTGv1/hal_usb_lld.h +++ b/os/hal/ports/AT32/LLD/OTGv1/hal_usb_lld.h @@ -1,7 +1,8 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + ChibiOS - Copyright (C) 2024..2025 Maxjta Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -111,6 +112,15 @@ #define AT32_USE_USB_OTG2_HS TRUE #endif +/** + * @brief Enables DMA mode on OTG2. + * @note The default is @p TRUE. + * @note Has effect only if @p BOARD_OTG2_USES_ULPI is defined. + */ +#if !defined(AT32_USE_USB_OTG2_HS_DMA) || defined(__DOXYGEN__) +#define AT32_USE_USB_OTG2_HS_DMA FALSE +#endif + /** * @brief Exception priority level during TXFIFOs operations. * @note Because an undocumented silicon behavior the operation of @@ -243,6 +253,7 @@ typedef struct { uint32_t rx_fifo_size; uint32_t otg_ram_size; uint32_t num_endpoints; + uint32_t dma_en; } at32_otg_params_t; /** diff --git a/os/hal/ports/AT32/LLD/RTCv2/hal_rtc_lld.c b/os/hal/ports/AT32/LLD/RTCv2/hal_rtc_lld.c index 2dff5520c1..01f340fe08 100644 --- a/os/hal/ports/AT32/LLD/RTCv2/hal_rtc_lld.c +++ b/os/hal/ports/AT32/LLD/RTCv2/hal_rtc_lld.c @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/RTCv2/hal_rtc_lld.h b/os/hal/ports/AT32/LLD/RTCv2/hal_rtc_lld.h index 59ed2c6d8b..9360e5d8c8 100644 --- a/os/hal/ports/AT32/LLD/RTCv2/hal_rtc_lld.h +++ b/os/hal/ports/AT32/LLD/RTCv2/hal_rtc_lld.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/SDIOv1/hal_sdc_lld.c b/os/hal/ports/AT32/LLD/SDIOv1/hal_sdc_lld.c index 9cbea0e255..5f7511a000 100644 --- a/os/hal/ports/AT32/LLD/SDIOv1/hal_sdc_lld.c +++ b/os/hal/ports/AT32/LLD/SDIOv1/hal_sdc_lld.c @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/SDIOv1/hal_sdc_lld.h b/os/hal/ports/AT32/LLD/SDIOv1/hal_sdc_lld.h index 5cef5fc617..b297b94411 100644 --- a/os/hal/ports/AT32/LLD/SDIOv1/hal_sdc_lld.h +++ b/os/hal/ports/AT32/LLD/SDIOv1/hal_sdc_lld.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/SPIv1/hal_spi_v2_lld.c b/os/hal/ports/AT32/LLD/SPIv1/hal_spi_v2_lld.c index 8489f04186..caf65de7f1 100644 --- a/os/hal/ports/AT32/LLD/SPIv1/hal_spi_v2_lld.c +++ b/os/hal/ports/AT32/LLD/SPIv1/hal_spi_v2_lld.c @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -40,6 +40,10 @@ #define SPI_SPID2_MEMORY #endif +#if !defined(SPI_SPID3_MEMORY) +#define SPI_SPID3_MEMORY +#endif + /*===========================================================================*/ /* Driver exported variables. */ /*===========================================================================*/ @@ -54,6 +58,11 @@ SPI_SPID1_MEMORY SPIDriver SPID1; SPI_SPID2_MEMORY SPIDriver SPID2; #endif +/** @brief SPI3 driver identifier.*/ +#if AT32_SPI_USE_SPI3 || defined(__DOXYGEN__) +SPI_SPID3_MEMORY SPIDriver SPID3; +#endif + /*===========================================================================*/ /* Driver local variables and types. */ /*===========================================================================*/ @@ -130,6 +139,12 @@ static msg_t spi_lld_stop_abort(SPIDriver *spip) { } #endif +#if AT32_SPI_USE_SPI3 + else if (&SPID3 == spip) { + crmResetSPI3(); + } +#endif + else { osalDbgAssert(false, "invalid SPI instance"); } @@ -276,6 +291,20 @@ void spi_lld_init(void) { AT32_DMA_CCTRL_DTD_M2P | AT32_DMA_CCTRL_DTERRIEN; #endif + +#if AT32_SPI_USE_SPI3 + spiObjectInit(&SPID3); + SPID3.spi = SPI3; + SPID3.dmarx = NULL; + SPID3.dmatx = NULL; + SPID3.rxdmamode = AT32_DMA_CCTRL_CHPL(AT32_SPI_SPI3_DMA_PRIORITY) | + AT32_DMA_CCTRL_DTD_P2M | + AT32_DMA_CCTRL_FDTIEN | + AT32_DMA_CCTRL_DTERRIEN; + SPID3.txdmamode = AT32_DMA_CCTRL_CHPL(AT32_SPI_SPI3_DMA_PRIORITY) | + AT32_DMA_CCTRL_DTD_M2P | + AT32_DMA_CCTRL_DTERRIEN; +#endif } /** @@ -333,6 +362,24 @@ msg_t spi_lld_start(SPIDriver *spip) { } #endif +#if AT32_SPI_USE_SPI3 + else if (&SPID3 == spip) { + msg = spi_lld_get_dma(spip, + AT32_SPI_SPI3_RX_DMA_STREAM, + AT32_SPI_SPI3_TX_DMA_STREAM, + AT32_SPI_SPI3_IRQ_PRIORITY); + if (msg != HAL_RET_SUCCESS) { + return msg; + } + crmEnableSPI3(true); + crmResetSPI3(); +#if AT32_DMA_SUPPORTS_DMAMUX + dmaSetRequestSource(spip->dmarx, AT32_SPI_SPI3_RX_DMAMUX_CHANNEL, AT32_DMAMUX_SPI3_RX); + dmaSetRequestSource(spip->dmatx, AT32_SPI_SPI3_TX_DMAMUX_CHANNEL, AT32_DMAMUX_SPI3_TX); +#endif + } +#endif + else { osalDbgAssert(false, "invalid SPI instance"); } @@ -414,6 +461,12 @@ void spi_lld_stop(SPIDriver *spip) { } #endif +#if AT32_SPI_USE_SPI3 + else if (&SPID3 == spip) { + crmDisableSPI3(); + } +#endif + else { osalDbgAssert(false, "invalid SPI instance"); } diff --git a/os/hal/ports/AT32/LLD/SPIv1/hal_spi_v2_lld.h b/os/hal/ports/AT32/LLD/SPIv1/hal_spi_v2_lld.h index d2abef7203..5a5eda43b2 100644 --- a/os/hal/ports/AT32/LLD/SPIv1/hal_spi_v2_lld.h +++ b/os/hal/ports/AT32/LLD/SPIv1/hal_spi_v2_lld.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -70,6 +70,15 @@ #define AT32_SPI_USE_SPI2 FALSE #endif +/** + * @brief SPI3 driver enable switch. + * @details If set to @p TRUE the support for SPI3 is included. + * @note The default is @p FALSE. + */ +#if !defined(AT32_SPI_USE_SPI3) || defined(__DOXYGEN__) +#define AT32_SPI_USE_SPI3 FALSE +#endif + /** * @brief Filler pattern used when there is nothing to transmit. */ @@ -91,6 +100,13 @@ #define AT32_SPI_SPI2_IRQ_PRIORITY 10 #endif +/** + * @brief SPI3 interrupt priority level setting. + */ +#if !defined(AT32_SPI_SPI3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define AT32_SPI_SPI3_IRQ_PRIORITY 10 +#endif + /** * @brief SPI1 DMA priority (0..3|lowest..highest). * @note The priority level is used for both the TX and RX DMA streams but @@ -111,6 +127,16 @@ #define AT32_SPI_SPI2_DMA_PRIORITY 1 #endif +/** + * @brief SPI3 DMA priority (0..3|lowest..highest). + * @note The priority level is used for both the TX and RX DMA streams but + * because of the streams ordering the RX stream has always priority + * over the TX stream. + */ +#if !defined(AT32_SPI_SPI3_DMA_PRIORITY) || defined(__DOXYGEN__) +#define AT32_SPI_SPI3_DMA_PRIORITY 1 +#endif + /** * @brief SPI DMA error hook. */ @@ -131,7 +157,11 @@ #error "SPI2 not present in the selected device" #endif -#if !AT32_SPI_USE_SPI1 && !AT32_SPI_USE_SPI2 +#if AT32_SPI_USE_SPI3 && !AT32_HAS_SPI3 +#error "SPI3 not present in the selected device" +#endif + +#if !AT32_SPI_USE_SPI1 && !AT32_SPI_USE_SPI2 && !AT32_SPI_USE_SPI3 #error "SPI driver activated but no SPI peripheral assigned" #endif @@ -145,6 +175,33 @@ #error "Invalid IRQ priority assigned to SPI2" #endif +#if AT32_SPI_USE_SPI3 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(AT32_SPI_SPI3_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to SPI3" +#endif + +/* The following checks are only required when there is a DMA able to + reassign streams to different channels.*/ +#if AT32_ADVANCED_DMA + +/* Check on the presence of the DMA streams settings in mcuconf.h.*/ +#if AT32_SPI_USE_SPI1 && (!defined(AT32_SPI_SPI1_RX_DMA_STREAM) || \ + !defined(AT32_SPI_SPI1_TX_DMA_STREAM)) +#error "SPI1 DMA streams not defined" +#endif + +#if AT32_SPI_USE_SPI2 && (!defined(AT32_SPI_SPI2_RX_DMA_STREAM) || \ + !defined(AT32_SPI_SPI2_TX_DMA_STREAM)) +#error "SPI2 DMA streams not defined" +#endif + +#if AT32_SPI_USE_SPI3 && (!defined(AT32_SPI_SPI3_RX_DMA_STREAM) || \ + !defined(AT32_SPI_SPI3_TX_DMA_STREAM)) +#error "SPI3 DMA streams not defined" +#endif + +#endif /* AT32_ADVANCED_DMA */ + #if !defined(AT32_DMA_REQUIRED) #define AT32_DMA_REQUIRED #endif @@ -198,6 +255,10 @@ extern SPIDriver SPID1; extern SPIDriver SPID2; #endif +#if AT32_SPI_USE_SPI3 && !defined(__DOXYGEN__) +extern SPIDriver SPID3; +#endif + #ifdef __cplusplus extern "C" { #endif diff --git a/os/hal/ports/AT32/LLD/SPIv2/hal_spi_v2_lld.c b/os/hal/ports/AT32/LLD/SPIv2/hal_spi_v2_lld.c index c1ef1cd24e..6369ce9ebf 100644 --- a/os/hal/ports/AT32/LLD/SPIv2/hal_spi_v2_lld.c +++ b/os/hal/ports/AT32/LLD/SPIv2/hal_spi_v2_lld.c @@ -1,8 +1,8 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian - ChibiOS - Copyright (C) 2023..2024 Maxjta + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + ChibiOS - Copyright (C) 2024..2025 Maxjta Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -41,6 +41,10 @@ #define SPI_SPID2_MEMORY #endif +#if !defined(SPI_SPID3_MEMORY) +#define SPI_SPID3_MEMORY +#endif + /*===========================================================================*/ /* Driver exported variables. */ /*===========================================================================*/ @@ -55,6 +59,11 @@ SPI_SPID1_MEMORY SPIDriver SPID1; SPI_SPID2_MEMORY SPIDriver SPID2; #endif +/** @brief SPI3 driver identifier.*/ +#if AT32_SPI_USE_SPI3 || defined(__DOXYGEN__) +SPI_SPID3_MEMORY SPIDriver SPID3; +#endif + /*===========================================================================*/ /* Driver local variables and types. */ /*===========================================================================*/ @@ -131,6 +140,12 @@ static msg_t spi_lld_stop_abort(SPIDriver *spip) { } #endif +#if AT32_SPI_USE_SPI3 + else if (&SPID3 == spip) { + crmResetSPI3(); + } +#endif + else { osalDbgAssert(false, "invalid SPI instance"); } @@ -255,13 +270,13 @@ void spi_lld_init(void) { SPID1.spi = SPI1; SPID1.dmarx = NULL; SPID1.dmatx = NULL; - SPID1.rxdmamode = AT32_DMA_CTRL_CHPL(AT32_SPI_SPI1_DMA_PRIORITY) | - AT32_DMA_CTRL_DTD_P2M | - AT32_DMA_CTRL_FDTIEN | - AT32_DMA_CTRL_DTERRIEN; - SPID1.txdmamode = AT32_DMA_CTRL_CHPL(AT32_SPI_SPI1_DMA_PRIORITY) | - AT32_DMA_CTRL_DTD_M2P | - AT32_DMA_CTRL_DTERRIEN; + SPID1.rxdmamode = AT32_DMA_CCTRL_CHPL(AT32_SPI_SPI1_DMA_PRIORITY) | + AT32_DMA_CCTRL_DTD_P2M | + AT32_DMA_CCTRL_FDTIEN | + AT32_DMA_CCTRL_DTERRIEN; + SPID1.txdmamode = AT32_DMA_CCTRL_CHPL(AT32_SPI_SPI1_DMA_PRIORITY) | + AT32_DMA_CCTRL_DTD_M2P | + AT32_DMA_CCTRL_DTERRIEN; #endif #if AT32_SPI_USE_SPI2 @@ -269,13 +284,27 @@ void spi_lld_init(void) { SPID2.spi = SPI2; SPID2.dmarx = NULL; SPID2.dmatx = NULL; - SPID2.rxdmamode = AT32_DMA_CTRL_CHPL(AT32_SPI_SPI2_DMA_PRIORITY) | - AT32_DMA_CTRL_DTD_P2M | - AT32_DMA_CTRL_FDTIEN | - AT32_DMA_CTRL_DTERRIEN; - SPID2.txdmamode = AT32_DMA_CTRL_CHPL(AT32_SPI_SPI2_DMA_PRIORITY) | - AT32_DMA_CTRL_DTD_M2P | - AT32_DMA_CTRL_DTERRIEN; + SPID2.rxdmamode = AT32_DMA_CCTRL_CHPL(AT32_SPI_SPI2_DMA_PRIORITY) | + AT32_DMA_CCTRL_DTD_P2M | + AT32_DMA_CCTRL_FDTIEN | + AT32_DMA_CCTRL_DTERRIEN; + SPID2.txdmamode = AT32_DMA_CCTRL_CHPL(AT32_SPI_SPI2_DMA_PRIORITY) | + AT32_DMA_CCTRL_DTD_M2P | + AT32_DMA_CCTRL_DTERRIEN; +#endif + +#if AT32_SPI_USE_SPI3 + spiObjectInit(&SPID3); + SPID3.spi = SPI3; + SPID3.dmarx = NULL; + SPID3.dmatx = NULL; + SPID3.rxdmamode = AT32_DMA_CCTRL_CHPL(AT32_SPI_SPI3_DMA_PRIORITY) | + AT32_DMA_CCTRL_DTD_P2M | + AT32_DMA_CCTRL_FDTIEN | + AT32_DMA_CCTRL_DTERRIEN; + SPID3.txdmamode = AT32_DMA_CCTRL_CHPL(AT32_SPI_SPI3_DMA_PRIORITY) | + AT32_DMA_CCTRL_DTD_M2P | + AT32_DMA_CCTRL_DTERRIEN; #endif } @@ -334,6 +363,24 @@ msg_t spi_lld_start(SPIDriver *spip) { } #endif +#if AT32_SPI_USE_SPI3 + else if (&SPID3 == spip) { + msg = spi_lld_get_dma(spip, + AT32_SPI_SPI3_RX_DMA_STREAM, + AT32_SPI_SPI3_TX_DMA_STREAM, + AT32_SPI_SPI3_IRQ_PRIORITY); + if (msg != HAL_RET_SUCCESS) { + return msg; + } + crmEnableSPI3(true); + crmResetSPI3(); +#if AT32_DMA_SUPPORTS_DMAMUX + dmaSetRequestSource(spip->dmarx, AT32_DMAMUX_SPI3_RX); + dmaSetRequestSource(spip->dmatx, AT32_DMAMUX_SPI3_TX); +#endif + } +#endif + else { osalDbgAssert(false, "invalid SPI instance"); } @@ -346,26 +393,26 @@ msg_t spi_lld_start(SPIDriver *spip) { /* Configuration-specific DMA setup.*/ if ((spip->config->ctrl1 & SPI_CTRL1_FBN) == 0) { /* Frame width is 8 bits or smaller.*/ - spip->rxdmamode = (spip->rxdmamode & ~AT32_DMA_CTRL_WIDTH_MASK) | - AT32_DMA_CTRL_PWIDTH_BYTE | AT32_DMA_CTRL_MWIDTH_BYTE; - spip->txdmamode = (spip->txdmamode & ~AT32_DMA_CTRL_WIDTH_MASK) | - AT32_DMA_CTRL_PWIDTH_BYTE | AT32_DMA_CTRL_MWIDTH_BYTE; + spip->rxdmamode = (spip->rxdmamode & ~AT32_DMA_CCTRL_SIZE_MASK) | + AT32_DMA_CCTRL_PWIDTH_BYTE | AT32_DMA_CCTRL_MWIDTH_BYTE; + spip->txdmamode = (spip->txdmamode & ~AT32_DMA_CCTRL_SIZE_MASK) | + AT32_DMA_CCTRL_PWIDTH_BYTE | AT32_DMA_CCTRL_MWIDTH_BYTE; } else { /* Frame width is larger than 8 bits.*/ - spip->rxdmamode = (spip->rxdmamode & ~AT32_DMA_CTRL_WIDTH_MASK) | - AT32_DMA_CTRL_PWIDTH_HWORD | AT32_DMA_CTRL_MWIDTH_HWORD; - spip->txdmamode = (spip->txdmamode & ~AT32_DMA_CTRL_WIDTH_MASK) | - AT32_DMA_CTRL_PWIDTH_HWORD | AT32_DMA_CTRL_MWIDTH_HWORD; + spip->rxdmamode = (spip->rxdmamode & ~AT32_DMA_CCTRL_SIZE_MASK) | + AT32_DMA_CCTRL_PWIDTH_HWORD | AT32_DMA_CCTRL_MWIDTH_HWORD; + spip->txdmamode = (spip->txdmamode & ~AT32_DMA_CCTRL_SIZE_MASK) | + AT32_DMA_CCTRL_PWIDTH_HWORD | AT32_DMA_CCTRL_MWIDTH_HWORD; } if (spip->config->circular) { - spip->rxdmamode |= (AT32_DMA_CTRL_LM | AT32_DMA_CTRL_HDTIEN); - spip->txdmamode |= (AT32_DMA_CTRL_LM | AT32_DMA_CTRL_HDTIEN); + spip->rxdmamode |= (AT32_DMA_CCTRL_LM | AT32_DMA_CCTRL_HDTIEN); + spip->txdmamode |= (AT32_DMA_CCTRL_LM | AT32_DMA_CCTRL_HDTIEN); } else { - spip->rxdmamode &= ~(AT32_DMA_CTRL_LM | AT32_DMA_CTRL_HDTIEN); - spip->txdmamode &= ~(AT32_DMA_CTRL_LM | AT32_DMA_CTRL_HDTIEN); + spip->rxdmamode &= ~(AT32_DMA_CCTRL_LM | AT32_DMA_CCTRL_HDTIEN); + spip->txdmamode &= ~(AT32_DMA_CCTRL_LM | AT32_DMA_CCTRL_HDTIEN); } /* SPI setup.*/ @@ -415,6 +462,12 @@ void spi_lld_stop(SPIDriver *spip) { } #endif +#if AT32_SPI_USE_SPI3 + else if (&SPID3 == spip) { + crmDisableSPI3(); + } +#endif + else { osalDbgAssert(false, "invalid SPI instance"); } @@ -502,11 +555,11 @@ msg_t spi_lld_exchange(SPIDriver *spip, size_t n, dmaStreamSetMemory0(spip->dmarx, rxbuf); dmaStreamSetTransactionSize(spip->dmarx, n); - dmaStreamSetMode(spip->dmarx, spip->rxdmamode | AT32_DMA_CTRL_MINCM); + dmaStreamSetMode(spip->dmarx, spip->rxdmamode | AT32_DMA_CCTRL_MINCM); dmaStreamSetMemory0(spip->dmatx, txbuf); dmaStreamSetTransactionSize(spip->dmatx, n); - dmaStreamSetMode(spip->dmatx, spip->txdmamode | AT32_DMA_CTRL_MINCM); + dmaStreamSetMode(spip->dmatx, spip->txdmamode | AT32_DMA_CCTRL_MINCM); dmaStreamEnable(spip->dmarx); dmaStreamEnable(spip->dmatx); @@ -538,7 +591,7 @@ msg_t spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) { dmaStreamSetMemory0(spip->dmatx, txbuf); dmaStreamSetTransactionSize(spip->dmatx, n); - dmaStreamSetMode(spip->dmatx, spip->txdmamode | AT32_DMA_CTRL_MINCM); + dmaStreamSetMode(spip->dmatx, spip->txdmamode | AT32_DMA_CCTRL_MINCM); dmaStreamEnable(spip->dmarx); dmaStreamEnable(spip->dmatx); @@ -566,7 +619,7 @@ msg_t spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) { dmaStreamSetMemory0(spip->dmarx, rxbuf); dmaStreamSetTransactionSize(spip->dmarx, n); - dmaStreamSetMode(spip->dmarx, spip->rxdmamode | AT32_DMA_CTRL_MINCM); + dmaStreamSetMode(spip->dmarx, spip->rxdmamode | AT32_DMA_CCTRL_MINCM); dmaStreamSetMemory0(spip->dmatx, &spip->txsource); dmaStreamSetTransactionSize(spip->dmatx, n); diff --git a/os/hal/ports/AT32/LLD/SPIv2/hal_spi_v2_lld.h b/os/hal/ports/AT32/LLD/SPIv2/hal_spi_v2_lld.h index 02f96a82ef..92bdde53f0 100644 --- a/os/hal/ports/AT32/LLD/SPIv2/hal_spi_v2_lld.h +++ b/os/hal/ports/AT32/LLD/SPIv2/hal_spi_v2_lld.h @@ -1,8 +1,8 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian - ChibiOS - Copyright (C) 2024 Maxjta + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + ChibiOS - Copyright (C) 2024..2025 Maxjta Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -71,6 +71,15 @@ #define AT32_SPI_USE_SPI2 FALSE #endif +/** + * @brief SPI3 driver enable switch. + * @details If set to @p TRUE the support for SPI3 is included. + * @note The default is @p FALSE. + */ +#if !defined(AT32_SPI_USE_SPI3) || defined(__DOXYGEN__) +#define AT32_SPI_USE_SPI3 FALSE +#endif + /** * @brief Filler pattern used when there is nothing to transmit. */ @@ -92,6 +101,13 @@ #define AT32_SPI_SPI2_IRQ_PRIORITY 10 #endif +/** + * @brief SPI3 interrupt priority level setting. + */ +#if !defined(AT32_SPI_SPI3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define AT32_SPI_SPI3_IRQ_PRIORITY 10 +#endif + /** * @brief SPI1 DMA priority (0..3|lowest..highest). * @note The priority level is used for both the TX and RX DMA streams but @@ -113,17 +129,20 @@ #endif /** - * @brief SPI DMA error hook. + * @brief SPI3 DMA priority (0..3|lowest..highest). + * @note The priority level is used for both the TX and RX DMA streams but + * because of the streams ordering the RX stream has always priority + * over the TX stream. */ -#if !defined(AT32_SPI_DMA_ERROR_HOOK) || defined(__DOXYGEN__) -#define AT32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") +#if !defined(AT32_SPI_SPI3_DMA_PRIORITY) || defined(__DOXYGEN__) +#define AT32_SPI_SPI3_DMA_PRIORITY 1 #endif /** - * @brief SPI DMA max transfer hook. + * @brief SPI DMA error hook. */ -#if !defined(AT32_DMA_MAX_TRANSFER) || defined(__DOXYGEN__) -#define AT32_DMA_MAX_TRANSFER 65536 +#if !defined(AT32_SPI_DMA_ERROR_HOOK) || defined(__DOXYGEN__) +#define AT32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") #endif /** @} */ @@ -139,7 +158,11 @@ #error "SPI2 not present in the selected device" #endif -#if !AT32_SPI_USE_SPI1 && !AT32_SPI_USE_SPI2 +#if AT32_SPI_USE_SPI3 && !AT32_HAS_SPI3 +#error "SPI3 not present in the selected device" +#endif + +#if !AT32_SPI_USE_SPI1 && !AT32_SPI_USE_SPI2 && !AT32_SPI_USE_SPI3 #error "SPI driver activated but no SPI peripheral assigned" #endif @@ -153,6 +176,33 @@ #error "Invalid IRQ priority assigned to SPI2" #endif +#if AT32_SPI_USE_SPI3 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(AT32_SPI_SPI3_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to SPI3" +#endif + +/* The following checks are only required when there is a DMA able to + reassign streams to different channels.*/ +#if AT32_ADVANCED_DMA + +/* Check on the presence of the DMA streams settings in mcuconf.h.*/ +#if AT32_SPI_USE_SPI1 && (!defined(AT32_SPI_SPI1_RX_DMA_STREAM) || \ + !defined(AT32_SPI_SPI1_TX_DMA_STREAM)) +#error "SPI1 DMA streams not defined" +#endif + +#if AT32_SPI_USE_SPI2 && (!defined(AT32_SPI_SPI2_RX_DMA_STREAM) || \ + !defined(AT32_SPI_SPI2_TX_DMA_STREAM)) +#error "SPI2 DMA streams not defined" +#endif + +#if AT32_SPI_USE_SPI3 && (!defined(AT32_SPI_SPI3_RX_DMA_STREAM) || \ + !defined(AT32_SPI_SPI3_TX_DMA_STREAM)) +#error "SPI3 DMA streams not defined" +#endif + +#endif /* AT32_ADVANCED_DMA */ + #if !defined(AT32_DMA_REQUIRED) #define AT32_DMA_REQUIRED #endif @@ -206,6 +256,10 @@ extern SPIDriver SPID1; extern SPIDriver SPID2; #endif +#if AT32_SPI_USE_SPI3 && !defined(__DOXYGEN__) +extern SPIDriver SPID3; +#endif + #ifdef __cplusplus extern "C" { #endif diff --git a/os/hal/ports/AT32/LLD/SYSTICKv1/hal_st_lld.c b/os/hal/ports/AT32/LLD/SYSTICKv1/hal_st_lld.c index 0ec4ae3e3e..7a8a277bda 100644 --- a/os/hal/ports/AT32/LLD/SYSTICKv1/hal_st_lld.c +++ b/os/hal/ports/AT32/LLD/SYSTICKv1/hal_st_lld.c @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -60,7 +60,11 @@ #define ST_NUMBER AT32_TMR1_CH_NUMBER #define ST_CLOCK_SRC AT32_TMRCLK2 #define ST_ENABLE_CLOCK() crmEnableTMR1(true) +#if defined(AT32F415) #define ST_ENABLE_PAUSE() DEBUG->CTRL |= DEBUG_CTRL_TMR1_PAUSE +#else +#define ST_ENABLE_PAUSE() DEBUG->APB2_PAUSE |= DEBUG_APB2_PAUSE_TMR1_PAUSE +#endif #elif AT32_ST_USE_TIMER == 2 @@ -76,7 +80,11 @@ #define ST_NUMBER AT32_TMR2_NUMBER #define ST_CLOCK_SRC AT32_TMRCLK1 #define ST_ENABLE_CLOCK() crmEnableTMR2(true) +#if defined(AT32F415) #define ST_ENABLE_PAUSE() DEBUG->CTRL |= DEBUG_CTRL_TMR2_PAUSE +#else +#define ST_ENABLE_PAUSE() DEBUG->APB1_PAUSE |= DEBUG_APB1_PAUSE_TMR2_PAUSE +#endif #elif AT32_ST_USE_TIMER == 3 @@ -92,7 +100,11 @@ #define ST_NUMBER AT32_TMR3_NUMBER #define ST_CLOCK_SRC AT32_TMRCLK1 #define ST_ENABLE_CLOCK() crmEnableTMR3(true) +#if defined(AT32F415) #define ST_ENABLE_PAUSE() DEBUG->CTRL |= DEBUG_CTRL_TMR3_PAUSE +#else +#define ST_ENABLE_PAUSE() DEBUG->APB1_PAUSE |= DEBUG_APB1_PAUSE_TMR3_PAUSE +#endif #elif AT32_ST_USE_TIMER == 4 @@ -108,7 +120,11 @@ #define ST_NUMBER AT32_TMR4_NUMBER #define ST_CLOCK_SRC AT32_TMRCLK1 #define ST_ENABLE_CLOCK() crmEnableTMR4(true) +#if defined(AT32F415) #define ST_ENABLE_PAUSE() DEBUG->CTRL |= DEBUG_CTRL_TMR4_PAUSE +#else +#define ST_ENABLE_PAUSE() DEBUG->APB1_PAUSE |= DEBUG_APB1_PAUSE_TMR4_PAUSE +#endif #elif AT32_ST_USE_TIMER == 5 @@ -124,7 +140,9 @@ #define ST_NUMBER AT32_TMR5_NUMBER #define ST_CLOCK_SRC AT32_TMRCLK1 #define ST_ENABLE_CLOCK() crmEnableTMR5(true) +#if defined(AT32F415) #define ST_ENABLE_PAUSE() DEBUG->CTRL |= DEBUG_CTRL_TMR5_PAUSE +#endif #elif AT32_ST_USE_TIMER == 9 @@ -140,7 +158,11 @@ #define ST_NUMBER AT32_TMR9_NUMBER #define ST_CLOCK_SRC AT32_TMRCLK2 #define ST_ENABLE_CLOCK() crmEnableTMR9(true) +#if defined(AT32F415) #define ST_ENABLE_PAUSE() DEBUG->CTRL |= DEBUG_CTRL_TMR9_PAUSE +#else +#define ST_ENABLE_PAUSE() DEBUG->APB2_PAUSE |= DEBUG_APB2_PAUSE_TMR9_PAUSE +#endif #elif AT32_ST_USE_TIMER == 10 @@ -156,7 +178,11 @@ #define ST_NUMBER AT32_TMR10_NUMBER #define ST_CLOCK_SRC AT32_TMRCLK2 #define ST_ENABLE_CLOCK() crmEnableTMR10(true) +#if defined(AT32F415) #define ST_ENABLE_PAUSE() DEBUG->CTRL |= DEBUG_CTRL_TMR10_PAUSE +#else +#define ST_ENABLE_PAUSE() DEBUG->APB2_PAUSE |= DEBUG_APB2_PAUSE_TMR10_PAUSE +#endif #elif AT32_ST_USE_TIMER == 11 @@ -172,7 +198,43 @@ #define ST_NUMBER AT32_TMR11_NUMBER #define ST_CLOCK_SRC AT32_TMRCLK2 #define ST_ENABLE_CLOCK() crmEnableTMR11(true) +#if defined(AT32F415) #define ST_ENABLE_PAUSE() DEBUG->CTRL |= DEBUG_CTRL_TMR11_PAUSE +#else +#define ST_ENABLE_PAUSE() DEBUG->APB2_PAUSE |= DEBUG_APB2_PAUSE_TMR11_PAUSE +#endif + +#elif AT32_ST_USE_TIMER == 13 + +#if !AT32_HAS_TMR13 +#error "TMR13 not present in the selected device" +#endif + +#if (OSAL_ST_RESOLUTION == 32) && !AT32_TMR13_IS_32BITS +#error "TMR13 is not a 32bits timer" +#endif + +#define ST_HANDLER AT32_TMR13_HANDLER +#define ST_NUMBER AT32_TMR13_NUMBER +#define ST_CLOCK_SRC AT32_TMRCLK1 +#define ST_ENABLE_CLOCK() crmEnableTMR13(true) +#define ST_ENABLE_PAUSE() DEBUG->APB1_PAUSE |= DEBUG_APB1_PAUSE_TMR13_PAUSE + +#elif AT32_ST_USE_TIMER == 14 + +#if !AT32_HAS_TMR14 +#error "TMR14 not present in the selected device" +#endif + +#if (OSAL_ST_RESOLUTION == 32) && !AT32_TMR14_IS_32BITS +#error "TMR14 is not a 32bits timer" +#endif + +#define ST_HANDLER AT32_TMR14_HANDLER +#define ST_NUMBER AT32_TMR14_NUMBER +#define ST_CLOCK_SRC AT32_TMRCLK1 +#define ST_ENABLE_CLOCK() crmEnableTMR14(true) +#define ST_ENABLE_PAUSE() DEBUG->APB1_PAUSE |= DEBUG_APB1_PAUSE_TMR14_PAUSE #else #error "AT32_ST_USE_TIMER specifies an unsupported timer" diff --git a/os/hal/ports/AT32/LLD/SYSTICKv1/hal_st_lld.h b/os/hal/ports/AT32/LLD/SYSTICKv1/hal_st_lld.h index c821d52232..c67f91d167 100644 --- a/os/hal/ports/AT32/LLD/SYSTICKv1/hal_st_lld.h +++ b/os/hal/ports/AT32/LLD/SYSTICKv1/hal_st_lld.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -110,6 +110,14 @@ #if !defined(AT32_HAS_TMR11) #define AT32_HAS_TMR11 FALSE #endif + +#if !defined(AT32_HAS_TMR13) +#define AT32_HAS_TMR13 FALSE +#endif + +#if !defined(AT32_HAS_TMR14) +#define AT32_HAS_TMR14 FALSE +#endif /* End of checks to be removed.*/ #if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING @@ -137,6 +145,8 @@ #define AT32_ST_USE_TMR9 FALSE #define AT32_ST_USE_TMR10 FALSE #define AT32_ST_USE_TMR11 FALSE +#define AT32_ST_USE_TMR13 FALSE +#define AT32_ST_USE_TMR14 FALSE #elif AT32_ST_USE_TIMER == 2 @@ -161,6 +171,8 @@ #define AT32_ST_USE_TMR9 FALSE #define AT32_ST_USE_TMR10 FALSE #define AT32_ST_USE_TMR11 FALSE +#define AT32_ST_USE_TMR13 FALSE +#define AT32_ST_USE_TMR14 FALSE #elif AT32_ST_USE_TIMER == 3 @@ -185,6 +197,8 @@ #define AT32_ST_USE_TMR9 FALSE #define AT32_ST_USE_TMR10 FALSE #define AT32_ST_USE_TMR11 FALSE +#define AT32_ST_USE_TMR13 FALSE +#define AT32_ST_USE_TMR14 FALSE #elif AT32_ST_USE_TIMER == 4 @@ -209,6 +223,8 @@ #define AT32_ST_USE_TMR9 FALSE #define AT32_ST_USE_TMR10 FALSE #define AT32_ST_USE_TMR11 FALSE +#define AT32_ST_USE_TMR13 FALSE +#define AT32_ST_USE_TMR14 FALSE #elif AT32_ST_USE_TIMER == 5 @@ -233,6 +249,8 @@ #define AT32_ST_USE_TMR9 FALSE #define AT32_ST_USE_TMR10 FALSE #define AT32_ST_USE_TMR11 FALSE +#define AT32_ST_USE_TMR13 FALSE +#define AT32_ST_USE_TMR14 FALSE #elif AT32_ST_USE_TIMER == 9 @@ -257,6 +275,8 @@ #define AT32_ST_USE_TMR9 TRUE #define AT32_ST_USE_TMR10 FALSE #define AT32_ST_USE_TMR11 FALSE +#define AT32_ST_USE_TMR13 FALSE +#define AT32_ST_USE_TMR14 FALSE #elif AT32_ST_USE_TIMER == 10 @@ -281,6 +301,8 @@ #define AT32_ST_USE_TMR9 FALSE #define AT32_ST_USE_TMR10 TRUE #define AT32_ST_USE_TMR11 FALSE +#define AT32_ST_USE_TMR13 FALSE +#define AT32_ST_USE_TMR14 FALSE #elif AT32_ST_USE_TIMER == 11 @@ -305,6 +327,60 @@ #define AT32_ST_USE_TMR9 FALSE #define AT32_ST_USE_TMR10 FALSE #define AT32_ST_USE_TMR11 TRUE +#define AT32_ST_USE_TMR13 FALSE +#define AT32_ST_USE_TMR14 FALSE + +#elif AT32_ST_USE_TIMER == 13 + +#if defined(AT32_TMR13_IS_USED) +#error "ST requires TMR13 but the timer is already used" +#else +#define AT32_TMR13_IS_USED +#endif + +#if defined(AT32_TMR13_SUPPRESS_ISR) +#define AT32_SYSTICK_SUPPRESS_ISR +#endif + +#define AT32_ST_TMR AT32_TMR13 +#define ST_LLD_NUM_ALARMS AT32_TMR13_CHANNELS +#define AT32_ST_USE_SYSTICK FALSE +#define AT32_ST_USE_TMR1 FALSE +#define AT32_ST_USE_TMR2 FALSE +#define AT32_ST_USE_TMR3 FALSE +#define AT32_ST_USE_TMR4 FALSE +#define AT32_ST_USE_TMR5 FALSE +#define AT32_ST_USE_TMR9 FALSE +#define AT32_ST_USE_TMR10 FALSE +#define AT32_ST_USE_TMR11 FALSE +#define AT32_ST_USE_TMR13 TRUE +#define AT32_ST_USE_TMR14 FALSE + +#elif AT32_ST_USE_TIMER == 14 + +#if defined(AT32_TMR14_IS_USED) +#error "ST requires TMR14 but the timer is already used" +#else +#define AT32_TMR14_IS_USED +#endif + +#if defined(AT32_TMR14_SUPPRESS_ISR) +#define AT32_SYSTICK_SUPPRESS_ISR +#endif + +#define AT32_ST_TMR AT32_TMR14 +#define ST_LLD_NUM_ALARMS AT32_TMR14_CHANNELS +#define AT32_ST_USE_SYSTICK FALSE +#define AT32_ST_USE_TMR1 FALSE +#define AT32_ST_USE_TMR2 FALSE +#define AT32_ST_USE_TMR3 FALSE +#define AT32_ST_USE_TMR4 FALSE +#define AT32_ST_USE_TMR5 FALSE +#define AT32_ST_USE_TMR9 FALSE +#define AT32_ST_USE_TMR10 FALSE +#define AT32_ST_USE_TMR11 FALSE +#define AT32_ST_USE_TMR13 FALSE +#define AT32_ST_USE_TMR14 TRUE #else #error "AT32_ST_USE_TIMER specifies an unsupported timer" @@ -331,6 +407,8 @@ #define AT32_ST_USE_TMR9 FALSE #define AT32_ST_USE_TMR10 FALSE #define AT32_ST_USE_TMR11 FALSE +#define AT32_ST_USE_TMR13 FALSE +#define AT32_ST_USE_TMR14 FALSE #else @@ -343,6 +421,8 @@ #define AT32_ST_USE_TMR9 FALSE #define AT32_ST_USE_TMR10 FALSE #define AT32_ST_USE_TMR11 FALSE +#define AT32_ST_USE_TMR13 FALSE +#define AT32_ST_USE_TMR14 FALSE #endif diff --git a/os/hal/ports/AT32/LLD/TMRv1/at32_tmr.h b/os/hal/ports/AT32/LLD/TMRv1/at32_tmr.h index 18411700c0..9768a3d005 100644 --- a/os/hal/ports/AT32/LLD/TMRv1/at32_tmr.h +++ b/os/hal/ports/AT32/LLD/TMRv1/at32_tmr.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -126,7 +126,6 @@ AT32_TMR_IDEN_HALLIEN | \ AT32_TMR_IDEN_TIEN | \ AT32_TMR_IDEN_BRKIE) - /** @} */ /** @@ -285,6 +284,9 @@ #define AT32_TMR_BRK_BRKV (1U << 13) #define AT32_TMR_BRK_AOEN (1U << 14) #define AT32_TMR_BRK_OEN (1U << 15) + +#define AT32_TMR_BRK_BKF_MASK (15U << 16) +#define AT32_TMR_BRK_BKF(n) ((n) << 16) /** @} */ /** @@ -307,9 +309,13 @@ #define AT32_TMR3 ((at32_tmr_t *)TMR3_BASE) #define AT32_TMR4 ((at32_tmr_t *)TMR4_BASE) #define AT32_TMR5 ((at32_tmr_t *)TMR5_BASE) +#define AT32_TMR6 ((at32_tmr_t *)TMR6_BASE) +#define AT32_TMR7 ((at32_tmr_t *)TMR7_BASE) #define AT32_TMR9 ((at32_tmr_t *)TMR9_BASE) #define AT32_TMR10 ((at32_tmr_t *)TMR10_BASE) #define AT32_TMR11 ((at32_tmr_t *)TMR11_BASE) +#define AT32_TMR13 ((at32_tmr_t *)TMR13_BASE) +#define AT32_TMR14 ((at32_tmr_t *)TMR14_BASE) /** @} */ /*===========================================================================*/ @@ -347,6 +353,7 @@ typedef struct { volatile uint32_t BRK; volatile uint32_t DMACTRL; volatile uint32_t DMADT; + volatile uint32_t RMP; } at32_tmr_t; /*===========================================================================*/ diff --git a/os/hal/ports/AT32/LLD/TMRv1/at32_tmr13.inc b/os/hal/ports/AT32/LLD/TMRv1/at32_tmr13.inc index e55972480b..1c3f22680b 100644 --- a/os/hal/ports/AT32/LLD/TMRv1/at32_tmr13.inc +++ b/os/hal/ports/AT32/LLD/TMRv1/at32_tmr13.inc @@ -1,8 +1,8 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian - ChibiOS - Copyright (C) 2023..2024 Maxjta + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + ChibiOS - Copyright (C) 2024..2025 Maxjta Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -41,16 +41,16 @@ /* Driver checks for robustness, undefined USE macros are defaulted to FALSE. This makes this module independent from drivers implementation.*/ #if !defined(AT32_GPT_USE_TMR13) -#define AT32_GPT_USE_TMR13 FALSE +#define AT32_GPT_USE_TMR13 FALSE #endif #if !defined(AT32_ICU_USE_TMR13) -#define AT32_ICU_USE_TMR13 FALSE +#define AT32_ICU_USE_TMR13 FALSE #endif #if !defined(AT32_PWM_USE_TMR13) -#define AT32_PWM_USE_TMR13 FALSE +#define AT32_PWM_USE_TMR13 FALSE #endif #if !defined(AT32_ST_USE_TMR13) -#define AT32_ST_USE_TMR13 FALSE +#define AT32_ST_USE_TMR13 FALSE #endif #if AT32_HAS_TMR13 diff --git a/os/hal/ports/AT32/LLD/TMRv1/at32_tmr14.inc b/os/hal/ports/AT32/LLD/TMRv1/at32_tmr14.inc index 4b70b97a64..c5c1c2ffb2 100644 --- a/os/hal/ports/AT32/LLD/TMRv1/at32_tmr14.inc +++ b/os/hal/ports/AT32/LLD/TMRv1/at32_tmr14.inc @@ -1,8 +1,8 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian - ChibiOS - Copyright (C) 2023..2024 Maxjta + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + ChibiOS - Copyright (C) 2024..2025 Maxjta Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -41,16 +41,16 @@ /* Driver checks for robustness, undefined USE macros are defaulted to FALSE. This makes this module independent from drivers implementation.*/ #if !defined(AT32_GPT_USE_TMR14) -#define AT32_GPT_USE_TMR14 FALSE +#define AT32_GPT_USE_TMR14 FALSE #endif #if !defined(AT32_ICU_USE_TMR14) -#define AT32_ICU_USE_TMR14 FALSE +#define AT32_ICU_USE_TMR14 FALSE #endif #if !defined(AT32_PWM_USE_TMR14) -#define AT32_PWM_USE_TMR14 FALSE +#define AT32_PWM_USE_TMR14 FALSE #endif #if !defined(AT32_ST_USE_TMR14) -#define AT32_ST_USE_TMR14 FALSE +#define AT32_ST_USE_TMR14 FALSE #endif #if AT32_HAS_TMR14 diff --git a/os/hal/ports/AT32/LLD/TMRv1/at32_tmr1_9_10_11.inc b/os/hal/ports/AT32/LLD/TMRv1/at32_tmr1_9_10_11.inc index d4d536d15b..f1fb9baf05 100644 --- a/os/hal/ports/AT32/LLD/TMRv1/at32_tmr1_9_10_11.inc +++ b/os/hal/ports/AT32/LLD/TMRv1/at32_tmr1_9_10_11.inc @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/TMRv1/at32_tmr2.inc b/os/hal/ports/AT32/LLD/TMRv1/at32_tmr2.inc index 6198264c28..4ddac9bbd6 100644 --- a/os/hal/ports/AT32/LLD/TMRv1/at32_tmr2.inc +++ b/os/hal/ports/AT32/LLD/TMRv1/at32_tmr2.inc @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/TMRv1/at32_tmr3.inc b/os/hal/ports/AT32/LLD/TMRv1/at32_tmr3.inc index 5c2ea3954e..557ced5f4c 100644 --- a/os/hal/ports/AT32/LLD/TMRv1/at32_tmr3.inc +++ b/os/hal/ports/AT32/LLD/TMRv1/at32_tmr3.inc @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/TMRv1/at32_tmr4.inc b/os/hal/ports/AT32/LLD/TMRv1/at32_tmr4.inc index dbecd46685..48cc110f4f 100644 --- a/os/hal/ports/AT32/LLD/TMRv1/at32_tmr4.inc +++ b/os/hal/ports/AT32/LLD/TMRv1/at32_tmr4.inc @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/TMRv1/at32_tmr5.inc b/os/hal/ports/AT32/LLD/TMRv1/at32_tmr5.inc index 36ad2208bf..772037c1f2 100644 --- a/os/hal/ports/AT32/LLD/TMRv1/at32_tmr5.inc +++ b/os/hal/ports/AT32/LLD/TMRv1/at32_tmr5.inc @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/TMRv1/at32_tmr6.inc b/os/hal/ports/AT32/LLD/TMRv1/at32_tmr6.inc index aac92e5593..5f1298b7b6 100644 --- a/os/hal/ports/AT32/LLD/TMRv1/at32_tmr6.inc +++ b/os/hal/ports/AT32/LLD/TMRv1/at32_tmr6.inc @@ -1,8 +1,8 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian - ChibiOS - Copyright (C) 2023..2024 Maxjta + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + ChibiOS - Copyright (C) 2024..2025 Maxjta Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/TMRv1/at32_tmr7.inc b/os/hal/ports/AT32/LLD/TMRv1/at32_tmr7.inc index 6e2317d06b..f1f9807660 100644 --- a/os/hal/ports/AT32/LLD/TMRv1/at32_tmr7.inc +++ b/os/hal/ports/AT32/LLD/TMRv1/at32_tmr7.inc @@ -1,8 +1,8 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian - ChibiOS - Copyright (C) 2023..2024 Maxjta + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + ChibiOS - Copyright (C) 2024..2025 Maxjta Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/TMRv1/hal_gpt_lld.c b/os/hal/ports/AT32/LLD/TMRv1/hal_gpt_lld.c index 6c43aecdfb..b49a18baf7 100644 --- a/os/hal/ports/AT32/LLD/TMRv1/hal_gpt_lld.c +++ b/os/hal/ports/AT32/LLD/TMRv1/hal_gpt_lld.c @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -76,6 +76,22 @@ GPTDriver GPTD4; GPTDriver GPTD5; #endif +/** + * @brief GPTD6 driver identifier. + * @note The driver GPTD6 allocates the timer TMR6 when enabled. + */ +#if AT32_GPT_USE_TMR6 || defined(__DOXYGEN__) +GPTDriver GPTD6; +#endif + +/** + * @brief GPTD7 driver identifier. + * @note The driver GPTD7 allocates the timer TMR7 when enabled. + */ +#if AT32_GPT_USE_TMR7 || defined(__DOXYGEN__) +GPTDriver GPTD7; +#endif + /** * @brief GPTD9 driver identifier. * @note The driver GPTD9 allocates the timer TMR9 when enabled. @@ -100,6 +116,22 @@ GPTDriver GPTD10; GPTDriver GPTD11; #endif +/** + * @brief GPTD13 driver identifier. + * @note The driver GPTD13 allocates the timer TMR13 when enabled. + */ +#if AT32_GPT_USE_TMR13 || defined(__DOXYGEN__) +GPTDriver GPTD13; +#endif + +/** + * @brief GPTD14 driver identifier. + * @note The driver GPTD14 allocates the timer TMR14 when enabled. + */ +#if AT32_GPT_USE_TMR14 || defined(__DOXYGEN__) +GPTDriver GPTD14; +#endif + /*===========================================================================*/ /* Driver local variables and types. */ /*===========================================================================*/ @@ -217,6 +249,48 @@ OSAL_IRQ_HANDLER(AT32_TMR5_HANDLER) { #endif /* !defined(AT32_TMR5_SUPPRESS_ISR) */ #endif /* AT32_GPT_USE_TMR5 */ +#if AT32_GPT_USE_TMR6 || defined(__DOXYGEN__) +#if !defined(AT32_TMR6_SUPPRESS_ISR) +#if !defined(AT32_TMR6_HANDLER) +#error "AT32_TMR6_HANDLER not defined" +#endif +/** + * @brief TMR6 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_TMR6_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD6); + + OSAL_IRQ_EPILOGUE(); +} +#endif /* !defined(AT32_TMR6_SUPPRESS_ISR) */ +#endif /* AT32_GPT_USE_TMR6 */ + +#if AT32_GPT_USE_TMR7 || defined(__DOXYGEN__) +#if !defined(AT32_TMR7_SUPPRESS_ISR) +#if !defined(AT32_TMR7_HANDLER) +#error "AT32_TMR7_HANDLER not defined" +#endif +/** + * @brief TMR7 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(AT32_TMR7_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD7); + + OSAL_IRQ_EPILOGUE(); +} +#endif /* !defined(AT32_TMR7_SUPPRESS_ISR) */ +#endif /* AT32_GPT_USE_TMR7 */ + #if AT32_GPT_USE_TMR9 || defined(__DOXYGEN__) #if !defined(AT32_TMR9_SUPPRESS_ISR) #error "TMR9 ISR not defined by platform" @@ -235,6 +309,18 @@ OSAL_IRQ_HANDLER(AT32_TMR5_HANDLER) { #endif /* !defined(AT32_TMR11_SUPPRESS_ISR) */ #endif /* AT32_GPT_USE_TMR11 */ +#if AT32_GPT_USE_TMR13 || defined(__DOXYGEN__) +#if !defined(AT32_TMR13_SUPPRESS_ISR) +#error "TMR13 ISR not defined by platform" +#endif /* !defined(AT32_TMR13_SUPPRESS_ISR) */ +#endif /* AT32_GPT_USE_TMR13 */ + +#if AT32_GPT_USE_TMR14 || defined(__DOXYGEN__) +#if !defined(AT32_TMR14_SUPPRESS_ISR) +#error "TMR14 ISR not defined by platform" +#endif /* !defined(AT32_TMR14_SUPPRESS_ISR) */ +#endif /* AT32_GPT_USE_TMR14 */ + /*===========================================================================*/ /* Driver exported functions. */ /*===========================================================================*/ @@ -281,6 +367,20 @@ void gpt_lld_init(void) { gptObjectInit(&GPTD5); #endif +#if AT32_GPT_USE_TMR6 + /* Driver initialization.*/ + GPTD6.tmr = AT32_TMR6; + GPTD6.has_plus_mode = (bool)AT32_TMR6_IS_32BITS; + gptObjectInit(&GPTD6); +#endif + +#if AT32_GPT_USE_TMR7 + /* Driver initialization.*/ + GPTD7.tmr = AT32_TMR7; + GPTD7.has_plus_mode = (bool)AT32_TMR7_IS_32BITS; + gptObjectInit(&GPTD7); +#endif + #if AT32_GPT_USE_TMR9 /* Driver initialization.*/ GPTD9.tmr = AT32_TMR9; @@ -301,6 +401,20 @@ void gpt_lld_init(void) { GPTD11.has_plus_mode = (bool)AT32_TMR11_IS_32BITS; gptObjectInit(&GPTD11); #endif + +#if AT32_GPT_USE_TMR13 + /* Driver initialization.*/ + GPTD13.tmr = AT32_TMR13; + GPTD13.has_plus_mode = (bool)AT32_TMR13_IS_32BITS; + gptObjectInit(&GPTD13); +#endif + +#if AT32_GPT_USE_TMR14 + /* Driver initialization.*/ + GPTD14.tmr = AT32_TMR14; + GPTD14.has_plus_mode = (bool)AT32_TMR14_IS_32BITS; + gptObjectInit(&GPTD14); +#endif } /** @@ -370,6 +484,28 @@ void gpt_lld_start(GPTDriver *gptp) { } #endif +#if AT32_GPT_USE_TMR6 + if (&GPTD6 == gptp) { + crmEnableTMR6(true); + crmResetTMR6(); +#if !defined(AT32_TMR6_SUPPRESS_ISR) + nvicEnableVector(AT32_TMR6_NUMBER, AT32_GPT_TMR6_IRQ_PRIORITY); +#endif + gptp->clock = AT32_TMRCLK1; + } +#endif + +#if AT32_GPT_USE_TMR7 + if (&GPTD7 == gptp) { + crmEnableTMR7(true); + crmResetTMR7(); +#if !defined(AT32_TMR7_SUPPRESS_ISR) + nvicEnableVector(AT32_TMR7_NUMBER, AT32_GPT_TMR7_IRQ_PRIORITY); +#endif + gptp->clock = AT32_TMRCLK1; + } +#endif + #if AT32_GPT_USE_TMR9 if (&GPTD9 == gptp) { crmEnableTMR9(true); @@ -402,6 +538,28 @@ void gpt_lld_start(GPTDriver *gptp) { gptp->clock = AT32_TMRCLK2; } #endif + +#if AT32_GPT_USE_TMR13 + if (&GPTD13 == gptp) { + crmEnableTMR13(true); + crmResetTMR13(); +#if !defined(AT32_TMR13_SUPPRESS_ISR) + nvicEnableVector(AT32_TMR13_NUMBER, AT32_GPT_TMR13_IRQ_PRIORITY); +#endif + gptp->clock = AT32_TMRCLK1; + } +#endif + +#if AT32_GPT_USE_TMR14 + if (&GPTD14 == gptp) { + crmEnableTMR14(true); + crmResetTMR14(); +#if !defined(AT32_TMR14_SUPPRESS_ISR) + nvicEnableVector(AT32_TMR14_NUMBER, AT32_GPT_TMR14_IRQ_PRIORITY); +#endif + gptp->clock = AT32_TMRCLK1; + } +#endif } /* Prescaler value calculation.*/ @@ -484,6 +642,24 @@ void gpt_lld_stop(GPTDriver *gptp) { } #endif +#if AT32_GPT_USE_TMR6 + if (&GPTD6 == gptp) { +#if !defined(AT32_TMR6_SUPPRESS_ISR) + nvicDisableVector(AT32_TMR6_NUMBER); +#endif + crmDisableTMR6(); + } +#endif + +#if AT32_GPT_USE_TMR7 + if (&GPTD7 == gptp) { +#if !defined(AT32_TMR7_SUPPRESS_ISR) + nvicDisableVector(AT32_TMR7_NUMBER); +#endif + crmDisableTMR7(); + } +#endif + #if AT32_GPT_USE_TMR9 if (&GPTD9 == gptp) { #if !defined(AT32_TMR9_SUPPRESS_ISR) @@ -510,11 +686,30 @@ void gpt_lld_stop(GPTDriver *gptp) { crmDisableTMR11(); } #endif + +#if AT32_GPT_USE_TMR13 + if (&GPTD13 == gptp) { +#if !defined(AT32_TMR13_SUPPRESS_ISR) + nvicDisableVector(AT32_TMR13_NUMBER); +#endif + crmDisableTMR13(); + } +#endif + +#if AT32_GPT_USE_TMR14 + if (&GPTD14 == gptp) { +#if !defined(AT32_TMR14_SUPPRESS_ISR) + nvicDisableVector(AT32_TMR14_NUMBER); +#endif + crmDisableTMR14(); + } +#endif } } /** * @brief Starts the timer in continuous mode. + * @note Interval values 0 and 1 are invalid on this architecture. * * @param[in] gptp pointer to the @p GPTDriver object * @param[in] interval period in ticks @@ -523,6 +718,8 @@ void gpt_lld_stop(GPTDriver *gptp) { */ void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) { + osalDbgAssert(interval > (gptcnt_t)0, "invalid interval"); + gptp->tmr->PR = (uint32_t)(interval - 1U); /* Time constant. */ gptp->tmr->SWEVT = AT32_TMR_SWEVT_OVFSWTR; /* Update event. */ gptp->tmr->CVAL = 0U; /* Reset counter. */ @@ -557,6 +754,7 @@ void gpt_lld_stop_timer(GPTDriver *gptp) { * @details This function specifically polls the timer waiting for completion * in order to not have extra delays caused by interrupt servicing, * this function is only recommended for short delays. + * @note Interval values 0 and 1 are invalid on this architecture. * * @param[in] gptp pointer to the @p GPTDriver object * @param[in] interval time interval in ticks @@ -565,6 +763,8 @@ void gpt_lld_stop_timer(GPTDriver *gptp) { */ void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval) { + osalDbgAssert(interval > (gptcnt_t)0, "invalid interval"); + gptp->tmr->CTRL1 = AT32_TMR_CTRL1_OVFEN; /* Immediate update. */ gptp->tmr->PR = (uint32_t)(interval - 1U); /* Time constant. */ gptp->tmr->SWEVT = AT32_TMR_SWEVT_OVFSWTR; /* Update event. */ diff --git a/os/hal/ports/AT32/LLD/TMRv1/hal_gpt_lld.h b/os/hal/ports/AT32/LLD/TMRv1/hal_gpt_lld.h index d3ba5ffb65..fb5cf7d3e9 100644 --- a/os/hal/ports/AT32/LLD/TMRv1/hal_gpt_lld.h +++ b/os/hal/ports/AT32/LLD/TMRv1/hal_gpt_lld.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -88,6 +88,24 @@ #define AT32_GPT_USE_TMR5 FALSE #endif +/** + * @brief GPTD6 driver enable switch. + * @details If set to @p TRUE the support for GPTD6 is included. + * @note The default is @p FALSE. + */ +#if !defined(AT32_GPT_USE_TMR6) || defined(__DOXYGEN__) +#define AT32_GPT_USE_TMR6 FALSE +#endif + +/** + * @brief GPTD7 driver enable switch. + * @details If set to @p TRUE the support for GPTD7 is included. + * @note The default is @p FALSE. + */ +#if !defined(AT32_GPT_USE_TMR7) || defined(__DOXYGEN__) +#define AT32_GPT_USE_TMR7 FALSE +#endif + /** * @brief GPTD9 driver enable switch. * @details If set to @p TRUE the support for GPTD9 is included. @@ -115,6 +133,24 @@ #define AT32_GPT_USE_TMR11 FALSE #endif +/** + * @brief GPTD13 driver enable switch. + * @details If set to @p TRUE the support for GPTD13 is included. + * @note The default is @p FALSE. + */ +#if !defined(AT32_GPT_USE_TMR13) || defined(__DOXYGEN__) +#define AT32_GPT_USE_TMR13 FALSE +#endif + +/** + * @brief GPTD14 driver enable switch. + * @details If set to @p TRUE the support for GPTD14 is included. + * @note The default is @p FALSE. + */ +#if !defined(AT32_GPT_USE_TMR14) || defined(__DOXYGEN__) +#define AT32_GPT_USE_TMR14 FALSE +#endif + /** * @brief GPTD1 interrupt priority level setting. */ @@ -150,6 +186,20 @@ #define AT32_GPT_TMR5_IRQ_PRIORITY 7 #endif +/** + * @brief GPTD6 interrupt priority level setting. + */ +#if !defined(AT32_GPT_TMR6_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define AT32_GPT_TMR6_IRQ_PRIORITY 7 +#endif + +/** + * @brief GPTD7 interrupt priority level setting. + */ +#if !defined(AT32_GPT_TMR7_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define AT32_GPT_TMR7_IRQ_PRIORITY 7 +#endif + /** * @brief GPTD9 interrupt priority level setting. */ @@ -170,6 +220,20 @@ #if !defined(AT32_GPT_TMR11_IRQ_PRIORITY) || defined(__DOXYGEN__) #define AT32_GPT_TMR11_IRQ_PRIORITY 7 #endif + +/** + * @brief GPTD13 interrupt priority level setting. + */ +#if !defined(AT32_GPT_TMR13_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define AT32_GPT_TMR13_IRQ_PRIORITY 7 +#endif + +/** + * @brief GPTD14 interrupt priority level setting. + */ +#if !defined(AT32_GPT_TMR14_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define AT32_GPT_TMR14_IRQ_PRIORITY 7 +#endif /** @} */ /*===========================================================================*/ @@ -196,6 +260,14 @@ #define AT32_HAS_TMR5 FALSE #endif +#if !defined(AT32_HAS_TMR6) +#define AT32_HAS_TMR6 FALSE +#endif + +#if !defined(AT32_HAS_TMR7) +#define AT32_HAS_TMR7 FALSE +#endif + #if !defined(AT32_HAS_TMR9) #define AT32_HAS_TMR9 FALSE #endif @@ -208,6 +280,14 @@ #define AT32_HAS_TMR11 FALSE #endif +#if !defined(AT32_HAS_TMR13) +#define AT32_HAS_TMR13 FALSE +#endif + +#if !defined(AT32_HAS_TMR14) +#define AT32_HAS_TMR14 FALSE +#endif + #if AT32_GPT_USE_TMR1 && !AT32_HAS_TMR1 #error "TMR1 not present in the selected device" #endif @@ -228,6 +308,14 @@ #error "TMR5 not present in the selected device" #endif +#if AT32_GPT_USE_TMR6 && !AT32_HAS_TMR6 +#error "TMR6 not present in the selected device" +#endif + +#if AT32_GPT_USE_TMR7 && !AT32_HAS_TMR7 +#error "TMR7 not present in the selected device" +#endif + #if AT32_GPT_USE_TMR9 && !AT32_HAS_TMR9 #error "TMR9 not present in the selected device" #endif @@ -240,10 +328,20 @@ #error "TMR11 not present in the selected device" #endif +#if AT32_GPT_USE_TMR13 && !AT32_HAS_TMR13 +#error "TMR13 not present in the selected device" +#endif + +#if AT32_GPT_USE_TMR14 && !AT32_HAS_TMR14 +#error "TMR14 not present in the selected device" +#endif + #if !AT32_GPT_USE_TMR1 && !AT32_GPT_USE_TMR2 && \ !AT32_GPT_USE_TMR3 && !AT32_GPT_USE_TMR4 && \ - !AT32_GPT_USE_TMR5 && !AT32_GPT_USE_TMR9 && \ - !AT32_GPT_USE_TMR10 && !AT32_GPT_USE_TMR11 + !AT32_GPT_USE_TMR5 && !AT32_GPT_USE_TMR6 && \ + !AT32_GPT_USE_TMR7 && !AT32_GPT_USE_TMR9 && \ + !AT32_GPT_USE_TMR10 && !AT32_GPT_USE_TMR11 && \ + !AT32_GPT_USE_TMR13 && !AT32_GPT_USE_TMR14 #error "GPT driver activated but no TMR peripheral assigned" #endif @@ -288,6 +386,22 @@ #endif #endif +#if AT32_GPT_USE_TMR6 +#if defined(AT32_TMR6_IS_USED) +#error "GPTD6 requires TMR6 but the timer is already used" +#else +#define AT32_TMR6_IS_USED +#endif +#endif + +#if AT32_GPT_USE_TMR7 +#if defined(AT32_TMR7_IS_USED) +#error "GPTD7 requires TMR7 but the timer is already used" +#else +#define AT32_TMR7_IS_USED +#endif +#endif + #if AT32_GPT_USE_TMR9 #if defined(AT32_TMR9_IS_USED) #error "GPTD9 requires TMR9 but the timer is already used" @@ -312,6 +426,22 @@ #endif #endif +#if AT32_GPT_USE_TMR13 +#if defined(AT32_TMR13_IS_USED) +#error "GPTD13 requires TMR13 but the timer is already used" +#else +#define AT32_TMR13_IS_USED +#endif +#endif + +#if AT32_GPT_USE_TMR14 +#if defined(AT32_TMR14_IS_USED) +#error "GPTD14 requires TMR14 but the timer is already used" +#else +#define AT32_TMR14_IS_USED +#endif +#endif + /* IRQ priority checks.*/ #if AT32_GPT_USE_TMR1 && !defined(AT32_TMR1_SUPPRESS_ISR) && \ !OSAL_IRQ_IS_VALID_PRIORITY(AT32_GPT_TMR1_IRQ_PRIORITY) @@ -338,6 +468,16 @@ #error "Invalid IRQ priority assigned to TMR5" #endif +#if AT32_GPT_USE_TMR6 && !defined(AT32_TMR6_SUPPRESS_ISR) && \ + !OSAL_IRQ_IS_VALID_PRIORITY(AT32_GPT_TMR6_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to TMR6" +#endif + +#if AT32_GPT_USE_TMR7 && !defined(AT32_TMR7_SUPPRESS_ISR) && \ + !OSAL_IRQ_IS_VALID_PRIORITY(AT32_GPT_TMR7_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to TMR7" +#endif + #if AT32_GPT_USE_TMR9 && !defined(AT32_TMR9_SUPPRESS_ISR) && \ !OSAL_IRQ_IS_VALID_PRIORITY(AT32_GPT_TMR9_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to TMR9" @@ -353,6 +493,16 @@ #error "Invalid IRQ priority assigned to TMR11" #endif +#if AT32_GPT_USE_TMR13 && !defined(AT32_TMR13_SUPPRESS_ISR) && \ + !OSAL_IRQ_IS_VALID_PRIORITY(AT32_GPT_TMR13_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to TMR13" +#endif + +#if AT32_GPT_USE_TMR14 && !defined(AT32_TMR14_SUPPRESS_ISR) && \ + !OSAL_IRQ_IS_VALID_PRIORITY(AT32_GPT_TMR14_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to TMR14" +#endif + /*===========================================================================*/ /* Driver data structures and types. */ /*===========================================================================*/ @@ -496,6 +646,14 @@ extern GPTDriver GPTD4; extern GPTDriver GPTD5; #endif +#if AT32_GPT_USE_TMR6 && !defined(__DOXYGEN__) +extern GPTDriver GPTD6; +#endif + +#if AT32_GPT_USE_TMR7 && !defined(__DOXYGEN__) +extern GPTDriver GPTD7; +#endif + #if AT32_GPT_USE_TMR9 && !defined(__DOXYGEN__) extern GPTDriver GPTD9; #endif @@ -508,6 +666,14 @@ extern GPTDriver GPTD10; extern GPTDriver GPTD11; #endif +#if AT32_GPT_USE_TMR13 && !defined(__DOXYGEN__) +extern GPTDriver GPTD13; +#endif + +#if AT32_GPT_USE_TMR14 && !defined(__DOXYGEN__) +extern GPTDriver GPTD14; +#endif + #ifdef __cplusplus extern "C" { #endif diff --git a/os/hal/ports/AT32/LLD/TMRv1/hal_icu_lld.c b/os/hal/ports/AT32/LLD/TMRv1/hal_icu_lld.c index 4637ae3c39..39f3c30955 100644 --- a/os/hal/ports/AT32/LLD/TMRv1/hal_icu_lld.c +++ b/os/hal/ports/AT32/LLD/TMRv1/hal_icu_lld.c @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -104,6 +104,22 @@ ICUDriver ICUD10; ICUDriver ICUD11; #endif +/** + * @brief ICUD13 driver identifier. + * @note The driver ICUD13 allocates the timer TMR13 when enabled. + */ +#if AT32_ICU_USE_TMR13 || defined(__DOXYGEN__) +ICUDriver ICUD13; +#endif + +/** + * @brief ICUD14 driver identifier. + * @note The driver ICUD14 allocates the timer TMR14 when enabled. + */ +#if AT32_ICU_USE_TMR14 || defined(__DOXYGEN__) +ICUDriver ICUD14; +#endif + /*===========================================================================*/ /* Driver local variables and types. */ /*===========================================================================*/ @@ -292,6 +308,18 @@ OSAL_IRQ_HANDLER(AT32_TMR5_HANDLER) { #endif /* !defined(AT32_TMR11_SUPPRESS_ISR) */ #endif /* AT32_ICU_USE_TMR11 */ +#if AT32_ICU_USE_TMR13 || defined(__DOXYGEN__) +#if !defined(AT32_TMR13_SUPPRESS_ISR) +#error "TMR13 ISR not defined by platform" +#endif /* !defined(AT32_TMR13_SUPPRESS_ISR) */ +#endif /* AT32_ICU_USE_TMR13 */ + +#if AT32_ICU_USE_TMR14 || defined(__DOXYGEN__) +#if !defined(AT32_TMR14_SUPPRESS_ISR) +#error "TMR14 ISR not defined by platform" +#endif /* !defined(AT32_TMR14_SUPPRESS_ISR) */ +#endif /* AT32_ICU_USE_TMR14 */ + /*===========================================================================*/ /* Driver exported functions. */ /*===========================================================================*/ @@ -358,6 +386,20 @@ void icu_lld_init(void) { ICUD11.tmr = AT32_TMR11; ICUD11.has_plus_mode = (bool)AT32_TMR11_IS_32BITS; #endif + +#if AT32_ICU_USE_TMR13 + /* Driver initialization.*/ + icuObjectInit(&ICUD13); + ICUD13.tmr = AT32_TMR13; + ICUD13.has_plus_mode = (bool)AT32_TMR13_IS_32BITS; +#endif + +#if AT32_ICU_USE_TMR14 + /* Driver initialization.*/ + icuObjectInit(&ICUD14); + ICUD14.tmr = AT32_TMR14; + ICUD14.has_plus_mode = (bool)AT32_TMR14_IS_32BITS; +#endif } /** @@ -406,7 +448,7 @@ void icu_lld_start(ICUDriver *icup) { #if !defined(AT32_TMR3_SUPPRESS_ISR) nvicEnableVector(AT32_TMR3_NUMBER, AT32_ICU_TMR3_IRQ_PRIORITY); #endif - icup->clock = AT32_TMRCLK1; + icup->clock = AT32_TMRCLK1; } #endif @@ -455,6 +497,22 @@ void icu_lld_start(ICUDriver *icup) { icup->clock = AT32_TMRCLK2; } #endif + +#if AT32_ICU_USE_TMR13 + if (&ICUD13 == icup) { + crmEnableTMR13(true); + crmResetTMR13(); + icup->clock = AT32_TMRCLK1; + } +#endif + +#if AT32_ICU_USE_TMR14 + if (&ICUD14 == icup) { + crmEnableTMR14(true); + crmResetTMR14(); + icup->clock = AT32_TMRCLK1; + } +#endif } else { /* Driver re-configuration scenario, it must be stopped first.*/ @@ -617,6 +675,18 @@ void icu_lld_stop(ICUDriver *icup) { crmDisableTMR11(); } #endif + +#if AT32_ICU_USE_TMR13 + if (&ICUD13 == icup) { + crmDisableTMR13(); + } +#endif + +#if AT32_ICU_USE_TMR14 + if (&ICUD14 == icup) { + crmDisableTMR14(); + } +#endif } } diff --git a/os/hal/ports/AT32/LLD/TMRv1/hal_icu_lld.h b/os/hal/ports/AT32/LLD/TMRv1/hal_icu_lld.h index b101125433..137cb24401 100644 --- a/os/hal/ports/AT32/LLD/TMRv1/hal_icu_lld.h +++ b/os/hal/ports/AT32/LLD/TMRv1/hal_icu_lld.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -115,6 +115,24 @@ #define AT32_ICU_USE_TMR11 FALSE #endif +/** + * @brief ICUD13 driver enable switch. + * @details If set to @p TRUE the support for ICUD13 is included. + * @note The default is @p FALSE. + */ +#if !defined(AT32_ICU_USE_TMR13) || defined(__DOXYGEN__) +#define AT32_ICU_USE_TMR13 FALSE +#endif + +/** + * @brief ICUD14 driver enable switch. + * @details If set to @p TRUE the support for ICUD14 is included. + * @note The default is @p FALSE. + */ +#if !defined(AT32_ICU_USE_TMR14) || defined(__DOXYGEN__) +#define AT32_ICU_USE_TMR14 FALSE +#endif + /** * @brief ICUD1 interrupt priority level setting. */ @@ -170,6 +188,20 @@ #if !defined(AT32_ICU_TMR11_IRQ_PRIORITY) || defined(__DOXYGEN__) #define AT32_ICU_TMR11_IRQ_PRIORITY 7 #endif + +/** + * @brief ICUD13 interrupt priority level setting. + */ +#if !defined(AT32_ICU_TMR13_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define AT32_ICU_TMR13_IRQ_PRIORITY 7 +#endif + +/** + * @brief ICUD14 interrupt priority level setting. + */ +#if !defined(AT32_ICU_TMR14_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define AT32_ICU_TMR14_IRQ_PRIORITY 7 +#endif /** @} */ /*===========================================================================*/ @@ -208,6 +240,14 @@ #define AT32_HAS_TMR11 FALSE #endif +#if !defined(AT32_HAS_TMR13) +#define AT32_HAS_TMR13 FALSE +#endif + +#if !defined(AT32_HAS_TMR14) +#define AT32_HAS_TMR14 FALSE +#endif + #if AT32_ICU_USE_TMR1 && !AT32_HAS_TMR1 #error "TMR1 not present in the selected device" #endif @@ -240,10 +280,19 @@ #error "TMR11 not present in the selected device" #endif +#if AT32_ICU_USE_TMR13 && !AT32_HAS_TMR13 +#error "TMR13 not present in the selected device" +#endif + +#if AT32_ICU_USE_TMR14 && !AT32_HAS_TMR14 +#error "TMR14 not present in the selected device" +#endif + #if !AT32_ICU_USE_TMR1 && !AT32_ICU_USE_TMR2 && \ !AT32_ICU_USE_TMR3 && !AT32_ICU_USE_TMR4 && \ !AT32_ICU_USE_TMR5 && !AT32_ICU_USE_TMR9 && \ - !AT32_ICU_USE_TMR10 && !AT32_ICU_USE_TMR11 + !AT32_ICU_USE_TMR10 && !AT32_ICU_USE_TMR11 && \ + !AT32_ICU_USE_TMR13 && !AT32_ICU_USE_TMR14 #error "ICU driver activated but no TMR peripheral assigned" #endif @@ -312,6 +361,22 @@ #endif #endif +#if AT32_ICU_USE_TMR13 +#if defined(AT32_TMR13_IS_USED) +#error "ICUD13 requires TMR13 but the timer is already used" +#else +#define AT32_TMR13_IS_USED +#endif +#endif + +#if AT32_ICU_USE_TMR14 +#if defined(AT32_TMR14_IS_USED) +#error "ICUD14 requires TMR14 but the timer is already used" +#else +#define AT32_TMR14_IS_USED +#endif +#endif + /* IRQ priority checks.*/ #if AT32_ICU_USE_TMR1 && !defined(AT32_TMR1_SUPPRESS_ISR) && \ !OSAL_IRQ_IS_VALID_PRIORITY(AT32_ICU_TMR1_IRQ_PRIORITY) @@ -353,6 +418,16 @@ #error "Invalid IRQ priority assigned to TMR11" #endif +#if AT32_ICU_USE_TMR13 && !defined(AT32_TMR13_SUPPRESS_ISR) && \ + !OSAL_IRQ_IS_VALID_PRIORITY(AT32_ICU_TMR13_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to TMR13" +#endif + +#if AT32_ICU_USE_TMR14 && !defined(AT32_TMR14_SUPPRESS_ISR) && \ + !OSAL_IRQ_IS_VALID_PRIORITY(AT32_ICU_TMR14_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to TMR14" +#endif + /*===========================================================================*/ /* Driver data structures and types. */ /*===========================================================================*/ @@ -544,6 +619,14 @@ extern ICUDriver ICUD10; extern ICUDriver ICUD11; #endif +#if AT32_ICU_USE_TMR13 && !defined(__DOXYGEN__) +extern ICUDriver ICUD13; +#endif + +#if AT32_ICU_USE_TMR14 && !defined(__DOXYGEN__) +extern ICUDriver ICUD14; +#endif + #ifdef __cplusplus extern "C" { #endif diff --git a/os/hal/ports/AT32/LLD/TMRv1/hal_pwm_lld.c b/os/hal/ports/AT32/LLD/TMRv1/hal_pwm_lld.c index 1ccd7ee104..c7036eff18 100644 --- a/os/hal/ports/AT32/LLD/TMRv1/hal_pwm_lld.c +++ b/os/hal/ports/AT32/LLD/TMRv1/hal_pwm_lld.c @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -100,6 +100,22 @@ PWMDriver PWMD10; PWMDriver PWMD11; #endif +/** + * @brief PWMD13 driver identifier. + * @note The driver PWMD13 allocates the timer TMR13 when enabled. + */ +#if AT32_PWM_USE_TMR13 || defined(__DOXYGEN__) +PWMDriver PWMD13; +#endif + +/** + * @brief PWMD14 driver identifier. + * @note The driver PWMD14 allocates the timer TMR14 when enabled. + */ +#if AT32_PWM_USE_TMR14 || defined(__DOXYGEN__) +PWMDriver PWMD14; +#endif + /*===========================================================================*/ /* Driver local variables and types. */ /*===========================================================================*/ @@ -258,6 +274,18 @@ OSAL_IRQ_HANDLER(AT32_TMR5_HANDLER) { #endif /* !defined(AT32_TMR11_SUPPRESS_ISR) */ #endif /* AT32_PWM_USE_TMR11 */ +#if AT32_PWM_USE_TMR13 || defined(__DOXYGEN__) +#if !defined(AT32_TMR13_SUPPRESS_ISR) +#error "TMR13 ISR not defined by platform" +#endif /* !defined(AT32_TMR13_SUPPRESS_ISR) */ +#endif /* AT32_PWM_USE_TMR13 */ + +#if AT32_PWM_USE_TMR14 || defined(__DOXYGEN__) +#if !defined(AT32_TMR14_SUPPRESS_ISR) +#error "TMR14 ISR not defined by platform" +#endif /* !defined(AT32_TMR14_SUPPRESS_ISR) */ +#endif /* AT32_PWM_USE_TMR14 */ + /*===========================================================================*/ /* Driver exported functions. */ /*===========================================================================*/ @@ -319,7 +347,7 @@ void pwm_lld_init(void) { pwmObjectInit(&PWMD9); PWMD9.channels = AT32_TMR9_CHANNELS; PWMD9.tmr = AT32_TMR9; - PWMD9.has_brk = false; + PWMD9.has_brk = true; PWMD9.has_plus_mode = (bool)AT32_TMR9_IS_32BITS; #endif @@ -328,7 +356,7 @@ void pwm_lld_init(void) { pwmObjectInit(&PWMD10); PWMD10.channels = AT32_TMR10_CHANNELS; PWMD10.tmr = AT32_TMR10; - PWMD10.has_brk = false; + PWMD10.has_brk = true; PWMD10.has_plus_mode = (bool)AT32_TMR10_IS_32BITS; #endif @@ -337,9 +365,27 @@ void pwm_lld_init(void) { pwmObjectInit(&PWMD11); PWMD11.channels = AT32_TMR11_CHANNELS; PWMD11.tmr = AT32_TMR11; - PWMD11.has_brk = false; + PWMD11.has_brk = true; PWMD11.has_plus_mode = (bool)AT32_TMR11_IS_32BITS; #endif + +#if AT32_PWM_USE_TMR13 + /* Driver initialization.*/ + pwmObjectInit(&PWMD13); + PWMD13.channels = AT32_TMR13_CHANNELS; + PWMD13.tmr = AT32_TMR13; + PWMD13.has_brk = true; + PWMD13.has_plus_mode = (bool)AT32_TMR13_IS_32BITS; +#endif + +#if AT32_PWM_USE_TMR14 + /* Driver initialization.*/ + pwmObjectInit(&PWMD14); + PWMD14.channels = AT32_TMR14_CHANNELS; + PWMD14.tmr = AT32_TMR14; + PWMD14.has_brk = true; + PWMD14.has_plus_mode = (bool)AT32_TMR14_IS_32BITS; +#endif } /** @@ -437,6 +483,22 @@ void pwm_lld_start(PWMDriver *pwmp) { } #endif +#if AT32_PWM_USE_TMR13 + if (&PWMD13 == pwmp) { + crmEnableTMR13(true); + crmResetTMR13(); + pwmp->clock = AT32_TMRCLK1; + } +#endif + +#if AT32_PWM_USE_TMR14 + if (&PWMD14 == pwmp) { + crmEnableTMR14(true); + crmResetTMR14(); + pwmp->clock = AT32_TMRCLK1; + } +#endif + /* All channels configured in PWM1 mode with preload enabled and will stay that way until the driver is stopped.*/ pwmp->tmr->CM1 = AT32_TMR_CM1_C1OCTRL(6) | AT32_TMR_CM1_C1OBEN | @@ -637,6 +699,18 @@ void pwm_lld_stop(PWMDriver *pwmp) { crmDisableTMR11(); } #endif + +#if AT32_PWM_USE_TMR13 + if (&PWMD13 == pwmp) { + crmDisableTMR13(); + } +#endif + +#if AT32_PWM_USE_TMR14 + if (&PWMD14 == pwmp) { + crmDisableTMR14(); + } +#endif } } diff --git a/os/hal/ports/AT32/LLD/TMRv1/hal_pwm_lld.h b/os/hal/ports/AT32/LLD/TMRv1/hal_pwm_lld.h index 5a40b54841..72740a81e3 100644 --- a/os/hal/ports/AT32/LLD/TMRv1/hal_pwm_lld.h +++ b/os/hal/ports/AT32/LLD/TMRv1/hal_pwm_lld.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -153,6 +153,24 @@ #define AT32_PWM_USE_TMR11 FALSE #endif +/** + * @brief PWMD13 driver enable switch. + * @details If set to @p TRUE the support for PWMD13 is included. + * @note The default is @p FALSE. + */ +#if !defined(AT32_PWM_USE_TMR13) || defined(__DOXYGEN__) +#define AT32_PWM_USE_TMR13 FALSE +#endif + +/** + * @brief PWMD14 driver enable switch. + * @details If set to @p TRUE the support for PWMD14 is included. + * @note The default is @p FALSE. + */ +#if !defined(AT32_PWM_USE_TMR14) || defined(__DOXYGEN__) +#define AT32_PWM_USE_TMR14 FALSE +#endif + /** * @brief PWMD1 interrupt priority level setting. */ @@ -208,6 +226,20 @@ #if !defined(AT32_PWM_TMR11_IRQ_PRIORITY) || defined(__DOXYGEN__) #define AT32_PWM_TMR11_IRQ_PRIORITY 7 #endif + +/** + * @brief PWMD13 interrupt priority level setting. + */ +#if !defined(AT32_PWM_TMR13_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define AT32_PWM_TMR13_IRQ_PRIORITY 7 +#endif + +/** + * @brief PWMD14 interrupt priority level setting. + */ +#if !defined(AT32_PWM_TMR14_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define AT32_PWM_TMR14_IRQ_PRIORITY 7 +#endif /** @} */ /*===========================================================================*/ @@ -246,6 +278,14 @@ #define AT32_HAS_TMR11 FALSE #endif +#if !defined(AT32_HAS_TMR13) +#define AT32_HAS_TMR13 FALSE +#endif + +#if !defined(AT32_HAS_TMR14) +#define AT32_HAS_TMR14 FALSE +#endif + #if AT32_PWM_USE_TMR1 && !AT32_HAS_TMR1 #error "TMR1 not present in the selected device" #endif @@ -278,10 +318,19 @@ #error "TMR11 not present in the selected device" #endif +#if AT32_PWM_USE_TMR13 && !AT32_HAS_TMR13 +#error "TMR13 not present in the selected device" +#endif + +#if AT32_PWM_USE_TMR14 && !AT32_HAS_TMR14 +#error "TMR14 not present in the selected device" +#endif + #if !AT32_PWM_USE_TMR1 && !AT32_PWM_USE_TMR2 && \ !AT32_PWM_USE_TMR3 && !AT32_PWM_USE_TMR4 && \ !AT32_PWM_USE_TMR5 && !AT32_PWM_USE_TMR9 && \ - !AT32_PWM_USE_TMR10 && !AT32_PWM_USE_TMR11 + !AT32_PWM_USE_TMR10 && !AT32_PWM_USE_TMR11 && \ + !AT32_PWM_USE_TMR13 && !AT32_PWM_USE_TMR14 #error "PWM driver activated but no TMR peripheral assigned" #endif @@ -350,6 +399,22 @@ #endif #endif +#if AT32_PWM_USE_TMR13 +#if defined(AT32_TMR13_IS_USED) +#error "PWMD13 requires TMR13 but the timer is already used" +#else +#define AT32_TMR13_IS_USED +#endif +#endif + +#if AT32_PWM_USE_TMR14 +#if defined(AT32_TMR14_IS_USED) +#error "PWMD14 requires TMR14 but the timer is already used" +#else +#define AT32_TMR14_IS_USED +#endif +#endif + /* IRQ priority checks.*/ #if AT32_PWM_USE_TMR1 && !defined(AT32_TMR1_SUPPRESS_ISR) && \ !OSAL_IRQ_IS_VALID_PRIORITY(AT32_PWM_TMR1_IRQ_PRIORITY) @@ -391,6 +456,16 @@ #error "Invalid IRQ priority assigned to TMR11" #endif +#if AT32_PWM_USE_TMR13 && !defined(AT32_TMR13_SUPPRESS_ISR) && \ + !OSAL_IRQ_IS_VALID_PRIORITY(AT32_PWM_TMR13_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to TMR13" +#endif + +#if AT32_PWM_USE_TMR14 && !defined(AT32_TMR14_SUPPRESS_ISR) && \ + !OSAL_IRQ_IS_VALID_PRIORITY(AT32_PWM_TMR14_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to TMR14" +#endif + /*===========================================================================*/ /* Driver data structures and types. */ /*===========================================================================*/ @@ -582,6 +657,14 @@ extern PWMDriver PWMD10; extern PWMDriver PWMD11; #endif +#if AT32_PWM_USE_TMR13 && !defined(__DOXYGEN__) +extern PWMDriver PWMD13; +#endif + +#if AT32_PWM_USE_TMR14 && !defined(__DOXYGEN__) +extern PWMDriver PWMD14; +#endif + #ifdef __cplusplus extern "C" { #endif diff --git a/os/hal/ports/AT32/LLD/TMRv1/readme.md b/os/hal/ports/AT32/LLD/TMRv1/readme.md new file mode 100644 index 0000000000..ba0e228663 --- /dev/null +++ b/os/hal/ports/AT32/LLD/TMRv1/readme.md @@ -0,0 +1,8 @@ +## TMR units IRQ collisions mapping. + +| MCU | 1_BRK | 1_OVF | 1_THALL | 1_CH | 2 | 3 | 4 | 5 | 6 | 7 | 9 | 10 | 11 | 13 | 14 | +| -------- | ----- | ----- | ------- | ---- | ---- | ---- | ---- | ---- | ---- | ---- | ---- | ---- | ---- | ---- | ---- | +| AT32F402 | 1 | 2 | 3 | ✓ | ✓ | ✓ | ✓ | | ✓ | ✓ | 1 | 2 | 3 | ✓ | ✓ | +| AT32F405 | 1 | 2 | 3 | ✓ | ✓ | ✓ | ✓ | | ✓ | ✓ | 1 | 2 | 3 | ✓ | ✓ | +| AT32F415 | 1 | 2 | 3 | ✓ | ✓ | ✓ | ✓ | ✓ | | | 1 | 2 | 3 | | | +| | | | | | | | | | | | | | | | | diff --git a/os/hal/ports/AT32/LLD/USARTv1/at32_uart4.inc b/os/hal/ports/AT32/LLD/USART/at32_uart4.inc similarity index 94% rename from os/hal/ports/AT32/LLD/USARTv1/at32_uart4.inc rename to os/hal/ports/AT32/LLD/USART/at32_uart4.inc index c07c8ff8c6..c3afdd304e 100644 --- a/os/hal/ports/AT32/LLD/USARTv1/at32_uart4.inc +++ b/os/hal/ports/AT32/LLD/USART/at32_uart4.inc @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -94,6 +94,12 @@ OSAL_IRQ_HANDLER(AT32_UART4_HANDLER) { #endif #endif +#if HAL_USE_SIO +#if AT32_SIO_USE_UART4 + sio_lld_serve_interrupt(&SIOD4); +#endif +#endif + #if HAL_USE_UART #if AT32_UART_USE_UART4 uart_lld_serve_interrupt(&UARTD4); diff --git a/os/hal/ports/AT32/LLD/USARTv1/at32_uart5.inc b/os/hal/ports/AT32/LLD/USART/at32_uart5.inc similarity index 94% rename from os/hal/ports/AT32/LLD/USARTv1/at32_uart5.inc rename to os/hal/ports/AT32/LLD/USART/at32_uart5.inc index fff0dadae3..1499bd7fe4 100644 --- a/os/hal/ports/AT32/LLD/USARTv1/at32_uart5.inc +++ b/os/hal/ports/AT32/LLD/USART/at32_uart5.inc @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -94,6 +94,12 @@ OSAL_IRQ_HANDLER(AT32_UART5_HANDLER) { #endif #endif +#if HAL_USE_SIO +#if AT32_SIO_USE_UART5 + sio_lld_serve_interrupt(&SIOD5); +#endif +#endif + #if HAL_USE_UART #if AT32_UART_USE_UART5 uart_lld_serve_interrupt(&UARTD5); diff --git a/os/hal/ports/AT32/LLD/USARTv2/at32_uart7.inc b/os/hal/ports/AT32/LLD/USART/at32_uart7.inc similarity index 93% rename from os/hal/ports/AT32/LLD/USARTv2/at32_uart7.inc rename to os/hal/ports/AT32/LLD/USART/at32_uart7.inc index 0ddf35dd0c..3a4401a69c 100644 --- a/os/hal/ports/AT32/LLD/USARTv2/at32_uart7.inc +++ b/os/hal/ports/AT32/LLD/USART/at32_uart7.inc @@ -1,8 +1,8 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian - ChibiOS - Copyright (C) 2023..2024 Maxjta + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + ChibiOS - Copyright (C) 2024..2025 Maxjta Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -95,6 +95,12 @@ OSAL_IRQ_HANDLER(AT32_UART7_HANDLER) { #endif #endif +#if HAL_USE_SIO +#if AT32_SIO_USE_UART7 + sio_lld_serve_interrupt(&SIOD7); +#endif +#endif + #if HAL_USE_UART #if AT32_UART_USE_UART7 uart_lld_serve_interrupt(&UARTD7); diff --git a/os/hal/ports/AT32/LLD/USARTv2/at32_uart8.inc b/os/hal/ports/AT32/LLD/USART/at32_uart8.inc similarity index 92% rename from os/hal/ports/AT32/LLD/USARTv2/at32_uart8.inc rename to os/hal/ports/AT32/LLD/USART/at32_uart8.inc index 3ec2763eb4..832fc13fc9 100644 --- a/os/hal/ports/AT32/LLD/USARTv2/at32_uart8.inc +++ b/os/hal/ports/AT32/LLD/USART/at32_uart8.inc @@ -1,8 +1,8 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian - ChibiOS - Copyright (C) 2023..2024 Maxjta + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + ChibiOS - Copyright (C) 2024..2025 Maxjta Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -18,7 +18,7 @@ */ /** - * @file USART/at32_UART8.inc + * @file USART/at32_uart8.inc * @brief Shared UART8 handler. * * @addtogroup AT32_UART8_HANDLER @@ -95,6 +95,12 @@ OSAL_IRQ_HANDLER(AT32_UART8_HANDLER) { #endif #endif +#if HAL_USE_SIO +#if AT32_SIO_USE_UART8 + sio_lld_serve_interrupt(&SIOD8); +#endif +#endif + #if HAL_USE_UART #if AT32_UART_USE_UART8 uart_lld_serve_interrupt(&UARTD8); diff --git a/os/hal/ports/AT32/LLD/USARTv2/at32_usart1.inc b/os/hal/ports/AT32/LLD/USART/at32_usart1.inc similarity index 94% rename from os/hal/ports/AT32/LLD/USARTv2/at32_usart1.inc rename to os/hal/ports/AT32/LLD/USART/at32_usart1.inc index f215b4f7c7..da86470108 100644 --- a/os/hal/ports/AT32/LLD/USARTv2/at32_usart1.inc +++ b/os/hal/ports/AT32/LLD/USART/at32_usart1.inc @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -94,6 +94,12 @@ OSAL_IRQ_HANDLER(AT32_USART1_HANDLER) { #endif #endif +#if HAL_USE_SIO +#if AT32_SIO_USE_USART1 + sio_lld_serve_interrupt(&SIOD1); +#endif +#endif + #if HAL_USE_UART #if AT32_UART_USE_USART1 uart_lld_serve_interrupt(&UARTD1); diff --git a/os/hal/ports/AT32/LLD/USARTv2/at32_usart2.inc b/os/hal/ports/AT32/LLD/USART/at32_usart2.inc similarity index 94% rename from os/hal/ports/AT32/LLD/USARTv2/at32_usart2.inc rename to os/hal/ports/AT32/LLD/USART/at32_usart2.inc index 1652352b72..81ee8f9aee 100644 --- a/os/hal/ports/AT32/LLD/USARTv2/at32_usart2.inc +++ b/os/hal/ports/AT32/LLD/USART/at32_usart2.inc @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -94,6 +94,12 @@ OSAL_IRQ_HANDLER(AT32_USART2_HANDLER) { #endif #endif +#if HAL_USE_SIO +#if AT32_SIO_USE_USART2 + sio_lld_serve_interrupt(&SIOD2); +#endif +#endif + #if HAL_USE_UART #if AT32_UART_USE_USART2 uart_lld_serve_interrupt(&UARTD2); diff --git a/os/hal/ports/AT32/LLD/USARTv1/at32_usart3.inc b/os/hal/ports/AT32/LLD/USART/at32_usart3.inc similarity index 94% rename from os/hal/ports/AT32/LLD/USARTv1/at32_usart3.inc rename to os/hal/ports/AT32/LLD/USART/at32_usart3.inc index a00a1a09ad..d23f4aaa62 100644 --- a/os/hal/ports/AT32/LLD/USARTv1/at32_usart3.inc +++ b/os/hal/ports/AT32/LLD/USART/at32_usart3.inc @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -94,6 +94,12 @@ OSAL_IRQ_HANDLER(AT32_USART3_HANDLER) { #endif #endif +#if HAL_USE_SIO +#if AT32_SIO_USE_USART3 + sio_lld_serve_interrupt(&SIOD3); +#endif +#endif + #if HAL_USE_UART #if AT32_UART_USE_USART3 uart_lld_serve_interrupt(&UARTD3); diff --git a/os/hal/ports/AT32/LLD/USARTv2/at32_usart6.inc b/os/hal/ports/AT32/LLD/USART/at32_usart6.inc similarity index 93% rename from os/hal/ports/AT32/LLD/USARTv2/at32_usart6.inc rename to os/hal/ports/AT32/LLD/USART/at32_usart6.inc index cedbc7a285..20320dc1ce 100644 --- a/os/hal/ports/AT32/LLD/USARTv2/at32_usart6.inc +++ b/os/hal/ports/AT32/LLD/USART/at32_usart6.inc @@ -1,8 +1,8 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian - ChibiOS - Copyright (C) 2024 Maxjta + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + ChibiOS - Copyright (C) 2024..2025 Maxjta Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -95,6 +95,12 @@ OSAL_IRQ_HANDLER(AT32_USART6_HANDLER) { #endif #endif +#if HAL_USE_SIO +#if AT32_SIO_USE_USART6 + sio_lld_serve_interrupt(&SIOD6); +#endif +#endif + #if HAL_USE_UART #if AT32_UART_USE_USART6 uart_lld_serve_interrupt(&UARTD6); diff --git a/os/hal/ports/AT32/LLD/USARTv1/at32_usart1.inc b/os/hal/ports/AT32/LLD/USARTv1/at32_usart1.inc deleted file mode 100644 index f215b4f7c7..0000000000 --- a/os/hal/ports/AT32/LLD/USARTv1/at32_usart1.inc +++ /dev/null @@ -1,111 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file USART/at32_usart1.inc - * @brief Shared USART1 handler. - * - * @addtogroup AT32_USART1_HANDLER - * @{ - */ - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/* Registry checks for robustness.*/ -#if !defined(AT32_HAS_USART1) -#error "AT32_HAS_USART1 not defined in registry" -#endif - -#if AT32_HAS_USART1 - -/* Priority settings checks.*/ -#if !defined(AT32_IRQ_USART1_PRIORITY) -#error "AT32_IRQ_USART1_PRIORITY not defined in mcuconf.h" -#endif - -#if !OSAL_IRQ_IS_VALID_PRIORITY(AT32_IRQ_USART1_PRIORITY) -#error "Invalid IRQ priority assigned to AT32_IRQ_USART1_PRIORITY" -#endif - -#endif /* AT32_HAS_USART1 */ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -static inline void usart1_irq_init(void) { -#if defined(AT32_USART1_IS_USED) - nvicEnableVector(AT32_USART1_NUMBER, AT32_IRQ_USART1_PRIORITY); -#endif -} - -static inline void usart1_irq_deinit(void) { -#if defined(AT32_USART1_IS_USED) - nvicDisableVector(AT32_USART1_NUMBER); -#endif -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if defined(AT32_USART1_IS_USED) || defined(__DOXYGEN__) -/** - * @brief USART1 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(AT32_USART1_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - -#if HAL_USE_SERIAL -#if AT32_SERIAL_USE_USART1 - sd_lld_serve_interrupt(&SD1); -#endif -#endif - -#if HAL_USE_UART -#if AT32_UART_USE_USART1 - uart_lld_serve_interrupt(&UARTD1); -#endif -#endif - - OSAL_IRQ_EPILOGUE(); -} -#endif - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** @} */ diff --git a/os/hal/ports/AT32/LLD/USARTv1/at32_usart2.inc b/os/hal/ports/AT32/LLD/USARTv1/at32_usart2.inc deleted file mode 100644 index 1652352b72..0000000000 --- a/os/hal/ports/AT32/LLD/USARTv1/at32_usart2.inc +++ /dev/null @@ -1,111 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file USART/at32_usart2.inc - * @brief Shared USART2 handler. - * - * @addtogroup AT32_USART2_HANDLER - * @{ - */ - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/* Registry checks for robustness.*/ -#if !defined(AT32_HAS_USART2) -#error "AT32_HAS_USART2 not defined in registry" -#endif - -#if AT32_HAS_USART2 - -/* Priority settings checks.*/ -#if !defined(AT32_IRQ_USART2_PRIORITY) -#error "AT32_IRQ_USART2_PRIORITY not defined in mcuconf.h" -#endif - -#if !OSAL_IRQ_IS_VALID_PRIORITY(AT32_IRQ_USART2_PRIORITY) -#error "Invalid IRQ priority assigned to AT32_IRQ_USART2_PRIORITY" -#endif - -#endif /* AT32_HAS_USART2 */ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -static inline void usart2_irq_init(void) { -#if defined(AT32_USART2_IS_USED) - nvicEnableVector(AT32_USART2_NUMBER, AT32_IRQ_USART2_PRIORITY); -#endif -} - -static inline void usart2_irq_deinit(void) { -#if defined(AT32_USART2_IS_USED) - nvicDisableVector(AT32_USART2_NUMBER); -#endif -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if defined(AT32_USART2_IS_USED) || defined(__DOXYGEN__) -/** - * @brief USART2 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(AT32_USART2_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - -#if HAL_USE_SERIAL -#if AT32_SERIAL_USE_USART2 - sd_lld_serve_interrupt(&SD2); -#endif -#endif - -#if HAL_USE_UART -#if AT32_UART_USE_USART2 - uart_lld_serve_interrupt(&UARTD2); -#endif -#endif - - OSAL_IRQ_EPILOGUE(); -} -#endif - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** @} */ diff --git a/os/hal/ports/AT32/LLD/USARTv1/driver.mk b/os/hal/ports/AT32/LLD/USARTv1/driver.mk index 652a4742fe..7fc7bca838 100644 --- a/os/hal/ports/AT32/LLD/USARTv1/driver.mk +++ b/os/hal/ports/AT32/LLD/USARTv1/driver.mk @@ -10,4 +10,5 @@ PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/USARTv1/hal_seri PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/USARTv1/hal_uart_lld.c endif -PLATFORMINC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/USARTv1 +PLATFORMINC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/USART \ + $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/USARTv1 diff --git a/os/hal/ports/AT32/LLD/USARTv1/hal_serial_lld.c b/os/hal/ports/AT32/LLD/USARTv1/hal_serial_lld.c index 0c205de859..f7033d04fb 100644 --- a/os/hal/ports/AT32/LLD/USARTv1/hal_serial_lld.c +++ b/os/hal/ports/AT32/LLD/USARTv1/hal_serial_lld.c @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/USARTv1/hal_serial_lld.h b/os/hal/ports/AT32/LLD/USARTv1/hal_serial_lld.h index 41da42389e..e27bbb0ef2 100644 --- a/os/hal/ports/AT32/LLD/USARTv1/hal_serial_lld.h +++ b/os/hal/ports/AT32/LLD/USARTv1/hal_serial_lld.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/USARTv1/hal_uart_lld.c b/os/hal/ports/AT32/LLD/USARTv1/hal_uart_lld.c index d5d2b8260e..9d995c2311 100644 --- a/os/hal/ports/AT32/LLD/USARTv1/hal_uart_lld.c +++ b/os/hal/ports/AT32/LLD/USARTv1/hal_uart_lld.c @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -153,7 +153,8 @@ static void usart_start(UARTDriver *uartp) { usart_stop(uartp); /* Baud rate setting.*/ - baudr = (uint32_t)((uartp->clock + uartp->config->speed/2) / uartp->config->speed); + baudr = (uint32_t)((uartp->clock + uartp->config->speed / 2) / + uartp->config->speed); u->BAUDR = baudr; /* Resetting eventual pending status flags.*/ @@ -180,7 +181,7 @@ static void usart_start(UARTDriver *uartp) { * @brief RX DMA common service routine. * * @param[in] uartp pointer to the @p UARTDriver object - * @param[in] flags pre-shifted content of the ISR register + * @param[in] flags pre-shifted content of the STS register */ static void uart_lld_serve_rx_end_irq(UARTDriver *uartp, uint32_t flags) { @@ -210,7 +211,7 @@ static void uart_lld_serve_rx_end_irq(UARTDriver *uartp, uint32_t flags) { * @brief TX DMA common service routine. * * @param[in] uartp pointer to the @p UARTDriver object - * @param[in] flags pre-shifted content of the ISR register + * @param[in] flags pre-shifted content of the STS register */ static void uart_lld_serve_tx_end_irq(UARTDriver *uartp, uint32_t flags) { @@ -351,52 +352,52 @@ void uart_lld_init(void) { #if AT32_UART_USE_USART1 uartObjectInit(&UARTD1); - UARTD1.usart = USART1; - UARTD1.clock = AT32_PCLK2; + UARTD1.usart = USART1; + UARTD1.clock = AT32_PCLK2; UARTD1.dmarxmode = AT32_DMA_CCTRL_DTERRIEN; UARTD1.dmatxmode = AT32_DMA_CCTRL_DTERRIEN; - UARTD1.dmarx = NULL; - UARTD1.dmatx = NULL; + UARTD1.dmarx = NULL; + UARTD1.dmatx = NULL; #endif #if AT32_UART_USE_USART2 uartObjectInit(&UARTD2); - UARTD2.usart = USART2; - UARTD2.clock = AT32_PCLK1; + UARTD2.usart = USART2; + UARTD2.clock = AT32_PCLK1; UARTD2.dmarxmode = AT32_DMA_CCTRL_DTERRIEN; UARTD2.dmatxmode = AT32_DMA_CCTRL_DTERRIEN; - UARTD2.dmarx = NULL; - UARTD2.dmatx = NULL; + UARTD2.dmarx = NULL; + UARTD2.dmatx = NULL; #endif #if AT32_UART_USE_USART3 uartObjectInit(&UARTD3); - UARTD3.usart = USART3; - UARTD3.clock = AT32_PCLK1; + UARTD3.usart = USART3; + UARTD3.clock = AT32_PCLK1; UARTD3.dmarxmode = AT32_DMA_CCTRL_DTERRIEN; UARTD3.dmatxmode = AT32_DMA_CCTRL_DTERRIEN; - UARTD3.dmarx = NULL; - UARTD3.dmatx = NULL; + UARTD3.dmarx = NULL; + UARTD3.dmatx = NULL; #endif #if AT32_UART_USE_UART4 uartObjectInit(&UARTD4); - UARTD4.usart = UART4; - UARTD4.clock = AT32_PCLK1; + UARTD4.usart = UART4; + UARTD4.clock = AT32_PCLK1; UARTD4.dmarxmode = AT32_DMA_CCTRL_DTERRIEN; UARTD4.dmatxmode = AT32_DMA_CCTRL_DTERRIEN; - UARTD4.dmarx = NULL; - UARTD4.dmatx = NULL; + UARTD4.dmarx = NULL; + UARTD4.dmatx = NULL; #endif #if AT32_UART_USE_UART5 uartObjectInit(&UARTD5); - UARTD5.usart = UART5; - UARTD5.clock = AT32_PCLK1; + UARTD5.usart = UART5; + UARTD5.clock = AT32_PCLK1; UARTD5.dmarxmode = AT32_DMA_CCTRL_DTERRIEN; UARTD5.dmatxmode = AT32_DMA_CCTRL_DTERRIEN; - UARTD5.dmarx = NULL; - UARTD5.dmatx = NULL; + UARTD5.dmarx = NULL; + UARTD5.dmatx = NULL; #endif } @@ -548,7 +549,7 @@ void uart_lld_start(UARTDriver *uartp) { #endif /* Static DMA setup, the transfer size depends on the USART settings, - it is 16 bits if M=1 and PEN=0 else it is 8 bits.*/ + it is 16 bits if DBN=1 and PEN=0 else it is 8 bits.*/ if ((uartp->config->ctrl1 & (USART_CTRL1_DBN | USART_CTRL1_PEN)) == USART_CTRL1_DBN) { uartp->dmarxmode |= AT32_DMA_CCTRL_PWIDTH_HWORD | AT32_DMA_CCTRL_MWIDTH_HWORD; uartp->dmatxmode |= AT32_DMA_CCTRL_PWIDTH_HWORD | AT32_DMA_CCTRL_MWIDTH_HWORD; diff --git a/os/hal/ports/AT32/LLD/USARTv1/hal_uart_lld.h b/os/hal/ports/AT32/LLD/USARTv1/hal_uart_lld.h index 12981f5457..8fdef0815a 100644 --- a/os/hal/ports/AT32/LLD/USARTv1/hal_uart_lld.h +++ b/os/hal/ports/AT32/LLD/USARTv1/hal_uart_lld.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -172,7 +172,7 @@ #endif /** - * @brief USART DMA error hook. + * @brief UART DMA error hook. * @note The default action for DMA errors is a system halt because DMA * error can only happen because programming errors. */ @@ -206,7 +206,7 @@ #endif #if !AT32_UART_USE_USART1 && !AT32_UART_USE_USART2 && \ - !AT32_UART_USE_USART3 && !AT32_UART_USE_UART4 && \ + !AT32_UART_USE_USART3 && !AT32_UART_USE_UART4 && \ !AT32_UART_USE_UART5 #error "UART driver activated but no USART/UART peripheral assigned" #endif @@ -404,7 +404,7 @@ typedef struct hal_uart_config { /** * @brief Receiver timeout callback. * @details Handles idle interrupts depending on configured - * flags in CR registers and supported hardware features. + * flags in CTRL registers and supported hardware features. */ uartcb_t timeout_cb; /** diff --git a/os/hal/ports/AT32/LLD/USARTv2/at32_usart.h b/os/hal/ports/AT32/LLD/USARTv2/at32_usart.h new file mode 100644 index 0000000000..ba1341368d --- /dev/null +++ b/os/hal/ports/AT32/LLD/USARTv2/at32_usart.h @@ -0,0 +1,83 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file USARTv2/at32_usart.h + * @brief AT32 USART helpers header. + * + * @addtogroup AT32_ + * @{ + */ + +#ifndef AT32_USART_H +#define AT32_USART_H + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name CTRL1 register additional macros + * @{ + */ +#define USART_CTRL1_DATA7 (USART_CTRL1_DBN1) +#define USART_CTRL1_DATA8 (0U) +#define USART_CTRL1_DATA9 (USART_CTRL1_DBN0) +/** @} */ + +/** + * @name CTRL2 register additional macros + * @{ + */ +#define USART_CTRL2_STOPBN1_BITS (0U << 12) +#define USART_CTRL2_STOPBN0P5_BITS (1U << 12) +#define USART_CTRL2_STOPBN2_BITS (2U << 12) +#define USART_CTRL2_STOPBN1P5_BITS (3U << 12) +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* AT32_USART_H */ + +/** @} */ diff --git a/os/hal/ports/AT32/LLD/USARTv2/at32_usart3.inc b/os/hal/ports/AT32/LLD/USARTv2/at32_usart3.inc deleted file mode 100644 index a00a1a09ad..0000000000 --- a/os/hal/ports/AT32/LLD/USARTv2/at32_usart3.inc +++ /dev/null @@ -1,111 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file USART/at32_usart3.inc - * @brief Shared USART3 handler. - * - * @addtogroup AT32_USART3_HANDLER - * @{ - */ - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/* Registry checks for robustness.*/ -#if !defined(AT32_HAS_USART3) -#error "AT32_HAS_USART3 not defined in registry" -#endif - -#if AT32_HAS_USART3 - -/* Priority settings checks.*/ -#if !defined(AT32_IRQ_USART3_PRIORITY) -#error "AT32_IRQ_USART3_PRIORITY not defined in mcuconf.h" -#endif - -#if !OSAL_IRQ_IS_VALID_PRIORITY(AT32_IRQ_USART3_PRIORITY) -#error "Invalid IRQ priority assigned to AT32_IRQ_USART3_PRIORITY" -#endif - -#endif /* AT32_HAS_USART3 */ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -static inline void usart3_irq_init(void) { -#if defined(AT32_USART3_IS_USED) - nvicEnableVector(AT32_USART3_NUMBER, AT32_IRQ_USART3_PRIORITY); -#endif -} - -static inline void usart3_irq_deinit(void) { -#if defined(AT32_USART3_IS_USED) - nvicDisableVector(AT32_USART3_NUMBER); -#endif -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if defined(AT32_USART3_IS_USED) || defined(__DOXYGEN__) -/** - * @brief USART3 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(AT32_USART3_HANDLER) { - - OSAL_IRQ_PROLOGUE(); - -#if HAL_USE_SERIAL -#if AT32_SERIAL_USE_USART3 - sd_lld_serve_interrupt(&SD3); -#endif -#endif - -#if HAL_USE_UART -#if AT32_UART_USE_USART3 - uart_lld_serve_interrupt(&UARTD3); -#endif -#endif - - OSAL_IRQ_EPILOGUE(); -} -#endif - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** @} */ diff --git a/os/hal/ports/AT32/LLD/USARTv2/driver.mk b/os/hal/ports/AT32/LLD/USARTv2/driver.mk index 65b0977e25..890a90ce02 100644 --- a/os/hal/ports/AT32/LLD/USARTv2/driver.mk +++ b/os/hal/ports/AT32/LLD/USARTv2/driver.mk @@ -2,12 +2,17 @@ ifeq ($(USE_SMART_BUILD),yes) ifneq ($(findstring HAL_USE_SERIAL TRUE,$(HALCONF)),) PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/USARTv2/hal_serial_lld.c endif +ifneq ($(findstring HAL_USE_SIO TRUE,$(HALCONF)),) +PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/USARTv2/hal_sio_lld.c +endif ifneq ($(findstring HAL_USE_UART TRUE,$(HALCONF)),) PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/USARTv2/hal_uart_lld.c endif else PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/USARTv2/hal_serial_lld.c +PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/USARTv2/hal_sio_lld.c PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/USARTv2/hal_uart_lld.c endif -PLATFORMINC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/USARTv2 +PLATFORMINC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/USART \ + $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/LLD/USARTv2 diff --git a/os/hal/ports/AT32/LLD/USARTv2/hal_serial_lld.c b/os/hal/ports/AT32/LLD/USARTv2/hal_serial_lld.c index ecfbc5fb2b..ede8c7300e 100644 --- a/os/hal/ports/AT32/LLD/USARTv2/hal_serial_lld.c +++ b/os/hal/ports/AT32/LLD/USARTv2/hal_serial_lld.c @@ -1,8 +1,8 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian - ChibiOS - Copyright (C) 2023..2024 Maxjta + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + ChibiOS - Copyright (C) 2024..2025 Maxjta Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -33,6 +33,23 @@ /* Driver local definitions. */ /*===========================================================================*/ +/* Handling differences in frame size bits.*/ +#if !defined(USART_CTRL1_DBN_0) +#define USART_CTRL1_DBN_0 (1 << 12) +#endif + +#if !defined(USART_CTRL1_DBN_1) +#define USART_CTRL1_DBN_1 (1 << 28) +#endif + +/* Workarounds for those devices where UARTs are USARTs.*/ +#if defined(USART4) +#define UART4 USART4 +#endif +#if defined(USART5) +#define UART5 USART5 +#endif + /*===========================================================================*/ /* Driver exported variables. */ /*===========================================================================*/ @@ -90,6 +107,70 @@ static const SerialConfig default_config = 0 }; +#if AT32_SERIAL_USE_USART1 || defined(__DOXYGEN__) +/** @brief Input buffer for SD1.*/ +static uint8_t sd_in_buf1[AT32_SERIAL_USART1_IN_BUF_SIZE]; + +/** @brief Output buffer for SD1.*/ +static uint8_t sd_out_buf1[AT32_SERIAL_USART1_OUT_BUF_SIZE]; +#endif + +#if AT32_SERIAL_USE_USART2 || defined(__DOXYGEN__) +/** @brief Input buffer for SD2.*/ +static uint8_t sd_in_buf2[AT32_SERIAL_USART2_IN_BUF_SIZE]; + +/** @brief Output buffer for SD2.*/ +static uint8_t sd_out_buf2[AT32_SERIAL_USART2_OUT_BUF_SIZE]; +#endif + +#if AT32_SERIAL_USE_USART3 || defined(__DOXYGEN__) +/** @brief Input buffer for SD3.*/ +static uint8_t sd_in_buf3[AT32_SERIAL_USART3_IN_BUF_SIZE]; + +/** @brief Output buffer for SD3.*/ +static uint8_t sd_out_buf3[AT32_SERIAL_USART3_OUT_BUF_SIZE]; +#endif + +#if AT32_SERIAL_USE_UART4 || defined(__DOXYGEN__) +/** @brief Input buffer for SD4.*/ +static uint8_t sd_in_buf4[AT32_SERIAL_UART4_IN_BUF_SIZE]; + +/** @brief Output buffer for SD4.*/ +static uint8_t sd_out_buf4[AT32_SERIAL_UART4_OUT_BUF_SIZE]; +#endif + +#if AT32_SERIAL_USE_UART5 || defined(__DOXYGEN__) +/** @brief Input buffer for SD5.*/ +static uint8_t sd_in_buf5[AT32_SERIAL_UART5_IN_BUF_SIZE]; + +/** @brief Output buffer for SD5.*/ +static uint8_t sd_out_buf5[AT32_SERIAL_UART5_OUT_BUF_SIZE]; +#endif + +#if AT32_SERIAL_USE_USART6 || defined(__DOXYGEN__) +/** @brief Input buffer for SD6.*/ +static uint8_t sd_in_buf6[AT32_SERIAL_USART6_IN_BUF_SIZE]; + +/** @brief Output buffer for SD6.*/ +static uint8_t sd_out_buf6[AT32_SERIAL_USART6_OUT_BUF_SIZE]; +#endif + +#if AT32_SERIAL_USE_UART7 || defined(__DOXYGEN__) +/** @brief Input buffer for SD7.*/ +static uint8_t sd_in_buf7[AT32_SERIAL_UART7_IN_BUF_SIZE]; + +/** @brief Output buffer for SD7.*/ +static uint8_t sd_out_buf7[AT32_SERIAL_UART7_OUT_BUF_SIZE]; +#endif + +#if AT32_SERIAL_USE_UART8 || defined(__DOXYGEN__) +/** @brief Input buffer for SD8.*/ +static uint8_t sd_in_buf8[AT32_SERIAL_UART8_IN_BUF_SIZE]; + +/** @brief Output buffer for SD8.*/ +static uint8_t sd_out_buf8[AT32_SERIAL_UART8_OUT_BUF_SIZE]; +#endif + /*===========================================================================*/ /* Driver local functions. */ /*===========================================================================*/ @@ -101,13 +182,16 @@ static const SerialConfig default_config = * @param[in] sdp pointer to a @p SerialDriver object * @param[in] config the architecture-dependent serial driver configuration */ -static void usart_init(SerialDriver *sdp, const SerialConfig *config) { - uint32_t baudr; +static void usart_init(SerialDriver *sdp, + const SerialConfig *config) { + uint32_t baudr, clock; USART_TypeDef *u = sdp->usart; - baudr = (uint32_t)((sdp->clock + config->speed/2) / config->speed); + /* Baud rate setting.*/ + clock = sdp->clock; + baudr = (uint32_t)((clock + config->speed / 2) / config->speed); - osalDbgAssert(baudr < 0x10000, "invalid BAUDR value"); + osalDbgAssert(baudr < 0x10000, "invalid BAUDR value"); u->BAUDR = baudr; @@ -117,14 +201,21 @@ static void usart_init(SerialDriver *sdp, const SerialConfig *config) { u->CTRL1 = config->ctrl1 | USART_CTRL1_UEN | USART_CTRL1_PERRIEN | USART_CTRL1_RDBFIEN | USART_CTRL1_TEN | USART_CTRL1_REN; - u->STS = 0; - (void)u->STS; /* STS reset step 1.*/ - (void)u->DT; /* STS reset step 2.*/ + u->IFC = 0xFFFFFFFFU; /* Deciding mask to be applied on the data register on receive, this is required in order to mask out the parity bit.*/ - if ((config->ctrl1 & (USART_CTRL1_DBN | USART_CTRL1_PEN)) == USART_CTRL1_PEN) { - sdp->rxmask = 0x7F; + if ((config->ctrl1 & USART_CTRL1_PEN) != 0U) { + switch (config->ctrl1 & (USART_CTRL1_DBN_1 | USART_CTRL1_DBN_0)) { + case 0: + sdp->rxmask = 0x7F; + break; + case USART_CTRL1_DBN_1: + sdp->rxmask = 0x3F; + break; + default: + sdp->rxmask = 0xFF; + } } else { sdp->rxmask = 0xFF; @@ -161,7 +252,9 @@ static void set_error(SerialDriver *sdp, uint16_t sts) { status |= SD_FRAMING_ERROR; if (sts & USART_STS_NERR) status |= SD_NOISE_ERROR; + osalSysLockFromISR(); chnAddFlagsI(sdp, status); + osalSysUnlockFromISR(); } #if AT32_SERIAL_USE_USART1 || defined(__DOXYGEN__) @@ -412,7 +505,9 @@ OSAL_IRQ_HANDLER(AT32_UART8_HANDLER) { void sd_lld_init(void) { #if AT32_SERIAL_USE_USART1 - sdObjectInit(&SD1, NULL, notify1); + sdObjectInit(&SD1); + iqObjectInit(&SD1.iqueue, sd_in_buf1, sizeof sd_in_buf1, NULL, &SD1); + oqObjectInit(&SD1.oqueue, sd_out_buf1, sizeof sd_out_buf1, notify1, &SD1); SD1.usart = USART1; SD1.clock = AT32_PCLK2; #if !defined(AT32_USART1_SUPPRESS_ISR) && defined(AT32_USART1_NUMBER) @@ -421,7 +516,9 @@ void sd_lld_init(void) { #endif #if AT32_SERIAL_USE_USART2 - sdObjectInit(&SD2, NULL, notify2); + sdObjectInit(&SD2); + iqObjectInit(&SD2.iqueue, sd_in_buf2, sizeof sd_in_buf2, NULL, &SD2); + oqObjectInit(&SD2.oqueue, sd_out_buf2, sizeof sd_out_buf2, notify2, &SD2); SD2.usart = USART2; SD2.clock = AT32_PCLK1; #if !defined(AT32_USART2_SUPPRESS_ISR) && defined(AT32_USART2_NUMBER) @@ -430,7 +527,9 @@ void sd_lld_init(void) { #endif #if AT32_SERIAL_USE_USART3 - sdObjectInit(&SD3, NULL, notify3); + sdObjectInit(&SD3); + iqObjectInit(&SD3.iqueue, sd_in_buf3, sizeof sd_in_buf3, NULL, &SD3); + oqObjectInit(&SD3.oqueue, sd_out_buf3, sizeof sd_out_buf3, notify3, &SD3); SD3.usart = USART3; SD3.clock = AT32_PCLK1; #if !defined(AT32_USART3_SUPPRESS_ISR) && defined(AT32_USART3_NUMBER) @@ -439,7 +538,9 @@ void sd_lld_init(void) { #endif #if AT32_SERIAL_USE_UART4 - sdObjectInit(&SD4, NULL, notify4); + sdObjectInit(&SD4); + iqObjectInit(&SD4.iqueue, sd_in_buf4, sizeof sd_in_buf4, NULL, &SD4); + oqObjectInit(&SD4.oqueue, sd_out_buf4, sizeof sd_out_buf4, notify4, &SD4); SD4.usart = UART4; SD4.clock = AT32_PCLK1; #if !defined(AT32_UART4_SUPPRESS_ISR) && defined(AT32_UART4_NUMBER) @@ -448,7 +549,9 @@ void sd_lld_init(void) { #endif #if AT32_SERIAL_USE_UART5 - sdObjectInit(&SD5, NULL, notify5); + sdObjectInit(&SD5); + iqObjectInit(&SD5.iqueue, sd_in_buf5, sizeof sd_in_buf5, NULL, &SD5); + oqObjectInit(&SD5.oqueue, sd_out_buf5, sizeof sd_out_buf5, notify5, &SD5); SD5.usart = UART5; SD5.clock = AT32_PCLK1; #if !defined(AT32_UART5_SUPPRESS_ISR) && defined(AT32_UART5_NUMBER) @@ -457,7 +560,9 @@ void sd_lld_init(void) { #endif #if AT32_SERIAL_USE_USART6 - sdObjectInit(&SD6, NULL, notify3); + sdObjectInit(&SD6); + iqObjectInit(&SD6.iqueue, sd_in_buf6, sizeof sd_in_buf6, NULL, &SD6); + oqObjectInit(&SD6.oqueue, sd_out_buf6, sizeof sd_out_buf6, notify6, &SD6); SD6.usart = USART6; SD6.clock = AT32_PCLK2; #if !defined(AT32_USART6_SUPPRESS_ISR) && defined(AT32_USART6_NUMBER) @@ -466,7 +571,9 @@ void sd_lld_init(void) { #endif #if AT32_SERIAL_USE_UART7 - sdObjectInit(&SD7, NULL, notify4); + sdObjectInit(&SD7); + iqObjectInit(&SD7.iqueue, sd_in_buf7, sizeof sd_in_buf7, NULL, &SD7); + oqObjectInit(&SD7.oqueue, sd_out_buf7, sizeof sd_out_buf7, notify7, &SD7); SD7.usart = UART7; SD7.clock = AT32_PCLK1; #if !defined(AT32_UART7_SUPPRESS_ISR) && defined(AT32_UART7_NUMBER) @@ -475,14 +582,15 @@ void sd_lld_init(void) { #endif #if AT32_SERIAL_USE_UART8 - sdObjectInit(&SD8, NULL, notify5); + sdObjectInit(&SD8); + iqObjectInit(&SD8.iqueue, sd_in_buf8, sizeof sd_in_buf8, NULL, &SD8); + oqObjectInit(&SD8.oqueue, sd_out_buf8, sizeof sd_out_buf8, notify8, &SD8); SD8.usart = UART8; SD8.clock = AT32_PCLK1; #if !defined(AT32_UART8_SUPPRESS_ISR) && defined(AT32_UART8_NUMBER) nvicEnableVector(AT32_UART8_NUMBER, AT32_SERIAL_UART8_PRIORITY); #endif #endif - } /** @@ -557,7 +665,9 @@ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { void sd_lld_stop(SerialDriver *sdp) { if (sdp->state == SD_READY) { + /* UART is de-initialized then clocks are disabled.*/ usart_deinit(sdp->usart); + #if AT32_SERIAL_USE_USART1 if (&SD1 == sdp) { crmDisableUSART1(); @@ -616,48 +726,63 @@ void sd_lld_stop(SerialDriver *sdp) { */ void sd_lld_serve_interrupt(SerialDriver *sdp) { USART_TypeDef *u = sdp->usart; - uint16_t ctrl1; - uint16_t sts = u->STS; + uint32_t ctrl1; + uint32_t sts; + + /* Reading and clearing status.*/ + sts = u->STS; + u->IFC = sts; + + /* Error condition detection.*/ + if (sts & (USART_STS_ROERR | USART_STS_NERR | USART_STS_FERR | USART_STS_PERR)) + set_error(sdp, sts); /* Special case, LIN break detection.*/ if (sts & USART_STS_BFF) { osalSysLockFromISR(); chnAddFlagsI(sdp, SD_BREAK_DETECTED); - u->STS = ~USART_STS_BFF; osalSysUnlockFromISR(); } - /* Data available.*/ - osalSysLockFromISR(); - while (sts & (USART_STS_RDBF | USART_STS_ROERR | USART_STS_NERR | USART_STS_FERR | - USART_STS_PERR)) { - uint8_t b; - - /* Error condition detection.*/ - if (sts & (USART_STS_ROERR | USART_STS_NERR | USART_STS_FERR | USART_STS_PERR)) - set_error(sdp, sts); - b = (uint8_t)u->DT & sdp->rxmask; - if (sts & USART_STS_RDBF) - sdIncomingDataI(sdp, b); + /* Data available, note it is a while in order to handle two situations: + 1) Another byte arrived after removing the previous one, this would cause + an extra interrupt to serve. + 2) FIFO mode is enabled on devices that support it, we need to empty + the FIFO.*/ + while (sts & USART_STS_RDBF) { + osalSysLockFromISR(); + sdIncomingDataI(sdp, (uint8_t)u->DT & sdp->rxmask); + osalSysUnlockFromISR(); + sts = u->STS; } - osalSysUnlockFromISR(); /* Caching CTRL1.*/ ctrl1 = u->CTRL1; - /* Transmission buffer empty.*/ - if ((ctrl1 & USART_CTRL1_TDBEIEN) && (sts & USART_STS_TDBE)) { - msg_t b; - osalSysLockFromISR(); - b = oqGetI(&sdp->oqueue); - if (b < MSG_OK) { - chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY); - ctrl1 &= ~USART_CTRL1_TDBEIEN; - } - else + /* Transmission buffer empty, note it is a while in order to handle two + situations: + 1) The data registers has been emptied immediately after writing it, this + would cause an extra interrupt to serve. + 2) FIFO mode is enabled on devices that support it, we need to fill + the FIFO.*/ + if (ctrl1 & USART_CTRL1_TDBEIEN) { + while (sts & USART_STS_TDBE) { + msg_t b; + + osalSysLockFromISR(); + b = oqGetI(&sdp->oqueue); + if (b < MSG_OK) { + chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY); + ctrl1 &= ~USART_CTRL1_TDBEIEN; + osalSysUnlockFromISR(); + break; + } u->DT = b; - osalSysUnlockFromISR(); + osalSysUnlockFromISR(); + + sts = u->STS; + } } /* Physical transmission end.*/ diff --git a/os/hal/ports/AT32/LLD/USARTv2/hal_serial_lld.h b/os/hal/ports/AT32/LLD/USARTv2/hal_serial_lld.h index 86998e70cd..5777ff8723 100644 --- a/os/hal/ports/AT32/LLD/USARTv2/hal_serial_lld.h +++ b/os/hal/ports/AT32/LLD/USARTv2/hal_serial_lld.h @@ -1,8 +1,8 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian - ChibiOS - Copyright (C) 2023..2024 Maxjta + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + ChibiOS - Copyright (C) 2024..2025 Maxjta Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -30,10 +30,21 @@ #if HAL_USE_SERIAL || defined(__DOXYGEN__) +#include "at32_usart.h" + /*===========================================================================*/ /* Driver constants. */ /*===========================================================================*/ +/** + * @brief Advanced buffering support switch. + * @details This constants enables the advanced buffering support in the + * low level driver, the queue buffer is no more part of the + * @p SerialDriver structure, each driver can have a different + * queue size. + */ +#define SERIAL_ADVANCED_BUFFERING_SUPPORT TRUE + /*===========================================================================*/ /* Driver pre-compile time settings. */ /*===========================================================================*/ @@ -170,6 +181,117 @@ #define AT32_SERIAL_UART8_PRIORITY 12 #endif +/** + * @brief Input buffer size for USART1. + */ +#if !defined(AT32_SERIAL_USART1_IN_BUF_SIZE) || defined(__DOXYGEN__) +#define AT32_SERIAL_USART1_IN_BUF_SIZE SERIAL_BUFFERS_SIZE +#endif + +/** + * @brief Output buffer size for USART1. + */ +#if !defined(AT32_SERIAL_USART1_OUT_BUF_SIZE) || defined(__DOXYGEN__) +#define AT32_SERIAL_USART1_OUT_BUF_SIZE SERIAL_BUFFERS_SIZE +#endif + +/** + * @brief Input buffer size for USART2. + */ +#if !defined(AT32_SERIAL_USART2_IN_BUF_SIZE) || defined(__DOXYGEN__) +#define AT32_SERIAL_USART2_IN_BUF_SIZE SERIAL_BUFFERS_SIZE +#endif + +/** + * @brief Output buffer size for USART2. + */ +#if !defined(AT32_SERIAL_USART2_OUT_BUF_SIZE) || defined(__DOXYGEN__) +#define AT32_SERIAL_USART2_OUT_BUF_SIZE SERIAL_BUFFERS_SIZE +#endif + +/** + * @brief Input buffer size for USART3. + */ +#if !defined(AT32_SERIAL_USART3_IN_BUF_SIZE) || defined(__DOXYGEN__) +#define AT32_SERIAL_USART3_IN_BUF_SIZE SERIAL_BUFFERS_SIZE +#endif + +/** + * @brief Output buffer size for USART3. + */ +#if !defined(AT32_SERIAL_USART3_OUT_BUF_SIZE) || defined(__DOXYGEN__) +#define AT32_SERIAL_USART3_OUT_BUF_SIZE SERIAL_BUFFERS_SIZE +#endif + +/** + * @brief Input buffer size for UART4. + */ +#if !defined(AT32_SERIAL_UART4_IN_BUF_SIZE) || defined(__DOXYGEN__) +#define AT32_SERIAL_UART4_IN_BUF_SIZE SERIAL_BUFFERS_SIZE +#endif + +/** + * @brief Output buffer size for UART4. + */ +#if !defined(AT32_SERIAL_UART4_OUT_BUF_SIZE) || defined(__DOXYGEN__) +#define AT32_SERIAL_UART4_OUT_BUF_SIZE SERIAL_BUFFERS_SIZE +#endif + +/** + * @brief Input buffer size for UART5. + */ +#if !defined(AT32_SERIAL_UART5_IN_BUF_SIZE) || defined(__DOXYGEN__) +#define AT32_SERIAL_UART5_IN_BUF_SIZE SERIAL_BUFFERS_SIZE +#endif + +/** + * @brief Output buffer size for UART5. + */ +#if !defined(AT32_SERIAL_UART5_OUT_BUF_SIZE) || defined(__DOXYGEN__) +#define AT32_SERIAL_UART5_OUT_BUF_SIZE SERIAL_BUFFERS_SIZE +#endif + +/** + * @brief Input buffer size for USART6. + */ +#if !defined(AT32_SERIAL_USART6_IN_BUF_SIZE) || defined(__DOXYGEN__) +#define AT32_SERIAL_USART6_IN_BUF_SIZE SERIAL_BUFFERS_SIZE +#endif + +/** + * @brief Output buffer size for USART6. + */ +#if !defined(AT32_SERIAL_USART6_OUT_BUF_SIZE) || defined(__DOXYGEN__) +#define AT32_SERIAL_USART6_OUT_BUF_SIZE SERIAL_BUFFERS_SIZE +#endif + +/** + * @brief Input buffer size for UART7. + */ +#if !defined(AT32_SERIAL_UART7_IN_BUF_SIZE) || defined(__DOXYGEN__) +#define AT32_SERIAL_UART7_IN_BUF_SIZE SERIAL_BUFFERS_SIZE +#endif + +/** + * @brief Output buffer size for UART7. + */ +#if !defined(AT32_SERIAL_UART7_OUT_BUF_SIZE) || defined(__DOXYGEN__) +#define AT32_SERIAL_UART7_OUT_BUF_SIZE SERIAL_BUFFERS_SIZE +#endif + +/** + * @brief Input buffer size for UART8. + */ +#if !defined(AT32_SERIAL_UART8_IN_BUF_SIZE) || defined(__DOXYGEN__) +#define AT32_SERIAL_UART8_IN_BUF_SIZE SERIAL_BUFFERS_SIZE +#endif + +/** + * @brief Output buffer size for UART8. + */ +#if !defined(AT32_SERIAL_UART8_OUT_BUF_SIZE) || defined(__DOXYGEN__) +#define AT32_SERIAL_UART8_OUT_BUF_SIZE SERIAL_BUFFERS_SIZE +#endif /** @} */ /*===========================================================================*/ @@ -210,47 +332,55 @@ #if !AT32_SERIAL_USE_USART1 && !AT32_SERIAL_USE_USART2 && \ !AT32_SERIAL_USE_USART3 && !AT32_SERIAL_USE_UART4 && \ - !AT32_SERIAL_USE_UART5 && !AT32_SERIAL_USE_USART6 && \ - !AT32_SERIAL_USE_UART7 && !AT32_SERIAL_USE_UART8 + !AT32_SERIAL_USE_UART5 && !AT32_SERIAL_USE_USART6 && \ + !AT32_SERIAL_USE_UART7 && !AT32_SERIAL_USE_UART8 #error "SERIAL driver activated but no USART/UART peripheral assigned" #endif -#if AT32_SERIAL_USE_USART1 && \ +#if !defined(AT32_USART1_SUPPRESS_ISR) && \ + AT32_SERIAL_USE_USART1 && \ !OSAL_IRQ_IS_VALID_PRIORITY(AT32_SERIAL_USART1_PRIORITY) #error "Invalid IRQ priority assigned to USART1" #endif -#if AT32_SERIAL_USE_USART2 && \ +#if !defined(AT32_USART2_SUPPRESS_ISR) && \ + AT32_SERIAL_USE_USART2 && \ !OSAL_IRQ_IS_VALID_PRIORITY(AT32_SERIAL_USART2_PRIORITY) #error "Invalid IRQ priority assigned to USART2" #endif -#if AT32_SERIAL_USE_USART3 && \ +#if !defined(AT32_USART3_SUPPRESS_ISR) && \ + AT32_SERIAL_USE_USART3 && \ !OSAL_IRQ_IS_VALID_PRIORITY(AT32_SERIAL_USART3_PRIORITY) #error "Invalid IRQ priority assigned to USART3" #endif -#if AT32_SERIAL_USE_UART4 && \ +#if !defined(AT32_UART4_SUPPRESS_ISR) && \ + AT32_SERIAL_USE_UART4 && \ !OSAL_IRQ_IS_VALID_PRIORITY(AT32_SERIAL_UART4_PRIORITY) #error "Invalid IRQ priority assigned to UART4" #endif -#if AT32_SERIAL_USE_UART5 && \ +#if !defined(AT32_UART5_SUPPRESS_ISR) && \ + AT32_SERIAL_USE_UART5 && \ !OSAL_IRQ_IS_VALID_PRIORITY(AT32_SERIAL_UART5_PRIORITY) #error "Invalid IRQ priority assigned to UART5" #endif -#if AT32_SERIAL_USE_USART6 && \ +#if !defined(AT32_USART6_SUPPRESS_ISR) && \ + AT32_SERIAL_USE_USART6 && \ !OSAL_IRQ_IS_VALID_PRIORITY(AT32_SERIAL_USART6_PRIORITY) #error "Invalid IRQ priority assigned to USART6" #endif -#if AT32_SERIAL_USE_UART7 && \ +#if !defined(AT32_UART7_SUPPRESS_ISR) && \ + AT32_SERIAL_USE_UART7 && \ !OSAL_IRQ_IS_VALID_PRIORITY(AT32_SERIAL_UART7_PRIORITY) #error "Invalid IRQ priority assigned to UART7" #endif -#if AT32_SERIAL_USE_UART8 && \ +#if !defined(AT32_UART8_SUPPRESS_ISR) && \ + AT32_SERIAL_USE_UART8 && \ !OSAL_IRQ_IS_VALID_PRIORITY(AT32_SERIAL_UART8_PRIORITY) #error "Invalid IRQ priority assigned to UART8" #endif @@ -341,15 +471,15 @@ typedef struct hal_serial_config { /** * @brief Initialization value for the CTRL1 register. */ - uint16_t ctrl1; + uint32_t ctrl1; /** * @brief Initialization value for the CTRL2 register. */ - uint16_t ctrl2; + uint32_t ctrl2; /** * @brief Initialization value for the CTRL3 register. */ - uint16_t ctrl3; + uint32_t ctrl3; } SerialConfig; /** @@ -363,10 +493,6 @@ typedef struct hal_serial_config { input_queue_t iqueue; \ /* Output queue.*/ \ output_queue_t oqueue; \ - /* Input circular buffer.*/ \ - uint8_t ib[SERIAL_BUFFERS_SIZE]; \ - /* Output circular buffer.*/ \ - uint8_t ob[SERIAL_BUFFERS_SIZE]; \ /* End of the mandatory fields.*/ \ /* Pointer to the USART registers block.*/ \ USART_TypeDef *usart; \ @@ -379,14 +505,6 @@ typedef struct hal_serial_config { /* Driver macros. */ /*===========================================================================*/ -/* - * Extra USARTs definitions here (missing from the AT header file). - */ -#define USART_CTRL2_STOPBN1_BITS (0 << 12) /**< @brief CTRL2 1 stop bit value.*/ -#define USART_CTRL2_STOPBN0P5_BITS (1 << 12) /**< @brief CTRL2 0.5 stop bit value.*/ -#define USART_CTRL2_STOPBN2_BITS (2 << 12) /**< @brief CTRL2 2 stop bit value.*/ -#define USART_CTRL2_STOPBN1P5_BITS (3 << 12) /**< @brief CTRL2 1.5 stop bit value.*/ - /*===========================================================================*/ /* External declarations. */ /*===========================================================================*/ diff --git a/os/hal/ports/AT32/LLD/USARTv2/hal_sio_lld.c b/os/hal/ports/AT32/LLD/USARTv2/hal_sio_lld.c new file mode 100644 index 0000000000..e6f0a151c7 --- /dev/null +++ b/os/hal/ports/AT32/LLD/USARTv2/hal_sio_lld.c @@ -0,0 +1,788 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file USARTv2/hal_sio_lld.c + * @brief AT32 SIO subsystem low level driver source. + * + * @addtogroup SIO + * @{ + */ + +#include "hal.h" + +#if (HAL_USE_SIO == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +#define USART_CTRL1_CFG_FORBIDDEN (USART_CTRL1_RETODIE | \ + USART_CTRL1_CMDIE | \ + USART_CTRL1_PERRIEN | \ + USART_CTRL1_TDBEIEN | \ + USART_CTRL1_TDCIEN | \ + USART_CTRL1_RDBFIEN | \ + USART_CTRL1_IDLEIEN | \ + USART_CTRL1_TEN | \ + USART_CTRL1_REN | \ + USART_CTRL1_UEN) +#define USART_CTRL2_CFG_FORBIDDEN (USART_CTRL2_BFIEN) +#define USART_CTRL3_CFG_FORBIDDEN (USART_CTRL3_CTSCFIEN | \ + USART_CTRL3_ERRIEN) + +/* This mask includes IDLEF, ROERR, NERR, FERR, PERR bits.*/ +#define USART_STS_IRNFP_Pos USART_STS_PERR_Pos +#define USART_STS_IRNFP_Msk (0x1FUL << USART_STS_IRNFP_Pos) + +/* This mask includes ROERR, NERR, FERR, PERR bits.*/ +#define USART_STS_RNFP_Pos USART_STS_PERR_Pos +#define USART_STS_RNFP_Msk (0xFUL << USART_STS_RNFP_Pos) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief USART1 SIO driver identifier. + */ +#if (AT32_SIO_USE_USART1 == TRUE) || defined(__DOXYGEN__) +SIODriver SIOD1; +#endif + +/** + * @brief USART2 SIO driver identifier. + */ +#if (AT32_SIO_USE_USART2 == TRUE) || defined(__DOXYGEN__) +SIODriver SIOD2; +#endif + +/** + * @brief USART3 SIO driver identifier. + */ +#if (AT32_SIO_USE_USART3 == TRUE) || defined(__DOXYGEN__) +SIODriver SIOD3; +#endif + +/** + * @brief UART4 SIO driver identifier. + */ +#if (AT32_SIO_USE_UART4 == TRUE) || defined(__DOXYGEN__) +SIODriver SIOD4; +#endif + +/** + * @brief UART5 SIO driver identifier. + */ +#if (AT32_SIO_USE_UART5 == TRUE) || defined(__DOXYGEN__) +SIODriver SIOD5; +#endif + +/** + * @brief USART6 SIO driver identifier. + */ +#if (AT32_SIO_USE_USART6 == TRUE) || defined(__DOXYGEN__) +SIODriver SIOD6; +#endif + +/** + * @brief UART7 SIO driver identifier. + */ +#if (AT32_SIO_USE_UART7 == TRUE) || defined(__DOXYGEN__) +SIODriver SIOD7; +#endif + +/** + * @brief UART8 SIO driver identifier. + */ +#if (AT32_SIO_USE_UART8 == TRUE) || defined(__DOXYGEN__) +SIODriver SIOD8; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** + * @brief Driver default configuration. + * @note In this implementation it is: 38400-8-N-1. + */ +static const SIOConfig default_config = { + .baud = SIO_DEFAULT_BITRATE, + .ctrl1 = USART_CTRL1_DATA8, + .ctrl2 = USART_CTRL2_STOPBN1_BITS, + .ctrl3 = 0U +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +__STATIC_INLINE void usart_enable_rx_irq(SIODriver *siop) { + uint32_t ctrl1; + + ctrl1 = siop->usart->CTRL1; + if ((siop->enabled & SIO_EV_RXNOTEMPY) != 0U) { + ctrl1 |= USART_CTRL1_RDBFIEN; + } + if ((siop->enabled & SIO_EV_RXIDLE) != 0U) { + ctrl1 |= USART_CTRL1_IDLEIEN; + } + siop->usart->CTRL1 = ctrl1; +} + +__STATIC_INLINE void usart_enable_rx_errors_irq(SIODriver *siop) { + + siop->usart->CTRL1 |= __sio_reloc_field(siop->enabled, SIO_EV_PARITY_ERR, SIO_EV_PARITY_ERR_POS, USART_CTRL1_PERRIEN_Pos); + siop->usart->CTRL2 |= __sio_reloc_field(siop->enabled, SIO_EV_RXBREAK, SIO_EV_RXBREAK_POS, USART_CTRL2_BFIEN_Pos); + + /* The following 3 are grouped.*/ + if ((siop->enabled & (SIO_EV_FRAMING_ERR | + SIO_EV_OVERRUN_ERR | + SIO_EV_NOISE_ERR)) != 0U) { + siop->usart->CTRL3 |= USART_CTRL3_ERRIEN; + } +} + +__STATIC_INLINE void usart_enable_tx_irq(SIODriver *siop) { + + if ((siop->enabled & SIO_EV_TXNOTFULL) != 0U) { + siop->usart->CTRL1 |= USART_CTRL1_TDBEIEN; + } +} + +__STATIC_INLINE void usart_enable_tx_end_irq(SIODriver *siop) { + + if ((siop->enabled & SIO_EV_TXDONE) != 0U) { + siop->usart->CTRL1 |= USART_CTRL1_TDCIEN; + } +} + +/** + * @brief USART initialization. + * @details This function must be invoked with interrupts disabled. + * + * @param[in] siop pointer to a @p SIODriver object + */ +__STATIC_INLINE void usart_init(SIODriver *siop) { + USART_TypeDef *u = siop->usart; + uint32_t baudr; + + /* Baud rate setting.*/ + baudr = (uint32_t)((siop->clock) / siop->config->baud); + + osalDbgAssert(baudr < 0x10000, "invalid BAUDR value"); + + /* Setting up USART.*/ + u->CTRL1 = siop->config->ctrl1 & ~USART_CTRL1_CFG_FORBIDDEN; + u->CTRL2 = siop->config->ctrl2 & ~USART_CTRL2_CFG_FORBIDDEN; + u->CTRL3 = siop->config->ctrl3 & ~USART_CTRL3_CFG_FORBIDDEN; + u->BAUDR = baudr; + + /* Starting operations.*/ + u->IFC = u->STS; + u->CTRL1 |= USART_CTRL1_UEN | USART_CTRL1_TEN | USART_CTRL1_REN; +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level SIO driver initialization. + * + * @notapi + */ +void sio_lld_init(void) { + + /* Driver instances initialization.*/ +#if AT32_SIO_USE_USART1 == TRUE + sioObjectInit(&SIOD1); + SIOD1.usart = USART1; + SIOD1.clock = AT32_PCLK2; +#endif +#if AT32_SIO_USE_USART2 == TRUE + sioObjectInit(&SIOD2); + SIOD2.usart = USART2; + SIOD2.clock = AT32_PCLK1; +#endif +#if AT32_SIO_USE_USART3 == TRUE + sioObjectInit(&SIOD3); + SIOD3.usart = USART3; + SIOD3.clock = AT32_PCLK1; +#endif +#if AT32_SIO_USE_UART4 == TRUE + sioObjectInit(&SIOD4); + SIOD4.usart = UART4; + SIOD4.clock = AT32_PCLK1; +#endif +#if AT32_SIO_USE_UART5 == TRUE + sioObjectInit(&SIOD5); + SIOD5.usart = UART5; + SIOD5.clock = AT32_PCLK1; +#endif +#if AT32_SIO_USE_USART6 == TRUE + sioObjectInit(&SIOD6); + SIOD6.usart = USART6; + SIOD6.clock = AT32_PCLK2; +#endif +#if AT32_SIO_USE_UART7 == TRUE + sioObjectInit(&SIOD7); + SIOD7.usart = UART7; + SIOD7.clock = AT32_PCLK1; +#endif +#if AT32_SIO_USE_UART8 == TRUE + sioObjectInit(&SIOD8); + SIOD8.usart = UART8; + SIOD8.clock = AT32_PCLK1; +#endif +} + +/** + * @brief Configures and activates the SIO peripheral. + * + * @param[in] siop pointer to the @p SIODriver object + * @return The operation status. + * + * @notapi + */ +msg_t sio_lld_start(SIODriver *siop) { + + /* Using the default configuration if the application passed a + NULL pointer.*/ + if (siop->config == NULL) { + siop->config = &default_config; + } + + if (siop->state == SIO_STOP) { + + /* Enables the peripheral.*/ + if (false) { + } +#if AT32_SIO_USE_USART1 == TRUE + else if (&SIOD1 == siop) { + crmResetUSART1(); + crmEnableUSART1(true); + } +#endif +#if AT32_SIO_USE_USART2 == TRUE + else if (&SIOD2 == siop) { + crmResetUSART2(); + crmEnableUSART2(true); + } +#endif +#if AT32_SIO_USE_USART3 == TRUE + else if (&SIOD3 == siop) { + crmResetUSART3(); + crmEnableUSART3(true); + } +#endif +#if AT32_SIO_USE_UART4 == TRUE + else if (&SIOD4 == siop) { + crmResetUART4(); + crmEnableUART4(true); + } +#endif +#if AT32_SIO_USE_UART5 == TRUE + else if (&SIOD5 == siop) { + crmResetUART5(); + crmEnableUART5(true); + } +#endif +#if AT32_SIO_USE_USART6 == TRUE + else if (&SIOD6 == siop) { + crmResetUSART6(); + crmEnableUSART6(true); + } +#endif +#if AT32_SIO_USE_UART7 == TRUE + else if (&SIOD7 == siop) { + crmResetUART7(); + crmEnableUART7(true); + } +#endif +#if AT32_SIO_USE_UART8 == TRUE + else if (&SIOD8 == siop) { + crmResetUART8(); + crmEnableUART8(true); + } +#endif + else { + osalDbgAssert(false, "invalid SIO instance"); + } + } + + /* Configures the peripheral.*/ + usart_init(siop); + + return HAL_RET_SUCCESS; +} + +/** + * @brief Deactivates the SIO peripheral. + * + * @param[in] siop pointer to the @p SIODriver object + * + * @notapi + */ +void sio_lld_stop(SIODriver *siop) { + + if (siop->state == SIO_READY) { + /* Resets the peripheral.*/ + + /* Disables the peripheral.*/ + if (false) { + } +#if AT32_SIO_USE_USART1 == TRUE + else if (&SIOD1 == siop) { + crmResetUSART1(); + crmDisableUSART1(); + } +#endif +#if AT32_SIO_USE_USART2 == TRUE + else if (&SIOD2 == siop) { + crmResetUSART2(); + crmDisableUSART2(); + } +#endif +#if AT32_SIO_USE_USART3 == TRUE + else if (&SIOD3 == siop) { + crmResetUSART3(); + crmDisableUSART3(); + } +#endif +#if AT32_SIO_USE_UART4 == TRUE + else if (&SIOD4 == siop) { + crmResetUART4(); + crmDisableUART4(); + } +#endif +#if AT32_SIO_USE_UART5 == TRUE + else if (&SIOD5 == siop) { + crmResetUART5(); + crmDisableUART5(); + } +#endif +#if AT32_SIO_USE_USART6 == TRUE + else if (&SIOD6 == siop) { + crmResetUSART6(); + crmDisableUSART6(); + } +#endif +#if AT32_SIO_USE_UART7 == TRUE + else if (&SIOD7 == siop) { + crmResetUART7(); + crmDisableUART7(); + } +#endif +#if AT32_SIO_USE_UART8 == TRUE + else if (&SIOD8 == siop) { + crmResetUART8(); + crmDisableUART8(); + } +#endif + else { + osalDbgAssert(false, "invalid SIO instance"); + } + } +} + +/** + * @brief Enable flags change notification. + * + * @param[in] siop pointer to the @p SIODriver object + */ +void sio_lld_update_enable_flags(SIODriver *siop) { + uint32_t ctrl1, ctrl2, ctrl3; + + ctrl1 = siop->usart->CTRL1 & ~(USART_CTRL1_TDBEIEN | USART_CTRL1_RDBFIEN | + USART_CTRL1_IDLEIEN | USART_CTRL1_TDCIEN | + USART_CTRL1_PERRIEN); + ctrl2 = siop->usart->CTRL2 & ~(USART_CTRL2_BFIEN); + ctrl3 = siop->usart->CTRL3 & ~(USART_CTRL3_ERRIEN); + + ctrl1 |= __sio_reloc_field(siop->enabled, SIO_EV_RXNOTEMPY, SIO_EV_RXNOTEMPY_POS, USART_CTRL1_RDBFIEN_Pos) | + __sio_reloc_field(siop->enabled, SIO_EV_TXNOTFULL, SIO_EV_TXNOTFULL_POS, USART_CTRL1_TDBEIEN_Pos) | + __sio_reloc_field(siop->enabled, SIO_EV_RXIDLE, SIO_EV_RXIDLE_POS, USART_CTRL1_IDLEIEN_Pos) | + __sio_reloc_field(siop->enabled, SIO_EV_TXDONE, SIO_EV_TXDONE_POS, USART_CTRL1_TDCIEN_Pos) | + __sio_reloc_field(siop->enabled, SIO_EV_PARITY_ERR, SIO_EV_PARITY_ERR_POS, USART_CTRL1_PERRIEN_Pos); + ctrl2 |= __sio_reloc_field(siop->enabled, SIO_EV_RXBREAK, SIO_EV_RXBREAK_POS, USART_CTRL2_BFIEN_Pos); + + /* The following 3 are grouped.*/ + if ((siop->enabled & (SIO_EV_FRAMING_ERR | + SIO_EV_OVERRUN_ERR | + SIO_EV_NOISE_ERR)) != 0U) { + ctrl3 |= USART_CTRL3_ERRIEN; + } + + /* Setting up the operation.*/ + siop->usart->CTRL1 = ctrl1; + siop->usart->CTRL2 = ctrl2; + siop->usart->CTRL3 = ctrl3; +} + +/** + * @brief Get and clears SIO error event flags. + * + * @param[in] siop pointer to the @p SIODriver object + * @return The pending event flags. + * + * @notapi + */ +sioevents_t sio_lld_get_and_clear_errors(SIODriver *siop) { + uint32_t sts; + sioevents_t errors; + + /* Getting all error STS flags (and only those). + NOTE: Do not trust the position of other bits in STS/IFC because + some scientist decided to use different positions for some + of them.*/ + sts = siop->usart->STS & SIO_LLD_ISR_RX_ERRORS; + + /* Clearing captured events.*/ + siop->usart->IFC = sts; + + /* Status flags cleared, now the error-related interrupts can be + enabled again.*/ + usart_enable_rx_errors_irq(siop); + + /* Translating the status flags in SIO events.*/ + errors = __sio_reloc_field(sts, USART_STS_RNFP_Msk, USART_STS_RNFP_Pos, SIO_EV_ALL_ERRORS_POS) | + __sio_reloc_field(sts, USART_STS_BFF_Msk, USART_STS_BFF_Pos, SIO_EV_RXBREAK_POS); + + return errors; +} + +/** + * @brief Get and clears SIO event flags. + * + * @param[in] siop pointer to the @p SIODriver object + * @return The pending event flags. + * + * @notapi + */ +sioevents_t sio_lld_get_and_clear_events(SIODriver *siop) { + uint32_t sts; + sioevents_t events; + + /* Getting all STS flags. + NOTE: Do not trust the position of other bits in STS/IFC because + some scientist decided to use different positions for some + of them.*/ + sts = siop->usart->STS & (SIO_LLD_ISR_RX_ERRORS | + USART_STS_RDBF | + USART_STS_IDLEF | + USART_STS_TDBE | + USART_STS_TDC); + + /* Clearing captured events.*/ + siop->usart->IFC = sts; + + /* Status flags cleared, now the RX-related interrupts can be + enabled again.*/ + usart_enable_rx_irq(siop); + usart_enable_rx_errors_irq(siop); + + /* Translating the status flags in SIO events.*/ + events = __sio_reloc_field(sts, USART_STS_RDBF_Msk, USART_STS_RDBF_Pos, SIO_EV_RXNOTEMPY_POS) | + __sio_reloc_field(sts, USART_STS_TDBE_Msk, USART_STS_TDBE_Pos, SIO_EV_TXNOTFULL_POS) | + __sio_reloc_field(sts, USART_STS_TDC_Msk, USART_STS_TDC_Pos, SIO_EV_TXDONE_POS) | + __sio_reloc_field(sts, USART_STS_IRNFP_Msk, USART_STS_IRNFP_Pos, SIO_EV_ALL_ERRORS_POS) | + __sio_reloc_field(sts, USART_STS_BFF_Msk, USART_STS_BFF_Pos, SIO_EV_RXBREAK_POS); + + return events; +} + +/** + * @brief Returns the pending SIO event flags. + * + * @param[in] siop pointer to the @p SIODriver object + * @return The pending event flags. + * + * @notapi + */ +sioevents_t sio_lld_get_events(SIODriver *siop) { + uint32_t sts; + sioevents_t events; + + /* Getting all STS flags.*/ + sts = siop->usart->STS & (SIO_LLD_ISR_RX_ERRORS | + USART_STS_RDBF | + USART_STS_IDLEF | + USART_STS_TDBE | + USART_STS_TDC); + + /* Translating the status flags in SIO events.*/ + events = __sio_reloc_field(sts, USART_STS_RDBF_Msk, USART_STS_RDBF_Pos, SIO_EV_RXNOTEMPY_POS) | + __sio_reloc_field(sts, USART_STS_TDBE_Msk, USART_STS_TDBE_Pos, SIO_EV_TXNOTFULL_POS) | + __sio_reloc_field(sts, USART_STS_TDC_Msk, USART_STS_TDC_Pos, SIO_EV_TXDONE_POS) | + __sio_reloc_field(sts, USART_STS_IRNFP_Msk, USART_STS_IRNFP_Pos, SIO_EV_ALL_ERRORS_POS) | + __sio_reloc_field(sts, USART_STS_BFF_Msk, USART_STS_BFF_Pos, SIO_EV_RXBREAK_POS); + + return events; +} + +/** + * @brief Reads data from the RX FIFO. + * @details The function is not blocking, it writes frames until there + * is space available without waiting. + * + * @param[in] siop pointer to an @p SIODriver structure + * @param[in] buffer pointer to the buffer for read frames + * @param[in] n maximum number of frames to be read + * @return The number of frames copied from the buffer. + * @retval 0 if the TX FIFO is full. + */ +size_t sio_lld_read(SIODriver *siop, uint8_t *buffer, size_t n) { + size_t rd; + + rd = 0U; + while (true) { + + /* If the RX FIFO has been emptied then the RX FIFO and IDLE interrupts + are enabled again.*/ + if (sio_lld_is_rx_empty(siop)) { + usart_enable_rx_irq(siop); + break; + } + + /* Buffer filled condition.*/ + if (rd >= n) { + break; + } + + *buffer++ = (uint8_t)siop->usart->DT; + rd++; + } + + return rd; +} + +/** + * @brief Writes data into the TX FIFO. + * @details The function is not blocking, it writes frames until there + * is space available without waiting. + * + * @param[in] siop pointer to an @p SIODriver structure + * @param[in] buffer pointer to the buffer for read frames + * @param[in] n maximum number of frames to be written + * @return The number of frames copied from the buffer. + * @retval 0 if the TX FIFO is full. + */ +size_t sio_lld_write(SIODriver *siop, const uint8_t *buffer, size_t n) { + size_t wr; + + wr = 0U; + while (true) { + + /* If the TX FIFO has been filled then the interrupt is enabled again.*/ + if (sio_lld_is_tx_full(siop)) { + usart_enable_tx_irq(siop); + break; + } + + /* Buffer emptied condition.*/ + if (wr >= n) { + break; + } + + siop->usart->DT = (uint32_t)*buffer++; + wr++; + } + + /* The transmit complete interrupt is always re-enabled on write.*/ + usart_enable_tx_end_irq(siop); + + return wr; +} + +/** + * @brief Returns one frame from the RX FIFO. + * @note If the FIFO is empty then the returned value is unpredictable. + * + * @param[in] siop pointer to the @p SIODriver object + * @return The frame from RX FIFO. + * + * @notapi + */ +msg_t sio_lld_get(SIODriver *siop) { + msg_t msg; + + msg = (msg_t)siop->usart->DT; + + /* If the RX FIFO has been emptied then the interrupt is enabled again.*/ + if (sio_lld_is_rx_empty(siop)) { + usart_enable_rx_irq(siop); + } + + return msg; +} + +/** + * @brief Pushes one frame into the TX FIFO. + * @note If the FIFO is full then the behavior is unpredictable. + * + * @param[in] siop pointer to the @p SIODriver object + * @param[in] data frame to be written + * + * @notapi + */ +void sio_lld_put(SIODriver *siop, uint_fast16_t data) { + + siop->usart->DT = data; + + /* If the TX FIFO has been filled then the interrupt is enabled again.*/ + if (sio_lld_is_tx_full(siop)) { + usart_enable_tx_irq(siop); + } + + /* The transmit complete interrupt is always re-enabled on write.*/ + usart_enable_tx_end_irq(siop); +} + +/** + * @brief Control operation on a serial port. + * + * @param[in] siop pointer to the @p SIODriver object + * @param[in] operation control operation code + * @param[in,out] arg operation argument + * + * @return The control operation status. + * @retval MSG_OK in case of success. + * @retval MSG_TIMEOUT in case of operation timeout. + * @retval MSG_RESET in case of operation reset. + * + * @notapi + */ +msg_t sio_lld_control(SIODriver *siop, unsigned int operation, void *arg) { + + (void)siop; + (void)operation; + (void)arg; + + return MSG_OK; +} + +/** + * @brief Serves an USART interrupt. + * + * @param[in] siop pointer to the @p SIODriver object + * + * @notapi + */ +void sio_lld_serve_interrupt(SIODriver *siop) { + USART_TypeDef *u = siop->usart; + uint32_t ctrl1, ctrl2, ctrl3, sts, stsmask; + + osalDbgAssert(siop->state == SIO_READY, "invalid state"); + + /* Read on control registers.*/ + ctrl1 = u->CTRL1; + ctrl2 = u->CTRL2; + ctrl3 = u->CTRL3; + + /* Calculating the mask of status bits that should be processed according + to the state of the various CRx registers.*/ + stsmask = __sio_reloc_field(ctrl1, USART_CTRL1_TDBEIEN, USART_CTRL1_TDBEIEN_Pos, USART_STS_TDBE_Pos) | + __sio_reloc_field(ctrl1, USART_CTRL1_RDBFIEN, USART_CTRL1_RDBFIEN_Pos, USART_STS_RDBF_Pos) | + __sio_reloc_field(ctrl1, USART_CTRL1_IDLEIEN, USART_CTRL1_IDLEIEN_Pos, USART_STS_IDLEF_Pos) | + __sio_reloc_field(ctrl1, USART_CTRL1_TDCIEN, USART_CTRL1_TDCIEN_Pos, USART_STS_TDC_Pos) | + __sio_reloc_field(ctrl1, USART_CTRL1_PERRIEN, USART_CTRL1_PERRIEN_Pos, USART_STS_PERR_Pos) | + __sio_reloc_field(ctrl2, USART_CTRL2_BFIEN, USART_CTRL2_BFIEN_Pos, USART_STS_BFF_Pos); + if ((ctrl3 & USART_CTRL3_ERRIEN) != 0U) { + stsmask |= USART_STS_NERR | USART_STS_FERR | USART_STS_ROERR; + } + + /* Status flags to be processed.*/ + sts = u->STS & stsmask; + if (sts != 0U) { + + /* Error flags handled as a group.*/ + if ((sts & SIO_LLD_ISR_RX_ERRORS) != 0U) { + /* All RX-related interrupt sources disabled.*/ + ctrl1 &= ~(USART_CTRL1_PERRIEN | USART_CTRL1_RDBFIEN | USART_CTRL1_IDLEIEN); + ctrl2 &= ~(USART_CTRL2_BFIEN); + ctrl3 &= ~(USART_CTRL3_ERRIEN); + + /* Waiting thread woken, if any.*/ + __sio_wakeup_errors(siop); + } + /* If there are no errors then we check for the other RX-related + status flags.*/ + else { + /* Idle RX flag.*/ + if ((sts & USART_STS_IDLEF) != 0U) { + + /* Interrupt source disabled.*/ + ctrl1 &= ~USART_CTRL1_IDLEIEN; + + /* Waiting thread woken, if any.*/ + __sio_wakeup_rxidle(siop); + } + + /* RX FIFO is non-empty.*/ + if ((sts & USART_STS_RDBF) != 0U) { + + /* Interrupt source disabled.*/ + ctrl1 &= ~USART_CTRL1_RDBFIEN; + + /* Waiting thread woken, if any.*/ + __sio_wakeup_rx(siop); + } + } + + /* TX FIFO is non-full.*/ + if ((sts & USART_STS_TDBE) != 0U) { + + /* Interrupt source disabled.*/ + ctrl1 &= ~USART_CTRL1_TDBEIEN; + + /* Waiting thread woken, if any.*/ + __sio_wakeup_tx(siop); + } + + /* Physical transmission end.*/ + if ((sts & USART_STS_TDC) != 0U) { + + /* Interrupt source disabled.*/ + ctrl1 &= ~USART_CTRL1_TDCIEN; + + /* Waiting thread woken, if any.*/ + __sio_wakeup_txend(siop); + } + + /* Updating control registers, some sources could have been disabled.*/ + u->CTRL1 = ctrl1; + u->CTRL2 = ctrl2; + u->CTRL3 = ctrl3; + + /* The callback is invoked.*/ + __sio_callback(siop); + } + else { + osalDbgAssert(false, "spurious interrupt"); + } +} + +#endif /* HAL_USE_SIO == TRUE */ + +/** @} */ diff --git a/os/hal/ports/AT32/LLD/USARTv2/hal_sio_lld.h b/os/hal/ports/AT32/LLD/USARTv2/hal_sio_lld.h new file mode 100644 index 0000000000..e4d66dc3ee --- /dev/null +++ b/os/hal/ports/AT32/LLD/USARTv2/hal_sio_lld.h @@ -0,0 +1,391 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file USARTv2/hal_sio_lld.h + * @brief AT32 SIO subsystem low level driver header. + * + * @addtogroup SIO + * @{ + */ + +#ifndef HAL_SIO_LLD_H +#define HAL_SIO_LLD_H + +#if (HAL_USE_SIO == TRUE) || defined(__DOXYGEN__) + +#include "at32_usart.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Mask of RX-related errors in the ISR register. + */ +#define SIO_LLD_ISR_RX_ERRORS (USART_STS_NERR | USART_STS_FERR | \ + USART_STS_PERR | USART_STS_ROERR | \ + USART_STS_BFF) + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name AT32 configuration options + * @{ + */ +/** + * @brief SIO driver 1 enable switch. + * @details If set to @p TRUE the support for USART1 is included. + * @note The default is @p FALSE. + */ +#if !defined(AT32_SIO_USE_USART1) || defined(__DOXYGEN__) +#define AT32_SIO_USE_USART1 FALSE +#endif + +/** + * @brief SIO driver 2 enable switch. + * @details If set to @p TRUE the support for USART2 is included. + * @note The default is @p FALSE. + */ +#if !defined(AT32_SIO_USE_USART2) || defined(__DOXYGEN__) +#define AT32_SIO_USE_USART2 FALSE +#endif + +/** + * @brief SIO driver 3 enable switch. + * @details If set to @p TRUE the support for USART3 is included. + * @note The default is @p FALSE. + */ +#if !defined(AT32_SIO_USE_USART3) || defined(__DOXYGEN__) +#define AT32_SIO_USE_USART3 FALSE +#endif + +/** + * @brief SIO driver 4 enable switch. + * @details If set to @p TRUE the support for UART4 is included. + * @note The default is @p FALSE. + */ +#if !defined(AT32_SIO_USE_UART4) || defined(__DOXYGEN__) +#define AT32_SIO_USE_UART4 FALSE +#endif + +/** + * @brief SIO driver 5 enable switch. + * @details If set to @p TRUE the support for UART5 is included. + * @note The default is @p FALSE. + */ +#if !defined(AT32_SIO_USE_UART5) || defined(__DOXYGEN__) +#define AT32_SIO_USE_UART5 FALSE +#endif + +/** + * @brief SIO driver 6 enable switch. + * @details If set to @p TRUE the support for USART6 is included. + * @note The default is @p FALSE. + */ +#if !defined(AT32_SIO_USE_USART6) || defined(__DOXYGEN__) +#define AT32_SIO_USE_USART6 FALSE +#endif + +/** + * @brief SIO driver 7 enable switch. + * @details If set to @p TRUE the support for UART7 is included. + * @note The default is @p FALSE. + */ +#if !defined(AT32_SIO_USE_UART7) || defined(__DOXYGEN__) +#define AT32_SIO_USE_UART7 FALSE +#endif + +/** + * @brief SIO driver 8 enable switch. + * @details If set to @p TRUE the support for UART8 is included. + * @note The default is @p FALSE. + */ +#if !defined(AT32_SIO_USE_UART8) || defined(__DOXYGEN__) +#define AT32_SIO_USE_UART8 FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if AT32_SIO_USE_USART1 && !AT32_HAS_USART1 +#error "USART1 not present in the selected device" +#endif + +#if AT32_SIO_USE_USART2 && !AT32_HAS_USART2 +#error "USART2 not present in the selected device" +#endif + +#if AT32_SIO_USE_USART3 && !AT32_HAS_USART3 +#error "USART3 not present in the selected device" +#endif + +#if AT32_SIO_USE_UART4 && !AT32_HAS_UART4 +#error "UART4 not present in the selected device" +#endif + +#if AT32_SIO_USE_UART5 && !AT32_HAS_UART5 +#error "UART5 not present in the selected device" +#endif + +#if AT32_SIO_USE_USART6 && !AT32_HAS_USART6 +#error "USART6 not present in the selected device" +#endif + +#if AT32_SIO_USE_UART7 && !AT32_HAS_UART7 +#error "UART7 not present in the selected device" +#endif + +#if AT32_SIO_USE_UART8 && !AT32_HAS_UART8 +#error "UART8 not present in the selected device" +#endif + +#if !AT32_SIO_USE_USART1 && !AT32_SIO_USE_USART2 && \ + !AT32_SIO_USE_USART3 && !AT32_SIO_USE_UART4 && \ + !AT32_SIO_USE_UART5 && !AT32_SIO_USE_USART6 && \ + !AT32_SIO_USE_UART7 && !AT32_SIO_USE_UART8 +#error "SIO driver activated but no USART/UART peripheral assigned" +#endif + +/* Checks on allocation of USARTx units.*/ +#if AT32_SIO_USE_USART1 +#if defined(AT32_USART1_IS_USED) +#error "SIOD1 requires USART1 but it is already used" +#else +#define AT32_USART1_IS_USED +#endif +#endif + +#if AT32_SIO_USE_USART2 +#if defined(AT32_USART2_IS_USED) +#error "SIOD2 requires USART2 but it is already used" +#else +#define AT32_USART2_IS_USED +#endif +#endif + +#if AT32_SIO_USE_USART3 +#if defined(AT32_USART3_IS_USED) +#error "SIOD3 requires USART3 but it is already used" +#else +#define AT32_USART3_IS_USED +#endif +#endif + +#if AT32_SIO_USE_UART4 +#if defined(AT32_UART4_IS_USED) +#error "SIOD4 requires UART4 but it is already used" +#else +#define AT32_UART4_IS_USED +#endif +#endif + +#if AT32_SIO_USE_UART5 +#if defined(AT32_UART5_IS_USED) +#error "SIOD5 requires UART5 but it is already used" +#else +#define AT32_UART5_IS_USED +#endif +#endif + +#if AT32_SIO_USE_USART6 +#if defined(AT32_USART6_IS_USED) +#error "SIOD6 requires USART6 but it is already used" +#else +#define AT32_USART6_IS_USED +#endif +#endif + +#if AT32_SIO_USE_UART7 +#if defined(AT32_UART7_IS_USED) +#error "SIOD7 requires UART7 but it is already used" +#else +#define AT32_UART7_IS_USED +#endif +#endif + +#if AT32_SIO_USE_UART8 +#if defined(AT32_UART8_IS_USED) +#error "SIOD8 requires UART8 but it is already used" +#else +#define AT32_UART8_IS_USED +#endif +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Low level fields of the SIO driver structure. + */ +#define sio_lld_driver_fields \ + /* Pointer to the USARTx registers block.*/ \ + USART_TypeDef *usart; \ + /* Clock frequency for the associated USART/UART.*/ \ + uint32_t clock + +/** + * @brief Low level fields of the SIO configuration structure. + */ +#define sio_lld_config_fields \ + /* Desired baud rate.*/ \ + uint32_t baud; \ + /* USART CTRL1 register initialization data.*/ \ + uint32_t ctrl1; \ + /* USART CTRL2 register initialization data.*/ \ + uint32_t ctrl2; \ + /* USART CTRL3 register initialization data.*/ \ + uint32_t ctrl3 + +/** + * @brief Determines the state of the RX FIFO. + * + * @param[in] siop pointer to the @p SIODriver object + * @return The RX FIFO state. + * @retval false if RX FIFO is not empty + * @retval true if RX FIFO is empty + * + * @notapi + */ +#define sio_lld_is_rx_empty(siop) \ + (bool)(((siop)->usart->STS & USART_STS_RDBF) == 0U) + +/** + * @brief Determines the activity state of the receiver. + * + * @param[in] siop pointer to the @p SIODriver object + * @return The RX activity state. + * @retval false if RX is in active state. + * @retval true if RX is in idle state. + * + * @notapi + */ +#define sio_lld_is_rx_idle(siop) \ + (bool)(((siop)->usart->STS & USART_STS_IDLEF) != 0U) + +/** + * @brief Determines if RX has pending error events to be read and cleared. + * @note Only error and protocol errors are handled, data events are not + * considered. + * + * @param[in] siop pointer to the @p SIODriver object + * @return The RX error events. + * @retval false if RX has no pending events + * @retval true if RX has pending events + * + * @notapi + */ +#define sio_lld_has_rx_errors(siop) \ + (bool)(((siop)->usart->STS & SIO_LLD_ISR_RX_ERRORS) != 0U) + +/** + * @brief Determines the state of the TX FIFO. + * + * @param[in] siop pointer to the @p SIODriver object + * @return The TX FIFO state. + * @retval false if TX FIFO is not full + * @retval true if TX FIFO is full + * + * @notapi + */ +#define sio_lld_is_tx_full(siop) \ + (bool)(((siop)->usart->STS & USART_STS_TDBE) == 0U) + +/** + * @brief Determines the transmission state. + * + * @param[in] siop pointer to the @p SIODriver object + * @return The TX FIFO state. + * @retval false if transmission is idle + * @retval true if transmission is ongoing + * + * @notapi + */ +#define sio_lld_is_tx_ongoing(siop) \ + (bool)(((siop)->usart->STS & USART_STS_TDC) == 0U) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if (AT32_SIO_USE_USART1 == TRUE) && !defined(__DOXYGEN__) +extern SIODriver SIOD1; +#endif + +#if (AT32_SIO_USE_USART2 == TRUE) && !defined(__DOXYGEN__) +extern SIODriver SIOD2; +#endif + +#if (AT32_SIO_USE_USART3 == TRUE) && !defined(__DOXYGEN__) +extern SIODriver SIOD3; +#endif + +#if (AT32_SIO_USE_UART4 == TRUE) && !defined(__DOXYGEN__) +extern SIODriver SIOD4; +#endif + +#if (AT32_SIO_USE_UART5 == TRUE) && !defined(__DOXYGEN__) +extern SIODriver SIOD5; +#endif + +#if (AT32_SIO_USE_USART6 == TRUE) && !defined(__DOXYGEN__) +extern SIODriver SIOD6; +#endif + +#if (AT32_SIO_USE_UART7 == TRUE) && !defined(__DOXYGEN__) +extern SIODriver SIOD7; +#endif + +#if (AT32_SIO_USE_UART8 == TRUE) && !defined(__DOXYGEN__) +extern SIODriver SIOD8; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void sio_lld_init(void); + msg_t sio_lld_start(SIODriver *siop); + void sio_lld_stop(SIODriver *siop); + void sio_lld_update_enable_flags(SIODriver *siop); + sioevents_t sio_lld_get_and_clear_errors(SIODriver *siop); + sioevents_t sio_lld_get_and_clear_events(SIODriver *siop); + sioevents_t sio_lld_get_events(SIODriver *siop); + size_t sio_lld_read(SIODriver *siop, uint8_t *buffer, size_t n); + size_t sio_lld_write(SIODriver *siop, const uint8_t *buffer, size_t n); + msg_t sio_lld_get(SIODriver *siop); + void sio_lld_put(SIODriver *siop, uint_fast16_t data); + msg_t sio_lld_control(SIODriver *siop, unsigned int operation, void *arg); + void sio_lld_serve_interrupt(SIODriver *siop); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SIO == TRUE */ + +#endif /* HAL_SIO_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/AT32/LLD/USARTv2/hal_uart_lld.c b/os/hal/ports/AT32/LLD/USARTv2/hal_uart_lld.c index a8c507490c..d0a7c5995b 100644 --- a/os/hal/ports/AT32/LLD/USARTv2/hal_uart_lld.c +++ b/os/hal/ports/AT32/LLD/USARTv2/hal_uart_lld.c @@ -1,8 +1,8 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian - ChibiOS - Copyright (C) 2023..2024 Maxjta + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + ChibiOS - Copyright (C) 2024..2025 Maxjta Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -33,13 +33,13 @@ /* Driver local definitions. */ /*===========================================================================*/ -#define AT32_UART_CTRL2_CHECK_MASK \ - (USART_CTRL2_STOP_0 | USART_CTRL2_CLKEN | USART_CTRL2_CLKPOL | \ - USART_CTRL2_CLKPHA | USART_CTRL2_LBCP) - -#define AT32_UART_CTRL3_CHECK_MASK \ - (USART_CTRL3_CTSCFIEN | USART_CTRL3_CTSEN | USART_CTRL3_RTSEN | \ - USART_CTRL3_SCMEN | USART_CTRL3_SCNACKEN) +/* Workarounds for those devices where UARTs are USARTs.*/ +#if defined(USART4) +#define UART4 USART4 +#endif +#if defined(USART5) +#define UART5 USART5 +#endif /*===========================================================================*/ /* Driver exported variables. */ @@ -100,7 +100,7 @@ UARTDriver UARTD8; * * @return The error flags. */ -static uartflags_t translate_errors(uint16_t sts) { +static uartflags_t translate_errors(uint32_t sts) { uartflags_t status = 0; if (sts & USART_STS_ROERR) @@ -162,20 +162,20 @@ static void usart_stop(UARTDriver *uartp) { */ static void usart_start(UARTDriver *uartp) { uint32_t baudr; - uint16_t ctrl1; + uint32_t ctrl1; + const uint32_t tmo = uartp->config->timeout; USART_TypeDef *u = uartp->usart; /* Defensive programming, starting from a clean state.*/ usart_stop(uartp); /* Baud rate setting.*/ - baudr = (uint32_t)((uartp->clock + uartp->config->speed/2) / uartp->config->speed); + baudr = (uint32_t)((uartp->clock + uartp->config->speed / 2) / + uartp->config->speed); u->BAUDR = baudr; /* Resetting eventual pending status flags.*/ - (void)u->STS; /* STS reset step 1.*/ - (void)u->DT; /* STS reset step 2.*/ - u->STS = 0; + u->IFC = 0xFFFFFFFFU; /* Note that some bits are enforced because required for correct driver operations.*/ @@ -188,6 +188,13 @@ static void usart_start(UARTDriver *uartp) { ctrl1 = USART_CTRL1_UEN | USART_CTRL1_PERRIEN | USART_CTRL1_TEN | USART_CTRL1_REN; u->CTRL1 = uartp->config->ctrl1 | ctrl1; + /* Set receive timeout and checks if it is really applied.*/ + if (tmo > 0) { + osalDbgAssert(tmo <= USART_RTOV_RTOV, "Timeout overflow"); + u->RTOV = tmo; + osalDbgAssert(tmo == u->RTOV, "Timeout feature unsupported in this UART"); + } + /* Starting the receiver idle loop.*/ uart_enter_rx_idle_loop(uartp); } @@ -196,7 +203,7 @@ static void usart_start(UARTDriver *uartp) { * @brief RX DMA common service routine. * * @param[in] uartp pointer to the @p UARTDriver object - * @param[in] flags pre-shifted content of the ISR register + * @param[in] flags pre-shifted content of the STS register */ static void uart_lld_serve_rx_end_irq(UARTDriver *uartp, uint32_t flags) { @@ -226,7 +233,7 @@ static void uart_lld_serve_rx_end_irq(UARTDriver *uartp, uint32_t flags) { * @brief TX DMA common service routine. * * @param[in] uartp pointer to the @p UARTDriver object - * @param[in] flags pre-shifted content of the ISR register + * @param[in] flags pre-shifted content of the STS register */ static void uart_lld_serve_tx_end_irq(UARTDriver *uartp, uint32_t flags) { @@ -402,7 +409,7 @@ OSAL_IRQ_HANDLER(AT32_UART7_HANDLER) { #error "AT32_UART8_HANDLER not defined" #endif /** - * @brief UART5 IRQ handler. + * @brief UART8 IRQ handler. * * @isr */ @@ -415,7 +422,7 @@ OSAL_IRQ_HANDLER(AT32_UART8_HANDLER) { OSAL_IRQ_EPILOGUE(); } #endif -#endif /* AT32_UART_USE_UART5 */ +#endif /* AT32_UART_USE_UART8 */ /*===========================================================================*/ /* Driver exported functions. */ @@ -430,82 +437,106 @@ void uart_lld_init(void) { #if AT32_UART_USE_USART1 uartObjectInit(&UARTD1); - UARTD1.usart = USART1; - UARTD1.clock = AT32_PCLK2; + UARTD1.usart = USART1; + UARTD1.clock = AT32_PCLK2; UARTD1.dmarxmode = AT32_DMA_CCTRL_DTERRIEN; UARTD1.dmatxmode = AT32_DMA_CCTRL_DTERRIEN; - UARTD1.dmarx = NULL; - UARTD1.dmatx = NULL; + UARTD1.dmarx = NULL; + UARTD1.dmatx = NULL; +#if !defined(AT32_USART1_SUPPRESS_ISR) && defined(AT32_USART1_NUMBER) + nvicEnableVector(AT32_USART1_NUMBER, AT32_UART_USART1_IRQ_PRIORITY); +#endif #endif #if AT32_UART_USE_USART2 uartObjectInit(&UARTD2); - UARTD2.usart = USART2; - UARTD2.clock = AT32_PCLK1; + UARTD2.usart = USART2; + UARTD2.clock = AT32_PCLK1; UARTD2.dmarxmode = AT32_DMA_CCTRL_DTERRIEN; UARTD2.dmatxmode = AT32_DMA_CCTRL_DTERRIEN; - UARTD2.dmarx = NULL; - UARTD2.dmatx = NULL; + UARTD2.dmarx = NULL; + UARTD2.dmatx = NULL; +#if !defined(AT32_USART2_SUPPRESS_ISR) && defined(AT32_USART2_NUMBER) + nvicEnableVector(AT32_USART2_NUMBER, AT32_UART_USART2_IRQ_PRIORITY); +#endif #endif #if AT32_UART_USE_USART3 uartObjectInit(&UARTD3); - UARTD3.usart = USART3; - UARTD3.clock = AT32_PCLK1; + UARTD3.usart = USART3; + UARTD3.clock = AT32_PCLK1; UARTD3.dmarxmode = AT32_DMA_CCTRL_DTERRIEN; UARTD3.dmatxmode = AT32_DMA_CCTRL_DTERRIEN; - UARTD3.dmarx = NULL; - UARTD3.dmatx = NULL; + UARTD3.dmarx = NULL; + UARTD3.dmatx = NULL; +#if !defined(AT32_USART3_SUPPRESS_ISR) && defined(AT32_USART3_NUMBER) + nvicEnableVector(AT32_USART3_NUMBER, AT32_UART_USART3_IRQ_PRIORITY); +#endif #endif #if AT32_UART_USE_UART4 uartObjectInit(&UARTD4); - UARTD4.usart = UART4; - UARTD4.clock = AT32_PCLK1; + UARTD4.usart = UART4; + UARTD4.clock = AT32_PCLK1; UARTD4.dmarxmode = AT32_DMA_CCTRL_DTERRIEN; UARTD4.dmatxmode = AT32_DMA_CCTRL_DTERRIEN; - UARTD4.dmarx = NULL; - UARTD4.dmatx = NULL; + UARTD4.dmarx = NULL; + UARTD4.dmatx = NULL; +#if !defined(AT32_UART4_SUPPRESS_ISR) && defined(AT32_UART4_NUMBER) + nvicEnableVector(AT32_UART4_NUMBER, AT32_UART_UART4_IRQ_PRIORITY); +#endif #endif #if AT32_UART_USE_UART5 uartObjectInit(&UARTD5); - UARTD5.usart = UART5; - UARTD5.clock = AT32_PCLK1; + UARTD5.usart = UART5; + UARTD5.clock = AT32_PCLK1; UARTD5.dmarxmode = AT32_DMA_CCTRL_DTERRIEN; UARTD5.dmatxmode = AT32_DMA_CCTRL_DTERRIEN; - UARTD5.dmarx = NULL; - UARTD5.dmatx = NULL; + UARTD5.dmarx = NULL; + UARTD5.dmatx = NULL; +#if !defined(AT32_UART5_SUPPRESS_ISR) && defined(AT32_UART5_NUMBER) + nvicEnableVector(AT32_UART5_NUMBER, AT32_UART_UART5_IRQ_PRIORITY); +#endif #endif #if AT32_UART_USE_USART6 uartObjectInit(&UARTD6); - UARTD6.usart = USART6; - UARTD6.clock = AT32_PCLK2; + UARTD6.usart = USART6; + UARTD6.clock = AT32_PCLK2; UARTD6.dmarxmode = AT32_DMA_CCTRL_DTERRIEN; UARTD6.dmatxmode = AT32_DMA_CCTRL_DTERRIEN; - UARTD6.dmarx = NULL; - UARTD6.dmatx = NULL; + UARTD6.dmarx = NULL; + UARTD6.dmatx = NULL; +#if !defined(AT32_USART6_SUPPRESS_ISR) && defined(AT32_USART6_NUMBER) + nvicEnableVector(AT32_USART6_NUMBER, AT32_UART_USART6_IRQ_PRIORITY); +#endif #endif #if AT32_UART_USE_UART7 uartObjectInit(&UARTD7); - UARTD7.usart = UART7; - UARTD7.clock = AT32_PCLK1; + UARTD7.usart = UART7; + UARTD7.clock = AT32_PCLK1; UARTD7.dmarxmode = AT32_DMA_CCTRL_DTERRIEN; UARTD7.dmatxmode = AT32_DMA_CCTRL_DTERRIEN; - UARTD7.dmarx = NULL; - UARTD7.dmatx = NULL; + UARTD7.dmarx = NULL; + UARTD7.dmatx = NULL; +#if !defined(AT32_UART7_SUPPRESS_ISR) && defined(AT32_UART7_NUMBER) + nvicEnableVector(AT32_UART7_NUMBER, AT32_UART_UART7_IRQ_PRIORITY); +#endif #endif #if AT32_UART_USE_UART8 uartObjectInit(&UARTD8); - UARTD8.usart = UART8; - UARTD8.clock = AT32_PCLK1; + UARTD8.usart = UART8; + UARTD8.clock = AT32_PCLK1; UARTD8.dmarxmode = AT32_DMA_CCTRL_DTERRIEN; UARTD8.dmatxmode = AT32_DMA_CCTRL_DTERRIEN; - UARTD8.dmarx = NULL; - UARTD8.dmatx = NULL; + UARTD8.dmarx = NULL; + UARTD8.dmatx = NULL; +#if !defined(AT32_UART8_SUPPRESS_ISR) && defined(AT32_UART8_NUMBER) + nvicEnableVector(AT32_UART8_NUMBER, AT32_UART_UART8_IRQ_PRIORITY); +#endif #endif } @@ -519,8 +550,11 @@ void uart_lld_init(void) { void uart_lld_start(UARTDriver *uartp) { if (uartp->state == UART_STOP) { + + if (false) { + } #if AT32_UART_USE_USART1 - if (&UARTD1 == uartp) { + else if (&UARTD1 == uartp) { uartp->dmarx = dmaStreamAllocI(AT32_UART_USART1_RX_DMA_STREAM, AT32_UART_USART1_IRQ_PRIORITY, (at32_dmasts_t)uart_lld_serve_rx_end_irq, @@ -532,20 +566,18 @@ void uart_lld_start(UARTDriver *uartp) { (void *)uartp); osalDbgAssert(uartp->dmatx != NULL, "unable to allocate stream"); + crmEnableUSART1(true); + uartp->dmarxmode |= AT32_DMA_CCTRL_CHPL(AT32_UART_USART1_DMA_PRIORITY); + uartp->dmatxmode |= AT32_DMA_CCTRL_CHPL(AT32_UART_USART1_DMA_PRIORITY); #if AT32_DMA_SUPPORTS_DMAMUX dmaSetRequestSource(uartp->dmarx, AT32_DMAMUX_USART1_RX); dmaSetRequestSource(uartp->dmatx, AT32_DMAMUX_USART1_TX); #endif - - crmEnableUSART1(true); - nvicEnableVector(AT32_USART1_NUMBER, AT32_UART_USART1_IRQ_PRIORITY); - uartp->dmarxmode |= AT32_DMA_CCTRL_CHPL(AT32_UART_USART1_DMA_PRIORITY); - uartp->dmatxmode |= AT32_DMA_CCTRL_CHPL(AT32_UART_USART1_DMA_PRIORITY); } #endif #if AT32_UART_USE_USART2 - if (&UARTD2 == uartp) { + else if (&UARTD2 == uartp) { uartp->dmarx = dmaStreamAllocI(AT32_UART_USART2_RX_DMA_STREAM, AT32_UART_USART2_IRQ_PRIORITY, (at32_dmasts_t)uart_lld_serve_rx_end_irq, @@ -557,20 +589,18 @@ void uart_lld_start(UARTDriver *uartp) { (void *)uartp); osalDbgAssert(uartp->dmatx != NULL, "unable to allocate stream"); + crmEnableUSART2(true); + uartp->dmarxmode |= AT32_DMA_CCTRL_CHPL(AT32_UART_USART2_DMA_PRIORITY); + uartp->dmatxmode |= AT32_DMA_CCTRL_CHPL(AT32_UART_USART2_DMA_PRIORITY); #if AT32_DMA_SUPPORTS_DMAMUX dmaSetRequestSource(uartp->dmarx, AT32_DMAMUX_USART2_RX); dmaSetRequestSource(uartp->dmatx, AT32_DMAMUX_USART2_TX); #endif - - crmEnableUSART2(true); - nvicEnableVector(AT32_USART2_NUMBER, AT32_UART_USART2_IRQ_PRIORITY); - uartp->dmarxmode |= AT32_DMA_CCTRL_CHPL(AT32_UART_USART2_DMA_PRIORITY); - uartp->dmatxmode |= AT32_DMA_CCTRL_CHPL(AT32_UART_USART2_DMA_PRIORITY); } #endif #if AT32_UART_USE_USART3 - if (&UARTD3 == uartp) { + else if (&UARTD3 == uartp) { uartp->dmarx = dmaStreamAllocI(AT32_UART_USART3_RX_DMA_STREAM, AT32_UART_USART3_IRQ_PRIORITY, (at32_dmasts_t)uart_lld_serve_rx_end_irq, @@ -582,26 +612,18 @@ void uart_lld_start(UARTDriver *uartp) { (void *)uartp); osalDbgAssert(uartp->dmatx != NULL, "unable to allocate stream"); + crmEnableUSART3(true); + uartp->dmarxmode |= AT32_DMA_CCTRL_CHPL(AT32_UART_USART3_DMA_PRIORITY); + uartp->dmatxmode |= AT32_DMA_CCTRL_CHPL(AT32_UART_USART3_DMA_PRIORITY); #if AT32_DMA_SUPPORTS_DMAMUX dmaSetRequestSource(uartp->dmarx, AT32_DMAMUX_USART3_RX); dmaSetRequestSource(uartp->dmatx, AT32_DMAMUX_USART3_TX); #endif - - crmEnableUSART3(true); - nvicEnableVector(AT32_USART3_NUMBER, AT32_UART_USART3_IRQ_PRIORITY); - uartp->dmarxmode |= AT32_DMA_CCTRL_CHPL(AT32_UART_USART3_DMA_PRIORITY); - uartp->dmatxmode |= AT32_DMA_CCTRL_CHPL(AT32_UART_USART3_DMA_PRIORITY); } #endif #if AT32_UART_USE_UART4 - if (&UARTD4 == uartp) { - - osalDbgAssert((uartp->config->ctrl2 & AT32_UART_CTRL2_CHECK_MASK) == 0, - "specified invalid bits in UART4 CTRL2 register settings"); - osalDbgAssert((uartp->config->ctrl3 & AT32_UART_CTRL3_CHECK_MASK) == 0, - "specified invalid bits in UART4 CTRL3 register settings"); - + else if (&UARTD4 == uartp) { uartp->dmarx = dmaStreamAllocI(AT32_UART_UART4_RX_DMA_STREAM, AT32_UART_UART4_IRQ_PRIORITY, (at32_dmasts_t)uart_lld_serve_rx_end_irq, @@ -613,26 +635,18 @@ void uart_lld_start(UARTDriver *uartp) { (void *)uartp); osalDbgAssert(uartp->dmatx != NULL, "unable to allocate stream"); + crmEnableUART4(true); + uartp->dmarxmode |= AT32_DMA_CCTRL_CHPL(AT32_UART_UART4_DMA_PRIORITY); + uartp->dmatxmode |= AT32_DMA_CCTRL_CHPL(AT32_UART_UART4_DMA_PRIORITY); #if AT32_DMA_SUPPORTS_DMAMUX dmaSetRequestSource(uartp->dmarx, AT32_DMAMUX_UART4_RX); dmaSetRequestSource(uartp->dmatx, AT32_DMAMUX_UART4_TX); #endif - - crmEnableUART4(true); - nvicEnableVector(AT32_UART4_NUMBER, AT32_UART_UART4_IRQ_PRIORITY); - uartp->dmarxmode |= AT32_DMA_CCTRL_CHPL(AT32_UART_UART4_DMA_PRIORITY); - uartp->dmatxmode |= AT32_DMA_CCTRL_CHPL(AT32_UART_UART4_DMA_PRIORITY); } #endif #if AT32_UART_USE_UART5 - if (&UARTD5 == uartp) { - - osalDbgAssert((uartp->config->ctrl2 & AT32_UART_CTRL2_CHECK_MASK) == 0, - "specified invalid bits in UART5 CTRL2 register settings"); - osalDbgAssert((uartp->config->ctrl3 & AT32_UART_CTRL3_CHECK_MASK) == 0, - "specified invalid bits in UART5 CTRL3 register settings"); - + else if (&UARTD5 == uartp) { uartp->dmarx = dmaStreamAllocI(AT32_UART_UART5_RX_DMA_STREAM, AT32_UART_UART5_IRQ_PRIORITY, (at32_dmasts_t)uart_lld_serve_rx_end_irq, @@ -644,20 +658,18 @@ void uart_lld_start(UARTDriver *uartp) { (void *)uartp); osalDbgAssert(uartp->dmatx != NULL, "unable to allocate stream"); + crmEnableUART5(true); + uartp->dmarxmode |= AT32_DMA_CCTRL_CHPL(AT32_UART_UART5_DMA_PRIORITY); + uartp->dmatxmode |= AT32_DMA_CCTRL_CHPL(AT32_UART_UART5_DMA_PRIORITY); #if AT32_DMA_SUPPORTS_DMAMUX dmaSetRequestSource(uartp->dmarx, AT32_DMAMUX_UART5_RX); dmaSetRequestSource(uartp->dmatx, AT32_DMAMUX_UART5_TX); #endif - - crmEnableUART5(true); - nvicEnableVector(AT32_UART5_NUMBER, AT32_UART_UART5_IRQ_PRIORITY); - uartp->dmarxmode |= AT32_DMA_CCTRL_CHPL(AT32_UART_UART5_DMA_PRIORITY); - uartp->dmatxmode |= AT32_DMA_CCTRL_CHPL(AT32_UART_UART5_DMA_PRIORITY); } #endif #if AT32_UART_USE_USART6 - if (&UARTD6 == uartp) { + else if (&UARTD6 == uartp) { uartp->dmarx = dmaStreamAllocI(AT32_UART_USART6_RX_DMA_STREAM, AT32_UART_USART6_IRQ_PRIORITY, (at32_dmasts_t)uart_lld_serve_rx_end_irq, @@ -669,26 +681,18 @@ void uart_lld_start(UARTDriver *uartp) { (void *)uartp); osalDbgAssert(uartp->dmatx != NULL, "unable to allocate stream"); + crmEnableUSART6(true); + uartp->dmarxmode |= AT32_DMA_CCTRL_CHPL(AT32_UART_USART6_DMA_PRIORITY); + uartp->dmatxmode |= AT32_DMA_CCTRL_CHPL(AT32_UART_USART6_DMA_PRIORITY); #if AT32_DMA_SUPPORTS_DMAMUX dmaSetRequestSource(uartp->dmarx, AT32_DMAMUX_USART6_RX); dmaSetRequestSource(uartp->dmatx, AT32_DMAMUX_USART6_TX); #endif - - crmEnableUSART6(true); - nvicEnableVector(AT32_USART6_NUMBER, AT32_UART_USART6_IRQ_PRIORITY); - uartp->dmarxmode |= AT32_DMA_CCTRL_CHPL(AT32_UART_USART6_DMA_PRIORITY); - uartp->dmatxmode |= AT32_DMA_CCTRL_CHPL(AT32_UART_USART6_DMA_PRIORITY); } #endif #if AT32_UART_USE_UART7 - if (&UARTD7 == uartp) { - - osalDbgAssert((uartp->config->ctrl2 & AT32_UART_CTRL2_CHECK_MASK) == 0, - "specified invalid bits in UART7 CTRL2 register settings"); - osalDbgAssert((uartp->config->ctrl3 & AT32_UART_CTRL3_CHECK_MASK) == 0, - "specified invalid bits in UART7 CTRL3 register settings"); - + else if (&UARTD7 == uartp) { uartp->dmarx = dmaStreamAllocI(AT32_UART_UART7_RX_DMA_STREAM, AT32_UART_UART7_IRQ_PRIORITY, (at32_dmasts_t)uart_lld_serve_rx_end_irq, @@ -700,26 +704,18 @@ void uart_lld_start(UARTDriver *uartp) { (void *)uartp); osalDbgAssert(uartp->dmatx != NULL, "unable to allocate stream"); + crmEnableUART7(true); + uartp->dmarxmode |= AT32_DMA_CCTRL_CHPL(AT32_UART_UART7_DMA_PRIORITY); + uartp->dmatxmode |= AT32_DMA_CCTRL_CHPL(AT32_UART_UART7_DMA_PRIORITY); #if AT32_DMA_SUPPORTS_DMAMUX dmaSetRequestSource(uartp->dmarx, AT32_DMAMUX_UART7_RX); dmaSetRequestSource(uartp->dmatx, AT32_DMAMUX_UART7_TX); #endif - - crmEnableUART7(true); - nvicEnableVector(AT32_UART7_NUMBER, AT32_UART_UART7_IRQ_PRIORITY); - uartp->dmarxmode |= AT32_DMA_CCTRL_CHPL(AT32_UART_UART7_DMA_PRIORITY); - uartp->dmatxmode |= AT32_DMA_CCTRL_CHPL(AT32_UART_UART7_DMA_PRIORITY); } #endif #if AT32_UART_USE_UART8 - if (&UARTD8 == uartp) { - - osalDbgAssert((uartp->config->ctrl2 & AT32_UART_CTRL2_CHECK_MASK) == 0, - "specified invalid bits in UART8 CTRL2 register settings"); - osalDbgAssert((uartp->config->ctrl3 & AT32_UART_CTRL3_CHECK_MASK) == 0, - "specified invalid bits in UART8 CTRL3 register settings"); - + else if (&UARTD8 == uartp) { uartp->dmarx = dmaStreamAllocI(AT32_UART_UART8_RX_DMA_STREAM, AT32_UART_UART8_IRQ_PRIORITY, (at32_dmasts_t)uart_lld_serve_rx_end_irq, @@ -731,21 +727,22 @@ void uart_lld_start(UARTDriver *uartp) { (void *)uartp); osalDbgAssert(uartp->dmatx != NULL, "unable to allocate stream"); + crmEnableUART8(true); + uartp->dmarxmode |= AT32_DMA_CCTRL_CHPL(AT32_UART_UART8_DMA_PRIORITY); + uartp->dmatxmode |= AT32_DMA_CCTRL_CHPL(AT32_UART_UART8_DMA_PRIORITY); #if AT32_DMA_SUPPORTS_DMAMUX dmaSetRequestSource(uartp->dmarx, AT32_DMAMUX_UART8_RX); dmaSetRequestSource(uartp->dmatx, AT32_DMAMUX_UART8_TX); #endif - - crmEnableUART8(true); - nvicEnableVector(AT32_UART5_NUMBER, AT32_UART_UART8_IRQ_PRIORITY); - uartp->dmarxmode |= AT32_DMA_CCTRL_CHPL(AT32_UART_UART8_DMA_PRIORITY); - uartp->dmatxmode |= AT32_DMA_CCTRL_CHPL(AT32_UART_UART8_DMA_PRIORITY); } #endif + else { + osalDbgAssert(false, "invalid USART instance"); + } /* Static DMA setup, the transfer size depends on the USART settings, - it is 16 bits if M=1 and PEN=0 else it is 8 bits.*/ - if ((uartp->config->ctrl1 & (USART_CTRL1_DBN | USART_CTRL1_PEN)) == USART_CTRL1_DBN) { + it is 16 bits if DBN=1 and PEN=0 else it is 8 bits.*/ + if ((uartp->config->ctrl1 & (USART_CTRL1_DBN0 | USART_CTRL1_PEN)) == USART_CTRL1_DBN0) { uartp->dmarxmode |= AT32_DMA_CCTRL_PWIDTH_HWORD | AT32_DMA_CCTRL_MWIDTH_HWORD; uartp->dmatxmode |= AT32_DMA_CCTRL_PWIDTH_HWORD | AT32_DMA_CCTRL_MWIDTH_HWORD; } @@ -777,7 +774,6 @@ void uart_lld_stop(UARTDriver *uartp) { #if AT32_UART_USE_USART1 if (&UARTD1 == uartp) { - nvicDisableVector(AT32_USART1_NUMBER); crmDisableUSART1(); return; } @@ -785,7 +781,6 @@ void uart_lld_stop(UARTDriver *uartp) { #if AT32_UART_USE_USART2 if (&UARTD2 == uartp) { - nvicDisableVector(AT32_USART2_NUMBER); crmDisableUSART2(); return; } @@ -793,7 +788,6 @@ void uart_lld_stop(UARTDriver *uartp) { #if AT32_UART_USE_USART3 if (&UARTD3 == uartp) { - nvicDisableVector(AT32_USART3_NUMBER); crmDisableUSART3(); return; } @@ -801,7 +795,6 @@ void uart_lld_stop(UARTDriver *uartp) { #if AT32_UART_USE_UART4 if (&UARTD4 == uartp) { - nvicDisableVector(AT32_UART4_NUMBER); crmDisableUART4(); return; } @@ -809,7 +802,6 @@ void uart_lld_stop(UARTDriver *uartp) { #if AT32_UART_USE_UART5 if (&UARTD5 == uartp) { - nvicDisableVector(AT32_UART5_NUMBER); crmDisableUART5(); return; } @@ -817,7 +809,6 @@ void uart_lld_stop(UARTDriver *uartp) { #if AT32_UART_USE_USART6 if (&UARTD6 == uartp) { - nvicDisableVector(AT32_USART6_NUMBER); crmDisableUSART6(); return; } @@ -825,7 +816,6 @@ void uart_lld_stop(UARTDriver *uartp) { #if AT32_UART_USE_UART7 if (&UARTD7 == uartp) { - nvicDisableVector(AT32_UART7_NUMBER); crmDisableUART7(); return; } @@ -833,12 +823,10 @@ void uart_lld_stop(UARTDriver *uartp) { #if AT32_UART_USE_UART8 if (&UARTD8 == uartp) { - nvicDisableVector(AT32_UART8_NUMBER); crmDisableUART8(); return; } #endif - } } @@ -869,7 +857,6 @@ void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf) { #else if (uartp->config->txend2_cb != NULL) { #endif - uartp->usart->STS = ~USART_STS_TDC; uartp->usart->CTRL1 |= USART_CTRL1_TDCIEN; } @@ -948,24 +935,21 @@ size_t uart_lld_stop_receive(UARTDriver *uartp) { * @param[in] uartp pointer to the @p UARTDriver object */ void uart_lld_serve_interrupt(UARTDriver *uartp) { - uint16_t sts; + uint32_t sts; USART_TypeDef *u = uartp->usart; uint32_t ctrl1 = u->CTRL1; - sts = u->STS; /* STS reset step 1.*/ + /* Reading and clearing status.*/ + sts = u->STS; + u->IFC = sts; if (sts & (USART_STS_BFF | USART_STS_ROERR | USART_STS_NERR | USART_STS_FERR | USART_STS_PERR)) { - - (void)u->DT; /* STS reset step 2 - clear ROERR.*/ - - u->STS = ~USART_STS_BFF; _uart_rx_error_isr_code(uartp, translate_errors(sts)); } if ((sts & USART_STS_TDC) && (ctrl1 & USART_CTRL1_TDCIEN)) { - /* TDC interrupt cleared and disabled.*/ - u->STS = ~USART_STS_TDC; + /* TDC interrupt disabled.*/ u->CTRL1 = ctrl1 & ~USART_CTRL1_TDCIEN; /* End of transmission, a callback is generated.*/ @@ -973,7 +957,8 @@ void uart_lld_serve_interrupt(UARTDriver *uartp) { } /* Timeout interrupt sources are only checked if enabled in CTRL1.*/ - if ((ctrl1 & USART_CTRL1_IDLEIEN) && (sts & USART_STS_IDLEF)) { + if (((ctrl1 & USART_CTRL1_IDLEIEN) && (sts & USART_STS_IDLEF)) || + ((ctrl1 & USART_CTRL1_RETODIE) && (sts & USART_STS_RTODF))) { _uart_timeout_isr_code(uartp); } } diff --git a/os/hal/ports/AT32/LLD/USARTv2/hal_uart_lld.h b/os/hal/ports/AT32/LLD/USARTv2/hal_uart_lld.h index 4c808717cd..4608c29c4b 100644 --- a/os/hal/ports/AT32/LLD/USARTv2/hal_uart_lld.h +++ b/os/hal/ports/AT32/LLD/USARTv2/hal_uart_lld.h @@ -1,8 +1,8 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian - ChibiOS - Copyright (C) 2023..2024 Maxjta + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + ChibiOS - Copyright (C) 2024..2025 Maxjta Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -93,7 +93,7 @@ * @note The default is @p FALSE. */ #if !defined(AT32_UART_USE_USART6) || defined(__DOXYGEN__) -#define AT32_UART_USE_USART6 FALSE +#define AT32_UART_USE_USART6 FALSE #endif /** @@ -251,7 +251,7 @@ #endif /** - * @brief USART DMA error hook. + * @brief UART DMA error hook. * @note The default action for DMA errors is a system halt because DMA * error can only happen because programming errors. */ @@ -297,52 +297,61 @@ #endif #if !AT32_UART_USE_USART1 && !AT32_UART_USE_USART2 && \ - !AT32_UART_USE_USART3 && !AT32_UART_USE_UART4 && \ - !AT32_UART_USE_UART5 && !AT32_UART_USE_USART6 && \ - !AT32_UART_USE_UART7 && !AT32_UART_USE_UART8 + !AT32_UART_USE_USART3 && !AT32_UART_USE_UART4 && \ + !AT32_UART_USE_UART5 && !AT32_UART_USE_USART6 && \ + !AT32_UART_USE_UART7 && !AT32_UART_USE_UART8 #error "UART driver activated but no USART/UART peripheral assigned" #endif -#if AT32_UART_USE_USART1 && \ +#if !defined(AT32_USART1_SUPPRESS_ISR) && \ + AT32_UART_USE_USART1 && \ !OSAL_IRQ_IS_VALID_PRIORITY(AT32_UART_USART1_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to USART1" #endif -#if AT32_UART_USE_USART2 && \ +#if !defined(AT32_USART2_SUPPRESS_ISR) && \ + AT32_UART_USE_USART2 && \ !OSAL_IRQ_IS_VALID_PRIORITY(AT32_UART_USART2_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to USART2" #endif -#if AT32_UART_USE_USART3 && \ +#if !defined(AT32_USART3_SUPPRESS_ISR) && \ + AT32_UART_USE_USART3 && \ !OSAL_IRQ_IS_VALID_PRIORITY(AT32_UART_USART3_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to USART3" #endif -#if AT32_UART_USE_UART4 && \ +#if !defined(AT32_UART4_SUPPRESS_ISR) && \ + AT32_UART_USE_UART4 && \ !OSAL_IRQ_IS_VALID_PRIORITY(AT32_UART_UART4_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to UART4" #endif -#if AT32_UART_USE_UART5 && \ +#if !defined(AT32_UART5_SUPPRESS_ISR) && \ + AT32_UART_USE_UART5 && \ !OSAL_IRQ_IS_VALID_PRIORITY(AT32_UART_UART5_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to UART5" #endif -#if AT32_UART_USE_USART6 && \ +#if !defined(AT32_USART6_SUPPRESS_ISR) && \ + AT32_UART_USE_USART6 && \ !OSAL_IRQ_IS_VALID_PRIORITY(AT32_UART_USART6_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to USART6" #endif -#if AT32_UART_USE_UART7 && \ +#if !defined(AT32_UART7_SUPPRESS_ISR) && \ + AT32_UART_USE_UART7 && \ !OSAL_IRQ_IS_VALID_PRIORITY(AT32_UART_UART7_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to UART7" #endif -#if AT32_UART_USE_UART8 && \ +#if !defined(AT32_UART8_SUPPRESS_ISR) && \ + AT32_UART_USE_UART8 && \ !OSAL_IRQ_IS_VALID_PRIORITY(AT32_UART_UART8_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to UART8" #endif +/* Check on DMA priorities.*/ #if AT32_UART_USE_USART1 && \ !AT32_DMA_IS_VALID_PRIORITY(AT32_UART_USART1_DMA_PRIORITY) #error "Invalid DMA priority assigned to USART1" @@ -383,6 +392,128 @@ #error "Invalid DMA priority assigned to UART8" #endif +/* Check on the presence of the DMA streams settings.*/ +#if AT32_UART_USE_USART1 && (!defined(AT32_UART_USART1_RX_DMA_STREAM) || \ + !defined(AT32_UART_USART1_TX_DMA_STREAM)) +#error "USART1 DMA streams not defined" +#endif + +#if AT32_UART_USE_USART2 && (!defined(AT32_UART_USART2_RX_DMA_STREAM) || \ + !defined(AT32_UART_USART2_TX_DMA_STREAM)) +#error "USART2 DMA streams not defined" +#endif + +#if AT32_UART_USE_USART3 && (!defined(AT32_UART_USART3_RX_DMA_STREAM) || \ + !defined(AT32_UART_USART3_TX_DMA_STREAM)) +#error "USART3 DMA streams not defined" +#endif + +#if AT32_UART_USE_UART4 && (!defined(AT32_UART_UART4_RX_DMA_STREAM) || \ + !defined(AT32_UART_UART4_TX_DMA_STREAM)) +#error "UART4 DMA streams not defined" +#endif + +#if AT32_UART_USE_UART5 && (!defined(AT32_UART_UART5_RX_DMA_STREAM) || \ + !defined(AT32_UART_UART5_TX_DMA_STREAM)) +#error "UART5 DMA streams not defined" +#endif + +#if AT32_UART_USE_USART6 && (!defined(AT32_UART_USART6_RX_DMA_STREAM) || \ + !defined(AT32_UART_USART6_TX_DMA_STREAM)) +#error "USART6 DMA streams not defined" +#endif + +#if AT32_UART_USE_UART7 && (!defined(AT32_UART_UART7_RX_DMA_STREAM) || \ + !defined(AT32_UART_UART7_TX_DMA_STREAM)) +#error "UART7 DMA streams not defined" +#endif + +#if AT32_UART_USE_UART8 && (!defined(AT32_UART_UART8_RX_DMA_STREAM) || \ + !defined(AT32_UART_UART8_TX_DMA_STREAM)) +#error "UART8 DMA streams not defined" +#endif + +/* Check on the validity of the assigned DMA channels.*/ +#if AT32_UART_USE_USART1 && \ + !AT32_DMA_IS_VALID_STREAM(AT32_UART_USART1_RX_DMA_STREAM) +#error "Invalid DMA channel assigned to USART1 RX" +#endif + +#if AT32_UART_USE_USART1 && \ + !AT32_DMA_IS_VALID_STREAM(AT32_UART_USART1_TX_DMA_STREAM) +#error "Invalid DMA channel assigned to USART1 TX" +#endif + +#if AT32_UART_USE_USART2 && \ + !AT32_DMA_IS_VALID_STREAM(AT32_UART_USART2_RX_DMA_STREAM) +#error "Invalid DMA channel assigned to USART2 RX" +#endif + +#if AT32_UART_USE_USART2 && \ + !AT32_DMA_IS_VALID_STREAM(AT32_UART_USART2_TX_DMA_STREAM) +#error "Invalid DMA channel assigned to USART2 TX" +#endif + +#if AT32_UART_USE_USART3 && \ + !AT32_DMA_IS_VALID_STREAM(AT32_UART_USART3_RX_DMA_STREAM) +#error "Invalid DMA channel assigned to USART3 RX" +#endif + +#if AT32_UART_USE_USART3 && \ + !AT32_DMA_IS_VALID_STREAM(AT32_UART_USART3_TX_DMA_STREAM) +#error "Invalid DMA channel assigned to USART3 TX" +#endif + +#if AT32_UART_USE_UART4 && \ + !AT32_DMA_IS_VALID_STREAM(AT32_UART_UART4_RX_DMA_STREAM) +#error "Invalid DMA channel assigned to UART4 RX" +#endif + +#if AT32_UART_USE_UART4 && \ + !AT32_DMA_IS_VALID_STREAM(AT32_UART_UART4_TX_DMA_STREAM) +#error "Invalid DMA channel assigned to UART4 TX" +#endif + +#if AT32_UART_USE_UART5 && \ + !AT32_DMA_IS_VALID_STREAM(AT32_UART_UART5_RX_DMA_STREAM) +#error "Invalid DMA channel assigned to UART5 RX" +#endif + +#if AT32_UART_USE_UART5 && \ + !AT32_DMA_IS_VALID_STREAM(AT32_UART_UART5_TX_DMA_STREAM) +#error "Invalid DMA channel assigned to UART5 TX" +#endif + +#if AT32_UART_USE_USART6 && \ + !AT32_DMA_IS_VALID_STREAM(AT32_UART_USART6_RX_DMA_STREAM) +#error "Invalid DMA channel assigned to USART6 RX" +#endif + +#if AT32_UART_USE_USART6 && \ + !AT32_DMA_IS_VALID_STREAM(AT32_UART_USART6_TX_DMA_STREAM) +#error "Invalid DMA channel assigned to USART6 TX" +#endif + +#if AT32_UART_USE_UART7 && \ + !AT32_DMA_IS_VALID_STREAM(AT32_UART_UART7_RX_DMA_STREAM) +#error "Invalid DMA channel assigned to UART7 RX" +#endif + +#if AT32_UART_USE_UART7 && \ + !AT32_DMA_IS_VALID_STREAM(AT32_UART_UART7_TX_DMA_STREAM) +#error "Invalid DMA channel assigned to UART7 TX" +#endif + +#if AT32_UART_USE_UART8 && \ + !AT32_DMA_IS_VALID_STREAM(AT32_UART_UART8_RX_DMA_STREAM) +#error "Invalid DMA channel assigned to UART8 RX" +#endif + +#if AT32_UART_USE_UART8 && \ + !AT32_DMA_IS_VALID_STREAM(AT32_UART_UART8_TX_DMA_STREAM) +#error "Invalid DMA channel assigned to UART8 TX" +#endif + #if !defined(AT32_DMA_REQUIRED) #define AT32_DMA_REQUIRED #endif @@ -517,10 +648,16 @@ typedef struct hal_uart_config { /* End of the mandatory fields.*/ /** * @brief Receiver timeout callback. - * @details Handles idle interrupts depending on configured - * flags in CR registers and supported hardware features. + * @details Handles both idle and timeout interrupts depending on configured + * flags in CTRL registers and supported hardware features. */ uartcb_t timeout_cb; + /** + * @brief Receiver timeout value in terms of number of bit duration. + * @details Set it to 0 when you want to handle idle interrupt instead of + * hardware timeout. + */ + uint32_t timeout; /** * @brief Bit rate. */ @@ -528,15 +665,15 @@ typedef struct hal_uart_config { /** * @brief Initialization value for the CTRL1 register. */ - uint16_t ctrl1; + uint32_t ctrl1; /** * @brief Initialization value for the CTRL2 register. */ - uint16_t ctrl2; + uint32_t ctrl2; /** * @brief Initialization value for the CTRL3 register. */ - uint16_t ctrl3; + uint32_t ctrl3; } UARTConfig; /** diff --git a/os/hal/ports/AT32/LLD/xWDGv1/hal_wdg_lld.c b/os/hal/ports/AT32/LLD/xWDGv1/hal_wdg_lld.c index acde648698..eef84a0a0e 100644 --- a/os/hal/ports/AT32/LLD/xWDGv1/hal_wdg_lld.c +++ b/os/hal/ports/AT32/LLD/xWDGv1/hal_wdg_lld.c @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/ports/AT32/LLD/xWDGv1/hal_wdg_lld.h b/os/hal/ports/AT32/LLD/xWDGv1/hal_wdg_lld.h index f2e47c9963..554f200c7f 100644 --- a/os/hal/ports/AT32/LLD/xWDGv1/hal_wdg_lld.h +++ b/os/hal/ports/AT32/LLD/xWDGv1/hal_wdg_lld.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/testhal/AT32/multi/ERTC/Makefile b/testhal/AT32/multi/ERTC/Makefile index c8606df05e..fdf3019a85 100644 --- a/testhal/AT32/multi/ERTC/Makefile +++ b/testhal/AT32/multi/ERTC/Makefile @@ -3,6 +3,14 @@ # all: + @echo + @echo === Building for AT-START-F402 ===================================== + +@make --no-print-directory -f ./make/at-start-f402.make all + @echo ==================================================================== + @echo + @echo === Building for AT-START-F405 ===================================== + +@make --no-print-directory -f ./make/at-start-f405.make all + @echo ==================================================================== @echo @echo === Building for AT-START-F415 ===================================== +@make --no-print-directory -f ./make/at-start-f415.make all @@ -10,6 +18,10 @@ all: @echo clean: + @echo + +@make --no-print-directory -f ./make/at-start-f402.make clean + @echo + +@make --no-print-directory -f ./make/at-start-f405.make clean @echo +@make --no-print-directory -f ./make/at-start-f415.make clean @echo diff --git a/testhal/AT32/multi/ERTC/cfg/at-start-f402/chconf.h b/testhal/AT32/multi/ERTC/cfg/at-start-f402/chconf.h new file mode 100644 index 0000000000..56fe06776a --- /dev/null +++ b/testhal/AT32/multi/ERTC/cfg/at-start-f402/chconf.h @@ -0,0 +1,842 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_7_0_ + +/*===========================================================================*/ +/** + * @name System settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Handling of instances. + * @note If enabled then threads assigned to various instances can + * interact each other using the same synchronization objects. + * If disabled then each OS instance is a separate world, no + * direct interactions are handled by the OS. + */ +#if !defined(CH_CFG_SMP_MODE) +#define CH_CFG_SMP_MODE FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_ST_RESOLUTION) +#define CH_CFG_ST_RESOLUTION 32 +#endif + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_CFG_ST_FREQUENCY) +#define CH_CFG_ST_FREQUENCY 10000 +#endif + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_INTERVALS_SIZE) +#define CH_CFG_INTERVALS_SIZE 32 +#endif + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_TIME_TYPES_SIZE) +#define CH_CFG_TIME_TYPES_SIZE 32 +#endif + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#if !defined(CH_CFG_ST_TIMEDELTA) +#define CH_CFG_ST_TIMEDELTA 2 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#if !defined(CH_CFG_TIME_QUANTUM) +#define CH_CFG_TIME_QUANTUM 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#if !defined(CH_CFG_NO_IDLE_THREAD) +#define CH_CFG_NO_IDLE_THREAD FALSE +#endif + +/** + * @brief Kernel hardening level. + * @details This option is the level of functional-safety checks enabled + * in the kerkel. The meaning is: + * - 0: No checks, maximum performance. + * - 1: Reasonable checks. + * - 2: All checks. + * . + */ +#if !defined(CH_CFG_HARDENING_LEVEL) +#define CH_CFG_HARDENING_LEVEL 0 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_OPTIMIZE_SPEED) +#define CH_CFG_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TM) +#define CH_CFG_USE_TM TRUE +#endif + +/** + * @brief Time Stamps APIs. + * @details If enabled then the time stamps APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TIMESTAMP) +#define CH_CFG_USE_TIMESTAMP TRUE +#endif + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_REGISTRY) +#define CH_CFG_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_WAITEXIT) +#define CH_CFG_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_SEMAPHORES) +#define CH_CFG_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MUTEXES) +#define CH_CFG_USE_MUTEXES TRUE +#endif + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_CONDVARS) +#define CH_CFG_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_EVENTS) +#define CH_CFG_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MESSAGES) +#define CH_CFG_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#if !defined(CH_CFG_USE_DYNAMIC) +#define CH_CFG_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name OSLIB options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_MAILBOXES) +#define CH_CFG_USE_MAILBOXES TRUE +#endif + +/** + * @brief Memory checks APIs. + * @details If enabled then the memory checks APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCHECKS) +#define CH_CFG_USE_MEMCHECKS TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCORE) +#define CH_CFG_USE_MEMCORE TRUE +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#if !defined(CH_CFG_MEMCORE_SIZE) +#define CH_CFG_MEMCORE_SIZE 0 +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_CFG_USE_HEAP) +#define CH_CFG_USE_HEAP TRUE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMPOOLS) +#define CH_CFG_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_FIFOS) +#define CH_CFG_USE_OBJ_FIFOS TRUE +#endif + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Objects Caches APIs. + * @details If enabled then the objects caches APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_CACHES) +#define CH_CFG_USE_OBJ_CACHES TRUE +#endif + +/** + * @brief Delegate threads APIs. + * @details If enabled then the delegate threads APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_DELEGATES) +#define CH_CFG_USE_DELEGATES TRUE +#endif + +/** + * @brief Jobs Queues APIs. + * @details If enabled then the jobs queues APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_JOBS) +#define CH_CFG_USE_JOBS TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_CFG_USE_FACTORY) +#define CH_CFG_USE_FACTORY TRUE +#endif + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 +#endif + +/** + * @brief Enables the registry of generic objects. + */ +#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE +#endif + +/** + * @brief Enables factory for generic buffers. + */ +#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE +#endif + +/** + * @brief Enables factory for semaphores. + */ +#if !defined(CH_CFG_FACTORY_SEMAPHORES) +#define CH_CFG_FACTORY_SEMAPHORES TRUE +#endif + +/** + * @brief Enables factory for mailboxes. + */ +#if !defined(CH_CFG_FACTORY_MAILBOXES) +#define CH_CFG_FACTORY_MAILBOXES TRUE +#endif + +/** + * @brief Enables factory for objects FIFOs. + */ +#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE +#endif + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_STATISTICS) +#define CH_DBG_STATISTICS FALSE +#endif + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_MASK) +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_ALL +#endif + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_BUFFER_SIZE) +#define CH_DBG_TRACE_BUFFER_SIZE 128 +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#if !defined(CH_DBG_THREADS_PROFILING) +#define CH_DBG_THREADS_PROFILING FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add system custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add system initialization code here.*/ \ +} + +/** + * @brief OS instance structure extension. + * @details User fields added to the end of the @p os_instance_t structure. + */ +#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS \ + /* Add OS instance custom fields here.*/ + +/** + * @brief OS instance initialization hook. + * + * @param[in] oip pointer to the @p os_instance_t structure + */ +#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) { \ + /* Add OS instance initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + * + * @param[in] ntp thread being switched in + * @param[in] otp thread being switched out + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** + * @brief Runtime Faults Collection Unit hook. + * @details This hook is invoked each time new faults are collected and stored. + */ +#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) { \ + /* Faults handling code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/testhal/AT32/multi/ERTC/cfg/at-start-f402/config.h b/testhal/AT32/multi/ERTC/cfg/at-start-f402/config.h new file mode 100644 index 0000000000..1e7c044f47 --- /dev/null +++ b/testhal/AT32/multi/ERTC/cfg/at-start-f402/config.h @@ -0,0 +1,39 @@ +/* + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * CRC driver system settings. + */ +#define AT32_CRC_USE_CRC1 FALSE + +#define CRC_USE_DMA FALSE +#define AT32_CRC_CRC1_DMA_PRIORITY 2 +#define AT32_CRC_CRC1_IRQ_PRIORITY 5 +#define AT32_CRC_CRC1_DMA_STREAM AT32_DMA_STREAM_ID_ANY + +/* + * I2C fallback driver system settings. + */ +#define SW_I2C_USE_I2C1 FALSE +#define SW_I2C_USE_I2C2 FALSE +#define SW_I2C_USE_I2C3 FALSE +#define SW_I2C_USE_I2C4 FALSE + +/* + * Other settings. + */ +#define BOARD_OTG_VBUSIG diff --git a/testhal/AT32/multi/ERTC/cfg/at-start-f402/halconf.h b/testhal/AT32/multi/ERTC/cfg/at-start-f402/halconf.h new file mode 100644 index 0000000000..1056b191e3 --- /dev/null +++ b/testhal/AT32/multi/ERTC/cfg/at-start-f402/halconf.h @@ -0,0 +1,557 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_8_4_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the EFlash subsystem. + */ +#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__) +#define HAL_USE_EFL FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC TRUE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/** + * @brief Enables the WSPI subsystem. + */ +#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) +#define HAL_USE_WSPI FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS FALSE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS FALSE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Timeout before assuming a failure while waiting for card idle. + * @note Time is in milliseconds. + */ +#if !defined(MMC_IDLE_TIMEOUT_MS) || defined(__DOXYGEN__) +#define MMC_IDLE_TIMEOUT_MS 1000 +#endif + +/** + * @brief Mutual exclusion on the SPI bus. + */ +#if !defined(MMC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define MMC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SIO driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SIO_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SIO_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Support for thread synchronization API. + */ +#if !defined(SIO_USE_SYNCHRONIZATION) || defined(__DOXYGEN__) +#define SIO_USE_SYNCHRONIZATION TRUE +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 256 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 2 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Inserts an assertion on function errors before returning. + */ +#if !defined(SPI_USE_ASSERT_ON_ERROR) || defined(__DOXYGEN__) +#define SPI_USE_ASSERT_ON_ERROR TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#include "halconf_community.h" + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/testhal/AT32/multi/ERTC/cfg/at-start-f402/halconf_community.h b/testhal/AT32/multi/ERTC/cfg/at-start-f402/halconf_community.h new file mode 100644 index 0000000000..5a77290c71 --- /dev/null +++ b/testhal/AT32/multi/ERTC/cfg/at-start-f402/halconf_community.h @@ -0,0 +1,182 @@ +/* + ChibiOS - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef HALCONF_COMMUNITY_H +#define HALCONF_COMMUNITY_H + +/** + * @brief Enables the community overlay. + */ +#if !defined(HAL_USE_COMMUNITY) || defined(__DOXYGEN__) +#define HAL_USE_COMMUNITY TRUE +#endif + +/** + * @brief Enables the FSMC subsystem. + */ +#if !defined(HAL_USE_FSMC) || defined(__DOXYGEN__) +#define HAL_USE_FSMC FALSE +#endif + +/** + * @brief Enables the NAND subsystem. + */ +#if !defined(HAL_USE_NAND) || defined(__DOXYGEN__) +#define HAL_USE_NAND FALSE +#endif + +/** + * @brief Enables the 1-wire subsystem. + */ +#if !defined(HAL_USE_ONEWIRE) || defined(__DOXYGEN__) +#define HAL_USE_ONEWIRE FALSE +#endif + +/** + * @brief Enables the EICU subsystem. + */ +#if !defined(HAL_USE_EICU) || defined(__DOXYGEN__) +#define HAL_USE_EICU FALSE +#endif + +/** + * @brief Enables the CRC subsystem. + */ +#if !defined(HAL_USE_CRC) || defined(__DOXYGEN__) +#define HAL_USE_CRC FALSE +#endif + +/** + * @brief Enables the RNG subsystem. + */ +#if !defined(HAL_USE_RNG) || defined(__DOXYGEN__) +#define HAL_USE_RNG FALSE +#endif + +/** + * @brief Enables the EEPROM subsystem. + */ +#if !defined(HAL_USE_EEPROM) || defined(__DOXYGEN__) +#define HAL_USE_EEPROM FALSE +#endif + +/** + * @brief Enables the TIMCAP subsystem. + */ +#if !defined(HAL_USE_TIMCAP) || defined(__DOXYGEN__) +#define HAL_USE_TIMCAP FALSE +#endif + +/** + * @brief Enables the COMP subsystem. + */ +#if !defined(HAL_USE_COMP) || defined(__DOXYGEN__) +#define HAL_USE_COMP FALSE +#endif + +/** + * @brief Enables the OPAMP subsystem. + */ +#if !defined(HAL_USE_OPAMP) || defined(__DOXYGEN__) +#define HAL_USE_OPAMP FALSE +#endif + +/** + * @brief Enables the QEI subsystem. + */ +#if !defined(HAL_USE_QEI) || defined(__DOXYGEN__) +#define HAL_USE_QEI FALSE +#endif + +/** + * @brief Enables the USBH subsystem. + */ +#if !defined(HAL_USE_USBH) || defined(__DOXYGEN__) +#define HAL_USE_USBH FALSE +#endif + +/** + * @brief Enables the USB_MSD subsystem. + */ +#if !defined(HAL_USE_USB_MSD) || defined(__DOXYGEN__) +#define HAL_USE_USB_MSD FALSE +#endif + +/*===========================================================================*/ +/* FSMCNAND driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the @p nandAcquireBus() and @p nanReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(NAND_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define NAND_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* 1-wire driver related settings. */ +/*===========================================================================*/ +/** + * @brief Enables strong pull up feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_STRONG_PULLUP FALSE + +/** + * @brief Enables search ROM feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_SEARCH_ROM TRUE + +/*===========================================================================*/ +/* QEI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables discard of overlow + */ +#if !defined(QEI_USE_OVERFLOW_DISCARD) || defined(__DOXYGEN__) +#define QEI_USE_OVERFLOW_DISCARD FALSE +#endif + +/** + * @brief Enables min max of overlow + */ +#if !defined(QEI_USE_OVERFLOW_MINMAX) || defined(__DOXYGEN__) +#define QEI_USE_OVERFLOW_MINMAX FALSE +#endif + +/*===========================================================================*/ +/* EEProm driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables 24xx series I2C eeprom device driver. + * @note Disabling this option saves both code and data space. + */ +#define EEPROM_USE_EE24XX FALSE + /** + * @brief Enables 25xx series SPI eeprom device driver. + * @note Disabling this option saves both code and data space. + */ +#define EEPROM_USE_EE25XX FALSE + +#endif /* HALCONF_COMMUNITY_H */ + +/** @} */ diff --git a/testhal/AT32/multi/ERTC/cfg/at-start-f402/mcuconf.h b/testhal/AT32/multi/ERTC/cfg/at-start-f402/mcuconf.h new file mode 100644 index 0000000000..af05f71aa5 --- /dev/null +++ b/testhal/AT32/multi/ERTC/cfg/at-start-f402/mcuconf.h @@ -0,0 +1,268 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef MCUCONF_H +#define MCUCONF_H + +/* + * AT32F402 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define AT32F402_MCUCONF + +/* + * General settings. + */ +#define AT32_NO_INIT FALSE + +/* + * HAL driver system settings. + */ +#define AT32_HICK_ENABLED TRUE +#define AT32_LICK_ENABLED TRUE +#define AT32_HEXT_ENABLED TRUE +#define AT32_LEXT_ENABLED FALSE +#define AT32_PLLU_ENABLED TRUE +#define AT32_SCLKSEL AT32_SCLKSEL_PLL +#define AT32_PLLRCS AT32_PLLRCS_HEXT +#define AT32_PLL_MS_VALUE 1 +#define AT32_PLL_NS_VALUE 72 +#define AT32_PLL_FP_VALUE 4 +#define AT32_PLL_FU_VALUE 18 +#define AT32_AHBDIV AT32_AHBDIV_DIV1 +#define AT32_APB1DIV AT32_APB1DIV_DIV2 +#define AT32_APB2DIV AT32_APB2DIV_DIV1 +#define AT32_HICK_TO_SCLK AT32_HICK_TO_SCLK_48M +#define AT32_HICKDIV AT32_HICKDIV_DIV1 +#define AT32_HICK_TO_SCLK_DIV AT32_HICK_TO_SCLK_DIV_DIV1 +#define AT32_HEXT_TO_SCLK_DIV AT32_HEXT_TO_SCLK_DIV_DIV1 +#define AT32_USB_CLOCK48_REQUIRED TRUE +#define AT32_PLLU_USB48_SEL AT32_PLLU_USB48_SEL_PLLU +#define AT32_CLKOUT_SEL AT32_CLKOUT_SEL_HICK +#define AT32_CLKOUTDIV1 AT32_CLKOUTDIV1_DIV1 +#define AT32_CLKOUTDIV2 AT32_CLKOUTDIV2_DIV1 +#define AT32_ERTCSEL AT32_ERTCSEL_LICK +#define AT32_ERTCDIV_VALUE 12 +#define AT32_I2SF5CLKSEL AT32_I2SF5CLKSEL_SCLK +#define AT32_PVM_ENABLE FALSE +#define AT32_PVMSEL AT32_PVMSEL_LEV1 +#define AT32_LDOOVSEL AT32_LDOOVSEL_LEV3 + +/* + * IRQ system settings. + */ +#define AT32_IRQ_EXINT0_PRIORITY 6 +#define AT32_IRQ_EXINT1_PRIORITY 6 +#define AT32_IRQ_EXINT2_PRIORITY 6 +#define AT32_IRQ_EXINT3_PRIORITY 6 +#define AT32_IRQ_EXINT4_PRIORITY 6 +#define AT32_IRQ_EXINT5_9_PRIORITY 6 +#define AT32_IRQ_EXINT10_15_PRIORITY 6 +#define AT32_IRQ_EXINT16_PRIORITY 6 +#define AT32_IRQ_EXINT17_PRIORITY 15 +#define AT32_IRQ_EXINT18_PRIORITY 6 +#define AT32_IRQ_EXINT20_PRIORITY 6 +#define AT32_IRQ_EXINT21_PRIORITY 15 +#define AT32_IRQ_EXINT22_PRIORITY 15 + +#define AT32_IRQ_TMR1_BRK_TMR9_PRIORITY 7 +#define AT32_IRQ_TMR1_OVF_TMR10_PRIORITY 7 +#define AT32_IRQ_TMR1_HALL_TMR11_PRIORITY 7 +#define AT32_IRQ_TMR1_CH_PRIORITY 7 +#define AT32_IRQ_TMR2_PRIORITY 7 +#define AT32_IRQ_TMR3_PRIORITY 7 +#define AT32_IRQ_TMR4_PRIORITY 7 +#define AT32_IRQ_TMR6_PRIORITY 7 +#define AT32_IRQ_TMR7_PRIORITY 7 +#define AT32_IRQ_TMR13_PRIORITY 7 +#define AT32_IRQ_TMR14_PRIORITY 7 + +#define AT32_IRQ_USART1_PRIORITY 12 +#define AT32_IRQ_USART2_PRIORITY 12 +#define AT32_IRQ_USART3_PRIORITY 12 +#define AT32_IRQ_UART4_PRIORITY 12 +#define AT32_IRQ_UART5_PRIORITY 12 +#define AT32_IRQ_USART6_PRIORITY 12 +#define AT32_IRQ_UART7_PRIORITY 12 +#define AT32_IRQ_UART8_PRIORITY 12 + +/* + * ADC driver system settings. + */ +#define AT32_ADC_USE_ADC1 FALSE +#define AT32_ADC_ADC1_DMA_PRIORITY 2 +#define AT32_ADC_IRQ_PRIORITY 6 +#define AT32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define AT32_ADC_ADCDIV 8 + +/* + * CAN driver system settings. + */ +#define AT32_CAN_USE_CAN1 FALSE +#define AT32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * GPT driver system settings. + */ +#define AT32_GPT_USE_TMR1 FALSE +#define AT32_GPT_USE_TMR2 FALSE +#define AT32_GPT_USE_TMR3 FALSE +#define AT32_GPT_USE_TMR4 FALSE +#define AT32_GPT_USE_TMR6 FALSE +#define AT32_GPT_USE_TMR7 FALSE +#define AT32_GPT_USE_TMR9 FALSE +#define AT32_GPT_USE_TMR10 FALSE +#define AT32_GPT_USE_TMR11 FALSE +#define AT32_GPT_USE_TMR13 FALSE +#define AT32_GPT_USE_TMR14 FALSE + +/* + * I2C driver system settings. + */ +#define AT32_I2C_USE_I2C1 FALSE +#define AT32_I2C_USE_I2C2 FALSE +#define AT32_I2C_USE_I2C3 FALSE +#define AT32_I2C_BUSY_TIMEOUT 50 +#define AT32_I2C_I2C1_DMA_PRIORITY 3 +#define AT32_I2C_I2C2_DMA_PRIORITY 3 +#define AT32_I2C_I2C3_DMA_PRIORITY 3 +#define AT32_I2C_I2C1_IRQ_PRIORITY 5 +#define AT32_I2C_I2C2_IRQ_PRIORITY 5 +#define AT32_I2C_I2C3_IRQ_PRIORITY 5 +#define AT32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define AT32_ICU_USE_TMR1 FALSE +#define AT32_ICU_USE_TMR2 FALSE +#define AT32_ICU_USE_TMR3 FALSE +#define AT32_ICU_USE_TMR4 FALSE +#define AT32_ICU_USE_TMR9 FALSE + +/* + * PWM driver system settings. + */ +#define AT32_PWM_USE_TMR1 FALSE +#define AT32_PWM_USE_TMR2 FALSE +#define AT32_PWM_USE_TMR3 FALSE +#define AT32_PWM_USE_TMR4 FALSE +#define AT32_PWM_USE_TMR9 FALSE +#define AT32_PWM_USE_TMR10 FALSE +#define AT32_PWM_USE_TMR11 FALSE +#define AT32_PWM_USE_TMR13 FALSE +#define AT32_PWM_USE_TMR14 FALSE + +/* + * RTC driver system settings. + */ +#define AT32_ERTC_DIVA_VALUE 32 +#define AT32_ERTC_DIVB_VALUE 1024 +#define AT32_ERTC_CTRL_INIT 0 +#define AT32_ERTC_TAMP_INIT 0 + +/* + * SERIAL driver system settings. + */ +#define AT32_SERIAL_USE_USART1 TRUE +#define AT32_SERIAL_USE_USART2 FALSE +#define AT32_SERIAL_USE_USART3 FALSE +#define AT32_SERIAL_USE_UART4 FALSE +#define AT32_SERIAL_USE_UART5 FALSE +#define AT32_SERIAL_USE_USART6 FALSE +#define AT32_SERIAL_USE_UART7 FALSE +#define AT32_SERIAL_USE_UART8 FALSE + +/* + * SIO driver system settings. + */ +#define AT32_SIO_USE_USART1 FALSE +#define AT32_SIO_USE_USART2 FALSE +#define AT32_SIO_USE_USART3 FALSE +#define AT32_SIO_USE_UART4 FALSE +#define AT32_SIO_USE_UART5 FALSE +#define AT32_SIO_USE_USART6 FALSE +#define AT32_SIO_USE_UART7 FALSE +#define AT32_SIO_USE_UART8 FALSE + +/* + * SPI driver system settings. + */ +#define AT32_SPI_USE_SPI1 FALSE +#define AT32_SPI_USE_SPI2 FALSE +#define AT32_SPI_USE_SPI3 FALSE +#define AT32_SPI_SPI1_DMA_PRIORITY 1 +#define AT32_SPI_SPI2_DMA_PRIORITY 1 +#define AT32_SPI_SPI3_DMA_PRIORITY 1 +#define AT32_SPI_SPI1_IRQ_PRIORITY 10 +#define AT32_SPI_SPI2_IRQ_PRIORITY 10 +#define AT32_SPI_SPI3_IRQ_PRIORITY 10 +#define AT32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define AT32_ST_IRQ_PRIORITY 8 +#define AT32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define AT32_UART_USE_USART1 FALSE +#define AT32_UART_USE_USART2 FALSE +#define AT32_UART_USE_USART3 FALSE +#define AT32_UART_USE_UART4 FALSE +#define AT32_UART_USE_UART5 FALSE +#define AT32_UART_USE_USART6 FALSE +#define AT32_UART_USE_UART7 FALSE +#define AT32_UART_USE_UART8 FALSE +#define AT32_UART_USART1_DMA_PRIORITY 0 +#define AT32_UART_USART2_DMA_PRIORITY 0 +#define AT32_UART_USART3_DMA_PRIORITY 0 +#define AT32_UART_UART4_DMA_PRIORITY 0 +#define AT32_UART_UART5_DMA_PRIORITY 0 +#define AT32_UART_USART6_DMA_PRIORITY 0 +#define AT32_UART_UART7_DMA_PRIORITY 0 +#define AT32_UART_UART8_DMA_PRIORITY 0 +#define AT32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define AT32_USB_USE_OTG1 FALSE +#define AT32_USB_OTG1_IRQ_PRIORITY 14 +#define AT32_USB_OTG1_RX_FIFO_SIZE 512 + +/* + * WDG driver system settings. + */ +#define AT32_WDG_USE_WDT FALSE + +#include "config.h" + +#endif /* MCUCONF_H */ diff --git a/testhal/AT32/multi/ERTC/cfg/at-start-f402/portab.c b/testhal/AT32/multi/ERTC/cfg/at-start-f402/portab.c new file mode 100644 index 0000000000..ceaf0ff400 --- /dev/null +++ b/testhal/AT32/multi/ERTC/cfg/at-start-f402/portab.c @@ -0,0 +1,59 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file portab.c + * @brief Application portability module code. + * + * @addtogroup application_portability + * @{ + */ + +#include "hal.h" + +#include "portab.h" + +/*===========================================================================*/ +/* Module local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module exported functions. */ +/*===========================================================================*/ + +void portab_setup(void) { + +} + +/** @} */ diff --git a/testhal/AT32/multi/ERTC/cfg/at-start-f402/portab.h b/testhal/AT32/multi/ERTC/cfg/at-start-f402/portab.h new file mode 100644 index 0000000000..ef5548aeb7 --- /dev/null +++ b/testhal/AT32/multi/ERTC/cfg/at-start-f402/portab.h @@ -0,0 +1,78 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file portab.h + * @brief Application portability macros and structures. + * + * @addtogroup application_portability + * @{ + */ + +#ifndef PORTAB_H +#define PORTAB_H + +/*===========================================================================*/ +/* Module constants. */ +/*===========================================================================*/ + +#define PORTAB_RTC1 RTCD1 + +#define PORTAB_SD1 SD1 + +#define PORTAB_BLINK_LED1 LINE_LED_RED + +#define PORTAB_BLINK_LED2 LINE_LED_YELLOW + +#define PORTAB_BLINK_LED3 LINE_LED_GREEN + +/*===========================================================================*/ +/* Module pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void portab_setup(void); +#ifdef __cplusplus +} +#endif + +/*===========================================================================*/ +/* Module inline functions. */ +/*===========================================================================*/ + +#endif /* PORTAB_H */ + +/** @} */ diff --git a/testhal/AT32/multi/ERTC/cfg/at-start-f405/chconf.h b/testhal/AT32/multi/ERTC/cfg/at-start-f405/chconf.h new file mode 100644 index 0000000000..56fe06776a --- /dev/null +++ b/testhal/AT32/multi/ERTC/cfg/at-start-f405/chconf.h @@ -0,0 +1,842 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_7_0_ + +/*===========================================================================*/ +/** + * @name System settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Handling of instances. + * @note If enabled then threads assigned to various instances can + * interact each other using the same synchronization objects. + * If disabled then each OS instance is a separate world, no + * direct interactions are handled by the OS. + */ +#if !defined(CH_CFG_SMP_MODE) +#define CH_CFG_SMP_MODE FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_ST_RESOLUTION) +#define CH_CFG_ST_RESOLUTION 32 +#endif + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_CFG_ST_FREQUENCY) +#define CH_CFG_ST_FREQUENCY 10000 +#endif + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_INTERVALS_SIZE) +#define CH_CFG_INTERVALS_SIZE 32 +#endif + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_TIME_TYPES_SIZE) +#define CH_CFG_TIME_TYPES_SIZE 32 +#endif + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#if !defined(CH_CFG_ST_TIMEDELTA) +#define CH_CFG_ST_TIMEDELTA 2 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#if !defined(CH_CFG_TIME_QUANTUM) +#define CH_CFG_TIME_QUANTUM 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#if !defined(CH_CFG_NO_IDLE_THREAD) +#define CH_CFG_NO_IDLE_THREAD FALSE +#endif + +/** + * @brief Kernel hardening level. + * @details This option is the level of functional-safety checks enabled + * in the kerkel. The meaning is: + * - 0: No checks, maximum performance. + * - 1: Reasonable checks. + * - 2: All checks. + * . + */ +#if !defined(CH_CFG_HARDENING_LEVEL) +#define CH_CFG_HARDENING_LEVEL 0 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_OPTIMIZE_SPEED) +#define CH_CFG_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TM) +#define CH_CFG_USE_TM TRUE +#endif + +/** + * @brief Time Stamps APIs. + * @details If enabled then the time stamps APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TIMESTAMP) +#define CH_CFG_USE_TIMESTAMP TRUE +#endif + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_REGISTRY) +#define CH_CFG_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_WAITEXIT) +#define CH_CFG_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_SEMAPHORES) +#define CH_CFG_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MUTEXES) +#define CH_CFG_USE_MUTEXES TRUE +#endif + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_CONDVARS) +#define CH_CFG_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_EVENTS) +#define CH_CFG_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MESSAGES) +#define CH_CFG_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#if !defined(CH_CFG_USE_DYNAMIC) +#define CH_CFG_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name OSLIB options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_MAILBOXES) +#define CH_CFG_USE_MAILBOXES TRUE +#endif + +/** + * @brief Memory checks APIs. + * @details If enabled then the memory checks APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCHECKS) +#define CH_CFG_USE_MEMCHECKS TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCORE) +#define CH_CFG_USE_MEMCORE TRUE +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#if !defined(CH_CFG_MEMCORE_SIZE) +#define CH_CFG_MEMCORE_SIZE 0 +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_CFG_USE_HEAP) +#define CH_CFG_USE_HEAP TRUE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMPOOLS) +#define CH_CFG_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_FIFOS) +#define CH_CFG_USE_OBJ_FIFOS TRUE +#endif + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Objects Caches APIs. + * @details If enabled then the objects caches APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_CACHES) +#define CH_CFG_USE_OBJ_CACHES TRUE +#endif + +/** + * @brief Delegate threads APIs. + * @details If enabled then the delegate threads APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_DELEGATES) +#define CH_CFG_USE_DELEGATES TRUE +#endif + +/** + * @brief Jobs Queues APIs. + * @details If enabled then the jobs queues APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_JOBS) +#define CH_CFG_USE_JOBS TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_CFG_USE_FACTORY) +#define CH_CFG_USE_FACTORY TRUE +#endif + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 +#endif + +/** + * @brief Enables the registry of generic objects. + */ +#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE +#endif + +/** + * @brief Enables factory for generic buffers. + */ +#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE +#endif + +/** + * @brief Enables factory for semaphores. + */ +#if !defined(CH_CFG_FACTORY_SEMAPHORES) +#define CH_CFG_FACTORY_SEMAPHORES TRUE +#endif + +/** + * @brief Enables factory for mailboxes. + */ +#if !defined(CH_CFG_FACTORY_MAILBOXES) +#define CH_CFG_FACTORY_MAILBOXES TRUE +#endif + +/** + * @brief Enables factory for objects FIFOs. + */ +#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE +#endif + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_STATISTICS) +#define CH_DBG_STATISTICS FALSE +#endif + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_MASK) +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_ALL +#endif + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_BUFFER_SIZE) +#define CH_DBG_TRACE_BUFFER_SIZE 128 +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#if !defined(CH_DBG_THREADS_PROFILING) +#define CH_DBG_THREADS_PROFILING FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add system custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add system initialization code here.*/ \ +} + +/** + * @brief OS instance structure extension. + * @details User fields added to the end of the @p os_instance_t structure. + */ +#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS \ + /* Add OS instance custom fields here.*/ + +/** + * @brief OS instance initialization hook. + * + * @param[in] oip pointer to the @p os_instance_t structure + */ +#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) { \ + /* Add OS instance initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + * + * @param[in] ntp thread being switched in + * @param[in] otp thread being switched out + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** + * @brief Runtime Faults Collection Unit hook. + * @details This hook is invoked each time new faults are collected and stored. + */ +#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) { \ + /* Faults handling code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/testhal/AT32/multi/ERTC/cfg/at-start-f405/config.h b/testhal/AT32/multi/ERTC/cfg/at-start-f405/config.h new file mode 100644 index 0000000000..1e7c044f47 --- /dev/null +++ b/testhal/AT32/multi/ERTC/cfg/at-start-f405/config.h @@ -0,0 +1,39 @@ +/* + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * CRC driver system settings. + */ +#define AT32_CRC_USE_CRC1 FALSE + +#define CRC_USE_DMA FALSE +#define AT32_CRC_CRC1_DMA_PRIORITY 2 +#define AT32_CRC_CRC1_IRQ_PRIORITY 5 +#define AT32_CRC_CRC1_DMA_STREAM AT32_DMA_STREAM_ID_ANY + +/* + * I2C fallback driver system settings. + */ +#define SW_I2C_USE_I2C1 FALSE +#define SW_I2C_USE_I2C2 FALSE +#define SW_I2C_USE_I2C3 FALSE +#define SW_I2C_USE_I2C4 FALSE + +/* + * Other settings. + */ +#define BOARD_OTG_VBUSIG diff --git a/testhal/AT32/multi/ERTC/cfg/at-start-f405/halconf.h b/testhal/AT32/multi/ERTC/cfg/at-start-f405/halconf.h new file mode 100644 index 0000000000..1056b191e3 --- /dev/null +++ b/testhal/AT32/multi/ERTC/cfg/at-start-f405/halconf.h @@ -0,0 +1,557 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_8_4_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the EFlash subsystem. + */ +#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__) +#define HAL_USE_EFL FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC TRUE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/** + * @brief Enables the WSPI subsystem. + */ +#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) +#define HAL_USE_WSPI FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS FALSE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS FALSE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Timeout before assuming a failure while waiting for card idle. + * @note Time is in milliseconds. + */ +#if !defined(MMC_IDLE_TIMEOUT_MS) || defined(__DOXYGEN__) +#define MMC_IDLE_TIMEOUT_MS 1000 +#endif + +/** + * @brief Mutual exclusion on the SPI bus. + */ +#if !defined(MMC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define MMC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SIO driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SIO_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SIO_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Support for thread synchronization API. + */ +#if !defined(SIO_USE_SYNCHRONIZATION) || defined(__DOXYGEN__) +#define SIO_USE_SYNCHRONIZATION TRUE +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 256 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 2 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Inserts an assertion on function errors before returning. + */ +#if !defined(SPI_USE_ASSERT_ON_ERROR) || defined(__DOXYGEN__) +#define SPI_USE_ASSERT_ON_ERROR TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#include "halconf_community.h" + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/testhal/AT32/multi/ERTC/cfg/at-start-f405/halconf_community.h b/testhal/AT32/multi/ERTC/cfg/at-start-f405/halconf_community.h new file mode 100644 index 0000000000..5a77290c71 --- /dev/null +++ b/testhal/AT32/multi/ERTC/cfg/at-start-f405/halconf_community.h @@ -0,0 +1,182 @@ +/* + ChibiOS - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef HALCONF_COMMUNITY_H +#define HALCONF_COMMUNITY_H + +/** + * @brief Enables the community overlay. + */ +#if !defined(HAL_USE_COMMUNITY) || defined(__DOXYGEN__) +#define HAL_USE_COMMUNITY TRUE +#endif + +/** + * @brief Enables the FSMC subsystem. + */ +#if !defined(HAL_USE_FSMC) || defined(__DOXYGEN__) +#define HAL_USE_FSMC FALSE +#endif + +/** + * @brief Enables the NAND subsystem. + */ +#if !defined(HAL_USE_NAND) || defined(__DOXYGEN__) +#define HAL_USE_NAND FALSE +#endif + +/** + * @brief Enables the 1-wire subsystem. + */ +#if !defined(HAL_USE_ONEWIRE) || defined(__DOXYGEN__) +#define HAL_USE_ONEWIRE FALSE +#endif + +/** + * @brief Enables the EICU subsystem. + */ +#if !defined(HAL_USE_EICU) || defined(__DOXYGEN__) +#define HAL_USE_EICU FALSE +#endif + +/** + * @brief Enables the CRC subsystem. + */ +#if !defined(HAL_USE_CRC) || defined(__DOXYGEN__) +#define HAL_USE_CRC FALSE +#endif + +/** + * @brief Enables the RNG subsystem. + */ +#if !defined(HAL_USE_RNG) || defined(__DOXYGEN__) +#define HAL_USE_RNG FALSE +#endif + +/** + * @brief Enables the EEPROM subsystem. + */ +#if !defined(HAL_USE_EEPROM) || defined(__DOXYGEN__) +#define HAL_USE_EEPROM FALSE +#endif + +/** + * @brief Enables the TIMCAP subsystem. + */ +#if !defined(HAL_USE_TIMCAP) || defined(__DOXYGEN__) +#define HAL_USE_TIMCAP FALSE +#endif + +/** + * @brief Enables the COMP subsystem. + */ +#if !defined(HAL_USE_COMP) || defined(__DOXYGEN__) +#define HAL_USE_COMP FALSE +#endif + +/** + * @brief Enables the OPAMP subsystem. + */ +#if !defined(HAL_USE_OPAMP) || defined(__DOXYGEN__) +#define HAL_USE_OPAMP FALSE +#endif + +/** + * @brief Enables the QEI subsystem. + */ +#if !defined(HAL_USE_QEI) || defined(__DOXYGEN__) +#define HAL_USE_QEI FALSE +#endif + +/** + * @brief Enables the USBH subsystem. + */ +#if !defined(HAL_USE_USBH) || defined(__DOXYGEN__) +#define HAL_USE_USBH FALSE +#endif + +/** + * @brief Enables the USB_MSD subsystem. + */ +#if !defined(HAL_USE_USB_MSD) || defined(__DOXYGEN__) +#define HAL_USE_USB_MSD FALSE +#endif + +/*===========================================================================*/ +/* FSMCNAND driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the @p nandAcquireBus() and @p nanReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(NAND_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define NAND_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* 1-wire driver related settings. */ +/*===========================================================================*/ +/** + * @brief Enables strong pull up feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_STRONG_PULLUP FALSE + +/** + * @brief Enables search ROM feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_SEARCH_ROM TRUE + +/*===========================================================================*/ +/* QEI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables discard of overlow + */ +#if !defined(QEI_USE_OVERFLOW_DISCARD) || defined(__DOXYGEN__) +#define QEI_USE_OVERFLOW_DISCARD FALSE +#endif + +/** + * @brief Enables min max of overlow + */ +#if !defined(QEI_USE_OVERFLOW_MINMAX) || defined(__DOXYGEN__) +#define QEI_USE_OVERFLOW_MINMAX FALSE +#endif + +/*===========================================================================*/ +/* EEProm driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables 24xx series I2C eeprom device driver. + * @note Disabling this option saves both code and data space. + */ +#define EEPROM_USE_EE24XX FALSE + /** + * @brief Enables 25xx series SPI eeprom device driver. + * @note Disabling this option saves both code and data space. + */ +#define EEPROM_USE_EE25XX FALSE + +#endif /* HALCONF_COMMUNITY_H */ + +/** @} */ diff --git a/testhal/AT32/multi/ERTC/cfg/at-start-f405/mcuconf.h b/testhal/AT32/multi/ERTC/cfg/at-start-f405/mcuconf.h new file mode 100644 index 0000000000..e745923283 --- /dev/null +++ b/testhal/AT32/multi/ERTC/cfg/at-start-f405/mcuconf.h @@ -0,0 +1,272 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef MCUCONF_H +#define MCUCONF_H + +/* + * AT32F405 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define AT32F405_MCUCONF + +/* + * General settings. + */ +#define AT32_NO_INIT FALSE + +/* + * HAL driver system settings. + */ +#define AT32_HICK_ENABLED TRUE +#define AT32_LICK_ENABLED TRUE +#define AT32_HEXT_ENABLED TRUE +#define AT32_LEXT_ENABLED FALSE +#define AT32_PLLU_ENABLED TRUE +#define AT32_SCLKSEL AT32_SCLKSEL_PLL +#define AT32_PLLRCS AT32_PLLRCS_HEXT +#define AT32_PLL_MS_VALUE 1 +#define AT32_PLL_NS_VALUE 72 +#define AT32_PLL_FP_VALUE 4 +#define AT32_PLL_FU_VALUE 18 +#define AT32_AHBDIV AT32_AHBDIV_DIV1 +#define AT32_APB1DIV AT32_APB1DIV_DIV2 +#define AT32_APB2DIV AT32_APB2DIV_DIV1 +#define AT32_HICK_TO_SCLK AT32_HICK_TO_SCLK_48M +#define AT32_HICKDIV AT32_HICKDIV_DIV1 +#define AT32_HICK_TO_SCLK_DIV AT32_HICK_TO_SCLK_DIV_DIV1 +#define AT32_HEXT_TO_SCLK_DIV AT32_HEXT_TO_SCLK_DIV_DIV1 +#define AT32_USB_CLOCK48_REQUIRED TRUE +#define AT32_PLLU_USB48_SEL AT32_PLLU_USB48_SEL_PLLU +#define AT32_CLKOUT_SEL AT32_CLKOUT_SEL_HICK +#define AT32_CLKOUTDIV1 AT32_CLKOUTDIV1_DIV1 +#define AT32_CLKOUTDIV2 AT32_CLKOUTDIV2_DIV1 +#define AT32_ERTCSEL AT32_ERTCSEL_LICK +#define AT32_ERTCDIV_VALUE 12 +#define AT32_I2SF5CLKSEL AT32_I2SF5CLKSEL_SCLK +#define AT32_PVM_ENABLE FALSE +#define AT32_PVMSEL AT32_PVMSEL_LEV1 +#define AT32_LDOOVSEL AT32_LDOOVSEL_LEV3 + +/* + * IRQ system settings. + */ +#define AT32_IRQ_EXINT0_PRIORITY 6 +#define AT32_IRQ_EXINT1_PRIORITY 6 +#define AT32_IRQ_EXINT2_PRIORITY 6 +#define AT32_IRQ_EXINT3_PRIORITY 6 +#define AT32_IRQ_EXINT4_PRIORITY 6 +#define AT32_IRQ_EXINT5_9_PRIORITY 6 +#define AT32_IRQ_EXINT10_15_PRIORITY 6 +#define AT32_IRQ_EXINT16_PRIORITY 6 +#define AT32_IRQ_EXINT17_PRIORITY 15 +#define AT32_IRQ_EXINT18_PRIORITY 6 +#define AT32_IRQ_EXINT20_PRIORITY 6 +#define AT32_IRQ_EXINT21_PRIORITY 15 +#define AT32_IRQ_EXINT22_PRIORITY 15 + +#define AT32_IRQ_TMR1_BRK_TMR9_PRIORITY 7 +#define AT32_IRQ_TMR1_OVF_TMR10_PRIORITY 7 +#define AT32_IRQ_TMR1_HALL_TMR11_PRIORITY 7 +#define AT32_IRQ_TMR1_CH_PRIORITY 7 +#define AT32_IRQ_TMR2_PRIORITY 7 +#define AT32_IRQ_TMR3_PRIORITY 7 +#define AT32_IRQ_TMR4_PRIORITY 7 +#define AT32_IRQ_TMR6_PRIORITY 7 +#define AT32_IRQ_TMR7_PRIORITY 7 +#define AT32_IRQ_TMR13_PRIORITY 7 +#define AT32_IRQ_TMR14_PRIORITY 7 + +#define AT32_IRQ_USART1_PRIORITY 12 +#define AT32_IRQ_USART2_PRIORITY 12 +#define AT32_IRQ_USART3_PRIORITY 12 +#define AT32_IRQ_UART4_PRIORITY 12 +#define AT32_IRQ_UART5_PRIORITY 12 +#define AT32_IRQ_USART6_PRIORITY 12 +#define AT32_IRQ_UART7_PRIORITY 12 +#define AT32_IRQ_UART8_PRIORITY 12 + +/* + * ADC driver system settings. + */ +#define AT32_ADC_USE_ADC1 FALSE +#define AT32_ADC_ADC1_DMA_PRIORITY 2 +#define AT32_ADC_IRQ_PRIORITY 6 +#define AT32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define AT32_ADC_ADCDIV 8 + +/* + * CAN driver system settings. + */ +#define AT32_CAN_USE_CAN1 FALSE +#define AT32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * GPT driver system settings. + */ +#define AT32_GPT_USE_TMR1 FALSE +#define AT32_GPT_USE_TMR2 FALSE +#define AT32_GPT_USE_TMR3 FALSE +#define AT32_GPT_USE_TMR4 FALSE +#define AT32_GPT_USE_TMR6 FALSE +#define AT32_GPT_USE_TMR7 FALSE +#define AT32_GPT_USE_TMR9 FALSE +#define AT32_GPT_USE_TMR10 FALSE +#define AT32_GPT_USE_TMR11 FALSE +#define AT32_GPT_USE_TMR13 FALSE +#define AT32_GPT_USE_TMR14 FALSE + +/* + * I2C driver system settings. + */ +#define AT32_I2C_USE_I2C1 FALSE +#define AT32_I2C_USE_I2C2 FALSE +#define AT32_I2C_USE_I2C3 FALSE +#define AT32_I2C_BUSY_TIMEOUT 50 +#define AT32_I2C_I2C1_DMA_PRIORITY 3 +#define AT32_I2C_I2C2_DMA_PRIORITY 3 +#define AT32_I2C_I2C3_DMA_PRIORITY 3 +#define AT32_I2C_I2C1_IRQ_PRIORITY 5 +#define AT32_I2C_I2C2_IRQ_PRIORITY 5 +#define AT32_I2C_I2C3_IRQ_PRIORITY 5 +#define AT32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define AT32_ICU_USE_TMR1 FALSE +#define AT32_ICU_USE_TMR2 FALSE +#define AT32_ICU_USE_TMR3 FALSE +#define AT32_ICU_USE_TMR4 FALSE +#define AT32_ICU_USE_TMR9 FALSE + +/* + * PWM driver system settings. + */ +#define AT32_PWM_USE_TMR1 FALSE +#define AT32_PWM_USE_TMR2 FALSE +#define AT32_PWM_USE_TMR3 FALSE +#define AT32_PWM_USE_TMR4 FALSE +#define AT32_PWM_USE_TMR9 FALSE +#define AT32_PWM_USE_TMR10 FALSE +#define AT32_PWM_USE_TMR11 FALSE +#define AT32_PWM_USE_TMR13 FALSE +#define AT32_PWM_USE_TMR14 FALSE + +/* + * RTC driver system settings. + */ +#define AT32_ERTC_DIVA_VALUE 32 +#define AT32_ERTC_DIVB_VALUE 1024 +#define AT32_ERTC_CTRL_INIT 0 +#define AT32_ERTC_TAMP_INIT 0 + +/* + * SERIAL driver system settings. + */ +#define AT32_SERIAL_USE_USART1 TRUE +#define AT32_SERIAL_USE_USART2 FALSE +#define AT32_SERIAL_USE_USART3 FALSE +#define AT32_SERIAL_USE_UART4 FALSE +#define AT32_SERIAL_USE_UART5 FALSE +#define AT32_SERIAL_USE_USART6 FALSE +#define AT32_SERIAL_USE_UART7 FALSE +#define AT32_SERIAL_USE_UART8 FALSE + +/* + * SIO driver system settings. + */ +#define AT32_SIO_USE_USART1 FALSE +#define AT32_SIO_USE_USART2 FALSE +#define AT32_SIO_USE_USART3 FALSE +#define AT32_SIO_USE_UART4 FALSE +#define AT32_SIO_USE_UART5 FALSE +#define AT32_SIO_USE_USART6 FALSE +#define AT32_SIO_USE_UART7 FALSE +#define AT32_SIO_USE_UART8 FALSE + +/* + * SPI driver system settings. + */ +#define AT32_SPI_USE_SPI1 FALSE +#define AT32_SPI_USE_SPI2 FALSE +#define AT32_SPI_USE_SPI3 FALSE +#define AT32_SPI_SPI1_DMA_PRIORITY 1 +#define AT32_SPI_SPI2_DMA_PRIORITY 1 +#define AT32_SPI_SPI3_DMA_PRIORITY 1 +#define AT32_SPI_SPI1_IRQ_PRIORITY 10 +#define AT32_SPI_SPI2_IRQ_PRIORITY 10 +#define AT32_SPI_SPI3_IRQ_PRIORITY 10 +#define AT32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define AT32_ST_IRQ_PRIORITY 8 +#define AT32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define AT32_UART_USE_USART1 FALSE +#define AT32_UART_USE_USART2 FALSE +#define AT32_UART_USE_USART3 FALSE +#define AT32_UART_USE_UART4 FALSE +#define AT32_UART_USE_UART5 FALSE +#define AT32_UART_USE_USART6 FALSE +#define AT32_UART_USE_UART7 FALSE +#define AT32_UART_USE_UART8 FALSE +#define AT32_UART_USART1_DMA_PRIORITY 0 +#define AT32_UART_USART2_DMA_PRIORITY 0 +#define AT32_UART_USART3_DMA_PRIORITY 0 +#define AT32_UART_UART4_DMA_PRIORITY 0 +#define AT32_UART_UART5_DMA_PRIORITY 0 +#define AT32_UART_USART6_DMA_PRIORITY 0 +#define AT32_UART_UART7_DMA_PRIORITY 0 +#define AT32_UART_UART8_DMA_PRIORITY 0 +#define AT32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define AT32_USB_USE_OTG1 FALSE +#define AT32_USB_USE_OTG2 FALSE +#define AT32_USB_OTG1_IRQ_PRIORITY 14 +#define AT32_USB_OTG2_IRQ_PRIORITY 14 +#define AT32_USB_OTG1_RX_FIFO_SIZE 512 +#define AT32_USB_OTG2_RX_FIFO_SIZE 1024 +#define AT32_USE_USB_OTG2_HS_DMA FALSE + +/* + * WDG driver system settings. + */ +#define AT32_WDG_USE_WDT FALSE + +#include "config.h" + +#endif /* MCUCONF_H */ diff --git a/testhal/AT32/multi/ERTC/cfg/at-start-f405/portab.c b/testhal/AT32/multi/ERTC/cfg/at-start-f405/portab.c new file mode 100644 index 0000000000..ceaf0ff400 --- /dev/null +++ b/testhal/AT32/multi/ERTC/cfg/at-start-f405/portab.c @@ -0,0 +1,59 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file portab.c + * @brief Application portability module code. + * + * @addtogroup application_portability + * @{ + */ + +#include "hal.h" + +#include "portab.h" + +/*===========================================================================*/ +/* Module local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module exported functions. */ +/*===========================================================================*/ + +void portab_setup(void) { + +} + +/** @} */ diff --git a/testhal/AT32/multi/ERTC/cfg/at-start-f405/portab.h b/testhal/AT32/multi/ERTC/cfg/at-start-f405/portab.h new file mode 100644 index 0000000000..ef5548aeb7 --- /dev/null +++ b/testhal/AT32/multi/ERTC/cfg/at-start-f405/portab.h @@ -0,0 +1,78 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file portab.h + * @brief Application portability macros and structures. + * + * @addtogroup application_portability + * @{ + */ + +#ifndef PORTAB_H +#define PORTAB_H + +/*===========================================================================*/ +/* Module constants. */ +/*===========================================================================*/ + +#define PORTAB_RTC1 RTCD1 + +#define PORTAB_SD1 SD1 + +#define PORTAB_BLINK_LED1 LINE_LED_RED + +#define PORTAB_BLINK_LED2 LINE_LED_YELLOW + +#define PORTAB_BLINK_LED3 LINE_LED_GREEN + +/*===========================================================================*/ +/* Module pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void portab_setup(void); +#ifdef __cplusplus +} +#endif + +/*===========================================================================*/ +/* Module inline functions. */ +/*===========================================================================*/ + +#endif /* PORTAB_H */ + +/** @} */ diff --git a/testhal/AT32/multi/ERTC/cfg/at-start-f415/chconf.h b/testhal/AT32/multi/ERTC/cfg/at-start-f415/chconf.h index 46b3f78b68..56fe06776a 100644 --- a/testhal/AT32/multi/ERTC/cfg/at-start-f415/chconf.h +++ b/testhal/AT32/multi/ERTC/cfg/at-start-f415/chconf.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/testhal/AT32/multi/ERTC/cfg/at-start-f415/config.h b/testhal/AT32/multi/ERTC/cfg/at-start-f415/config.h index 361e185d9c..056a8f39ff 100644 --- a/testhal/AT32/multi/ERTC/cfg/at-start-f415/config.h +++ b/testhal/AT32/multi/ERTC/cfg/at-start-f415/config.h @@ -1,6 +1,6 @@ /* - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/testhal/AT32/multi/ERTC/cfg/at-start-f415/halconf.h b/testhal/AT32/multi/ERTC/cfg/at-start-f415/halconf.h index 9f0399ec2a..1056b191e3 100644 --- a/testhal/AT32/multi/ERTC/cfg/at-start-f415/halconf.h +++ b/testhal/AT32/multi/ERTC/cfg/at-start-f415/halconf.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/testhal/AT32/multi/ERTC/cfg/at-start-f415/halconf_community.h b/testhal/AT32/multi/ERTC/cfg/at-start-f415/halconf_community.h index c43d668764..5a77290c71 100644 --- a/testhal/AT32/multi/ERTC/cfg/at-start-f415/halconf_community.h +++ b/testhal/AT32/multi/ERTC/cfg/at-start-f415/halconf_community.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/testhal/AT32/multi/ERTC/cfg/at-start-f415/mcuconf.h b/testhal/AT32/multi/ERTC/cfg/at-start-f415/mcuconf.h index 83d3bfaa93..f0b85388f2 100644 --- a/testhal/AT32/multi/ERTC/cfg/at-start-f415/mcuconf.h +++ b/testhal/AT32/multi/ERTC/cfg/at-start-f415/mcuconf.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -106,6 +106,7 @@ #define AT32_ADC_USE_ADC1 FALSE #define AT32_ADC_ADC1_DMA_PRIORITY 2 #define AT32_ADC_ADC1_IRQ_PRIORITY 6 +#define AT32_ADC_ADC1_DMA_IRQ_PRIORITY 6 /* * CAN driver system settings. diff --git a/testhal/AT32/multi/ERTC/cfg/at-start-f415/portab.c b/testhal/AT32/multi/ERTC/cfg/at-start-f415/portab.c index 25e871321a..ceaf0ff400 100644 --- a/testhal/AT32/multi/ERTC/cfg/at-start-f415/portab.c +++ b/testhal/AT32/multi/ERTC/cfg/at-start-f415/portab.c @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/testhal/AT32/multi/ERTC/cfg/at-start-f415/portab.h b/testhal/AT32/multi/ERTC/cfg/at-start-f415/portab.h index 022c388716..ef5548aeb7 100644 --- a/testhal/AT32/multi/ERTC/cfg/at-start-f415/portab.h +++ b/testhal/AT32/multi/ERTC/cfg/at-start-f415/portab.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/testhal/AT32/multi/ERTC/main.c b/testhal/AT32/multi/ERTC/main.c index 36a683a0a4..80acf12a1c 100644 --- a/testhal/AT32/multi/ERTC/main.c +++ b/testhal/AT32/multi/ERTC/main.c @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/testhal/AT32/multi/ERTC/make/at-start-f402.make b/testhal/AT32/multi/ERTC/make/at-start-f402.make new file mode 100644 index 0000000000..bc38709398 --- /dev/null +++ b/testhal/AT32/multi/ERTC/make/at-start-f402.make @@ -0,0 +1,198 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO). +ifeq ($(USE_LTO),) + USE_LTO = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# Enable this if you want to use bitbang I2C. +ifeq ($(USE_HAL_I2C_FALLBACK),) + USE_HAL_I2C_FALLBACK = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x400 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU (no, softfp, hard). +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# FPU-related options. +ifeq ($(USE_FPU_OPT),) + USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16 +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, target, sources and paths +# + +# Define project name here +PROJECT = ch + +# Target settings. +MCU = cortex-m4 + +# Imported source files and paths. +CHIBIOS := ../../../../../ChibiOS +CHIBIOS_CONTRIB := ../../../.. +CONFDIR := ./cfg/at-start-f402 +BUILDDIR := ./build/at-start-f402 +DEPDIR := ./.dep/at-start-f402 + +# Licensing files. +include $(CHIBIOS)/os/license/license.mk +# Startup files. +include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_at32f402.mk +# HAL-OSAL files (optional). +include $(CHIBIOS_CONTRIB)/os/hal/hal.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/AT32F402_405/platform.mk +include $(CHIBIOS_CONTRIB)/os/hal/boards/AT_START_F402/board.mk +include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMv7-M/compilers/GCC/mk/port.mk +# Auto-build files in ./source recursively. +include $(CHIBIOS)/tools/mk/autobuild.mk +# Other files (optional). +include $(CHIBIOS)/os/test/test.mk +include $(CHIBIOS)/test/rt/rt_test.mk +include $(CHIBIOS)/test/oslib/oslib_test.mk +include $(CHIBIOS)/os/hal/lib/streams/streams.mk +include $(CHIBIOS)/os/various/shell/shell.mk + +# Define linker script file here. +LDSCRIPT= $(STARTUPLD_CONTRIB)/AT32F402xC.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(ALLCSRC) \ + $(TESTSRC) \ + $(CONFDIR)/portab.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = $(ALLCPPSRC) + +# List ASM source files here. +ASMSRC = $(ALLASMSRC) + +# List ASM with preprocessor source files here. +ASMXSRC = $(ALLXASMSRC) + +# Inclusion directories. +INCDIR = $(CONFDIR) $(ALLINC) $(TESTINC) + +# Define C warning options here. +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes + +# Define C++ warning options here. +CPPWARN = -Wall -Wextra -Wundef + +# +# Project, target, sources and paths +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user section +############################################################################## + +############################################################################## +# Common rules +# + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk +include $(RULESPATH)/arm-none-eabi.mk +include $(RULESPATH)/rules.mk + +# +# Common rules +############################################################################## + +############################################################################## +# Custom rules +# + +# +# Custom rules +############################################################################## diff --git a/testhal/AT32/multi/ERTC/make/at-start-f405.make b/testhal/AT32/multi/ERTC/make/at-start-f405.make new file mode 100644 index 0000000000..e58a437a00 --- /dev/null +++ b/testhal/AT32/multi/ERTC/make/at-start-f405.make @@ -0,0 +1,198 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO). +ifeq ($(USE_LTO),) + USE_LTO = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# Enable this if you want to use bitbang I2C. +ifeq ($(USE_HAL_I2C_FALLBACK),) + USE_HAL_I2C_FALLBACK = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x400 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU (no, softfp, hard). +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# FPU-related options. +ifeq ($(USE_FPU_OPT),) + USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16 +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, target, sources and paths +# + +# Define project name here +PROJECT = ch + +# Target settings. +MCU = cortex-m4 + +# Imported source files and paths. +CHIBIOS := ../../../../../ChibiOS +CHIBIOS_CONTRIB := ../../../.. +CONFDIR := ./cfg/at-start-f405 +BUILDDIR := ./build/at-start-f405 +DEPDIR := ./.dep/at-start-f405 + +# Licensing files. +include $(CHIBIOS)/os/license/license.mk +# Startup files. +include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_at32f405.mk +# HAL-OSAL files (optional). +include $(CHIBIOS_CONTRIB)/os/hal/hal.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/AT32F402_405/platform.mk +include $(CHIBIOS_CONTRIB)/os/hal/boards/AT_START_F405/board.mk +include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMv7-M/compilers/GCC/mk/port.mk +# Auto-build files in ./source recursively. +include $(CHIBIOS)/tools/mk/autobuild.mk +# Other files (optional). +include $(CHIBIOS)/os/test/test.mk +include $(CHIBIOS)/test/rt/rt_test.mk +include $(CHIBIOS)/test/oslib/oslib_test.mk +include $(CHIBIOS)/os/hal/lib/streams/streams.mk +include $(CHIBIOS)/os/various/shell/shell.mk + +# Define linker script file here. +LDSCRIPT= $(STARTUPLD_CONTRIB)/AT32F405xC.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(ALLCSRC) \ + $(TESTSRC) \ + $(CONFDIR)/portab.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = $(ALLCPPSRC) + +# List ASM source files here. +ASMSRC = $(ALLASMSRC) + +# List ASM with preprocessor source files here. +ASMXSRC = $(ALLXASMSRC) + +# Inclusion directories. +INCDIR = $(CONFDIR) $(ALLINC) $(TESTINC) + +# Define C warning options here. +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes + +# Define C++ warning options here. +CPPWARN = -Wall -Wextra -Wundef + +# +# Project, target, sources and paths +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user section +############################################################################## + +############################################################################## +# Common rules +# + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk +include $(RULESPATH)/arm-none-eabi.mk +include $(RULESPATH)/rules.mk + +# +# Common rules +############################################################################## + +############################################################################## +# Custom rules +# + +# +# Custom rules +############################################################################## diff --git a/testhal/AT32/multi/I2C_HW/Makefile b/testhal/AT32/multi/I2C_HW/Makefile index c8606df05e..fdf3019a85 100644 --- a/testhal/AT32/multi/I2C_HW/Makefile +++ b/testhal/AT32/multi/I2C_HW/Makefile @@ -3,6 +3,14 @@ # all: + @echo + @echo === Building for AT-START-F402 ===================================== + +@make --no-print-directory -f ./make/at-start-f402.make all + @echo ==================================================================== + @echo + @echo === Building for AT-START-F405 ===================================== + +@make --no-print-directory -f ./make/at-start-f405.make all + @echo ==================================================================== @echo @echo === Building for AT-START-F415 ===================================== +@make --no-print-directory -f ./make/at-start-f415.make all @@ -10,6 +18,10 @@ all: @echo clean: + @echo + +@make --no-print-directory -f ./make/at-start-f402.make clean + @echo + +@make --no-print-directory -f ./make/at-start-f405.make clean @echo +@make --no-print-directory -f ./make/at-start-f415.make clean @echo diff --git a/testhal/AT32/multi/I2C_HW/cfg/at-start-f402/chconf.h b/testhal/AT32/multi/I2C_HW/cfg/at-start-f402/chconf.h new file mode 100644 index 0000000000..56fe06776a --- /dev/null +++ b/testhal/AT32/multi/I2C_HW/cfg/at-start-f402/chconf.h @@ -0,0 +1,842 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_7_0_ + +/*===========================================================================*/ +/** + * @name System settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Handling of instances. + * @note If enabled then threads assigned to various instances can + * interact each other using the same synchronization objects. + * If disabled then each OS instance is a separate world, no + * direct interactions are handled by the OS. + */ +#if !defined(CH_CFG_SMP_MODE) +#define CH_CFG_SMP_MODE FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_ST_RESOLUTION) +#define CH_CFG_ST_RESOLUTION 32 +#endif + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_CFG_ST_FREQUENCY) +#define CH_CFG_ST_FREQUENCY 10000 +#endif + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_INTERVALS_SIZE) +#define CH_CFG_INTERVALS_SIZE 32 +#endif + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_TIME_TYPES_SIZE) +#define CH_CFG_TIME_TYPES_SIZE 32 +#endif + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#if !defined(CH_CFG_ST_TIMEDELTA) +#define CH_CFG_ST_TIMEDELTA 2 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#if !defined(CH_CFG_TIME_QUANTUM) +#define CH_CFG_TIME_QUANTUM 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#if !defined(CH_CFG_NO_IDLE_THREAD) +#define CH_CFG_NO_IDLE_THREAD FALSE +#endif + +/** + * @brief Kernel hardening level. + * @details This option is the level of functional-safety checks enabled + * in the kerkel. The meaning is: + * - 0: No checks, maximum performance. + * - 1: Reasonable checks. + * - 2: All checks. + * . + */ +#if !defined(CH_CFG_HARDENING_LEVEL) +#define CH_CFG_HARDENING_LEVEL 0 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_OPTIMIZE_SPEED) +#define CH_CFG_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TM) +#define CH_CFG_USE_TM TRUE +#endif + +/** + * @brief Time Stamps APIs. + * @details If enabled then the time stamps APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TIMESTAMP) +#define CH_CFG_USE_TIMESTAMP TRUE +#endif + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_REGISTRY) +#define CH_CFG_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_WAITEXIT) +#define CH_CFG_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_SEMAPHORES) +#define CH_CFG_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MUTEXES) +#define CH_CFG_USE_MUTEXES TRUE +#endif + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_CONDVARS) +#define CH_CFG_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_EVENTS) +#define CH_CFG_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MESSAGES) +#define CH_CFG_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#if !defined(CH_CFG_USE_DYNAMIC) +#define CH_CFG_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name OSLIB options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_MAILBOXES) +#define CH_CFG_USE_MAILBOXES TRUE +#endif + +/** + * @brief Memory checks APIs. + * @details If enabled then the memory checks APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCHECKS) +#define CH_CFG_USE_MEMCHECKS TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCORE) +#define CH_CFG_USE_MEMCORE TRUE +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#if !defined(CH_CFG_MEMCORE_SIZE) +#define CH_CFG_MEMCORE_SIZE 0 +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_CFG_USE_HEAP) +#define CH_CFG_USE_HEAP TRUE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMPOOLS) +#define CH_CFG_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_FIFOS) +#define CH_CFG_USE_OBJ_FIFOS TRUE +#endif + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Objects Caches APIs. + * @details If enabled then the objects caches APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_CACHES) +#define CH_CFG_USE_OBJ_CACHES TRUE +#endif + +/** + * @brief Delegate threads APIs. + * @details If enabled then the delegate threads APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_DELEGATES) +#define CH_CFG_USE_DELEGATES TRUE +#endif + +/** + * @brief Jobs Queues APIs. + * @details If enabled then the jobs queues APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_JOBS) +#define CH_CFG_USE_JOBS TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_CFG_USE_FACTORY) +#define CH_CFG_USE_FACTORY TRUE +#endif + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 +#endif + +/** + * @brief Enables the registry of generic objects. + */ +#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE +#endif + +/** + * @brief Enables factory for generic buffers. + */ +#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE +#endif + +/** + * @brief Enables factory for semaphores. + */ +#if !defined(CH_CFG_FACTORY_SEMAPHORES) +#define CH_CFG_FACTORY_SEMAPHORES TRUE +#endif + +/** + * @brief Enables factory for mailboxes. + */ +#if !defined(CH_CFG_FACTORY_MAILBOXES) +#define CH_CFG_FACTORY_MAILBOXES TRUE +#endif + +/** + * @brief Enables factory for objects FIFOs. + */ +#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE +#endif + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_STATISTICS) +#define CH_DBG_STATISTICS FALSE +#endif + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_MASK) +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_ALL +#endif + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_BUFFER_SIZE) +#define CH_DBG_TRACE_BUFFER_SIZE 128 +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#if !defined(CH_DBG_THREADS_PROFILING) +#define CH_DBG_THREADS_PROFILING FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add system custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add system initialization code here.*/ \ +} + +/** + * @brief OS instance structure extension. + * @details User fields added to the end of the @p os_instance_t structure. + */ +#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS \ + /* Add OS instance custom fields here.*/ + +/** + * @brief OS instance initialization hook. + * + * @param[in] oip pointer to the @p os_instance_t structure + */ +#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) { \ + /* Add OS instance initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + * + * @param[in] ntp thread being switched in + * @param[in] otp thread being switched out + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** + * @brief Runtime Faults Collection Unit hook. + * @details This hook is invoked each time new faults are collected and stored. + */ +#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) { \ + /* Faults handling code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/testhal/AT32/multi/I2C_HW/cfg/at-start-f402/config.h b/testhal/AT32/multi/I2C_HW/cfg/at-start-f402/config.h new file mode 100644 index 0000000000..1e7c044f47 --- /dev/null +++ b/testhal/AT32/multi/I2C_HW/cfg/at-start-f402/config.h @@ -0,0 +1,39 @@ +/* + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * CRC driver system settings. + */ +#define AT32_CRC_USE_CRC1 FALSE + +#define CRC_USE_DMA FALSE +#define AT32_CRC_CRC1_DMA_PRIORITY 2 +#define AT32_CRC_CRC1_IRQ_PRIORITY 5 +#define AT32_CRC_CRC1_DMA_STREAM AT32_DMA_STREAM_ID_ANY + +/* + * I2C fallback driver system settings. + */ +#define SW_I2C_USE_I2C1 FALSE +#define SW_I2C_USE_I2C2 FALSE +#define SW_I2C_USE_I2C3 FALSE +#define SW_I2C_USE_I2C4 FALSE + +/* + * Other settings. + */ +#define BOARD_OTG_VBUSIG diff --git a/testhal/AT32/multi/I2C_HW/cfg/at-start-f402/halconf.h b/testhal/AT32/multi/I2C_HW/cfg/at-start-f402/halconf.h new file mode 100644 index 0000000000..f1bf5fd204 --- /dev/null +++ b/testhal/AT32/multi/I2C_HW/cfg/at-start-f402/halconf.h @@ -0,0 +1,557 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_8_4_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the EFlash subsystem. + */ +#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__) +#define HAL_USE_EFL FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C TRUE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/** + * @brief Enables the WSPI subsystem. + */ +#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) +#define HAL_USE_WSPI FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS FALSE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS FALSE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Timeout before assuming a failure while waiting for card idle. + * @note Time is in milliseconds. + */ +#if !defined(MMC_IDLE_TIMEOUT_MS) || defined(__DOXYGEN__) +#define MMC_IDLE_TIMEOUT_MS 1000 +#endif + +/** + * @brief Mutual exclusion on the SPI bus. + */ +#if !defined(MMC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define MMC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SIO driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SIO_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SIO_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Support for thread synchronization API. + */ +#if !defined(SIO_USE_SYNCHRONIZATION) || defined(__DOXYGEN__) +#define SIO_USE_SYNCHRONIZATION TRUE +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 256 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 2 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Inserts an assertion on function errors before returning. + */ +#if !defined(SPI_USE_ASSERT_ON_ERROR) || defined(__DOXYGEN__) +#define SPI_USE_ASSERT_ON_ERROR TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#include "halconf_community.h" + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/testhal/AT32/multi/I2C_HW/cfg/at-start-f402/halconf_community.h b/testhal/AT32/multi/I2C_HW/cfg/at-start-f402/halconf_community.h new file mode 100644 index 0000000000..5a77290c71 --- /dev/null +++ b/testhal/AT32/multi/I2C_HW/cfg/at-start-f402/halconf_community.h @@ -0,0 +1,182 @@ +/* + ChibiOS - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef HALCONF_COMMUNITY_H +#define HALCONF_COMMUNITY_H + +/** + * @brief Enables the community overlay. + */ +#if !defined(HAL_USE_COMMUNITY) || defined(__DOXYGEN__) +#define HAL_USE_COMMUNITY TRUE +#endif + +/** + * @brief Enables the FSMC subsystem. + */ +#if !defined(HAL_USE_FSMC) || defined(__DOXYGEN__) +#define HAL_USE_FSMC FALSE +#endif + +/** + * @brief Enables the NAND subsystem. + */ +#if !defined(HAL_USE_NAND) || defined(__DOXYGEN__) +#define HAL_USE_NAND FALSE +#endif + +/** + * @brief Enables the 1-wire subsystem. + */ +#if !defined(HAL_USE_ONEWIRE) || defined(__DOXYGEN__) +#define HAL_USE_ONEWIRE FALSE +#endif + +/** + * @brief Enables the EICU subsystem. + */ +#if !defined(HAL_USE_EICU) || defined(__DOXYGEN__) +#define HAL_USE_EICU FALSE +#endif + +/** + * @brief Enables the CRC subsystem. + */ +#if !defined(HAL_USE_CRC) || defined(__DOXYGEN__) +#define HAL_USE_CRC FALSE +#endif + +/** + * @brief Enables the RNG subsystem. + */ +#if !defined(HAL_USE_RNG) || defined(__DOXYGEN__) +#define HAL_USE_RNG FALSE +#endif + +/** + * @brief Enables the EEPROM subsystem. + */ +#if !defined(HAL_USE_EEPROM) || defined(__DOXYGEN__) +#define HAL_USE_EEPROM FALSE +#endif + +/** + * @brief Enables the TIMCAP subsystem. + */ +#if !defined(HAL_USE_TIMCAP) || defined(__DOXYGEN__) +#define HAL_USE_TIMCAP FALSE +#endif + +/** + * @brief Enables the COMP subsystem. + */ +#if !defined(HAL_USE_COMP) || defined(__DOXYGEN__) +#define HAL_USE_COMP FALSE +#endif + +/** + * @brief Enables the OPAMP subsystem. + */ +#if !defined(HAL_USE_OPAMP) || defined(__DOXYGEN__) +#define HAL_USE_OPAMP FALSE +#endif + +/** + * @brief Enables the QEI subsystem. + */ +#if !defined(HAL_USE_QEI) || defined(__DOXYGEN__) +#define HAL_USE_QEI FALSE +#endif + +/** + * @brief Enables the USBH subsystem. + */ +#if !defined(HAL_USE_USBH) || defined(__DOXYGEN__) +#define HAL_USE_USBH FALSE +#endif + +/** + * @brief Enables the USB_MSD subsystem. + */ +#if !defined(HAL_USE_USB_MSD) || defined(__DOXYGEN__) +#define HAL_USE_USB_MSD FALSE +#endif + +/*===========================================================================*/ +/* FSMCNAND driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the @p nandAcquireBus() and @p nanReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(NAND_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define NAND_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* 1-wire driver related settings. */ +/*===========================================================================*/ +/** + * @brief Enables strong pull up feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_STRONG_PULLUP FALSE + +/** + * @brief Enables search ROM feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_SEARCH_ROM TRUE + +/*===========================================================================*/ +/* QEI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables discard of overlow + */ +#if !defined(QEI_USE_OVERFLOW_DISCARD) || defined(__DOXYGEN__) +#define QEI_USE_OVERFLOW_DISCARD FALSE +#endif + +/** + * @brief Enables min max of overlow + */ +#if !defined(QEI_USE_OVERFLOW_MINMAX) || defined(__DOXYGEN__) +#define QEI_USE_OVERFLOW_MINMAX FALSE +#endif + +/*===========================================================================*/ +/* EEProm driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables 24xx series I2C eeprom device driver. + * @note Disabling this option saves both code and data space. + */ +#define EEPROM_USE_EE24XX FALSE + /** + * @brief Enables 25xx series SPI eeprom device driver. + * @note Disabling this option saves both code and data space. + */ +#define EEPROM_USE_EE25XX FALSE + +#endif /* HALCONF_COMMUNITY_H */ + +/** @} */ diff --git a/testhal/AT32/multi/I2C_HW/cfg/at-start-f402/mcuconf.h b/testhal/AT32/multi/I2C_HW/cfg/at-start-f402/mcuconf.h new file mode 100644 index 0000000000..de5ef83e35 --- /dev/null +++ b/testhal/AT32/multi/I2C_HW/cfg/at-start-f402/mcuconf.h @@ -0,0 +1,268 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef MCUCONF_H +#define MCUCONF_H + +/* + * AT32F402 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define AT32F402_MCUCONF + +/* + * General settings. + */ +#define AT32_NO_INIT FALSE + +/* + * HAL driver system settings. + */ +#define AT32_HICK_ENABLED TRUE +#define AT32_LICK_ENABLED FALSE +#define AT32_HEXT_ENABLED TRUE +#define AT32_LEXT_ENABLED FALSE +#define AT32_PLLU_ENABLED TRUE +#define AT32_SCLKSEL AT32_SCLKSEL_PLL +#define AT32_PLLRCS AT32_PLLRCS_HEXT +#define AT32_PLL_MS_VALUE 1 +#define AT32_PLL_NS_VALUE 72 +#define AT32_PLL_FP_VALUE 4 +#define AT32_PLL_FU_VALUE 18 +#define AT32_AHBDIV AT32_AHBDIV_DIV1 +#define AT32_APB1DIV AT32_APB1DIV_DIV2 +#define AT32_APB2DIV AT32_APB2DIV_DIV1 +#define AT32_HICK_TO_SCLK AT32_HICK_TO_SCLK_48M +#define AT32_HICKDIV AT32_HICKDIV_DIV1 +#define AT32_HICK_TO_SCLK_DIV AT32_HICK_TO_SCLK_DIV_DIV1 +#define AT32_HEXT_TO_SCLK_DIV AT32_HEXT_TO_SCLK_DIV_DIV1 +#define AT32_USB_CLOCK48_REQUIRED TRUE +#define AT32_PLLU_USB48_SEL AT32_PLLU_USB48_SEL_PLLU +#define AT32_CLKOUT_SEL AT32_CLKOUT_SEL_HICK +#define AT32_CLKOUTDIV1 AT32_CLKOUTDIV1_DIV1 +#define AT32_CLKOUTDIV2 AT32_CLKOUTDIV2_DIV1 +#define AT32_ERTCSEL AT32_ERTCSEL_NOCLOCK +#define AT32_ERTCDIV_VALUE 12 +#define AT32_I2SF5CLKSEL AT32_I2SF5CLKSEL_SCLK +#define AT32_PVM_ENABLE FALSE +#define AT32_PVMSEL AT32_PVMSEL_LEV1 +#define AT32_LDOOVSEL AT32_LDOOVSEL_LEV3 + +/* + * IRQ system settings. + */ +#define AT32_IRQ_EXINT0_PRIORITY 6 +#define AT32_IRQ_EXINT1_PRIORITY 6 +#define AT32_IRQ_EXINT2_PRIORITY 6 +#define AT32_IRQ_EXINT3_PRIORITY 6 +#define AT32_IRQ_EXINT4_PRIORITY 6 +#define AT32_IRQ_EXINT5_9_PRIORITY 6 +#define AT32_IRQ_EXINT10_15_PRIORITY 6 +#define AT32_IRQ_EXINT16_PRIORITY 6 +#define AT32_IRQ_EXINT17_PRIORITY 15 +#define AT32_IRQ_EXINT18_PRIORITY 6 +#define AT32_IRQ_EXINT20_PRIORITY 6 +#define AT32_IRQ_EXINT21_PRIORITY 15 +#define AT32_IRQ_EXINT22_PRIORITY 15 + +#define AT32_IRQ_TMR1_BRK_TMR9_PRIORITY 7 +#define AT32_IRQ_TMR1_OVF_TMR10_PRIORITY 7 +#define AT32_IRQ_TMR1_HALL_TMR11_PRIORITY 7 +#define AT32_IRQ_TMR1_CH_PRIORITY 7 +#define AT32_IRQ_TMR2_PRIORITY 7 +#define AT32_IRQ_TMR3_PRIORITY 7 +#define AT32_IRQ_TMR4_PRIORITY 7 +#define AT32_IRQ_TMR6_PRIORITY 7 +#define AT32_IRQ_TMR7_PRIORITY 7 +#define AT32_IRQ_TMR13_PRIORITY 7 +#define AT32_IRQ_TMR14_PRIORITY 7 + +#define AT32_IRQ_USART1_PRIORITY 12 +#define AT32_IRQ_USART2_PRIORITY 12 +#define AT32_IRQ_USART3_PRIORITY 12 +#define AT32_IRQ_UART4_PRIORITY 12 +#define AT32_IRQ_UART5_PRIORITY 12 +#define AT32_IRQ_USART6_PRIORITY 12 +#define AT32_IRQ_UART7_PRIORITY 12 +#define AT32_IRQ_UART8_PRIORITY 12 + +/* + * ADC driver system settings. + */ +#define AT32_ADC_USE_ADC1 FALSE +#define AT32_ADC_ADC1_DMA_PRIORITY 2 +#define AT32_ADC_IRQ_PRIORITY 6 +#define AT32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define AT32_ADC_ADCDIV 8 + +/* + * CAN driver system settings. + */ +#define AT32_CAN_USE_CAN1 FALSE +#define AT32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * GPT driver system settings. + */ +#define AT32_GPT_USE_TMR1 FALSE +#define AT32_GPT_USE_TMR2 FALSE +#define AT32_GPT_USE_TMR3 FALSE +#define AT32_GPT_USE_TMR4 FALSE +#define AT32_GPT_USE_TMR6 FALSE +#define AT32_GPT_USE_TMR7 FALSE +#define AT32_GPT_USE_TMR9 FALSE +#define AT32_GPT_USE_TMR10 FALSE +#define AT32_GPT_USE_TMR11 FALSE +#define AT32_GPT_USE_TMR13 FALSE +#define AT32_GPT_USE_TMR14 FALSE + +/* + * I2C driver system settings. + */ +#define AT32_I2C_USE_I2C1 TRUE +#define AT32_I2C_USE_I2C2 FALSE +#define AT32_I2C_USE_I2C3 FALSE +#define AT32_I2C_BUSY_TIMEOUT 50 +#define AT32_I2C_I2C1_DMA_PRIORITY 3 +#define AT32_I2C_I2C2_DMA_PRIORITY 3 +#define AT32_I2C_I2C3_DMA_PRIORITY 3 +#define AT32_I2C_I2C1_IRQ_PRIORITY 5 +#define AT32_I2C_I2C2_IRQ_PRIORITY 5 +#define AT32_I2C_I2C3_IRQ_PRIORITY 5 +#define AT32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define AT32_ICU_USE_TMR1 FALSE +#define AT32_ICU_USE_TMR2 FALSE +#define AT32_ICU_USE_TMR3 FALSE +#define AT32_ICU_USE_TMR4 FALSE +#define AT32_ICU_USE_TMR9 FALSE + +/* + * PWM driver system settings. + */ +#define AT32_PWM_USE_TMR1 FALSE +#define AT32_PWM_USE_TMR2 FALSE +#define AT32_PWM_USE_TMR3 FALSE +#define AT32_PWM_USE_TMR4 FALSE +#define AT32_PWM_USE_TMR9 FALSE +#define AT32_PWM_USE_TMR10 FALSE +#define AT32_PWM_USE_TMR11 FALSE +#define AT32_PWM_USE_TMR13 FALSE +#define AT32_PWM_USE_TMR14 FALSE + +/* + * RTC driver system settings. + */ +#define AT32_ERTC_DIVA_VALUE 32 +#define AT32_ERTC_DIVB_VALUE 1024 +#define AT32_ERTC_CTRL_INIT 0 +#define AT32_ERTC_TAMP_INIT 0 + +/* + * SERIAL driver system settings. + */ +#define AT32_SERIAL_USE_USART1 FALSE +#define AT32_SERIAL_USE_USART2 FALSE +#define AT32_SERIAL_USE_USART3 FALSE +#define AT32_SERIAL_USE_UART4 FALSE +#define AT32_SERIAL_USE_UART5 FALSE +#define AT32_SERIAL_USE_USART6 FALSE +#define AT32_SERIAL_USE_UART7 FALSE +#define AT32_SERIAL_USE_UART8 FALSE + +/* + * SIO driver system settings. + */ +#define AT32_SIO_USE_USART1 FALSE +#define AT32_SIO_USE_USART2 FALSE +#define AT32_SIO_USE_USART3 FALSE +#define AT32_SIO_USE_UART4 FALSE +#define AT32_SIO_USE_UART5 FALSE +#define AT32_SIO_USE_USART6 FALSE +#define AT32_SIO_USE_UART7 FALSE +#define AT32_SIO_USE_UART8 FALSE + +/* + * SPI driver system settings. + */ +#define AT32_SPI_USE_SPI1 FALSE +#define AT32_SPI_USE_SPI2 FALSE +#define AT32_SPI_USE_SPI3 FALSE +#define AT32_SPI_SPI1_DMA_PRIORITY 1 +#define AT32_SPI_SPI2_DMA_PRIORITY 1 +#define AT32_SPI_SPI3_DMA_PRIORITY 1 +#define AT32_SPI_SPI1_IRQ_PRIORITY 10 +#define AT32_SPI_SPI2_IRQ_PRIORITY 10 +#define AT32_SPI_SPI3_IRQ_PRIORITY 10 +#define AT32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define AT32_ST_IRQ_PRIORITY 8 +#define AT32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define AT32_UART_USE_USART1 FALSE +#define AT32_UART_USE_USART2 FALSE +#define AT32_UART_USE_USART3 FALSE +#define AT32_UART_USE_UART4 FALSE +#define AT32_UART_USE_UART5 FALSE +#define AT32_UART_USE_USART6 FALSE +#define AT32_UART_USE_UART7 FALSE +#define AT32_UART_USE_UART8 FALSE +#define AT32_UART_USART1_DMA_PRIORITY 0 +#define AT32_UART_USART2_DMA_PRIORITY 0 +#define AT32_UART_USART3_DMA_PRIORITY 0 +#define AT32_UART_UART4_DMA_PRIORITY 0 +#define AT32_UART_UART5_DMA_PRIORITY 0 +#define AT32_UART_USART6_DMA_PRIORITY 0 +#define AT32_UART_UART7_DMA_PRIORITY 0 +#define AT32_UART_UART8_DMA_PRIORITY 0 +#define AT32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define AT32_USB_USE_OTG1 FALSE +#define AT32_USB_OTG1_IRQ_PRIORITY 14 +#define AT32_USB_OTG1_RX_FIFO_SIZE 512 + +/* + * WDG driver system settings. + */ +#define AT32_WDG_USE_WDT FALSE + +#include "config.h" + +#endif /* MCUCONF_H */ diff --git a/testhal/AT32/multi/I2C_HW/cfg/at-start-f402/portab.c b/testhal/AT32/multi/I2C_HW/cfg/at-start-f402/portab.c new file mode 100644 index 0000000000..95d45183f7 --- /dev/null +++ b/testhal/AT32/multi/I2C_HW/cfg/at-start-f402/portab.c @@ -0,0 +1,71 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file portab.c + * @brief Application portability module code. + * + * @addtogroup application_portability + * @{ + */ + +#include "hal.h" + +#include "portab.h" + +/*===========================================================================*/ +/* Module local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module exported variables. */ +/*===========================================================================*/ + +/* + * I2C driver configuration structure. + */ +I2CConfig i2ccfg = { + AT32_CLKCTRL_DIV(9U) | + AT32_CLKCTRL_SCLD(14U) | AT32_CLKCTRL_SDAD(0U) | + AT32_CLKCTRL_SCLH(49U) | AT32_CLKCTRL_SCLL(49U), + 0, + 0 +}; + +/*===========================================================================*/ +/* Module local types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module exported functions. */ +/*===========================================================================*/ + +void portab_setup(void) { + palSetLineMode(PAL_LINE(GPIOB, 6U), PAL_MODE_MUX(4) | PAL_AT32_OMODE_OPENDRAIN); + palSetLineMode(PAL_LINE(GPIOB, 7U), PAL_MODE_MUX(4) | PAL_AT32_OMODE_OPENDRAIN); +} + +/** @} */ diff --git a/testhal/AT32/multi/I2C_HW/cfg/at-start-f402/portab.h b/testhal/AT32/multi/I2C_HW/cfg/at-start-f402/portab.h new file mode 100644 index 0000000000..c714e7e8f1 --- /dev/null +++ b/testhal/AT32/multi/I2C_HW/cfg/at-start-f402/portab.h @@ -0,0 +1,78 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file portab.h + * @brief Application portability macros and structures. + * + * @addtogroup application_portability + * @{ + */ + +#ifndef PORTAB_H +#define PORTAB_H + +/*===========================================================================*/ +/* Module constants. */ +/*===========================================================================*/ + +#define PORTAB_I2C1 I2CD1 + +#define PORTAB_BLINK_LED1 LINE_LED_RED + +#define PORTAB_BLINK_LED2 LINE_LED_YELLOW + +#define PORTAB_BLINK_LED3 LINE_LED_GREEN + +/*===========================================================================*/ +/* Module pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +extern I2CConfig i2ccfg; + +#ifdef __cplusplus +extern "C" { +#endif + void portab_setup(void); +#ifdef __cplusplus +} +#endif + +/*===========================================================================*/ +/* Module inline functions. */ +/*===========================================================================*/ + +#endif /* PORTAB_H */ + +/** @} */ diff --git a/testhal/AT32/multi/I2C_HW/cfg/at-start-f405/chconf.h b/testhal/AT32/multi/I2C_HW/cfg/at-start-f405/chconf.h new file mode 100644 index 0000000000..56fe06776a --- /dev/null +++ b/testhal/AT32/multi/I2C_HW/cfg/at-start-f405/chconf.h @@ -0,0 +1,842 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_7_0_ + +/*===========================================================================*/ +/** + * @name System settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Handling of instances. + * @note If enabled then threads assigned to various instances can + * interact each other using the same synchronization objects. + * If disabled then each OS instance is a separate world, no + * direct interactions are handled by the OS. + */ +#if !defined(CH_CFG_SMP_MODE) +#define CH_CFG_SMP_MODE FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_ST_RESOLUTION) +#define CH_CFG_ST_RESOLUTION 32 +#endif + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_CFG_ST_FREQUENCY) +#define CH_CFG_ST_FREQUENCY 10000 +#endif + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_INTERVALS_SIZE) +#define CH_CFG_INTERVALS_SIZE 32 +#endif + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_TIME_TYPES_SIZE) +#define CH_CFG_TIME_TYPES_SIZE 32 +#endif + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#if !defined(CH_CFG_ST_TIMEDELTA) +#define CH_CFG_ST_TIMEDELTA 2 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#if !defined(CH_CFG_TIME_QUANTUM) +#define CH_CFG_TIME_QUANTUM 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#if !defined(CH_CFG_NO_IDLE_THREAD) +#define CH_CFG_NO_IDLE_THREAD FALSE +#endif + +/** + * @brief Kernel hardening level. + * @details This option is the level of functional-safety checks enabled + * in the kerkel. The meaning is: + * - 0: No checks, maximum performance. + * - 1: Reasonable checks. + * - 2: All checks. + * . + */ +#if !defined(CH_CFG_HARDENING_LEVEL) +#define CH_CFG_HARDENING_LEVEL 0 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_OPTIMIZE_SPEED) +#define CH_CFG_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TM) +#define CH_CFG_USE_TM TRUE +#endif + +/** + * @brief Time Stamps APIs. + * @details If enabled then the time stamps APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TIMESTAMP) +#define CH_CFG_USE_TIMESTAMP TRUE +#endif + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_REGISTRY) +#define CH_CFG_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_WAITEXIT) +#define CH_CFG_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_SEMAPHORES) +#define CH_CFG_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MUTEXES) +#define CH_CFG_USE_MUTEXES TRUE +#endif + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_CONDVARS) +#define CH_CFG_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_EVENTS) +#define CH_CFG_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MESSAGES) +#define CH_CFG_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#if !defined(CH_CFG_USE_DYNAMIC) +#define CH_CFG_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name OSLIB options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_MAILBOXES) +#define CH_CFG_USE_MAILBOXES TRUE +#endif + +/** + * @brief Memory checks APIs. + * @details If enabled then the memory checks APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCHECKS) +#define CH_CFG_USE_MEMCHECKS TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCORE) +#define CH_CFG_USE_MEMCORE TRUE +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#if !defined(CH_CFG_MEMCORE_SIZE) +#define CH_CFG_MEMCORE_SIZE 0 +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_CFG_USE_HEAP) +#define CH_CFG_USE_HEAP TRUE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMPOOLS) +#define CH_CFG_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_FIFOS) +#define CH_CFG_USE_OBJ_FIFOS TRUE +#endif + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Objects Caches APIs. + * @details If enabled then the objects caches APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_CACHES) +#define CH_CFG_USE_OBJ_CACHES TRUE +#endif + +/** + * @brief Delegate threads APIs. + * @details If enabled then the delegate threads APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_DELEGATES) +#define CH_CFG_USE_DELEGATES TRUE +#endif + +/** + * @brief Jobs Queues APIs. + * @details If enabled then the jobs queues APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_JOBS) +#define CH_CFG_USE_JOBS TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_CFG_USE_FACTORY) +#define CH_CFG_USE_FACTORY TRUE +#endif + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 +#endif + +/** + * @brief Enables the registry of generic objects. + */ +#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE +#endif + +/** + * @brief Enables factory for generic buffers. + */ +#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE +#endif + +/** + * @brief Enables factory for semaphores. + */ +#if !defined(CH_CFG_FACTORY_SEMAPHORES) +#define CH_CFG_FACTORY_SEMAPHORES TRUE +#endif + +/** + * @brief Enables factory for mailboxes. + */ +#if !defined(CH_CFG_FACTORY_MAILBOXES) +#define CH_CFG_FACTORY_MAILBOXES TRUE +#endif + +/** + * @brief Enables factory for objects FIFOs. + */ +#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE +#endif + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_STATISTICS) +#define CH_DBG_STATISTICS FALSE +#endif + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_MASK) +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_ALL +#endif + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_BUFFER_SIZE) +#define CH_DBG_TRACE_BUFFER_SIZE 128 +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#if !defined(CH_DBG_THREADS_PROFILING) +#define CH_DBG_THREADS_PROFILING FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add system custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add system initialization code here.*/ \ +} + +/** + * @brief OS instance structure extension. + * @details User fields added to the end of the @p os_instance_t structure. + */ +#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS \ + /* Add OS instance custom fields here.*/ + +/** + * @brief OS instance initialization hook. + * + * @param[in] oip pointer to the @p os_instance_t structure + */ +#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) { \ + /* Add OS instance initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + * + * @param[in] ntp thread being switched in + * @param[in] otp thread being switched out + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** + * @brief Runtime Faults Collection Unit hook. + * @details This hook is invoked each time new faults are collected and stored. + */ +#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) { \ + /* Faults handling code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/testhal/AT32/multi/I2C_HW/cfg/at-start-f405/config.h b/testhal/AT32/multi/I2C_HW/cfg/at-start-f405/config.h new file mode 100644 index 0000000000..1e7c044f47 --- /dev/null +++ b/testhal/AT32/multi/I2C_HW/cfg/at-start-f405/config.h @@ -0,0 +1,39 @@ +/* + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * CRC driver system settings. + */ +#define AT32_CRC_USE_CRC1 FALSE + +#define CRC_USE_DMA FALSE +#define AT32_CRC_CRC1_DMA_PRIORITY 2 +#define AT32_CRC_CRC1_IRQ_PRIORITY 5 +#define AT32_CRC_CRC1_DMA_STREAM AT32_DMA_STREAM_ID_ANY + +/* + * I2C fallback driver system settings. + */ +#define SW_I2C_USE_I2C1 FALSE +#define SW_I2C_USE_I2C2 FALSE +#define SW_I2C_USE_I2C3 FALSE +#define SW_I2C_USE_I2C4 FALSE + +/* + * Other settings. + */ +#define BOARD_OTG_VBUSIG diff --git a/testhal/AT32/multi/I2C_HW/cfg/at-start-f405/halconf.h b/testhal/AT32/multi/I2C_HW/cfg/at-start-f405/halconf.h new file mode 100644 index 0000000000..f1bf5fd204 --- /dev/null +++ b/testhal/AT32/multi/I2C_HW/cfg/at-start-f405/halconf.h @@ -0,0 +1,557 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_8_4_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the EFlash subsystem. + */ +#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__) +#define HAL_USE_EFL FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C TRUE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/** + * @brief Enables the WSPI subsystem. + */ +#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) +#define HAL_USE_WSPI FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS FALSE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS FALSE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Timeout before assuming a failure while waiting for card idle. + * @note Time is in milliseconds. + */ +#if !defined(MMC_IDLE_TIMEOUT_MS) || defined(__DOXYGEN__) +#define MMC_IDLE_TIMEOUT_MS 1000 +#endif + +/** + * @brief Mutual exclusion on the SPI bus. + */ +#if !defined(MMC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define MMC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SIO driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SIO_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SIO_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Support for thread synchronization API. + */ +#if !defined(SIO_USE_SYNCHRONIZATION) || defined(__DOXYGEN__) +#define SIO_USE_SYNCHRONIZATION TRUE +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 256 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 2 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Inserts an assertion on function errors before returning. + */ +#if !defined(SPI_USE_ASSERT_ON_ERROR) || defined(__DOXYGEN__) +#define SPI_USE_ASSERT_ON_ERROR TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#include "halconf_community.h" + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/testhal/AT32/multi/I2C_HW/cfg/at-start-f405/halconf_community.h b/testhal/AT32/multi/I2C_HW/cfg/at-start-f405/halconf_community.h new file mode 100644 index 0000000000..5a77290c71 --- /dev/null +++ b/testhal/AT32/multi/I2C_HW/cfg/at-start-f405/halconf_community.h @@ -0,0 +1,182 @@ +/* + ChibiOS - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef HALCONF_COMMUNITY_H +#define HALCONF_COMMUNITY_H + +/** + * @brief Enables the community overlay. + */ +#if !defined(HAL_USE_COMMUNITY) || defined(__DOXYGEN__) +#define HAL_USE_COMMUNITY TRUE +#endif + +/** + * @brief Enables the FSMC subsystem. + */ +#if !defined(HAL_USE_FSMC) || defined(__DOXYGEN__) +#define HAL_USE_FSMC FALSE +#endif + +/** + * @brief Enables the NAND subsystem. + */ +#if !defined(HAL_USE_NAND) || defined(__DOXYGEN__) +#define HAL_USE_NAND FALSE +#endif + +/** + * @brief Enables the 1-wire subsystem. + */ +#if !defined(HAL_USE_ONEWIRE) || defined(__DOXYGEN__) +#define HAL_USE_ONEWIRE FALSE +#endif + +/** + * @brief Enables the EICU subsystem. + */ +#if !defined(HAL_USE_EICU) || defined(__DOXYGEN__) +#define HAL_USE_EICU FALSE +#endif + +/** + * @brief Enables the CRC subsystem. + */ +#if !defined(HAL_USE_CRC) || defined(__DOXYGEN__) +#define HAL_USE_CRC FALSE +#endif + +/** + * @brief Enables the RNG subsystem. + */ +#if !defined(HAL_USE_RNG) || defined(__DOXYGEN__) +#define HAL_USE_RNG FALSE +#endif + +/** + * @brief Enables the EEPROM subsystem. + */ +#if !defined(HAL_USE_EEPROM) || defined(__DOXYGEN__) +#define HAL_USE_EEPROM FALSE +#endif + +/** + * @brief Enables the TIMCAP subsystem. + */ +#if !defined(HAL_USE_TIMCAP) || defined(__DOXYGEN__) +#define HAL_USE_TIMCAP FALSE +#endif + +/** + * @brief Enables the COMP subsystem. + */ +#if !defined(HAL_USE_COMP) || defined(__DOXYGEN__) +#define HAL_USE_COMP FALSE +#endif + +/** + * @brief Enables the OPAMP subsystem. + */ +#if !defined(HAL_USE_OPAMP) || defined(__DOXYGEN__) +#define HAL_USE_OPAMP FALSE +#endif + +/** + * @brief Enables the QEI subsystem. + */ +#if !defined(HAL_USE_QEI) || defined(__DOXYGEN__) +#define HAL_USE_QEI FALSE +#endif + +/** + * @brief Enables the USBH subsystem. + */ +#if !defined(HAL_USE_USBH) || defined(__DOXYGEN__) +#define HAL_USE_USBH FALSE +#endif + +/** + * @brief Enables the USB_MSD subsystem. + */ +#if !defined(HAL_USE_USB_MSD) || defined(__DOXYGEN__) +#define HAL_USE_USB_MSD FALSE +#endif + +/*===========================================================================*/ +/* FSMCNAND driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the @p nandAcquireBus() and @p nanReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(NAND_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define NAND_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* 1-wire driver related settings. */ +/*===========================================================================*/ +/** + * @brief Enables strong pull up feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_STRONG_PULLUP FALSE + +/** + * @brief Enables search ROM feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_SEARCH_ROM TRUE + +/*===========================================================================*/ +/* QEI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables discard of overlow + */ +#if !defined(QEI_USE_OVERFLOW_DISCARD) || defined(__DOXYGEN__) +#define QEI_USE_OVERFLOW_DISCARD FALSE +#endif + +/** + * @brief Enables min max of overlow + */ +#if !defined(QEI_USE_OVERFLOW_MINMAX) || defined(__DOXYGEN__) +#define QEI_USE_OVERFLOW_MINMAX FALSE +#endif + +/*===========================================================================*/ +/* EEProm driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables 24xx series I2C eeprom device driver. + * @note Disabling this option saves both code and data space. + */ +#define EEPROM_USE_EE24XX FALSE + /** + * @brief Enables 25xx series SPI eeprom device driver. + * @note Disabling this option saves both code and data space. + */ +#define EEPROM_USE_EE25XX FALSE + +#endif /* HALCONF_COMMUNITY_H */ + +/** @} */ diff --git a/testhal/AT32/multi/I2C_HW/cfg/at-start-f405/mcuconf.h b/testhal/AT32/multi/I2C_HW/cfg/at-start-f405/mcuconf.h new file mode 100644 index 0000000000..ae59b7a87b --- /dev/null +++ b/testhal/AT32/multi/I2C_HW/cfg/at-start-f405/mcuconf.h @@ -0,0 +1,272 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef MCUCONF_H +#define MCUCONF_H + +/* + * AT32F405 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define AT32F405_MCUCONF + +/* + * General settings. + */ +#define AT32_NO_INIT FALSE + +/* + * HAL driver system settings. + */ +#define AT32_HICK_ENABLED TRUE +#define AT32_LICK_ENABLED FALSE +#define AT32_HEXT_ENABLED TRUE +#define AT32_LEXT_ENABLED FALSE +#define AT32_PLLU_ENABLED TRUE +#define AT32_SCLKSEL AT32_SCLKSEL_PLL +#define AT32_PLLRCS AT32_PLLRCS_HEXT +#define AT32_PLL_MS_VALUE 1 +#define AT32_PLL_NS_VALUE 72 +#define AT32_PLL_FP_VALUE 4 +#define AT32_PLL_FU_VALUE 18 +#define AT32_AHBDIV AT32_AHBDIV_DIV1 +#define AT32_APB1DIV AT32_APB1DIV_DIV2 +#define AT32_APB2DIV AT32_APB2DIV_DIV1 +#define AT32_HICK_TO_SCLK AT32_HICK_TO_SCLK_48M +#define AT32_HICKDIV AT32_HICKDIV_DIV1 +#define AT32_HICK_TO_SCLK_DIV AT32_HICK_TO_SCLK_DIV_DIV1 +#define AT32_HEXT_TO_SCLK_DIV AT32_HEXT_TO_SCLK_DIV_DIV1 +#define AT32_USB_CLOCK48_REQUIRED TRUE +#define AT32_PLLU_USB48_SEL AT32_PLLU_USB48_SEL_PLLU +#define AT32_CLKOUT_SEL AT32_CLKOUT_SEL_HICK +#define AT32_CLKOUTDIV1 AT32_CLKOUTDIV1_DIV1 +#define AT32_CLKOUTDIV2 AT32_CLKOUTDIV2_DIV1 +#define AT32_ERTCSEL AT32_ERTCSEL_NOCLOCK +#define AT32_ERTCDIV_VALUE 12 +#define AT32_I2SF5CLKSEL AT32_I2SF5CLKSEL_SCLK +#define AT32_PVM_ENABLE FALSE +#define AT32_PVMSEL AT32_PVMSEL_LEV1 +#define AT32_LDOOVSEL AT32_LDOOVSEL_LEV3 + +/* + * IRQ system settings. + */ +#define AT32_IRQ_EXINT0_PRIORITY 6 +#define AT32_IRQ_EXINT1_PRIORITY 6 +#define AT32_IRQ_EXINT2_PRIORITY 6 +#define AT32_IRQ_EXINT3_PRIORITY 6 +#define AT32_IRQ_EXINT4_PRIORITY 6 +#define AT32_IRQ_EXINT5_9_PRIORITY 6 +#define AT32_IRQ_EXINT10_15_PRIORITY 6 +#define AT32_IRQ_EXINT16_PRIORITY 6 +#define AT32_IRQ_EXINT17_PRIORITY 15 +#define AT32_IRQ_EXINT18_PRIORITY 6 +#define AT32_IRQ_EXINT20_PRIORITY 6 +#define AT32_IRQ_EXINT21_PRIORITY 15 +#define AT32_IRQ_EXINT22_PRIORITY 15 + +#define AT32_IRQ_TMR1_BRK_TMR9_PRIORITY 7 +#define AT32_IRQ_TMR1_OVF_TMR10_PRIORITY 7 +#define AT32_IRQ_TMR1_HALL_TMR11_PRIORITY 7 +#define AT32_IRQ_TMR1_CH_PRIORITY 7 +#define AT32_IRQ_TMR2_PRIORITY 7 +#define AT32_IRQ_TMR3_PRIORITY 7 +#define AT32_IRQ_TMR4_PRIORITY 7 +#define AT32_IRQ_TMR6_PRIORITY 7 +#define AT32_IRQ_TMR7_PRIORITY 7 +#define AT32_IRQ_TMR13_PRIORITY 7 +#define AT32_IRQ_TMR14_PRIORITY 7 + +#define AT32_IRQ_USART1_PRIORITY 12 +#define AT32_IRQ_USART2_PRIORITY 12 +#define AT32_IRQ_USART3_PRIORITY 12 +#define AT32_IRQ_UART4_PRIORITY 12 +#define AT32_IRQ_UART5_PRIORITY 12 +#define AT32_IRQ_USART6_PRIORITY 12 +#define AT32_IRQ_UART7_PRIORITY 12 +#define AT32_IRQ_UART8_PRIORITY 12 + +/* + * ADC driver system settings. + */ +#define AT32_ADC_USE_ADC1 FALSE +#define AT32_ADC_ADC1_DMA_PRIORITY 2 +#define AT32_ADC_IRQ_PRIORITY 6 +#define AT32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define AT32_ADC_ADCDIV 8 + +/* + * CAN driver system settings. + */ +#define AT32_CAN_USE_CAN1 FALSE +#define AT32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * GPT driver system settings. + */ +#define AT32_GPT_USE_TMR1 FALSE +#define AT32_GPT_USE_TMR2 FALSE +#define AT32_GPT_USE_TMR3 FALSE +#define AT32_GPT_USE_TMR4 FALSE +#define AT32_GPT_USE_TMR6 FALSE +#define AT32_GPT_USE_TMR7 FALSE +#define AT32_GPT_USE_TMR9 FALSE +#define AT32_GPT_USE_TMR10 FALSE +#define AT32_GPT_USE_TMR11 FALSE +#define AT32_GPT_USE_TMR13 FALSE +#define AT32_GPT_USE_TMR14 FALSE + +/* + * I2C driver system settings. + */ +#define AT32_I2C_USE_I2C1 TRUE +#define AT32_I2C_USE_I2C2 FALSE +#define AT32_I2C_USE_I2C3 FALSE +#define AT32_I2C_BUSY_TIMEOUT 50 +#define AT32_I2C_I2C1_DMA_PRIORITY 3 +#define AT32_I2C_I2C2_DMA_PRIORITY 3 +#define AT32_I2C_I2C3_DMA_PRIORITY 3 +#define AT32_I2C_I2C1_IRQ_PRIORITY 5 +#define AT32_I2C_I2C2_IRQ_PRIORITY 5 +#define AT32_I2C_I2C3_IRQ_PRIORITY 5 +#define AT32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define AT32_ICU_USE_TMR1 FALSE +#define AT32_ICU_USE_TMR2 FALSE +#define AT32_ICU_USE_TMR3 FALSE +#define AT32_ICU_USE_TMR4 FALSE +#define AT32_ICU_USE_TMR9 FALSE + +/* + * PWM driver system settings. + */ +#define AT32_PWM_USE_TMR1 FALSE +#define AT32_PWM_USE_TMR2 FALSE +#define AT32_PWM_USE_TMR3 FALSE +#define AT32_PWM_USE_TMR4 FALSE +#define AT32_PWM_USE_TMR9 FALSE +#define AT32_PWM_USE_TMR10 FALSE +#define AT32_PWM_USE_TMR11 FALSE +#define AT32_PWM_USE_TMR13 FALSE +#define AT32_PWM_USE_TMR14 FALSE + +/* + * RTC driver system settings. + */ +#define AT32_ERTC_DIVA_VALUE 32 +#define AT32_ERTC_DIVB_VALUE 1024 +#define AT32_ERTC_CTRL_INIT 0 +#define AT32_ERTC_TAMP_INIT 0 + +/* + * SERIAL driver system settings. + */ +#define AT32_SERIAL_USE_USART1 FALSE +#define AT32_SERIAL_USE_USART2 FALSE +#define AT32_SERIAL_USE_USART3 FALSE +#define AT32_SERIAL_USE_UART4 FALSE +#define AT32_SERIAL_USE_UART5 FALSE +#define AT32_SERIAL_USE_USART6 FALSE +#define AT32_SERIAL_USE_UART7 FALSE +#define AT32_SERIAL_USE_UART8 FALSE + +/* + * SIO driver system settings. + */ +#define AT32_SIO_USE_USART1 FALSE +#define AT32_SIO_USE_USART2 FALSE +#define AT32_SIO_USE_USART3 FALSE +#define AT32_SIO_USE_UART4 FALSE +#define AT32_SIO_USE_UART5 FALSE +#define AT32_SIO_USE_USART6 FALSE +#define AT32_SIO_USE_UART7 FALSE +#define AT32_SIO_USE_UART8 FALSE + +/* + * SPI driver system settings. + */ +#define AT32_SPI_USE_SPI1 FALSE +#define AT32_SPI_USE_SPI2 FALSE +#define AT32_SPI_USE_SPI3 FALSE +#define AT32_SPI_SPI1_DMA_PRIORITY 1 +#define AT32_SPI_SPI2_DMA_PRIORITY 1 +#define AT32_SPI_SPI3_DMA_PRIORITY 1 +#define AT32_SPI_SPI1_IRQ_PRIORITY 10 +#define AT32_SPI_SPI2_IRQ_PRIORITY 10 +#define AT32_SPI_SPI3_IRQ_PRIORITY 10 +#define AT32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define AT32_ST_IRQ_PRIORITY 8 +#define AT32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define AT32_UART_USE_USART1 FALSE +#define AT32_UART_USE_USART2 FALSE +#define AT32_UART_USE_USART3 FALSE +#define AT32_UART_USE_UART4 FALSE +#define AT32_UART_USE_UART5 FALSE +#define AT32_UART_USE_USART6 FALSE +#define AT32_UART_USE_UART7 FALSE +#define AT32_UART_USE_UART8 FALSE +#define AT32_UART_USART1_DMA_PRIORITY 0 +#define AT32_UART_USART2_DMA_PRIORITY 0 +#define AT32_UART_USART3_DMA_PRIORITY 0 +#define AT32_UART_UART4_DMA_PRIORITY 0 +#define AT32_UART_UART5_DMA_PRIORITY 0 +#define AT32_UART_USART6_DMA_PRIORITY 0 +#define AT32_UART_UART7_DMA_PRIORITY 0 +#define AT32_UART_UART8_DMA_PRIORITY 0 +#define AT32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define AT32_USB_USE_OTG1 FALSE +#define AT32_USB_USE_OTG2 FALSE +#define AT32_USB_OTG1_IRQ_PRIORITY 14 +#define AT32_USB_OTG2_IRQ_PRIORITY 14 +#define AT32_USB_OTG1_RX_FIFO_SIZE 512 +#define AT32_USB_OTG2_RX_FIFO_SIZE 1024 +#define AT32_USE_USB_OTG2_HS_DMA FALSE + +/* + * WDG driver system settings. + */ +#define AT32_WDG_USE_WDT FALSE + +#include "config.h" + +#endif /* MCUCONF_H */ diff --git a/testhal/AT32/multi/I2C_HW/cfg/at-start-f405/portab.c b/testhal/AT32/multi/I2C_HW/cfg/at-start-f405/portab.c new file mode 100644 index 0000000000..95d45183f7 --- /dev/null +++ b/testhal/AT32/multi/I2C_HW/cfg/at-start-f405/portab.c @@ -0,0 +1,71 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file portab.c + * @brief Application portability module code. + * + * @addtogroup application_portability + * @{ + */ + +#include "hal.h" + +#include "portab.h" + +/*===========================================================================*/ +/* Module local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module exported variables. */ +/*===========================================================================*/ + +/* + * I2C driver configuration structure. + */ +I2CConfig i2ccfg = { + AT32_CLKCTRL_DIV(9U) | + AT32_CLKCTRL_SCLD(14U) | AT32_CLKCTRL_SDAD(0U) | + AT32_CLKCTRL_SCLH(49U) | AT32_CLKCTRL_SCLL(49U), + 0, + 0 +}; + +/*===========================================================================*/ +/* Module local types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module exported functions. */ +/*===========================================================================*/ + +void portab_setup(void) { + palSetLineMode(PAL_LINE(GPIOB, 6U), PAL_MODE_MUX(4) | PAL_AT32_OMODE_OPENDRAIN); + palSetLineMode(PAL_LINE(GPIOB, 7U), PAL_MODE_MUX(4) | PAL_AT32_OMODE_OPENDRAIN); +} + +/** @} */ diff --git a/testhal/AT32/multi/I2C_HW/cfg/at-start-f405/portab.h b/testhal/AT32/multi/I2C_HW/cfg/at-start-f405/portab.h new file mode 100644 index 0000000000..c714e7e8f1 --- /dev/null +++ b/testhal/AT32/multi/I2C_HW/cfg/at-start-f405/portab.h @@ -0,0 +1,78 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file portab.h + * @brief Application portability macros and structures. + * + * @addtogroup application_portability + * @{ + */ + +#ifndef PORTAB_H +#define PORTAB_H + +/*===========================================================================*/ +/* Module constants. */ +/*===========================================================================*/ + +#define PORTAB_I2C1 I2CD1 + +#define PORTAB_BLINK_LED1 LINE_LED_RED + +#define PORTAB_BLINK_LED2 LINE_LED_YELLOW + +#define PORTAB_BLINK_LED3 LINE_LED_GREEN + +/*===========================================================================*/ +/* Module pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +extern I2CConfig i2ccfg; + +#ifdef __cplusplus +extern "C" { +#endif + void portab_setup(void); +#ifdef __cplusplus +} +#endif + +/*===========================================================================*/ +/* Module inline functions. */ +/*===========================================================================*/ + +#endif /* PORTAB_H */ + +/** @} */ diff --git a/testhal/AT32/multi/I2C_HW/cfg/at-start-f415/chconf.h b/testhal/AT32/multi/I2C_HW/cfg/at-start-f415/chconf.h index 46b3f78b68..56fe06776a 100644 --- a/testhal/AT32/multi/I2C_HW/cfg/at-start-f415/chconf.h +++ b/testhal/AT32/multi/I2C_HW/cfg/at-start-f415/chconf.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/testhal/AT32/multi/I2C_HW/cfg/at-start-f415/config.h b/testhal/AT32/multi/I2C_HW/cfg/at-start-f415/config.h index 361e185d9c..056a8f39ff 100644 --- a/testhal/AT32/multi/I2C_HW/cfg/at-start-f415/config.h +++ b/testhal/AT32/multi/I2C_HW/cfg/at-start-f415/config.h @@ -1,6 +1,6 @@ /* - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/testhal/AT32/multi/I2C_HW/cfg/at-start-f415/halconf.h b/testhal/AT32/multi/I2C_HW/cfg/at-start-f415/halconf.h index 7aff43b894..f1bf5fd204 100644 --- a/testhal/AT32/multi/I2C_HW/cfg/at-start-f415/halconf.h +++ b/testhal/AT32/multi/I2C_HW/cfg/at-start-f415/halconf.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/testhal/AT32/multi/I2C_HW/cfg/at-start-f415/halconf_community.h b/testhal/AT32/multi/I2C_HW/cfg/at-start-f415/halconf_community.h index c43d668764..5a77290c71 100644 --- a/testhal/AT32/multi/I2C_HW/cfg/at-start-f415/halconf_community.h +++ b/testhal/AT32/multi/I2C_HW/cfg/at-start-f415/halconf_community.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/testhal/AT32/multi/I2C_HW/cfg/at-start-f415/mcuconf.h b/testhal/AT32/multi/I2C_HW/cfg/at-start-f415/mcuconf.h index 208ae769ef..1e76232a99 100644 --- a/testhal/AT32/multi/I2C_HW/cfg/at-start-f415/mcuconf.h +++ b/testhal/AT32/multi/I2C_HW/cfg/at-start-f415/mcuconf.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -106,6 +106,7 @@ #define AT32_ADC_USE_ADC1 FALSE #define AT32_ADC_ADC1_DMA_PRIORITY 2 #define AT32_ADC_ADC1_IRQ_PRIORITY 6 +#define AT32_ADC_ADC1_DMA_IRQ_PRIORITY 6 /* * CAN driver system settings. diff --git a/testhal/AT32/multi/I2C_HW/cfg/at-start-f415/portab.c b/testhal/AT32/multi/I2C_HW/cfg/at-start-f415/portab.c index d175de5b7a..ac59375175 100644 --- a/testhal/AT32/multi/I2C_HW/cfg/at-start-f415/portab.c +++ b/testhal/AT32/multi/I2C_HW/cfg/at-start-f415/portab.c @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/testhal/AT32/multi/I2C_HW/cfg/at-start-f415/portab.h b/testhal/AT32/multi/I2C_HW/cfg/at-start-f415/portab.h index d01a8c4c5c..c714e7e8f1 100644 --- a/testhal/AT32/multi/I2C_HW/cfg/at-start-f415/portab.h +++ b/testhal/AT32/multi/I2C_HW/cfg/at-start-f415/portab.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/testhal/AT32/multi/I2C_HW/main.c b/testhal/AT32/multi/I2C_HW/main.c index 365894bed0..9e741b0ce0 100644 --- a/testhal/AT32/multi/I2C_HW/main.c +++ b/testhal/AT32/multi/I2C_HW/main.c @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/testhal/AT32/multi/I2C_HW/make/at-start-f402.make b/testhal/AT32/multi/I2C_HW/make/at-start-f402.make new file mode 100644 index 0000000000..c2d5988d83 --- /dev/null +++ b/testhal/AT32/multi/I2C_HW/make/at-start-f402.make @@ -0,0 +1,196 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO). +ifeq ($(USE_LTO),) + USE_LTO = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# Enable this if you want to use bitbang I2C. +ifeq ($(USE_HAL_I2C_FALLBACK),) + USE_HAL_I2C_FALLBACK = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x400 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU (no, softfp, hard). +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# FPU-related options. +ifeq ($(USE_FPU_OPT),) + USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16 +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, target, sources and paths +# + +# Define project name here +PROJECT = ch + +# Target settings. +MCU = cortex-m4 + +# Imported source files and paths. +CHIBIOS := ../../../../../ChibiOS +CHIBIOS_CONTRIB := ../../../.. +CONFDIR := ./cfg/at-start-f402 +BUILDDIR := ./build/at-start-f402 +DEPDIR := ./.dep/at-start-f402 + +# Licensing files. +include $(CHIBIOS)/os/license/license.mk +# Startup files. +include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_at32f402.mk +# HAL-OSAL files (optional). +include $(CHIBIOS_CONTRIB)/os/hal/hal.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/AT32F402_405/platform.mk +include $(CHIBIOS_CONTRIB)/os/hal/boards/AT_START_F402/board.mk +include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMv7-M/compilers/GCC/mk/port.mk +# Auto-build files in ./source recursively. +include $(CHIBIOS)/tools/mk/autobuild.mk +# Other files (optional). +#include $(CHIBIOS)/os/test/test.mk +#include $(CHIBIOS)/test/rt/rt_test.mk +#include $(CHIBIOS)/test/oslib/oslib_test.mk + +# Define linker script file here. +LDSCRIPT= $(STARTUPLD_CONTRIB)/AT32F402xC.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(ALLCSRC) \ + $(TESTSRC) \ + $(CONFDIR)/portab.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = $(ALLCPPSRC) + +# List ASM source files here. +ASMSRC = $(ALLASMSRC) + +# List ASM with preprocessor source files here. +ASMXSRC = $(ALLXASMSRC) + +# Inclusion directories. +INCDIR = $(CONFDIR) $(ALLINC) + +# Define C warning options here. +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes + +# Define C++ warning options here. +CPPWARN = -Wall -Wextra -Wundef + +# +# Project, target, sources and paths +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user section +############################################################################## + +############################################################################## +# Common rules +# + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk +include $(RULESPATH)/arm-none-eabi.mk +include $(RULESPATH)/rules.mk + +# +# Common rules +############################################################################## + +############################################################################## +# Custom rules +# + +# +# Custom rules +############################################################################## diff --git a/testhal/AT32/multi/I2C_HW/make/at-start-f405.make b/testhal/AT32/multi/I2C_HW/make/at-start-f405.make new file mode 100644 index 0000000000..d3cc3ac36c --- /dev/null +++ b/testhal/AT32/multi/I2C_HW/make/at-start-f405.make @@ -0,0 +1,196 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO). +ifeq ($(USE_LTO),) + USE_LTO = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# Enable this if you want to use bitbang I2C. +ifeq ($(USE_HAL_I2C_FALLBACK),) + USE_HAL_I2C_FALLBACK = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x400 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU (no, softfp, hard). +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# FPU-related options. +ifeq ($(USE_FPU_OPT),) + USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16 +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, target, sources and paths +# + +# Define project name here +PROJECT = ch + +# Target settings. +MCU = cortex-m4 + +# Imported source files and paths. +CHIBIOS := ../../../../../ChibiOS +CHIBIOS_CONTRIB := ../../../.. +CONFDIR := ./cfg/at-start-f405 +BUILDDIR := ./build/at-start-f405 +DEPDIR := ./.dep/at-start-f405 + +# Licensing files. +include $(CHIBIOS)/os/license/license.mk +# Startup files. +include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_at32f405.mk +# HAL-OSAL files (optional). +include $(CHIBIOS_CONTRIB)/os/hal/hal.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/AT32F402_405/platform.mk +include $(CHIBIOS_CONTRIB)/os/hal/boards/AT_START_F405/board.mk +include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMv7-M/compilers/GCC/mk/port.mk +# Auto-build files in ./source recursively. +include $(CHIBIOS)/tools/mk/autobuild.mk +# Other files (optional). +#include $(CHIBIOS)/os/test/test.mk +#include $(CHIBIOS)/test/rt/rt_test.mk +#include $(CHIBIOS)/test/oslib/oslib_test.mk + +# Define linker script file here. +LDSCRIPT= $(STARTUPLD_CONTRIB)/AT32F405xC.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(ALLCSRC) \ + $(TESTSRC) \ + $(CONFDIR)/portab.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = $(ALLCPPSRC) + +# List ASM source files here. +ASMSRC = $(ALLASMSRC) + +# List ASM with preprocessor source files here. +ASMXSRC = $(ALLXASMSRC) + +# Inclusion directories. +INCDIR = $(CONFDIR) $(ALLINC) + +# Define C warning options here. +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes + +# Define C++ warning options here. +CPPWARN = -Wall -Wextra -Wundef + +# +# Project, target, sources and paths +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user section +############################################################################## + +############################################################################## +# Common rules +# + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk +include $(RULESPATH)/arm-none-eabi.mk +include $(RULESPATH)/rules.mk + +# +# Common rules +############################################################################## + +############################################################################## +# Custom rules +# + +# +# Custom rules +############################################################################## diff --git a/testhal/AT32/multi/I2C_SW/Makefile b/testhal/AT32/multi/I2C_SW/Makefile index c8606df05e..fdf3019a85 100644 --- a/testhal/AT32/multi/I2C_SW/Makefile +++ b/testhal/AT32/multi/I2C_SW/Makefile @@ -3,6 +3,14 @@ # all: + @echo + @echo === Building for AT-START-F402 ===================================== + +@make --no-print-directory -f ./make/at-start-f402.make all + @echo ==================================================================== + @echo + @echo === Building for AT-START-F405 ===================================== + +@make --no-print-directory -f ./make/at-start-f405.make all + @echo ==================================================================== @echo @echo === Building for AT-START-F415 ===================================== +@make --no-print-directory -f ./make/at-start-f415.make all @@ -10,6 +18,10 @@ all: @echo clean: + @echo + +@make --no-print-directory -f ./make/at-start-f402.make clean + @echo + +@make --no-print-directory -f ./make/at-start-f405.make clean @echo +@make --no-print-directory -f ./make/at-start-f415.make clean @echo diff --git a/testhal/AT32/multi/I2C_SW/cfg/at-start-f402/chconf.h b/testhal/AT32/multi/I2C_SW/cfg/at-start-f402/chconf.h new file mode 100644 index 0000000000..5988b2b4b9 --- /dev/null +++ b/testhal/AT32/multi/I2C_SW/cfg/at-start-f402/chconf.h @@ -0,0 +1,842 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_7_0_ + +/*===========================================================================*/ +/** + * @name System settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Handling of instances. + * @note If enabled then threads assigned to various instances can + * interact each other using the same synchronization objects. + * If disabled then each OS instance is a separate world, no + * direct interactions are handled by the OS. + */ +#if !defined(CH_CFG_SMP_MODE) +#define CH_CFG_SMP_MODE FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_ST_RESOLUTION) +#define CH_CFG_ST_RESOLUTION 32 +#endif + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_CFG_ST_FREQUENCY) +#define CH_CFG_ST_FREQUENCY 100000 +#endif + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_INTERVALS_SIZE) +#define CH_CFG_INTERVALS_SIZE 32 +#endif + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_TIME_TYPES_SIZE) +#define CH_CFG_TIME_TYPES_SIZE 32 +#endif + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#if !defined(CH_CFG_ST_TIMEDELTA) +#define CH_CFG_ST_TIMEDELTA 2 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#if !defined(CH_CFG_TIME_QUANTUM) +#define CH_CFG_TIME_QUANTUM 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#if !defined(CH_CFG_NO_IDLE_THREAD) +#define CH_CFG_NO_IDLE_THREAD FALSE +#endif + +/** + * @brief Kernel hardening level. + * @details This option is the level of functional-safety checks enabled + * in the kerkel. The meaning is: + * - 0: No checks, maximum performance. + * - 1: Reasonable checks. + * - 2: All checks. + * . + */ +#if !defined(CH_CFG_HARDENING_LEVEL) +#define CH_CFG_HARDENING_LEVEL 0 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_OPTIMIZE_SPEED) +#define CH_CFG_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TM) +#define CH_CFG_USE_TM TRUE +#endif + +/** + * @brief Time Stamps APIs. + * @details If enabled then the time stamps APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TIMESTAMP) +#define CH_CFG_USE_TIMESTAMP TRUE +#endif + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_REGISTRY) +#define CH_CFG_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_WAITEXIT) +#define CH_CFG_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_SEMAPHORES) +#define CH_CFG_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MUTEXES) +#define CH_CFG_USE_MUTEXES TRUE +#endif + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_CONDVARS) +#define CH_CFG_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_EVENTS) +#define CH_CFG_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MESSAGES) +#define CH_CFG_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#if !defined(CH_CFG_USE_DYNAMIC) +#define CH_CFG_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name OSLIB options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_MAILBOXES) +#define CH_CFG_USE_MAILBOXES TRUE +#endif + +/** + * @brief Memory checks APIs. + * @details If enabled then the memory checks APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCHECKS) +#define CH_CFG_USE_MEMCHECKS TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCORE) +#define CH_CFG_USE_MEMCORE TRUE +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#if !defined(CH_CFG_MEMCORE_SIZE) +#define CH_CFG_MEMCORE_SIZE 0 +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_CFG_USE_HEAP) +#define CH_CFG_USE_HEAP TRUE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMPOOLS) +#define CH_CFG_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_FIFOS) +#define CH_CFG_USE_OBJ_FIFOS TRUE +#endif + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Objects Caches APIs. + * @details If enabled then the objects caches APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_CACHES) +#define CH_CFG_USE_OBJ_CACHES TRUE +#endif + +/** + * @brief Delegate threads APIs. + * @details If enabled then the delegate threads APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_DELEGATES) +#define CH_CFG_USE_DELEGATES TRUE +#endif + +/** + * @brief Jobs Queues APIs. + * @details If enabled then the jobs queues APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_JOBS) +#define CH_CFG_USE_JOBS TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_CFG_USE_FACTORY) +#define CH_CFG_USE_FACTORY TRUE +#endif + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 +#endif + +/** + * @brief Enables the registry of generic objects. + */ +#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE +#endif + +/** + * @brief Enables factory for generic buffers. + */ +#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE +#endif + +/** + * @brief Enables factory for semaphores. + */ +#if !defined(CH_CFG_FACTORY_SEMAPHORES) +#define CH_CFG_FACTORY_SEMAPHORES TRUE +#endif + +/** + * @brief Enables factory for mailboxes. + */ +#if !defined(CH_CFG_FACTORY_MAILBOXES) +#define CH_CFG_FACTORY_MAILBOXES TRUE +#endif + +/** + * @brief Enables factory for objects FIFOs. + */ +#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE +#endif + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_STATISTICS) +#define CH_DBG_STATISTICS FALSE +#endif + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_MASK) +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_ALL +#endif + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_BUFFER_SIZE) +#define CH_DBG_TRACE_BUFFER_SIZE 128 +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#if !defined(CH_DBG_THREADS_PROFILING) +#define CH_DBG_THREADS_PROFILING FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add system custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add system initialization code here.*/ \ +} + +/** + * @brief OS instance structure extension. + * @details User fields added to the end of the @p os_instance_t structure. + */ +#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS \ + /* Add OS instance custom fields here.*/ + +/** + * @brief OS instance initialization hook. + * + * @param[in] oip pointer to the @p os_instance_t structure + */ +#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) { \ + /* Add OS instance initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + * + * @param[in] ntp thread being switched in + * @param[in] otp thread being switched out + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** + * @brief Runtime Faults Collection Unit hook. + * @details This hook is invoked each time new faults are collected and stored. + */ +#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) { \ + /* Faults handling code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/testhal/AT32/multi/I2C_SW/cfg/at-start-f402/config.h b/testhal/AT32/multi/I2C_SW/cfg/at-start-f402/config.h new file mode 100644 index 0000000000..109de45450 --- /dev/null +++ b/testhal/AT32/multi/I2C_SW/cfg/at-start-f402/config.h @@ -0,0 +1,39 @@ +/* + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * CRC driver system settings. + */ +#define AT32_CRC_USE_CRC1 FALSE + +#define CRC_USE_DMA FALSE +#define AT32_CRC_CRC1_DMA_PRIORITY 2 +#define AT32_CRC_CRC1_IRQ_PRIORITY 5 +#define AT32_CRC_CRC1_DMA_STREAM AT32_DMA_STREAM_ID_ANY + +/* + * I2C fallback driver system settings. + */ +#define SW_I2C_USE_I2C1 TRUE +#define SW_I2C_USE_I2C2 FALSE +#define SW_I2C_USE_I2C3 FALSE +#define SW_I2C_USE_I2C4 FALSE + +/* + * Other settings. + */ +#define BOARD_OTG_VBUSIG diff --git a/testhal/AT32/multi/I2C_SW/cfg/at-start-f402/halconf.h b/testhal/AT32/multi/I2C_SW/cfg/at-start-f402/halconf.h new file mode 100644 index 0000000000..f1bf5fd204 --- /dev/null +++ b/testhal/AT32/multi/I2C_SW/cfg/at-start-f402/halconf.h @@ -0,0 +1,557 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_8_4_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the EFlash subsystem. + */ +#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__) +#define HAL_USE_EFL FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C TRUE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/** + * @brief Enables the WSPI subsystem. + */ +#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) +#define HAL_USE_WSPI FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS FALSE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS FALSE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Timeout before assuming a failure while waiting for card idle. + * @note Time is in milliseconds. + */ +#if !defined(MMC_IDLE_TIMEOUT_MS) || defined(__DOXYGEN__) +#define MMC_IDLE_TIMEOUT_MS 1000 +#endif + +/** + * @brief Mutual exclusion on the SPI bus. + */ +#if !defined(MMC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define MMC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SIO driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SIO_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SIO_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Support for thread synchronization API. + */ +#if !defined(SIO_USE_SYNCHRONIZATION) || defined(__DOXYGEN__) +#define SIO_USE_SYNCHRONIZATION TRUE +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 256 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 2 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Inserts an assertion on function errors before returning. + */ +#if !defined(SPI_USE_ASSERT_ON_ERROR) || defined(__DOXYGEN__) +#define SPI_USE_ASSERT_ON_ERROR TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#include "halconf_community.h" + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/testhal/AT32/multi/I2C_SW/cfg/at-start-f402/halconf_community.h b/testhal/AT32/multi/I2C_SW/cfg/at-start-f402/halconf_community.h new file mode 100644 index 0000000000..5a77290c71 --- /dev/null +++ b/testhal/AT32/multi/I2C_SW/cfg/at-start-f402/halconf_community.h @@ -0,0 +1,182 @@ +/* + ChibiOS - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef HALCONF_COMMUNITY_H +#define HALCONF_COMMUNITY_H + +/** + * @brief Enables the community overlay. + */ +#if !defined(HAL_USE_COMMUNITY) || defined(__DOXYGEN__) +#define HAL_USE_COMMUNITY TRUE +#endif + +/** + * @brief Enables the FSMC subsystem. + */ +#if !defined(HAL_USE_FSMC) || defined(__DOXYGEN__) +#define HAL_USE_FSMC FALSE +#endif + +/** + * @brief Enables the NAND subsystem. + */ +#if !defined(HAL_USE_NAND) || defined(__DOXYGEN__) +#define HAL_USE_NAND FALSE +#endif + +/** + * @brief Enables the 1-wire subsystem. + */ +#if !defined(HAL_USE_ONEWIRE) || defined(__DOXYGEN__) +#define HAL_USE_ONEWIRE FALSE +#endif + +/** + * @brief Enables the EICU subsystem. + */ +#if !defined(HAL_USE_EICU) || defined(__DOXYGEN__) +#define HAL_USE_EICU FALSE +#endif + +/** + * @brief Enables the CRC subsystem. + */ +#if !defined(HAL_USE_CRC) || defined(__DOXYGEN__) +#define HAL_USE_CRC FALSE +#endif + +/** + * @brief Enables the RNG subsystem. + */ +#if !defined(HAL_USE_RNG) || defined(__DOXYGEN__) +#define HAL_USE_RNG FALSE +#endif + +/** + * @brief Enables the EEPROM subsystem. + */ +#if !defined(HAL_USE_EEPROM) || defined(__DOXYGEN__) +#define HAL_USE_EEPROM FALSE +#endif + +/** + * @brief Enables the TIMCAP subsystem. + */ +#if !defined(HAL_USE_TIMCAP) || defined(__DOXYGEN__) +#define HAL_USE_TIMCAP FALSE +#endif + +/** + * @brief Enables the COMP subsystem. + */ +#if !defined(HAL_USE_COMP) || defined(__DOXYGEN__) +#define HAL_USE_COMP FALSE +#endif + +/** + * @brief Enables the OPAMP subsystem. + */ +#if !defined(HAL_USE_OPAMP) || defined(__DOXYGEN__) +#define HAL_USE_OPAMP FALSE +#endif + +/** + * @brief Enables the QEI subsystem. + */ +#if !defined(HAL_USE_QEI) || defined(__DOXYGEN__) +#define HAL_USE_QEI FALSE +#endif + +/** + * @brief Enables the USBH subsystem. + */ +#if !defined(HAL_USE_USBH) || defined(__DOXYGEN__) +#define HAL_USE_USBH FALSE +#endif + +/** + * @brief Enables the USB_MSD subsystem. + */ +#if !defined(HAL_USE_USB_MSD) || defined(__DOXYGEN__) +#define HAL_USE_USB_MSD FALSE +#endif + +/*===========================================================================*/ +/* FSMCNAND driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the @p nandAcquireBus() and @p nanReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(NAND_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define NAND_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* 1-wire driver related settings. */ +/*===========================================================================*/ +/** + * @brief Enables strong pull up feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_STRONG_PULLUP FALSE + +/** + * @brief Enables search ROM feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_SEARCH_ROM TRUE + +/*===========================================================================*/ +/* QEI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables discard of overlow + */ +#if !defined(QEI_USE_OVERFLOW_DISCARD) || defined(__DOXYGEN__) +#define QEI_USE_OVERFLOW_DISCARD FALSE +#endif + +/** + * @brief Enables min max of overlow + */ +#if !defined(QEI_USE_OVERFLOW_MINMAX) || defined(__DOXYGEN__) +#define QEI_USE_OVERFLOW_MINMAX FALSE +#endif + +/*===========================================================================*/ +/* EEProm driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables 24xx series I2C eeprom device driver. + * @note Disabling this option saves both code and data space. + */ +#define EEPROM_USE_EE24XX FALSE + /** + * @brief Enables 25xx series SPI eeprom device driver. + * @note Disabling this option saves both code and data space. + */ +#define EEPROM_USE_EE25XX FALSE + +#endif /* HALCONF_COMMUNITY_H */ + +/** @} */ diff --git a/testhal/AT32/multi/I2C_SW/cfg/at-start-f402/mcuconf.h b/testhal/AT32/multi/I2C_SW/cfg/at-start-f402/mcuconf.h new file mode 100644 index 0000000000..09806daf4b --- /dev/null +++ b/testhal/AT32/multi/I2C_SW/cfg/at-start-f402/mcuconf.h @@ -0,0 +1,268 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef MCUCONF_H +#define MCUCONF_H + +/* + * AT32F402 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define AT32F402_MCUCONF + +/* + * General settings. + */ +#define AT32_NO_INIT FALSE + +/* + * HAL driver system settings. + */ +#define AT32_HICK_ENABLED TRUE +#define AT32_LICK_ENABLED FALSE +#define AT32_HEXT_ENABLED TRUE +#define AT32_LEXT_ENABLED FALSE +#define AT32_PLLU_ENABLED TRUE +#define AT32_SCLKSEL AT32_SCLKSEL_PLL +#define AT32_PLLRCS AT32_PLLRCS_HEXT +#define AT32_PLL_MS_VALUE 1 +#define AT32_PLL_NS_VALUE 72 +#define AT32_PLL_FP_VALUE 4 +#define AT32_PLL_FU_VALUE 18 +#define AT32_AHBDIV AT32_AHBDIV_DIV1 +#define AT32_APB1DIV AT32_APB1DIV_DIV2 +#define AT32_APB2DIV AT32_APB2DIV_DIV1 +#define AT32_HICK_TO_SCLK AT32_HICK_TO_SCLK_48M +#define AT32_HICKDIV AT32_HICKDIV_DIV1 +#define AT32_HICK_TO_SCLK_DIV AT32_HICK_TO_SCLK_DIV_DIV1 +#define AT32_HEXT_TO_SCLK_DIV AT32_HEXT_TO_SCLK_DIV_DIV1 +#define AT32_USB_CLOCK48_REQUIRED TRUE +#define AT32_PLLU_USB48_SEL AT32_PLLU_USB48_SEL_PLLU +#define AT32_CLKOUT_SEL AT32_CLKOUT_SEL_HICK +#define AT32_CLKOUTDIV1 AT32_CLKOUTDIV1_DIV1 +#define AT32_CLKOUTDIV2 AT32_CLKOUTDIV2_DIV1 +#define AT32_ERTCSEL AT32_ERTCSEL_NOCLOCK +#define AT32_ERTCDIV_VALUE 12 +#define AT32_I2SF5CLKSEL AT32_I2SF5CLKSEL_SCLK +#define AT32_PVM_ENABLE FALSE +#define AT32_PVMSEL AT32_PVMSEL_LEV1 +#define AT32_LDOOVSEL AT32_LDOOVSEL_LEV3 + +/* + * IRQ system settings. + */ +#define AT32_IRQ_EXINT0_PRIORITY 6 +#define AT32_IRQ_EXINT1_PRIORITY 6 +#define AT32_IRQ_EXINT2_PRIORITY 6 +#define AT32_IRQ_EXINT3_PRIORITY 6 +#define AT32_IRQ_EXINT4_PRIORITY 6 +#define AT32_IRQ_EXINT5_9_PRIORITY 6 +#define AT32_IRQ_EXINT10_15_PRIORITY 6 +#define AT32_IRQ_EXINT16_PRIORITY 6 +#define AT32_IRQ_EXINT17_PRIORITY 15 +#define AT32_IRQ_EXINT18_PRIORITY 6 +#define AT32_IRQ_EXINT20_PRIORITY 6 +#define AT32_IRQ_EXINT21_PRIORITY 15 +#define AT32_IRQ_EXINT22_PRIORITY 15 + +#define AT32_IRQ_TMR1_BRK_TMR9_PRIORITY 7 +#define AT32_IRQ_TMR1_OVF_TMR10_PRIORITY 7 +#define AT32_IRQ_TMR1_HALL_TMR11_PRIORITY 7 +#define AT32_IRQ_TMR1_CH_PRIORITY 7 +#define AT32_IRQ_TMR2_PRIORITY 7 +#define AT32_IRQ_TMR3_PRIORITY 7 +#define AT32_IRQ_TMR4_PRIORITY 7 +#define AT32_IRQ_TMR6_PRIORITY 7 +#define AT32_IRQ_TMR7_PRIORITY 7 +#define AT32_IRQ_TMR13_PRIORITY 7 +#define AT32_IRQ_TMR14_PRIORITY 7 + +#define AT32_IRQ_USART1_PRIORITY 12 +#define AT32_IRQ_USART2_PRIORITY 12 +#define AT32_IRQ_USART3_PRIORITY 12 +#define AT32_IRQ_UART4_PRIORITY 12 +#define AT32_IRQ_UART5_PRIORITY 12 +#define AT32_IRQ_USART6_PRIORITY 12 +#define AT32_IRQ_UART7_PRIORITY 12 +#define AT32_IRQ_UART8_PRIORITY 12 + +/* + * ADC driver system settings. + */ +#define AT32_ADC_USE_ADC1 FALSE +#define AT32_ADC_ADC1_DMA_PRIORITY 2 +#define AT32_ADC_IRQ_PRIORITY 6 +#define AT32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define AT32_ADC_ADCDIV 8 + +/* + * CAN driver system settings. + */ +#define AT32_CAN_USE_CAN1 FALSE +#define AT32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * GPT driver system settings. + */ +#define AT32_GPT_USE_TMR1 FALSE +#define AT32_GPT_USE_TMR2 FALSE +#define AT32_GPT_USE_TMR3 FALSE +#define AT32_GPT_USE_TMR4 FALSE +#define AT32_GPT_USE_TMR6 FALSE +#define AT32_GPT_USE_TMR7 FALSE +#define AT32_GPT_USE_TMR9 FALSE +#define AT32_GPT_USE_TMR10 FALSE +#define AT32_GPT_USE_TMR11 FALSE +#define AT32_GPT_USE_TMR13 FALSE +#define AT32_GPT_USE_TMR14 FALSE + +/* + * I2C driver system settings. + */ +#define AT32_I2C_USE_I2C1 FALSE +#define AT32_I2C_USE_I2C2 FALSE +#define AT32_I2C_USE_I2C3 FALSE +#define AT32_I2C_BUSY_TIMEOUT 50 +#define AT32_I2C_I2C1_DMA_PRIORITY 3 +#define AT32_I2C_I2C2_DMA_PRIORITY 3 +#define AT32_I2C_I2C3_DMA_PRIORITY 3 +#define AT32_I2C_I2C1_IRQ_PRIORITY 5 +#define AT32_I2C_I2C2_IRQ_PRIORITY 5 +#define AT32_I2C_I2C3_IRQ_PRIORITY 5 +#define AT32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define AT32_ICU_USE_TMR1 FALSE +#define AT32_ICU_USE_TMR2 FALSE +#define AT32_ICU_USE_TMR3 FALSE +#define AT32_ICU_USE_TMR4 FALSE +#define AT32_ICU_USE_TMR9 FALSE + +/* + * PWM driver system settings. + */ +#define AT32_PWM_USE_TMR1 FALSE +#define AT32_PWM_USE_TMR2 FALSE +#define AT32_PWM_USE_TMR3 FALSE +#define AT32_PWM_USE_TMR4 FALSE +#define AT32_PWM_USE_TMR9 FALSE +#define AT32_PWM_USE_TMR10 FALSE +#define AT32_PWM_USE_TMR11 FALSE +#define AT32_PWM_USE_TMR13 FALSE +#define AT32_PWM_USE_TMR14 FALSE + +/* + * RTC driver system settings. + */ +#define AT32_ERTC_DIVA_VALUE 32 +#define AT32_ERTC_DIVB_VALUE 1024 +#define AT32_ERTC_CTRL_INIT 0 +#define AT32_ERTC_TAMP_INIT 0 + +/* + * SERIAL driver system settings. + */ +#define AT32_SERIAL_USE_USART1 FALSE +#define AT32_SERIAL_USE_USART2 FALSE +#define AT32_SERIAL_USE_USART3 FALSE +#define AT32_SERIAL_USE_UART4 FALSE +#define AT32_SERIAL_USE_UART5 FALSE +#define AT32_SERIAL_USE_USART6 FALSE +#define AT32_SERIAL_USE_UART7 FALSE +#define AT32_SERIAL_USE_UART8 FALSE + +/* + * SIO driver system settings. + */ +#define AT32_SIO_USE_USART1 FALSE +#define AT32_SIO_USE_USART2 FALSE +#define AT32_SIO_USE_USART3 FALSE +#define AT32_SIO_USE_UART4 FALSE +#define AT32_SIO_USE_UART5 FALSE +#define AT32_SIO_USE_USART6 FALSE +#define AT32_SIO_USE_UART7 FALSE +#define AT32_SIO_USE_UART8 FALSE + +/* + * SPI driver system settings. + */ +#define AT32_SPI_USE_SPI1 FALSE +#define AT32_SPI_USE_SPI2 FALSE +#define AT32_SPI_USE_SPI3 FALSE +#define AT32_SPI_SPI1_DMA_PRIORITY 1 +#define AT32_SPI_SPI2_DMA_PRIORITY 1 +#define AT32_SPI_SPI3_DMA_PRIORITY 1 +#define AT32_SPI_SPI1_IRQ_PRIORITY 10 +#define AT32_SPI_SPI2_IRQ_PRIORITY 10 +#define AT32_SPI_SPI3_IRQ_PRIORITY 10 +#define AT32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define AT32_ST_IRQ_PRIORITY 8 +#define AT32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define AT32_UART_USE_USART1 FALSE +#define AT32_UART_USE_USART2 FALSE +#define AT32_UART_USE_USART3 FALSE +#define AT32_UART_USE_UART4 FALSE +#define AT32_UART_USE_UART5 FALSE +#define AT32_UART_USE_USART6 FALSE +#define AT32_UART_USE_UART7 FALSE +#define AT32_UART_USE_UART8 FALSE +#define AT32_UART_USART1_DMA_PRIORITY 0 +#define AT32_UART_USART2_DMA_PRIORITY 0 +#define AT32_UART_USART3_DMA_PRIORITY 0 +#define AT32_UART_UART4_DMA_PRIORITY 0 +#define AT32_UART_UART5_DMA_PRIORITY 0 +#define AT32_UART_USART6_DMA_PRIORITY 0 +#define AT32_UART_UART7_DMA_PRIORITY 0 +#define AT32_UART_UART8_DMA_PRIORITY 0 +#define AT32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define AT32_USB_USE_OTG1 FALSE +#define AT32_USB_OTG1_IRQ_PRIORITY 14 +#define AT32_USB_OTG1_RX_FIFO_SIZE 512 + +/* + * WDG driver system settings. + */ +#define AT32_WDG_USE_WDT FALSE + +#include "config.h" + +#endif /* MCUCONF_H */ diff --git a/testhal/AT32/multi/I2C_SW/cfg/at-start-f402/portab.c b/testhal/AT32/multi/I2C_SW/cfg/at-start-f402/portab.c new file mode 100644 index 0000000000..d9f0b8a099 --- /dev/null +++ b/testhal/AT32/multi/I2C_SW/cfg/at-start-f402/portab.c @@ -0,0 +1,75 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file portab.c + * @brief Application portability module code. + * + * @addtogroup application_portability + * @{ + */ + +#include "hal.h" + +#include "portab.h" + +#include "math.h" + +/*===========================================================================*/ +/* Module local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module exported variables. */ +/*===========================================================================*/ + +/* + * I2C fallback driver configuration structure. + */ +I2CConfig i2ccfg = { + FALSE, + PORTAB_SCL_PIN, + PORTAB_SDA_PIN, +#if (SW_I2C_USE_OSAL_DELAY) + ceil((CH_CFG_ST_FREQUENCY / 100000) / 2), +#else + &i2c_sw_delay +#endif +}; + +/*===========================================================================*/ +/* Module local types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module exported functions. */ +/*===========================================================================*/ + +void portab_setup(void) { + +} + +/** @} */ diff --git a/os/hal/ports/AT32/LLD/USARTv2/at32_uart4.inc b/testhal/AT32/multi/I2C_SW/cfg/at-start-f402/portab.h similarity index 54% rename from os/hal/ports/AT32/LLD/USARTv2/at32_uart4.inc rename to testhal/AT32/multi/I2C_SW/cfg/at-start-f402/portab.h index c07c8ff8c6..e01c42ed43 100644 --- a/os/hal/ports/AT32/LLD/USARTv2/at32_uart4.inc +++ b/testhal/AT32/multi/I2C_SW/cfg/at-start-f402/portab.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -17,95 +17,66 @@ */ /** - * @file USART/at32_uart4.inc - * @brief Shared UART4 handler. + * @file portab.h + * @brief Application portability macros and structures. * - * @addtogroup AT32_UART4_HANDLER + * @addtogroup application_portability * @{ */ -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ +#ifndef PORTAB_H +#define PORTAB_H /*===========================================================================*/ -/* Derived constants and error checks. */ +/* Module constants. */ /*===========================================================================*/ -/* Registry checks for robustness.*/ -#if !defined(AT32_HAS_UART4) -#error "AT32_HAS_UART4 not defined in registry" -#endif +#define PORTAB_I2C1 I2CD1 -#if AT32_HAS_UART4 +#define PORTAB_SCL_PIN PAL_LINE(GPIOB, 6U) -/* Priority settings checks.*/ -#if !defined(AT32_IRQ_UART4_PRIORITY) -#error "AT32_IRQ_UART4_PRIORITY not defined in mcuconf.h" -#endif +#define PORTAB_SDA_PIN PAL_LINE(GPIOB, 7U) -#if !OSAL_IRQ_IS_VALID_PRIORITY(AT32_IRQ_UART4_PRIORITY) -#error "Invalid IRQ priority assigned to AT32_IRQ_UART4_PRIORITY" -#endif +#define PORTAB_BLINK_LED1 LINE_LED_RED + +#define PORTAB_BLINK_LED2 LINE_LED_YELLOW -#endif /* AT32_HAS_UART4 */ +#define PORTAB_BLINK_LED3 LINE_LED_GREEN /*===========================================================================*/ -/* Driver exported variables. */ +/* Module pre-compile time settings. */ /*===========================================================================*/ /*===========================================================================*/ -/* Driver local variables. */ +/* Derived constants and error checks. */ /*===========================================================================*/ /*===========================================================================*/ -/* Driver local functions. */ +/* Module data structures and types. */ /*===========================================================================*/ -static inline void uart4_irq_init(void) { -#if defined(AT32_UART4_IS_USED) - nvicEnableVector(AT32_UART4_NUMBER, AT32_IRQ_UART4_PRIORITY); -#endif -} - -static inline void uart4_irq_deinit(void) { -#if defined(AT32_UART4_IS_USED) - nvicDisableVector(AT32_UART4_NUMBER); -#endif -} - /*===========================================================================*/ -/* Driver interrupt handlers. */ +/* Module macros. */ /*===========================================================================*/ -#if defined(AT32_UART4_IS_USED) || defined(__DOXYGEN__) -/** - * @brief UART4 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(AT32_UART4_HANDLER) { - - OSAL_IRQ_PROLOGUE(); +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ -#if HAL_USE_SERIAL -#if AT32_SERIAL_USE_UART4 - sd_lld_serve_interrupt(&SD4); -#endif -#endif +extern I2CConfig i2ccfg; -#if HAL_USE_UART -#if AT32_UART_USE_UART4 - uart_lld_serve_interrupt(&UARTD4); +#ifdef __cplusplus +extern "C" { #endif -#endif - - OSAL_IRQ_EPILOGUE(); + void portab_setup(void); +#ifdef __cplusplus } #endif /*===========================================================================*/ -/* Driver exported functions. */ +/* Module inline functions. */ /*===========================================================================*/ +#endif /* PORTAB_H */ + /** @} */ diff --git a/testhal/AT32/multi/I2C_SW/cfg/at-start-f405/chconf.h b/testhal/AT32/multi/I2C_SW/cfg/at-start-f405/chconf.h new file mode 100644 index 0000000000..5988b2b4b9 --- /dev/null +++ b/testhal/AT32/multi/I2C_SW/cfg/at-start-f405/chconf.h @@ -0,0 +1,842 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_7_0_ + +/*===========================================================================*/ +/** + * @name System settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Handling of instances. + * @note If enabled then threads assigned to various instances can + * interact each other using the same synchronization objects. + * If disabled then each OS instance is a separate world, no + * direct interactions are handled by the OS. + */ +#if !defined(CH_CFG_SMP_MODE) +#define CH_CFG_SMP_MODE FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_ST_RESOLUTION) +#define CH_CFG_ST_RESOLUTION 32 +#endif + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_CFG_ST_FREQUENCY) +#define CH_CFG_ST_FREQUENCY 100000 +#endif + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_INTERVALS_SIZE) +#define CH_CFG_INTERVALS_SIZE 32 +#endif + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_TIME_TYPES_SIZE) +#define CH_CFG_TIME_TYPES_SIZE 32 +#endif + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#if !defined(CH_CFG_ST_TIMEDELTA) +#define CH_CFG_ST_TIMEDELTA 2 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#if !defined(CH_CFG_TIME_QUANTUM) +#define CH_CFG_TIME_QUANTUM 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#if !defined(CH_CFG_NO_IDLE_THREAD) +#define CH_CFG_NO_IDLE_THREAD FALSE +#endif + +/** + * @brief Kernel hardening level. + * @details This option is the level of functional-safety checks enabled + * in the kerkel. The meaning is: + * - 0: No checks, maximum performance. + * - 1: Reasonable checks. + * - 2: All checks. + * . + */ +#if !defined(CH_CFG_HARDENING_LEVEL) +#define CH_CFG_HARDENING_LEVEL 0 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_OPTIMIZE_SPEED) +#define CH_CFG_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TM) +#define CH_CFG_USE_TM TRUE +#endif + +/** + * @brief Time Stamps APIs. + * @details If enabled then the time stamps APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TIMESTAMP) +#define CH_CFG_USE_TIMESTAMP TRUE +#endif + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_REGISTRY) +#define CH_CFG_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_WAITEXIT) +#define CH_CFG_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_SEMAPHORES) +#define CH_CFG_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MUTEXES) +#define CH_CFG_USE_MUTEXES TRUE +#endif + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_CONDVARS) +#define CH_CFG_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_EVENTS) +#define CH_CFG_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MESSAGES) +#define CH_CFG_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#if !defined(CH_CFG_USE_DYNAMIC) +#define CH_CFG_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name OSLIB options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_MAILBOXES) +#define CH_CFG_USE_MAILBOXES TRUE +#endif + +/** + * @brief Memory checks APIs. + * @details If enabled then the memory checks APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCHECKS) +#define CH_CFG_USE_MEMCHECKS TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCORE) +#define CH_CFG_USE_MEMCORE TRUE +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#if !defined(CH_CFG_MEMCORE_SIZE) +#define CH_CFG_MEMCORE_SIZE 0 +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_CFG_USE_HEAP) +#define CH_CFG_USE_HEAP TRUE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMPOOLS) +#define CH_CFG_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_FIFOS) +#define CH_CFG_USE_OBJ_FIFOS TRUE +#endif + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Objects Caches APIs. + * @details If enabled then the objects caches APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_CACHES) +#define CH_CFG_USE_OBJ_CACHES TRUE +#endif + +/** + * @brief Delegate threads APIs. + * @details If enabled then the delegate threads APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_DELEGATES) +#define CH_CFG_USE_DELEGATES TRUE +#endif + +/** + * @brief Jobs Queues APIs. + * @details If enabled then the jobs queues APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_JOBS) +#define CH_CFG_USE_JOBS TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_CFG_USE_FACTORY) +#define CH_CFG_USE_FACTORY TRUE +#endif + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 +#endif + +/** + * @brief Enables the registry of generic objects. + */ +#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE +#endif + +/** + * @brief Enables factory for generic buffers. + */ +#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE +#endif + +/** + * @brief Enables factory for semaphores. + */ +#if !defined(CH_CFG_FACTORY_SEMAPHORES) +#define CH_CFG_FACTORY_SEMAPHORES TRUE +#endif + +/** + * @brief Enables factory for mailboxes. + */ +#if !defined(CH_CFG_FACTORY_MAILBOXES) +#define CH_CFG_FACTORY_MAILBOXES TRUE +#endif + +/** + * @brief Enables factory for objects FIFOs. + */ +#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE +#endif + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_STATISTICS) +#define CH_DBG_STATISTICS FALSE +#endif + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_MASK) +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_ALL +#endif + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_BUFFER_SIZE) +#define CH_DBG_TRACE_BUFFER_SIZE 128 +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#if !defined(CH_DBG_THREADS_PROFILING) +#define CH_DBG_THREADS_PROFILING FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add system custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add system initialization code here.*/ \ +} + +/** + * @brief OS instance structure extension. + * @details User fields added to the end of the @p os_instance_t structure. + */ +#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS \ + /* Add OS instance custom fields here.*/ + +/** + * @brief OS instance initialization hook. + * + * @param[in] oip pointer to the @p os_instance_t structure + */ +#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) { \ + /* Add OS instance initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + * + * @param[in] ntp thread being switched in + * @param[in] otp thread being switched out + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** + * @brief Runtime Faults Collection Unit hook. + * @details This hook is invoked each time new faults are collected and stored. + */ +#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) { \ + /* Faults handling code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/testhal/AT32/multi/I2C_SW/cfg/at-start-f405/config.h b/testhal/AT32/multi/I2C_SW/cfg/at-start-f405/config.h new file mode 100644 index 0000000000..109de45450 --- /dev/null +++ b/testhal/AT32/multi/I2C_SW/cfg/at-start-f405/config.h @@ -0,0 +1,39 @@ +/* + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * CRC driver system settings. + */ +#define AT32_CRC_USE_CRC1 FALSE + +#define CRC_USE_DMA FALSE +#define AT32_CRC_CRC1_DMA_PRIORITY 2 +#define AT32_CRC_CRC1_IRQ_PRIORITY 5 +#define AT32_CRC_CRC1_DMA_STREAM AT32_DMA_STREAM_ID_ANY + +/* + * I2C fallback driver system settings. + */ +#define SW_I2C_USE_I2C1 TRUE +#define SW_I2C_USE_I2C2 FALSE +#define SW_I2C_USE_I2C3 FALSE +#define SW_I2C_USE_I2C4 FALSE + +/* + * Other settings. + */ +#define BOARD_OTG_VBUSIG diff --git a/testhal/AT32/multi/I2C_SW/cfg/at-start-f405/halconf.h b/testhal/AT32/multi/I2C_SW/cfg/at-start-f405/halconf.h new file mode 100644 index 0000000000..f1bf5fd204 --- /dev/null +++ b/testhal/AT32/multi/I2C_SW/cfg/at-start-f405/halconf.h @@ -0,0 +1,557 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_8_4_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the EFlash subsystem. + */ +#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__) +#define HAL_USE_EFL FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C TRUE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/** + * @brief Enables the WSPI subsystem. + */ +#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) +#define HAL_USE_WSPI FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS FALSE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS FALSE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Timeout before assuming a failure while waiting for card idle. + * @note Time is in milliseconds. + */ +#if !defined(MMC_IDLE_TIMEOUT_MS) || defined(__DOXYGEN__) +#define MMC_IDLE_TIMEOUT_MS 1000 +#endif + +/** + * @brief Mutual exclusion on the SPI bus. + */ +#if !defined(MMC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define MMC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SIO driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SIO_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SIO_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Support for thread synchronization API. + */ +#if !defined(SIO_USE_SYNCHRONIZATION) || defined(__DOXYGEN__) +#define SIO_USE_SYNCHRONIZATION TRUE +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 256 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 2 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Inserts an assertion on function errors before returning. + */ +#if !defined(SPI_USE_ASSERT_ON_ERROR) || defined(__DOXYGEN__) +#define SPI_USE_ASSERT_ON_ERROR TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#include "halconf_community.h" + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/testhal/AT32/multi/I2C_SW/cfg/at-start-f405/halconf_community.h b/testhal/AT32/multi/I2C_SW/cfg/at-start-f405/halconf_community.h new file mode 100644 index 0000000000..5a77290c71 --- /dev/null +++ b/testhal/AT32/multi/I2C_SW/cfg/at-start-f405/halconf_community.h @@ -0,0 +1,182 @@ +/* + ChibiOS - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef HALCONF_COMMUNITY_H +#define HALCONF_COMMUNITY_H + +/** + * @brief Enables the community overlay. + */ +#if !defined(HAL_USE_COMMUNITY) || defined(__DOXYGEN__) +#define HAL_USE_COMMUNITY TRUE +#endif + +/** + * @brief Enables the FSMC subsystem. + */ +#if !defined(HAL_USE_FSMC) || defined(__DOXYGEN__) +#define HAL_USE_FSMC FALSE +#endif + +/** + * @brief Enables the NAND subsystem. + */ +#if !defined(HAL_USE_NAND) || defined(__DOXYGEN__) +#define HAL_USE_NAND FALSE +#endif + +/** + * @brief Enables the 1-wire subsystem. + */ +#if !defined(HAL_USE_ONEWIRE) || defined(__DOXYGEN__) +#define HAL_USE_ONEWIRE FALSE +#endif + +/** + * @brief Enables the EICU subsystem. + */ +#if !defined(HAL_USE_EICU) || defined(__DOXYGEN__) +#define HAL_USE_EICU FALSE +#endif + +/** + * @brief Enables the CRC subsystem. + */ +#if !defined(HAL_USE_CRC) || defined(__DOXYGEN__) +#define HAL_USE_CRC FALSE +#endif + +/** + * @brief Enables the RNG subsystem. + */ +#if !defined(HAL_USE_RNG) || defined(__DOXYGEN__) +#define HAL_USE_RNG FALSE +#endif + +/** + * @brief Enables the EEPROM subsystem. + */ +#if !defined(HAL_USE_EEPROM) || defined(__DOXYGEN__) +#define HAL_USE_EEPROM FALSE +#endif + +/** + * @brief Enables the TIMCAP subsystem. + */ +#if !defined(HAL_USE_TIMCAP) || defined(__DOXYGEN__) +#define HAL_USE_TIMCAP FALSE +#endif + +/** + * @brief Enables the COMP subsystem. + */ +#if !defined(HAL_USE_COMP) || defined(__DOXYGEN__) +#define HAL_USE_COMP FALSE +#endif + +/** + * @brief Enables the OPAMP subsystem. + */ +#if !defined(HAL_USE_OPAMP) || defined(__DOXYGEN__) +#define HAL_USE_OPAMP FALSE +#endif + +/** + * @brief Enables the QEI subsystem. + */ +#if !defined(HAL_USE_QEI) || defined(__DOXYGEN__) +#define HAL_USE_QEI FALSE +#endif + +/** + * @brief Enables the USBH subsystem. + */ +#if !defined(HAL_USE_USBH) || defined(__DOXYGEN__) +#define HAL_USE_USBH FALSE +#endif + +/** + * @brief Enables the USB_MSD subsystem. + */ +#if !defined(HAL_USE_USB_MSD) || defined(__DOXYGEN__) +#define HAL_USE_USB_MSD FALSE +#endif + +/*===========================================================================*/ +/* FSMCNAND driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the @p nandAcquireBus() and @p nanReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(NAND_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define NAND_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* 1-wire driver related settings. */ +/*===========================================================================*/ +/** + * @brief Enables strong pull up feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_STRONG_PULLUP FALSE + +/** + * @brief Enables search ROM feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_SEARCH_ROM TRUE + +/*===========================================================================*/ +/* QEI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables discard of overlow + */ +#if !defined(QEI_USE_OVERFLOW_DISCARD) || defined(__DOXYGEN__) +#define QEI_USE_OVERFLOW_DISCARD FALSE +#endif + +/** + * @brief Enables min max of overlow + */ +#if !defined(QEI_USE_OVERFLOW_MINMAX) || defined(__DOXYGEN__) +#define QEI_USE_OVERFLOW_MINMAX FALSE +#endif + +/*===========================================================================*/ +/* EEProm driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables 24xx series I2C eeprom device driver. + * @note Disabling this option saves both code and data space. + */ +#define EEPROM_USE_EE24XX FALSE + /** + * @brief Enables 25xx series SPI eeprom device driver. + * @note Disabling this option saves both code and data space. + */ +#define EEPROM_USE_EE25XX FALSE + +#endif /* HALCONF_COMMUNITY_H */ + +/** @} */ diff --git a/testhal/AT32/multi/I2C_SW/cfg/at-start-f405/mcuconf.h b/testhal/AT32/multi/I2C_SW/cfg/at-start-f405/mcuconf.h new file mode 100644 index 0000000000..760c5a94c2 --- /dev/null +++ b/testhal/AT32/multi/I2C_SW/cfg/at-start-f405/mcuconf.h @@ -0,0 +1,272 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef MCUCONF_H +#define MCUCONF_H + +/* + * AT32F405 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define AT32F405_MCUCONF + +/* + * General settings. + */ +#define AT32_NO_INIT FALSE + +/* + * HAL driver system settings. + */ +#define AT32_HICK_ENABLED TRUE +#define AT32_LICK_ENABLED FALSE +#define AT32_HEXT_ENABLED TRUE +#define AT32_LEXT_ENABLED FALSE +#define AT32_PLLU_ENABLED TRUE +#define AT32_SCLKSEL AT32_SCLKSEL_PLL +#define AT32_PLLRCS AT32_PLLRCS_HEXT +#define AT32_PLL_MS_VALUE 1 +#define AT32_PLL_NS_VALUE 72 +#define AT32_PLL_FP_VALUE 4 +#define AT32_PLL_FU_VALUE 18 +#define AT32_AHBDIV AT32_AHBDIV_DIV1 +#define AT32_APB1DIV AT32_APB1DIV_DIV2 +#define AT32_APB2DIV AT32_APB2DIV_DIV1 +#define AT32_HICK_TO_SCLK AT32_HICK_TO_SCLK_48M +#define AT32_HICKDIV AT32_HICKDIV_DIV1 +#define AT32_HICK_TO_SCLK_DIV AT32_HICK_TO_SCLK_DIV_DIV1 +#define AT32_HEXT_TO_SCLK_DIV AT32_HEXT_TO_SCLK_DIV_DIV1 +#define AT32_USB_CLOCK48_REQUIRED TRUE +#define AT32_PLLU_USB48_SEL AT32_PLLU_USB48_SEL_PLLU +#define AT32_CLKOUT_SEL AT32_CLKOUT_SEL_HICK +#define AT32_CLKOUTDIV1 AT32_CLKOUTDIV1_DIV1 +#define AT32_CLKOUTDIV2 AT32_CLKOUTDIV2_DIV1 +#define AT32_ERTCSEL AT32_ERTCSEL_NOCLOCK +#define AT32_ERTCDIV_VALUE 12 +#define AT32_I2SF5CLKSEL AT32_I2SF5CLKSEL_SCLK +#define AT32_PVM_ENABLE FALSE +#define AT32_PVMSEL AT32_PVMSEL_LEV1 +#define AT32_LDOOVSEL AT32_LDOOVSEL_LEV3 + +/* + * IRQ system settings. + */ +#define AT32_IRQ_EXINT0_PRIORITY 6 +#define AT32_IRQ_EXINT1_PRIORITY 6 +#define AT32_IRQ_EXINT2_PRIORITY 6 +#define AT32_IRQ_EXINT3_PRIORITY 6 +#define AT32_IRQ_EXINT4_PRIORITY 6 +#define AT32_IRQ_EXINT5_9_PRIORITY 6 +#define AT32_IRQ_EXINT10_15_PRIORITY 6 +#define AT32_IRQ_EXINT16_PRIORITY 6 +#define AT32_IRQ_EXINT17_PRIORITY 15 +#define AT32_IRQ_EXINT18_PRIORITY 6 +#define AT32_IRQ_EXINT20_PRIORITY 6 +#define AT32_IRQ_EXINT21_PRIORITY 15 +#define AT32_IRQ_EXINT22_PRIORITY 15 + +#define AT32_IRQ_TMR1_BRK_TMR9_PRIORITY 7 +#define AT32_IRQ_TMR1_OVF_TMR10_PRIORITY 7 +#define AT32_IRQ_TMR1_HALL_TMR11_PRIORITY 7 +#define AT32_IRQ_TMR1_CH_PRIORITY 7 +#define AT32_IRQ_TMR2_PRIORITY 7 +#define AT32_IRQ_TMR3_PRIORITY 7 +#define AT32_IRQ_TMR4_PRIORITY 7 +#define AT32_IRQ_TMR6_PRIORITY 7 +#define AT32_IRQ_TMR7_PRIORITY 7 +#define AT32_IRQ_TMR13_PRIORITY 7 +#define AT32_IRQ_TMR14_PRIORITY 7 + +#define AT32_IRQ_USART1_PRIORITY 12 +#define AT32_IRQ_USART2_PRIORITY 12 +#define AT32_IRQ_USART3_PRIORITY 12 +#define AT32_IRQ_UART4_PRIORITY 12 +#define AT32_IRQ_UART5_PRIORITY 12 +#define AT32_IRQ_USART6_PRIORITY 12 +#define AT32_IRQ_UART7_PRIORITY 12 +#define AT32_IRQ_UART8_PRIORITY 12 + +/* + * ADC driver system settings. + */ +#define AT32_ADC_USE_ADC1 FALSE +#define AT32_ADC_ADC1_DMA_PRIORITY 2 +#define AT32_ADC_IRQ_PRIORITY 6 +#define AT32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define AT32_ADC_ADCDIV 8 + +/* + * CAN driver system settings. + */ +#define AT32_CAN_USE_CAN1 FALSE +#define AT32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * GPT driver system settings. + */ +#define AT32_GPT_USE_TMR1 FALSE +#define AT32_GPT_USE_TMR2 FALSE +#define AT32_GPT_USE_TMR3 FALSE +#define AT32_GPT_USE_TMR4 FALSE +#define AT32_GPT_USE_TMR6 FALSE +#define AT32_GPT_USE_TMR7 FALSE +#define AT32_GPT_USE_TMR9 FALSE +#define AT32_GPT_USE_TMR10 FALSE +#define AT32_GPT_USE_TMR11 FALSE +#define AT32_GPT_USE_TMR13 FALSE +#define AT32_GPT_USE_TMR14 FALSE + +/* + * I2C driver system settings. + */ +#define AT32_I2C_USE_I2C1 FALSE +#define AT32_I2C_USE_I2C2 FALSE +#define AT32_I2C_USE_I2C3 FALSE +#define AT32_I2C_BUSY_TIMEOUT 50 +#define AT32_I2C_I2C1_DMA_PRIORITY 3 +#define AT32_I2C_I2C2_DMA_PRIORITY 3 +#define AT32_I2C_I2C3_DMA_PRIORITY 3 +#define AT32_I2C_I2C1_IRQ_PRIORITY 5 +#define AT32_I2C_I2C2_IRQ_PRIORITY 5 +#define AT32_I2C_I2C3_IRQ_PRIORITY 5 +#define AT32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define AT32_ICU_USE_TMR1 FALSE +#define AT32_ICU_USE_TMR2 FALSE +#define AT32_ICU_USE_TMR3 FALSE +#define AT32_ICU_USE_TMR4 FALSE +#define AT32_ICU_USE_TMR9 FALSE + +/* + * PWM driver system settings. + */ +#define AT32_PWM_USE_TMR1 FALSE +#define AT32_PWM_USE_TMR2 FALSE +#define AT32_PWM_USE_TMR3 FALSE +#define AT32_PWM_USE_TMR4 FALSE +#define AT32_PWM_USE_TMR9 FALSE +#define AT32_PWM_USE_TMR10 FALSE +#define AT32_PWM_USE_TMR11 FALSE +#define AT32_PWM_USE_TMR13 FALSE +#define AT32_PWM_USE_TMR14 FALSE + +/* + * RTC driver system settings. + */ +#define AT32_ERTC_DIVA_VALUE 32 +#define AT32_ERTC_DIVB_VALUE 1024 +#define AT32_ERTC_CTRL_INIT 0 +#define AT32_ERTC_TAMP_INIT 0 + +/* + * SERIAL driver system settings. + */ +#define AT32_SERIAL_USE_USART1 FALSE +#define AT32_SERIAL_USE_USART2 FALSE +#define AT32_SERIAL_USE_USART3 FALSE +#define AT32_SERIAL_USE_UART4 FALSE +#define AT32_SERIAL_USE_UART5 FALSE +#define AT32_SERIAL_USE_USART6 FALSE +#define AT32_SERIAL_USE_UART7 FALSE +#define AT32_SERIAL_USE_UART8 FALSE + +/* + * SIO driver system settings. + */ +#define AT32_SIO_USE_USART1 FALSE +#define AT32_SIO_USE_USART2 FALSE +#define AT32_SIO_USE_USART3 FALSE +#define AT32_SIO_USE_UART4 FALSE +#define AT32_SIO_USE_UART5 FALSE +#define AT32_SIO_USE_USART6 FALSE +#define AT32_SIO_USE_UART7 FALSE +#define AT32_SIO_USE_UART8 FALSE + +/* + * SPI driver system settings. + */ +#define AT32_SPI_USE_SPI1 FALSE +#define AT32_SPI_USE_SPI2 FALSE +#define AT32_SPI_USE_SPI3 FALSE +#define AT32_SPI_SPI1_DMA_PRIORITY 1 +#define AT32_SPI_SPI2_DMA_PRIORITY 1 +#define AT32_SPI_SPI3_DMA_PRIORITY 1 +#define AT32_SPI_SPI1_IRQ_PRIORITY 10 +#define AT32_SPI_SPI2_IRQ_PRIORITY 10 +#define AT32_SPI_SPI3_IRQ_PRIORITY 10 +#define AT32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define AT32_ST_IRQ_PRIORITY 8 +#define AT32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define AT32_UART_USE_USART1 FALSE +#define AT32_UART_USE_USART2 FALSE +#define AT32_UART_USE_USART3 FALSE +#define AT32_UART_USE_UART4 FALSE +#define AT32_UART_USE_UART5 FALSE +#define AT32_UART_USE_USART6 FALSE +#define AT32_UART_USE_UART7 FALSE +#define AT32_UART_USE_UART8 FALSE +#define AT32_UART_USART1_DMA_PRIORITY 0 +#define AT32_UART_USART2_DMA_PRIORITY 0 +#define AT32_UART_USART3_DMA_PRIORITY 0 +#define AT32_UART_UART4_DMA_PRIORITY 0 +#define AT32_UART_UART5_DMA_PRIORITY 0 +#define AT32_UART_USART6_DMA_PRIORITY 0 +#define AT32_UART_UART7_DMA_PRIORITY 0 +#define AT32_UART_UART8_DMA_PRIORITY 0 +#define AT32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define AT32_USB_USE_OTG1 FALSE +#define AT32_USB_USE_OTG2 FALSE +#define AT32_USB_OTG1_IRQ_PRIORITY 14 +#define AT32_USB_OTG2_IRQ_PRIORITY 14 +#define AT32_USB_OTG1_RX_FIFO_SIZE 512 +#define AT32_USB_OTG2_RX_FIFO_SIZE 1024 +#define AT32_USE_USB_OTG2_HS_DMA FALSE + +/* + * WDG driver system settings. + */ +#define AT32_WDG_USE_WDT FALSE + +#include "config.h" + +#endif /* MCUCONF_H */ diff --git a/testhal/AT32/multi/I2C_SW/cfg/at-start-f405/portab.c b/testhal/AT32/multi/I2C_SW/cfg/at-start-f405/portab.c new file mode 100644 index 0000000000..d9f0b8a099 --- /dev/null +++ b/testhal/AT32/multi/I2C_SW/cfg/at-start-f405/portab.c @@ -0,0 +1,75 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file portab.c + * @brief Application portability module code. + * + * @addtogroup application_portability + * @{ + */ + +#include "hal.h" + +#include "portab.h" + +#include "math.h" + +/*===========================================================================*/ +/* Module local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module exported variables. */ +/*===========================================================================*/ + +/* + * I2C fallback driver configuration structure. + */ +I2CConfig i2ccfg = { + FALSE, + PORTAB_SCL_PIN, + PORTAB_SDA_PIN, +#if (SW_I2C_USE_OSAL_DELAY) + ceil((CH_CFG_ST_FREQUENCY / 100000) / 2), +#else + &i2c_sw_delay +#endif +}; + +/*===========================================================================*/ +/* Module local types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module exported functions. */ +/*===========================================================================*/ + +void portab_setup(void) { + +} + +/** @} */ diff --git a/os/hal/ports/AT32/LLD/USARTv2/at32_uart5.inc b/testhal/AT32/multi/I2C_SW/cfg/at-start-f405/portab.h similarity index 54% rename from os/hal/ports/AT32/LLD/USARTv2/at32_uart5.inc rename to testhal/AT32/multi/I2C_SW/cfg/at-start-f405/portab.h index fff0dadae3..e01c42ed43 100644 --- a/os/hal/ports/AT32/LLD/USARTv2/at32_uart5.inc +++ b/testhal/AT32/multi/I2C_SW/cfg/at-start-f405/portab.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -17,95 +17,66 @@ */ /** - * @file USART/at32_uart5.inc - * @brief Shared UART5 handler. + * @file portab.h + * @brief Application portability macros and structures. * - * @addtogroup AT32_UART5_HANDLER + * @addtogroup application_portability * @{ */ -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ +#ifndef PORTAB_H +#define PORTAB_H /*===========================================================================*/ -/* Derived constants and error checks. */ +/* Module constants. */ /*===========================================================================*/ -/* Registry checks for robustness.*/ -#if !defined(AT32_HAS_UART5) -#error "AT32_HAS_UART5 not defined in registry" -#endif +#define PORTAB_I2C1 I2CD1 -#if AT32_HAS_UART5 +#define PORTAB_SCL_PIN PAL_LINE(GPIOB, 6U) -/* Priority settings checks.*/ -#if !defined(AT32_IRQ_UART5_PRIORITY) -#error "AT32_IRQ_UART5_PRIORITY not defined in mcuconf.h" -#endif +#define PORTAB_SDA_PIN PAL_LINE(GPIOB, 7U) -#if !OSAL_IRQ_IS_VALID_PRIORITY(AT32_IRQ_UART5_PRIORITY) -#error "Invalid IRQ priority assigned to AT32_IRQ_UART5_PRIORITY" -#endif +#define PORTAB_BLINK_LED1 LINE_LED_RED + +#define PORTAB_BLINK_LED2 LINE_LED_YELLOW -#endif /* AT32_HAS_UART5 */ +#define PORTAB_BLINK_LED3 LINE_LED_GREEN /*===========================================================================*/ -/* Driver exported variables. */ +/* Module pre-compile time settings. */ /*===========================================================================*/ /*===========================================================================*/ -/* Driver local variables. */ +/* Derived constants and error checks. */ /*===========================================================================*/ /*===========================================================================*/ -/* Driver local functions. */ +/* Module data structures and types. */ /*===========================================================================*/ -static inline void uart5_irq_init(void) { -#if defined(AT32_UART5_IS_USED) - nvicEnableVector(AT32_UART5_NUMBER, AT32_IRQ_UART5_PRIORITY); -#endif -} - -static inline void uart5_irq_deinit(void) { -#if defined(AT32_UART5_IS_USED) - nvicDisableVector(AT32_UART5_NUMBER); -#endif -} - /*===========================================================================*/ -/* Driver interrupt handlers. */ +/* Module macros. */ /*===========================================================================*/ -#if defined(AT32_UART5_IS_USED) || defined(__DOXYGEN__) -/** - * @brief UART5 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(AT32_UART5_HANDLER) { - - OSAL_IRQ_PROLOGUE(); +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ -#if HAL_USE_SERIAL -#if AT32_SERIAL_USE_UART5 - sd_lld_serve_interrupt(&SD5); -#endif -#endif +extern I2CConfig i2ccfg; -#if HAL_USE_UART -#if AT32_UART_USE_UART5 - uart_lld_serve_interrupt(&UARTD5); +#ifdef __cplusplus +extern "C" { #endif -#endif - - OSAL_IRQ_EPILOGUE(); + void portab_setup(void); +#ifdef __cplusplus } #endif /*===========================================================================*/ -/* Driver exported functions. */ +/* Module inline functions. */ /*===========================================================================*/ +#endif /* PORTAB_H */ + /** @} */ diff --git a/testhal/AT32/multi/I2C_SW/cfg/at-start-f415/chconf.h b/testhal/AT32/multi/I2C_SW/cfg/at-start-f415/chconf.h index 9baf444de4..5988b2b4b9 100644 --- a/testhal/AT32/multi/I2C_SW/cfg/at-start-f415/chconf.h +++ b/testhal/AT32/multi/I2C_SW/cfg/at-start-f415/chconf.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/testhal/AT32/multi/I2C_SW/cfg/at-start-f415/config.h b/testhal/AT32/multi/I2C_SW/cfg/at-start-f415/config.h index b9f1c17460..acc9892f31 100644 --- a/testhal/AT32/multi/I2C_SW/cfg/at-start-f415/config.h +++ b/testhal/AT32/multi/I2C_SW/cfg/at-start-f415/config.h @@ -1,6 +1,6 @@ /* - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/testhal/AT32/multi/I2C_SW/cfg/at-start-f415/halconf.h b/testhal/AT32/multi/I2C_SW/cfg/at-start-f415/halconf.h index 7aff43b894..f1bf5fd204 100644 --- a/testhal/AT32/multi/I2C_SW/cfg/at-start-f415/halconf.h +++ b/testhal/AT32/multi/I2C_SW/cfg/at-start-f415/halconf.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/testhal/AT32/multi/I2C_SW/cfg/at-start-f415/halconf_community.h b/testhal/AT32/multi/I2C_SW/cfg/at-start-f415/halconf_community.h index c43d668764..5a77290c71 100644 --- a/testhal/AT32/multi/I2C_SW/cfg/at-start-f415/halconf_community.h +++ b/testhal/AT32/multi/I2C_SW/cfg/at-start-f415/halconf_community.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/testhal/AT32/multi/I2C_SW/cfg/at-start-f415/mcuconf.h b/testhal/AT32/multi/I2C_SW/cfg/at-start-f415/mcuconf.h index c036f365a3..eeeaecc624 100644 --- a/testhal/AT32/multi/I2C_SW/cfg/at-start-f415/mcuconf.h +++ b/testhal/AT32/multi/I2C_SW/cfg/at-start-f415/mcuconf.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -106,6 +106,7 @@ #define AT32_ADC_USE_ADC1 FALSE #define AT32_ADC_ADC1_DMA_PRIORITY 2 #define AT32_ADC_ADC1_IRQ_PRIORITY 6 +#define AT32_ADC_ADC1_DMA_IRQ_PRIORITY 6 /* * CAN driver system settings. diff --git a/testhal/AT32/multi/I2C_SW/cfg/at-start-f415/portab.c b/testhal/AT32/multi/I2C_SW/cfg/at-start-f415/portab.c index 798046ff8d..d9f0b8a099 100644 --- a/testhal/AT32/multi/I2C_SW/cfg/at-start-f415/portab.c +++ b/testhal/AT32/multi/I2C_SW/cfg/at-start-f415/portab.c @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/testhal/AT32/multi/I2C_SW/cfg/at-start-f415/portab.h b/testhal/AT32/multi/I2C_SW/cfg/at-start-f415/portab.h index c3bd55be49..e01c42ed43 100644 --- a/testhal/AT32/multi/I2C_SW/cfg/at-start-f415/portab.h +++ b/testhal/AT32/multi/I2C_SW/cfg/at-start-f415/portab.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/testhal/AT32/multi/I2C_SW/main.c b/testhal/AT32/multi/I2C_SW/main.c index 365894bed0..9e741b0ce0 100644 --- a/testhal/AT32/multi/I2C_SW/main.c +++ b/testhal/AT32/multi/I2C_SW/main.c @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/testhal/AT32/multi/I2C_SW/make/at-start-f402.make b/testhal/AT32/multi/I2C_SW/make/at-start-f402.make new file mode 100644 index 0000000000..a4e4cb824b --- /dev/null +++ b/testhal/AT32/multi/I2C_SW/make/at-start-f402.make @@ -0,0 +1,196 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO). +ifeq ($(USE_LTO),) + USE_LTO = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# Enable this if you want to use bitbang I2C. +ifeq ($(USE_HAL_I2C_FALLBACK),) + USE_HAL_I2C_FALLBACK = yes +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x400 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU (no, softfp, hard). +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# FPU-related options. +ifeq ($(USE_FPU_OPT),) + USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16 +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, target, sources and paths +# + +# Define project name here +PROJECT = ch + +# Target settings. +MCU = cortex-m4 + +# Imported source files and paths. +CHIBIOS := ../../../../../ChibiOS +CHIBIOS_CONTRIB := ../../../.. +CONFDIR := ./cfg/at-start-f402 +BUILDDIR := ./build/at-start-f402 +DEPDIR := ./.dep/at-start-f402 + +# Licensing files. +include $(CHIBIOS)/os/license/license.mk +# Startup files. +include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_at32f402.mk +# HAL-OSAL files (optional). +include $(CHIBIOS_CONTRIB)/os/hal/hal.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/AT32F402_405/platform.mk +include $(CHIBIOS_CONTRIB)/os/hal/boards/AT_START_F402/board.mk +include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMv7-M/compilers/GCC/mk/port.mk +# Auto-build files in ./source recursively. +include $(CHIBIOS)/tools/mk/autobuild.mk +# Other files (optional). +#include $(CHIBIOS)/os/test/test.mk +#include $(CHIBIOS)/test/rt/rt_test.mk +#include $(CHIBIOS)/test/oslib/oslib_test.mk + +# Define linker script file here. +LDSCRIPT= $(STARTUPLD_CONTRIB)/AT32F402xC.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(ALLCSRC) \ + $(TESTSRC) \ + $(CONFDIR)/portab.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = $(ALLCPPSRC) + +# List ASM source files here. +ASMSRC = $(ALLASMSRC) + +# List ASM with preprocessor source files here. +ASMXSRC = $(ALLXASMSRC) + +# Inclusion directories. +INCDIR = $(CONFDIR) $(ALLINC) + +# Define C warning options here. +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes + +# Define C++ warning options here. +CPPWARN = -Wall -Wextra -Wundef + +# +# Project, target, sources and paths +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user section +############################################################################## + +############################################################################## +# Common rules +# + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk +include $(RULESPATH)/arm-none-eabi.mk +include $(RULESPATH)/rules.mk + +# +# Common rules +############################################################################## + +############################################################################## +# Custom rules +# + +# +# Custom rules +############################################################################## diff --git a/testhal/AT32/multi/I2C_SW/make/at-start-f405.make b/testhal/AT32/multi/I2C_SW/make/at-start-f405.make new file mode 100644 index 0000000000..8bae274794 --- /dev/null +++ b/testhal/AT32/multi/I2C_SW/make/at-start-f405.make @@ -0,0 +1,196 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO). +ifeq ($(USE_LTO),) + USE_LTO = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# Enable this if you want to use bitbang I2C. +ifeq ($(USE_HAL_I2C_FALLBACK),) + USE_HAL_I2C_FALLBACK = yes +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x400 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU (no, softfp, hard). +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# FPU-related options. +ifeq ($(USE_FPU_OPT),) + USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16 +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, target, sources and paths +# + +# Define project name here +PROJECT = ch + +# Target settings. +MCU = cortex-m4 + +# Imported source files and paths. +CHIBIOS := ../../../../../ChibiOS +CHIBIOS_CONTRIB := ../../../.. +CONFDIR := ./cfg/at-start-f405 +BUILDDIR := ./build/at-start-f405 +DEPDIR := ./.dep/at-start-f405 + +# Licensing files. +include $(CHIBIOS)/os/license/license.mk +# Startup files. +include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_at32f405.mk +# HAL-OSAL files (optional). +include $(CHIBIOS_CONTRIB)/os/hal/hal.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/AT32F402_405/platform.mk +include $(CHIBIOS_CONTRIB)/os/hal/boards/AT_START_F405/board.mk +include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMv7-M/compilers/GCC/mk/port.mk +# Auto-build files in ./source recursively. +include $(CHIBIOS)/tools/mk/autobuild.mk +# Other files (optional). +#include $(CHIBIOS)/os/test/test.mk +#include $(CHIBIOS)/test/rt/rt_test.mk +#include $(CHIBIOS)/test/oslib/oslib_test.mk + +# Define linker script file here. +LDSCRIPT= $(STARTUPLD_CONTRIB)/AT32F405xC.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(ALLCSRC) \ + $(TESTSRC) \ + $(CONFDIR)/portab.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = $(ALLCPPSRC) + +# List ASM source files here. +ASMSRC = $(ALLASMSRC) + +# List ASM with preprocessor source files here. +ASMXSRC = $(ALLXASMSRC) + +# Inclusion directories. +INCDIR = $(CONFDIR) $(ALLINC) + +# Define C warning options here. +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes + +# Define C++ warning options here. +CPPWARN = -Wall -Wextra -Wundef + +# +# Project, target, sources and paths +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user section +############################################################################## + +############################################################################## +# Common rules +# + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk +include $(RULESPATH)/arm-none-eabi.mk +include $(RULESPATH)/rules.mk + +# +# Common rules +############################################################################## + +############################################################################## +# Custom rules +# + +# +# Custom rules +############################################################################## diff --git a/testhal/AT32/multi/PWM_ICU/Makefile b/testhal/AT32/multi/PWM_ICU/Makefile index c8606df05e..fdf3019a85 100644 --- a/testhal/AT32/multi/PWM_ICU/Makefile +++ b/testhal/AT32/multi/PWM_ICU/Makefile @@ -3,6 +3,14 @@ # all: + @echo + @echo === Building for AT-START-F402 ===================================== + +@make --no-print-directory -f ./make/at-start-f402.make all + @echo ==================================================================== + @echo + @echo === Building for AT-START-F405 ===================================== + +@make --no-print-directory -f ./make/at-start-f405.make all + @echo ==================================================================== @echo @echo === Building for AT-START-F415 ===================================== +@make --no-print-directory -f ./make/at-start-f415.make all @@ -10,6 +18,10 @@ all: @echo clean: + @echo + +@make --no-print-directory -f ./make/at-start-f402.make clean + @echo + +@make --no-print-directory -f ./make/at-start-f405.make clean @echo +@make --no-print-directory -f ./make/at-start-f415.make clean @echo diff --git a/testhal/AT32/multi/PWM_ICU/cfg/at-start-f402/chconf.h b/testhal/AT32/multi/PWM_ICU/cfg/at-start-f402/chconf.h new file mode 100644 index 0000000000..56fe06776a --- /dev/null +++ b/testhal/AT32/multi/PWM_ICU/cfg/at-start-f402/chconf.h @@ -0,0 +1,842 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_7_0_ + +/*===========================================================================*/ +/** + * @name System settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Handling of instances. + * @note If enabled then threads assigned to various instances can + * interact each other using the same synchronization objects. + * If disabled then each OS instance is a separate world, no + * direct interactions are handled by the OS. + */ +#if !defined(CH_CFG_SMP_MODE) +#define CH_CFG_SMP_MODE FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_ST_RESOLUTION) +#define CH_CFG_ST_RESOLUTION 32 +#endif + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_CFG_ST_FREQUENCY) +#define CH_CFG_ST_FREQUENCY 10000 +#endif + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_INTERVALS_SIZE) +#define CH_CFG_INTERVALS_SIZE 32 +#endif + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_TIME_TYPES_SIZE) +#define CH_CFG_TIME_TYPES_SIZE 32 +#endif + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#if !defined(CH_CFG_ST_TIMEDELTA) +#define CH_CFG_ST_TIMEDELTA 2 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#if !defined(CH_CFG_TIME_QUANTUM) +#define CH_CFG_TIME_QUANTUM 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#if !defined(CH_CFG_NO_IDLE_THREAD) +#define CH_CFG_NO_IDLE_THREAD FALSE +#endif + +/** + * @brief Kernel hardening level. + * @details This option is the level of functional-safety checks enabled + * in the kerkel. The meaning is: + * - 0: No checks, maximum performance. + * - 1: Reasonable checks. + * - 2: All checks. + * . + */ +#if !defined(CH_CFG_HARDENING_LEVEL) +#define CH_CFG_HARDENING_LEVEL 0 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_OPTIMIZE_SPEED) +#define CH_CFG_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TM) +#define CH_CFG_USE_TM TRUE +#endif + +/** + * @brief Time Stamps APIs. + * @details If enabled then the time stamps APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TIMESTAMP) +#define CH_CFG_USE_TIMESTAMP TRUE +#endif + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_REGISTRY) +#define CH_CFG_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_WAITEXIT) +#define CH_CFG_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_SEMAPHORES) +#define CH_CFG_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MUTEXES) +#define CH_CFG_USE_MUTEXES TRUE +#endif + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_CONDVARS) +#define CH_CFG_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_EVENTS) +#define CH_CFG_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MESSAGES) +#define CH_CFG_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#if !defined(CH_CFG_USE_DYNAMIC) +#define CH_CFG_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name OSLIB options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_MAILBOXES) +#define CH_CFG_USE_MAILBOXES TRUE +#endif + +/** + * @brief Memory checks APIs. + * @details If enabled then the memory checks APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCHECKS) +#define CH_CFG_USE_MEMCHECKS TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCORE) +#define CH_CFG_USE_MEMCORE TRUE +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#if !defined(CH_CFG_MEMCORE_SIZE) +#define CH_CFG_MEMCORE_SIZE 0 +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_CFG_USE_HEAP) +#define CH_CFG_USE_HEAP TRUE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMPOOLS) +#define CH_CFG_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_FIFOS) +#define CH_CFG_USE_OBJ_FIFOS TRUE +#endif + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Objects Caches APIs. + * @details If enabled then the objects caches APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_CACHES) +#define CH_CFG_USE_OBJ_CACHES TRUE +#endif + +/** + * @brief Delegate threads APIs. + * @details If enabled then the delegate threads APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_DELEGATES) +#define CH_CFG_USE_DELEGATES TRUE +#endif + +/** + * @brief Jobs Queues APIs. + * @details If enabled then the jobs queues APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_JOBS) +#define CH_CFG_USE_JOBS TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_CFG_USE_FACTORY) +#define CH_CFG_USE_FACTORY TRUE +#endif + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 +#endif + +/** + * @brief Enables the registry of generic objects. + */ +#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE +#endif + +/** + * @brief Enables factory for generic buffers. + */ +#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE +#endif + +/** + * @brief Enables factory for semaphores. + */ +#if !defined(CH_CFG_FACTORY_SEMAPHORES) +#define CH_CFG_FACTORY_SEMAPHORES TRUE +#endif + +/** + * @brief Enables factory for mailboxes. + */ +#if !defined(CH_CFG_FACTORY_MAILBOXES) +#define CH_CFG_FACTORY_MAILBOXES TRUE +#endif + +/** + * @brief Enables factory for objects FIFOs. + */ +#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE +#endif + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_STATISTICS) +#define CH_DBG_STATISTICS FALSE +#endif + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_MASK) +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_ALL +#endif + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_BUFFER_SIZE) +#define CH_DBG_TRACE_BUFFER_SIZE 128 +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#if !defined(CH_DBG_THREADS_PROFILING) +#define CH_DBG_THREADS_PROFILING FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add system custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add system initialization code here.*/ \ +} + +/** + * @brief OS instance structure extension. + * @details User fields added to the end of the @p os_instance_t structure. + */ +#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS \ + /* Add OS instance custom fields here.*/ + +/** + * @brief OS instance initialization hook. + * + * @param[in] oip pointer to the @p os_instance_t structure + */ +#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) { \ + /* Add OS instance initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + * + * @param[in] ntp thread being switched in + * @param[in] otp thread being switched out + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** + * @brief Runtime Faults Collection Unit hook. + * @details This hook is invoked each time new faults are collected and stored. + */ +#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) { \ + /* Faults handling code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/testhal/AT32/multi/PWM_ICU/cfg/at-start-f402/config.h b/testhal/AT32/multi/PWM_ICU/cfg/at-start-f402/config.h new file mode 100644 index 0000000000..1e7c044f47 --- /dev/null +++ b/testhal/AT32/multi/PWM_ICU/cfg/at-start-f402/config.h @@ -0,0 +1,39 @@ +/* + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * CRC driver system settings. + */ +#define AT32_CRC_USE_CRC1 FALSE + +#define CRC_USE_DMA FALSE +#define AT32_CRC_CRC1_DMA_PRIORITY 2 +#define AT32_CRC_CRC1_IRQ_PRIORITY 5 +#define AT32_CRC_CRC1_DMA_STREAM AT32_DMA_STREAM_ID_ANY + +/* + * I2C fallback driver system settings. + */ +#define SW_I2C_USE_I2C1 FALSE +#define SW_I2C_USE_I2C2 FALSE +#define SW_I2C_USE_I2C3 FALSE +#define SW_I2C_USE_I2C4 FALSE + +/* + * Other settings. + */ +#define BOARD_OTG_VBUSIG diff --git a/testhal/AT32/multi/PWM_ICU/cfg/at-start-f402/halconf.h b/testhal/AT32/multi/PWM_ICU/cfg/at-start-f402/halconf.h new file mode 100644 index 0000000000..892ec9159c --- /dev/null +++ b/testhal/AT32/multi/PWM_ICU/cfg/at-start-f402/halconf.h @@ -0,0 +1,557 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_8_4_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the EFlash subsystem. + */ +#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__) +#define HAL_USE_EFL FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU TRUE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM TRUE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/** + * @brief Enables the WSPI subsystem. + */ +#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) +#define HAL_USE_WSPI FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS FALSE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS FALSE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Timeout before assuming a failure while waiting for card idle. + * @note Time is in milliseconds. + */ +#if !defined(MMC_IDLE_TIMEOUT_MS) || defined(__DOXYGEN__) +#define MMC_IDLE_TIMEOUT_MS 1000 +#endif + +/** + * @brief Mutual exclusion on the SPI bus. + */ +#if !defined(MMC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define MMC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SIO driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SIO_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SIO_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Support for thread synchronization API. + */ +#if !defined(SIO_USE_SYNCHRONIZATION) || defined(__DOXYGEN__) +#define SIO_USE_SYNCHRONIZATION TRUE +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 256 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 2 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Inserts an assertion on function errors before returning. + */ +#if !defined(SPI_USE_ASSERT_ON_ERROR) || defined(__DOXYGEN__) +#define SPI_USE_ASSERT_ON_ERROR TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#include "halconf_community.h" + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/testhal/AT32/multi/PWM_ICU/cfg/at-start-f402/halconf_community.h b/testhal/AT32/multi/PWM_ICU/cfg/at-start-f402/halconf_community.h new file mode 100644 index 0000000000..5a77290c71 --- /dev/null +++ b/testhal/AT32/multi/PWM_ICU/cfg/at-start-f402/halconf_community.h @@ -0,0 +1,182 @@ +/* + ChibiOS - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef HALCONF_COMMUNITY_H +#define HALCONF_COMMUNITY_H + +/** + * @brief Enables the community overlay. + */ +#if !defined(HAL_USE_COMMUNITY) || defined(__DOXYGEN__) +#define HAL_USE_COMMUNITY TRUE +#endif + +/** + * @brief Enables the FSMC subsystem. + */ +#if !defined(HAL_USE_FSMC) || defined(__DOXYGEN__) +#define HAL_USE_FSMC FALSE +#endif + +/** + * @brief Enables the NAND subsystem. + */ +#if !defined(HAL_USE_NAND) || defined(__DOXYGEN__) +#define HAL_USE_NAND FALSE +#endif + +/** + * @brief Enables the 1-wire subsystem. + */ +#if !defined(HAL_USE_ONEWIRE) || defined(__DOXYGEN__) +#define HAL_USE_ONEWIRE FALSE +#endif + +/** + * @brief Enables the EICU subsystem. + */ +#if !defined(HAL_USE_EICU) || defined(__DOXYGEN__) +#define HAL_USE_EICU FALSE +#endif + +/** + * @brief Enables the CRC subsystem. + */ +#if !defined(HAL_USE_CRC) || defined(__DOXYGEN__) +#define HAL_USE_CRC FALSE +#endif + +/** + * @brief Enables the RNG subsystem. + */ +#if !defined(HAL_USE_RNG) || defined(__DOXYGEN__) +#define HAL_USE_RNG FALSE +#endif + +/** + * @brief Enables the EEPROM subsystem. + */ +#if !defined(HAL_USE_EEPROM) || defined(__DOXYGEN__) +#define HAL_USE_EEPROM FALSE +#endif + +/** + * @brief Enables the TIMCAP subsystem. + */ +#if !defined(HAL_USE_TIMCAP) || defined(__DOXYGEN__) +#define HAL_USE_TIMCAP FALSE +#endif + +/** + * @brief Enables the COMP subsystem. + */ +#if !defined(HAL_USE_COMP) || defined(__DOXYGEN__) +#define HAL_USE_COMP FALSE +#endif + +/** + * @brief Enables the OPAMP subsystem. + */ +#if !defined(HAL_USE_OPAMP) || defined(__DOXYGEN__) +#define HAL_USE_OPAMP FALSE +#endif + +/** + * @brief Enables the QEI subsystem. + */ +#if !defined(HAL_USE_QEI) || defined(__DOXYGEN__) +#define HAL_USE_QEI FALSE +#endif + +/** + * @brief Enables the USBH subsystem. + */ +#if !defined(HAL_USE_USBH) || defined(__DOXYGEN__) +#define HAL_USE_USBH FALSE +#endif + +/** + * @brief Enables the USB_MSD subsystem. + */ +#if !defined(HAL_USE_USB_MSD) || defined(__DOXYGEN__) +#define HAL_USE_USB_MSD FALSE +#endif + +/*===========================================================================*/ +/* FSMCNAND driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the @p nandAcquireBus() and @p nanReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(NAND_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define NAND_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* 1-wire driver related settings. */ +/*===========================================================================*/ +/** + * @brief Enables strong pull up feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_STRONG_PULLUP FALSE + +/** + * @brief Enables search ROM feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_SEARCH_ROM TRUE + +/*===========================================================================*/ +/* QEI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables discard of overlow + */ +#if !defined(QEI_USE_OVERFLOW_DISCARD) || defined(__DOXYGEN__) +#define QEI_USE_OVERFLOW_DISCARD FALSE +#endif + +/** + * @brief Enables min max of overlow + */ +#if !defined(QEI_USE_OVERFLOW_MINMAX) || defined(__DOXYGEN__) +#define QEI_USE_OVERFLOW_MINMAX FALSE +#endif + +/*===========================================================================*/ +/* EEProm driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables 24xx series I2C eeprom device driver. + * @note Disabling this option saves both code and data space. + */ +#define EEPROM_USE_EE24XX FALSE + /** + * @brief Enables 25xx series SPI eeprom device driver. + * @note Disabling this option saves both code and data space. + */ +#define EEPROM_USE_EE25XX FALSE + +#endif /* HALCONF_COMMUNITY_H */ + +/** @} */ diff --git a/testhal/AT32/multi/PWM_ICU/cfg/at-start-f402/mcuconf.h b/testhal/AT32/multi/PWM_ICU/cfg/at-start-f402/mcuconf.h new file mode 100644 index 0000000000..5e7c25e015 --- /dev/null +++ b/testhal/AT32/multi/PWM_ICU/cfg/at-start-f402/mcuconf.h @@ -0,0 +1,268 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef MCUCONF_H +#define MCUCONF_H + +/* + * AT32F402 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define AT32F402_MCUCONF + +/* + * General settings. + */ +#define AT32_NO_INIT FALSE + +/* + * HAL driver system settings. + */ +#define AT32_HICK_ENABLED TRUE +#define AT32_LICK_ENABLED FALSE +#define AT32_HEXT_ENABLED TRUE +#define AT32_LEXT_ENABLED FALSE +#define AT32_PLLU_ENABLED TRUE +#define AT32_SCLKSEL AT32_SCLKSEL_PLL +#define AT32_PLLRCS AT32_PLLRCS_HEXT +#define AT32_PLL_MS_VALUE 1 +#define AT32_PLL_NS_VALUE 72 +#define AT32_PLL_FP_VALUE 4 +#define AT32_PLL_FU_VALUE 18 +#define AT32_AHBDIV AT32_AHBDIV_DIV1 +#define AT32_APB1DIV AT32_APB1DIV_DIV2 +#define AT32_APB2DIV AT32_APB2DIV_DIV1 +#define AT32_HICK_TO_SCLK AT32_HICK_TO_SCLK_48M +#define AT32_HICKDIV AT32_HICKDIV_DIV1 +#define AT32_HICK_TO_SCLK_DIV AT32_HICK_TO_SCLK_DIV_DIV1 +#define AT32_HEXT_TO_SCLK_DIV AT32_HEXT_TO_SCLK_DIV_DIV1 +#define AT32_USB_CLOCK48_REQUIRED TRUE +#define AT32_PLLU_USB48_SEL AT32_PLLU_USB48_SEL_PLLU +#define AT32_CLKOUT_SEL AT32_CLKOUT_SEL_HICK +#define AT32_CLKOUTDIV1 AT32_CLKOUTDIV1_DIV1 +#define AT32_CLKOUTDIV2 AT32_CLKOUTDIV2_DIV1 +#define AT32_ERTCSEL AT32_ERTCSEL_NOCLOCK +#define AT32_ERTCDIV_VALUE 12 +#define AT32_I2SF5CLKSEL AT32_I2SF5CLKSEL_SCLK +#define AT32_PVM_ENABLE FALSE +#define AT32_PVMSEL AT32_PVMSEL_LEV1 +#define AT32_LDOOVSEL AT32_LDOOVSEL_LEV3 + +/* + * IRQ system settings. + */ +#define AT32_IRQ_EXINT0_PRIORITY 6 +#define AT32_IRQ_EXINT1_PRIORITY 6 +#define AT32_IRQ_EXINT2_PRIORITY 6 +#define AT32_IRQ_EXINT3_PRIORITY 6 +#define AT32_IRQ_EXINT4_PRIORITY 6 +#define AT32_IRQ_EXINT5_9_PRIORITY 6 +#define AT32_IRQ_EXINT10_15_PRIORITY 6 +#define AT32_IRQ_EXINT16_PRIORITY 6 +#define AT32_IRQ_EXINT17_PRIORITY 15 +#define AT32_IRQ_EXINT18_PRIORITY 6 +#define AT32_IRQ_EXINT20_PRIORITY 6 +#define AT32_IRQ_EXINT21_PRIORITY 15 +#define AT32_IRQ_EXINT22_PRIORITY 15 + +#define AT32_IRQ_TMR1_BRK_TMR9_PRIORITY 7 +#define AT32_IRQ_TMR1_OVF_TMR10_PRIORITY 7 +#define AT32_IRQ_TMR1_HALL_TMR11_PRIORITY 7 +#define AT32_IRQ_TMR1_CH_PRIORITY 7 +#define AT32_IRQ_TMR2_PRIORITY 7 +#define AT32_IRQ_TMR3_PRIORITY 7 +#define AT32_IRQ_TMR4_PRIORITY 7 +#define AT32_IRQ_TMR6_PRIORITY 7 +#define AT32_IRQ_TMR7_PRIORITY 7 +#define AT32_IRQ_TMR13_PRIORITY 7 +#define AT32_IRQ_TMR14_PRIORITY 7 + +#define AT32_IRQ_USART1_PRIORITY 12 +#define AT32_IRQ_USART2_PRIORITY 12 +#define AT32_IRQ_USART3_PRIORITY 12 +#define AT32_IRQ_UART4_PRIORITY 12 +#define AT32_IRQ_UART5_PRIORITY 12 +#define AT32_IRQ_USART6_PRIORITY 12 +#define AT32_IRQ_UART7_PRIORITY 12 +#define AT32_IRQ_UART8_PRIORITY 12 + +/* + * ADC driver system settings. + */ +#define AT32_ADC_USE_ADC1 FALSE +#define AT32_ADC_ADC1_DMA_PRIORITY 2 +#define AT32_ADC_IRQ_PRIORITY 6 +#define AT32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define AT32_ADC_ADCDIV 8 + +/* + * CAN driver system settings. + */ +#define AT32_CAN_USE_CAN1 FALSE +#define AT32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * GPT driver system settings. + */ +#define AT32_GPT_USE_TMR1 FALSE +#define AT32_GPT_USE_TMR2 FALSE +#define AT32_GPT_USE_TMR3 FALSE +#define AT32_GPT_USE_TMR4 FALSE +#define AT32_GPT_USE_TMR6 FALSE +#define AT32_GPT_USE_TMR7 FALSE +#define AT32_GPT_USE_TMR9 FALSE +#define AT32_GPT_USE_TMR10 FALSE +#define AT32_GPT_USE_TMR11 FALSE +#define AT32_GPT_USE_TMR13 FALSE +#define AT32_GPT_USE_TMR14 FALSE + +/* + * I2C driver system settings. + */ +#define AT32_I2C_USE_I2C1 FALSE +#define AT32_I2C_USE_I2C2 FALSE +#define AT32_I2C_USE_I2C3 FALSE +#define AT32_I2C_BUSY_TIMEOUT 50 +#define AT32_I2C_I2C1_DMA_PRIORITY 3 +#define AT32_I2C_I2C2_DMA_PRIORITY 3 +#define AT32_I2C_I2C3_DMA_PRIORITY 3 +#define AT32_I2C_I2C1_IRQ_PRIORITY 5 +#define AT32_I2C_I2C2_IRQ_PRIORITY 5 +#define AT32_I2C_I2C3_IRQ_PRIORITY 5 +#define AT32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define AT32_ICU_USE_TMR1 FALSE +#define AT32_ICU_USE_TMR2 FALSE +#define AT32_ICU_USE_TMR3 TRUE +#define AT32_ICU_USE_TMR4 FALSE +#define AT32_ICU_USE_TMR9 FALSE + +/* + * PWM driver system settings. + */ +#define AT32_PWM_USE_TMR1 TRUE +#define AT32_PWM_USE_TMR2 FALSE +#define AT32_PWM_USE_TMR3 FALSE +#define AT32_PWM_USE_TMR4 FALSE +#define AT32_PWM_USE_TMR9 FALSE +#define AT32_PWM_USE_TMR10 FALSE +#define AT32_PWM_USE_TMR11 FALSE +#define AT32_PWM_USE_TMR13 FALSE +#define AT32_PWM_USE_TMR14 FALSE + +/* + * RTC driver system settings. + */ +#define AT32_ERTC_DIVA_VALUE 32 +#define AT32_ERTC_DIVB_VALUE 1024 +#define AT32_ERTC_CTRL_INIT 0 +#define AT32_ERTC_TAMP_INIT 0 + +/* + * SERIAL driver system settings. + */ +#define AT32_SERIAL_USE_USART1 FALSE +#define AT32_SERIAL_USE_USART2 FALSE +#define AT32_SERIAL_USE_USART3 FALSE +#define AT32_SERIAL_USE_UART4 FALSE +#define AT32_SERIAL_USE_UART5 FALSE +#define AT32_SERIAL_USE_USART6 FALSE +#define AT32_SERIAL_USE_UART7 FALSE +#define AT32_SERIAL_USE_UART8 FALSE + +/* + * SIO driver system settings. + */ +#define AT32_SIO_USE_USART1 FALSE +#define AT32_SIO_USE_USART2 FALSE +#define AT32_SIO_USE_USART3 FALSE +#define AT32_SIO_USE_UART4 FALSE +#define AT32_SIO_USE_UART5 FALSE +#define AT32_SIO_USE_USART6 FALSE +#define AT32_SIO_USE_UART7 FALSE +#define AT32_SIO_USE_UART8 FALSE + +/* + * SPI driver system settings. + */ +#define AT32_SPI_USE_SPI1 FALSE +#define AT32_SPI_USE_SPI2 FALSE +#define AT32_SPI_USE_SPI3 FALSE +#define AT32_SPI_SPI1_DMA_PRIORITY 1 +#define AT32_SPI_SPI2_DMA_PRIORITY 1 +#define AT32_SPI_SPI3_DMA_PRIORITY 1 +#define AT32_SPI_SPI1_IRQ_PRIORITY 10 +#define AT32_SPI_SPI2_IRQ_PRIORITY 10 +#define AT32_SPI_SPI3_IRQ_PRIORITY 10 +#define AT32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define AT32_ST_IRQ_PRIORITY 8 +#define AT32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define AT32_UART_USE_USART1 FALSE +#define AT32_UART_USE_USART2 FALSE +#define AT32_UART_USE_USART3 FALSE +#define AT32_UART_USE_UART4 FALSE +#define AT32_UART_USE_UART5 FALSE +#define AT32_UART_USE_USART6 FALSE +#define AT32_UART_USE_UART7 FALSE +#define AT32_UART_USE_UART8 FALSE +#define AT32_UART_USART1_DMA_PRIORITY 0 +#define AT32_UART_USART2_DMA_PRIORITY 0 +#define AT32_UART_USART3_DMA_PRIORITY 0 +#define AT32_UART_UART4_DMA_PRIORITY 0 +#define AT32_UART_UART5_DMA_PRIORITY 0 +#define AT32_UART_USART6_DMA_PRIORITY 0 +#define AT32_UART_UART7_DMA_PRIORITY 0 +#define AT32_UART_UART8_DMA_PRIORITY 0 +#define AT32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define AT32_USB_USE_OTG1 FALSE +#define AT32_USB_OTG1_IRQ_PRIORITY 14 +#define AT32_USB_OTG1_RX_FIFO_SIZE 512 + +/* + * WDG driver system settings. + */ +#define AT32_WDG_USE_WDT FALSE + +#include "config.h" + +#endif /* MCUCONF_H */ diff --git a/testhal/AT32/multi/PWM_ICU/cfg/at-start-f402/portab.c b/testhal/AT32/multi/PWM_ICU/cfg/at-start-f402/portab.c new file mode 100644 index 0000000000..b1bd7ba902 --- /dev/null +++ b/testhal/AT32/multi/PWM_ICU/cfg/at-start-f402/portab.c @@ -0,0 +1,99 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file portab.c + * @brief Application portability module code. + * + * @addtogroup application_portability + * @{ + */ + +#include "hal.h" + +#include "portab.h" + +/*===========================================================================*/ +/* Module local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module exported variables. */ +/*===========================================================================*/ + +void pwmpcb(PWMDriver *pwmp); +void pwmc1cb(PWMDriver *pwmp); + +/* + * PWM driver configuration structure. + */ +PWMConfig pwmcfg = { + 10000, /* 10kHz PWM clock frequency. */ + 10000, /* Initial PWM period 1S. */ + pwmpcb, + { + {PWM_OUTPUT_ACTIVE_HIGH, pwmc1cb}, + {PWM_OUTPUT_DISABLED, NULL}, + {PWM_OUTPUT_DISABLED, NULL}, + {PWM_OUTPUT_DISABLED, NULL} + }, + 0, + 0, + 0 +}; + +void icuwidthcb(ICUDriver *icup); +void icuperiodcb(ICUDriver *icup); +void icuovfcb(ICUDriver *icup); + +/* + * ICU driver configuration structure. + */ +ICUConfig icucfg = { + ICU_INPUT_ACTIVE_HIGH, + 10000, /* 10kHz ICU clock frequency. */ + icuwidthcb, + icuperiodcb, + NULL, + ICU_CHANNEL_1, + 0, + 0xFFFFFFFFU +}; + +/*===========================================================================*/ +/* Module local types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module exported functions. */ +/*===========================================================================*/ + +void portab_setup(void) { + palSetLineMode(LINE_ARD_D7, PAL_MODE_MUX(1)); + palSetLineMode(LINE_ARD_D12, PAL_MODE_MUX(2)); +} + +/** @} */ diff --git a/testhal/AT32/multi/PWM_ICU/cfg/at-start-f402/portab.h b/testhal/AT32/multi/PWM_ICU/cfg/at-start-f402/portab.h new file mode 100644 index 0000000000..b470c57707 --- /dev/null +++ b/testhal/AT32/multi/PWM_ICU/cfg/at-start-f402/portab.h @@ -0,0 +1,81 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file portab.h + * @brief Application portability macros and structures. + * + * @addtogroup application_portability + * @{ + */ + +#ifndef PORTAB_H +#define PORTAB_H + +/*===========================================================================*/ +/* Module constants. */ +/*===========================================================================*/ + +#define PORTAB_PWM1 PWMD1 + +#define PORTAB_ICU1 ICUD3 + +#define PORTAB_BLINK_LED1 LINE_LED_RED + +#define PORTAB_BLINK_LED2 LINE_LED_YELLOW + +#define PORTAB_BLINK_LED3 LINE_LED_GREEN + +/*===========================================================================*/ +/* Module pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +extern PWMConfig pwmcfg; +extern ICUConfig icucfg; + +#ifdef __cplusplus +extern "C" { +#endif + void portab_setup(void); +#ifdef __cplusplus +} +#endif + +/*===========================================================================*/ +/* Module inline functions. */ +/*===========================================================================*/ + +#endif /* PORTAB_H */ + +/** @} */ diff --git a/testhal/AT32/multi/PWM_ICU/cfg/at-start-f405/chconf.h b/testhal/AT32/multi/PWM_ICU/cfg/at-start-f405/chconf.h new file mode 100644 index 0000000000..56fe06776a --- /dev/null +++ b/testhal/AT32/multi/PWM_ICU/cfg/at-start-f405/chconf.h @@ -0,0 +1,842 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_7_0_ + +/*===========================================================================*/ +/** + * @name System settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Handling of instances. + * @note If enabled then threads assigned to various instances can + * interact each other using the same synchronization objects. + * If disabled then each OS instance is a separate world, no + * direct interactions are handled by the OS. + */ +#if !defined(CH_CFG_SMP_MODE) +#define CH_CFG_SMP_MODE FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_ST_RESOLUTION) +#define CH_CFG_ST_RESOLUTION 32 +#endif + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_CFG_ST_FREQUENCY) +#define CH_CFG_ST_FREQUENCY 10000 +#endif + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_INTERVALS_SIZE) +#define CH_CFG_INTERVALS_SIZE 32 +#endif + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_TIME_TYPES_SIZE) +#define CH_CFG_TIME_TYPES_SIZE 32 +#endif + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#if !defined(CH_CFG_ST_TIMEDELTA) +#define CH_CFG_ST_TIMEDELTA 2 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#if !defined(CH_CFG_TIME_QUANTUM) +#define CH_CFG_TIME_QUANTUM 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#if !defined(CH_CFG_NO_IDLE_THREAD) +#define CH_CFG_NO_IDLE_THREAD FALSE +#endif + +/** + * @brief Kernel hardening level. + * @details This option is the level of functional-safety checks enabled + * in the kerkel. The meaning is: + * - 0: No checks, maximum performance. + * - 1: Reasonable checks. + * - 2: All checks. + * . + */ +#if !defined(CH_CFG_HARDENING_LEVEL) +#define CH_CFG_HARDENING_LEVEL 0 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_OPTIMIZE_SPEED) +#define CH_CFG_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TM) +#define CH_CFG_USE_TM TRUE +#endif + +/** + * @brief Time Stamps APIs. + * @details If enabled then the time stamps APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TIMESTAMP) +#define CH_CFG_USE_TIMESTAMP TRUE +#endif + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_REGISTRY) +#define CH_CFG_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_WAITEXIT) +#define CH_CFG_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_SEMAPHORES) +#define CH_CFG_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MUTEXES) +#define CH_CFG_USE_MUTEXES TRUE +#endif + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_CONDVARS) +#define CH_CFG_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_EVENTS) +#define CH_CFG_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MESSAGES) +#define CH_CFG_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#if !defined(CH_CFG_USE_DYNAMIC) +#define CH_CFG_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name OSLIB options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_MAILBOXES) +#define CH_CFG_USE_MAILBOXES TRUE +#endif + +/** + * @brief Memory checks APIs. + * @details If enabled then the memory checks APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCHECKS) +#define CH_CFG_USE_MEMCHECKS TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCORE) +#define CH_CFG_USE_MEMCORE TRUE +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#if !defined(CH_CFG_MEMCORE_SIZE) +#define CH_CFG_MEMCORE_SIZE 0 +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_CFG_USE_HEAP) +#define CH_CFG_USE_HEAP TRUE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMPOOLS) +#define CH_CFG_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_FIFOS) +#define CH_CFG_USE_OBJ_FIFOS TRUE +#endif + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Objects Caches APIs. + * @details If enabled then the objects caches APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_CACHES) +#define CH_CFG_USE_OBJ_CACHES TRUE +#endif + +/** + * @brief Delegate threads APIs. + * @details If enabled then the delegate threads APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_DELEGATES) +#define CH_CFG_USE_DELEGATES TRUE +#endif + +/** + * @brief Jobs Queues APIs. + * @details If enabled then the jobs queues APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_JOBS) +#define CH_CFG_USE_JOBS TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_CFG_USE_FACTORY) +#define CH_CFG_USE_FACTORY TRUE +#endif + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 +#endif + +/** + * @brief Enables the registry of generic objects. + */ +#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE +#endif + +/** + * @brief Enables factory for generic buffers. + */ +#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE +#endif + +/** + * @brief Enables factory for semaphores. + */ +#if !defined(CH_CFG_FACTORY_SEMAPHORES) +#define CH_CFG_FACTORY_SEMAPHORES TRUE +#endif + +/** + * @brief Enables factory for mailboxes. + */ +#if !defined(CH_CFG_FACTORY_MAILBOXES) +#define CH_CFG_FACTORY_MAILBOXES TRUE +#endif + +/** + * @brief Enables factory for objects FIFOs. + */ +#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE +#endif + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_STATISTICS) +#define CH_DBG_STATISTICS FALSE +#endif + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_MASK) +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_ALL +#endif + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_BUFFER_SIZE) +#define CH_DBG_TRACE_BUFFER_SIZE 128 +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#if !defined(CH_DBG_THREADS_PROFILING) +#define CH_DBG_THREADS_PROFILING FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add system custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add system initialization code here.*/ \ +} + +/** + * @brief OS instance structure extension. + * @details User fields added to the end of the @p os_instance_t structure. + */ +#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS \ + /* Add OS instance custom fields here.*/ + +/** + * @brief OS instance initialization hook. + * + * @param[in] oip pointer to the @p os_instance_t structure + */ +#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) { \ + /* Add OS instance initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + * + * @param[in] ntp thread being switched in + * @param[in] otp thread being switched out + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** + * @brief Runtime Faults Collection Unit hook. + * @details This hook is invoked each time new faults are collected and stored. + */ +#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) { \ + /* Faults handling code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/testhal/AT32/multi/PWM_ICU/cfg/at-start-f405/config.h b/testhal/AT32/multi/PWM_ICU/cfg/at-start-f405/config.h new file mode 100644 index 0000000000..1e7c044f47 --- /dev/null +++ b/testhal/AT32/multi/PWM_ICU/cfg/at-start-f405/config.h @@ -0,0 +1,39 @@ +/* + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * CRC driver system settings. + */ +#define AT32_CRC_USE_CRC1 FALSE + +#define CRC_USE_DMA FALSE +#define AT32_CRC_CRC1_DMA_PRIORITY 2 +#define AT32_CRC_CRC1_IRQ_PRIORITY 5 +#define AT32_CRC_CRC1_DMA_STREAM AT32_DMA_STREAM_ID_ANY + +/* + * I2C fallback driver system settings. + */ +#define SW_I2C_USE_I2C1 FALSE +#define SW_I2C_USE_I2C2 FALSE +#define SW_I2C_USE_I2C3 FALSE +#define SW_I2C_USE_I2C4 FALSE + +/* + * Other settings. + */ +#define BOARD_OTG_VBUSIG diff --git a/testhal/AT32/multi/PWM_ICU/cfg/at-start-f405/halconf.h b/testhal/AT32/multi/PWM_ICU/cfg/at-start-f405/halconf.h new file mode 100644 index 0000000000..892ec9159c --- /dev/null +++ b/testhal/AT32/multi/PWM_ICU/cfg/at-start-f405/halconf.h @@ -0,0 +1,557 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_8_4_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the EFlash subsystem. + */ +#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__) +#define HAL_USE_EFL FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU TRUE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM TRUE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/** + * @brief Enables the WSPI subsystem. + */ +#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) +#define HAL_USE_WSPI FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS FALSE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS FALSE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Timeout before assuming a failure while waiting for card idle. + * @note Time is in milliseconds. + */ +#if !defined(MMC_IDLE_TIMEOUT_MS) || defined(__DOXYGEN__) +#define MMC_IDLE_TIMEOUT_MS 1000 +#endif + +/** + * @brief Mutual exclusion on the SPI bus. + */ +#if !defined(MMC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define MMC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SIO driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SIO_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SIO_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Support for thread synchronization API. + */ +#if !defined(SIO_USE_SYNCHRONIZATION) || defined(__DOXYGEN__) +#define SIO_USE_SYNCHRONIZATION TRUE +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 256 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 2 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Inserts an assertion on function errors before returning. + */ +#if !defined(SPI_USE_ASSERT_ON_ERROR) || defined(__DOXYGEN__) +#define SPI_USE_ASSERT_ON_ERROR TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#include "halconf_community.h" + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/testhal/AT32/multi/PWM_ICU/cfg/at-start-f405/halconf_community.h b/testhal/AT32/multi/PWM_ICU/cfg/at-start-f405/halconf_community.h new file mode 100644 index 0000000000..5a77290c71 --- /dev/null +++ b/testhal/AT32/multi/PWM_ICU/cfg/at-start-f405/halconf_community.h @@ -0,0 +1,182 @@ +/* + ChibiOS - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef HALCONF_COMMUNITY_H +#define HALCONF_COMMUNITY_H + +/** + * @brief Enables the community overlay. + */ +#if !defined(HAL_USE_COMMUNITY) || defined(__DOXYGEN__) +#define HAL_USE_COMMUNITY TRUE +#endif + +/** + * @brief Enables the FSMC subsystem. + */ +#if !defined(HAL_USE_FSMC) || defined(__DOXYGEN__) +#define HAL_USE_FSMC FALSE +#endif + +/** + * @brief Enables the NAND subsystem. + */ +#if !defined(HAL_USE_NAND) || defined(__DOXYGEN__) +#define HAL_USE_NAND FALSE +#endif + +/** + * @brief Enables the 1-wire subsystem. + */ +#if !defined(HAL_USE_ONEWIRE) || defined(__DOXYGEN__) +#define HAL_USE_ONEWIRE FALSE +#endif + +/** + * @brief Enables the EICU subsystem. + */ +#if !defined(HAL_USE_EICU) || defined(__DOXYGEN__) +#define HAL_USE_EICU FALSE +#endif + +/** + * @brief Enables the CRC subsystem. + */ +#if !defined(HAL_USE_CRC) || defined(__DOXYGEN__) +#define HAL_USE_CRC FALSE +#endif + +/** + * @brief Enables the RNG subsystem. + */ +#if !defined(HAL_USE_RNG) || defined(__DOXYGEN__) +#define HAL_USE_RNG FALSE +#endif + +/** + * @brief Enables the EEPROM subsystem. + */ +#if !defined(HAL_USE_EEPROM) || defined(__DOXYGEN__) +#define HAL_USE_EEPROM FALSE +#endif + +/** + * @brief Enables the TIMCAP subsystem. + */ +#if !defined(HAL_USE_TIMCAP) || defined(__DOXYGEN__) +#define HAL_USE_TIMCAP FALSE +#endif + +/** + * @brief Enables the COMP subsystem. + */ +#if !defined(HAL_USE_COMP) || defined(__DOXYGEN__) +#define HAL_USE_COMP FALSE +#endif + +/** + * @brief Enables the OPAMP subsystem. + */ +#if !defined(HAL_USE_OPAMP) || defined(__DOXYGEN__) +#define HAL_USE_OPAMP FALSE +#endif + +/** + * @brief Enables the QEI subsystem. + */ +#if !defined(HAL_USE_QEI) || defined(__DOXYGEN__) +#define HAL_USE_QEI FALSE +#endif + +/** + * @brief Enables the USBH subsystem. + */ +#if !defined(HAL_USE_USBH) || defined(__DOXYGEN__) +#define HAL_USE_USBH FALSE +#endif + +/** + * @brief Enables the USB_MSD subsystem. + */ +#if !defined(HAL_USE_USB_MSD) || defined(__DOXYGEN__) +#define HAL_USE_USB_MSD FALSE +#endif + +/*===========================================================================*/ +/* FSMCNAND driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the @p nandAcquireBus() and @p nanReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(NAND_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define NAND_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* 1-wire driver related settings. */ +/*===========================================================================*/ +/** + * @brief Enables strong pull up feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_STRONG_PULLUP FALSE + +/** + * @brief Enables search ROM feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_SEARCH_ROM TRUE + +/*===========================================================================*/ +/* QEI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables discard of overlow + */ +#if !defined(QEI_USE_OVERFLOW_DISCARD) || defined(__DOXYGEN__) +#define QEI_USE_OVERFLOW_DISCARD FALSE +#endif + +/** + * @brief Enables min max of overlow + */ +#if !defined(QEI_USE_OVERFLOW_MINMAX) || defined(__DOXYGEN__) +#define QEI_USE_OVERFLOW_MINMAX FALSE +#endif + +/*===========================================================================*/ +/* EEProm driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables 24xx series I2C eeprom device driver. + * @note Disabling this option saves both code and data space. + */ +#define EEPROM_USE_EE24XX FALSE + /** + * @brief Enables 25xx series SPI eeprom device driver. + * @note Disabling this option saves both code and data space. + */ +#define EEPROM_USE_EE25XX FALSE + +#endif /* HALCONF_COMMUNITY_H */ + +/** @} */ diff --git a/testhal/AT32/multi/PWM_ICU/cfg/at-start-f405/mcuconf.h b/testhal/AT32/multi/PWM_ICU/cfg/at-start-f405/mcuconf.h new file mode 100644 index 0000000000..39864f3d0b --- /dev/null +++ b/testhal/AT32/multi/PWM_ICU/cfg/at-start-f405/mcuconf.h @@ -0,0 +1,272 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef MCUCONF_H +#define MCUCONF_H + +/* + * AT32F405 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define AT32F405_MCUCONF + +/* + * General settings. + */ +#define AT32_NO_INIT FALSE + +/* + * HAL driver system settings. + */ +#define AT32_HICK_ENABLED TRUE +#define AT32_LICK_ENABLED FALSE +#define AT32_HEXT_ENABLED TRUE +#define AT32_LEXT_ENABLED FALSE +#define AT32_PLLU_ENABLED TRUE +#define AT32_SCLKSEL AT32_SCLKSEL_PLL +#define AT32_PLLRCS AT32_PLLRCS_HEXT +#define AT32_PLL_MS_VALUE 1 +#define AT32_PLL_NS_VALUE 72 +#define AT32_PLL_FP_VALUE 4 +#define AT32_PLL_FU_VALUE 18 +#define AT32_AHBDIV AT32_AHBDIV_DIV1 +#define AT32_APB1DIV AT32_APB1DIV_DIV2 +#define AT32_APB2DIV AT32_APB2DIV_DIV1 +#define AT32_HICK_TO_SCLK AT32_HICK_TO_SCLK_48M +#define AT32_HICKDIV AT32_HICKDIV_DIV1 +#define AT32_HICK_TO_SCLK_DIV AT32_HICK_TO_SCLK_DIV_DIV1 +#define AT32_HEXT_TO_SCLK_DIV AT32_HEXT_TO_SCLK_DIV_DIV1 +#define AT32_USB_CLOCK48_REQUIRED TRUE +#define AT32_PLLU_USB48_SEL AT32_PLLU_USB48_SEL_PLLU +#define AT32_CLKOUT_SEL AT32_CLKOUT_SEL_HICK +#define AT32_CLKOUTDIV1 AT32_CLKOUTDIV1_DIV1 +#define AT32_CLKOUTDIV2 AT32_CLKOUTDIV2_DIV1 +#define AT32_ERTCSEL AT32_ERTCSEL_NOCLOCK +#define AT32_ERTCDIV_VALUE 12 +#define AT32_I2SF5CLKSEL AT32_I2SF5CLKSEL_SCLK +#define AT32_PVM_ENABLE FALSE +#define AT32_PVMSEL AT32_PVMSEL_LEV1 +#define AT32_LDOOVSEL AT32_LDOOVSEL_LEV3 + +/* + * IRQ system settings. + */ +#define AT32_IRQ_EXINT0_PRIORITY 6 +#define AT32_IRQ_EXINT1_PRIORITY 6 +#define AT32_IRQ_EXINT2_PRIORITY 6 +#define AT32_IRQ_EXINT3_PRIORITY 6 +#define AT32_IRQ_EXINT4_PRIORITY 6 +#define AT32_IRQ_EXINT5_9_PRIORITY 6 +#define AT32_IRQ_EXINT10_15_PRIORITY 6 +#define AT32_IRQ_EXINT16_PRIORITY 6 +#define AT32_IRQ_EXINT17_PRIORITY 15 +#define AT32_IRQ_EXINT18_PRIORITY 6 +#define AT32_IRQ_EXINT20_PRIORITY 6 +#define AT32_IRQ_EXINT21_PRIORITY 15 +#define AT32_IRQ_EXINT22_PRIORITY 15 + +#define AT32_IRQ_TMR1_BRK_TMR9_PRIORITY 7 +#define AT32_IRQ_TMR1_OVF_TMR10_PRIORITY 7 +#define AT32_IRQ_TMR1_HALL_TMR11_PRIORITY 7 +#define AT32_IRQ_TMR1_CH_PRIORITY 7 +#define AT32_IRQ_TMR2_PRIORITY 7 +#define AT32_IRQ_TMR3_PRIORITY 7 +#define AT32_IRQ_TMR4_PRIORITY 7 +#define AT32_IRQ_TMR6_PRIORITY 7 +#define AT32_IRQ_TMR7_PRIORITY 7 +#define AT32_IRQ_TMR13_PRIORITY 7 +#define AT32_IRQ_TMR14_PRIORITY 7 + +#define AT32_IRQ_USART1_PRIORITY 12 +#define AT32_IRQ_USART2_PRIORITY 12 +#define AT32_IRQ_USART3_PRIORITY 12 +#define AT32_IRQ_UART4_PRIORITY 12 +#define AT32_IRQ_UART5_PRIORITY 12 +#define AT32_IRQ_USART6_PRIORITY 12 +#define AT32_IRQ_UART7_PRIORITY 12 +#define AT32_IRQ_UART8_PRIORITY 12 + +/* + * ADC driver system settings. + */ +#define AT32_ADC_USE_ADC1 FALSE +#define AT32_ADC_ADC1_DMA_PRIORITY 2 +#define AT32_ADC_IRQ_PRIORITY 6 +#define AT32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define AT32_ADC_ADCDIV 8 + +/* + * CAN driver system settings. + */ +#define AT32_CAN_USE_CAN1 FALSE +#define AT32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * GPT driver system settings. + */ +#define AT32_GPT_USE_TMR1 FALSE +#define AT32_GPT_USE_TMR2 FALSE +#define AT32_GPT_USE_TMR3 FALSE +#define AT32_GPT_USE_TMR4 FALSE +#define AT32_GPT_USE_TMR6 FALSE +#define AT32_GPT_USE_TMR7 FALSE +#define AT32_GPT_USE_TMR9 FALSE +#define AT32_GPT_USE_TMR10 FALSE +#define AT32_GPT_USE_TMR11 FALSE +#define AT32_GPT_USE_TMR13 FALSE +#define AT32_GPT_USE_TMR14 FALSE + +/* + * I2C driver system settings. + */ +#define AT32_I2C_USE_I2C1 FALSE +#define AT32_I2C_USE_I2C2 FALSE +#define AT32_I2C_USE_I2C3 FALSE +#define AT32_I2C_BUSY_TIMEOUT 50 +#define AT32_I2C_I2C1_DMA_PRIORITY 3 +#define AT32_I2C_I2C2_DMA_PRIORITY 3 +#define AT32_I2C_I2C3_DMA_PRIORITY 3 +#define AT32_I2C_I2C1_IRQ_PRIORITY 5 +#define AT32_I2C_I2C2_IRQ_PRIORITY 5 +#define AT32_I2C_I2C3_IRQ_PRIORITY 5 +#define AT32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define AT32_ICU_USE_TMR1 FALSE +#define AT32_ICU_USE_TMR2 FALSE +#define AT32_ICU_USE_TMR3 TRUE +#define AT32_ICU_USE_TMR4 FALSE +#define AT32_ICU_USE_TMR9 FALSE + +/* + * PWM driver system settings. + */ +#define AT32_PWM_USE_TMR1 TRUE +#define AT32_PWM_USE_TMR2 FALSE +#define AT32_PWM_USE_TMR3 FALSE +#define AT32_PWM_USE_TMR4 FALSE +#define AT32_PWM_USE_TMR9 FALSE +#define AT32_PWM_USE_TMR10 FALSE +#define AT32_PWM_USE_TMR11 FALSE +#define AT32_PWM_USE_TMR13 FALSE +#define AT32_PWM_USE_TMR14 FALSE + +/* + * RTC driver system settings. + */ +#define AT32_ERTC_DIVA_VALUE 32 +#define AT32_ERTC_DIVB_VALUE 1024 +#define AT32_ERTC_CTRL_INIT 0 +#define AT32_ERTC_TAMP_INIT 0 + +/* + * SERIAL driver system settings. + */ +#define AT32_SERIAL_USE_USART1 FALSE +#define AT32_SERIAL_USE_USART2 FALSE +#define AT32_SERIAL_USE_USART3 FALSE +#define AT32_SERIAL_USE_UART4 FALSE +#define AT32_SERIAL_USE_UART5 FALSE +#define AT32_SERIAL_USE_USART6 FALSE +#define AT32_SERIAL_USE_UART7 FALSE +#define AT32_SERIAL_USE_UART8 FALSE + +/* + * SIO driver system settings. + */ +#define AT32_SIO_USE_USART1 FALSE +#define AT32_SIO_USE_USART2 FALSE +#define AT32_SIO_USE_USART3 FALSE +#define AT32_SIO_USE_UART4 FALSE +#define AT32_SIO_USE_UART5 FALSE +#define AT32_SIO_USE_USART6 FALSE +#define AT32_SIO_USE_UART7 FALSE +#define AT32_SIO_USE_UART8 FALSE + +/* + * SPI driver system settings. + */ +#define AT32_SPI_USE_SPI1 FALSE +#define AT32_SPI_USE_SPI2 FALSE +#define AT32_SPI_USE_SPI3 FALSE +#define AT32_SPI_SPI1_DMA_PRIORITY 1 +#define AT32_SPI_SPI2_DMA_PRIORITY 1 +#define AT32_SPI_SPI3_DMA_PRIORITY 1 +#define AT32_SPI_SPI1_IRQ_PRIORITY 10 +#define AT32_SPI_SPI2_IRQ_PRIORITY 10 +#define AT32_SPI_SPI3_IRQ_PRIORITY 10 +#define AT32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define AT32_ST_IRQ_PRIORITY 8 +#define AT32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define AT32_UART_USE_USART1 FALSE +#define AT32_UART_USE_USART2 FALSE +#define AT32_UART_USE_USART3 FALSE +#define AT32_UART_USE_UART4 FALSE +#define AT32_UART_USE_UART5 FALSE +#define AT32_UART_USE_USART6 FALSE +#define AT32_UART_USE_UART7 FALSE +#define AT32_UART_USE_UART8 FALSE +#define AT32_UART_USART1_DMA_PRIORITY 0 +#define AT32_UART_USART2_DMA_PRIORITY 0 +#define AT32_UART_USART3_DMA_PRIORITY 0 +#define AT32_UART_UART4_DMA_PRIORITY 0 +#define AT32_UART_UART5_DMA_PRIORITY 0 +#define AT32_UART_USART6_DMA_PRIORITY 0 +#define AT32_UART_UART7_DMA_PRIORITY 0 +#define AT32_UART_UART8_DMA_PRIORITY 0 +#define AT32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define AT32_USB_USE_OTG1 FALSE +#define AT32_USB_USE_OTG2 FALSE +#define AT32_USB_OTG1_IRQ_PRIORITY 14 +#define AT32_USB_OTG2_IRQ_PRIORITY 14 +#define AT32_USB_OTG1_RX_FIFO_SIZE 512 +#define AT32_USB_OTG2_RX_FIFO_SIZE 1024 +#define AT32_USE_USB_OTG2_HS_DMA FALSE + +/* + * WDG driver system settings. + */ +#define AT32_WDG_USE_WDT FALSE + +#include "config.h" + +#endif /* MCUCONF_H */ diff --git a/testhal/AT32/multi/PWM_ICU/cfg/at-start-f405/portab.c b/testhal/AT32/multi/PWM_ICU/cfg/at-start-f405/portab.c new file mode 100644 index 0000000000..b1bd7ba902 --- /dev/null +++ b/testhal/AT32/multi/PWM_ICU/cfg/at-start-f405/portab.c @@ -0,0 +1,99 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file portab.c + * @brief Application portability module code. + * + * @addtogroup application_portability + * @{ + */ + +#include "hal.h" + +#include "portab.h" + +/*===========================================================================*/ +/* Module local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module exported variables. */ +/*===========================================================================*/ + +void pwmpcb(PWMDriver *pwmp); +void pwmc1cb(PWMDriver *pwmp); + +/* + * PWM driver configuration structure. + */ +PWMConfig pwmcfg = { + 10000, /* 10kHz PWM clock frequency. */ + 10000, /* Initial PWM period 1S. */ + pwmpcb, + { + {PWM_OUTPUT_ACTIVE_HIGH, pwmc1cb}, + {PWM_OUTPUT_DISABLED, NULL}, + {PWM_OUTPUT_DISABLED, NULL}, + {PWM_OUTPUT_DISABLED, NULL} + }, + 0, + 0, + 0 +}; + +void icuwidthcb(ICUDriver *icup); +void icuperiodcb(ICUDriver *icup); +void icuovfcb(ICUDriver *icup); + +/* + * ICU driver configuration structure. + */ +ICUConfig icucfg = { + ICU_INPUT_ACTIVE_HIGH, + 10000, /* 10kHz ICU clock frequency. */ + icuwidthcb, + icuperiodcb, + NULL, + ICU_CHANNEL_1, + 0, + 0xFFFFFFFFU +}; + +/*===========================================================================*/ +/* Module local types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module exported functions. */ +/*===========================================================================*/ + +void portab_setup(void) { + palSetLineMode(LINE_ARD_D7, PAL_MODE_MUX(1)); + palSetLineMode(LINE_ARD_D12, PAL_MODE_MUX(2)); +} + +/** @} */ diff --git a/testhal/AT32/multi/PWM_ICU/cfg/at-start-f405/portab.h b/testhal/AT32/multi/PWM_ICU/cfg/at-start-f405/portab.h new file mode 100644 index 0000000000..b470c57707 --- /dev/null +++ b/testhal/AT32/multi/PWM_ICU/cfg/at-start-f405/portab.h @@ -0,0 +1,81 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file portab.h + * @brief Application portability macros and structures. + * + * @addtogroup application_portability + * @{ + */ + +#ifndef PORTAB_H +#define PORTAB_H + +/*===========================================================================*/ +/* Module constants. */ +/*===========================================================================*/ + +#define PORTAB_PWM1 PWMD1 + +#define PORTAB_ICU1 ICUD3 + +#define PORTAB_BLINK_LED1 LINE_LED_RED + +#define PORTAB_BLINK_LED2 LINE_LED_YELLOW + +#define PORTAB_BLINK_LED3 LINE_LED_GREEN + +/*===========================================================================*/ +/* Module pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +extern PWMConfig pwmcfg; +extern ICUConfig icucfg; + +#ifdef __cplusplus +extern "C" { +#endif + void portab_setup(void); +#ifdef __cplusplus +} +#endif + +/*===========================================================================*/ +/* Module inline functions. */ +/*===========================================================================*/ + +#endif /* PORTAB_H */ + +/** @} */ diff --git a/testhal/AT32/multi/PWM_ICU/cfg/at-start-f415/chconf.h b/testhal/AT32/multi/PWM_ICU/cfg/at-start-f415/chconf.h index 46b3f78b68..56fe06776a 100644 --- a/testhal/AT32/multi/PWM_ICU/cfg/at-start-f415/chconf.h +++ b/testhal/AT32/multi/PWM_ICU/cfg/at-start-f415/chconf.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/testhal/AT32/multi/PWM_ICU/cfg/at-start-f415/config.h b/testhal/AT32/multi/PWM_ICU/cfg/at-start-f415/config.h index 361e185d9c..056a8f39ff 100644 --- a/testhal/AT32/multi/PWM_ICU/cfg/at-start-f415/config.h +++ b/testhal/AT32/multi/PWM_ICU/cfg/at-start-f415/config.h @@ -1,6 +1,6 @@ /* - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/testhal/AT32/multi/PWM_ICU/cfg/at-start-f415/halconf.h b/testhal/AT32/multi/PWM_ICU/cfg/at-start-f415/halconf.h index 0581c87686..892ec9159c 100644 --- a/testhal/AT32/multi/PWM_ICU/cfg/at-start-f415/halconf.h +++ b/testhal/AT32/multi/PWM_ICU/cfg/at-start-f415/halconf.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/testhal/AT32/multi/PWM_ICU/cfg/at-start-f415/halconf_community.h b/testhal/AT32/multi/PWM_ICU/cfg/at-start-f415/halconf_community.h index c43d668764..5a77290c71 100644 --- a/testhal/AT32/multi/PWM_ICU/cfg/at-start-f415/halconf_community.h +++ b/testhal/AT32/multi/PWM_ICU/cfg/at-start-f415/halconf_community.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/testhal/AT32/multi/PWM_ICU/cfg/at-start-f415/mcuconf.h b/testhal/AT32/multi/PWM_ICU/cfg/at-start-f415/mcuconf.h index 0eb2e7a407..4ae2652a32 100644 --- a/testhal/AT32/multi/PWM_ICU/cfg/at-start-f415/mcuconf.h +++ b/testhal/AT32/multi/PWM_ICU/cfg/at-start-f415/mcuconf.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -106,6 +106,7 @@ #define AT32_ADC_USE_ADC1 FALSE #define AT32_ADC_ADC1_DMA_PRIORITY 2 #define AT32_ADC_ADC1_IRQ_PRIORITY 6 +#define AT32_ADC_ADC1_DMA_IRQ_PRIORITY 6 /* * CAN driver system settings. diff --git a/testhal/AT32/multi/PWM_ICU/cfg/at-start-f415/portab.c b/testhal/AT32/multi/PWM_ICU/cfg/at-start-f415/portab.c index c3e5018c6d..571be5beba 100644 --- a/testhal/AT32/multi/PWM_ICU/cfg/at-start-f415/portab.c +++ b/testhal/AT32/multi/PWM_ICU/cfg/at-start-f415/portab.c @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -93,6 +93,7 @@ ICUConfig icucfg = { void portab_setup(void) { palSetLineMode(LINE_ARD_D7, PAL_MODE_AT32_MUX_PUSHPULL); + palSetLine(LINE_ARD_D12); } /** @} */ diff --git a/testhal/AT32/multi/PWM_ICU/cfg/at-start-f415/portab.h b/testhal/AT32/multi/PWM_ICU/cfg/at-start-f415/portab.h index 45937f93e1..b470c57707 100644 --- a/testhal/AT32/multi/PWM_ICU/cfg/at-start-f415/portab.h +++ b/testhal/AT32/multi/PWM_ICU/cfg/at-start-f415/portab.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/testhal/AT32/multi/PWM_ICU/main.c b/testhal/AT32/multi/PWM_ICU/main.c index 5efc6d1a1e..af9a6c7b1b 100644 --- a/testhal/AT32/multi/PWM_ICU/main.c +++ b/testhal/AT32/multi/PWM_ICU/main.c @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -83,17 +83,16 @@ int main(void) { pwmStart(&PORTAB_PWM1, &pwmcfg); pwmEnablePeriodicNotification(&PORTAB_PWM1); - /* - * Board-dependent setup code. - */ - portab_setup(); - /* * Starting ICU driver 3. * GPIOA6 is programmed as ICU input (channel 1 of TMR3). */ icuStart(&PORTAB_ICU1, &icucfg); - palSetLine(LINE_ARD_D12); + + /* + * Board-dependent setup code. + */ + portab_setup(); /* * Board LED is programmed as output. diff --git a/testhal/AT32/multi/PWM_ICU/make/at-start-f402.make b/testhal/AT32/multi/PWM_ICU/make/at-start-f402.make new file mode 100644 index 0000000000..c2d5988d83 --- /dev/null +++ b/testhal/AT32/multi/PWM_ICU/make/at-start-f402.make @@ -0,0 +1,196 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO). +ifeq ($(USE_LTO),) + USE_LTO = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# Enable this if you want to use bitbang I2C. +ifeq ($(USE_HAL_I2C_FALLBACK),) + USE_HAL_I2C_FALLBACK = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x400 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU (no, softfp, hard). +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# FPU-related options. +ifeq ($(USE_FPU_OPT),) + USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16 +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, target, sources and paths +# + +# Define project name here +PROJECT = ch + +# Target settings. +MCU = cortex-m4 + +# Imported source files and paths. +CHIBIOS := ../../../../../ChibiOS +CHIBIOS_CONTRIB := ../../../.. +CONFDIR := ./cfg/at-start-f402 +BUILDDIR := ./build/at-start-f402 +DEPDIR := ./.dep/at-start-f402 + +# Licensing files. +include $(CHIBIOS)/os/license/license.mk +# Startup files. +include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_at32f402.mk +# HAL-OSAL files (optional). +include $(CHIBIOS_CONTRIB)/os/hal/hal.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/AT32F402_405/platform.mk +include $(CHIBIOS_CONTRIB)/os/hal/boards/AT_START_F402/board.mk +include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMv7-M/compilers/GCC/mk/port.mk +# Auto-build files in ./source recursively. +include $(CHIBIOS)/tools/mk/autobuild.mk +# Other files (optional). +#include $(CHIBIOS)/os/test/test.mk +#include $(CHIBIOS)/test/rt/rt_test.mk +#include $(CHIBIOS)/test/oslib/oslib_test.mk + +# Define linker script file here. +LDSCRIPT= $(STARTUPLD_CONTRIB)/AT32F402xC.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(ALLCSRC) \ + $(TESTSRC) \ + $(CONFDIR)/portab.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = $(ALLCPPSRC) + +# List ASM source files here. +ASMSRC = $(ALLASMSRC) + +# List ASM with preprocessor source files here. +ASMXSRC = $(ALLXASMSRC) + +# Inclusion directories. +INCDIR = $(CONFDIR) $(ALLINC) + +# Define C warning options here. +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes + +# Define C++ warning options here. +CPPWARN = -Wall -Wextra -Wundef + +# +# Project, target, sources and paths +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user section +############################################################################## + +############################################################################## +# Common rules +# + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk +include $(RULESPATH)/arm-none-eabi.mk +include $(RULESPATH)/rules.mk + +# +# Common rules +############################################################################## + +############################################################################## +# Custom rules +# + +# +# Custom rules +############################################################################## diff --git a/testhal/AT32/multi/PWM_ICU/make/at-start-f405.make b/testhal/AT32/multi/PWM_ICU/make/at-start-f405.make new file mode 100644 index 0000000000..d3cc3ac36c --- /dev/null +++ b/testhal/AT32/multi/PWM_ICU/make/at-start-f405.make @@ -0,0 +1,196 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO). +ifeq ($(USE_LTO),) + USE_LTO = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# Enable this if you want to use bitbang I2C. +ifeq ($(USE_HAL_I2C_FALLBACK),) + USE_HAL_I2C_FALLBACK = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x400 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU (no, softfp, hard). +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# FPU-related options. +ifeq ($(USE_FPU_OPT),) + USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16 +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, target, sources and paths +# + +# Define project name here +PROJECT = ch + +# Target settings. +MCU = cortex-m4 + +# Imported source files and paths. +CHIBIOS := ../../../../../ChibiOS +CHIBIOS_CONTRIB := ../../../.. +CONFDIR := ./cfg/at-start-f405 +BUILDDIR := ./build/at-start-f405 +DEPDIR := ./.dep/at-start-f405 + +# Licensing files. +include $(CHIBIOS)/os/license/license.mk +# Startup files. +include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_at32f405.mk +# HAL-OSAL files (optional). +include $(CHIBIOS_CONTRIB)/os/hal/hal.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/AT32F402_405/platform.mk +include $(CHIBIOS_CONTRIB)/os/hal/boards/AT_START_F405/board.mk +include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMv7-M/compilers/GCC/mk/port.mk +# Auto-build files in ./source recursively. +include $(CHIBIOS)/tools/mk/autobuild.mk +# Other files (optional). +#include $(CHIBIOS)/os/test/test.mk +#include $(CHIBIOS)/test/rt/rt_test.mk +#include $(CHIBIOS)/test/oslib/oslib_test.mk + +# Define linker script file here. +LDSCRIPT= $(STARTUPLD_CONTRIB)/AT32F405xC.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(ALLCSRC) \ + $(TESTSRC) \ + $(CONFDIR)/portab.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = $(ALLCPPSRC) + +# List ASM source files here. +ASMSRC = $(ALLASMSRC) + +# List ASM with preprocessor source files here. +ASMXSRC = $(ALLXASMSRC) + +# Inclusion directories. +INCDIR = $(CONFDIR) $(ALLINC) + +# Define C warning options here. +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes + +# Define C++ warning options here. +CPPWARN = -Wall -Wextra -Wundef + +# +# Project, target, sources and paths +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user section +############################################################################## + +############################################################################## +# Common rules +# + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk +include $(RULESPATH)/arm-none-eabi.mk +include $(RULESPATH)/rules.mk + +# +# Common rules +############################################################################## + +############################################################################## +# Custom rules +# + +# +# Custom rules +############################################################################## diff --git a/testhal/AT32/multi/SDC-FATFS/cfg/at-start-f415/chconf.h b/testhal/AT32/multi/SDC-FATFS/cfg/at-start-f415/chconf.h index 46b3f78b68..56fe06776a 100644 --- a/testhal/AT32/multi/SDC-FATFS/cfg/at-start-f415/chconf.h +++ b/testhal/AT32/multi/SDC-FATFS/cfg/at-start-f415/chconf.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/testhal/AT32/multi/SDC-FATFS/cfg/at-start-f415/config.h b/testhal/AT32/multi/SDC-FATFS/cfg/at-start-f415/config.h index 361e185d9c..056a8f39ff 100644 --- a/testhal/AT32/multi/SDC-FATFS/cfg/at-start-f415/config.h +++ b/testhal/AT32/multi/SDC-FATFS/cfg/at-start-f415/config.h @@ -1,6 +1,6 @@ /* - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/testhal/AT32/multi/SDC-FATFS/cfg/at-start-f415/halconf.h b/testhal/AT32/multi/SDC-FATFS/cfg/at-start-f415/halconf.h index 825b931c85..1c115ed0e0 100644 --- a/testhal/AT32/multi/SDC-FATFS/cfg/at-start-f415/halconf.h +++ b/testhal/AT32/multi/SDC-FATFS/cfg/at-start-f415/halconf.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/testhal/AT32/multi/SDC-FATFS/cfg/at-start-f415/halconf_community.h b/testhal/AT32/multi/SDC-FATFS/cfg/at-start-f415/halconf_community.h index c43d668764..5a77290c71 100644 --- a/testhal/AT32/multi/SDC-FATFS/cfg/at-start-f415/halconf_community.h +++ b/testhal/AT32/multi/SDC-FATFS/cfg/at-start-f415/halconf_community.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/testhal/AT32/multi/SDC-FATFS/cfg/at-start-f415/mcuconf.h b/testhal/AT32/multi/SDC-FATFS/cfg/at-start-f415/mcuconf.h index a26144619e..61aa7ec5fd 100644 --- a/testhal/AT32/multi/SDC-FATFS/cfg/at-start-f415/mcuconf.h +++ b/testhal/AT32/multi/SDC-FATFS/cfg/at-start-f415/mcuconf.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -106,6 +106,7 @@ #define AT32_ADC_USE_ADC1 FALSE #define AT32_ADC_ADC1_DMA_PRIORITY 2 #define AT32_ADC_ADC1_IRQ_PRIORITY 6 +#define AT32_ADC_ADC1_DMA_IRQ_PRIORITY 6 /* * CAN driver system settings. diff --git a/testhal/AT32/multi/SDC-FATFS/cfg/at-start-f415/portab.c b/testhal/AT32/multi/SDC-FATFS/cfg/at-start-f415/portab.c index 25e871321a..ceaf0ff400 100644 --- a/testhal/AT32/multi/SDC-FATFS/cfg/at-start-f415/portab.c +++ b/testhal/AT32/multi/SDC-FATFS/cfg/at-start-f415/portab.c @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/testhal/AT32/multi/SDC-FATFS/cfg/at-start-f415/portab.h b/testhal/AT32/multi/SDC-FATFS/cfg/at-start-f415/portab.h index ccb75be217..acf5bef758 100644 --- a/testhal/AT32/multi/SDC-FATFS/cfg/at-start-f415/portab.h +++ b/testhal/AT32/multi/SDC-FATFS/cfg/at-start-f415/portab.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/testhal/AT32/multi/SDC-FATFS/main.c b/testhal/AT32/multi/SDC-FATFS/main.c index 640f41c000..34ff5f2c6e 100644 --- a/testhal/AT32/multi/SDC-FATFS/main.c +++ b/testhal/AT32/multi/SDC-FATFS/main.c @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/testhal/AT32/multi/SDC/cfg/at-start-f415/chconf.h b/testhal/AT32/multi/SDC/cfg/at-start-f415/chconf.h index 46b3f78b68..56fe06776a 100644 --- a/testhal/AT32/multi/SDC/cfg/at-start-f415/chconf.h +++ b/testhal/AT32/multi/SDC/cfg/at-start-f415/chconf.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/testhal/AT32/multi/SDC/cfg/at-start-f415/config.h b/testhal/AT32/multi/SDC/cfg/at-start-f415/config.h index 361e185d9c..056a8f39ff 100644 --- a/testhal/AT32/multi/SDC/cfg/at-start-f415/config.h +++ b/testhal/AT32/multi/SDC/cfg/at-start-f415/config.h @@ -1,6 +1,6 @@ /* - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/testhal/AT32/multi/SDC/cfg/at-start-f415/halconf.h b/testhal/AT32/multi/SDC/cfg/at-start-f415/halconf.h index 825b931c85..1c115ed0e0 100644 --- a/testhal/AT32/multi/SDC/cfg/at-start-f415/halconf.h +++ b/testhal/AT32/multi/SDC/cfg/at-start-f415/halconf.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/testhal/AT32/multi/SDC/cfg/at-start-f415/halconf_community.h b/testhal/AT32/multi/SDC/cfg/at-start-f415/halconf_community.h index c43d668764..5a77290c71 100644 --- a/testhal/AT32/multi/SDC/cfg/at-start-f415/halconf_community.h +++ b/testhal/AT32/multi/SDC/cfg/at-start-f415/halconf_community.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/testhal/AT32/multi/SDC/cfg/at-start-f415/mcuconf.h b/testhal/AT32/multi/SDC/cfg/at-start-f415/mcuconf.h index a26144619e..61aa7ec5fd 100644 --- a/testhal/AT32/multi/SDC/cfg/at-start-f415/mcuconf.h +++ b/testhal/AT32/multi/SDC/cfg/at-start-f415/mcuconf.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -106,6 +106,7 @@ #define AT32_ADC_USE_ADC1 FALSE #define AT32_ADC_ADC1_DMA_PRIORITY 2 #define AT32_ADC_ADC1_IRQ_PRIORITY 6 +#define AT32_ADC_ADC1_DMA_IRQ_PRIORITY 6 /* * CAN driver system settings. diff --git a/testhal/AT32/multi/SDC/cfg/at-start-f415/portab.c b/testhal/AT32/multi/SDC/cfg/at-start-f415/portab.c index 25e871321a..ceaf0ff400 100644 --- a/testhal/AT32/multi/SDC/cfg/at-start-f415/portab.c +++ b/testhal/AT32/multi/SDC/cfg/at-start-f415/portab.c @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/testhal/AT32/multi/SDC/cfg/at-start-f415/portab.h b/testhal/AT32/multi/SDC/cfg/at-start-f415/portab.h index ccb75be217..acf5bef758 100644 --- a/testhal/AT32/multi/SDC/cfg/at-start-f415/portab.h +++ b/testhal/AT32/multi/SDC/cfg/at-start-f415/portab.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/testhal/AT32/multi/SDC/main.c b/testhal/AT32/multi/SDC/main.c index 07de28b1bd..30b1d7f473 100644 --- a/testhal/AT32/multi/SDC/main.c +++ b/testhal/AT32/multi/SDC/main.c @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/testhal/AT32/multi/SIO/.cproject b/testhal/AT32/multi/SIO/.cproject new file mode 100644 index 0000000000..a083a058e7 --- /dev/null +++ b/testhal/AT32/multi/SIO/.cproject @@ -0,0 +1,56 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/testhal/AT32/multi/SIO/.project b/testhal/AT32/multi/SIO/.project new file mode 100644 index 0000000000..937d1ee249 --- /dev/null +++ b/testhal/AT32/multi/SIO/.project @@ -0,0 +1,78 @@ + + + AT32-SIO + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + mingw32-make + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + false + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/testhal/AT32/multi/SIO/Makefile b/testhal/AT32/multi/SIO/Makefile new file mode 100644 index 0000000000..652f718eee --- /dev/null +++ b/testhal/AT32/multi/SIO/Makefile @@ -0,0 +1,24 @@ +############################################################################## +# Multi-project makefile rules +# + +all: + @echo + @echo === Building for AT-START-F402 ===================================== + +@make --no-print-directory -f ./make/at-start-f402.make all + @echo ==================================================================== + @echo + @echo === Building for AT-START-F405 ===================================== + +@make --no-print-directory -f ./make/at-start-f405.make all + @echo ==================================================================== + @echo + +clean: + @echo + +@make --no-print-directory -f ./make/at-start-f402.make clean + @echo + +@make --no-print-directory -f ./make/at-start-f405.make clean + @echo + +# +############################################################################## diff --git a/testhal/AT32/multi/SIO/cfg/at-start-f402/chconf.h b/testhal/AT32/multi/SIO/cfg/at-start-f402/chconf.h new file mode 100644 index 0000000000..56fe06776a --- /dev/null +++ b/testhal/AT32/multi/SIO/cfg/at-start-f402/chconf.h @@ -0,0 +1,842 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_7_0_ + +/*===========================================================================*/ +/** + * @name System settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Handling of instances. + * @note If enabled then threads assigned to various instances can + * interact each other using the same synchronization objects. + * If disabled then each OS instance is a separate world, no + * direct interactions are handled by the OS. + */ +#if !defined(CH_CFG_SMP_MODE) +#define CH_CFG_SMP_MODE FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_ST_RESOLUTION) +#define CH_CFG_ST_RESOLUTION 32 +#endif + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_CFG_ST_FREQUENCY) +#define CH_CFG_ST_FREQUENCY 10000 +#endif + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_INTERVALS_SIZE) +#define CH_CFG_INTERVALS_SIZE 32 +#endif + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_TIME_TYPES_SIZE) +#define CH_CFG_TIME_TYPES_SIZE 32 +#endif + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#if !defined(CH_CFG_ST_TIMEDELTA) +#define CH_CFG_ST_TIMEDELTA 2 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#if !defined(CH_CFG_TIME_QUANTUM) +#define CH_CFG_TIME_QUANTUM 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#if !defined(CH_CFG_NO_IDLE_THREAD) +#define CH_CFG_NO_IDLE_THREAD FALSE +#endif + +/** + * @brief Kernel hardening level. + * @details This option is the level of functional-safety checks enabled + * in the kerkel. The meaning is: + * - 0: No checks, maximum performance. + * - 1: Reasonable checks. + * - 2: All checks. + * . + */ +#if !defined(CH_CFG_HARDENING_LEVEL) +#define CH_CFG_HARDENING_LEVEL 0 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_OPTIMIZE_SPEED) +#define CH_CFG_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TM) +#define CH_CFG_USE_TM TRUE +#endif + +/** + * @brief Time Stamps APIs. + * @details If enabled then the time stamps APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TIMESTAMP) +#define CH_CFG_USE_TIMESTAMP TRUE +#endif + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_REGISTRY) +#define CH_CFG_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_WAITEXIT) +#define CH_CFG_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_SEMAPHORES) +#define CH_CFG_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MUTEXES) +#define CH_CFG_USE_MUTEXES TRUE +#endif + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_CONDVARS) +#define CH_CFG_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_EVENTS) +#define CH_CFG_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MESSAGES) +#define CH_CFG_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#if !defined(CH_CFG_USE_DYNAMIC) +#define CH_CFG_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name OSLIB options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_MAILBOXES) +#define CH_CFG_USE_MAILBOXES TRUE +#endif + +/** + * @brief Memory checks APIs. + * @details If enabled then the memory checks APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCHECKS) +#define CH_CFG_USE_MEMCHECKS TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCORE) +#define CH_CFG_USE_MEMCORE TRUE +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#if !defined(CH_CFG_MEMCORE_SIZE) +#define CH_CFG_MEMCORE_SIZE 0 +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_CFG_USE_HEAP) +#define CH_CFG_USE_HEAP TRUE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMPOOLS) +#define CH_CFG_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_FIFOS) +#define CH_CFG_USE_OBJ_FIFOS TRUE +#endif + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Objects Caches APIs. + * @details If enabled then the objects caches APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_CACHES) +#define CH_CFG_USE_OBJ_CACHES TRUE +#endif + +/** + * @brief Delegate threads APIs. + * @details If enabled then the delegate threads APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_DELEGATES) +#define CH_CFG_USE_DELEGATES TRUE +#endif + +/** + * @brief Jobs Queues APIs. + * @details If enabled then the jobs queues APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_JOBS) +#define CH_CFG_USE_JOBS TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_CFG_USE_FACTORY) +#define CH_CFG_USE_FACTORY TRUE +#endif + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 +#endif + +/** + * @brief Enables the registry of generic objects. + */ +#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE +#endif + +/** + * @brief Enables factory for generic buffers. + */ +#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE +#endif + +/** + * @brief Enables factory for semaphores. + */ +#if !defined(CH_CFG_FACTORY_SEMAPHORES) +#define CH_CFG_FACTORY_SEMAPHORES TRUE +#endif + +/** + * @brief Enables factory for mailboxes. + */ +#if !defined(CH_CFG_FACTORY_MAILBOXES) +#define CH_CFG_FACTORY_MAILBOXES TRUE +#endif + +/** + * @brief Enables factory for objects FIFOs. + */ +#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE +#endif + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_STATISTICS) +#define CH_DBG_STATISTICS FALSE +#endif + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_MASK) +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_ALL +#endif + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_BUFFER_SIZE) +#define CH_DBG_TRACE_BUFFER_SIZE 128 +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#if !defined(CH_DBG_THREADS_PROFILING) +#define CH_DBG_THREADS_PROFILING FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add system custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add system initialization code here.*/ \ +} + +/** + * @brief OS instance structure extension. + * @details User fields added to the end of the @p os_instance_t structure. + */ +#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS \ + /* Add OS instance custom fields here.*/ + +/** + * @brief OS instance initialization hook. + * + * @param[in] oip pointer to the @p os_instance_t structure + */ +#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) { \ + /* Add OS instance initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + * + * @param[in] ntp thread being switched in + * @param[in] otp thread being switched out + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** + * @brief Runtime Faults Collection Unit hook. + * @details This hook is invoked each time new faults are collected and stored. + */ +#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) { \ + /* Faults handling code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/testhal/AT32/multi/SIO/cfg/at-start-f402/config.h b/testhal/AT32/multi/SIO/cfg/at-start-f402/config.h new file mode 100644 index 0000000000..1e7c044f47 --- /dev/null +++ b/testhal/AT32/multi/SIO/cfg/at-start-f402/config.h @@ -0,0 +1,39 @@ +/* + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * CRC driver system settings. + */ +#define AT32_CRC_USE_CRC1 FALSE + +#define CRC_USE_DMA FALSE +#define AT32_CRC_CRC1_DMA_PRIORITY 2 +#define AT32_CRC_CRC1_IRQ_PRIORITY 5 +#define AT32_CRC_CRC1_DMA_STREAM AT32_DMA_STREAM_ID_ANY + +/* + * I2C fallback driver system settings. + */ +#define SW_I2C_USE_I2C1 FALSE +#define SW_I2C_USE_I2C2 FALSE +#define SW_I2C_USE_I2C3 FALSE +#define SW_I2C_USE_I2C4 FALSE + +/* + * Other settings. + */ +#define BOARD_OTG_VBUSIG diff --git a/testhal/AT32/multi/SIO/cfg/at-start-f402/halconf.h b/testhal/AT32/multi/SIO/cfg/at-start-f402/halconf.h new file mode 100644 index 0000000000..8ddf72a71a --- /dev/null +++ b/testhal/AT32/multi/SIO/cfg/at-start-f402/halconf.h @@ -0,0 +1,557 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_8_4_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the EFlash subsystem. + */ +#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__) +#define HAL_USE_EFL FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO TRUE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/** + * @brief Enables the WSPI subsystem. + */ +#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) +#define HAL_USE_WSPI FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS FALSE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS FALSE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Timeout before assuming a failure while waiting for card idle. + * @note Time is in milliseconds. + */ +#if !defined(MMC_IDLE_TIMEOUT_MS) || defined(__DOXYGEN__) +#define MMC_IDLE_TIMEOUT_MS 1000 +#endif + +/** + * @brief Mutual exclusion on the SPI bus. + */ +#if !defined(MMC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define MMC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SIO driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SIO_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SIO_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Support for thread synchronization API. + */ +#if !defined(SIO_USE_SYNCHRONIZATION) || defined(__DOXYGEN__) +#define SIO_USE_SYNCHRONIZATION TRUE +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 256 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 2 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Inserts an assertion on function errors before returning. + */ +#if !defined(SPI_USE_ASSERT_ON_ERROR) || defined(__DOXYGEN__) +#define SPI_USE_ASSERT_ON_ERROR TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#include "halconf_community.h" + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/testhal/AT32/multi/SIO/cfg/at-start-f402/halconf_community.h b/testhal/AT32/multi/SIO/cfg/at-start-f402/halconf_community.h new file mode 100644 index 0000000000..5a77290c71 --- /dev/null +++ b/testhal/AT32/multi/SIO/cfg/at-start-f402/halconf_community.h @@ -0,0 +1,182 @@ +/* + ChibiOS - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef HALCONF_COMMUNITY_H +#define HALCONF_COMMUNITY_H + +/** + * @brief Enables the community overlay. + */ +#if !defined(HAL_USE_COMMUNITY) || defined(__DOXYGEN__) +#define HAL_USE_COMMUNITY TRUE +#endif + +/** + * @brief Enables the FSMC subsystem. + */ +#if !defined(HAL_USE_FSMC) || defined(__DOXYGEN__) +#define HAL_USE_FSMC FALSE +#endif + +/** + * @brief Enables the NAND subsystem. + */ +#if !defined(HAL_USE_NAND) || defined(__DOXYGEN__) +#define HAL_USE_NAND FALSE +#endif + +/** + * @brief Enables the 1-wire subsystem. + */ +#if !defined(HAL_USE_ONEWIRE) || defined(__DOXYGEN__) +#define HAL_USE_ONEWIRE FALSE +#endif + +/** + * @brief Enables the EICU subsystem. + */ +#if !defined(HAL_USE_EICU) || defined(__DOXYGEN__) +#define HAL_USE_EICU FALSE +#endif + +/** + * @brief Enables the CRC subsystem. + */ +#if !defined(HAL_USE_CRC) || defined(__DOXYGEN__) +#define HAL_USE_CRC FALSE +#endif + +/** + * @brief Enables the RNG subsystem. + */ +#if !defined(HAL_USE_RNG) || defined(__DOXYGEN__) +#define HAL_USE_RNG FALSE +#endif + +/** + * @brief Enables the EEPROM subsystem. + */ +#if !defined(HAL_USE_EEPROM) || defined(__DOXYGEN__) +#define HAL_USE_EEPROM FALSE +#endif + +/** + * @brief Enables the TIMCAP subsystem. + */ +#if !defined(HAL_USE_TIMCAP) || defined(__DOXYGEN__) +#define HAL_USE_TIMCAP FALSE +#endif + +/** + * @brief Enables the COMP subsystem. + */ +#if !defined(HAL_USE_COMP) || defined(__DOXYGEN__) +#define HAL_USE_COMP FALSE +#endif + +/** + * @brief Enables the OPAMP subsystem. + */ +#if !defined(HAL_USE_OPAMP) || defined(__DOXYGEN__) +#define HAL_USE_OPAMP FALSE +#endif + +/** + * @brief Enables the QEI subsystem. + */ +#if !defined(HAL_USE_QEI) || defined(__DOXYGEN__) +#define HAL_USE_QEI FALSE +#endif + +/** + * @brief Enables the USBH subsystem. + */ +#if !defined(HAL_USE_USBH) || defined(__DOXYGEN__) +#define HAL_USE_USBH FALSE +#endif + +/** + * @brief Enables the USB_MSD subsystem. + */ +#if !defined(HAL_USE_USB_MSD) || defined(__DOXYGEN__) +#define HAL_USE_USB_MSD FALSE +#endif + +/*===========================================================================*/ +/* FSMCNAND driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the @p nandAcquireBus() and @p nanReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(NAND_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define NAND_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* 1-wire driver related settings. */ +/*===========================================================================*/ +/** + * @brief Enables strong pull up feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_STRONG_PULLUP FALSE + +/** + * @brief Enables search ROM feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_SEARCH_ROM TRUE + +/*===========================================================================*/ +/* QEI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables discard of overlow + */ +#if !defined(QEI_USE_OVERFLOW_DISCARD) || defined(__DOXYGEN__) +#define QEI_USE_OVERFLOW_DISCARD FALSE +#endif + +/** + * @brief Enables min max of overlow + */ +#if !defined(QEI_USE_OVERFLOW_MINMAX) || defined(__DOXYGEN__) +#define QEI_USE_OVERFLOW_MINMAX FALSE +#endif + +/*===========================================================================*/ +/* EEProm driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables 24xx series I2C eeprom device driver. + * @note Disabling this option saves both code and data space. + */ +#define EEPROM_USE_EE24XX FALSE + /** + * @brief Enables 25xx series SPI eeprom device driver. + * @note Disabling this option saves both code and data space. + */ +#define EEPROM_USE_EE25XX FALSE + +#endif /* HALCONF_COMMUNITY_H */ + +/** @} */ diff --git a/testhal/AT32/multi/SIO/cfg/at-start-f402/mcuconf.h b/testhal/AT32/multi/SIO/cfg/at-start-f402/mcuconf.h new file mode 100644 index 0000000000..93644549c9 --- /dev/null +++ b/testhal/AT32/multi/SIO/cfg/at-start-f402/mcuconf.h @@ -0,0 +1,268 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef MCUCONF_H +#define MCUCONF_H + +/* + * AT32F402 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define AT32F402_MCUCONF + +/* + * General settings. + */ +#define AT32_NO_INIT FALSE + +/* + * HAL driver system settings. + */ +#define AT32_HICK_ENABLED TRUE +#define AT32_LICK_ENABLED FALSE +#define AT32_HEXT_ENABLED TRUE +#define AT32_LEXT_ENABLED FALSE +#define AT32_PLLU_ENABLED TRUE +#define AT32_SCLKSEL AT32_SCLKSEL_PLL +#define AT32_PLLRCS AT32_PLLRCS_HEXT +#define AT32_PLL_MS_VALUE 1 +#define AT32_PLL_NS_VALUE 72 +#define AT32_PLL_FP_VALUE 4 +#define AT32_PLL_FU_VALUE 18 +#define AT32_AHBDIV AT32_AHBDIV_DIV1 +#define AT32_APB1DIV AT32_APB1DIV_DIV2 +#define AT32_APB2DIV AT32_APB2DIV_DIV1 +#define AT32_HICK_TO_SCLK AT32_HICK_TO_SCLK_48M +#define AT32_HICKDIV AT32_HICKDIV_DIV1 +#define AT32_HICK_TO_SCLK_DIV AT32_HICK_TO_SCLK_DIV_DIV1 +#define AT32_HEXT_TO_SCLK_DIV AT32_HEXT_TO_SCLK_DIV_DIV1 +#define AT32_USB_CLOCK48_REQUIRED TRUE +#define AT32_PLLU_USB48_SEL AT32_PLLU_USB48_SEL_PLLU +#define AT32_CLKOUT_SEL AT32_CLKOUT_SEL_HICK +#define AT32_CLKOUTDIV1 AT32_CLKOUTDIV1_DIV1 +#define AT32_CLKOUTDIV2 AT32_CLKOUTDIV2_DIV1 +#define AT32_ERTCSEL AT32_ERTCSEL_NOCLOCK +#define AT32_ERTCDIV_VALUE 12 +#define AT32_I2SF5CLKSEL AT32_I2SF5CLKSEL_SCLK +#define AT32_PVM_ENABLE FALSE +#define AT32_PVMSEL AT32_PVMSEL_LEV1 +#define AT32_LDOOVSEL AT32_LDOOVSEL_LEV3 + +/* + * IRQ system settings. + */ +#define AT32_IRQ_EXINT0_PRIORITY 6 +#define AT32_IRQ_EXINT1_PRIORITY 6 +#define AT32_IRQ_EXINT2_PRIORITY 6 +#define AT32_IRQ_EXINT3_PRIORITY 6 +#define AT32_IRQ_EXINT4_PRIORITY 6 +#define AT32_IRQ_EXINT5_9_PRIORITY 6 +#define AT32_IRQ_EXINT10_15_PRIORITY 6 +#define AT32_IRQ_EXINT16_PRIORITY 6 +#define AT32_IRQ_EXINT17_PRIORITY 15 +#define AT32_IRQ_EXINT18_PRIORITY 6 +#define AT32_IRQ_EXINT20_PRIORITY 6 +#define AT32_IRQ_EXINT21_PRIORITY 15 +#define AT32_IRQ_EXINT22_PRIORITY 15 + +#define AT32_IRQ_TMR1_BRK_TMR9_PRIORITY 7 +#define AT32_IRQ_TMR1_OVF_TMR10_PRIORITY 7 +#define AT32_IRQ_TMR1_HALL_TMR11_PRIORITY 7 +#define AT32_IRQ_TMR1_CH_PRIORITY 7 +#define AT32_IRQ_TMR2_PRIORITY 7 +#define AT32_IRQ_TMR3_PRIORITY 7 +#define AT32_IRQ_TMR4_PRIORITY 7 +#define AT32_IRQ_TMR6_PRIORITY 7 +#define AT32_IRQ_TMR7_PRIORITY 7 +#define AT32_IRQ_TMR13_PRIORITY 7 +#define AT32_IRQ_TMR14_PRIORITY 7 + +#define AT32_IRQ_USART1_PRIORITY 12 +#define AT32_IRQ_USART2_PRIORITY 12 +#define AT32_IRQ_USART3_PRIORITY 12 +#define AT32_IRQ_UART4_PRIORITY 12 +#define AT32_IRQ_UART5_PRIORITY 12 +#define AT32_IRQ_USART6_PRIORITY 12 +#define AT32_IRQ_UART7_PRIORITY 12 +#define AT32_IRQ_UART8_PRIORITY 12 + +/* + * ADC driver system settings. + */ +#define AT32_ADC_USE_ADC1 FALSE +#define AT32_ADC_ADC1_DMA_PRIORITY 2 +#define AT32_ADC_IRQ_PRIORITY 6 +#define AT32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define AT32_ADC_ADCDIV 8 + +/* + * CAN driver system settings. + */ +#define AT32_CAN_USE_CAN1 FALSE +#define AT32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * GPT driver system settings. + */ +#define AT32_GPT_USE_TMR1 FALSE +#define AT32_GPT_USE_TMR2 FALSE +#define AT32_GPT_USE_TMR3 FALSE +#define AT32_GPT_USE_TMR4 FALSE +#define AT32_GPT_USE_TMR6 FALSE +#define AT32_GPT_USE_TMR7 FALSE +#define AT32_GPT_USE_TMR9 FALSE +#define AT32_GPT_USE_TMR10 FALSE +#define AT32_GPT_USE_TMR11 FALSE +#define AT32_GPT_USE_TMR13 FALSE +#define AT32_GPT_USE_TMR14 FALSE + +/* + * I2C driver system settings. + */ +#define AT32_I2C_USE_I2C1 FALSE +#define AT32_I2C_USE_I2C2 FALSE +#define AT32_I2C_USE_I2C3 FALSE +#define AT32_I2C_BUSY_TIMEOUT 50 +#define AT32_I2C_I2C1_DMA_PRIORITY 3 +#define AT32_I2C_I2C2_DMA_PRIORITY 3 +#define AT32_I2C_I2C3_DMA_PRIORITY 3 +#define AT32_I2C_I2C1_IRQ_PRIORITY 5 +#define AT32_I2C_I2C2_IRQ_PRIORITY 5 +#define AT32_I2C_I2C3_IRQ_PRIORITY 5 +#define AT32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define AT32_ICU_USE_TMR1 FALSE +#define AT32_ICU_USE_TMR2 FALSE +#define AT32_ICU_USE_TMR3 FALSE +#define AT32_ICU_USE_TMR4 FALSE +#define AT32_ICU_USE_TMR9 FALSE + +/* + * PWM driver system settings. + */ +#define AT32_PWM_USE_TMR1 FALSE +#define AT32_PWM_USE_TMR2 FALSE +#define AT32_PWM_USE_TMR3 FALSE +#define AT32_PWM_USE_TMR4 FALSE +#define AT32_PWM_USE_TMR9 FALSE +#define AT32_PWM_USE_TMR10 FALSE +#define AT32_PWM_USE_TMR11 FALSE +#define AT32_PWM_USE_TMR13 FALSE +#define AT32_PWM_USE_TMR14 FALSE + +/* + * RTC driver system settings. + */ +#define AT32_ERTC_DIVA_VALUE 32 +#define AT32_ERTC_DIVB_VALUE 1024 +#define AT32_ERTC_CTRL_INIT 0 +#define AT32_ERTC_TAMP_INIT 0 + +/* + * SERIAL driver system settings. + */ +#define AT32_SERIAL_USE_USART1 FALSE +#define AT32_SERIAL_USE_USART2 FALSE +#define AT32_SERIAL_USE_USART3 FALSE +#define AT32_SERIAL_USE_UART4 FALSE +#define AT32_SERIAL_USE_UART5 FALSE +#define AT32_SERIAL_USE_USART6 FALSE +#define AT32_SERIAL_USE_UART7 FALSE +#define AT32_SERIAL_USE_UART8 FALSE + +/* + * SIO driver system settings. + */ +#define AT32_SIO_USE_USART1 TRUE +#define AT32_SIO_USE_USART2 TRUE +#define AT32_SIO_USE_USART3 FALSE +#define AT32_SIO_USE_UART4 FALSE +#define AT32_SIO_USE_UART5 FALSE +#define AT32_SIO_USE_USART6 FALSE +#define AT32_SIO_USE_UART7 FALSE +#define AT32_SIO_USE_UART8 FALSE + +/* + * SPI driver system settings. + */ +#define AT32_SPI_USE_SPI1 FALSE +#define AT32_SPI_USE_SPI2 FALSE +#define AT32_SPI_USE_SPI3 FALSE +#define AT32_SPI_SPI1_DMA_PRIORITY 1 +#define AT32_SPI_SPI2_DMA_PRIORITY 1 +#define AT32_SPI_SPI3_DMA_PRIORITY 1 +#define AT32_SPI_SPI1_IRQ_PRIORITY 10 +#define AT32_SPI_SPI2_IRQ_PRIORITY 10 +#define AT32_SPI_SPI3_IRQ_PRIORITY 10 +#define AT32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define AT32_ST_IRQ_PRIORITY 8 +#define AT32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define AT32_UART_USE_USART1 FALSE +#define AT32_UART_USE_USART2 FALSE +#define AT32_UART_USE_USART3 FALSE +#define AT32_UART_USE_UART4 FALSE +#define AT32_UART_USE_UART5 FALSE +#define AT32_UART_USE_USART6 FALSE +#define AT32_UART_USE_UART7 FALSE +#define AT32_UART_USE_UART8 FALSE +#define AT32_UART_USART1_DMA_PRIORITY 0 +#define AT32_UART_USART2_DMA_PRIORITY 0 +#define AT32_UART_USART3_DMA_PRIORITY 0 +#define AT32_UART_UART4_DMA_PRIORITY 0 +#define AT32_UART_UART5_DMA_PRIORITY 0 +#define AT32_UART_USART6_DMA_PRIORITY 0 +#define AT32_UART_UART7_DMA_PRIORITY 0 +#define AT32_UART_UART8_DMA_PRIORITY 0 +#define AT32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define AT32_USB_USE_OTG1 FALSE +#define AT32_USB_OTG1_IRQ_PRIORITY 14 +#define AT32_USB_OTG1_RX_FIFO_SIZE 512 + +/* + * WDG driver system settings. + */ +#define AT32_WDG_USE_WDT FALSE + +#include "config.h" + +#endif /* MCUCONF_H */ diff --git a/testhal/AT32/multi/SIO/cfg/at-start-f402/portab.c b/testhal/AT32/multi/SIO/cfg/at-start-f402/portab.c new file mode 100644 index 0000000000..ceaf0ff400 --- /dev/null +++ b/testhal/AT32/multi/SIO/cfg/at-start-f402/portab.c @@ -0,0 +1,59 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file portab.c + * @brief Application portability module code. + * + * @addtogroup application_portability + * @{ + */ + +#include "hal.h" + +#include "portab.h" + +/*===========================================================================*/ +/* Module local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module exported functions. */ +/*===========================================================================*/ + +void portab_setup(void) { + +} + +/** @} */ diff --git a/testhal/AT32/multi/SIO/cfg/at-start-f402/portab.h b/testhal/AT32/multi/SIO/cfg/at-start-f402/portab.h new file mode 100644 index 0000000000..6c48277ad0 --- /dev/null +++ b/testhal/AT32/multi/SIO/cfg/at-start-f402/portab.h @@ -0,0 +1,76 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file portab.h + * @brief Application portability macros and structures. + * + * @addtogroup application_portability + * @{ + */ + +#ifndef PORTAB_H +#define PORTAB_H + +/*===========================================================================*/ +/* Module constants. */ +/*===========================================================================*/ + +#define PORTAB_SIO1 SIOD1 + +#define PORTAB_SIO2 SIOD2 + +#define PORTAB_LINE_BUTTON LINE_BUTTON + +#define PORTAB_BUTTON_PRESSED PAL_HIGH + +/*===========================================================================*/ +/* Module pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void portab_setup(void); +#ifdef __cplusplus +} +#endif + +/*===========================================================================*/ +/* Module inline functions. */ +/*===========================================================================*/ + +#endif /* PORTAB_H */ + +/** @} */ diff --git a/testhal/AT32/multi/SIO/cfg/at-start-f405/chconf.h b/testhal/AT32/multi/SIO/cfg/at-start-f405/chconf.h new file mode 100644 index 0000000000..56fe06776a --- /dev/null +++ b/testhal/AT32/multi/SIO/cfg/at-start-f405/chconf.h @@ -0,0 +1,842 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_7_0_ + +/*===========================================================================*/ +/** + * @name System settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Handling of instances. + * @note If enabled then threads assigned to various instances can + * interact each other using the same synchronization objects. + * If disabled then each OS instance is a separate world, no + * direct interactions are handled by the OS. + */ +#if !defined(CH_CFG_SMP_MODE) +#define CH_CFG_SMP_MODE FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_ST_RESOLUTION) +#define CH_CFG_ST_RESOLUTION 32 +#endif + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_CFG_ST_FREQUENCY) +#define CH_CFG_ST_FREQUENCY 10000 +#endif + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_INTERVALS_SIZE) +#define CH_CFG_INTERVALS_SIZE 32 +#endif + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_TIME_TYPES_SIZE) +#define CH_CFG_TIME_TYPES_SIZE 32 +#endif + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#if !defined(CH_CFG_ST_TIMEDELTA) +#define CH_CFG_ST_TIMEDELTA 2 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#if !defined(CH_CFG_TIME_QUANTUM) +#define CH_CFG_TIME_QUANTUM 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#if !defined(CH_CFG_NO_IDLE_THREAD) +#define CH_CFG_NO_IDLE_THREAD FALSE +#endif + +/** + * @brief Kernel hardening level. + * @details This option is the level of functional-safety checks enabled + * in the kerkel. The meaning is: + * - 0: No checks, maximum performance. + * - 1: Reasonable checks. + * - 2: All checks. + * . + */ +#if !defined(CH_CFG_HARDENING_LEVEL) +#define CH_CFG_HARDENING_LEVEL 0 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_OPTIMIZE_SPEED) +#define CH_CFG_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TM) +#define CH_CFG_USE_TM TRUE +#endif + +/** + * @brief Time Stamps APIs. + * @details If enabled then the time stamps APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TIMESTAMP) +#define CH_CFG_USE_TIMESTAMP TRUE +#endif + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_REGISTRY) +#define CH_CFG_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_WAITEXIT) +#define CH_CFG_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_SEMAPHORES) +#define CH_CFG_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MUTEXES) +#define CH_CFG_USE_MUTEXES TRUE +#endif + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_CONDVARS) +#define CH_CFG_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_EVENTS) +#define CH_CFG_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MESSAGES) +#define CH_CFG_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#if !defined(CH_CFG_USE_DYNAMIC) +#define CH_CFG_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name OSLIB options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_MAILBOXES) +#define CH_CFG_USE_MAILBOXES TRUE +#endif + +/** + * @brief Memory checks APIs. + * @details If enabled then the memory checks APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCHECKS) +#define CH_CFG_USE_MEMCHECKS TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCORE) +#define CH_CFG_USE_MEMCORE TRUE +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#if !defined(CH_CFG_MEMCORE_SIZE) +#define CH_CFG_MEMCORE_SIZE 0 +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_CFG_USE_HEAP) +#define CH_CFG_USE_HEAP TRUE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMPOOLS) +#define CH_CFG_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_FIFOS) +#define CH_CFG_USE_OBJ_FIFOS TRUE +#endif + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Objects Caches APIs. + * @details If enabled then the objects caches APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_CACHES) +#define CH_CFG_USE_OBJ_CACHES TRUE +#endif + +/** + * @brief Delegate threads APIs. + * @details If enabled then the delegate threads APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_DELEGATES) +#define CH_CFG_USE_DELEGATES TRUE +#endif + +/** + * @brief Jobs Queues APIs. + * @details If enabled then the jobs queues APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_JOBS) +#define CH_CFG_USE_JOBS TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_CFG_USE_FACTORY) +#define CH_CFG_USE_FACTORY TRUE +#endif + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 +#endif + +/** + * @brief Enables the registry of generic objects. + */ +#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE +#endif + +/** + * @brief Enables factory for generic buffers. + */ +#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE +#endif + +/** + * @brief Enables factory for semaphores. + */ +#if !defined(CH_CFG_FACTORY_SEMAPHORES) +#define CH_CFG_FACTORY_SEMAPHORES TRUE +#endif + +/** + * @brief Enables factory for mailboxes. + */ +#if !defined(CH_CFG_FACTORY_MAILBOXES) +#define CH_CFG_FACTORY_MAILBOXES TRUE +#endif + +/** + * @brief Enables factory for objects FIFOs. + */ +#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE +#endif + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_STATISTICS) +#define CH_DBG_STATISTICS FALSE +#endif + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_MASK) +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_ALL +#endif + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_BUFFER_SIZE) +#define CH_DBG_TRACE_BUFFER_SIZE 128 +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#if !defined(CH_DBG_THREADS_PROFILING) +#define CH_DBG_THREADS_PROFILING FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add system custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add system initialization code here.*/ \ +} + +/** + * @brief OS instance structure extension. + * @details User fields added to the end of the @p os_instance_t structure. + */ +#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS \ + /* Add OS instance custom fields here.*/ + +/** + * @brief OS instance initialization hook. + * + * @param[in] oip pointer to the @p os_instance_t structure + */ +#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) { \ + /* Add OS instance initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + * + * @param[in] ntp thread being switched in + * @param[in] otp thread being switched out + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** + * @brief Runtime Faults Collection Unit hook. + * @details This hook is invoked each time new faults are collected and stored. + */ +#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) { \ + /* Faults handling code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/testhal/AT32/multi/SIO/cfg/at-start-f405/config.h b/testhal/AT32/multi/SIO/cfg/at-start-f405/config.h new file mode 100644 index 0000000000..1e7c044f47 --- /dev/null +++ b/testhal/AT32/multi/SIO/cfg/at-start-f405/config.h @@ -0,0 +1,39 @@ +/* + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * CRC driver system settings. + */ +#define AT32_CRC_USE_CRC1 FALSE + +#define CRC_USE_DMA FALSE +#define AT32_CRC_CRC1_DMA_PRIORITY 2 +#define AT32_CRC_CRC1_IRQ_PRIORITY 5 +#define AT32_CRC_CRC1_DMA_STREAM AT32_DMA_STREAM_ID_ANY + +/* + * I2C fallback driver system settings. + */ +#define SW_I2C_USE_I2C1 FALSE +#define SW_I2C_USE_I2C2 FALSE +#define SW_I2C_USE_I2C3 FALSE +#define SW_I2C_USE_I2C4 FALSE + +/* + * Other settings. + */ +#define BOARD_OTG_VBUSIG diff --git a/testhal/AT32/multi/SIO/cfg/at-start-f405/halconf.h b/testhal/AT32/multi/SIO/cfg/at-start-f405/halconf.h new file mode 100644 index 0000000000..8ddf72a71a --- /dev/null +++ b/testhal/AT32/multi/SIO/cfg/at-start-f405/halconf.h @@ -0,0 +1,557 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_8_4_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the EFlash subsystem. + */ +#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__) +#define HAL_USE_EFL FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO TRUE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/** + * @brief Enables the WSPI subsystem. + */ +#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) +#define HAL_USE_WSPI FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS FALSE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS FALSE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Timeout before assuming a failure while waiting for card idle. + * @note Time is in milliseconds. + */ +#if !defined(MMC_IDLE_TIMEOUT_MS) || defined(__DOXYGEN__) +#define MMC_IDLE_TIMEOUT_MS 1000 +#endif + +/** + * @brief Mutual exclusion on the SPI bus. + */ +#if !defined(MMC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define MMC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SIO driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SIO_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SIO_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Support for thread synchronization API. + */ +#if !defined(SIO_USE_SYNCHRONIZATION) || defined(__DOXYGEN__) +#define SIO_USE_SYNCHRONIZATION TRUE +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 256 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 2 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Inserts an assertion on function errors before returning. + */ +#if !defined(SPI_USE_ASSERT_ON_ERROR) || defined(__DOXYGEN__) +#define SPI_USE_ASSERT_ON_ERROR TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#include "halconf_community.h" + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/testhal/AT32/multi/SIO/cfg/at-start-f405/halconf_community.h b/testhal/AT32/multi/SIO/cfg/at-start-f405/halconf_community.h new file mode 100644 index 0000000000..5a77290c71 --- /dev/null +++ b/testhal/AT32/multi/SIO/cfg/at-start-f405/halconf_community.h @@ -0,0 +1,182 @@ +/* + ChibiOS - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef HALCONF_COMMUNITY_H +#define HALCONF_COMMUNITY_H + +/** + * @brief Enables the community overlay. + */ +#if !defined(HAL_USE_COMMUNITY) || defined(__DOXYGEN__) +#define HAL_USE_COMMUNITY TRUE +#endif + +/** + * @brief Enables the FSMC subsystem. + */ +#if !defined(HAL_USE_FSMC) || defined(__DOXYGEN__) +#define HAL_USE_FSMC FALSE +#endif + +/** + * @brief Enables the NAND subsystem. + */ +#if !defined(HAL_USE_NAND) || defined(__DOXYGEN__) +#define HAL_USE_NAND FALSE +#endif + +/** + * @brief Enables the 1-wire subsystem. + */ +#if !defined(HAL_USE_ONEWIRE) || defined(__DOXYGEN__) +#define HAL_USE_ONEWIRE FALSE +#endif + +/** + * @brief Enables the EICU subsystem. + */ +#if !defined(HAL_USE_EICU) || defined(__DOXYGEN__) +#define HAL_USE_EICU FALSE +#endif + +/** + * @brief Enables the CRC subsystem. + */ +#if !defined(HAL_USE_CRC) || defined(__DOXYGEN__) +#define HAL_USE_CRC FALSE +#endif + +/** + * @brief Enables the RNG subsystem. + */ +#if !defined(HAL_USE_RNG) || defined(__DOXYGEN__) +#define HAL_USE_RNG FALSE +#endif + +/** + * @brief Enables the EEPROM subsystem. + */ +#if !defined(HAL_USE_EEPROM) || defined(__DOXYGEN__) +#define HAL_USE_EEPROM FALSE +#endif + +/** + * @brief Enables the TIMCAP subsystem. + */ +#if !defined(HAL_USE_TIMCAP) || defined(__DOXYGEN__) +#define HAL_USE_TIMCAP FALSE +#endif + +/** + * @brief Enables the COMP subsystem. + */ +#if !defined(HAL_USE_COMP) || defined(__DOXYGEN__) +#define HAL_USE_COMP FALSE +#endif + +/** + * @brief Enables the OPAMP subsystem. + */ +#if !defined(HAL_USE_OPAMP) || defined(__DOXYGEN__) +#define HAL_USE_OPAMP FALSE +#endif + +/** + * @brief Enables the QEI subsystem. + */ +#if !defined(HAL_USE_QEI) || defined(__DOXYGEN__) +#define HAL_USE_QEI FALSE +#endif + +/** + * @brief Enables the USBH subsystem. + */ +#if !defined(HAL_USE_USBH) || defined(__DOXYGEN__) +#define HAL_USE_USBH FALSE +#endif + +/** + * @brief Enables the USB_MSD subsystem. + */ +#if !defined(HAL_USE_USB_MSD) || defined(__DOXYGEN__) +#define HAL_USE_USB_MSD FALSE +#endif + +/*===========================================================================*/ +/* FSMCNAND driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the @p nandAcquireBus() and @p nanReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(NAND_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define NAND_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* 1-wire driver related settings. */ +/*===========================================================================*/ +/** + * @brief Enables strong pull up feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_STRONG_PULLUP FALSE + +/** + * @brief Enables search ROM feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_SEARCH_ROM TRUE + +/*===========================================================================*/ +/* QEI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables discard of overlow + */ +#if !defined(QEI_USE_OVERFLOW_DISCARD) || defined(__DOXYGEN__) +#define QEI_USE_OVERFLOW_DISCARD FALSE +#endif + +/** + * @brief Enables min max of overlow + */ +#if !defined(QEI_USE_OVERFLOW_MINMAX) || defined(__DOXYGEN__) +#define QEI_USE_OVERFLOW_MINMAX FALSE +#endif + +/*===========================================================================*/ +/* EEProm driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables 24xx series I2C eeprom device driver. + * @note Disabling this option saves both code and data space. + */ +#define EEPROM_USE_EE24XX FALSE + /** + * @brief Enables 25xx series SPI eeprom device driver. + * @note Disabling this option saves both code and data space. + */ +#define EEPROM_USE_EE25XX FALSE + +#endif /* HALCONF_COMMUNITY_H */ + +/** @} */ diff --git a/testhal/AT32/multi/SIO/cfg/at-start-f405/mcuconf.h b/testhal/AT32/multi/SIO/cfg/at-start-f405/mcuconf.h new file mode 100644 index 0000000000..9d8b29ed8f --- /dev/null +++ b/testhal/AT32/multi/SIO/cfg/at-start-f405/mcuconf.h @@ -0,0 +1,272 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef MCUCONF_H +#define MCUCONF_H + +/* + * AT32F405 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define AT32F405_MCUCONF + +/* + * General settings. + */ +#define AT32_NO_INIT FALSE + +/* + * HAL driver system settings. + */ +#define AT32_HICK_ENABLED TRUE +#define AT32_LICK_ENABLED FALSE +#define AT32_HEXT_ENABLED TRUE +#define AT32_LEXT_ENABLED FALSE +#define AT32_PLLU_ENABLED TRUE +#define AT32_SCLKSEL AT32_SCLKSEL_PLL +#define AT32_PLLRCS AT32_PLLRCS_HEXT +#define AT32_PLL_MS_VALUE 1 +#define AT32_PLL_NS_VALUE 72 +#define AT32_PLL_FP_VALUE 4 +#define AT32_PLL_FU_VALUE 18 +#define AT32_AHBDIV AT32_AHBDIV_DIV1 +#define AT32_APB1DIV AT32_APB1DIV_DIV2 +#define AT32_APB2DIV AT32_APB2DIV_DIV1 +#define AT32_HICK_TO_SCLK AT32_HICK_TO_SCLK_48M +#define AT32_HICKDIV AT32_HICKDIV_DIV1 +#define AT32_HICK_TO_SCLK_DIV AT32_HICK_TO_SCLK_DIV_DIV1 +#define AT32_HEXT_TO_SCLK_DIV AT32_HEXT_TO_SCLK_DIV_DIV1 +#define AT32_USB_CLOCK48_REQUIRED TRUE +#define AT32_PLLU_USB48_SEL AT32_PLLU_USB48_SEL_PLLU +#define AT32_CLKOUT_SEL AT32_CLKOUT_SEL_HICK +#define AT32_CLKOUTDIV1 AT32_CLKOUTDIV1_DIV1 +#define AT32_CLKOUTDIV2 AT32_CLKOUTDIV2_DIV1 +#define AT32_ERTCSEL AT32_ERTCSEL_NOCLOCK +#define AT32_ERTCDIV_VALUE 12 +#define AT32_I2SF5CLKSEL AT32_I2SF5CLKSEL_SCLK +#define AT32_PVM_ENABLE FALSE +#define AT32_PVMSEL AT32_PVMSEL_LEV1 +#define AT32_LDOOVSEL AT32_LDOOVSEL_LEV3 + +/* + * IRQ system settings. + */ +#define AT32_IRQ_EXINT0_PRIORITY 6 +#define AT32_IRQ_EXINT1_PRIORITY 6 +#define AT32_IRQ_EXINT2_PRIORITY 6 +#define AT32_IRQ_EXINT3_PRIORITY 6 +#define AT32_IRQ_EXINT4_PRIORITY 6 +#define AT32_IRQ_EXINT5_9_PRIORITY 6 +#define AT32_IRQ_EXINT10_15_PRIORITY 6 +#define AT32_IRQ_EXINT16_PRIORITY 6 +#define AT32_IRQ_EXINT17_PRIORITY 15 +#define AT32_IRQ_EXINT18_PRIORITY 6 +#define AT32_IRQ_EXINT20_PRIORITY 6 +#define AT32_IRQ_EXINT21_PRIORITY 15 +#define AT32_IRQ_EXINT22_PRIORITY 15 + +#define AT32_IRQ_TMR1_BRK_TMR9_PRIORITY 7 +#define AT32_IRQ_TMR1_OVF_TMR10_PRIORITY 7 +#define AT32_IRQ_TMR1_HALL_TMR11_PRIORITY 7 +#define AT32_IRQ_TMR1_CH_PRIORITY 7 +#define AT32_IRQ_TMR2_PRIORITY 7 +#define AT32_IRQ_TMR3_PRIORITY 7 +#define AT32_IRQ_TMR4_PRIORITY 7 +#define AT32_IRQ_TMR6_PRIORITY 7 +#define AT32_IRQ_TMR7_PRIORITY 7 +#define AT32_IRQ_TMR13_PRIORITY 7 +#define AT32_IRQ_TMR14_PRIORITY 7 + +#define AT32_IRQ_USART1_PRIORITY 12 +#define AT32_IRQ_USART2_PRIORITY 12 +#define AT32_IRQ_USART3_PRIORITY 12 +#define AT32_IRQ_UART4_PRIORITY 12 +#define AT32_IRQ_UART5_PRIORITY 12 +#define AT32_IRQ_USART6_PRIORITY 12 +#define AT32_IRQ_UART7_PRIORITY 12 +#define AT32_IRQ_UART8_PRIORITY 12 + +/* + * ADC driver system settings. + */ +#define AT32_ADC_USE_ADC1 FALSE +#define AT32_ADC_ADC1_DMA_PRIORITY 2 +#define AT32_ADC_IRQ_PRIORITY 6 +#define AT32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define AT32_ADC_ADCDIV 8 + +/* + * CAN driver system settings. + */ +#define AT32_CAN_USE_CAN1 FALSE +#define AT32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * GPT driver system settings. + */ +#define AT32_GPT_USE_TMR1 FALSE +#define AT32_GPT_USE_TMR2 FALSE +#define AT32_GPT_USE_TMR3 FALSE +#define AT32_GPT_USE_TMR4 FALSE +#define AT32_GPT_USE_TMR6 FALSE +#define AT32_GPT_USE_TMR7 FALSE +#define AT32_GPT_USE_TMR9 FALSE +#define AT32_GPT_USE_TMR10 FALSE +#define AT32_GPT_USE_TMR11 FALSE +#define AT32_GPT_USE_TMR13 FALSE +#define AT32_GPT_USE_TMR14 FALSE + +/* + * I2C driver system settings. + */ +#define AT32_I2C_USE_I2C1 FALSE +#define AT32_I2C_USE_I2C2 FALSE +#define AT32_I2C_USE_I2C3 FALSE +#define AT32_I2C_BUSY_TIMEOUT 50 +#define AT32_I2C_I2C1_DMA_PRIORITY 3 +#define AT32_I2C_I2C2_DMA_PRIORITY 3 +#define AT32_I2C_I2C3_DMA_PRIORITY 3 +#define AT32_I2C_I2C1_IRQ_PRIORITY 5 +#define AT32_I2C_I2C2_IRQ_PRIORITY 5 +#define AT32_I2C_I2C3_IRQ_PRIORITY 5 +#define AT32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define AT32_ICU_USE_TMR1 FALSE +#define AT32_ICU_USE_TMR2 FALSE +#define AT32_ICU_USE_TMR3 FALSE +#define AT32_ICU_USE_TMR4 FALSE +#define AT32_ICU_USE_TMR9 FALSE + +/* + * PWM driver system settings. + */ +#define AT32_PWM_USE_TMR1 FALSE +#define AT32_PWM_USE_TMR2 FALSE +#define AT32_PWM_USE_TMR3 FALSE +#define AT32_PWM_USE_TMR4 FALSE +#define AT32_PWM_USE_TMR9 FALSE +#define AT32_PWM_USE_TMR10 FALSE +#define AT32_PWM_USE_TMR11 FALSE +#define AT32_PWM_USE_TMR13 FALSE +#define AT32_PWM_USE_TMR14 FALSE + +/* + * RTC driver system settings. + */ +#define AT32_ERTC_DIVA_VALUE 32 +#define AT32_ERTC_DIVB_VALUE 1024 +#define AT32_ERTC_CTRL_INIT 0 +#define AT32_ERTC_TAMP_INIT 0 + +/* + * SERIAL driver system settings. + */ +#define AT32_SERIAL_USE_USART1 FALSE +#define AT32_SERIAL_USE_USART2 FALSE +#define AT32_SERIAL_USE_USART3 FALSE +#define AT32_SERIAL_USE_UART4 FALSE +#define AT32_SERIAL_USE_UART5 FALSE +#define AT32_SERIAL_USE_USART6 FALSE +#define AT32_SERIAL_USE_UART7 FALSE +#define AT32_SERIAL_USE_UART8 FALSE + +/* + * SIO driver system settings. + */ +#define AT32_SIO_USE_USART1 TRUE +#define AT32_SIO_USE_USART2 TRUE +#define AT32_SIO_USE_USART3 FALSE +#define AT32_SIO_USE_UART4 FALSE +#define AT32_SIO_USE_UART5 FALSE +#define AT32_SIO_USE_USART6 FALSE +#define AT32_SIO_USE_UART7 FALSE +#define AT32_SIO_USE_UART8 FALSE + +/* + * SPI driver system settings. + */ +#define AT32_SPI_USE_SPI1 FALSE +#define AT32_SPI_USE_SPI2 FALSE +#define AT32_SPI_USE_SPI3 FALSE +#define AT32_SPI_SPI1_DMA_PRIORITY 1 +#define AT32_SPI_SPI2_DMA_PRIORITY 1 +#define AT32_SPI_SPI3_DMA_PRIORITY 1 +#define AT32_SPI_SPI1_IRQ_PRIORITY 10 +#define AT32_SPI_SPI2_IRQ_PRIORITY 10 +#define AT32_SPI_SPI3_IRQ_PRIORITY 10 +#define AT32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define AT32_ST_IRQ_PRIORITY 8 +#define AT32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define AT32_UART_USE_USART1 FALSE +#define AT32_UART_USE_USART2 FALSE +#define AT32_UART_USE_USART3 FALSE +#define AT32_UART_USE_UART4 FALSE +#define AT32_UART_USE_UART5 FALSE +#define AT32_UART_USE_USART6 FALSE +#define AT32_UART_USE_UART7 FALSE +#define AT32_UART_USE_UART8 FALSE +#define AT32_UART_USART1_DMA_PRIORITY 0 +#define AT32_UART_USART2_DMA_PRIORITY 0 +#define AT32_UART_USART3_DMA_PRIORITY 0 +#define AT32_UART_UART4_DMA_PRIORITY 0 +#define AT32_UART_UART5_DMA_PRIORITY 0 +#define AT32_UART_USART6_DMA_PRIORITY 0 +#define AT32_UART_UART7_DMA_PRIORITY 0 +#define AT32_UART_UART8_DMA_PRIORITY 0 +#define AT32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define AT32_USB_USE_OTG1 FALSE +#define AT32_USB_USE_OTG2 FALSE +#define AT32_USB_OTG1_IRQ_PRIORITY 14 +#define AT32_USB_OTG2_IRQ_PRIORITY 14 +#define AT32_USB_OTG1_RX_FIFO_SIZE 512 +#define AT32_USB_OTG2_RX_FIFO_SIZE 1024 +#define AT32_USE_USB_OTG2_HS_DMA FALSE + +/* + * WDG driver system settings. + */ +#define AT32_WDG_USE_WDT FALSE + +#include "config.h" + +#endif /* MCUCONF_H */ diff --git a/testhal/AT32/multi/SIO/cfg/at-start-f405/portab.c b/testhal/AT32/multi/SIO/cfg/at-start-f405/portab.c new file mode 100644 index 0000000000..ceaf0ff400 --- /dev/null +++ b/testhal/AT32/multi/SIO/cfg/at-start-f405/portab.c @@ -0,0 +1,59 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file portab.c + * @brief Application portability module code. + * + * @addtogroup application_portability + * @{ + */ + +#include "hal.h" + +#include "portab.h" + +/*===========================================================================*/ +/* Module local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module exported functions. */ +/*===========================================================================*/ + +void portab_setup(void) { + +} + +/** @} */ diff --git a/testhal/AT32/multi/SIO/cfg/at-start-f405/portab.h b/testhal/AT32/multi/SIO/cfg/at-start-f405/portab.h new file mode 100644 index 0000000000..6c48277ad0 --- /dev/null +++ b/testhal/AT32/multi/SIO/cfg/at-start-f405/portab.h @@ -0,0 +1,76 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file portab.h + * @brief Application portability macros and structures. + * + * @addtogroup application_portability + * @{ + */ + +#ifndef PORTAB_H +#define PORTAB_H + +/*===========================================================================*/ +/* Module constants. */ +/*===========================================================================*/ + +#define PORTAB_SIO1 SIOD1 + +#define PORTAB_SIO2 SIOD2 + +#define PORTAB_LINE_BUTTON LINE_BUTTON + +#define PORTAB_BUTTON_PRESSED PAL_HIGH + +/*===========================================================================*/ +/* Module pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void portab_setup(void); +#ifdef __cplusplus +} +#endif + +/*===========================================================================*/ +/* Module inline functions. */ +/*===========================================================================*/ + +#endif /* PORTAB_H */ + +/** @} */ diff --git a/testhal/AT32/multi/SIO/main.c b/testhal/AT32/multi/SIO/main.c new file mode 100644 index 0000000000..c2a35c7afc --- /dev/null +++ b/testhal/AT32/multi/SIO/main.c @@ -0,0 +1,195 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" +#include "hal_buffered_sio.h" + +#include "portab.h" + +#include "chprintf.h" +#include "shell.h" + +static BufferedSIODriver bsio1; +static uint8_t rxbuf[32]; +static uint8_t txbuf[32]; + +/*===========================================================================*/ +/* Command line related. */ +/*===========================================================================*/ + +#define SHELL_WA_SIZE THD_WORKING_AREA_SIZE(2048) + +/* Can be measured using dd if=/dev/xxxx of=/dev/null bs=512 count=10000.*/ +static void cmd_write(BaseSequentialStream *chp, int argc, char *argv[]) { + static uint8_t buf[] = + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef" + "0123456789abcdef0123456789abcdef0123456789abcdef0123456789abcdef"; + + (void)argv; + if (argc > 0) { + chprintf(chp, "Usage: write\r\n"); + return; + } + + while (chnGetTimeout((BaseChannel *)chp, TIME_IMMEDIATE) == Q_TIMEOUT) { + chnWrite(&bsio1, buf, sizeof buf - 1); + } + chprintf(chp, "\r\n\nstopped\r\n"); +} + +static const ShellCommand commands[] = { + {"write", cmd_write}, + {NULL, NULL} +}; + +static const ShellConfig shell_cfg1 = { + (BaseSequentialStream *)&bsio1, + commands +}; + +/*===========================================================================*/ +/* Generic code. */ +/*===========================================================================*/ + +/* + * RX consumer thread, times are in milliseconds. + */ +static THD_WORKING_AREA(waThread1, 256); +static THD_FUNCTION(Thread1, arg) { + size_t n; + + (void)arg; + + chRegSetThreadName("consumer"); + + while (!chThdShouldTerminateX()) { + uint8_t buf[16]; + + n = chnReadTimeout(&PORTAB_SIO1, buf, 16, TIME_MS2I(10)); + (void) chnWriteTimeout(&PORTAB_SIO2, buf, n, TIME_MS2I(10)); + } +} + +/* + * Application entry point. + */ +int main(void) { + thread_t *tp; + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Board-dependent setup code. + */ + portab_setup(); + + /* + * Activates the SIO drivers using the default configuration. + */ + sioStart(&PORTAB_SIO2, NULL); + sioStart(&PORTAB_SIO1, NULL); + + /* + * Creates the RX consumer thread. + */ + tp = chThdCreateStatic(waThread1, sizeof(waThread1), + NORMALPRIO + 1, Thread1, NULL); + + /* + * Short TX writes. + */ + do { + char c; + + for (c = 'A'; c <= 'Z'; c++) { + chnWrite(&PORTAB_SIO1, (const uint8_t *)&c, 1); + sioSynchronizeTXEnd(&PORTAB_SIO1, TIME_INFINITE); + chThdSleepMilliseconds(10); + } + } while (palReadLine(PORTAB_LINE_BUTTON) != PORTAB_BUTTON_PRESSED); + + /* Waiting button release.*/ + while (palReadLine(PORTAB_LINE_BUTTON) == PORTAB_BUTTON_PRESSED) { + chThdSleepMilliseconds(100); + } + + /* + * Long TX writes. + */ + do { + chnWrite(&PORTAB_SIO1, (const uint8_t *)"Hello World!!!\r\n", 16); + sioSynchronizeTXEnd(&PORTAB_SIO1, TIME_INFINITE); + chThdSleepMilliseconds(100); + } while (palReadLine(PORTAB_LINE_BUTTON) != PORTAB_BUTTON_PRESSED); + + /* Waiting button release.*/ + while (palReadLine(PORTAB_LINE_BUTTON) == PORTAB_BUTTON_PRESSED) { + chThdSleepMilliseconds(100); + } + + /* + * Stopping SIOs. + */ + chThdTerminate(tp); + chThdWait(tp); + sioStop(&PORTAB_SIO2); + sioStop(&PORTAB_SIO1); + + /* + * Starting a buffered SIO, it must behave exactly as a serial driver. + */ + bsioObjectInit(&bsio1, &PORTAB_SIO2, + rxbuf, sizeof rxbuf, + txbuf, sizeof txbuf); + bsioStart(&bsio1, NULL); + + /* + * Normal main() thread activity, spawning shells. + */ + while (true) { + tp = chThdCreateFromHeap(NULL, SHELL_WA_SIZE, + "shell", NORMALPRIO + 1, + shellThread, (void *)&shell_cfg1); + chThdWait(tp); /* Waiting termination. */ + chThdSleepMilliseconds(1000); + } + return 0; +} diff --git a/testhal/AT32/multi/SIO/make/at-start-f402.make b/testhal/AT32/multi/SIO/make/at-start-f402.make new file mode 100644 index 0000000000..f4bdae9a7c --- /dev/null +++ b/testhal/AT32/multi/SIO/make/at-start-f402.make @@ -0,0 +1,199 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO). +ifeq ($(USE_LTO),) + USE_LTO = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# Enable this if you want to use bitbang I2C. +ifeq ($(USE_HAL_I2C_FALLBACK),) + USE_HAL_I2C_FALLBACK = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x400 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU (no, softfp, hard). +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# FPU-related options. +ifeq ($(USE_FPU_OPT),) + USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16 +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, target, sources and paths +# + +# Define project name here +PROJECT = ch + +# Target settings. +MCU = cortex-m4 + +# Imported source files and paths. +CHIBIOS := ../../../../../ChibiOS +CHIBIOS_CONTRIB := ../../../.. +CONFDIR := ./cfg/at-start-f402 +BUILDDIR := ./build/at-start-f402 +DEPDIR := ./.dep/at-start-f402 + +# Licensing files. +include $(CHIBIOS)/os/license/license.mk +# Startup files. +include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_at32f402.mk +# HAL-OSAL files (optional). +include $(CHIBIOS_CONTRIB)/os/hal/hal.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/AT32F402_405/platform.mk +include $(CHIBIOS_CONTRIB)/os/hal/boards/AT_START_F402/board.mk +include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk +include $(CHIBIOS)/os/hal/lib/complex/buffered_sio/hal_buffered_sio.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMv7-M/compilers/GCC/mk/port.mk +# Auto-build files in ./source recursively. +include $(CHIBIOS)/tools/mk/autobuild.mk +# Other files (optional). +include $(CHIBIOS)/os/test/test.mk +include $(CHIBIOS)/test/rt/rt_test.mk +include $(CHIBIOS)/test/oslib/oslib_test.mk +include $(CHIBIOS)/os/hal/lib/streams/streams.mk +include $(CHIBIOS)/os/various/shell/shell.mk + +# Define linker script file here. +LDSCRIPT= $(STARTUPLD_CONTRIB)/AT32F402xC.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(ALLCSRC) \ + $(TESTSRC) \ + $(CONFDIR)/portab.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = $(ALLCPPSRC) + +# List ASM source files here. +ASMSRC = $(ALLASMSRC) + +# List ASM with preprocessor source files here. +ASMXSRC = $(ALLXASMSRC) + +# Inclusion directories. +INCDIR = $(CONFDIR) $(ALLINC) $(TESTINC) + +# Define C warning options here. +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes + +# Define C++ warning options here. +CPPWARN = -Wall -Wextra -Wundef + +# +# Project, target, sources and paths +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user section +############################################################################## + +############################################################################## +# Common rules +# + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk +include $(RULESPATH)/arm-none-eabi.mk +include $(RULESPATH)/rules.mk + +# +# Common rules +############################################################################## + +############################################################################## +# Custom rules +# + +# +# Custom rules +############################################################################## diff --git a/testhal/AT32/multi/SIO/make/at-start-f405.make b/testhal/AT32/multi/SIO/make/at-start-f405.make new file mode 100644 index 0000000000..3ea2ba4bdb --- /dev/null +++ b/testhal/AT32/multi/SIO/make/at-start-f405.make @@ -0,0 +1,199 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO). +ifeq ($(USE_LTO),) + USE_LTO = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# Enable this if you want to use bitbang I2C. +ifeq ($(USE_HAL_I2C_FALLBACK),) + USE_HAL_I2C_FALLBACK = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x400 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU (no, softfp, hard). +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# FPU-related options. +ifeq ($(USE_FPU_OPT),) + USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16 +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, target, sources and paths +# + +# Define project name here +PROJECT = ch + +# Target settings. +MCU = cortex-m4 + +# Imported source files and paths. +CHIBIOS := ../../../../../ChibiOS +CHIBIOS_CONTRIB := ../../../.. +CONFDIR := ./cfg/at-start-f405 +BUILDDIR := ./build/at-start-f405 +DEPDIR := ./.dep/at-start-f405 + +# Licensing files. +include $(CHIBIOS)/os/license/license.mk +# Startup files. +include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_at32f405.mk +# HAL-OSAL files (optional). +include $(CHIBIOS_CONTRIB)/os/hal/hal.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/AT32F402_405/platform.mk +include $(CHIBIOS_CONTRIB)/os/hal/boards/AT_START_F405/board.mk +include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk +include $(CHIBIOS)/os/hal/lib/complex/buffered_sio/hal_buffered_sio.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMv7-M/compilers/GCC/mk/port.mk +# Auto-build files in ./source recursively. +include $(CHIBIOS)/tools/mk/autobuild.mk +# Other files (optional). +include $(CHIBIOS)/os/test/test.mk +include $(CHIBIOS)/test/rt/rt_test.mk +include $(CHIBIOS)/test/oslib/oslib_test.mk +include $(CHIBIOS)/os/hal/lib/streams/streams.mk +include $(CHIBIOS)/os/various/shell/shell.mk + +# Define linker script file here. +LDSCRIPT= $(STARTUPLD_CONTRIB)/AT32F405xC.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(ALLCSRC) \ + $(TESTSRC) \ + $(CONFDIR)/portab.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = $(ALLCPPSRC) + +# List ASM source files here. +ASMSRC = $(ALLASMSRC) + +# List ASM with preprocessor source files here. +ASMXSRC = $(ALLXASMSRC) + +# Inclusion directories. +INCDIR = $(CONFDIR) $(ALLINC) $(TESTINC) + +# Define C warning options here. +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes + +# Define C++ warning options here. +CPPWARN = -Wall -Wextra -Wundef + +# +# Project, target, sources and paths +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user section +############################################################################## + +############################################################################## +# Common rules +# + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk +include $(RULESPATH)/arm-none-eabi.mk +include $(RULESPATH)/rules.mk + +# +# Common rules +############################################################################## + +############################################################################## +# Custom rules +# + +# +# Custom rules +############################################################################## diff --git a/testhal/AT32/multi/UART/Makefile b/testhal/AT32/multi/UART/Makefile index c8606df05e..fdf3019a85 100644 --- a/testhal/AT32/multi/UART/Makefile +++ b/testhal/AT32/multi/UART/Makefile @@ -3,6 +3,14 @@ # all: + @echo + @echo === Building for AT-START-F402 ===================================== + +@make --no-print-directory -f ./make/at-start-f402.make all + @echo ==================================================================== + @echo + @echo === Building for AT-START-F405 ===================================== + +@make --no-print-directory -f ./make/at-start-f405.make all + @echo ==================================================================== @echo @echo === Building for AT-START-F415 ===================================== +@make --no-print-directory -f ./make/at-start-f415.make all @@ -10,6 +18,10 @@ all: @echo clean: + @echo + +@make --no-print-directory -f ./make/at-start-f402.make clean + @echo + +@make --no-print-directory -f ./make/at-start-f405.make clean @echo +@make --no-print-directory -f ./make/at-start-f415.make clean @echo diff --git a/testhal/AT32/multi/UART/cfg/at-start-f402/chconf.h b/testhal/AT32/multi/UART/cfg/at-start-f402/chconf.h new file mode 100644 index 0000000000..56fe06776a --- /dev/null +++ b/testhal/AT32/multi/UART/cfg/at-start-f402/chconf.h @@ -0,0 +1,842 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_7_0_ + +/*===========================================================================*/ +/** + * @name System settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Handling of instances. + * @note If enabled then threads assigned to various instances can + * interact each other using the same synchronization objects. + * If disabled then each OS instance is a separate world, no + * direct interactions are handled by the OS. + */ +#if !defined(CH_CFG_SMP_MODE) +#define CH_CFG_SMP_MODE FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_ST_RESOLUTION) +#define CH_CFG_ST_RESOLUTION 32 +#endif + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_CFG_ST_FREQUENCY) +#define CH_CFG_ST_FREQUENCY 10000 +#endif + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_INTERVALS_SIZE) +#define CH_CFG_INTERVALS_SIZE 32 +#endif + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_TIME_TYPES_SIZE) +#define CH_CFG_TIME_TYPES_SIZE 32 +#endif + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#if !defined(CH_CFG_ST_TIMEDELTA) +#define CH_CFG_ST_TIMEDELTA 2 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#if !defined(CH_CFG_TIME_QUANTUM) +#define CH_CFG_TIME_QUANTUM 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#if !defined(CH_CFG_NO_IDLE_THREAD) +#define CH_CFG_NO_IDLE_THREAD FALSE +#endif + +/** + * @brief Kernel hardening level. + * @details This option is the level of functional-safety checks enabled + * in the kerkel. The meaning is: + * - 0: No checks, maximum performance. + * - 1: Reasonable checks. + * - 2: All checks. + * . + */ +#if !defined(CH_CFG_HARDENING_LEVEL) +#define CH_CFG_HARDENING_LEVEL 0 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_OPTIMIZE_SPEED) +#define CH_CFG_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TM) +#define CH_CFG_USE_TM TRUE +#endif + +/** + * @brief Time Stamps APIs. + * @details If enabled then the time stamps APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TIMESTAMP) +#define CH_CFG_USE_TIMESTAMP TRUE +#endif + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_REGISTRY) +#define CH_CFG_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_WAITEXIT) +#define CH_CFG_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_SEMAPHORES) +#define CH_CFG_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MUTEXES) +#define CH_CFG_USE_MUTEXES TRUE +#endif + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_CONDVARS) +#define CH_CFG_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_EVENTS) +#define CH_CFG_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MESSAGES) +#define CH_CFG_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#if !defined(CH_CFG_USE_DYNAMIC) +#define CH_CFG_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name OSLIB options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_MAILBOXES) +#define CH_CFG_USE_MAILBOXES TRUE +#endif + +/** + * @brief Memory checks APIs. + * @details If enabled then the memory checks APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCHECKS) +#define CH_CFG_USE_MEMCHECKS TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCORE) +#define CH_CFG_USE_MEMCORE TRUE +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#if !defined(CH_CFG_MEMCORE_SIZE) +#define CH_CFG_MEMCORE_SIZE 0 +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_CFG_USE_HEAP) +#define CH_CFG_USE_HEAP TRUE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMPOOLS) +#define CH_CFG_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_FIFOS) +#define CH_CFG_USE_OBJ_FIFOS TRUE +#endif + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Objects Caches APIs. + * @details If enabled then the objects caches APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_CACHES) +#define CH_CFG_USE_OBJ_CACHES TRUE +#endif + +/** + * @brief Delegate threads APIs. + * @details If enabled then the delegate threads APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_DELEGATES) +#define CH_CFG_USE_DELEGATES TRUE +#endif + +/** + * @brief Jobs Queues APIs. + * @details If enabled then the jobs queues APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_JOBS) +#define CH_CFG_USE_JOBS TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_CFG_USE_FACTORY) +#define CH_CFG_USE_FACTORY TRUE +#endif + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 +#endif + +/** + * @brief Enables the registry of generic objects. + */ +#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE +#endif + +/** + * @brief Enables factory for generic buffers. + */ +#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE +#endif + +/** + * @brief Enables factory for semaphores. + */ +#if !defined(CH_CFG_FACTORY_SEMAPHORES) +#define CH_CFG_FACTORY_SEMAPHORES TRUE +#endif + +/** + * @brief Enables factory for mailboxes. + */ +#if !defined(CH_CFG_FACTORY_MAILBOXES) +#define CH_CFG_FACTORY_MAILBOXES TRUE +#endif + +/** + * @brief Enables factory for objects FIFOs. + */ +#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE +#endif + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_STATISTICS) +#define CH_DBG_STATISTICS FALSE +#endif + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_MASK) +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_ALL +#endif + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_BUFFER_SIZE) +#define CH_DBG_TRACE_BUFFER_SIZE 128 +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#if !defined(CH_DBG_THREADS_PROFILING) +#define CH_DBG_THREADS_PROFILING FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add system custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add system initialization code here.*/ \ +} + +/** + * @brief OS instance structure extension. + * @details User fields added to the end of the @p os_instance_t structure. + */ +#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS \ + /* Add OS instance custom fields here.*/ + +/** + * @brief OS instance initialization hook. + * + * @param[in] oip pointer to the @p os_instance_t structure + */ +#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) { \ + /* Add OS instance initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + * + * @param[in] ntp thread being switched in + * @param[in] otp thread being switched out + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** + * @brief Runtime Faults Collection Unit hook. + * @details This hook is invoked each time new faults are collected and stored. + */ +#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) { \ + /* Faults handling code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/testhal/AT32/multi/UART/cfg/at-start-f402/config.h b/testhal/AT32/multi/UART/cfg/at-start-f402/config.h new file mode 100644 index 0000000000..1e7c044f47 --- /dev/null +++ b/testhal/AT32/multi/UART/cfg/at-start-f402/config.h @@ -0,0 +1,39 @@ +/* + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * CRC driver system settings. + */ +#define AT32_CRC_USE_CRC1 FALSE + +#define CRC_USE_DMA FALSE +#define AT32_CRC_CRC1_DMA_PRIORITY 2 +#define AT32_CRC_CRC1_IRQ_PRIORITY 5 +#define AT32_CRC_CRC1_DMA_STREAM AT32_DMA_STREAM_ID_ANY + +/* + * I2C fallback driver system settings. + */ +#define SW_I2C_USE_I2C1 FALSE +#define SW_I2C_USE_I2C2 FALSE +#define SW_I2C_USE_I2C3 FALSE +#define SW_I2C_USE_I2C4 FALSE + +/* + * Other settings. + */ +#define BOARD_OTG_VBUSIG diff --git a/testhal/AT32/multi/UART/cfg/at-start-f402/halconf.h b/testhal/AT32/multi/UART/cfg/at-start-f402/halconf.h new file mode 100644 index 0000000000..476444be80 --- /dev/null +++ b/testhal/AT32/multi/UART/cfg/at-start-f402/halconf.h @@ -0,0 +1,557 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_8_4_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the EFlash subsystem. + */ +#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__) +#define HAL_USE_EFL FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART TRUE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/** + * @brief Enables the WSPI subsystem. + */ +#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) +#define HAL_USE_WSPI FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS FALSE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS FALSE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Timeout before assuming a failure while waiting for card idle. + * @note Time is in milliseconds. + */ +#if !defined(MMC_IDLE_TIMEOUT_MS) || defined(__DOXYGEN__) +#define MMC_IDLE_TIMEOUT_MS 1000 +#endif + +/** + * @brief Mutual exclusion on the SPI bus. + */ +#if !defined(MMC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define MMC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SIO driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SIO_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SIO_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Support for thread synchronization API. + */ +#if !defined(SIO_USE_SYNCHRONIZATION) || defined(__DOXYGEN__) +#define SIO_USE_SYNCHRONIZATION TRUE +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 256 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 2 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Inserts an assertion on function errors before returning. + */ +#if !defined(SPI_USE_ASSERT_ON_ERROR) || defined(__DOXYGEN__) +#define SPI_USE_ASSERT_ON_ERROR TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#include "halconf_community.h" + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/testhal/AT32/multi/UART/cfg/at-start-f402/halconf_community.h b/testhal/AT32/multi/UART/cfg/at-start-f402/halconf_community.h new file mode 100644 index 0000000000..5a77290c71 --- /dev/null +++ b/testhal/AT32/multi/UART/cfg/at-start-f402/halconf_community.h @@ -0,0 +1,182 @@ +/* + ChibiOS - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef HALCONF_COMMUNITY_H +#define HALCONF_COMMUNITY_H + +/** + * @brief Enables the community overlay. + */ +#if !defined(HAL_USE_COMMUNITY) || defined(__DOXYGEN__) +#define HAL_USE_COMMUNITY TRUE +#endif + +/** + * @brief Enables the FSMC subsystem. + */ +#if !defined(HAL_USE_FSMC) || defined(__DOXYGEN__) +#define HAL_USE_FSMC FALSE +#endif + +/** + * @brief Enables the NAND subsystem. + */ +#if !defined(HAL_USE_NAND) || defined(__DOXYGEN__) +#define HAL_USE_NAND FALSE +#endif + +/** + * @brief Enables the 1-wire subsystem. + */ +#if !defined(HAL_USE_ONEWIRE) || defined(__DOXYGEN__) +#define HAL_USE_ONEWIRE FALSE +#endif + +/** + * @brief Enables the EICU subsystem. + */ +#if !defined(HAL_USE_EICU) || defined(__DOXYGEN__) +#define HAL_USE_EICU FALSE +#endif + +/** + * @brief Enables the CRC subsystem. + */ +#if !defined(HAL_USE_CRC) || defined(__DOXYGEN__) +#define HAL_USE_CRC FALSE +#endif + +/** + * @brief Enables the RNG subsystem. + */ +#if !defined(HAL_USE_RNG) || defined(__DOXYGEN__) +#define HAL_USE_RNG FALSE +#endif + +/** + * @brief Enables the EEPROM subsystem. + */ +#if !defined(HAL_USE_EEPROM) || defined(__DOXYGEN__) +#define HAL_USE_EEPROM FALSE +#endif + +/** + * @brief Enables the TIMCAP subsystem. + */ +#if !defined(HAL_USE_TIMCAP) || defined(__DOXYGEN__) +#define HAL_USE_TIMCAP FALSE +#endif + +/** + * @brief Enables the COMP subsystem. + */ +#if !defined(HAL_USE_COMP) || defined(__DOXYGEN__) +#define HAL_USE_COMP FALSE +#endif + +/** + * @brief Enables the OPAMP subsystem. + */ +#if !defined(HAL_USE_OPAMP) || defined(__DOXYGEN__) +#define HAL_USE_OPAMP FALSE +#endif + +/** + * @brief Enables the QEI subsystem. + */ +#if !defined(HAL_USE_QEI) || defined(__DOXYGEN__) +#define HAL_USE_QEI FALSE +#endif + +/** + * @brief Enables the USBH subsystem. + */ +#if !defined(HAL_USE_USBH) || defined(__DOXYGEN__) +#define HAL_USE_USBH FALSE +#endif + +/** + * @brief Enables the USB_MSD subsystem. + */ +#if !defined(HAL_USE_USB_MSD) || defined(__DOXYGEN__) +#define HAL_USE_USB_MSD FALSE +#endif + +/*===========================================================================*/ +/* FSMCNAND driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the @p nandAcquireBus() and @p nanReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(NAND_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define NAND_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* 1-wire driver related settings. */ +/*===========================================================================*/ +/** + * @brief Enables strong pull up feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_STRONG_PULLUP FALSE + +/** + * @brief Enables search ROM feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_SEARCH_ROM TRUE + +/*===========================================================================*/ +/* QEI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables discard of overlow + */ +#if !defined(QEI_USE_OVERFLOW_DISCARD) || defined(__DOXYGEN__) +#define QEI_USE_OVERFLOW_DISCARD FALSE +#endif + +/** + * @brief Enables min max of overlow + */ +#if !defined(QEI_USE_OVERFLOW_MINMAX) || defined(__DOXYGEN__) +#define QEI_USE_OVERFLOW_MINMAX FALSE +#endif + +/*===========================================================================*/ +/* EEProm driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables 24xx series I2C eeprom device driver. + * @note Disabling this option saves both code and data space. + */ +#define EEPROM_USE_EE24XX FALSE + /** + * @brief Enables 25xx series SPI eeprom device driver. + * @note Disabling this option saves both code and data space. + */ +#define EEPROM_USE_EE25XX FALSE + +#endif /* HALCONF_COMMUNITY_H */ + +/** @} */ diff --git a/testhal/AT32/multi/UART/cfg/at-start-f402/mcuconf.h b/testhal/AT32/multi/UART/cfg/at-start-f402/mcuconf.h new file mode 100644 index 0000000000..c4787f773c --- /dev/null +++ b/testhal/AT32/multi/UART/cfg/at-start-f402/mcuconf.h @@ -0,0 +1,268 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef MCUCONF_H +#define MCUCONF_H + +/* + * AT32F402 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define AT32F402_MCUCONF + +/* + * General settings. + */ +#define AT32_NO_INIT FALSE + +/* + * HAL driver system settings. + */ +#define AT32_HICK_ENABLED TRUE +#define AT32_LICK_ENABLED FALSE +#define AT32_HEXT_ENABLED TRUE +#define AT32_LEXT_ENABLED FALSE +#define AT32_PLLU_ENABLED TRUE +#define AT32_SCLKSEL AT32_SCLKSEL_PLL +#define AT32_PLLRCS AT32_PLLRCS_HEXT +#define AT32_PLL_MS_VALUE 1 +#define AT32_PLL_NS_VALUE 72 +#define AT32_PLL_FP_VALUE 4 +#define AT32_PLL_FU_VALUE 18 +#define AT32_AHBDIV AT32_AHBDIV_DIV1 +#define AT32_APB1DIV AT32_APB1DIV_DIV2 +#define AT32_APB2DIV AT32_APB2DIV_DIV1 +#define AT32_HICK_TO_SCLK AT32_HICK_TO_SCLK_48M +#define AT32_HICKDIV AT32_HICKDIV_DIV1 +#define AT32_HICK_TO_SCLK_DIV AT32_HICK_TO_SCLK_DIV_DIV1 +#define AT32_HEXT_TO_SCLK_DIV AT32_HEXT_TO_SCLK_DIV_DIV1 +#define AT32_USB_CLOCK48_REQUIRED TRUE +#define AT32_PLLU_USB48_SEL AT32_PLLU_USB48_SEL_PLLU +#define AT32_CLKOUT_SEL AT32_CLKOUT_SEL_HICK +#define AT32_CLKOUTDIV1 AT32_CLKOUTDIV1_DIV1 +#define AT32_CLKOUTDIV2 AT32_CLKOUTDIV2_DIV1 +#define AT32_ERTCSEL AT32_ERTCSEL_NOCLOCK +#define AT32_ERTCDIV_VALUE 12 +#define AT32_I2SF5CLKSEL AT32_I2SF5CLKSEL_SCLK +#define AT32_PVM_ENABLE FALSE +#define AT32_PVMSEL AT32_PVMSEL_LEV1 +#define AT32_LDOOVSEL AT32_LDOOVSEL_LEV3 + +/* + * IRQ system settings. + */ +#define AT32_IRQ_EXINT0_PRIORITY 6 +#define AT32_IRQ_EXINT1_PRIORITY 6 +#define AT32_IRQ_EXINT2_PRIORITY 6 +#define AT32_IRQ_EXINT3_PRIORITY 6 +#define AT32_IRQ_EXINT4_PRIORITY 6 +#define AT32_IRQ_EXINT5_9_PRIORITY 6 +#define AT32_IRQ_EXINT10_15_PRIORITY 6 +#define AT32_IRQ_EXINT16_PRIORITY 6 +#define AT32_IRQ_EXINT17_PRIORITY 15 +#define AT32_IRQ_EXINT18_PRIORITY 6 +#define AT32_IRQ_EXINT20_PRIORITY 6 +#define AT32_IRQ_EXINT21_PRIORITY 15 +#define AT32_IRQ_EXINT22_PRIORITY 15 + +#define AT32_IRQ_TMR1_BRK_TMR9_PRIORITY 7 +#define AT32_IRQ_TMR1_OVF_TMR10_PRIORITY 7 +#define AT32_IRQ_TMR1_HALL_TMR11_PRIORITY 7 +#define AT32_IRQ_TMR1_CH_PRIORITY 7 +#define AT32_IRQ_TMR2_PRIORITY 7 +#define AT32_IRQ_TMR3_PRIORITY 7 +#define AT32_IRQ_TMR4_PRIORITY 7 +#define AT32_IRQ_TMR6_PRIORITY 7 +#define AT32_IRQ_TMR7_PRIORITY 7 +#define AT32_IRQ_TMR13_PRIORITY 7 +#define AT32_IRQ_TMR14_PRIORITY 7 + +#define AT32_IRQ_USART1_PRIORITY 12 +#define AT32_IRQ_USART2_PRIORITY 12 +#define AT32_IRQ_USART3_PRIORITY 12 +#define AT32_IRQ_UART4_PRIORITY 12 +#define AT32_IRQ_UART5_PRIORITY 12 +#define AT32_IRQ_USART6_PRIORITY 12 +#define AT32_IRQ_UART7_PRIORITY 12 +#define AT32_IRQ_UART8_PRIORITY 12 + +/* + * ADC driver system settings. + */ +#define AT32_ADC_USE_ADC1 FALSE +#define AT32_ADC_ADC1_DMA_PRIORITY 2 +#define AT32_ADC_IRQ_PRIORITY 6 +#define AT32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define AT32_ADC_ADCDIV 8 + +/* + * CAN driver system settings. + */ +#define AT32_CAN_USE_CAN1 FALSE +#define AT32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * GPT driver system settings. + */ +#define AT32_GPT_USE_TMR1 FALSE +#define AT32_GPT_USE_TMR2 FALSE +#define AT32_GPT_USE_TMR3 FALSE +#define AT32_GPT_USE_TMR4 FALSE +#define AT32_GPT_USE_TMR6 FALSE +#define AT32_GPT_USE_TMR7 FALSE +#define AT32_GPT_USE_TMR9 FALSE +#define AT32_GPT_USE_TMR10 FALSE +#define AT32_GPT_USE_TMR11 FALSE +#define AT32_GPT_USE_TMR13 FALSE +#define AT32_GPT_USE_TMR14 FALSE + +/* + * I2C driver system settings. + */ +#define AT32_I2C_USE_I2C1 FALSE +#define AT32_I2C_USE_I2C2 FALSE +#define AT32_I2C_USE_I2C3 FALSE +#define AT32_I2C_BUSY_TIMEOUT 50 +#define AT32_I2C_I2C1_DMA_PRIORITY 3 +#define AT32_I2C_I2C2_DMA_PRIORITY 3 +#define AT32_I2C_I2C3_DMA_PRIORITY 3 +#define AT32_I2C_I2C1_IRQ_PRIORITY 5 +#define AT32_I2C_I2C2_IRQ_PRIORITY 5 +#define AT32_I2C_I2C3_IRQ_PRIORITY 5 +#define AT32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define AT32_ICU_USE_TMR1 FALSE +#define AT32_ICU_USE_TMR2 FALSE +#define AT32_ICU_USE_TMR3 FALSE +#define AT32_ICU_USE_TMR4 FALSE +#define AT32_ICU_USE_TMR9 FALSE + +/* + * PWM driver system settings. + */ +#define AT32_PWM_USE_TMR1 FALSE +#define AT32_PWM_USE_TMR2 FALSE +#define AT32_PWM_USE_TMR3 FALSE +#define AT32_PWM_USE_TMR4 FALSE +#define AT32_PWM_USE_TMR9 FALSE +#define AT32_PWM_USE_TMR10 FALSE +#define AT32_PWM_USE_TMR11 FALSE +#define AT32_PWM_USE_TMR13 FALSE +#define AT32_PWM_USE_TMR14 FALSE + +/* + * RTC driver system settings. + */ +#define AT32_ERTC_DIVA_VALUE 32 +#define AT32_ERTC_DIVB_VALUE 1024 +#define AT32_ERTC_CTRL_INIT 0 +#define AT32_ERTC_TAMP_INIT 0 + +/* + * SERIAL driver system settings. + */ +#define AT32_SERIAL_USE_USART1 FALSE +#define AT32_SERIAL_USE_USART2 FALSE +#define AT32_SERIAL_USE_USART3 FALSE +#define AT32_SERIAL_USE_UART4 FALSE +#define AT32_SERIAL_USE_UART5 FALSE +#define AT32_SERIAL_USE_USART6 FALSE +#define AT32_SERIAL_USE_UART7 FALSE +#define AT32_SERIAL_USE_UART8 FALSE + +/* + * SIO driver system settings. + */ +#define AT32_SIO_USE_USART1 FALSE +#define AT32_SIO_USE_USART2 FALSE +#define AT32_SIO_USE_USART3 FALSE +#define AT32_SIO_USE_UART4 FALSE +#define AT32_SIO_USE_UART5 FALSE +#define AT32_SIO_USE_USART6 FALSE +#define AT32_SIO_USE_UART7 FALSE +#define AT32_SIO_USE_UART8 FALSE + +/* + * SPI driver system settings. + */ +#define AT32_SPI_USE_SPI1 FALSE +#define AT32_SPI_USE_SPI2 FALSE +#define AT32_SPI_USE_SPI3 FALSE +#define AT32_SPI_SPI1_DMA_PRIORITY 1 +#define AT32_SPI_SPI2_DMA_PRIORITY 1 +#define AT32_SPI_SPI3_DMA_PRIORITY 1 +#define AT32_SPI_SPI1_IRQ_PRIORITY 10 +#define AT32_SPI_SPI2_IRQ_PRIORITY 10 +#define AT32_SPI_SPI3_IRQ_PRIORITY 10 +#define AT32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define AT32_ST_IRQ_PRIORITY 8 +#define AT32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define AT32_UART_USE_USART1 TRUE +#define AT32_UART_USE_USART2 FALSE +#define AT32_UART_USE_USART3 FALSE +#define AT32_UART_USE_UART4 FALSE +#define AT32_UART_USE_UART5 FALSE +#define AT32_UART_USE_USART6 FALSE +#define AT32_UART_USE_UART7 FALSE +#define AT32_UART_USE_UART8 FALSE +#define AT32_UART_USART1_DMA_PRIORITY 0 +#define AT32_UART_USART2_DMA_PRIORITY 0 +#define AT32_UART_USART3_DMA_PRIORITY 0 +#define AT32_UART_UART4_DMA_PRIORITY 0 +#define AT32_UART_UART5_DMA_PRIORITY 0 +#define AT32_UART_USART6_DMA_PRIORITY 0 +#define AT32_UART_UART7_DMA_PRIORITY 0 +#define AT32_UART_UART8_DMA_PRIORITY 0 +#define AT32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define AT32_USB_USE_OTG1 FALSE +#define AT32_USB_OTG1_IRQ_PRIORITY 14 +#define AT32_USB_OTG1_RX_FIFO_SIZE 512 + +/* + * WDG driver system settings. + */ +#define AT32_WDG_USE_WDT FALSE + +#include "config.h" + +#endif /* MCUCONF_H */ diff --git a/testhal/AT32/multi/UART/cfg/at-start-f402/portab.c b/testhal/AT32/multi/UART/cfg/at-start-f402/portab.c new file mode 100644 index 0000000000..c61b6ed4be --- /dev/null +++ b/testhal/AT32/multi/UART/cfg/at-start-f402/portab.c @@ -0,0 +1,82 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file portab.c + * @brief Application portability module code. + * + * @addtogroup application_portability + * @{ + */ + +#include "hal.h" + +#include "portab.h" + +/*===========================================================================*/ +/* Module local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module exported variables. */ +/*===========================================================================*/ + +void txend1(UARTDriver *uartp); +void txend2(UARTDriver *uartp); +void rxend(UARTDriver *uartp); +void rxchar(UARTDriver *uartp, uint16_t c); +void rxerr(UARTDriver *uartp, uartflags_t e); + +/* + * UART driver configuration structure. + */ +UARTConfig uartcfg = { + txend1, + txend2, + rxend, + rxchar, + rxerr, + NULL, + 0, + 38400, + 0, + USART_CTRL2_LINEN, + 0 +}; + +/*===========================================================================*/ +/* Module local types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module exported functions. */ +/*===========================================================================*/ + +void portab_setup(void) { + +} + +/** @} */ diff --git a/testhal/AT32/multi/UART/cfg/at-start-f402/portab.h b/testhal/AT32/multi/UART/cfg/at-start-f402/portab.h new file mode 100644 index 0000000000..35724bce27 --- /dev/null +++ b/testhal/AT32/multi/UART/cfg/at-start-f402/portab.h @@ -0,0 +1,78 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file portab.h + * @brief Application portability macros and structures. + * + * @addtogroup application_portability + * @{ + */ + +#ifndef PORTAB_H +#define PORTAB_H + +/*===========================================================================*/ +/* Module constants. */ +/*===========================================================================*/ + +#define PORTAB_UART1 UARTD1 + +#define PORTAB_BLINK_LED1 LINE_LED_RED + +#define PORTAB_BLINK_LED2 LINE_LED_YELLOW + +#define PORTAB_BLINK_LED3 LINE_LED_GREEN + +/*===========================================================================*/ +/* Module pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +extern UARTConfig uartcfg; + +#ifdef __cplusplus +extern "C" { +#endif + void portab_setup(void); +#ifdef __cplusplus +} +#endif + +/*===========================================================================*/ +/* Module inline functions. */ +/*===========================================================================*/ + +#endif /* PORTAB_H */ + +/** @} */ diff --git a/testhal/AT32/multi/UART/cfg/at-start-f405/chconf.h b/testhal/AT32/multi/UART/cfg/at-start-f405/chconf.h new file mode 100644 index 0000000000..56fe06776a --- /dev/null +++ b/testhal/AT32/multi/UART/cfg/at-start-f405/chconf.h @@ -0,0 +1,842 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_7_0_ + +/*===========================================================================*/ +/** + * @name System settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Handling of instances. + * @note If enabled then threads assigned to various instances can + * interact each other using the same synchronization objects. + * If disabled then each OS instance is a separate world, no + * direct interactions are handled by the OS. + */ +#if !defined(CH_CFG_SMP_MODE) +#define CH_CFG_SMP_MODE FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_ST_RESOLUTION) +#define CH_CFG_ST_RESOLUTION 32 +#endif + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_CFG_ST_FREQUENCY) +#define CH_CFG_ST_FREQUENCY 10000 +#endif + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_INTERVALS_SIZE) +#define CH_CFG_INTERVALS_SIZE 32 +#endif + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_TIME_TYPES_SIZE) +#define CH_CFG_TIME_TYPES_SIZE 32 +#endif + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#if !defined(CH_CFG_ST_TIMEDELTA) +#define CH_CFG_ST_TIMEDELTA 2 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#if !defined(CH_CFG_TIME_QUANTUM) +#define CH_CFG_TIME_QUANTUM 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#if !defined(CH_CFG_NO_IDLE_THREAD) +#define CH_CFG_NO_IDLE_THREAD FALSE +#endif + +/** + * @brief Kernel hardening level. + * @details This option is the level of functional-safety checks enabled + * in the kerkel. The meaning is: + * - 0: No checks, maximum performance. + * - 1: Reasonable checks. + * - 2: All checks. + * . + */ +#if !defined(CH_CFG_HARDENING_LEVEL) +#define CH_CFG_HARDENING_LEVEL 0 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_OPTIMIZE_SPEED) +#define CH_CFG_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TM) +#define CH_CFG_USE_TM TRUE +#endif + +/** + * @brief Time Stamps APIs. + * @details If enabled then the time stamps APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TIMESTAMP) +#define CH_CFG_USE_TIMESTAMP TRUE +#endif + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_REGISTRY) +#define CH_CFG_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_WAITEXIT) +#define CH_CFG_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_SEMAPHORES) +#define CH_CFG_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MUTEXES) +#define CH_CFG_USE_MUTEXES TRUE +#endif + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_CONDVARS) +#define CH_CFG_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_EVENTS) +#define CH_CFG_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MESSAGES) +#define CH_CFG_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#if !defined(CH_CFG_USE_DYNAMIC) +#define CH_CFG_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name OSLIB options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_MAILBOXES) +#define CH_CFG_USE_MAILBOXES TRUE +#endif + +/** + * @brief Memory checks APIs. + * @details If enabled then the memory checks APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCHECKS) +#define CH_CFG_USE_MEMCHECKS TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCORE) +#define CH_CFG_USE_MEMCORE TRUE +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#if !defined(CH_CFG_MEMCORE_SIZE) +#define CH_CFG_MEMCORE_SIZE 0 +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_CFG_USE_HEAP) +#define CH_CFG_USE_HEAP TRUE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMPOOLS) +#define CH_CFG_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_FIFOS) +#define CH_CFG_USE_OBJ_FIFOS TRUE +#endif + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Objects Caches APIs. + * @details If enabled then the objects caches APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_CACHES) +#define CH_CFG_USE_OBJ_CACHES TRUE +#endif + +/** + * @brief Delegate threads APIs. + * @details If enabled then the delegate threads APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_DELEGATES) +#define CH_CFG_USE_DELEGATES TRUE +#endif + +/** + * @brief Jobs Queues APIs. + * @details If enabled then the jobs queues APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_JOBS) +#define CH_CFG_USE_JOBS TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_CFG_USE_FACTORY) +#define CH_CFG_USE_FACTORY TRUE +#endif + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 +#endif + +/** + * @brief Enables the registry of generic objects. + */ +#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE +#endif + +/** + * @brief Enables factory for generic buffers. + */ +#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE +#endif + +/** + * @brief Enables factory for semaphores. + */ +#if !defined(CH_CFG_FACTORY_SEMAPHORES) +#define CH_CFG_FACTORY_SEMAPHORES TRUE +#endif + +/** + * @brief Enables factory for mailboxes. + */ +#if !defined(CH_CFG_FACTORY_MAILBOXES) +#define CH_CFG_FACTORY_MAILBOXES TRUE +#endif + +/** + * @brief Enables factory for objects FIFOs. + */ +#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE +#endif + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_STATISTICS) +#define CH_DBG_STATISTICS FALSE +#endif + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_MASK) +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_ALL +#endif + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_BUFFER_SIZE) +#define CH_DBG_TRACE_BUFFER_SIZE 128 +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#if !defined(CH_DBG_THREADS_PROFILING) +#define CH_DBG_THREADS_PROFILING FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add system custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add system initialization code here.*/ \ +} + +/** + * @brief OS instance structure extension. + * @details User fields added to the end of the @p os_instance_t structure. + */ +#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS \ + /* Add OS instance custom fields here.*/ + +/** + * @brief OS instance initialization hook. + * + * @param[in] oip pointer to the @p os_instance_t structure + */ +#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) { \ + /* Add OS instance initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + * + * @param[in] ntp thread being switched in + * @param[in] otp thread being switched out + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** + * @brief Runtime Faults Collection Unit hook. + * @details This hook is invoked each time new faults are collected and stored. + */ +#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) { \ + /* Faults handling code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/testhal/AT32/multi/UART/cfg/at-start-f405/config.h b/testhal/AT32/multi/UART/cfg/at-start-f405/config.h new file mode 100644 index 0000000000..1e7c044f47 --- /dev/null +++ b/testhal/AT32/multi/UART/cfg/at-start-f405/config.h @@ -0,0 +1,39 @@ +/* + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * CRC driver system settings. + */ +#define AT32_CRC_USE_CRC1 FALSE + +#define CRC_USE_DMA FALSE +#define AT32_CRC_CRC1_DMA_PRIORITY 2 +#define AT32_CRC_CRC1_IRQ_PRIORITY 5 +#define AT32_CRC_CRC1_DMA_STREAM AT32_DMA_STREAM_ID_ANY + +/* + * I2C fallback driver system settings. + */ +#define SW_I2C_USE_I2C1 FALSE +#define SW_I2C_USE_I2C2 FALSE +#define SW_I2C_USE_I2C3 FALSE +#define SW_I2C_USE_I2C4 FALSE + +/* + * Other settings. + */ +#define BOARD_OTG_VBUSIG diff --git a/testhal/AT32/multi/UART/cfg/at-start-f405/halconf.h b/testhal/AT32/multi/UART/cfg/at-start-f405/halconf.h new file mode 100644 index 0000000000..476444be80 --- /dev/null +++ b/testhal/AT32/multi/UART/cfg/at-start-f405/halconf.h @@ -0,0 +1,557 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_8_4_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the EFlash subsystem. + */ +#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__) +#define HAL_USE_EFL FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART TRUE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/** + * @brief Enables the WSPI subsystem. + */ +#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) +#define HAL_USE_WSPI FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS FALSE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS FALSE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Timeout before assuming a failure while waiting for card idle. + * @note Time is in milliseconds. + */ +#if !defined(MMC_IDLE_TIMEOUT_MS) || defined(__DOXYGEN__) +#define MMC_IDLE_TIMEOUT_MS 1000 +#endif + +/** + * @brief Mutual exclusion on the SPI bus. + */ +#if !defined(MMC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define MMC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SIO driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SIO_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SIO_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Support for thread synchronization API. + */ +#if !defined(SIO_USE_SYNCHRONIZATION) || defined(__DOXYGEN__) +#define SIO_USE_SYNCHRONIZATION TRUE +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 256 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 2 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Inserts an assertion on function errors before returning. + */ +#if !defined(SPI_USE_ASSERT_ON_ERROR) || defined(__DOXYGEN__) +#define SPI_USE_ASSERT_ON_ERROR TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#include "halconf_community.h" + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/testhal/AT32/multi/UART/cfg/at-start-f405/halconf_community.h b/testhal/AT32/multi/UART/cfg/at-start-f405/halconf_community.h new file mode 100644 index 0000000000..5a77290c71 --- /dev/null +++ b/testhal/AT32/multi/UART/cfg/at-start-f405/halconf_community.h @@ -0,0 +1,182 @@ +/* + ChibiOS - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef HALCONF_COMMUNITY_H +#define HALCONF_COMMUNITY_H + +/** + * @brief Enables the community overlay. + */ +#if !defined(HAL_USE_COMMUNITY) || defined(__DOXYGEN__) +#define HAL_USE_COMMUNITY TRUE +#endif + +/** + * @brief Enables the FSMC subsystem. + */ +#if !defined(HAL_USE_FSMC) || defined(__DOXYGEN__) +#define HAL_USE_FSMC FALSE +#endif + +/** + * @brief Enables the NAND subsystem. + */ +#if !defined(HAL_USE_NAND) || defined(__DOXYGEN__) +#define HAL_USE_NAND FALSE +#endif + +/** + * @brief Enables the 1-wire subsystem. + */ +#if !defined(HAL_USE_ONEWIRE) || defined(__DOXYGEN__) +#define HAL_USE_ONEWIRE FALSE +#endif + +/** + * @brief Enables the EICU subsystem. + */ +#if !defined(HAL_USE_EICU) || defined(__DOXYGEN__) +#define HAL_USE_EICU FALSE +#endif + +/** + * @brief Enables the CRC subsystem. + */ +#if !defined(HAL_USE_CRC) || defined(__DOXYGEN__) +#define HAL_USE_CRC FALSE +#endif + +/** + * @brief Enables the RNG subsystem. + */ +#if !defined(HAL_USE_RNG) || defined(__DOXYGEN__) +#define HAL_USE_RNG FALSE +#endif + +/** + * @brief Enables the EEPROM subsystem. + */ +#if !defined(HAL_USE_EEPROM) || defined(__DOXYGEN__) +#define HAL_USE_EEPROM FALSE +#endif + +/** + * @brief Enables the TIMCAP subsystem. + */ +#if !defined(HAL_USE_TIMCAP) || defined(__DOXYGEN__) +#define HAL_USE_TIMCAP FALSE +#endif + +/** + * @brief Enables the COMP subsystem. + */ +#if !defined(HAL_USE_COMP) || defined(__DOXYGEN__) +#define HAL_USE_COMP FALSE +#endif + +/** + * @brief Enables the OPAMP subsystem. + */ +#if !defined(HAL_USE_OPAMP) || defined(__DOXYGEN__) +#define HAL_USE_OPAMP FALSE +#endif + +/** + * @brief Enables the QEI subsystem. + */ +#if !defined(HAL_USE_QEI) || defined(__DOXYGEN__) +#define HAL_USE_QEI FALSE +#endif + +/** + * @brief Enables the USBH subsystem. + */ +#if !defined(HAL_USE_USBH) || defined(__DOXYGEN__) +#define HAL_USE_USBH FALSE +#endif + +/** + * @brief Enables the USB_MSD subsystem. + */ +#if !defined(HAL_USE_USB_MSD) || defined(__DOXYGEN__) +#define HAL_USE_USB_MSD FALSE +#endif + +/*===========================================================================*/ +/* FSMCNAND driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the @p nandAcquireBus() and @p nanReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(NAND_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define NAND_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* 1-wire driver related settings. */ +/*===========================================================================*/ +/** + * @brief Enables strong pull up feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_STRONG_PULLUP FALSE + +/** + * @brief Enables search ROM feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_SEARCH_ROM TRUE + +/*===========================================================================*/ +/* QEI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables discard of overlow + */ +#if !defined(QEI_USE_OVERFLOW_DISCARD) || defined(__DOXYGEN__) +#define QEI_USE_OVERFLOW_DISCARD FALSE +#endif + +/** + * @brief Enables min max of overlow + */ +#if !defined(QEI_USE_OVERFLOW_MINMAX) || defined(__DOXYGEN__) +#define QEI_USE_OVERFLOW_MINMAX FALSE +#endif + +/*===========================================================================*/ +/* EEProm driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables 24xx series I2C eeprom device driver. + * @note Disabling this option saves both code and data space. + */ +#define EEPROM_USE_EE24XX FALSE + /** + * @brief Enables 25xx series SPI eeprom device driver. + * @note Disabling this option saves both code and data space. + */ +#define EEPROM_USE_EE25XX FALSE + +#endif /* HALCONF_COMMUNITY_H */ + +/** @} */ diff --git a/testhal/AT32/multi/UART/cfg/at-start-f405/mcuconf.h b/testhal/AT32/multi/UART/cfg/at-start-f405/mcuconf.h new file mode 100644 index 0000000000..3ad2801e5f --- /dev/null +++ b/testhal/AT32/multi/UART/cfg/at-start-f405/mcuconf.h @@ -0,0 +1,272 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef MCUCONF_H +#define MCUCONF_H + +/* + * AT32F405 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define AT32F405_MCUCONF + +/* + * General settings. + */ +#define AT32_NO_INIT FALSE + +/* + * HAL driver system settings. + */ +#define AT32_HICK_ENABLED TRUE +#define AT32_LICK_ENABLED FALSE +#define AT32_HEXT_ENABLED TRUE +#define AT32_LEXT_ENABLED FALSE +#define AT32_PLLU_ENABLED TRUE +#define AT32_SCLKSEL AT32_SCLKSEL_PLL +#define AT32_PLLRCS AT32_PLLRCS_HEXT +#define AT32_PLL_MS_VALUE 1 +#define AT32_PLL_NS_VALUE 72 +#define AT32_PLL_FP_VALUE 4 +#define AT32_PLL_FU_VALUE 18 +#define AT32_AHBDIV AT32_AHBDIV_DIV1 +#define AT32_APB1DIV AT32_APB1DIV_DIV2 +#define AT32_APB2DIV AT32_APB2DIV_DIV1 +#define AT32_HICK_TO_SCLK AT32_HICK_TO_SCLK_48M +#define AT32_HICKDIV AT32_HICKDIV_DIV1 +#define AT32_HICK_TO_SCLK_DIV AT32_HICK_TO_SCLK_DIV_DIV1 +#define AT32_HEXT_TO_SCLK_DIV AT32_HEXT_TO_SCLK_DIV_DIV1 +#define AT32_USB_CLOCK48_REQUIRED TRUE +#define AT32_PLLU_USB48_SEL AT32_PLLU_USB48_SEL_PLLU +#define AT32_CLKOUT_SEL AT32_CLKOUT_SEL_HICK +#define AT32_CLKOUTDIV1 AT32_CLKOUTDIV1_DIV1 +#define AT32_CLKOUTDIV2 AT32_CLKOUTDIV2_DIV1 +#define AT32_ERTCSEL AT32_ERTCSEL_NOCLOCK +#define AT32_ERTCDIV_VALUE 12 +#define AT32_I2SF5CLKSEL AT32_I2SF5CLKSEL_SCLK +#define AT32_PVM_ENABLE FALSE +#define AT32_PVMSEL AT32_PVMSEL_LEV1 +#define AT32_LDOOVSEL AT32_LDOOVSEL_LEV3 + +/* + * IRQ system settings. + */ +#define AT32_IRQ_EXINT0_PRIORITY 6 +#define AT32_IRQ_EXINT1_PRIORITY 6 +#define AT32_IRQ_EXINT2_PRIORITY 6 +#define AT32_IRQ_EXINT3_PRIORITY 6 +#define AT32_IRQ_EXINT4_PRIORITY 6 +#define AT32_IRQ_EXINT5_9_PRIORITY 6 +#define AT32_IRQ_EXINT10_15_PRIORITY 6 +#define AT32_IRQ_EXINT16_PRIORITY 6 +#define AT32_IRQ_EXINT17_PRIORITY 15 +#define AT32_IRQ_EXINT18_PRIORITY 6 +#define AT32_IRQ_EXINT20_PRIORITY 6 +#define AT32_IRQ_EXINT21_PRIORITY 15 +#define AT32_IRQ_EXINT22_PRIORITY 15 + +#define AT32_IRQ_TMR1_BRK_TMR9_PRIORITY 7 +#define AT32_IRQ_TMR1_OVF_TMR10_PRIORITY 7 +#define AT32_IRQ_TMR1_HALL_TMR11_PRIORITY 7 +#define AT32_IRQ_TMR1_CH_PRIORITY 7 +#define AT32_IRQ_TMR2_PRIORITY 7 +#define AT32_IRQ_TMR3_PRIORITY 7 +#define AT32_IRQ_TMR4_PRIORITY 7 +#define AT32_IRQ_TMR6_PRIORITY 7 +#define AT32_IRQ_TMR7_PRIORITY 7 +#define AT32_IRQ_TMR13_PRIORITY 7 +#define AT32_IRQ_TMR14_PRIORITY 7 + +#define AT32_IRQ_USART1_PRIORITY 12 +#define AT32_IRQ_USART2_PRIORITY 12 +#define AT32_IRQ_USART3_PRIORITY 12 +#define AT32_IRQ_UART4_PRIORITY 12 +#define AT32_IRQ_UART5_PRIORITY 12 +#define AT32_IRQ_USART6_PRIORITY 12 +#define AT32_IRQ_UART7_PRIORITY 12 +#define AT32_IRQ_UART8_PRIORITY 12 + +/* + * ADC driver system settings. + */ +#define AT32_ADC_USE_ADC1 FALSE +#define AT32_ADC_ADC1_DMA_PRIORITY 2 +#define AT32_ADC_IRQ_PRIORITY 6 +#define AT32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define AT32_ADC_ADCDIV 8 + +/* + * CAN driver system settings. + */ +#define AT32_CAN_USE_CAN1 FALSE +#define AT32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * GPT driver system settings. + */ +#define AT32_GPT_USE_TMR1 FALSE +#define AT32_GPT_USE_TMR2 FALSE +#define AT32_GPT_USE_TMR3 FALSE +#define AT32_GPT_USE_TMR4 FALSE +#define AT32_GPT_USE_TMR6 FALSE +#define AT32_GPT_USE_TMR7 FALSE +#define AT32_GPT_USE_TMR9 FALSE +#define AT32_GPT_USE_TMR10 FALSE +#define AT32_GPT_USE_TMR11 FALSE +#define AT32_GPT_USE_TMR13 FALSE +#define AT32_GPT_USE_TMR14 FALSE + +/* + * I2C driver system settings. + */ +#define AT32_I2C_USE_I2C1 FALSE +#define AT32_I2C_USE_I2C2 FALSE +#define AT32_I2C_USE_I2C3 FALSE +#define AT32_I2C_BUSY_TIMEOUT 50 +#define AT32_I2C_I2C1_DMA_PRIORITY 3 +#define AT32_I2C_I2C2_DMA_PRIORITY 3 +#define AT32_I2C_I2C3_DMA_PRIORITY 3 +#define AT32_I2C_I2C1_IRQ_PRIORITY 5 +#define AT32_I2C_I2C2_IRQ_PRIORITY 5 +#define AT32_I2C_I2C3_IRQ_PRIORITY 5 +#define AT32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define AT32_ICU_USE_TMR1 FALSE +#define AT32_ICU_USE_TMR2 FALSE +#define AT32_ICU_USE_TMR3 FALSE +#define AT32_ICU_USE_TMR4 FALSE +#define AT32_ICU_USE_TMR9 FALSE + +/* + * PWM driver system settings. + */ +#define AT32_PWM_USE_TMR1 FALSE +#define AT32_PWM_USE_TMR2 FALSE +#define AT32_PWM_USE_TMR3 FALSE +#define AT32_PWM_USE_TMR4 FALSE +#define AT32_PWM_USE_TMR9 FALSE +#define AT32_PWM_USE_TMR10 FALSE +#define AT32_PWM_USE_TMR11 FALSE +#define AT32_PWM_USE_TMR13 FALSE +#define AT32_PWM_USE_TMR14 FALSE + +/* + * RTC driver system settings. + */ +#define AT32_ERTC_DIVA_VALUE 32 +#define AT32_ERTC_DIVB_VALUE 1024 +#define AT32_ERTC_CTRL_INIT 0 +#define AT32_ERTC_TAMP_INIT 0 + +/* + * SERIAL driver system settings. + */ +#define AT32_SERIAL_USE_USART1 FALSE +#define AT32_SERIAL_USE_USART2 FALSE +#define AT32_SERIAL_USE_USART3 FALSE +#define AT32_SERIAL_USE_UART4 FALSE +#define AT32_SERIAL_USE_UART5 FALSE +#define AT32_SERIAL_USE_USART6 FALSE +#define AT32_SERIAL_USE_UART7 FALSE +#define AT32_SERIAL_USE_UART8 FALSE + +/* + * SIO driver system settings. + */ +#define AT32_SIO_USE_USART1 FALSE +#define AT32_SIO_USE_USART2 FALSE +#define AT32_SIO_USE_USART3 FALSE +#define AT32_SIO_USE_UART4 FALSE +#define AT32_SIO_USE_UART5 FALSE +#define AT32_SIO_USE_USART6 FALSE +#define AT32_SIO_USE_UART7 FALSE +#define AT32_SIO_USE_UART8 FALSE + +/* + * SPI driver system settings. + */ +#define AT32_SPI_USE_SPI1 FALSE +#define AT32_SPI_USE_SPI2 FALSE +#define AT32_SPI_USE_SPI3 FALSE +#define AT32_SPI_SPI1_DMA_PRIORITY 1 +#define AT32_SPI_SPI2_DMA_PRIORITY 1 +#define AT32_SPI_SPI3_DMA_PRIORITY 1 +#define AT32_SPI_SPI1_IRQ_PRIORITY 10 +#define AT32_SPI_SPI2_IRQ_PRIORITY 10 +#define AT32_SPI_SPI3_IRQ_PRIORITY 10 +#define AT32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define AT32_ST_IRQ_PRIORITY 8 +#define AT32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define AT32_UART_USE_USART1 TRUE +#define AT32_UART_USE_USART2 FALSE +#define AT32_UART_USE_USART3 FALSE +#define AT32_UART_USE_UART4 FALSE +#define AT32_UART_USE_UART5 FALSE +#define AT32_UART_USE_USART6 FALSE +#define AT32_UART_USE_UART7 FALSE +#define AT32_UART_USE_UART8 FALSE +#define AT32_UART_USART1_DMA_PRIORITY 0 +#define AT32_UART_USART2_DMA_PRIORITY 0 +#define AT32_UART_USART3_DMA_PRIORITY 0 +#define AT32_UART_UART4_DMA_PRIORITY 0 +#define AT32_UART_UART5_DMA_PRIORITY 0 +#define AT32_UART_USART6_DMA_PRIORITY 0 +#define AT32_UART_UART7_DMA_PRIORITY 0 +#define AT32_UART_UART8_DMA_PRIORITY 0 +#define AT32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define AT32_USB_USE_OTG1 FALSE +#define AT32_USB_USE_OTG2 FALSE +#define AT32_USB_OTG1_IRQ_PRIORITY 14 +#define AT32_USB_OTG2_IRQ_PRIORITY 14 +#define AT32_USB_OTG1_RX_FIFO_SIZE 512 +#define AT32_USB_OTG2_RX_FIFO_SIZE 1024 +#define AT32_USE_USB_OTG2_HS_DMA FALSE + +/* + * WDG driver system settings. + */ +#define AT32_WDG_USE_WDT FALSE + +#include "config.h" + +#endif /* MCUCONF_H */ diff --git a/testhal/AT32/multi/UART/cfg/at-start-f405/portab.c b/testhal/AT32/multi/UART/cfg/at-start-f405/portab.c new file mode 100644 index 0000000000..c61b6ed4be --- /dev/null +++ b/testhal/AT32/multi/UART/cfg/at-start-f405/portab.c @@ -0,0 +1,82 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file portab.c + * @brief Application portability module code. + * + * @addtogroup application_portability + * @{ + */ + +#include "hal.h" + +#include "portab.h" + +/*===========================================================================*/ +/* Module local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module exported variables. */ +/*===========================================================================*/ + +void txend1(UARTDriver *uartp); +void txend2(UARTDriver *uartp); +void rxend(UARTDriver *uartp); +void rxchar(UARTDriver *uartp, uint16_t c); +void rxerr(UARTDriver *uartp, uartflags_t e); + +/* + * UART driver configuration structure. + */ +UARTConfig uartcfg = { + txend1, + txend2, + rxend, + rxchar, + rxerr, + NULL, + 0, + 38400, + 0, + USART_CTRL2_LINEN, + 0 +}; + +/*===========================================================================*/ +/* Module local types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module exported functions. */ +/*===========================================================================*/ + +void portab_setup(void) { + +} + +/** @} */ diff --git a/testhal/AT32/multi/UART/cfg/at-start-f405/portab.h b/testhal/AT32/multi/UART/cfg/at-start-f405/portab.h new file mode 100644 index 0000000000..35724bce27 --- /dev/null +++ b/testhal/AT32/multi/UART/cfg/at-start-f405/portab.h @@ -0,0 +1,78 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file portab.h + * @brief Application portability macros and structures. + * + * @addtogroup application_portability + * @{ + */ + +#ifndef PORTAB_H +#define PORTAB_H + +/*===========================================================================*/ +/* Module constants. */ +/*===========================================================================*/ + +#define PORTAB_UART1 UARTD1 + +#define PORTAB_BLINK_LED1 LINE_LED_RED + +#define PORTAB_BLINK_LED2 LINE_LED_YELLOW + +#define PORTAB_BLINK_LED3 LINE_LED_GREEN + +/*===========================================================================*/ +/* Module pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +extern UARTConfig uartcfg; + +#ifdef __cplusplus +extern "C" { +#endif + void portab_setup(void); +#ifdef __cplusplus +} +#endif + +/*===========================================================================*/ +/* Module inline functions. */ +/*===========================================================================*/ + +#endif /* PORTAB_H */ + +/** @} */ diff --git a/testhal/AT32/multi/UART/cfg/at-start-f415/chconf.h b/testhal/AT32/multi/UART/cfg/at-start-f415/chconf.h index 46b3f78b68..56fe06776a 100644 --- a/testhal/AT32/multi/UART/cfg/at-start-f415/chconf.h +++ b/testhal/AT32/multi/UART/cfg/at-start-f415/chconf.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/testhal/AT32/multi/UART/cfg/at-start-f415/config.h b/testhal/AT32/multi/UART/cfg/at-start-f415/config.h index 361e185d9c..056a8f39ff 100644 --- a/testhal/AT32/multi/UART/cfg/at-start-f415/config.h +++ b/testhal/AT32/multi/UART/cfg/at-start-f415/config.h @@ -1,6 +1,6 @@ /* - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/testhal/AT32/multi/UART/cfg/at-start-f415/halconf.h b/testhal/AT32/multi/UART/cfg/at-start-f415/halconf.h index 5b1de987e6..476444be80 100644 --- a/testhal/AT32/multi/UART/cfg/at-start-f415/halconf.h +++ b/testhal/AT32/multi/UART/cfg/at-start-f415/halconf.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/testhal/AT32/multi/UART/cfg/at-start-f415/halconf_community.h b/testhal/AT32/multi/UART/cfg/at-start-f415/halconf_community.h index c43d668764..5a77290c71 100644 --- a/testhal/AT32/multi/UART/cfg/at-start-f415/halconf_community.h +++ b/testhal/AT32/multi/UART/cfg/at-start-f415/halconf_community.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/testhal/AT32/multi/UART/cfg/at-start-f415/mcuconf.h b/testhal/AT32/multi/UART/cfg/at-start-f415/mcuconf.h index 7f99b385d2..072eb17843 100644 --- a/testhal/AT32/multi/UART/cfg/at-start-f415/mcuconf.h +++ b/testhal/AT32/multi/UART/cfg/at-start-f415/mcuconf.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -106,6 +106,7 @@ #define AT32_ADC_USE_ADC1 FALSE #define AT32_ADC_ADC1_DMA_PRIORITY 2 #define AT32_ADC_ADC1_IRQ_PRIORITY 6 +#define AT32_ADC_ADC1_DMA_IRQ_PRIORITY 6 /* * CAN driver system settings. diff --git a/testhal/AT32/multi/UART/cfg/at-start-f415/portab.c b/testhal/AT32/multi/UART/cfg/at-start-f415/portab.c index b2d669c604..a88c37c50e 100644 --- a/testhal/AT32/multi/UART/cfg/at-start-f415/portab.c +++ b/testhal/AT32/multi/UART/cfg/at-start-f415/portab.c @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/testhal/AT32/multi/UART/cfg/at-start-f415/portab.h b/testhal/AT32/multi/UART/cfg/at-start-f415/portab.h index 1d682cf18d..35724bce27 100644 --- a/testhal/AT32/multi/UART/cfg/at-start-f415/portab.h +++ b/testhal/AT32/multi/UART/cfg/at-start-f415/portab.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/testhal/AT32/multi/UART/main.c b/testhal/AT32/multi/UART/main.c index 22299fe4ee..0c7e047a2d 100644 --- a/testhal/AT32/multi/UART/main.c +++ b/testhal/AT32/multi/UART/main.c @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/testhal/AT32/multi/UART/make/at-start-f402.make b/testhal/AT32/multi/UART/make/at-start-f402.make new file mode 100644 index 0000000000..c2d5988d83 --- /dev/null +++ b/testhal/AT32/multi/UART/make/at-start-f402.make @@ -0,0 +1,196 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO). +ifeq ($(USE_LTO),) + USE_LTO = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# Enable this if you want to use bitbang I2C. +ifeq ($(USE_HAL_I2C_FALLBACK),) + USE_HAL_I2C_FALLBACK = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x400 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU (no, softfp, hard). +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# FPU-related options. +ifeq ($(USE_FPU_OPT),) + USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16 +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, target, sources and paths +# + +# Define project name here +PROJECT = ch + +# Target settings. +MCU = cortex-m4 + +# Imported source files and paths. +CHIBIOS := ../../../../../ChibiOS +CHIBIOS_CONTRIB := ../../../.. +CONFDIR := ./cfg/at-start-f402 +BUILDDIR := ./build/at-start-f402 +DEPDIR := ./.dep/at-start-f402 + +# Licensing files. +include $(CHIBIOS)/os/license/license.mk +# Startup files. +include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_at32f402.mk +# HAL-OSAL files (optional). +include $(CHIBIOS_CONTRIB)/os/hal/hal.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/AT32F402_405/platform.mk +include $(CHIBIOS_CONTRIB)/os/hal/boards/AT_START_F402/board.mk +include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMv7-M/compilers/GCC/mk/port.mk +# Auto-build files in ./source recursively. +include $(CHIBIOS)/tools/mk/autobuild.mk +# Other files (optional). +#include $(CHIBIOS)/os/test/test.mk +#include $(CHIBIOS)/test/rt/rt_test.mk +#include $(CHIBIOS)/test/oslib/oslib_test.mk + +# Define linker script file here. +LDSCRIPT= $(STARTUPLD_CONTRIB)/AT32F402xC.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(ALLCSRC) \ + $(TESTSRC) \ + $(CONFDIR)/portab.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = $(ALLCPPSRC) + +# List ASM source files here. +ASMSRC = $(ALLASMSRC) + +# List ASM with preprocessor source files here. +ASMXSRC = $(ALLXASMSRC) + +# Inclusion directories. +INCDIR = $(CONFDIR) $(ALLINC) + +# Define C warning options here. +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes + +# Define C++ warning options here. +CPPWARN = -Wall -Wextra -Wundef + +# +# Project, target, sources and paths +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user section +############################################################################## + +############################################################################## +# Common rules +# + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk +include $(RULESPATH)/arm-none-eabi.mk +include $(RULESPATH)/rules.mk + +# +# Common rules +############################################################################## + +############################################################################## +# Custom rules +# + +# +# Custom rules +############################################################################## diff --git a/testhal/AT32/multi/UART/make/at-start-f405.make b/testhal/AT32/multi/UART/make/at-start-f405.make new file mode 100644 index 0000000000..d3cc3ac36c --- /dev/null +++ b/testhal/AT32/multi/UART/make/at-start-f405.make @@ -0,0 +1,196 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO). +ifeq ($(USE_LTO),) + USE_LTO = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# Enable this if you want to use bitbang I2C. +ifeq ($(USE_HAL_I2C_FALLBACK),) + USE_HAL_I2C_FALLBACK = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x400 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU (no, softfp, hard). +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# FPU-related options. +ifeq ($(USE_FPU_OPT),) + USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16 +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, target, sources and paths +# + +# Define project name here +PROJECT = ch + +# Target settings. +MCU = cortex-m4 + +# Imported source files and paths. +CHIBIOS := ../../../../../ChibiOS +CHIBIOS_CONTRIB := ../../../.. +CONFDIR := ./cfg/at-start-f405 +BUILDDIR := ./build/at-start-f405 +DEPDIR := ./.dep/at-start-f405 + +# Licensing files. +include $(CHIBIOS)/os/license/license.mk +# Startup files. +include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_at32f405.mk +# HAL-OSAL files (optional). +include $(CHIBIOS_CONTRIB)/os/hal/hal.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/AT32F402_405/platform.mk +include $(CHIBIOS_CONTRIB)/os/hal/boards/AT_START_F405/board.mk +include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMv7-M/compilers/GCC/mk/port.mk +# Auto-build files in ./source recursively. +include $(CHIBIOS)/tools/mk/autobuild.mk +# Other files (optional). +#include $(CHIBIOS)/os/test/test.mk +#include $(CHIBIOS)/test/rt/rt_test.mk +#include $(CHIBIOS)/test/oslib/oslib_test.mk + +# Define linker script file here. +LDSCRIPT= $(STARTUPLD_CONTRIB)/AT32F405xC.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(ALLCSRC) \ + $(TESTSRC) \ + $(CONFDIR)/portab.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = $(ALLCPPSRC) + +# List ASM source files here. +ASMSRC = $(ALLASMSRC) + +# List ASM with preprocessor source files here. +ASMXSRC = $(ALLXASMSRC) + +# Inclusion directories. +INCDIR = $(CONFDIR) $(ALLINC) + +# Define C warning options here. +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes + +# Define C++ warning options here. +CPPWARN = -Wall -Wextra -Wundef + +# +# Project, target, sources and paths +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user section +############################################################################## + +############################################################################## +# Common rules +# + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk +include $(RULESPATH)/arm-none-eabi.mk +include $(RULESPATH)/rules.mk + +# +# Common rules +############################################################################## + +############################################################################## +# Custom rules +# + +# +# Custom rules +############################################################################## diff --git a/testhal/AT32/multi/USB_CDC/Makefile b/testhal/AT32/multi/USB_CDC/Makefile index c8606df05e..4d39b55fad 100644 --- a/testhal/AT32/multi/USB_CDC/Makefile +++ b/testhal/AT32/multi/USB_CDC/Makefile @@ -3,6 +3,22 @@ # all: + @echo + @echo === Building for AT-START-F402 ===================================== + +@make --no-print-directory -f ./make/at-start-f402.make all + @echo ==================================================================== + @echo + @echo === Building for AT-START-F405_USBFS =============================== + +@make --no-print-directory -f ./make/at-start-f405_usbfs.make all + @echo ==================================================================== + @echo + @echo === Building for AT-START-F405_USBHS =============================== + +@make --no-print-directory -f ./make/at-start-f405_usbhs.make all + @echo ==================================================================== + @echo + @echo === Building for AT-START-F405_USBHS-DMA =========================== + +@make --no-print-directory -f ./make/at-start-f405_usbhs-dma.make all + @echo ==================================================================== @echo @echo === Building for AT-START-F415 ===================================== +@make --no-print-directory -f ./make/at-start-f415.make all @@ -10,6 +26,14 @@ all: @echo clean: + @echo + +@make --no-print-directory -f ./make/at-start-f402.make clean + @echo + +@make --no-print-directory -f ./make/at-start-f405_usbfs.make clean + @echo + +@make --no-print-directory -f ./make/at-start-f405_usbhs.make clean + @echo + +@make --no-print-directory -f ./make/at-start-f405_usbhs-dma.make clean @echo +@make --no-print-directory -f ./make/at-start-f415.make clean @echo diff --git a/testhal/AT32/multi/USB_CDC/cfg/at-start-f402/chconf.h b/testhal/AT32/multi/USB_CDC/cfg/at-start-f402/chconf.h new file mode 100644 index 0000000000..56fe06776a --- /dev/null +++ b/testhal/AT32/multi/USB_CDC/cfg/at-start-f402/chconf.h @@ -0,0 +1,842 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_7_0_ + +/*===========================================================================*/ +/** + * @name System settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Handling of instances. + * @note If enabled then threads assigned to various instances can + * interact each other using the same synchronization objects. + * If disabled then each OS instance is a separate world, no + * direct interactions are handled by the OS. + */ +#if !defined(CH_CFG_SMP_MODE) +#define CH_CFG_SMP_MODE FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_ST_RESOLUTION) +#define CH_CFG_ST_RESOLUTION 32 +#endif + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_CFG_ST_FREQUENCY) +#define CH_CFG_ST_FREQUENCY 10000 +#endif + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_INTERVALS_SIZE) +#define CH_CFG_INTERVALS_SIZE 32 +#endif + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_TIME_TYPES_SIZE) +#define CH_CFG_TIME_TYPES_SIZE 32 +#endif + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#if !defined(CH_CFG_ST_TIMEDELTA) +#define CH_CFG_ST_TIMEDELTA 2 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#if !defined(CH_CFG_TIME_QUANTUM) +#define CH_CFG_TIME_QUANTUM 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#if !defined(CH_CFG_NO_IDLE_THREAD) +#define CH_CFG_NO_IDLE_THREAD FALSE +#endif + +/** + * @brief Kernel hardening level. + * @details This option is the level of functional-safety checks enabled + * in the kerkel. The meaning is: + * - 0: No checks, maximum performance. + * - 1: Reasonable checks. + * - 2: All checks. + * . + */ +#if !defined(CH_CFG_HARDENING_LEVEL) +#define CH_CFG_HARDENING_LEVEL 0 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_OPTIMIZE_SPEED) +#define CH_CFG_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TM) +#define CH_CFG_USE_TM TRUE +#endif + +/** + * @brief Time Stamps APIs. + * @details If enabled then the time stamps APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TIMESTAMP) +#define CH_CFG_USE_TIMESTAMP TRUE +#endif + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_REGISTRY) +#define CH_CFG_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_WAITEXIT) +#define CH_CFG_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_SEMAPHORES) +#define CH_CFG_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MUTEXES) +#define CH_CFG_USE_MUTEXES TRUE +#endif + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_CONDVARS) +#define CH_CFG_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_EVENTS) +#define CH_CFG_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MESSAGES) +#define CH_CFG_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#if !defined(CH_CFG_USE_DYNAMIC) +#define CH_CFG_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name OSLIB options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_MAILBOXES) +#define CH_CFG_USE_MAILBOXES TRUE +#endif + +/** + * @brief Memory checks APIs. + * @details If enabled then the memory checks APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCHECKS) +#define CH_CFG_USE_MEMCHECKS TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCORE) +#define CH_CFG_USE_MEMCORE TRUE +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#if !defined(CH_CFG_MEMCORE_SIZE) +#define CH_CFG_MEMCORE_SIZE 0 +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_CFG_USE_HEAP) +#define CH_CFG_USE_HEAP TRUE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMPOOLS) +#define CH_CFG_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_FIFOS) +#define CH_CFG_USE_OBJ_FIFOS TRUE +#endif + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Objects Caches APIs. + * @details If enabled then the objects caches APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_CACHES) +#define CH_CFG_USE_OBJ_CACHES TRUE +#endif + +/** + * @brief Delegate threads APIs. + * @details If enabled then the delegate threads APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_DELEGATES) +#define CH_CFG_USE_DELEGATES TRUE +#endif + +/** + * @brief Jobs Queues APIs. + * @details If enabled then the jobs queues APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_JOBS) +#define CH_CFG_USE_JOBS TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_CFG_USE_FACTORY) +#define CH_CFG_USE_FACTORY TRUE +#endif + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 +#endif + +/** + * @brief Enables the registry of generic objects. + */ +#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE +#endif + +/** + * @brief Enables factory for generic buffers. + */ +#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE +#endif + +/** + * @brief Enables factory for semaphores. + */ +#if !defined(CH_CFG_FACTORY_SEMAPHORES) +#define CH_CFG_FACTORY_SEMAPHORES TRUE +#endif + +/** + * @brief Enables factory for mailboxes. + */ +#if !defined(CH_CFG_FACTORY_MAILBOXES) +#define CH_CFG_FACTORY_MAILBOXES TRUE +#endif + +/** + * @brief Enables factory for objects FIFOs. + */ +#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE +#endif + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_STATISTICS) +#define CH_DBG_STATISTICS FALSE +#endif + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_MASK) +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_ALL +#endif + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_BUFFER_SIZE) +#define CH_DBG_TRACE_BUFFER_SIZE 128 +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#if !defined(CH_DBG_THREADS_PROFILING) +#define CH_DBG_THREADS_PROFILING FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add system custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add system initialization code here.*/ \ +} + +/** + * @brief OS instance structure extension. + * @details User fields added to the end of the @p os_instance_t structure. + */ +#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS \ + /* Add OS instance custom fields here.*/ + +/** + * @brief OS instance initialization hook. + * + * @param[in] oip pointer to the @p os_instance_t structure + */ +#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) { \ + /* Add OS instance initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + * + * @param[in] ntp thread being switched in + * @param[in] otp thread being switched out + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** + * @brief Runtime Faults Collection Unit hook. + * @details This hook is invoked each time new faults are collected and stored. + */ +#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) { \ + /* Faults handling code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/testhal/AT32/multi/USB_CDC/cfg/at-start-f402/config.h b/testhal/AT32/multi/USB_CDC/cfg/at-start-f402/config.h new file mode 100644 index 0000000000..1e7c044f47 --- /dev/null +++ b/testhal/AT32/multi/USB_CDC/cfg/at-start-f402/config.h @@ -0,0 +1,39 @@ +/* + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * CRC driver system settings. + */ +#define AT32_CRC_USE_CRC1 FALSE + +#define CRC_USE_DMA FALSE +#define AT32_CRC_CRC1_DMA_PRIORITY 2 +#define AT32_CRC_CRC1_IRQ_PRIORITY 5 +#define AT32_CRC_CRC1_DMA_STREAM AT32_DMA_STREAM_ID_ANY + +/* + * I2C fallback driver system settings. + */ +#define SW_I2C_USE_I2C1 FALSE +#define SW_I2C_USE_I2C2 FALSE +#define SW_I2C_USE_I2C3 FALSE +#define SW_I2C_USE_I2C4 FALSE + +/* + * Other settings. + */ +#define BOARD_OTG_VBUSIG diff --git a/testhal/AT32/multi/USB_CDC/cfg/at-start-f402/halconf.h b/testhal/AT32/multi/USB_CDC/cfg/at-start-f402/halconf.h new file mode 100644 index 0000000000..5419a662a8 --- /dev/null +++ b/testhal/AT32/multi/USB_CDC/cfg/at-start-f402/halconf.h @@ -0,0 +1,557 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_8_4_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the EFlash subsystem. + */ +#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__) +#define HAL_USE_EFL FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB TRUE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB TRUE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/** + * @brief Enables the WSPI subsystem. + */ +#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) +#define HAL_USE_WSPI FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS FALSE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS FALSE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Timeout before assuming a failure while waiting for card idle. + * @note Time is in milliseconds. + */ +#if !defined(MMC_IDLE_TIMEOUT_MS) || defined(__DOXYGEN__) +#define MMC_IDLE_TIMEOUT_MS 1000 +#endif + +/** + * @brief Mutual exclusion on the SPI bus. + */ +#if !defined(MMC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define MMC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SIO driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SIO_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SIO_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Support for thread synchronization API. + */ +#if !defined(SIO_USE_SYNCHRONIZATION) || defined(__DOXYGEN__) +#define SIO_USE_SYNCHRONIZATION TRUE +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 256 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 2 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Inserts an assertion on function errors before returning. + */ +#if !defined(SPI_USE_ASSERT_ON_ERROR) || defined(__DOXYGEN__) +#define SPI_USE_ASSERT_ON_ERROR TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#include "halconf_community.h" + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/testhal/AT32/multi/USB_CDC/cfg/at-start-f402/halconf_community.h b/testhal/AT32/multi/USB_CDC/cfg/at-start-f402/halconf_community.h new file mode 100644 index 0000000000..5a77290c71 --- /dev/null +++ b/testhal/AT32/multi/USB_CDC/cfg/at-start-f402/halconf_community.h @@ -0,0 +1,182 @@ +/* + ChibiOS - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef HALCONF_COMMUNITY_H +#define HALCONF_COMMUNITY_H + +/** + * @brief Enables the community overlay. + */ +#if !defined(HAL_USE_COMMUNITY) || defined(__DOXYGEN__) +#define HAL_USE_COMMUNITY TRUE +#endif + +/** + * @brief Enables the FSMC subsystem. + */ +#if !defined(HAL_USE_FSMC) || defined(__DOXYGEN__) +#define HAL_USE_FSMC FALSE +#endif + +/** + * @brief Enables the NAND subsystem. + */ +#if !defined(HAL_USE_NAND) || defined(__DOXYGEN__) +#define HAL_USE_NAND FALSE +#endif + +/** + * @brief Enables the 1-wire subsystem. + */ +#if !defined(HAL_USE_ONEWIRE) || defined(__DOXYGEN__) +#define HAL_USE_ONEWIRE FALSE +#endif + +/** + * @brief Enables the EICU subsystem. + */ +#if !defined(HAL_USE_EICU) || defined(__DOXYGEN__) +#define HAL_USE_EICU FALSE +#endif + +/** + * @brief Enables the CRC subsystem. + */ +#if !defined(HAL_USE_CRC) || defined(__DOXYGEN__) +#define HAL_USE_CRC FALSE +#endif + +/** + * @brief Enables the RNG subsystem. + */ +#if !defined(HAL_USE_RNG) || defined(__DOXYGEN__) +#define HAL_USE_RNG FALSE +#endif + +/** + * @brief Enables the EEPROM subsystem. + */ +#if !defined(HAL_USE_EEPROM) || defined(__DOXYGEN__) +#define HAL_USE_EEPROM FALSE +#endif + +/** + * @brief Enables the TIMCAP subsystem. + */ +#if !defined(HAL_USE_TIMCAP) || defined(__DOXYGEN__) +#define HAL_USE_TIMCAP FALSE +#endif + +/** + * @brief Enables the COMP subsystem. + */ +#if !defined(HAL_USE_COMP) || defined(__DOXYGEN__) +#define HAL_USE_COMP FALSE +#endif + +/** + * @brief Enables the OPAMP subsystem. + */ +#if !defined(HAL_USE_OPAMP) || defined(__DOXYGEN__) +#define HAL_USE_OPAMP FALSE +#endif + +/** + * @brief Enables the QEI subsystem. + */ +#if !defined(HAL_USE_QEI) || defined(__DOXYGEN__) +#define HAL_USE_QEI FALSE +#endif + +/** + * @brief Enables the USBH subsystem. + */ +#if !defined(HAL_USE_USBH) || defined(__DOXYGEN__) +#define HAL_USE_USBH FALSE +#endif + +/** + * @brief Enables the USB_MSD subsystem. + */ +#if !defined(HAL_USE_USB_MSD) || defined(__DOXYGEN__) +#define HAL_USE_USB_MSD FALSE +#endif + +/*===========================================================================*/ +/* FSMCNAND driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the @p nandAcquireBus() and @p nanReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(NAND_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define NAND_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* 1-wire driver related settings. */ +/*===========================================================================*/ +/** + * @brief Enables strong pull up feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_STRONG_PULLUP FALSE + +/** + * @brief Enables search ROM feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_SEARCH_ROM TRUE + +/*===========================================================================*/ +/* QEI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables discard of overlow + */ +#if !defined(QEI_USE_OVERFLOW_DISCARD) || defined(__DOXYGEN__) +#define QEI_USE_OVERFLOW_DISCARD FALSE +#endif + +/** + * @brief Enables min max of overlow + */ +#if !defined(QEI_USE_OVERFLOW_MINMAX) || defined(__DOXYGEN__) +#define QEI_USE_OVERFLOW_MINMAX FALSE +#endif + +/*===========================================================================*/ +/* EEProm driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables 24xx series I2C eeprom device driver. + * @note Disabling this option saves both code and data space. + */ +#define EEPROM_USE_EE24XX FALSE + /** + * @brief Enables 25xx series SPI eeprom device driver. + * @note Disabling this option saves both code and data space. + */ +#define EEPROM_USE_EE25XX FALSE + +#endif /* HALCONF_COMMUNITY_H */ + +/** @} */ diff --git a/testhal/AT32/multi/USB_CDC/cfg/at-start-f402/mcuconf.h b/testhal/AT32/multi/USB_CDC/cfg/at-start-f402/mcuconf.h new file mode 100644 index 0000000000..98f48374a0 --- /dev/null +++ b/testhal/AT32/multi/USB_CDC/cfg/at-start-f402/mcuconf.h @@ -0,0 +1,268 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef MCUCONF_H +#define MCUCONF_H + +/* + * AT32F402 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define AT32F402_MCUCONF + +/* + * General settings. + */ +#define AT32_NO_INIT FALSE + +/* + * HAL driver system settings. + */ +#define AT32_HICK_ENABLED TRUE +#define AT32_LICK_ENABLED FALSE +#define AT32_HEXT_ENABLED TRUE +#define AT32_LEXT_ENABLED FALSE +#define AT32_PLLU_ENABLED TRUE +#define AT32_SCLKSEL AT32_SCLKSEL_PLL +#define AT32_PLLRCS AT32_PLLRCS_HEXT +#define AT32_PLL_MS_VALUE 1 +#define AT32_PLL_NS_VALUE 72 +#define AT32_PLL_FP_VALUE 4 +#define AT32_PLL_FU_VALUE 18 +#define AT32_AHBDIV AT32_AHBDIV_DIV1 +#define AT32_APB1DIV AT32_APB1DIV_DIV2 +#define AT32_APB2DIV AT32_APB2DIV_DIV1 +#define AT32_HICK_TO_SCLK AT32_HICK_TO_SCLK_48M +#define AT32_HICKDIV AT32_HICKDIV_DIV1 +#define AT32_HICK_TO_SCLK_DIV AT32_HICK_TO_SCLK_DIV_DIV1 +#define AT32_HEXT_TO_SCLK_DIV AT32_HEXT_TO_SCLK_DIV_DIV1 +#define AT32_USB_CLOCK48_REQUIRED TRUE +#define AT32_PLLU_USB48_SEL AT32_PLLU_USB48_SEL_PLLU +#define AT32_CLKOUT_SEL AT32_CLKOUT_SEL_HICK +#define AT32_CLKOUTDIV1 AT32_CLKOUTDIV1_DIV1 +#define AT32_CLKOUTDIV2 AT32_CLKOUTDIV2_DIV1 +#define AT32_ERTCSEL AT32_ERTCSEL_NOCLOCK +#define AT32_ERTCDIV_VALUE 12 +#define AT32_I2SF5CLKSEL AT32_I2SF5CLKSEL_SCLK +#define AT32_PVM_ENABLE FALSE +#define AT32_PVMSEL AT32_PVMSEL_LEV1 +#define AT32_LDOOVSEL AT32_LDOOVSEL_LEV3 + +/* + * IRQ system settings. + */ +#define AT32_IRQ_EXINT0_PRIORITY 6 +#define AT32_IRQ_EXINT1_PRIORITY 6 +#define AT32_IRQ_EXINT2_PRIORITY 6 +#define AT32_IRQ_EXINT3_PRIORITY 6 +#define AT32_IRQ_EXINT4_PRIORITY 6 +#define AT32_IRQ_EXINT5_9_PRIORITY 6 +#define AT32_IRQ_EXINT10_15_PRIORITY 6 +#define AT32_IRQ_EXINT16_PRIORITY 6 +#define AT32_IRQ_EXINT17_PRIORITY 15 +#define AT32_IRQ_EXINT18_PRIORITY 6 +#define AT32_IRQ_EXINT20_PRIORITY 6 +#define AT32_IRQ_EXINT21_PRIORITY 15 +#define AT32_IRQ_EXINT22_PRIORITY 15 + +#define AT32_IRQ_TMR1_BRK_TMR9_PRIORITY 7 +#define AT32_IRQ_TMR1_OVF_TMR10_PRIORITY 7 +#define AT32_IRQ_TMR1_HALL_TMR11_PRIORITY 7 +#define AT32_IRQ_TMR1_CH_PRIORITY 7 +#define AT32_IRQ_TMR2_PRIORITY 7 +#define AT32_IRQ_TMR3_PRIORITY 7 +#define AT32_IRQ_TMR4_PRIORITY 7 +#define AT32_IRQ_TMR6_PRIORITY 7 +#define AT32_IRQ_TMR7_PRIORITY 7 +#define AT32_IRQ_TMR13_PRIORITY 7 +#define AT32_IRQ_TMR14_PRIORITY 7 + +#define AT32_IRQ_USART1_PRIORITY 12 +#define AT32_IRQ_USART2_PRIORITY 12 +#define AT32_IRQ_USART3_PRIORITY 12 +#define AT32_IRQ_UART4_PRIORITY 12 +#define AT32_IRQ_UART5_PRIORITY 12 +#define AT32_IRQ_USART6_PRIORITY 12 +#define AT32_IRQ_UART7_PRIORITY 12 +#define AT32_IRQ_UART8_PRIORITY 12 + +/* + * ADC driver system settings. + */ +#define AT32_ADC_USE_ADC1 FALSE +#define AT32_ADC_ADC1_DMA_PRIORITY 2 +#define AT32_ADC_IRQ_PRIORITY 6 +#define AT32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define AT32_ADC_ADCDIV 8 + +/* + * CAN driver system settings. + */ +#define AT32_CAN_USE_CAN1 FALSE +#define AT32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * GPT driver system settings. + */ +#define AT32_GPT_USE_TMR1 FALSE +#define AT32_GPT_USE_TMR2 FALSE +#define AT32_GPT_USE_TMR3 FALSE +#define AT32_GPT_USE_TMR4 FALSE +#define AT32_GPT_USE_TMR6 FALSE +#define AT32_GPT_USE_TMR7 FALSE +#define AT32_GPT_USE_TMR9 FALSE +#define AT32_GPT_USE_TMR10 FALSE +#define AT32_GPT_USE_TMR11 FALSE +#define AT32_GPT_USE_TMR13 FALSE +#define AT32_GPT_USE_TMR14 FALSE + +/* + * I2C driver system settings. + */ +#define AT32_I2C_USE_I2C1 FALSE +#define AT32_I2C_USE_I2C2 FALSE +#define AT32_I2C_USE_I2C3 FALSE +#define AT32_I2C_BUSY_TIMEOUT 50 +#define AT32_I2C_I2C1_DMA_PRIORITY 3 +#define AT32_I2C_I2C2_DMA_PRIORITY 3 +#define AT32_I2C_I2C3_DMA_PRIORITY 3 +#define AT32_I2C_I2C1_IRQ_PRIORITY 5 +#define AT32_I2C_I2C2_IRQ_PRIORITY 5 +#define AT32_I2C_I2C3_IRQ_PRIORITY 5 +#define AT32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define AT32_ICU_USE_TMR1 FALSE +#define AT32_ICU_USE_TMR2 FALSE +#define AT32_ICU_USE_TMR3 FALSE +#define AT32_ICU_USE_TMR4 FALSE +#define AT32_ICU_USE_TMR9 FALSE + +/* + * PWM driver system settings. + */ +#define AT32_PWM_USE_TMR1 FALSE +#define AT32_PWM_USE_TMR2 FALSE +#define AT32_PWM_USE_TMR3 FALSE +#define AT32_PWM_USE_TMR4 FALSE +#define AT32_PWM_USE_TMR9 FALSE +#define AT32_PWM_USE_TMR10 FALSE +#define AT32_PWM_USE_TMR11 FALSE +#define AT32_PWM_USE_TMR13 FALSE +#define AT32_PWM_USE_TMR14 FALSE + +/* + * RTC driver system settings. + */ +#define AT32_ERTC_DIVA_VALUE 32 +#define AT32_ERTC_DIVB_VALUE 1024 +#define AT32_ERTC_CTRL_INIT 0 +#define AT32_ERTC_TAMP_INIT 0 + +/* + * SERIAL driver system settings. + */ +#define AT32_SERIAL_USE_USART1 FALSE +#define AT32_SERIAL_USE_USART2 FALSE +#define AT32_SERIAL_USE_USART3 FALSE +#define AT32_SERIAL_USE_UART4 FALSE +#define AT32_SERIAL_USE_UART5 FALSE +#define AT32_SERIAL_USE_USART6 FALSE +#define AT32_SERIAL_USE_UART7 FALSE +#define AT32_SERIAL_USE_UART8 FALSE + +/* + * SIO driver system settings. + */ +#define AT32_SIO_USE_USART1 FALSE +#define AT32_SIO_USE_USART2 FALSE +#define AT32_SIO_USE_USART3 FALSE +#define AT32_SIO_USE_UART4 FALSE +#define AT32_SIO_USE_UART5 FALSE +#define AT32_SIO_USE_USART6 FALSE +#define AT32_SIO_USE_UART7 FALSE +#define AT32_SIO_USE_UART8 FALSE + +/* + * SPI driver system settings. + */ +#define AT32_SPI_USE_SPI1 FALSE +#define AT32_SPI_USE_SPI2 FALSE +#define AT32_SPI_USE_SPI3 FALSE +#define AT32_SPI_SPI1_DMA_PRIORITY 1 +#define AT32_SPI_SPI2_DMA_PRIORITY 1 +#define AT32_SPI_SPI3_DMA_PRIORITY 1 +#define AT32_SPI_SPI1_IRQ_PRIORITY 10 +#define AT32_SPI_SPI2_IRQ_PRIORITY 10 +#define AT32_SPI_SPI3_IRQ_PRIORITY 10 +#define AT32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define AT32_ST_IRQ_PRIORITY 8 +#define AT32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define AT32_UART_USE_USART1 FALSE +#define AT32_UART_USE_USART2 FALSE +#define AT32_UART_USE_USART3 FALSE +#define AT32_UART_USE_UART4 FALSE +#define AT32_UART_USE_UART5 FALSE +#define AT32_UART_USE_USART6 FALSE +#define AT32_UART_USE_UART7 FALSE +#define AT32_UART_USE_UART8 FALSE +#define AT32_UART_USART1_DMA_PRIORITY 0 +#define AT32_UART_USART2_DMA_PRIORITY 0 +#define AT32_UART_USART3_DMA_PRIORITY 0 +#define AT32_UART_UART4_DMA_PRIORITY 0 +#define AT32_UART_UART5_DMA_PRIORITY 0 +#define AT32_UART_USART6_DMA_PRIORITY 0 +#define AT32_UART_UART7_DMA_PRIORITY 0 +#define AT32_UART_UART8_DMA_PRIORITY 0 +#define AT32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define AT32_USB_USE_OTG1 TRUE +#define AT32_USB_OTG1_IRQ_PRIORITY 14 +#define AT32_USB_OTG1_RX_FIFO_SIZE 512 + +/* + * WDG driver system settings. + */ +#define AT32_WDG_USE_WDT FALSE + +#include "config.h" + +#endif /* MCUCONF_H */ diff --git a/testhal/AT32/multi/USB_CDC/cfg/at-start-f402/portab.c b/testhal/AT32/multi/USB_CDC/cfg/at-start-f402/portab.c new file mode 100644 index 0000000000..ceaf0ff400 --- /dev/null +++ b/testhal/AT32/multi/USB_CDC/cfg/at-start-f402/portab.c @@ -0,0 +1,59 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file portab.c + * @brief Application portability module code. + * + * @addtogroup application_portability + * @{ + */ + +#include "hal.h" + +#include "portab.h" + +/*===========================================================================*/ +/* Module local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module exported functions. */ +/*===========================================================================*/ + +void portab_setup(void) { + +} + +/** @} */ diff --git a/testhal/AT32/multi/USB_CDC/cfg/at-start-f402/portab.h b/testhal/AT32/multi/USB_CDC/cfg/at-start-f402/portab.h new file mode 100644 index 0000000000..42ddef6c9e --- /dev/null +++ b/testhal/AT32/multi/USB_CDC/cfg/at-start-f402/portab.h @@ -0,0 +1,78 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file portab.h + * @brief Application portability macros and structures. + * + * @addtogroup application_portability + * @{ + */ + +#ifndef PORTAB_H +#define PORTAB_H + +/*===========================================================================*/ +/* Module constants. */ +/*===========================================================================*/ + +#define PORTAB_USB1 USBD1 + +#define PORTAB_SDU1 SDU1 + +#define PORTAB_BLINK_LED1 LINE_LED_RED + +#define PORTAB_BLINK_LED2 LINE_LED_YELLOW + +#define PORTAB_BLINK_LED3 LINE_LED_GREEN + +/*===========================================================================*/ +/* Module pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void portab_setup(void); +#ifdef __cplusplus +} +#endif + +/*===========================================================================*/ +/* Module inline functions. */ +/*===========================================================================*/ + +#endif /* PORTAB_H */ + +/** @} */ diff --git a/testhal/AT32/multi/USB_CDC/cfg/at-start-f405_usbfs/chconf.h b/testhal/AT32/multi/USB_CDC/cfg/at-start-f405_usbfs/chconf.h new file mode 100644 index 0000000000..56fe06776a --- /dev/null +++ b/testhal/AT32/multi/USB_CDC/cfg/at-start-f405_usbfs/chconf.h @@ -0,0 +1,842 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_7_0_ + +/*===========================================================================*/ +/** + * @name System settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Handling of instances. + * @note If enabled then threads assigned to various instances can + * interact each other using the same synchronization objects. + * If disabled then each OS instance is a separate world, no + * direct interactions are handled by the OS. + */ +#if !defined(CH_CFG_SMP_MODE) +#define CH_CFG_SMP_MODE FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_ST_RESOLUTION) +#define CH_CFG_ST_RESOLUTION 32 +#endif + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_CFG_ST_FREQUENCY) +#define CH_CFG_ST_FREQUENCY 10000 +#endif + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_INTERVALS_SIZE) +#define CH_CFG_INTERVALS_SIZE 32 +#endif + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_TIME_TYPES_SIZE) +#define CH_CFG_TIME_TYPES_SIZE 32 +#endif + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#if !defined(CH_CFG_ST_TIMEDELTA) +#define CH_CFG_ST_TIMEDELTA 2 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#if !defined(CH_CFG_TIME_QUANTUM) +#define CH_CFG_TIME_QUANTUM 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#if !defined(CH_CFG_NO_IDLE_THREAD) +#define CH_CFG_NO_IDLE_THREAD FALSE +#endif + +/** + * @brief Kernel hardening level. + * @details This option is the level of functional-safety checks enabled + * in the kerkel. The meaning is: + * - 0: No checks, maximum performance. + * - 1: Reasonable checks. + * - 2: All checks. + * . + */ +#if !defined(CH_CFG_HARDENING_LEVEL) +#define CH_CFG_HARDENING_LEVEL 0 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_OPTIMIZE_SPEED) +#define CH_CFG_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TM) +#define CH_CFG_USE_TM TRUE +#endif + +/** + * @brief Time Stamps APIs. + * @details If enabled then the time stamps APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TIMESTAMP) +#define CH_CFG_USE_TIMESTAMP TRUE +#endif + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_REGISTRY) +#define CH_CFG_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_WAITEXIT) +#define CH_CFG_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_SEMAPHORES) +#define CH_CFG_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MUTEXES) +#define CH_CFG_USE_MUTEXES TRUE +#endif + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_CONDVARS) +#define CH_CFG_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_EVENTS) +#define CH_CFG_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MESSAGES) +#define CH_CFG_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#if !defined(CH_CFG_USE_DYNAMIC) +#define CH_CFG_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name OSLIB options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_MAILBOXES) +#define CH_CFG_USE_MAILBOXES TRUE +#endif + +/** + * @brief Memory checks APIs. + * @details If enabled then the memory checks APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCHECKS) +#define CH_CFG_USE_MEMCHECKS TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCORE) +#define CH_CFG_USE_MEMCORE TRUE +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#if !defined(CH_CFG_MEMCORE_SIZE) +#define CH_CFG_MEMCORE_SIZE 0 +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_CFG_USE_HEAP) +#define CH_CFG_USE_HEAP TRUE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMPOOLS) +#define CH_CFG_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_FIFOS) +#define CH_CFG_USE_OBJ_FIFOS TRUE +#endif + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Objects Caches APIs. + * @details If enabled then the objects caches APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_CACHES) +#define CH_CFG_USE_OBJ_CACHES TRUE +#endif + +/** + * @brief Delegate threads APIs. + * @details If enabled then the delegate threads APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_DELEGATES) +#define CH_CFG_USE_DELEGATES TRUE +#endif + +/** + * @brief Jobs Queues APIs. + * @details If enabled then the jobs queues APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_JOBS) +#define CH_CFG_USE_JOBS TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_CFG_USE_FACTORY) +#define CH_CFG_USE_FACTORY TRUE +#endif + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 +#endif + +/** + * @brief Enables the registry of generic objects. + */ +#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE +#endif + +/** + * @brief Enables factory for generic buffers. + */ +#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE +#endif + +/** + * @brief Enables factory for semaphores. + */ +#if !defined(CH_CFG_FACTORY_SEMAPHORES) +#define CH_CFG_FACTORY_SEMAPHORES TRUE +#endif + +/** + * @brief Enables factory for mailboxes. + */ +#if !defined(CH_CFG_FACTORY_MAILBOXES) +#define CH_CFG_FACTORY_MAILBOXES TRUE +#endif + +/** + * @brief Enables factory for objects FIFOs. + */ +#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE +#endif + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_STATISTICS) +#define CH_DBG_STATISTICS FALSE +#endif + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_MASK) +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_ALL +#endif + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_BUFFER_SIZE) +#define CH_DBG_TRACE_BUFFER_SIZE 128 +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#if !defined(CH_DBG_THREADS_PROFILING) +#define CH_DBG_THREADS_PROFILING FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add system custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add system initialization code here.*/ \ +} + +/** + * @brief OS instance structure extension. + * @details User fields added to the end of the @p os_instance_t structure. + */ +#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS \ + /* Add OS instance custom fields here.*/ + +/** + * @brief OS instance initialization hook. + * + * @param[in] oip pointer to the @p os_instance_t structure + */ +#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) { \ + /* Add OS instance initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + * + * @param[in] ntp thread being switched in + * @param[in] otp thread being switched out + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** + * @brief Runtime Faults Collection Unit hook. + * @details This hook is invoked each time new faults are collected and stored. + */ +#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) { \ + /* Faults handling code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/testhal/AT32/multi/USB_CDC/cfg/at-start-f405_usbfs/config.h b/testhal/AT32/multi/USB_CDC/cfg/at-start-f405_usbfs/config.h new file mode 100644 index 0000000000..1e7c044f47 --- /dev/null +++ b/testhal/AT32/multi/USB_CDC/cfg/at-start-f405_usbfs/config.h @@ -0,0 +1,39 @@ +/* + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * CRC driver system settings. + */ +#define AT32_CRC_USE_CRC1 FALSE + +#define CRC_USE_DMA FALSE +#define AT32_CRC_CRC1_DMA_PRIORITY 2 +#define AT32_CRC_CRC1_IRQ_PRIORITY 5 +#define AT32_CRC_CRC1_DMA_STREAM AT32_DMA_STREAM_ID_ANY + +/* + * I2C fallback driver system settings. + */ +#define SW_I2C_USE_I2C1 FALSE +#define SW_I2C_USE_I2C2 FALSE +#define SW_I2C_USE_I2C3 FALSE +#define SW_I2C_USE_I2C4 FALSE + +/* + * Other settings. + */ +#define BOARD_OTG_VBUSIG diff --git a/testhal/AT32/multi/USB_CDC/cfg/at-start-f405_usbfs/halconf.h b/testhal/AT32/multi/USB_CDC/cfg/at-start-f405_usbfs/halconf.h new file mode 100644 index 0000000000..5419a662a8 --- /dev/null +++ b/testhal/AT32/multi/USB_CDC/cfg/at-start-f405_usbfs/halconf.h @@ -0,0 +1,557 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_8_4_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the EFlash subsystem. + */ +#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__) +#define HAL_USE_EFL FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB TRUE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB TRUE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/** + * @brief Enables the WSPI subsystem. + */ +#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) +#define HAL_USE_WSPI FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS FALSE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS FALSE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Timeout before assuming a failure while waiting for card idle. + * @note Time is in milliseconds. + */ +#if !defined(MMC_IDLE_TIMEOUT_MS) || defined(__DOXYGEN__) +#define MMC_IDLE_TIMEOUT_MS 1000 +#endif + +/** + * @brief Mutual exclusion on the SPI bus. + */ +#if !defined(MMC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define MMC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SIO driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SIO_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SIO_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Support for thread synchronization API. + */ +#if !defined(SIO_USE_SYNCHRONIZATION) || defined(__DOXYGEN__) +#define SIO_USE_SYNCHRONIZATION TRUE +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 256 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 2 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Inserts an assertion on function errors before returning. + */ +#if !defined(SPI_USE_ASSERT_ON_ERROR) || defined(__DOXYGEN__) +#define SPI_USE_ASSERT_ON_ERROR TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#include "halconf_community.h" + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/testhal/AT32/multi/USB_CDC/cfg/at-start-f405_usbfs/halconf_community.h b/testhal/AT32/multi/USB_CDC/cfg/at-start-f405_usbfs/halconf_community.h new file mode 100644 index 0000000000..5a77290c71 --- /dev/null +++ b/testhal/AT32/multi/USB_CDC/cfg/at-start-f405_usbfs/halconf_community.h @@ -0,0 +1,182 @@ +/* + ChibiOS - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef HALCONF_COMMUNITY_H +#define HALCONF_COMMUNITY_H + +/** + * @brief Enables the community overlay. + */ +#if !defined(HAL_USE_COMMUNITY) || defined(__DOXYGEN__) +#define HAL_USE_COMMUNITY TRUE +#endif + +/** + * @brief Enables the FSMC subsystem. + */ +#if !defined(HAL_USE_FSMC) || defined(__DOXYGEN__) +#define HAL_USE_FSMC FALSE +#endif + +/** + * @brief Enables the NAND subsystem. + */ +#if !defined(HAL_USE_NAND) || defined(__DOXYGEN__) +#define HAL_USE_NAND FALSE +#endif + +/** + * @brief Enables the 1-wire subsystem. + */ +#if !defined(HAL_USE_ONEWIRE) || defined(__DOXYGEN__) +#define HAL_USE_ONEWIRE FALSE +#endif + +/** + * @brief Enables the EICU subsystem. + */ +#if !defined(HAL_USE_EICU) || defined(__DOXYGEN__) +#define HAL_USE_EICU FALSE +#endif + +/** + * @brief Enables the CRC subsystem. + */ +#if !defined(HAL_USE_CRC) || defined(__DOXYGEN__) +#define HAL_USE_CRC FALSE +#endif + +/** + * @brief Enables the RNG subsystem. + */ +#if !defined(HAL_USE_RNG) || defined(__DOXYGEN__) +#define HAL_USE_RNG FALSE +#endif + +/** + * @brief Enables the EEPROM subsystem. + */ +#if !defined(HAL_USE_EEPROM) || defined(__DOXYGEN__) +#define HAL_USE_EEPROM FALSE +#endif + +/** + * @brief Enables the TIMCAP subsystem. + */ +#if !defined(HAL_USE_TIMCAP) || defined(__DOXYGEN__) +#define HAL_USE_TIMCAP FALSE +#endif + +/** + * @brief Enables the COMP subsystem. + */ +#if !defined(HAL_USE_COMP) || defined(__DOXYGEN__) +#define HAL_USE_COMP FALSE +#endif + +/** + * @brief Enables the OPAMP subsystem. + */ +#if !defined(HAL_USE_OPAMP) || defined(__DOXYGEN__) +#define HAL_USE_OPAMP FALSE +#endif + +/** + * @brief Enables the QEI subsystem. + */ +#if !defined(HAL_USE_QEI) || defined(__DOXYGEN__) +#define HAL_USE_QEI FALSE +#endif + +/** + * @brief Enables the USBH subsystem. + */ +#if !defined(HAL_USE_USBH) || defined(__DOXYGEN__) +#define HAL_USE_USBH FALSE +#endif + +/** + * @brief Enables the USB_MSD subsystem. + */ +#if !defined(HAL_USE_USB_MSD) || defined(__DOXYGEN__) +#define HAL_USE_USB_MSD FALSE +#endif + +/*===========================================================================*/ +/* FSMCNAND driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the @p nandAcquireBus() and @p nanReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(NAND_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define NAND_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* 1-wire driver related settings. */ +/*===========================================================================*/ +/** + * @brief Enables strong pull up feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_STRONG_PULLUP FALSE + +/** + * @brief Enables search ROM feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_SEARCH_ROM TRUE + +/*===========================================================================*/ +/* QEI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables discard of overlow + */ +#if !defined(QEI_USE_OVERFLOW_DISCARD) || defined(__DOXYGEN__) +#define QEI_USE_OVERFLOW_DISCARD FALSE +#endif + +/** + * @brief Enables min max of overlow + */ +#if !defined(QEI_USE_OVERFLOW_MINMAX) || defined(__DOXYGEN__) +#define QEI_USE_OVERFLOW_MINMAX FALSE +#endif + +/*===========================================================================*/ +/* EEProm driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables 24xx series I2C eeprom device driver. + * @note Disabling this option saves both code and data space. + */ +#define EEPROM_USE_EE24XX FALSE + /** + * @brief Enables 25xx series SPI eeprom device driver. + * @note Disabling this option saves both code and data space. + */ +#define EEPROM_USE_EE25XX FALSE + +#endif /* HALCONF_COMMUNITY_H */ + +/** @} */ diff --git a/testhal/AT32/multi/USB_CDC/cfg/at-start-f405_usbfs/mcuconf.h b/testhal/AT32/multi/USB_CDC/cfg/at-start-f405_usbfs/mcuconf.h new file mode 100644 index 0000000000..e91d34e63f --- /dev/null +++ b/testhal/AT32/multi/USB_CDC/cfg/at-start-f405_usbfs/mcuconf.h @@ -0,0 +1,271 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef MCUCONF_H +#define MCUCONF_H + +/* + * AT32F405 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define AT32F405_MCUCONF + +/* + * General settings. + */ +#define AT32_NO_INIT FALSE + +/* + * HAL driver system settings. + */ +#define AT32_HICK_ENABLED TRUE +#define AT32_LICK_ENABLED FALSE +#define AT32_HEXT_ENABLED TRUE +#define AT32_LEXT_ENABLED FALSE +#define AT32_PLLU_ENABLED TRUE +#define AT32_SCLKSEL AT32_SCLKSEL_PLL +#define AT32_PLLRCS AT32_PLLRCS_HEXT +#define AT32_PLL_MS_VALUE 1 +#define AT32_PLL_NS_VALUE 72 +#define AT32_PLL_FP_VALUE 4 +#define AT32_PLL_FU_VALUE 18 +#define AT32_AHBDIV AT32_AHBDIV_DIV1 +#define AT32_APB1DIV AT32_APB1DIV_DIV2 +#define AT32_APB2DIV AT32_APB2DIV_DIV1 +#define AT32_HICK_TO_SCLK AT32_HICK_TO_SCLK_48M +#define AT32_HICKDIV AT32_HICKDIV_DIV1 +#define AT32_HICK_TO_SCLK_DIV AT32_HICK_TO_SCLK_DIV_DIV1 +#define AT32_HEXT_TO_SCLK_DIV AT32_HEXT_TO_SCLK_DIV_DIV1 +#define AT32_USB_CLOCK48_REQUIRED TRUE +#define AT32_PLLU_USB48_SEL AT32_PLLU_USB48_SEL_PLLU +#define AT32_CLKOUT_SEL AT32_CLKOUT_SEL_HICK +#define AT32_CLKOUTDIV1 AT32_CLKOUTDIV1_DIV1 +#define AT32_CLKOUTDIV2 AT32_CLKOUTDIV2_DIV1 +#define AT32_ERTCSEL AT32_ERTCSEL_NOCLOCK +#define AT32_ERTCDIV_VALUE 12 +#define AT32_I2SF5CLKSEL AT32_I2SF5CLKSEL_SCLK +#define AT32_PVM_ENABLE FALSE +#define AT32_PVMSEL AT32_PVMSEL_LEV1 +#define AT32_LDOOVSEL AT32_LDOOVSEL_LEV3 + +/* + * IRQ system settings. + */ +#define AT32_IRQ_EXINT0_PRIORITY 6 +#define AT32_IRQ_EXINT1_PRIORITY 6 +#define AT32_IRQ_EXINT2_PRIORITY 6 +#define AT32_IRQ_EXINT3_PRIORITY 6 +#define AT32_IRQ_EXINT4_PRIORITY 6 +#define AT32_IRQ_EXINT5_9_PRIORITY 6 +#define AT32_IRQ_EXINT10_15_PRIORITY 6 +#define AT32_IRQ_EXINT16_PRIORITY 6 +#define AT32_IRQ_EXINT17_PRIORITY 15 +#define AT32_IRQ_EXINT18_PRIORITY 6 +#define AT32_IRQ_EXINT20_PRIORITY 6 +#define AT32_IRQ_EXINT21_PRIORITY 15 +#define AT32_IRQ_EXINT22_PRIORITY 15 + +#define AT32_IRQ_TMR1_BRK_TMR9_PRIORITY 7 +#define AT32_IRQ_TMR1_OVF_TMR10_PRIORITY 7 +#define AT32_IRQ_TMR1_HALL_TMR11_PRIORITY 7 +#define AT32_IRQ_TMR1_CH_PRIORITY 7 +#define AT32_IRQ_TMR2_PRIORITY 7 +#define AT32_IRQ_TMR3_PRIORITY 7 +#define AT32_IRQ_TMR4_PRIORITY 7 +#define AT32_IRQ_TMR6_PRIORITY 7 +#define AT32_IRQ_TMR7_PRIORITY 7 +#define AT32_IRQ_TMR13_PRIORITY 7 +#define AT32_IRQ_TMR14_PRIORITY 7 + +#define AT32_IRQ_USART1_PRIORITY 12 +#define AT32_IRQ_USART2_PRIORITY 12 +#define AT32_IRQ_USART3_PRIORITY 12 +#define AT32_IRQ_UART4_PRIORITY 12 +#define AT32_IRQ_UART5_PRIORITY 12 +#define AT32_IRQ_USART6_PRIORITY 12 +#define AT32_IRQ_UART7_PRIORITY 12 +#define AT32_IRQ_UART8_PRIORITY 12 + +/* + * ADC driver system settings. + */ +#define AT32_ADC_USE_ADC1 FALSE +#define AT32_ADC_ADC1_DMA_PRIORITY 2 +#define AT32_ADC_IRQ_PRIORITY 6 +#define AT32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define AT32_ADC_ADCDIV 8 + +/* + * CAN driver system settings. + */ +#define AT32_CAN_USE_CAN1 FALSE +#define AT32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * GPT driver system settings. + */ +#define AT32_GPT_USE_TMR1 FALSE +#define AT32_GPT_USE_TMR2 FALSE +#define AT32_GPT_USE_TMR3 FALSE +#define AT32_GPT_USE_TMR4 FALSE +#define AT32_GPT_USE_TMR6 FALSE +#define AT32_GPT_USE_TMR7 FALSE +#define AT32_GPT_USE_TMR9 FALSE +#define AT32_GPT_USE_TMR10 FALSE +#define AT32_GPT_USE_TMR11 FALSE +#define AT32_GPT_USE_TMR13 FALSE +#define AT32_GPT_USE_TMR14 FALSE + +/* + * I2C driver system settings. + */ +#define AT32_I2C_USE_I2C1 FALSE +#define AT32_I2C_USE_I2C2 FALSE +#define AT32_I2C_USE_I2C3 FALSE +#define AT32_I2C_BUSY_TIMEOUT 50 +#define AT32_I2C_I2C1_DMA_PRIORITY 3 +#define AT32_I2C_I2C2_DMA_PRIORITY 3 +#define AT32_I2C_I2C3_DMA_PRIORITY 3 +#define AT32_I2C_I2C1_IRQ_PRIORITY 5 +#define AT32_I2C_I2C2_IRQ_PRIORITY 5 +#define AT32_I2C_I2C3_IRQ_PRIORITY 5 +#define AT32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define AT32_ICU_USE_TMR1 FALSE +#define AT32_ICU_USE_TMR2 FALSE +#define AT32_ICU_USE_TMR3 FALSE +#define AT32_ICU_USE_TMR4 FALSE +#define AT32_ICU_USE_TMR9 FALSE + +/* + * PWM driver system settings. + */ +#define AT32_PWM_USE_TMR1 FALSE +#define AT32_PWM_USE_TMR2 FALSE +#define AT32_PWM_USE_TMR3 FALSE +#define AT32_PWM_USE_TMR4 FALSE +#define AT32_PWM_USE_TMR9 FALSE +#define AT32_PWM_USE_TMR10 FALSE +#define AT32_PWM_USE_TMR11 FALSE +#define AT32_PWM_USE_TMR13 FALSE +#define AT32_PWM_USE_TMR14 FALSE + +/* + * RTC driver system settings. + */ +#define AT32_ERTC_DIVA_VALUE 32 +#define AT32_ERTC_DIVB_VALUE 1024 +#define AT32_ERTC_CTRL_INIT 0 +#define AT32_ERTC_TAMP_INIT 0 + +/* + * SERIAL driver system settings. + */ +#define AT32_SERIAL_USE_USART1 FALSE +#define AT32_SERIAL_USE_USART2 FALSE +#define AT32_SERIAL_USE_USART3 FALSE +#define AT32_SERIAL_USE_UART4 FALSE +#define AT32_SERIAL_USE_UART5 FALSE +#define AT32_SERIAL_USE_USART6 FALSE +#define AT32_SERIAL_USE_UART7 FALSE +#define AT32_SERIAL_USE_UART8 FALSE + +/* + * SIO driver system settings. + */ +#define AT32_SIO_USE_USART1 FALSE +#define AT32_SIO_USE_USART2 FALSE +#define AT32_SIO_USE_USART3 FALSE +#define AT32_SIO_USE_UART4 FALSE +#define AT32_SIO_USE_UART5 FALSE +#define AT32_SIO_USE_USART6 FALSE +#define AT32_SIO_USE_UART7 FALSE +#define AT32_SIO_USE_UART8 FALSE + +/* + * SPI driver system settings. + */ +#define AT32_SPI_USE_SPI1 FALSE +#define AT32_SPI_USE_SPI2 FALSE +#define AT32_SPI_USE_SPI3 FALSE +#define AT32_SPI_SPI1_DMA_PRIORITY 1 +#define AT32_SPI_SPI2_DMA_PRIORITY 1 +#define AT32_SPI_SPI3_DMA_PRIORITY 1 +#define AT32_SPI_SPI1_IRQ_PRIORITY 10 +#define AT32_SPI_SPI2_IRQ_PRIORITY 10 +#define AT32_SPI_SPI3_IRQ_PRIORITY 10 +#define AT32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define AT32_ST_IRQ_PRIORITY 8 +#define AT32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define AT32_UART_USE_USART1 FALSE +#define AT32_UART_USE_USART2 FALSE +#define AT32_UART_USE_USART3 FALSE +#define AT32_UART_USE_UART4 FALSE +#define AT32_UART_USE_UART5 FALSE +#define AT32_UART_USE_USART6 FALSE +#define AT32_UART_USE_UART7 FALSE +#define AT32_UART_USE_UART8 FALSE +#define AT32_UART_USART1_DMA_PRIORITY 0 +#define AT32_UART_USART2_DMA_PRIORITY 0 +#define AT32_UART_USART3_DMA_PRIORITY 0 +#define AT32_UART_UART4_DMA_PRIORITY 0 +#define AT32_UART_UART5_DMA_PRIORITY 0 +#define AT32_UART_USART6_DMA_PRIORITY 0 +#define AT32_UART_UART7_DMA_PRIORITY 0 +#define AT32_UART_UART8_DMA_PRIORITY 0 +#define AT32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define AT32_USB_USE_OTG1 TRUE +#define AT32_USB_USE_OTG2 FALSE +#define AT32_USB_OTG1_IRQ_PRIORITY 14 +#define AT32_USB_OTG2_IRQ_PRIORITY 14 +#define AT32_USB_OTG1_RX_FIFO_SIZE 512 +#define AT32_USB_OTG2_RX_FIFO_SIZE 1024 + +/* + * WDG driver system settings. + */ +#define AT32_WDG_USE_WDT FALSE + +#include "config.h" + +#endif /* MCUCONF_H */ diff --git a/testhal/AT32/multi/USB_CDC/cfg/at-start-f405_usbfs/portab.c b/testhal/AT32/multi/USB_CDC/cfg/at-start-f405_usbfs/portab.c new file mode 100644 index 0000000000..ceaf0ff400 --- /dev/null +++ b/testhal/AT32/multi/USB_CDC/cfg/at-start-f405_usbfs/portab.c @@ -0,0 +1,59 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file portab.c + * @brief Application portability module code. + * + * @addtogroup application_portability + * @{ + */ + +#include "hal.h" + +#include "portab.h" + +/*===========================================================================*/ +/* Module local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module exported functions. */ +/*===========================================================================*/ + +void portab_setup(void) { + +} + +/** @} */ diff --git a/testhal/AT32/multi/USB_CDC/cfg/at-start-f405_usbfs/portab.h b/testhal/AT32/multi/USB_CDC/cfg/at-start-f405_usbfs/portab.h new file mode 100644 index 0000000000..42ddef6c9e --- /dev/null +++ b/testhal/AT32/multi/USB_CDC/cfg/at-start-f405_usbfs/portab.h @@ -0,0 +1,78 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file portab.h + * @brief Application portability macros and structures. + * + * @addtogroup application_portability + * @{ + */ + +#ifndef PORTAB_H +#define PORTAB_H + +/*===========================================================================*/ +/* Module constants. */ +/*===========================================================================*/ + +#define PORTAB_USB1 USBD1 + +#define PORTAB_SDU1 SDU1 + +#define PORTAB_BLINK_LED1 LINE_LED_RED + +#define PORTAB_BLINK_LED2 LINE_LED_YELLOW + +#define PORTAB_BLINK_LED3 LINE_LED_GREEN + +/*===========================================================================*/ +/* Module pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void portab_setup(void); +#ifdef __cplusplus +} +#endif + +/*===========================================================================*/ +/* Module inline functions. */ +/*===========================================================================*/ + +#endif /* PORTAB_H */ + +/** @} */ diff --git a/testhal/AT32/multi/USB_CDC/cfg/at-start-f405_usbhs-dma/chconf.h b/testhal/AT32/multi/USB_CDC/cfg/at-start-f405_usbhs-dma/chconf.h new file mode 100644 index 0000000000..56fe06776a --- /dev/null +++ b/testhal/AT32/multi/USB_CDC/cfg/at-start-f405_usbhs-dma/chconf.h @@ -0,0 +1,842 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_7_0_ + +/*===========================================================================*/ +/** + * @name System settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Handling of instances. + * @note If enabled then threads assigned to various instances can + * interact each other using the same synchronization objects. + * If disabled then each OS instance is a separate world, no + * direct interactions are handled by the OS. + */ +#if !defined(CH_CFG_SMP_MODE) +#define CH_CFG_SMP_MODE FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_ST_RESOLUTION) +#define CH_CFG_ST_RESOLUTION 32 +#endif + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_CFG_ST_FREQUENCY) +#define CH_CFG_ST_FREQUENCY 10000 +#endif + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_INTERVALS_SIZE) +#define CH_CFG_INTERVALS_SIZE 32 +#endif + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_TIME_TYPES_SIZE) +#define CH_CFG_TIME_TYPES_SIZE 32 +#endif + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#if !defined(CH_CFG_ST_TIMEDELTA) +#define CH_CFG_ST_TIMEDELTA 2 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#if !defined(CH_CFG_TIME_QUANTUM) +#define CH_CFG_TIME_QUANTUM 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#if !defined(CH_CFG_NO_IDLE_THREAD) +#define CH_CFG_NO_IDLE_THREAD FALSE +#endif + +/** + * @brief Kernel hardening level. + * @details This option is the level of functional-safety checks enabled + * in the kerkel. The meaning is: + * - 0: No checks, maximum performance. + * - 1: Reasonable checks. + * - 2: All checks. + * . + */ +#if !defined(CH_CFG_HARDENING_LEVEL) +#define CH_CFG_HARDENING_LEVEL 0 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_OPTIMIZE_SPEED) +#define CH_CFG_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TM) +#define CH_CFG_USE_TM TRUE +#endif + +/** + * @brief Time Stamps APIs. + * @details If enabled then the time stamps APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TIMESTAMP) +#define CH_CFG_USE_TIMESTAMP TRUE +#endif + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_REGISTRY) +#define CH_CFG_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_WAITEXIT) +#define CH_CFG_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_SEMAPHORES) +#define CH_CFG_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MUTEXES) +#define CH_CFG_USE_MUTEXES TRUE +#endif + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_CONDVARS) +#define CH_CFG_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_EVENTS) +#define CH_CFG_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MESSAGES) +#define CH_CFG_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#if !defined(CH_CFG_USE_DYNAMIC) +#define CH_CFG_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name OSLIB options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_MAILBOXES) +#define CH_CFG_USE_MAILBOXES TRUE +#endif + +/** + * @brief Memory checks APIs. + * @details If enabled then the memory checks APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCHECKS) +#define CH_CFG_USE_MEMCHECKS TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCORE) +#define CH_CFG_USE_MEMCORE TRUE +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#if !defined(CH_CFG_MEMCORE_SIZE) +#define CH_CFG_MEMCORE_SIZE 0 +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_CFG_USE_HEAP) +#define CH_CFG_USE_HEAP TRUE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMPOOLS) +#define CH_CFG_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_FIFOS) +#define CH_CFG_USE_OBJ_FIFOS TRUE +#endif + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Objects Caches APIs. + * @details If enabled then the objects caches APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_CACHES) +#define CH_CFG_USE_OBJ_CACHES TRUE +#endif + +/** + * @brief Delegate threads APIs. + * @details If enabled then the delegate threads APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_DELEGATES) +#define CH_CFG_USE_DELEGATES TRUE +#endif + +/** + * @brief Jobs Queues APIs. + * @details If enabled then the jobs queues APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_JOBS) +#define CH_CFG_USE_JOBS TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_CFG_USE_FACTORY) +#define CH_CFG_USE_FACTORY TRUE +#endif + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 +#endif + +/** + * @brief Enables the registry of generic objects. + */ +#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE +#endif + +/** + * @brief Enables factory for generic buffers. + */ +#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE +#endif + +/** + * @brief Enables factory for semaphores. + */ +#if !defined(CH_CFG_FACTORY_SEMAPHORES) +#define CH_CFG_FACTORY_SEMAPHORES TRUE +#endif + +/** + * @brief Enables factory for mailboxes. + */ +#if !defined(CH_CFG_FACTORY_MAILBOXES) +#define CH_CFG_FACTORY_MAILBOXES TRUE +#endif + +/** + * @brief Enables factory for objects FIFOs. + */ +#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE +#endif + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_STATISTICS) +#define CH_DBG_STATISTICS FALSE +#endif + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_MASK) +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_ALL +#endif + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_BUFFER_SIZE) +#define CH_DBG_TRACE_BUFFER_SIZE 128 +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#if !defined(CH_DBG_THREADS_PROFILING) +#define CH_DBG_THREADS_PROFILING FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add system custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add system initialization code here.*/ \ +} + +/** + * @brief OS instance structure extension. + * @details User fields added to the end of the @p os_instance_t structure. + */ +#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS \ + /* Add OS instance custom fields here.*/ + +/** + * @brief OS instance initialization hook. + * + * @param[in] oip pointer to the @p os_instance_t structure + */ +#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) { \ + /* Add OS instance initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + * + * @param[in] ntp thread being switched in + * @param[in] otp thread being switched out + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** + * @brief Runtime Faults Collection Unit hook. + * @details This hook is invoked each time new faults are collected and stored. + */ +#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) { \ + /* Faults handling code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/testhal/AT32/multi/USB_CDC/cfg/at-start-f405_usbhs-dma/config.h b/testhal/AT32/multi/USB_CDC/cfg/at-start-f405_usbhs-dma/config.h new file mode 100644 index 0000000000..1e7c044f47 --- /dev/null +++ b/testhal/AT32/multi/USB_CDC/cfg/at-start-f405_usbhs-dma/config.h @@ -0,0 +1,39 @@ +/* + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * CRC driver system settings. + */ +#define AT32_CRC_USE_CRC1 FALSE + +#define CRC_USE_DMA FALSE +#define AT32_CRC_CRC1_DMA_PRIORITY 2 +#define AT32_CRC_CRC1_IRQ_PRIORITY 5 +#define AT32_CRC_CRC1_DMA_STREAM AT32_DMA_STREAM_ID_ANY + +/* + * I2C fallback driver system settings. + */ +#define SW_I2C_USE_I2C1 FALSE +#define SW_I2C_USE_I2C2 FALSE +#define SW_I2C_USE_I2C3 FALSE +#define SW_I2C_USE_I2C4 FALSE + +/* + * Other settings. + */ +#define BOARD_OTG_VBUSIG diff --git a/testhal/AT32/multi/USB_CDC/cfg/at-start-f405_usbhs-dma/halconf.h b/testhal/AT32/multi/USB_CDC/cfg/at-start-f405_usbhs-dma/halconf.h new file mode 100644 index 0000000000..5419a662a8 --- /dev/null +++ b/testhal/AT32/multi/USB_CDC/cfg/at-start-f405_usbhs-dma/halconf.h @@ -0,0 +1,557 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_8_4_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the EFlash subsystem. + */ +#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__) +#define HAL_USE_EFL FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB TRUE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB TRUE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/** + * @brief Enables the WSPI subsystem. + */ +#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) +#define HAL_USE_WSPI FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS FALSE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS FALSE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Timeout before assuming a failure while waiting for card idle. + * @note Time is in milliseconds. + */ +#if !defined(MMC_IDLE_TIMEOUT_MS) || defined(__DOXYGEN__) +#define MMC_IDLE_TIMEOUT_MS 1000 +#endif + +/** + * @brief Mutual exclusion on the SPI bus. + */ +#if !defined(MMC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define MMC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SIO driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SIO_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SIO_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Support for thread synchronization API. + */ +#if !defined(SIO_USE_SYNCHRONIZATION) || defined(__DOXYGEN__) +#define SIO_USE_SYNCHRONIZATION TRUE +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 256 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 2 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Inserts an assertion on function errors before returning. + */ +#if !defined(SPI_USE_ASSERT_ON_ERROR) || defined(__DOXYGEN__) +#define SPI_USE_ASSERT_ON_ERROR TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#include "halconf_community.h" + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/testhal/AT32/multi/USB_CDC/cfg/at-start-f405_usbhs-dma/halconf_community.h b/testhal/AT32/multi/USB_CDC/cfg/at-start-f405_usbhs-dma/halconf_community.h new file mode 100644 index 0000000000..5a77290c71 --- /dev/null +++ b/testhal/AT32/multi/USB_CDC/cfg/at-start-f405_usbhs-dma/halconf_community.h @@ -0,0 +1,182 @@ +/* + ChibiOS - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef HALCONF_COMMUNITY_H +#define HALCONF_COMMUNITY_H + +/** + * @brief Enables the community overlay. + */ +#if !defined(HAL_USE_COMMUNITY) || defined(__DOXYGEN__) +#define HAL_USE_COMMUNITY TRUE +#endif + +/** + * @brief Enables the FSMC subsystem. + */ +#if !defined(HAL_USE_FSMC) || defined(__DOXYGEN__) +#define HAL_USE_FSMC FALSE +#endif + +/** + * @brief Enables the NAND subsystem. + */ +#if !defined(HAL_USE_NAND) || defined(__DOXYGEN__) +#define HAL_USE_NAND FALSE +#endif + +/** + * @brief Enables the 1-wire subsystem. + */ +#if !defined(HAL_USE_ONEWIRE) || defined(__DOXYGEN__) +#define HAL_USE_ONEWIRE FALSE +#endif + +/** + * @brief Enables the EICU subsystem. + */ +#if !defined(HAL_USE_EICU) || defined(__DOXYGEN__) +#define HAL_USE_EICU FALSE +#endif + +/** + * @brief Enables the CRC subsystem. + */ +#if !defined(HAL_USE_CRC) || defined(__DOXYGEN__) +#define HAL_USE_CRC FALSE +#endif + +/** + * @brief Enables the RNG subsystem. + */ +#if !defined(HAL_USE_RNG) || defined(__DOXYGEN__) +#define HAL_USE_RNG FALSE +#endif + +/** + * @brief Enables the EEPROM subsystem. + */ +#if !defined(HAL_USE_EEPROM) || defined(__DOXYGEN__) +#define HAL_USE_EEPROM FALSE +#endif + +/** + * @brief Enables the TIMCAP subsystem. + */ +#if !defined(HAL_USE_TIMCAP) || defined(__DOXYGEN__) +#define HAL_USE_TIMCAP FALSE +#endif + +/** + * @brief Enables the COMP subsystem. + */ +#if !defined(HAL_USE_COMP) || defined(__DOXYGEN__) +#define HAL_USE_COMP FALSE +#endif + +/** + * @brief Enables the OPAMP subsystem. + */ +#if !defined(HAL_USE_OPAMP) || defined(__DOXYGEN__) +#define HAL_USE_OPAMP FALSE +#endif + +/** + * @brief Enables the QEI subsystem. + */ +#if !defined(HAL_USE_QEI) || defined(__DOXYGEN__) +#define HAL_USE_QEI FALSE +#endif + +/** + * @brief Enables the USBH subsystem. + */ +#if !defined(HAL_USE_USBH) || defined(__DOXYGEN__) +#define HAL_USE_USBH FALSE +#endif + +/** + * @brief Enables the USB_MSD subsystem. + */ +#if !defined(HAL_USE_USB_MSD) || defined(__DOXYGEN__) +#define HAL_USE_USB_MSD FALSE +#endif + +/*===========================================================================*/ +/* FSMCNAND driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the @p nandAcquireBus() and @p nanReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(NAND_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define NAND_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* 1-wire driver related settings. */ +/*===========================================================================*/ +/** + * @brief Enables strong pull up feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_STRONG_PULLUP FALSE + +/** + * @brief Enables search ROM feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_SEARCH_ROM TRUE + +/*===========================================================================*/ +/* QEI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables discard of overlow + */ +#if !defined(QEI_USE_OVERFLOW_DISCARD) || defined(__DOXYGEN__) +#define QEI_USE_OVERFLOW_DISCARD FALSE +#endif + +/** + * @brief Enables min max of overlow + */ +#if !defined(QEI_USE_OVERFLOW_MINMAX) || defined(__DOXYGEN__) +#define QEI_USE_OVERFLOW_MINMAX FALSE +#endif + +/*===========================================================================*/ +/* EEProm driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables 24xx series I2C eeprom device driver. + * @note Disabling this option saves both code and data space. + */ +#define EEPROM_USE_EE24XX FALSE + /** + * @brief Enables 25xx series SPI eeprom device driver. + * @note Disabling this option saves both code and data space. + */ +#define EEPROM_USE_EE25XX FALSE + +#endif /* HALCONF_COMMUNITY_H */ + +/** @} */ diff --git a/testhal/AT32/multi/USB_CDC/cfg/at-start-f405_usbhs-dma/mcuconf.h b/testhal/AT32/multi/USB_CDC/cfg/at-start-f405_usbhs-dma/mcuconf.h new file mode 100644 index 0000000000..c83fc95efc --- /dev/null +++ b/testhal/AT32/multi/USB_CDC/cfg/at-start-f405_usbhs-dma/mcuconf.h @@ -0,0 +1,272 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef MCUCONF_H +#define MCUCONF_H + +/* + * AT32F405 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define AT32F405_MCUCONF + +/* + * General settings. + */ +#define AT32_NO_INIT FALSE + +/* + * HAL driver system settings. + */ +#define AT32_HICK_ENABLED TRUE +#define AT32_LICK_ENABLED FALSE +#define AT32_HEXT_ENABLED TRUE +#define AT32_LEXT_ENABLED FALSE +#define AT32_PLLU_ENABLED TRUE +#define AT32_SCLKSEL AT32_SCLKSEL_PLL +#define AT32_PLLRCS AT32_PLLRCS_HEXT +#define AT32_PLL_MS_VALUE 1 +#define AT32_PLL_NS_VALUE 72 +#define AT32_PLL_FP_VALUE 4 +#define AT32_PLL_FU_VALUE 18 +#define AT32_AHBDIV AT32_AHBDIV_DIV1 +#define AT32_APB1DIV AT32_APB1DIV_DIV2 +#define AT32_APB2DIV AT32_APB2DIV_DIV1 +#define AT32_HICK_TO_SCLK AT32_HICK_TO_SCLK_48M +#define AT32_HICKDIV AT32_HICKDIV_DIV1 +#define AT32_HICK_TO_SCLK_DIV AT32_HICK_TO_SCLK_DIV_DIV1 +#define AT32_HEXT_TO_SCLK_DIV AT32_HEXT_TO_SCLK_DIV_DIV1 +#define AT32_USB_CLOCK48_REQUIRED TRUE +#define AT32_PLLU_USB48_SEL AT32_PLLU_USB48_SEL_PLLU +#define AT32_CLKOUT_SEL AT32_CLKOUT_SEL_HICK +#define AT32_CLKOUTDIV1 AT32_CLKOUTDIV1_DIV1 +#define AT32_CLKOUTDIV2 AT32_CLKOUTDIV2_DIV1 +#define AT32_ERTCSEL AT32_ERTCSEL_NOCLOCK +#define AT32_ERTCDIV_VALUE 12 +#define AT32_I2SF5CLKSEL AT32_I2SF5CLKSEL_SCLK +#define AT32_PVM_ENABLE FALSE +#define AT32_PVMSEL AT32_PVMSEL_LEV1 +#define AT32_LDOOVSEL AT32_LDOOVSEL_LEV3 + +/* + * IRQ system settings. + */ +#define AT32_IRQ_EXINT0_PRIORITY 6 +#define AT32_IRQ_EXINT1_PRIORITY 6 +#define AT32_IRQ_EXINT2_PRIORITY 6 +#define AT32_IRQ_EXINT3_PRIORITY 6 +#define AT32_IRQ_EXINT4_PRIORITY 6 +#define AT32_IRQ_EXINT5_9_PRIORITY 6 +#define AT32_IRQ_EXINT10_15_PRIORITY 6 +#define AT32_IRQ_EXINT16_PRIORITY 6 +#define AT32_IRQ_EXINT17_PRIORITY 15 +#define AT32_IRQ_EXINT18_PRIORITY 6 +#define AT32_IRQ_EXINT20_PRIORITY 6 +#define AT32_IRQ_EXINT21_PRIORITY 15 +#define AT32_IRQ_EXINT22_PRIORITY 15 + +#define AT32_IRQ_TMR1_BRK_TMR9_PRIORITY 7 +#define AT32_IRQ_TMR1_OVF_TMR10_PRIORITY 7 +#define AT32_IRQ_TMR1_HALL_TMR11_PRIORITY 7 +#define AT32_IRQ_TMR1_CH_PRIORITY 7 +#define AT32_IRQ_TMR2_PRIORITY 7 +#define AT32_IRQ_TMR3_PRIORITY 7 +#define AT32_IRQ_TMR4_PRIORITY 7 +#define AT32_IRQ_TMR6_PRIORITY 7 +#define AT32_IRQ_TMR7_PRIORITY 7 +#define AT32_IRQ_TMR13_PRIORITY 7 +#define AT32_IRQ_TMR14_PRIORITY 7 + +#define AT32_IRQ_USART1_PRIORITY 12 +#define AT32_IRQ_USART2_PRIORITY 12 +#define AT32_IRQ_USART3_PRIORITY 12 +#define AT32_IRQ_UART4_PRIORITY 12 +#define AT32_IRQ_UART5_PRIORITY 12 +#define AT32_IRQ_USART6_PRIORITY 12 +#define AT32_IRQ_UART7_PRIORITY 12 +#define AT32_IRQ_UART8_PRIORITY 12 + +/* + * ADC driver system settings. + */ +#define AT32_ADC_USE_ADC1 FALSE +#define AT32_ADC_ADC1_DMA_PRIORITY 2 +#define AT32_ADC_IRQ_PRIORITY 6 +#define AT32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define AT32_ADC_ADCDIV 8 + +/* + * CAN driver system settings. + */ +#define AT32_CAN_USE_CAN1 FALSE +#define AT32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * GPT driver system settings. + */ +#define AT32_GPT_USE_TMR1 FALSE +#define AT32_GPT_USE_TMR2 FALSE +#define AT32_GPT_USE_TMR3 FALSE +#define AT32_GPT_USE_TMR4 FALSE +#define AT32_GPT_USE_TMR6 FALSE +#define AT32_GPT_USE_TMR7 FALSE +#define AT32_GPT_USE_TMR9 FALSE +#define AT32_GPT_USE_TMR10 FALSE +#define AT32_GPT_USE_TMR11 FALSE +#define AT32_GPT_USE_TMR13 FALSE +#define AT32_GPT_USE_TMR14 FALSE + +/* + * I2C driver system settings. + */ +#define AT32_I2C_USE_I2C1 FALSE +#define AT32_I2C_USE_I2C2 FALSE +#define AT32_I2C_USE_I2C3 FALSE +#define AT32_I2C_BUSY_TIMEOUT 50 +#define AT32_I2C_I2C1_DMA_PRIORITY 3 +#define AT32_I2C_I2C2_DMA_PRIORITY 3 +#define AT32_I2C_I2C3_DMA_PRIORITY 3 +#define AT32_I2C_I2C1_IRQ_PRIORITY 5 +#define AT32_I2C_I2C2_IRQ_PRIORITY 5 +#define AT32_I2C_I2C3_IRQ_PRIORITY 5 +#define AT32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define AT32_ICU_USE_TMR1 FALSE +#define AT32_ICU_USE_TMR2 FALSE +#define AT32_ICU_USE_TMR3 FALSE +#define AT32_ICU_USE_TMR4 FALSE +#define AT32_ICU_USE_TMR9 FALSE + +/* + * PWM driver system settings. + */ +#define AT32_PWM_USE_TMR1 FALSE +#define AT32_PWM_USE_TMR2 FALSE +#define AT32_PWM_USE_TMR3 FALSE +#define AT32_PWM_USE_TMR4 FALSE +#define AT32_PWM_USE_TMR9 FALSE +#define AT32_PWM_USE_TMR10 FALSE +#define AT32_PWM_USE_TMR11 FALSE +#define AT32_PWM_USE_TMR13 FALSE +#define AT32_PWM_USE_TMR14 FALSE + +/* + * RTC driver system settings. + */ +#define AT32_ERTC_DIVA_VALUE 32 +#define AT32_ERTC_DIVB_VALUE 1024 +#define AT32_ERTC_CTRL_INIT 0 +#define AT32_ERTC_TAMP_INIT 0 + +/* + * SERIAL driver system settings. + */ +#define AT32_SERIAL_USE_USART1 FALSE +#define AT32_SERIAL_USE_USART2 FALSE +#define AT32_SERIAL_USE_USART3 FALSE +#define AT32_SERIAL_USE_UART4 FALSE +#define AT32_SERIAL_USE_UART5 FALSE +#define AT32_SERIAL_USE_USART6 FALSE +#define AT32_SERIAL_USE_UART7 FALSE +#define AT32_SERIAL_USE_UART8 FALSE + +/* + * SIO driver system settings. + */ +#define AT32_SIO_USE_USART1 FALSE +#define AT32_SIO_USE_USART2 FALSE +#define AT32_SIO_USE_USART3 FALSE +#define AT32_SIO_USE_UART4 FALSE +#define AT32_SIO_USE_UART5 FALSE +#define AT32_SIO_USE_USART6 FALSE +#define AT32_SIO_USE_UART7 FALSE +#define AT32_SIO_USE_UART8 FALSE + +/* + * SPI driver system settings. + */ +#define AT32_SPI_USE_SPI1 FALSE +#define AT32_SPI_USE_SPI2 FALSE +#define AT32_SPI_USE_SPI3 FALSE +#define AT32_SPI_SPI1_DMA_PRIORITY 1 +#define AT32_SPI_SPI2_DMA_PRIORITY 1 +#define AT32_SPI_SPI3_DMA_PRIORITY 1 +#define AT32_SPI_SPI1_IRQ_PRIORITY 10 +#define AT32_SPI_SPI2_IRQ_PRIORITY 10 +#define AT32_SPI_SPI3_IRQ_PRIORITY 10 +#define AT32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define AT32_ST_IRQ_PRIORITY 8 +#define AT32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define AT32_UART_USE_USART1 FALSE +#define AT32_UART_USE_USART2 FALSE +#define AT32_UART_USE_USART3 FALSE +#define AT32_UART_USE_UART4 FALSE +#define AT32_UART_USE_UART5 FALSE +#define AT32_UART_USE_USART6 FALSE +#define AT32_UART_USE_UART7 FALSE +#define AT32_UART_USE_UART8 FALSE +#define AT32_UART_USART1_DMA_PRIORITY 0 +#define AT32_UART_USART2_DMA_PRIORITY 0 +#define AT32_UART_USART3_DMA_PRIORITY 0 +#define AT32_UART_UART4_DMA_PRIORITY 0 +#define AT32_UART_UART5_DMA_PRIORITY 0 +#define AT32_UART_USART6_DMA_PRIORITY 0 +#define AT32_UART_UART7_DMA_PRIORITY 0 +#define AT32_UART_UART8_DMA_PRIORITY 0 +#define AT32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define AT32_USB_USE_OTG1 FALSE +#define AT32_USB_USE_OTG2 TRUE +#define AT32_USB_OTG1_IRQ_PRIORITY 14 +#define AT32_USB_OTG2_IRQ_PRIORITY 14 +#define AT32_USB_OTG1_RX_FIFO_SIZE 512 +#define AT32_USB_OTG2_RX_FIFO_SIZE 1024 +#define AT32_USE_USB_OTG2_HS_DMA TRUE + +/* + * WDG driver system settings. + */ +#define AT32_WDG_USE_WDT FALSE + +#include "config.h" + +#endif /* MCUCONF_H */ diff --git a/testhal/AT32/multi/USB_CDC/cfg/at-start-f405_usbhs-dma/portab.c b/testhal/AT32/multi/USB_CDC/cfg/at-start-f405_usbhs-dma/portab.c new file mode 100644 index 0000000000..ceaf0ff400 --- /dev/null +++ b/testhal/AT32/multi/USB_CDC/cfg/at-start-f405_usbhs-dma/portab.c @@ -0,0 +1,59 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file portab.c + * @brief Application portability module code. + * + * @addtogroup application_portability + * @{ + */ + +#include "hal.h" + +#include "portab.h" + +/*===========================================================================*/ +/* Module local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module exported functions. */ +/*===========================================================================*/ + +void portab_setup(void) { + +} + +/** @} */ diff --git a/testhal/AT32/multi/USB_CDC/cfg/at-start-f405_usbhs-dma/portab.h b/testhal/AT32/multi/USB_CDC/cfg/at-start-f405_usbhs-dma/portab.h new file mode 100644 index 0000000000..23c10a93cb --- /dev/null +++ b/testhal/AT32/multi/USB_CDC/cfg/at-start-f405_usbhs-dma/portab.h @@ -0,0 +1,78 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file portab.h + * @brief Application portability macros and structures. + * + * @addtogroup application_portability + * @{ + */ + +#ifndef PORTAB_H +#define PORTAB_H + +/*===========================================================================*/ +/* Module constants. */ +/*===========================================================================*/ + +#define PORTAB_USB1 USBD2 + +#define PORTAB_SDU1 SDU1 + +#define PORTAB_BLINK_LED1 LINE_LED_RED + +#define PORTAB_BLINK_LED2 LINE_LED_YELLOW + +#define PORTAB_BLINK_LED3 LINE_LED_GREEN + +/*===========================================================================*/ +/* Module pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void portab_setup(void); +#ifdef __cplusplus +} +#endif + +/*===========================================================================*/ +/* Module inline functions. */ +/*===========================================================================*/ + +#endif /* PORTAB_H */ + +/** @} */ diff --git a/testhal/AT32/multi/USB_CDC/cfg/at-start-f405_usbhs/chconf.h b/testhal/AT32/multi/USB_CDC/cfg/at-start-f405_usbhs/chconf.h new file mode 100644 index 0000000000..56fe06776a --- /dev/null +++ b/testhal/AT32/multi/USB_CDC/cfg/at-start-f405_usbhs/chconf.h @@ -0,0 +1,842 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_7_0_ + +/*===========================================================================*/ +/** + * @name System settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Handling of instances. + * @note If enabled then threads assigned to various instances can + * interact each other using the same synchronization objects. + * If disabled then each OS instance is a separate world, no + * direct interactions are handled by the OS. + */ +#if !defined(CH_CFG_SMP_MODE) +#define CH_CFG_SMP_MODE FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_ST_RESOLUTION) +#define CH_CFG_ST_RESOLUTION 32 +#endif + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_CFG_ST_FREQUENCY) +#define CH_CFG_ST_FREQUENCY 10000 +#endif + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_INTERVALS_SIZE) +#define CH_CFG_INTERVALS_SIZE 32 +#endif + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_TIME_TYPES_SIZE) +#define CH_CFG_TIME_TYPES_SIZE 32 +#endif + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#if !defined(CH_CFG_ST_TIMEDELTA) +#define CH_CFG_ST_TIMEDELTA 2 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#if !defined(CH_CFG_TIME_QUANTUM) +#define CH_CFG_TIME_QUANTUM 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#if !defined(CH_CFG_NO_IDLE_THREAD) +#define CH_CFG_NO_IDLE_THREAD FALSE +#endif + +/** + * @brief Kernel hardening level. + * @details This option is the level of functional-safety checks enabled + * in the kerkel. The meaning is: + * - 0: No checks, maximum performance. + * - 1: Reasonable checks. + * - 2: All checks. + * . + */ +#if !defined(CH_CFG_HARDENING_LEVEL) +#define CH_CFG_HARDENING_LEVEL 0 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_OPTIMIZE_SPEED) +#define CH_CFG_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TM) +#define CH_CFG_USE_TM TRUE +#endif + +/** + * @brief Time Stamps APIs. + * @details If enabled then the time stamps APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TIMESTAMP) +#define CH_CFG_USE_TIMESTAMP TRUE +#endif + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_REGISTRY) +#define CH_CFG_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_WAITEXIT) +#define CH_CFG_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_SEMAPHORES) +#define CH_CFG_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MUTEXES) +#define CH_CFG_USE_MUTEXES TRUE +#endif + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_CONDVARS) +#define CH_CFG_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_EVENTS) +#define CH_CFG_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MESSAGES) +#define CH_CFG_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#if !defined(CH_CFG_USE_DYNAMIC) +#define CH_CFG_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name OSLIB options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_MAILBOXES) +#define CH_CFG_USE_MAILBOXES TRUE +#endif + +/** + * @brief Memory checks APIs. + * @details If enabled then the memory checks APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCHECKS) +#define CH_CFG_USE_MEMCHECKS TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCORE) +#define CH_CFG_USE_MEMCORE TRUE +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#if !defined(CH_CFG_MEMCORE_SIZE) +#define CH_CFG_MEMCORE_SIZE 0 +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_CFG_USE_HEAP) +#define CH_CFG_USE_HEAP TRUE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMPOOLS) +#define CH_CFG_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_FIFOS) +#define CH_CFG_USE_OBJ_FIFOS TRUE +#endif + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Objects Caches APIs. + * @details If enabled then the objects caches APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_CACHES) +#define CH_CFG_USE_OBJ_CACHES TRUE +#endif + +/** + * @brief Delegate threads APIs. + * @details If enabled then the delegate threads APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_DELEGATES) +#define CH_CFG_USE_DELEGATES TRUE +#endif + +/** + * @brief Jobs Queues APIs. + * @details If enabled then the jobs queues APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_JOBS) +#define CH_CFG_USE_JOBS TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_CFG_USE_FACTORY) +#define CH_CFG_USE_FACTORY TRUE +#endif + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 +#endif + +/** + * @brief Enables the registry of generic objects. + */ +#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE +#endif + +/** + * @brief Enables factory for generic buffers. + */ +#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE +#endif + +/** + * @brief Enables factory for semaphores. + */ +#if !defined(CH_CFG_FACTORY_SEMAPHORES) +#define CH_CFG_FACTORY_SEMAPHORES TRUE +#endif + +/** + * @brief Enables factory for mailboxes. + */ +#if !defined(CH_CFG_FACTORY_MAILBOXES) +#define CH_CFG_FACTORY_MAILBOXES TRUE +#endif + +/** + * @brief Enables factory for objects FIFOs. + */ +#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE +#endif + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_STATISTICS) +#define CH_DBG_STATISTICS FALSE +#endif + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_MASK) +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_ALL +#endif + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_BUFFER_SIZE) +#define CH_DBG_TRACE_BUFFER_SIZE 128 +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#if !defined(CH_DBG_THREADS_PROFILING) +#define CH_DBG_THREADS_PROFILING FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add system custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add system initialization code here.*/ \ +} + +/** + * @brief OS instance structure extension. + * @details User fields added to the end of the @p os_instance_t structure. + */ +#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS \ + /* Add OS instance custom fields here.*/ + +/** + * @brief OS instance initialization hook. + * + * @param[in] oip pointer to the @p os_instance_t structure + */ +#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) { \ + /* Add OS instance initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + * + * @param[in] ntp thread being switched in + * @param[in] otp thread being switched out + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** + * @brief Runtime Faults Collection Unit hook. + * @details This hook is invoked each time new faults are collected and stored. + */ +#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) { \ + /* Faults handling code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/testhal/AT32/multi/USB_CDC/cfg/at-start-f405_usbhs/config.h b/testhal/AT32/multi/USB_CDC/cfg/at-start-f405_usbhs/config.h new file mode 100644 index 0000000000..1e7c044f47 --- /dev/null +++ b/testhal/AT32/multi/USB_CDC/cfg/at-start-f405_usbhs/config.h @@ -0,0 +1,39 @@ +/* + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * CRC driver system settings. + */ +#define AT32_CRC_USE_CRC1 FALSE + +#define CRC_USE_DMA FALSE +#define AT32_CRC_CRC1_DMA_PRIORITY 2 +#define AT32_CRC_CRC1_IRQ_PRIORITY 5 +#define AT32_CRC_CRC1_DMA_STREAM AT32_DMA_STREAM_ID_ANY + +/* + * I2C fallback driver system settings. + */ +#define SW_I2C_USE_I2C1 FALSE +#define SW_I2C_USE_I2C2 FALSE +#define SW_I2C_USE_I2C3 FALSE +#define SW_I2C_USE_I2C4 FALSE + +/* + * Other settings. + */ +#define BOARD_OTG_VBUSIG diff --git a/testhal/AT32/multi/USB_CDC/cfg/at-start-f405_usbhs/halconf.h b/testhal/AT32/multi/USB_CDC/cfg/at-start-f405_usbhs/halconf.h new file mode 100644 index 0000000000..5419a662a8 --- /dev/null +++ b/testhal/AT32/multi/USB_CDC/cfg/at-start-f405_usbhs/halconf.h @@ -0,0 +1,557 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_8_4_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the EFlash subsystem. + */ +#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__) +#define HAL_USE_EFL FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB TRUE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB TRUE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/** + * @brief Enables the WSPI subsystem. + */ +#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) +#define HAL_USE_WSPI FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS FALSE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS FALSE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Timeout before assuming a failure while waiting for card idle. + * @note Time is in milliseconds. + */ +#if !defined(MMC_IDLE_TIMEOUT_MS) || defined(__DOXYGEN__) +#define MMC_IDLE_TIMEOUT_MS 1000 +#endif + +/** + * @brief Mutual exclusion on the SPI bus. + */ +#if !defined(MMC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define MMC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SIO driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SIO_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SIO_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Support for thread synchronization API. + */ +#if !defined(SIO_USE_SYNCHRONIZATION) || defined(__DOXYGEN__) +#define SIO_USE_SYNCHRONIZATION TRUE +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 256 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 2 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Inserts an assertion on function errors before returning. + */ +#if !defined(SPI_USE_ASSERT_ON_ERROR) || defined(__DOXYGEN__) +#define SPI_USE_ASSERT_ON_ERROR TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#include "halconf_community.h" + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/testhal/AT32/multi/USB_CDC/cfg/at-start-f405_usbhs/halconf_community.h b/testhal/AT32/multi/USB_CDC/cfg/at-start-f405_usbhs/halconf_community.h new file mode 100644 index 0000000000..5a77290c71 --- /dev/null +++ b/testhal/AT32/multi/USB_CDC/cfg/at-start-f405_usbhs/halconf_community.h @@ -0,0 +1,182 @@ +/* + ChibiOS - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef HALCONF_COMMUNITY_H +#define HALCONF_COMMUNITY_H + +/** + * @brief Enables the community overlay. + */ +#if !defined(HAL_USE_COMMUNITY) || defined(__DOXYGEN__) +#define HAL_USE_COMMUNITY TRUE +#endif + +/** + * @brief Enables the FSMC subsystem. + */ +#if !defined(HAL_USE_FSMC) || defined(__DOXYGEN__) +#define HAL_USE_FSMC FALSE +#endif + +/** + * @brief Enables the NAND subsystem. + */ +#if !defined(HAL_USE_NAND) || defined(__DOXYGEN__) +#define HAL_USE_NAND FALSE +#endif + +/** + * @brief Enables the 1-wire subsystem. + */ +#if !defined(HAL_USE_ONEWIRE) || defined(__DOXYGEN__) +#define HAL_USE_ONEWIRE FALSE +#endif + +/** + * @brief Enables the EICU subsystem. + */ +#if !defined(HAL_USE_EICU) || defined(__DOXYGEN__) +#define HAL_USE_EICU FALSE +#endif + +/** + * @brief Enables the CRC subsystem. + */ +#if !defined(HAL_USE_CRC) || defined(__DOXYGEN__) +#define HAL_USE_CRC FALSE +#endif + +/** + * @brief Enables the RNG subsystem. + */ +#if !defined(HAL_USE_RNG) || defined(__DOXYGEN__) +#define HAL_USE_RNG FALSE +#endif + +/** + * @brief Enables the EEPROM subsystem. + */ +#if !defined(HAL_USE_EEPROM) || defined(__DOXYGEN__) +#define HAL_USE_EEPROM FALSE +#endif + +/** + * @brief Enables the TIMCAP subsystem. + */ +#if !defined(HAL_USE_TIMCAP) || defined(__DOXYGEN__) +#define HAL_USE_TIMCAP FALSE +#endif + +/** + * @brief Enables the COMP subsystem. + */ +#if !defined(HAL_USE_COMP) || defined(__DOXYGEN__) +#define HAL_USE_COMP FALSE +#endif + +/** + * @brief Enables the OPAMP subsystem. + */ +#if !defined(HAL_USE_OPAMP) || defined(__DOXYGEN__) +#define HAL_USE_OPAMP FALSE +#endif + +/** + * @brief Enables the QEI subsystem. + */ +#if !defined(HAL_USE_QEI) || defined(__DOXYGEN__) +#define HAL_USE_QEI FALSE +#endif + +/** + * @brief Enables the USBH subsystem. + */ +#if !defined(HAL_USE_USBH) || defined(__DOXYGEN__) +#define HAL_USE_USBH FALSE +#endif + +/** + * @brief Enables the USB_MSD subsystem. + */ +#if !defined(HAL_USE_USB_MSD) || defined(__DOXYGEN__) +#define HAL_USE_USB_MSD FALSE +#endif + +/*===========================================================================*/ +/* FSMCNAND driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the @p nandAcquireBus() and @p nanReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(NAND_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define NAND_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* 1-wire driver related settings. */ +/*===========================================================================*/ +/** + * @brief Enables strong pull up feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_STRONG_PULLUP FALSE + +/** + * @brief Enables search ROM feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_SEARCH_ROM TRUE + +/*===========================================================================*/ +/* QEI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables discard of overlow + */ +#if !defined(QEI_USE_OVERFLOW_DISCARD) || defined(__DOXYGEN__) +#define QEI_USE_OVERFLOW_DISCARD FALSE +#endif + +/** + * @brief Enables min max of overlow + */ +#if !defined(QEI_USE_OVERFLOW_MINMAX) || defined(__DOXYGEN__) +#define QEI_USE_OVERFLOW_MINMAX FALSE +#endif + +/*===========================================================================*/ +/* EEProm driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables 24xx series I2C eeprom device driver. + * @note Disabling this option saves both code and data space. + */ +#define EEPROM_USE_EE24XX FALSE + /** + * @brief Enables 25xx series SPI eeprom device driver. + * @note Disabling this option saves both code and data space. + */ +#define EEPROM_USE_EE25XX FALSE + +#endif /* HALCONF_COMMUNITY_H */ + +/** @} */ diff --git a/testhal/AT32/multi/USB_CDC/cfg/at-start-f405_usbhs/mcuconf.h b/testhal/AT32/multi/USB_CDC/cfg/at-start-f405_usbhs/mcuconf.h new file mode 100644 index 0000000000..6202e39c0f --- /dev/null +++ b/testhal/AT32/multi/USB_CDC/cfg/at-start-f405_usbhs/mcuconf.h @@ -0,0 +1,272 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef MCUCONF_H +#define MCUCONF_H + +/* + * AT32F405 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define AT32F405_MCUCONF + +/* + * General settings. + */ +#define AT32_NO_INIT FALSE + +/* + * HAL driver system settings. + */ +#define AT32_HICK_ENABLED TRUE +#define AT32_LICK_ENABLED FALSE +#define AT32_HEXT_ENABLED TRUE +#define AT32_LEXT_ENABLED FALSE +#define AT32_PLLU_ENABLED TRUE +#define AT32_SCLKSEL AT32_SCLKSEL_PLL +#define AT32_PLLRCS AT32_PLLRCS_HEXT +#define AT32_PLL_MS_VALUE 1 +#define AT32_PLL_NS_VALUE 72 +#define AT32_PLL_FP_VALUE 4 +#define AT32_PLL_FU_VALUE 18 +#define AT32_AHBDIV AT32_AHBDIV_DIV1 +#define AT32_APB1DIV AT32_APB1DIV_DIV2 +#define AT32_APB2DIV AT32_APB2DIV_DIV1 +#define AT32_HICK_TO_SCLK AT32_HICK_TO_SCLK_48M +#define AT32_HICKDIV AT32_HICKDIV_DIV1 +#define AT32_HICK_TO_SCLK_DIV AT32_HICK_TO_SCLK_DIV_DIV1 +#define AT32_HEXT_TO_SCLK_DIV AT32_HEXT_TO_SCLK_DIV_DIV1 +#define AT32_USB_CLOCK48_REQUIRED TRUE +#define AT32_PLLU_USB48_SEL AT32_PLLU_USB48_SEL_PLLU +#define AT32_CLKOUT_SEL AT32_CLKOUT_SEL_HICK +#define AT32_CLKOUTDIV1 AT32_CLKOUTDIV1_DIV1 +#define AT32_CLKOUTDIV2 AT32_CLKOUTDIV2_DIV1 +#define AT32_ERTCSEL AT32_ERTCSEL_NOCLOCK +#define AT32_ERTCDIV_VALUE 12 +#define AT32_I2SF5CLKSEL AT32_I2SF5CLKSEL_SCLK +#define AT32_PVM_ENABLE FALSE +#define AT32_PVMSEL AT32_PVMSEL_LEV1 +#define AT32_LDOOVSEL AT32_LDOOVSEL_LEV3 + +/* + * IRQ system settings. + */ +#define AT32_IRQ_EXINT0_PRIORITY 6 +#define AT32_IRQ_EXINT1_PRIORITY 6 +#define AT32_IRQ_EXINT2_PRIORITY 6 +#define AT32_IRQ_EXINT3_PRIORITY 6 +#define AT32_IRQ_EXINT4_PRIORITY 6 +#define AT32_IRQ_EXINT5_9_PRIORITY 6 +#define AT32_IRQ_EXINT10_15_PRIORITY 6 +#define AT32_IRQ_EXINT16_PRIORITY 6 +#define AT32_IRQ_EXINT17_PRIORITY 15 +#define AT32_IRQ_EXINT18_PRIORITY 6 +#define AT32_IRQ_EXINT20_PRIORITY 6 +#define AT32_IRQ_EXINT21_PRIORITY 15 +#define AT32_IRQ_EXINT22_PRIORITY 15 + +#define AT32_IRQ_TMR1_BRK_TMR9_PRIORITY 7 +#define AT32_IRQ_TMR1_OVF_TMR10_PRIORITY 7 +#define AT32_IRQ_TMR1_HALL_TMR11_PRIORITY 7 +#define AT32_IRQ_TMR1_CH_PRIORITY 7 +#define AT32_IRQ_TMR2_PRIORITY 7 +#define AT32_IRQ_TMR3_PRIORITY 7 +#define AT32_IRQ_TMR4_PRIORITY 7 +#define AT32_IRQ_TMR6_PRIORITY 7 +#define AT32_IRQ_TMR7_PRIORITY 7 +#define AT32_IRQ_TMR13_PRIORITY 7 +#define AT32_IRQ_TMR14_PRIORITY 7 + +#define AT32_IRQ_USART1_PRIORITY 12 +#define AT32_IRQ_USART2_PRIORITY 12 +#define AT32_IRQ_USART3_PRIORITY 12 +#define AT32_IRQ_UART4_PRIORITY 12 +#define AT32_IRQ_UART5_PRIORITY 12 +#define AT32_IRQ_USART6_PRIORITY 12 +#define AT32_IRQ_UART7_PRIORITY 12 +#define AT32_IRQ_UART8_PRIORITY 12 + +/* + * ADC driver system settings. + */ +#define AT32_ADC_USE_ADC1 FALSE +#define AT32_ADC_ADC1_DMA_PRIORITY 2 +#define AT32_ADC_IRQ_PRIORITY 6 +#define AT32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define AT32_ADC_ADCDIV 8 + +/* + * CAN driver system settings. + */ +#define AT32_CAN_USE_CAN1 FALSE +#define AT32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * GPT driver system settings. + */ +#define AT32_GPT_USE_TMR1 FALSE +#define AT32_GPT_USE_TMR2 FALSE +#define AT32_GPT_USE_TMR3 FALSE +#define AT32_GPT_USE_TMR4 FALSE +#define AT32_GPT_USE_TMR6 FALSE +#define AT32_GPT_USE_TMR7 FALSE +#define AT32_GPT_USE_TMR9 FALSE +#define AT32_GPT_USE_TMR10 FALSE +#define AT32_GPT_USE_TMR11 FALSE +#define AT32_GPT_USE_TMR13 FALSE +#define AT32_GPT_USE_TMR14 FALSE + +/* + * I2C driver system settings. + */ +#define AT32_I2C_USE_I2C1 FALSE +#define AT32_I2C_USE_I2C2 FALSE +#define AT32_I2C_USE_I2C3 FALSE +#define AT32_I2C_BUSY_TIMEOUT 50 +#define AT32_I2C_I2C1_DMA_PRIORITY 3 +#define AT32_I2C_I2C2_DMA_PRIORITY 3 +#define AT32_I2C_I2C3_DMA_PRIORITY 3 +#define AT32_I2C_I2C1_IRQ_PRIORITY 5 +#define AT32_I2C_I2C2_IRQ_PRIORITY 5 +#define AT32_I2C_I2C3_IRQ_PRIORITY 5 +#define AT32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define AT32_ICU_USE_TMR1 FALSE +#define AT32_ICU_USE_TMR2 FALSE +#define AT32_ICU_USE_TMR3 FALSE +#define AT32_ICU_USE_TMR4 FALSE +#define AT32_ICU_USE_TMR9 FALSE + +/* + * PWM driver system settings. + */ +#define AT32_PWM_USE_TMR1 FALSE +#define AT32_PWM_USE_TMR2 FALSE +#define AT32_PWM_USE_TMR3 FALSE +#define AT32_PWM_USE_TMR4 FALSE +#define AT32_PWM_USE_TMR9 FALSE +#define AT32_PWM_USE_TMR10 FALSE +#define AT32_PWM_USE_TMR11 FALSE +#define AT32_PWM_USE_TMR13 FALSE +#define AT32_PWM_USE_TMR14 FALSE + +/* + * RTC driver system settings. + */ +#define AT32_ERTC_DIVA_VALUE 32 +#define AT32_ERTC_DIVB_VALUE 1024 +#define AT32_ERTC_CTRL_INIT 0 +#define AT32_ERTC_TAMP_INIT 0 + +/* + * SERIAL driver system settings. + */ +#define AT32_SERIAL_USE_USART1 FALSE +#define AT32_SERIAL_USE_USART2 FALSE +#define AT32_SERIAL_USE_USART3 FALSE +#define AT32_SERIAL_USE_UART4 FALSE +#define AT32_SERIAL_USE_UART5 FALSE +#define AT32_SERIAL_USE_USART6 FALSE +#define AT32_SERIAL_USE_UART7 FALSE +#define AT32_SERIAL_USE_UART8 FALSE + +/* + * SIO driver system settings. + */ +#define AT32_SIO_USE_USART1 FALSE +#define AT32_SIO_USE_USART2 FALSE +#define AT32_SIO_USE_USART3 FALSE +#define AT32_SIO_USE_UART4 FALSE +#define AT32_SIO_USE_UART5 FALSE +#define AT32_SIO_USE_USART6 FALSE +#define AT32_SIO_USE_UART7 FALSE +#define AT32_SIO_USE_UART8 FALSE + +/* + * SPI driver system settings. + */ +#define AT32_SPI_USE_SPI1 FALSE +#define AT32_SPI_USE_SPI2 FALSE +#define AT32_SPI_USE_SPI3 FALSE +#define AT32_SPI_SPI1_DMA_PRIORITY 1 +#define AT32_SPI_SPI2_DMA_PRIORITY 1 +#define AT32_SPI_SPI3_DMA_PRIORITY 1 +#define AT32_SPI_SPI1_IRQ_PRIORITY 10 +#define AT32_SPI_SPI2_IRQ_PRIORITY 10 +#define AT32_SPI_SPI3_IRQ_PRIORITY 10 +#define AT32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define AT32_ST_IRQ_PRIORITY 8 +#define AT32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define AT32_UART_USE_USART1 FALSE +#define AT32_UART_USE_USART2 FALSE +#define AT32_UART_USE_USART3 FALSE +#define AT32_UART_USE_UART4 FALSE +#define AT32_UART_USE_UART5 FALSE +#define AT32_UART_USE_USART6 FALSE +#define AT32_UART_USE_UART7 FALSE +#define AT32_UART_USE_UART8 FALSE +#define AT32_UART_USART1_DMA_PRIORITY 0 +#define AT32_UART_USART2_DMA_PRIORITY 0 +#define AT32_UART_USART3_DMA_PRIORITY 0 +#define AT32_UART_UART4_DMA_PRIORITY 0 +#define AT32_UART_UART5_DMA_PRIORITY 0 +#define AT32_UART_USART6_DMA_PRIORITY 0 +#define AT32_UART_UART7_DMA_PRIORITY 0 +#define AT32_UART_UART8_DMA_PRIORITY 0 +#define AT32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define AT32_USB_USE_OTG1 FALSE +#define AT32_USB_USE_OTG2 TRUE +#define AT32_USB_OTG1_IRQ_PRIORITY 14 +#define AT32_USB_OTG2_IRQ_PRIORITY 14 +#define AT32_USB_OTG1_RX_FIFO_SIZE 512 +#define AT32_USB_OTG2_RX_FIFO_SIZE 1024 +#define AT32_USE_USB_OTG2_HS_DMA FALSE + +/* + * WDG driver system settings. + */ +#define AT32_WDG_USE_WDT FALSE + +#include "config.h" + +#endif /* MCUCONF_H */ diff --git a/testhal/AT32/multi/USB_CDC/cfg/at-start-f405_usbhs/portab.c b/testhal/AT32/multi/USB_CDC/cfg/at-start-f405_usbhs/portab.c new file mode 100644 index 0000000000..ceaf0ff400 --- /dev/null +++ b/testhal/AT32/multi/USB_CDC/cfg/at-start-f405_usbhs/portab.c @@ -0,0 +1,59 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file portab.c + * @brief Application portability module code. + * + * @addtogroup application_portability + * @{ + */ + +#include "hal.h" + +#include "portab.h" + +/*===========================================================================*/ +/* Module local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module exported functions. */ +/*===========================================================================*/ + +void portab_setup(void) { + +} + +/** @} */ diff --git a/testhal/AT32/multi/USB_CDC/cfg/at-start-f405_usbhs/portab.h b/testhal/AT32/multi/USB_CDC/cfg/at-start-f405_usbhs/portab.h new file mode 100644 index 0000000000..23c10a93cb --- /dev/null +++ b/testhal/AT32/multi/USB_CDC/cfg/at-start-f405_usbhs/portab.h @@ -0,0 +1,78 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file portab.h + * @brief Application portability macros and structures. + * + * @addtogroup application_portability + * @{ + */ + +#ifndef PORTAB_H +#define PORTAB_H + +/*===========================================================================*/ +/* Module constants. */ +/*===========================================================================*/ + +#define PORTAB_USB1 USBD2 + +#define PORTAB_SDU1 SDU1 + +#define PORTAB_BLINK_LED1 LINE_LED_RED + +#define PORTAB_BLINK_LED2 LINE_LED_YELLOW + +#define PORTAB_BLINK_LED3 LINE_LED_GREEN + +/*===========================================================================*/ +/* Module pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void portab_setup(void); +#ifdef __cplusplus +} +#endif + +/*===========================================================================*/ +/* Module inline functions. */ +/*===========================================================================*/ + +#endif /* PORTAB_H */ + +/** @} */ diff --git a/testhal/AT32/multi/USB_CDC/cfg/at-start-f415/chconf.h b/testhal/AT32/multi/USB_CDC/cfg/at-start-f415/chconf.h index 46b3f78b68..56fe06776a 100644 --- a/testhal/AT32/multi/USB_CDC/cfg/at-start-f415/chconf.h +++ b/testhal/AT32/multi/USB_CDC/cfg/at-start-f415/chconf.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/testhal/AT32/multi/USB_CDC/cfg/at-start-f415/config.h b/testhal/AT32/multi/USB_CDC/cfg/at-start-f415/config.h index 361e185d9c..056a8f39ff 100644 --- a/testhal/AT32/multi/USB_CDC/cfg/at-start-f415/config.h +++ b/testhal/AT32/multi/USB_CDC/cfg/at-start-f415/config.h @@ -1,6 +1,6 @@ /* - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/testhal/AT32/multi/USB_CDC/cfg/at-start-f415/halconf.h b/testhal/AT32/multi/USB_CDC/cfg/at-start-f415/halconf.h index 256f1434f1..5419a662a8 100644 --- a/testhal/AT32/multi/USB_CDC/cfg/at-start-f415/halconf.h +++ b/testhal/AT32/multi/USB_CDC/cfg/at-start-f415/halconf.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/testhal/AT32/multi/USB_CDC/cfg/at-start-f415/halconf_community.h b/testhal/AT32/multi/USB_CDC/cfg/at-start-f415/halconf_community.h index c43d668764..5a77290c71 100644 --- a/testhal/AT32/multi/USB_CDC/cfg/at-start-f415/halconf_community.h +++ b/testhal/AT32/multi/USB_CDC/cfg/at-start-f415/halconf_community.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/testhal/AT32/multi/USB_CDC/cfg/at-start-f415/mcuconf.h b/testhal/AT32/multi/USB_CDC/cfg/at-start-f415/mcuconf.h index 873438fe57..caae00def9 100644 --- a/testhal/AT32/multi/USB_CDC/cfg/at-start-f415/mcuconf.h +++ b/testhal/AT32/multi/USB_CDC/cfg/at-start-f415/mcuconf.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -106,6 +106,7 @@ #define AT32_ADC_USE_ADC1 FALSE #define AT32_ADC_ADC1_DMA_PRIORITY 2 #define AT32_ADC_ADC1_IRQ_PRIORITY 6 +#define AT32_ADC_ADC1_DMA_IRQ_PRIORITY 6 /* * CAN driver system settings. diff --git a/testhal/AT32/multi/USB_CDC/cfg/at-start-f415/portab.c b/testhal/AT32/multi/USB_CDC/cfg/at-start-f415/portab.c index 25e871321a..ceaf0ff400 100644 --- a/testhal/AT32/multi/USB_CDC/cfg/at-start-f415/portab.c +++ b/testhal/AT32/multi/USB_CDC/cfg/at-start-f415/portab.c @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/testhal/AT32/multi/USB_CDC/cfg/at-start-f415/portab.h b/testhal/AT32/multi/USB_CDC/cfg/at-start-f415/portab.h index 586eb17f65..42ddef6c9e 100644 --- a/testhal/AT32/multi/USB_CDC/cfg/at-start-f415/portab.h +++ b/testhal/AT32/multi/USB_CDC/cfg/at-start-f415/portab.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/testhal/AT32/multi/USB_CDC/main.c b/testhal/AT32/multi/USB_CDC/main.c index 71eacb8799..98a52fa02f 100644 --- a/testhal/AT32/multi/USB_CDC/main.c +++ b/testhal/AT32/multi/USB_CDC/main.c @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/testhal/AT32/multi/USB_CDC/make/at-start-f402.make b/testhal/AT32/multi/USB_CDC/make/at-start-f402.make new file mode 100644 index 0000000000..bc38709398 --- /dev/null +++ b/testhal/AT32/multi/USB_CDC/make/at-start-f402.make @@ -0,0 +1,198 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO). +ifeq ($(USE_LTO),) + USE_LTO = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# Enable this if you want to use bitbang I2C. +ifeq ($(USE_HAL_I2C_FALLBACK),) + USE_HAL_I2C_FALLBACK = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x400 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU (no, softfp, hard). +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# FPU-related options. +ifeq ($(USE_FPU_OPT),) + USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16 +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, target, sources and paths +# + +# Define project name here +PROJECT = ch + +# Target settings. +MCU = cortex-m4 + +# Imported source files and paths. +CHIBIOS := ../../../../../ChibiOS +CHIBIOS_CONTRIB := ../../../.. +CONFDIR := ./cfg/at-start-f402 +BUILDDIR := ./build/at-start-f402 +DEPDIR := ./.dep/at-start-f402 + +# Licensing files. +include $(CHIBIOS)/os/license/license.mk +# Startup files. +include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_at32f402.mk +# HAL-OSAL files (optional). +include $(CHIBIOS_CONTRIB)/os/hal/hal.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/AT32F402_405/platform.mk +include $(CHIBIOS_CONTRIB)/os/hal/boards/AT_START_F402/board.mk +include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMv7-M/compilers/GCC/mk/port.mk +# Auto-build files in ./source recursively. +include $(CHIBIOS)/tools/mk/autobuild.mk +# Other files (optional). +include $(CHIBIOS)/os/test/test.mk +include $(CHIBIOS)/test/rt/rt_test.mk +include $(CHIBIOS)/test/oslib/oslib_test.mk +include $(CHIBIOS)/os/hal/lib/streams/streams.mk +include $(CHIBIOS)/os/various/shell/shell.mk + +# Define linker script file here. +LDSCRIPT= $(STARTUPLD_CONTRIB)/AT32F402xC.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(ALLCSRC) \ + $(TESTSRC) \ + $(CONFDIR)/portab.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = $(ALLCPPSRC) + +# List ASM source files here. +ASMSRC = $(ALLASMSRC) + +# List ASM with preprocessor source files here. +ASMXSRC = $(ALLXASMSRC) + +# Inclusion directories. +INCDIR = $(CONFDIR) $(ALLINC) $(TESTINC) + +# Define C warning options here. +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes + +# Define C++ warning options here. +CPPWARN = -Wall -Wextra -Wundef + +# +# Project, target, sources and paths +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user section +############################################################################## + +############################################################################## +# Common rules +# + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk +include $(RULESPATH)/arm-none-eabi.mk +include $(RULESPATH)/rules.mk + +# +# Common rules +############################################################################## + +############################################################################## +# Custom rules +# + +# +# Custom rules +############################################################################## diff --git a/testhal/AT32/multi/USB_CDC/make/at-start-f405_usbfs.make b/testhal/AT32/multi/USB_CDC/make/at-start-f405_usbfs.make new file mode 100644 index 0000000000..b8511e41c2 --- /dev/null +++ b/testhal/AT32/multi/USB_CDC/make/at-start-f405_usbfs.make @@ -0,0 +1,198 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO). +ifeq ($(USE_LTO),) + USE_LTO = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# Enable this if you want to use bitbang I2C. +ifeq ($(USE_HAL_I2C_FALLBACK),) + USE_HAL_I2C_FALLBACK = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x400 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU (no, softfp, hard). +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# FPU-related options. +ifeq ($(USE_FPU_OPT),) + USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16 +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, target, sources and paths +# + +# Define project name here +PROJECT = ch + +# Target settings. +MCU = cortex-m4 + +# Imported source files and paths. +CHIBIOS := ../../../../../ChibiOS +CHIBIOS_CONTRIB := ../../../.. +CONFDIR := ./cfg/at-start-f405_usbfs +BUILDDIR := ./build/at-start-f405_usbfs +DEPDIR := ./.dep/at-start-f405_usbfs + +# Licensing files. +include $(CHIBIOS)/os/license/license.mk +# Startup files. +include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_at32f405.mk +# HAL-OSAL files (optional). +include $(CHIBIOS_CONTRIB)/os/hal/hal.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/AT32F402_405/platform.mk +include $(CHIBIOS_CONTRIB)/os/hal/boards/AT_START_F405/board.mk +include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMv7-M/compilers/GCC/mk/port.mk +# Auto-build files in ./source recursively. +include $(CHIBIOS)/tools/mk/autobuild.mk +# Other files (optional). +include $(CHIBIOS)/os/test/test.mk +include $(CHIBIOS)/test/rt/rt_test.mk +include $(CHIBIOS)/test/oslib/oslib_test.mk +include $(CHIBIOS)/os/hal/lib/streams/streams.mk +include $(CHIBIOS)/os/various/shell/shell.mk + +# Define linker script file here. +LDSCRIPT= $(STARTUPLD_CONTRIB)/AT32F405xC.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(ALLCSRC) \ + $(TESTSRC) \ + $(CONFDIR)/portab.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = $(ALLCPPSRC) + +# List ASM source files here. +ASMSRC = $(ALLASMSRC) + +# List ASM with preprocessor source files here. +ASMXSRC = $(ALLXASMSRC) + +# Inclusion directories. +INCDIR = $(CONFDIR) $(ALLINC) $(TESTINC) + +# Define C warning options here. +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes + +# Define C++ warning options here. +CPPWARN = -Wall -Wextra -Wundef + +# +# Project, target, sources and paths +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user section +############################################################################## + +############################################################################## +# Common rules +# + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk +include $(RULESPATH)/arm-none-eabi.mk +include $(RULESPATH)/rules.mk + +# +# Common rules +############################################################################## + +############################################################################## +# Custom rules +# + +# +# Custom rules +############################################################################## diff --git a/testhal/AT32/multi/USB_CDC/make/at-start-f405_usbhs-dma.make b/testhal/AT32/multi/USB_CDC/make/at-start-f405_usbhs-dma.make new file mode 100644 index 0000000000..da14ea5de9 --- /dev/null +++ b/testhal/AT32/multi/USB_CDC/make/at-start-f405_usbhs-dma.make @@ -0,0 +1,198 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO). +ifeq ($(USE_LTO),) + USE_LTO = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# Enable this if you want to use bitbang I2C. +ifeq ($(USE_HAL_I2C_FALLBACK),) + USE_HAL_I2C_FALLBACK = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x400 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU (no, softfp, hard). +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# FPU-related options. +ifeq ($(USE_FPU_OPT),) + USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16 +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, target, sources and paths +# + +# Define project name here +PROJECT = ch + +# Target settings. +MCU = cortex-m4 + +# Imported source files and paths. +CHIBIOS := ../../../../../ChibiOS +CHIBIOS_CONTRIB := ../../../.. +CONFDIR := ./cfg/at-start-f405_usbhs-dma +BUILDDIR := ./build/at-start-f405_usbhs-dma +DEPDIR := ./.dep/at-start-f405_usbhs-dma + +# Licensing files. +include $(CHIBIOS)/os/license/license.mk +# Startup files. +include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_at32f405.mk +# HAL-OSAL files (optional). +include $(CHIBIOS_CONTRIB)/os/hal/hal.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/AT32F402_405/platform.mk +include $(CHIBIOS_CONTRIB)/os/hal/boards/AT_START_F405/board.mk +include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMv7-M/compilers/GCC/mk/port.mk +# Auto-build files in ./source recursively. +include $(CHIBIOS)/tools/mk/autobuild.mk +# Other files (optional). +include $(CHIBIOS)/os/test/test.mk +include $(CHIBIOS)/test/rt/rt_test.mk +include $(CHIBIOS)/test/oslib/oslib_test.mk +include $(CHIBIOS)/os/hal/lib/streams/streams.mk +include $(CHIBIOS)/os/various/shell/shell.mk + +# Define linker script file here. +LDSCRIPT= $(STARTUPLD_CONTRIB)/AT32F405xC.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(ALLCSRC) \ + $(TESTSRC) \ + $(CONFDIR)/portab.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = $(ALLCPPSRC) + +# List ASM source files here. +ASMSRC = $(ALLASMSRC) + +# List ASM with preprocessor source files here. +ASMXSRC = $(ALLXASMSRC) + +# Inclusion directories. +INCDIR = $(CONFDIR) $(ALLINC) $(TESTINC) + +# Define C warning options here. +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes + +# Define C++ warning options here. +CPPWARN = -Wall -Wextra -Wundef + +# +# Project, target, sources and paths +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user section +############################################################################## + +############################################################################## +# Common rules +# + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk +include $(RULESPATH)/arm-none-eabi.mk +include $(RULESPATH)/rules.mk + +# +# Common rules +############################################################################## + +############################################################################## +# Custom rules +# + +# +# Custom rules +############################################################################## diff --git a/testhal/AT32/multi/USB_CDC/make/at-start-f405_usbhs.make b/testhal/AT32/multi/USB_CDC/make/at-start-f405_usbhs.make new file mode 100644 index 0000000000..b31000b7b8 --- /dev/null +++ b/testhal/AT32/multi/USB_CDC/make/at-start-f405_usbhs.make @@ -0,0 +1,198 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO). +ifeq ($(USE_LTO),) + USE_LTO = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# Enable this if you want to use bitbang I2C. +ifeq ($(USE_HAL_I2C_FALLBACK),) + USE_HAL_I2C_FALLBACK = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x400 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU (no, softfp, hard). +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# FPU-related options. +ifeq ($(USE_FPU_OPT),) + USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16 +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, target, sources and paths +# + +# Define project name here +PROJECT = ch + +# Target settings. +MCU = cortex-m4 + +# Imported source files and paths. +CHIBIOS := ../../../../../ChibiOS +CHIBIOS_CONTRIB := ../../../.. +CONFDIR := ./cfg/at-start-f405_usbhs +BUILDDIR := ./build/at-start-f405_usbhs +DEPDIR := ./.dep/at-start-f405_usbhs + +# Licensing files. +include $(CHIBIOS)/os/license/license.mk +# Startup files. +include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_at32f405.mk +# HAL-OSAL files (optional). +include $(CHIBIOS_CONTRIB)/os/hal/hal.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/AT32F402_405/platform.mk +include $(CHIBIOS_CONTRIB)/os/hal/boards/AT_START_F405/board.mk +include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMv7-M/compilers/GCC/mk/port.mk +# Auto-build files in ./source recursively. +include $(CHIBIOS)/tools/mk/autobuild.mk +# Other files (optional). +include $(CHIBIOS)/os/test/test.mk +include $(CHIBIOS)/test/rt/rt_test.mk +include $(CHIBIOS)/test/oslib/oslib_test.mk +include $(CHIBIOS)/os/hal/lib/streams/streams.mk +include $(CHIBIOS)/os/various/shell/shell.mk + +# Define linker script file here. +LDSCRIPT= $(STARTUPLD_CONTRIB)/AT32F405xC.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(ALLCSRC) \ + $(TESTSRC) \ + $(CONFDIR)/portab.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = $(ALLCPPSRC) + +# List ASM source files here. +ASMSRC = $(ALLASMSRC) + +# List ASM with preprocessor source files here. +ASMXSRC = $(ALLXASMSRC) + +# Inclusion directories. +INCDIR = $(CONFDIR) $(ALLINC) $(TESTINC) + +# Define C warning options here. +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes + +# Define C++ warning options here. +CPPWARN = -Wall -Wextra -Wundef + +# +# Project, target, sources and paths +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user section +############################################################################## + +############################################################################## +# Common rules +# + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk +include $(RULESPATH)/arm-none-eabi.mk +include $(RULESPATH)/rules.mk + +# +# Common rules +############################################################################## + +############################################################################## +# Custom rules +# + +# +# Custom rules +############################################################################## diff --git a/testhal/AT32/multi/USB_CDC/source/usbcfg.c b/testhal/AT32/multi/USB_CDC/source/usbcfg.c index 4ec94841aa..f5415c1839 100644 --- a/testhal/AT32/multi/USB_CDC/source/usbcfg.c +++ b/testhal/AT32/multi/USB_CDC/source/usbcfg.c @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/testhal/AT32/multi/USB_CDC/source/usbcfg.h b/testhal/AT32/multi/USB_CDC/source/usbcfg.h index 40a9a2d3ef..b717d357ff 100644 --- a/testhal/AT32/multi/USB_CDC/source/usbcfg.h +++ b/testhal/AT32/multi/USB_CDC/source/usbcfg.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/testhal/AT32/multi/WDT/Makefile b/testhal/AT32/multi/WDT/Makefile index c8606df05e..fdf3019a85 100644 --- a/testhal/AT32/multi/WDT/Makefile +++ b/testhal/AT32/multi/WDT/Makefile @@ -3,6 +3,14 @@ # all: + @echo + @echo === Building for AT-START-F402 ===================================== + +@make --no-print-directory -f ./make/at-start-f402.make all + @echo ==================================================================== + @echo + @echo === Building for AT-START-F405 ===================================== + +@make --no-print-directory -f ./make/at-start-f405.make all + @echo ==================================================================== @echo @echo === Building for AT-START-F415 ===================================== +@make --no-print-directory -f ./make/at-start-f415.make all @@ -10,6 +18,10 @@ all: @echo clean: + @echo + +@make --no-print-directory -f ./make/at-start-f402.make clean + @echo + +@make --no-print-directory -f ./make/at-start-f405.make clean @echo +@make --no-print-directory -f ./make/at-start-f415.make clean @echo diff --git a/testhal/AT32/multi/WDT/cfg/at-start-f402/chconf.h b/testhal/AT32/multi/WDT/cfg/at-start-f402/chconf.h new file mode 100644 index 0000000000..56fe06776a --- /dev/null +++ b/testhal/AT32/multi/WDT/cfg/at-start-f402/chconf.h @@ -0,0 +1,842 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_7_0_ + +/*===========================================================================*/ +/** + * @name System settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Handling of instances. + * @note If enabled then threads assigned to various instances can + * interact each other using the same synchronization objects. + * If disabled then each OS instance is a separate world, no + * direct interactions are handled by the OS. + */ +#if !defined(CH_CFG_SMP_MODE) +#define CH_CFG_SMP_MODE FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_ST_RESOLUTION) +#define CH_CFG_ST_RESOLUTION 32 +#endif + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_CFG_ST_FREQUENCY) +#define CH_CFG_ST_FREQUENCY 10000 +#endif + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_INTERVALS_SIZE) +#define CH_CFG_INTERVALS_SIZE 32 +#endif + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_TIME_TYPES_SIZE) +#define CH_CFG_TIME_TYPES_SIZE 32 +#endif + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#if !defined(CH_CFG_ST_TIMEDELTA) +#define CH_CFG_ST_TIMEDELTA 2 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#if !defined(CH_CFG_TIME_QUANTUM) +#define CH_CFG_TIME_QUANTUM 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#if !defined(CH_CFG_NO_IDLE_THREAD) +#define CH_CFG_NO_IDLE_THREAD FALSE +#endif + +/** + * @brief Kernel hardening level. + * @details This option is the level of functional-safety checks enabled + * in the kerkel. The meaning is: + * - 0: No checks, maximum performance. + * - 1: Reasonable checks. + * - 2: All checks. + * . + */ +#if !defined(CH_CFG_HARDENING_LEVEL) +#define CH_CFG_HARDENING_LEVEL 0 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_OPTIMIZE_SPEED) +#define CH_CFG_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TM) +#define CH_CFG_USE_TM TRUE +#endif + +/** + * @brief Time Stamps APIs. + * @details If enabled then the time stamps APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TIMESTAMP) +#define CH_CFG_USE_TIMESTAMP TRUE +#endif + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_REGISTRY) +#define CH_CFG_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_WAITEXIT) +#define CH_CFG_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_SEMAPHORES) +#define CH_CFG_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MUTEXES) +#define CH_CFG_USE_MUTEXES TRUE +#endif + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_CONDVARS) +#define CH_CFG_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_EVENTS) +#define CH_CFG_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MESSAGES) +#define CH_CFG_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#if !defined(CH_CFG_USE_DYNAMIC) +#define CH_CFG_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name OSLIB options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_MAILBOXES) +#define CH_CFG_USE_MAILBOXES TRUE +#endif + +/** + * @brief Memory checks APIs. + * @details If enabled then the memory checks APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCHECKS) +#define CH_CFG_USE_MEMCHECKS TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCORE) +#define CH_CFG_USE_MEMCORE TRUE +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#if !defined(CH_CFG_MEMCORE_SIZE) +#define CH_CFG_MEMCORE_SIZE 0 +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_CFG_USE_HEAP) +#define CH_CFG_USE_HEAP TRUE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMPOOLS) +#define CH_CFG_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_FIFOS) +#define CH_CFG_USE_OBJ_FIFOS TRUE +#endif + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Objects Caches APIs. + * @details If enabled then the objects caches APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_CACHES) +#define CH_CFG_USE_OBJ_CACHES TRUE +#endif + +/** + * @brief Delegate threads APIs. + * @details If enabled then the delegate threads APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_DELEGATES) +#define CH_CFG_USE_DELEGATES TRUE +#endif + +/** + * @brief Jobs Queues APIs. + * @details If enabled then the jobs queues APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_JOBS) +#define CH_CFG_USE_JOBS TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_CFG_USE_FACTORY) +#define CH_CFG_USE_FACTORY TRUE +#endif + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 +#endif + +/** + * @brief Enables the registry of generic objects. + */ +#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE +#endif + +/** + * @brief Enables factory for generic buffers. + */ +#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE +#endif + +/** + * @brief Enables factory for semaphores. + */ +#if !defined(CH_CFG_FACTORY_SEMAPHORES) +#define CH_CFG_FACTORY_SEMAPHORES TRUE +#endif + +/** + * @brief Enables factory for mailboxes. + */ +#if !defined(CH_CFG_FACTORY_MAILBOXES) +#define CH_CFG_FACTORY_MAILBOXES TRUE +#endif + +/** + * @brief Enables factory for objects FIFOs. + */ +#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE +#endif + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_STATISTICS) +#define CH_DBG_STATISTICS FALSE +#endif + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_MASK) +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_ALL +#endif + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_BUFFER_SIZE) +#define CH_DBG_TRACE_BUFFER_SIZE 128 +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#if !defined(CH_DBG_THREADS_PROFILING) +#define CH_DBG_THREADS_PROFILING FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add system custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add system initialization code here.*/ \ +} + +/** + * @brief OS instance structure extension. + * @details User fields added to the end of the @p os_instance_t structure. + */ +#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS \ + /* Add OS instance custom fields here.*/ + +/** + * @brief OS instance initialization hook. + * + * @param[in] oip pointer to the @p os_instance_t structure + */ +#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) { \ + /* Add OS instance initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + * + * @param[in] ntp thread being switched in + * @param[in] otp thread being switched out + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** + * @brief Runtime Faults Collection Unit hook. + * @details This hook is invoked each time new faults are collected and stored. + */ +#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) { \ + /* Faults handling code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/testhal/AT32/multi/WDT/cfg/at-start-f402/config.h b/testhal/AT32/multi/WDT/cfg/at-start-f402/config.h new file mode 100644 index 0000000000..1e7c044f47 --- /dev/null +++ b/testhal/AT32/multi/WDT/cfg/at-start-f402/config.h @@ -0,0 +1,39 @@ +/* + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * CRC driver system settings. + */ +#define AT32_CRC_USE_CRC1 FALSE + +#define CRC_USE_DMA FALSE +#define AT32_CRC_CRC1_DMA_PRIORITY 2 +#define AT32_CRC_CRC1_IRQ_PRIORITY 5 +#define AT32_CRC_CRC1_DMA_STREAM AT32_DMA_STREAM_ID_ANY + +/* + * I2C fallback driver system settings. + */ +#define SW_I2C_USE_I2C1 FALSE +#define SW_I2C_USE_I2C2 FALSE +#define SW_I2C_USE_I2C3 FALSE +#define SW_I2C_USE_I2C4 FALSE + +/* + * Other settings. + */ +#define BOARD_OTG_VBUSIG diff --git a/testhal/AT32/multi/WDT/cfg/at-start-f402/halconf.h b/testhal/AT32/multi/WDT/cfg/at-start-f402/halconf.h new file mode 100644 index 0000000000..87d87120f4 --- /dev/null +++ b/testhal/AT32/multi/WDT/cfg/at-start-f402/halconf.h @@ -0,0 +1,557 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_8_4_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the EFlash subsystem. + */ +#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__) +#define HAL_USE_EFL FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG TRUE +#endif + +/** + * @brief Enables the WSPI subsystem. + */ +#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) +#define HAL_USE_WSPI FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS FALSE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS FALSE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Timeout before assuming a failure while waiting for card idle. + * @note Time is in milliseconds. + */ +#if !defined(MMC_IDLE_TIMEOUT_MS) || defined(__DOXYGEN__) +#define MMC_IDLE_TIMEOUT_MS 1000 +#endif + +/** + * @brief Mutual exclusion on the SPI bus. + */ +#if !defined(MMC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define MMC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SIO driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SIO_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SIO_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Support for thread synchronization API. + */ +#if !defined(SIO_USE_SYNCHRONIZATION) || defined(__DOXYGEN__) +#define SIO_USE_SYNCHRONIZATION TRUE +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 256 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 2 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Inserts an assertion on function errors before returning. + */ +#if !defined(SPI_USE_ASSERT_ON_ERROR) || defined(__DOXYGEN__) +#define SPI_USE_ASSERT_ON_ERROR TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#include "halconf_community.h" + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/testhal/AT32/multi/WDT/cfg/at-start-f402/halconf_community.h b/testhal/AT32/multi/WDT/cfg/at-start-f402/halconf_community.h new file mode 100644 index 0000000000..5a77290c71 --- /dev/null +++ b/testhal/AT32/multi/WDT/cfg/at-start-f402/halconf_community.h @@ -0,0 +1,182 @@ +/* + ChibiOS - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef HALCONF_COMMUNITY_H +#define HALCONF_COMMUNITY_H + +/** + * @brief Enables the community overlay. + */ +#if !defined(HAL_USE_COMMUNITY) || defined(__DOXYGEN__) +#define HAL_USE_COMMUNITY TRUE +#endif + +/** + * @brief Enables the FSMC subsystem. + */ +#if !defined(HAL_USE_FSMC) || defined(__DOXYGEN__) +#define HAL_USE_FSMC FALSE +#endif + +/** + * @brief Enables the NAND subsystem. + */ +#if !defined(HAL_USE_NAND) || defined(__DOXYGEN__) +#define HAL_USE_NAND FALSE +#endif + +/** + * @brief Enables the 1-wire subsystem. + */ +#if !defined(HAL_USE_ONEWIRE) || defined(__DOXYGEN__) +#define HAL_USE_ONEWIRE FALSE +#endif + +/** + * @brief Enables the EICU subsystem. + */ +#if !defined(HAL_USE_EICU) || defined(__DOXYGEN__) +#define HAL_USE_EICU FALSE +#endif + +/** + * @brief Enables the CRC subsystem. + */ +#if !defined(HAL_USE_CRC) || defined(__DOXYGEN__) +#define HAL_USE_CRC FALSE +#endif + +/** + * @brief Enables the RNG subsystem. + */ +#if !defined(HAL_USE_RNG) || defined(__DOXYGEN__) +#define HAL_USE_RNG FALSE +#endif + +/** + * @brief Enables the EEPROM subsystem. + */ +#if !defined(HAL_USE_EEPROM) || defined(__DOXYGEN__) +#define HAL_USE_EEPROM FALSE +#endif + +/** + * @brief Enables the TIMCAP subsystem. + */ +#if !defined(HAL_USE_TIMCAP) || defined(__DOXYGEN__) +#define HAL_USE_TIMCAP FALSE +#endif + +/** + * @brief Enables the COMP subsystem. + */ +#if !defined(HAL_USE_COMP) || defined(__DOXYGEN__) +#define HAL_USE_COMP FALSE +#endif + +/** + * @brief Enables the OPAMP subsystem. + */ +#if !defined(HAL_USE_OPAMP) || defined(__DOXYGEN__) +#define HAL_USE_OPAMP FALSE +#endif + +/** + * @brief Enables the QEI subsystem. + */ +#if !defined(HAL_USE_QEI) || defined(__DOXYGEN__) +#define HAL_USE_QEI FALSE +#endif + +/** + * @brief Enables the USBH subsystem. + */ +#if !defined(HAL_USE_USBH) || defined(__DOXYGEN__) +#define HAL_USE_USBH FALSE +#endif + +/** + * @brief Enables the USB_MSD subsystem. + */ +#if !defined(HAL_USE_USB_MSD) || defined(__DOXYGEN__) +#define HAL_USE_USB_MSD FALSE +#endif + +/*===========================================================================*/ +/* FSMCNAND driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the @p nandAcquireBus() and @p nanReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(NAND_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define NAND_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* 1-wire driver related settings. */ +/*===========================================================================*/ +/** + * @brief Enables strong pull up feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_STRONG_PULLUP FALSE + +/** + * @brief Enables search ROM feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_SEARCH_ROM TRUE + +/*===========================================================================*/ +/* QEI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables discard of overlow + */ +#if !defined(QEI_USE_OVERFLOW_DISCARD) || defined(__DOXYGEN__) +#define QEI_USE_OVERFLOW_DISCARD FALSE +#endif + +/** + * @brief Enables min max of overlow + */ +#if !defined(QEI_USE_OVERFLOW_MINMAX) || defined(__DOXYGEN__) +#define QEI_USE_OVERFLOW_MINMAX FALSE +#endif + +/*===========================================================================*/ +/* EEProm driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables 24xx series I2C eeprom device driver. + * @note Disabling this option saves both code and data space. + */ +#define EEPROM_USE_EE24XX FALSE + /** + * @brief Enables 25xx series SPI eeprom device driver. + * @note Disabling this option saves both code and data space. + */ +#define EEPROM_USE_EE25XX FALSE + +#endif /* HALCONF_COMMUNITY_H */ + +/** @} */ diff --git a/testhal/AT32/multi/WDT/cfg/at-start-f402/mcuconf.h b/testhal/AT32/multi/WDT/cfg/at-start-f402/mcuconf.h new file mode 100644 index 0000000000..ff7cab6b7f --- /dev/null +++ b/testhal/AT32/multi/WDT/cfg/at-start-f402/mcuconf.h @@ -0,0 +1,268 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef MCUCONF_H +#define MCUCONF_H + +/* + * AT32F402 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define AT32F402_MCUCONF + +/* + * General settings. + */ +#define AT32_NO_INIT FALSE + +/* + * HAL driver system settings. + */ +#define AT32_HICK_ENABLED TRUE +#define AT32_LICK_ENABLED TRUE +#define AT32_HEXT_ENABLED TRUE +#define AT32_LEXT_ENABLED FALSE +#define AT32_PLLU_ENABLED TRUE +#define AT32_SCLKSEL AT32_SCLKSEL_PLL +#define AT32_PLLRCS AT32_PLLRCS_HEXT +#define AT32_PLL_MS_VALUE 1 +#define AT32_PLL_NS_VALUE 72 +#define AT32_PLL_FP_VALUE 4 +#define AT32_PLL_FU_VALUE 18 +#define AT32_AHBDIV AT32_AHBDIV_DIV1 +#define AT32_APB1DIV AT32_APB1DIV_DIV2 +#define AT32_APB2DIV AT32_APB2DIV_DIV1 +#define AT32_HICK_TO_SCLK AT32_HICK_TO_SCLK_48M +#define AT32_HICKDIV AT32_HICKDIV_DIV1 +#define AT32_HICK_TO_SCLK_DIV AT32_HICK_TO_SCLK_DIV_DIV1 +#define AT32_HEXT_TO_SCLK_DIV AT32_HEXT_TO_SCLK_DIV_DIV1 +#define AT32_USB_CLOCK48_REQUIRED TRUE +#define AT32_PLLU_USB48_SEL AT32_PLLU_USB48_SEL_PLLU +#define AT32_CLKOUT_SEL AT32_CLKOUT_SEL_HICK +#define AT32_CLKOUTDIV1 AT32_CLKOUTDIV1_DIV1 +#define AT32_CLKOUTDIV2 AT32_CLKOUTDIV2_DIV1 +#define AT32_ERTCSEL AT32_ERTCSEL_LICK +#define AT32_ERTCDIV_VALUE 12 +#define AT32_I2SF5CLKSEL AT32_I2SF5CLKSEL_SCLK +#define AT32_PVM_ENABLE FALSE +#define AT32_PVMSEL AT32_PVMSEL_LEV1 +#define AT32_LDOOVSEL AT32_LDOOVSEL_LEV3 + +/* + * IRQ system settings. + */ +#define AT32_IRQ_EXINT0_PRIORITY 6 +#define AT32_IRQ_EXINT1_PRIORITY 6 +#define AT32_IRQ_EXINT2_PRIORITY 6 +#define AT32_IRQ_EXINT3_PRIORITY 6 +#define AT32_IRQ_EXINT4_PRIORITY 6 +#define AT32_IRQ_EXINT5_9_PRIORITY 6 +#define AT32_IRQ_EXINT10_15_PRIORITY 6 +#define AT32_IRQ_EXINT16_PRIORITY 6 +#define AT32_IRQ_EXINT17_PRIORITY 15 +#define AT32_IRQ_EXINT18_PRIORITY 6 +#define AT32_IRQ_EXINT20_PRIORITY 6 +#define AT32_IRQ_EXINT21_PRIORITY 15 +#define AT32_IRQ_EXINT22_PRIORITY 15 + +#define AT32_IRQ_TMR1_BRK_TMR9_PRIORITY 7 +#define AT32_IRQ_TMR1_OVF_TMR10_PRIORITY 7 +#define AT32_IRQ_TMR1_HALL_TMR11_PRIORITY 7 +#define AT32_IRQ_TMR1_CH_PRIORITY 7 +#define AT32_IRQ_TMR2_PRIORITY 7 +#define AT32_IRQ_TMR3_PRIORITY 7 +#define AT32_IRQ_TMR4_PRIORITY 7 +#define AT32_IRQ_TMR6_PRIORITY 7 +#define AT32_IRQ_TMR7_PRIORITY 7 +#define AT32_IRQ_TMR13_PRIORITY 7 +#define AT32_IRQ_TMR14_PRIORITY 7 + +#define AT32_IRQ_USART1_PRIORITY 12 +#define AT32_IRQ_USART2_PRIORITY 12 +#define AT32_IRQ_USART3_PRIORITY 12 +#define AT32_IRQ_UART4_PRIORITY 12 +#define AT32_IRQ_UART5_PRIORITY 12 +#define AT32_IRQ_USART6_PRIORITY 12 +#define AT32_IRQ_UART7_PRIORITY 12 +#define AT32_IRQ_UART8_PRIORITY 12 + +/* + * ADC driver system settings. + */ +#define AT32_ADC_USE_ADC1 FALSE +#define AT32_ADC_ADC1_DMA_PRIORITY 2 +#define AT32_ADC_IRQ_PRIORITY 6 +#define AT32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define AT32_ADC_ADCDIV 8 + +/* + * CAN driver system settings. + */ +#define AT32_CAN_USE_CAN1 FALSE +#define AT32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * GPT driver system settings. + */ +#define AT32_GPT_USE_TMR1 FALSE +#define AT32_GPT_USE_TMR2 FALSE +#define AT32_GPT_USE_TMR3 FALSE +#define AT32_GPT_USE_TMR4 FALSE +#define AT32_GPT_USE_TMR6 FALSE +#define AT32_GPT_USE_TMR7 FALSE +#define AT32_GPT_USE_TMR9 FALSE +#define AT32_GPT_USE_TMR10 FALSE +#define AT32_GPT_USE_TMR11 FALSE +#define AT32_GPT_USE_TMR13 FALSE +#define AT32_GPT_USE_TMR14 FALSE + +/* + * I2C driver system settings. + */ +#define AT32_I2C_USE_I2C1 FALSE +#define AT32_I2C_USE_I2C2 FALSE +#define AT32_I2C_USE_I2C3 FALSE +#define AT32_I2C_BUSY_TIMEOUT 50 +#define AT32_I2C_I2C1_DMA_PRIORITY 3 +#define AT32_I2C_I2C2_DMA_PRIORITY 3 +#define AT32_I2C_I2C3_DMA_PRIORITY 3 +#define AT32_I2C_I2C1_IRQ_PRIORITY 5 +#define AT32_I2C_I2C2_IRQ_PRIORITY 5 +#define AT32_I2C_I2C3_IRQ_PRIORITY 5 +#define AT32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define AT32_ICU_USE_TMR1 FALSE +#define AT32_ICU_USE_TMR2 FALSE +#define AT32_ICU_USE_TMR3 FALSE +#define AT32_ICU_USE_TMR4 FALSE +#define AT32_ICU_USE_TMR9 FALSE + +/* + * PWM driver system settings. + */ +#define AT32_PWM_USE_TMR1 FALSE +#define AT32_PWM_USE_TMR2 FALSE +#define AT32_PWM_USE_TMR3 FALSE +#define AT32_PWM_USE_TMR4 FALSE +#define AT32_PWM_USE_TMR9 FALSE +#define AT32_PWM_USE_TMR10 FALSE +#define AT32_PWM_USE_TMR11 FALSE +#define AT32_PWM_USE_TMR13 FALSE +#define AT32_PWM_USE_TMR14 FALSE + +/* + * RTC driver system settings. + */ +#define AT32_ERTC_DIVA_VALUE 32 +#define AT32_ERTC_DIVB_VALUE 1024 +#define AT32_ERTC_CTRL_INIT 0 +#define AT32_ERTC_TAMP_INIT 0 + +/* + * SERIAL driver system settings. + */ +#define AT32_SERIAL_USE_USART1 FALSE +#define AT32_SERIAL_USE_USART2 FALSE +#define AT32_SERIAL_USE_USART3 FALSE +#define AT32_SERIAL_USE_UART4 FALSE +#define AT32_SERIAL_USE_UART5 FALSE +#define AT32_SERIAL_USE_USART6 FALSE +#define AT32_SERIAL_USE_UART7 FALSE +#define AT32_SERIAL_USE_UART8 FALSE + +/* + * SIO driver system settings. + */ +#define AT32_SIO_USE_USART1 FALSE +#define AT32_SIO_USE_USART2 FALSE +#define AT32_SIO_USE_USART3 FALSE +#define AT32_SIO_USE_UART4 FALSE +#define AT32_SIO_USE_UART5 FALSE +#define AT32_SIO_USE_USART6 FALSE +#define AT32_SIO_USE_UART7 FALSE +#define AT32_SIO_USE_UART8 FALSE + +/* + * SPI driver system settings. + */ +#define AT32_SPI_USE_SPI1 FALSE +#define AT32_SPI_USE_SPI2 FALSE +#define AT32_SPI_USE_SPI3 FALSE +#define AT32_SPI_SPI1_DMA_PRIORITY 1 +#define AT32_SPI_SPI2_DMA_PRIORITY 1 +#define AT32_SPI_SPI3_DMA_PRIORITY 1 +#define AT32_SPI_SPI1_IRQ_PRIORITY 10 +#define AT32_SPI_SPI2_IRQ_PRIORITY 10 +#define AT32_SPI_SPI3_IRQ_PRIORITY 10 +#define AT32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define AT32_ST_IRQ_PRIORITY 8 +#define AT32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define AT32_UART_USE_USART1 FALSE +#define AT32_UART_USE_USART2 FALSE +#define AT32_UART_USE_USART3 FALSE +#define AT32_UART_USE_UART4 FALSE +#define AT32_UART_USE_UART5 FALSE +#define AT32_UART_USE_USART6 FALSE +#define AT32_UART_USE_UART7 FALSE +#define AT32_UART_USE_UART8 FALSE +#define AT32_UART_USART1_DMA_PRIORITY 0 +#define AT32_UART_USART2_DMA_PRIORITY 0 +#define AT32_UART_USART3_DMA_PRIORITY 0 +#define AT32_UART_UART4_DMA_PRIORITY 0 +#define AT32_UART_UART5_DMA_PRIORITY 0 +#define AT32_UART_USART6_DMA_PRIORITY 0 +#define AT32_UART_UART7_DMA_PRIORITY 0 +#define AT32_UART_UART8_DMA_PRIORITY 0 +#define AT32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define AT32_USB_USE_OTG1 FALSE +#define AT32_USB_OTG1_IRQ_PRIORITY 14 +#define AT32_USB_OTG1_RX_FIFO_SIZE 512 + +/* + * WDG driver system settings. + */ +#define AT32_WDG_USE_WDT TRUE + +#include "config.h" + +#endif /* MCUCONF_H */ diff --git a/testhal/AT32/multi/WDT/cfg/at-start-f402/portab.c b/testhal/AT32/multi/WDT/cfg/at-start-f402/portab.c new file mode 100644 index 0000000000..bd71ff0084 --- /dev/null +++ b/testhal/AT32/multi/WDT/cfg/at-start-f402/portab.c @@ -0,0 +1,70 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file portab.c + * @brief Application portability module code. + * + * @addtogroup application_portability + * @{ + */ + +#include "hal.h" + +#include "portab.h" + +/*===========================================================================*/ +/* Module local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module exported variables. */ +/*===========================================================================*/ + +/* + * Watchdog deadline set to more than one second (LICK = 40000 / (64 * 1000)). + */ +WDGConfig wdgcfg = { + AT32_WDT_DIV_64, + AT32_WDT_RLD(1000), +#if AT32_WDT_IS_WINDOWED + AT32_WDT_WIN_DISABLED +#endif +}; + +/*===========================================================================*/ +/* Module local types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module exported functions. */ +/*===========================================================================*/ + +void portab_setup(void) { + +} + +/** @} */ diff --git a/testhal/AT32/multi/WDT/cfg/at-start-f402/portab.h b/testhal/AT32/multi/WDT/cfg/at-start-f402/portab.h new file mode 100644 index 0000000000..f81dad3fbe --- /dev/null +++ b/testhal/AT32/multi/WDT/cfg/at-start-f402/portab.h @@ -0,0 +1,78 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file portab.h + * @brief Application portability macros and structures. + * + * @addtogroup application_portability + * @{ + */ + +#ifndef PORTAB_H +#define PORTAB_H + +/*===========================================================================*/ +/* Module constants. */ +/*===========================================================================*/ + +#define PORTAB_WDT1 WDGD1 + +#define PORTAB_BLINK_LED1 LINE_LED_RED + +#define PORTAB_BLINK_LED2 LINE_LED_YELLOW + +#define PORTAB_BLINK_LED3 LINE_LED_GREEN + +/*===========================================================================*/ +/* Module pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +extern WDGConfig wdgcfg; + +#ifdef __cplusplus +extern "C" { +#endif + void portab_setup(void); +#ifdef __cplusplus +} +#endif + +/*===========================================================================*/ +/* Module inline functions. */ +/*===========================================================================*/ + +#endif /* PORTAB_H */ + +/** @} */ diff --git a/testhal/AT32/multi/WDT/cfg/at-start-f405/chconf.h b/testhal/AT32/multi/WDT/cfg/at-start-f405/chconf.h new file mode 100644 index 0000000000..56fe06776a --- /dev/null +++ b/testhal/AT32/multi/WDT/cfg/at-start-f405/chconf.h @@ -0,0 +1,842 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_7_0_ + +/*===========================================================================*/ +/** + * @name System settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Handling of instances. + * @note If enabled then threads assigned to various instances can + * interact each other using the same synchronization objects. + * If disabled then each OS instance is a separate world, no + * direct interactions are handled by the OS. + */ +#if !defined(CH_CFG_SMP_MODE) +#define CH_CFG_SMP_MODE FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_ST_RESOLUTION) +#define CH_CFG_ST_RESOLUTION 32 +#endif + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_CFG_ST_FREQUENCY) +#define CH_CFG_ST_FREQUENCY 10000 +#endif + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_INTERVALS_SIZE) +#define CH_CFG_INTERVALS_SIZE 32 +#endif + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_TIME_TYPES_SIZE) +#define CH_CFG_TIME_TYPES_SIZE 32 +#endif + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#if !defined(CH_CFG_ST_TIMEDELTA) +#define CH_CFG_ST_TIMEDELTA 2 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#if !defined(CH_CFG_TIME_QUANTUM) +#define CH_CFG_TIME_QUANTUM 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#if !defined(CH_CFG_NO_IDLE_THREAD) +#define CH_CFG_NO_IDLE_THREAD FALSE +#endif + +/** + * @brief Kernel hardening level. + * @details This option is the level of functional-safety checks enabled + * in the kerkel. The meaning is: + * - 0: No checks, maximum performance. + * - 1: Reasonable checks. + * - 2: All checks. + * . + */ +#if !defined(CH_CFG_HARDENING_LEVEL) +#define CH_CFG_HARDENING_LEVEL 0 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_OPTIMIZE_SPEED) +#define CH_CFG_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TM) +#define CH_CFG_USE_TM TRUE +#endif + +/** + * @brief Time Stamps APIs. + * @details If enabled then the time stamps APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TIMESTAMP) +#define CH_CFG_USE_TIMESTAMP TRUE +#endif + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_REGISTRY) +#define CH_CFG_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_WAITEXIT) +#define CH_CFG_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_SEMAPHORES) +#define CH_CFG_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MUTEXES) +#define CH_CFG_USE_MUTEXES TRUE +#endif + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_CONDVARS) +#define CH_CFG_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_EVENTS) +#define CH_CFG_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MESSAGES) +#define CH_CFG_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#if !defined(CH_CFG_USE_DYNAMIC) +#define CH_CFG_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name OSLIB options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_MAILBOXES) +#define CH_CFG_USE_MAILBOXES TRUE +#endif + +/** + * @brief Memory checks APIs. + * @details If enabled then the memory checks APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCHECKS) +#define CH_CFG_USE_MEMCHECKS TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCORE) +#define CH_CFG_USE_MEMCORE TRUE +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#if !defined(CH_CFG_MEMCORE_SIZE) +#define CH_CFG_MEMCORE_SIZE 0 +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_CFG_USE_HEAP) +#define CH_CFG_USE_HEAP TRUE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMPOOLS) +#define CH_CFG_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_FIFOS) +#define CH_CFG_USE_OBJ_FIFOS TRUE +#endif + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Objects Caches APIs. + * @details If enabled then the objects caches APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_CACHES) +#define CH_CFG_USE_OBJ_CACHES TRUE +#endif + +/** + * @brief Delegate threads APIs. + * @details If enabled then the delegate threads APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_DELEGATES) +#define CH_CFG_USE_DELEGATES TRUE +#endif + +/** + * @brief Jobs Queues APIs. + * @details If enabled then the jobs queues APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_JOBS) +#define CH_CFG_USE_JOBS TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_CFG_USE_FACTORY) +#define CH_CFG_USE_FACTORY TRUE +#endif + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 +#endif + +/** + * @brief Enables the registry of generic objects. + */ +#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE +#endif + +/** + * @brief Enables factory for generic buffers. + */ +#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE +#endif + +/** + * @brief Enables factory for semaphores. + */ +#if !defined(CH_CFG_FACTORY_SEMAPHORES) +#define CH_CFG_FACTORY_SEMAPHORES TRUE +#endif + +/** + * @brief Enables factory for mailboxes. + */ +#if !defined(CH_CFG_FACTORY_MAILBOXES) +#define CH_CFG_FACTORY_MAILBOXES TRUE +#endif + +/** + * @brief Enables factory for objects FIFOs. + */ +#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE +#endif + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_STATISTICS) +#define CH_DBG_STATISTICS FALSE +#endif + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_MASK) +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_ALL +#endif + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_BUFFER_SIZE) +#define CH_DBG_TRACE_BUFFER_SIZE 128 +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#if !defined(CH_DBG_THREADS_PROFILING) +#define CH_DBG_THREADS_PROFILING FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add system custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add system initialization code here.*/ \ +} + +/** + * @brief OS instance structure extension. + * @details User fields added to the end of the @p os_instance_t structure. + */ +#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS \ + /* Add OS instance custom fields here.*/ + +/** + * @brief OS instance initialization hook. + * + * @param[in] oip pointer to the @p os_instance_t structure + */ +#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) { \ + /* Add OS instance initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + * + * @param[in] ntp thread being switched in + * @param[in] otp thread being switched out + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** + * @brief Runtime Faults Collection Unit hook. + * @details This hook is invoked each time new faults are collected and stored. + */ +#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) { \ + /* Faults handling code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/testhal/AT32/multi/WDT/cfg/at-start-f405/config.h b/testhal/AT32/multi/WDT/cfg/at-start-f405/config.h new file mode 100644 index 0000000000..1e7c044f47 --- /dev/null +++ b/testhal/AT32/multi/WDT/cfg/at-start-f405/config.h @@ -0,0 +1,39 @@ +/* + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * CRC driver system settings. + */ +#define AT32_CRC_USE_CRC1 FALSE + +#define CRC_USE_DMA FALSE +#define AT32_CRC_CRC1_DMA_PRIORITY 2 +#define AT32_CRC_CRC1_IRQ_PRIORITY 5 +#define AT32_CRC_CRC1_DMA_STREAM AT32_DMA_STREAM_ID_ANY + +/* + * I2C fallback driver system settings. + */ +#define SW_I2C_USE_I2C1 FALSE +#define SW_I2C_USE_I2C2 FALSE +#define SW_I2C_USE_I2C3 FALSE +#define SW_I2C_USE_I2C4 FALSE + +/* + * Other settings. + */ +#define BOARD_OTG_VBUSIG diff --git a/testhal/AT32/multi/WDT/cfg/at-start-f405/halconf.h b/testhal/AT32/multi/WDT/cfg/at-start-f405/halconf.h new file mode 100644 index 0000000000..87d87120f4 --- /dev/null +++ b/testhal/AT32/multi/WDT/cfg/at-start-f405/halconf.h @@ -0,0 +1,557 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_8_4_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the EFlash subsystem. + */ +#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__) +#define HAL_USE_EFL FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG TRUE +#endif + +/** + * @brief Enables the WSPI subsystem. + */ +#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) +#define HAL_USE_WSPI FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS FALSE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS FALSE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Timeout before assuming a failure while waiting for card idle. + * @note Time is in milliseconds. + */ +#if !defined(MMC_IDLE_TIMEOUT_MS) || defined(__DOXYGEN__) +#define MMC_IDLE_TIMEOUT_MS 1000 +#endif + +/** + * @brief Mutual exclusion on the SPI bus. + */ +#if !defined(MMC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define MMC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SIO driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SIO_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SIO_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Support for thread synchronization API. + */ +#if !defined(SIO_USE_SYNCHRONIZATION) || defined(__DOXYGEN__) +#define SIO_USE_SYNCHRONIZATION TRUE +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 256 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 2 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Inserts an assertion on function errors before returning. + */ +#if !defined(SPI_USE_ASSERT_ON_ERROR) || defined(__DOXYGEN__) +#define SPI_USE_ASSERT_ON_ERROR TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#include "halconf_community.h" + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/testhal/AT32/multi/WDT/cfg/at-start-f405/halconf_community.h b/testhal/AT32/multi/WDT/cfg/at-start-f405/halconf_community.h new file mode 100644 index 0000000000..5a77290c71 --- /dev/null +++ b/testhal/AT32/multi/WDT/cfg/at-start-f405/halconf_community.h @@ -0,0 +1,182 @@ +/* + ChibiOS - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef HALCONF_COMMUNITY_H +#define HALCONF_COMMUNITY_H + +/** + * @brief Enables the community overlay. + */ +#if !defined(HAL_USE_COMMUNITY) || defined(__DOXYGEN__) +#define HAL_USE_COMMUNITY TRUE +#endif + +/** + * @brief Enables the FSMC subsystem. + */ +#if !defined(HAL_USE_FSMC) || defined(__DOXYGEN__) +#define HAL_USE_FSMC FALSE +#endif + +/** + * @brief Enables the NAND subsystem. + */ +#if !defined(HAL_USE_NAND) || defined(__DOXYGEN__) +#define HAL_USE_NAND FALSE +#endif + +/** + * @brief Enables the 1-wire subsystem. + */ +#if !defined(HAL_USE_ONEWIRE) || defined(__DOXYGEN__) +#define HAL_USE_ONEWIRE FALSE +#endif + +/** + * @brief Enables the EICU subsystem. + */ +#if !defined(HAL_USE_EICU) || defined(__DOXYGEN__) +#define HAL_USE_EICU FALSE +#endif + +/** + * @brief Enables the CRC subsystem. + */ +#if !defined(HAL_USE_CRC) || defined(__DOXYGEN__) +#define HAL_USE_CRC FALSE +#endif + +/** + * @brief Enables the RNG subsystem. + */ +#if !defined(HAL_USE_RNG) || defined(__DOXYGEN__) +#define HAL_USE_RNG FALSE +#endif + +/** + * @brief Enables the EEPROM subsystem. + */ +#if !defined(HAL_USE_EEPROM) || defined(__DOXYGEN__) +#define HAL_USE_EEPROM FALSE +#endif + +/** + * @brief Enables the TIMCAP subsystem. + */ +#if !defined(HAL_USE_TIMCAP) || defined(__DOXYGEN__) +#define HAL_USE_TIMCAP FALSE +#endif + +/** + * @brief Enables the COMP subsystem. + */ +#if !defined(HAL_USE_COMP) || defined(__DOXYGEN__) +#define HAL_USE_COMP FALSE +#endif + +/** + * @brief Enables the OPAMP subsystem. + */ +#if !defined(HAL_USE_OPAMP) || defined(__DOXYGEN__) +#define HAL_USE_OPAMP FALSE +#endif + +/** + * @brief Enables the QEI subsystem. + */ +#if !defined(HAL_USE_QEI) || defined(__DOXYGEN__) +#define HAL_USE_QEI FALSE +#endif + +/** + * @brief Enables the USBH subsystem. + */ +#if !defined(HAL_USE_USBH) || defined(__DOXYGEN__) +#define HAL_USE_USBH FALSE +#endif + +/** + * @brief Enables the USB_MSD subsystem. + */ +#if !defined(HAL_USE_USB_MSD) || defined(__DOXYGEN__) +#define HAL_USE_USB_MSD FALSE +#endif + +/*===========================================================================*/ +/* FSMCNAND driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the @p nandAcquireBus() and @p nanReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(NAND_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define NAND_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* 1-wire driver related settings. */ +/*===========================================================================*/ +/** + * @brief Enables strong pull up feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_STRONG_PULLUP FALSE + +/** + * @brief Enables search ROM feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_SEARCH_ROM TRUE + +/*===========================================================================*/ +/* QEI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables discard of overlow + */ +#if !defined(QEI_USE_OVERFLOW_DISCARD) || defined(__DOXYGEN__) +#define QEI_USE_OVERFLOW_DISCARD FALSE +#endif + +/** + * @brief Enables min max of overlow + */ +#if !defined(QEI_USE_OVERFLOW_MINMAX) || defined(__DOXYGEN__) +#define QEI_USE_OVERFLOW_MINMAX FALSE +#endif + +/*===========================================================================*/ +/* EEProm driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables 24xx series I2C eeprom device driver. + * @note Disabling this option saves both code and data space. + */ +#define EEPROM_USE_EE24XX FALSE + /** + * @brief Enables 25xx series SPI eeprom device driver. + * @note Disabling this option saves both code and data space. + */ +#define EEPROM_USE_EE25XX FALSE + +#endif /* HALCONF_COMMUNITY_H */ + +/** @} */ diff --git a/testhal/AT32/multi/WDT/cfg/at-start-f405/mcuconf.h b/testhal/AT32/multi/WDT/cfg/at-start-f405/mcuconf.h new file mode 100644 index 0000000000..7959d53aef --- /dev/null +++ b/testhal/AT32/multi/WDT/cfg/at-start-f405/mcuconf.h @@ -0,0 +1,272 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef MCUCONF_H +#define MCUCONF_H + +/* + * AT32F405 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define AT32F405_MCUCONF + +/* + * General settings. + */ +#define AT32_NO_INIT FALSE + +/* + * HAL driver system settings. + */ +#define AT32_HICK_ENABLED TRUE +#define AT32_LICK_ENABLED TRUE +#define AT32_HEXT_ENABLED TRUE +#define AT32_LEXT_ENABLED FALSE +#define AT32_PLLU_ENABLED TRUE +#define AT32_SCLKSEL AT32_SCLKSEL_PLL +#define AT32_PLLRCS AT32_PLLRCS_HEXT +#define AT32_PLL_MS_VALUE 1 +#define AT32_PLL_NS_VALUE 72 +#define AT32_PLL_FP_VALUE 4 +#define AT32_PLL_FU_VALUE 18 +#define AT32_AHBDIV AT32_AHBDIV_DIV1 +#define AT32_APB1DIV AT32_APB1DIV_DIV2 +#define AT32_APB2DIV AT32_APB2DIV_DIV1 +#define AT32_HICK_TO_SCLK AT32_HICK_TO_SCLK_48M +#define AT32_HICKDIV AT32_HICKDIV_DIV1 +#define AT32_HICK_TO_SCLK_DIV AT32_HICK_TO_SCLK_DIV_DIV1 +#define AT32_HEXT_TO_SCLK_DIV AT32_HEXT_TO_SCLK_DIV_DIV1 +#define AT32_USB_CLOCK48_REQUIRED TRUE +#define AT32_PLLU_USB48_SEL AT32_PLLU_USB48_SEL_PLLU +#define AT32_CLKOUT_SEL AT32_CLKOUT_SEL_HICK +#define AT32_CLKOUTDIV1 AT32_CLKOUTDIV1_DIV1 +#define AT32_CLKOUTDIV2 AT32_CLKOUTDIV2_DIV1 +#define AT32_ERTCSEL AT32_ERTCSEL_LICK +#define AT32_ERTCDIV_VALUE 12 +#define AT32_I2SF5CLKSEL AT32_I2SF5CLKSEL_SCLK +#define AT32_PVM_ENABLE FALSE +#define AT32_PVMSEL AT32_PVMSEL_LEV1 +#define AT32_LDOOVSEL AT32_LDOOVSEL_LEV3 + +/* + * IRQ system settings. + */ +#define AT32_IRQ_EXINT0_PRIORITY 6 +#define AT32_IRQ_EXINT1_PRIORITY 6 +#define AT32_IRQ_EXINT2_PRIORITY 6 +#define AT32_IRQ_EXINT3_PRIORITY 6 +#define AT32_IRQ_EXINT4_PRIORITY 6 +#define AT32_IRQ_EXINT5_9_PRIORITY 6 +#define AT32_IRQ_EXINT10_15_PRIORITY 6 +#define AT32_IRQ_EXINT16_PRIORITY 6 +#define AT32_IRQ_EXINT17_PRIORITY 15 +#define AT32_IRQ_EXINT18_PRIORITY 6 +#define AT32_IRQ_EXINT20_PRIORITY 6 +#define AT32_IRQ_EXINT21_PRIORITY 15 +#define AT32_IRQ_EXINT22_PRIORITY 15 + +#define AT32_IRQ_TMR1_BRK_TMR9_PRIORITY 7 +#define AT32_IRQ_TMR1_OVF_TMR10_PRIORITY 7 +#define AT32_IRQ_TMR1_HALL_TMR11_PRIORITY 7 +#define AT32_IRQ_TMR1_CH_PRIORITY 7 +#define AT32_IRQ_TMR2_PRIORITY 7 +#define AT32_IRQ_TMR3_PRIORITY 7 +#define AT32_IRQ_TMR4_PRIORITY 7 +#define AT32_IRQ_TMR6_PRIORITY 7 +#define AT32_IRQ_TMR7_PRIORITY 7 +#define AT32_IRQ_TMR13_PRIORITY 7 +#define AT32_IRQ_TMR14_PRIORITY 7 + +#define AT32_IRQ_USART1_PRIORITY 12 +#define AT32_IRQ_USART2_PRIORITY 12 +#define AT32_IRQ_USART3_PRIORITY 12 +#define AT32_IRQ_UART4_PRIORITY 12 +#define AT32_IRQ_UART5_PRIORITY 12 +#define AT32_IRQ_USART6_PRIORITY 12 +#define AT32_IRQ_UART7_PRIORITY 12 +#define AT32_IRQ_UART8_PRIORITY 12 + +/* + * ADC driver system settings. + */ +#define AT32_ADC_USE_ADC1 FALSE +#define AT32_ADC_ADC1_DMA_PRIORITY 2 +#define AT32_ADC_IRQ_PRIORITY 6 +#define AT32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define AT32_ADC_ADCDIV 8 + +/* + * CAN driver system settings. + */ +#define AT32_CAN_USE_CAN1 FALSE +#define AT32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * GPT driver system settings. + */ +#define AT32_GPT_USE_TMR1 FALSE +#define AT32_GPT_USE_TMR2 FALSE +#define AT32_GPT_USE_TMR3 FALSE +#define AT32_GPT_USE_TMR4 FALSE +#define AT32_GPT_USE_TMR6 FALSE +#define AT32_GPT_USE_TMR7 FALSE +#define AT32_GPT_USE_TMR9 FALSE +#define AT32_GPT_USE_TMR10 FALSE +#define AT32_GPT_USE_TMR11 FALSE +#define AT32_GPT_USE_TMR13 FALSE +#define AT32_GPT_USE_TMR14 FALSE + +/* + * I2C driver system settings. + */ +#define AT32_I2C_USE_I2C1 FALSE +#define AT32_I2C_USE_I2C2 FALSE +#define AT32_I2C_USE_I2C3 FALSE +#define AT32_I2C_BUSY_TIMEOUT 50 +#define AT32_I2C_I2C1_DMA_PRIORITY 3 +#define AT32_I2C_I2C2_DMA_PRIORITY 3 +#define AT32_I2C_I2C3_DMA_PRIORITY 3 +#define AT32_I2C_I2C1_IRQ_PRIORITY 5 +#define AT32_I2C_I2C2_IRQ_PRIORITY 5 +#define AT32_I2C_I2C3_IRQ_PRIORITY 5 +#define AT32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define AT32_ICU_USE_TMR1 FALSE +#define AT32_ICU_USE_TMR2 FALSE +#define AT32_ICU_USE_TMR3 FALSE +#define AT32_ICU_USE_TMR4 FALSE +#define AT32_ICU_USE_TMR9 FALSE + +/* + * PWM driver system settings. + */ +#define AT32_PWM_USE_TMR1 FALSE +#define AT32_PWM_USE_TMR2 FALSE +#define AT32_PWM_USE_TMR3 FALSE +#define AT32_PWM_USE_TMR4 FALSE +#define AT32_PWM_USE_TMR9 FALSE +#define AT32_PWM_USE_TMR10 FALSE +#define AT32_PWM_USE_TMR11 FALSE +#define AT32_PWM_USE_TMR13 FALSE +#define AT32_PWM_USE_TMR14 FALSE + +/* + * RTC driver system settings. + */ +#define AT32_ERTC_DIVA_VALUE 32 +#define AT32_ERTC_DIVB_VALUE 1024 +#define AT32_ERTC_CTRL_INIT 0 +#define AT32_ERTC_TAMP_INIT 0 + +/* + * SERIAL driver system settings. + */ +#define AT32_SERIAL_USE_USART1 FALSE +#define AT32_SERIAL_USE_USART2 FALSE +#define AT32_SERIAL_USE_USART3 FALSE +#define AT32_SERIAL_USE_UART4 FALSE +#define AT32_SERIAL_USE_UART5 FALSE +#define AT32_SERIAL_USE_USART6 FALSE +#define AT32_SERIAL_USE_UART7 FALSE +#define AT32_SERIAL_USE_UART8 FALSE + +/* + * SIO driver system settings. + */ +#define AT32_SIO_USE_USART1 FALSE +#define AT32_SIO_USE_USART2 FALSE +#define AT32_SIO_USE_USART3 FALSE +#define AT32_SIO_USE_UART4 FALSE +#define AT32_SIO_USE_UART5 FALSE +#define AT32_SIO_USE_USART6 FALSE +#define AT32_SIO_USE_UART7 FALSE +#define AT32_SIO_USE_UART8 FALSE + +/* + * SPI driver system settings. + */ +#define AT32_SPI_USE_SPI1 FALSE +#define AT32_SPI_USE_SPI2 FALSE +#define AT32_SPI_USE_SPI3 FALSE +#define AT32_SPI_SPI1_DMA_PRIORITY 1 +#define AT32_SPI_SPI2_DMA_PRIORITY 1 +#define AT32_SPI_SPI3_DMA_PRIORITY 1 +#define AT32_SPI_SPI1_IRQ_PRIORITY 10 +#define AT32_SPI_SPI2_IRQ_PRIORITY 10 +#define AT32_SPI_SPI3_IRQ_PRIORITY 10 +#define AT32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define AT32_ST_IRQ_PRIORITY 8 +#define AT32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define AT32_UART_USE_USART1 FALSE +#define AT32_UART_USE_USART2 FALSE +#define AT32_UART_USE_USART3 FALSE +#define AT32_UART_USE_UART4 FALSE +#define AT32_UART_USE_UART5 FALSE +#define AT32_UART_USE_USART6 FALSE +#define AT32_UART_USE_UART7 FALSE +#define AT32_UART_USE_UART8 FALSE +#define AT32_UART_USART1_DMA_PRIORITY 0 +#define AT32_UART_USART2_DMA_PRIORITY 0 +#define AT32_UART_USART3_DMA_PRIORITY 0 +#define AT32_UART_UART4_DMA_PRIORITY 0 +#define AT32_UART_UART5_DMA_PRIORITY 0 +#define AT32_UART_USART6_DMA_PRIORITY 0 +#define AT32_UART_UART7_DMA_PRIORITY 0 +#define AT32_UART_UART8_DMA_PRIORITY 0 +#define AT32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define AT32_USB_USE_OTG1 FALSE +#define AT32_USB_USE_OTG2 FALSE +#define AT32_USB_OTG1_IRQ_PRIORITY 14 +#define AT32_USB_OTG2_IRQ_PRIORITY 14 +#define AT32_USB_OTG1_RX_FIFO_SIZE 512 +#define AT32_USB_OTG2_RX_FIFO_SIZE 1024 +#define AT32_USE_USB_OTG2_HS_DMA FALSE + +/* + * WDG driver system settings. + */ +#define AT32_WDG_USE_WDT TRUE + +#include "config.h" + +#endif /* MCUCONF_H */ diff --git a/testhal/AT32/multi/WDT/cfg/at-start-f405/portab.c b/testhal/AT32/multi/WDT/cfg/at-start-f405/portab.c new file mode 100644 index 0000000000..bd71ff0084 --- /dev/null +++ b/testhal/AT32/multi/WDT/cfg/at-start-f405/portab.c @@ -0,0 +1,70 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file portab.c + * @brief Application portability module code. + * + * @addtogroup application_portability + * @{ + */ + +#include "hal.h" + +#include "portab.h" + +/*===========================================================================*/ +/* Module local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module exported variables. */ +/*===========================================================================*/ + +/* + * Watchdog deadline set to more than one second (LICK = 40000 / (64 * 1000)). + */ +WDGConfig wdgcfg = { + AT32_WDT_DIV_64, + AT32_WDT_RLD(1000), +#if AT32_WDT_IS_WINDOWED + AT32_WDT_WIN_DISABLED +#endif +}; + +/*===========================================================================*/ +/* Module local types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module exported functions. */ +/*===========================================================================*/ + +void portab_setup(void) { + +} + +/** @} */ diff --git a/testhal/AT32/multi/WDT/cfg/at-start-f405/portab.h b/testhal/AT32/multi/WDT/cfg/at-start-f405/portab.h new file mode 100644 index 0000000000..f81dad3fbe --- /dev/null +++ b/testhal/AT32/multi/WDT/cfg/at-start-f405/portab.h @@ -0,0 +1,78 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file portab.h + * @brief Application portability macros and structures. + * + * @addtogroup application_portability + * @{ + */ + +#ifndef PORTAB_H +#define PORTAB_H + +/*===========================================================================*/ +/* Module constants. */ +/*===========================================================================*/ + +#define PORTAB_WDT1 WDGD1 + +#define PORTAB_BLINK_LED1 LINE_LED_RED + +#define PORTAB_BLINK_LED2 LINE_LED_YELLOW + +#define PORTAB_BLINK_LED3 LINE_LED_GREEN + +/*===========================================================================*/ +/* Module pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +extern WDGConfig wdgcfg; + +#ifdef __cplusplus +extern "C" { +#endif + void portab_setup(void); +#ifdef __cplusplus +} +#endif + +/*===========================================================================*/ +/* Module inline functions. */ +/*===========================================================================*/ + +#endif /* PORTAB_H */ + +/** @} */ diff --git a/testhal/AT32/multi/WDT/cfg/at-start-f415/chconf.h b/testhal/AT32/multi/WDT/cfg/at-start-f415/chconf.h index 46b3f78b68..56fe06776a 100644 --- a/testhal/AT32/multi/WDT/cfg/at-start-f415/chconf.h +++ b/testhal/AT32/multi/WDT/cfg/at-start-f415/chconf.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/testhal/AT32/multi/WDT/cfg/at-start-f415/config.h b/testhal/AT32/multi/WDT/cfg/at-start-f415/config.h index 361e185d9c..056a8f39ff 100644 --- a/testhal/AT32/multi/WDT/cfg/at-start-f415/config.h +++ b/testhal/AT32/multi/WDT/cfg/at-start-f415/config.h @@ -1,6 +1,6 @@ /* - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/testhal/AT32/multi/WDT/cfg/at-start-f415/halconf.h b/testhal/AT32/multi/WDT/cfg/at-start-f415/halconf.h index f239389a49..87d87120f4 100644 --- a/testhal/AT32/multi/WDT/cfg/at-start-f415/halconf.h +++ b/testhal/AT32/multi/WDT/cfg/at-start-f415/halconf.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/testhal/AT32/multi/WDT/cfg/at-start-f415/halconf_community.h b/testhal/AT32/multi/WDT/cfg/at-start-f415/halconf_community.h index c43d668764..5a77290c71 100644 --- a/testhal/AT32/multi/WDT/cfg/at-start-f415/halconf_community.h +++ b/testhal/AT32/multi/WDT/cfg/at-start-f415/halconf_community.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/testhal/AT32/multi/WDT/cfg/at-start-f415/mcuconf.h b/testhal/AT32/multi/WDT/cfg/at-start-f415/mcuconf.h index 5c73470acf..98bb2511e2 100644 --- a/testhal/AT32/multi/WDT/cfg/at-start-f415/mcuconf.h +++ b/testhal/AT32/multi/WDT/cfg/at-start-f415/mcuconf.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -106,6 +106,7 @@ #define AT32_ADC_USE_ADC1 FALSE #define AT32_ADC_ADC1_DMA_PRIORITY 2 #define AT32_ADC_ADC1_IRQ_PRIORITY 6 +#define AT32_ADC_ADC1_DMA_IRQ_PRIORITY 6 /* * CAN driver system settings. diff --git a/testhal/AT32/multi/WDT/cfg/at-start-f415/portab.c b/testhal/AT32/multi/WDT/cfg/at-start-f415/portab.c index 1221b387b3..bd71ff0084 100644 --- a/testhal/AT32/multi/WDT/cfg/at-start-f415/portab.c +++ b/testhal/AT32/multi/WDT/cfg/at-start-f415/portab.c @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/testhal/AT32/multi/WDT/cfg/at-start-f415/portab.h b/testhal/AT32/multi/WDT/cfg/at-start-f415/portab.h index 4c14ffc774..f81dad3fbe 100644 --- a/testhal/AT32/multi/WDT/cfg/at-start-f415/portab.h +++ b/testhal/AT32/multi/WDT/cfg/at-start-f415/portab.h @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/testhal/AT32/multi/WDT/main.c b/testhal/AT32/multi/WDT/main.c index 45987c7ea4..125844742e 100644 --- a/testhal/AT32/multi/WDT/main.c +++ b/testhal/AT32/multi/WDT/main.c @@ -1,7 +1,7 @@ /* ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - ChibiOS - Copyright (C) 2023..2024 HorrorTroll - ChibiOS - Copyright (C) 2023..2024 Zhaqian + ChibiOS - Copyright (C) 2023..2025 HorrorTroll + ChibiOS - Copyright (C) 2023..2025 Zhaqian Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/testhal/AT32/multi/WDT/make/at-start-f402.make b/testhal/AT32/multi/WDT/make/at-start-f402.make new file mode 100644 index 0000000000..c2d5988d83 --- /dev/null +++ b/testhal/AT32/multi/WDT/make/at-start-f402.make @@ -0,0 +1,196 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO). +ifeq ($(USE_LTO),) + USE_LTO = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# Enable this if you want to use bitbang I2C. +ifeq ($(USE_HAL_I2C_FALLBACK),) + USE_HAL_I2C_FALLBACK = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x400 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU (no, softfp, hard). +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# FPU-related options. +ifeq ($(USE_FPU_OPT),) + USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16 +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, target, sources and paths +# + +# Define project name here +PROJECT = ch + +# Target settings. +MCU = cortex-m4 + +# Imported source files and paths. +CHIBIOS := ../../../../../ChibiOS +CHIBIOS_CONTRIB := ../../../.. +CONFDIR := ./cfg/at-start-f402 +BUILDDIR := ./build/at-start-f402 +DEPDIR := ./.dep/at-start-f402 + +# Licensing files. +include $(CHIBIOS)/os/license/license.mk +# Startup files. +include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_at32f402.mk +# HAL-OSAL files (optional). +include $(CHIBIOS_CONTRIB)/os/hal/hal.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/AT32F402_405/platform.mk +include $(CHIBIOS_CONTRIB)/os/hal/boards/AT_START_F402/board.mk +include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMv7-M/compilers/GCC/mk/port.mk +# Auto-build files in ./source recursively. +include $(CHIBIOS)/tools/mk/autobuild.mk +# Other files (optional). +#include $(CHIBIOS)/os/test/test.mk +#include $(CHIBIOS)/test/rt/rt_test.mk +#include $(CHIBIOS)/test/oslib/oslib_test.mk + +# Define linker script file here. +LDSCRIPT= $(STARTUPLD_CONTRIB)/AT32F402xC.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(ALLCSRC) \ + $(TESTSRC) \ + $(CONFDIR)/portab.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = $(ALLCPPSRC) + +# List ASM source files here. +ASMSRC = $(ALLASMSRC) + +# List ASM with preprocessor source files here. +ASMXSRC = $(ALLXASMSRC) + +# Inclusion directories. +INCDIR = $(CONFDIR) $(ALLINC) + +# Define C warning options here. +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes + +# Define C++ warning options here. +CPPWARN = -Wall -Wextra -Wundef + +# +# Project, target, sources and paths +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user section +############################################################################## + +############################################################################## +# Common rules +# + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk +include $(RULESPATH)/arm-none-eabi.mk +include $(RULESPATH)/rules.mk + +# +# Common rules +############################################################################## + +############################################################################## +# Custom rules +# + +# +# Custom rules +############################################################################## diff --git a/testhal/AT32/multi/WDT/make/at-start-f405.make b/testhal/AT32/multi/WDT/make/at-start-f405.make new file mode 100644 index 0000000000..d3cc3ac36c --- /dev/null +++ b/testhal/AT32/multi/WDT/make/at-start-f405.make @@ -0,0 +1,196 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO). +ifeq ($(USE_LTO),) + USE_LTO = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# Enable this if you want to use bitbang I2C. +ifeq ($(USE_HAL_I2C_FALLBACK),) + USE_HAL_I2C_FALLBACK = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x400 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU (no, softfp, hard). +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# FPU-related options. +ifeq ($(USE_FPU_OPT),) + USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16 +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, target, sources and paths +# + +# Define project name here +PROJECT = ch + +# Target settings. +MCU = cortex-m4 + +# Imported source files and paths. +CHIBIOS := ../../../../../ChibiOS +CHIBIOS_CONTRIB := ../../../.. +CONFDIR := ./cfg/at-start-f405 +BUILDDIR := ./build/at-start-f405 +DEPDIR := ./.dep/at-start-f405 + +# Licensing files. +include $(CHIBIOS)/os/license/license.mk +# Startup files. +include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_at32f405.mk +# HAL-OSAL files (optional). +include $(CHIBIOS_CONTRIB)/os/hal/hal.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/AT32/AT32F402_405/platform.mk +include $(CHIBIOS_CONTRIB)/os/hal/boards/AT_START_F405/board.mk +include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMv7-M/compilers/GCC/mk/port.mk +# Auto-build files in ./source recursively. +include $(CHIBIOS)/tools/mk/autobuild.mk +# Other files (optional). +#include $(CHIBIOS)/os/test/test.mk +#include $(CHIBIOS)/test/rt/rt_test.mk +#include $(CHIBIOS)/test/oslib/oslib_test.mk + +# Define linker script file here. +LDSCRIPT= $(STARTUPLD_CONTRIB)/AT32F405xC.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(ALLCSRC) \ + $(TESTSRC) \ + $(CONFDIR)/portab.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = $(ALLCPPSRC) + +# List ASM source files here. +ASMSRC = $(ALLASMSRC) + +# List ASM with preprocessor source files here. +ASMXSRC = $(ALLXASMSRC) + +# Inclusion directories. +INCDIR = $(CONFDIR) $(ALLINC) + +# Define C warning options here. +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes + +# Define C++ warning options here. +CPPWARN = -Wall -Wextra -Wundef + +# +# Project, target, sources and paths +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user section +############################################################################## + +############################################################################## +# Common rules +# + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk +include $(RULESPATH)/arm-none-eabi.mk +include $(RULESPATH)/rules.mk + +# +# Common rules +############################################################################## + +############################################################################## +# Custom rules +# + +# +# Custom rules +##############################################################################