diff --git a/os/hal/include/hal_fsmc.h b/os/hal/include/hal_fsmc.h
index 69b524718c..443e85e1fe 100644
--- a/os/hal/include/hal_fsmc.h
+++ b/os/hal/include/hal_fsmc.h
@@ -43,7 +43,7 @@
      defined(STM32F745xx) || defined(STM32F746xx) || \
      defined(STM32F756xx) || defined(STM32F767xx) || \
      defined(STM32F769xx) || defined(STM32F777xx) || \
-     defined(STM32F779xx))
+     defined(STM32F779xx) || defined(STM32H743xx))
   #if !defined(FSMC_Bank1_R_BASE)
   #define FSMC_Bank1_R_BASE               (FMC_R_BASE + 0x0000)
   #endif
@@ -89,7 +89,7 @@
 #define FSMC_Bank4_MAP_BASE               ((uint32_t) 0x90000000)
 #if (defined(STM32F427xx) || defined(STM32F437xx) || \
      defined(STM32F429xx) || defined(STM32F439xx) || \
-     defined(STM32F7))
+     defined(STM32F7) || defined(STM32H743xx))
   #define FSMC_Bank5_MAP_BASE             ((uint32_t) 0xC0000000)
   #define FSMC_Bank6_MAP_BASE             ((uint32_t) 0xD0000000)
 #endif
@@ -167,7 +167,7 @@ typedef struct {
 
 #if (defined(STM32F427xx) || defined(STM32F437xx) || \
      defined(STM32F429xx) || defined(STM32F439xx) || \
-     defined(STM32F7))
+     defined(STM32F7) || defined(STM32H743xx))
 
 typedef struct {
   __IO uint32_t SDCR1;              /**< SDRAM control register (bank 1) */
@@ -221,7 +221,7 @@ typedef struct {
 #define  FSMC_BCR_MWID_16         ((uint32_t)1 << 4)
 #if (defined(STM32F427xx) || defined(STM32F437xx) || \
      defined(STM32F429xx) || defined(STM32F439xx) || \
-     defined(STM32F7))
+     defined(STM32F7) || defined(STM32H743xx))
 #define  FSMC_BCR_MWID_32         ((uint32_t)2 << 4)
 #else
 #define  FSMC_BCR_MWID_RESERVED1  ((uint32_t)2 << 4)
@@ -239,7 +239,7 @@ typedef struct {
 #define  FSMC_BCR_CBURSTRW        ((uint32_t)1 << 19)
 #if (defined(STM32F427xx) || defined(STM32F437xx) || \
      defined(STM32F429xx) || defined(STM32F439xx) || \
-     defined(STM32F7))
+     defined(STM32F7) || defined(STM32H743xx))
 #define  FSMC_BCR_CCLKEN          ((uint32_t)1 << 20)
 #endif
 #if (defined(STM32F7))
@@ -330,7 +330,7 @@ struct FSMCDriver {
 
 #if (defined(STM32F427xx) || defined(STM32F437xx) || \
      defined(STM32F429xx) || defined(STM32F439xx) || \
-     defined(STM32F7))
+     defined(STM32F7) || defined(STM32H743xx))
   #if HAL_USE_SDRAM
   FSMC_SDRAM_TypeDef        *sdram;
   #endif
diff --git a/os/hal/ports/STM32/LLD/DMA2Dv1/hal_stm32_dma2d.c b/os/hal/ports/STM32/LLD/DMA2Dv1/hal_stm32_dma2d.c
index b7c9b49770..3fde4cc9e2 100644
--- a/os/hal/ports/STM32/LLD/DMA2Dv1/hal_stm32_dma2d.c
+++ b/os/hal/ports/STM32/LLD/DMA2Dv1/hal_stm32_dma2d.c
@@ -98,7 +98,11 @@ OSAL_IRQ_HANDLER(STM32_DMA2D_HANDLER) {
     if (dma2dp->config->cfgerr_isr != NULL)
       dma2dp->config->cfgerr_isr(dma2dp);
     job_done = true;
+#if defined(STM32H743xx)
+    DMA2D->IFCR |= DMA2D_IFCR_CCEIF;
+#else
     DMA2D->IFCR |= DMA2D_IFSR_CCEIF;
+#endif
   }
 
   /* Handle CLUT (Palette) Transfer Complete ISR.*/
@@ -106,7 +110,11 @@ OSAL_IRQ_HANDLER(STM32_DMA2D_HANDLER) {
     if (dma2dp->config->paltrfdone_isr != NULL)
       dma2dp->config->paltrfdone_isr(dma2dp);
     job_done = true;
+#if defined(STM32H743xx)
+    DMA2D->IFCR |= DMA2D_IFCR_CCTCIF;
+#else
     DMA2D->IFCR |= DMA2D_IFSR_CCTCIF;
+#endif
   }
 
   /* Handle CLUT (Palette) Access Error ISR.*/
@@ -114,14 +122,22 @@ OSAL_IRQ_HANDLER(STM32_DMA2D_HANDLER) {
     if (dma2dp->config->palacserr_isr != NULL)
       dma2dp->config->palacserr_isr(dma2dp);
     job_done = true;
+#if defined(STM32H743xx)
+    DMA2D->IFCR |= DMA2D_ISR_CAEIF;
+#else
     DMA2D->IFCR |= DMA2D_IFSR_CCAEIF;
+#endif
   }
 
   /* Handle Transfer Watermark ISR.*/
   if ((DMA2D->ISR & DMA2D_ISR_TWIF) && (DMA2D->CR & DMA2D_CR_TWIE)) {
     if (dma2dp->config->trfwmark_isr != NULL)
       dma2dp->config->trfwmark_isr(dma2dp);
+#if defined(STM32H743xx)
+    DMA2D->IFCR |= DMA2D_IFCR_CTWIF;
+#else
     DMA2D->IFCR |= DMA2D_IFSR_CTWIF;
+#endif
   }
 
   /* Handle Transfer Complete ISR.*/
@@ -129,7 +145,11 @@ OSAL_IRQ_HANDLER(STM32_DMA2D_HANDLER) {
     if (dma2dp->config->trfdone_isr != NULL)
       dma2dp->config->trfdone_isr(dma2dp);
     job_done = true;
+#if defined(STM32H743xx)
+    DMA2D->IFCR |= DMA2D_IFCR_CTCIF;
+#else
     DMA2D->IFCR |= DMA2D_IFSR_CTCIF;
+#endif
   }
 
   /* Handle Transfer Error ISR.*/
@@ -137,7 +157,11 @@ OSAL_IRQ_HANDLER(STM32_DMA2D_HANDLER) {
     if (dma2dp->config->trferr_isr != NULL)
       dma2dp->config->trferr_isr(dma2dp);
     job_done = true;
+#if defined(STM32H743xx)
+    DMA2D->IFCR |= DMA2D_IFCR_CTEIF;
+#else
     DMA2D->IFCR |= DMA2D_IFSR_CTEIF;
+#endif
   }
 
   if (job_done) {
diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_sdram_lld.c b/os/hal/ports/STM32/LLD/FSMCv1/hal_sdram_lld.c
index 0353bb39bb..8953061378 100644
--- a/os/hal/ports/STM32/LLD/FSMCv1/hal_sdram_lld.c
+++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_sdram_lld.c
@@ -32,7 +32,7 @@
      defined(STM32F745xx) || defined(STM32F746xx) || \
      defined(STM32F756xx) || defined(STM32F767xx) || \
      defined(STM32F769xx) || defined(STM32F777xx) || \
-     defined(STM32F779xx))
+     defined(STM32F779xx) || defined(STM32H743xx))
 
 #if (HAL_USE_SDRAM == TRUE) || defined(__DOXYGEN__)
 
@@ -78,10 +78,12 @@ SDRAMDriver SDRAMD1;
  *
  * @notapi
  */
+#if !defined(STM32H743xx) // H7xx has no busy flag
 static void sdram_lld_wait_ready(void) {
   /* Wait until the SDRAM controller is ready */
   while (SDRAMD1.sdram->SDSR & FMC_SDSR_BUSY);
 }
+#endif
 
 /**
  * @brief   Executes the SDRAM memory initialization sequence.
@@ -102,36 +104,50 @@ static void sdram_lld_init_sequence(const SDRAMConfig *cfgp) {
 #endif
 
   /* Step 3: Configure a clock configuration enable command.*/
+#if !defined(STM32H743xx)
   sdram_lld_wait_ready();
+#endif
   SDRAMD1.sdram->SDCMR = FMCCM_CLK_ENABLED | command_target;
 
   /* Step 4: Insert delay (tipically 100uS).*/
   osalSysPolledDelayX(OSAL_US2RTC(STM32_HCLK, 100));
 
   /* Step 5: Configure a PALL (precharge all) command.*/
+#if !defined(STM32H743xx)
   sdram_lld_wait_ready();
+#endif
   SDRAMD1.sdram->SDCMR = FMCCM_PALL | command_target;
 
   /* Step 6.1: Configure a Auto-Refresh command: send the first command.*/
+#if !defined(STM32H743xx)
   sdram_lld_wait_ready();
+#endif
   SDRAMD1.sdram->SDCMR = FMCCM_AUTO_REFRESH | command_target |
       (cfgp->sdcmr & FMC_SDCMR_NRFS);
 
   /* Step 6.2: Send the second command.*/
+#if !defined(STM32H743xx)
   sdram_lld_wait_ready();
+#endif;
   SDRAMD1.sdram->SDCMR = FMCCM_AUTO_REFRESH | command_target |
       (cfgp->sdcmr & FMC_SDCMR_NRFS);
 
   /* Step 7: Program the external memory mode register.*/
+#if !defined(STM32H743xx)
   sdram_lld_wait_ready();
+#endif
   SDRAMD1.sdram->SDCMR = FMCCM_LOAD_MODE | command_target |
       (cfgp->sdcmr & FMC_SDCMR_MRD);
 
   /* Step 8: Set clock.*/
+#if !defined(STM32H743xx)
   sdram_lld_wait_ready();
+#endif
   SDRAMD1.sdram->SDRTR = cfgp->sdrtr & FMC_SDRTR_COUNT;
 
+#if !defined(STM32H743xx)
   sdram_lld_wait_ready();
+#endif
 }
 
 /*===========================================================================*/
@@ -149,6 +165,10 @@ void sdram_lld_start(SDRAMDriver *sdramp, const SDRAMConfig *cfgp)
   sdramp->sdram->SDCR2 = cfgp->sdcr;
   sdramp->sdram->SDTR2 = cfgp->sdtr;
 
+#if defined(STM32H743xx)
+  FMC_Bank1_R->BTCR[0] |= FMC_BCR1_FMCEN;
+#endif
+
   sdram_lld_init_sequence(cfgp);
 }
 
diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_sdram_lld.h b/os/hal/ports/STM32/LLD/FSMCv1/hal_sdram_lld.h
index 665c570ce4..557f273e8d 100644
--- a/os/hal/ports/STM32/LLD/FSMCv1/hal_sdram_lld.h
+++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_sdram_lld.h
@@ -83,7 +83,7 @@
      defined(STM32F745xx) || defined(STM32F746xx) || \
      defined(STM32F756xx) || defined(STM32F767xx) || \
      defined(STM32F769xx) || defined(STM32F777xx) || \
-     defined(STM32F779xx))
+     defined(STM32F779xx) || defined(STM32H743xx))
 #else
 #error "Device is not compatible with SDRAM"
 #endif
diff --git a/os/hal/ports/STM32/LLD/LTDCv1/hal_stm32_ltdc.c b/os/hal/ports/STM32/LLD/LTDCv1/hal_stm32_ltdc.c
index bffa47292d..e179538395 100644
--- a/os/hal/ports/STM32/LLD/LTDCv1/hal_stm32_ltdc.c
+++ b/os/hal/ports/STM32/LLD/LTDCv1/hal_stm32_ltdc.c
@@ -233,7 +233,11 @@ void ltdcInit(void) {
   rccResetLTDC();
 
   /* Enable the LTDC clock.*/
+#if defined(STM32H743xx)
+  RCC->D1CFGR = (RCC->D1CFGR & ~(0x3U << 16U)) | (2 << 16);
+#else
   RCC->DCKCFGR = (RCC->DCKCFGR & ~RCC_DCKCFGR_PLLSAIDIVR) | (2 << 16); /* /8 */
+#endif
   rccEnableLTDC(false);
 
   /* Driver struct initialization.*/
@@ -765,7 +769,11 @@ bool ltdcIsDitheringEnabledI(LTDCDriver *ltdcp) {
   osalDbgCheck(ltdcp == &LTDCD1);
   (void)ltdcp;
 
+#if defined(STM32H743xx)
+  return (LTDC->GCR & LTDC_GCR_DEN) != 0;
+#else
   return (LTDC->GCR & LTDC_GCR_DTEN) != 0;
+#endif
 }
 
 /**
@@ -836,7 +844,11 @@ void ltdcDisableDitheringI(LTDCDriver *ltdcp) {
   osalDbgCheck(ltdcp == &LTDCD1);
   (void)ltdcp;
 
+#if defined(STM32H743xx)
+  LTDC->GCR &= ~LTDC_GCR_DEN;
+#else
   LTDC->GCR &= ~LTDC_GCR_DTEN;
+#endif
 }
 
 /**
diff --git a/os/hal/src/hal_fsmc.c b/os/hal/src/hal_fsmc.c
index c3f2a99fbb..cecba465da 100644
--- a/os/hal/src/hal_fsmc.c
+++ b/os/hal/src/hal_fsmc.c
@@ -105,7 +105,7 @@ void fsmcInit(void) {
      defined(STM32F745xx) || defined(STM32F746xx) || \
      defined(STM32F756xx) || defined(STM32F767xx) || \
      defined(STM32F769xx) || defined(STM32F777xx) || \
-     defined(STM32F779xx))
+     defined(STM32F779xx)  || defined(STM32H743xx))
   #if STM32_SDRAM_USE_SDRAM1 || STM32_SDRAM_USE_SDRAM2
     FSMCD1.sdram = (FSMC_SDRAM_TypeDef *)FSMC_Bank5_6_R_BASE;
   #endif