Multi-clock domain support #10
Description
Summary
Support designs with multiple clock domains, including independent clock periods and cross-domain timing analysis.
Current State
GEM assumes a single clock domain with one clock period. Real SoCs (like mcu_soc) may have multiple clocks (CPU clock, peripheral clock, external interfaces).
Proposed Approach
- Identify clock domains from design constraints or SDF
- Track per-domain clock period and phase
- Separate timing checks per domain
- Flag cross-domain paths (CDC) as special cases
- Consider: should CDC paths be checked or excluded from timing?
Impact
High — required for realistic SoC timing analysis.
Effort
High — architectural change to clock handling, constraint specification, and timing check logic.