Add parameters for memory map resource names (#5)

Author: robtaylor

amaranth_orchard/memory/hyperram.py

@@ -60,7 +60,7 @@ class HRAMConfig(csr.Register, access="w"):
 
     This core favors portability and ease of use over performance.
     """
-    def __init__(self, *, pins, init_latency=7):
+    def __init__(self, mem_name=("mem",), *, pins, init_latency=7):
         self.pins = pins
         self.cs_count = len(self.pins.csn_o)
         self.size = 2**23 * self.cs_count # 8MB per CS pin
@@ -76,7 +76,7 @@ def __init__(self, *, pins, init_latency=7):
         ctrl_memory_map = self._bridge.bus.memory_map
 
         data_memory_map = MemoryMap(addr_width=ceil_log2(self.size), data_width=8)
-        data_memory_map.add_resource(name=("mem",), size=self.size, resource=self)
+        data_memory_map.add_resource(name=mem_name, size=self.size, resource=self)
 
         super().__init__({
             "ctrl_bus": csr.Signature(addr_width=regs.addr_width, data_width=regs.data_width),

amaranth_orchard/memory/spimemio.py

@@ -56,7 +56,8 @@ def elaborate(self, platform):
     - ctrl_bus is the original 32-bit control register
     - data_bus is a bus peripheral that directly maps the 16MB of read-only flash memory.
     """
-    def __init__(self, *, flash):
+
+    def __init__(self, mem_name=("mem",), cfg_name=("cfg",), *, flash):
         self.flash = flash
         self.size  = 2**24
         size_words = (self.size * 8) // 32
@@ -68,11 +69,11 @@ def __init__(self, *, flash):
         })
 
         ctrl_memory_map = MemoryMap(addr_width=exact_log2(4), data_width=8)
-        ctrl_memory_map.add_resource(name=("cfg",), size=4, resource=self)
+        ctrl_memory_map.add_resource(name=cfg_name, size=4, resource=self)
         self.ctrl_bus.memory_map = ctrl_memory_map
 
         data_memory_map = MemoryMap(addr_width=exact_log2(self.size), data_width=8)
-        data_memory_map.add_resource(name=("mem",), size=self.size, resource=self)
+        data_memory_map.add_resource(name=mem_name, size=self.size, resource=self)
         self.data_bus.memory_map = data_memory_map
 
     def elaborate(self, platform):