wip

Author: robtaylor

amaranth_orchard/base/__init__.py

@@ -0,0 +1,2 @@
+from platform_timer import *
+from soc_id import *

amaranth_orchard/base/gpio.py

@@ -0,0 +1,2 @@
+from .gpio import *
+from .uart import *

amaranth_orchard/io/__init__.py

@@ -0,0 +1,92 @@
+from amaranth import Module, unsigned
+from amaranth.lib import wiring
+from amaranth.lib.wiring import In, Out, flipped, connect
+
+from amaranth_soc import csr, gpio
+
+from chipflow_lib.platforms import BidirPinSignature, PinSignature
+
+__all__ = ["GPIOPeripheral"]
+
+
+class GPIOPeripheral(wiring.Component):
+
+    class Signature(wiring.Signature):
+        def __init__(self, pin_count=1):
+            if pin_count > 32:
+                raise ValueError(f"Pin pin_count must be lesser than or equal to 32, not {pin_count}")
+            self._pin_count = pin_count
+            super().__init__({
+                "gpio": Out(BidirPinSignature(pin_count, all_have_oe=True))
+                })
+
+        @property
+        def pin_count(self):
+            return self._pin_count
+
+    """Wrapper for amaranth_soc gpio with chipflow_lib.PinSignature support
+
+    Parameters
+    ----------
+    pin_count : :class:`int`
+        Number of GPIO pins.
+    addr_width : :class:`int`
+        CSR bus address width. Defaults to ``4``.
+    data_width : :class:`int`
+        CSR bus data width. Defaults to ``4``.
+    input_stages : :class:`int`
+        Number of synchronization stages between pin inputs and the :class:`~Peripheral.Input`
+        register. Optional. Defaults to ``2``.
+
+    Attributes
+    ----------
+    bus : :class:`csr.Interface`
+        CSR bus interface providing access to registers.
+    pins : :class:`list` of :class:`wiring.PureInterface` of :class:`PinSignature`
+        GPIO pin interfaces.
+    alt_mode : :class:`Signal`
+        Indicates which members of the :attr:`Peripheral.pins` array are in alternate mode.
+
+    Raises
+    ------
+    :exc:`TypeError`
+        If ``pin_count`` is not a positive integer.
+    :exc:`TypeError`
+        If ``input_stages`` is not a non-negative integer.
+    """
+
+    def __init__(self, *, pin_count, addr_width=4, data_width=4, input_stages=2):
+        self._gpio = gpio.Peripheral(pin_count=pin_count,
+                                     addr_width=addr_width,
+                                     data_width=data_width,
+                                     input_stages=input_stages)
+
+        super().__init__({
+            "bus": In(csr.Signature(addr_width=addr_width, data_width=data_width)),
+            "pins": Out(self.Signature(pin_count)),
+            "alt_mode": Out(unsigned(pin_count)),
+        })
+        self.bus.qmemory_map = self._gpio.bus.memory_map
+
+    def elaborate(self, platform):
+        m = Module()
+        m.submodules._gpio = self._gpio
+
+        connect(m, flipped(self.bus), self._gpio.bus)
+        for i in range(self._gpio.pin_count):
+            # m.d.comb += self.pins.gpio.i[i].eq(self._gpio.pins[i].i)
+            # m.d.comb += self._gpio.pins[i].o.eq(self.pins.gpio.o[i])
+            # m.d.comb += self._gpio.pins[i].oe.eq(self.pins.gpio.oe[i])
+            m.d.comb += self._gpio.pins[i].i.eq(self.pins.gpio.i[i])
+            m.d.comb += self.pins.gpio.o[i].eq(self._gpio.pins[i].o)
+            m.d.comb += self.pins.gpio.oe[i].eq(self._gpio.pins[i].oe)
+
+        return m
+
+    @property
+    def pin_count(self):
+        return self._gpio.pin_count
+
+    @property
+    def input_stages(self):
+        return self._gpio.input_stages

amaranth_orchard/io/gpio.py

@@ -1,13 +1,14 @@
 from amaranth import Module
 from amaranth.sim import Simulator
-from amaranth_orchard.memory import HyperRAM, HyperRAMPins
+from amaranth_orchard.memory import HyperRAM
+
 
 def test_hyperram_smoke():
-    pins = HyperRAMPins(cs_count=1)
     m = Module()
-    m.submodules.hram = hram = HyperRAM(pins=pins)
+    m.submodules.hram = hram = HyperRAM()
     sim = Simulator(m)
     sim.add_clock(1e-6)
+
     def process():
         yield hram.data_bus.adr.eq(0x5A5A5A)
         yield hram.data_bus.dat_w.eq(0xF0F0F0F0)
@@ -25,8 +26,8 @@ def process():
         yield hram.data_bus.we.eq(0)
         yield hram.data_bus.stb.eq(1)
         yield hram.data_bus.cyc.eq(1)
-        yield pins.rwds.i.eq(1)
-        yield pins.dq.i.eq(0xFF)
+        yield hram.pins.rwds.i.eq(1)
+        yield hram.pins.dq.i.eq(0xFF)
         for i in range(100):
             if (yield hram.data_bus.ack):
                 yield hram.data_bus.stb.eq(0)