Remove all passing of pins to constructor

Author: robtaylor

amaranth_orchard/base/gpio.py

@@ -9,7 +9,7 @@
 __all__ = ["GPIOPins", "GPIOPeripheral"]
 
 
-class GPIOPins(wiring.PureInterface):
+class GPIOPeripheral(wiring.Component):
     class Signature(wiring.Signature):
         def __init__(self, width):
             if width > 32:
@@ -23,40 +23,30 @@ def __init__(self, width):
         def width(self):
             return self._width
 
-        def create(self, *, path=(), src_loc_at=0):
-            return GPIOPins(width=self.width, path=path, src_loc_at=1 + src_loc_at)
-
-    def __init__(self, width, *, path=(), src_loc_at=0):
-        super().__init__(self.Signature(width), path=path, src_loc_at=1 + src_loc_at)
-
-    @property
-    def width(self):
-        return self.signature.width
-
-
-class GPIOPeripheral(wiring.Component):
     class DO(csr.Register, access="rw"):
         """output data (R/W, ignored for pins configured as inputs)"""
+
         def __init__(self, width):
             super().__init__({"pins": csr.Field(csr.action.RW, unsigned(width))})
 
     class OE(csr.Register, access="rw"):
         """output enable (R/W) 1=output, 0=input"""
+
         def __init__(self, width):
             super().__init__({"pins": csr.Field(csr.action.RW, unsigned(width))})
 
     class DI(csr.Register, access="r"):
         """input data (R)"""
+
         def __init__(self, width):
             super().__init__({"pins": csr.Field(csr.action.R, unsigned(width))})
 
-    def __init__(self, *, pins: GPIOPins):
+    def __init__(self, *, width: int):
         """Simple GPIO peripheral.
 
         All pins default to input at power up.
         """
-        self.width = pins.width
-        self.pins = pins
+        self.width = width
 
         regs = csr.Builder(addr_width=4, data_width=8)
 
@@ -68,6 +58,7 @@ def __init__(self, *, pins: GPIOPins):
 
         super().__init__({
             "bus": In(csr.Signature(addr_width=regs.addr_width, data_width=regs.data_width)),
+            "pins": Out(self.Signature(width))
         })
         self.bus.memory_map = self._bridge.bus.memory_map
 

amaranth_orchard/io/uart.py

@@ -8,25 +8,20 @@
 from chipflow_lib.platforms import OutputPinSignature, InputPinSignature
 
 
-__all__ = ["UARTPins", "UARTPeripheral"]
+__all__ = ["UARTPeripheral"]
 
 
-class UARTPins(wiring.PureInterface):
+class UARTPeripheral(wiring.Component):
     class Signature(wiring.Signature):
         def __init__(self):
             super().__init__({
                 "tx": Out(OutputPinSignature(1)),
                 "rx": Out(InputPinSignature(1)),
             })
 
-        def create(self, *, path=(), src_loc_at=0):
-            return UARTPins(path=path, src_loc_at=1 + src_loc_at)
-
     def __init__(self, *, path=(), src_loc_at=0):
         super().__init__(self.Signature(), path=path, src_loc_at=1 + src_loc_at)
 
-
-class UARTPeripheral(wiring.Component):
     class TxData(csr.Register, access="w"):
         """valid to write to when tx_rdy is 1, will trigger a transmit"""
         val: csr.Field(csr.action.W, unsigned(8))
@@ -55,22 +50,22 @@ def __init__(self, init_divisor):
 
     TODO: Interrupts support, perhaps mimic something with upstream Linux kernel support...
     """
-    def __init__(self, *, init_divisor, pins):
+    def __init__(self, *, init_divisor):
         self.init_divisor = init_divisor
-        self.pins = pins
 
         regs = csr.Builder(addr_width=5, data_width=8)
 
-        self._tx_data  = regs.add("tx_data",  self.TxData(),  offset=0x00)
-        self._rx_data  = regs.add("rx_data",  self.RxData(),  offset=0x04)
-        self._tx_rdy   = regs.add("tx_rdy",   self.TxReady(), offset=0x08)
+        self._tx_data = regs.add("tx_data",  self.TxData(),  offset=0x00)
+        self._rx_data = regs.add("rx_data",  self.RxData(),  offset=0x04)
+        self._tx_rdy = regs.add("tx_rdy",   self.TxReady(), offset=0x08)
         self._rx_avail = regs.add("rx_avail", self.RxAvail(), offset=0x0c)
-        self._divisor  = regs.add("divisor",  self.Divisor(init_divisor), offset=0x10)
+        self._divisor = regs.add("divisor",  self.Divisor(init_divisor), offset=0x10)
 
         self._bridge = csr.Bridge(regs.as_memory_map())
 
         super().__init__({
             "bus": In(csr.Signature(addr_width=regs.addr_width, data_width=regs.data_width)),
+            "pins": Out(self.Signature()),
         })
         self.bus.memory_map = self._bridge.bus.memory_map
 

amaranth_orchard/memory/hyperram.py

@@ -5,22 +5,20 @@
 # Copyright (c) 2021-2022 gatecat <[email protected]>
 # SPDX-License-Identifier: BSD-2-Clause
 
-from amaranth import *
+from amaranth import Module, ClockSignal, ResetSignal, Signal, unsigned, ClockDomain
 from amaranth.lib import wiring
 from amaranth.lib.wiring import In, Out, connect, flipped
 from amaranth.utils import ceil_log2
 
-from amaranth.sim import Simulator
-
 from amaranth_soc import csr, wishbone
 from amaranth_soc.memory import MemoryMap
 
 from chipflow_lib.platforms import BidirPinSignature, OutputPinSignature
 
-__all__ = ["HyperRAMPins", "HyperRAM"]
+__all__ = ["HyperRAM"]
 
 
-class HyperRAMPins(wiring.PureInterface):
+class HyperRAM(wiring.Component):
     class Signature(wiring.Signature):
         def __init__(self, *, cs_count=1):
             super().__init__({
@@ -31,15 +29,6 @@ def __init__(self, *, cs_count=1):
                 "dq": Out(BidirPinSignature(8)),
             })
 
-        def create(self, *, path=(), src_loc_at=0):
-            return HyperRAMPins(cs_count=self.cs_count, src_loc_at=1 + src_loc_at)
-
-    def __init__(self, *, cs_count=1, path=(), src_loc_at=0):
-        super().__init__(self.Signature(cs_count=cs_count), path=path, src_loc_at=1 + src_loc_at)
-        self.cs_count = cs_count
-
-
-class HyperRAM(wiring.Component):
     class CtrlConfig(csr.Register, access="rw"):
         def __init__(self, init_latency):
             super().__init__({
@@ -79,6 +68,7 @@ def __init__(self, mem_name=("mem",), *, pins, init_latency=7):
             "ctrl_bus": In(csr.Signature(addr_width=regs.addr_width, data_width=regs.data_width)),
             "data_bus": In(wishbone.Signature(addr_width=ceil_log2(self.size >> 2), data_width=32,
                            granularity=8)),
+            "pins": Out(self.Signature()),
         })
         self.ctrl_bus.memory_map = ctrl_memory_map
         self.data_bus.memory_map = data_memory_map
@@ -142,32 +132,32 @@ def elaborate(self, platform):
                         self.pins.dq.oe.eq(1),
                         counter.eq(6),
                         # Assign CA
-                        sr[47].eq(~self.data_bus.we), # R/W#
-                        sr[46].eq(0), # memory space
-                        sr[45].eq(1), # linear burst
-                        sr[16:45].eq(self.data_bus.adr[2:21]), # upper address
-                        sr[4:16].eq(0), # RFU
-                        sr[1:3].eq(self.data_bus.adr[0:2]), # lower address
-                        sr[0].eq(0), # address LSB (0 for 32-bit xfers)
+                        sr[47].eq(~self.data_bus.we),           # R/W#
+                        sr[46].eq(0),                           # memory space
+                        sr[45].eq(1),                           # linear burst
+                        sr[16:45].eq(self.data_bus.adr[2:21]),  # upper address
+                        sr[4:16].eq(0),                         # RFU
+                        sr[1:3].eq(self.data_bus.adr[0:2]),     # lower address
+                        sr[0].eq(0),                            # address LSB (0 for 32-bit xfers)
                         latched_adr.eq(self.data_bus.adr),
                         latched_we.eq(self.data_bus.we),
                         is_ctrl_write.eq(0),
                     ]
                     m.next = "WAIT_CA"
-                with m.If(self._hram_cfg.f.val.w_stb): # config register write
+                with m.If(self._hram_cfg.f.val.w_stb):  # config register write
                     m.d.sync += [
                         csn.eq(~(1 << (self._hram_cfg.f.val.w_data[16:16+ceil_log2(self.cs_count)]))),
                         self.pins.dq.oe.eq(1),
                         counter.eq(6),
                         # Assign CA
-                        sr[47].eq(0), # R/W#
-                        sr[46].eq(1), # memory space
-                        sr[45].eq(1), # linear burst
-                        sr[24:45].eq(1), # upper address
-                        sr[16:24].eq(0), # 
-                        sr[4:16].eq(0), # RFU
-                        sr[1:3].eq(0), # lower address
-                        sr[0].eq(0), # address LSB (0 for 32-bit xfers)
+                        sr[47].eq(0),      # R/W#
+                        sr[46].eq(1),      # memory space
+                        sr[45].eq(1),      # linear burst
+                        sr[24:45].eq(1),   # upper address
+                        sr[16:24].eq(0),   #
+                        sr[4:16].eq(0),    # RFU
+                        sr[1:3].eq(0),     # lower address
+                        sr[0].eq(0),       # address LSB (0 for 32-bit xfers)
                         latched_cfg.eq(self._hram_cfg.f.val.w_data[0:16]),
                         is_ctrl_write.eq(1),
                     ]
@@ -260,51 +250,3 @@ def elaborate(self, platform):
                 ]
                 m.next = "IDLE"
         return m
-
-def sim():
-    pins = HyperRAMPins(cs_count=1)
-    m = Module()
-    m.submodules.hram = hram = HyperRAM(pins=pins)
-    sim = Simulator(m)
-    sim.add_clock(1e-6)
-    def process():
-        yield hram.data_bus.adr.eq(0x5A5A5A)
-        yield hram.data_bus.dat_w.eq(0xF0F0F0F0)
-        yield hram.data_bus.sel.eq(1)
-        yield hram.data_bus.we.eq(1)
-        yield hram.data_bus.stb.eq(1)
-        yield hram.data_bus.cyc.eq(1)
-        for i in range(100):
-            if (yield hram.data_bus.ack):
-                yield hram.data_bus.stb.eq(0)
-                yield hram.data_bus.cyc.eq(0)
-            yield
-        yield hram.data_bus.adr.eq(0x5A5A5A)
-        yield hram.data_bus.sel.eq(1)
-        yield hram.data_bus.we.eq(0)
-        yield hram.data_bus.stb.eq(1)
-        yield hram.data_bus.cyc.eq(1)
-        yield pins.rwds.i.eq(1)
-        yield pins.dq.i.eq(0xFF)
-        for i in range(100):
-            if (yield hram.data_bus.ack):
-                yield hram.data_bus.stb.eq(0)
-                yield hram.data_bus.cyc.eq(0)
-            yield
-        yield hram.ctrl_bus.adr.eq(1)
-        yield hram.ctrl_bus.dat_w.eq(0x55AA)
-        yield hram.ctrl_bus.sel.eq(0xF)
-        yield hram.ctrl_bus.we.eq(1)
-        yield hram.ctrl_bus.stb.eq(1)
-        yield hram.ctrl_bus.cyc.eq(1)
-        for i in range(100):
-            if (yield hram.ctrl_bus.ack):
-                yield hram.ctrl_bus.stb.eq(0)
-                yield hram.ctrl_bus.cyc.eq(0)
-            yield
-    sim.add_sync_process(process)
-    with sim.write_vcd("hyperram.vcd", "hyperram.gtkw"):
-        sim.run()
-
-if __name__ == '__main__':
-    sim()

amaranth_orchard/memory/spimemio.py

@@ -9,10 +9,10 @@
 from amaranth_soc.memory import MemoryMap
 from chipflow_lib.platforms import BidirPinSignature,OutputPinSignature
 
-__all__ = ["QSPIPins", "SPIMemIO"]
+__all__ = ["SPIMemIO"]
 
 
-class QSPIPins(wiring.PureInterface):
+class SPIMemIO(wiring.Component):
     class Signature(wiring.Signature):
         def __init__(self):
             super().__init__({
@@ -21,14 +21,6 @@ def __init__(self):
                 "d": Out(BidirPinSignature(4, all_have_oe=True)),
             })
 
-        def create(self, *, path=(), src_loc_at=0):
-            return QSPIPins(path=path, src_loc_at=1 + src_loc_at)
-
-    def __init__(self, *, path=(), src_loc_at=0):
-        super().__init__(self.Signature(), path=path, src_loc_at=1 + src_loc_at)
-
-
-class SPIMemIO(wiring.Component):
     class _ControlBridge(wiring.Component):
         bus: In(csr.Signature(addr_width=exact_log2(4), data_width=8))
         cfgreg_we: Out(unsigned(4))
@@ -56,12 +48,12 @@ def elaborate(self, platform):
     - data_bus is a bus peripheral that directly maps the 16MB of read-only flash memory.
     """
 
-    def __init__(self, mem_name=("mem",), cfg_name=("cfg",), *):
+    def __init__(self, *,  mem_name=("mem",), cfg_name=("cfg",)):
         self.size  = 2**24
         size_words = (self.size * 8) // 32
 
         super().__init__({
-            "qspi": Out(QSPIPins.Signature()),
+            "pins": Out(QSPIPins.Signature()),
             "ctrl_bus": In(csr.Signature(addr_width=exact_log2(4), data_width=8)),
             "data_bus": In(wishbone.Signature(addr_width=exact_log2(size_words), data_width=32,
                                               granularity=8)),
@@ -89,19 +81,19 @@ def elaborate(self, platform):
             "i_resetn": ~ResetSignal(),
             "i_valid": self.data_bus.cyc & self.data_bus.stb,
             "o_ready": spi_ready,
-            "i_addr": Cat(Const(0, 2), self.data_bus.adr), # Hack to force a 1MB offset
+            "i_addr": Cat(Const(0, 2), self.data_bus.adr),  # Hack to force a 1MB offset
             "o_rdata": self.data_bus.dat_r,
-            "o_flash_csb": self.qspi.csn.o,
-            "o_flash_clk": self.qspi.clk.o,
+            "o_flash_csb": self.pins.csn.o,
+            "o_flash_clk": self.pins.clk.o,
             "i_cfgreg_we": ctrl_bridge.cfgreg_we,
             "i_cfgreg_di": ctrl_bridge.cfgreg_di,
             "o_cfgreg_do": ctrl_bridge.cfgreg_do,
         } | {
-            f"o_flash_io{n}_oe": self.qspi.d.oe[n] for n in range(4)
+            f"o_flash_io{n}_oe": self.pins.d.oe[n] for n in range(4)
         } | {
-            f"o_flash_io{n}_do": self.qspi.d.o[n] for n in range(4)
+            f"o_flash_io{n}_do": self.pins.d.o[n] for n in range(4)
         } | {
-            f"i_flash_io{n}_di": self.qspi.d.i[n] for n in range(4)
+            f"i_flash_io{n}_di": self.pins.d.i[n] for n in range(4)
         }
 
         m.submodules.spimemio = Instance("spimemio", **verilog_map)