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Use PinSignature for port wiring
1 parent c54c5f7 commit 23da273

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5 files changed

+34
-35
lines changed

5 files changed

+34
-35
lines changed

‎amaranth_orchard/base/gpio.py‎

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -4,6 +4,7 @@
44

55
from amaranth_soc import csr
66

7+
from chipflow_lib.platforms import BidirPinSignature
78

89
__all__ = ["GPIOPins", "GPIOPeripheral"]
910

@@ -13,9 +14,7 @@ class Signature(wiring.Signature):
1314
def __init__(self, width):
1415
self._width = width
1516
super().__init__({
16-
"o": Out(unsigned(width)),
17-
"oe": Out(unsigned(width)),
18-
"i": In(unsigned(width)),
17+
"o": Out(BidirPinSignature(width)),
1918
})
2019

2120
@property

‎amaranth_orchard/io/uart.py‎

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -5,6 +5,8 @@
55
from amaranth_soc import csr
66
from amaranth_stdio.serial import AsyncSerialRX, AsyncSerialTX
77

8+
from chipflow_lib.platforms import BidirPinSignature, OutputPinSignature, InputPinSignature
9+
810

911
__all__ = ["UARTPins", "UARTPeripheral"]
1012

@@ -13,8 +15,8 @@ class UARTPins(wiring.PureInterface):
1315
class Signature(wiring.Signature):
1416
def __init__(self):
1517
super().__init__({
16-
"tx_o": Out(1),
17-
"rx_i": In(1),
18+
"tx": Out(OutputPinSignature(1)),
19+
"rx": In(InputPinSignature(1)),
1820
})
1921

2022
def create(self, *, path=(), src_loc_at=0):
@@ -80,7 +82,7 @@ def elaborate(self, platform):
8082

8183
m.submodules.tx = tx = AsyncSerialTX(divisor=self.init_divisor, divisor_bits=24)
8284
m.d.comb += [
83-
self.pins.tx_o.eq(tx.o),
85+
self.pins.tx.o.eq(tx.o),
8486
tx.data.eq(self._tx_data.f.val.w_data),
8587
tx.ack.eq(self._tx_data.f.val.w_stb),
8688
self._tx_rdy.f.val.r_data.eq(tx.rdy),
@@ -102,7 +104,7 @@ def elaborate(self, platform):
102104
]
103105

104106
m.d.comb += [
105-
rx.i.eq(self.pins.rx_i),
107+
rx.i.eq(self.pins.rx.i),
106108
rx.ack.eq(~rx_avail),
107109
rx.divisor.eq(self._divisor.f.val.data),
108110
self._rx_data.f.val.r_data.eq(rx_buf),

‎amaranth_orchard/memory/hyperram.py‎

Lines changed: 6 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,7 @@
1515
from amaranth_soc import csr, wishbone
1616
from amaranth_soc.memory import MemoryMap
1717

18+
from chipflow_lib.platforms import BidirPinSignature, OutputPinSignature
1819

1920
__all__ = ["HyperRAMPins", "HyperRAM"]
2021

@@ -24,15 +25,11 @@ class Signature(wiring.Signature):
2425
def __init__(self, *, cs_count=1):
2526
self.cs_count = cs_count
2627
super().__init__({
27-
"clk_o": Out(1),
28-
"csn_o": Out(cs_count),
29-
"rstn_o": Out(1),
30-
"rwds_o": Out(1),
31-
"rwds_oe": Out(1),
32-
"rwds_i": In(1),
33-
"dq_o": Out(8),
34-
"dq_oe": Out(8),
35-
"dq_i": In(8),
28+
"clk": Out(OutputPinSignature(1)),
29+
"csn": Out(OutputPinSignature(cs_count)),
30+
"rstn": Out(OutputPinSignature(1)),
31+
"rwds": Out(BidirPinSignature(1)),
32+
"dq": Out(BidirPinSignature(1)),
3633
})
3734

3835
def create(self, *, path=(), src_loc_at=0):

‎amaranth_orchard/memory/spimemio.py‎

Lines changed: 18 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,7 @@
77

88
from amaranth_soc import csr, wishbone
99
from amaranth_soc.memory import MemoryMap
10+
from chipflow_lib.platforms import BidirPinSignature,OutputPinSignature
1011

1112
__all__ = ["QSPIPins", "SPIMemIO"]
1213

@@ -15,11 +16,9 @@ class QSPIPins(wiring.PureInterface):
1516
class Signature(wiring.Signature):
1617
def __init__(self):
1718
super().__init__({
18-
"clk_o": Out(1),
19-
"csn_o": Out(1),
20-
"d_o": Out(4),
21-
"d_oe": Out(4),
22-
"d_i": In(4),
19+
"clk": Out(OutputPinSignature(1)),
20+
"csn": Out(OutputPinSignature(1)),
21+
"d": Out(BidirPinSignature(4)),
2322
})
2423

2524
def create(self, *, path=(), src_loc_at=0):
@@ -92,20 +91,20 @@ def elaborate(self, platform):
9291
o_ready=spi_ready,
9392
i_addr=Cat(Const(0, 2), self.data_bus.adr), # Hack to force a 1MB offset
9493
o_rdata=self.data_bus.dat_r,
95-
o_flash_csb=self.flash.csn_o,
96-
o_flash_clk=self.flash.clk_o,
97-
o_flash_io0_oe=self.flash.d_oe[0],
98-
o_flash_io1_oe=self.flash.d_oe[1],
99-
o_flash_io2_oe=self.flash.d_oe[2],
100-
o_flash_io3_oe=self.flash.d_oe[3],
101-
o_flash_io0_do=self.flash.d_o[0],
102-
o_flash_io1_do=self.flash.d_o[1],
103-
o_flash_io2_do=self.flash.d_o[2],
104-
o_flash_io3_do=self.flash.d_o[3],
105-
i_flash_io0_di=self.flash.d_i[0],
106-
i_flash_io1_di=self.flash.d_i[1],
107-
i_flash_io2_di=self.flash.d_i[2],
108-
i_flash_io3_di=self.flash.d_i[3],
94+
o_flash_csb=self.flash.csn.o,
95+
o_flash_clk=self.flash.clk.o,
96+
o_flash_io0_oe=self.flash.d.oe[0],
97+
o_flash_io1_oe=self.flash.d.oe[1],
98+
o_flash_io2_oe=self.flash.d.oe[2],
99+
o_flash_io3_oe=self.flash.d.oe[3],
100+
o_flash_io0_do=self.flash.d.o[0],
101+
o_flash_io1_do=self.flash.d.o[1],
102+
o_flash_io2_do=self.flash.d.o[2],
103+
o_flash_io3_do=self.flash.d.o[3],
104+
i_flash_io0_di=self.flash.d.i[0],
105+
i_flash_io1_di=self.flash.d.i[1],
106+
i_flash_io2_di=self.flash.d.i[2],
107+
i_flash_io3_di=self.flash.d.i[3],
109108
i_cfgreg_we=ctrl_bridge.cfgreg_we,
110109
i_cfgreg_di=ctrl_bridge.cfgreg_di,
111110
o_cfgreg_do=ctrl_bridge.cfgreg_do,

‎pyproject.toml‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -16,6 +16,8 @@ license = {file = "LICENSE.txt"}
1616
requires-python = "~=3.8"
1717
dependencies = [
1818
"amaranth>=0.5,<0.6",
19+
"chipflow-lib",
20+
"amaranth-soc"
1921
]
2022

2123
# Build system configuration

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