version of GPTimer without excessive autoformatting (#32)

Author: ta10g22

chipflow_digital_ip/base/__init__.py

@@ -1,4 +1,5 @@
 from ._platform_timer import PlatformTimer
 from ._soc_id import SoCID
+from .gptimer import GPTimer
 
-__all__ = ['PlatformTimer', 'SoCID']
+__all__ = ['PlatformTimer', 'SoCID', 'GPTimer']

chipflow_digital_ip/base/gptimer.py

@@ -0,0 +1,122 @@
+from amaranth import Module, Signal, unsigned
+from amaranth.lib.wiring import Component, In, Out, connect, flipped
+
+from amaranth_soc import csr
+
+"""
+General-Purpose Timer:
+ - 32-bit up-counter
+ - 8-bit prescaler
+ - compare match + auto-reload
+ - level-high IRQ on match
+"""
+
+
+__all__ = ["GPTimer"]
+
+
+class GPTimer(Component):
+    class Ctrl(csr.Register, access="rw"):
+        """CTRL: [0]=EN, [1]=RST, [2]=AR, [3]=IRQ_EN
+        EN = Enables the counter
+        RST = Resets the counter
+        AR = Enable auto reload
+        IRQ_EN = Enable interrupt on match
+        """
+
+        en: csr.Field(csr.action.RW, unsigned(1))
+        rst: csr.Field(csr.action.RW, unsigned(1))
+        ar: csr.Field(csr.action.RW, unsigned(1))
+        irq_en: csr.Field(csr.action.RW, unsigned(1))
+        # bits [4:8) reserved
+
+    class Presc(csr.Register, access="rw"):
+        """Prescaler divisor (0 => /1, 255 => /256)"""
+
+        val: csr.Field(csr.action.RW, unsigned(8))
+
+    class Compare(csr.Register, access="rw"):
+        """32-bit compare value"""
+
+        val: csr.Field(csr.action.RW, unsigned(32))
+
+    class Count(csr.Register, access="r"):
+        """32-bit free-running counter (read-only)"""
+
+        val: csr.Field(csr.action.R, unsigned(32))
+
+    class Status(csr.Register, access="rw"):
+        """STATUS: [0]=MATCH (W1C)"""
+
+        match: csr.Field(csr.action.RW1C, unsigned(1))
+        # bits [1:8) reserved
+
+    def __init__(self):
+        # CSR bank: 5-bit address, 8-bit data bus
+        regs = csr.Builder(addr_width=5, data_width=8)
+        self._ctrl = regs.add("ctrl", self.Ctrl(), offset=0x00)
+        self._presc = regs.add("presc", self.Presc(), offset=0x04)
+        self._count = regs.add("count", self.Count(), offset=0x08)
+        self._compare = regs.add("compare", self.Compare(), offset=0x0C)
+        self._status = regs.add("status", self.Status(), offset=0x10)
+
+        self._bridge = csr.Bridge(regs.as_memory_map())
+
+        super().__init__(
+            {
+                "bus": In(
+                    csr.Signature(
+                        addr_width=regs.addr_width, data_width=regs.data_width
+                    )
+                ),
+                "irq": Out(1),
+            }
+        )
+        self.bus.memory_map = self._bridge.bus.memory_map
+
+    def elaborate(self, platform):
+        m = Module()
+        m.submodules.bridge = self._bridge
+        connect(m, flipped(self.bus), self._bridge.bus)
+
+        # shorthands to the field-ports
+        ctrl = self._ctrl.f
+        presc = self._presc.f
+        cmp_ = self._compare.f
+        cnt = self._count.f
+        status = self._status.f
+
+        # Internal timer signals:
+        p_cnt = Signal(8, name="prescaler_cnt")
+        cnt_r = Signal(32, name="counter")
+        mflag = Signal(1, name="match_pulse")
+
+        # prescaler & counter logic
+        with m.If(ctrl.rst.data):
+            m.d.sync += [p_cnt.eq(0), cnt_r.eq(0), mflag.eq(0)]
+        with m.Elif(ctrl.en.data):
+            with m.If(p_cnt == presc.val.data):
+                m.d.sync += [p_cnt.eq(0), cnt_r.eq(cnt_r + 1)]
+            with m.Else():
+                m.d.sync += p_cnt.eq(p_cnt + 1)
+
+        # default no pulse match
+        m.d.sync += mflag.eq(0)
+
+        # compare & auto-reload, set match-flag
+        with m.If((cnt_r == cmp_.val.data) & ctrl.en.data):
+            m.d.sync += mflag.eq(1)
+            with m.If(
+                ctrl.ar.data
+            ):  # if  auto reload isn't enabled the counter keeps incrementing after hitting the compare match value
+                m.d.sync += cnt_r.eq(0)
+
+        m.d.comb += status.match.set.eq(
+            mflag
+        )  # drive the RW1C “set” port from that pulse
+        m.d.comb += cnt.val.r_data.eq(cnt_r)  # mirror into COUNT CSR
+        m.d.comb += self.irq.eq(
+            status.match.data & ctrl.irq_en.data
+        )  # irq follows the *CSR storage
+
+        return m

tests/test_gptimer.py

@@ -0,0 +1,115 @@
+# amaranth: UnusedElaboratable=no
+
+# SPDX-License-Identifier: BSD-2-Clause
+
+from amaranth import *
+from amaranth.sim import Simulator
+from chipflow_digital_ip.base import GPTimer
+import unittest
+
+
+class _GPTimerHarness(Elaboratable):
+    def __init__(self):
+        self.timer = GPTimer()
+
+    def elaborate(self, platform):
+        m = Module()
+        m.submodules.timer = self.timer
+        return m
+
+
+class TestGPTimer(unittest.TestCase):
+    # CSR register offsets:
+    REG_CTRL = 0x00
+    REG_PRESC = 0x04
+    REG_COUNT = 0x08
+    REG_COMPARE = 0x0C
+    REG_STATUS = 0x10
+
+    async def _write_reg(self, ctx, bus, addr, value, width=1):  # width in bytes
+        for i in range(width):
+            ctx.set(bus.addr, addr + i)  # addr to write to
+            ctx.set(bus.w_data, (value >> (8 * i)) & 0xFF)  # exact byte value to write
+            ctx.set(bus.w_stb, 1)  # write strobe (write data on bus)
+            await ctx.tick()  # on the next clock edge
+
+        ctx.set(bus.w_stb, 0)  # done, you can stop writing
+        await ctx.tick()  # on the next edge
+
+    async def _read_reg(self, ctx, bus, addr, width=1):
+        result = 0
+        for i in range(width):
+            ctx.set(bus.addr, addr + i)  # set the bus to this address
+            ctx.set(bus.r_stb, 1)  # read from bus
+            await ctx.tick()  # on the next clock edge
+            result |= ctx.get(bus.r_data) << (8 * i)  # use bitwise or to assemble read
+        ctx.set(bus.r_stb, 0)
+        await ctx.tick()
+        return result
+
+    def test_prescaler_and_count(self):
+        """Counter should increment once per (PRESC+1) cycles."""
+        dut = _GPTimerHarness()
+
+        async def testbench(ctx):
+            bus = dut.timer.bus
+
+            # prescaler = 2 → increment every 3 cycles & enable timer
+            await self._write_reg(ctx, bus, self.REG_PRESC, 2, 1)
+            await self._write_reg(ctx, bus, self.REG_CTRL, 1 << 0, 1)
+
+            # run 10 cycles → floor(10/3) = 3
+            for _ in range(10):
+                await ctx.tick()
+
+            cnt = await self._read_reg(ctx, bus, self.REG_COUNT, width=4)
+            self.assertEqual(cnt, 3)  # generater error message if this test fails
+
+        sim = Simulator(dut)
+        sim.add_clock(1e-6)  # generate clock signal for ctx
+        sim.add_testbench(testbench)
+        with sim.write_vcd("gptimer_presc_test.vcd", "gptimer_presc_test.gtkw"):
+            sim.run()  # run simulation
+
+    def test_match_and_irq_and_auto_reload(self):
+        """COMPARE match should set STATUS.MATCH, assert IRQ, then auto-reload."""
+        dut = _GPTimerHarness()
+
+        async def testbench(ctx):
+            bus = dut.timer.bus
+
+            # setup: prescaler 0, compare = 5, enable + auto-reload + irq enable
+            await self._write_reg(ctx, bus, self.REG_PRESC, 0, 1)
+            await self._write_reg(ctx, bus, self.REG_COMPARE, 5, 4)
+            ctrl_bits = (1 << 0) | (1 << 2) | (1 << 3)
+            await self._write_reg(ctx, bus, self.REG_CTRL, ctrl_bits, 1)
+
+            # step up to compare
+            for _ in range(5):
+                await ctx.tick()
+
+            # on next tick, match → STATUS.MATCH=1 and irq=1
+            await ctx.tick()
+
+            cnt = await self._read_reg(ctx, bus, self.REG_COUNT, 4)
+            self.assertEqual(cnt, 0)
+
+            status = await self._read_reg(ctx, bus, self.REG_STATUS, 1)
+
+            self.assertEqual(status, 1)
+            self.assertEqual(ctx.get(dut.timer.irq), 1)
+
+            # clear the match bit
+            await self._write_reg(ctx, bus, self.REG_STATUS, 1, 1)
+            status = await self._read_reg(ctx, bus, self.REG_STATUS, 1)
+            self.assertEqual(status, 0)
+
+        sim = Simulator(dut)
+        sim.add_clock(1e-6)
+        sim.add_testbench(testbench)
+        with sim.write_vcd("gptimer_match_test.vcd", "gptimer_match_test.gtkw"):
+            sim.run()
+
+
+if __name__ == "__main__":
+    unittest.main()