wip

Author: robtaylor

amaranth_orchard/base/gpio.py

@@ -1,4 +1,4 @@
-from amaranth import *
+from amaranth import Module, unsigned
 from amaranth.lib import wiring
 from amaranth.lib.wiring import In, Out, flipped, connect
 

amaranth_orchard/io/uart.py

@@ -1,11 +1,11 @@
-from amaranth import *
+from amaranth import Module, Signal, unsigned
 from amaranth.lib import wiring
 from amaranth.lib.wiring import In, Out, flipped, connect
 
 from amaranth_soc import csr
 from amaranth_stdio.serial import AsyncSerialRX, AsyncSerialTX
 
-from chipflow_lib.platforms import BidirPinSignature, OutputPinSignature, InputPinSignature
+from chipflow_lib.platforms import OutputPinSignature, InputPinSignature
 
 
 __all__ = ["UARTPins", "UARTPeripheral"]

amaranth_orchard/memory/hyperram.py

@@ -7,10 +7,10 @@
 
 from amaranth import *
 from amaranth.lib import wiring
-from amaranth.lib.wiring import In, Out, connect, flipped
+from amaranth.lib.wiring import Out, connect, flipped
 from amaranth.utils import ceil_log2
 
-from amaranth.sim import *
+from amaranth.sim import Simulator
 
 from amaranth_soc import csr, wishbone
 from amaranth_soc.memory import MemoryMap
@@ -101,7 +101,6 @@ def elaborate(self, platform):
 
         # Data shift register
         sr = Signal(48)
-        sr_shift = Signal()
 
         # Whether or not we need to apply x2 latency
         x2_lat = Signal()

amaranth_orchard/memory/spimemio.py

@@ -121,7 +121,7 @@ def elaborate(self, platform):
             m.d.sync += self.data_bus.ack.eq(0)
 
         if platform is not None:
-            path = Path(__file__).parent / f"verilog/spimemio.v"
+            path = Path(__file__).parent / "verilog/spimemio.v"
             with open(path, 'r') as f:
                 platform.add_file(path.name, f)
 

pyproject.toml

@@ -13,7 +13,7 @@ authors = [
 readme = {file = "README.md", content-type = "text/markdown"}
 license = {file = "LICENSE.txt"}
 
-requires-python = "~=3.8"
+requires-python = ">=3.10"
 dependencies = [
     "amaranth>=0.5,<0.6",
     "chipflow-lib @ git+https://github.com/ChipFlow/chipflow-lib.git@replace-providers",
@@ -27,3 +27,13 @@ requires = ["pdm-backend"]
 build-backend = "pdm.backend"
 
 # Development workflow configuration
+
+[tool.pyright]
+diagnosticMode=false
+typeCheckingMode = "off"
+reportInvalidTypeForm = false
+reportMissingImports = false
+reportUnboundVariable = false
+
+[tool.ruff.lint]
+ignore = ['F403', 'F405']