Fix to do everything modern CSR way

Author: robtaylor

amaranth_orchard/base/gpio.py

@@ -55,12 +55,12 @@ def __init__(self, width):
 
     All pins default to input at power up.
     """
-    def __init__(self, *, name, pins):
+    def __init__(self, *, pins):
 
         self.width = pins.width
         self.pins  = pins
 
-        regs = csr.Builder(addr_width=4, data_width=8, name=name)
+        regs = csr.Builder(addr_width=4, data_width=8)
 
         self._do = regs.add("do", self.DO(self.width), offset=0x0)
         self._oe = regs.add("oe", self.OE(self.width), offset=0x4)

amaranth_orchard/base/soc_id.py

@@ -21,11 +21,11 @@ def __init__(self, width):
     Two read-only CSRs; the first contains a SoC-defined type ID and the second the git hash of the
     repo being used to build the SoC.
     """
-    def __init__(self, *, name, type_id=0xbadca77e):
+    def __init__(self, *, type_id=0xbadca77e):
         self.type_id  = type_id
         self.git_hash = int(subprocess.check_output('git rev-parse --verify HEAD'.split(' ')).strip()[0:8], base=16)
 
-        regs = csr.Builder(addr_width=4, data_width=8, name=name)
+        regs = csr.Builder(addr_width=4, data_width=8)
 
         self._soc_type    = regs.add("soc_type",    self.Register(32), offset=0x0)
         self._soc_version = regs.add("soc_version", self.Register(32), offset=0x4)

amaranth_orchard/io/uart.py

@@ -55,11 +55,11 @@ def __init__(self, init_divisor):
 
     TODO: Interrupts support, perhaps mimic something with upstream Linux kernel support...
     """
-    def __init__(self, *, name, init_divisor, pins):
+    def __init__(self, *, init_divisor, pins):
         self.init_divisor = init_divisor
         self.pins = pins
 
-        regs = csr.Builder(addr_width=5, data_width=8, name=name)
+        regs = csr.Builder(addr_width=5, data_width=8)
 
         self._tx_data  = regs.add("tx_data",  self.TxData(),  offset=0x00)
         self._rx_data  = regs.add("rx_data",  self.RxData(),  offset=0x04)

amaranth_orchard/memory/spimemio.py

@@ -55,23 +55,23 @@ def elaborate(self, platform):
     - ctrl_bus is the original 32-bit control register
     - data_bus is a bus peripheral that directly maps the 16MB of read-only flash memory.
     """
-    def __init__(self, *, name, flash):
-        self.flash = flash
+    def __init__(self, flash):
         self.size  = 2**24
         size_words = (self.size * 8) // 32
 
         super().__init__({
+            "qspi": Out(QSPIPins.Signature()),
             "ctrl_bus": In(csr.Signature(addr_width=exact_log2(4), data_width=8)),
             "data_bus": In(wishbone.Signature(addr_width=exact_log2(size_words), data_width=32,
                                               granularity=8)),
         })
 
         ctrl_memory_map = MemoryMap(addr_width=exact_log2(4), data_width=8)
-        ctrl_memory_map.add_resource(name=(name,), size=4, resource=self)
+        ctrl_memory_map.add_resource(name="spimemio", size=4, resource=self)
         self.ctrl_bus.memory_map = ctrl_memory_map
 
         data_memory_map = MemoryMap(addr_width=exact_log2(self.size), data_width=8)
-        data_memory_map.add_resource(name=(name,), size=self.size, resource=self)
+        data_memory_map.add_resource(name="spimemio", size=self.size, resource=self)
         self.data_bus.memory_map = data_memory_map
 
     def elaborate(self, platform):
@@ -90,17 +90,17 @@ def elaborate(self, platform):
             "o_ready": spi_ready,
             "i_addr": Cat(Const(0, 2), self.data_bus.adr), # Hack to force a 1MB offset
             "o_rdata": self.data_bus.dat_r,
-            "o_flash_csb": self.flash.csn.o,
-            "o_flash_clk": self.flash.clk.o,
+            "o_flash_csb": self.qspi.csn.o,
+            "o_flash_clk": self.qspi.clk.o,
             "i_cfgreg_we": ctrl_bridge.cfgreg_we,
             "i_cfgreg_di": ctrl_bridge.cfgreg_di,
             "o_cfgreg_do": ctrl_bridge.cfgreg_do,
         } | {
-            f"o_flash_io{n}_oe": getattr(self.flash, f"d{n}").oe for n in range(4)
+            f"o_flash_io{n}_oe": getattr(self.qspi, f"d{n}").oe for n in range(4)
         } | {
-            f"o_flash_io{n}_o": getattr(self.flash, f"d{n}").o for n in range(4)
+            f"o_flash_io{n}_o": getattr(self.qspi, f"d{n}").o for n in range(4)
         } | {
-            f"o_flash_io{n}_i": getattr(self.flash, f"d{n}").i for n in range(4) 
+            f"o_flash_io{n}_i": getattr(self.qspi, f"d{n}").i for n in range(4) 
         }
 
         m.submodules.spimemio = Instance("spimemio", **verilog_map)