Export more useful data

Author: robtaylor

chipflow_digital_ip/base/_platform_timer.py

@@ -7,30 +7,39 @@
 
 __all__ = ["PlatformTimer"]
 
+# Some deep weirness going on, putting docstrings in the normal location
+# doesn't work with subclasses of csr.Register. I have no idea why!!!
+#
+class CNT(csr.Register, access="r"):
+    """
+    Cycle counter (read-only).
+    """
+    def __init__(self, width):
+        super().__init__({"val": csr.Field(csr.action.R, unsigned(width))})
 
-class PlatformTimer(wiring.Component):
-    class CNT(csr.Register, access="r"):
-        """Cycle counter (read-only)."""
-        def __init__(self, width):
-            super().__init__({"val": csr.Field(csr.action.R, unsigned(width))})
 
-    class CMP(csr.Register, access="rw"):
-        """Comparator (read/write).
+class CMP(csr.Register, access="rw"):
+    """
+    Comparator (read/write).
+
+    If set to a non-zero value, an interrupt is triggered when CNT is greater than or equal
+    to CMP.
+    """
+    def __init__(self, width):
+        super().__init__({"val": csr.Field(csr.action.RW, unsigned(width))})
 
-        If set to a non-zero value, an interrupt is triggered when CNT is greater than or equal
-        to CMP.
-        """
-        def __init__(self, width):
-            super().__init__({"val": csr.Field(csr.action.RW, unsigned(width))})
 
-    """Platform timer peripheral."""
+class PlatformTimer(wiring.Component):
+    """
+    Simple timer that counts clock cycles and raises an interrupt when the count hits a configured threshold
+    """
     def __init__(self):
         self.width = 48
 
         regs = csr.Builder(addr_width=4, data_width=8)
 
-        self._cnt = regs.add("cnt", self.CNT(self.width), offset=0x0)
-        self._cmp = regs.add("cmp", self.CMP(self.width), offset=0x8)
+        self._cnt = regs.add("cnt", CNT(self.width), offset=0x0)
+        self._cmp = regs.add("cmp", CMP(self.width), offset=0x8)
 
         self._bridge = csr.Bridge(regs.as_memory_map())
 

chipflow_digital_ip/io/_gpio.py

@@ -10,20 +10,6 @@
 
 
 class GPIOPeripheral(wiring.Component):
-
-    class Signature(wiring.Signature):
-        def __init__(self, pin_count=1):
-            if pin_count > 32:
-                raise ValueError(f"Pin pin_count must be lesser than or equal to 32, not {pin_count}")
-            self._pin_count = pin_count
-            super().__init__({
-                "gpio": Out(BidirIOSignature(pin_count, all_have_oe=True))
-                })
-
-        @property
-        def pin_count(self):
-            return self._pin_count
-
     """Wrapper for amaranth_soc gpio with chipflow_lib.IOSignature support
 
     Parameters
@@ -55,7 +41,23 @@ def pin_count(self):
         If ``input_stages`` is not a non-negative integer.
     """
 
-    def __init__(self, *, pin_count, addr_width=4, data_width=8, input_stages=2):
+    class Signature(wiring.Signature):
+        """
+        Signature of the gpio port wiring
+        """
+        def __init__(self, pin_count=1):
+            if pin_count > 32:
+                raise ValueError(f"Pin pin_count must be lesser than or equal to 32, not {pin_count}")
+            self._pin_count = pin_count
+            super().__init__({
+                "gpio": Out(BidirIOSignature(pin_count, all_have_oe=True))
+                })
+
+        @property
+        def pin_count(self):
+            return self._pin_count
+
+    def __init__(self, *, pin_count=8, addr_width=4, data_width=8, input_stages=2):
         self._gpio = gpio.Peripheral(pin_count=pin_count,
                                      addr_width=addr_width,
                                      data_width=data_width,

chipflow_digital_ip/memory/_qspi_flash.py

@@ -256,7 +256,7 @@ def __init__(self):
                 "d": Out(BidirIOSignature(4, all_have_oe=True)),
             })
 
-    def __init__(self, *, addr_width, data_width):
+    def __init__(self, *, addr_width=24, data_width=32):
         super().__init__({
             "pins": Out(self.Signature()),
             "csr_bus": In(csr.Signature(addr_width=4, data_width=8)),

chipflow_digital_ip/memory/_sram.py

@@ -53,7 +53,7 @@ class SRAMPeripheral(wiring.Component):
         Wishbone bus interface.
     """
     # TODO raise bus.err if read-only and a bus write is attempted.
-    def __init__(self, *, size, data_width=32, granularity=8, writable=True):
+    def __init__(self, *, size=1024, data_width=32, granularity=8, writable=True):
         if not isinstance(size, int) or size <= 0 or size & size-1:
             raise ValueError("Size must be an integer power of two, not {!r}"
                              .format(size))

pyproject.toml

@@ -17,7 +17,7 @@ requires-python = ">=3.11"
 dependencies = [
     "amaranth>=0.5,<0.6",
     "chipflow-lib @ git+https://github.com/ChipFlow/chipflow-lib.git",
-    "amaranth-soc @ git+https://github.com/amaranth-lang/amaranth-soc",
+    "amaranth-soc @ git+https://github.com/ChipFlow/amaranth-soc.git",
     "amaranth-stdio @ git+https://github.com/amaranth-lang/amaranth-stdio",
 ]
 

tools/export_ips.py

@@ -4,8 +4,10 @@
 import sys
 
 from amaranth.lib import wiring
+from amaranth_soc.memory import MemoryMap
 from docstring_parser import parse_from_object
 
+
 import chipflow_digital_ip
 
 def children(mod):
@@ -23,16 +25,58 @@ def children(mod):
             done.append(e)
             stack.extend([(f"{e}.{attr}", getattr(o, attr)) for attr in dir(o) if not attr.startswith("_")])
 
+def name_to_str(n: MemoryMap.Name) -> str:
+    return  ".".join(f"{part}" for part in n)
+
+def docs_for_obj(obj) -> dict:
+    docstring = parse_from_object(obj)
+    #init_signature = inspect.signature(cls.__init__)
+    #print(f"{name} Signature:i {init_signature}")
+    d = {}
+    if docstring.short_description:
+        d['short_description'] = docstring.short_description
+    if docstring.long_description:
+        d['long_description'] = docstring.long_description
+    if docstring.params:
+        d['params'] = [p.__dict__ for p in docstring.params if p.args[0]=="param"]
+        d['attributes'] = [p.__dict__ for p in docstring.params if p.args[0]=="attribute"]
+    if docstring.raises:
+        d['raises'] = [p.__dict__ for p in docstring.raises]
+    if docstring.examples:
+        d['examples'] = [ e.__dict__ for e in docstring.examples]
+    return d
+
+
+def list_resources(mm: MemoryMap) -> dict:
+    d = {}
+    for resource, rname, _ in mm.resources():
+        cls = resource.__class__
+        print(f"adding resource {resource}. {type(resource)} {cls.__name__}, {cls.__qualname__}, {cls.__doc__}")
+        ri = mm.find_resource(resource)
+        d[name_to_str(rname)] = {
+                'resource': docs_for_obj(resource),
+                'start': f"{ri.start:#x}",
+                'end': f"{ri.end:#x}",
+                'width': ri.width,
+        }
+    for window, wname, (start, end, ratio) in mm.windows():
+        d[name_to_str(wname)] = {
+                'window': docs_for_obj(window),
+                'start': f"{start:#x}",
+                'end': f"{end:#x}",
+                'ratio': ratio,
+                'children': list_resources(window)
+                }
+    return d
+
 gen = children(chipflow_digital_ip)
 output={}
 for name, cls in gen:
-    docstring = parse_from_object(cls)
-    d = {
-        'short_description': docstring.short_description,
-        'long_description': docstring.long_description,
-        'params': [p.__dict__ for p in docstring.params],
-        'examples': [ e.__dict__ for e in docstring.examples],
-        }
+    # instantiate and get registers
+    obj = cls()
+    d = docs_for_obj(obj)
+    if hasattr(obj, 'bus') and hasattr(obj.bus, 'memory_map') and isinstance(obj.bus.memory_map, MemoryMap):
+        d['memory_map'] = list_resources(obj.bus.memory_map)
     output[name] = d
 
 json.dump(output, sys.stdout, indent=2)