Use new all_have_oe flag to BidirPinSignature for GPIO and SPIMemIO

Author: robtaylor

amaranth_orchard/base/gpio.py

@@ -15,10 +15,9 @@ def __init__(self, width):
             if width > 32:
                 raise ValueError(f"Pin width must be lesser than or equal to 32, not {width}")
             self._width = width
-            super().__init__(
-                # each pin has seperate output enable
-                {f"gpio{n}":Out(BidirPinSignature(1)) for n in range(width)}
-            )
+            super().__init__({
+                "gpio": Out(BidirPinSignature(width, all_have_oe=True))
+            })
 
         @property
         def width(self):
@@ -29,8 +28,8 @@ def create(self, *, path=(), src_loc_at=0):
 
     def __init__(self, width, *, path=(), src_loc_at=0):
         super().__init__(self.Signature(width), path=path, src_loc_at=1 + src_loc_at)
-    
-    @property  
+
+    @property
     def width(self):
         return self.signature.width
 
@@ -78,8 +77,8 @@ def elaborate(self, platform):
 
         connect(m, flipped(self.bus), self._bridge.bus)
 
-        m.d.comb += [ getattr(self.pins, f"gpio{n}").o.eq(self._do.f.pins.data[n]) for n in range(self.width)]
-        m.d.comb += [ getattr(self.pins, f"gpio{n}").oe.eq(self._oe.f.pins.data[n]) for n in range(self.width)]
-        m.d.comb += [ self._di.f.pins.r_data[n].eq(getattr(self.pins, f"gpio{n}").i) for n in range(self.width)]
+        m.d.comb += self.pins.gpio.o.eq(self._do.f.pins.data)
+        m.d.comb += self.pins.gpio.oe.eq(self._oe.f.pins.data)
+        m.d.comb += self._di.f.pins.r_data.eq(self.pins.gpio.i)
 
         return m

amaranth_orchard/memory/spimemio.py

@@ -18,8 +18,8 @@ def __init__(self):
             super().__init__({
                 "clk": Out(OutputPinSignature(1)),
                 "csn": Out(OutputPinSignature(1)),
-            } |
-            {f"d{n}": Out(BidirPinSignature(1)) for n in range(4)})
+                "d": Out(BidirPinSignature(4, all_have_oe=True)),
+            })
 
         def create(self, *, path=(), src_loc_at=0):
             return QSPIPins(path=path, src_loc_at=1 + src_loc_at)
@@ -98,11 +98,11 @@ def elaborate(self, platform):
             "i_cfgreg_di": ctrl_bridge.cfgreg_di,
             "o_cfgreg_do": ctrl_bridge.cfgreg_do,
         } | {
-            f"o_flash_io{n}_oe": getattr(self.qspi, f"d{n}").oe for n in range(4)
+            f"o_flash_io{n}_oe": self.qspi.d.oe[n] for n in range(4)
         } | {
-            f"o_flash_io{n}_o": getattr(self.qspi, f"d{n}").o for n in range(4)
+            f"o_flash_io{n}_do": self.qspi.d.o[n] for n in range(4)
         } | {
-            f"o_flash_io{n}_i": getattr(self.qspi, f"d{n}").i for n in range(4) 
+            f"o_flash_io{n}_di": self.qspi.d.i[n] for n in range(4)
         }
 
         m.submodules.spimemio = Instance("spimemio", **verilog_map)