Rename SPI miso/mosi to more modern cipo/copi

Author: robtaylor

my_design/ips/spi.py

@@ -12,8 +12,8 @@
 
 SPISignature = wiring.Signature({
     "sck": Out(OutputPinSignature(1)),
-    "mosi": Out(OutputPinSignature(1)),
-    "miso": Out(InputPinSignature(1)),
+    "copi": Out(OutputPinSignature(1)),
+    "cipo": Out(InputPinSignature(1)),
     "csn": Out(OutputPinSignature(1)),
 })
 
@@ -104,11 +104,11 @@ def elaborate(self, platform):
         with m.If(setup):
             m.d.sync += sr_o.eq(Cat(C(0, 1), sr_o))
         with m.If(latch):
-            m.d.sync += sr_i.eq(Cat(self.spi.miso.i, sr_i))
+            m.d.sync += sr_i.eq(Cat(self.spi.cipo.i, sr_i))
 
         m.d.comb += [
             self.d_recv.eq(sr_i),
-            self.spi.mosi.o.eq(sr_o[-1])
+            self.spi.copi.o.eq(sr_o[-1])
         ]
 
         return m

my_design/ips/test_spi.py

@@ -64,16 +64,16 @@ def testbench():
                     yield Tick()
                     for i in reversed(range(width)):
                         if sck_edge:
-                            yield dut.spi_pins.miso.i.eq((d_recv >> i) & 0x1)
+                            yield dut.spi_pins.cipo.i.eq((d_recv >> i) & 0x1)
                         else:
-                            self.assertEqual((yield dut.spi_pins.mosi.o), (d_send >> i) & 0x1)
+                            self.assertEqual((yield dut.spi_pins.copi.o), (d_send >> i) & 0x1)
                         self.assertEqual((yield dut.spi_pins.sck.o), 0 ^ sck_idle)
                         yield Tick()
                         self.assertEqual((yield dut.spi_pins.sck.o), 0 ^ sck_idle)
                         if sck_edge:
-                            self.assertEqual((yield dut.spi_pins.mosi.o), (d_send >> i) & 0x1)
+                            self.assertEqual((yield dut.spi_pins.copi.o), (d_send >> i) & 0x1)
                         else:
-                            yield dut.spi_pins.miso.i.eq((d_recv >> i) & 0x1)
+                            yield dut.spi_pins.cipo.i.eq((d_recv >> i) & 0x1)
                         yield Tick()
                         self.assertEqual((yield dut.spi_pins.sck.o), 1 ^ sck_idle)
                         yield Tick()
@@ -106,7 +106,7 @@ def testbench():
             yield from self._write_reg(dut, self.REG_SEND_DATA, (d_send << (32 - width)), 4)
             yield Tick()
             for i in reversed(range(width)):
-                self.assertEqual((yield dut.spi_pins.mosi.o),(d_send >> i) & 0x1)
+                self.assertEqual((yield dut.spi_pins.copi.o),(d_send >> i) & 0x1)
                 self.assertEqual((yield dut.spi_pins.sck.o), 0)
                 for j in range(divide+1): yield Tick()
                 self.assertEqual((yield dut.spi_pins.sck.o), 1)

my_design/sim/main.cc

@@ -23,9 +23,9 @@ int main(int argc, char **argv) {
     gpio_model gpio_0("gpio_0", top.p_gpio__0____gpio____o, top.p_gpio__0____gpio____oe, top.p_gpio__0____gpio____i);
     gpio_model gpio_1("gpio_1", top.p_gpio__1____gpio____o, top.p_gpio__1____gpio____oe, top.p_gpio__1____gpio____i);
 
-    spi_model spi_0("spi_0", top.p_user__spi__0____sck____o, top.p_user__spi__0____csn____o, top.p_user__spi__0____mosi____o, top.p_user__spi__0____miso____i);
-    spi_model spi_1("spi_1", top.p_user__spi__1____sck____o, top.p_user__spi__1____csn____o, top.p_user__spi__1____mosi____o, top.p_user__spi__1____miso____i);
-    spi_model spi_2("spi_2", top.p_user__spi__2____sck____o, top.p_user__spi__2____csn____o, top.p_user__spi__2____mosi____o, top.p_user__spi__2____miso____i);
+    spi_model spi_0("spi_0", top.p_user__spi__0____sck____o, top.p_user__spi__0____csn____o, top.p_user__spi__0____copi____o, top.p_user__spi__0____cipo____i);
+    spi_model spi_1("spi_1", top.p_user__spi__1____sck____o, top.p_user__spi__1____csn____o, top.p_user__spi__1____copi____o, top.p_user__spi__1____cipo____i);
+    spi_model spi_2("spi_2", top.p_user__spi__2____sck____o, top.p_user__spi__2____csn____o, top.p_user__spi__2____copi____o, top.p_user__spi__2____cipo____i);
 
     i2c_model i2c_0("i2c_0", top.p_i2c__0____sda____oe, top.p_i2c__0____sda____i, top.p_i2c__0____scl____oe, top.p_i2c__0____scl____i);
     i2c_model i2c_1("i2c_1", top.p_i2c__1____sda____oe, top.p_i2c__1____sda____i, top.p_i2c__1____scl____oe, top.p_i2c__1____scl____i);

my_design/steps/board.py

@@ -34,13 +34,13 @@ def elaborate(self, platform):
                 "expansion",
                 0,
                 Subsignal("user_spi0_sck",  Pins("0+", conn=("gpio", 0), dir='o')),
-                Subsignal("user_spi0_mosi", Pins("0-", conn=("gpio", 0), dir='o')),
-                Subsignal("user_spi0_miso", Pins("1+", conn=("gpio", 0), dir='i')),
+                Subsignal("user_spi0_copi", Pins("0-", conn=("gpio", 0), dir='o')),
+                Subsignal("user_spi0_cipo", Pins("1+", conn=("gpio", 0), dir='i')),
                 Subsignal("user_spi0_csn", Pins("1-", conn=("gpio", 0), dir='o')),
 
                 Subsignal("user_spi1_sck",  Pins("2+", conn=("gpio", 0), dir='o')),
-                Subsignal("user_spi1_mosi", Pins("2-", conn=("gpio", 0), dir='o')),
-                Subsignal("user_spi1_miso", Pins("3+", conn=("gpio", 0), dir='i')),
+                Subsignal("user_spi1_copi", Pins("2-", conn=("gpio", 0), dir='o')),
+                Subsignal("user_spi1_cipo", Pins("3+", conn=("gpio", 0), dir='i')),
                 Subsignal("user_spi1_csn", Pins("3-", conn=("gpio", 0), dir='o')),
 
                 Subsignal("i2c0_sda", Pins("4+", conn=("gpio", 0), dir='io')),

pins.lock

@@ -282,7 +282,7 @@
             "init": null
           }
         },
-        "user_spi_0_mosi": {
+        "user_spi_0_copi": {
           "pins": [
             "99"
           ],
@@ -293,7 +293,7 @@
             "init": null
           }
         },
-        "user_spi_0_miso": {
+        "user_spi_0_cipo": {
           "pins": [
             "10"
           ],
@@ -328,7 +328,7 @@
             "init": null
           }
         },
-        "user_spi_1_mosi": {
+        "user_spi_1_copi": {
           "pins": [
             "43"
           ],
@@ -339,7 +339,7 @@
             "init": null
           }
         },
-        "user_spi_1_miso": {
+        "user_spi_1_cipo": {
           "pins": [
             "44"
           ],
@@ -374,7 +374,7 @@
             "init": null
           }
         },
-        "user_spi_2_mosi": {
+        "user_spi_2_copi": {
           "pins": [
             "83"
           ],
@@ -385,7 +385,7 @@
             "init": null
           }
         },
-        "user_spi_2_miso": {
+        "user_spi_2_cipo": {
           "pins": [
             "84"
           ],
@@ -1138,12 +1138,12 @@
                   }
                 }
               },
-              "mosi": {
+              "copi": {
                 "type": "interface",
                 "members": {
                   "o": {
                     "type": "port",
-                    "name": "user_spi_0__mosi__o",
+                    "name": "user_spi_0__copi__o",
                     "dir": "out",
                     "width": 1,
                     "signed": false,
@@ -1161,12 +1161,12 @@
                   }
                 }
               },
-              "miso": {
+              "cipo": {
                 "type": "interface",
                 "members": {
                   "i": {
                     "type": "port",
-                    "name": "user_spi_0__miso__i",
+                    "name": "user_spi_0__cipo__i",
                     "dir": "in",
                     "width": 1,
                     "signed": false,
@@ -1236,12 +1236,12 @@
                   }
                 }
               },
-              "mosi": {
+              "copi": {
                 "type": "interface",
                 "members": {
                   "o": {
                     "type": "port",
-                    "name": "user_spi_1__mosi__o",
+                    "name": "user_spi_1__copi__o",
                     "dir": "out",
                     "width": 1,
                     "signed": false,
@@ -1259,12 +1259,12 @@
                   }
                 }
               },
-              "miso": {
+              "cipo": {
                 "type": "interface",
                 "members": {
                   "i": {
                     "type": "port",
-                    "name": "user_spi_1__miso__i",
+                    "name": "user_spi_1__cipo__i",
                     "dir": "in",
                     "width": 1,
                     "signed": false,
@@ -1334,12 +1334,12 @@
                   }
                 }
               },
-              "mosi": {
+              "copi": {
                 "type": "interface",
                 "members": {
                   "o": {
                     "type": "port",
-                    "name": "user_spi_2__mosi__o",
+                    "name": "user_spi_2__copi__o",
                     "dir": "out",
                     "width": 1,
                     "signed": false,
@@ -1357,12 +1357,12 @@
                   }
                 }
               },
-              "miso": {
+              "cipo": {
                 "type": "interface",
                 "members": {
                   "i": {
                     "type": "port",
-                    "name": "user_spi_2__miso__i",
+                    "name": "user_spi_2__cipo__i",
                     "dir": "in",
                     "width": 1,
                     "signed": false,

pins.lock.bak

@@ -367,10 +367,10 @@
     "user_spi_0_csn_o": {
       "pin": 22
     },
-    "user_spi_0_miso_i": {
+    "user_spi_0_cipo_i": {
       "pin": 21
     },
-    "user_spi_0_mosi_o": {
+    "user_spi_0_copi_o": {
       "pin": 20
     },
     "user_spi_0_sck_o": {
@@ -379,10 +379,10 @@
     "user_spi_1_csn_o": {
       "pin": 26
     },
-    "user_spi_1_miso_i": {
+    "user_spi_1_cipo_i": {
       "pin": 25
     },
-    "user_spi_1_mosi_o": {
+    "user_spi_1_copi_o": {
       "pin": 24
     },
     "user_spi_1_sck_o": {
@@ -391,10 +391,10 @@
     "user_spi_2_csn_o": {
       "pin": 30
     },
-    "user_spi_2_miso_i": {
+    "user_spi_2_cipo_i": {
       "pin": 29
     },
-    "user_spi_2_mosi_o": {
+    "user_spi_2_copi_o": {
       "pin": 28
     },
     "user_spi_2_sck_o": {

pyuvm_verif/utils_spi.py

@@ -32,7 +32,7 @@ def __init__(self):
         self.driver_queue = Queue(maxsize=1)
         self.cmd_mon_queue = Queue(maxsize=0)
         self.result_mon_queue = Queue(maxsize=0)
-        self.data_miso = 0
+        self.data_cipo = 0
         self.clk_div = 0
         self.width_num = 0
         self.width_en = 0
@@ -112,8 +112,8 @@ async def result_mon_bfm(self):
                             await RisingEdge(self.dut.sck)
                         else:
                             await FallingEdge(self.dut.sck)
-                        """uvm_root().logger.info(f"I: {i} MOSI: {get_int(self.dut.mosi)}")"""
-                        write_result = write_result + get_int(self.dut.mosi)*(2**i)
+                        """uvm_root().logger.info(f"I: {i} MOSI: {get_int(self.dut.copi)}")"""
+                        write_result = write_result + get_int(self.dut.copi)*(2**i)
                     for i in range(0, 100):
                         await RisingEdge(self.dut.clk_test)
                     final_result = self.reverse_bits(write_result,8)
@@ -132,7 +132,7 @@ async def reset(self):
         self.dut.wdata.value = 0
         self.dut.rstb.value = 0
         self.dut.wstb.value = 0
-        self.dut.miso.value = 0
+        self.dut.cipo.value = 0
         await FallingEdge(self.dut.clk_test)
         await FallingEdge(self.dut.clk_test)
         await FallingEdge(self.dut.clk_test)
@@ -156,18 +156,18 @@ async def driver_bfm(self):
                     self.dut.wstb.value = 1
                     self.dut.addr.value = addr
                     self.dut.wdata.value = data
-                    data_wr_miso = bin(data)[2:]
-                    data_wr_rd = (8 - len(data_wr_miso)) * '0' + data_wr_miso
-                    self.data_miso = int(data_wr_rd,2)
-                    binary_miso = bin(self.data_miso)[2:]
-                    uvm_root().logger.info(f"DATA EXTEND: {data_wr_rd} DATA MISO: {self.data_miso } BINARY MISO: {binary_miso}")
+                    data_wr_cipo = bin(data)[2:]
+                    data_wr_rd = (8 - len(data_wr_cipo)) * '0' + data_wr_cipo
+                    self.data_cipo = int(data_wr_rd,2)
+                    binary_cipo = bin(self.data_cipo)[2:]
+                    uvm_root().logger.info(f"DATA EXTEND: {data_wr_rd} DATA MISO: {self.data_cipo } BINARY MISO: {binary_cipo}")
                     await FallingEdge(self.dut.clk_test)
                     self.dut.wstb.value = 0
                     await RisingEdge(self.dut.clk_test)
 
-                    for bit_miso in data_wr_rd:
-                        self.dut.miso.value = int(bit_miso)
-                        """uvm_root().logger.info(f"DATA MISO BIT: {int(bit_miso)}")"""
+                    for bit_cipo in data_wr_rd:
+                        self.dut.cipo.value = int(bit_cipo)
+                        """uvm_root().logger.info(f"DATA MISO BIT: {int(bit_cipo)}")"""
                         await RisingEdge(self.dut.clk_test)
                         await RisingEdge(self.dut.clk_test)
 

pyuvm_verif/verilog/spi_wrap.v

@@ -9,11 +9,11 @@ module spi_wrap
            input          wstb,
            input  [4:0]   addr,
            input  [7:0]   wdata,
-           input          miso,
+           input          cipo,
 
            output [7:0]   rdata,
            output         sck,
-           output         mosi,
+           output         copi,
            output         csn,
            output reg     done
        );
@@ -49,10 +49,10 @@ module spi_wrap
     .bus__w_data(wdata),
     .bus__w_stb(wstb),
     .spi_pins__sck_o(sck),
-    .spi_pins__mosi_o(mosi),
+    .spi_pins__copi_o(copi),
     .spi_pins__csn_o(csn),
     .bus__r_data(rdata),
-    .spi_pins__miso_i(miso)
+    .spi_pins__cipo_i(cipo)
   );
 
 endmodule : spi_wrap