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Replace UART with that from amaranth-soc RFC
Signed-off-by: gatecat <[email protected]>
1 parent 516f369 commit 8df3d5a

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3 files changed

+142
-139
lines changed

3 files changed

+142
-139
lines changed

my_design/design.py

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -186,7 +186,7 @@ def elaborate(self, platform):
186186

187187
# UART
188188
for i in range(self.uart_count):
189-
uart = UARTPeripheral(init_divisor=int(25e6//115200))
189+
uart = UARTPeripheral(init_divisor=int(25e6//115200), addr_width=5)
190190
base_addr = self.csr_uart_base + i * self.periph_offset
191191
csr_decoder.add(uart.bus, name=f"uart_{i}", addr=base_addr - self.csr_base)
192192
sw.add_periph("uart", f"UART_{i}", base_addr)

my_design/software/main.c

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2,9 +2,9 @@
22
#include "generated/soc.h"
33

44
char uart_getch_block(volatile uart_regs_t *uart) {
5-
while (!uart->rx_avail)
5+
while (!(uart->rx.status & 0x1))
66
;
7-
return uart->rx_data;
7+
return uart->rx.data;
88
}
99

1010
uint32_t spi_xfer(volatile spi_regs_t *spi, uint32_t data, uint32_t width) {
@@ -43,6 +43,9 @@ void i2c_stop(volatile i2c_regs_t *i2c) {
4343
}
4444

4545
void main() {
46+
uart_init(UART_0, 25000000/115200);
47+
uart_init(UART_1, 25000000/115200);
48+
4649
puts("🐱: nyaa~!\r\n");
4750

4851
puts("SoC type: ");

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