Fix lint issues in amaranth test files

- Remove unused imports in test_silicon_platform_additional.py
- Remove unused imports in test_silicon_platform_amaranth.py
- Fix F821 undefined name errors for Signal and ClockDomain
- Remove unused variable in test_silicon_platform_amaranth.py

🤖 Generated with [Claude Code](https://claude.ai/code)

Co-Authored-By: Claude <[email protected]>

Author: robtaylor

tests/test_silicon_platform_additional.py

@@ -6,9 +6,8 @@
 from unittest import mock
 
 import tomli
-from amaranth import Module, Signal, ClockDomain, ClockSignal, ResetSignal
-from amaranth.lib import io, wiring
-from amaranth.lib.wiring import Component, In
+from amaranth import Module, Signal, ClockDomain
+from amaranth.lib import io
 
 from chipflow_lib.platforms.silicon import (
     IOBuffer, FFBuffer, SiliconPlatformPort
@@ -93,8 +92,8 @@ def setUp(self):
     def test_instantiate_ports(self, mock_load_pinlock):
         """Test instantiate_ports method with minimal mocking"""
         # Import here to avoid issues during test collection
-        from chipflow_lib.platforms.silicon import SiliconPlatform, Port
-        from amaranth import Module, Signal, ClockDomain
+        from chipflow_lib.platforms.silicon import SiliconPlatform
+        from amaranth import Module
 
         # Create mock pinlock
         mock_pinlock = mock.MagicMock()
@@ -213,8 +212,8 @@ def test_instantiate_ports_with_clocks_and_resets(self, mock_load_pinlock, mock_
                                                     mock_reset_signal, mock_clock_signal):
         """Test instantiate_ports method with clocks and resets"""
         # Import here to avoid issues during test collection
-        from chipflow_lib.platforms.silicon import SiliconPlatform, Port
-        from amaranth import Module, Signal
+        from chipflow_lib.platforms.silicon import SiliconPlatform
+        from amaranth import Module
 
         # Create mocks for signals and buffer
         mock_clock_signal_instance = Signal()

tests/test_silicon_platform_amaranth.py

@@ -6,8 +6,8 @@
 from unittest import mock
 
 import tomli
-from amaranth import Module, Signal, Cat, ClockDomain, ClockSignal, ResetSignal
-from amaranth.lib import io, wiring
+from amaranth import Module, Signal, ClockDomain
+from amaranth.lib import io
 from amaranth.hdl._ir import Fragment
 
 from chipflow_lib import ChipFlowError
@@ -439,7 +439,7 @@ def elaborate(self, platform):
                 return m
 
         # Call build with our test elaboratable
-        result = platform.build(TestElaboratable(), name="test_build")
+        platform.build(TestElaboratable(), name="test_build")
 
         # Check that prepare was called
         platform._prepare.assert_called_once()