wip clocks

Author: robtaylor

chipflow_lib/platforms/silicon.py

@@ -263,7 +263,7 @@ def instantiate_ports(self, m: Module):
             return
 
         pinlock = load_pinlock()
-        for component, iface in pinlock.port_map.items():
+        for component, iface in pinlock.port_map.ports.items():
             for k, v in iface.items():
                 for name, port in v.items():
                     self._ports[port.port_name] = SiliconPlatformPort(component, name, port)

chipflow_lib/platforms/utils.py

@@ -476,7 +476,7 @@ class Package(pydantic.BaseModel):
     Serialisable identifier for a defined packaging option
     """
     type: PackageDef = pydantic.Field(discriminator="package_type")
-
+    clocks: List[str]
 
 def _linear_allocate_components(interfaces: dict, lockfile: LockFile | None, allocate, unallocated) -> PortMap:
     port_map = PortMap()
@@ -595,6 +595,7 @@ def model_post_init(self, __context):
 
     def allocate_pins(self, process: 'Process', lockfile: LockFile|None) -> LockFile:
         portmap =  _linear_allocate_components(self._interfaces, lockfile, self._allocate, set(self._ordered_pins))
+        #clocks = 
         return LockFile(package=Package(type=self), process=process, metadata=self._interfaces, port_map=portmap)
 
     @property

docs/chipflow-toml-guide.rst

@@ -69,18 +69,11 @@ You probably won't need to change these if you're starting from an example repos
 .. _chipflow_lib: https://github.com/ChipFlow/chipflow-lib
 
 
-``[chipflow.clocks]``
----------------------
-
-.. code-block:: TOML
+Clock Definitions
+-----------------
 
-   [chipflow.clocks]
-   default = 'sys_clk'
+The clock pins to be allocation on the package are determined from the top level clock domains exposed by components in `[chipflow.top]`.
 
-This section links the clock domains utilized in the design to specific pads.
-These pads need to be specified in the `[silicon.pads]`_ section with the :term:`type` set to :term:`clock`.
-The ``default`` clock domain is associated with the Amaranth :any:`sync <lang-domains>` :ref:`clock domain <lang-clockdomains>`.
-Currently, only one ``default`` clock domain is supported.
 
 
 ``[chipflow.resets]``
@@ -140,20 +133,15 @@ Available Package Definitions
 +----------+-----------+--------------------+------------------------------------+
 
 
-``[silicon.power]``
--------------------
 
-This section outlines the connection of pads to the power supply available for the selected process and package.
-These pads are declared with the :term:type parameter, along with a name and other optional information, like voltage.
+Power connections
+-----------------
 
-Note that in this context, the :term:type parameter can only be ``ground`` or ``power``.
+The package definition provides default locations for pins needed for bringup and test, like core power, ground, clock and reset, along with JTAG.
 
-The package definition provides default locations for pins needed for bringup and test, like core power, ground, clock and reset, along with JTAG. These are called:
+These can be determined by calling `BasePackageDef.bringup_pins`.
 
-[chipflow.silicon.power]
-vdd = { type = "power", name = "vdd", voltage = "1.8V" }
-gnd = { type = "ground", name = "gnd" }
-```
+For ports that require their own power lines, you can set ``allocate_power`` and ``power_voltage`` in their `IOSignature`.
 
 .. glossary::