Adding new tests for SPI (#27)

johnymil-chipflow · robtaylor · commit 0d17d54a3c4f · 2024-09-14T16:09:20.000+02:00
* Adding new tests for SPI
* Removing unused signal
diff --git a/pyuvm_verif/testbench_spi.py b/pyuvm_verif/testbench_spi.py
@@ -115,49 +115,6 @@ async def body(self):
             spiwr3 = SpiSeq("spiwr3", 0xb, data3, 1)
             await spiwr3.start(seqr)
 
-        spiwr0 = SpiSeq("spiwr0", 0x0, 0x87, 1)
-        spiwr1 = SpiSeq("spiwr1", 0x4, 0x0, 1)
-        spiwr2 = SpiSeq("spiwr2", 0xb, 0x45, 1)
-        await spiwr0.start(seqr)
-        await spiwr1.start(seqr)
-        await spiwr2.start(seqr)
-        for i in range(1):
-            data3 = random.randint(0, 255)
-            spiwr3 = SpiSeq("spiwr3", 0xb, data3, 1)
-            await spiwr3.start(seqr)
-
-        spiwr0 = SpiSeq("spiwr0", 0x0, 0x86, 1)
-        spiwr1 = SpiSeq("spiwr1", 0x4, 0x0, 1)
-        spiwr2 = SpiSeq("spiwr2", 0xb, 0x45, 1)
-        await spiwr0.start(seqr)
-        await spiwr1.start(seqr)
-        await spiwr2.start(seqr)
-        for i in range(1):
-            data3 = random.randint(0, 255)
-            spiwr3 = SpiSeq("spiwr3", 0xb, data3, 1)
-            await spiwr3.start(seqr)
-
-        spiwr0 = SpiSeq("spiwr0", 0x0, 0x3d, 1)
-        spiwr1 = SpiSeq("spiwr1", 0x4, 0x0, 1)
-        spiwr2 = SpiSeq("spiwr2", 0xb, 0x45, 1)
-        await spiwr0.start(seqr)
-        await spiwr1.start(seqr)
-        await spiwr2.start(seqr)
-        for i in range(0):
-            data3 = random.randint(0, 255)
-            spiwr3 = SpiSeq("spiwr3", 0xb, data3, 1)
-            await spiwr3.start(seqr)
-
-        spiwr0 = SpiSeq("spiwr0", 0x0, 0x3c, 1)
-        spiwr1 = SpiSeq("spiwr1", 0x4, 0x0, 1)
-        spiwr2 = SpiSeq("spiwr2", 0xb, 0x45, 1)
-        await spiwr0.start(seqr)
-        await spiwr1.start(seqr)
-        await spiwr2.start(seqr)
-        for i in range(0):
-            data3 = random.randint(0, 255)
-            spiwr3 = SpiSeq("spiwr3", 0xb, data3, 1)
-            await spiwr3.start(seqr)
 
 class TestRdSeq(uvm_sequence):
     async def body(self):
@@ -185,40 +142,33 @@ async def body(self):
             spird = SpiSeq("spird", 0xc, data3, 2)
             await spird.start(seqr)
 
-        spiwr0 = SpiSeq("spiwr0", 0x0, 0x3d, 1)
-        spiwr1 = SpiSeq("spiwr1", 0x4, 0x0, 1)
-        await spiwr0.start(seqr)
-        await spiwr1.start(seqr)
-        for i in range(1):
-            data3 = random.randint(0, 255)
-            spiwr3 = SpiSeq("spiwr3", 0xb, data3, 1)
-            await spiwr3.start(seqr)
-            spird = SpiSeq("spird", 0xc, data3, 2)
-            await spird.start(seqr)
-
-        spiwr0 = SpiSeq("spiwr0", 0x0, 0x3c, 1)
-        spiwr1 = SpiSeq("spiwr1", 0x4, 0x0, 1)
-        await spiwr0.start(seqr)
-        await spiwr1.start(seqr)
-        for i in range(1):
-            data3 = random.randint(0, 255)
-            spiwr3 = SpiSeq("spiwr3", 0xb, data3, 1)
-            await spiwr3.start(seqr)
-            spird = SpiSeq("spird", 0xc, data3, 2)
-            await spird.start(seqr)
-
 class TestClkdivSeq(uvm_sequence):
     async def body(self):
         uvm_root().logger.info(f"TEST: CLOCK DIVIDER")
         seqr = ConfigDB().get(None, "", "SEQR")
         spiwr0 = SpiSeq("spiwr0", 0x0, 0x3f, 1)
         await spiwr0.start(seqr)
-        data1 = random.randint(0, 255)
-        spiwr1 = SpiSeq("spiwr1", 0x4, data1, 1)
-        await spiwr1.start(seqr)
-        data2 = random.randint(0, 255)
-        spiwr2 = SpiSeq("spiwr2", 0xb, data2, 1)
-        await spiwr2.start(seqr)
+        for i in (1,25,63,127):
+            data1 = i
+            spiwr1 = SpiSeq("spiwr1", 0x4, data1, 1)
+            await spiwr1.start(seqr)
+            data2 = random.randint(0, 255)
+            spiwr2 = SpiSeq("spiwr2", 0xb, data2, 1)
+            await spiwr2.start(seqr)
+
+class WidthSeq(uvm_sequence):
+    async def body(self):
+        uvm_root().logger.info(f"TEST: SPI WIDTH")
+        seqr = ConfigDB().get(None, "", "SEQR")
+        for i in (0x3f, 0x47):
+            data1 = i;
+            spiwr0 = SpiSeq("spiwr0", 0x0, data1, 1)
+            await spiwr0.start(seqr)
+            spiwr1 = SpiSeq("spiwr1", 0x4, 0x0, 1)
+            await spiwr1.start(seqr)
+            data2 = random.randint(0, 255)
+            spiwr2 = SpiSeq("spiwr2", 0xb, data2, 1)
+            await spiwr2.start(seqr)
 
 class Driver(uvm_driver):
     def build_phase(self):
@@ -359,4 +309,11 @@ class ClkdividerTest(BasicTest):
 
     def build_phase(self):
         uvm_factory().set_type_override_by_type(TestSeq, TestClkdivSeq)
+        super().build_phase()
+
+@pyuvm.test()
+class WidthTest(BasicTest):
+
+    def build_phase(self):
+        uvm_factory().set_type_override_by_type(TestSeq, WidthSeq)
         super().build_phase()
diff --git a/pyuvm_verif/utils_spi.py b/pyuvm_verif/utils_spi.py
@@ -34,6 +34,8 @@ def __init__(self):
         self.result_mon_queue = Queue(maxsize=0)
         self.data_miso = 0
         self.clk_div = 0
+        self.width_num = 0
+        self.width_en = 0
     def reverse_bits(self, number, bit_size):
         binary = bin(number)
         reverse = binary[-1:1:-1]
@@ -53,6 +55,7 @@ async def get_result(self):
         result = await self.result_mon_queue.get()
         return result
     async def cmd_mon_bfm(self):
+        global wid_end
         while True:
             await RisingEdge(self.dut.clk_test)
             wstb = get_int(self.dut.wstb)
@@ -65,11 +68,20 @@ async def cmd_mon_bfm(self):
                     if addr == 0:
                         self.sck_start  = (data & 0x01)
                         self.sck_edge   = (data & 0x02)
+                        width_bin = bin(data)[2:].zfill(8)
+                        self.width_num = int(width_bin[:5],2)
                         uvm_root().logger.info(f"SCK EDGE: {self.sck_edge}")
                         uvm_root().logger.info(f"SCK START: {self.sck_start}")
+                        uvm_root().logger.info(f"!!!WIDTH NUMBER: {self.width_num}!!!")
+                        wid_end = self.width_num + 10
                     if addr == 4:
                         self.clk_div = get_int(self.dut.wdata)
                         uvm_root().logger.info(f"CLK DIV: {self.clk_div}")
+                    if addr == 11:
+                        self.width_en = 1
+                        for i in range(0,wid_end):
+                            await FallingEdge(self.dut.clk_test)
+                        self.width_en = 0
                 else:
                     op = 2
                 cmd_tuple = (addr,
@@ -180,7 +192,6 @@ async def clkdiv_assert_bfm(self):
             wstb = get_int(self.dut.wstb)
             if wstb == 1:
                 await FallingEdge(self.dut.clk_test)
-                result = get_int(self.dut.wdata)
                 addr = get_int(self.dut.addr)
                 if addr == 11:
                     await RisingEdge(self.dut.sck)
@@ -191,8 +202,26 @@ async def clkdiv_assert_bfm(self):
                     uvm_root().logger.info(f"CLK DIVIDER MEASURED: {clk_div_measr}")
                     assert self.clk_div == (clk_div_measr-2), f"CLK DIV {self.clk_div} NOT EQUAL TO CLK DIV MEASURED {clk_div_measr-2}"
 
+    async def width_assert_bfm(self):
+        while True:
+            await RisingEdge(self.dut.clk_test)
+            wstb = get_int(self.dut.wstb)
+            if wstb == 1:
+                await FallingEdge(self.dut.clk_test)
+                addr = get_int(self.dut.addr)
+                if addr == 11:
+                    width_measer = 0
+                    while self.width_en == 1:
+                        await RisingEdge(self.dut.sck)
+                        width_measer = width_measer + 1
+                    uvm_root().logger.info(f"!!!! WIDTH OF SPI MEASURED: {width_measer} !!!!")
+                    if self.clk_div == 0:
+                        assert self.width_num == (
+                            width_measer-1), f"WIDTH {self.width_num} NOT EQUAL TO WIDTH MEASURED {width_measer-1}"
+
     def start_bfm(self):
         cocotb.start_soon(self.driver_bfm())
         cocotb.start_soon(self.cmd_mon_bfm())
         cocotb.start_soon(self.result_mon_bfm())
-        cocotb.start_soon(self.clkdiv_assert_bfm())
+        cocotb.start_soon(self.clkdiv_assert_bfm())
+        cocotb.start_soon(self.width_assert_bfm())
diff --git a/pyuvm_verif/verilog/spi_wrap.v b/pyuvm_verif/verilog/spi_wrap.v
@@ -20,7 +20,6 @@ module spi_wrap
 
   //clock generation
   bit clk_test;
-  bit wstb_test;
 
   initial clk_test = 0;
   always #5 clk_test = ~clk_test;
