Remove usage of 'design' as a path for user design

Author: robtaylor

chipflow_lib/steps/sim.py

@@ -32,14 +32,6 @@ def common():
     with importlib.resources.as_file(common) as f:
         yield f
 
-@contextmanager
-def source():
-    root = _ensure_chipflow_root()
-    sourcedir = Path(root) / 'design' / 'sim'
-    #sim_src = sourcedir.joinpath('design','sim')
-    #with importlib.resources.as_file(sim_src) as f:
-    yield sourcedir
-
 @contextmanager
 def runtime():
     yowasp = importlib.resources.files("yowasp_yosys")
@@ -128,7 +120,6 @@ def build(self, *args):
         with common() as common_dir, source() as source_dir, runtime() as runtime_dir:
             context = {
                 "COMMON_DIR": common_dir,
-                "SOURCE_DIR": source_dir,
                 "RUNTIME_DIR": runtime_dir,
                 "PROJECT_ROOT": _ensure_chipflow_root(),
                 "BUILD_DIR": _ensure_chipflow_root() / 'build',