wip

Author: robtaylor

tests/fixtures/chipflow-flexic.toml

@@ -0,0 +1,25 @@
+[chipflow]
+project_name = "proj-name"
+
+[chipflow.steps]
+silicon = "chipflow_lib.steps.silicon:SiliconStep"
+
+[chipflow.silicon]
+process = "test"
+pad_ring = "cf20"
+
+[chipflow.clocks]
+default = 'sys_clk'
+
+[chipflow.resets]
+default = 'sys_rst_n'
+
+[chipflow.silicon.pads]
+sys_clk     = { type = "clk", loc = "N3" }
+sys_rst_n    = { type = "i",   loc = "N4" }
+
+[chipflow.silicon.power]
+vss         = { loc = "N1" }
+vssio       = { loc = "N5" }
+vddio       = { loc = "N6" }
+vdd         = { loc = "N7" }

tests/fixtures/mock.toml

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+# SPDX-License-Identifier: BSD-2-Clause
+from amaranth import Module
+from amaranth.lib import wiring
+from amaranth.lib.wiring import In, Out, flipped, connect
+
+from chipflow_lib.platforms import InputPinSignature, OutputPinSignature, BidirPinSignature
+
+__all__ = ["MockTop"]
+
+TestSignature1 = wiring.Signature({
+    "a": In(InputPinSignature(1)),
+    "b": In(InputPinSignature(5)),
+    "c": Out(OutputPinSignature(1)),
+    "d": Out(OutputPinSignature(10)),
+    "e": In(BidirPinSignature(1)),
+    "f": In(BidirPinSignature(7)),
+})
+
+TestSignature2 = wiring.Signature({
+    "a": Out(OutputPinSignature(1)),
+    "b": Out(OutputPinSignature(5)),
+    "c": In(InputPinSignature(1)),
+    "d": In(InputPinSignature(10)),
+    "e": Out(BidirPinSignature(1)),
+    "f": Out(BidirPinSignature(7)),
+})
+
+
+# ---------
+
+class MockTop(wiring.Component):
+    def __init__(self):
+        # Top level interfaces
+
+        interfaces = {
+            "test1" : Out(TestSignature1),
+            "test2": Out(TestSignature2)
+        }
+
+        super().__init__(interfaces)
+
+    def elaborate(self, platform):
+        m = Module()
+        for inpin, outpin in zip(self.test1.members, self.test2.members):
+            m.d.comb += inpin.eq(outpin)
+ 
+        return m