Phase 6 (Part 2): Update imports in remaining platform modules

Updated imports in all platform modules to use new structure:
- sim.py: Updated to import from .io.signatures and ..packaging
- sim_step.py: Updated to import from .base, .utils, .sim
- software.py: Updated to import from .io.signatures, .io.annotate
- software_step.py: Updated to import from .base, .software, .utils
- board_step.py: Updated to import from .base
- platform/__init__.py: Added exports for sim, software, board modules

All platform modules now use correct internal imports. Ready for
backward compatibility shims.

🤖 Generated with [Claude Code](https://claude.com/claude-code)

Co-Authored-By: Claude <[email protected]>

Author: robtaylor

chipflow_lib/platform/__init__.py

@@ -10,16 +10,16 @@
 from .silicon import SiliconPlatformPort, SiliconPlatform
 from .silicon_step import SiliconStep, SiliconTop
 
-# Simulation platform (will be added)
-# from .sim import SimPlatform
-# from .sim_step import SimStep
+# Simulation platform
+from .sim import SimPlatform, BasicCxxBuilder
+from .sim_step import SimStep
 
-# Software platform (will be added)
-# from .software import SoftwarePlatform
-# from .software_step import SoftwareStep
+# Software platform
+from .software import SoftwarePlatform
+from .software_step import SoftwareStep
 
-# Board step (will be added)
-# from .board_step import BoardStep
+# Board step
+from .board_step import BoardStep
 
 # IO signatures and utilities
 from .io import (
@@ -40,6 +40,15 @@
     'SiliconPlatform',
     'SiliconStep',
     'SiliconTop',
+    # Simulation
+    'SimPlatform',
+    'BasicCxxBuilder',
+    'SimStep',
+    # Software
+    'SoftwarePlatform',
+    'SoftwareStep',
+    # Board
+    'BoardStep',
     # IO
     'IO_ANNOTATION_SCHEMA',
     'IOSignature',

chipflow_lib/platform/board_step.py

@@ -1,5 +1,5 @@
 # SPDX-License-Identifier: BSD-2-Clause
-from . import StepBase, setup_amaranth_tools
+from .base import StepBase, setup_amaranth_tools
 
 class BoardStep(StepBase):
     """Build the design for a board."""

chipflow_lib/platform/sim.py

@@ -18,12 +18,12 @@
 from jinja2 import Environment, PackageLoader, select_autoescape
 from pydantic import BaseModel, TypeAdapter
 
-from .. import ChipFlowError, _ensure_chipflow_root
-from ._signatures import (
+from ..utils import ChipFlowError, ensure_chipflow_root
+from .io.signatures import (
         I2CSignature, GPIOSignature, UARTSignature, SPISignature, QSPIFlashSignature,
         SIM_ANNOTATION_SCHEMA, DATA_SCHEMA, SimInterface, SoftwareBuild
         )
-from ._utils import load_pinlock, Interface
+from ..packaging import load_pinlock, Interface
 
 
 logger = logging.getLogger(__name__)
@@ -153,7 +153,7 @@ def find_builder(builders: List[BasicCxxBuilder], sim_interface: SimInterface):
 
 class SimPlatform:
     def __init__(self, config):
-        self.build_dir = _ensure_chipflow_root() / 'build' / 'sim'
+        self.build_dir = ensure_chipflow_root() / 'build' / 'sim'
         self.extra_files = dict()
         self.sim_boxes = dict()
         self._ports: Dict[str, io.SimulationPort] = {}
@@ -225,7 +225,7 @@ def build(self, e, top):
             args = [f"0x{d.offset:X}U"]
             p = d.filename
             if not p.is_absolute():
-                p = _ensure_chipflow_root() / p
+                p = ensure_chipflow_root() / p
             data_load.append({'model_name': i, 'file_name': p, 'args': args})
 
 

chipflow_lib/platform/sim_step.py

@@ -12,12 +12,13 @@
 
 from amaranth import Module
 
-from . import StepBase, _wire_up_ports
-from ._json_compare import compare_events
-from .. import ChipFlowError, _ensure_chipflow_root
+from .base import StepBase, _wire_up_ports
+from .utils import top_components
+from .sim import VARIABLES, TASKS, DOIT_CONFIG, SimPlatform
+from ..steps._json_compare import compare_events
+from ..utils import ChipFlowError, ensure_chipflow_root
 from ..cli import run
-from ..platforms._utils import top_components, load_pinlock
-from ..platforms.sim import VARIABLES, TASKS, DOIT_CONFIG, SimPlatform
+from ..packaging import load_pinlock
 
 
 EXE = ".exe" if os.name == "nt" else ""
@@ -92,7 +93,7 @@ def run_cli(self, args):
 
     @property
     def sim_dir(self):
-        return _ensure_chipflow_root() / 'build' / 'sim'
+        return ensure_chipflow_root() / 'build' / 'sim'
 
     def build(self, *args):
         """
@@ -120,8 +121,8 @@ def build(self, *args):
             context = {
                 "COMMON_DIR": common_dir,
                 "RUNTIME_DIR": runtime_dir,
-                "PROJECT_ROOT": _ensure_chipflow_root(),
-                "BUILD_DIR": _ensure_chipflow_root() / 'build',
+                "PROJECT_ROOT": ensure_chipflow_root(),
+                "BUILD_DIR": ensure_chipflow_root() / 'build',
                 "EXE": EXE,
                 }
             for k,v in VARIABLES.items():

chipflow_lib/platform/software.py

@@ -11,9 +11,9 @@
 from amaranth_soc.wishbone.sram import WishboneSRAM
 from pydantic import TypeAdapter
 
-from .. import ChipFlowError
-from ._signatures import DRIVER_MODEL_SCHEMA, DriverModel, DATA_SCHEMA, SoftwareBuild
-from ._annotate import submodule_metadata
+from ..utils import ChipFlowError
+from .io.signatures import DRIVER_MODEL_SCHEMA, DriverModel, DATA_SCHEMA, SoftwareBuild
+from .io.annotate import submodule_metadata
 from ..software.soft_gen import SoftwareGenerator
 
 

chipflow_lib/platform/software_step.py

@@ -6,10 +6,10 @@
 from doit.doit_cmd import DoitMain
 from amaranth import Module
 
-from . import StepBase
-from .. import ChipFlowError
-from ..platforms._software import SoftwarePlatform
-from ..platforms._utils import top_components
+from .base import StepBase
+from .software import SoftwarePlatform
+from .utils import top_components
+from ..utils import ChipFlowError
 
 logger = logging.getLogger(__name__)
 
@@ -42,7 +42,7 @@ def build(self, *args):
 
         generators = self._platform.build(m, top)
 
-        from ..platforms import software_build
+        from . import software_build
         for name, gen in generators.items():
             loader = ModuleTaskLoader(software_build)
             loader.task_opts = {"build_software": {"generator": gen}, "build_software_elf": {'generator': gen}}  #type: ignore