wip: enable a a bidir port to have either one output enable, or one for each wire

Author: robtaylor

chipflow_lib/platforms/utils.py

@@ -65,18 +65,23 @@ def as_json(self):  # type: ignore
 
 class PinSignature(wiring.Signature):
     """Amaranth Signtaure used to decorate wires that would
-    usually be brought out onto a pin on the package.
+    usually be brought out onto a port on the package.
+
+    direction: Input, Output or Bidir
+    width: width of port
+    all_have_oe: For Bidir ports, should Output Enable be per wire or for the whole port
+    init: a  :ref:`const-castable object <lang-constcasting>` for the initial values of the port
     """
 
-    def __init__(self, direction, width=1, init=None):
+    def __init__(self, direction: io.Direction, width: int = 1, all_have_oe: bool = False, init = None):
         self._direction = direction
         self._width = width
         self._init = init
         match direction:
             case io.Direction.Bidir:
                 sig = {
                     "o": Out(width),
-                    "oe": Out(1),
+                    "oe": Out(width if all_have_oe else 1),
                     "i": In(width)
                 }
             case io.Direction.Input: