Add OpenframePackageDef to available packages

Author: robtaylor

chipflow_lib/_appresponse.py

@@ -13,7 +13,7 @@ def _serialize(self):
         serialize_aliases = dict()
 
         # Gather fields that should omit if None
-        for name, field_info in self.__class__.model_fields.items():
+        for name, field_info in self.model_fields.items():
             if any(
                 isinstance(metadata, OmitIfNone) for metadata in field_info.metadata
             ):
@@ -30,9 +30,9 @@ def _serialize(self):
             serialize_key = serialize_aliases.get(name, name)
 
             # Run Annotated PlainSerializer
-            for metadata in self.__class__.model_fields[name].metadata:
+            for metadata in self.model_fields[name].metadata:
                 if isinstance(metadata, PlainSerializer):
-                    value = metadata.func(value)  # type: ignore
+                    value = metadata.func(value)
 
             serialized[serialize_key] = value
 

chipflow_lib/platforms/_openframe.py

@@ -106,7 +106,7 @@ def model_post_init(self, __context):
 
 
     @property
-    def core_power(self) -> List[PowerPins]:
+    def _core_power(self) -> List[PowerPins]:
         pps = []
 
         for power, ground in OF_CORE_POWER:
@@ -118,7 +118,7 @@ def core_power(self) -> List[PowerPins]:
     @property
     def bringup_pins(self) -> BringupPins:
         return BringupPins(
-            core_power=self.core_power,
+            core_power=self._core_power,
             core_clock=OF_CLOCK_PIN,
             core_reset=OF_RESET_PIN,
             core_heartbeat=OF_HEARTBEAT_PIN,

chipflow_lib/platforms/_packages.py

@@ -1,11 +1,11 @@
-from .utils import QuadPackageDef, BareDiePackageDef
+from .utils import QuadPackageDef, BareDiePackageDef, GAPackageDef, Package
 from ._openframe import OpenframePackageDef
 
-
 # Add any new package types to both PACKAGE_DEFINITIONS and the PackageDef union
 PACKAGE_DEFINITIONS = {
     "pga144": QuadPackageDef(name="pga144", width=36, height=36),
     "cf20": BareDiePackageDef(name="cf20", width=7, height=3),
     "openframe": OpenframePackageDef()
 }
 
+Package.model_rebuild()

chipflow_lib/platforms/silicon.py

@@ -279,14 +279,14 @@ def instantiate_ports(self, m: Module):
                     self._ports[port.port_name] = SiliconPlatformPort(component, name, port)
 
         for clock in pinlock.port_map.get_clocks():
-            domain = name=clock.iomodel['clock_domain_o']
+            domain = name=clock.iomodel['clock_domain']
             setattr(m.domains, domain, ClockDomain(name=domain))
             clk_buffer = io.Buffer("i", self._ports[clock.port_name])
             setattr(m.submodules, "clk_buffer_" + domain, clk_buffer)
             m.d.comb += ClockSignal().eq(clk_buffer.i)  #type: ignore[reportAttributeAccessIssue]
 
         for reset in pinlock.port_map.get_resets():
-            domain = name=clock.iomodel['clock_domain_o']
+            domain = name=clock.iomodel['clock_domain']
             rst_buffer = io.Buffer("i", self._ports[reset.port_name])
             setattr(m.submodules, reset.port_name, rst_buffer)
             setattr(m.submodules, reset.port_name + "_sync", FFSynchronizer(rst_buffer.i, ResetSignal()))  #type: ignore[reportAttributeAccessIssue]

chipflow_lib/platforms/sim.py

@@ -81,17 +81,17 @@ def instantiate_ports(self, m: Module):
                    self._ports[port.port_name] = io.SimulationPort(port.direction, port.width, invert=invert, name=f"{component}-{name}")
 
         for clock in pinlock.port_map.get_clocks():
-            assert 'clock_domain_o' in clock.iomodel
-            domain = clock.iomodel['clock_domain_o']
+            assert 'clock_domain' in clock.iomodel
+            domain = clock.iomodel['clock_domain']
             logger.debug(f"Instantiating clock buffer for {clock.port_name}, domain {domain}")
             setattr(m.domains, domain, ClockDomain(name=domain))
             clk_buffer = io.Buffer(clock.direction, self._ports[clock.port_name])
             setattr(m.submodules, "clk_buffer_" + clock.port_name, clk_buffer)
             m.d.comb += ClockSignal().eq(clk_buffer.i)  # type: ignore[reportAttributeAccessIssue]
 
         for reset in pinlock.port_map.get_resets():
-            assert 'clock_domain_o' in reset.iomodel
-            domain = reset.iomodel['clock_domain_o']
+            assert 'clock_domain' in reset.iomodel
+            domain = reset.iomodel['clock_domain']
             logger.debug(f"Instantiating reset synchronizer for {reset.port_name}, domain {domain}")
             rst_buffer = io.Buffer(reset.direction, self._ports[clock.port_name])
             setattr(m.submodules, reset.port_name, rst_buffer)

chipflow_lib/platforms/utils.py

@@ -34,6 +34,7 @@
 
 if TYPE_CHECKING:
     from ..config_models import Config
+    from ._openframe import OpenframePackageDef
 
 
 logger = logging.getLogger(__name__)
@@ -334,12 +335,13 @@ class BringupPins:
     core_clock: Pin
     core_reset: Pin
     core_heartbeat: Pin
-    core_jtag: JTAGPins
+    core_jtag: Optional[JTAGPins] = None
 
     def to_set(self) -> Set[Pin]:
+        jtag = self.core_jtag.to_set() if self.core_jtag else set()
         return {p for pp in self.core_power for p in asdict(pp).values()} | \
                set([self.core_clock, self.core_reset, self.core_heartbeat]) | \
-               self.core_jtag.to_set()
+               jtag
 
 
 class _Side(IntEnum):
@@ -378,8 +380,10 @@ def direction(self):
     @property
     def invert(self) -> Iterable[bool] | None:
         if 'invert' in self.iomodel:
-            assert type(self.iomodel['invert']) is tuple
-            return self.iomodel['invert']
+            if type(self.iomodel['invert']) is bool:
+                return (self.iomodel['invert'],)
+            else:
+                return self.iomodel['invert']
         else:
             return None
 
@@ -513,7 +517,7 @@ def _allocate_pins(name: str, member: Dict[str, Any], pins: List[Pin], port_name
 Interface = Dict[str, Port]
 Component = Dict[str, Interface]
 
-class PortMap(AppResponseModel):
+class PortMap(pydantic.BaseModel):
     ports: Dict[str, Component] = {}
 
     def _add_port(self, component: str, interface: str, port_name: str, port: Port):
@@ -571,7 +575,7 @@ class LockFile(pydantic.BaseModel):
     metadata: dict
 
 
-PackageDef = Union['GAPackageDef', 'QuadPackageDef', 'BareDiePackageDef']
+PackageDef = Union['GAPackageDef', 'QuadPackageDef', 'BareDiePackageDef', 'OpenframePackageDef']
 
 class Package(pydantic.BaseModel):
     """