maybe working...

Author: robtaylor

chipflow_lib/pin_lock.py

@@ -29,14 +29,15 @@ def lock_pins() -> None:
     # Get package definition from dict instead of Pydantic model
     package_name = config_dict["chipflow"]["silicon"]["package"]
     package_def = PACKAGE_DEFINITIONS[package_name]
+    process = config_dict["chipflow"]["silicon"]["process"]
 
     top = top_components(config_dict)
 
     # Use the PackageDef to allocate the pins:
     for name, component in top.items():
         package_def.register_component(name, component)
 
-    newlock = package_def.allocate_pins(oldlock)
+    newlock = package_def.allocate_pins(process, oldlock)
 
     with open(lockfile, 'w') as f:
         f.write(newlock.model_dump_json(indent=2, serialize_as_any=True))
@@ -47,9 +48,10 @@ def __init__(self, config):
         self.config = config
 
     def build_cli_parser(self, parser):
+        assert inspect.getdoc(self.lock) is not None
         action_argument = parser.add_subparsers(dest="action")
         action_argument.add_parser(
-            "lock", help=inspect.getdoc(self.lock).splitlines()[0])
+            "lock", help=inspect.getdoc(self.lock).splitlines()[0])  # type: ignore
 
     def run_cli(self, args):
         logger.debug(f"command {args}")

chipflow_lib/platforms/utils.py

@@ -88,7 +88,7 @@ class IOModel(TypedDict):
     """
 
     width: NotRequired[int]
-    direction: NotRequired[io.Direction]
+    direction: NotRequired[Annotated[io.Direction, PlainSerializer(lambda x: str(x))]]
     all_have_oe: NotRequired[bool]
     allocate_power: NotRequired[bool]
     power_voltage: NotRequired[VoltageRange]
@@ -214,7 +214,7 @@ def BidirIOSignature(width:int , **kwargs: Unpack[IOModel]):
     return IOSignature(**kwargs)
 
 
-Pin = Union[tuple, str, int]
+Pin = Union[Tuple[Any,...], str, int]
 PinSet = Set[Pin]
 PinList = List[Pin]
 Pins = Union[PinSet, PinList]
@@ -400,12 +400,9 @@ def _allocate_pins(name: str, member: Dict[str, Any], pins: List[str], port_name
         logger.debug(f"matched PinSignature {sig}")
         name = name
         width = sig['width']
-        options = sig['options']
         pin_map[name] = {'pins': pins[0:width],
-                         'direction': sig['direction'],
                          'type': 'io',
-                         'port_name': port_name,
-                         'options': options}
+                         'port_name': port_name } | sig
         logger.debug(f"added '{name}':{pin_map[name]} to pin_map")
         return pin_map, pins[width:]
     elif member['type'] == 'interface':
@@ -501,17 +498,16 @@ class LockFile(pydantic.BaseModel):
     metadata: dict
 
 
-PackageDef = Union['GAPackageDef', 'QuadPackageDef', 'BareDiePackageDef', 'BasePackageDef']
-
+PackageDef = Union['GAPackageDef', 'QuadPackageDef', 'BareDiePackageDef']
 
 class Package(pydantic.BaseModel):
     """
     Serialisable identifier for a defined packaging option
     """
-    package_type: PackageDef = pydantic.Field(discriminator="package_type")
+    type: PackageDef = pydantic.Field(discriminator="package_type")
 
 
-def _linear_allocate_components(interfaces: dict, lockfile: LockFile , allocate, unallocated) -> PortMap:
+def _linear_allocate_components(interfaces: dict, lockfile: LockFile | None, allocate, unallocated) -> PortMap:
     port_map = PortMap()
     for component, iface in interfaces.items():
         for k, v in iface['interface']['members'].items():
@@ -534,7 +530,7 @@ def _linear_allocate_components(interfaces: dict, lockfile: LockFile , allocate,
             else:
                 pins = allocate(unallocated, width)
                 if len(pins) == 0:
-                    raise ChipFlowError("No pins were allocated by {package}")
+                    raise ChipFlowError("No pins were allocated")
                 logger.debug(f"allocated range: {pins}")
                 unallocated = unallocated - set(pins)
                 _map, _ = _allocate_pins(k, v, pins)
@@ -558,9 +554,6 @@ class BasePackageDef(pydantic.BaseModel, abc.ABC):
 
     """
 
-     # Used by pydantic to differentate when deserialising,
-    # override appropriately when you subclass
-    package_type: Literal["BasePackageDef"] = "BasePackageDef"
     name: str
 
     def model_post_init(self, __context):
@@ -579,7 +572,7 @@ def register_component(self, name: str, component: wiring.Component) -> None:
 
 
     @abc.abstractmethod
-    def allocate_pins(self, lockfile: Optional[LockFile]) -> LockFile:
+    def allocate_pins(self, process: 'Process', lockfile: Optional[LockFile]) -> LockFile:
         """
         Allocate package pins to the registered component.
         Pins should be allocated in the most usable way for *users* of the packaged IC.
@@ -622,16 +615,16 @@ class BareDiePackageDef(BasePackageDef):
     height: int
 
     def model_post_init(self, __context):
-        pins = (
-            set(itertools.product((_Side.N, _Side.S), range(self.width)))
-            | set(itertools.product((_Side.W, _Side.E), range(self.height)))
-            - set(self.bringup_pins.to_set())
-        )
-        self._ordered_pins = sorted(pins)
+        pins = set(itertools.product((_Side.N, _Side.S), range(self.width)))
+        pins |= set(itertools.product((_Side.W, _Side.E), range(self.height)))
+        pins -= set(self.bringup_pins.to_set())
+
+        self._ordered_pins: List[Pin] = sorted(pins)
         return super().model_post_init(__context)
 
-    def allocate_pins(self, lockfile: LockFile|None) -> 'LockFile':
-        return _linear_allocate_components(self._interfaces, lockfile, self._allocate, set(self._ordered_pins))
+    def allocate_pins(self, process: 'Process', lockfile: LockFile|None) -> LockFile:
+        portmap =  _linear_allocate_components(self._interfaces, lockfile, self._allocate, set(self._ordered_pins))
+        return LockFile(package=Package(type=self), process=process, metadata=self._interfaces, port_map=portmap)
 
     @property
     def bringup_pins(self) -> BringupPins:
@@ -703,19 +696,20 @@ class QuadPackageDef(BasePackageDef):
     allocate_jtag: bool = True
 
     def model_post_init(self, __context):
-        pins =(
-            set([i for i in range(1, self.width * 2 + self.height * 2)])
-            - set(self._power)
-            - self._jtag.to_set()
-        )
-        self._ordered_pins = sorted(pins)
+        pins = set([i for i in range(1, self.width * 2 + self.height * 2)])
+        pins.difference_update(*[x.to_set() for x in self._power])
+        pins.difference_update(self._jtag.to_set())
+
+        self._ordered_pins: List[Pin] = sorted(pins)
         return super().model_post_init(__context)
 
-    def allocate_pins(self, lockfile: LockFile|None) -> 'LockFile':
-        return _linear_allocate_components(self._interfaces, lockfile, self._allocate, set(self._ordered_pins))
+    def allocate_pins(self, process: 'Process', lockfile: LockFile|None) -> 'LockFile':
+        portmap = _linear_allocate_components(self._interfaces, lockfile, self._allocate, set(self._ordered_pins))
+        return LockFile(package=Package(type=self), process=process, metadata=self._interfaces, port_map=portmap)
 
-    def _allocate(self, available: Set[int], width: int) -> List[int]:
-        avail_n = sorted(available)
+
+    def _allocate(self, available: Set[int], width: int) -> List[Pin]:
+        avail_n: List[Pin] = sorted(available)
         logger.debug(f"QuadPackageDef.allocate {width} from {len(avail_n)} remaining: {available}")
         ret = _find_contiguous_sequence(self._ordered_pins, avail_n, width)
         logger.debug(f"QuadPackageDef.returned {ret}")
@@ -743,19 +737,23 @@ def _power(self) -> List[PowerPins]:
         pins = []
         n = (self.width + self.height)//12
         # Left
-        pins.append(self.height//2 + self.height//2 +1)
+        p = self.height//2 + self.height//2
+        pins.append(PowerPins(p, p +1))
         # Bottom
         start = self.height
         if n > 2:
-            pins.append(start + self.width//2 + self.width//2 +1)
+            p = start + self.width//2 + self.width//2
+            pins.append(PowerPins(p, p+1))
         # Right
         start = start + self.width
         if n > 1:
-            pins.append(start + self.height//2 + self.height//2 +1)
+            p = start + self.height//2 + self.height//2
+            pins.append(PowerPins(p, p+1))
         # Top
         start = start + self.height
         if n > 3:
-            pins.append(start + self.width//2 + self.width//2 +1)
+            p = start + self.width//2 + self.width//2
+            pins.append(PowerPins(p, p+1))
         return pins
 
 
@@ -861,11 +859,11 @@ def int_to_alpha(i: int):
                 out = valid_letters[char-1] + out
             return out
 
-        def pins_for_range(h1: int, h2: int, w1: int, w2: int) -> Set[GAPin]:
+        def pins_for_range(h1: int, h2: int, w1: int, w2: int) -> Set[Pin]:
             pins = [GAPin(int_to_alpha(h),w) for h in range(h1, h2) for w in range(w1, w2)]
             return set(pins)
 
-        def sort_by_quadrant(pins: Set[GAPin]) -> List[GAPin]:
+        def sort_by_quadrant(pins: Set[GAPin]) -> List[Pin]:
             quadrants:List[Set[GAPin]] = [set(), set(), set(), set()]
             midline_h = int_to_alpha(self.height // 2)
             midline_w = self.width // 2
@@ -883,6 +881,7 @@ def sort_by_quadrant(pins: Set[GAPin]) -> List[GAPin]:
                 ret.append(sorted(quadrants[q]))
             return ret
 
+        self._ordered_pins: List[Pin] = []
         match self.layout_type:
             case GALayout.FULL:
                 pins = pins_for_range(1, self.height, 1, self.width)
@@ -917,8 +916,9 @@ def sort_by_quadrant(pins: Set[GAPin]) -> List[GAPin]:
         return super().model_post_init(__context)
 
 
-    def allocate_pins(self, lockfile: LockFile|None) -> 'LockFile':
-        return _linear_allocate_components(self._interfaces, lockfile, self._allocate, set(self._ordered_pins))
+    def allocate_pins(self, process: 'Process', lockfile: LockFile|None) -> 'LockFile':
+        portmap = _linear_allocate_components(self._interfaces, lockfile, self._allocate, set(self._ordered_pins))
+        return LockFile(package=Package(type=self), process=process, metadata=self._interfaces, port_map=portmap)
 
     def _allocate(self, available: Set[str], width: int) -> List[str]:
         avail_n = sorted(available)

docs/package_pins.md

@@ -42,7 +42,7 @@ tms_pin = jtag_pins[JTAGWireName.TMS]  # Get the TMS pin
 ### Creating a Package with Default Pins
 
 ```python
-from chipflow_lib.platforms.utils import Package, PACKAGE_DEFINITIONS
+from chipflow_lib.platforms.utils import PACKAGE_DEFINITIONS
 
 # Create a package with a specific package definition
 package = Package(package_type=PACKAGE_DEFINITIONS["pga144"])

tests/test_package_pins.py

@@ -78,26 +78,23 @@ def test_bringup_pins(self):
 class TestPackage(unittest.TestCase):
     def setUp(self):
         self.package_def = BareDiePackageDef(name="test_package", width=8, height=4)
-        self.package = Package(package_type=self.package_def)
+        self.package = Package(type=self.package_def)
 
     def test_package_initialization(self):
         """Test basic package initialization"""
-        self.assertIsNotNone(self.package.package_type)
-        self.assertEqual(self.package.package_type.name, "test_package")
-        self.assertEqual(self.package.package_type.width, 8)
-        self.assertEqual(self.package.package_type.height, 4)
+        self.assertIsNotNone(self.package.type)
+        self.assertEqual(self.package.type.name, "test_package")
+        self.assertEqual(self.package.type.width, 8)
+        self.assertEqual(self.package.type.height, 4)
 
     def test_package_type_access(self):
         """Test accessing package type properties through Package"""
         # Should be able to access package type bringup pins
-        bringup_pins = self.package.package_type.bringup_pins
+        bringup_pins = self.package.type.bringup_pins
         self.assertIsNotNone(bringup_pins)
 
         # Test package discriminator
-        self.assertEqual(self.package.package_type.package_type, "BareDiePackageDef")
-
-        # Basic test of Package structure
-        self.assertIsInstance(self.package.package_type, BareDiePackageDef)
+        self.assertEqual(self.package.type.package_type, "BareDiePackageDef")
 
 
 class TestGAPackage(unittest.TestCase):

tests/test_steps_silicon.py

@@ -25,12 +25,10 @@
 DEFAULT_PINLOCK = {
     "process" : "ihp_sg13g2",
     "package" : {
-        "package_type": {
         "package_type": "QuadPackageDef",
         "name": "pga144",
         "width": 36,
         "height": 36
-        },
     },
     "port_map" : {},
     "metadata" : {},