Set reset port to inverted on simulation and silicon

Author: robtaylor

chipflow_lib/platforms/silicon.py

@@ -286,7 +286,7 @@ def instantiate_ports(self, m: Module):
 
         for reset, name in self._config["chipflow"]["resets"].items():
             port_data = pinlock.package.resets[name]
-            port = SiliconPlatformPort(component, name, port_data)
+            port = SiliconPlatformPort(component, name, port_data, invert=True)
             self._ports[name] = port
             rst_buffer = io.Buffer("i", port)
             setattr(m.submodules, reset, rst_buffer)

chipflow_lib/platforms/sim.py

@@ -93,7 +93,7 @@ def instantiate_ports(self, m: Module):
 
         for reset, name in self._config["chipflow"]["resets"].items():
             port_data = pinlock.package.resets[name]
-            port = io.SimulationPort(io.Direction.Input, port_data.width, name=f"reset-{name}", )
+            port = io.SimulationPort(io.Direction.Input, port_data.width, name=f"reset-{name}", invert=True)
             self._ports[name] = port
             rst_buffer = io.Buffer("i", port)
             setattr(m.submodules, reset, rst_buffer)

chipflow_lib/steps/__init__.py

@@ -1,14 +1,16 @@
 """
 Steps provide an extensible way to modify the `chipflow` command behavior for a given design
 """
-
+import logging
 import os
 from abc import ABC
 
 from amaranth import Module
 
 from ..platforms.utils import IOSignature
 
+logger = logging.getLogger(__name__)
+
 def setup_amaranth_tools():
     _amaranth_settings = {
         "AMARANTH_USE_YOSYS": "system",
@@ -43,12 +45,17 @@ def run_cli(self, args):
 
 
 def _wire_up_ports(m: Module, top, platform):
+    logger.debug("wiring up ports")
+    logger.debug("adding top:")
     for n, t in top.items():
+        logger.debug(f"    > {n}, {t}")
         setattr(m.submodules, n, t)
 
+    logger.debug("wiring up:")
     for component, iface in platform._pinlock.port_map.items():
         for iface_name, member, in iface.items():
             for name, port in member.items():
+                logger.debug(f"    > {component}, {iface_name}, {member}")
                 iface = getattr(top[component], iface_name)
                 wire = (iface if isinstance(iface.signature, IOSignature)
                         else getattr(iface, name))