Make PortMap more normal

Author: robtaylor

chipflow_lib/pin_lock.py

@@ -3,6 +3,7 @@
 import logging
 
 from pathlib import Path
+from pprint import pformat
 
 from chipflow_lib import _parse_config, _ensure_chipflow_root
 from chipflow_lib.platforms import top_components, LockFile, PACKAGE_DEFINITIONS
@@ -23,7 +24,7 @@ def lock_pins() -> None:
 
     if lockfile.exists():
         oldlock = LockFile.model_validate_json(lockfile.read_text())
-
+    print(f"Old Lock =\n{pformat(oldlock)}")
     print(f"Locking pins: {'using pins.lock' if lockfile.exists() else ''}")
 
     # Get package definition from dict instead of Pydantic model

chipflow_lib/platforms/utils.py

@@ -285,7 +285,7 @@ def __str__(self):
 
 class Port(pydantic.BaseModel):
     type: str
-    pins: List[str] | None  # None implies must be allocated at end
+    pins: List[Pin] | None  # None implies must be allocated at end
     port_name: str
     direction: Optional[io.Direction] = None
     options: Optional[dict] = None
@@ -430,57 +430,28 @@ def _allocate_pins(name: str, member: Dict[str, Any], pins: List[str], port_name
 Interface = Dict[str, Port]
 Component = Dict[str, Interface]
 
-class PortMap(MutableMapping[str, Component]):
-    def __init__(self, data = {}):
-        self.map: Dict[str, Component]  = data
-        return super().__init__()
-    "Represents a mapping of `Port`s to Package pins, grouped by `Component` and  `Interface`"
-    def __getitem__(self, key: str):
-        "Gets an `Component` from the map by name"
-        return self.map[key]
-
-    def __setitem__(self, key: str, value: Component):
-        "Adds or modifies a `Component` in the map by name"
-        self.map[key] = value
-
-    def __delitem__(self, key: str):
-        "Deletes a `Component` in the map by name"
-        del self.map[key]
-
-    def __iter__(self):
-        "Iterates `Component`s in the map by name"
-        return iter(self.map)
-
-    def __len__(self):
-        return len(self.map)
+class PortMap(pydantic.BaseModel):
+    ports: Dict[str, Component] = {}
 
     def _add_port(self, component: str, interface: str, port_name: str, port: Port):
         "Internally used by a `PackageDef`"
-        if component not in self:
-            self[component] = {}
-        if interface not in self[component]:
-            self[component][interface] = {}
-        self[component][interface][port_name] = port
+        if component not in self.ports:
+            self.ports[component] = {}
+        if interface not in self.ports[component]:
+            self.ports[component][interface] = {}
+        self.ports[component][interface][port_name] = port
 
     def _add_ports(self, component: str, interface: str, ports: Dict[str, Port]):
         "Internally used by a `PackageDef`"
-        if component not in self:
-            self[component] = {}
-        self[component][interface] = ports
+        if component not in self.ports:
+            self.ports[component] = {}
+        self.ports[component][interface] = ports
 
     def get_ports(self, component: str, interface: str) -> Dict[str, Port]:
         "List the ports allocated in this PortMap for the given `Component` and `Interface`"
-        if component not in self:
+        if component not in self.ports:
             raise KeyError(f"'{component}' not found in {self}")
-        return self[component][interface]
-
-    @classmethod
-    def __get_pydantic_core_schema__(cls, source_type: Any, handler: GetCoreSchemaHandler):
-         return core_schema.dict_schema(
-            keys_schema=core_schema.str_schema(),
-            values_schema=core_schema.any_schema()
-        )
-
+        return self.ports[component][interface]
 
 
 class LockFile(pydantic.BaseModel):

tests/test_package_pins.py

@@ -50,7 +50,6 @@ def test_basic_properties(self):
         self.assertEqual(self.package.width, 36)
         self.assertEqual(self.package.height, 36)
         self.assertEqual(self.package.package_type, "QuadPackageDef")
-        self.assertTrue(self.package.allocate_jtag)  # Default should be True
 
     def test_bringup_pins(self):
         """Test bringup pins configuration"""

tests/test_utils_additional.py

@@ -87,34 +87,34 @@ def test_portmap_creation(self):
         }
 
         # Create a PortMap
-        port_map = PortMap(data)
+        port_map = PortMap(ports=data)
 
         # Basic checks
-        self.assertEqual(len(port_map), 1)
-        self.assertIn("comp1", port_map)
-        self.assertIn("iface1", port_map["comp1"])
-        self.assertIn("port1", port_map["comp1"]["iface1"])
-        self.assertEqual(port_map["comp1"]["iface1"]["port1"], port1)
+        self.assertEqual(len(port_map.ports), 1)
+        self.assertIn("comp1", port_map.ports)
+        self.assertIn("iface1", port_map.ports["comp1"])
+        self.assertIn("port1", port_map.ports["comp1"]["iface1"])
+        self.assertEqual(port_map.ports["comp1"]["iface1"]["port1"], port1)
 
     def test_portmap_mutable_mapping(self):
         """Test PortMap MutableMapping methods"""
         # Create an empty PortMap
-        port_map = PortMap({})
+        port_map = PortMap()
 
         # Test __setitem__ and __getitem__
-        port_map["comp1"] = {"iface1": {"port1": Port(type="input", pins=["1"], port_name="port1")}}
-        self.assertIn("comp1", port_map)
-        self.assertEqual(port_map["comp1"]["iface1"]["port1"].pins, ["1"])
+        port_map.ports["comp1"] = {"iface1": {"port1": Port(type="input", pins=["1"], port_name="port1")}}
+        self.assertIn("comp1", port_map.ports)
+        self.assertEqual(port_map.ports["comp1"]["iface1"]["port1"].pins, ["1"])
 
         # Test __delitem__
-        del port_map["comp1"]
-        self.assertNotIn("comp1", port_map)
+        del port_map.ports["comp1"]
+        self.assertNotIn("comp1", port_map.ports)
 
         # Test __iter__ and __len__
-        port_map["comp1"] = {"iface1": {}}
-        port_map["comp2"] = {"iface2": {}}
-        self.assertEqual(len(port_map), 2)
-        self.assertEqual(set(port_map), {"comp1", "comp2"})
+        port_map.ports["comp1"] = {"iface1": {}}
+        port_map.ports["comp2"] = {"iface2": {}}
+        self.assertEqual(len(port_map.ports), 2)
+        self.assertEqual(set(port_map.ports), {"comp1", "comp2"})
 
     def test_portmap_methods(self):
         """Test PortMap helper methods"""
@@ -125,10 +125,10 @@ def test_portmap_methods(self):
         port1 = Port(type="input", pins=["1"], port_name="port1", direction=io.Direction.Input)
         port_map._add_port("comp1", "iface1", "port1", port1)
 
-        self.assertIn("comp1", port_map)
-        self.assertIn("iface1", port_map["comp1"])
-        self.assertIn("port1", port_map["comp1"]["iface1"])
-        self.assertEqual(port_map["comp1"]["iface1"]["port1"], port1)
+        self.assertIn("comp1", port_map.ports)
+        self.assertIn("iface1", port_map.ports["comp1"])
+        self.assertIn("port1", port_map.ports["comp1"]["iface1"])
+        self.assertEqual(port_map.ports["comp1"]["iface1"]["port1"], port1)
 
         # Test _add_ports with a new interface
         ports = {
@@ -137,9 +137,9 @@ def test_portmap_methods(self):
         }
         port_map._add_ports("comp1", "iface2", ports)
 
-        self.assertIn("iface2", port_map["comp1"])
-        self.assertEqual(len(port_map["comp1"]["iface2"]), 2)
-        self.assertEqual(port_map["comp1"]["iface2"]["port2"].pins, ["2"])
+        self.assertIn("iface2", port_map.ports["comp1"])
+        self.assertEqual(len(port_map.ports["comp1"]["iface2"]), 2)
+        self.assertEqual(port_map.ports["comp1"]["iface2"]["port2"].pins, ["2"])
 
         # Test get_ports
         result = port_map.get_ports("comp1", "iface1")