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1 parent 9ac25b6 commit 3efd206Copy full SHA for 3efd206
chipflow_lib/steps/silicon.py
@@ -20,12 +20,12 @@
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class SiliconTop(Elaboratable):
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def __init__(self, config={}):
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self._config = config
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- self._clocks = config["chipflow"]["silicon"]["clocks"]
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- self._reset = config["chipflow"]["silicon"]["reset"]
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- def elaborate(self, platform):
+ def elaborate(self, platform: SiliconPlatform):
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m = Module()
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+ platform.instantiate_ports()
+
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for clock, pin in self._clocks.items():
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if clock == 'default':
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clock = 'sync'
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