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chipflow_lib/steps/silicon.py

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -20,12 +20,12 @@
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class SiliconTop(Elaboratable):
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def __init__(self, config={}):
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self._config = config
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self._clocks = config["chipflow"]["silicon"]["clocks"]
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self._reset = config["chipflow"]["silicon"]["reset"]
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26-
def elaborate(self, platform):
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def elaborate(self, platform: SiliconPlatform):
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m = Module()
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platform.instantiate_ports()
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for clock, pin in self._clocks.items():
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if clock == 'default':
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clock = 'sync'

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