Enable various pyright checks and fix code for them

Author: robtaylor

chipflow_lib/platforms/silicon.py

@@ -386,18 +386,15 @@ def elaborate(self, platform):
                 m.d.comb += o_inv.eq(self.o ^ invert)
             else:
                 o_inv = self.o
+            m.d.comb += self.port.o.eq(o_inv)
+            m.d.comb += self.port.oe.eq(self.oe)
         if self.direction is not io.Direction.Output:
             if invert:
                 i_inv = Signal.like(self.i)
                 m.d.comb += self.i.eq(i_inv ^ invert)
             else:
                 i_inv = self.i
-
-        if self.direction in (io.Direction.Input, io.Direction.Bidir):
             m.d.comb += i_inv.eq(self.port.i)
-        if self.direction in (io.Direction.Output, io.Direction.Bidir):
-            m.d.comb += self.port.o.eq(o_inv)
-            m.d.comb += self.port.oe.eq(self.oe)
 
         return m
 

chipflow_lib/platforms/sim.py

@@ -5,7 +5,7 @@
 import sys
 from pathlib import Path
 
-from amaranth import *
+from amaranth import Module, ClockDomain, ClockSignal, ResetSignal
 from amaranth.lib import io
 from amaranth.back import rtlil  # type: ignore[reportAttributeAccessIssue]
 from amaranth.hdl._ir import PortDirection

chipflow_lib/steps/silicon.py

@@ -19,7 +19,7 @@
 
 import dotenv
 
-from amaranth import *
+from amaranth import Module, Signal, Elaboratable
 from halo import Halo
 
 from . import StepBase, _wire_up_ports
@@ -182,6 +182,7 @@ def network_err(e):
             sp.start("Sending design to ChipFlow Cloud")
 
             assert self._chipflow_api_key
+            resp = None
             try:
                 resp = requests.post(
                     build_submit_url,
@@ -203,6 +204,7 @@ def network_err(e):
             except requests.exceptions.ReadTimeout as e:
                 network_err(e)
 
+            assert resp
             # Parse response body
             try:
                 resp_data = resp.json()

chipflow_lib/steps/sim.py

@@ -10,7 +10,7 @@
 from doit.doit_cmd import DoitMain
 from doit.task import dict_to_task
 
-from amaranth import *
+from amaranth import Module
 
 from . import StepBase, _wire_up_ports
 from .. import ChipFlowError, _ensure_chipflow_root

pdm.lock

@@ -44,10 +44,6 @@ build-backend = "pdm.backend"
 [tool.pyright]
 diagnosticMode=true
 typeCheckingMode = "standard"
-reportInvalidTypeForm = false
-reportMissingImports = false
-reportUnboundVariable = false
-reportWildcardImportFromLibrary = false
 
 [tool.ruff]
 include = [