wip

Author: robtaylor

chipflow_lib/_signatures.py

@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: BSD-2-Clause
+
+from typing_extensions import Unpack, TypedDict
+
+from amaranth.lib import wiring
+from amaranth.lib.wiring import Out
+
+from .platforms._utils import InputIOSignature, OutputIOSignature, BidirIOSignature, IOModelOptions, _chipflow_schema_uri, amaranth_annotate
+
+SIM_ANNOTATION_SCHEMA = str(_chipflow_schema_uri("sim-interface", 0))
+
+def sim_annotate(klass):
+    class Model(TypedDict):
+        sim_interface: str
+
+    original_init_subclass = klass.__init_subclass__
+    @classmethod
+    def new_init_subclass(cls, /, **kwargs):
+        if original_init_subclass:
+            original_init_subclass(**kwargs)
+        cls._model = {"sim_interface": cls.__name__}
+
+    dec = amaranth_annotate(Model, SIM_ANNOTATION_SCHEMA)
+    klass = dec(klass)
+    klass.__init_subclass__ = new_init_subclass
+    return klass
+
+
+@sim_annotate
+class SimulatableSignature(wiring.Signature):
+    ...
+
+
+SPISignature = SimulatableSignature({
+    "sck": Out(OutputIOSignature(1)),
+    "copi": Out(OutputIOSignature(1)),
+    "cipo": Out(InputIOSignature(1)),
+    "csn": Out(OutputIOSignature(1)),
+})
+
+UARTSignature = SimulatableSignature({
+                "tx": Out(OutputIOSignature(1)),
+                "rx": Out(InputIOSignature(1)),
+            })
+
+I2CSignature = SimulatableSignature({
+    "scl": Out(BidirIOSignature(1)),
+    "sda": Out(BidirIOSignature(1))
+    })
+
+class GPIOSignature(SimulatableSignature):
+    def __init__(self, pin_count=1, **kwargs: Unpack[IOModelOptions]):
+        if pin_count > 32:
+            raise ValueError(f"Pin pin_count must be lesser than or equal to 32, not {pin_count}")
+        self._pin_count = pin_count
+        super().__init__({
+            "gpio": Out(BidirIOSignature(pin_count, individual_oe=True, **kwargs))
+            })
+    def get_sim_parameters(self):
+        return {'pin_count': self._pin_count}
+
+    def __repr__(self) -> str:
+        return f"GPIOSignature(pin_count={self._pin_count}, {dict(self.members.items())})"

chipflow_lib/platforms/_utils.py

@@ -13,7 +13,7 @@
 from enum import Enum, IntEnum, StrEnum, auto
 from math import ceil, floor
 from typing import (
-    Any, Annotated, NamedTuple, Self, Iterator, Type,
+    Any, Annotated, NamedTuple, Self, Type,
     TYPE_CHECKING
 )
 from typing_extensions import (
@@ -157,19 +157,17 @@ def as_json(self):  # type: ignore
 
     def annotations(self, *args):  # type: ignore
         annotations = wiring.Signature.annotations(self, *args)  # type: ignore
-
-        io_annotation = Annotation(self._model)
-        return annotations + (io_annotation,)  # type: ignore
-
-
-
+        print(f"annotating {self} with {self._model}")
+        annotation = Annotation(self._model)
+        print(f"returning {annotations + (annotation,)}")
+        return annotations + (annotation,)  # type: ignore
 
     def decorator(klass):
         klass.annotations = annotations
-        klass.__repr__
         return klass
     return decorator
 
+
 @amaranth_annotate(IOModel, IO_ANNOTATION_SCHEMA)
 class IOSignature(wiring.Signature):
     """An :py:obj:`Amaranth Signature <amaranth.lib.wiring.Signature>` used to decorate wires that would usually be brought out onto a port on the package.

chipflow_lib/platforms/sim.py

@@ -3,29 +3,115 @@
 import logging
 import os
 import sys
+
+from dataclasses import dataclass
+from enum import StrEnum, auto
 from pathlib import Path
+from pprint import pformat
+from typing import List, Optional, TypedDict, Optional, Unpack, Union, Type
 
 from amaranth import Module, ClockDomain, ClockSignal, ResetSignal
-from amaranth.lib import io
+from amaranth.lib import io, meta, wiring
+from amaranth.lib.wiring import In, Out
 from amaranth.back import rtlil  # type: ignore[reportAttributeAccessIssue]
+from amaranth.hdl import _ir, _ast
 from amaranth.hdl._ir import PortDirection
 from amaranth.lib.cdc import FFSynchronizer
+from pydantic import BaseModel, ConfigDict
 
-from ._utils import load_pinlock
+from .. import ChipFlowError
+from .._signatures import I2CSignature, GPIOSignature, UARTSignature, SPISignature
+from ._utils import load_pinlock, _chipflow_schema_uri, amaranth_annotate, InputIOSignature, OutputIOSignature, BidirIOSignature
 
 
-__all__ = ["SimPlatform"]
 logger = logging.getLogger(__name__)
+__all__ = ["SimPlatform", "BuildObject", "BasicCxxBuild"]
+
+
+class SimModelCapability(StrEnum):
+    LOAD_DATA = "load-data"
+
+
+@dataclass
+class SimModel:
+    """
+    Description of a model available from a BuildObject
+    Attributes:
+        name: the model name
+        capabilities: List of capabilities of the model.
+        signature: the wiring connection of the model. This is also used to match with interfaces.
+    """
+    name: str
+    signature: Type[wiring.Signature]
+    capabilities: Optional[List[SimModelCapability]] = None
+
+
+class BuildObject(BaseModel):
+    """
+    Represents an object built from a compiled language
+
+    Attributes:
+        capabilities: arbitary list of capability identifiers
+    """
+    kind: str = "base"
+    models: List[SimModel]
+
+    @classmethod
+    def get_subclasses(cls):
+        return tuple(cls.__subclasses__())
+
+    def model_for_signature(self, signature: wiring.Signature) -> SimModel | None:
+        """
+        Checks if this build object has a model for the given signature (matching by type equality)
+
+        Returns:
+            A tuple of the model and a dict of parameters from the signature
+            None on failure to find a matching model
+        """
+        for m in self.models:
+            if isinstance(signature, m.signature):
+                return m
+
+
+
+class BasicCxxBuild(BuildObject):
+    """
+    Represents an object built from C++, where the compilation is simply done with a collection of
+    cpp and hpp files, simply compiled and linked together with no dependencies
+
+    Assumes model name corresponds to the c++ class name and that the class constructors take
+    a name followed by the wires of the interface.
+
+    Attributes:
+        cpp_files: C++ files used to define the model
+        hpp_files: C++ header files to define the model interfaces
+    """
+    kind: str = "basic-c++"
+    cpp_files: List[Path]
+    hpp_files: Optional[List[Path]] = None
+    hpp_dirs: Optional[List[Path]] = None
+
+
+_COMMON_MODELS = BasicCxxBuild(
+    models=[
+        SimModel('spiflash_model', SPISignature, [SimModelCapability.LOAD_DATA]),
+        SimModel('uart_model', UARTSignature),
+        SimModel('i2c_model', I2CSignature),
+        SimModel('gpio_model', GPIOSignature),
+        ],
+    cpp_files=[ Path('common','sim','models.cc') ],
+    hpp_files=[ Path('common','sim','models.h') ],
+    )
 
 
 class SimPlatform:
-
     def __init__(self, config):
         self.build_dir = os.path.join(os.environ['CHIPFLOW_ROOT'], 'build', 'sim')
         self.extra_files = dict()
         self.sim_boxes = dict()
         self._ports = {}
         self._config = config
+        self._top_sim = {}
 
     def add_file(self, filename, content):
         if not isinstance(content, (str, bytes)):
@@ -67,6 +153,10 @@ def build(self, e):
             print("read_rtlil sim_soc.il", file=yosys_file)
             print("hierarchy -top sim_top", file=yosys_file)
             print("write_cxxrtl -header sim_soc.cc", file=yosys_file)
+        main = Path(self.build_dir) / "main.cc"
+        with open(main, "w") as main_file:
+            for p in self._ports:
+                print(p, file=main_file)
 
     def instantiate_ports(self, m: Module):
         if hasattr(self, "_pinlock"):
@@ -76,10 +166,11 @@ def instantiate_ports(self, m: Module):
         for component, iface in pinlock.port_map.ports.items():
             for k, v in iface.items():
                 for name, port_desc in v.items():
-                   logger.debug(f"Instantiating port {port_desc.port_name}: {port_desc}")
-                   invert = port_desc.invert if port_desc.invert else False
-                   self._ports[port_desc.port_name] = io.SimulationPort(port_desc.direction, port_desc.width, invert=invert, name=port_desc.port_name)
-
+                    logger.debug(f"Instantiating port {port_desc.port_name}: {port_desc}")
+                    invert = port_desc.invert if port_desc.invert else False
+                    self._ports[port_desc.port_name] = io.SimulationPort(port_desc.direction, port_desc.width, invert=invert, name=port_desc.port_name)
+                    # TODO, allow user to add models
+                    #self._port_model = model_for_signature(port_desc.
         for clock in pinlock.port_map.get_clocks():
             assert 'clock_domain' in clock.iomodel
             domain = clock.iomodel['clock_domain']
@@ -123,8 +214,6 @@ def instantiate_ports(self, m: Module):
             "{OUTPUT_DIR}/sim_soc.cc",
             "{OUTPUT_DIR}/sim_soc.h",
             "{SOURCE_DIR}/main.cc",
-            "{COMMON_DIR}/models.cc",
-            "{COMMON_DIR}/models.h",
             "{COMMON_DIR}/vendor/nlohmann/json.hpp",
             "{COMMON_DIR}/vendor/cxxrtl/cxxrtl_server.h",
         ],