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Copy file name to clipboardExpand all lines: docs/chipflow-toml-guide.rst
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@@ -51,6 +51,29 @@ You probably won't need to change these if you're starting from an example repos
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``[chipflow.clocks]``
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---------------------
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.. code-block:: TOML
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[chipflow.clocks]
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default = 'sys_clk'
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This section links the clock domains utilized in the design to specific pads.
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These pads need to be specified in the `[silicon.pads]`_ section with `type`_ equal to ``clock``.
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The ``default`` clock domain is associated with the Amaranth ``sync`` clock domain.
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Currently, only one ``default`` clock domain is supported.
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``[chipflow.resets]``
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---------------------
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.. code-block:: TOML
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[chipflow.resets]
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default = 'sys_rst_n'
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This section identifies the input pads designated for reset functionality.
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These pads need to be specified in the `[silicon.pads]`_ section with `type`_ equal to ``reset``.
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The logic that synchronizes the reset signal with the clock will be generated automatically.
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``[chipflow.silicon]``
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----------------------
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package = "pga144"
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The ``silicon`` section sets the Foundry ``process`` (i.e. PDK) that we are targeting for manufacturing, and the physical ``package`` we want to place our design inside.
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The ``silicon`` section sets the Foundry ``process`` (i.e. PDK) that we are targeting for manufacturing, and the physical ``package`` (pad ring) we want to place our design inside.
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You'll choose the ``process`` and ``package`` based in the requirements of your design.
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