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1 parent 81814bd commit 4ba30bfCopy full SHA for 4ba30bf
chipflow_lib/platforms/silicon.py
@@ -333,16 +333,6 @@ def __init__(self,
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self._gpio_analog_sel = None # analog mux select
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self._gpio_analog_pol = None # analog mux select
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- def wire(self, m: Module, interface: PureInterface):
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- super().wire(m, interface)
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-
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- # wire up drive mode bits
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- bit = 0
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- for i in self._dms:
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- m.d.comb += self._dm0[bit].eq(i[0]) # type: ignore
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- m.d.comb += self._dm1[bit].eq(i[1]) # type: ignore
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- m.d.comb += self._dm2[bit].eq(i[2]) # type: ignore
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def instantiate_toplevel(self):
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ports = super().instantiate_toplevel()
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for s, d in self._signals:
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